SAK-TC264DC-40F200W BC [INFINEON]
SAK-TC264DC-40F200W BC 属于第一代 Aurix TC26xD 系列产品。其创新多核心架构基于多达三个独立 32 位 TriCore CPU，专为满足极高的安全标准，同时大幅提高性能而设计。TC26xD 系列产品配备 200 MHz TriCore、5V 或 3.3V 单电压供电和强大的通用定时器模块 (GTM)，旨在降低复杂度、实现同类产品中极其优秀的功耗并节省大量成本。;
| 型号： | SAK-TC264DC-40F200W BC |
| 厂家： | 
Infineon |
| 描述： | SAK-TC264DC-40F200W BC 属于第一代 Aurix TC26xD 系列产品。其创新多核心架构基于多达三个独立 32 位 TriCore CPU，专为满足极高的安全标准，同时大幅提高性能而设计。TC26xD 系列产品配备 200 MHz TriCore、5V 或 3.3V 单电压供电和强大的通用定时器模块 (GTM)，旨在降低复杂度、实现同类产品中极其优秀的功耗并节省大量成本。 |
| 文件： | 总318页 (文件大小：4442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Bit
Microcontroller
TC260 / 264 / 265 / 267
32-Bit Single-Chip Microcontroller
BC-Step
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.0, 2017-06
Microcontrollers
Edition 2017-06
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TC 260 / 264 / 265 / 267
Revision History
Page or Item
Subjects (major changes since previous revision)
V 1.0, 2017-06
The history is documented in the last chapter
Data Sheet
3
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
Package and Pinning Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TC264x Pin Definition and Functions: LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TC264 LQFP144 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TC265x Pin Definition and Functions: LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
TC265 LQFP176 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TC267x Pin Definition and Functions: BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
TC267 BGA292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
TC260 Bare Die Pad Definition: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
TC 260 / 264 / 265 / 267 Bare Die Pad Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
2.4
2.4.1
2.4.2
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.3 V only Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
High performance LVDS Pads (LVDSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Medium performance LVDS Pads (LVDSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.14.1
3.15
3.15.1
3.15.2
3.15.3
3.15.4
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
Data Sheet
TOC-1
V 1.0, 2017-06
TC 260 / 264 / 265 / 267
3.26
3.27
3.28
3.29
3.29.1
3.29.2
3.29.3
3.29.4
3.30
3.31
3.32
3.33
3.33.1
3.33.2
3.33.3
3.34
3.35
3.36
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
MSC Timing 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 282
ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
SCR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
SSC Timing 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
SPD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
WCAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
CIF Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
TC260 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
3.36.1
3.36.2
3.37
4
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Data Sheet
2
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
3
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Summary of Features
1
Summary of Features
The TC26x product family has the following features:
•
•
High Performance Microcontroller with two CPU cores
One 32-bit super-scalar TriCore CPUs (TC1.6P), having the following features:
–
–
–
–
–
–
–
–
–
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Multiply-accumulate unit able to sustain 2 MAC operations per cycle
up to 200 MHz operation at full temperature range
up to 120 Kbyte Data Scratch-Pad RAM (DSPR)
up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
16 Kbyte Instruction Cache (ICACHE)
8 Kbyte Data Cache (DCACHE)
•
Power Efficient scalar TriCore CPU (TC1.6E), having the following features:
–
–
–
–
–
–
Binary code compatibility with TC1.6P
up to 200 MHz operation at full temperature range
up to 72 Kbyte Data Scratch-Pad RAM (DSPR)
up to 16 Kbyte Instruction Scratch-Pad RAM (PSPR)
8 Kbyte Instruction Cache (ICACHE)
0.125Kbyte Data Read Buffer (DRB)
•
•
Lockstepped shadow core for TC1.6P
Multiple on-chip memories
–
–
–
–
–
All embedded NVM and SRAM are ECC protected
up to 2.5 Mbyte Program Flash Memory (PFLASH)
up to 96 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
0 Kbyte Memory (LMU)
BootROM (BROM)
•
•
•
48-Channel DMA Controller with safe data transfer
Sophisticated interrupt system (ECC protected)
High performance on-chip bus structure
–
–
–
64-bit Cross Bar Interconnect (SRI) giving fast parallel access between busmasters, CPUs and memories
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (SFI Bridge)
•
•
•
•
Safety Management Unit (SMU) handling safety monitor alarms
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
Hardware I/O Monitor (IOM) for checking of digital I/O
Versatile On-chip Peripheral Units
–
Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
–
–
Four Queued SPI Interface Channels (QSPI) with master and slave capability upto 50 Mbit/s
High Speed Serial Link (HSSL) for serial inter-processor communication up to 320Mbit/s
Data Sheet
1-1
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Summary of Features
–
–
Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
One MultiCAN+ Module with 5 CAN nodes and 256 free assignable messageobjects for high efficiency data
handling via FIFO buffering and gateway data transfer
–
–
–
6 Single Edge Nibble Transmission (SENT) channels for connection to sensors
One FlexRayTMmodule with 2 channels (E-Ray) supporting V2.1
One Generic Timer Module (GTM) providing a powerful set of digital signal filteringand timer functionality
to realize autonomous and complex Input/Output management
–
–
–
–
–
–
One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
One General Purpose 12 Timer Unit (GPT120)
Three channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
Peripheral Sensor Interface with Serial PHY (PSI5-S)
Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)
•
8-bit Standby Controller (TC2x_SCR)
–
–
–
–
–
–
–
Two 8-bit timers
One 16-bit timer
Timer 2 Capture Compare Unit
Real Time Clock
Universal Asynchronous Receiver/Transmitter
High Speed Synchronous Serial Interface
Wake-up CAN Filter
•
•
Versatile Successive Approximation ADC (VADC)
–
–
Cluster of 4 independent ADC kernels
Input voltage range from 0 V to 5.5V (ADC supply)
Delta-Sigma ADC (DSADC)
Three/Four channels
–
•
•
•
Digital programmable I/O ports
On-chip debug support for OCDS Level 1 (CPUs , DMA, On Chip Buses)
Dedicated Emulation Device chip available (ED)
–
–
–
multi-core debugging, real time tracing, and calibration
Aurora Gigabit Trace Port (AGBT) on some variants (See below)
four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
•
•
•
Power Management System and on-chip regulators
Clock Generation Unit with System PLL and Flexray PLL
Embedded Voltage Regulator
The support of the Feature 8-bit Standby Controller (TC2x_SCR) is discontinued.
Data Sheet
1-2
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply voltage
The package and the type of delivery.
For the available ordering codes for the TC 260 / 264 / 265 / 267 please refer to the
“AURIX™ TC2x Data Sheet Addendum”, which summarizes all available variants.
Table 1-1 Overview of TC 260 / 264 / 265 / 267 Functions
Feature
TC1.6P / TC1.6E
CPU Core
Type
1 /
1 /
1 /
0
P Cores /
Checker Cores /
E Cores /
Checker Cores
200 MHz
yes
Max. Freq.
FPU
2.5 Mbyte
Program
Flash
Size
96 Kbyte
16 Kbyte / 8 Kbyte
8 Kbyte / -
Data Flash
Cache
Size
Instruction
Data
120 Kbyte / 32 Kbyte2)
SRAM
Size TC1.6P
(DPSR/PSPR)
72 Kbyte / 16 Kbyte1) 2)
Size TC1.6E
(DPSR/PSPR)
0 Kbyte
Size LMU
Channels
Channels
Converter
Channels
TIM
48
DMA
ADC
38 + 12
4
3 / 4
3
DSADC
GTM
2
TOM
4 / 3
1 / 1
1
ATOM / MCS
CMU / ICM
PSM
1
TBU
2
SPE
1 / 1
0 / 1
2
CMP / MON
BRC / DPLL
GPT12
Timer
2
CCU6
Data Sheet
1-3
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Summary of Features
Table 1-1 Overview of TC 260 / 264 / 265 / 267 Functions
Feature
2
1
STM
Modules
Modules
Channels
Nodes
FlexRay
2
5
CAN
256
Message
Objects
4
QSPI
ASCLIN
I2C
Channels
Interfaces
Interfaces
Modules
Channels
Modules
Channels
Channels
Channels
Level
4
1
6
SENT
PSI5
3
1
PSI5-S
HSSL
MSC
1
2
1
Ethernet
ASIL
up to ASIL-D
1
1
1
FCE
Modules
SMU
Safety
Support
IOM
ADAS
No
Yes
Standby-Controller
Feature Discontinued
8-bit
Yes
Yes
Yes
Yes
Embedded Voltage Regulator
DCDC from 5 V/ 3.3 V to 1.3 V
LDO from 5 V / 3.3 V to 1.3 V
LDO from 5 V to 3.3 V
Standby RAM
Low Power Features
Packages
PG-LQFP-144-22 / PG-LQFP-176-
22 / PG-LFBGA-292-6
Type
5 V CMOS / 3.3 V CMOS / LVDS
I/O
Type
-40 ... + 150°C
Tambient
Range
1) Address range starts at lowest address defined in the User’s Manual. For reference see the Memory Maps chapter of the
User’s Manual.
2) To ensure the processor cores are provided with a constant stream of instructions the Instruction Fetch Units will
speculatively fetch instructions from the up to 64 bytes ahead of the current PC.
If the current PC is within 64 bytes of the top of an instruction memory the Instruction Fetch Unit may attempt to
speculatively fetch instruction from beyond the physical range. This may then lead to error conditions and alarms being
triggered by the bus and memory systems.
It is therefore recommended that the upper 64 bytes of any memory be unused for instruction storage.
Data Sheet
1-4
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning Definitions
2
Package and Pinning Definitions
This chapter gives a pinning of the different packages of the TC 260 / 264 / 265 / 267.
Data Sheet
2-5
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
2.1
TC264x Pin Definition and Functions: LQFP144
Figure 2-1 is showing the TC264x Logic Symbol for the package variant: QFP144.
1
2
P02.0
P02.1
P02.2
P02.3
108
P20. 14
107
106
105
104
103
P20. 13
P20. 12
P20. 11
P20. 10
3
4
5
6
P02.4
P02.5
P02.6
P02.7
P20. 9
P20. 8
P20. 7
P20. 6
7
8
9
102
101
100
99
P02.8
DD/VDDSB
P00.0
P00.1
10
V
VDD
11
12
13
14
98
97
96
95
ESR0
PORST
ESR1
P00.2
P00.3
P00.4
P00.5
P00.6
P20. 3
P20. 2 / TESTMODE
P20. 0
TCK
15
16
17
18
94
93
92
91
P00.7
P00.8
P00.9
TRST
P21. 7 / TDO
TMS
P21. 6 / TDI
P21. 5
19
20
21
22
23
TC26x
90
89
88
87
P00.12
VDD
VEXT
AN49
AN48
86
85
84
83
P21. 4
P21. 3
P21. 2
VDDP3
24
25
26
27
AN47
AN46
AN45
AN44
82
81
80
79
78
XTAL2
XTAL1
VSS
28
29
30
31
AN39
AN38
AN37
AN36
VDD
VEXT
32
33
34
35
77
76
75
74
P22. 3
P22. 2
P22. 1
AN35
AN25
AN24
P22. 0
P23. 1
36
73
Figure 2-1 TC264x Logic Symbol for the package variant LQFP144.
Data Sheet
2-6
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
2.1.1
TC264 LQFP144 Package Variant Pin Configuration
Table 2-1 Port 00 Functions
Pin
11
Symbol
Ctrl
Type
Function
P00.0
TIN9
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I/O
I
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
General-purpose input
GTM input
12
P00.1
TIN10
LP /
PU1 /
VEXT
ARX3E
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN0A
VADCG3.11
CIFD10
P00.1
ASCLIN3 input
CAN node 1 input
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 0 input A
VADC analog input channel 11 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
Reserved
–
DSCOUT0
–
DSADC channel 0 output
Reserved
SPC0
SENT output
CC60
CCU61 output
Data Sheet
2-7
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
13
Symbol
Ctrl
Type
Function
P00.2
TIN11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT1B
DSDIN0A
VADCG3.10
CIFD11
P00.2
SENT input
DSADC channel 0 input A
VADC analog input channel 10 of group 3 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT11
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
TXDCAN3
–
PSI5 output
CAN node 3 output
Reserved
COUT60
CCU61 output
14
P00.3
TIN12
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN3A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG3.9
CIFD12
P00.3
CAN node 3 input
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input A
VADC analog input channel 9 of group 3 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
Data Sheet
2-8
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
15
Symbol
Ctrl
Type
Function
P00.4
TIN13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG3.8
CIFD13
SENT input
DSADC channel 3 input A
DSADC input
VADC analog input channel 8 of group 3
CIF input
P00.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT13
PSISTX
TXDCAN4
PSITX1
PSI5-S output
CAN node 4 output
PSI5 output
VADCG2BFL0
SPC3
VADC output
SENT output
COUT61
CCU61 output
16
P00.5
TIN14
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSIRX2A
SENT4B
RXDCAN4A
CC62INB
CC62INA
DSCIN2A
VADCG3.7
CIFD14
PSI5 input
SENT input
CAN node 4 input
CCU60 input
CCU61 input
DSADC channel 2 input A
VADC analog input channel 7 of group 3
CIF input
P00.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT14
DSCGPWMN
–
DSADC output
Reserved
DSCOUT2
VADCG2BFL1
SPC4
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
Data Sheet
2-9
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
17
Symbol
Ctrl
Type
Function
P00.6
TIN15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT5B
SENT input
DSDIN2A
VADCG3.6
CIFD15
DSADC channel 2 input A
VADC analog input channel 6 of group 3
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG2BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
CCU61 output
General-purpose input
GTM input
18
P00.7
TIN16
LP /
PU1 /
VEXT
CC60INC
CCPOS0A
T12HRB
T2INA
CCU61 input
CCU61 input
CCU60 input
GPT120 input
VADCG3.5
CIFCLK
P00.7
VADC analog input channel 5 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG2BFL3
–
VADC output
Reserved
VADCEMUX11
–
VADC output
Reserved
CC60
CCU61 output
Data Sheet
2-10
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
19
Symbol
Ctrl
Type
Function
P00.8
TIN17
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
CC61INC
CCPOS1A
T13HRB
T2EUDA
VADCG3.4
CIFVSNC
P00.8
CCU61 input
CCU61 input
CCU60 input
GPT120 input
VADC analog input channel 4 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
–
VADC output
Reserved
CC61
CCU61 output
General-purpose input
GTM input
20
P00.9
TIN18
LP /
PU1 /
VEXT
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
VADCG3.3
DSITR3F
CIFHSNC
P00.9
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
VADC analog input channel 3 of group 3
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
–
QSPI3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
CC62
CCU61 output
Data Sheet
2-11
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
21
Symbol
Ctrl
Type
Function
P00.12
TIN21
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS3A
ASCLIN3 input
VADC analog input channel 0 of group 3
General-purpose output
GTM output
VADCG3.0
P00.12
O0
O1
O2
O3
O4
O5
O6
O7
TOUT21
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
Table 2-2 Port 02 Functions
Pin
1
Symbol
Ctrl
Type
Function
P02.0
TIN0
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ARX2G
REQ6
ASCLIN2 input
SCU input
CC60INA
CC60INB
CIFD0
CCU60 input
CCU61 input
CIF input
P02.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY output
SLSO31
DSCGPWMN
TXDCAN0
TXDA
CC60
CCU60 output
Data Sheet
2-12
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
2
Symbol
Ctrl
Type
Function
P02.1
TIN1
I
LP / PU1 General-purpose input
/ VEXT
GTM input
REQ14
ARX2B
RXDCAN0A
RXDA2
CIFD1
P02.1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT1
–
Reserved
SLSO32
DSCGPWMP
–
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
CCU60 output
3
P02.2
TIN2
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
PSI5 output
SLSO33
PSITX0
TXDCAN2
TXDB
CAN node 2 output
ERAY output
CC61
CCU60 output
Data Sheet
2-13
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
4
Symbol
Ctrl
Type
Function
P02.3
TIN3
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1G
RXDCAN2B
RXDB2
PSIRX0B
SDI11
CIFD3
P02.3
ASCLIN1 input
CAN node 2 input
ERAY input
PSI5 input
MSC1 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
COUT61
CCU60 output
General-purpose input
GTM input
5
P02.4
TIN4
MP+ /
PU1 /
VEXT
SLSI3A
ECTT1
QSPI3 input
TTCAN input
CAN node 0 input
CCU60 input
CCU61 input
I2C0 input
RXDCAN0D
CC62INA
CC62INB
SDA0A
CIFD4
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXENA
CC62
ERAY output
CCU60 output
Data Sheet
2-14
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
6
Symbol
Ctrl
Type
Function
P02.5
TIN5
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
MRST3A
ECTT2
PSIRX1B
PSISRXB
SENT3C
SCL0A
CIFD5
QSPI3 input
TTCAN input
PSI5 input
PSI5-S input
SENT input
I2C0 input
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
–
CAN node 0 output
QSPI3 output
Reserved
SCL0
I2C0 output
TXENB
COUT62
ERAY output
CCU60 output
General-purpose input
GTM input
7
P02.6
TIN6
MP /
PU1 /
VEXT
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
P02.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
Data Sheet
2-15
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-2 Port 02 Functions (cont’d)
Pin
8
Symbol
Ctrl
Type
Function
P02.7
TIN7
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
P02.7
DSADC channel 3 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSADC channel 3 output
VADC output
SENT output
DSCOUT3
VADCEMUX01
SPC1
CC61
CCU60 output
9
P02.8
TIN8
LP / PU1 General-purpose input
/
GTM input
VEXT
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
CIFD8
DSDIN3B
DSITR3E
P02.8
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
Data Sheet
2-16
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-3 Port 10 Functions
Pin
140
Symbol
Ctrl
Type
Function
P10.1
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG3BFL1
END03
–
141
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
QSPI1 input
GPT120 input
SCU input
REQ2
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG3BFL2
END02
–
Data Sheet
2-17
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-3 Port 10 Functions (cont’d)
Pin
142
Symbol
Ctrl
Type
Function
P10.3
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG3BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
143
P10.5
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
RXDCAN4B
INJ01
SCU input
CAN node 4 input
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
QSPI1 output
GPT120 output
ASCLIN2 output
Reserved
SLSO38
SLSO19
T6OUT
ASLSO2
–
Data Sheet
2-18
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-3 Port 10 Functions (cont’d)
Pin
144
Symbol
Ctrl
Type
Function
P10.6
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
ASCLIN2 input
QSPI3 input
MTSR3B
HWCFG5
P10.6
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
ASCLIN2 output
QSPI3 output
GPT120 output
CAN node 4 output
QSPI1 output
VADC output
T3OUT
TXDCAN4
MRST1
VADCG3BFL0
Table 2-4 Port 11 Functions
Pin
132
Symbol
Ctrl
Type
Function
P11.2
TIN95
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
P11.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT95
END03
SLSO05
SLSO15
EN01
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
CCU60 output
General-purpose input
GTM input
133
P11.3
TIN96
MPR /
PU1 /
VFLEX
MRST1B
SDI03
P11.3
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT96
–
Reserved
MRST1
TXDA
–
QSPI1 output
ERAY output
Reserved
ETHTXD0
COUT62
ETH output
CCU60 output
Data Sheet
2-19
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-4 Port 11 Functions (cont’d)
Pin
134
Symbol
Ctrl
Type
Function
P11.6
TIN97
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
SCLK1B
P11.6
QSPI1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT97
TXENB
SCLK1
ERAY output
QSPI1 output
ERAY output
MSC0 output
ETH output
TXENA
FCLP0
ETHTXEN
COUT61
CCU60 output
General-purpose input
GTM input
135
P11.9
TIN98
MP+ /
PU1 /
VFLEX
MTSR1B
RXDA1
ETHRXD1
P11.9
TOUT98
–
QSPI1 input
ERAY input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
–
MSC0 output
Reserved
COUT60
CCU60 output
Data Sheet
2-20
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-4 Port 11 Functions (cont’d)
Pin
137
Symbol
Ctrl
Type
Function
P11.10
TIN99
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXDB1
ETHRXD0
SDI00
P11.10
TOUT99
–
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY input
ETH input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
General-purpose input
GTM input
138
P11.11
TIN100
MP+ /
PU1 /
VFLEX
ETHCRSDVA
P11.11
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT100
END02
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY output
CCU60 output
SLSO04
SLSO14
EN00
TXENB
CC61
Data Sheet
2-21
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-4 Port 11 Functions (cont’d)
Pin
139
Symbol
Ctrl
Type
Function
P11.12
TIN101
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
ETHRXCLKA
ETH input
(Not for productive purposes)
P11.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT101
ATX1
ASCLIN1 output
GTM output
GTMCLK2
TXDB
ERAY output
TXDCAN3
EXTCLK1
CC60
CAN node 3 output
SCU output
CCU60 output
Table 2-5 Port 13 Functions
Pin
128
Symbol
Ctrl
Type
Function
P13.0
TIN91
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
P13.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT91
END03
SCLK2N
EN01
MSC0 output
QSPI2 output (LVDS)
MSC0 output
FCLN0
FCLND0
TXDCAN4
MSC0 output (LVDS)
MSC0 output (LVDS)
CAN node 4 output
Data Sheet
2-22
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-5 Port 13 Functions (cont’d)
Pin
129
Symbol
Ctrl
Type
Function
P13.1
TIN92
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
SCL0B
RXDCAN4C
P13.1
TOUT92
–
I2C0 input
CAN node 4 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
–
MSC0 output (LVDS)
I2C0 output
Reserved
130
P13.2
TIN93
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
CAPINA
SDA0B
P13.2
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT93
–
Reserved
MTSR2N
FCLP0
SON0
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
SDA0
SOND0
MSC0 output (LVDS)
General-purpose input
GTM input
131
P13.3
TIN94
LVDSM_P /
PU1 /
VEXT
P13.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT94
–
Reserved
MTSR2P
QSPI2 output (LVDS)
Reserved
–
SOP0
MSC0 output (LVDS)
Reserved
–
–
Reserved
Data Sheet
2-23
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-6 Port 14 Functions
Pin
118
Symbol
Ctrl
Type
Function
P14.0
TIN80
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P14.0
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
TXDA
O3
O4
O5
ERAY output
ERAY output
TXDB
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function.
ASCLK0
COUT62
O6
O7
I
ASCLIN0 output
CCU60 output
General-purpose input
GTM input
119
P14.1
TIN81
MP /
PU1 /
VEXT
REQ15
SCU input
ARX0A
ASCLIN0 input
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function.
RXDA3
RXDB3
EVRWUPA
P14.1
ERAY input
ERAY input
SCU input
O0
O1
O2
General-purpose output
GTM output
TOUT81
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
–
O3
O4
O5
O6
O7
Reserved
Reserved
Reserved
Reserved
CCU60 output
–
–
–
COUT63
Data Sheet
2-24
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-6 Port 14 Functions (cont’d)
Pin
120
Symbol
Ctrl
Type
Function
P14.2
TIN82
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
SLSO21
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
121
P14.3
TIN83
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX2A
REQ10
HWCFG3_BMI
SDI02
ASCLIN2 input
SCU input
SCU input
MSC0 input
P14.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT83
ATX2
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
Data Sheet
2-25
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-6 Port 14 Functions (cont’d)
Pin
122
Symbol
Ctrl
Type
Function
P14.4
TIN84
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT84
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
123
P14.5
TIN85
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT85
–
–
Reserved
–
Reserved
–
Reserved
TXDB
–
ERAY output
Reserved
124
P14.6
TIN86
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT86
–
SLSO22
QSPI2 output
Reserved
–
–
Reserved
TXENB
–
ERAY output
Reserved
Data Sheet
2-26
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-7 Port 15 Functions
Pin
109
Symbol
Ctrl
Type
Function
P15.0
TIN71
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
P15.0
TOUT71
ATX1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
Reserved
SLSO013
–
TXDCAN2
ASCLK1
–
CAN node 2 output
ASCLIN1 output
Reserved
110
P15.1
TIN72
LP /
PU1 /
VEXT
General-purpose input
GTM input
REQ16
SCU input
ARX1A
ASCLIN1 input
CAN node 2 input
QSPI2 input
RXDCAN2A
SLSI2B
EVRWUPB
SCU input
P15.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT72
ATX1
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
–
–
Reserved
Reserved
Reserved
111
P15.2
TIN73
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI2A
MRST2E
HSIC2INA
P15.2
QSPI2 input
QSPI2 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT73
ATX0
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
Data Sheet
2-27
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-7 Port 15 Functions (cont’d)
Pin
112
Symbol
Ctrl
Type
Function
P15.3
TIN74
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX0B
SCLK2A
RXDCAN1A
HSIC2INB
P15.3
ASCLIN0 input
QSPI2 input
CAN node 1 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT74
ATX0
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
113
P15.4
TIN75
MP /
PU1 /
VEXT
General-purpose input
GTM input
MRST2A
REQ0
SCL0C
P15.4
TOUT75
ATX1
MRST2
–
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
–
Reserved
SCL0
CC62
I2C0 output
CCU60 output
Data Sheet
2-28
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-7 Port 15 Functions (cont’d)
Pin
114
Symbol
Ctrl
Type
Function
P15.5
TIN76
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1B
MTSR2A
SDA0C
REQ13
P15.5
ASCLIN1 input
QSPI2 input
I2C0 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT76
ATX1
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
General-purpose input
GTM input
115
P15.6
TIN77
MP /
PU1 /
VEXT
MTSR2B
P15.6
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT77
ATX3
ASCLIN3 output
QSPI2 output
Reserved
MTSR2
–
SCLK2
ASCLK3
CC60
QSPI2 output
ASCLIN3 output
CCU60 output
General-purpose input
GTM input
116
P15.7
TIN78
MP /
PU1 /
VEXT
ARX3A
MRST2B
P15.7
TOUT78
ATX3
MRST2
–
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
2-29
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-7 Port 15 Functions (cont’d)
Pin
117
Symbol
Ctrl
Type
Function
P15.8
TIN79
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SCLK2B
REQ1
P15.8
TOUT79
–
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
ASCLIN3 output
CCU60 output
Table 2-8 Port 20 Functions
Pin
93
Symbol
Ctrl
Type
Function
P20.0
TIN59
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN3C
T6EUDA
REQ9
SYSCLK
TGI0
CAN node 3 input
GPT120 input
SCU input
HSCT input
OCDS input
P20.0
TOUT59
ATX3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
Data Sheet
2-30
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
94
Symbol
Ctrl
Type
Function
P20.2
I
LP /
General-purpose input
PU /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
OCDS input
P20.2
O0
O1
O2
O3
O4
O5
O6
O7
I
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
General-purpose input
GTM input
–
–
–
–
–
–
–
95
P20.3
TIN61
T6INA
ARX3C
P20.3
TOUT61
ATX3
LP /
PU1 /
VEXT
GPT120 input
ASCLIN3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
SLSO09
SLSO29
TXDCAN3
–
QSPI0 output
QSPI2 output
CAN node 3 output
Reserved
–
Reserved
100
P20.6
TIN62
LP /
PU1 /
VEXT
General-purpose input
GTM input
P20.6
TOUT62
ARTS1
SLSO08
SLSO28
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
Data Sheet
2-31
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
101
Symbol
Ctrl
Type
Function
P20.7
TIN63
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS1A
ASCLIN1 input
CAN node 0 input
General-purpose output
GTM output
RXDCAN0B
P20.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT63
–
Reserved
–
Reserved
–
Reserved
–
Reserved
WDT1LCK
COUT63
SCU output
CCU61 output
General-purpose input
GTM input
102
P20.8
TIN64
MP /
PU1 /
VEXT
P20.8
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT64
ASLSO1
SLSO00
SLSO10
TXDCAN0
WDT0LCK
CC60
ASCLIN1 output
QSPI0 output
QSPI1 output
CAN node 0 output
SCU output
CCU61 output
General-purpose input
GTM input
103
P20.9
TIN65
LP /
PU1 /
VEXT
ARX1C
RXDCAN3E
REQ11
SLSI0B
P20.9
ASCLIN1 input
CAN node 3 input
SCU input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT65
–
Reserved
SLSO01
SLSO11
–
QSPI0 output
QSPI1 output
Reserved
WDTSLCK
CC61
SCU output
CCU61 output
Data Sheet
2-32
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
104
Symbol
Ctrl
Type
Function
P20.10
TIN66
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
P20.10
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT66
ATX1
ASCLIN1 output
QSPI0 output
QSPI2 output
CAN node 3 output
ASCLIN1 output
CCU61 output
General-purpose input
GTM input
SLSO06
SLSO27
TXDCAN3
ASCLK1
CC62
105
P20.11
TIN67
MP /
PU1 /
VEXT
SCLK0A
QSPI0 input
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT67
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
COUT60
CCU61 output
General-purpose input
GTM input
106
P20.12
TIN68
MP /
PU1 /
VEXT
MRST0A
P20.12
TOUT68
–
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MRST0
MTSR0
–
QSPI0 output
QSPI0 output
Reserved
–
Reserved
COUT61
CCU61 output
Data Sheet
2-33
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-8 Port 20 Functions (cont’d)
Pin
107
Symbol
Ctrl
Type
Function
P20.13
TIN69
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI0A
P20.13
TOUT69
–
QSPI0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
SLSO02
SLSO12
SCLK0
–
QSPI0 output
QSPI1 output
QSPI0 output
Reserved
COUT62
CCU61 output
General-purpose input
GTM input
108
P20.14
TIN70
MP /
PU1 /
VEXT
MTSR0A
QSPI0 input
General-purpose output
GTM output
P20.14
O0
O1
O2
O3
O4
O5
O6
O7
TOUT70
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
–
–
Reserved
Reserved
Reserved
Data Sheet
2-34
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-9 Port 21 Functions
Symbol
Ctrl
I
Type
Pin
84
Function
P21.2
TIN53
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
MRST2CN
MRST3FN
EMGSTOPB
RXDN
P21.2
QSPI2 input (LVDS)
QSPI3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT53
ASLSO3
–
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
–
Reserved
85
P21.3
TIN54
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
MRST2CP
QSPI2 input (LVDS)
QSPI3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
MRST3FP
RXDP
P21.3
O0
O1
O2
O3
O4
O5
O6
O7
TOUT54
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDIOD
HWOU
T
ETH input/output
Data Sheet
2-35
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-9 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
86
Function
P21.4
TIN55
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM output
TOUT55
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDN
HSCT output (LVDS)
General-purpose input
GTM input
87
P21.5
TIN56
I
LVDSH_P/
PU1 /
VDDP3
P21.5
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM output
TOUT56
ASCLK3
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDP
HSCT output (LVDS)
General-purpose input
GTM input
881)
P21.6
TIN57
I
A2 /
PU /
VDDP3
ARX3F
TGI2
TDI
ASCLIN3 input
OCDS input
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
TOUT57
ASLSO3
–
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
Reserved
–
Reserved
SYSCLK
–
HSCT output
Reserved
T3OUT
TGO2
GPT120 output
OCDS; ENx
HWOU
T
Data Sheet
2-36
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-9 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
90
Function
P21.7
TIN58
A2 /
PU /
VDDP3
General-purpose input
GTM input
DAP2
OCDS (3-Pin DAP) input
In the 3-Pin DAP mode this pin is used as DAP2.
In the 2-PIN DAP mode this pin is used as P21.7
and controlled by the related port control logic.
TGI3
ETHRXERB
T5INA
P21.7
TOUT58
ATX3
ASCLK3
–
OCDS input
ETH input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
T6OUT
TGO3
TDO
GPT120 output
OCDS; ENx
HWOU
T
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ.
DAP2
OCDS (DAP2); ENx
In the 3-Pin DAP mode this pin is used as DAP2.
1) For an Emulation Device in a non Fusion Quad package this pin is used as VDDPSB (3.3V)
Table 2-10 Port 22 Functions
Pin
74
Symbol
Ctrl
Type
Function
P22.0
TIN47
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
MTSR3E
P22.0
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT47
–
Reserved
MTSR3
SCLK3N
FCLN1
FCLND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
2-37
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-10 Port 22 Functions (cont’d)
Pin
75
Symbol
Ctrl
Type
Function
P22.1
TIN48
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
MRST3E
P22.1
TOUT48
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST3
SCLK3P
FCLP1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
76
P22.2
TIN49
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3D
P22.2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT49
–
Reserved
SLSO312
MTSR3N
SON1
SOND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
77
P22.3
TIN50
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
SCLK3E
P22.3
TOUT50
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK3
MTSR3P
SOP1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
Data Sheet
2-38
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-11 Port 23 Functions
Pin
73
Symbol
Ctrl
Type
Function
P23.1
TIN42
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
SDI10
P23.1
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT42
ARTS1
SLSO313
GTMCLK0
–
ASCLIN1 output
QSPI3 output
GTM output
Reserved
EXTCLK0
–
SCU output
Reserved
Table 2-12 Port 32 Functions
Pin
70
Symbol
Ctrl
Type
Function
P32.0
TIN36
I
LP /
PX/
VEXT
General-purpose input
GTM input
FDEST
PMU input
VGATE1N
SMPS mode: analog output. External Pass Device
gate control for EVR13
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT36
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
2-39
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-12 Port 32 Functions (cont’d)
Pin
72
Symbol
Ctrl
Type
Function
P32.4
TIN40
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ACTS1B
SDI12
ASCLIN1 input
MSC1 input
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT40
–
Reserved
END12
GTMCLK1
EN10
MSC1 output
GTM output
MSC1 output
SCU output
EXTCLK1
COUT63
CCU60 output
Table 2-13 Port 33 Functions
Pin
60
Symbol
Ctrl
Type
Function
P33.4
TIN26
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
CTRAPC
DSITR0F
P33.4
CCU61 input
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
ASCLIN2 output
Reserved
–
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
2-40
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
61
Symbol
Ctrl
Type
Function
P33.5
TIN27
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
62
P33.6
TIN28
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
–
ASCLIN2 output
Reserved
PSITX2
PSI5 output
VADCEMUX10
VADCG0BFL2
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
2-41
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
63
Symbol
Ctrl
Type
Function
P33.7
TIN29
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO37
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
VADCG0BFL3
–
VADC output
Reserved
64
P33.8
TIN30
MP /
HighZ/
VEXT
General-purpose input
GTM input
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI3 output
Reserved
SLSO32
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
65
P33.9
TIN31
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HSIC3INA
P33.9
TOUT31
ATX2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI3 output
ASCLIN2 output
Reserved
SLSO31
ASCLK2
–
–
Reserved
CC62
CCU61 output
Data Sheet
2-42
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
66
Symbol
Ctrl
Type
Function
P33.10
TIN32
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3C
HSIC3INB
P33.10
QSPI3 input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT32
SLSO16
SLSO311
ASLSO1
PSISCLK
–
QSPI1 output
QSPI3 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
CCU61 output
General-purpose input
GTM input
67
P33.11
TIN33
MP /
PU1 /
VEXT
SCLK3D
P33.11
TOUT33
ASCLK1
SCLK3
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC output
CCU61 output
General-purpose input
GTM input
68
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR3D
P33.12
TOUT34
ATX1
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
ASCLIN1 output
Reserved
MTSR3
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
2-43
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-13 Port 33 Functions (cont’d)
Pin
69
Symbol
Ctrl
Type
Function
P33.13
TIN35
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1F
MRST3D
DSSGNB
INJ11
ASCLIN1 input
QSPI3 input
DSADC input
MSC1 input
P33.13
TOUT35
ATX1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
QSPI2 output
Reserved
MRST3
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
Table 2-14 Port 40 Functions
Pin
36
Symbol
Ctrl
Type
Function
P40.0
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 8 of group 1
CCU60 input
VADCG1.8
CCPOS0D
SENT0A
SENT input
35
33
P40.1
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 9 of group 1 (MD)
CCU60 input
VADCG1.9
CCPOS1B
SENT1A
SENT input
P40.6
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 3, pin A
CCU61 input
VADCG2.4
DS3PA
CCPOS1B
SENT2D
SENT input
32
P40.7
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 5 of group 2
VADCG2.5
DS3NA
DSADC: negative analog input channel of DSADC 3,
pin A
CCPOS1D
SENT3D
CCU61 input
SENT input
Data Sheet
2-44
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-14 Port 40 Functions (cont’d)
Pin
31
Symbol
Ctrl
Type
Function
P40.8
I
S /
General-purpose input
HighZ /
VDDM
VADCG2.6
VADC analog input channel 6 of group 2
DSADC: positive analog input of channel 3, pin B
CCU61 input
DS3PB
CCPOS2B
SENT4A
SENT input
30
P40.9
I
S /
General-purpose input
HighZ /
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
DS3NB
DSADC: negative analog input channel of DSADC 3,
pin B
CCPOS2D
SENT5A
CCU61 input
SENT input
Table 2-15 Analog Inputs
Pin
57
Symbol
Ctrl
Type
Function
AN0
I
D /
Analog input 0
HighZ /
VDDM
VADCG0.0
VADC analog input channel 0 of group 0
DSADC: positive analog input of channel 0, pin B
Analog input 1
DS0PB
56
AN1
I
D /
HighZ /
VDDM
VADCG0.1
VADC analog input channel 1 of group 0 (MD)
DS0NB
DSADC: negative analog input channel of DSADC 0,
pin B
55
54
AN2
I
I
D /
HighZ /
VDDM
Analog input 2
VADCG0.2
VADC analog input channel 2 of group 0 (MD)
DSADC: positive analog input of channel 0, pin A
Analog input 3
DS0PA
AN3
D /
HighZ /
VDDM
VADCG0.3
VADC analog input channel 3 of group 0
DS0NA
DSADC: negative analog input channel of DSADC 0,
pin A
53
52
51
50
AN4
I
I
I
I
D /
HighZ /
VDDM
Analog input 4
VADCG0.4
VADC analog input channel 4 of group 0
AN5
D /
HighZ /
VDDM
Analog input 5
VADCG0.5
VADC analog input channel 5 of group 0
AN6
D /
HighZ /
VDDM
Analog input 6
VADCG0.6
VADC analog input channel 6 of group 0
AN7
D /
Analog input 7
HighZ /
VDDM
VADCG0.7
VADC analog input channel 7 of group 0 (with pull
down diagnostics)
Data Sheet
2-45
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-15 Analog Inputs (cont’d)
Pin
49
Symbol
Ctrl
Type
Function
AN8
I
D /
Analog input 8
HighZ /
VDDM
VADCG0.8
VADC analog input channel 8 of group 0
48
47
46
45
40
39
38
AN10
I
I
I
I
I
I
I
D /
HighZ /
VDDM
Analog input 10
VADCG0.10
VADC analog input channel 10 of group 0 (MD)
AN11
D /
HighZ /
VDDM
Analog input 11
VADCG0.11
VADC analog input channel 11 of group 0
AN12
D /
HighZ /
VDDM
Analog input 12
VADCG0.12
VADC analog input channel 12 of group 0
AN13
D /
HighZ /
VDDM
Analog input 13
VADCG0.13
VADC analog input channel 13 of group 0
AN16
D /
HighZ /
VDDM
Analog input 16
VADCG1.0
VADC analog input channel 0 of group 1
AN17
D /
HighZ /
VDDM
Analog input 17
VADCG1.1
VADC analog input channel 1 of group 1 (MD)
AN20
D /
Analog input 20
HighZ /
VDDM
VADCG1.4
VADC analog input channel 4 of group 1
DSADC: positive analog input of channel 2, pin A
Analog input 21
DS2PA
37
AN21
I
D /
HighZ /
VDDM
VADCG1.5
VADC analog input channel 5 of group 1
DS2NA
DSADC: negative analog input channel of DSADC 2,
pin A
36
35
AN24
I
I
S /
HighZ /
VDDM
Analog input 24
VADCG1.8
VADC analog input channel 8 of group 1
SENT input channel 0, pin A
Analog input 24
SENT0A
AN25
S /
HighZ /
VDDM
VADCG1.9
SENT1A
VADC analog input channel 9of group 1 (MD)
SENT input channel 1, pin A
Analog input 35
34
33
AN35
I
I
D /
HighZ /
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
AN36
S /
Analog input 34
HighZ /
VDDM
VADCG2.4
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 3, pin A
SENT input channel 2, pin D
DS3PA
SENT2D
Data Sheet
2-46
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-15 Analog Inputs (cont’d)
Pin
32
Symbol
Ctrl
Type
Function
AN37
I
S /
Analog input 37
HighZ /
VDDM
VADCG2.5
VADC analog input channel 5 of group 2
DS3NA
DSADC: negative analog input channel of DSADC 3,
pin A
SENT3D
SENT input channel 3, pin D
Analog input 38
31
30
AN38
I
I
S /
HighZ /
VDDM
VADCG2.6
VADC analog input channel 6 of group 2
DSADC: positive analog input of channel 3, pin B
SENT input channel 4, pin A
Analog input 39
DS3PB
SENT4A
AN39
S /
HighZ /
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
DS3NB
DSADC: negative analog input channel of DSADC 3,
pin B
SENT5A
SENT input channel 5, pin A
29
28
AN44
I
I
D /
HighZ /
VDDM
Analog input 44
VADCG2.10
VADC analog input channel 10 of group 2 (MD)
DSADC: positive analog input of channel 3, pin C
Analog input 45
DS3PC
AN45
D /
HighZ /
VDDM
VADCG2.11
VADC analog input channel 11 of group 2
DS3NC
DSADC: negative analog input channel of DSADC 3,
pin C
27
26
AN46
I
I
D /
HighZ /
VDDM
Analog input 46
VADCG2.12
VADC analog input channel 12 of group 24
DSADC: positive analog input of channel 3, pin D
Analog input 47
DS3PD
AN47
D /
HighZ /
VDDM
VADCG2.13
VADC analog input channel 13 of group 2
DS3ND
DSADC: negative analog input channel of DSADC 3,
pin D
25
24
AN48
I
I
D /
HighZ /
VDDM
Analog input 48
VADCG2.14
VADC analog input channel 14 of group 2
AN49
D /
Analog input 49
HighZ /
VDDM
VADCG2.15
VADC analog input channel 15 of group 2
Data Sheet
2-47
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-16 System I/O
Pin
97
Symbol
Ctrl
Type
Function
PORST
I
PORST /
PD /
Power On Reset Input
Additional strong PD in case of power fail.
VEXT
98
ESR0
I/O
MP / OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished.
See also SCU chapter for details.
Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR
register description.
EVRWUP
ESR1
I
EVR Wakeup Pin
96
I/O
MP /
External System Request Reset 1
PU1 /
VEXT
Default NMI function. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
EVRWUP
I
EVR Wakeup Pin
71
89
91
92
VGATE1P
O
VGATE1P / External Pass Device gate control for EVR13
- /
VEXT
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
TRST
I
A2 /
JTAG Module Reset/Enable Input
PD /
VDDP3
TCK
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
81
82
XTAL1
XTAL2
I
XTAL1 /
- / -
Main Oscillator/PLL/Clock Generator Input
Main Oscillator/PLL/Clock Generator Output
O
XTAL2 /
- / -
Table 2-17 Supply
Pin
42
Symbol
Ctrl
Type
Vx
Function
VAREF1
I
Positive Analog Reference Voltage 1
41
44
VAGND1
VDDM
I
I
Vx
Vx
Negative Analog Reference Voltage 1
ADC Analog Power Supply (3.3V / 5V)
Data Sheet
2-48
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
Table 2-17 Supply (cont’d)
Pin
10
Symbol
Ctrl
Type
Vx
Function
VDD / VDDSB
I
Emulation Device: Emulation SRAM Standby Power
Supply (1.3V) (Emulation Device only).
Production Device: VDD (1.3V).
99, 58, 22 VDD
I
I
Vx
Vx
Digital Core Power Supply (1.3V)
79
VDD
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (1.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
125, 78,
59, 23
VEXT
I
I
I
Vx
Vx
Vx
External Supply (5V / 3.3V)
126
83
VDDP3
VDDP3
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power Supply for
VFLEX.
Digital Power Supply for Oscillator, LVDSH and A2
pads (3.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (3.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
127
136
VDDFL3
VFLEX
I
I
Vx
Vx
Flash Power Supply (3.3V)
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
80
43
VSS
I
I
Vx
Vx
Digital Ground
VSSM
Analog Ground for VDDM
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
Data Sheet
2-49
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSH (LVDS/CMOS 3.3V)
S = Pad class S (ADC overlay with General Purpose Input)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply (the Exposed Pad is also considered as VSS and shall be connected to ground)
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
2.1.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during PORST active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
2-50
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC264x Pin Definition and Functions:
•
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O
Ports and Peripheral I/O Lines”, P00 / P01)
•
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
2.1.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-18 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
2-51
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
2.2
TC265x Pin Definition and Functions: LQFP176
Figure 2-1 is showing the TC265x Logic Symbol for the package variant: QFP176.
P02.0
1
132
131
130
129
P20. 14
P20. 13
P20. 12
P20. 11
P02.1
P02.2
P02.3
P02.4
2
3
4
5
128
127
126
125
P20. 10
P20. 9
P20. 8
P20. 7
P02.5
P02.6
P02.7
P02.8
6
7
8
9
124
123
122
121
P20. 6
VDD
ESR0
PORST
V
DD/VDDSB
P00.0
P00.1
P00.2
10
11
12
13
120
119
118
117
ESR1
P20. 3
P20. 2 / TESTMODE
P20. 1
P20. 0
P00.3
P00.4
P00.5
P00.6
14
15
16
17
116
115
114
113
P00.7
P00.8
P00.9
18
19
20
21
TCK
TRST
P21. 7 / TDO
TMS
P00.10
112
111
110
109
P00.11
P00.12
VDD
VEXT
AN49
22
23
24
25
26
P21. 6 / TDI
P21. 5
P21. 4
TC26x
P21. 3
108
107
106
105
104
P21. 2
P21. 1
P21. 0
AN48
AN47
AN46
AN45
27
28
29
30
VDDP
3
103
102
101
100
XTAL2
XTAL1
VSS
AN44
AN39
AN38
AN37
31
32
33
34
VDD
99
98
97
96
VEXT
AN36
AN35
AN33
AN32
35
36
37
38
P22. 3
P22. 2
P22. 1
95
94
93
92
P22. 0
P23. 5
P23. 4
P23. 3
P23. 2
AN29
AN28
AN27
AN26
39
40
41
42
91
90
89
AN25
AN24
43
44
P23. 1
P23. 0
Figure 2-2 TC265x Logic Symbol for the package variant LQFP176.
Data Sheet
2-52
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
2.2.1
TC265 LQFP176 Package Variant Pin Configuration
Table 2-19 Port 00 Functions
Pin
11
Symbol
Ctrl
Type
Function
P00.0
TIN9
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I/O
I
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
General-purpose input
GTM input
12
P00.1
TIN10
LP /
PU1 /
VEXT
ARX3E
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN0A
VADCG3.11
CIFD10
P00.1
ASCLIN3 input
CAN node 1 input
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 0 input A
VADC analog input channel 11 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
Reserved
–
DSCOUT0
–
DSADC channel 0 output
Reserved
SPC0
SENT output
CC60
CCU61 output
Data Sheet
2-53
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
13
Symbol
Ctrl
Type
Function
P00.2
TIN11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT1B
DSDIN0A
VADCG3.10
CIFD11
P00.2
SENT input
DSADC channel 0 input A
VADC analog input channel 10 of group 3 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT11
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
TXDCAN3
–
PSI5 output
CAN node 3 output
Reserved
COUT60
CCU61 output
14
P00.3
TIN12
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN3A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG3.9
CIFD12
P00.3
CAN node 3 input
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input A
VADC analog input channel 9 of group 3 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
Data Sheet
2-54
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
15
Symbol
Ctrl
Type
Function
P00.4
TIN13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG3.8
CIFD13
SENT input
DSADC channel 3 input A
DSADC input
VADC analog input channel 8 of group 3
CIF input
P00.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT13
PSISTX
TXDCAN4
PSITX1
PSI5-S output
CAN node 4 output
PSI5 output
VADCG2BFL0
SPC3
VADC output
SENT output
COUT61
CCU61 output
16
P00.5
TIN14
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSIRX2A
SENT4B
RXDCAN4A
CC62INB
CC62INA
DSCIN2A
VADCG3.7
CIFD14
PSI5 input
SENT input
CAN node 4 input
CCU60 input
CCU61 input
DSADC channel 2 input A
VADC analog input channel 7 of group 3
CIF input
P00.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT14
DSCGPWMN
–
DSADC output
Reserved
DSCOUT2
VADCG2BFL1
SPC4
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
Data Sheet
2-55
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
17
Symbol
Ctrl
Type
Function
P00.6
TIN15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT5B
SENT input
DSDIN2A
VADCG3.6
CIFD15
DSADC channel 2 input A
VADC analog input channel 6 of group 3
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG2BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
CCU61 output
General-purpose input
GTM input
18
P00.7
TIN16
LP /
PU1 /
VEXT
CC60INC
CCPOS0A
T12HRB
T2INA
CCU61 input
CCU61 input
CCU60 input
GPT120 input
VADCG3.5
CIFCLK
P00.7
VADC analog input channel 5 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG2BFL3
–
VADC output
Reserved
VADCEMUX11
–
VADC output
Reserved
CC60
CCU61 output
Data Sheet
2-56
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
19
Symbol
Ctrl
Type
Function
P00.8
TIN17
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
CC61INC
CCPOS1A
T13HRB
T2EUDA
VADCG3.4
CIFVSNC
P00.8
CCU61 input
CCU61 input
CCU60 input
GPT120 input
VADC analog input channel 4 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
–
VADC output
Reserved
CC61
CCU61 output
General-purpose input
GTM input
20
P00.9
TIN18
LP /
PU1 /
VEXT
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
VADCG3.3
DSITR3F
CIFHSNC
P00.9
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
VADC analog input channel 3 of group 3
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
–
QSPI3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
CC62
CCU61 output
Data Sheet
2-57
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-19 Port 00 Functions (cont’d)
Pin
21
Symbol
Ctrl
Type
Function
P00.10
TIN19
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
VADCG3.2
VADC analog input channel 2 of group 3 (MD)
General-purpose output
GTM output
P00.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT19
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
General-purpose input
GTM input
22
P00.11
TIN20
LP /
PU1 /
VEXT
CTRAPA
CCU60 input
T12HRE
CCU61 input
VADCG3.1
VADC analog input channel of group 3
General-purpose output
GTM output
P00.11
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT20
–
Reserved
–
Reserved
DSCOUT0
DSADC channel 0 output
Reserved
–
–
–
Reserved
Reserved
23
P00.12
TIN21
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS3A
ASCLIN3 input
VADC analog input channel 0 of group 3
General-purpose output
GTM output
VADCG3.0
P00.12
O0
O1
O2
O3
O4
O5
O6
O7
TOUT21
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
Data Sheet
2-58
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-20 Port 02 Functions
Pin
1
Symbol
Ctrl
Type
Function
P02.0
TIN0
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ARX2G
REQ6
ASCLIN2 input
SCU input
CC60INA
CC60INB
CIFD0
CCU60 input
CCU61 input
CIF input
P02.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY output
SLSO31
DSCGPWMN
TXDCAN0
TXDA
CC60
CCU60 output
2
P02.1
TIN1
LP / PU1 General-purpose input
/ VEXT
GTM input
REQ14
ARX2B
RXDCAN0A
RXDA2
CIFD1
P02.1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT1
–
Reserved
SLSO32
DSCGPWMP
–
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
2-59
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-20 Port 02 Functions (cont’d)
Pin
3
Symbol
Ctrl
Type
Function
P02.2
TIN2
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
PSI5 output
SLSO33
PSITX0
TXDCAN2
TXDB
CAN node 2 output
ERAY output
CCU60 output
General-purpose input
GTM input
CC61
4
P02.3
TIN3
LP /
PU1 /
VEXT
ARX1G
RXDCAN2B
RXDB2
PSIRX0B
SDI11
CIFD3
P02.3
ASCLIN1 input
CAN node 2 input
ERAY input
PSI5 input
MSC1 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
2-60
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-20 Port 02 Functions (cont’d)
Pin
5
Symbol
Ctrl
Type
Function
P02.4
TIN4
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3A
ECTT1
QSPI3 input
TTCAN input
CAN node 0 input
CCU60 input
CCU61 input
I2C0 input
RXDCAN0D
CC62INA
CC62INB
SDA0A
CIFD4
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXENA
CC62
ERAY output
CCU60 output
General-purpose input
GTM input
6
P02.5
TIN5
MP+ /
PU1 /
VEXT
MRST3A
ECTT2
PSIRX1B
PSISRXB
SENT3C
SCL0A
CIFD5
QSPI3 input
TTCAN input
PSI5 input
PSI5-S input
SENT input
I2C0 input
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
–
CAN node 0 output
QSPI3 output
Reserved
SCL0
I2C0 output
TXENB
COUT62
ERAY output
CCU60 output
Data Sheet
2-61
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-20 Port 02 Functions (cont’d)
Pin
7
Symbol
Ctrl
Type
Function
P02.6
TIN6
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
P02.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
General-purpose input
GTM input
8
P02.7
TIN7
MP /
PU1 /
VEXT
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
P02.7
DSADC channel 3 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSADC channel 3 output
VADC output
SENT output
CCU60 output
DSCOUT3
VADCEMUX01
SPC1
CC61
Data Sheet
2-62
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-20 Port 02 Functions (cont’d)
Pin
9
Symbol
Ctrl
Type
Function
P02.8
TIN8
I
LP / PU1 General-purpose input
/
VEXT
GTM input
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
CIFD8
DSDIN3B
DSITR3E
P02.8
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
Table 2-21 Port 10 Functions
Pin
168
Symbol
Ctrl
Type
Function
P10.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN102
T6EUDB
GPT120 input
General-purpose output
GTM output
P10.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT102
–
Reserved
SLSO110
QSPI1 output
Reserved
–
VADCG3BFL0
VADC output
Reserved
–
–
Reserved
Data Sheet
2-63
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-21 Port 10 Functions (cont’d)
Pin
169
Symbol
Ctrl
Type
Function
P10.1
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG3BFL1
END03
–
170
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
QSPI1 input
GPT120 input
SCU input
REQ2
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG3BFL2
END02
–
Data Sheet
2-64
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-21 Port 10 Functions (cont’d)
Pin
171
Symbol
Ctrl
Type
Function
P10.3
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG3BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
172
P10.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN106
MTSR1C
CCPOS0C
T3INB
P10.4
QSPI1 input
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT106
–
Reserved
SLSO18
MTSR1
EN00
QSPI1 output
QSPI1 output
MSC0 output
MSC0 output
Reserved
END02
–
Data Sheet
2-65
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-21 Port 10 Functions (cont’d)
Pin
173
Symbol
Ctrl
Type
Function
P10.5
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
RXDCAN4B
INJ01
SCU input
CAN node 4 input
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
QSPI1 output
GPT120 output
ASCLIN2 output
Reserved
SLSO38
SLSO19
T6OUT
ASLSO2
–
174
P10.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
ASCLIN2 input
QSPI3 input
MTSR3B
HWCFG5
P10.6
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
ASCLIN2 output
QSPI3 output
GPT120 output
CAN node 4 output
QSPI1 output
VADC output
T3OUT
TXDCAN4
MRST1
VADCG3BFL0
Data Sheet
2-66
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-21 Port 10 Functions (cont’d)
Pin
175
Symbol
Ctrl
Type
Function
P10.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN109
ACTS2A
MRST3B
REQ4
CCPOS1C
T3EUDB
P10.7
ASCLIN2 input
QSPI3 input
SCU input
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT109
–
Reserved
MRST3
VADCG3BFL1
–
QSPI3 output
VADC output
Reserved
–
Reserved
–
Reserved
176
P10.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN110
SCLK3B
REQ5
CCPOS2C
T4INB
P10.8
TOUT110
ARTS2
SCLK3
–
QSPI3 input
SCU input
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
2-67
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-22 Port 11 Functions
Pin
160
Symbol
Ctrl
Type
Function
P11.2
TIN95
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
P11.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT95
END03
SLSO05
SLSO15
EN01
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
CCU60 output
General-purpose input
GTM input
161
P11.3
TIN96
MPR /
PU1 /
VFLEX
MRST1B
SDI03
P11.3
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT96
–
Reserved
MRST1
TXDA
–
QSPI1 output
ERAY output
Reserved
ETHTXD0
COUT62
ETH output
CCU60 output
General-purpose input
GTM input
162
P11.6
TIN97
MPR /
PU1 /
VFLEX
SCLK1B
P11.6
QSPI1 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT97
TXENB
SCLK1
ERAY output
QSPI1 output
ERAY output
MSC0 output
ETH output
TXENA
FCLP0
ETHTXEN
COUT61
CCU60 output
Data Sheet
2-68
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-22 Port 11 Functions (cont’d)
Pin
163
Symbol
Ctrl
Type
Function
P11.9
TIN98
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
MTSR1B
RXDA1
ETHRXD1
P11.9
TOUT98
–
QSPI1 input
ERAY input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
–
MSC0 output
Reserved
COUT60
CCU60 output
General-purpose input
GTM input
165
P11.10
TIN99
LP /
PU1 /
VFLEX
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXDB1
ETHRXD0
SDI00
P11.10
TOUT99
–
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY input
ETH input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
Data Sheet
2-69
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-22 Port 11 Functions (cont’d)
Pin
166
Symbol
Ctrl
Type
Function
P11.11
TIN100
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
ETHCRSDVA
P11.11
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT100
END02
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY output
CCU60 output
General-purpose input
GTM input
SLSO04
SLSO14
EN00
TXENB
CC61
167
P11.12
TIN101
MPR /
PU1 /
VFLEX
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
ETHRXCLKA
ETH input
(Not for productive purposes)
P11.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT101
ATX1
ASCLIN1 output
GTM output
GTMCLK2
TXDB
ERAY output
TXDCAN3
EXTCLK1
CC60
CAN node 3 output
SCU output
CCU60 output
Table 2-23 Port 13 Functions
Pin
156
Symbol
Ctrl
Type
Function
P13.0
TIN91
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
P13.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT91
END03
SCLK2N
EN01
MSC0 output
QSPI2 output (LVDS)
MSC0 output
FCLN0
FCLND0
TXDCAN4
MSC0 output (LVDS)
MSC0 output (LVDS)
CAN node 4 output
Data Sheet
2-70
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-23 Port 13 Functions (cont’d)
Pin
157
Symbol
Ctrl
Type
Function
P13.1
TIN92
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
SCL0B
RXDCAN4C
P13.1
TOUT92
–
I2C0 input
CAN node 4 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
–
MSC0 output (LVDS)
I2C0 output
Reserved
158
P13.2
TIN93
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
CAPINA
SDA0B
P13.2
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT93
–
Reserved
MTSR2N
FCLP0
SON0
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
SDA0
SOND0
MSC0 output (LVDS)
General-purpose input
GTM input
159
P13.3
TIN94
LVDSM_P /
PU1 /
VEXT
P13.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT94
–
Reserved
MTSR2P
QSPI2 output (LVDS)
Reserved
–
SOP0
MSC0 output (LVDS)
Reserved
–
–
Reserved
Data Sheet
2-71
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-24 Port 14 Functions
Pin
142
Symbol
Ctrl
Type
Function
P14.0
TIN80
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P14.0
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
TXDA
O3
O4
O5
ERAY output
ERAY output
TXDB
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function.
ASCLK0
COUT62
O6
O7
I
ASCLIN0 output
CCU60 output
General-purpose input
GTM input
143
P14.1
TIN81
MP /
PU1 /
VEXT
REQ15
SCU input
ARX0A
ASCLIN0 input
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function.
RXDA3
RXDB3
EVRWUPA
P14.1
ERAY input
ERAY input
SCU input
O0
O1
O2
General-purpose output
GTM output
TOUT81
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
–
O3
O4
O5
O6
O7
Reserved
Reserved
Reserved
Reserved
CCU60 output
–
–
–
COUT63
Data Sheet
2-72
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-24 Port 14 Functions (cont’d)
Pin
144
Symbol
Ctrl
Type
Function
P14.2
TIN82
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
SLSO21
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
145
P14.3
TIN83
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX2A
REQ10
HWCFG3_BMI
SDI02
ASCLIN2 input
SCU input
SCU input
MSC0 input
P14.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT83
ATX2
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
Data Sheet
2-73
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-24 Port 14 Functions (cont’d)
Pin
146
Symbol
Ctrl
Type
Function
P14.4
TIN84
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT84
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
147
P14.5
TIN85
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT85
–
–
Reserved
–
Reserved
–
Reserved
TXDB
–
ERAY output
Reserved
148
P14.6
TIN86
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT86
–
SLSO22
QSPI2 output
Reserved
–
–
Reserved
TXENB
–
ERAY output
Reserved
Data Sheet
2-74
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-24 Port 14 Functions (cont’d)
Pin
149
Symbol
Ctrl
Type
Function
P14.7
TIN87
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDB0
ERAY input
P14.7
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT87
ARTS0
ASCLIN0 output
QSPI2 output
Reserved
SLSO24
–
–
–
–
Reserved
Reserved
Reserved
150
P14.8
TIN88
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1D
ASCLIN1 input
CAN node 2 input
ERAY input
RXDCAN2D
RXDA0
P14.8
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT88
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
151
P14.9
TIN89
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ACTS0A
P14.9
TOUT89
END03
EN01
–
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
MSC0 output
MSC0 output
Reserved
TXENB
TXENA
–
ERAY output
ERAY output
Reserved
Data Sheet
2-75
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-24 Port 14 Functions (cont’d)
Pin
152
Symbol
Ctrl
Type
Function
P14.10
TIN90
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P14.10
TOUT90
END02
EN00
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
MSC0 output
ATX1
ASCLIN1 output
CAN node 2 output
ERAY output
TXDCAN2
TXDA
–
Reserved
Table 2-25 Port 15 Functions
Pin
133
Symbol
Ctrl
Type
Function
P15.0
TIN71
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
P15.0
TOUT71
ATX1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
Reserved
SLSO013
–
TXDCAN2
ASCLK1
–
CAN node 2 output
ASCLIN1 output
Reserved
134
P15.1
TIN72
LP /
PU1 /
VEXT
General-purpose input
GTM input
REQ16
SCU input
ARX1A
ASCLIN1 input
CAN node 2 input
QSPI2 input
RXDCAN2A
SLSI2B
EVRWUPB
SCU input
P15.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT72
ATX1
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
–
–
Reserved
Reserved
Reserved
Data Sheet
2-76
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-25 Port 15 Functions (cont’d)
Pin
135
Symbol
Ctrl
Type
Function
P15.2
TIN73
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI2A
MRST2E
HSIC2INA
P15.2
QSPI2 input
QSPI2 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT73
ATX0
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
136
P15.3
TIN74
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX0B
SCLK2A
RXDCAN1A
HSIC2INB
P15.3
ASCLIN0 input
QSPI2 input
CAN node 1 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT74
ATX0
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
Data Sheet
2-77
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-25 Port 15 Functions (cont’d)
Pin
137
Symbol
Ctrl
Type
Function
P15.4
TIN75
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
MRST2A
REQ0
SCL0C
P15.4
TOUT75
ATX1
MRST2
–
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
–
Reserved
SCL0
CC62
I2C0 output
CCU60 output
General-purpose input
GTM input
138
P15.5
TIN76
MP /
PU1 /
VEXT
ARX1B
MTSR2A
SDA0C
REQ13
P15.5
ASCLIN1 input
QSPI2 input
I2C0 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT76
ATX1
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
General-purpose input
GTM input
139
P15.6
TIN77
MP /
PU1 /
VEXT
MTSR2B
P15.6
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT77
ATX3
ASCLIN3 output
QSPI2 output
Reserved
MTSR2
–
SCLK2
ASCLK3
CC60
QSPI2 output
ASCLIN3 output
CCU60 output
Data Sheet
2-78
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-25 Port 15 Functions (cont’d)
Pin
140
Symbol
Ctrl
Type
Function
P15.7
TIN78
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX3A
MRST2B
P15.7
TOUT78
ATX3
MRST2
–
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
COUT60
CCU60 output
General-purpose input
GTM input
141
P15.8
TIN79
MP /
PU1 /
VEXT
SCLK2B
REQ1
P15.8
TOUT79
–
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
ASCLIN3 output
CCU60 output
Data Sheet
2-79
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-26 Port 20 Functions
Pin
116
Symbol
Ctrl
Type
Function
P20.0
TIN59
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN3C
T6EUDA
REQ9
SYSCLK
TGI0
CAN node 3 input
GPT120 input
SCU input
HSCT input
OCDS input
P20.0
TOUT59
ATX3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
117
P20.1
TIN60
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TGI1
OCDS input
General-purpose output
GTM output
Reserved
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
TOUT60
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO1
HWOU
T
OCDS; ENx
Data Sheet
2-80
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-26 Port 20 Functions (cont’d)
Pin
118
Symbol
Ctrl
Type
Function
P20.2
I
LP /
General-purpose input
PU /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
OCDS input
P20.2
O0
O1
O2
O3
O4
O5
O6
O7
I
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
General-purpose input
GTM input
–
–
–
–
–
–
–
119
P20.3
TIN61
T6INA
ARX3C
P20.3
TOUT61
ATX3
LP /
PU1 /
VEXT
GPT120 input
ASCLIN3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
SLSO09
SLSO29
TXDCAN3
–
QSPI0 output
QSPI2 output
CAN node 3 output
Reserved
–
Reserved
124
P20.6
TIN62
LP /
PU1 /
VEXT
General-purpose input
GTM input
P20.6
TOUT62
ARTS1
SLSO08
SLSO28
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
Data Sheet
2-81
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-26 Port 20 Functions (cont’d)
Pin
125
Symbol
Ctrl
Type
Function
P20.7
TIN63
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS1A
ASCLIN1 input
CAN node 0 input
General-purpose output
GTM output
RXDCAN0B
P20.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT63
–
Reserved
–
Reserved
–
Reserved
–
Reserved
WDT1LCK
COUT63
SCU output
CCU61 output
General-purpose input
GTM input
126
P20.8
TIN64
MP /
PU1 /
VEXT
P20.8
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT64
ASLSO1
SLSO00
SLSO10
TXDCAN0
WDT0LCK
CC60
ASCLIN1 output
QSPI0 output
QSPI1 output
CAN node 0 output
SCU output
CCU61 output
General-purpose input
GTM input
127
P20.9
TIN65
LP /
PU1 /
VEXT
ARX1C
RXDCAN3E
REQ11
SLSI0B
P20.9
ASCLIN1 input
CAN node 3 input
SCU input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT65
–
Reserved
SLSO01
SLSO11
–
QSPI0 output
QSPI1 output
Reserved
WDTSLCK
CC61
SCU output
CCU61 output
Data Sheet
2-82
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-26 Port 20 Functions (cont’d)
Pin
128
Symbol
Ctrl
Type
Function
P20.10
TIN66
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
P20.10
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT66
ATX1
ASCLIN1 output
QSPI0 output
QSPI2 output
CAN node 3 output
ASCLIN1 output
CCU61 output
General-purpose input
GTM input
SLSO06
SLSO27
TXDCAN3
ASCLK1
CC62
129
P20.11
TIN67
MP /
PU1 /
VEXT
SCLK0A
QSPI0 input
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT67
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
COUT60
CCU61 output
General-purpose input
GTM input
130
P20.12
TIN68
MP /
PU1 /
VEXT
MRST0A
P20.12
TOUT68
–
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MRST0
MTSR0
–
QSPI0 output
QSPI0 output
Reserved
–
Reserved
COUT61
CCU61 output
Data Sheet
2-83
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-26 Port 20 Functions (cont’d)
Pin
131
Symbol
Ctrl
Type
Function
P20.13
TIN69
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI0A
P20.13
TOUT69
–
QSPI0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
SLSO02
SLSO12
SCLK0
–
QSPI0 output
QSPI1 output
QSPI0 output
Reserved
COUT62
CCU61 output
General-purpose input
GTM input
132
P20.14
TIN70
MP /
PU1 /
VEXT
MTSR0A
QSPI0 input
General-purpose output
GTM output
P20.14
O0
O1
O2
O3
O4
O5
O6
O7
TOUT70
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
–
–
Reserved
Reserved
Reserved
Table 2-27 Port 21 Functions
Symbol
Ctrl
Type
Pin
105
Function
P21.0
TIN51
I
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT51
–
–
Reserved
–
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
Data Sheet
2-84
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-27 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
106
Function
P21.1
TIN52
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
ETHMDIOB
ETH input
(Not for production purposes)
P21.1
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM output
Reserved
TOUT52
–
–
Reserved
–
Reserved
–
Reserved
ETHMDIO
ETH output
(Not for production purposes)
–
O7
I
Reserved
107
P21.2
TIN53
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
MRST2CN
MRST3FN
EMGSTOPB
RXDN
P21.2
QSPI2 input (LVDS)
QSPI3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT53
ASLSO3
–
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
–
Reserved
Data Sheet
2-85
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-27 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
108
Function
P21.3
TIN54
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
MRST2CP
QSPI2 input (LVDS)
QSPI3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
MRST3FP
RXDP
P21.3
O0
O1
O2
O3
O4
O5
O6
O7
TOUT54
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDIOD
HWOU
T
ETH input/output
109
P21.4
TIN55
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM output
TOUT55
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDN
HSCT output (LVDS)
General-purpose input
GTM input
110
P21.5
TIN56
I
LVDSH_P/
PU1 /
VDDP3
P21.5
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM output
TOUT56
ASCLK3
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDP
HSCT output (LVDS)
Data Sheet
2-86
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-27 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
1111)
Function
P21.6
TIN57
A2 /
PU /
VDDP3
General-purpose input
GTM input
ARX3F
TGI2
TDI
ASCLIN3 input
OCDS input
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
TOUT57
ASLSO3
–
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
Reserved
–
Reserved
SYSCLK
–
HSCT output
Reserved
T3OUT
TGO2
GPT120 output
OCDS; ENx
HWOU
T
Data Sheet
2-87
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-27 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
113
Function
P21.7
TIN58
A2 /
PU /
VDDP3
General-purpose input
GTM input
DAP2
OCDS (3-Pin DAP) input
In the 3-Pin DAP mode this pin is used as DAP2.
In the 2-PIN DAP mode this pin is used as P21.7
and controlled by the related port control logic.
TGI3
ETHRXERB
T5INA
P21.7
TOUT58
ATX3
ASCLK3
–
OCDS input
ETH input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
T6OUT
TGO3
TDO
GPT120 output
OCDS; ENx
HWOU
T
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ.
DAP2
OCDS (DAP2); ENx
In the 3-Pin DAP mode this pin is used as DAP2.
1) For an Emulation Device in a non Fusion Quad package this pin is used as VDDPSB (3.3V)
Table 2-28 Port 22 Functions
Pin
95
Symbol
Ctrl
Type
Function
P22.0
TIN47
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
MTSR3E
P22.0
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT47
–
Reserved
MTSR3
SCLK3N
FCLN1
FCLND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
2-88
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-28 Port 22 Functions (cont’d)
Pin
96
Symbol
Ctrl
Type
Function
P22.1
TIN48
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
MRST3E
P22.1
TOUT48
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST3
SCLK3P
FCLP1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
97
P22.2
TIN49
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3D
P22.2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT49
–
Reserved
SLSO312
MTSR3N
SON1
SOND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
98
P22.3
TIN50
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
SCLK3E
P22.3
TOUT50
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK3
MTSR3P
SOP1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
Data Sheet
2-89
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-29 Port 23 Functions
Pin
89
Symbol
Ctrl
Type
Function
P23.0
TIN41
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT41
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
90
P23.1
TIN42
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
SDI10
P23.1
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
GTM output
Reserved
TOUT42
ARTS1
SLSO313
GTMCLK0
–
EXTCLK0
–
SCU output
Reserved
91
P23.2
TIN43
LP /
PU1 /
VEXT
General-purpose input
GTM input
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT43
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
2-90
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-29 Port 23 Functions (cont’d)
Pin
92
Symbol
Ctrl
Type
Function
P23.3
TIN44
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
INJ10
MSC1 input
P23.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT44
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
93
P23.4
TIN45
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P23.4
TOUT45
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO35
END12
EN10
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
94
P23.5
TIN46
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P23.5
TOUT46
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO34
END13
EN11
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Data Sheet
2-91
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-30 Port 32 Functions
Pin
84
Symbol
Ctrl
Type
Function
P32.0
TIN36
I
LP /
PX/
VEXT
General-purpose input
GTM input
FDEST
PMU input
VGATE1N
SMPS mode: analog output. External Pass Device
gate control for EVR13
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT36
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
86
P32.2
TIN38
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX3D
ASCLIN3 input
CAN node 3 input
General-purpose output
GTM output
RXDCAN3B
P32.2
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT38
ATX3
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
DCDCSYNC
–
SCU output
Reserved
87
P32.3
TIN39
LP /
PU1 /
VEXT
General-purpose input
GTM input
P32.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT39
ATX3
ASCLIN3 output
Reserved
–
ASCLK3
ASCLIN3 output
CAN node 3 output
Reserved
TXDCAN3
–
–
Reserved
Data Sheet
2-92
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-30 Port 32 Functions (cont’d)
Pin
88
Symbol
Ctrl
Type
Function
P32.4
TIN40
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ACTS1B
SDI12
ASCLIN1 input
MSC1 input
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT40
–
Reserved
END12
GTMCLK1
EN10
MSC1 output
GTM output
MSC1 output
SCU output
EXTCLK1
COUT63
CCU60 output
Table 2-31 Port 33 Functions
Pin
70
Symbol
Ctrl
Type
Function
P33.0
TIN22
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSITR0E
DSADC channel 0 input E
General-purpose output
GTM output
P33.0
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT22
–
Reserved
–
Reserved
–
Reserved
–
Reserved
VADCG1BFL0
–
VADC output
Reserved
71
P33.1
TIN23
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSIRX0C
DSCIN2B
P33.1
PSI5 input
DSADC channel 2 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT23
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT2
VADCEMUX02
VADCG1BFL1
–
DSADC channel 2 output
VADC output
VADC output
Reserved
Data Sheet
2-93
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-31 Port 33 Functions (cont’d)
Pin
72
Symbol
Ctrl
Type
Function
P33.2
TIN24
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSDIN2B
DSITR2E
P33.2
DSADC channel 2 input B
DSADC channel 2 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT24
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
VADCEMUX01
VADCG1BFL2
–
PSI5 output
VADC output
VADC output
Reserved
73
P33.3
TIN25
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSIRX1C
PSI5 input
P33.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT25
–
Reserved
–
Reserved
–
Reserved
VADCEMUX00
VADCG1BFL3
–
VADC output
VADC output
Reserved
74
P33.4
TIN26
LP /
PU1 /
VEXT
General-purpose input
GTM input
CTRAPC
DSITR0F
P33.4
CCU61 input
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
ASCLIN2 output
Reserved
–
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
2-94
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-31 Port 33 Functions (cont’d)
Pin
75
Symbol
Ctrl
Type
Function
P33.5
TIN27
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
76
P33.6
TIN28
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
–
ASCLIN2 output
Reserved
PSITX2
PSI5 output
VADCEMUX10
VADCG0BFL2
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
2-95
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-31 Port 33 Functions (cont’d)
Pin
77
Symbol
Ctrl
Type
Function
P33.7
TIN29
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO37
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
VADCG0BFL3
–
VADC output
Reserved
78
P33.8
TIN30
MP /
HighZ/
VEXT
General-purpose input
GTM input
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI3 output
Reserved
SLSO32
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
79
P33.9
TIN31
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HSIC3INA
P33.9
TOUT31
ATX2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI3 output
ASCLIN2 output
Reserved
SLSO31
ASCLK2
–
–
Reserved
CC62
CCU61 output
Data Sheet
2-96
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-31 Port 33 Functions (cont’d)
Pin
80
Symbol
Ctrl
Type
Function
P33.10
TIN32
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3C
HSIC3INB
P33.10
QSPI3 input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT32
SLSO16
SLSO311
ASLSO1
PSISCLK
–
QSPI1 output
QSPI3 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
CCU61 output
General-purpose input
GTM input
81
P33.11
TIN33
MP /
PU1 /
VEXT
SCLK3D
P33.11
TOUT33
ASCLK1
SCLK3
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC output
CCU61 output
General-purpose input
GTM input
82
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR3D
P33.12
TOUT34
ATX1
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
ASCLIN1 output
Reserved
MTSR3
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
2-97
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-31 Port 33 Functions (cont’d)
Pin
83
Symbol
Ctrl
Type
Function
P33.13
TIN35
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1F
MRST3D
DSSGNB
INJ11
ASCLIN1 input
QSPI3 input
DSADC input
MSC1 input
P33.13
TOUT35
ATX1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
QSPI2 output
Reserved
MRST3
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
Table 2-32 Port 40 Functions
Pin
44
Symbol
Ctrl
Type
Function
P40.0
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 8 of group 1
CCU60 input
VADCG1.8
CCPOS0D
SENT0A
SENT input
43
42
41
35
P40.1
I
I
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 9 of group 1 (MD)
CCU60 input
VADCG1.9
CCPOS1B
SENT1A
SENT input
P40.2
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 10 of group 1 (MD)
CCU60 input
VADCG1.10
CCPOS1D
SENT2A
SENT input
P40.3
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 11 of group 1
CCU60 input
VADCG1.11
CCPOS2B
SENT3A
SENT input
P40.6
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 3, pin A
CCU61 input
VADCG2.4
DS3PA
CCPOS1B
SENT2D
SENT input
Data Sheet
2-98
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-32 Port 40 Functions (cont’d)
Pin
34
Symbol
Ctrl
Type
Function
P40.7
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 5 of group 2
VADCG2.5
DS3NA
DSADC: negative analog input channel of DSADC 3,
pin A
CCPOS1D
SENT3D
CCU61 input
SENT input
33
32
P40.8
I
I
S /
HighZ /
VDDM
General-purpose input
VADCG2.6
VADC analog input channel 6 of group 2
DSADC: positive analog input of channel 3, pin B
CCU61 input
DS3PB
CCPOS2B
SENT4A
SENT input
P40.9
S /
General-purpose input
HighZ /
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
DS3NB
DSADC: negative analog input channel of DSADC 3,
pin B
CCPOS2D
SENT5A
CCU61 input
SENT input
Table 2-33 Analog Inputs
Pin
67
Symbol
Ctrl
Type
Function
AN0
I
D /
Analog input 0
HighZ /
VDDM
VADCG0.0
VADC analog input channel 0 of group 0
DSADC: positive analog input of channel 0, pin B
Analog input 1
DS0PB
66
AN1
I
D /
HighZ /
VDDM
VADCG0.1
VADC analog input channel 1 of group 0 (MD)
DS0NB
DSADC: negative analog input channel of DSADC 0,
pin B
65
64
AN2
I
I
D /
HighZ /
VDDM
Analog input 2
VADCG0.2
VADC analog input channel 2 of group 0 (MD)
DSADC: positive analog input of channel 0, pin A
Analog input 3
DS0PA
AN3
D /
HighZ /
VDDM
VADCG0.3
VADC analog input channel 3 of group 0
DS0NA
DSADC: negative analog input channel of DSADC 0,
pin A
63
62
AN4
I
I
D /
HighZ /
VDDM
Analog input 4
VADCG0.4
VADC analog input channel 4 of group 0
AN5
D /
Analog input 5
HighZ /
VDDM
VADCG0.5
VADC analog input channel 5 of group 0
Data Sheet
2-99
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-33 Analog Inputs (cont’d)
Pin
61
Symbol
Ctrl
Type
Function
AN6
I
D /
Analog input 6
HighZ /
VDDM
VADCG0.6
VADC analog input channel 6 of group 0
60
AN7
I
D /
Analog input 7
HighZ /
VDDM
VADCG0.7
VADC analog input channel 7 of group 0 (with pull
down diagnostics)
59
58
57
56
55
50
49
48
47
AN8
I
I
I
I
I
I
I
I
I
D /
HighZ /
VDDM
Analog input 8
VADCG0.8
VADC analog input channel 8 of group 0
AN10
D /
HighZ /
VDDM
Analog input 10
VADCG0.10
VADC analog input channel 10 of group 0 (MD)
AN11
D /
HighZ /
VDDM
Analog input 11
VADCG0.11
VADC analog input channel 11 of group 0
AN12
D /
HighZ /
VDDM
Analog input 12
VADCG0.12
VADC analog input channel 12 of group 0
AN13
D /
HighZ /
VDDM
Analog input 13
VADCG0.13
VADC analog input channel 13 of group 0
AN16
D /
HighZ /
VDDM
Analog input 16
VADCG1.0
VADC analog input channel 0 of group 1
AN17
D /
HighZ /
VDDM
Analog input 17
VADCG1.1
VADC analog input channel 1 of group 1 (MD)
AN18
D /
HighZ /
VDDM
Analog input 18
VADCG1.2
VADC analog input channel 2 of group 1 (MD)
AN19
D /
Analog input 19
HighZ /
VDDM
VADCG1.3
VADC analog input channel 3 of group 1 (with pull
down diagnostics)
46
45
AN20
I
I
D /
HighZ /
VDDM
Analog input 20
VADCG1.4
VADC analog input channel 4 of group 1
DSADC: positive analog input of channel 2, pin A
Analog input 21
DS2PA
AN21
D /
HighZ /
VDDM
VADCG1.5
VADC analog input channel 5 of group 1
DS2NA
DSADC: negative analog input channel of DSADC 2,
pin A
44
AN24
I
S /
Analog input 24
HighZ /
VDDM
VADCG1.8
VADC analog input channel 8 of group 1
SENT input channel 0, pin A
SENT0A
Data Sheet
2-100
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-33 Analog Inputs (cont’d)
Pin
43
Symbol
AN25
Ctrl
Type
Function
I
S /
Analog input 24
HighZ /
VDDM
VADCG1.9
SENT1A
VADC analog input channel 9of group 1 (MD)
SENT input channel 1, pin A
Analog input 26
42
41
AN26
I
I
S /
HighZ /
VDDM
VADCG1.10
VADC analog input channel 10 of group 1 (MD)
SENT input channel 2, pin A
Analog input 27
SENT2A
AN27
S /
HighZ /
VDDM
VADCG1.11
VADC analog input channel 11 of group 1
SENT input channel 3, pin A
Analog input 28
SENT3A
40
39
38
37
36
AN28
I
I
I
I
I
D /
HighZ /
VDDM
VADCG1.12
VADC analog input channel 12 of group 1
AN29
D /
HighZ /
VDDM
Analog input 29
VADCG1.13
VADC analog input channel 13 of group 1
AN32
D /
HighZ /
VDDM
Analog input 32
VADCG2.0
VADC analog input channel 0 of group 2
AN33
D /
HighZ /
VDDM
Analog input 33
VADCG2.1
VADC analog input channel 1 of group 2 (MD)
AN35
D /
Analog input 35
HighZ /
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
35
34
AN36
I
I
S /
HighZ /
VDDM
Analog input 34
VADCG2.4
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 3, pin A
SENT input channel 2, pin D
DS3PA
SENT2D
AN37
S /
Analog input 37
HighZ /
VDDM
VADCG2.5
VADC analog input channel 5 of group 2
DS3NA
DSADC: negative analog input channel of DSADC 3,
pin A
SENT3D
SENT input channel 3, pin D
33
AN38
I
S /
Analog input 38
HighZ /
VDDM
VADCG2.6
VADC analog input channel 6 of group 2
DSADC: positive analog input of channel 3, pin B
SENT input channel 4, pin A
DS3PB
SENT4A
Data Sheet
2-101
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-33 Analog Inputs (cont’d)
Pin
32
Symbol
Ctrl
Type
Function
AN39
I
S /
Analog input 39
HighZ /
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
DS3NB
DSADC: negative analog input channel of DSADC 3,
pin B
SENT5A
SENT input channel 5, pin A
31
30
AN44
I
I
D /
HighZ /
VDDM
Analog input 44
VADCG2.10
VADC analog input channel 10 of group 2 (MD)
DSADC: positive analog input of channel 3, pin C
Analog input 45
DS3PC
AN45
D /
HighZ /
VDDM
VADCG2.11
VADC analog input channel 11 of group 2
DS3NC
DSADC: negative analog input channel of DSADC 3,
pin C
29
28
AN46
I
I
D /
HighZ /
VDDM
Analog input 46
VADCG2.12
VADC analog input channel 12 of group 24
DSADC: positive analog input of channel 3, pin D
Analog input 47
DS3PD
AN47
D /
HighZ /
VDDM
VADCG2.13
VADC analog input channel 13 of group 2
DS3ND
DSADC: negative analog input channel of DSADC 3,
pin D
27
26
AN48
I
I
D /
HighZ /
VDDM
Analog input 48
VADCG2.14
VADC analog input channel 14 of group 2
AN49
D /
Analog input 49
HighZ /
VDDM
VADCG2.15
VADC analog input channel 15 of group 2
Table 2-34 System I/O
Pin
121
Symbol
Ctrl
Type
Function
PORST
I
PORST /
PD /
Power On Reset Input
Additional strong PD in case of power fail.
VEXT
122
ESR0
I/O
MP / OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished.
See also SCU chapter for details.
Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR
register description.
EVRWUP
I
EVR Wakeup Pin
Data Sheet
2-102
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-34 System I/O (cont’d)
Pin
120
Symbol
Ctrl
Type
Function
ESR1
I/O
MP /
External System Request Reset 1
PU1 /
VEXT
Default NMI function. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
EVRWUP
I
EVR Wakeup Pin
85
VGATE1P
O
VGATE1P / External Pass Device gate control for EVR13
- /
VEXT
112
114
115
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
TRST
I
A2 /
PD /
VDDP3
JTAG Module Reset/Enable Input
TCK
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
102
103
XTAL1
XTAL2
I
XTAL1 /
- / -
Main Oscillator/PLL/Clock Generator Input
Main Oscillator/PLL/Clock Generator Output
O
XTAL2 /
- / -
Table 2-35 Supply
Pin
52
Symbol
Ctrl
Type
Vx
Function
VAREF1
I
Positive Analog Reference Voltage 1
51
54
10
VAGND1
VDDM
I
I
I
Vx
Vx
Vx
Negative Analog Reference Voltage 1
ADC Analog Power Supply (3.3V / 5V)
VDD / VDDSB
Emulation Device: Emulation SRAM Standby Power
Supply (1.3V) (Emulation Device only).
Production Device: VDD (1.3V).
123, 68,
24
VDD
VDD
I
I
Vx
Vx
Digital Core Power Supply (1.3V)
100
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (1.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
153, 99,
69, 25
VEXT
I
Vx
External Supply (5V / 3.3V)
Data Sheet
2-103
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
Table 2-35 Supply (cont’d)
Pin
154
Symbol
Ctrl
Type
Vx
Function
VDDP3
I
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power Supply for
VFLEX.
104
VDDP3
I
Vx
Digital Power Supply for Oscillator, LVDSH and A2
pads (3.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (3.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
155
164
101
53
VDDFL3
VFLEX
VSS
I
I
I
I
Vx
Vx
Vx
Vx
Flash Power Supply (3.3V)
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
Digital Ground
VSSM
Analog Ground for VDDM
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSH (LVDS/CMOS 3.3V)
S = Pad class S (ADC overlayed with General Purpose Input)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
Data Sheet
2-104
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply (the Exposed Pad is also considered as VSS and shall be connected to ground)
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
2.2.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during PORST active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O
Ports and Peripheral I/O Lines”, P00 / P01)
•
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1/PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
2-105
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC265x Pin Definition and Functions:
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
2.2.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-36 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
2-106
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
2.3
TC267x Pin Definition and Functions: BGA292
Figure 2-3 is showing the TC267x Logic Symbol for the package variant: BGA292.
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Y
W
V
U
T
VSS
P32.3
P32.2
P32.0 P33.13 P33.11
P33.9
P33.7
P33.5
P33.3
P33.1
AN5
AN10 VAGND1 VAREF1 VDDM VSSM
AN20
AN21
NC
Y
W
V
U
T
VGATE1
VEXT
P23.0
P23.2
P23.4
P22.2
P22.0
VDDP3
VSS
VEXT
P23.1
P23.3
P22.3
P22.1
VDD
P32.4
P33.12 P33.10
P
P33.8
P33.6
P33.4
P33.2
P33.0
AN2
AN8
AN11
AN13
AN16
AN18
AN19
AN24
AN26
AN28
AN25
AN27
AN29
17
16
15
14
13
12
11
10
9
8
7
6
5
4
VSS
P32.7
P32.6
P33.15
P34.5
P34.3
P34.1
AN1
AN3
AN7
AN9
AN14
AN17
NC
U
T
U
P23.5
P23.6
P22.5
P22.7
P22.9
VSS
P32.5
P33.14
P34.4
VDD
P34.2 VEVRSB AN0
AN4
AN6
AN12
AN15
AN22
AN23
AN34
AN38
AN40
AN42
AN30
AN31
AN32
AN36
AN41
AN43
VAGND2 VAREF2
T
R
P
N
M
L
P23.7
P22.4
P22.6
P22.8
Top-View
AN35
AN37
AN45
AN47
AN33
AN39
AN44
AN46
R
P
N
M
L
R
P
N
M
L
R
P
N
M
L
VSS
(AGBT (AGBT
TX0P)
VSS
VSS
VSS
VSS
VSS
VSS
VDD
TX0N)
VSS
VDD
VSS
VDD
VSS
XTAL1 XTAL2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(AGBT
ERR)
VSS
(AGBT
CLKN)
VSS
TRST
P21.2
P21.3
P20.2
P20.1
P20.7
P22.11 P22.10
VSS
VSS
VSS
VSS
P00.12 P00.11
VSS
(AGBT
CLKP)
NC
(VDDPSB)
K
J
P21.4
P21.5
P20.0
P20.3
P20.8
P21.0
P21.1
P21.6
TMS
TCK
P00.10 P00.8
P00.9
P00.5
P00.3
P00.1
P02.7
P02.5
P02.3
P02.1
VSS
P00.7
P00.4
P00.2
P00.0
P02.8
P02.6
P02.4
P02.2
P02.0
K
J
K
J
K
J
VSS
VDD
VSS
P01.7
P01.5
P01.3
P00.6
P01.6
P01.4
VDD
(VDDSB)
H
G
F
H
G
F
P21.7
VSS
VSS
VSS
VSS
H
G
F
H
G
F
VDD
(VDDSB)
PORST ESR1
VDD
P20.6
P20.9
ESR0
P02.10 P02.11
E
D
C
B
A
P20.11 P20.10
P20.13 P20.12
E
D
VSS VDDFL3 P15.5
P14.2
P12.0
P12.1
P11.0
P11.1
P11.7
P11.8
P11.13
VSS
P02.9
E
D
E
D
C
B
A
VSS VDDFL3 P15.7
P15.8
14
P14.7
13
P14.9 P14.10 P11.4
P11.6
9
P11.5 P11.14 P11.15 VFLEX
VSS
4
17
16
15
12
11
10
8
7
6
5
P20.14
P15.0
P15.2
VSS
VDDP3 P15.3
P14.0
P14.4
P14.3
P14.6
P13.0
P13.2
P11.3 P11.10 P11.12 P10.1
P10.4
P10.5
P10.8
VEXT
VSS
VDDP3 P15.1
19 18
P15.4
P15.6
P14.1
P14.5
P14.8
P13.1
P13.3
P11.2
P11.9 P11.11 P10.0
P10.3
P10.2
P10.6
P10.7
VEXT
NC
20
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 2-3 TC267x Logic Symbol for the package variant BGA292.
Data Sheet
2-107
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
2.3.1
TC267 BGA292 Package Variant Pin Configuration
Table 2-37 Port 00 Functions
Pin
G1
Symbol
Ctrl
Type
Function
P00.0
TIN9
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I/O
I
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
General-purpose input
GTM input
G2
P00.1
TIN10
LP /
PU1 /
VEXT
ARX3E
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN0A
VADCG3.11
CIFD10
P00.1
ASCLIN3 input
CAN node 1 input
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 0 input A
VADC analog input channel 11 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
Reserved
–
DSCOUT0
–
DSADC channel 0 output
Reserved
SPC0
SENT output
CC60
CCU61 output
Data Sheet
2-108
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-37 Port 00 Functions (cont’d)
Pin
H1
Symbol
Ctrl
Type
Function
P00.2
TIN11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT1B
DSDIN0A
VADCG3.10
CIFD11
P00.2
SENT input
DSADC channel 0 input A
VADC analog input channel 10 of group 3 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT11
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
TXDCAN3
–
PSI5 output
CAN node 3 output
Reserved
COUT60
CCU61 output
H2
P00.3
TIN12
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN3A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG3.9
CIFD12
P00.3
CAN node 3 input
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input A
VADC analog input channel 9 of group 3 (MD)
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
Data Sheet
2-109
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-37 Port 00 Functions (cont’d)
Pin
J1
Symbol
Ctrl
Type
Function
P00.4
TIN13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG3.8
CIFD13
SENT input
DSADC channel 3 input A
DSADC input
VADC analog input channel 8 of group 3
CIF input
P00.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT13
PSISTX
TXDCAN4
PSITX1
PSI5-S output
CAN node 4 output
PSI5 output
VADCG2BFL0
SPC3
VADC output
SENT output
COUT61
CCU61 output
J2
P00.5
TIN14
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSIRX2A
SENT4B
RXDCAN4A
CC62INB
CC62INA
DSCIN2A
VADCG3.7
CIFD14
PSI5 input
SENT input
CAN node 4 input
CCU60 input
CCU61 input
DSADC channel 2 input A
VADC analog input channel 7 of group 3
CIF input
P00.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT14
DSCGPWMN
–
DSADC output
Reserved
DSCOUT2
VADCG2BFL1
SPC4
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
Data Sheet
2-110
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-37 Port 00 Functions (cont’d)
Pin
J4
Symbol
Ctrl
Type
Function
P00.6
TIN15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT5B
SENT input
DSDIN2A
VADCG3.6
CIFD15
DSADC channel 2 input A
VADC analog input channel 6 of group 3
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG2BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
CCU61 output
General-purpose input
GTM input
K1
P00.7
TIN16
LP /
PU1 /
VEXT
CC60INC
CCPOS0A
T12HRB
T2INA
CCU61 input
CCU61 input
CCU60 input
GPT120 input
VADCG3.5
CIFCLK
P00.7
VADC analog input channel 5 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG2BFL3
–
VADC output
Reserved
VADCEMUX11
–
VADC output
Reserved
CC60
CCU61 output
Data Sheet
2-111
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-37 Port 00 Functions (cont’d)
Pin
K4
Symbol
Ctrl
Type
Function
P00.8
TIN17
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
CC61INC
CCPOS1A
T13HRB
T2EUDA
VADCG3.4
CIFVSNC
P00.8
CCU61 input
CCU61 input
CCU60 input
GPT120 input
VADC analog input channel 4 of group 3
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
–
VADC output
Reserved
CC61
CCU61 output
General-purpose input
GTM input
K2
P00.9
TIN18
LP /
PU1 /
VEXT
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
VADCG3.3
DSITR3F
CIFHSNC
P00.9
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
VADC analog input channel 3 of group 3
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
–
QSPI3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
CC62
CCU61 output
Data Sheet
2-112
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-37 Port 00 Functions (cont’d)
Pin
K5
Symbol
Ctrl
Type
Function
P00.10
TIN19
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
VADCG3.2
VADC analog input channel 2 of group 3 (MD)
General-purpose output
GTM output
P00.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT19
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
General-purpose input
GTM input
L1
P00.11
TIN20
LP /
PU1 /
VEXT
CTRAPA
CCU60 input
T12HRE
CCU61 input
VADCG3.1
VADC analog input channel of group 3
General-purpose output
GTM output
P00.11
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT20
–
Reserved
–
Reserved
DSCOUT0
DSADC channel 0 output
Reserved
–
–
–
Reserved
Reserved
L2
P00.12
TIN21
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS3A
ASCLIN3 input
VADC analog input channel 0 of group 3
General-purpose output
GTM output
VADCG3.0
P00.12
O0
O1
O2
O3
O4
O5
O6
O7
TOUT21
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
Data Sheet
2-113
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-38 Port 02 Functions
Pin
B1
Symbol
Ctrl
Type
Function
P02.0
TIN0
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ARX2G
REQ6
ASCLIN2 input
SCU input
CC60INA
CC60INB
CIFD0
CCU60 input
CCU61 input
CIF input
P02.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY output
SLSO31
DSCGPWMN
TXDCAN0
TXDA
CC60
CCU60 output
C2
P02.1
TIN1
LP / PU1 General-purpose input
/ VEXT
GTM input
REQ14
ARX2B
RXDCAN0A
RXDA2
CIFD1
P02.1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT1
–
Reserved
SLSO32
DSCGPWMP
–
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
2-114
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-38 Port 02 Functions (cont’d)
Pin
C1
Symbol
Ctrl
Type
Function
P02.2
TIN2
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
PSI5 output
SLSO33
PSITX0
TXDCAN2
TXDB
CAN node 2 output
ERAY output
CCU60 output
General-purpose input
GTM input
CC61
D2
P02.3
TIN3
LP /
PU1 /
VEXT
ARX1G
RXDCAN2B
RXDB2
PSIRX0B
SDI11
CIFD3
P02.3
ASCLIN1 input
CAN node 2 input
ERAY input
PSI5 input
MSC1 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
2-115
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-38 Port 02 Functions (cont’d)
Pin
D1
Symbol
Ctrl
Type
Function
P02.4
TIN4
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3A
ECTT1
QSPI3 input
TTCAN input
CAN node 0 input
CCU60 input
CCU61 input
I2C0 input
RXDCAN0D
CC62INA
CC62INB
SDA0A
CIFD4
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXENA
CC62
ERAY output
CCU60 output
General-purpose input
GTM input
E2
P02.5
TIN5
MP+ /
PU1 /
VEXT
MRST3A
ECTT2
PSIRX1B
PSISRXB
SENT3C
SCL0A
CIFD5
QSPI3 input
TTCAN input
PSI5 input
PSI5-S input
SENT input
I2C0 input
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
–
CAN node 0 output
QSPI3 output
Reserved
SCL0
I2C0 output
TXENB
COUT62
ERAY output
CCU60 output
Data Sheet
2-116
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-38 Port 02 Functions (cont’d)
Pin
E1
Symbol
Ctrl
Type
Function
P02.6
TIN6
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
P02.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
General-purpose input
GTM input
F2
P02.7
TIN7
MP /
PU1 /
VEXT
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
P02.7
DSADC channel 3 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSADC channel 3 output
VADC output
SENT output
CCU60 output
DSCOUT3
VADCEMUX01
SPC1
CC61
Data Sheet
2-117
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-38 Port 02 Functions (cont’d)
Pin
F1
Symbol
Ctrl
Type
Function
P02.8
TIN8
I
LP / PU1 General-purpose input
/
VEXT
GTM input
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
CIFD8
DSDIN3B
DSITR3E
P02.8
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
Table 2-39 Port 10 Functions
Pin
A7
Symbol
Ctrl
Type
Function
P10.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN102
T6EUDB
GPT120 input
General-purpose output
GTM output
P10.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT102
–
Reserved
SLSO110
QSPI1 output
Reserved
–
VADCG3BFL0
VADC output
Reserved
–
–
Reserved
Data Sheet
2-118
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-39 Port 10 Functions (cont’d)
Pin
B7
Symbol
Ctrl
Type
Function
P10.1
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG3BFL1
END03
–
A5
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
QSPI1 input
GPT120 input
SCU input
REQ2
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG3BFL2
END02
–
Data Sheet
2-119
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-39 Port 10 Functions (cont’d)
Pin
A6
Symbol
Ctrl
Type
Function
P10.3
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG3BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
B6
P10.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN106
MTSR1C
CCPOS0C
T3INB
P10.4
QSPI1 input
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT106
–
Reserved
SLSO18
MTSR1
EN00
QSPI1 output
QSPI1 output
MSC0 output
MSC0 output
Reserved
END02
–
Data Sheet
2-120
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-39 Port 10 Functions (cont’d)
Pin
B5
Symbol
Ctrl
Type
Function
P10.5
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
RXDCAN4B
INJ01
SCU input
CAN node 4 input
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
QSPI1 output
GPT120 output
ASCLIN2 output
Reserved
SLSO38
SLSO19
T6OUT
ASLSO2
–
A4
P10.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
ASCLIN2 input
QSPI3 input
MTSR3B
HWCFG5
P10.6
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
ASCLIN2 output
QSPI3 output
GPT120 output
CAN node 4 output
QSPI1 output
VADC output
T3OUT
TXDCAN4
MRST1
VADCG3BFL0
Data Sheet
2-121
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-39 Port 10 Functions (cont’d)
Pin
A3
Symbol
Ctrl
Type
Function
P10.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN109
ACTS2A
MRST3B
REQ4
CCPOS1C
T3EUDB
P10.7
ASCLIN2 input
QSPI3 input
SCU input
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT109
–
Reserved
MRST3
VADCG3BFL1
–
QSPI3 output
VADC output
Reserved
–
Reserved
–
Reserved
B4
P10.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN110
SCLK3B
REQ5
CCPOS2C
T4INB
P10.8
TOUT110
ARTS2
SCLK3
–
QSPI3 input
SCU input
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
2-122
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-40 Port 11 Functions
Pin
Symbol
Ctrl
Type
Function
A10
P11.2
TIN95
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
P11.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT95
END03
SLSO05
SLSO15
EN01
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
CCU60 output
General-purpose input
GTM input
B10
P11.3
TIN96
MPR /
PU1 /
VFLEX
MRST1B
SDI03
P11.3
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT96
–
Reserved
MRST1
TXDA
–
QSPI1 output
ERAY output
Reserved
ETHTXD0
COUT62
ETH output
CCU60 output
General-purpose input
GTM input
D9
P11.6
TIN97
MPR /
PU1 /
VFLEX
SCLK1B
P11.6
QSPI1 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT97
TXENB
SCLK1
ERAY output
QSPI1 output
ERAY output
MSC0 output
ETH output
TXENA
FCLP0
ETHTXEN
COUT61
CCU60 output
Data Sheet
2-123
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-40 Port 11 Functions (cont’d)
Pin
A9
Symbol
Ctrl
Type
Function
P11.9
TIN98
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
MTSR1B
RXDA1
ETHRXD1
P11.9
TOUT98
–
QSPI1 input
ERAY input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
–
MSC0 output
Reserved
COUT60
CCU60 output
General-purpose input
GTM input
B9
P11.10
TIN99
LP /
PU1 /
VFLEX
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXDB1
ETHRXD0
SDI00
P11.10
TOUT99
–
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY input
ETH input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
Data Sheet
2-124
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-40 Port 11 Functions (cont’d)
Pin
A8
Symbol
Ctrl
Type
Function
P11.11
TIN100
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
ETHCRSDVA
P11.11
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT100
END02
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY output
CCU60 output
General-purpose input
GTM input
SLSO04
SLSO14
EN00
TXENB
CC61
B8
P11.12
TIN101
MPR /
PU1 /
VFLEX
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
ETHRXCLKA
ETH input
(Not for productive purposes)
P11.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT101
ATX1
ASCLIN1 output
GTM output
GTMCLK2
TXDB
ERAY output
TXDCAN3
EXTCLK1
CC60
CAN node 3 output
SCU output
CCU60 output
Table 2-41 Port 13 Functions
Pin
Symbol
Ctrl
Type
Function
B12
P13.0
TIN91
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
P13.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT91
END03
SCLK2N
EN01
MSC0 output
QSPI2 output (LVDS)
MSC0 output
FCLN0
FCLND0
TXDCAN4
MSC0 output (LVDS)
MSC0 output (LVDS)
CAN node 4 output
Data Sheet
2-125
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-41 Port 13 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
A12
P13.1
TIN92
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
SCL0B
RXDCAN4C
P13.1
TOUT92
–
I2C0 input
CAN node 4 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
–
MSC0 output (LVDS)
I2C0 output
Reserved
B11
P13.2
TIN93
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
CAPINA
SDA0B
P13.2
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT93
–
Reserved
MTSR2N
FCLP0
SON0
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
SDA0
SOND0
MSC0 output (LVDS)
General-purpose input
GTM input
A11
P13.3
TIN94
LVDSM_P /
PU1 /
VEXT
P13.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT94
–
Reserved
MTSR2P
QSPI2 output (LVDS)
Reserved
–
SOP0
MSC0 output (LVDS)
Reserved
–
–
Reserved
Data Sheet
2-126
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-42 Port 14 Functions
Pin
Symbol
Ctrl
Type
Function
B16
P14.0
TIN80
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P14.0
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
TXDA
O3
O4
O5
ERAY output
ERAY output
TXDB
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function.
ASCLK0
COUT62
O6
O7
I
ASCLIN0 output
CCU60 output
General-purpose input
GTM input
A15
P14.1
TIN81
MP /
PU1 /
VEXT
REQ15
SCU input
ARX0A
ASCLIN0 input
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function.
RXDA3
RXDB3
EVRWUPA
P14.1
ERAY input
ERAY input
SCU input
O0
O1
O2
General-purpose output
GTM output
TOUT81
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
–
O3
O4
O5
O6
O7
Reserved
Reserved
Reserved
Reserved
CCU60 output
–
–
–
COUT63
Data Sheet
2-127
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-42 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
E13
P14.2
TIN82
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
SLSO21
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
B14
P14.3
TIN83
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX2A
REQ10
HWCFG3_BMI
SDI02
ASCLIN2 input
SCU input
SCU input
MSC0 input
P14.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT83
ATX2
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
Data Sheet
2-128
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-42 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
B15
P14.4
TIN84
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT84
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
A14
P14.5
TIN85
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT85
–
–
Reserved
–
Reserved
–
Reserved
TXDB
–
ERAY output
Reserved
B13
P14.6
TIN86
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT86
–
SLSO22
QSPI2 output
Reserved
–
–
Reserved
TXENB
–
ERAY output
Reserved
Data Sheet
2-129
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-42 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
D13
P14.7
TIN87
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDB0
ERAY input
P14.7
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT87
ARTS0
ASCLIN0 output
QSPI2 output
Reserved
SLSO24
–
–
–
–
Reserved
Reserved
Reserved
A13
P14.8
TIN88
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1D
ASCLIN1 input
CAN node 2 input
ERAY input
RXDCAN2D
RXDA0
P14.8
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT88
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D12
P14.9
TIN89
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ACTS0A
P14.9
TOUT89
END03
EN01
–
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
MSC0 output
MSC0 output
Reserved
TXENB
TXENA
–
ERAY output
ERAY output
Reserved
Data Sheet
2-130
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-42 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
D11
P14.10
TIN90
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P14.10
TOUT90
END02
EN00
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
MSC0 output
ATX1
ASCLIN1 output
CAN node 2 output
ERAY output
TXDCAN2
TXDA
–
Reserved
Table 2-43 Port 15 Functions
Pin
Symbol
Ctrl
Type
Function
B20
P15.0
TIN71
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
P15.0
TOUT71
ATX1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
Reserved
SLSO013
–
TXDCAN2
ASCLK1
–
CAN node 2 output
ASCLIN1 output
Reserved
A18
P15.1
TIN72
LP /
PU1 /
VEXT
General-purpose input
GTM input
REQ16
SCU input
ARX1A
ASCLIN1 input
CAN node 2 input
QSPI2 input
RXDCAN2A
SLSI2B
EVRWUPB
SCU input
P15.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT72
ATX1
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
–
–
Reserved
Reserved
Reserved
Data Sheet
2-131
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-43 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
C19
P15.2
TIN73
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI2A
MRST2E
HSIC2INA
P15.2
QSPI2 input
QSPI2 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT73
ATX0
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
B17
P15.3
TIN74
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX0B
SCLK2A
RXDCAN1A
HSIC2INB
P15.3
ASCLIN0 input
QSPI2 input
CAN node 1 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT74
ATX0
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
Data Sheet
2-132
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-43 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
A17
P15.4
TIN75
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
MRST2A
REQ0
SCL0C
P15.4
TOUT75
ATX1
MRST2
–
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
–
Reserved
SCL0
CC62
I2C0 output
CCU60 output
General-purpose input
GTM input
E14
P15.5
TIN76
MP /
PU1 /
VEXT
ARX1B
MTSR2A
SDA0C
REQ13
P15.5
ASCLIN1 input
QSPI2 input
I2C0 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT76
ATX1
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
General-purpose input
GTM input
A16
P15.6
TIN77
MP /
PU1 /
VEXT
MTSR2B
P15.6
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT77
ATX3
ASCLIN3 output
QSPI2 output
Reserved
MTSR2
–
SCLK2
ASCLK3
CC60
QSPI2 output
ASCLIN3 output
CCU60 output
Data Sheet
2-133
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-43 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
D15
P15.7
TIN78
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX3A
MRST2B
P15.7
TOUT78
ATX3
MRST2
–
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
COUT60
CCU60 output
General-purpose input
GTM input
D14
P15.8
TIN79
MP /
PU1 /
VEXT
SCLK2B
REQ1
P15.8
TOUT79
–
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
ASCLIN3 output
CCU60 output
Data Sheet
2-134
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-44 Port 20 Functions
Pin
Symbol
Ctrl
Type
Function
H20
P20.0
TIN59
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN3C
T6EUDA
REQ9
SYSCLK
TGI0
CAN node 3 input
GPT120 input
SCU input
HSCT input
OCDS input
P20.0
TOUT59
ATX3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
G19
P20.1
TIN60
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TGI1
OCDS input
General-purpose output
GTM output
Reserved
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
TOUT60
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO1
HWOU
T
OCDS; ENx
Data Sheet
2-135
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-44 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
H19
P20.2
I
LP /
General-purpose input
PU /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
OCDS input
P20.2
O0
O1
O2
O3
O4
O5
O6
O7
I
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
General-purpose input
GTM input
–
–
–
–
–
–
–
G20
P20.3
TIN61
T6INA
ARX3C
P20.3
TOUT61
ATX3
LP /
PU1 /
VEXT
GPT120 input
ASCLIN3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
SLSO09
SLSO29
TXDCAN3
–
QSPI0 output
QSPI2 output
CAN node 3 output
Reserved
–
Reserved
F17
P20.6
TIN62
LP /
PU1 /
VEXT
General-purpose input
GTM input
P20.6
TOUT62
ARTS1
SLSO08
SLSO28
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
Data Sheet
2-136
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-44 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
F19
P20.7
TIN63
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS1A
ASCLIN1 input
CAN node 0 input
General-purpose output
GTM output
RXDCAN0B
P20.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT63
–
Reserved
–
Reserved
–
Reserved
–
Reserved
WDT1LCK
COUT63
SCU output
CCU61 output
General-purpose input
GTM input
F20
P20.8
TIN64
MP /
PU1 /
VEXT
P20.8
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT64
ASLSO1
SLSO00
SLSO10
TXDCAN0
WDT0LCK
CC60
ASCLIN1 output
QSPI0 output
QSPI1 output
CAN node 0 output
SCU output
CCU61 output
General-purpose input
GTM input
E17
P20.9
TIN65
LP /
PU1 /
VEXT
ARX1C
RXDCAN3E
REQ11
SLSI0B
P20.9
ASCLIN1 input
CAN node 3 input
SCU input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT65
–
Reserved
SLSO01
SLSO11
–
QSPI0 output
QSPI1 output
Reserved
WDTSLCK
CC61
SCU output
CCU61 output
Data Sheet
2-137
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-44 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
E19
P20.10
TIN66
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
P20.10
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT66
ATX1
ASCLIN1 output
QSPI0 output
QSPI2 output
CAN node 3 output
ASCLIN1 output
CCU61 output
General-purpose input
GTM input
SLSO06
SLSO27
TXDCAN3
ASCLK1
CC62
E20
P20.11
TIN67
MP /
PU1 /
VEXT
SCLK0A
QSPI0 input
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT67
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
COUT60
CCU61 output
General-purpose input
GTM input
D19
P20.12
TIN68
MP /
PU1 /
VEXT
MRST0A
P20.12
TOUT68
–
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MRST0
MTSR0
–
QSPI0 output
QSPI0 output
Reserved
–
Reserved
COUT61
CCU61 output
Data Sheet
2-138
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-44 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
D20
P20.13
TIN69
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI0A
P20.13
TOUT69
–
QSPI0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
SLSO02
SLSO12
SCLK0
–
QSPI0 output
QSPI1 output
QSPI0 output
Reserved
COUT62
CCU61 output
General-purpose input
GTM input
C20
P20.14
TIN70
MP /
PU1 /
VEXT
MTSR0A
QSPI0 input
General-purpose output
GTM output
P20.14
O0
O1
O2
O3
O4
O5
O6
O7
TOUT70
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
–
–
Reserved
Reserved
Reserved
Table 2-45 Port 21 Functions
Symbol
Ctrl
Type
Pin
Function
K17
P21.0
TIN51
I
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT51
–
–
Reserved
–
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
Data Sheet
2-139
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-45 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
J17
Function
P21.1
TIN52
A2 /
PU1 /
VDDP3
General-purpose input
GTM input
ETHMDIOB
ETH input
(Not for production purposes)
P21.1
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM output
Reserved
TOUT52
–
–
Reserved
–
Reserved
–
Reserved
ETHMDIO
ETH output
(Not for production purposes)
–
O7
I
Reserved
K19
P21.2
TIN53
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
MRST2CN
MRST3FN
EMGSTOPB
RXDN
P21.2
QSPI2 input (LVDS)
QSPI3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT53
ASLSO3
–
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
–
ETH output
Reserved
–
Reserved
Data Sheet
2-140
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-45 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
J19
Function
P21.3
TIN54
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
MRST2CP
QSPI2 input (LVDS)
QSPI3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
MRST3FP
RXDP
P21.3
O0
O1
O2
O3
O4
O5
O6
O7
TOUT54
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDIOD
HWOU
T
ETH input/output
K20
P21.4
TIN55
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM output
TOUT55
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDN
HSCT output (LVDS)
General-purpose input
GTM input
J20
P21.5
TIN56
I
LVDSH_P/
PU1 /
VDDP3
P21.5
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM output
TOUT56
ASCLK3
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TXDP
HSCT output (LVDS)
Data Sheet
2-141
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-45 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
Function
H17
P21.6
TIN57
A2 /
PU /
VDDP3
General-purpose input
GTM input
ARX3F
TGI2
TDI
ASCLIN3 input
OCDS input
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
TOUT57
ASLSO3
–
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
Reserved
–
Reserved
SYSCLK
–
HSCT output
Reserved
T3OUT
TGO2
GPT120 output
OCDS; ENx
HWOU
T
Data Sheet
2-142
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-45 Port 21 Functions (cont’d)
Symbol
Ctrl
I
Type
Pin
Function
H16
P21.7
TIN58
A2 /
PU /
VDDP3
General-purpose input
GTM input
DAP2
OCDS (3-Pin DAP) input
In the 3-Pin DAP mode this pin is used as DAP2.
In the 2-PIN DAP mode this pin is used as P21.7
and controlled by the related port control logic.
TGI3
ETHRXERB
T5INA
P21.7
TOUT58
ATX3
ASCLK3
–
OCDS input
ETH input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN3 output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
T6OUT
TGO3
TDO
GPT120 output
OCDS; ENx
HWOU
T
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ.
DAP2
OCDS (DAP2); ENx
In the 3-Pin DAP mode this pin is used as DAP2.
Table 2-46 Port 22 Functions
Pin
Symbol
Ctrl
Type
Function
P20
P22.0
TIN47
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
MTSR3E
P22.0
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT47
–
Reserved
MTSR3
SCLK3N
FCLN1
FCLND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
2-143
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-46 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
P19
P22.1
TIN48
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
MRST3E
P22.1
TOUT48
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST3
SCLK3P
FCLP1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
R20
P22.2
TIN49
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3D
P22.2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT49
–
Reserved
SLSO312
MTSR3N
SON1
SOND1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
R19
P22.3
TIN50
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
SCLK3E
P22.3
TOUT50
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK3
MTSR3P
SOP1
–
QSPI3 output
QSPI3 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
Data Sheet
2-144
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-47 Port 23 Functions
Pin
Symbol
Ctrl
Type
Function
V20
P23.0
TIN41
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT41
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
U19
P23.1
TIN42
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
SDI10
P23.1
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
GTM output
Reserved
TOUT42
ARTS1
SLSO313
GTMCLK0
–
EXTCLK0
–
SCU output
Reserved
U20
P23.2
TIN43
LP /
PU1 /
VEXT
General-purpose input
GTM input
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT43
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
2-145
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-47 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
T19
P23.3
TIN44
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
INJ10
MSC1 input
P23.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT44
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
T20
P23.4
TIN45
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P23.4
TOUT45
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO35
END12
EN10
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
T17
P23.5
TIN46
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P23.5
TOUT46
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO34
END13
EN11
–
QSPI3 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Data Sheet
2-146
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-48 Port 32 Functions
Pin
Symbol
Ctrl
Type
Function
Y17
P32.0
TIN36
I
LP /
PX/
VEXT
General-purpose input
GTM input
FDEST
PMU input
VGATE1N
SMPS mode: analog output. External Pass Device
gate control for EVR13
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT36
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Y18
P32.2
TIN38
LP /
PU1 /
VEXT
General-purpose input
GTM input
ARX3D
ASCLIN3 input
CAN node 3 input
General-purpose output
GTM output
RXDCAN3B
P32.2
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT38
ATX3
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
DCDCSYNC
–
SCU output
Reserved
Y19
P32.3
TIN39
LP /
PU1 /
VEXT
General-purpose input
GTM input
P32.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT39
ATX3
ASCLIN3 output
Reserved
–
ASCLK3
ASCLIN3 output
CAN node 3 output
Reserved
TXDCAN3
–
–
Reserved
Data Sheet
2-147
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-48 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
W18
P32.4
TIN40
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ACTS1B
SDI12
ASCLIN1 input
MSC1 input
P32.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT40
–
Reserved
END12
GTMCLK1
EN10
MSC1 output
GTM output
MSC1 output
SCU output
EXTCLK1
COUT63
CCU60 output
Table 2-49 Port 33 Functions
Pin
Symbol
Ctrl
Type
Function
W10
P33.0
TIN22
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSITR0E
DSADC channel 0 input E
General-purpose output
GTM output
P33.0
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT22
–
Reserved
–
Reserved
–
Reserved
–
Reserved
VADCG1BFL0
–
VADC output
Reserved
Y10
P33.1
TIN23
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSIRX0C
DSCIN2B
P33.1
PSI5 input
DSADC channel 2 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT23
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT2
VADCEMUX02
VADCG1BFL1
–
DSADC channel 2 output
VADC output
VADC output
Reserved
Data Sheet
2-148
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-49 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
W11
P33.2
TIN24
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSDIN2B
DSITR2E
P33.2
DSADC channel 2 input B
DSADC channel 2 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT24
ASCLK3
–
ASCLIN3 output
Reserved
PSITX0
VADCEMUX01
VADCG1BFL2
–
PSI5 output
VADC output
VADC output
Reserved
Y11
P33.3
TIN25
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSIRX1C
PSI5 input
P33.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT25
–
Reserved
–
Reserved
–
Reserved
VADCEMUX00
VADCG1BFL3
–
VADC output
VADC output
Reserved
W12
P33.4
TIN26
LP /
PU1 /
VEXT
General-purpose input
GTM input
CTRAPC
DSITR0F
P33.4
CCU61 input
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
ASCLIN2 output
Reserved
–
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
2-149
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-49 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
Y12
P33.5
TIN27
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
W13
P33.6
TIN28
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
–
ASCLIN2 output
Reserved
PSITX2
PSI5 output
VADCEMUX10
VADCG0BFL2
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
2-150
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-49 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
Y13
P33.7
TIN29
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO37
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
VADCG0BFL3
–
VADC output
Reserved
W14
P33.8
TIN30
MP /
HighZ/
VEXT
General-purpose input
GTM input
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI3 output
Reserved
SLSO32
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
Y14
P33.9
TIN31
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
HSIC3INA
P33.9
TOUT31
ATX2
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI3 output
ASCLIN2 output
Reserved
SLSO31
ASCLK2
–
–
Reserved
CC62
CCU61 output
Data Sheet
2-151
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-49 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
W15
P33.10
TIN32
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI3C
HSIC3INB
P33.10
QSPI3 input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT32
SLSO16
SLSO311
ASLSO1
PSISCLK
–
QSPI1 output
QSPI3 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
CCU61 output
General-purpose input
GTM input
Y15
P33.11
TIN33
MP /
PU1 /
VEXT
SCLK3D
P33.11
TOUT33
ASCLK1
SCLK3
–
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC output
CCU61 output
General-purpose input
GTM input
W16
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR3D
P33.12
TOUT34
ATX1
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
ASCLIN1 output
Reserved
MTSR3
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
2-152
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-49 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
Y16
P33.13
TIN35
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ARX1F
MRST3D
DSSGNB
INJ11
ASCLIN1 input
QSPI3 input
DSADC input
MSC1 input
P33.13
TOUT35
ATX1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI3 output
QSPI2 output
Reserved
MRST3
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
Table 2-50 Port 40 Functions
Pin
W2
Symbol
Ctrl
Type
Function
P40.0
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 8 of group 1
CCU60 input
VADCG1.8
CCPOS0D
SENT0A
SENT input
W1
V2
V1
N4
P40.1
I
I
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 9 of group 1 (MD)
CCU60 input
VADCG1.9
CCPOS1B
SENT1A
SENT input
P40.2
S /
HighZ /
VDDM
General-purpose inpu.t
VADC analog input channel 10 of group 1 (MD)
CCU60 input
VADCG1.10
CCPOS1D
SENT2A
SENT input
P40.3
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 11 of group 1
CCU60 input
VADCG1.11
CCPOS2B
SENT3A
SENT input
P40.6
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 3, pin A
CCU61 input
VADCG2.4
DS3PA
CCPOS1B
SENT2D
SENT input
Data Sheet
2-153
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-50 Port 40 Functions (cont’d)
Pin
P2
Symbol
Ctrl
Type
Function
P40.7
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 5 of group 2
VADCG2.5
DS3NA
DSADC: negative analog input channel of DSADC 3,
pin A
CCPOS1D
SENT3D
CCU61 input
SENT input
N5
P1
P40.8
I
I
S /
HighZ /
VDDM
General-purpose input
VADCG2.6
VADC analog input channel 6 of group 2
DSADC: positive analog input of channel 3, pin B
CCU61 input
DS3PB
CCPOS2B
SENT4A
SENT input
P40.9
S /
General-purpose input
HighZ /
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
DS3NB
DSADC: negative analog input channel of DSADC 3,
pin B
CCPOS2D
SENT5A
CCU61 input
SENT input
Table 2-51 Analog Inputs
Pin
Symbol
Ctrl
Type
Function
T10
AN0
I
D /
Analog input 0
HighZ /
VDDM
VADCG0.0
VADC analog input channel 0 of group 0
DSADC: positive analog input of channel 0, pin B
Analog input 1
DS0PB
U10
AN1
I
D /
HighZ /
VDDM
VADCG0.1
VADC analog input channel 1 of group 0 (MD)
DS0NB
DSADC: negative analog input channel of DSADC 0,
pin B
W9
U9
AN2
I
I
D /
HighZ /
VDDM
Analog input 2
VADCG0.2
VADC analog input channel 2 of group 0 (MD)
DSADC: positive analog input of channel 0, pin A
Analog input 3
DS0PA
AN3
D /
HighZ /
VDDM
VADCG0.3
VADC analog input channel 3 of group 0
DS0NA
DSADC: negative analog input channel of DSADC 0,
pin A
T9
Y9
AN4
I
I
D /
HighZ /
VDDM
Analog input 4
VADCG0.4
VADC analog input channel 4 of group 0
AN5
D /
Analog input 5
HighZ /
VDDM
VADCG0.5
VADC analog input channel 5 of group 0
Data Sheet
2-154
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-51 Analog Inputs (cont’d)
Pin
T8
Symbol
Ctrl
Type
Function
AN6
I
D /
Analog input 6
HighZ /
VDDM
VADCG0.6
VADC analog input channel 6 of group 0
U8
AN7
I
D /
Analog input 7
HighZ /
VDDM
VADCG0.7
VADC analog input channel 7 of group 0 (with pull
down diagnostics)
W8
Y8
AN8
I
I
I
I
I
I
I
I
I
D /
HighZ /
VDDM
Analog input 8
VADCG0.8
VADC analog input channel 8 of group 0
AN10
D /
HighZ /
VDDM
Analog input 10
VADCG0.10
VADC analog input channel 10 of group 0 (MD)
W7
T7
AN11
D /
HighZ /
VDDM
Analog input 11
VADCG0.11
VADC analog input channel 11 of group 0
AN12
D /
HighZ /
VDDM
Analog input 12
VADCG0.12
VADC analog input channel 12 of group 0
W6
W5
U5
AN13
D /
HighZ /
VDDM
Analog input 13
VADCG0.13
VADC analog input channel 13 of group 0
AN16
D /
HighZ /
VDDM
Analog input 16
VADCG1.0
VADC analog input channel 0 of group 1
AN17
D /
HighZ /
VDDM
Analog input 17
VADCG1.1
VADC analog input channel 1 of group 1 (MD)
W4
W3
AN18
D /
HighZ /
VDDM
Analog input 18
VADCG1.2
VADC analog input channel 2 of group 1 (MD)
AN19
D /
Analog input 19
HighZ /
VDDM
VADCG1.3
VADC analog input channel 3 of group 1 (with pull
down diagnostics)
Y3
Y2
AN20
I
I
D /
HighZ /
VDDM
Analog input 20
VADCG1.4
VADC analog input channel 4 of group 1
DSADC: positive analog input of channel 2, pin A
Analog input 21
DS2PA
AN21
D /
HighZ /
VDDM
VADCG1.5
VADC analog input channel 5 of group 1
DS2NA
DSADC: negative analog input channel of DSADC 2,
pin A
W2
AN24
I
S /
Analog input 24
HighZ /
VDDM
VADCG1.8
VADC analog input channel 8 of group 1
SENT input channel 0, pin A
SENT0A
Data Sheet
2-155
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-51 Analog Inputs (cont’d)
Pin
W1
Symbol
AN25
Ctrl
Type
Function
I
S /
Analog input 24
HighZ /
VDDM
VADCG1.9
SENT1A
VADC analog input channel 9of group 1 (MD)
SENT input channel 1, pin A
Analog input 26
V2
V1
AN26
I
I
S /
HighZ /
VDDM
VADCG1.10
VADC analog input channel 10 of group 1 (MD)
SENT input channel 2, pin A
Analog input 27
SENT2A
AN27
S /
HighZ /
VDDM
VADCG1.11
VADC analog input channel 11 of group 1
SENT input channel 3, pin A
Analog input 28
SENT3A
U2
U1
P4
R1
R2
AN28
I
I
I
I
I
D /
HighZ /
VDDM
VADCG1.12
VADC analog input channel 12 of group 1
AN29
D /
HighZ /
VDDM
Analog input 29
VADCG1.13
VADC analog input channel 13 of group 1
AN32
D /
HighZ /
VDDM
Analog input 32
VADCG2.0
VADC analog input channel 0 of group 2
AN33
D /
HighZ /
VDDM
Analog input 33
VADCG2.1
VADC analog input channel 1 of group 2 (MD)
AN35
D /
Analog input 35
HighZ /
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
N4
P2
AN36
I
I
S /
HighZ /
VDDM
Analog input 34
VADCG2.4
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 3, pin A
SENT input channel 2, pin D
DS3PA
SENT2D
AN37
S /
Analog input 37
HighZ /
VDDM
VADCG2.5
VADC analog input channel 5 of group 2
DS3NA
DSADC: negative analog input channel of DSADC 3,
pin A
SENT3D
SENT input channel 3, pin D
N5
AN38
I
S /
Analog input 38
HighZ /
VDDM
VADCG2.6
VADC analog input channel 6 of group 2
DSADC: positive analog input of channel 3, pin B
SENT input channel 4, pin A
DS3PB
SENT4A
Data Sheet
2-156
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-51 Analog Inputs (cont’d)
Pin
P1
Symbol
Ctrl
Type
Function
AN39
I
S /
Analog input 39
HighZ /
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
DS3NB
DSADC: negative analog input channel of DSADC 3,
pin B
SENT5A
SENT input channel 5, pin A
N1
N2
AN44
I
I
D /
HighZ /
VDDM
Analog input 44
VADCG2.10
VADC analog input channel 10 of group 2 (MD)
DSADC: positive analog input of channel 3, pin C
Analog input 45
DS3PC
AN45
D /
HighZ /
VDDM
VADCG2.11
VADC analog input channel 11 of group 2
DS3NC
DSADC: negative analog input channel of DSADC 3,
pin C
M1
M2
AN46
I
I
D /
HighZ /
VDDM
Analog input 46
VADCG2.12
VADC analog input channel 12 of group 24
DSADC: positive analog input of channel 3, pin D
Analog input 47
DS3PD
AN47
D /
HighZ /
VDDM
VADCG2.13
VADC analog input channel 13 of group 2
DS3ND
DSADC: negative analog input channel of DSADC 3,
pin D
M4
M5
AN48
I
I
D /
HighZ /
VDDM
Analog input 48
VADCG2.14
VADC analog input channel 14 of group 2
AN49
D /
Analog input 49
HighZ /
VDDM
VADCG2.15
VADC analog input channel 15 of group 2
Table 2-52 System I/O
Pin
Symbol
Ctrl
Type
Function
G17
PORST
I
PORST /
PD /
Power On Reset Input
Additional strong PD in case of power fail.
VEXT
F16
ESR0
I/O
MP / OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished.
See also SCU chapter for details.
Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR
register description.
EVRWUP
I
EVR Wakeup Pin
Data Sheet
2-157
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-52 System I/O (cont’d)
Pin
Symbol
Ctrl
Type
Function
G16
ESR1
I/O
MP /
External System Request Reset 1
PU1 /
VEXT
Default NMI function. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
EVRWUP
I
EVR Wakeup Pin
W17
K16
L19
J16
VGATE1P
O
VGATE1P / External Pass Device gate control for EVR13
- /
VEXT
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
TRST
I
A2 /
JTAG Module Reset/Enable Input
PD /
VDDP3
TCK
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
M20
M19
XTAL1
XTAL2
I
XTAL1 /
- / -
Main Oscillator/PLL/Clock Generator Input
Main Oscillator/PLL/Clock Generator Output
O
XTAL2 /
- / -
Table 2-53 Supply
Pin
Y6
Symbol
Ctrl
Type
Vx
Function
VAREF1
I
Positive Analog Reference Voltage 1
Y7
VAGND1
VDDM
I
I
I
Vx
Vx
Vx
Negative Analog Reference Voltage 1
ADC Analog Power Supply (3.3V / 5V)
Y5
G8, H7
VDD / VDDSB
Emulation Device: Emulation SRAM Standby Power
Supply (1.3V) (Emulation Device only).
Production Device: VDD (1.3V).
P8, P13,
N7, N14,
H14, G13
VDD
VDD
I
I
Vx
Vx
Digital Core Power Supply (1.3V)
N19
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (1.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
A2, B3,
VEXT
I
Vx
External Power Supply (5V / 3.3V)
V19, W20
Data Sheet
2-158
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-53 Supply (cont’d)
Pin Symbol
B18, A19 VDDP3
Ctrl
Type
Vx
Function
I
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power Supply for
VFLEX.
N20
VDDP3
I
Vx
Digital Power Supply for Oscillator, LVDSH and A2
pads (3.3V).
The supply pin inturn supplies the main XTAL
Oscillator/PLL (3.3V) . A higher decoupling capacitor is
therefore recommended to the VSS pin for better noise
immunity.
E15, D16 VDDFL3
I
I
I
I
Vx
Vx
Vx
Vx
Flash Power Supply (3.3V)
D5
VFLEX
VSSM
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
Y4
Analog Ground for VDDM
T11
VEVRSB
Standby Power Supply (3.3V/5V) for the Standby
SRAM (CPU0.DSPR).
If Standby mode is not used: To be handled like VEXT
(3.3V/5V).
B2, D4,
VSS
I
Vx
Digital Ground
E5, L20,
T16, U17,
W19, Y20
E16, D17, VSS
B19, A20
I
I
Vx
Vx
Digital Ground (outer balls)
Digital Ground (center balls)
P9, P12,
N9, N10,
N11, N12
VSS
VSS
VSS
VSS
VSS
M7, M8,
M10, M11,
M13, M14
I
I
I
I
I
Vx
Vx
Vx
Vx
Vx
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
L8, L9,
L10, L11,
L12, L13
K8, K9,
K10, K11,
K12, K13
J7, J8,
J10, J11,
J13, J14
H9, H10, VSS
H11, H12,
G9, G10,
G11, G12
Data Sheet
2-159
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-53 Supply (cont’d)
Pin
Symbol
Ctrl
Type
Vx
Function
P10
VSS
I
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT TX0N
P11
L7
VSS
I
I
I
I
I
Vx
Vx
Vx
Vx
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT TX0P
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT CLKN
K7
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT CLKP
L14
K14
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device as
AGBT ERR
NC / VDDPSB
NCVDDP Emulation Device: Power Supply (3.3V) for DAP/JTAG
SB
pad group.
Production Device: Not Connected.
U16, U15, NC
U14, U13,
U12, U11,
U7, U6
I
I
I
NC
Not Connected. These pins are reserved for future
extensions and shall not be connected externally.
T15, T14, NC
T13, T12,
T6,T5,T4,
T2, T1
NC
NC
Not Connected. These pins are reserved for future
extensions and shall not be connected externally.
E12, E11, NC
E10, E9,
E8, E7,
Not Connected. These pins are reserved for future
extensions and shall not be connected externally.
E6, E4,
D10, D8,
D7, D6
R5, R4,
P5, L5,
L4, J5,
H5, H4,
G5, G4,
F5, F4
NC
I
NC
Not Connected. These pins are reserved for future
extensions and shall not be connected externally.
Data Sheet
2-160
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
Table 2-53 Supply (cont’d)
Pin Symbol
Ctrl
Type
NC
Function
R17, R16, NC
P17, P16,
I
Not Connected. These pins are reserved for future
extensions and shall not be connected externally.
N17, N16,
M17, M16,
L17, L16
A1, Y1, U4 NC
I
NC1
Not Connected.
These pins are not connected on package level and
will not be used for future extensions.
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSH (LVDS/CMOS 3.3V)
S = Pad class S (ADC overlayed with General Purpose Input)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1/PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
2-161
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC267x Pin Definition and Functions:
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
2.3.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during PORST active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O
Ports and Peripheral I/O Lines”, P00 / P01)
•
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
2.3.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Data Sheet
2-162
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-54 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
2.4
TC260 Bare Die Pad Definition:
List of the TC260x Bare Die Pads describes the pads of the TC260 bare die. It describes also the mapping of
VADC / DS-ADC channels to the analog inputs (ANx) and the mapping of Port functions to the pads.
The detailed description of the port functions (Px.y) can be found in the User’s Manual chapter “General Purpose
I/O Ports and Peripheral I/O LInes (Ports)“.
Data Sheet
2-163
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Pad 132
Pad 65
Pad 64
Pad 133
Y
0.0
X
Pad 1
Pad 197
Pad 260
Pad 198
Figure 2-4 TC 260 / 264 / 265 / 267 Logic Symbol for the Bare Die.
Table 2-55 List of the TC260x Bare Die Pads
Number
Pad Name
P10.8
Pad Type
X
Y
Comment
GPIO
1
2
LP / PU1 / VEXT 2756500
-2951000
-2861000
P02.0
MP+ / PU1 /
VEXT
2865000
GPIO
3
4
5
P02.1
VSS
LP / PU1 / VEXT 2756500
-2671000
-2581000
-2446000
GPIO
Vx
2865000
2756500
Must be bonded to VSS
GPIO
P02.2
MP+ / PU1 /
VEXT
6
7
8
VEXT
P02.3
P02.4
Vx
2865000
-2311000
-2256000
-2166000
Must be bonded to VEXT
LP / PU1 / VEXT 2756500
GPIO
GPIO
MP+ / PU1 /
VEXT
2865000
9
P02.5
MP+ / PU1 /
VEXT
2756500
-1976000
GPIO
Data Sheet
2-164
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
10
Pad Name
VSS
Pad Type
X
Y
Comment
Vx
2865000
-1891000
-1826000
-1746000
-1681000
-1616000
-1229000
-1099000
Must be bonded to VSS
GPIO
11
P02.6
P02.7
VEXT
P02.8
VDD
MP / PU1 / VEXT 2756500
MP / PU1 / VEXT 2865000
12
GPIO
13
Vx
2756500
Must be bonded to VEXT
GPIO
14
LP / PU1 / VEXT 2865000
15
Vx
Vx
2865000
2865000
Must be bonded to VDD
16
VSS
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 17.
17
VSS
Vx
2865000
-1059000
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 16.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VDD
Vx
2865000
-929000
-814000
-714000
-443000
-383000
-263000
-208000
-153000
-93000
Must be bonded to VDD
GPIO
P00.0
VSS
MP / PU1 / VEXT 2865000
Vx 2865000
Must be bonded to VSS
GPIO
P00.1
P00.2
P00.3
VSS
LP / PU1 / VEXT 2756500
LP / PU1 / VEXT 2865000
LP / PU1 / VEXT 2756500
GPIO
GPIO
Vx
2865000
Must be bonded to VSS
GPIO
P00.4
P00.5
P00.6
VEXT
P00.7
P00.8
P00.9
P00.10
P00.11
VSS
LP / PU1 / VEXT 2756500
LP / PU1 / VEXT 2865000
LP / PU1 / VEXT 2756500
GPIO
27000
GPIO
Vx
2865000
82000
Must be bonded to VEXT
GPIO
LP / PU1 / VEXT 2756500
LP / PU1 / VEXT 2865000
LP / PU1 / VEXT 2756500
LP / PU1 / VEXT 2865000
LP / PU1 / VEXT 2756500
147000
217000
297000
377000
442000
497000
552000
607000
707000
807000
907000
1007000
1107000
1227000
GPIO
GPIO
GPIO
GPIO
Vx
2865000
Must be bonded to VSS
GPIO
P00.12
VDD
LP / PU1 / VEXT 2756500
Vx
Vx
Vx
Vx
Vx
Vx
D
2865000
2865000
2865000
2865000
2865000
2865000
2865000
Must be bonded to VDD
Must be bonded to VSS
Must be bonded to VSS
Must be bonded to VDD
Must be bonded to VEXT
Must be bonded to VSS
Analog input
VSS
VSS
VDD
VEXT
VSS
AN49
(VADCG2.15)
43
AN48
(VADCG2.14)
D
2756500
2-165
1287000
Analog input
Data Sheet
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
44
Pad Name
Pad Type
X
Y
Comment
VDDM
Vx
2865000
2756500
1347000
1407000
ADC external supply
45
AN47 (VADCG2.13 D
/ DS3.N3)
Analog input, GPI (SENT,
CCU6)
46
47
48
49
AN46 (VADCG2.12 D
/ DS3.P3)
2865000
2756500
2865000
2756500
1470000
1530000
1605000
1665000
Analog input, GPI (SENT,
CCU6)
AN45 (VADCG2.11 D
/ DS3.N2)
Analog input, GPI (SENT,
CCU6)
AN44 (VADCG2.10 D
/ DS3.P2)
Analog input, GPI (SENT,
CCU6)
AN39 (VADCG2.7 / S
DS3.N1), P40.9
(SENT5A)
Analog input, GPI (SENT,
CCU6)
50
51
AN38 (VADCG2.6 / S
DS3.P1), P40.8
(SENT4A)
2865000
2756500
1754000
1816000
Analog input, GPI (SENT,
CCU6)
AN37 (VADCG2.5 / S
DS3.N0), P40.7
(SENT3D)
Analog input, GPI (SENT,
CCU6)
52
53
VDDM
Vx
2865000
2756500
1876000
1936000
ADC external supply
AN36 (VADCG2.4 / S
DS3.P0), P40.6
(SENT2D)
Analog input, GPI (SENT,
CCU6)
54
55
VSSM
Vx
2865000
2865000
1996000
2096000
ADC ground
AN35 (VADCG2.3) D
Analog input (mtm) (with
pull down diagnostics)
56
57
58
AN33 (VADCG2.1) D
AN32 (VADCG2.0) D
2865000
2865000
2865000
2196000
2296000
2396000
Analog input
Analog input
Analog input
AN29
(VADCG1.13)
D
D
S
59
60
AN28
(VADCG1.12)
2865000
2865000
2496000
2596000
Analog input
AN27
Analog input, GPI (SENT,
CCU6)
(VADCG1.11),
P40.3 (SENT3A)
61
AN26
(VADCG1.10),
P40.2 (SENT2A)
S
2865000
2696000
Analog input, GPI (SENT,
CCU6)
62
63
AN25(VADCG1.9), S
P40.1 (SENT1A)
2865000
2865000
2796000
2896000
Analog input, GPI (SENT,
CCU6)
AN24(VADCG1.8), S
P40.0 (SENT0A)
Analog input, GPI (SENT,
CCU6)
64
65
VDDM
VSSM
Vx
Vx
2756500
2685000
2956000
3136000
ADC external supply
ADC ground
Data Sheet
2-166
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
66
AN21 (VADCG1.5 / D
DS2NA)
2625000
3027500
Analog input
67
68
AN20 (VADCG1.4 / D
DS2PA)
2525000
2425000
3027500
3027500
Analog input
AN19 (VADCG1.3) D
Analog input (with pull down
diagnostics)
69
70
71
72
AN18 (VADCG1.2) D
AN17 (VADCG1.1) D
AN16 (VADCG1.0) D
2325000
2225000
2165000
2105000
3027500
3027500
3136000
3027500
Analog input
Analog input
Analog input
VAGND1
VAGND0
VAREF1
VAREF0
Vx
Negative Analog Reference
Voltage 1
73
74
75
Vx
Vx
Vx
2045000
1985000
1925000
3136000
3027500
3136000
Negative Analog Reference
Voltage 0
Positive Analog Reference
Voltage 1
Positive Analog Reference
Voltage 0
76
77
78
VSSM
Vx
Vx
Vx
1865000
1805000
1745000
3027500
3136000
3027500
ADC ground
VSSMREF
VSSM_DS
ADC reference ground.
DS-ADC ground. Must be
bonded with VSSM.
79
80
VDDM
Vx
Vx
1675000
1585000
3136000
3027500
ADC external supply
VDDM_DS
DS-ADC external supply.
Must be bonded with
VDDM.
81
82
83
84
AN13
(VADCG0.13)
D
D
D
D
1525000
1465000
1405000
1345000
3136000
3027500
3136000
3027500
Analog input
Analog input
Analog input
Analog input
Analog input
AN12
(VADCG0.12)
AN11
(VADCG0.11)
AN10
(VADCG0.10)
85
86
AN8 (VADCG0.8)
AN7 (VADCG0.7)
D
D
1285000
1225000
3136000
3027500
Analog input (with pull down
diagnostics)
87
88
89
90
AN6 (VADCG0.6)
AN5 (VADCG0.5)
AN4 (VADCG0.4)
D
D
D
D
1165000
1105000
1043000
983000
3136000
3027500
3136000
3027500
Analog input
Analog input
Analog input
Analog input
AN3 (VADCG0.3 /
DS0NA)
91
VSSM
Vx
923000
2-167
3136000
ADC ground
Data Sheet
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
92
AN2 (VADCG0.2 /
DS0PA)
D
863000
3027500
Analog input
93
94
VDDM
Vx
D
803000
743000
3136000
3027500
ADC external supply
Analog input
AN1 (VADCG0.1 /
DS0NB)
95
AN0 (VADCG0.0 /
DS0PB)
D
656000
3136000
Analog input
96
97
98
99
VSS
VEXT
VDD
VSS
Vx
Vx
Vx
Vx
536000
486000
436000
306000
3136000
3027500
3136000
3136000
Must be bonded to VSS
Must be bonded to VEXT
Must be bonded to VDD
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 98.
100
VSS
Vx
266000
3136000
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 97.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
VDD
Vx
Vx
Vx
Vx
136000
-250000
-315000
-415000
3136000
3027500
3136000
3136000
3027500
3136000
3027500
3136000
3027500
3136000
3027500
3136000
3027500
3136000
Must be bonded to VDD
VEXT
VEXT
EVR_OFF
P33.0
P33.1
P33.2
P33.3
P33.4
VSS
Must be bonded to VEXT
Must be bonded to VEXT
Must be bonded to VSS
LP / PU1 / VEXT -470000
LP / PU1 / VEXT -540000
LP / PU1 / VEXT -600000
LP / PU1 / VEXT -710000
LP / PU1 / VEXT -770000
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
-825000
Must be bonded to VSS
P33.5
P33.6
P33.7
P33.8
LP / PU1 / VEXT -880000
LP / PU1 / VEXT -1000000
LP / PU1 / VEXT -1060000
GPIO
GPIO
GPIO
GPIO
MP / HighZ /
VEXT
-1190000
115
116
117
118
119
120
121
122
123
P33.9
VEXT
P33.10
P33.11
P33.12
VSS
LP / PU1 / VEXT -1260000
Vx -1315000
3027500
3136000
3027500
3136000
3027500
3136000
3027500
3136000
3136000
GPIO
Must be bonded to VEXT
GPIO
MP / PU1 / VEXT -1380000
MP / PU1 / VEXT -1520000
MP / PU1 / VEXT -1600000
GPIO
GPIO
Vx
-1665000
Must be bonded to VSS
GPIO
P33.13
VSS
MP / PU1 / VEXT -1730000
Vx
Vx
-1795000
-1895000
Must be bonded to VSS
Must be bonded to VDD
VDD
Data Sheet
2-168
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
124
P32.0
LP / EVR13
SMPS -> PD,
GPIO -> PU1 /
VEXT
-1950000
3027500
GPIO
125
126
VGATE1N (SMPS) VGATE1N
-2005000
-2055000
3136000
3027500
Must be bonded to VSS if
EVR13 SMPS is not used.
Must be bonded to NMOS
gate if EVR13 SMPS is
used.
VGATE1P (SMPS) VGATE1P
Must be bonded to VEXT if
EVR13 SMPS is not used.
Must be bonded to PMOS
gate if EVR13 SMPS is
used.
127
128
VGATE3P (LDO)
VGATE1P (LDO)
VGATE3P
VGATE1P
-2105000
-2155000
3136000
3027500
Must be bonded to VSS
Must be bonded to VSS if
no external P channel
MOSFET is used for EVR13
LDO generation. Must be
bonded to external P
channnel MOSFET if
external LDO pass device is
used.
129
130
131
132
133
VEXT
P32.2
P32.3
VSS
Vx
-2205000
3136000
3027500
3027500
3136000
3027500
Must be bonded to VEXT
LP / PU1 / VEXT -2260000
LP / PU1 / VEXT -2360000
GPIO
GPIO
Vx
-2415000
-2570000
Must be bonded to VSS
GPIO
P32.4
MP+ / PU1 /
VEXT
134
135
P23.0
P23.1
LP / PU1 / VEXT -2670000
3027500
2921000
GPIO
GPIO
MP+ / PU1 /
VEXT
-2865000
136
137
138
139
VEXT
P23.2
P23.3
P23.4
Vx
-2756500
2846000
2791000
2689000
2589000
Must be bonded to VEXT
LP / PU1 / VEXT -2865000
LP / PU1 / VEXT -2865000
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
-2865000
-2756500
-2865000
140
P23.5
MP+ / PU1 /
VEXT
2489000
GPIO
141
142
VSS
Vx
2414000
2349000
Must be bonded to VSS
GPIO
P22.0
MP / LVDSM_N / -2756500
PU1 / VEXT
Data Sheet
2-169
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
143
P22.1
MP / LVDS_P /
PU1 / VEXT
-2756500
1999000
GPIO
144
145
P22.2
P22.3
MP / LVDSM_N / -2756500
PU1 / VEXT
1899000
1549000
GPIO
GPIO
MP / LVDS_P /
PU1 / VEXT
-2756500
146
147
148
149
150
151
152
153
154
VEXT
VEXT
VDD
Vx
-2865000
-2756500
-2865000
-2865000
-2865000
-2865000
-2865000
-2865000
-2756500
1484000
1434000
1384000
1284000
1184000
1084000
818000
Must be bonded to VEXT
Must be bonded to VEXT
Must be bonded to VDD
Must be bonded to VSS
Must be bonded to VSS
Must be bonded to VDD
Must be bonded to VDD
Must be bonded to VSS
Vx
Vx
VSS
Vx
VSS
Vx
VDD
Vx
VDDOSC
VSSOSC
XTAL1
Vx
Vx
718000
XTAL1
610500
Main Oscillator/PLL/Clock
Generator Input. Must be
bonded to external quartz or
resonator.
155
XTAL2
XTAL2
-2756500
510500
Main Oscillator/PLL/Clock
Generator Input. Must be
bonded to external quartz or
resonator.
156
157
158
159
160
161
162
163
VSSOSC
VDDOSC3
VDDP3
VSSP
Vx
Vx
Vx
Vx
-2865000
-2756500
-2756500
-2865000
403000
353000
253000
203000
153000
53000
Must be bonded to VSS
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VSS
GPIO
P21.0
A2 / PU1 / VDDP3 -2756500
A2 / PU1 / VDDP3 -2756500
P21.1
GPIO
VSSP
Vx
-2865000
3000
Must be bonded to VSS
GPIO
P21.2
LVDSH_N / PU1 / -2756500
VDDP3
-59500
164
P21.3
LVDSH_P / PU1 / -2756500
VDDP3
-159500
GPIO
165
166
VDDP3
P21.4
Vx
-2865000
-222000
-296500
Must be bonded to VDDP3
GPIO
LVDSH_N / PU1 / -2756500
VDDP3
167
P21.5
LVDSH_P / PU1 / -2756500
VDDP3
-447500
GPIO
168
169
170
P21.6
VDDP3
VSSP
A2 / PU / VDDP3 -2756500
-547000
-597000
-812000
GPIO, TDI
Vx
Vx
-2865000
-2865000
Must be bonded to VDDP3
Must be bonded to VSS
Data Sheet
2-170
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
171
TMS /DAP1
A2 / PD / VDDP3 -2756500
-862000
JTAG Module TMS Input /
Device Access Port Line 1
172
173
P21.7
A2 / PU / VDDP3 -2865000
A2 / PD / VDDP3 -2756500
-912000
-982000
GPIO, TDO
TRST (N)
JTAGModuleReset/Enable
Input
174
TCK /DAP0
A2 / PD / VDDP3 -2865000
-1032000
JTAG Module Clock Input /
Device Access Port Line 0
175
176
177
P20.0
P20.1
P20.2
MP / PU1 / VEXT -2756500
LP / PU1 / VEXT -2865000
-1167000
-1237000
-1292000
GPIO
GPIO
LP / PU / VEXT
-2756500
Testmode pin must be
bonded
178
179
180
VSS
Vx
-2865000
-1342000
-1397000
-1472000
Must be bonded to VSS
GPIO
P20.3
LP / PU1 / VEXT -2756500
ESR1 (N)
/EVRWUP
MP / PU1
-2865000
-2756500
-2865000
External System Request
Reset 1. Default NMI
function. / EVR Wakeup Pin
181
182
PORST (N)
PORST / PD /
VEXT
-1554500
-1642000
Power On Reset Input.
Additional strong PD in case
of power fail.
ESR0 (N)
/EVRWUP
MP / OD
External System Request
Reset 0. Default
configuration during and
after reset is open-drain
driver. The driver drives low
during power-on reset.
/EVR Wakeup Pin
183
184
185
VEXT
VDD
VSS
Vx
Vx
Vx
-2756500
-2865000
-2865000
-1707000
-1757000
-1887000
Must be bonded to VEXT
Must be bonded to VDD
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 184.
186
VSS
Vx
-2865000
-1927000
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 183.
187
188
189
190
191
192
193
194
VDD
Vx
-2865000
-2057000
-2112000
-2167000
-2222000
-2317000
-2387000
-2497000
-2562000
Must be bonded to VDD
P20.6
VSS
LP / PU1 / VEXT -2756500
Vx -2865000
GPIO
Must be bonded to VSS
P20.7
P20.8
P20.9
P20.10
VEXT
LP / PU1 / VEXT -2756500
MP / PU1 / VEXT -2865000
LP / PU1 / VEXT -2756500
MP / PU1 / VEXT -2865000
GPIO
GPIO
GPIO
GPIO
Vx
-2756500
Must be bonded to VEXT
Data Sheet
2-171
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
Pad Name
P20.11
P20.12
VSS
Pad Type
X
Y
Comment
MP / PU1 / VEXT -2865000
MP / PU1 / VEXT -2756500
-2627000
-2707000
-2772000
-2837000
-2937000
-3027500
-3027500
-3136000
-3136000
-3027500
-3136000
-3136000
-3027500
-3136000
-3027500
-3136000
-3027500
GPIO
GPIO
Vx
-2865000
Must be bonded to VSS
P20.13
P20.14
P15.0
P15.1
P15.2
P15.3
VEXT
P15.4
P15.5
P15.6
VSS
MP / PU1 / VEXT -2756500
MP / PU1 / VEXT -2756500
LP / PU1 / VEXT -2680000
LP / PU1 / VEXT -2580000
MP / PU1 / VEXT -2510000
MP / PU1 / VEXT -2410000
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
-2345000
Must be bonded to VEXT
MP / PU1 / VEXT -2280000
MP / PU1 / VEXT -2180000
MP / PU1 / VEXT -2059000
GPIO
GPIO
GPIO
Vx
-1994000
Must be bonded to VSS
P15.7
P15.8
P14.0
MP / PU1 / VEXT -1929000
MP / PU1 / VEXT -1849000
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
-1741000
212
213
214
P14.1
VEXT
P14.2
MP / PU1 / VEXT -1641000
Vx -1576000
-3027500
-3136000
-3027500
GPIO
Must be bonded to VEXT
LP / PU1 / VEXT -1521000
Must be bonded to VEXT if
EVR13 active. Must be
bonded to VSS if EVR13
inactive.
215
216
217
218
P14.3
P14.4
VSS
LP / PU1 / VEXT -1461000
LP / PU1 / VEXT -1386000
-3136000
-3027500
-3136000
-3027500
GPIO
GPIO
Vx
-1331000
-1256000
Must be bonded to VSS
GPIO
P14.5
MP+ / PU1 /
VEXT
219
P14.6
MP+ / PU1 /
VEXT
-1156000
-3136000
GPIO
220
221
222
P14.7
P14.8
P14.9
LP / PU1 / VEXT -1076000
LP / PU1 / VEXT -1016000
-3027500
-3136000
-3027500
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
-936000
223
P14.10
MP+ / PU1 /
VEXT
-836000
-3027500
GPIO
224
225
226
Reserved
VEXT
Vx
Vx
Vx
-761000
-711000
-661000
-3136000
-3027500
-3136000
Must be bonded to VSS
Must be bonded to VEXT
Must be bonded to VSS
VSS
Data Sheet
2-172
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
227
Pad Name
VEXT
Pad Type
X
Y
Comment
Vx
Vx
-611000
-531000
-3027500
-3136000
Must be bonded to VEXT
228
VSS
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 228.
229
230
VDDP3
VSS
Vx
Vx
-508500
-486000
-3027500
-3136000
Must be bonded to VDDP3
Must be bonded to VSS.
Double Pad (Elephant Pad),
shared with Pad Nr. 226.
231
232
233
234
235
236
VDDP3
VDDFL3
VDDFL3
VDDFL3
VSS
Vx
Vx
Vx
Vx
Vx
-391000
-311000
-211000
-143500
-91000
-3027500
-3136000
-3136000
-3027500
-3136000
-3027500
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VSS
GPIO
P13.0
MP / LVDSM_N / -26000
PU1 / VEXT
237
P13.1
MP / LVDSM_P / 324000
PU1 / VEXT
-3027500
GPIO
238
239
VEXT
P13.2
Vx
389000
-3136000
-3027500
Must be bonded to VEXT
GPIO
MP / LVDSM_N / 454000
PU1 / VEXT
240
241
242
243
244
P13.3
P11.2
P11.3
P11.6
P11.9
MP / LVDSM_P / 804000
PU1 / VEXT
-3027500
-3027500
-3027500
-3027500
-3027500
GPIO
MPR / PU1 /
VFLEX
964000
GPIO
MPR / PU1 /
VFLEX
1064000
1164000
1264000
GPIO
MPR / PU1 /
VFLEX
GPIO
MP+ / PU1 /
VFLEX
GPIO
245
246
VSSFLEX
VDDFLEX
Vx
Vx
1339000
1389000
-3136000
-3027500
Must be bonded to VSS
Must be bonded to VEXT or
VDDP3
247
248
249
250
VDD
Vx
Vx
1439000
1539000
-3136000
-3136000
-3027500
-3136000
Must be bonded to VDD
Must be bonded to VSS
GPIO
VSS
P11.10
P11.11
LP / PU1 / VFLEX 1594000
MP+ / PU1 /
VFLEX
1682000
GPIO
251
252
P11.12
P10.0
MPR / PU1 /
VFLEX
1782000
-3027500
-3136000
GPIO
GPIO
LP / PU1 /VEXT 1932000
Data Sheet
2-173
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
Table 2-55 List of the TC260x Bare Die Pads
Number
Pad Name
Pad Type
X
Y
Comment
253
P10.1
MP+ / PU1 /
VEXT
2012000
-3027500
GPIO
254
255
256
257
P10.2
VSS
MP / PU1 / VEXT 2112000
Vx 2177000
MP / PU1 / VEXT 2242000
-3027500
-3136000
-3027500
-3136000
GPIO
Must be bonded to VSS
P10.3
P10.4
GPIO
GPIO
MP+ / PU1 /
VEXT
2360000
258
259
260
261
262
P10.5
VEXT
P10.6
P10.7
VSS
LP / PU1 / VEXT 2460000
Vx 2515000
-3136000
-3027500
-3136000
-3027500
-3136000
GPIO
Must be bonded to VEXT
GPIO
LP / PU1 / VEXT 2570000
LP / PU1 / VEXT 2630000
GPIO
Vx
2685000
Must be bonded to VSS
Data Sheet
2-174
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
2.4.1
TC 260 / 264 / 265 / 267 Bare Die Pad Description
Legend:
Column “Number”:
Running number of pads in the pad frame
Column “Name”:
Symbolic name of the pad.
The functions mapped on GPIO pads “Px.y” are described in the User’s Manual chapter ”General Purpose I/O
Ports and Peripheral I/O LInes (Ports)”
Column “Type”:
LP = Pad class LP (5V/3.3V, LVTTL)
MP = Pad class MP (5V/3.3V, LVTTL)
MP+ = Pad class MP (5V/3.3V, LVTTL)
A2 = Pad class A2 (3.3V, LVTTL)
LVDSM = Pad class LVDSM (LVDS/CMOS 5V/3.3V)
LVDSH = Pad class LVDSM (LVDS/CMOS 3.3V)
S = Pad class D (ADC)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)1)
PD = with pull-down device connected during reset (PORST = 0)
OD = open drain during reset (PORST = 0)
High-Z = tri-state during reset (PORST = 0)
Column “X” / “Y”:
Pad opening center coordinates
2.4.2
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-56 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
1) The default pad reset state (PU or High-Z) can be controlled via HWCFG6 (P14.4).
Data Sheet
2-175
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Package and Pinning DefinitionsTC260 Bare Die Pad Definition:
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
2-176
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationParameter Interpretation
3
Electrical Specification
3.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC 260 / 264 / 265 / 267 and partly
its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they
are marked with an two-letter abbreviation in column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of the TC 260 / 264 / 265 /
267 and must be regarded for a system design.
•
SR
Such parameters indicate System Requirements which must provided by the microcontroller system in which
the TC 260 / 264 / 265 / 267 designed in.
Data Sheet
4-177
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationAbsolute Maximum Ratings
3.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3-1 Absolute Maximum Ratings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Storage Temperature
T
ST SR
-65
-
170
°C
upto 65h @ TJ =
150°C; upto 15h @ TJ
= 170°C
Voltage at VDD power supply
pins with respect to VSS
V
V
DD SR
-
-
-
-
1.9
V
V
1)
Voltage at VDDP3 and VDDFL3
DDP3 SR
4.43
power supply pins with respect
1)
to VSS
Voltage at VDDM, VEXT and
V
DDM SR
-
-
-
7.0
V
V
V
FLEX power supply pins with
1)
respect to VSS
Voltage on any class A2 and
LVDSH input pin with respect
VIN SR
-0.5
min(
VDDP3
0.6 , 4.23
Whatever is lower
+
1)2)
to VSS
)
Voltage on all other input pins VIN SR
with respect to VSS
-0.5
-10
-
-
-
7.0
10
V
1)2)
Input current on any pin during IIN SR
mA
mA
overload condition 3)
Absolute maximum sum of all ΣIIN SR
input circuit currents during
overload condition 3)
-100
100
1) Valid for cumulated for up to 2.8h and pulse forms following a power supply switch on phase, where the rise and fall times
are releated to the system capacities and coils.
2) Voltages below VINmin have no Impact to the device reliabiltiy as Long as the times and currents defined in section Pin
Reliability in Overload for the affected pad(s) are not violated.
3) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may
damage the device.
Data Sheet
4-178
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPin Reliability in Overload
3.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience overload currents and
voltages that go beyond their own IO power supplies specification.
The following table defines overload conditions that will not cause any negative reliability impact if all the following
conditions are met:
•
•
full operation life-time is not exceeded
Operating Conditions are met for
–
–
pad supply levels
temperature
If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters
functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still
possible in most cases but with relaxed parameters.
Note:An overload condition on one or more pins does not require a reset.
Table 3-2 Overload Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-5
-15 1)
Max.
5
15 1)
Input current on any digital pin IIN
during overload condition
-
-
mA
mA
except LVDS pins
except LVDS pins;
limited to max. 20
pulses with 1ms pulse
length
Input current on LVDS pin
during overload condition
IINLVDS
-3
-
-
3
mA
mA
Absolute maximum sum of all IING
input circuit currents during
overload condition
-50
50
Input current on analog input
pin during overload condition
IINANA
-3
-5
-
-
3
5
mA
mA
limited to 60h over
lifetime
Absolute sum of all ADC inputs IINSCA
during overload condition
-20
-
-
20
mA
mA
Absolute maximum sum of all ΣIINS
input circuit currents during
overload condition
-100
100
Signal voltage over/undershoot VOUS
at GPIOs
V
SS - 2
-
VEXT/FLEX
+ 2
V
limited to 60h over
lifetime; Valid for LP,
MP, MP+, and MPR
pads
Inactive device pin current
during overload condtion 2)
IID
-1
-
-
1
mA
mA
All power supply
voltages VDDx = 0
Sum of all inactive device pin IIDS
-100
100
currents 2)
Data Sheet
4-179
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
digital inputs, negative 3)
KOVDN CC
-
2*10-4
6*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
LP and A2 pads; -2mA
< IIN < 0mA
-
-
-
-
1*10-2
Overload injected on
GPIO non LVDS pad
and affecting neighbor
LP and A2 pads; -5mA
< IIN < -2mA
1.7*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
MP, MP+, and MPR
pads; -2mA < IIN <
0mA
-
-
-
-
2*10-2
Overload injected on
GPIO non LVDS pad
and affecting neighbor
MP, MP+, and MPR
pads; -5mA < IIN < -
2mA
0.3
Overload injected on
LVDS pad and
affecting neighbor
LVDS pads
-
-
-
-
0.93
couplingbetweenpads
21.2 and 21.3
Overload coupling factor for
digital inputs, positive 3)
KOVDP CC
1*10-5
Overload injected on
GPIO non LVDS pad
and affecting neighbor
GPIO non LVDS pads
-
-
-
-
1*10-4
5*10-4
Overload injected on
GPIO pad and
affecting neighbor
P32.0 pad
Overload injected on
LVDS pad and
affecting neighbor
LVDS pads
Data Sheet
4-180
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
analog inputs, negative
KOVAN CC
-
-
6*10-4 4)
Analog Inputs overlaid
with class LP pads or
pull down diagnostics;
-1mA < IIN < 0mA
-
-
1*10-2
Analog Inputs overlaid
with class LP pads or
pull down diagnostics;
-5mA < IIN < -1mA
-
-
-
-
1*10-4
1*10-5
else; -5mA < IIN < 0mA
5mA < IIN < 0mA
Overload coupling factor for
analog inputs, positive
KOVAP CC
1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters.
2) Limitations for time and supply levels specified in this section are not valid for this parameter.
3) Overload is measured as increase of pad leakage caused by injection on neighbor pad.
4) For analogue inputs overlaid with DSADC function the VCM holdbuffer shall be enabled, in case DSADCs are enabled.
Note:DSADC input pins count as analog pins as they are overlaid with VADC pins.
Table 3-3 PN-Junction Characteristics for positive Overload
Pad Type
IIN = 3 mA
IIN = 5 mA
F / A2
UIN = VDDP3 + 0.5 V
UIN = VEXT / FLEX + 0.75 V
UIN = VEXT + 0.75 V
UIN = VDDP3 + 0.5 V
UIN = VDDM + 0.75 V
UIN = VDDP3 + 0.6 V
LP / MP / MP+ / MPR
UIN = VEXT / FLEX + 0.8 V
LVDSM
LVDSH
D
-
-
-
Table 3-4 PN-Junction Characteristics for negative Overload
Pad Type
IIN = -3 mA
IIN = -5 mA
F / A2
UIN = VSS - 0.5 V
UIN = VSS - 0.75 V
UIN = VSS - 0.75 V
UIN = VSS - 0.5 V
UIN = VSS - 0.75 V
UIN = VSS - 0.6 V
LP / MP / MP+ / MPR
UIN = VSS - 0.8 V
LVDSM
LVDSH
D
-
-
-
Data Sheet
4-181
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationOperating Conditions
3.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the
TC 260 / 264 / 265 / 267. All parameters specified in the following tables refer to these operating conditions, unless
otherwise noticed.
Digital supply voltages applied to the TC 260 / 264 / 265 / 267 must be static regulated voltages.
All parameters specified in the following tables refer to these operating conditions (see table below), unless
otherwise noticed in the Note / Test Condition column.
Table 3-5 Operating Conditions
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
200
200
200
200
200
400
100
200
100
200
100
200
100
100
100
80
SRI frequency
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SRI SR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mA
Max System Frequency
CPU0 Frequency
CPU1 Frequency
PLL output frequency
PLL_ERAY output frequency
SPB frequency
MAX SR
CPU0 SR
CPU1 SR
PLL SR
-
-
-
20
PLLERAY SR 20
SPB SR
-
-
-
-
-
-
-
-
-
-
-
-
-
ASCLIN fast frequency
ASCLIN slow frequency
Baud2 frequency
Baud1 frequency
FSI2 frequency
ASCLINF SR
ASCLINS SR
BAUD2 SR
BAUD1 SR
FSI2 SR
FSI frequency
FSI SR
GTM frequency
GTM SR
STM SR
STM frequency
ERAY frequency
ERAY SR
BBB SR
BBB frequency
100
100
100
MultiCAN frequency
CAN SR
Absolute sum of short circuit
currents of the device
ΣISC_D SR
Ambient Temperature
TA SR
-40
-40
-40
-
-
-
125
150
170
°C
°C
°C
valid for all SAK
products
valid for all SAL
products
valid for all SAL
products without
package
Junction Temperature
TJ SR
-40
-40
-
-
150
170
°C
°C
valid for all SAK
products
valid for all SAL
products
Data Sheet
4-182
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationOperating Conditions
Table 3-5 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Core Supply Voltage 1)
V
DD SR
1.17
1.3
1.43 2)
V
Only required if
externally supplied
ADC analog supply voltage
V
V
DDM SR
EXT SR
2.97
2.97
5.0
-
5.5 3)
4.5
V
V
Digital external supply voltage
for LP, MP, MP+ and LVDSM
pads and EVR 4)
3.3V pad parameters
are valid
4.5
5.0
-
5.5 3)
4.5
V
V
V
V
5V pad parameters are
valid
Digital supply voltage for Flex
port
V
FLEX SR
2.97
4.5
3.3V pad parameters
are valid
5.0
3.3
5.5 3)
3.63 6)
5V pad parameters are
valid
Digital supply voltage for
LVDSH and A2 pads 5)
V
V
DDP3 SR
2.97
3.3V pad parameters
are valid; only required
if externally supplied
Flash supply voltage 3.3V 1)
DDFL3 SR 2.97
3.3
3.63
V
Only required if
externally supplied
Digital ground voltage
V
V
SS SR
0
-
-
V
V
V
V
Analog ground voltage for VDDM
SSM CC
-0.1
0
-
0.1
Voltage to ensure defined pad VDDPPA CC 0.72
-
-
A2 and LVDSH
states 7)
1.4
-
LP, MP, MP+, MPR
and LVDSM
Digital supply voltage for GPIO VDDP3 SR
2.97
3.3
3.63
V
pads and EVR 5)
SCR CCLK frequency
SCR PCLK frequency
SCR RTC frequency
SCR WDT frequency
f
f
f
f
CCLK SR
PCLK SR
RTC SR
0.07
-
-
-
-
20
20
20
20
MHz
MHz
MHz
MHz
0.07
0.0002
WDTCLK SR 0.00078
1) No external inductive load permissible if EVR is used. All VDD pins shall be connected together externally on the PCB.
2) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
3) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
4) All VEXT pins shall be connected together externally on the PCB.
5) All VDDP3 pins shall be connected together externally on the PCB.
6) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
7) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-up/power-down
of VDDP3
.
Data Sheet
4-183
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
3.5
5 V / 3.3 V switchable Pads
Pad classes LP, MP, MP+, and MPR support both Automotive Level (AL) or TTL level (TTL) operation. Parameters
are defined for AL operation and degrade in TTL operation.
Table 3-6 Standard_Pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pin capacitance (digital
inputs/outputs)
CIO CC
-
6
10
pF
ns
Spike filter always blocked
pulse duration
t
SF1 CC
-
-
80
-
PORST only
PORST only
Spike filter pass-through pulse tSF2 CC
220
-
ns
duration
PORST pad output current 1)
I
PORST CC 11
13
-
-
mA
mA
V
EXT = 3.0V; VPORST
0.9V; TJ = 165°C
EXT = 4.5V; VPORST
1.0V
=
=
-
-
V
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
Table 3-7 Class LP 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for LP pad 1) HYSLP CC 0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input Leakage current for LP
pad
I
OZLP CC
-150
150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
-
350
nA
nA
else
Input leakage current for P32.0 IOZP320 CC -4900
4900
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-9400
-
9400
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); for TJ >
150°C
-5800
-
-
-
-
-
5800
nA
nA
µA
µA
µA
else
-12000
12000
else; for TJ > 150°C
Pull-up current for LP pad
I
PUHLP CC
|30|
|43|
-
-
V
V
V
IHmin; AL
-
IHmin; TTL
|107|
ILmax; AL and TTL
Data Sheet
4-184
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-7 Class LP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
|100|
-
Pull-down current for LP pad
I
PDLLP CC
-
µA
V
V
V
IHmin; AL and TTL
ILmax; AL
|46|
|21|
200
-
µA
-
-
µA
ILmax; TTL
On-Resistance for LP pad,
weak driver 2)
RDSONLPW
CC
620
1040
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-Resistance for LP pad,
medium driver 2)
Rise / fall time for LP pad 3)
RDSONLPM
CC
50
-
155
260
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
t
LP CC
-
-
-
-
-
95+2.1 * ns
CL
CL≤50pF; pin out
driver=weak
-
200+2.9 * ns
( CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=weak
-
25+0.5 * ns
CL
CL≤50pF; pin out
driver=medium
-
50+0.75 * ns
( CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=medium
Input high voltage for LP pad
Input low voltage for LP pad
V
V
V
IHLP SR
ILLP SR
ILHLP CC
(0.73*VEX
T/FLEX)-
0.25
2.03 4)
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
-
(0.52*VEX
T/FLEX)-
0.25
0.8 5)
-
-
-
V
V
Hysteresis active, TTL
Input low / high voltage for LP
pad
1.85
3.0
Hysteresis inactive;
not available for P14.2,
P14.4, and P15.1
Pad set-up time for LP pad
t
SET_LP CC
-
-
-
100
ns
Input leakage current for P02.1 IOZ021 CC
-150
1030
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ >
150°C
-150
-
340
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ =
150°C
-420
-350
-
-
-
-
-
-
-
-
1100
nA
nA
µA
µA
µA
µA
µA
µA
else; TJ > 150°C
else; TJ = 150°C
380
Pull down current for P32_0 pin IPDLP320 CC -
|41|
|105|
V
V
V
V
V
V
IHmin; AL and TTL
ILmax; AL
-
|16|
-
ILmax; TTL
Pull Up Current for P32_0 pin
I
PUHP320 CC |25|
-
IHmin; AL
|38|
-
-
IHmin; TTL
|112|
ILmax; AL and TTL
Data Sheet
4-185
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-7 Class LP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Short Circuit current for LP pad ISC SR
-10
-
10
mA
%
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-8 Class LP 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for LP pad 1) HYSLP CC 0.05 *
VEXT/FLEX
Input Leakage current for LP
pad
I
OZLP CC
-150
-
150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
-
350
nA
nA
else
Input leakage current for P32.0 IOZP320 CC -4900
4900
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-9400
-
9400
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); for TJ >
150 °C
-5800
-
5900
nA
nA
µA
µA
µA
µA
µA
µA
Ohm
else
-12000
-
12000
else; for TJ > 150°C
Pull-up current for LP pad
I
I
PUHLP CC
|17|
|19|
-
-
-
V
V
V
V
V
V
IHmin; AL
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for LP pad
PDLLP CC
-
-
|22|
|11|
250
-
-
-
ILmax; TTL
On-Resistance for LP pad,
weak driver 2)
RDSONLPW
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
On-Resistance for LP pad,
medium driver 2)
RDSONLPM
CC
70
235
400
Ohm
; NMOS/PMOS ;
IOH=1mA; IOL=1mA
Data Sheet
4-186
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-8 Class LP 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise / fall time for LP pad 3)
t
LP CC
-
-
-
-
-
-
150+3.4 * ns
CL
CL≤50pF; pin out
driver=weak
-
-
-
320+4.5 * ns
( CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=weak
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
70+1.1 * ( ns
CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=medium
Input high voltage for LP pad
Input low voltage for LP pad
V
V
V
IHLP SR
ILLP SR
ILHLP CC
(0.73*VEX
T/FLEX)-
0.25
1.6 4)
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Input low / high voltage for LP
pad
1.1
1.9
Hysteresis inactive;
not available for P14.2,
P14.4, and P15.1
Pad set-up time for LP pad
t
SET_LP CC
-
-
-
100
920
ns
Input leakage current for P02.1 IOZ021 CC
-150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ >
150°C
-150
-
330
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ =
150°C
-360
-350
-
-
-
-
-
-
-
-
-
1000
nA
nA
µA
µA
µA
µA
µA
µA
mA
else; TJ > 150°C
else; TJ = 150°C
375
Pull down current for P32_0 pin IPDLP320 CC -
|17|
|80|
V
V
V
V
V
V
IHmin; AL and TTL
ILmax; AL
-
|6|
-
ILmax; TTL
Pull Up Current for P32_0 pin
I
PUHP320 CC |12|
-
IHmin; AL
|14|
-
-
IHmin; TTL
|80|
10
ILmax; AL and TTL
Short Circuit current for LP pad ISC SR
-10
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
Data Sheet
4-187
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-9 Class MP 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for MP pad 1) HYSMP CC 0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input Leakage current for MP
pad
I
I
OZMP CC
-500
500
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1000
-
1000
nA
else
Pull-up current for MP pad
PUHMP CC |30|
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|43|
-
-
-
IHmin; TTL
-
|107|
|100|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP pad
I
PDLMP CC
-
-
|46|
|21|
-
-
-
ILmax; TTL
On-Resistance for MP pad,
weak driver 2)
RDSONMPW 200
CC
620
1040
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-Resistance for MP pad,
medium driver 2)
RDSONMPM
CC
50
20
155
75
260
130
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-Resistance for MP pad,
strong driver 2)
RDSONMPS
CC
PMOS/NMOS ;
IOH=8mA; IOL=8mA
Data Sheet
4-188
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-9 Class MP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise / fall time for MP pad 3)
t
MP CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF; pin out
driver=weak
L
-
-
-
200+2.9*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
25+0.5*C ns
CL≤50pF; pin out
driver=medium
L
50 + 0.75 ns
CL≥50pF; CL≤200pF;
* ( CL - 50
)
pin out driver=medium
-
-
-
-
17.5+0.25 ns
*CL
CL≤50pF;
edge=medium ; pin out
driver=strong
30+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
7+0.2*CL ns
CL≤50pF; edge=sharp
; pin out driver=strong
17+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
Input high voltage for MP pad
Input low voltage for MP pad
V
V
IHMP SR
(0.73*VEX
T/FLEX)-
0.25
2.03 4)
-
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
ILMP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP VILHMP CC 1.85
3.0
pad
Pad set-up time for MP pad
t
SET_MP CC
-
-
-
100
10
ns
Short Circuit current for MP pad ISC SR
-10
mA
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Data Sheet
4-189
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-10 Class MP 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for MP pad 1) HYSMP CC 0.05 *
VEXT/FLEX
Input Leakage current for MP
pad
I
OZMP CC
-500
-
500
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1000
-
1000
nA
else
Pull-up current for MP pad
I
PUHMP CC |17|
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP pad
I
PDLMP CC
-
-
|22|
|11|
-
-
-
ILmax; TTL
On-Resistance for MP pad,
weak driver 2)
RDSONMPW 250
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
On-Resistance for MP pad,
medium driver 2)
RDSONMPM
CC
70
20
-
235
400
200
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA; IOL=1mA
On-Resistance for MP pad,
strong driver 2)
Rise / fall time for MP pad 3)
RDSONMPS
CC
110
PMOS/NMOS ;
I
OH=4mA; IOL=4mA
t
MP CC
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF; pin out
driver=weak
-
320+4.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
-
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
-
70+1.1*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
-
32.5+0.35 ns
CL≤50pF;
*CL
edge=medium ; pin out
driver=strong
-
-
50+0.45*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
14.5+0.35 ns
*CL
CL≤50pF; edge=sharp
; pin out driver=strong
32+0.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
Data Sheet
4-190
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-10 Class MP 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for MP pad
V
V
IHMP SR
(0.73*VEX
T/FLEX)-
0.25
1.6 4)
-
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP pad
ILMP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP VILHMP CC 1.1
1.9
pad
Pad set-up time for MP pad
t
SET_MP CC
-
-
-
100
10
ns
Short Circuit current for MP pad ISC SR
-10
mA
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-11 Class MP+ 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input hysteresis for MP+ pad 1) HYSMPP
0.09 *
CC
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input leakage current for MP+
pad
I
I
OZMPP CC -750
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPP CC |30|
-
-
-
-
-
-
-
1500
nA
µA
µA
µA
µA
µA
µA
else
Pull-up current for MP+ pad
-
V
V
V
V
V
V
IHmin; AL
|43|
-
-
IHmin; TTL
|107|
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP+ pad IPDLMPP CC
-
|100|
|46|
|21|
-
-
ILmax; TTL
Data Sheet
4-191
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-11 Class MP+ 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-resistance for MP+ pad,
weak driver 2)
RDSONMPPW 200
CC
620
1040
Ohm
Ohm
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-resistance for MP+ pad,
medium driver 2)
RDSONMPPM 50
CC
155
260
90
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-resistance for MP+ pad,
strong driver 2)
Rise/fall time for MP+ pad 3)
RDSONMPPS 20
CC
55
-
PMOS/NMOS ;
I
OH=8mA; IOL=8mA
t
MPP CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF; pin out
driver=weak
L
-
200+2.9*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
-
25+0.5*C ns
CL≤50pF; pin out
driver=medium
L
-
50+0.75*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
-
9+0.16*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=strong
-
-
17+0.2*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
4+0.16*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
12+0.21*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
-
-
5
ns
from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out
driver=strong
-
-
4.5
-
ns
V
CL=15pF; edge=sharp
; pin out driver=strong
Input high voltage for MP+ pad VIHMPP SR (0.73*VEX
Hysteresis active, AL
T/FLEX)-
0.25
2.03 4)
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP+ pad
V
ILMPP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP+ VILHMPP CC 1.85
3.0
pad
Pad set-up time for MP+ pad
t
SET_MPP CC -
-
100
ns
Data Sheet
4-192
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-11 Class MP+ 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Short circuit current for MP+
pad 6)
I
SCMPP SR -10
-
10
mA
%
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-12 Class MP+ 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input hysteresis for MP+ pad 1) HYSMPP
0.05 *
CC
VEXT/FLEX
Input leakage current for MP+
pad
I
OZMPP CC -750
-
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPP CC |17|
-
1500
nA
else
Pull-up current for MP+ pad
I
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP+ pad IPDLMPP CC
-
-
|22|
|11|
-
-
-
ILmax; TTL
On-resistance for MP+ pad,
weak driver 2)
RDSONMPPW 250
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
On-resistance for MP+ pad,
medium driver 2)
RDSONMPPM 70
CC
235
75
400
130
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA; IOL=1mA
PMOS/NMOS ;
IOH=4mA; IOL=4mA
On-resistance for MP+ pad,
strong driver 2)
RDSONMPPS 20
CC
Data Sheet
4-193
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-12 Class MP+ 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time for MP+ pad 3)
t
MPP CC
-
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF; pin out
driver=weak
-
-
-
-
320+4.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
70+1.1*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
20+0.2*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=strong
-
-
30+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
13+0.2*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
7.65
5.42
7.36
5.32
5.9
ns
ns
ns
ns
ns
ns
CL = 15pF; VEXT/FLEX
3.135V; V = 0V to
=
2.0V; edge=sharp ; pin
out driver=strong
-
-
-
-
-
-
-
-
-
-
-
CL = 15pF; VEXT/FLEX =
3.135V; V = 3.135V to
0.8V; edge=sharp ; pin
out driver=strong
CL = 15pF; VEXT/FLEX
3.201V; V = 0V to
=
2.0V; edge=sharp ; pin
out driver=strong
CL = 15pF; VEXT/FLEX
=
3.201V; V = 3.201V to
0.8V; edge=sharp ; pin
out driver=strong
CL = 15pF; VEXT/FLEX
=
3.63V; V = 0V to 2.0V;
edge=sharp ; pin out
driver=strong
4.8
CL = 15pF; VEXT/FLEX
3.63V; V = 3.63V to
=
0.8V; edge=sharp ; pin
out driver=strong
-
-
23+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
5
ns
ns
from 0.8V to 2.0V
(RMII) ; CL=25pF;
V 1.0 2017-06
edge=sharp ; pin out
Data Sheet
4-194
driver=strong
-
-
4.5
from 0.2 * VEXT/FLEX to
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-12 Class MP+ 3.3V (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for MP+ pad VIHMPP SR (0.73*VEX
-
-
V
Hysteresis active, AL
T/FLEX)-
0.25
1.6 4)
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP+ pad
V
ILMPP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP+ VILHMPP CC 1.1
1.9
pad
Pad set-up time for MP+ pad
t
SET_MPP CC -
SCMPP SR -10
-
-
100
10
ns
Short circuit current for MP+
pad 6)
I
mA
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-13 Class MPR 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for MPR pads HYSMPR
0.09 *
VEXT/FLEX
1)
CC
0.075*
VEXT/FLEX
-
-
-
V
TTL
Input leakage current class
MPR
I
I
OZMPR CC -750
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPR CC |30|
-
-
-
-
-
-
-
1500
nA
µA
µA
µA
µA
µA
µA
else
Pull-up current
-
V
V
V
V
V
V
IHmin; AL
|43|
-
-
IHmin; TTL
|107|
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current
I
PDLMPR CC -
|100|
|46|
|21|
-
-
ILmax; TTL
Data Sheet
4-195
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-13 Class MPR 5V (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
On-resistance of the MPR pad, RDSONMPRW 200
weak driver 2)
CC
On-resistance of the MPR pad, RDSONMPRM 50
medium driver 2)
CC
Max.
620
1040
Ohm
Ohm
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
155
260
90
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-resistance of the MPR pad, RDSONMPRS 20
55
-
PMOS/NMOS ;
strong driver 2)
Rise/fall time 3)
CC
I
OH=8mA; IOL=8mA
t
MPR CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF; pin out
driver=weak
L
-
200+2.9*( ns
CL≥50pF; CL≤200pF;
pin out driver=weak
CL-50)
-
25+0.5*C ns
CL≤50pF; pin out
driver=medium
L
-
50+0.75*( ns
CL≥50pF; CL≤200pF;
pin out driver=medium
CL-50)
-
9+0.16*C ns
CL≥0pF; CL≤50pF;
edge=medium ; pin out
driver=strong
L
-
-
17+0.2*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
4+0.16*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
12+0.21*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
-
-
-
-
5
ns
ns
V
from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out
driver=strong
4.5
from 0.2 * VEXT/FLEX to
0.8 * VEXT/FLEX
;
CL=15pF; edge=sharp
; pin out driver=strong
Input high voltage, class MPR
pads
V
V
V
IHMPR SR (0.73*VEX
-
-
Hysteresis active, AL
T/FLEX)-
0.25
2.03 4)
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage, class MPR
pads
ILMPR SR
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage, class
MPR pads
ILHMPR SR 1.2
2.3
Data Sheet
4-196
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-13 Class MPR 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
100
10
Pad set-up time
t
SET_MPR CC -
-
-
ns
Short circuit current Class MPR ISC SR
-10
mA
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
Table 3-14 Class MPR 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for MPR pads HYSMPR
0.05 *
VEXT/FLEX
1)
CC
Input leakage current class
MPR
I
OZMPR CC -750
-
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPR CC |17|
-
1500
nA
else
Pull-up current
I
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current
I
PDLMPR CC -
-
|22|
|11|
-
-
-
ILmax; TTL
On-resistance of the MPR pad, RDSONMPRW 250
weak driver 2)
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
On-resistance of the MPR pad, RDSONMPRM 70
medium driver 2)
CC
On-resistance of the MPR pad, RDSONMPRS 20
strong driver 2)
CC
235
75
400
130
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA; IOL=1mA
PMOS/NMOS ;
OH=4mA; IOL=4mA
I
Data Sheet
4-197
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-14 Class MPR 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time 3)
t
MPR CC
-
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF; pin out
driver=weak
-
-
-
-
320+4.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
70+1.1*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
20+0.2*C ns
CL≥0pF; CL≤50pF;
edge=medium ; pin out
driver=strong
L
-
-
30+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
13+0.2*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
23+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
-
-
-
-
5
ns
ns
V
from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out
driver=strong
4.5
from 0.2 * VEXT/FLEX to
0.8 * VEXT/FLEX
;
CL=15pF; edge=sharp
; pin out driver=strong
Input high voltage, class MPR
pads
V
V
V
IHMPR SR (0.73*VEX
-
-
Hysteresis active, AL
T/FLEX)-
0.25
1.6 4)
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage, class MPR
pads
ILMPR SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage, class
MPR pads
ILHMPR SR 0.8
1.7
Pad set-up time
t
SET_MPR CC -
-10
-
-
100
10
ns
Short circuit current Class MPR ISC SR
mA
absolute max value
(PSI5)
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
Data Sheet
4-198
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
Table 3-15 Class S
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
75
Input frequency
-
-
-
-
-
-
-
-
MHz
MHz
V
Hysteresis active
-
150
-
Hysteresis inactive
Input Hysteresis for S pad 1)
Pull-up current for S pad
HYSS CC
0.3
|30|
-
I
PUHS CC
-
µA
VIHmin
VILmax
VIHmin
VILmax
|107|
|100|
-
µA
Pull-down current for S pad
I
PDLS CC
-
µA
|46|
-350
µA
Input Leakage current Class S IOZS CC
350
nA
Analog Inputs with pull
down diagnostics
-150
-
-
-
150
nA
V
else
Input voltage high for S pad
Input voltage low for S pad
V
V
IHS SR
ILS SR
(0.73*VDD
M)-0.25
Hysteresis active
(0.52*VDD
M)-0.25
-
-
-
V
Hysteresis active
Input low threshold variation for VILSD SR
-50
50
mV
max. variation of 1ms;
VDDM=constant
S pad 2)
Input capacitance for S pad
Pad set-up time for S pad
C
INS CC
-
-
-
-
10
pF
ns
t
SETS CC
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VILSD is implemented to ensure J2716 specification. For details of dedicated pins please see AP32286 for details.
Table 3-16 Class I 5V
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
PORST pad only
150
-
Input Hysteresis for I pad 1)
HYSI CC
0.07 *
VEXT/FLEX
0.09 *
VEXT/FLEX
-
-
-
-
V
V
AL
0.075 *
TTL
VEXT/FLEX
Pull-up current for I pad
Data Sheet
I
PUHI CC
|30|
|43|
-
-
-
-
-
µA
µA
µA
V
V
V
IHmin; AL
-
IHmin; TTL
|107|
ILmax; AL and TTL
4-199
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-16 Class I 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
|100|
-
Pull-down current for I pad
I
PDLI CC
-
-
-
-
µA
µA
µA
nA
V
V
V
IHmin; AL and TTL
ILmax; AL
|46|
|21|
-150
-
ILmax; TTL
Input Leakage Current for I pad IOZI CC
150
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
2.03 2)
-
-
-
350
nA
V
else
Input high voltage for I pad
Input low voltage for I pad
V
V
IHI SR
-
-
Hysteresis active, TTL
(0.73*VEX
T/FLEX)-
0.25
V
Hysteresis active; AL;
not available for the
PORST pad
ILI SR
-
-
-
-
0.8 3)
V
V
Hysteresis active, TTL
(0.52*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low / high voltage for I pad VILHI CC
Pad set-up time for I pad SETI CC
1.85
-
-
-
3.0
V
Hysteresis inactive
t
100
ns
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VIHx = 0.27 * VEXT/FLEX + 0.545V
3) VILx = 0.17 * VEXT/FLEX
Table 3-17 Class I 3.3V
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
PORST pad only
100
-
Input Hysteresis for I pad 1)
HYSI CC
0.045 *
VEXT/FLEX
0.05 *
-
-
V
AL and TTL
VEXT/FLEX
Pull-up current for I pad
I
I
PUHI CC
|17|
|19|
-
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
µA
nA
V
V
V
V
V
V
IHmin; AL
-
IHmin; TTL
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for I pad
PDLI CC
-
|22|
|11|
-150
-
ILmax; TTL
Input Leakage Current for I pad IOZI CC
150
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
350
nA
else
Data Sheet
4-200
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-17 Class I 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for I pad
V
V
IHI SR
1.6 2)
-
-
-
-
V
V
Hysteresis active, TTL
(0.73*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low voltage for I pad
ILI SR
-
-
-
-
0.5 3)
V
V
Hysteresis active, TTL
(0.52*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low / high voltage for I pad VILHI CC
Pad set-up time for I pad SETI CC
1.1
-
-
-
1.9
V
Hysteresis inactive
t
100
ns
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VIHx = 0.27 * VEXT/FLEX + 0.545V
3) VILx = 0.17 * VEXT/FLEX
Table 3-18 Driver Mode Selection for LP Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Driver Setting
medium (LPm)
weak (LPw)
X
X
X
X
0
1
Table 3-19 Driver Mode Selection for MP / MP+ Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Driver Setting
X
0
0
Speed grade 1
Strong sharp edge
(MPss / MP+ss / MPRss)
X
0
1
Speed grade 2
Strong medium edge
(MPsm / MP+sm / MPRsm)
X
X
1
1
0
1
Speed grade 3
Speed grade 4
medium (MPm / MP+m / MPRm)
weak (MPw / MP+w / MPRw)
Data Sheet
4-201
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification3.3 V only Pads
3.6
3.3 V only Pads
Pad classes LP, MP and MP+ support both Automotive Level (AL) or TTL level (TTL) operation. Parameters are
defined for AL operation and degrade in TTL operation.
Table 3-20 Class A2
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input Hysteresis for A2 pad 1) HYSA2 CC 0.1 *
fIN SR
-
-
-
MHz
V
TTL;else
VDDP3
0.06 *
VDDP3
-
-
-
V
valid for P21.6 and
P21.7
Input Leakage current for A2
pad
I
OZA2 CC
-300
300
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-800
-
-
500
|100|
-
nA
else
Pull-up current for A2 pad
I
I
PUHA2 CC
-
µA
VIHmin
|25|
|23|
-
-
µA
VILmax
Pull-down current for A2 pad
PDLA2 CC
-
-
µA
VIHmin
-
|100|
325
µA
VILmax
On-Resistance for A2 pad,
weak driver 2)
RDSONA2W
CC
100
200
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-Resistance for A2 pad,
medium driver 2)
RDSONA2M
CC
40
20
-
70
35
-
100
50
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-Resistance for A2 pad,
strong driver 2)
Rise/fall time for A2 pad 3)
RDSONA2S
CC
PMOS/NMOS ;
I
OH=8mA; IOL=8mA
t
A2 CC
20+0.8*C ns
CL≤50pF; pin out
driver=weak
L
-
-
17.5+0.85 ns
CL≥50pF; CL≤200pF;
*CL
pin out driver=weak
-
-
12+0.16* ns
CL≤50pF; pin out
CL
driver=medium
-
-
11.5+0.17 ns
CL≥50pF; CL≤200pF;
*CL
pin out driver=medium
-
-
6+0.06*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=strong
-
-
5.5+0.07* ns
CL
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
0.0+0.12* ns
CL
CL≤50pF; edge=sharp
; pin out driver=strong
0.0+0.12* ns
CL
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
Data Sheet
4-202
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical Specification3.3 V only Pads
Table 3-20 Class A2 (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for A2 pad
Input low voltage for A2 pad
Pad set-up time for A2 pad
V
IHA2 SR
2.04 4)
-
-
V
TTL;valid for all A2
pads except
TMS/DAP1, TRST,
and TCK/DAP0
0.7 *
VDDP3
-
-
-
V
V
valid for TMS/DAP1,
TRST, and TCK/DAP0
V
ILA2 SR
-
0.8 5)
TTL;valid for all A2
pads except
TMS/DAP1, TRST,
and TCK/DAP0
-
-
0.3 *
VDDP3
V
valid for TMS/DAP1,
TRST, and TCK/DAP0
t
SETA2 CC
-
-
-
-
100
20
ns
%
Deviation of symmetry for rising SYM CC
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VDDP3
4) VIHx = 0.57 * VDDP3 - 0.03V
.
5) VILx = 0.25 * VDDP3 + 0.058V
Table 3-21 Driver Mode Selection for A2 Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
Strong sharp edge
Strong medium edge
medium
X
X
X
X
0
0
1
1
0
1
0
1
weak
Table 3-22 Driver Mode Selection for F Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Reduced Strong sharp edge
Reduced Strong medium edge
medium
weak
Data Sheet
4-203
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
3.7
High performance LVDS Pads (LVDSH)
This LVDS pad type is used for the high speed chip to chip communication inferface of the new TC 260 / 264 / 265
/ 267. It compose out of a LVDSH pad and a Class F pad.
This pad combination is always supplied by the 3.3V supply rail.
Table 3-23 Class F
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
-
Input frequency
Input Hysteresis for F pad 1)
fIN SR
-
-
-
MHz
V
HYSF CC 0.1 *
TTL
VDDP3
Input Leakage Current for F
pad
I
OZF CC
-1000
-1500
-300
-
-
-
1000
1500
300
nA
nA
nA
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.2 and P21.3; TJ =
150°C
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.2 and P21.3; TJ =
170°C
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.4 and P21.5
-2000
-3000
-600
-
-
-
2000
3000
600
nA
nA
nA
else; valid for P21.2
and P21.3; TJ = 150°C
else; valid for P21.2
and P21.3; TJ = 170°C
else; valid for P21.4
and P21.5
Pull-up current for F pad
I
I
PUHF CC
PDLF CC
|25|
-
-
-
µA
VIHmin
-
|100|
|100|
-
µA
VILmax
Pull-down current for class F
pads
-
-
µA
VIHmin
|25|
100
-
µA
VILmax
On resistance for F pad, weak RDSONFW
200
325
Ohm
PMOS/NMOS ;
driver 2)
CC
I
OH=0.5mA; IOL=0.5mA
On resistance for F pad,
medium driver 2)
RDSONFM
CC
40
70
50
100
80
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On resistance for F pad, strong RDSONFS CC 20
PMOS/NMOS ;
IOH=4mA; IOL=4mA
driver 2)
Data Sheet
4-204
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-23 Class F (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time for F pad 3)
t
rfF CC
-
-
-
-
-
-
20+0.8*C ns
CL≤50pF; pin out
driver=weak
L
-
-
-
-
17.5+0.85 ns
*CL
CL≥50pF; CL≤200pF;
pin out driver=weak
12+0.16* ns
CL
CL≤50pF; pin out
driver=medium
11.5+0.17 ns
*CL
CL≥50pF; CL≤200pF;
pin out driver=medium
7+0.16*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=reduced strong
-
-
-
-
-
-
6.5+0.17* ns
CL
CL≥50pF; CL≤200pF;
edge=meduim ; pin out
driver>reduced strong
4+0.16*C ns
CL≤50pF; edge=sharp
; pin out
driver=reduced strong
L
3.5+0.17* ns
CL
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=reduced strong
Input high voltage for F pad
Input low voltage for F pad
Pad set-up time for F pad
V
V
IHF SR
ILF SR
2.04 4)
-
-
-
-
-
V
TTL
TTL
-
-
-
0.8 5)
100
20
V
t
SETF CC
ns
%
Deviation of symmetry for rising SYM CC
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VDDP3
4) VIHx = 0.57 * VDDP3 - 0.03V
.
5) VILx = 0.25 * VDDP3 + 0.058V
CL = 2.5 pF for all LVDSH parameters.
Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
0.5
Output impedance
Rise time 1)
R0 CC
-
-
Ohm
ns
Vcm = 1.0 V and 1.4 V
t
rise20 CC
ZL = 100 Ohm ±5%
@2 pF
Fall time 1)
t
fall20 CC
-
-
0.5
ns
ZL = 100 Ohm ±5% @
2 pF
Output differential voltage
Data Sheet
V
OD CC
250
-
400
mV
RT = 100 Ohm ±5%
4-205
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Output voltage high
Output voltage low
V
V
OH CC
OL CC
-
-
1475
mV
RT = 100 Ohm ±5%
(400 mV/2) + 1275 mV
925
-
-
-
mV
mV
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
Output offset (Common mode) VOS CC
1125
1275
voltage
Input voltage range
VI SR
0
0
-
-
1600
2000
mV
mV
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±10%
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±20%
Input differential threshold
Delta output impedance
V
idth SR
-100
-
-
-
-
-
100
10
25
25
55
mV
%
Driver ground potential
difference < 925 mV
dR0 SR
-
Vcm = 1.0 V and 1.4 V
(mismatch Pd and Pn)
Change in VOS between 0 and dVOS CC
1
-
mV
mV
%
RT = 100 Ohm ±5%
Change in Vod between 0 and dVod CC
1
-
RT = 100 Ohm ±5%
Duty cycle
t
duty CC
45
1) Rise / fall times are defined for 20% - 80% of VOD
Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
140
250
1375
-
Output impedance
R0 CC
-
-
-
-
-
Ohm
mV
mV
mV
mV
Vcm = 1.0 V and 1.4 V
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
Output differential voltage
Output voltage high
Output voltage low
V
V
V
OD CC
OH CC
OL CC
150
-
1025
1125
Output offset (Common mode) VOS CC
1275
voltage
Input voltage range
VI SR
idth SR
825
-100
-
-
-
-
-
-
1575
100
25
mV
mV
mV
mV
%
Driver ground potential
difference < 50 mV
Input differential threshold
V
Driver ground potential
difference < 50 mV
Change in VOS between 0 and dVOS CC
1
RT = 100 Ohm ±5%
Change in Vod between 0 and dVod CC
1
-
25
RT = 100 Ohm ±5%
Duty cycle
t
duty CC
45
55
Data Sheet
4-206
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL) (cont’d)
Parameter Symbol Values
Typ.
Unit
Note / Test Condition
Min.
Max.
1)
V
OD Fall time
t
fall10 CC
-
-
0.5
ns
ns
ZL = 100 Ohm ±5% @
2pF
1)
VOD Rise time
t
rise10 CC
-
-
0.5
ZL = 100 Ohm ±5% @
2pF
1) Rise / fall times are defined for 10% - 90% of VOD
default after start-up = CMOS function
P
Htotal=5nH
Ctotal=3.5pF
Cext=2pF
LVDSH
Rin
IN
RT=100Ohm
Htotal=5nH
Cext=2pF
N
Ctotal=3.5pF
LVDSH _Input _Pad _Model .vsd
Figure 3-1 LVDSH pad Input model
Data Sheet
4-207
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMedium performance LVDS Pads (LVDSM)
3.8
Medium performance LVDS Pads (LVDSM)
This LVDS pad type is used for the medium speed chip to chip communication inferface of the new TC 260 / 264
/ 265 / 267. It compose out of a LVDSM pad and a MP pad.
This pad combination is always supplied by the 5V or 3.3V.
For the parameters of the MP pad please see Chapter 3.5.
Table 3-26 LVDSM
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
2.5
Output impedance
Fall time
RO CC
tF CC
100
-
Ohm
ns
Zload = 100 Ohm;
termination 100 Ohm
±1%
Rise time
tR CC
-
-
2.5
ns
Zload = 100 Ohm;
termination 100 Ohm
±1%
Pad set-up time
tSET_LVDS
CC
-
10
-
13
µs
Output Differential Voltage
Output voltage high
Output voltage low
Output Offset Voltage
V
V
V
V
OD CC
OH CC
OL CC
OS CC
250
-
400
1475
-
mV
mV
mV
mV
termination 100 Ohm
±1%
-
termination 100 Ohm
±1%
925
1125
-
termination 100 Ohm
±1%
-
1275
termination 100 Ohm
±1%
default after start-up = CMOS function
Data Sheet
4-208
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationVADC Parameters
3.9
VADC Parameters
VADC parameter are valid for VDDM = 4.5 V to 5.5 V.
This tables also covers the parameters for Class D pads.
Table 3-27 VADC
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Analog reference voltage 1)
Analog reference ground
V
V
V
AREF SR
VAGND
1.0
+
-
VDDM
0.05
+
+
V
V
AGND SR VSSM
-
-
VSSM
0.05
0.05
Analog input voltage range
Converter reference clock
AIN SR
VAGND
-
VAREF
20
V
f
ADCI SR
CONV CC
2
-
-
MHz
pC
Charge consumption per
conversion 2) 3)
Q
50
75
VAIN = 5 V, charge
consumed from
reference pin,
precharging disabled
-
-
-
-
-
10
22
-
pC
VAIN = 5 V, charge
consumed from
reference pin,
precharging enabled
Conversion time for 12-bit
result
t
t
C12 CC
(16 +
Includes sample time
and post calibration
STC) x
tADCI + 2 x
tVADC
Conversion time for 10-bit
result
C10 CC
(14 +
-
Includes sample time
Includes sample time
Includes sample time
STC) x
tADCI + 2 x
tVADC
Conversion time for 8-bit result tC8 CC
(12 +
-
STC) x
tADCI + 2 x
tVADC
Conversion time for fast
compare mode
t
CF CC
(4 + STC) -
x tADCI + 2
x tVADC
Broken wire detection delay
against VAGND
t
t
BWG CC
BWR CC
-
-
-
-
120
cycles Result below 10%
cycles Result above 80%
4)
Broken wire detection delay
-
60
5)
against VAREF
Input leakage at analog inputs IOZ1 CC
-350
350
nA
Analog Inputs overlaid
with class LP pads or
pull down diagnostics
-150
-4 6)
-
-
150
4 6)
nA
else
Total Unadjusted Error 1)
Data Sheet
TUE CC
LSB
12-bit resolution
4-209
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationVADC Parameters
Table 3-27 VADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
3
INL Error
EAINL CC
-3
-
-
-
-
-
LSB
LSB
LSB
LSB
pF
12-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
Gain Error 1)
DNL error 1)
Offset Error 1)
EAGAIN CC -3.5
EADNL CC -3
EAOFF CC -4
3.5
3
4
Total capacitance of an analog CAINT CC
-
30
input
Switched capacitance of an
analog input
CAINS CC
2
4
7
pF
Resistance of the analog input RAIN CC
path
-
-
-
-
1.5
1.8
kOhm else
kOhm valid for analog inputs
mapped to GPIOs
Switched capacitance of a
reference input
CAREFS CC
-
-
30
pF
RMS Noise 7)
ENRMS CC
OZ2 CC
-
0.5
-
0.8 6)8)
2
LSB
Positive reference VAREFx pin
I
-2
µA
µA
µA
µA
µA
µA
µA
µA
V
V
AREFx = VAREF1
AREF≤VDDMV;
;
;
;
;
leakage
TJ≤150°C
-3
-
-
-
-
-
-
-
3
V
V
AREFx = VAREF1
AREF≤VDDMV;
TJ>150°C
-4
4
V
V
AREFx = VAREF1
AREF>VDDMV;
TJ≤150°C
-7
7
V
V
AREFx = VAREF1
AREF>VDDMV;
TJ>150°C
AGNDx = VAGND1
AGND < VSSM ; TJ > 150
°C
AGNDx = VAGND1
AGND < VSSM ; TJ ≤ 150
°C
AGNDx = VAGND1
AGND ≥ VSSM ; TJ > 150
°C
AGNDx = VAGND1
AGND ≥ VSSM ; TJ ≤ 150
°C
Negative reference VAGNDx pin IOZ3 CC
leakage
-13
-7
13
7
V
V
;
V
V
;
-3
3
V
V
;
-2.5
2.5
V
V
;
Resistance of the reference
input path
CSD resistance 9)
R
R
AREF CC
CSD CC
-
-
-
-
1
kOhm
kOhm
28
Data Sheet
4-210
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationVADC Parameters
Table 3-27 VADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
35 + 8*VIN kOhm 0 V ≤ VIN ≤ 2.5 V
Resistance of the multiplexer
diagnostics pull-down device
R
R
R
MDD CC
MDU CC
PDD CC
25 + 1*VIN
-
-
-5 +
13*VIN
15 +
16*VIN
kOhm 2.5 V ≤ VIN ≤ VDDM
Resistance of the multiplexer
diagnostics pull-up device
45 - 6*VIN
-
90 -
16*VIN
kOhm 0 V ≥ VIN ≤ 2.5 V
40 - 4*VIN
-
-
65 - 6*VIN kOhm 2.5 V ≤ VIN ≤ VDDM
Resistance of the pull-down
test device 10)
-
0.3
kOhm
CSD voltage accuracy 11) 12)
dVCSD CC -
WU CC
-
-
10
12
%
Wakeup time
t
-
µs
1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor
1/k. VAREF must be decoupled with an external capacitor.
2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx
.
3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual.
4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 500 ms.
5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.
6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
7) This parameter is valid for soldered devices and requires careful analog board design.
8) Value is defined for one sigma Gauss distribution.
9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS
.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad
itself adds another 200-Ohm series resistance, when measuring through the pin.
11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.
12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current
of max. VAREF / 45 kOhm.
The following VADC parameter are valid for VDDM = 2.97 V to 4.5 V.
Table 3-28 VADC_33V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Analog reference voltage 1)
Analog reference ground
V
V
V
AREF SR
VAGND
1.0
+
-
VDDM
0.05
+
+
V
V
AGND SR VSSM
-
-
VSSM
0.05
0.05
Analog input voltage range
Converter reference clock
AIN SR
VAGND
-
-
VAREF
V
f
ADCI SR
2
20
MHz
Data Sheet
4-211
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Charge consumption per
conversion 2) 3)
QCONV CC
-
35
50
pC
VAIN = 3.3 V, charge
consumed from
reference pin,
precharging disabled
-
-
-
-
-
8
17
-
pC
VAIN = 3.3 V, charge
consumed from
reference pin,
precharging enabled
Conversion time for 12-bit
result
t
t
C12 CC
(16 +
Includes sample time
and post calibration
STC) x
tADCI + 2 x
tVADC
Conversion time for 10-bit
result
C10 CC
(14 +
-
Includes sample time
Includes sample time
Includes sample time
STC) x
tADCI + 2 x
tVADC
Conversion time for 8-bit result tC8 CC
(12 +
-
STC) x
tADCI + 2 x
tVADC
Conversion time for fast
compare mode
t
CF CC
(4 + STC) -
x tADCI + 2
x tVADC
Broken wire detection delay
against VAGND
t
t
BWG CC
BWR CC
-
-
-
-
120
cycles Result below 10%
cycles Result above 80%
4)
Broken wire detection delay
-
60
5)
against VAREF
Input leakage at analog inputs IOZ1 CC
-350
350
nA
Analog Inputs overlaid
with class LP pads or
pull down diagnostics
-150
-12 6)
-
-
150
12 6)
nA
else
Total Unadjusted Error 1)
TUE CC
EAINL CC
LSB
12-bit Resolution; TJ >
150 °C
-6 6)
-12
-5
-
-
-
-
-
6 6)
12
5
LSB
LSB
LSB
LSB
LSB
12-bit Resolution; TJ ≤
150 °C
INL Error
12-bit Resolution; TJ >
150 °C
12-bit Resolution; TJ ≤
150 °C
Gain Error 1)
EAGAIN CC -6
-5.5
6
12-bit Resolution; TJ >
150 °C
5.5
12-bit Resolution; TJ ≤
150 °C
Data Sheet
4-212
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DNL error 1)
Offset Error 1)
EADNL CC -4
EAOFF CC -6
-
-
4
6
LSB
LSB
12-bit resolution
12-bit Resolution; TJ >
150 °C
-5
-
5
LSB
pF
12-bit Resolution; TJ ≤
150 °C
Total capacitance of an analog CAINT CC
input
-
-
30
7
Switched capacitance of an
analog input
CAINS CC
2
-
4
-
pF
Resistance of the analog input RAIN CC
path
4.5
30
kOhm
pF
Switched capacitance of a
reference input
CAREFS CC
-
-
RMS Noise 7)
ENRMS CC
OZ2 CC
-
-
-
1.7 6)8)
6
LSB
µA
Positive reference VAREFx pin
I
-6
V
V
AREFx = VAREF1
AREF>VDDMV;
;
;
;
;
leakage
TJ>150°C
-3.5
-3
-
-
-
-
-
-
-
3.5
3
µA
µA
µA
µA
µA
µA
µA
V
V
AREFx = VAREF1
AREF>VDDMV;
TJ≤150°C
V
V
AREFx = VAREF1
AREF≤VDDMV;
TJ>150°C
-2
2
V
V
AREFx = VAREF1
AREF≤VDDMV;
TJ≤150°C
AGNDx = VAGND1
AGND < VSSM ; TJ > 150
°C
AGNDx = VAGND1
AGND < VSSM ; TJ ≤ 150
°C
AGNDx = VAGND1
AGND ≥ VSSM ; TJ > 150
°C
AGNDx = VAGND1
AGND ≥ VSSM ; TJ ≤ 150
°C
Negative reference VAGNDx pin IOZ3 CC
leakage
-12
-6.5
-3
12
6.5
3
V
V
;
V
V
;
V
V
;
-2
2
V
V
;
Resistance of the reference
input path
CSD resistance 9)
R
R
AREF CC
CSD CC
-
-
-
-
3
kOhm
kOhm
28
Data Sheet
4-213
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Resistance of the multiplexer
diagnostics pull-down device
R
MDD CC
25 + 3*VIN
-
40 +
12*VIN
kOhm 0 V ≤ VIN ≤ 1.667 V
0 + 18*VIN
-
-
0 + 18*VIN kOhm 1.667 V ≤ VIN ≤ VDDM
Resistance of the multiplexer
diagnostics pull-up device
R
R
MDU CC
60 -
12*VIN
120 -
kOhm 0 V ≤ VIN ≤ 1.667 V
kOhm 1.667 V ≤ VIN ≤ VDDM
kOhm
30*VIN
55 - 9*VIN
-
-
95 -
15*VIN
Resistance of the pull-down
test device 10)
PDD CC
-
0.9
CSD voltage accuracy 11) 12)
dVCSD CC -
WU CC
-
-
10
12
%
Wakeup time
t
-
µs
1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor
1/k. VAREF must be decoupled with an external capacitor.
2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx
.
3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual.
4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 500 ms.
5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.
6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
7) This parameter is valid for soldered devices and requires careful analog board design.
8) Value is defined for one sigma Gauss distribution.
9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS
.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad
itself adds another 200-Ohm series resistance, when measuring through the pin.
11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.
12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current
of max. VAREF / 45 kOhm.
A/D Converter
RSource
RAIN, On
VAIN
-
CExt
CAINT CAINS
CAINS
MCS05570
Figure 3-2 Equivalent Circuitry for Analog Inputs
Data Sheet
4-214
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDSADC Parameters
3.10
DSADC Parameters
The following DSADC parameter are valid for VDDM = 4.5 V to 5.5 V.
Table 3-29 DSADC
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
5
Analog input voltage range 1)
V
DSIN SR
0
0
-
-
V
V
single ended
10
differential;VDSxP -
VDSxN
Reference load current
I
REF SR
-
4.52)
7.8 2)
µA
per twin-modulator (1
or 2 channels)
Modulator clock frequency 3)
Gain error
f
MOD SR
10
-
-
-
-
20
1 4)
3.5 5)
0.2 6)
MHz
%
EDGAIN CC -1
-3.5 5)
-0.2
Calibrated once
Uncalibrated
%
%
calibrated; GAIN = 1;
MODCFG.INCFGx=01
DC offset error
EDOFF CC -5
-
5 6)
50
100 5)
mV
mV
mV
calibrated
-50
-100 5)7)
-
calibrated once
gain = 1; uncalibrated
05)7)
500
130
Common Mode Rejection Ratio EDCM CC
Input impedance 8)
200
-
R
DAIN CC
100
170
kOhm Exact value (±1%)
available in UCB
Signal-Noise Ratio 9) 10) 11) 12) SNR CC
80
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
kHz
fPB = 30 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
78
-
fPB = 50 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
70
-
fPB = 100 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
74
-
fPB = 100 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
76
-
fPB = 30 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
74
-
fPB = 50 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
Pass band
f
PB CC
10 13)
100
Output data rate fD =
f
PB * 3
Pass band ripple 10)
Output sampling rate
dfPB CC
fD CC
-1
-
-
1
%
30
330
kHz
Data Sheet
4-215
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDSADC Parameters
Table 3-29 DSADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-3
Max.
DC compensation factor
DCF CC
-
-
-
dB
µA
10-5 fD
Positive reference VAREF1 pin
I
OZ5 CC
-2
2
V
VAREFx = VVAREF1
VAREF ≤ VDDM ; TJ ≤
150 °C
VAREFx = VVAREF1
VAREF ≤ VDDM ; TJ >
150 °C
VAREFx = VVAREF1
VAREF > VDDM ; TJ ≤
150 °C
VAREFx = VVAREF1
VAREF > VDDM ; TJ >
150 °C
AGNDx = VAGND1
AGND > VSSM ; TJ ≤ 150
°C
AGNDx = VAGND1
AGND > VSSM ; TJ > 150
°C
AGNDx = VAGND1
AGND < VSSM ; TJ ≤ 150
°C
AGNDx = VAGND1
AGND < VSSM ; TJ > 150
;
leakage
V
-3
-
-
-
-
-
-
-
3
µA
µA
µA
µA
µA
µA
µA
V
V
;
-4
4
V
V
;
-7
7
V
V
;
Negative reference VAGND1 pin IOZ6 CC
leakage
-2.5
-3
2.5
3
V
V
;
V
V
;
-7
7
V
V
;
-13
13
V
V
;
°C
Stop band attenuation 10)
SBA CC
40
45
50
55
60
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
V
0.5 ... 1 fD
1 ... 1.5 fD
1.5 ... 2 fD
2 ... 2.5 fD
2.5 ... OSR/2 fD
Reference ground voltage
Positive reference voltage
V
V
AGND SR VSSM
-
VSSM
0.05
+
+
0.05
AREF SR
V
DDMnom * -
VDDM
V
0.9
0.05
Common mode voltage
accuracy
dVCM CC
-100
-
-
100
200
mV
mV
from selected voltage
Common mode hold voltage
deviation 14)
dVCMH CC -200
From common mode
voltage
Analog filter settling time
Modulator recovery time
t
t
AFSET CC
MREC CC
-
-
2
4
µs
µs
If enabled
3.5
5.5
After leaving overdrive
state
Data Sheet
4-216
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDSADC Parameters
Table 3-29 DSADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Modulator settling time 15)
t
MSET CC
-
1
-
µs
After switching on,
voltage regulator
already running
Spurious Free Dynamic Range SFDR CC 60
-
-
dB
V
CM = 2.2 V, DC
9)16)
coupled; VDDM = ±10%
1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external
common mode voltage. In this case the Amplitude is limited to VCM * 2.
2) When measuring at pin VAREF1, leakage/operating currents of the VADC must be added to IREF
3) All modulators must run on the same frequency.
.
4) The calibration sequence must be executed once after an Application Reset
5) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF
6) Recalibration needed in case of a temperature change > 20ºC
7) Systematic offset shift
8) The variation of the impedance between different channels is < 1.5%.
9) Derating factors:
-2 dB in standard-performance mode.
-3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
10) CIC3, FIR0, FIR1 filters enabled.
11) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM
(GAIN = 2).
12) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM
.
13) 10 kHz only reachable with 10 MHz modulator clock frequency.
14) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM
.
15) The modulator needs to settle after being switched on and after leaving the overdrive state.
16) SFDR = 20 * log(INL / 2N); N = amount of bits
The following DSADC parameter are valid for VDDM = 2.97 V to 3.63 V.
Table 3-30 DSADC_33V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
3.3
Analog input voltage range 1)
V
DSIN SR
0
0
-
-
V
V
single ended
6.6
differential;VDSxP -
VDSxN
Reference load current
I
REF SR
-
4.52)
6.9 2)
µA
per twin-modulator (1
or 2 channels)
Modulator clock frequency 3)
Gain error
f
MOD SR
10
-
-
-
-
20
MHz
%
EDGAIN CC -1.5
-10 5)
-0.3
1.5 4)
10 5)
0.3 6)
Calibrated once
Uncalibrated
%
%
calibrated; GAIN = 1;
MODCFG.INCFGx=01
DC offset error
Data Sheet
EDOFF CC -5
-
5 6)
mV
mV
mV
calibrated
-50
-100 5)
-
05)
50
100 5)
calibrated once
gain = 1; uncalibrated
4-217
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDSADC Parameters
Table 3-30 DSADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
100
Max.
-
Common Mode Rejection Ratio EDCM CC
Input impedance 7)
500
130
R
DAIN CC
170
kOhm Exact value (±1%)
available in UCB
Signal-Noise Ratio 8) 9) 10) 11)
SNR CC
45
63
69
68
74
66
72
-
-
dB
dB
dB
dB
dB
dB
kHz
fPB = 100kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
60
-
fPB = 100kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
60
-
fPB = 30kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
69
-
fPB = 30kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
55
-
fPB = 50kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
65
-
fPB = 50kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
Pass band
f
PB CC
10 12)
100
Output data rate fD =
f
PB * 3
Pass band ripple 9)
dfPB CC
fD CC
-1
30
-3
-6
-
-
-
-
1
%
Output sampling rate
DC compensation factor
330
kHz
dB
µA
DCF CC
-
10-5 fD
AREFx = VAREF1 ; VAREF
> VDDM ; TJ > 150 °C
AREFx = VAREF1 ; VAREF
> VDDM ; TJ ≤ 150 °C
AREFx = VAREF1 ; VAREF
≤ VDDM ; TJ > 150 °C
AREFx = VAREF1 ; VAREF
Positive reference VAREF1 pin
I
OZ5 CC
6
V
leakage
-3.5
-3
-
-
-
3.5
3
µA
µA
µA
V
V
-2
2
V
≤ VDDM ; TJ ≤ 150 °C
Data Sheet
4-218
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDSADC Parameters
Table 3-30 DSADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Negative reference VAGND1 pin IOZ6 CC
leakage
-2
-
-
-
-
2
µA
V
V
AGNDx = VAGND1
AGND ≥ VSSM ; TJ ≤ 150
°C
AGNDx = VAGND1
AGND ≥ VSSM ; TJ > 150
°C
AGNDx = VAGND1
AGND < VSSM ; TJ ≤ 150
°C
AGNDx = VAGND1
AGND < VSSM ; TJ > 150
;
-3
3
µA
µA
µA
V
V
;
-6.5
-12
6.5
12
V
V
;
V
V
;
°C
Stop band attenuation 9)
SBA CC
40
45
50
55
60
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
V
0.5 ... 1 fD
1 ... 1.5 fD
1.5 ... 2 fD
2 ... 2.5 fD
2.5 ... OSR/2 fD
Reference ground voltage
Positive reference voltage
V
V
AGND SR VSSM
-
VSSM
0.05
+
+
0.05
AREF SR
V
DDMnom * -
VDDM
V
0.9
0.05
Common mode voltage
accuracy
dVCM CC
-100
-
-
100
200
mV
mV
from selected voltage
Common mode hold voltage
deviation 13)
dVCMH CC -200
From common mode
voltage
Analog filter settling time
Modulator recovery time
t
t
AFSET CC
MREC CC
-
-
2
4
-
µs
µs
If enabled
3.5
After leaving overdrive
state
Modulator settling time 14)
t
MSET CC
-
1
-
µs
After switching on,
voltage regulator
already running
Spurious Free Dynamic Range SFDR CC 52
-
-
-
-
dB
dB
V
CM = 2.2 V, DC
coupled; VDDM = ±10%
CM = 2.2 V, DC
coupled; VDDM = ±5%
8)15)
60
V
1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external
common mode voltage. In this case the Amplitude is limited to VCM * 2.
2) When measuring at pin VAREF1, leakage/operating currents of the VADC must be added to IREF
3) All modulators must run on the same frequency.
.
4) The calibration sequence must be executed once after an Application Reset
5) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF
6) Recalibration needed in case of a temperature change > 20ºC.
7) The variation of the impedance between different channels is < 1.5%.
Data Sheet
4-219
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDSADC Parameters
8) Derating factors:
-2 dB in standard-performance mode.
-3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
9) CIC3, FIR0, FIR1 filters enabled.
10) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM
(GAIN = 2).
11) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM
.
12) 10 kHz bandwidth only with 10Mhz modulator clock frequency reachable
13) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM
.
14) The modulator needs to settle after being switched on and after leaving the overdrive state.
15) SFDR = 20 * log(INL / 2N); N = amount of bits
VCM
Gain
VOFFSET
130 kΩ
130 kΩ
=
Modu-
lator
Gain
MC_DSADC_MODULATORBLOCK
Figure 3-3 DSADC Analog Inputs
Data Sheet
4-220
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMHz Oscillator
3.11
MHz Oscillator
OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 8 MHz to 40 MHz crystals external
outside of the device. Support of ceramic resonators is also provided.
Table 3-31 OSC_XTAL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-25
4
Max.
25
Input current at XTAL1
Oscillator frequency
I
IX1 CC
-
-
µA
VIN>0V; VIN<VDDP3V
f
OSC SR
40
MHz
Direct Input Mode
selected
8
-
40
MHz
External Crystal Mode
selected
Oscillator start-up time 1)
t
OSCS CC
-
-
-
5 2)
ms
V
Input high voltage at XTAL1
V
IHBX SR
0.8
VDDP3
+
If shaper is bypassed
If shaper is bypassed
0.5
Input low voltage at XTAL1
Input voltage at XTAL1
V
ILBX SR
-0.5
-0.5
-
-
0.4
V
V
VIX SR
VDDP3
0.5
+
+
If shaper is not
bypassed
Input amplitude (peak to peak) VPPX SR
at XTAL1
0.3 *
VDDP3
-
-
VDDP3
1.0
V
V
If shaper is not
bypassed; fOSC
>
25MHz
0.4 *
VDDP3
VDDP3
1.0
+
If shaper is not
bypassed; fOSC
25MHz
≤
Internal load capacitor
Internal load capacitor
Internal load capacitor
Internal load capacitor
CL0 CC
CL1 CC
CL2 CC
CL3 CC
2
2.35
2.35
3.5
2.7
2.7
4
pF
pF
pF
pF
2
3
5.1
5.9
6.6
1) tOSCS is defined from the moment when VDDP3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDP3
.
The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended
and specified by crystal suppliers.
2) This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.
Note:It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
Data Sheet
4-221
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationBack-up Clock
3.12
Back-up Clock
The back-up clock provides an alternative clock source.
Table 3-32 Back-up Clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Back-up clock before trimming fBACKUT CC 75
Max.
125
100
100
100
MHz
kHz
V
V
V
EXT≥2.97V
EXT≥2.97V
EXT≥2.97V
Slow speed Back-up clock
Back-up clock after trimming
f
f
BACKSS CC 75
BACKT CC 97.5
125
102.5
MHz
Data Sheet
4-222
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationTemperature Sensor
3.13
Temperature Sensor
Table 3-33 DTS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
100
1
Measurement time
tM CC
-
-
-
µs
°C
Calibration reference accuracy TCALACC CC -1
calibration points @
TJ=-40°C and
TJ=127°C
Non-linearity accuracy over
temperature range
T
T
NL CC
SR SR
-2
-
2
°C
Temperature sensor range
-40
-
-
-
170
20
°C
µs
Start-up time after resets
inactive
tTSST SR
The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the
DTSSTAT register.
(3.1)
DTSSTATRESULT – (607)
Tj = ---------------------------------------------------------------------------
2, 13
Data Sheet
4-223
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower Supply Current
3.14
Power Supply Current
The total power supply current defined below consists of leakage and switching component.
Application relevant values are typically lower than those given in the following table and depend on the customer's
system operating conditions (e.g. thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
The real (realisic) power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
CPU0 = 80 MHz
SRI = fMAX = fCPU1 = 160 MHz
SPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 40 MHz
V
V
V
DD = 1.326 V
DDP3 = 3.366 V
EXT / FLEX = VDDM = 5.1 V
all cores are active including one lockstep core
the following peripherals are inactive: HSM, HSCT, Ethernet, PSI5, I2C, FCE, MTU, and 50% of the DSADC
channels
The max power pattern defines the following conditions:
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
SRI = fMAX = fCPU0 = 200 MHz
SPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 100 MHz
V
V
V
DD = 1.43 V
DDP3 = 3.63 V
EXT / FLEX = VDDM = 5.5 V
all cores and lockstep cores are active
all peripherals are active
Table 3-34 Power Supply
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of IDD 1.3 V core and
peripheral supply currents
I
DD CC
-
-
-
-
-
380 1)
mA
valid for Feature
Package D and DC;
max power pattern
-
-
-
198 1)
432
mA
mA
mA
valid for Feature
Package D and DC;
real power pattern
valid for Feature
Package DA; max
power pattern
250
valid for Feature
Package DA; real
power pattern
Data Sheet
4-224
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DD core current during active IDDPORST
-
-
-
-
-
-
-
-
60
mA
valid for Feature
Package D and DC;
TJ=125°C
power-on reset (PORST held CC
low)
-
-
-
-
-
-
112
103
160
154
216
38
mA
mA
mA
mA
mA
mA
valid for Feature
Package D and DC;
TJ=150°C
valid for Feature
Package DA;
TJ=125°C
valid for Feature
Package D and DC;
TJ=165°C
valid for Feature
Package DA;
TJ=150°C
valid for Feature
Package DA;
TJ=165°C
I
DD core current of CPU1 main IDDC10 CC
real power pattern
core with CPU1 lockstep core
inactive
I
DD core current of CPU1 main IDDC11 CC
core with lockstep core active
DD core current added by FFT IDDFFT CC
-
-
-
-
-
IDDC10
32
+
mA
mA
mA
real power pattern
I
40
FFT running at
200MHz
∑ Sum of 3.3 V supply currents IDDx3RAIL CC -
46 2)
real power pattern
without pad activity
I
DDFL3 Flash memory current
I
DDFL3 CC
-
-
-
-
33 3)
33 4)
mA
mA
flash read current
flash read current
while programming
Dflash
I
DDP3 supply current without
I
DDP3 CC
-
-
-
-
13 3)
27 5)
mA
mA
real power pattern;
incl. OSC & flash read
current
pad activity
incl. OSC current and
flash 3.3V
programming current
when using external
5V supply
-
-
31 4)
mA
incl. OSC current and
flash programming
current when using
3.3V supply only
Data Sheet
4-225
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DDP3 supply current for LVDSH IDDP3LVDSH
-
-
16
mA
mA
pads in LVDS mode
CC
Σ Sum of external and ADC
supply currents (incl.
I
I
EXTRAIL CC -
-
31
11
real power pattern
EXTFLEX+IDDM+IEXTLVDSM)
Sum of IEXT and IFLEX supply
I
EXT/FLEX CC -
-
mA
real power pattern;
PORST output
inactive.
current without pad activity
I
EXT supply current for LVDSM IEXTLVDSM
pads in LVDS mode CC
DDM supply current DDM CC
-
-
-
-
6 6)
14
mA
mA
real power pattern
I
I
real power pattern;
sum of currents of
DSADC and VADC
modules
-
-
-
-
12
mA
mA
current for DSADC
module only; 50%
DSADC channels
active.
32 7)
max power pattern; All
DSADC channels
active 100% time.
-
-
-
-
2
mA
mA
real pattern; current for
VADC only
7 8)
max power pattern; All
VADC converters are
active 100% time
Σ Sum of all currents (incl.
EXTRAIL+IDDx3RAIL+IDD)
I
DDTOT CC
-
-
-
-
275
327
mA
mA
valid for Feature
Package D and DC;
real power pattern
I
valid for Feature
Package DA; real
power pattern
Σ Sum of all currents with DC- IDDTOTDC3
-
-
-
-
-
-
180
mA
mA
µA
real power pattern;
9)
DC EVR13 regulator active
CC
V
EXT = 3.3V
real power pattern;
EXT = 5V
Σ Sum of all currents with DC- IDDTOTDC5
150
9)
DC EVR13 regulator active
CC
EVRSB CC
V
∑ Sum of all currents
I
150 10)
Standby RAM is
active. Power to
remaining domains
switched off. TJ =
25°C; VEVRSB = 5V
(STANDBY mode)
Data Sheet
4-226
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of all currents (SLEEP
mode)
I
SLEEP CC
-
-
15
mA
All CPUs in idle, All
peripherals in sleep,
f
SRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C; valid for Feature
Package D and DC
-
-
19
mA
All CPUs in idle, All
peripherals in sleep,
f
SRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C; valid for Feature
Package DA
Maximum power dissipation
PD CC
-
-
-
-
-
-
-
-
1090
614
mW
mW
mW
mW
valid for Feature
Package D and DC;
max power pattern
valid for Feature
Package D and DC;
real power pattern
1145
669
valid for Feature
Package DA; max
power pattern
valid for Feature
Package DA; real
power pattern
SCR 8-bit Standby Controller in ISCRSB CC
STANDBY Mode
-
-
25
-
-
µA
f
SYS_SCR = 100KHz;
TJ=25°C
SYS_SCR = 20MHz;
TJ=25°C
4
1
mA
mA
f
SCR 8-bit Standby Controller
CPU in IDLE mode
I
SCRIDLE CC -
-
1) The real pattern usecase is limited to 160 MHz in TC26x to limit the IDD current to less than 200 mA to ensure that internal
pass devices of EVR13 LDO can deliver the required IDD current. The max pattern IDD current can only be met with EVR13
LDO using external pass devices or EVR13 SMPS mode.
2) In case EVR33 is not used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited
to 500 mA if during power sequencing 3.3V is supplied before 5V by external regulator.
3) Realistic Pflash read pattern with 70% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. Dynamic Flash
Idle via FCON.IDLE is activated bringing a benefit of 8 mA. A common decoupling capacitor of atleast 100nF for
(VDDFL3+VDDP3) is used. Dflash read current is also included. Flash read current is predominantly drawn from VDDFL3 pin and
a minor part drawn from the neighbouring VDDP3 pin.
4) Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Dynamic Flash
Idle via FCON.IDLE is activated bringing a benefit of 8 mA. Erase currents of the corresponding flash modules are less
than the respective programming currents at VDDP3 pin. Programming and erasing flash may generate transient current
spikes of up to x mA for maximum x us which is handled by the decoupling and buffer capacitors. This parameter is relevant
for external power supply dimensioning and not for thermal considerations.
5) In addition to the current specified, upto 4 mA is additionally drawn at VEXT supply in burst programming mode with 5V
external supply. Erase currents of the corresponding flash modules are less than the respective programming currents at
V
DDP3 supply. This parameter is relevant for external power supply dimensioning and not for thermal considerations.
Data Sheet
4-227
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower Supply Current
6) The current consumption is for 1 pair of LVDSM differential pads (4 pins).
7) The current consumption is for 6 DS channels with standard performance (MCFG=11b). A single DS channel instance
consumes 6-8 mA.
8) A single converter instance of VADC unit consumes 2 mA.
9) The total current drawn from external regulator is estimated with 72% EVR13 SMPS regulator Efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and
IDDM
.
10) Current at VEVRSB supply pin during normal RUN mode is less than 5 mA at TJ =150 °C. The transition between RUN mode
to STANDBY mode has a duration of less than 100us during which the current is higher but is less than 8 mA at TJ =150
°C. Once STANDBY mode is entered with only Standby RAM active the current is less than 5mA at TJ = 150 °C. It is
recommended to have atleast 100 nF decoupling capacitor at this pin. The standby current indicated is solely drawn from
VEVRSB pin.
3.14.1
Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts:
•
•
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic current consumption
depends of the configured clocking frequencies and the software application executed. These two parts needs to
be added in order to get the rail current consumption.
Valid for Feature Package D and DC products:
(3.2)
mA
0, 0255 × T
--------
C
I
= 0, 741
= 2, 86
× e
[C]
J
0
(3.3)
mA
--------
0, 0244 × T
I
× e
[C]
J
0
C
Valid for Feature Package DA products:
(3.4)
(3.5)
mA
--------
0, 02483 × T
I
= 0, 99
× e
[C]
J
0
C
mA
--------
0, 02308 × T
I
= 4, 8
× e
[C]
J
0
C
Function 2 defines the typical static current consumption and Function 3 defines the maximum static current
consumption. Both functions are valid for VDD = 1.326 V.
Data Sheet
4-228
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
3.15
Power-up and Power-down
External Supply Mode
3.15.1
5 V & 1.3 V supplies are externally supplied. 3.3V is generated internally by EVR33.
•
External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Voltage Ramp-up from a residual threshold (Eg : up to 1 V) should also lead to a normal
startup of the device.
•
The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-4 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supplies
ramp up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR33 regulator is initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR33 regulator
has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge.
Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset
thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
4-229
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
4
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
VDD (externally supplied )
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDDP3 (internally generated
by EVR33)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
Basic Supply & Clock
Infrastructure
EVR33 Ramp-up Phase
Firmware Execution
User Code Execution
fCPU=100MHz default
on firmware exit
Power Ramp-down phase
Startup_Diag_1 v 0.1
Figure 3-4 External Supply Mode - 5 V and 1.3 V externally supplied
Data Sheet
4-230
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
3.15.2
Single Supply Mode
5 V single supply mode. 1.3 V & 3.3 V are generated internally by EVR13 & EVR33.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-5 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR13 and EVR33 regulators are initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 and EVR33
regulators have ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST
rising edge. Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset
thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
4-231
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
4
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDD
(internally generated
by EVR13)
1. 33 V
1.30
V
1. 17 V
Primary Reset Threshold
0 V
VDDP3
(internally generated
by EVR33)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
EVR13 & EVR 33 Ramp-up
Basic Supply & Clock
Infrastructure
User Code Execution
Firmware Execution
Power Ramp-down phase
Phase
fCPU=100MHz default
on firmware exit
Startup_Diag_2 v 0.1
Figure 3-5 Single Supply Mode - 5 V single supply
Data Sheet
4-232
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
3.15.3
External Supply Mode
All supplies, namely 5 V, 3.3 V & 1.3 V, are externally supplied.
•
•
External supplies VEXT ,, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s).
The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-6 is enumerated below
–
T1 refers to the point in time when all supplies are above their primary reset thresholds and basic clock
infrastructure is available. The supply mode is evaluated based on the HWCFG [0:2] pins. PORST (output)
is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated.
–
–
T2 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T3 refers to the point in time during the Ramp-down phase when atleast one of the externally provided
supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
4-233
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
VDD (externally supplied )
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
VDDP3
(externally supplied)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
T0
T1
T2
T3
Basic Supply & Clock
Infrastructure
User Code Execution
fCPU=100 MHz default
on firmware exit
Firmware Execution
Power Ramp-down phase
Startup_Diag_3 v 0.1
Figure 3-6 External Supply Mode - 5 V, 3.3 V & 1.3 V externally supplied
Data Sheet
4-234
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
3.15.4
Single Supply Mode
3.3 V single supply mode. 1.3 V is generated internally by EVR13.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V or 3.3 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-7 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR13 regulator is initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 regulator
has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge.
Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V or 3.3 V) drop below their respective primary under-voltage reset thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
4-235
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPower-up and Power-down
VEXT
0
1
2
3
4
(externally supplied )
&
VDDP3 (externally
supplied )
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDD (internally generated
by EVR 13)
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
Basic Supply & Clock
Infrastructure
User Code Execution
fCPU=100MHz default
on firmware exit
EVR13 Ramp-up Phase
Firmware Execution
Power Ramp-down phase
Startup_Diag_4 v 0.1
Figure 3-7 Single Supply Mode - 3.3 V single supply
Data Sheet
4-236
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationReset Timing
3.16
Reset Timing
Table 3-35 Reset Timings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Application Reset Boot Time 1) tB CC
-
-
350 2)
µs
operating with max.
frequencies.
System Reset Boot Time
Power on Reset Boot Time 3)
t
t
BS CC
BP CC
-
-
-
-
1 2)
2.5
ms
ms
dV/dT=1V/ms.
including EVR ramp-
up and Firmware
execution time
-
-
-
1.1 2)
ms
µs
Firmware execution
time; without EVR
operation (external
supply only)
Minimum PORST hold time
incase of power fail event
issued by EVR primary monitor
t
EVRPOR CC 10
-
EVR start-up or ramp-up time tEVRstartup
-
-
-
1
-
ms
ms
dV/dT=1V/ms. EVR13
and EVR33 active
CC
Minimum PORST active hold
time after power supplies are
stable at operating levels 4)
t
POA CC
1
Configurable PORST digital
filter delay in addition to analog
pad filter delay
t
PORSTDF CC 600
-
1200
ns
HWCFG pins hold time from
ESR0 rising edge
t
t
HDH CC
HDS CC
16 / fSPB
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
HWCFG pins setup time to
ESR0 rising edge
0
-
Ports inactive after ESR0 reset tPI CC
active
-
8/fSPB
Ports inactive after PORST
reset active 5)
t
t
t
t
PIP CC
POH SR
POS SR
SCR CC
-
150
Hold time from PORST rising
edge
150
0
-
-
Setup time to PORST rising
edge
SCR reset boot time
-
-
-
-
300
300
-
µs
µs
µs
User Mode 0
User Mode 1
-
13.3
WDT double bit ECC,
soft reset
Data Sheet
4-237
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationReset Timing
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when
the first user instruction has entered the CPU pipeline and its processing starts.
2) The timing values assumes programmed BMI with ESR0CNT inactive.
3) The duration of the boot time is defined by all external supply voltages are inside there operation condictions and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
4) The regulator that supplies VEXT should ensure that VEXT is in the operational region before PORST is externally released
by the regulator. Incase of 5V nominal supply, it should be ensured that VEXT > 4V before PORST is released. Incase of
3.3V nominal supply , it should be ensured that VEXT > 3V before PORST is released. The additional minimum PORST hold
time is required as an additional mechanism to avoid consecutive PORST toggling owing to slow supply slopes or residual
supply ramp-ups. It is also required to activate external PORST atleast 100us before power-fail is recognised to avoid
consecutive PORST toggling on a power fail event.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
VDDPPA
VDDPPA
VDDP
VDD
VDDPR
tPOA
tPOA
Warm
PORST
ESR0
Cold
t PI
tPI
tPIP
Tristate Z / pullup H
Programmed
Z / H
Programmed
Z / H
Programmed
Pads
Pad-
state
undefined
Pad-
state
undefined
tPOS
tPOS
tPOH
tPOH
TRST
TESTMODE
tHDH
tHDH
config
tHDA
tHDH
config
tHDA
HWCFG
power -on config
reset_beh_aurix
Figure 3-8 Power, Pad and Reset Timing
Data Sheet
4-238
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEVR
3.17
EVR
Table 3-36 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
4
Max.
5.50
3.63
Input voltage range 1)
VIN SR
-
V
V
pass device=on chip
pass device=on chip
Output voltage operational
range including load/line
regulation and aging incase of
LDO regulator
V
V
OUT CC
2.97
3.3
Output VDDx3 static voltage
accuracy after trimming and
aging without dynamic load/line
Regulation incase of LDO
regulator.
OUTT CC
3.225
3.3
3.375
V
pass device=on chip
Output buffer capacitance on
VOUT
C
OUT CC
-
-
1
-
-
µF
V
pass device=on chip
2)
Primary Undervoltage Reset
V
RST33 CC
3.0
by reset release before
EVR trimming on
supply ramp-up.
3)
threshold for VDDx3
Startup time
External VIN supply ramp 4)
t
STR CC
-
-
-
1000
50
µs
pass device=on chip
dVin/dT
1
V/ms pass device=on chip
SR
Load step response
Line step response
dVout/dIout -
CC
-
-
-
240
-
mV
mV
mV
dI=-70mA/20ns;
Tsettle=20us; pass
device=on chip
-240
dI=50mA/20ns;
Tsettle=100us; pass
device=on chip
dVout/dVin -20
20
dV/dT=1V/ms; pass
CC
device=on chip
1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device
operation.
2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the
resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
3) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold.
This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to
voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated
internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher
voltage of 3.0V at the VDDP3 pin.
4) EVR robust against residual voltage ramp-up starting between 0-1 V.
Data Sheet
4-239
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEVR
Table 3-37 1.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input voltage range 1)
VIN SR
2.97
-
5.5
V
VIN≥; pass device=on
chip
2.97
1.17
-
5.5
V
V
pass device=off chip
Output voltage operational
range including load/line
regulation and aging incase of
LDO regulator
V
V
OUT CC
1.3
1.43
VIN≥; pass device=on
chip
1.17
1.3
1.3
1.43
V
V
pass device=off chip
Output VDD static voltage
accuracy after trimming without
dynamic load/line regulation
with aging incase of LDO
regulator.
OUTT CC
1.275
1.325
VIN≥; pass device=on
chip
1.275
1.4
1.3
2.2
1.325
3
V
pass device=off chip
Output buffer capacitance on
C
OUT CC
µF
On chip pass device
usage restricted to IDD
2)
VOUT
< 200mA. If IDD
>
200mA, off chip pass
device to be used.;
VIN≥; pass device=on
chip
3
-
4.7
-
6.3
µF
V
pass device=off chip
Primary undervoltage reset
threshold for VDD
V
RST13 CC
1.17
VIN≥; pass device=on
chip
3)
-
-
1.17
V
by reset release before
EVR trimming on
supply ramp-up. pass
device=off chip
Startup time
t
STR CC
-
-
1000
µs
µs
VIN≥; pass device=on
chip
-
-
-
1000
50
pass device=off chip
External VIN supply ramp 4)
dVin/dT
1
V/ms VIN≥; pass device=on
SR
chip
-
1
50
V/ms pass device=off chip
Data Sheet
4-240
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEVR
Table 3-37 1.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Load step response
dVout/dIout -
CC
-
-
-
-
100
mV
mV
mV
mV
dI=-125mA;
Tsettle=20µs; VIN≥;
pass device=on chip
-
100
dI=-150mA;
Tsettle=20µs; pass
device=off chip
-100
-
-
dI=100mA;
Tsettle=20µs; pass
device=off chip
-100
dI=75mA;
Tsettle=20µs; VIN≥;
pass device=on chip
Line step response
dVout/dVin -10
CC
-
-
10
10
mV
mV
dV/dT=1V/ms; VIN≥;
pass device=on chip
-10
dV/dT=1V/ms; pass
device=off chip
1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device
operation.
2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the
resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
3) The reset release on supply ramp-up is delayed by a time duration 30-60 µs after reaching undervoltage reset threshold.
This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to
voltage drop/current jumps when reset is released.The reset limit of 1,17V at pin is for the case with 1.3V generated
internally from EVR13. In case the 1.3V supply is provided externally, the bondwire drop will cause a reset at a higher
voltage of 1.18V at the VDD pin.
4) EVR robust against residual voltage ramp-up starting between 0-1 V.
Table 3-38 Supply Monitoring
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
EXT primary undervoltage
VEXTPRIUV
SR
2.86
2.92
2.90
1.15
5.0
2.97
V
V
EXT = Undervoltage
monitor accuracy after
trimming 1)
Reset Threshold
VDDP3 primary undervoltage
VDDP3PRIUV 2.86
SR
2.97
1.17
5.1
V
V
V
V
DDP3 = Undervoltage
monitor accuracy after
trimming
Reset Threshold
1)
VDD primary undervoltage
VDDPRIUV
SR
1.13
VDD = Undervoltage
Reset Threshold
monitor accuracy after
trimming
1)
VEXT secondary supply monitor VEXTMON CC 4.9
SWDxxVAL VEXT
monitoring
accuracy
threshold=5V=DBh
Data Sheet
4-241
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEVR
Table 3-38 Supply Monitoring (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
DDP3 secondary supply
VDDP3MON
CC
3.23
3.30
1.30
-
3.37
V
EVR33xxVAL VDDP3
monitoring
threshold=3.3V=91h
monitor accuracy
VDD secondary supply monitor VDDMON CC 1.27
1.33
1.8
V
EVR13xxVAL VDD
monitoring
threshold=1.3V=E4h
accuracy
EVR primary and secondary
monitor measurement latency
for a new supply value
t
EVRMON CC -
µs
after trimming
1) The monitor tolerances constitute the inherent variation of the bandgap and ADC over process, voltage and temperature
operational ranges. The xxxPRIUV parameters are device individually tested in production with ±1% tolerance about the
min and max xxxPRIUV limits. In TQFP100 and QFP80 pin packages, VDDPRIUV is not tested as HWCFG2 pin is absent.
Table 3-39 EVR13 SMPS External components
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
29.7
13.5
50
External output capacitor value COUTDC SR 15.4
22
10
-
µF
µF
I
I
DDDC=1A
1)
6.5
DDDC=400mA
External output capacitor ESR CDC_ESR SR -
mOhm f≥0.5MHz; f≤10MHz
-
-
100
13.5
9.18
50
Ohm
µF
f=10Hz
External input capacitor value 1) CIN SR
6.5
4.42
-
10
6.8
-
I
I
DDDC=1A
µF
DDDC=400mA
External input capacitor ESR
External inductor value 2)
External inductor ESR
C
IN_ESR SR
mOhm f≥0.5MHz; f≤10MHz
-
-
100
4.29
6.11
0.2
Ohm
µH
f=100Hz
L
DC SR
2.31
3.29
3.3
4.7
-
f
f
DCDC=1.5MHz
DCDC=1MHz
µH
L
DC_ESR SR -
LL SR
Ohm
V
P + N-channel MOSFET logic
level
V
-
-
2.5
P + N-channel MOSFET drain |VBR_DS| SR -
-
7
V
source breakdown voltage
P + N-channel MOSFET drain RON SR
source ON-state resistance
-
-
-
-
-
150
mOhm IDDDC=1A;VGS=2.5V ;
TA=25°C
-
200
mOhm IDDDC=400mA;VGS=2.5
V ; TA=25°C
P + N-channel MOSFET Gate Qac SR
Charge
4
8
-
-
nC
I
DDDC=1A; MOS-
VGS=5V
DDDC=400mA; MOS-
VGS=5V
nC
I
Data Sheet
4-242
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEVR
Table 3-39 EVR13 SMPS External components (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
External MOSFET
commutation time
tc SR
10
30
40
ns
V
configurable
N-channel MOSFET reverse
diode forward voltage
V
RDN SR
-
0.8
-
1) Capacitor min-max range represent typical ±35% tolerance including DC bias effect. The trace resistance from the
capacitor to the supply or ground rail should be limited to 25 mOhm.
2) External inductor min-max range represent typical ±30% tolerance at a DC bias current of 100mA.
Table 3-40 EVR13 SMPS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2.97
1.17
Max.
5.5
Input VEXT Voltage range
VIN SR
-
-
V
V
SMPS regulator output voltage VDDDC CC
range including load/line
regulation and aging 1)
1.43
V
DD≥2.97V; VDD≤5.5V;
I
DDDC≥1mA; IDDDC≤1A
SMPS regulator static voltage
output accuracy after trimming
without dynamic load/line
Regulation with aging. 2)
V
DDDCT CC 1.275
1.3
1.325
V
V
DD≥2.97V; VDD≤5.5V;
I
DDDC≥1mA; IDDDC≤1A
Programmable switching
frequency
f
DCDC CC
0.4
-
-
-
2.0
2%
15
MHz
MHz
mV
Switching frequency
modulation spread
∆fDCSPR CC -
Maximum ripple at IMAX (peak- ∆VDDDC CC -
VDD≥2.97V; VDD≤5.5V;
to-peak) 3)
I
I
DDDC≥300mA;
DDDC≤1A
No load current consumption of IDCNL CC
SMPS regulator
-
5
-
10
25
mA
mV
fDCDC=1MHz
SMPS regulator load transient dVout/dIout -25
response CC
dI < 200mA ;
DCDC=1MHz; tr=0.1us;
f
tf=0.1us; VDDDC=1.3V
-65
-
-
-
65
1
mV
A
dI < 400mA ;
f
DCDC=1MHz; tr=0.1us;
tf=0.1us; VDDDC=1.3V
Maximum output current of the IMAX SR
regulator
limited by thermal
constraints and
component choice
Data Sheet
4-243
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEVR
Table 3-40 EVR13 SMPS (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SMPS regulator efficiency
n
DC CC
-
85
-
%
VIN=3.3V;
I
f
DDDC=300mA;
DCDC=1MHz
VIN=5V; IDDDC=400mA;
DCDC=1.5MHz
VIN=5V; IDDDC=400mA;
DCDC=1MHz
-
-
75
80
-
-
%
%
f
f
1) Incase of SMPS mode, It shall be ensured that the VDD output pin shall be connected on PCB level to all other VDD Input
pins.
2) Incase of fSRI running with max frequency, it shall be ensured that the VDD operating range is limited to 1.235V upto 1.430V.
The DCDC may be configured in this case with a nominal voltage of 1.33V±7.5%. The static accuracy and regulation
parameter ranges remain also valid for this case.
3) If frequency spreading (SDFREQSPRD = 1) is activated, an additional ripple of 1% need to be considered.
Data Sheet
4-244
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPhase Locked Loop (PLL)
3.18
Phase Locked Loop (PLL)
Table 3-41 PLL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
PLLBASE CC 80
Max.
360
800
24
PLL base frequency
VCO frequency range
VCO Input frequency range
Modulation Amplitude
Peak Period jitter
f
f
f
150
MHz
MHz
MHz
%
VCO SR
REF CC
400
8
-
-
-
-
-
-
MA CC
DP CC
0
2
-200
-5
200
5
ps
Peak Accumulated Jitter
Total long term jitter
DPP CC
ns
without modulation
JTOT CC
-
11.5
ns
including modulation;
MA ≤ 1%
System frequency deviation
f
SYSD CC
-
-
0.01
5.4
%
with active modulation
Modulation variation frequency fMV CC
PLL lock-in time tL CC
2
3.6
-
MHz
µs
11.5
200
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
4-245
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationERAY Phase Locked Loop (ERAY_PLL)
3.19
ERAY Phase Locked Loop (ERAY_PLL)
Table 3-42 PLL_ERAY
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
PLL Base Frequency of the
ERAY PLL
fPLLBASE_ERA 50
Y CC
200
320
MHz
MHz
MHz
VCO frequency range of the
ERAY PLL
fVCO_ERAY
400
-
-
480
24
SR
VCO input frequency of the
ERAY PLL
f
REF SR
16
Accumulated_Jitter
DP CC
DPP CC
-0.5
-0.8
-
-
0.5
0.8
ns
ns
Accumulated jitter at SYSCLK
pin
PLL lock-in time
tL CC
5.6
-
200
µs
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
4-246
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationAC Specifications
3.20
AC Specifications
All AC parameters are specified for the complette operating range defined in Chapter 3.4 unless otherwise noted
in colum Note / test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FLEX / VDDP3
90%
90%
10%
10%
VSS
tr
tf
rise_fall
Figure 3-9 Definition of rise / fall times
VEXT/FLEX / VDDP3
Timing
Reference
Points
VEXT/FLEX /VDDP3
V
EXT /FLEX / VDDP3
2
2
VSS
timing_reference
Figure 3-10 Time Reference Point Definition
Data Sheet
4-247
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationJTAG Parameters
3.21
JTAG Parameters
The following parameters are applicable for communication through the JTAG debug interface. The JTAG module
is fully compliant with IEEE1149.1-2000.
Table 3-43 JTAG
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
25
10
10
-
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
TCK low time
-
TCK clock rise time
TCK clock fall time
4
4
-
-
TDI/TMS setup to TCK rising
edge
6.0
TDI/TMS hold after TCK rising t7 SR
6.0
-
-
ns
edge
TDO valid after TCK falling
edge (propagation delay) 1)
t8 CC
3.0
-
-
-
-
-
ns
ns
ns
CL≤20pF
CL≤50pF
16
-
TDO hold after TCK falling
edge 1)
t
18 CC
2
TDO high impedance to valid t9 CC
-
-
-
-
17.5
17
ns
ns
CL≤50pF
CL≤50pF
from TCK falling edge 1)2)
TDO valid output to high
impedance from TCK falling
edge 1)
t10 CC
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
t1
0.9 VDDP
0.1 VDDP
0.5 VDDP
t5
t4
t2
t3
MC_JTAG_TCK
Figure 3-11 Test Clock Timing (TCK)
Data Sheet
4-248
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationJTAG Parameters
TCK
TMS
TDI
t6
t7
t6
t7
t9
t8
t10
TDO
t18
MC_JTAG
Figure 3-12 JTAG Timing
Data Sheet
4-249
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDAP Parameters
3.22
DAP Parameters
The following parameters are applicable for communication through the DAP debug interface.
Table 3-44 DAP
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DAP0 clock period
DAP0 high time
t
t
t
t
11 SR
12 SR
13 SR
14 SR
6.25
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
2
2
-
-
DAP0 low time
-
DAP0 clock rise time
1
2
1
2
-
f=160MHz
f=80MHz
f=160MHz
f=80MHz
-
DAP0 clock fall time
t
15 SR
-
-
DAP1 setup to DAP0 rising
edge
t
t
t
16 SR
17 SR
19 CC
4
DAP1 hold after DAP0 rising
edge
2
-
-
ns
DAP1 valid per DAP0 clock
period 1)
3
-
-
-
-
-
-
ns
ns
ns
CL=20pF; f=160MHz
CL=20pF; f=80MHz
CL=50pF; f=40MHz
8
10
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VDDP
0.1 VDDP
0.5 VDDP
t15
t14
t12
t13
MC_DAP0
Figure 3-13 Test Clock Timing (DAP0)
DAP0
t16
t17
DAP1
MC_DAP1_RX
Figure 3-14 DAP Timing Host to Device
Data Sheet
4-250
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationDAP Parameters
t11
DAP1
t19
MC_DAP1_TX
Figure 3-15 DAP Timing Device to Host (DAP1 and DAP2 pins)
Note:The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
Data Sheet
4-251
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationASCLIN SPI Master Timing
3.23
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC 260 / 264 / 265 / 267, for 5V power supply.
Note:Pad asymmetry is already included in the following timings.
Table 3-45 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-3
3
0 < CL < 50pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-7
5
-
-
-
-
6
35
-
ns
ns
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
CL=25pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
28
-6
CL=25pF
MRST hold from ASCLKO
latching edge
-
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-46 Master Mode MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-2
3.5+0.035 ns
0 < CL < 200pF
2)
* CL
MTSR delay from ASCLKO
shifting edge
t
t
t
51 CC
510 CC
52 SR
-7
-7
-
-
6
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
6
CL=25pF
MRST setup to ASCLKO
latching edge
30
33 3)
-
-
-
-
ns
ns
CL=25pF, else
CL=25pF, for P14.2,
P14.4, and P15.1
MRST hold from ASCLKO
latching edge
t
53 SR
-5
-
-
ns
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
3) Please note that these pins didn't support the hystereses inactive feature.
Data Sheet
4-252
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationASCLIN SPI Master Timing
Table 3-47 Master Mode MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
4+0.04 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-11
-11
60
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-10
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-48 Master Mode medium output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-8
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
4+0.04 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-20
-20
70
-
-
-
-
15
20
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-10
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-49 Master Mode weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
1000
-30
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
30+0.15 * ns
0 < CL < 200pF
2)
CL
Data Sheet
4-253
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationASCLIN SPI Master Timing
Table 3-49 Master Mode weak output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-75
-
-
-
-
75
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
-65
510
-50
65
-
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
t50
ASCLKO
t51
t51
t500
MTSR
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-16 ASCLIN SPI Master Timing
Data Sheet
4-254
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationASCLIN SPI Master Timing
3.24
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC 260 / 264 / 265 / 267, for 3.3V power supply, Medium
Performance pads, strong sharp edge (MPss), CL=25pF.
Note:Pad asymmetry is already included in the following timings.
Table 3-50 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-5
5
0 < CL < 50pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-12
0
-
-
-
-
12
60
-
ns
ns
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
CL=25pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
50
-5
CL=25pF
MRST hold from ASCLKO
latching edge
-
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-51 Master Mode MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-5
7+0.07 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-12
-12
50
-5
-
-
-
-
12
12
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
4-255
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationASCLIN SPI Master Timing
Table 3-52 Master Mode MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-5
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
9+0.06 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-19
-19
100
-13
-
-
-
-
17
17
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-53 Master Mode medium output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ASCLKO clock period 1)
t
50 CC
400
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
-6-0.07 *
CL
6+0.07 * ns
CL
0 < CL < 200pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-33
-35
120
-13
-
-
-
-
25
35
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-54 Master Mode weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2000
-110
Max.
-
ASCLKO clock period 1)
t
50 CC
-
-
ns
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
150
0 < CL < 200pF
2)
Data Sheet
4-256
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationASCLIN SPI Master Timing
Table 3-54 Master Mode weak output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-170
-
-
-
-
170
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
-170
510
-40
170
MRST setup to ASCLKO
latching edge
-
-
MRST hold from ASCLKO
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-55 Master Mode A2ss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
-3
3
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-4
-5
17
0
-
-
-
-
4
4
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-56 Master Mode A2sm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
-4
4
2)
MTSR delay from ASCLKO
shifting edge
t
t
51 CC
-8
-8
-
-
6
9
ns
ns
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
510 CC
Data Sheet
4-257
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationASCLIN SPI Master Timing
Table 3-56 Master Mode A2sm output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to ASCLKO
latching edge
t
t
52 SR
53 SR
26
-
-
ns
ns
CL=50pF
CL=50pF
MRST hold from ASCLKO
latching edge
0
-
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
t50
ASCLKO
t51
t51
t500
MTSR
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-17 ASCLIN SPI Master Timing
Data Sheet
4-258
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
3.25
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC 260 / 264 / 265 / 267, for 5V pad power supply.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
•
•
LVDSM output pads,LVDSH input pad, master mode, CL=25pF
Medium Performance Plus Pads (MP+):
–
–
–
–
strong sharp edge (MP+ss), CL=25pF
strong medium edge (MP+sm), CL=50pF
medium edge (MP+m), CL=50pF
weak edge (MP+w), CL=50pF
•
•
Medium Performance Pads (MP):
–
–
strong sharp edge (MPss), CL=25pF
strong medium edge (MPsm), CL=50pF
Medium and Low Performance Pads (MP/LP), the identical output strength settings:
–
–
medium edge (LP/MPm), CL=50pF
weak edge (MPw), CL=50pF
Note:Pad asymmetry is already included in the following timings.
Table 3-57 Master Mode Timing, LVDSM output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20 2)
-1
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 3) 4)
500 CC
1
MTSR delay from SCLKO
shifting edge
t
51 CC
-3
-
3
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
0
-
-
-
-
-
30
7
ns
ns
ns
ns
ns
CL=25pF; MPsm
CL=25pF; MPss
MP+ss; CL=25pF
MP+sm; CL=25pF
-5
-4
7
-1
19 5)
15
-
MRST setup to SCLK latching
edge 5)
t
52 SR
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR
edge
-6 5)
-
-
ns
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
4) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
5) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Data Sheet
4-259
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-58 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-3
3
0 < CL < 50pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-7
-
-
-
-
6
6
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-7
MRST setup to SCLK latching
edge 4)
t
52 SR
27 4)5)
-6 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-59 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
3+0.01 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-10
-
10
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-10
-13
0
-
-
-
10
1
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
40
MP+m, MPm, LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
-10 4)5)
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
4-260
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-60 Master Mode timing MPss output pads for data and clock, CL=50pF
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
3.5+0.035 ns
0 < CL < 200pF
* CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-8
-
8
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-8
-1
0
-
-
-
8
ns
ns
ns
MPss; CL=50pF
15
50
MP+sm; CL=50pF
MP+m, MPm, LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
40 4)5)
-5 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-61 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
4+0.04 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-11
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-11
MRST setup to SCLK latching
edge 4)
t
52 SR
60 4)5)
-10 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
Data Sheet
4-261
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-62 Master Mode timing MPRm/MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-10
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
4+0.04 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-15
-
-
-
-
17
20
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-20
MRST setup to SCLK latching
edge 4)
t
52 SR
70 4)5)
-10 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-63 Master Mode Weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
1000
-30
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
30+0.15 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-65
-
-
-
-
65
65
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-65
MRST setup to SCLK latching
edge 4)
t
52 SR
300 4)5)
-40 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
Data Sheet
4-262
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-64 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SCLK clock period
SCLK duty cycle
t
t
t
54 SR
4 x TMAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
%
55/t54 SR
56 SR
40
4
60
-
MTSR setup to SCLK latching
edge
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hystheresis Inactive
Input Level AL
5
-
5
-
Input Level TTL
Hystheresis Inactive
Input Level AL
MTSR hold from SCLK latching t57 SR
edge
3
-
6
-
9
-
Input Level TTL
Hystheresis Inactive
Input Level AL
SLSI setup to first SCLK shift
edge
t
58 SR
5 1)
4 1)
8
-
-
-
Input Level TTL
Only for pin 15.1, AL
Hystheresis Inactive
Input Level AL
6
-
SLSI hold from last SCLK
latching edge
t
t
59 SR
60 CC
3
-
4
-
8
-
Input Level TTL
MRST delay from SCLK shift
edge
10
70
MP+m/MPRm;
CL=50pF
10
5
-
-
-
50
ns
ns
ns
MP+sm/MPRsm;
CL=50pF
30
MP+ss/MPRss;
CL=25pF
40
300
MP+w/MPRw;
CL=50pF
10
10
5
-
-
-
-
-
70
55
30
300
5
ns
ns
ns
ns
ns
MPm/LPm; CL=50pF
MPsm; CL=50pF
MPss; CL=25pF
40
-
MPw/LPw; CL=50pF
SLSI to valid data on MRST
1) Except pin P15.1.
t
61 SR
Data Sheet
4-263
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-18 Master Mode Timing
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-19 Slave Mode Timing
Data Sheet
4-264
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
3.26
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC 260 / 264 / 265 / 267, for 3.3V pad power supply.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
•
•
LVDSM output pads, LVDSH input pad, master mode, CL=25pF
Medium Performance Plus Pads (MP+):
–
–
–
–
strong sharp edge (MP+ss), CL=25pF
strong medium edge (MP+sm), CL=50pF
medium edge (MP+m), CL=50pF
weak edge (MP+w), CL=50pF
•
•
Medium Performance Pads (MP):
–
–
strong sharp edge (MPss), CL=25pF
strong medium edge (MPsm), CL=50pF
Medium and Low Performance Pads (MP/LP), the identical output strength settings:
–
–
medium edge (LP/MPm), CL=50pF
weak edge (MPw), CL=50pF
Note:Pad asymmetry is already included in the following timings.
Table 3-65 Master Mode Timing, LVDSM output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
2
MTSR delay from SCLKO
shifting edge
t
51 CC
-5
-
5
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-2
-9
-7
-2
20
-
-
-
-
-
55
12
12
26
-
ns
ns
ns
ns
ns
CL=25pF; MPsm
CL=25pF; MPss
MP+ss; CL=25pF
MP+sm; CL=25pF
MRST setup to SCLK latching
edge 4)
t
52 SR
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR
edge
-6
-
-
ns
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Data Sheet
4-265
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-66 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-5
5
0 < CL < 50pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-12
-
-
-
-
12
12
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-12
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-6 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-67 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
7
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-17
-
17
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-17
-22
0
-
-
-
17
2
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
70
MP+m; MPm; LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
85 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
-10 4)5)
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
4-266
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-68 Master Mode timing MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-5
7+0.07 * ns
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-10
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-10
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-6 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-69 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-5
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
9+0.06 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-19
-
-
-
-
19
17
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-19
MRST setup to SCLK latching
edge 4)
t
52 SR
100 4)5)
-13 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
4-267
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-70 Master Mode timing MPRm/MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SCLKO clock period 1)
t
t
50 CC
400
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-6-0.07 *
CL
6+0.07 * ns
CL
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-25
-
-
-
-
33
35
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-35
MRST setup to SCLK latching
edge 4)
t
52 SR
120 4)5)
-13 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-71 Master Mode Weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2000
-110
Max.
-
SCLKO clock period 1)
t
t
50 CC
-
-
ns
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
110
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-170
-
-
-
-
170
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-170
170
MRST setup to SCLK latching
edge 4)
t
52 SR
510 4)5)
-40 4)5)
-
-
MRST hold from SCLK latching t53 SR
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
4-268
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-72 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
4 x TMAX
40
7
Max.
SCLK clock period
SCLK duty cycle
t
t
t
54 SR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
%
55/t54 SR
56 SR
60
MTSR setup to SCLK latching
edge
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hystheresis inactive
Input Level AL
9
-
7
-
Input Level TTL
Hystheresis inactive
Input Level AL
MTSR hold from SCLK latching t57 SR
edge
5
-
11
16
7 1)
7 1)
14
11
5
-
-
Input Level TTL
Hystheresis inactive
Input Level AL
SLSI setup to first SCLK shift
edge
t
58 SR
-
-
-
Input Level TTL
Only for pin P15.1, AL
Hystheresis inactive
Input Level AL
-
SLSI hold from last SCLK
latching edge
t
t
59 SR
60 CC
-
7
-
14
13
-
Input Level TTL
MRST delay from SCLK shift
edge
120
MP+m/MPRm;
CL=50pF
13
6
-
-
-
85
ns
ns
ns
MP+sm/MPRsm;
CL=50pF
50
MP+ss/MPRss;
CL=25pF
70
500
MP+w/MPRw;
CL=50pF
13
13
6
-
-
-
-
-
120
100
52
ns
ns
ns
ns
ns
MPm/LPm; CL=50pF
MPsm; CL=50pF
MPss; CL=25pF
70
-
500
9
MPw/LPw; CL=50pF
SLSI to valid data on MRST
1) Except pin P15.1
t
61 SR
Data Sheet
4-269
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQSPI Timings, Master and Slave Mode
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-20 Master Mode Timing
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-21 Slave Mode Timing
Data Sheet
4-270
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 5 V Operation
3.27
MSC Timing 5 V Operation
The following section defines the timings for 5V pad power supply.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Table 3-73 LVDS clock/data (LVDS pads in LVDS mode)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-1
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
ns
LVDSM; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
1
LVDSM; 0 < CL < 50pF
4) 5)
SOPx output delay 6)
t
t
44 CC
-3
-4
-4
-3
-3
-
-
-
-
-
4
ns
ns
ns
ns
ns
LVDSM; CL=50pF;
option EN01
4.5
5
LVDSM; CL=50pF;
option EN01D
ENx output delay 6)
45 CC
MP+ss/MPRss; option
EN01; CL=25pF
7
MP+ss/MPRss; option
EN01; CL=50pF
11
MP+sm/MPRsm;
option EN01D;
CL=50pF
-2
-2
-3
-7
-5
-4
-7
-
-
-
-
-
-
-
9
ns
ns
ns
ns
ns
ns
ns
MP+ss/MPRss; option
EN23; CL=25pF
10
11
2
MP+ss/MPRss; option
EN23; CL=50pF
MPss; option EN01;
CL=50pF
MP+ss/MPRss; option
EN01; CL=0pF
3
MP+sm/MPRsm;
option EN01D; CL=0pF
5
MP+ss/MPRss; option
EN23; CL=0pF
4
MPss; option EN01;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
Data Sheet
4-271
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 5 V Operation
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Data Sheet
4-272
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 5 V Operation
Timing Options for t45
The wiring shown in the Figure 3-22 provides three useful timing options for t45. depending on the signals selected
with the alternate output lines (ALT1 to ALT7) in the ports:
•
•
•
EN01 - FCLN, SON, EN0, EN1
EN01D - FCLND, SOND, EN0, EN1 - t45 window shifted to the left
EN23 - FCLN, SON, EN2, EN3 - t45 window shifted to the right
- t45 reference timing
The timings corresponding to EN01, EN01D, and EN23 are defined in the LVDS mode. In order to use the EN23
timings, the application should use the EN2 and EN3 outputs of the MSC module.
ALT1
FCLN ALTx
ALTy
LVDSM
FCLP
FCLN
FCLND
ALT7
PAD
ALT1
SON ALTx
ALTy
LVDSM
SOP
SON
SOND
ALT7
PAD
ALT1
ALTx
ALTy
EN0
EN1
CMOS
ALT7
PAD
EN2
EN3
ALT1
ALTx
ALTy
CMOS
MSC
ALT7
PAD
_DoublePath_4a.vsd
Figure 3-22 Timing Options for t45
Table 3-74 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
MPss; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
3+0.035 * ns
MPss; 0 < CL < 100pF
4) 5)
CL
SOPx output delay 6)
t
44 CC
-4
-
7
ns
MPss; CL=50pF
Data Sheet
4-273
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 5 V Operation
Table 3-74 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ENx output delay 6)
t
45 CC
-5
-
7
ns
ns
MP+ss/MPRss;
CL=50pF
-2
-
15
MP+sm/MPRsm;
CL=50pF
-4
0
-
-
10
30
ns
ns
MPss; CL=50pF
MPsm; CL=50pF;
except pin P13.0
0
-
-
-
-
31
45
2
ns
ns
ns
ns
MPsm; CL=50pF; pin
P13.0
6
MPm/MP+m/MPRm;
CL=50pF
-11
-4
MP+ss/MPRss;
CL=0pF
7
MP+sm/MPRsm;
CL=0pF
-10
-1
-
-
-
2
ns
ns
ns
MPss; CL=0pF
MPsm; CL=0pF
16
18
-2
MP+m/MPm/MPRm;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) FCLP signal high and low can be minimum 1 * TMSC
.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Table 3-75 MP+sm/MPRsm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
-
-
ns
MP+sm/MPRsm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-2
-5
3+0.01 * ns
CL
MP+sm/MPRsm; 0 <
CL < 200pF
2) 3)
SOPx output delay 4)
Data Sheet
t
44 CC
7
ns
MP+sm; CL=50pF
4-274
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 5 V Operation
Table 3-75 MP+sm/MPRsm clock/data (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-13
-5
Max.
2 5)
ENx output delay 4)
t
45 CC
-
-
ns
ns
MPss; CL=50pF
11
MP+sm/MPRsm;
CL=50pF
1
4
-
-
24
37
ns
ns
MPsm; CL=50pF
MP+m/MPm/MPRm;
CL=50pF
-19
-13
-5
-
-
-
-
-1
2
ns
ns
ns
ns
MPss; CL=0pF
MP+sm; CL=0pF
MPsm; CL=0pF
8
-5
10
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
5) If EN1 is configured to P13.0 the max limt is increased by 0.5ns to 2.5ns.
Table 3-76 MPm/MP+m/MPRm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
MPm/MP+m/MPRm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-8
-
4+0.04 * ns
CL
MPm/MP+m; 0 < CL <
200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-11
-13
-
-
9
ns
ns
MPm/MP+m; CL=50pF
11
MPm/MP+m/MPRm;
CL=50pF
-33
-
-4
ns
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
Data Sheet
4-275
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 3.3 V Operation
t40
t400
FCLP
SOP
t44
t44
t45
t45
0.5 VEXT/FLEX
EN
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-23 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
3.28
MSC Timing 3.3 V Operation
The following section defines the timings for 3.3V pad power supply.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Mapping A, Combo Pads in LVDS Mode or CMOS Mode
The timing applies for the LVDS pads in LVDS operating mode:
•
•
The LVDSM output pads for clock and data signals set in LVDS mode
The CMOS MP pads for enable signals, with strong driver sharp edge (MPss) or strong driver medium edge
(MPsm).
Table 3-77 LVDS clock/data (LVDS pads in LVDS mode)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
ns
LVDSM; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
2
LVDSM; 0 < CL < 50pF
4) 5)
SOPx output delay 6)
t
44 CC
-5
-7
-
-
5
7
ns
ns
LVDSM; CL=50pF;
option EN01
LVDSM; CL=50pF;
option EN01D
Data Sheet
4-276
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-77 LVDS clock/data (LVDS pads in LVDS mode) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ENx output delay 6)
t
45 CC
-7
-
-
-
9
ns
ns
ns
MP+ss/MPRss; option
EN01; CL=25pF
-5
-5
13
26
MP+ss/MPRss; option
EN01; CL=50pF
MP+sm/MPRsm;
option EN01D;
CL=50pF
-4
-
-
-
-
-
-
-
16
17
19
4
ns
ns
ns
ns
ns
ns
ns
MP+ss/MPRss; option
EN23; CL=25pF
-4
MP+ss/MPRss; option
EN23; CL=50pF
-5
MPss; option EN01;
CL=50pF
-12
-9
MP+ss/MPRss; option
EN01; CL=0pF
11
9
MP+sm/MPRsm;
option EN01D; CL=0pF
-7
MP+ss/MPRss; option
EN23; CL=0pF
-12
7
MPss; option EN01;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Table 3-78 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-5
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
MPss; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
7+0.07 * ns
MPss; 0 < CL < 100pF
4) 5)
CL
Data Sheet
4-277
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-78 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-7
Max.
12
SOPx output delay 6)
ENx output delay 6)
t
t
44 CC
45 CC
-
-
ns
ns
MPss; CL=50pF
-9
12
MP+ss/MPRss;
CL=50pF
-4
-
26
ns
MP+sm/MPRsm;
CL=50pF
-7
0
-
-
17
54
ns
ns
MPss; CL=50pF
MPsm; CL=50pF;
except pin P13.0
0
-
-
-
-
58
77
4
ns
ns
ns
ns
MPsm; CL=50pF; pin
P13.0
4
MPm/MP+m/MPRm;
CL=50pF
-19
-7
MP+ss/MPRss;
CL=0pF
12
MP+sm/MPRsm;
CL=0pF
-17
-2
-
-
-
4
ns
ns
ns
MPss; CL=0pF
MPsm; CL=0pF
28
31
-4
MP+m/MPm/MPRm;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) FCLP signal high and low can be minimum 1 * TMSC
.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Mapping B, CMOS MP Pads
This timing applies for the dedicated CMOS pads, pin Mapping B:
•
•
MP strong sharp (MPss) output pads for the clock and the data signals
MP strong sharp or strong medium (MPss or MPsm) output pads for enable signals
Data Sheet
4-278
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-79 MP+sm/MPRsm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
ns
MP+sm/MPRsm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-3
-
7
MP+sm/MPRsm; 0 <
CL < 200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-9
-
-
-
12
4
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
-20
-9
19
MP+sm/MPRsm;
CL=50pF
0
0
-
-
44
63
ns
ns
MPsm; CL=50pF
MP+m/MPm/MPRm;
CL=50pF
-33
-23
-
-
0
4
ns
ns
MPss; CL=0pF
MP+sm/MPRsm;
CL=0pF
-9
-9
-
-
14
17
ns
ns
MPsm; CL=0pF
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
Table 3-80 MPm/MP+m/MPRm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
MPm/MP+m/MPRm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-6-0.07 *
CL
-
6+0.07 * ns
CL
MPm/MP+m/MPRm; 0
< CL < 200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-19
-19
-
-
16
20
ns
ns
MPm/MP+m; CL=50pF
MPm/MP+m/MPRm;
CL=50pF
-57
-
0
ns
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
4-279
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationMSC Timing 3.3 V Operation
4) From FCLP rising edge.
t40
t400
FCLP
t44
t44
SOP
EN
t45
t45
0.5 VEXT/FLEX
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-24 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
Data Sheet
4-280
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29
Ethernet Interface (ETH) Characteristics
3.29.1
ETH Measurement Reference Points
ETH Clock
ETH I/O
1.4
2.0
V
1.4 V
V
2.0
V
0.8
V
0.8
V
tR
tF
ETH_Testpoints.vsd
Figure 3-25 ETH Measurement Reference Points
Data Sheet
4-281
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29.2
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 3-81 ETH Management Signal Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
400
160
160
10
Max.
ETH_MDC period
ETH_MDC high time
ETH_MDC low time
t1 CC
t2 CC
t3 CC
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
-
-
ETH_MDIO setup time (output) t4 CC
ETH_MDIO hold time (output) t5 CC
ETH_MDIO data valid (input) t6 SR
-
10
-
0
300
t1
t3
t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4
t5
ETH_MDIO
(output )
Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input )
Valid Data
ETH_Timing-Mgmt.vsd
Figure 3-26 ETH Management Signal Timing
Data Sheet
4-282
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29.3
ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.
Table 3-82 ETH MII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Clock period
t7 SR
40
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF;
baudrate=100Mbps
400
14
-
CL=25pF;
baudrate=10Mbps
Clock high time
Clock low time
t8 SR
t9 SR
26
CL=25pF;
baudrate=100Mbps
140 1)
14
260 2)
26
CL=25pF;
baudrate=10Mbps
CL=25pF;
baudrate=100Mbps
140 1)
260 2)
CL=25pF;
baudrate=10Mbps
Input setup time
Input hold time
t
t
t
10 SR
11 SR
12 CC
10
10
0
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
-
Output valid time
25
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t7
t9
t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t10
t11
ETH_MII_RXD[3:0]
ETH_MII_RX_DV
ETH_MII_RX_ER
(sourced by PHY )
Valid Data
ETH_MII_TX_CLK
t12
ETH_MII_TXD[3:0]
ETH_MII_TXEN
Valid Data
(sourced by controller )
ETH_Timing-MII.vsd
Figure 3-27 ETH MII Signal Timing
Data Sheet
4-283
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.29.4
ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.
Table 3-83 ETH RMII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ETH_RMII_REF_CL clock
period
t
13 CC
20
-
-
-
-
-
ns
ns
ns
ns
CL=25pF; 50ppm
CL=25pF
ETH_RMII_REF_CL clock high t14 CC
time
7 1)
7 1)
4
13 2)
13 2)
-
ETH_RMII_REF_CL clock low t15 CC
time
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV,
ETHRXER; setup time
t
t
16 CC
17 CC
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV,
ETHRXER; hold time
2
-
-
ns
CL=25pF
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t13
t15
t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t16
t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0],
ETHCRSDV,
ETHRXER
Valid Data
ETH_Timing-RMII.vsd
Figure 3-28 ETH RMII Signal Timing
Data Sheet
4-284
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationE-Ray Parameters
3.30
E-Ray Parameters
The timings of this section are valid for the strong driver and either sharp edge settings of the output drivers with
CL = 25 pF. For the inputs the hysteresis has to be configured to inactive.
Table 3-84 Transmit Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise time of TxEN
Fall time of TxEN
tdCCTxENRise2
5 CC
-
-
-
-
9
ns
ns
ns
CL=25pF
tdCCTxENFall25
CC
-
-
9
9
CL=25pF
Sum of rise and fall time
tdCCTxRise25+
20% - 80%; CL=25pF
dCCTxFall25
CC
Sum of delay between TP1_FF tdCCTxEN01
-
-
-
-
25
25
ns
ns
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxEN
CC
Sum of delay between TP1_FF tdCCTxEN10
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxEN
CC
Asymmetry of sending
t
tx_asym CC -2.45
-
-
2.45
25
ns
ns
CL=25pF
Sum of delay between TP1_FF tdCCTxD01
-
-
-
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxD
CC
Sum of delay between TP1_FF tdCCTxD10
-
-
25
9
ns
ns
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxD
CC
TxD signal sum of rise and fall ttxd_sum CC
time at TP1_BD
Table 3-85 Receive Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -30.5
ept25 SR
-
43.0
ns
ns
%
%
CL=25pF
CL=15pF
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -31.5
ept15 SR
-
-
-
44.0
70
Threshold for detecting logical TuCCLogic1
high SR
Threshold for detecting logical TuCCLogic0
35
30
65
low
SR
Data Sheet
4-285
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationE-Ray Parameters
Table 3-85 Receive Parameters (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sum of delay between TP4_CC tdCCRxD01
-
-
10
ns
and TP4_FF and delays
derived from TP4_FFi, rising
edge of RxD
CC
Sum of delay between TP1_CC tdCCRxD10
-
-
10
ns
and TP1_CC and delays
derived from TP4_FFi, falling
edge of RxD
CC
Data Sheet
4-286
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationHSCT Parameters
3.31
HSCT Parameters
Table 3-86 HSCT - Rx/Tx setup timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
60
RX o/p duty cycle
Bias startup time
DCrx CC
-
%
t
bias CC
5
10
µs
Bias distributor waking
up from power down
and provide stable
Bias.
RX startup time
TX startup time
trxi CC
ttx CC
-
-
5
5
-
-
µs
µs
Wake-up RX from
power down.
Wake-up TX from
power down.
Table 3-87 HSCT - Rx parasitics and loads
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Capacitance total budget
Ctotal CC
-
3.5
5
pF
Total Budget for
complete receiver
including silicon,
package, pins and
bond wire
Parasitic inductance budget
Htotal CC
-
5
-
nH
Table 3-88 LVDSH - Reduced TX and RX (RED)
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Output differential voltage
V
OD CC
150
200
285
mV
Rt = 100 Ohm ±20%
@2pF
Output voltage high
Output voltage low
V
V
OH CC
OL CC
-
-
1463
-
mV
mV
V
Rt = 100 Ohm ±20%
Rt = 100 Ohm ±20%
937
1.08
-
Output offset (Common mode) VOS CC
voltage
1.2
1.32
Rt = 100 Ohm ±20%
@2pF
Input voltage range
VI SR
-
-
-
-
1.6
-
V
Absolute max = 1.6 V +
(285mV/2) = 1.743
0.15
-100
V
Absolute min = 0.15 V -
(285 mV /2) = 0 V
Input differential threshold
Data frequency
V
idth SR
100
mV
100 mV for 55% of bit
period; Note Absolute
Value (Vidth - Vidthl)
DR CC
5
-
320
Mbps
Data Sheet
4-287
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationHSCT Parameters
Table 3-88 LVDSH - Reduced TX and RX (RED) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
90
80
-
Max.
110
120
2
Receiver differential input
impedance
Rin CC
100
Ohm
Ohm
V/ns
mV
0 V < VI < 1.6V
100
1.6 V < VI < 2.0V
Slew rate
SRtx CC
-
-
Change in VOS between 0 and dVOS CC
1
-
50
Peak to peak
(including DC
transients).
Change in Vod between 0 and dVod CC
1
-
-
50
mV
Peak to peak
(including DC
transients)
Fall time 1)
Rise time 1)
t
t
fall CC
rise CC
0.26
0.26
-
-
1.2
1.2
ns
ns
Rt = 100 Ohm ±20%
@2pF
Rt = 100 Ohm ±20%
@2pF
1) Rise / fall times are defined for 10% - 90% of VOD
Table 3-89 HSCT PLL
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
12.5
10
-
Typ.
Max.
320
PLL frequency range
PLL input frequency
PLL lock-in time
f
f
t
PLL CC
REF CC
LOCK CC
320
MHz
MHz
µs
-
-
-
20
50
Bit Error Rate based on 10 MHz BER10 CC
reference clock at Slave PLL
side
-
10EXP-9
-
Bit Error Rate based
on Slave interface
reference clock at 10
MHz
Bit Error Rate based on 20 MHz BER20 CC
reference clock at Slave PLL
side
-
-
-
-
10EXP-
12
-
Bit Error Rate based
on Slave interface
reference clock at 20
MHz
Absolute RMS Jitter (TX out)
JABS10 CC
-125
-85
125
85
ps
ps
Measured at link TX
out; valid for
Reference frequency
at 10 MHz
Absolute RMS Jitter (TX out)
JABS20 CC
Measured at link TX
out; valid for
Reference frequency
at 20 MHz
Data Sheet
4-288
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationHSCT Parameters
Table 3-89 HSCT PLL (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Accumulated RMS Jitter (RX
side)
J
ACC10 CC
-
-
-
-
145
ps
Measured at link RX
input, based on 5000
measures, each 300
clock cycles; valid for
Reference frequency
at 10 MHz
Accumulated RMS Jitter (link
RX side)
JACC20 CC
-
-
115
ps
Measured at link RX
input, based on 5000
measures, each 300
clock cycles; valid for
Reference frequency
at 20 MHz
Total Jitter peak to peak
TJpp CC
2083
ps
Total Jitter as sum of
deterministic jitter and
random jitter
Table 3-90 HSCT Sysclk
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
20
1
Frequency
f
SYSCLK CC 10
-
-
-
-
-
-
MHz
%
Frequency error
Duty Cycle
dfERR CC -1
DCsys CC 45
55
-
%
Load impedance
Load capacitance
Integrated phase noise
R
LOAD CC
LOAD CC
PN CC
10
-
kOhm
pF
C
10
-58
I
-
dB
single sideband phase
noise in 10 kHz to 10
Mhz at 20 MHz SysClk
Data Sheet
4-289
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationInter-IC (I2C) Interface Timing
3.32
Inter-IC (I2C) Interface Timing
This section defines the timings for I2C in the TC 260 / 264 / 265 / 267.
All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-91 I2C Standard Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
-
-
300
ns
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
4.7
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
-
-
-
-
-
-
-
1000
ns
µs
ns
µs
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data hold time
t3
t4
t5
t6
t7
0
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
250
4.7
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Hold time for the (repeated)
START condition
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
4-290
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationInter-IC (I2C) Interface Timing
Table 3-91 I2C Standard Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Set-up time for (repeated)
START condition
t8
4.7
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
4
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Table 3-92 I2C Fast Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
20+0.1*C -
300
ns
Measured with a pull-
up resistor of 4.7
b
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
1.3
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
20+0.1*C -
300
ns
µs
ns
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
b
Data hold time
t3
t4
t5
t6
0
-
-
-
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
100
1.3
0.6
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
4-291
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationInter-IC (I2C) Interface Timing
Table 3-92 I2C Fast Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Hold time for the (repeated)
START condition
t7
0.6
-
-
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for (repeated)
START condition
t8
0.6
0.6
-
-
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
4-292
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationSCR Parameters
3.33
SCR Parameters
SSC Timing 5V
3.33.1
It is assumed that SCLKO and MTSR pads have the same pad settings:
•
Medium Performance Plus Pads (MP+):
–
–
–
–
strong sharp edge (MP+ss), CL=25pF
strong medium edge (MP+sm), CL=50pF
medium edge (MP+m), CL=50pF
weak edge (MP+w), CL=50pF
•
•
Medium Performance Pads (MP):
–
–
strong sharp edge (MPss), CL=25pF
strong medium edge (MPsm), CL=50pF
Medium and Low Performance Pads (MP/LP), the identical output strength settings:
–
–
medium edge (LP/MPm), CL=50pF
weak edge (MPw), CL=50pF
Table 3-93 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-10
Max.
-
SCLKO clock period 1)
t
t
50 CC
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
10
MTSR delay from SCLKO
shifting edge
t
51 CC
-10
-
-
10
-
ns
ns
CL=50pF
CL=50pF
MRST hold from SCLK latching t53 SR
-10 4) 5)
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-94 Master Mode timing MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-15
Max.
-
SCLKO clock period 1)
t
t
50 CC
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
15
MTSR delay from SCLKO
shifting edge
t
51 CC
-15
-
15
ns
CL=50pF
Data Sheet
4-293
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationSCR Parameters
Table 3-94 Master Mode timing MP+m/MPm/LPm output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to SCLK latching
edge 4)
t
52 SR
-70 4)5)
-
-
ns
ns
CL=50pF
CL=50pF
MRST hold from SCLK latching t53 SR
-10 4)5)
-
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-95 Slave mode timing
Parameter
Symbol
Values
Typ.
4 x TSSC -
Unit
Note / Test Condition
Min.
Max.
SCLK clock period
SCLK duty cycle
t
t
t
54 SR
-
ns
%
55/t54 SR
56 SR
40
-
-
60
-
MTSR setup to SCLK latching
edge
40 1)
ns
MTSR hold from SCLK latching t57 SR
edge
3
-
-
-
-
ns
ns
SLSI setup to first SCLK shift
edge
t
t
58 SR
60 CC
3 1)
MRST delay from SCLK shift
edge
10
10
5
-
-
-
-
-
-
-
-
70
ns
ns
ns
ns
ns
ns
ns
ns
MP+m; CL=50pF
MP+sm; CL=50pF
MP+ss; CL=25pF
MP+w; CL=50pF
MPm/LPm; CL=50pF
MPsm; CL=50pF
MPss; CL=25pF
50
30
100
10
10
5
300
70
50
30
100
300
MPw/LPw; CL=50pF
1) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Data Sheet
4-294
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationSCR Parameters
t0
SCLK1)
t1
t1
t00
1)
MTSR
t2
t3
Data
valid
Data
valid
1)
MRST
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_TmgMM.vsd
Figure 3-29 Master Mode Timing
t4
Last latching
SCLK edge
First latching
SCLK edge
First shift
SCLK edge
SCLK1)
t5
t5
t6
t6
t7
t7
1)
Data
valid
Data
valid
MTSR
t8
t8
1)
MRST
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_TmgSM.vsd
Figure 3-30 Slave Mode Timing
3.33.2
SPD Timing
The SPD interface will work with standard SPD tools having a sample/output clock frequency deviation of +/- 5%
or less. For further details please refer to application note AP24004 in section SPD Timing Requirements.
3.33.3
WCAN Timing
The following table defines the timing parameter for the WCAN filter.
Data Sheet
4-295
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationSCR Parameters
Table 3-96 WCAN
Parameter
Symbol
Values
Typ.
0.75
Unit
Note / Test Condition
Min.
SILENCE SR 0.6
Max.
Timeout for bus inactivity
t
1.2
s
Data Sheet
4-296
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationCIF Parameters
3.34
CIF Parameters
Table 3-97 Timings for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
2.5
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
96 MHz
HSYNC, VSYNC set up time
AL input level,
hysteresis bypass
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TTL input level,
hysteresis bypass
6.5
4
TTL input level,
hysteresis on
AL input level,
hysteresis on
HSYNC, VSYNC hold time
Pixel data set up time
Pixel data hold time
t
t
t
72 SR
73 SR
74 SR
2.5
2.5
7
AL input level,
hysteresis bypass
TTL input level,
hysteresis bypass
TTL input level,
hysteresis on
4
AL input level,
hysteresis on
2.5
2
AL input level,
hysteresis bypass
TTL input level,
hysteresis bypass
6.5
4
TTL input level,
hysteresis on
AL input level,
hysteresis on
2.5
2.5
7
AL input level,
hysteresis bypass
TTL input level,
hysteresis bypass
TTL input level,
hysteresis on
4
AL input level,
hysteresis on
Data Sheet
4-297
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationCIF Parameters
Table 3-98 Timings for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
3.5
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
AL input level,
hysteresis bypass
4.5
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AL input level,
hysteresis on
TTL input level,
hysteresis on
3
TTL input level,
hysteresis bypass
HSYNC, VSYNC hold time
Pixel data set up time
Pixel data hold time
t
t
t
72 SR
73 SR
74 SR
4
AL input level,
hysteresis bypass
5
AL input level,
hysteresis on
10
3.5
3.5
4.5
9
TTL input level,
hysteresis on
TTL input level,
hysteresis bypass
AL input level,
hysteresis bypass
AL input level,
hysteresis on
TTL input level,
hysteresis on
3
TTL input level,
hysteresis bypass
4
AL input level,
hysteresis bypass
5
AL input level,
hysteresis on
10
3.5
TTL input level,
hysteresis on
TTL input level,
hysteresis bypass
Table 3-99 Timings for 0.4V to 2.4V input signals (2.8V imager)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel clock period
t
70 SR
10.42
-
-
ns
Data Sheet
4-298
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationCIF Parameters
Table 3-99 Timings for 0.4V to 2.4V input signals (2.8V imager) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
HSYNC, VSYNC set up time
t
t
t
t
71 SR
72 SR
73 SR
74 SR
3
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hysteresis Bypass,
3.3V±10%
9
-
-
-
-
-
-
-
-
-
-
-
TTL Input Levels,
3.3V±10%
4.5
3.5
10
5
TTL Input Levels,
5V±10%
HSYNC, VSYNC hold time
Pixel data set up time
Pixel data hold time
Hysteresis Bypass,
3.3V±10%
TTL Input Levels,
3.3V±10%
TTL Input Levels,
5V±10%
3
Hysteresis Bypass,
3.3V±10%
9
TTL Input Levels,
3.3V±10%
4.5
3.5
10
5
TTL Input Levels,
5V±10%
Hysteresis Bypass,
3.3V±10%
TTL Input Levels,
3.3V±10%
TTL Input Levels,
5V±10%
Table 3-100 Timings for 0.4V to 2.4V input signals (2.8V imager), ± 5% pad power supply
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
3
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
Hysteresis Bypass,
3.3V±5%
9
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
TTL Input Levels,
3.3V±5%
4.5
3.5
10
5
TTL Input Levels,
5V±5%
HSYNC, VSYNC hold time
t
72 SR
Hysteresis Bypass,
3.3V±5%
TTL Input Levels,
3.3V±5%
TTL Input Levels,
5V±5%
Data Sheet
4-299
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationCIF Parameters
Table 3-100 Timings for 0.4V to 2.4V input signals (2.8V imager), ± 5% pad power supply (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel data set up time
t
73 SR
3
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Hysteresis Bypass,
3.3V±5%
9
-
-
-
-
-
TTL Input Levels,
3.3V±5%
4.5
3.5
10
5
TTL Input Levels,
5V±5%
Pixel data hold time
t
74 SR
Hysteresis Bypass,
3.3V±5%
TTL Input Levels,
3.3V±5%
TTL Input Levels,
5V±5%
Table 3-101 Timings for 1.8V imager, TTL input level
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
10.42
3
Typ.
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
Input signal 0.1V to
1.7V
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input signal 0.2V to
1.6V
4.5
3.5
3.5
10
5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
HSYNC, VSYNC hold time
t
72 SR
Input signal 0.1V to
1.7V
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Pixel data set up time
t
73 SR
3
Input signal 0.1V to
1.7V
9
Input signal 0.2V to
1.6V
4.5
3.5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
Data Sheet
4-300
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationCIF Parameters
Table 3-101 Timings for 1.8V imager, TTL input level (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel data hold time
t
74 SR
3.5
-
-
-
-
-
ns
ns
ns
ns
Input signal 0.1V to
1.7V
10
5
-
-
-
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Table 3-102 Timings for 1.8V imager, 3.3V ± 5% pad power supply, TTL input level
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
3
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
Input signal 0.1V to
1.7V
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input signal 0.2V to
1.6V
4.5
3.5
3.5
10
5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
HSYNC, VSYNC hold time
t
72 SR
Input signal 0.1V to
1.7V
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Pixel data set up time
t
73 SR
3
Input signal 0.1V to
1.7V
9
Input signal 0.2V to
1.6V
4.5
3.5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
Data Sheet
4-301
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationCIF Parameters
Table 3-102 Timings for 1.8V imager, 3.3V ± 5% pad power supply, TTL input level (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel data hold time
t
74 SR
3.5
-
-
-
-
-
ns
ns
ns
ns
Input signal 0.1V to
1.7V
10
5
-
-
-
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Data Sheet
4-302
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationFlash Target Parameters
3.35
Flash Target Parameters
Program Flash program and erase operation is only allowed up the TJ = 150°C.
Table 3-103 FLASH
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program Flash Erase Time per tERP CC
logical sector
-
-
-
1
-
s
s
cycle count < 1000
0.207 +
0.003 * (S
[KByte]) /
(fFSI
cycle count < 1000, for
sector of size S
[MHz])1)
Program Flash Erase Time per tMERP CC
Multi-Sector Command
-
-
-
1
-
s
s
Forconsecutivelogical
sectors in a physical
sector, cycle count <
1000
0.207 +
0.003 * (S
[KByte]) /
(fFSI
Forconsecutivelogical
sector range of size S
in a physical sector,
cycle count < 1000
[MHz])1)
Program Flash program time
per page in 5 V mode
t
t
t
t
PRP5 CC
PRP3 CC
PRPB5 CC
PRPB3 CC
-
-
-
-
-
-
-
-
-
-
50 +
3000/(fFSI
[MHz])
µs
µs
µs
µs
s
32 Byte
32 Byte
256 Byte
256 Byte
Program Flash program time
per page in 3.3 V mode
81 +
3400/(fFSI
[MHz])
Program Flash program time
per burst in 5 V mode
125 +
9500/(fFSI
[MHz])
Program Flash program time
per burst in 3.3 V mode
410 +
12000/(fF
SI [MHz])
Program Flash program time
for 1 MByte with burst
programming in 3 V mode
excluding communication
tPRPB3_1MB
CC
2.2
0.9
2.3
Derived value for
documentation
purpose, valid for fFSI
=
=
=
100MHz
Program Flash program time
for 1 MByte with burst
programming in 5 V mode
excluding communication
tPRPB5_1MB
CC
-
-
-
-
s
s
Derived value for
documentation
purpose, valid for fFSI
100MHz
Program Flash program time
for complete PFlash with burst CC
programming in 5 V mode
tPRPB5_PF
Derived value for
documentation
purpose, valid for fFSI
100MHz
excluding communication
Data Sheet
4-303
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationFlash Target Parameters
Table 3-103 FLASH (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Write Page Once adder
t
ADD CC
-
-
15 +
500/(fFSI
[MHz])
µs
Adder to Program
Time when using Write
Page Once
Program Flash suspend to read tSPNDP CC
latency
-
-
12000/(fF µs
SI [MHz])
For Write Burst, Verify
Erased and for multi-
(logical) sector erase
commands
Data Flash Erase Time per
Sector 2)
t
t
ERD CC
-
-
-
0.12 +
0.08/(fFSI
[MHz])1)
-
s
s
s
cycle count < 1000
0.57 +
0.928 +
cycle count < 125000
0.15/(fFSI 0.15/(fFSI
[MHz])1)
[MHz])
Data Flash Erase Time per
Multi-Sector Command 2)
MERD CC
0.12 +
-
Forconsecutivelogical
sector range of size S,
cycle count < 1000
0.01 * (S
[KByte]) /
(fFSI
[MHz])1)
-
0.57 +
0.019 * (S 0.019 * (S
[KByte]) / [KByte]) /
0.928 +
s
Forconsecutivelogical
sector range of size S,
cycle count < 125000
(fFSI
(fFSI
[MHz])
[MHz])1)
Data Flash erase disturb limit
N
DFD CC
-
-
-
-
50
cycles
µs
Program time data flash per
page 3)
t
PRD CC
50 +
2500/(fFSI
[MHz]) 3)
8 Byte
Complete Device Flash Erase
Time PFlash and DFlash 4)
t
ER_Dev CC
-
-
-
-
6
s
Derived value for
documentation
purpose, valid for fFSI
=
100MHz
Data Flash program time per
burst 3)
t
t
PRDB CC
96 +
4400/(fFSI
[MHz]) 3)
µs
32 Bytes
Data Flash suspend to read
latency
SPNDD CC
-
-
-
-
-
12000/(fF µs
SI [MHz])
Wait time after margin change tFL_MarginDel
-
10
-
µs
CC
Program Flash Retention Time, tRET CC
Sector
20
years
Max. 1000
erase/program cycles
Data Flash Endurance per
EEPROMx sector 5)
NE_EEP10
CC
125000
-
cycles Max. data retention
time 10 years
Data Sheet
4-304
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationFlash Target Parameters
Table 3-103 FLASH (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
E_HSM CC 125000
Max.
Data Flash Endurance per
HSMx sector 5)
N
-
-
cycles Max. data retention
time 10 years
UCB Retention Time
t
RTU CC
20
-
-
years
Max. 100
erase/program cycles
per UCB, max 400
erase/program cycles
in total
Data Flash access delay
Data Flash ECC Delay
t
t
t
t
DF CC
-
-
-
-
-
-
-
-
100
20
ns
ns
ns
ns
see
PMU_FCON.WSDFLA
SH
DFECC CC
see
PMU_FCON.WSECD
F
Program Flash access delay
Program Flash ECC delay
PF CC
30
see
PMU_FCON.WSPFLA
SH
PFECC CC
10
see
PMU_FCON.WSECP
F
Number of erase operations on NERD0 CC
DF0 over lifetime
-
-
-
-
750000
150
cycles
°C
Junction temperature limit for
PFlash program/erase
operations
TJPFlash SR
1) All typical values were characterised, but are not tested. Typical values are safe median values at room temperature
2) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase
processes may be increased by up to 50%.
3) Time is not dependent on program mode (5V or 3.3V).
4) Using 512 KByte erase commands.
5) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
Data Sheet
4-305
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPackage Outline
3.36
Package Outline
Figure 3-31 Package Outlines PG-LQFP-144-22
Table 3-104 Exposed Pad Dimensions
Ax; vaild for Feature Package D and DC (nominal EPad size)
Ay; vaild for Feature Package D and DC (nominal EPad size)
Ex; vaild for Feature Package D and DC (solder able EPad size)
Ey; vaild for Feature Package D and DC (solder able EPad size)
Ax; vaild for Feature Package DA (nominal EPad size)
Ay; vaild for Feature Package DA (nominal EPad size)
Ex; vaild for Feature Package DA (solder able EPad size)
Ey; vaild for Feature Package DA (solder able EPad size)
7.5 mm ± 50 µm
7.5 mm ± 50 µm
6.7 mm ± 50 µm
6.7 mm ± 50 µm
7.7 mm ± 50 µm
9.2 mm ± 50 µm
6.9 mm ± 50 µm
8.4 mm ± 50 µm
Note:It is recommended to use dimensions Ex and Ey for board layout considerations. Solder wetting between
Ex / Ey and Ax / Ay and lead between Ex / Ey and Ax / Ay will not case any harm.
Data Sheet
4-306
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPackage Outline
Figure 3-32 Package Outlines PG-LQFP-176-22
Table 3-105 Exposed Pad Dimensions
Ax; vaild for Feature Package D and DC (nominal EPad size)
Ay; vaild for Feature Package D and DC (nominal EPad size)
Ex; vaild for Feature Package D and DC (solder able EPad size)
Ey; vaild for Feature Package D and DC (solder able EPad size)
Ax; vaild for Feature Package DA (nominal EPad size)
Ay; vaild for Feature Package DA (nominal EPad size)
Ex; vaild for Feature Package DA (solder able EPad size)
Ey; vaild for Feature Package DA (solder able EPad size)
7.5 mm ± 50 µm
7.5 mm ± 50 µm
6.7 mm ± 50 µm
6.7 mm ± 50 µm
7.7 mm ± 50 µm
9.2 mm ± 50 µm
6.9 mm ± 50 µm
8.4 mm ± 50 µm
Note:It is recommended to use dimensions Ex and Ey for board layout considerations. Solder wetting between
Ex / Ey and Ax / Ay and lead between Ex / Ey and Ax / Ay will not case any harm.
Data Sheet
4-307
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPackage Outline
292x
0.5 ±0 .0 5
M
M
0.15
0.08
C
C
A B
1.7 MAX
0.1 C
17 ±0.1
B
A
20
19
18
17
16
15
14
13
12
11
10
9
CODE
8
7
292x
0.15
6
5
4
3
COPLANARITY
2
1
Y W V U T R P N M L K J HG F E D C B
19 x 0.8 = 15.2
A
INDEX
INDEX MARKING
(LASERED )
0.8
MARKING
C
0.33 MIN
STANDOFF
Figure 3-33 Package Outlines PG-LFBGA-292-6
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
3.36.1
Package Parameters
Table 3-106 Thermal Characteristics of the Package
Device
Package
RQJCT1)
RQJCB1) RQJA
Unit
Note
TC264
PG-LQFP-144-22PG-
LFBGA-292-6
13,3
3,3
18,62)
19,42)
24,93)
K/W
with soldered
exposed pad
TC265
PG-LQFP-176-22PG-
LFBGA-292-6
11,7
3,5
K/W
with soldered
exposed pad
TC267
PG-LFBGA-292-6
11,1
15,0
K/W
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the
thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal
resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT
,
R
TCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA * PD, where the RTJA is the total
thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from
the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
2) Value is defined in accordance with JEDEC JESD51-3, JESD51-5, and JESD51-7.
3) Value is defined in accordance with JEDEC JESD51-1.
3.36.2
TC260 Carrier Tape
Data Sheet
4-308
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationPackage Outline
Figure 3-34 Carrier Tape Dimenions
Table 3-107 TC260 Chip Dimenions
Device
A
B
T
TC260
5,910 mm
6,453 mm
0,3 mm
Data Sheet
4-309
V 1.0 2017-06
TC 260 / 264 / 265 / 267
Electrical SpecificationQuality Declarations
3.37
Quality Declarations
Table 3-108 Quality Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
24500
2000
Operation Lifetime
tOP
-
-
-
-
hour
V
ESD susceptibility according to VHBM
Conforming to
Human Body Model (HBM)
JESD22-A114-B
ESD susceptibility of the LVDS VHBM1
pins
-
-
-
-
500
500
V
V
ESD susceptibility according to VCDM
for all other balls/pins;
conforming to
Charged Device Model (CDM)
JESD22-C101-C
-
-
-
-
750
3
V
for corner balls/pins;
conforming to
JESD22-C101-C
Moisture Sensitivity Level
MSL
Conforming to Jedec
J-STD--020C for 240C
Data Sheet
4-310
V 1.0 2017-06
TC 260 / 264 / 265 / 267
History
4
History
Version 1.0 is the first version of this document.
•
•
VADC
–
–
–
Add parameter tWU
Add parameter RMDU
Add parameter RMDD
Calculating the 1.3 V Current Consumption
–
–
Add formula 3.4
Add furmula 3.5
•
•
Changes in table 'Master Mode timing MPRm/MP+m/MPm/LPm output pads' of QSPI/5V
Change max value of t51 from '15 ns' to '17 ns'
EVR/Supply Monitoring
Change note of tEVRMON from '' to 'after trimming'
–
–
Data Sheet
5-311
V 1.0 2017-06
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明