SAK-TC297TX-128F300N BC [INFINEON]
SAK-TC297TX-128F300N BC 属于第一代 Aurix TC29xTX 系列产品。其创新多核心架构基于多达三个独立 32 位 TriCore CPU，专为满足极高的安全标准，同时大幅提高性能而设计。TC29xTX 系列属于第一代 TC2xxAurix应用。TC29xTX 系列产品配备 300 MHz TriCore、5V 或者 3.3V 单供电电压和强大的通用定时器模块 (GTM)，旨在降低复杂度、实现同类产品中极其优秀的功耗并节省大量成本。;
| 型号： | SAK-TC297TX-128F300N BC |
| 厂家： | 
Infineon |
| 描述： | SAK-TC297TX-128F300N BC 属于第一代 Aurix TC29xTX 系列产品。其创新多核心架构基于多达三个独立 32 位 TriCore CPU，专为满足极高的安全标准，同时大幅提高性能而设计。TC29xTX 系列属于第一代 TC2xxAurix应用。TC29xTX 系列产品配备 300 MHz TriCore、5V 或者 3.3V 单供电电压和强大的通用定时器模块 (GTM)，旨在降低复杂度、实现同类产品中极其优秀的功耗并节省大量成本。 |
| 文件： | 总459页 (文件大小：18939K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Bit
Microcontroller
TC290 / TC297 / TC298 / TC299
32-Bit Single-Chip Microcontroller
BC-Step
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1, 2019-03
Microcontrollers
Edition 2019-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TC290 / TC297 / TC298 / TC299 BC-Step
Revision History
Page or Item
Subjects (major changes since previous revision)
V 1.1, 2019-03
The history is documented in the last chapter
Data Sheet
3
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
Package and Pinning Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TC299x Pin Definition and Functions: BGA516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TC299x BGA516 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
TC298x Pin Definition and Functions: BGA416 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TC298x BGA416 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
TC297x Pin Definition and Functions: BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
TC297x BGA292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
TC29x Bare Die Pad Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Pad Openings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.3.2
2.3.3
2.4
2.4.1
2.4.2
2.4.3
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
High performance LVDS Pads (LVDSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Medium performance LVDS Pads (LVDSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
3.8
3.9
3.10
3.11
3.12
3.13
3.13.1
3.14
3.14.1
3.14.2
3.14.3
3.14.4
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
Data Sheet
TOC-1
V 1.1, 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
3.25
3.26
3.27
3.28
3.28.1
3.28.2
3.28.3
3.28.4
3.29
3.30
3.31
3.32
3.32.1
3.32.2
3.32.3
3.32.4
3.33
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
MSC Timing 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 424
ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
CIF Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
TC290 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
3.34
3.35
3.35.1
3.35.2
3.36
4
4.1
4.2
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Changes from TC29xBB_v1.1 to TC29xBC_v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Changes from v1.0 to v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Data Sheet
2
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
3
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Summary of Features
1
Summary of Features
The TC29x product family has the following features:
•
•
High Performance Microcontroller with three CPU cores
Two 32-bit super-scalar TriCore CPUs (TC1.6P), each having the following features:
–
–
–
–
–
–
–
–
–
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Multiply-accumulate unit able to sustain 2 MAC operations per cycle
up to 300 MHz operation at full temperature range
up to 120 / 240 Kbyte Data Scratch-Pad RAM (DSPR)
up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR)
16 / 32 Kbyte Instruction Cache (ICACHE)
8 Kbyte Data Cache (DCACHE)
•
•
Lockstepped shadow cores for TC1.6P core 1
Multiple on-chip memories
–
–
–
–
–
All embedded NVM and SRAM are ECC protected
up to 8 Mbyte Program Flash Memory (PFLASH)
up to 768 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
32 Kbyte Memory (LMU)
BootROM (BROM)
•
•
•
128-Channel DMA Controller with safe data transfer
Sophisticated interrupt system (ECC protected)
High performance on-chip bus structure
–
–
–
64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (SFI Bridge)
•
•
•
•
Safety Management Unit (SMU) handling safety monitor alarms
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
Hardware I/O Monitor (IOM) for checking of digital I/O
Versatile On-chip Peripheral Units
–
Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
–
–
–
–
Six Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
Two MultiCAN+ Module with 6 CAN nodes and 384 free assignable message objects for high efficiency
data handling via FIFO buffering and gateway data transfer
–
–
–
15 Single Edge Nibble Transmission (SENT) channels for connection to sensors
Up to two FlexRayTM modules with 2 channels (E-Ray) supporting V2.1
One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management
–
One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
Data Sheet
4
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Summary of Features
–
–
–
–
–
One General Purpose 12 Timer Unit (GPT120)
Five channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
Peripheral Sensor Interface with Serial PHY (PSI5-S)
Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
Optional IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)
•
•
Versatile Successive Approximation ADC (VADC)
–
–
Cluster of 11 independent ADC kernels
Input voltage range from 0v to 5.5V (ADC supply)
Delta-Sigma ADC (DSADC)
Ten channels
–
•
•
•
Digital programmable I/O ports
On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
Dedicated Emulation Device chip available
–
–
–
multi-core debugging, real time tracing, and calibration
Aurora Gigabit Trace Port (AGBT) on some variants
four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
•
•
•
Power Management System and on-chip regulators
Clock Generation Unit with System PLL and Flexray PLL
Embedded Voltage Regulator
Data Sheet
5
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply voltage
The package and the type of delivery.
For the available ordering codes for the TC290 / TC297 / TC298 / TC299 please refer to the
“AURIX™ TC2xx Data Sheet Addendum”, which summarizes all available variants.
Table 1-1 Overview of TC27x Functions
Feature
TC1.6P
3 / 1
CPU Core
Type
P Cores / Checker Cores
Max. Freq.
FPU
300 MHz
yes
8 Mbyte
Program Flash
Data Flash
Cache
Size
768 Kbyte
16 / 32 / 32 Kbyte
8 Kbyte
Size
Instruction (P / E)
Data (P / E)
120 Kbyte / 32 Kbyte 1) 2)
240Kbyte / 32 Kbyte
240 Kbyte / 32 Kbyte
SRAM
Size TC1.6P
(DSPR/PSPR)
32 Kbyte
Size LMU
Channels
Channels
Converter
Channels
TIM
128
DMA
ADC
72 + 12
11
10
6
DSADC
GTM
5
TOM
9 / 6
1 / 1
2
ATOM / MCS
CMU / ICM
PSM
1
TBU
4
SPE
1 / 1
1 / 1
1
CMP / MON
BRC / DPLL
GPT12
Timer
2
CCU6
3
STM
Modules
Modules
Channels
Nodes
2
FlexRay
4
6
CAN
384
Message Objects
Data Sheet
6
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Summary of Features
Table 1-1 Overview of TC27x Functions (cont’d)
Feature
6
QSPI
Channels
Interfaces
Interfaces
Channels
Modules
Modules
Channels
Channels
Channels
Level
4
ASCLIN
I2C
2
15
SENT
PSI5
5
1
PSI5-S
HSSL
1
3
MSC
1
Ethernet
ASIL
up to ASIL-D
1
1
FCE
Modules
SMU
Safety support
1
IOM
1
Security
HSM
Yes
ADAS
Yes
Yes
Yes
Yes
Embedded Voltage Regulator
Embedded Voltage Regulator
Embedded Voltage Regulator
Low Power Feature
Packages
DCDC from 5 V / 3.3 V to 1.3 V
LDO from 5 V / 3.3 V to 1.3 V
LDO from 5 V to 3.3 V
Standby RAM
LF-BGA-292-6 / LF-BGA-292-10 /
PG-BGA-416-26 / PG-BGA-416-
29 / PG-LFBGA-516-5 / PG-LFBGA-
516-10
Type
5 V CMOS / 3.3 V CMOS / LVDS
I/O
Type
−40 … +125°C
Tambient
Range
1) Address range starts at lowest address defined in the User’s Manual. For reference see the Memory Maps chapter of the
User’s Manual.
2) To ensure the processor cores are provided with a constant stream of instructions the Instruction Fetch Units will
speculatively fetch instructions from the up to 64 bytes ahead of the current PC.
If the current PC is within 64 bytes of the top of an instruction memory the Instruction Fetch Unit may attempt to
speculatively fetch instruction from beyond the physical range. This may then lead to error conditions and alarms being
triggered by the bus and memory systems.
It is therefore recommended that the upper 64 bytes of any memory be unused for instruction storage.
Data Sheet
7
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning Definitions
2
Package and Pinning Definitions
This chapter gives a pinning of the different packages of the TC290 / TC297 / TC298 / TC299.
Data Sheet
TOC-8
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
2.1
TC299x Pin Definition and Functions: BGA516
Figure 2-1 is showing the TC299x Logic Symbol for the package variant: BGA516.
6
5
4
3
2
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
AN51
AN53
AN55
NC
NC
NC
VSS VFLEXE P30.15 P30.13 P30.11 P30.9 P30.7 P30.5
P30.3
P30.1
VFLEXE P31.15 P31.13 P31.11 P31.9
P31.7 P31.5
P31.3
P31.1 VFLEXE VSS
VDDM VSSM
AN48
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AN50
AN52
AN54
NC
NC
NC
VEXT
VEBU
P25.0
P25.1
P25.3
P25.5
P25.9
VSS
VEXT
P26.0
P25.2
P25.4
P25.7
P25.8
P30.14 P30.12 P30.10 P30.8 P30.6 P30.4
P30.2
P30.0 VGATE3P P31.14 P31.12 P31.10 P31.8
P31.6 P31.4
P31.2
P31.0 VFLEXE VSS
VDDM VSSM
AN49
NC
NC
NC
NC
Top-View
AN57
AN58
AN61
AN62
AN64
AN66
AN69
AN56
AN59
AN60
AN63
AN65
AN67
AN68
6
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
NC
VSS
P32.3 P32.2
P32.0
P33.13 P33.11
P33.9
P33.7 P33.5
P33.6 P33.4
P33.3
P33.1
AN5
AN10 VAGND1 VAREF1 VDDM VSSM AN20
AN21
AE
AD
AC
AB
AA
Y
AE
AD
AC
AB
AA
Y
AN25
AN27
VEXT
P23.0
VSS
P32.4 VGATE1P P33.12 P33.10
P33.8
P33.2
P33.0
AN2
AN8
AN11
AN13
AN16
AN18
AN19
AN24
AN26
VEXT
22
21
20
19
18
17
16
15
14
AN3
AN4
13
AN7
AN6
12
AN9
11
10
9
AN29
P25.11 P25.10
P25.13 P25.12
P25.15 P25.14
P23.2 P23.1
P23.4 P23.3
P22.2 P22.3
VSS
P32.7
VSS
P32.6
P32.5
P33.15 P34.5 P34.3
P34.1
AN1
AN14
AN15
AN17
AN22
AN23
NC
AN28
AB
AA
Y
AB
AA
Y
VAREF2
AN33
P23.5
P23.6
P33.14 P34.4 P34.2 VEVRSB AN0
AN12
AN30
AN31
VAGND2
AN35
P23.7
19
18
17
16
15
14
13
12
VSS
(AGBT (AGBT
TX0P)
VSS
VSS
AN39
AN71
NC
AN70
NC
NC
P25.6
P22.0 P22.1
P22.5
P22.4
VDD
VSS
VSS
VDD
AN34
AN32
AN37
W
W
W
W
W
W
W
W
TX0N)
VSS
AN44
AN46
NC
NC
VDDP3 VDD
XTAL1 XTAL2
P22.7
P22.9
P22.6
P22.8
VDD
VSS
VSS
VSS
VDD
VSS
AN38
AN40
AN36
AN41
AN45
AN47
V
U
T
V
U
T
V
U
T
V
U
T
V
U
T
V
U
T
V
U
T
V
U
T
P00.14 P00.15
P24.1
P24.0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(AGBT
ERR)
VSS
(AGBT
CLKN)
P00.11
P00.13
NC
NC
NC
P24.3
P24.2
VSS
TRST
P22.11 P22.10
VSS
VSS
VSS
VSS
AN42
AN43
P00.12
NC
VSS
(AGBT
CLKP)
P00.7
P00.4
P00.2
P24.5
P24.7
P24.9
P24.4
P24.6
P24.8
P21.4 P21.2
P21.5 P21.3
P20.0 P20.2
P21.0
P21.1
P21.6
TMS
TCK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P00.10 P00.8
P01.7 P00.6
P01.5 P01.6
P00.9
P00.5
P00.3
R
P
N
R
P
N
(VDDPSB VSS
)
R
P
N
R
P
N
R
P
N
R
P
N
R
P
N
R
P
N
P01.14 P01.15
P01.12 P01.13
VSS
VDD
VSS
VSS
VDD
(VDDSB)
P21.7
VSS
VSS
17
VSS
VSS
14
VDD
(VDDSB)
P00.0
P01.10 P01.11
M
M
P24.11 P24.10
P20.3 P20.1
PORST
ESR1
VDD
VSS
VSS
P01.3 P01.4
P02.10 P02.11
P00.1
M
M
M
M
M
M
P02.8
P02.6
P02.4
P02.2
P02.0
NC
P01.9 P01.8
P01.2 P01.1
L
K
J
L
K
J
P24.13 P24.12
P24.15 P24.14
P20.8 P20.7
P20.11 P20.10
P20.13 P20.12
P20.14 P15.2
P20.6
P20.9
VSS
ESR0
VSS
P02.7
P02.5
P02.3
P02.1
VSS
L
K
J
L
K
J
L
K
J
19
18
16
15
13
12
L
K
J
VDDFL3
P15.5
P15.8
P14.2 P12.0
P12.1
P11.0 P11.1
P11.7
P11.5
P11.8 P11.13
VSS
P02.9
VSS
P01.0
NC
NC
NC
VEBU
VSS
NC
VEBU
VSS
NC
VDDFL3 P15.7
P14.7 P14.9 P14.10 P11.4 P11.6
P11.14 P11.15 VFLEX
H
G
F
H
G
F
H
G
F
H
G
F
22
21
20
19
18
17
16
15
14
13
12
11
10
9
P02.14 P02.15
P02.12 P02.13
P15.0
VSS VDDP3
P15.3
P14.0
P14.4
P14.3
P14.6 P13.0
P14.8 P13.1
P13.2
P11.3 P11.10 P11.12
P11.2 P11.9 P11.11
P10.1
P10.4
P10.5 P10.8
VEXT
NC
NC
VSS VDDP3 P15.1
P15.4
P15.6
P14.1
P14.5
P13.3
P10.0
P10.3
P10.2 P10.6 P10.7
VEXT
NC
NC
NC
NC
NC
NC
6
E
D
C
B
A
NC
NC
E
D
C
B
A
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
NC
NC
NC
NC
NC
NC
P10.14
NC
VEXT
VSS
VSS
VSS
VDDP3
NC
NC
NC
P15.10 P15.12 P15.14
P15.11 P15.13 P15.15
NC
NC
P14.12 P14.14
P14.13 P14.15
NC
P13.4
P13.6
NC
P13.10 P13.12 P13.14
NC
NC
P10.9 P10.10
P10.13 P10.15
NC
NC
VEXT
NC
VSS
VDDP3
NC
NC
NC
NC
NC
P14.11
NC
P13.5
P13.7 P13.9 P13.11 P13.13 P13.15
15 14 13 12 11
NC
NC
NC
P10.11
6
5
4
3
2
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
10
9
8
7
Figure 2-1 TC299x Logic Symbol for the package variant BGA516.
Data Sheet
TOC-9
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
2.1.1
TC299x BGA516 Package Variant Pin Configuration
Table 2-1 Port 00 Functions
Pin
M6
Symbol
P00.0
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN9
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
HWOU
T
Data Sheet
TOC-10
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
M7
Symbol
P00.1
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN10
ARX3E
ASCLIN3 input
CAN node 1 input
PSI5 input
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN5A
DS5NA
SENT input
CCU60 input
CCU61 input
DSADC channel 5 input
DSADC positive analog input of channel channel 5,
pin A
DSCIN7B
VADCG7.5
CIFD10
P00.1
DSADC channel 7 input
VADC analog input channel 5 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
–
Reserved
DSCOUT5
DSCOUT7
SPC0
DSADC channel 5 output
DSADC channel 7 output
SENT output
CC60
CCU61 output
N6
P00.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN11
SENT1B
DSDIN5A
DSDIN7B
DS5PA
SENT input
DSADC channel 5 input
DSADC channel 7 input
DSADC negative analog input of channel 5, pin A
VADC analog input channel 4 of group 7
CIF input
VADCG7.4
CIFD11
P00.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT11
ASCLK3
TXDCANr1
PSITX0
TXDCAN3
SLSO34
COUT60
ASCLIN3 output
CAN node 1 output (MultiCANr+)
PSI5 output
CAN node 3 output
QSPI3 output
CCU61 output
Data Sheet
TOC-11
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
N7
Symbol
P00.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN12
RXDCAN3A
RXDCANr1A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG7.3
DSITR5F
CIFD12
P00.3
CAN node 3 input
CAN node 1 input (MultiCANr+)
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input
VADC analog input channel 3 of group 7
DSADC channel 5 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
P6
P00.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN13
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG7.2
CIFD13
P00.4
SENT input
DSADC channel 3 input
DSADC channel input
VADC analog input channel 2 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT13
PSISTX
–
PSI5-S output
Reserved
PSITX1
VADCG4BFL0
SPC3
PSI5 output
VADC output
SENT output
COUT61
CCU61 output
Data Sheet
TOC-12
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
P7
Symbol
P00.5
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN14
PSIRX2A
SENT4B
CC62INB
CC62INA
DSCIN2A
VADCG7.1
CIFD14
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 2 input
VADC analog input channel 1 of group 7
CIF input
P00.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT14
DSCGPWMN
SLSO33
DSCOUT2
VADCG4BFL1
SPC4
DSADC output
QSPI3 output
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
P9
P00.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN15
SENT5B
DSDIN2A
VADCG7.0
SENT input
DSADC channel 2 input A
VADC analog input channel 0 of group 7 (with pull
down diagnostics)
DSITR4F
CIFD15
DSADC channel 4 input F
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG4BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
CCU61 output
Data Sheet
TOC-13
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
R6
Symbol
P00.7
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN16
SENT6B
CC60INC
CCPOS0A
T12HRB
T2INA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSCIN4A
DS4NA
VADCG6.5
CIFCLK
P00.7
DSADC channel 4 input A
DSADC negative analog input channel 4, pin A
VADC analog input channel 5 of group 6
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG4BFL3
DSCOUT4
VADCEMUX11
SPC6
VADC output
DSADC channel 4 output
VADC output
SENT output
CC60
CCU61 output
R9
P00.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN17
SENT7B
CC61INC
CCPOS1A
T13HRB
T2EUDA
DSDIN4A
DS4PA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSADC channel 4 input A
DSADC positive analog input of channel 4, pin A
VADC analog input channel 4 of group 6
CIF input
VADCG6.4
CIFVSNC
P00.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
SPC7
VADC output
SENT output
CC61
CCU61 output
Data Sheet
TOC-14
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
R7
Symbol
P00.9
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN18
SENT8B
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
DSCIN1A
VADCG6.3
DSITR3F
CIFHSNC
P00.9
SENT input
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
DSADC channel 1 input A
VADC analog input channel 3 of group 6
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
DSCOUT1
–
QSPI3 output
ASCLIN3 output
DSADC channel 1 output
Reserved
SPC8
SENT output
CC62
CCU61 output
R10
P00.10
TIN19
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT9B
DSDIN1A
VADCG6.2
P00.10
TOUT19
–
SENT input
DSADC channel 1 input A
VADC analog input channel 2 of group 6
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
SPC9
SENT output
COUT63
CCU61 output
Data Sheet
TOC-15
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
T6
Symbol
Ctrl
Type
Function
P00.11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN20
CTRAPA
CCU60 input
T12HRE
CCU61 input
DSCIN0A
DSADC channel 0 input A
VADC analog input channel 1 of group 6
General-purpose output
GTM output
VADCG6.1
P00.11
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT20
–
Reserved
–
Reserved
DSCOUT0
DSADC channel 0 output
Reserved
–
–
Reserved
–
Reserved
T7
P00.12
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN21
ACTS3A
ASCLIN3 input
DSADC channel 0 input A
VADC analog input channel 0 of group 6
General-purpose output
GTM output
DSDIN0A
VADCG6.0
P00.12
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT21
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
General-purpose input
GTM input
T2
P00.13
MP+ /
PU1 /
VEXT
TIN167
DSDIN6A
DSADC channel 6 input A
General-purpose output
GTM output
P00.13
O0
O1
O2
O3
O4
O5
O6
O7
TOUT167
–
Reserved
–
Reserved
EXTCLK1
SCU output
–
–
–
Reserved
Reserved
Reserved
Data Sheet
TOC-16
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-1 Port 00 Functions (cont’d)
Pin
U2
Symbol
Ctrl
Type
Function
P00.14
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN166
DSCIN6A
DSADC channel 6 input A
General-purpose output
GTM output
P00.14
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT166
–
Reserved
–
Reserved
DSCOUT6
DSADC channel 6 output
Reserved
–
–
Reserved
–
Reserved
U1
P00.15
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN168
DSITR6F
DSADC channel 6 input F
General-purpose output
GTM output
P00.15
O0
O1
O2
O3
O4
O5
O6
O7
TOUT168
–
Reserved
–
Reserved
EXTCLK0
SCU output
–
–
–
Reserved
Reserved
Reserved
Table 2-2 Port 01 Functions
Pin
J2
Symbol
Ctrl
Type
Function
P01.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN155
DSITR6E
DSADC channel 6 input E
CAN node 3 input
CAN node 1 input (MultiCANr+)
General-purpose output
GTM output
RXDCAN3F
RXDCANr1E
P01.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT155
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-17
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-2 Port 01 Functions (cont’d)
Pin
K1
Symbol
P01.1
TIN159
DSITR8E
RXD1A1
SENT10B
P01.1
TOUT159
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSADC channel 8 input E
ERAY1 input
SENT input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
K2
P01.2
TIN156
DSCIN7A
P01.2
TOUT156
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSADC channel 7 input A
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
TXDCAN3
–
CAN node 3 output
Reserved
TXDCANr1
DSCOUT7
–
CAN node 1 output (MultiCANr+)
DSADC channel 7 output
Reserved
M10
P01.3
TIN111
SLSI3B
DSITR7F
P01.3
TOUT111
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 7 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
SLSO39
TXDCAN1
–
QSPI3 output
CAN node 1 output
Reserved
–
Reserved
Data Sheet
TOC-18
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-2 Port 01 Functions (cont’d)
Pin
M9
Symbol
Ctrl
Type
Function
P01.4
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN112
RXDCAN1C
CAN node 1 input
DSADC channel 7 input E
General-purpose output
GTM output
DSITR7E
P01.4
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT112
–
Reserved
–
Reserved
SLSO310
QSPI3 output
Reserved
–
–
Reserved
–
Reserved
N10
P01.5
TIN113
MRST3C
DSCIN8A
P01.5
TOUT113
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 8 input A
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
MRST3
–
QSPI3 output
Reserved
DSCOUT8
–
DSADC channel 8 output
Reserved
N9
P01.6
TIN114
MTSR3C
DSDIN8A
P01.6
TOUT114
–
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 8 input A
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
MTSR3
–
QSPI3 output
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-19
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-2 Port 01 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
P10
P01.7
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN115
SCLK3C
QSPI3 input
DSITR8F
DSADC channel 8 input F
General-purpose output
GTM output
P01.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT115
–
Reserved
–
Reserved
SCLK3
QSPI3 output
Reserved
–
–
Reserved
–
Reserved
L1
P01.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN162
DSDIN9A
DSADC channel 9 input A
SENT input
SENT12B
ARX0C
ASCLIN0 input
CAN node 0 input
CAN node 0 input (MultiCANr+)
ERAY1 input
RXDCAN0F
RXDCANr0E
RXD1B1
P01.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT162
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-20
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-2 Port 01 Functions (cont’d)
Pin
L2
Symbol
Ctrl
Type
Function
P01.9
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN160
DSCIN9A
DSADC channel 9 input A
SENT input
SENT11B
P01.9
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT160
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DSCOUT9
DSADC channel 9 output
Reserved
–
M2
P01.10
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN163
DSITR9F
DSADC channel 9 input F
SENT input
SENT13B
P01.10
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT163
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
M1
P01.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN165
DSITR9E
DSADC channel 9 input E
SENT input
SENT14B
P01.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT165
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-21
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-2 Port 01 Functions (cont’d)
Pin
N2
Symbol
P01.12
TIN158
P01.12
TOUT158
–
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
TXD1A
–
ERAY1 output
Reserved
N1
P01.13
TIN161
P01.13
TOUT161
ATX0
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
TXDCAN0
TXDCANr0
TXD1B
–
CAN node 0 output
CAN node 0 output (MultiCANr+)
ERAY1 output
Reserved
P2
P01.14
TIN164
P01.14
TOUT164
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
TXEN1A
–
ERAY1 output
Reserved
Data Sheet
TOC-22
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-2 Port 01 Functions (cont’d)
Pin
P1
Symbol
Ctrl
Type
Function
P01.15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN157
DSDIN7A
DSADC channel 7 input A
General-purpose output
GTM output
P01.15
O0
O1
O2
O3
O4
O5
O6
O7
TOUT157
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-3 Port 02 Functions
Pin
G6
Symbol
P02.0
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN0
REQ6
SCU input
ARX2G
CC60INA
CC60INB
CIFD0
ASCLIN2 input
CCU60 input
CCU61 input
CIF input
P02.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY0 output
CCU60 output
SLSO31
DSCGPWMN
TXDCAN0
TXD0A
CC60
Data Sheet
TOC-23
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-3 Port 02 Functions (cont’d)
Pin
H7
Symbol
P02.1
Ctrl
Type
Function
I
LP / PU1 General-purpose input
/ VEXT
TIN1
GTM input
REQ14
ARX2B
RXDCAN0A
RXD0A2
CIFD1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY0 input
CIF input
P02.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT1
SLSO47
SLSO32
DSCGPWMP
–
QSPI4 output
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
P02.2
CCU60 output
H6
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN2
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
PSI5 output
SLSO33
PSITX0
TXDCAN2
TXD0B
CC61
CAN node 2 output
ERAY0 output
CCU60 output
Data Sheet
TOC-24
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-3 Port 02 Functions (cont’d)
Pin
J7
Symbol
P02.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN3
ARX1G
RXDCAN2B
RXD0B2
PSIRX0B
DSCIN5B
SDI11
ASCLIN1 input
CAN node 2 input
ERAY0 input
PSI5 input
DSADC channel 5 input B
MSC1 input
CIFD3
CIF input
P02.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
DSCOUT5
–
ASCLIN2 output
QSPI3 output
DSADC channel 5 output
Reserved
–
Reserved
COUT61
P02.4
CCU60 output
General-purpose input
GTM input
J6
MP+ /
PU1 /
VEXT
TIN4
SLSI3A
ECTT1
RXDCAN0D
CC62INA
CC62INB
DSDIN5B
SDA0A
CIFD4
QSPI3 input
TTCAN input
CAN node 0 input
CCU60 input
CCU61 input
DSADC channel 5 input B
I2C0 input
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXEN0A
CC62
ERAY0 output
CCU60 output
Data Sheet
TOC-25
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-3 Port 02 Functions (cont’d)
Pin
K7
Symbol
P02.5
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN5
MRST3A
ECTT2
QSPI3 input
TTCAN input
PSIRX1B
PSISRXB
SENT3C
DSCIN4B
SCL0A
PSI5 input
PSI5-S input
SENT input
DSADC channel 4 input B
I2C0 input
CIFD5
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
DSCOUT4
SCL0
CAN node 0 output
QSPI3 output
DSADC channel 4 output
I2C0 output
TXEN0B
COUT62
P02.6
ERAY0 output
CCU60 output
General-purpose input
GTM input
K6
MP /
PU1 /
VEXT
TIN6
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
DSDIN4B
DSITR5E
P02.6
DSADC channel 4 input B
DSADC channel 5 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
Data Sheet
TOC-26
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-3 Port 02 Functions (cont’d)
Pin
L7
Symbol
P02.7
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN7
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
DSITR4E
P02.7
DSADC channel 3 input B
DSADC channel 4 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSCOUT3
VADCEMUX01
SPC1
DSADC channel 3 output
VADC output
SENT output
CC61
CCU60 output
Data Sheet
TOC-27
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-3 Port 02 Functions (cont’d)
Pin
L6
Symbol
P02.8
Ctrl
Type
Function
I
LP / PU1 General-purpose input
/
TIN8
GTM input
VEXT
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
CIFD8
DSDIN3B
DSITR3E
P02.8
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
K9
P02.9
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN116
P02.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT116
ATX2
ASCLIN2 output
Reserved
–
–
Reserved
TXDCAN1
–
CAN node 1 output
Reserved
–
Reserved
Data Sheet
TOC-28
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-3 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
L10
P02.10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN117
ARX2C
ASCLIN2 input
CAN node 1 input
General-purpose output
GTM output
Reserved
RXDCAN1E
P02.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT117
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
L9
P02.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN118
P02.11
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT118
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
F2
P02.12
TIN151
P02.12
TOUT151
SLSO35
SLSO44
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
QSPI3 output
QSPI4 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-29
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-3 Port 02 Functions (cont’d)
Pin
F1
Symbol
P02.13
TIN153
P02.13
TOUT153
SLSO37
SLSO46
TXDCAN0
TXDCANr0
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
QSPI3 output
QSPI4 output
CAN node 0 output
CAN node 0 output (MultiCANr+)
Reserved
–
Reserved
G2
P02.14
TIN154
RXDCAN0H
RXDCANr0D
P02.14
TOUT154
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
CAN node 0 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
G1
P02.15
TIN152
P02.15
TOUT152
SLSO36
SLSO45
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
QSPI3 output
QSPI4 output
Reserved
–
Reserved
TXEN1B
–
ERAY1 output
Reserved
Data Sheet
TOC-30
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-4 Port 10 Functions
Pin
Symbol
P10.0
Ctrl
Type
Function
F12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN102
T6EUDB
P10.0
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT102
–
Reserved
SLSO110
–
QSPI1 output
Reserved
VADCG6BFL0
–
VADC output
Reserved
–
Reserved
G12
P10.1
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL1
END03
–
F10
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
REQ2
QSPI1 input
GPT120 input
SCU input
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL2
END02
–
Data Sheet
TOC-31
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-4 Port 10 Functions (cont’d)
Pin
Symbol
P10.3
Ctrl
Type
Function
F11
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG6BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
G11
P10.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN106
MTSR1C
CCPOS0C
T3INB
QSPI1 input
CCU60 input
GPT120 input
General-purpose output
GTM output
P10.4
O0
O1
O2
O3
O4
O5
O6
O7
TOUT106
–
Reserved
SLSO18
MTSR1
EN00
QSPI1 output
QSPI1 output
MSC0 output
MSC0 output
Reserved
END02
–
Data Sheet
TOC-32
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-4 Port 10 Functions (cont’d)
Pin
Symbol
P10.5
Ctrl
Type
Function
G10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
RXDCANr0A
INJ01
SCU input
CAN node 0 input (MultiCANr+)
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
SLSO38
SLSO19
T6OUT
QSPI1 output
GPT120 output
ASCLIN2 output
PSI5 output
ASLSO2
PSITX3
P10.6
F9
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
ASCLIN2 input
QSPI3 input
MTSR3B
PSIRX3C
HWCFG5
P10.6
PSI5 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
ASCLIN2 output
QSPI3 output
T3OUT
GPT120 output
CAN node 0 output (MultiCANr+)
QSPI1 output
TXDCANr0
MRST1
VADCG7BFL0
VADC output
Data Sheet
TOC-33
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-4 Port 10 Functions (cont’d)
Pin
F8
Symbol
P10.7
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN109
ACTS2A
MRST3B
REQ4
ASCLIN2 input
QSPI3 input
SCU input
CCPOS1C
T3EUDB
P10.7
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT109
–
Reserved
MRST3
VADCG7BFL1
TXDCANr0
–
QSPI3 output
VADC output
CAN node 0 output (MultiCANr+)
Reserved
–
Reserved
G9
P10.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN110
SCLK3B
REQ5
QSPI3 input
SCU input
CCPOS2C
T4INB
RXDCANr0B
P10.8
CCU60 input
GPT120 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT110
ARTS2
SCLK3
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-34
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-4 Port 10 Functions (cont’d)
Pin
B8
Symbol
Ctrl
Type
Function
P10.9
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN265
SENT10C
SENT input
General-purpose output
GTM output
Reserved
P10.9
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT265
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
B7
P10.10
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN266
SENT11C
SENT input
General-purpose output
GTM output
Reserved
P10.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT266
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
A7
P10.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN269
SENT14C
SENT input
General-purpose output
GTM output
Reserved
P10.11
O0
O1
O2
O3
O4
O5
O6
O7
TOUT269
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-35
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-4 Port 10 Functions (cont’d)
Pin
A6
Symbol
Ctrl
Type
Function
P10.13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN268
SENT13C
SENT input
General-purpose output
GTM output
Reserved
P10.13
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT268
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
B5
P10.14
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN267
SENT12C
SENT input
General-purpose output
GTM output
Reserved
P10.14
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT267
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
A5
P10.15
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN270
P10.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT270
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-36
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-5 Port 11 Functions
Pin
Symbol
P11.0
TIN119
ARX3B
P11.0
TOUT119
ATX3
Ctrl
Type
Function
K15
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
ASCLIN3 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
ETHTXD3
–
ETH output
Reserved
K14
P11.1
TIN120
P11.1
TOUT120
ASCLK3
ATX3
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
–
–
Reserved
ETHTXD2
–
ETH output
Reserved
F15
P11.2
TIN95
P11.2
TOUT95
END03
SLSO05
SLSO15
EN01
MPR/
PU1 /
VFLEX
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
CCU60 output
Data Sheet
TOC-37
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-5 Port 11 Functions (cont’d)
Pin
Symbol
P11.3
TIN96
MRST1B
SDI03
P11.3
TOUT96
–
Ctrl
Type
Function
G15
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST1
TXD0A
–
QSPI1 output
ERAY0 output
Reserved
ETHTXD0
COUT62
P11.4
TIN121
ETHRXCLKB
P11.4
TOUT121
ASCLK3
–
ETH output
CCU60 output
General-purpose input
GTM input
J15
MP+ /
PU1 /
VFLEX
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
ETHTXER
–
ETH output
Reserved
J13
P11.5
TIN122
ETHTXCLKA
P11.5
TOUT122
–
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-38
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-5 Port 11 Functions (cont’d)
Pin
J14
Symbol
P11.6
TIN97
SCLK1B
P11.6
TOUT97
TXEN0B
SCLK1
TXEN0A
FCLP0
ETHTXEN
COUT61
P11.7
TIN123
ETHRXD3
P11.7
TOUT123
–
Ctrl
Type
Function
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
General-purpose output
GTM output
ERAY0 output
QSPI1 output
ERAY0 output
MSC0 output
ETH output
O0
O1
O2
O3
O4
O5
O6
O7
I
CCU60 output
General-purpose input
GTM input
K13
LP /
PU1 /
VFLEX
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
K12
P11.8
TIN124
ETHRXD2
P11.8
TOUT124
–
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-39
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-5 Port 11 Functions (cont’d)
Pin
Symbol
P11.9
Ctrl
Type
Function
F14
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
TIN98
MTSR1B
RXD0A1
ETHRXD1
P11.9
QSPI1 input
ERAY0 input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT98
–
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
MSC0 output
Reserved
–
COUT60
P11.10
TIN99
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXD0B1
ETHRXD0
SDI00
P11.10
TOUT99
–
CCU60 output
General-purpose input
GTM input
G14
LP /
PU1 /
VFLEX
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY0 input
ETH input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
Data Sheet
TOC-40
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-5 Port 11 Functions (cont’d)
Pin
Symbol
P11.11
Ctrl
Type
Function
F13
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
TIN100
ETHCRSDVA
ETHRXDVA
ETHCRSB
P11.11
ETH input
ETH input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT100
END02
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY0 output
CCU60 output
General-purpose input
GTM input
SLSO04
SLSO14
EN00
TXEN0B
CC61
G13
P11.12
MPR /
PU1 /
VFLEX
TIN101
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
ETHRXCLKA
ETH input
(Not for productive purposes)
P11.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT101
ATX1
ASCLIN1 output
GTM output
GTMCLK2
TXD0B
ERAY0 output
CAN node 3 output
SCU output
TXDCAN3
EXTCLK1
CC60
CCU60 output
Data Sheet
TOC-41
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-5 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
K11
P11.13
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN125
ETHRXERA
ETH input
SDA1A
I2C1 input
P11.13
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT125
–
–
Reserved
–
Reserved
–
Reserved
SDA1
I2C1 output
Reserved
–
J12
P11.14
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN126
ETHCRSDVB
ETH input
ETHRXDVB
ETH input
ETHCRSA
ETH input
SCL1A
I2C1 input
P11.14
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT126
–
–
Reserved
–
Reserved
–
Reserved
SCL1
I2C1 output
Reserved
–
J11
P11.15
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN127
ETHCOL
ETH input
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT127
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-42
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-6 Port 12 Functions
Pin
Symbol
Ctrl
Type
Function
K17
P12.0
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN128
ETHRXCLKC
ETH input
RXDCAN0C
CAN node 0 input
General-purpose output
GTM output
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT128
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDC
ETH output
–
Reserved
K16
P12.1
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN129
P12.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT129
ASLSO3
ASCLIN3 output
Reserved
–
–
Reserved
TXDCAN0
CAN node 0 output
Reserved
–
–
Reserved
ETHMDIOC
HWOU
T
ETH input/output
Table 2-7 Port 13 Functions
Pin
Symbol
P13.0
Ctrl
Type
Function
G17
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN91
P13.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT91
END03
SCLK2N
EN01
MSC0 output
QSPI2 output (LVDS)
MSC0 output
FCLN0
FCLND0
–
MSC0 output (LVDS)
MSC0 output (LVDS)
Reserved
Data Sheet
TOC-43
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-7 Port 13 Functions (cont’d)
Pin
Symbol
P13.1
TIN92
SCL0B
P13.1
TOUT92
–
Ctrl
Type
Function
F17
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
–
MSC0 output (LVDS)
I2C0 output
Reserved
G16
P13.2
TIN93
CAPINA
SDA0B
P13.2
TOUT93
–
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MTSR2N
FCLP0
SON0
SDA0
SOND0
P13.3
TIN94
P13.3
TOUT94
–
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
MSC0 output (LVDS)
General-purpose input
GTM input
F16
LVDSM_P /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR2P
–
QSPI2 output (LVDS)
Reserved
SOP0
–
MSC0 output (LVDS)
Reserved
–
Reserved
Data Sheet
TOC-44
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-7 Port 13 Functions (cont’d)
Pin
Symbol
P13.4
TIN253
PSIRX4A
P13.4
TOUT253
END22
–
Ctrl
Type
Function
B16
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
PSI5 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC2 output
Reserved
EN20
FCLN2
FCLND2
–
MSC2 output
MSC2 output (LVDS)
MSC2 output (LVDS)
Reserved
A16
P13.5
TIN254
P13.5
TOUT254
–
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
FCLP2
–
MSC2 output (LVDS)
Reserved
–
Reserved
B15
P13.6
TIN255
P13.6
TOUT255
–
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
SON2
SOND2
–
MSC2 output (LVDS)
MSC2 output (LVDS)
Reserved
Data Sheet
TOC-45
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-7 Port 13 Functions (cont’d)
Pin
Symbol
P13.7
TIN256
P13.7
TOUT256
–
Ctrl
Type
Function
A15
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
SOP2
–
MSC2 output (LVDS)
Reserved
–
Reserved
A14
P13.9
TIN248
SCL1B
P13.9
TOUT248
ATX3
SLSO55
–
MP /
PU1 /
VEXT
General-purpose input
GTM input
I2C1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI5 output
Reserved
TXDCANr1
SCL1
–
CAN node 1 output (MultiCANr+)
I2C1 output
Reserved
B13
P13.10
TIN251
PSIRX3A
P13.10
TOUT251
ATX0
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSI5 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-46
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-7 Port 13 Functions (cont’d)
Pin
Symbol
P13.11
TIN250
ARX0E
P13.11
TOUT250
–
Ctrl
Type
Function
A13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
–
Reserved
PSITX3
–
PSI5 output
Reserved
–
Reserved
B12
P13.12
TIN249
ARX3H
RXDCANr1B
SDA1B
P13.12
TOUT249
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN3 input
CAN node 1 input (MultiCANr+)
I2C1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
SDA1
–
I2C1 output
Reserved
A12
P13.13
TIN262
PSIRX3B
INJ20
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSI5 input
MSC2 input
P13.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT262
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-47
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-7 Port 13 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
B11
P13.14
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN252
P13.14
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT252
–
SLSO54
QSPI5 output
Reserved
–
–
Reserved
–
Reserved
–
Reserved
A11
P13.15
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN264
P13.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT264
–
–
Reserved
PSITX3
PSI5 output
Reserved
–
–
–
Reserved
Reserved
Table 2-8 Port 14 Functions
Pin
Symbol
P14.0
Ctrl
Type
Function
G21
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN80
SENT12D
P14.0
SENT input
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin
TXD0A
O3
O4
O5
ERAY0 output
ERAY0 output
TXD0B
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function
ASCLK0
COUT62
O6
O7
ASCLIN0 output
CCU60 output
Data Sheet
TOC-48
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-8 Port 14 Functions (cont’d)
Pin
Symbol
P14.1
Ctrl
Type
Function
F20
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN81
REQ15
SENT13D
ARX0A
SCU input
SENT input
ASCLIN0 input
Recommended as Boot loader pin
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function
RXD0A3
RXD0B3
EVRWUPA
P14.1
ERAY0 input
ERAY0 input
SCU input
O0
O1
O2
General-purpose output
GTM output
TOUT81
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
–
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
P14.2
TIN82
CCU60 output
General-purpose input
GTM input
K18
LP /
PU1 /
VEXT
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
SLSO21
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
Data Sheet
TOC-49
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-8 Port 14 Functions (cont’d)
Pin
Symbol
P14.3
Ctrl
Type
Function
G19
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN83
ARX2A
REQ10
HWCFG3_BMI
SDI02
ASCLIN2 input
SCU input
SCU input
MSC0 input
P14.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT83
ATX2
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
G20
P14.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN84
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT84
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-50
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-8 Port 14 Functions (cont’d)
Pin
Symbol
P14.5
Ctrl
Type
Function
F19
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN85
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
TOUT85
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
TXD0B
TXD1B
P14.6
TIN86
ERAY0 output
ERAY1 output
General-purpose input
GTM input
G18
MP+ /
PU1 /
VEXT
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
TOUT86
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO22
–
QSPI2 output
Reserved
–
Reserved
TXEN0B
TXEN1B
P14.7
TIN87
RXD0B0
RXD1B0
P14.7
TOUT87
ARTS0
SLSO24
–
ERAY0 output
ERAY1 output
General-purpose input
GTM input
J18
LP /
PU1 /
VEXT
ERAY0 input
ERAY1 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-51
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-8 Port 14 Functions (cont’d)
Pin
Symbol
P14.8
TIN88
ARX1D
RXDCAN2D
RXD0A0
RXD1A0
P14.8
TOUT88
–
Ctrl
Type
Function
F18
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
CAN node 2 input
ERAY0 input
ERAY1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
J17
P14.9
TIN89
ACTS0A
P14.9
TOUT89
END03
EN01
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
MSC0 output
MSC0 output
Reserved
–
TXEN0B
TXEN0A
TXEN1A
P14.10
TIN90
P14.10
TOUT90
END02
EN00
ERAY0 output
ERAY0 output
ERAY1 output
General-purpose input
GTM input
J16
MP+ /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
MSC0 output
ASCLIN1 output
CAN node 2 output
ERAY0 output
ERAY1 output
ATX1
TXDCAN2
TXD0A
TXD1A
Data Sheet
TOC-52
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-8 Port 14 Functions (cont’d)
Pin
Symbol
P14.11
TIN258
P14.11
TOUT258
END20
PSITX4
EN22
SOP2
–
Ctrl
Type
Function
A20
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC2 output
PSI5 output
MSC2 output
MSC2 output
Reserved
–
Reserved
B19
P14.12
TIN261
SDI20
P14.12
TOUT261
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
MSC2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
A19
P14.13
TIN260
P14.13
TOUT260
END23
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC2 output
Reserved
EN21
–
MSC2 output
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-53
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-8 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
B18
P14.14
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN259
P14.14
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT259
END22
MSC2 output
Reserved
–
EN20
MSC2 output
Reserved
–
–
Reserved
–
Reserved
A18
P14.15
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN263
INJ21
MSC2 output
General-purpose output
GTM output
P14.15
O0
O1
O2
O3
O4
O5
O6
O7
TOUT263
ATX1
ASCLIN1 output
Reserved
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Table 2-9 Port 15 Functions
Pin
Symbol
P15.0
Ctrl
Type
Function
G25
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN71
P15.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT71
ATX1
ASCLIN1 output
QSPI0 output
Reserved
SLSO013
–
TXDCAN2
ASCLK1
–
CAN node 2 output
ASCLIN1 output
Reserved
Data Sheet
TOC-54
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-9 Port 15 Functions (cont’d)
Pin
Symbol
P15.1
Ctrl
Type
Function
F23
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN72
REQ16
ARX1A
RXDCAN2A
SLSI2B
EVRWUPB
P15.1
SCU input
ASCLIN1 input
CAN node 2 input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT72
ATX1
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
Reserved
–
Reserved
–
Reserved
H24
P15.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN73
SLSI2A
MRST2E
SENT10D
HSIC2INA
P15.2
QSPI2 input
QSPI2 input
SENT input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT73
ATX0
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
Data Sheet
TOC-55
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-9 Port 15 Functions (cont’d)
Pin
Symbol
P15.3
Ctrl
Type
Function
G22
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN74
ARX0B
SCLK2A
RXDCAN1A
HSIC2INB
P15.3
ASCLIN0 input
QSPI2 input
CAN node 1 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT74
ATX0
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
F22
P15.4
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN75
MRST2A
REQ0
SCL0C
SENT11D
P15.4
QSPI2 input
SCU input
I2C0 input
SENT input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT75
ATX1
ASCLIN1 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
SCL0
I2C0 output
CC62
CCU60 output
Data Sheet
TOC-56
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-9 Port 15 Functions (cont’d)
Pin
Symbol
P15.5
Ctrl
Type
Function
K19
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN76
ARX1B
MTSR2A
REQ13
SDA0C
P15.5
ASCLIN1 input
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT76
ATX1
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
General-purpose input
GTM input
F21
P15.6
MP /
PU1 /
VEXT
TIN77
MTSR2B
P15.6
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT77
ATX3
ASCLIN3 output
QSPI2 output
QSPI5 output
QSPI2 output
ASCLIN3 output
CCU60 output
General-purpose input
GTM input
MTSR2
SLSO53
SCLK2
ASCLK3
CC60
J20
P15.7
MP /
PU1 /
VEXT
TIN78
ARX3A
MRST2B
P15.7
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT78
ATX3
ASCLIN3 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
TOC-57
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-9 Port 15 Functions (cont’d)
Pin
J19
Symbol
P15.8
TIN79
SCLK2B
REQ1
P15.8
TOUT79
–
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
P15.10
TIN242
MRST5A
P15.10
TOUT242
–
ASCLIN3 output
CCU60 output
General-purpose input
GTM input
B24
LP /
PU1 /
VEXT
QSPI5 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
MRST5
–
QSPI5 output
Reserved
–
Reserved
–
Reserved
–
Reserved
A24
P15.11
TIN243
SLSI5A
P15.11
TOUT243
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI5 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
SLSO52
–
QSPI5 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-58
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-9 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
B23
P15.12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN244
P15.12
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT244
–
SLSO51
QSPI5 output
Reserved
–
–
Reserved
–
Reserved
–
Reserved
A23
P15.13
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN245
P15.13
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT245
–
SLSO50
QSPI5 output
Reserved
–
–
Reserved
–
Reserved
–
Reserved
B22
P15.14
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN246
MTSR5A
QSPI5 input
General-purpose output
GTM output
Reserved
P15.14
O0
O1
O2
O3
O4
O5
O6
O7
TOUT246
–
MTSR5
QSPI5 output
Reserved
–
–
–
–
Reserved
Reserved
Reserved
Data Sheet
TOC-59
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-9 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
A22
P15.15
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN247
SCLK5A
QSPI5 input
General-purpose output
GTM output
Reserved
P15.15
O0
O1
O2
O3
O4
O5
O6
O7
TOUT247
–
SCLK5
QSPI5 output
Reserved
–
–
–
–
Reserved
Reserved
Reserved
Table 2-10 Port 20 Functions
Pin
Symbol
P20.0
Ctrl
Type
Function
N25
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN59
RXDCAN3C
RXDCANr1C
T6EUDA
REQ9
CAN node 3 input
CAN node 1 input (MultiCANr+)
GPT120 input
SCU input
SYSCLK
TGI0
HSCT input
OCDS input
P20.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT59
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
Data Sheet
TOC-60
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-10 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
M24
P20.1
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN60
TGI1
OCDS input
General-purpose output
GTM output
Reserved
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
TOUT60
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO1
HWOU
T
OCDS; ENx
N24
P20.2
I
LP /
General-purpose input
PU1 /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
OCDS input
P20.2
O0
O1
O2
O3
O4
O5
O6
O7
I
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
General-purpose input
GTM input
–
–
–
–
–
–
–
M25
P20.3
TIN61
T6INA
ARX3C
P20.3
TOUT61
ATX3
SLSO09
SLSO29
TXDCAN3
TXDCANr1
–
LP /
PU1 /
VEXT
GPT120 input
ASCLIN3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
QSPI0 output
QSPI2 output
CAN node 3 output
CAN node 1 output (MultiCANr+)
Reserved
Data Sheet
TOC-61
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-10 Port 20 Functions (cont’d)
Pin
Symbol
P20.6
Ctrl
Type
Function
L22
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN62
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT62
ARTS1
SLSO08
SLSO28
–
ASCLIN1 output
QSPI0 output
QSPI2 output
Reserved
WDT2LCK
–
SCU output
Reserved
L24
P20.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN63
ACTS1A
RXDCAN0B
P20.7
ASCLIN1 input
CAN node 0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT63
–
Reserved
–
Reserved
–
Reserved
–
Reserved
WDT1LCK
COUT63
P20.8
SCU output
CCU61 output
General-purpose input
GTM input
L25
MP /
PU1 /
VEXT
TIN64
P20.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT64
ASLSO1
SLSO00
SLSO10
TXDCAN0
WDT0LCK
CC60
ASCLIN1 output
QSPI0 output
QSPI1 output
CAN node 0 output
SCU output
CCU61 output
Data Sheet
TOC-62
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-10 Port 20 Functions (cont’d)
Pin
Symbol
P20.9
Ctrl
Type
Function
K22
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN65
ARX1C
RXDCAN3E
REQ11
SLSI0B
P20.9
ASCLIN1 input
CAN node 3 input
SCU input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT65
–
Reserved
SLSO01
SLSO11
–
QSPI0 output
QSPI1 output
Reserved
WDTSLCK
CC61
SCU output
CCU61 output
General-purpose input
GTM input
K24
P20.10
TIN66
P20.10
TOUT66
ATX1
MP /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
CAN node 3 output
ASCLIN1 output
CCU61 output
General-purpose input
GTM input
SLSO06
SLSO27
TXDCAN3
ASCLK1
CC62
K25
P20.11
TIN67
SCLK0A
P20.11
TOUT67
–
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
COUT60
CCU61 output
Data Sheet
TOC-63
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-10 Port 20 Functions (cont’d)
Pin
J24
Symbol
P20.12
TIN68
MRST0A
P20.12
TOUT68
–
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST0
MTSR0
–
QSPI0 output
QSPI0 output
Reserved
–
Reserved
COUT61
P20.13
TIN69
SLSI0A
P20.13
TOUT69
–
CCU61 output
General-purpose input
GTM input
J25
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO02
SLSO12
SCLK0
–
QSPI0 output
QSPI1 output
QSPI0 output
Reserved
COUT62
P20.14
TIN70
MTSR0A
P20.14
TOUT70
–
CCU61 output
General-purpose input
GTM input
H25
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-64
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-11 Port 21 Functions
Pin
Symbol
P21.0
TIN51
MRST4DN
HOLD
P21.0
TOUT51
–
Ctrl
Type
Function
R22
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
QSPI4 input (LVDS)
EBU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDC
BAABA0
ETH output
EBU output
(combined for BAA and BA0)
HSM1
O
I
HSM output
P22
P21.1
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
TIN52
ETHMDIOB
ETH input
(Not for production purposes)
MRST4DP
QSPI4 input (LVDS)
EBU input
WAIT
P21.1
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM output
Reserved
TOUT52
–
–
Reserved
–
Reserved
–
Reserved
ETHMDIO
ETH output
(Not for production purposes)
BREQBA1
HSM2
O7
O
EBU output
(combined for BREQ and BA1)
HSM output
Data Sheet
TOC-65
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-11 Port 21 Functions (cont’d)
Pin
Symbol
P21.2
Ctrl
Type
Function
R24
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
TIN53
MRST2CN
MRST4CN
ARX3GN
EMGSTOPB
RXDN
P21.2
QSPI2 input (LVDS)
QSPI4 input (LVDS)
ASCLIN3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT53
ASLSO3
–
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
SDRAMA8
–
ETH output
EBU output
Reserved
P24
P21.3
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
TIN54
MRST2CP
MRST4CP
ARX3GP
RXDP
P21.3
QSPI2 input (LVDS)
QSPI4 input (LVDS)
ASCLIN3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
O0
TOUT54
–
O1
O2
Reserved
–
O3
Reserved
–
O4
Reserved
–
O5
Reserved
SDRAMA9
–
O6
EBU output
O7
Reserved
ETHMDIOD
HWOUT
ETH input/output
Data Sheet
TOC-66
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-11 Port 21 Functions (cont’d)
Pin
Symbol
P21.4
TIN55
P21.4
TOUT55
–
Ctrl
Type
Function
R25
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
SDRAMA10
–
EBU output
Reserved
TXDN
P21.5
TIN56
P21.5
TOUT56
ASCLK3
–
HSCT output (LVDS)
General-purpose input
GTM input
P25
LVDSH_P/
PU1 /
VDDP3
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
SDRAMA11
–
EBU output
Reserved
TXDP
P21.6
TIN57
ARX3F
TGI2
HSCT output (LVDS)
General-purpose input
GTM input
N22
A2 /
PU /
VDDP3
ASCLIN3 input
OCDS input
TDI
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
TOUT57
ASLSO3
–
O0
O1
O2
ASCLIN3 output
Reserved
O3
–
O4
Reserved
SYSCLK
SDRAMA12
T3OUT
TGO2
O5
HSCT output
EBU output
O6
O7
GPT120 output
OCDS; ENx
HWOUT
Data Sheet
TOC-67
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-11 Port 21 Functions (cont’d)
Pin
Symbol
P21.7
Ctrl
Type
Function
N21
I
A2 /
PU /
VDDP3
General-purpose input
GTM input
TIN58
DAP2
OCDS (3-Pin DAP) input
In the 3-Pin DAP mode this pin is used as DAP2.
In the 2-PIN DAP mode this pin is used as P21.7
and controlled by the related port control logic
TGI3
OCDS input
ETHRXERB
T5INA
P21.7
ETH input
GPT120 input
General-purpose output
GTM output
O0
TOUT58
ATX3
O1
O2
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
O3
O4
–
O5
Reserved
SDRAMA13
T6OUT
TGO3
TDO
O6
EBU output
O7
GPT120 output
OCDS; ENx
HWOUT
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ.
DAP2
OCDS (3-Pin DAP); ENx
In the 3-Pin DAP mode this pin is used as DAP2.
Table 2-12 Port 22 Functions
Pin
Symbol
P22.0
Ctrl
Type
Function
W25
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN47
MTSR4B
P22.0
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT47
ATX3N
MTSR4
SCLK4N
FCLN1
FCLND1
–
ASCLIN3 output (LVDS)
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
TOC-68
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-12 Port 22 Functions (cont’d)
Pin
Symbol
P22.1
TIN48
MRST4B
P22.1
TOUT48
ATX3P
MRST4
SCLK4P
FCLP1
–
Ctrl
Type
Function
W24
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output (LVDS)
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
Y25
P22.2
TIN49
SLSI4B
P22.2
TOUT49
–
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO43
MTSR4N
SON1
SOND1
–
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Y24
P22.3
TIN50
SCLK4B
P22.3
TOUT50
–
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK4
MTSR4P
SOP1
–
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
Data Sheet
TOC-69
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-12 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
W21
P22.4
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN130
P22.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT130
–
–
Reserved
SLSO012
QSPI0 output
PSI5 output
Reserved
PSITX4
–
–
Reserved
W22
P22.5
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN131
MTSR0C
QSPI0 input
PSI5 input
PSIRX4B
P22.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT131
–
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
V21
P22.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN132
MRST0C
QSPI0 input
General-purpose output
GTM output
Reserved
P22.6
O0
O1
O2
O3
O4
O5
O6
O7
TOUT132
–
–
Reserved
MRST0
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
TOC-70
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-12 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
V22
P22.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN133
SCLK0C
QSPI0 input
General-purpose output
GTM output
Reserved
P22.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT133
–
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
U21
P22.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN134
SCLK0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.8
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT134
–
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
U22
P22.9
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN135
MRST0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.9
O0
O1
O2
O3
O4
O5
O6
O7
TOUT135
–
–
Reserved
MRST0
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
TOC-71
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-12 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
T21
P22.10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN136
MTSR0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT136
–
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
T22
P22.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN137
P22.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT137
–
–
Reserved
SLSO010
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Table 2-13 Port 23 Functions
Pin
Symbol
Ctrl
Type
Function
AC25
P23.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN41
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT41
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-72
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-13 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AB24
P23.1
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN42
SDI10
MSC1 input
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
GTM output
Reserved
TOUT42
ARTS1
SLSO46
GTMCLK0
–
EXTCLK0
SCU output
–
Reserved
AB25
P23.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN43
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT43
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AA24
P23.3
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN44
INJ10
MSC1 input
P23.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT44
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-73
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-13 Port 23 Functions (cont’d)
Pin
Symbol
P23.4
TIN45
P23.4
TOUT45
–
Ctrl
Type
Function
AA25
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO45
END12
EN10
–
QSPI4 output
MSC1 output
MSC1 output
Reserved
–
Reserved
AA22
P23.5
TIN46
P23.5
TOUT46
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO44
END13
EN11
–
QSPI4 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Y22
P23.6
TIN138
P23.6
TOUT138
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
SLSO011
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-74
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-13 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
Y21
P23.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN139
P23.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT139
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-14 Port 24 Functions
Pin
Symbol
Ctrl
Type
Function
U29
P24.0
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN222
P24.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT222
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ11
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A11
U30
P24.1
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN223
P24.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT223
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ15
A15
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-75
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-14 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
T29
P24.2
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN224
P24.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT224
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ14
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A14
T30
P24.3
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN225
P24.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT225
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ13
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A13
R29
P24.4
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN226
P24.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT226
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ9
A9
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-76
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-14 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
R30
P24.5
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN227
P24.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT227
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ12
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A12
P29
P24.6
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN228
P24.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT228
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ5
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A5
P30
P24.7
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN229
P24.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT229
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ8
A8
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-77
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-14 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
N29
P24.8
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN230
P24.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT230
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ10
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A10
N30
P24.9
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN231
P24.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT231
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ6
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A6
M29
P24.10
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN232
P24.10
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT232
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ4
A4
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-78
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-14 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
M30
P24.11
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN233
P24.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT233
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ3
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A3
L29
P24.12
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN234
P24.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT234
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ1
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A1
L30
P24.13
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN235
P24.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT235
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ2
A2
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-79
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-14 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
K29
P24.14
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN236
P24.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT236
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ0
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A0
K30
P24.15
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN237
P24.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT237
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ7
A7
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-80
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-15 Port 25 Functions
Pin
Symbol
Ctrl
Type
Function
AG30
P25.0
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN206
SDCLKI
EBU input
P25.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT206
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
BFCLKO
HWOU
T
EBU output
EBU output
General-purpose input
GTM input
SDCLKO
AF30
P25.1
I
A2 /
PU1 /
VEBU
TIN207
P25.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT207
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
RD
HWOU
T
EBU output
EBU output
General-purpose input
GTM input
RAS
AF29
P25.2
I
A2 /
PU1 /
VEBU
TIN208
P25.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT208
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
RD/WR
WR
HWOU
T
EBU output
EBU output
Data Sheet
TOC-81
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-15 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AE30
P25.3
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN209
HOLDA
EBU input
P25.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT209
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
BAABA0
EBU output
(combined for BAA and BA0)
CS2
HWOU
T
EBU output
EBU output
EBU output
General-purpose input
GTM input
DQM1
HOLDA
AE29
P25.4
I
A2 /
PU1 /
VEBU
TIN210
P25.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT210
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CS1
HWOU
T
EBU output
EBU output
General-purpose input
GTM input
DQM0
AD30
P25.5
I
A2 /
PU1 /
VEBU
TIN211
P25.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT211
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CS0
HWOU
T
EBU output
Data Sheet
TOC-82
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-15 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
I
Type
Function
W29
P25.6
A2 /
PU1 /
VEBU
General-purpose input
General-purpose output
GTM output
Reserved
P25.6
O0
O1
O2
O3
O4
O5
O6
O7
TOUT212
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CKE
HWOU
T
EBU output
AD29
P25.7
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN213
P25.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT213
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ADV
CAS
P25.8
TIN214
P25.8
TOUT214
–
HWOU
T
EBU output
EBU output
AC29
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
A23
EBU output
EBU output
Reserved
SDRAMA0
–
BC0
HWOU
T
EBU output
Data Sheet
TOC-83
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-15 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AC30
P25.9
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN215
P25.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT215
–
–
Reserved
–
Reserved
A22
EBU output
EBU output
Reserved
SDRAMA1
–
BC1
HWOU
T
EBU output
AB29
P25.10
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN216
P25.10
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT216
–
–
Reserved
–
Reserved
A21
EBU output
SDRAMA2
EBU output
–
Reserved
BC2
HWOU
T
EBU output
AB30
P25.11
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN217
P25.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT217
–
–
Reserved
–
Reserved
A20
EBU output
SDRAMA3
EBU output
–
Reserved
BC3
HWOU
T
EBU output
Data Sheet
TOC-84
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-15 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AA29
P25.12
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN218
P25.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT218
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA4
EBU output
Reserved
–
A19
HWOU
T
EBU output
AA30
P25.13
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN219
P25.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT219
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA5
EBU output
–
Reserved
A17
HWOU
T
EBU output
Y29
P25.14
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN220
P25.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT220
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA6
EBU output
–
Reserved
A18
HWOU
T
EBU output
Data Sheet
TOC-85
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-15 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
Y30
P25.15
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN221
P25.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT221
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA7
EBU output
Reserved
–
A16
HWOU
T
EBU output
Table 2-16 Port 26 Functions
Pin
Symbol
Ctrl
Type
Function
AG29
P26.0
I
LP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN212
BFCLKI
EBU input
P26.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT212
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-86
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-17 Port 30 Functions
Pin
Symbol
Ctrl
Type
Function
AJ21
P30.0
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN190
P30.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT190
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD14
HWOU
T
EBU Address / Data Bus Line
AK21
P30.1
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN191
P30.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT191
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD11
HWOU
T
EBU Address / Data Bus Line
AJ22
P30.2
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN192
P30.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT192
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD12
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-87
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-17 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AK22
P30.3
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN193
P30.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT193
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD15
HWOU
T
EBU Address / Data Bus Line
AJ23
P30.4
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN194
P30.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT194
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD8
HWOU
T
EBU Address / Data Bus Line
AK23
P30.5
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN195
P30.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT195
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD13
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-88
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-17 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AJ24
P30.6
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN196
P30.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT196
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD4
HWOU
T
EBU Address / Data Bus Line
AK24
P30.7
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN197
P30.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT197
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD7
HWOU
T
EBU Address / Data Bus Line
AJ25
P30.8
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN198
P30.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT198
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD3
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-89
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-17 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AK25
P30.9
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN199
P30.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT199
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD0
HWOU
T
EBU Address / Data Bus Line
AJ26
P30.10
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN200
P30.10
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT200
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD5
HWOU
T
EBU Address / Data Bus Line
AK26
P30.11
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN201
P30.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT201
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD10
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-90
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-17 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AJ27
P30.12
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN202
P30.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT202
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD9
HWOU
T
EBU Address / Data Bus Line
AK27
P30.13
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN203
P30.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT203
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD2
HWOU
T
EBU Address / Data Bus Line
AJ28
P30.14
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN204
P30.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT204
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD1
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-91
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-17 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AK28
P30.15
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN205
P30.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT205
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD6
HWOU
T
EBU Address / Data Bus Line
Table 2-18 Port 31 Functions
Pin
Symbol
Ctrl
Type
Function
AJ12
P31.0
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN174
P31.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT174
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD30
HWOU
T
EBU Address / Data Bus Line
AK12
P31.1
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN175
P31.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT175
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD29
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-92
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-18 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AJ13
P31.2
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN176
P31.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT176
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD28
HWOU
T
EBU Address / Data Bus Line
AK13
P31.3
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN177
P31.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT177
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD26
HWOU
T
EBU Address / Data Bus Line
AJ14
P31.4
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN178
P31.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT178
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD24
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-93
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-18 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AK14
P31.5
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN179
P31.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT179
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD23
HWOU
T
EBU Address / Data Bus Line
AJ15
P31.6
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN180
P31.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT180
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD20
HWOU
T
EBU Address / Data Bus Line
AK15
P31.7
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN181
P31.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT181
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD16
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-94
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-18 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AJ16
P31.8
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN182
P31.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT182
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD31
HWOU
T
EBU Address / Data Bus Line
AK16
P31.9
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN183
P31.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT183
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD27
HWOU
T
EBU Address / Data Bus Line
AJ17
P31.10
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN184
P31.10
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT184
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD21
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-95
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-18 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AK17
P31.11
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN185
P31.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT185
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD25
HWOU
T
EBU Address / Data Bus Line
AJ18
P31.12
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN186
P31.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT186
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD19
HWOU
T
EBU Address / Data Bus Line
AK18
P31.13
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN187
P31.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT187
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD22
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-96
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-18 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AJ19
P31.14
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN188
P31.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT188
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD18
HWOU
T
EBU Address / Data Bus Line
AK19
P31.15
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN189
P31.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT189
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD17
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-97
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-19 Port 32 Functions
Pin
Symbol
P32.0
Ctrl
Type
Function
AE22
I
LP /
PX/
VEXT
General-purpose input
GTM input
TIN36
FDEST
VGATE1N
PMU input
SMPS mode: analog output. External Pass Device
gate control for EVR13
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT36
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AE23
P32.2
TIN38
ARX3D
RXDCAN3B
RXDCANr1D
P32.2
TOUT38
ATX3
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN3 input
CAN node 3 input
CAN node 1 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
DCDCSYNC
–
SCU output
Reserved
AE24
P32.3
TIN39
P32.3
TOUT39
ATX3
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
ASCLK3
TXDCAN3
TXDCANr1
–
ASCLIN3 output
CAN node 3 output
CAN node 1 output (MultiCANr+)
Reserved
Data Sheet
TOC-98
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-19 Port 32 Functions (cont’d)
Pin
Symbol
P32.4
TIN40
ACTS1B
SDI12
P32.4
TOUT40
–
Ctrl
Type
Function
AD23
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
END12
GTMCLK1
EN10
EXTCLK1
COUT63
P32.5
TIN140
P32.5
TOUT140
ATX2
–
MSC1 output
GTM output
MSC1 output
SCU output
CCU60 output
General-purpose input
GTM input
AA20
LP /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN2 output
Reserved
–
Reserved
–
Reserved
TXDCAN2
–
CAN node 2 output
Reserved
AB20
P32.6
TGI4
LP /
PU1 /
VEXT
General-purpose input
OCDS input
TIN141
RXDCAN2C
ARX2F
P32.6
TOUT141
–
GTM input
CAN node 2 input
ASCLIN2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
SLSO212
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
TGO4
HWOU
T
OCDS; ENx
Data Sheet
TOC-99
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-19 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AB21
P32.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN142
TGI5
OCDS input
General-purpose output
GTM output
Reserved
P32.7
O0
O1
O2
O3
O4
O5
O6
O7
TOUT142
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO5
HWOU
T
OCDS; ENx
Table 2-20 Port 33 Functions
Pin
Symbol
Ctrl
Type
Function
AD15
P33.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN22
DSITR0E
DSADC channel 0 input E
General-purpose output
GTM output
P33.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT22
–
Reserved
–
Reserved
–
Reserved
–
Reserved
VADCG2BFL0
–
VADC output
Reserved
Data Sheet
TOC-100
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-20 Port 33 Functions (cont’d)
Pin
Symbol
P33.1
Ctrl
Type
Function
AE15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN23
PSIRX0C
SENT9C
DSCIN2B
DSITR1E
P33.1
PSI5 input
SENT input
DSADC channel 2 input B
DSADC channel 1 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT23
ASLSO3
SCLK2
ASCLIN3 output
QSPI2 output
DSCOUT2
VADCEMUX02
VADCG2BFL1
–
DSADC channel 2 output
VADC output
VADC output
Reserved
AD16
P33.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN24
SENT8C
DSDIN2B
DSITR2E
P33.2
SENT input
DSADC channel 2 input B
DSADC channel 2 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT24
ASCLK3
SLSO210
PSITX0
ASCLIN3 output
QSPI2 output
PSI5 output
VADCEMUX01
VADCG2BFL2
–
VADC output
VADC output
Reserved
Data Sheet
TOC-101
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-20 Port 33 Functions (cont’d)
Pin
Symbol
P33.3
Ctrl
Type
Function
AE16
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN25
PSIRX1C
SENT7C
DSCIN1B
P33.3
PSI5 input
SENT input
DSADC channel 1 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT25
–
Reserved
–
Reserved
DSCOUT1
VADCEMUX00
VADCG2BFL3
–
DSADC channel 1 output
VADC output
VADC output
Reserved
AD17
P33.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN26
SENT6C
CTRAPC
DSDIN1B
DSITR0F
P33.4
SENT input
CCU61 input
DSADC channel 1 input
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
ASCLIN2 output
QSPI2 output
SLSO212
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
TOC-102
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-20 Port 33 Functions (cont’d)
Pin
Symbol
P33.5
Ctrl
Type
Function
AE17
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN27
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
DSITR1F
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 1 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
AD18
P33.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN28
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
SLSO211
PSITX2
ASCLIN2 output
QSPI2 output
PSI5 output
VADCEMUX10
VADCG1BFL0
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
TOC-103
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-20 Port 33 Functions (cont’d)
Pin
Symbol
P33.7
Ctrl
Type
Function
AE18
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN29
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO47
–
ASCLIN2 output
QSPI4 output
Reserved
–
Reserved
VADCG1BFL1
–
VADC output
Reserved
AD19
P33.8
MP /
HighZ /
VEXT
General-purpose input
GTM input
TIN30
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI4 output
Reserved
SLSO42
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
AE19
P33.9
TIN31
HSIC3INA
P33.9
TOUT31
ATX2
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI4 output
ASCLIN2 output
Reserved
SLSO41
ASCLK2
–
–
Reserved
CC62
CCU61 output
Data Sheet
TOC-104
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-20 Port 33 Functions (cont’d)
Pin
Symbol
P33.10
TIN32
Ctrl
Type
Function
AD20
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI4A
HSIC3INB
P33.10
TOUT32
SLSO16
SLSO40
ASLSO1
PSISCLK
–
QSPI4 input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
QSPI1 output
QSPI4 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
P33.11
TIN33
CCU61 output
General-purpose input
GTM input
AE20
MP /
PU1 /
VEXT
SCLK4A
P33.11
TOUT33
ASCLK1
SCLK4
–
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC channel output
CCU61 output
General-purpose input
GTM input
AD21
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR4A
P33.12
TOUT34
ATX1
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
ASCLIN1 output
Reserved
MTSR4
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
TOC-105
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-20 Port 33 Functions (cont’d)
Pin
Symbol
P33.13
TIN35
ARX1F
MRST4A
DSSGNB
INJ11
P33.13
TOUT35
ATX1
Ctrl
Type
Function
AE21
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
QSPI4 input
DSADC channel input B
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
QSPI2 output
Reserved
MRST4
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
General-purpose input
GTM input
AA19
P33.14
TIN143
TGI6
LP /
PU1 /
VEXT
OCDS input
SCLK2D
P33.14
TOUT143
–
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
CC62
CCU60 output
OCDS; ENx
TGO6
HWOU
T
Data Sheet
TOC-106
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-20 Port 33 Functions (cont’d)
Pin
Symbol
P33.15
TIN144
TGI7
Ctrl
Type
Function
AB19
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
OCDS input
General-purpose output
GTM output
Reserved
P33.15
TOUT144
–
O0
O1
O2
O3
O4
O5
O6
O7
SLSO211
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
COUT62
TGO7
CCU60 output
OCDS; ENx
HWOU
T
Table 2-21 Port 34 Functions
Pin
Symbol
P34.1
TIN146
P34.1
TOUT146
ATX0
Ctrl
Type
Function
AB16
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
–
TXDCAN0
TXDCANr0
–
CAN node 0 output
CAN node 0 output (MultiCANr+)
Reserved
COUT63
P34.2
TIN147
ARX0D
RXDCAN0G
RXDCANr0C
P34.2
TOUT147
–
CCU60 output
General-purpose input
GTM input
AA17
LP /
PU1 /
VEXT
ASCLIN0 input
CAN node 0 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CC60
CCU60 output
Data Sheet
TOC-107
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-21 Port 34 Functions (cont’d)
Pin
Symbol
P34.3
TIN148
P34.3
TOUT148
–
Ctrl
Type
Function
AB17
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
SLSO210
–
QSPI2 output
Reserved
–
Reserved
COUT60
P34.4
TIN149
MRST2D
P34.4
TOUT149
–
CCU60 output
General-purpose input
GTM input
AA18
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
MRST2
–
QSPI2 output
Reserved
–
Reserved
CC61
P34.5
TIN150
MTSR2D
P34.5
TOUT150
–
CCU60 output
General-purpose input
GTM input
AB18
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
MTSR2
–
QSPI2 output
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
TOC-108
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-22 Port 40 Functions
Pin
Symbol
P40.0
Ctrl
Type
Function
AD7
I
S /
General-purpose input
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
CCU60 input
HighZ /
VDDM
VADCG3.0
DS2PB
CCPOS0D
SENT0A
P40.1
SENT input
AD6
I
S /
General-purpose inpu.t
HighZ /
VDDM
VADCG3.1
VADC analog input channel 1 of group 3 (with pull
down diagnostics)
DS2NB
DSADC: negative analog input channel 2, pin B
CCU60 input
CCPOS1B
SENT1A
P40.2
SENT input
AC7
AC6
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADCG3.2
VADC analog input channel 2 of group 3 (with pull
down diagnostics)
CCPOS1D
SENT2A
P40.3
CCU60 input
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
CCPOS2B
SENT3A
P40.4
CCU60 input
SENT input
W9
Y6
V9
I
I
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 0 of group 4
CCU60 input
VADCG4.0
CCPOS2D
SENT4A
P40.5
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 1 of group 4
CCU61 input
VADCG4.1
CCPOS0D
SENT5A
P40.6
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
CCU61 input
VADCG4.4
DS3PA
CCPOS1B
SENT6A
SENT input
Data Sheet
TOC-109
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-22 Port 40 Functions (cont’d)
Pin
W7
Symbol
P40.7
Ctrl
Type
Function
I
S /
General-purpose input
HighZ /
VDDM
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input channel 3, pin A
CCU61 input
CCPOS1D
SENT7A
P40.8
SENT input
V10
W6
I
I
S /
HighZ /
VDDM
General-purpose input
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel 3, pin B
CCU61 input
CCPOS2B
SENT8A
P40.9
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input channel 3, pin B
CCU61 input
CCPOS2D
SENT9A
P40.10
SENT input
AA1
Y1
I
I
I
I
I
S /
General-purpose input
HighZ /
VDDM
VADCG10.3
DS8NB
VADC analog input channel 3 of group 10
DSADC: negative analog input channel 8, pin B
SENT input
SENT10A
P40.11
S /
HighZ /
VDDM
General-purpose input
VADCG10.4
DS8PA
VADC analog input channel 4 of group 10
DSADC: positive analog input of channel 8, pin A
SENT input
SENT11A
P40.12
Y2
S /
HighZ /
VDDM
General-purpose input
VADCG10.5
DS8NA
VADC analog input channel 5 of group 10
DSADC: positive analog input of channel 8, pin A
SENT input
SENT12A
P40.13
W1
W2
S /
HighZ /
VDDM
General-purpose input
VADCG10.6
DS9PA
VADC analog input channel 6 of group 10
DSADC: positive analog input of channel 9, pin A
SENT input
SENT13A
P40.14
S /
General-purpose input
HighZ /
VDDM
VADCG10.7
DS9NA
VADC analog input channel 7 of group 10
DSADC: positive analog input of channel 9, pin A
SENT input
SENT14A
Data Sheet
TOC-110
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-23 Analog Inputs
Pin
Symbol
AN0
Ctrl
Type
Function
AA15
I
D / HighZ / Analog input 0
VDDM
VADCG0.0
DS1PA
AN1
VADC analog input channel 0 of group 0
DSADC: positive analog input of channel 1, pin A
D / HighZ / Analog input 1
AB15
AD14
AB14
I
I
I
VDDM
VADCG0.1
DS1NA
AN2
VADC analog input channel 1 of group 0
DSADC: negative analog input channel 1, pin A
D / HighZ / Analog input 2
VDDM
VADCG0.2
DS0PA
AN3
VADC analog input channel 2 of group 0
DSADC: positive analog input of channel 0, pin A
D / HighZ / Analog input 3
VDDM
VADCG0.3
DS0NA
AN4
VADC analog input channel 3 of group 0
DSADC: negative analog input channel 0, pin A
AA14
AE14
AA13
AB13
I
I
I
I
D / HighZ / Analog input 4
VDDM
VADCG0.4
AN5
VADC analog input channel 4 of group 0
D / HighZ / Analog input 5
VDDM
VADCG0.5
AN6
VADC analog input channel 5 of group 0
D / HighZ / Analog input 6
VDDM
VADCG0.6
AN7
VADC analog input channel 6 of group 0
D / HighZ / Analog input 7
VDDM
VADCG0.7
VADC analog input channel 7 of group 0 (with pull
down diagnostics)
AD13
AB12
AE13
AD12
AN8
I
I
I
I
D / HighZ / Analog input 8
VDDM
VADCG1.0
AN9
VADC analog input channel 0 of group 1
D / HighZ / Analog input 9
VDDM
VADCG1.1
AN10
VADC analog input channel 1 of group 1
D / HighZ / Analog input 10
VDDM
VADCG1.2
AN11
VADC analog input channel 2 of group 1
D / HighZ / Analog input 11
VDDM
VADCG1.3
VADC analog input channel 3 of group 1 (with pull
down diagnostics)
AA12
AD11
AB11
AA11
AN12
I
I
I
I
D / HighZ / Analog input 12
VDDM
VADCG1.4
AN13
VADC analog input channel 4 of group 1
D / HighZ / Analog input 13
VDDM
VADCG1.5
AN14
VADC analog input channel 5 of group 1
D / HighZ / Analog input 14
VDDM
VADCG1.6
AN15
VADC analog input channel 6 of group 1
D / HighZ / Analog input 15
VDDM
VADCG1.7
VADC analog input channel 7 of group 1
Data Sheet
TOC-111
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-23 Analog Inputs (cont’d)
Pin
Symbol
AN16
Ctrl
Type
Function
AD10
I
D / HighZ / Analog input 16
VDDM
VADCG2.0
AN17
VADC analog input channel 0 of group 2
AB10
AD9
AD8
I
I
I
D / HighZ / Analog input 17
VDDM
VADCG2.1
AN18
VADC analog input channel 1 of group 2
D / HighZ / Analog input 18
VDDM
VADCG2.2
AN19
VADC analog input channel 2 of group 2
D / HighZ / Analog input 19
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
AE8
AE7
AN20
I
I
D / HighZ / Analog input 20
VDDM
VADCG2.4
DS2PA
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 2, pin A
D / HighZ / Analog input 21
AN21
VDDM
VADCG2.5
DS2NA
VADC analog input channel 5 of group 2
DSADC: negative analog input channel 2, pin A
AA10
Y10
AN22
I
I
I
D / HighZ / Analog input 22
VDDM
VADCG2.6
AN23
VADC analog input channel 6 of group 2
D / HighZ / Analog input 23
VDDM
VADCG2.7
AN24
VADC analog input channel 7 of group 2
Analog input 24
AD7
S /
HighZ /
VDDM
VADCG3.0
DS2PB
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
SENT input channel 0, pin A
SENT0A
AN25
AD6
I
S /
Analog input 24
HighZ /
VDDM
VADCG3.1
VADC analog input channel 1 of group 3 (with pull
down diagnostics)
DS2NB
DSADC: negative analog input channel 2, pin B
SENT input channel 1, pin A
Analog input 26
SENT1A
AN26
AC7
AC6
AB7
I
I
I
S /
HighZ /
VDDM
VADCG3.2
VADC analog input channel 2 of group 3 (with pull
down diagnostics)
SENT2A
AN27
SENT input channel 2, pin A
Analog input 27
S /
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
SENT3A
AN28
SENT input channel 3, pin A
D / HighZ / Analog input 28
VDDM
VADCG3.4
VADC analog input channel 4 of group 3 (with pull
down diagnostics)
Data Sheet
TOC-112
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-23 Analog Inputs (cont’d)
Pin
Symbol
AN29
Ctrl
Type
Function
AB6
I
D / HighZ / Analog input 29
VDDM
VADCG3.5
VADC analog input channel 5 of group 3 (with pull
down diagnostics)
AA9
Y9
AN30
I
I
I
D / HighZ / Analog input 30
VDDM
VADCG3.6
AN31
VADC analog input channel 6 of group 3
D / HighZ / Analog input 31
VDDM
VADCG3.7
AN32
VADC analog input channel 7 of group 3
Analog input 32
W9
S /
HighZ /
VDDM
VADCG4.0
SENT4A
AN33
VADC analog input channel 0 of group 4
SENT input channel 4, pin A
Analog input 33
Y6
I
S /
HighZ /
VDDM
VADCG4.1
SENT5A
AN34
VADC analog input channel 1 of group 4
SENT input channel 5, pin A
W10
Y7
I
I
D / HighZ / Analog input 34
VDDM
VADCG4.2
AN35
VADC analog input channel 2 of group 4
D / HighZ / Analog input 35
VDDM
VADCG4.3
VADC analog input channel 3 of group 4 (with pull
down diagnostics)
V9
AN36
I
I
I
I
S /
HighZ /
VDDM
Analog input 34
VADCG4.4
DS3PA
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
SENT input channel 6, pin A
SENT6A
AN37
W7
V10
W6
S /
HighZ /
VDDM
Analog input 37
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input channel 3, pin A
SENT input channel 7, pin A
SENT7A
AN38
S /
HighZ /
VDDM
Analog input 38
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel 3, pin B
SENT input channel 8, pin A
SENT8A
AN39
S /
Analog input 39
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input channel 3, pin B
SENT input channel 9, pin A
SENT9A
AN40
U10
U9
I
I
D / HighZ / Analog input 40
VDDM
VADCG5.0
AN41
VADC analog input channel 0 of group 5
D / HighZ / Analog input 41
VDDM
VADCG5.1
VADC analog input channel 1 of group 5
Data Sheet
TOC-113
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-23 Analog Inputs (cont’d)
Pin
Symbol
AN42
Ctrl
Type
Function
T10
I
D / HighZ / Analog input 42
VDDM
VADCG5.2
AN43
VADC analog input channel 2 of group 5
T9
V6
I
I
D / HighZ / Analog input 43
VDDM
VADCG5.3
VADC analog input channel 3 of group 5 (with pull
down diagnostics)
AN44
D / HighZ / Analog input 44
VDDM
VADCG5.4
DS3PC
AN45
VADC analog input channel 4 of group 5
DSADC: positive analog input of channel 3, pin C
D / HighZ / Analog input 45
V7
U6
U7
I
I
I
VDDM
VADCG5.5
DS3NC
AN46
VADC analog input channel 5 of group 5
DSADC: negative analog input channel 3, pin C
D / HighZ / Analog input 46
VDDM
VADCG5.6
DS3PD
AN47
VADC analog input channel 6 of group 5
DSADC: positive analog input of channel 3, pin D
D / HighZ / Analog input 47
VDDM
VADCG5.7
DS3ND
AN48
VADC analog input channel 7 of group 5
DSADC: negative analog input channel 3, pin D
AK7
AJ7
AJ6
AK6
AJ5
I
I
I
I
I
D / HighZ / Analog input 48
VDDM
VADCG8.0
AN49
VADC analog input channel 0 of group 8
D / HighZ / Analog input 49
VDDM
VADCG8.1
AN50
VADC analog input channel 1 of group 8 (muxtest)
D / HighZ / Analog input 50
VDDM
VADCG8.2
AN51
VADC analog input channel 2 of group 8 (muxtest)
D / HighZ / Analog input 51
VDDM
VADCG8.3
AN52
VADC analog input channel 3 of group 8
D / HighZ / Analog input 52
VDDM
VADCG8.4
DS6PA
VADC analog input channel 4 of group 8
DSADC: positive analog input of channel 6, pin A
D / HighZ / Analog input 53
AK5
AJ4
AK4
AN53
I
I
I
I
VDDM
VADCG8.5
DS6NA
AN54
VADC analog input channel 5 of group 8
DSADC: negative analog input channel 6, pin A
D / HighZ / Analog input 5
VDDM
VADCG8.6
DS6PB
VADC analog input channel 6 of group 8
DSADC: positive analog input of channel 6, pin B
D / HighZ / Analog input 50
AN55
VDDM
VADCG8.7
DS6NB
AN56
VADC analog input channel 7 of group 8
DSADC: negative analog input channel 6, pin B
AF1
D / HighZ / Analog input 56
VDDM
VADCG9.0
VADC analog input channel 0 of group 9
Data Sheet
TOC-114
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-23 Analog Inputs (cont’d)
Pin
Symbol
AN57
Ctrl
Type
Function
AF2
I
D / HighZ / Analog input 57
VDDM
VADCG9.1
AN58
VADC analog input channel 1 of group 9 (muxtest)
AE2
AE1
AD1
I
I
I
D / HighZ / Analog input 58
VDDM
VADCG9.2
AN59
VADC analog input channel 2 of group 9 (muxtest)
D / HighZ / Analog input 59
VDDM
VADCG9.3
AN60
VADC analog input channel 3 of group 9
D / HighZ / Analog input 60
VDDM
VADCG9.4
DS7PA
VADC analog input channel 4 of group 9
DSADC: positive analog input of channel 7, pin A
D / HighZ / Analog input 61
AD2
AC2
AC1
AN61
I
I
I
VDDM
VADCG9.5
DS7NA
VADC analog input channel 5 of group 9
DSADC: negative analog input channel 7, pin A
AN62
D / HighZ / Analog input 62
VDDM
VADCG9.6
DS7PB
VADC analog input channel 6 of group 9
DSADC: positive analog input of channel 7, pin B
D / HighZ / Analog input 63
AN63
VDDM
VADCG9.7
DS7NB
VADC analog input channel 7 of group 9
DSADC: negative analog input channel 7, pin B
AB2
AB1
AA2
AN64
I
I
I
D / HighZ / Analog input 64
VDDM
VADCG10.0
AN65
VADC analog input channel 0 of group 10
D / HighZ / Analog input 65
VDDM
VADCG10.1
AN66
VADC analog input channel 1 of group 10 (muxtest)
D / HighZ / Analog input 66
VDDM
VADCG10.2
DS8PB
VADC analog input channel 2 of group 10 (muxtest)
DSADC: positive analog input of channel 8, pin B
Analog input 67
AA1
Y1
AN67
I
I
I
S /
HighZ /
VDDM
VADCG10.3
DS8NB
VADC analog input channel 3 of group 10
DSADC: negative analog input channel 8, pin B
SENT input channel 10, pin A
SENT10A
AN68
S /
HighZ /
VDDM
Analog input 68
VADCG10.4
DS8PA
VADC analog input channel 4 of group 10
DSADC: positive analog input of channel 8, pin A
SENT input channel 11, pin A
SENT11A
AN69
Y2
S /
Analog input 69
HighZ /
VDDM
VADCG10.5
DS8NA
VADC analog input channel 5 of group 10
DSADC: negative analog input channel 8, pin A
SENT input channel 12, pin A
SENT12A
Data Sheet
TOC-115
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-23 Analog Inputs (cont’d)
Pin
W1
Symbol
AN70
Ctrl
Type
Function
I
S /
Analog input 70
HighZ /
VDDM
VADCG10.6
DS9PA
VADC analog input channel 6 of group 10
DSADC: positive analog input of channel 9, pin A
SENT input channel 13, pin A
Analog input 71
SENT13A
AN71
W2
I
S /
HighZ /
VDDM
VADCG10.7
DS9NA
VADC analog input channel 7 of group 10
DSADC: negative analog input channel 9, pin A
SENT input channel 14, pin A
SENT14A
Table 2-24 System I/O
Pin
Symbol
Ctrl
Type
Function
M22
PORST
I
PORST /
PD /
Power On Reset Input
Additional strong PD in case of power fail.
VEXT
L21
ESR0
I/O
MP /
OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished.
See also SCU chapter for details.
Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR
register description.
EVRWUP
ESR1
I
EVR Wakeup Pin
M21
I/O
MP /
PU1 /
VEXT
External System Request Reset 1
Default NMI function.
See also SCU chapter ´Reset Control Unit´ and
SCU_IOCR register description.
EVRWUP
VGATE1P
I
EVR Wakeup Pin
AD22
AJ20
R21
O
VGATE1P / External Pass Device gate control for EVR13
- /
VEXT
VGATE3P
O
VGATE3P / External Pass Device gate control for EVR33
- /
VEXT
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
T24
TRST
I
A2 /
JTAG Module Reset/Enable Input
PD /
VDDP3
Data Sheet
TOC-116
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-24 System I/O (cont’d)
Pin
Symbol
TCK
Ctrl
Type
Function
P21
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
U25
U24
XTAL1
XTAL2
I
XTAL1 /
- /
VDDP3
Main Oscillator/PLL/Clock Generator Input
O
XTAL2 /
- /
Main Oscillator/PLL/Clock Generator Output
VDDP3
Table 2-25 Supply
Pin
Symbol
Ctrl
Type
Vx
Function
AE11
VAREF1
VAGND1
VAREF2
VAGND2
VDDM
I
I
I
I
I
I
Positive Analog Reference Voltage 1
Negative Analog Reference Voltage 1
Positive Analog Reference Voltage 2
Negative Analog Reference Voltage 2
ADC Analog Power Supply (3.3V / 5V)
AE12
Vx
AA6
Vx
AA7
Vx
AE10, AJ9, AK9
N12, M13
Vx
VDD / VDDSB
Vx
Emulation Device: Emulation SRAM
Standby Power Supply (1.3V) (Emulation
Device only).
Production Device: VDD (1.3V).
M18, N19, V12, V19, W13,
W18
VDD
VDD
I
I
Vx
Vx
Digital Core Power Supply (1.3V)
V24
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main
XTAL Oscillator/PLL (1.3V) . A higher
decoupling capacitor is therefore
recommended to the VSS pin for better
noise immunity.
A2, B3, F7, G8, AC24, AD25, VEXT
AH29, AJ30
I
I
Vx
Vx
External Power Supply (5V / 3.3V)
A29, B28, F24, G23
VDDP3
VDDP3
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power
Supply for VFLEX.
V25
I
Vx
Digital Power Supply for Oscillator,
LVDSH and A2 pads (3.3V).
The supply pin inturn supplies the main
XTAL Oscillator/PLL (3.3V) . A higher
decoupling capacitor is therefore
recommended to the VSS pin for better
noise immunity.
K20, J21
J10
VDDFL3
VFLEX
I
I
Vx
Vx
Flash Power Supply (3.3V)
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
Data Sheet
TOC-117
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-25 Supply (cont’d)
Pin
Symbol
Ctrl
Type
Vx
Function
AJ11, AK11, AK20, AK29
VFLEXE
I
Digital Power Supply for EBU Flex Port
Pads
(5V / 3.3V)
J29,J30, AH30
VEBU
I
Vx
Digital Power Supply for EBU
(3.3V)
AK8, AJ8, AE9
AA16
VSSM
I
I
Vx
Vx
Analog Ground for VDDM
VEVRSB
Standby Power Supply (3.3V/5V) for the
Standby SRAM (CPU0.DSPR).
If Standby mode is not used: To be
handled like VEXT (3.3V/5V).
A30, B2, B29, B30, F25, G7, VSS
G24, H29, H30, J9, J22, K10,
K21, T25, AA21, AB22, AD24,
AE25, AJ10, AJ29, AK10,
AK30
I
Vx
Digital Ground (outer balls)
W14, W17, V14, V15, V16,
V17
VSS
I
Vx
Digital Ground (center balls)
U12, U13, U15, U16, U18, U19 VSS
T13, T14, T15, T16, T17, T18 VSS
R13, R14, R15, R16, R17, R18 VSS
P12, P13, P15, P16, P18, P19 VSS
I
I
I
I
I
Vx
Vx
Vx
Vx
Vx
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
M14, M15, M16, M17, N14,
N15, N16, N17
VSS
W15
W16
T12
R12
T19
VSS
I
I
I
I
I
Vx
Vx
Vx
Vx
Vx
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT TX0N
VSS
VSS
VSS
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT TX0P
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT CLKN
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT CLKP
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT ERR
Data Sheet
TOC-118
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
Table 2-25 Supply (cont’d)
Pin
Symbol
Ctrl
Type
NC
Function
AK2, AK3, AJ1, AJ2, AJ3,
AH1, AH2, AG1, AG2,
W30, V1, V2, V29, V30, T1,
R1, R2, J1, H1, H2, G29, G30,
F29, F30, E1, E2, E29, E30,
D1, D2, D29, D30, C1, C2,
C29, C30
NC
I
Not Connected. These pins are reserved
for future extensions and shall not be
connected externally.
B1, B4, B6, B9, B10, B14,
B17, B20, B21, B25, B26,
B27,
A3, A4, A8, A9, A10, A17,
A21, A25, A26, A27, A28
R19
NC / VDDPSB
I
NCVDD Emulation Device: Power Supply (3.3V)
PSB
for DAP/JTAG pad group. Can be
connected to VDDP or can be left
unsupplied (see document ´AurixED´ /
Aurix Emulation Devices specification.
Production Device:
This pin is not connected on package
level. It can be connected on PCB level
to VDDP or Ground or can be left
unsupplied.
A1, F6, AK1, AE6, AB9
NC
I
NC1
Not Connected.
These pins are not connected on
package level and will not be used for
future extensions.
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input
function)
MP = Pad class MP (5V/3.3V)
MP+ = Pad class MP+ (5V/3.3V)
MPR = Pad class MPR (5V/3.3V)
A2 = Pad class A2 (3.3V)
Data Sheet
TOC-119
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
LVDSM = Pad class LVDSM (5V/3.3V)
LVDSH = Pad class LVDSH (3.3V)
S = Pad class S (Class S parameters for digital input and class D parameters for analog input function)
D = Pad class D (VADC / DSADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
2.1.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during Porst active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
TOC-120
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
•
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O
Ports and Peripheral I/O Lines”, P00 / P01)
•
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.1.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-26 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
TOC-121
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
2.2
TC298x Pin Definition and Functions: BGA416
Figure 2-2 is showing the TC298x Logic Symbol for the package variant: BGA416.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC
P10.15 P10.11 P10.8 P11.3 P10.5 P10.2 P10.4 P10.0 P11.7 P12.0 P13.14 P13.10 P14.8 P14.12 P13.6 P13.5 VDDFL3 P14.11 P15.7
P15.4
ESR1
ESR0
P20.0
VEXT
VSS
A
B
C
D
E
F
A
B
C
D
E
F
P02.1 P02.0 P10.13 P10.7 P11.9 P10.9 P10.3 P10.1 P11.13 P11.5 P12.1 P13.12 P13.11 P14.15 P14.14 P13.7 P13.4 VDDFL3 P14.13 P15.6
P15.2
P14.0
P14.1
PORST P20.2
VEXT
VSS
VDD
TCK
TMS
VSS
VDD
P21.7
P21.6
VSS
VDD
P21.5
P21.4
VDDP3
VDD
P02.4 P02.11 P10.14 P10.10 P11.12 P11.6 P11.15 P11.14 P11.8 P11.4 P11.1 P13.9 P14.6 P14.3 P14.10 P13.3 P13.0
P13.1
P15.3
P14.9
P15.5
P14.5
P14.2
P15.1
VEXT
E
VEXT
VSS
P02.13 P02.15 P02.12 P02.5 P11.10 P11.11 VFLEX VSS
VDD
9
P11.2 P11.0 P14.7 P14.4 VEXT VSS P15.8 P13.2
P02.14 P02.2 P01.7 P02.9
E
VDD
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
P01.0
P02.3 P01.6 P02.10
P10.6 P01.4 P01.5
TRST
P21.3
F
G
H
J
F
P01.2
P21.1 XTAL2
XTAL1
G
H
G
H
J
G
H
J
Top-View
P02.7 P02.6 P01.3
P01.9 P01.1 P02.8
P01.11 P01.10 P01.8
VDD
VSS
P21.2 VDDP3 VDDP3 VDDP3
P21.0
P22.0
VSS
P22.1
P23.4
P23.1
P22.2
P23.5
P23.2
P22.3
P23.6
P23.3
P23.0
J
10
11
12
13
14
15
16
17
VEXT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
L
K
L
K
L
K
K
L
K
L
P01.15 P01.14 P01.13 P01.12
P00.3 P00.2 P00.1 P00.0
P00.10 P00.9 P00.5 P00.4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L
VEBU P24.14 P24.15
M
N
M
N
M
N
M
N
M
N
M
N
VSS
VSS
(AGBT VSS
CLKP)
P24.10 P24.11 P24.12 P24.13
NC
(VDDPSB)
P00.12 P00.11 P00.13 P00.15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
P24.7
P24.4
P24.8
P24.9
P
P
P
P
P
P
VSS
(AGBT VSS
CLKN)
VSS
(AGBT
ERR)
NC/
VDDSB
NC/
VDDSB
P00.14 P00.6
VSS
VSS
P24.5
P24.2
P24.6
P24.3
R
T
R
T
R
T
R
T
R
T
R
T
AN42 P00.8 P00.7
VSS
AN40
AN36
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VEBU P24.1
AN43
AN70
AN41
AN37
VSS (AGBT (AGBT VSS
TX0N) TX0P)
P24.0 P25.13 P25.14 P25.15
VDD P25.10 P25.11 P25.12
U
U
U
U
U
U
AN71
AN69
AN65
AN61
AN28
AN29
AN6
AN68
AN64
AN60
AN26
AN27
AN4
V
W
Y
V
W
Y
V
W
Y
V
10
11
12
13
14
15
16
17
AN32 VAREF2
AN33 VAGND2
VSS
P25.7
P25.8
P25.4
P26.0
P30.7
P30.8
P30.9
P25.9
P25.5
W
Y
VEBU P25.3
AN5
AN56
AN7
AN8
AN9
AN2
P25.2
VDD
VSS
P25.1
P30.2
P30.3
P25.0
AA
AB
AA
AB
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
AN57
AN16
AN17
AN10
P30.12
P30.13
P30.14
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
AN0 VAGND1 AN24 AN20 P34.1 P34.2 P33.0 P33.4 P33.14 P32.4 P33.7 VEXT VGATE1P VFLEXE
VSS
VDD VGATE3P VFLEXE
AN48
AN18
AN1 VAREF1 AN25 AN21 VEVRSB P34.4 P33.1 P33.5 P33.15 P32.5 P33.8 VEXT P32.0
VDDM AN52 AN54 AN22 VDDM P34.5 P33.2 P33.6 P32.2 P33.10 P33.13 VEXT P32.6
P31.0
P31.1
P31.3
P31.4
P31.6
P31.7
P31.9
P31.12
P31.13
P31.14 P30.4
AN49
P31.10
P31.15 P30.5 P30.10 P30.15
NC
AN19
AN11
AN3
VSSM AN53 AN55 AN23
VSSM P34.3 P33.3 P33.9 P32.3 P33.11 P33.12 VEXT P32.7
P31.2
P31.5
P31.8
P31.11
P30.0
P30.1
P30.6 P30.11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Figure 2-2 TC298x Logic Symbol for the package variant BGA416.
Data Sheet
TOC-122
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
2.2.1
TC298x BGA416 Package Variant Pin Configuration
Table 2-27 Port 00 Functions
Pin
M4
Symbol
P00.0
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN9
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
HWOU
T
Data Sheet
TOC-123
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-27 Port 00 Functions (cont’d)
Pin
M3
Symbol
P00.1
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN10
ARX3E
ASCLIN3 input
CAN node 1 input
PSI5 input
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN5A
DS5NA
SENT input
CCU60 input
CCU61 input
DSADC channel 5 input
DSADC positive analog input of channel channel 5,
pin A
DSCIN7B
VADCG7.5
CIFD10
P00.1
DSADC channel 7 input
VADC analog input channel 5 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
–
Reserved
DSCOUT5
DSCOUT7
SPC0
DSADC channel 5 output
DSADC channel 7 output
SENT output
CC60
CCU61 output
M2
P00.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN11
SENT1B
DSDIN5A
DSDIN7B
DS5PA
SENT input
DSADC channel 5 input
DSADC channel 7 input
DSADC negative analog input of channel 5, pin A
VADC analog input channel 4 of group 7
CIF input
VADCG7.4
CIFD11
P00.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT11
ASCLK3
TXDCANr1
PSITX0
TXDCAN3
SLSO34
COUT60
ASCLIN3 output
CAN node 1 output (MultiCANr+)
PSI5 output
CAN node 3 output
QSPI3 output
CCU61 output
Data Sheet
TOC-124
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-27 Port 00 Functions (cont’d)
Pin
M1
Symbol
P00.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN12
RXDCAN3A
RXDCANr1A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG7.3
DSITR5F
CIFD12
P00.3
CAN node 3 input
CAN node 1 input (MultiCANr+)
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input
VADC analog input channel 3 of group 7
DSADC channel 5 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
N4
P00.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN13
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG7.2
CIFD13
P00.4
SENT input
DSADC channel 3 input
DSADC channel input
VADC analog input channel 2 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT13
PSISTX
–
PSI5-S output
Reserved
PSITX1
VADCG4BFL0
SPC3
PSI5 output
VADC output
SENT output
COUT61
CCU61 output
Data Sheet
TOC-125
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-27 Port 00 Functions (cont’d)
Pin
N3
Symbol
P00.5
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN14
PSIRX2A
SENT4B
CC62INB
CC62INA
DSCIN2A
VADCG7.1
CIFD14
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 2 input
VADC analog input channel 1 of group 7
CIF input
P00.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT14
DSCGPWMN
SLSO33
DSCOUT2
VADCG4BFL1
SPC4
DSADC output
QSPI3 output
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
R3
P00.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN15
SENT5B
DSDIN2A
VADCG7.0
SENT input
DSADC channel 2 input A
VADC analog input channel 0 of group 7 (with pull
down diagnostics)
DSITR4F
CIFD15
DSADC channel 4 input F
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG4BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
CCU61 output
Data Sheet
TOC-126
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-27 Port 00 Functions (cont’d)
Pin
T3
Symbol
P00.7
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN16
SENT6B
CC60INC
CCPOS0A
T12HRB
T2INA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSCIN4A
DS4NA
VADCG6.5
CIFCLK
P00.7
DSADC channel 4 input A
DSADC negative analog input channel 4, pin A
VADC analog input channel 5 of group 6
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG4BFL3
DSCOUT4
VADCEMUX11
SPC6
VADC output
DSADC channel 4 output
VADC output
SENT output
CC60
CCU61 output
T2
P00.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN17
SENT7B
CC61INC
CCPOS1A
T13HRB
T2EUDA
DSDIN4A
DS4PA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSADC channel 4 input A
DSADC positive analog input of channel 4, pin A
VADC analog input channel 4 of group 6
CIF input
VADCG6.4
CIFVSNC
P00.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
SPC7
VADC output
SENT output
CC61
CCU61 output
Data Sheet
TOC-127
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-27 Port 00 Functions (cont’d)
Pin
N2
Symbol
P00.9
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN18
SENT8B
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
DSCIN1A
VADCG6.3
DSITR3F
CIFHSNC
P00.9
SENT input
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
DSADC channel 1 input A
VADC analog input channel 3 of group 6
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
DSCOUT1
–
QSPI3 output
ASCLIN3 output
DSADC channel 1 output
Reserved
SPC8
SENT output
CC62
CCU61 output
N1
P00.10
TIN19
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT9B
DSDIN1A
VADCG6.2
P00.10
TOUT19
–
SENT input
DSADC channel 1 input A
VADC analog input channel 2 of group 6
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
SPC9
SENT output
COUT63
CCU61 output
Data Sheet
TOC-128
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-27 Port 00 Functions (cont’d)
Pin
P2
Symbol
Ctrl
Type
Function
P00.11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN20
CTRAPA
CCU60 input
T12HRE
CCU61 input
DSCIN0A
DSADC channel 0 input A
VADC analog input channel 1 of group 6
General-purpose output
GTM output
VADCG6.1
P00.11
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT20
–
Reserved
–
Reserved
DSCOUT0
DSADC channel 0 output
Reserved
–
–
Reserved
–
Reserved
P1
P00.12
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN21
ACTS3A
ASCLIN3 input
DSADC channel 0 input A
VADC analog input channel 0 of group 6
General-purpose output
GTM output
DSDIN0A
VADCG6.0
P00.12
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT21
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
General-purpose input
GTM input
P3
P00.13
MP+ /
PU1 /
VEXT
TIN167
DSDIN6A
DSADC channel 6 input A
General-purpose output
GTM output
P00.13
O0
O1
O2
O3
O4
O5
O6
O7
TOUT167
–
Reserved
–
Reserved
EXTCLK1
SCU output
–
–
–
Reserved
Reserved
Reserved
Data Sheet
TOC-129
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-27 Port 00 Functions (cont’d)
Pin
R2
Symbol
Ctrl
Type
Function
P00.14
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN166
DSCIN6A
DSADC channel 6 input A
General-purpose output
GTM output
P00.14
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT166
–
Reserved
–
Reserved
DSCOUT6
DSADC channel 6 output
Reserved
–
–
Reserved
–
Reserved
P4
P00.15
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN168
DSITR6F
DSADC channel 6 input F
General-purpose output
GTM output
P00.15
O0
O1
O2
O3
O4
O5
O6
O7
TOUT168
–
Reserved
–
Reserved
EXTCLK0
SCU output
–
–
–
Reserved
Reserved
Reserved
Table 2-28 Port 01 Functions
Pin
F1
Symbol
Ctrl
Type
Function
P01.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN155
DSITR6E
DSADC channel 6 input E
CAN node 3 input
CAN node 1 input (MultiCANr+)
General-purpose output
GTM output
RXDCAN3F
RXDCANr1E
P01.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT155
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-130
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-28 Port 01 Functions (cont’d)
Pin
J2
Symbol
P01.1
TIN159
DSITR8E
RXD1A1
SENT10B
P01.1
TOUT159
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSADC channel 8 input E
ERAY1 input
SENT input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
G1
P01.2
TIN156
DSCIN7A
P01.2
TOUT156
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
DSADC channel 7 input A
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
TXDCAN3
–
CAN node 3 output
Reserved
TXDCANr1
DSCOUT7
–
CAN node 1 output (MultiCANr+)
DSADC channel 7 output
Reserved
H3
P01.3
TIN111
SLSI3B
DSITR7F
P01.3
TOUT111
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 7 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
SLSO39
TXDCAN1
–
QSPI3 output
CAN node 1 output
Reserved
–
Reserved
Data Sheet
TOC-131
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-28 Port 01 Functions (cont’d)
Pin
G3
Symbol
Ctrl
Type
Function
P01.4
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN112
RXDCAN1C
CAN node 1 input
DSADC channel 7 input E
General-purpose output
GTM output
DSITR7E
P01.4
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT112
–
Reserved
–
Reserved
SLSO310
QSPI3 output
Reserved
–
–
Reserved
–
Reserved
G4
P01.5
TIN113
MRST3C
DSCIN8A
P01.5
TOUT113
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 8 input A
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
MRST3
–
QSPI3 output
Reserved
DSCOUT8
–
DSADC channel 8 output
Reserved
F3
P01.6
TIN114
MTSR3C
DSDIN8A
P01.6
TOUT114
–
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 8 input A
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
MTSR3
–
QSPI3 output
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-132
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-28 Port 01 Functions (cont’d)
Pin
E3
Symbol
Ctrl
Type
Function
P01.7
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN115
SCLK3C
QSPI3 input
DSITR8F
DSADC channel 8 input F
General-purpose output
GTM output
P01.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT115
–
Reserved
–
Reserved
SCLK3
QSPI3 output
Reserved
–
–
Reserved
–
Reserved
K3
P01.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN162
DSDIN9A
DSADC channel 9 input A
SENT input
SENT12B
ARX0C
ASCLIN0 input
CAN node 0 input
CAN node 0 input (MultiCANr+)
ERAY1 input
RXDCAN0F
RXDCANr0E
RXD1B1
P01.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT162
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-133
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-28 Port 01 Functions (cont’d)
Pin
J1
Symbol
Ctrl
Type
Function
P01.9
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN160
DSCIN9A
DSADC channel 9 input A
SENT input
SENT11B
P01.9
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT160
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DSCOUT9
DSADC channel 9 output
Reserved
–
K2
P01.10
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN163
DSITR9F
DSADC channel 9 input F
SENT input
SENT13B
P01.10
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT163
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
K1
P01.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN165
DSITR9E
DSADC channel 9 input E
SENT input
SENT14B
P01.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT165
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-134
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-28 Port 01 Functions (cont’d)
Pin
L4
Symbol
P01.12
TIN158
P01.12
TOUT158
–
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
TXD1A
–
ERAY1 output
Reserved
L3
P01.13
TIN161
P01.13
TOUT161
ATX0
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
TXDCAN0
TXDCANr0
TXD1B
–
CAN node 0 output
CAN node 0 output (MultiCANr+)
ERAY1 output
Reserved
L2
P01.14
TIN164
P01.14
TOUT164
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
TXEN1A
–
ERAY1 output
Reserved
Data Sheet
TOC-135
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-28 Port 01 Functions (cont’d)
Pin
L1
Symbol
Ctrl
Type
Function
P01.15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN157
DSDIN7A
DSADC channel 7 input A
General-purpose output
GTM output
P01.15
O0
O1
O2
O3
O4
O5
O6
O7
TOUT157
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-29 Port 02 Functions
Pin
B2
Symbol
P02.0
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN0
REQ6
SCU input
ARX2G
CC60INA
CC60INB
CIFD0
ASCLIN2 input
CCU60 input
CCU61 input
CIF input
P02.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY0 output
CCU60 output
SLSO31
DSCGPWMN
TXDCAN0
TXD0A
CC60
Data Sheet
TOC-136
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-29 Port 02 Functions (cont’d)
Pin
B1
Symbol
P02.1
Ctrl
Type
Function
I
LP / PU1 General-purpose input
/ VEXT
TIN1
GTM input
REQ14
ARX2B
RXDCAN0A
RXD0A2
CIFD1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY0 input
CIF input
P02.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT1
SLSO47
SLSO32
DSCGPWMP
–
QSPI4 output
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
P02.2
CCU60 output
E2
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN2
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
PSI5 output
SLSO33
PSITX0
TXDCAN2
TXD0B
CC61
CAN node 2 output
ERAY0 output
CCU60 output
Data Sheet
TOC-137
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-29 Port 02 Functions (cont’d)
Pin
F2
Symbol
P02.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN3
ARX1G
RXDCAN2B
RXD0B2
PSIRX0B
DSCIN5B
SDI11
ASCLIN1 input
CAN node 2 input
ERAY0 input
PSI5 input
DSADC channel 5 input B
MSC1 input
CIFD3
CIF input
P02.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
DSCOUT5
–
ASCLIN2 output
QSPI3 output
DSADC channel 5 output
Reserved
–
Reserved
COUT61
P02.4
CCU60 output
General-purpose input
GTM input
C1
MP+ /
PU1 /
VEXT
TIN4
SLSI3A
ECTT1
RXDCAN0D
CC62INA
CC62INB
DSDIN5B
SDA0A
CIFD4
QSPI3 input
TTCAN input
CAN node 0 input
CCU60 input
CCU61 input
DSADC channel 5 input B
I2C0 input
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXEN0A
CC62
ERAY0 output
CCU60 output
Data Sheet
TOC-138
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-29 Port 02 Functions (cont’d)
Pin
D4
Symbol
P02.5
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN5
MRST3A
ECTT2
QSPI3 input
TTCAN input
PSIRX1B
PSISRXB
SENT3C
DSCIN4B
SCL0A
PSI5 input
PSI5-S input
SENT input
DSADC channel 4 input B
I2C0 input
CIFD5
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
DSCOUT4
SCL0
CAN node 0 output
QSPI3 output
DSADC channel 4 output
I2C0 output
TXEN0B
COUT62
P02.6
ERAY0 output
CCU60 output
General-purpose input
GTM input
H2
MP /
PU1 /
VEXT
TIN6
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
DSDIN4B
DSITR5E
P02.6
DSADC channel 4 input B
DSADC channel 5 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
Data Sheet
TOC-139
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-29 Port 02 Functions (cont’d)
Pin
H1
Symbol
P02.7
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN7
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
DSITR4E
P02.7
DSADC channel 3 input B
DSADC channel 4 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSCOUT3
VADCEMUX01
SPC1
DSADC channel 3 output
VADC output
SENT output
CC61
CCU60 output
Data Sheet
TOC-140
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-29 Port 02 Functions (cont’d)
Pin
J3
Symbol
P02.8
Ctrl
Type
Function
I
LP / PU1 General-purpose input
/
TIN8
GTM input
VEXT
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
CIFD8
DSDIN3B
DSITR3E
P02.8
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
E4
P02.9
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN116
P02.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT116
ATX2
ASCLIN2 output
Reserved
–
–
Reserved
TXDCAN1
–
CAN node 1 output
Reserved
–
Reserved
Data Sheet
TOC-141
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-29 Port 02 Functions (cont’d)
Pin
F4
Symbol
Ctrl
Type
Function
P02.10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN117
ARX2C
ASCLIN2 input
CAN node 1 input
General-purpose output
GTM output
Reserved
RXDCAN1E
P02.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT117
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
C2
P02.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN118
P02.11
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT118
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
D3
P02.12
TIN151
P02.12
TOUT151
SLSO35
SLSO44
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
QSPI3 output
QSPI4 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-142
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-29 Port 02 Functions (cont’d)
Pin
D1
Symbol
P02.13
TIN153
P02.13
TOUT153
SLSO37
SLSO46
TXDCAN0
TXDCANr0
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
QSPI3 output
QSPI4 output
CAN node 0 output
CAN node 0 output (MultiCANr+)
Reserved
–
Reserved
E1
P02.14
TIN154
RXDCAN0H
RXDCANr0D
P02.14
TOUT154
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
CAN node 0 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
D2
P02.15
TIN152
P02.15
TOUT152
SLSO36
SLSO45
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
QSPI3 output
QSPI4 output
Reserved
–
Reserved
TXEN1B
–
ERAY1 output
Reserved
Data Sheet
TOC-143
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-30 Port 10 Functions
Pin
A9
Symbol
P10.0
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN102
T6EUDB
P10.0
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT102
–
Reserved
SLSO110
–
QSPI1 output
Reserved
VADCG6BFL0
–
VADC output
Reserved
–
Reserved
B8
P10.1
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL1
END03
–
A7
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
REQ2
QSPI1 input
GPT120 input
SCU input
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL2
END02
–
Data Sheet
TOC-144
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-30 Port 10 Functions (cont’d)
Pin
B7
Symbol
P10.3
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG6BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
A8
P10.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN106
MTSR1C
CCPOS0C
T3INB
QSPI1 input
CCU60 input
GPT120 input
General-purpose output
GTM output
P10.4
O0
O1
O2
O3
O4
O5
O6
O7
TOUT106
–
Reserved
SLSO18
MTSR1
EN00
QSPI1 output
QSPI1 output
MSC0 output
MSC0 output
Reserved
END02
–
Data Sheet
TOC-145
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-30 Port 10 Functions (cont’d)
Pin
A6
Symbol
P10.5
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
RXDCANr0A
INJ01
SCU input
CAN node 0 input (MultiCANr+)
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
SLSO38
SLSO19
T6OUT
QSPI1 output
GPT120 output
ASCLIN2 output
PSI5 output
ASLSO2
PSITX3
P10.6
G2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
ASCLIN2 input
QSPI3 input
MTSR3B
PSIRX3C
HWCFG5
P10.6
PSI5 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
ASCLIN2 output
QSPI3 output
T3OUT
GPT120 output
CAN node 0 output (MultiCANr+)
QSPI1 output
TXDCANr0
MRST1
VADCG7BFL0
VADC output
Data Sheet
TOC-146
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-30 Port 10 Functions (cont’d)
Pin
B4
Symbol
P10.7
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN109
ACTS2A
MRST3B
REQ4
ASCLIN2 input
QSPI3 input
SCU input
CCPOS1C
T3EUDB
P10.7
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT109
–
Reserved
MRST3
VADCG7BFL1
TXDCANr0
–
QSPI3 output
VADC output
CAN node 0 output (MultiCANr+)
Reserved
–
Reserved
A4
P10.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN110
SCLK3B
REQ5
QSPI3 input
SCU input
CCPOS2C
T4INB
RXDCANr0B
P10.8
CCU60 input
GPT120 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT110
ARTS2
SCLK3
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-147
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-30 Port 10 Functions (cont’d)
Pin
B6
Symbol
Ctrl
Type
Function
P10.9
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN265
SENT10C
SENT input
General-purpose output
GTM output
Reserved
P10.9
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT265
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
C4
P10.10
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN266
SENT11C
SENT input
General-purpose output
GTM output
Reserved
P10.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT266
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
A3
P10.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN269
SENT14C
SENT input
General-purpose output
GTM output
Reserved
P10.11
O0
O1
O2
O3
O4
O5
O6
O7
TOUT269
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-148
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-30 Port 10 Functions (cont’d)
Pin
B3
Symbol
Ctrl
Type
Function
P10.13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN268
SENT13C
SENT input
General-purpose output
GTM output
Reserved
P10.13
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT268
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
C3
P10.14
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN267
SENT12C
SENT input
General-purpose output
GTM output
Reserved
P10.14
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT267
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
A2
P10.15
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN270
P10.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT270
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-149
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-31 Port 11 Functions
Pin
Symbol
P11.0
TIN119
ARX3B
P11.0
TOUT119
ATX3
Ctrl
Type
Function
D11
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
ASCLIN3 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
ETHTXD3
–
ETH output
Reserved
C11
P11.1
TIN120
P11.1
TOUT120
ASCLK3
ATX3
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
–
–
Reserved
ETHTXD2
–
ETH output
Reserved
D10
P11.2
TIN95
P11.2
TOUT95
END03
SLSO05
SLSO15
EN01
MPR/
PU1 /
VFLEX
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
CCU60 output
Data Sheet
TOC-150
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-31 Port 11 Functions (cont’d)
Pin
A5
Symbol
P11.3
TIN96
MRST1B
SDI03
P11.3
TOUT96
–
Ctrl
Type
Function
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST1
TXD0A
–
QSPI1 output
ERAY0 output
Reserved
ETHTXD0
COUT62
P11.4
TIN121
ETHRXCLKB
P11.4
TOUT121
ASCLK3
–
ETH output
CCU60 output
General-purpose input
GTM input
C10
MP+ /
PU1 /
VFLEX
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
ETHTXER
–
ETH output
Reserved
B10
P11.5
TIN122
ETHTXCLKA
P11.5
TOUT122
–
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-151
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-31 Port 11 Functions (cont’d)
Pin
C6
Symbol
P11.6
TIN97
SCLK1B
P11.6
TOUT97
TXEN0B
SCLK1
TXEN0A
FCLP0
ETHTXEN
COUT61
P11.7
TIN123
ETHRXD3
P11.7
TOUT123
–
Ctrl
Type
Function
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
General-purpose output
GTM output
ERAY0 output
QSPI1 output
ERAY0 output
MSC0 output
ETH output
O0
O1
O2
O3
O4
O5
O6
O7
I
CCU60 output
General-purpose input
GTM input
A10
LP /
PU1 /
VFLEX
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
C9
P11.8
TIN124
ETHRXD2
P11.8
TOUT124
–
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-152
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-31 Port 11 Functions (cont’d)
Pin
B5
Symbol
P11.9
Ctrl
Type
Function
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
TIN98
MTSR1B
RXD0A1
ETHRXD1
P11.9
QSPI1 input
ERAY0 input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT98
–
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
MSC0 output
Reserved
–
COUT60
P11.10
TIN99
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXD0B1
ETHRXD0
SDI00
P11.10
TOUT99
–
CCU60 output
General-purpose input
GTM input
D5
LP /
PU1 /
VFLEX
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY0 input
ETH input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
Data Sheet
TOC-153
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-31 Port 11 Functions (cont’d)
Pin
D6
Symbol
P11.11
Ctrl
Type
Function
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
TIN100
ETHCRSDVA
ETHRXDVA
ETHCRSB
P11.11
ETH input
ETH input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT100
END02
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY0 output
CCU60 output
General-purpose input
GTM input
SLSO04
SLSO14
EN00
TXEN0B
CC61
C5
P11.12
MPR /
PU1 /
VFLEX
TIN101
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
ETHRXCLKA
ETH input
(Not for productive purposes)
P11.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT101
ATX1
ASCLIN1 output
GTM output
GTMCLK2
TXD0B
ERAY0 output
CAN node 3 output
SCU output
TXDCAN3
EXTCLK1
CC60
CCU60 output
Data Sheet
TOC-154
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-31 Port 11 Functions (cont’d)
Pin
B9
Symbol
Ctrl
Type
Function
P11.13
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN125
ETHRXERA
ETH input
SDA1A
I2C1 input
P11.13
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT125
–
–
Reserved
–
Reserved
–
Reserved
SDA1
I2C1 output
Reserved
–
C8
P11.14
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN126
ETHCRSDVB
ETH input
ETHRXDVB
ETH input
ETHCRSA
ETH input
SCL1A
I2C1 input
P11.14
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT126
–
–
Reserved
–
Reserved
–
Reserved
SCL1
I2C1 output
Reserved
–
C7
P11.15
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN127
ETHCOL
ETH input
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT127
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-155
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-32 Port 12 Functions
Pin
Symbol
Ctrl
Type
Function
A11
P12.0
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN128
ETHRXCLKC
ETH input
RXDCAN0C
CAN node 0 input
General-purpose output
GTM output
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT128
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDC
ETH output
–
Reserved
B11
P12.1
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN129
P12.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT129
ASLSO3
ASCLIN3 output
Reserved
–
–
Reserved
TXDCAN0
CAN node 0 output
Reserved
–
–
Reserved
ETHMDIOC
HWOU
T
ETH input/output
Table 2-33 Port 13 Functions
Pin
Symbol
P13.0
Ctrl
Type
Function
C17
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN91
P13.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT91
END03
SCLK2N
EN01
MSC0 output
QSPI2 output (LVDS)
MSC0 output
FCLN0
FCLND0
–
MSC0 output (LVDS)
MSC0 output (LVDS)
Reserved
Data Sheet
TOC-156
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-33 Port 13 Functions (cont’d)
Pin
Symbol
P13.1
TIN92
SCL0B
P13.1
TOUT92
–
Ctrl
Type
Function
C18
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
–
MSC0 output (LVDS)
I2C0 output
Reserved
D17
P13.2
TIN93
CAPINA
SDA0B
P13.2
TOUT93
–
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MTSR2N
FCLP0
SON0
SDA0
SOND0
P13.3
TIN94
P13.3
TOUT94
–
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
MSC0 output (LVDS)
General-purpose input
GTM input
C16
LVDSM_P /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR2P
–
QSPI2 output (LVDS)
Reserved
SOP0
–
MSC0 output (LVDS)
Reserved
–
Reserved
Data Sheet
TOC-157
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-33 Port 13 Functions (cont’d)
Pin
Symbol
P13.4
TIN253
PSIRX4A
P13.4
TOUT253
END22
–
Ctrl
Type
Function
B17
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
PSI5 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC2 output
Reserved
EN20
FCLN2
FCLND2
–
MSC2 output
MSC2 output (LVDS)
MSC2 output (LVDS)
Reserved
A17
P13.5
TIN254
P13.5
TOUT254
–
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
FCLP2
–
MSC2 output (LVDS)
Reserved
–
Reserved
A16
P13.6
TIN255
P13.6
TOUT255
–
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
SON2
SOND2
–
MSC2 output (LVDS)
MSC2 output (LVDS)
Reserved
Data Sheet
TOC-158
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-33 Port 13 Functions (cont’d)
Pin
Symbol
P13.7
TIN256
P13.7
TOUT256
–
Ctrl
Type
Function
B16
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
SOP2
–
MSC2 output (LVDS)
Reserved
–
Reserved
C12
P13.9
TIN248
SCL1B
P13.9
TOUT248
ATX3
SLSO55
–
MP /
PU1 /
VEXT
General-purpose input
GTM input
I2C1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI5 output
Reserved
TXDCANr1
SCL1
–
CAN node 1 output (MultiCANr+)
I2C1 output
Reserved
A13
P13.10
TIN251
PSIRX3A
P13.10
TOUT251
ATX0
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
PSI5 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-159
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-33 Port 13 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
B13
P13.11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN250
ARX0E
ASCLIN0 input
General-purpose output
GTM output
P13.11
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT250
–
Reserved
–
Reserved
–
Reserved
PSITX3
PSI5 output
–
Reserved
–
Reserved
B12
P13.12
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN249
ARX3H
ASCLIN3 input
CAN node 1 input (MultiCANr+)
I2C1 input
RXDCANr1B
SDA1B
P13.12
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT249
–
Reserved
–
Reserved
–
Reserved
–
Reserved
SDA1
I2C1 output
–
Reserved
A12
P13.14
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN252
P13.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT252
–
Reserved
SLSO54
QSPI5 output
Reserved
–
–
–
–
Reserved
Reserved
Reserved
Data Sheet
TOC-160
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-34 Port 14 Functions
Pin
Symbol
P14.0
Ctrl
Type
Function
C21
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN80
SENT12D
P14.0
SENT input
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin
TXD0A
O3
O4
O5
ERAY0 output
ERAY0 output
TXD0B
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function
ASCLK0
COUT62
P14.1
O6
O7
I
ASCLIN0 output
CCU60 output
General-purpose input
GTM input
D21
MP /
PU1 /
VEXT
TIN81
REQ15
SENT13D
ARX0A
SCU input
SENT input
ASCLIN0 input
Recommended as Boot loader pin
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function
RXD0A3
RXD0B3
EVRWUPA
P14.1
ERAY0 input
ERAY0 input
SCU input
O0
O1
O2
General-purpose output
GTM output
TOUT81
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
–
O3
O4
O5
O6
O7
Reserved
Reserved
Reserved
Reserved
CCU60 output
–
–
–
COUT63
Data Sheet
TOC-161
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-34 Port 14 Functions (cont’d)
Pin
Symbol
P14.2
Ctrl
Type
Function
D20
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN82
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
SLSO21
–
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
C14
P14.3
TIN83
ARX2A
REQ10
HWCFG3_BMI
SDI02
P14.3
TOUT83
ATX2
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN2 input
SCU input
SCU input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
Data Sheet
TOC-162
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-34 Port 14 Functions (cont’d)
Pin
Symbol
P14.4
Ctrl
Type
Function
D13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN84
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT84
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
C20
P14.5
TIN85
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
TOUT85
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
TXD0B
TXD1B
P14.6
TIN86
ERAY0 output
ERAY1 output
General-purpose input
GTM input
C13
MP+ /
PU1 /
VEXT
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
TOUT86
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO22
–
QSPI2 output
Reserved
–
Reserved
TXEN0B
TXEN1B
ERAY0 output
ERAY1 output
Data Sheet
TOC-163
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-34 Port 14 Functions (cont’d)
Pin
Symbol
P14.7
TIN87
RXD0B0
RXD1B0
P14.7
TOUT87
ARTS0
SLSO24
–
Ctrl
Type
Function
D12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ERAY0 input
ERAY1 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
–
Reserved
A14
P14.8
TIN88
ARX1D
RXDCAN2D
RXD0A0
RXD1A0
P14.8
TOUT88
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
CAN node 2 input
ERAY0 input
ERAY1 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
C19
P14.9
TIN89
ACTS0A
P14.9
TOUT89
END03
EN01
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
MSC0 output
MSC0 output
Reserved
TXEN0B
TXEN0A
TXEN1A
ERAY0 output
ERAY0 output
ERAY1 output
Data Sheet
TOC-164
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-34 Port 14 Functions (cont’d)
Pin
Symbol
P14.10
TIN90
P14.10
TOUT90
END02
EN00
ATX1
TXDCAN2
TXD0A
TXD1A
P14.11
TIN258
P14.11
TOUT258
END20
PSITX4
EN22
SOP2
–
Ctrl
Type
Function
C15
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC0 output
MSC0 output
ASCLIN1 output
CAN node 2 output
ERAY0 output
ERAY1 output
General-purpose input
GTM input
A19
LP /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC2 output
PSI5 output
MSC2 output
MSC2 output
Reserved
–
Reserved
A15
P14.12
TIN261
SDI20
P14.12
TOUT261
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
MSC2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-165
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-34 Port 14 Functions (cont’d)
Pin
Symbol
P14.13
TIN260
P14.13
TOUT260
END23
–
Ctrl
Type
Function
B19
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC2 output
Reserved
EN21
–
MSC2 output
Reserved
–
Reserved
–
Reserved
B15
P14.14
TIN259
P14.14
TOUT259
END22
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
MSC2 output
Reserved
EN20
–
MSC2 output
Reserved
–
Reserved
–
Reserved
B14
P14.15
TIN263
INJ21
P14.15
TOUT263
ATX1
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
MSC2 output
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
ASCLIN1 output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-166
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-35 Port 15 Functions
Pin
Symbol
P15.1
Ctrl
Type
Function
C22
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN72
REQ16
ARX1A
RXDCAN2A
SLSI2B
EVRWUPB
P15.1
SCU input
ASCLIN1 input
CAN node 2 input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT72
ATX1
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
Reserved
–
Reserved
–
Reserved
B21
P15.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN73
SLSI2A
MRST2E
SENT10D
HSIC2INA
P15.2
QSPI2 input
QSPI2 input
SENT input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT73
ATX0
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
Data Sheet
TOC-167
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-35 Port 15 Functions (cont’d)
Pin
Symbol
P15.3
Ctrl
Type
Function
D18
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN74
ARX0B
SCLK2A
RXDCAN1A
HSIC2INB
P15.3
ASCLIN0 input
QSPI2 input
CAN node 1 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT74
ATX0
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
A21
P15.4
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN75
MRST2A
REQ0
SCL0C
SENT11D
P15.4
QSPI2 input
SCU input
I2C0 input
SENT input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT75
ATX1
ASCLIN1 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
SCL0
I2C0 output
CC62
CCU60 output
Data Sheet
TOC-168
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-35 Port 15 Functions (cont’d)
Pin
Symbol
P15.5
Ctrl
Type
Function
D19
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN76
ARX1B
MTSR2A
REQ13
SDA0C
P15.5
ASCLIN1 input
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT76
ATX1
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
General-purpose input
GTM input
B20
P15.6
MP /
PU1 /
VEXT
TIN77
MTSR2B
P15.6
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT77
ATX3
ASCLIN3 output
QSPI2 output
QSPI5 output
QSPI2 output
ASCLIN3 output
CCU60 output
General-purpose input
GTM input
MTSR2
SLSO53
SCLK2
ASCLK3
CC60
A20
P15.7
MP /
PU1 /
VEXT
TIN78
ARX3A
MRST2B
P15.7
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT78
ATX3
ASCLIN3 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
TOC-169
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-35 Port 15 Functions (cont’d)
Pin
Symbol
P15.8
TIN79
SCLK2B
REQ1
P15.8
TOUT79
–
Ctrl
Type
Function
D16
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
ASCLIN3 output
CCU60 output
Table 2-36 Port 20 Functions
Pin
Symbol
P20.0
Ctrl
Type
Function
A24
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN59
RXDCAN3C
RXDCANr1C
T6EUDA
REQ9
CAN node 3 input
CAN node 1 input (MultiCANr+)
GPT120 input
SCU input
SYSCLK
TGI0
HSCT input
OCDS input
P20.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT59
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
Data Sheet
TOC-170
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-36 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
B23
P20.2
I
LP /
General-purpose input
PU1 /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
OCDS input
P20.2
O0
O1
O2
O3
O4
O5
O6
O7
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
–
–
–
–
–
–
–
Table 2-37 Port 21 Functions
Pin
J23
Symbol
P21.0
TIN51
MRST4DN
HOLD
P21.0
TOUT51
–
Ctrl
Type
Function
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
QSPI4 input (LVDS)
EBU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDC
BAABA0
ETH output
EBU output
(combined for BAA and BA0)
HSM1
O
HSM output
Data Sheet
TOC-171
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-37 Port 21 Functions (cont’d)
Pin
Symbol
P21.1
Ctrl
Type
Function
G24
I
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
TIN52
ETHMDIOB
ETH input
(Not for production purposes)
MRST4DP
QSPI4 input (LVDS)
EBU input
WAIT
P21.1
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM output
Reserved
TOUT52
–
–
Reserved
–
Reserved
–
Reserved
ETHMDIO
ETH output
(Not for production purposes)
BREQBA1
O7
EBU output
(combined for BREQ and BA1)
HSM2
O
I
HSM output
H23
P21.2
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
TIN53
MRST2CN
MRST4CN
ARX3GN
EMGSTOPB
RXDN
QSPI2 input (LVDS)
QSPI4 input (LVDS)
ASCLIN3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
P21.2
O0
O1
O2
O3
O4
O5
O6
O7
TOUT53
ASLSO3
–
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
SDRAMA8
–
ETH output
EBU output
Reserved
Data Sheet
TOC-172
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-37 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
G23
P21.3
I
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
TIN54
MRST2CP
QSPI2 input (LVDS)
QSPI4 input (LVDS)
ASCLIN3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
MRST4CP
ARX3GP
RXDP
P21.3
O0
TOUT54
O1
–
O2
Reserved
–
O3
Reserved
–
O4
Reserved
–
O5
Reserved
SDRAMA9
O6
EBU output
–
O7
Reserved
ETHMDIOD
HWOUT
I
ETH input/output
General-purpose input
GTM input
D26
P21.4
LVDSH_N/
PU1 /
VDDP3
TIN55
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
TOUT55
–
Reserved
–
Reserved
–
Reserved
–
Reserved
SDRAMA10
EBU output
–
Reserved
TXDN
P21.5
TIN56
P21.5
TOUT56
ASCLK3
–
HSCT output (LVDS)
General-purpose input
GTM input
C26
LVDSH_P/
PU1 /
VDDP3
O0
General-purpose output
GTM output
O1
O2
ASCLIN3 output
Reserved
O3
–
O4
Reserved
–
O5
Reserved
SDRAMA11
–
O6
EBU output
O7
Reserved
TXDP
HSCT
HSCT output (LVDS)
Data Sheet
TOC-173
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-37 Port 21 Functions (cont’d)
Pin
Symbol
P21.6
Ctrl
Type
Function
E25
I
A2 /
PU /
VDDP3
General-purpose input
GTM input
TIN57
ARX3F
TGI2
ASCLIN3 input
OCDS input
TDI
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
O0
TOUT57
ASLSO3
–
O1
O2
ASCLIN3 output
Reserved
O3
–
O4
Reserved
SYSCLK
SDRAMA12
T3OUT
TGO2
P21.7
O5
HSCT output
O6
EBU output
O7
GPT120 output
OCDS; ENx
HWOUT
I
D25
A2 /
PU /
VDDP3
General-purpose input
GTM input
TIN58
DAP2
OCDS (3-Pin DAP) input
In the 3-Pin DAP mode this pin is used as DAP2.
In the 2-PIN DAP mode this pin is used as P21.7
and controlled by the related port control logic
TGI3
OCDS input
ETHRXERB
T5INA
P21.7
ETH input
GPT120 input
General-purpose output
GTM output
O0
TOUT58
ATX3
O1
O2
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
O3
O4
–
O5
Reserved
SDRAMA13
T6OUT
TGO3
TDO
O6
EBU output
O7
GPT120 output
OCDS; ENx
HWOUT
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ.
DAP2
OCDS (3-Pin DAP); ENx
In the 3-Pin DAP mode this pin is used as DAP2.
Data Sheet
TOC-174
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-38 Port 22 Functions
Pin
Symbol
P22.0
Ctrl
Type
Function
K23
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN47
MTSR4B
P22.0
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT47
ATX3N
MTSR4
SCLK4N
FCLN1
FCLND1
–
ASCLIN3 output (LVDS)
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
J24
P22.1
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
TIN48
MRST4B
P22.1
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT48
ATX3P
MRST4
SCLK4P
FCLP1
–
ASCLIN3 output (LVDS)
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
J25
P22.2
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN49
SLSI4B
P22.2
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT49
–
Reserved
SLSO43
MTSR4N
SON1
SOND1
–
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
TOC-175
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-38 Port 22 Functions (cont’d)
Pin
J26
Symbol
P22.3
TIN50
SCLK4B
P22.3
TOUT50
–
Ctrl
Type
Function
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK4
MTSR4P
SOP1
–
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
Table 2-39 Port 23 Functions
Pin
Symbol
P23.0
TIN41
P23.0
TOUT41
–
Ctrl
Type
Function
General-purpose input
M26
I
LP /
PU1 /
VEXT
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
L24
P23.1
TIN42
SDI10
P23.1
TOUT42
ARTS1
SLSO46
GTMCLK0
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
MSC1 input
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
GTM output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
EXTCLK0
–
SCU output
Reserved
Data Sheet
TOC-176
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-39 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
L25
P23.2
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN43
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT43
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
L26
P23.3
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN44
INJ10
MSC1 input
General-purpose output
GTM output
Reserved
P23.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT44
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
K24
P23.4
TIN45
P23.4
TOUT45
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO45
END12
EN10
–
QSPI4 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Data Sheet
TOC-177
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-39 Port 23 Functions (cont’d)
Pin
Symbol
P23.5
TIN46
P23.5
TOUT46
–
Ctrl
Type
Function
K25
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO44
END13
EN11
–
QSPI4 output
MSC1 output
MSC1 output
Reserved
–
Reserved
K26
P23.6
TIN138
P23.6
TOUT138
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
SLSO011
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
Table 2-40 Port 24 Functions
Pin
Symbol
Ctrl
Type
Function
U23
P24.0
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN222
P24.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT222
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ11
A11
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-178
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-40 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
T24
P24.1
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN223
P24.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT223
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ15
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A15
T25
P24.2
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN224
P24.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT224
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ14
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A14
T26
P24.3
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN225
P24.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT225
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ13
A13
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-179
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-40 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
R24
P24.4
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN226
P24.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT226
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ9
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A9
R25
P24.5
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN227
P24.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT227
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ12
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A12
R26
P24.6
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN228
P24.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT228
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ5
A5
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-180
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-40 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
P24
P24.7
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN229
P24.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT229
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ8
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A8
P25
P24.8
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN230
P24.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT230
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ10
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A10
P26
P24.9
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN231
P24.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT231
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ6
A6
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-181
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-40 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
N23
P24.10
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN232
P24.10
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT232
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ4
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A4
N24
P24.11
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN233
P24.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT233
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ3
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A3
N25
P24.12
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN234
P24.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT234
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ1
A1
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-182
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-40 Port 24 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
N26
P24.13
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN235
P24.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT235
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ2
A2
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
M24
P24.14
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN236
P24.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT236
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ0
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
A0
M25
P24.15
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN237
P24.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT237
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
DQ7
A7
HWOU
T
EBU Data Bus Line (SDRAM)
EBU output
Data Sheet
TOC-183
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-41 Port 25 Functions
Pin
Symbol
Ctrl
Type
Function
AA26
P25.0
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN206
SDCLKI
EBU input
P25.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT206
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
BFCLKO
HWOU
T
EBU output
EBU output
General-purpose input
GTM input
SDCLKO
AA24
P25.1
I
A2 /
PU1 /
VEBU
TIN207
P25.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT207
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
RD
HWOU
T
EBU output
EBU output
General-purpose input
GTM input
RAS
AA23
P25.2
I
A2 /
PU1 /
VEBU
TIN208
P25.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT208
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
RD/WR
WR
HWOU
T
EBU output
EBU output
Data Sheet
TOC-184
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-41 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
Y24
P25.3
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN209
HOLDA
EBU input
P25.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT209
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
BAABA0
EBU output
(combined for BAA and BA0)
CS2
HWOU
T
EBU output
EBU output
EBU output
General-purpose input
GTM input
DQM1
HOLDA
Y25
P25.4
I
A2 /
PU1 /
VEBU
TIN210
P25.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT210
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CS1
HWOU
T
EBU output
EBU output
General-purpose input
GTM input
DQM0
Y26
P25.5
I
A2 /
PU1 /
VEBU
TIN211
P25.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT211
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CS0
HWOU
T
EBU output
Data Sheet
TOC-185
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-41 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
W24
P25.7
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN213
P25.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT213
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ADV
CAS
P25.8
TIN214
P25.8
TOUT214
–
HWOU
T
EBU output
EBU output
General-purpose input
GTM input
W25
I
A2 /
PU1 /
VEBU
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
A23
EBU output
EBU output
Reserved
SDRAMA0
–
BC0
HWOU
T
EBU output
W26
P25.9
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN215
P25.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT215
–
–
Reserved
–
Reserved
A22
EBU output
SDRAMA1
EBU output
–
Reserved
BC1
HWOU
T
EBU output
Data Sheet
TOC-186
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-41 Port 25 Functions (cont’d)
Pin
Symbol
P25.10
TIN216
P25.10
TOUT216
–
Ctrl
Type
Function
V24
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
A21
EBU output
EBU output
Reserved
SDRAMA2
–
BC2
HWOU
T
EBU output
V25
P25.11
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN217
P25.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT217
–
–
Reserved
–
Reserved
A20
EBU output
SDRAMA3
EBU output
–
Reserved
BC3
HWOU
T
EBU output
V26
P25.12
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN218
P25.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT218
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA4
EBU output
–
Reserved
A19
HWOU
T
EBU output
Data Sheet
TOC-187
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-41 Port 25 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
U24
P25.13
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN219
P25.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT219
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA5
EBU output
Reserved
–
A17
HWOU
T
EBU output
U25
P25.14
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN220
P25.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT220
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA6
EBU output
–
Reserved
A18
HWOU
T
EBU output
U26
P25.15
I
A2 /
PU1 /
VEBU
General-purpose input
GTM input
TIN221
P25.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT221
–
–
Reserved
–
Reserved
–
Reserved
SDRAMA7
EBU output
–
Reserved
A16
HWOU
T
EBU output
Data Sheet
TOC-188
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-42 Port 26 Functions
Pin
Symbol
Ctrl
Type
Function
AA25
P26.0
I
LP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN212
BFCLKI
EBU input
P26.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT212
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-43 Port 30 Functions
Pin
Symbol
Ctrl
Type
Function
AF22
P30.0
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN190
P30.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT190
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD14
HWOU
T
EBU Address / Data Bus Line
AF23
P30.1
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN191
P30.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT191
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD11
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-189
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-43 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AB24
P30.2
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN192
P30.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT192
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD12
HWOU
T
EBU Address / Data Bus Line
AC24
P30.3
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN193
P30.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT193
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD15
HWOU
T
EBU Address / Data Bus Line
AD24
P30.4
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN194
P30.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT194
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD8
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-190
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-43 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AE24
P30.5
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN195
P30.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT195
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD13
HWOU
T
EBU Address / Data Bus Line
AF24
P30.6
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN196
P30.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT196
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD4
HWOU
T
EBU Address / Data Bus Line
AB25
P30.7
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN197
P30.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT197
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD7
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-191
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-43 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AC25
P30.8
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN198
P30.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT198
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD3
HWOU
T
EBU Address / Data Bus Line
AD25
P30.9
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN199
P30.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT199
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD0
HWOU
T
EBU Address / Data Bus Line
AE25
P30.10
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN200
P30.10
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT200
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD5
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-192
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-43 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AF25
P30.11
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN201
P30.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT201
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD10
HWOU
T
EBU Address / Data Bus Line
AB26
P30.12
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN202
P30.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT202
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD9
HWOU
T
EBU Address / Data Bus Line
AC26
P30.13
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN203
P30.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT203
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD2
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-193
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-43 Port 30 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AD26
P30.14
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN204
P30.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT204
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD1
HWOU
T
EBU Address / Data Bus Line
AE26
P30.15
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN205
P30.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT205
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD6
HWOU
T
EBU Address / Data Bus Line
Table 2-44 Port 31 Functions
Pin
Symbol
Ctrl
Type
Function
AD18
P31.0
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN174
P31.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT174
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD30
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-194
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-44 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AE18
P31.1
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN175
P31.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT175
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD29
HWOU
T
EBU Address / Data Bus Line
AF18
P31.2
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN176
P31.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT176
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD28
HWOU
T
EBU Address / Data Bus Line
AD19
P31.3
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN177
P31.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT177
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD26
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-195
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-44 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AE19
P31.4
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN178
P31.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT178
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD24
HWOU
T
EBU Address / Data Bus Line
AF19
P31.5
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN179
P31.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT179
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD23
HWOU
T
EBU Address / Data Bus Line
AD20
P31.6
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN180
P31.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT180
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD20
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-196
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-44 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AE20
P31.7
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN181
P31.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT181
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD16
HWOU
T
EBU Address / Data Bus Line
AF20
P31.8
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN182
P31.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT182
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD31
HWOU
T
EBU Address / Data Bus Line
AD21
P31.9
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN183
P31.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT183
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD27
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-197
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-44 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AE21
P31.10
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN184
P31.10
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT184
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD21
HWOU
T
EBU Address / Data Bus Line
AF21
P31.11
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN185
P31.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT185
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD25
HWOU
T
EBU Address / Data Bus Line
AD22
P31.12
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN186
P31.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT186
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD19
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-198
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-44 Port 31 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AE22
P31.13
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN187
P31.13
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT187
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD22
HWOU
T
EBU Address / Data Bus Line
AD23
P31.14
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN188
P31.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT188
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD18
HWOU
T
EBU Address / Data Bus Line
AE23
P31.15
I
MP /
PU1 /
VFLEXE
General-purpose input
GTM input
TIN189
P31.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT189
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AD17
HWOU
T
EBU Address / Data Bus Line
Data Sheet
TOC-199
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-45 Port 32 Functions
Pin
Symbol
P32.0
Ctrl
Type
Function
AD17
I
LP /
PX/
VEXT
General-purpose input
GTM input
TIN36
FDEST
VGATE1N
PMU input
SMPS mode: analog output. External Pass Device
gate control for EVR13
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT36
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
AE13
P32.2
TIN38
ARX3D
RXDCAN3B
RXDCANr1D
P32.2
TOUT38
ATX3
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN3 input
CAN node 3 input
CAN node 1 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
DCDCSYNC
–
SCU output
Reserved
AF13
P32.3
TIN39
P32.3
TOUT39
ATX3
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
ASCLK3
TXDCAN3
TXDCANr1
–
ASCLIN3 output
CAN node 3 output
CAN node 1 output (MultiCANr+)
Reserved
Data Sheet
TOC-200
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-45 Port 32 Functions (cont’d)
Pin
Symbol
P32.4
TIN40
ACTS1B
SDI12
P32.4
TOUT40
–
Ctrl
Type
Function
AC14
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
END12
GTMCLK1
EN10
EXTCLK1
COUT63
P32.5
TIN140
P32.5
TOUT140
ATX2
–
MSC1 output
GTM output
MSC1 output
SCU output
CCU60 output
General-purpose input
GTM input
AD14
LP /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN2 output
Reserved
–
Reserved
–
Reserved
TXDCAN2
–
CAN node 2 output
Reserved
AE17
P32.6
TGI4
LP /
PU1 /
VEXT
General-purpose input
OCDS input
TIN141
RXDCAN2C
ARX2F
P32.6
TOUT141
–
GTM input
CAN node 2 input
ASCLIN2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
SLSO212
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
TGO4
HWOU
T
OCDS; ENx
Data Sheet
TOC-201
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-45 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
AF17
P32.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN142
TGI5
OCDS input
General-purpose output
GTM output
Reserved
P32.7
O0
O1
O2
O3
O4
O5
O6
O7
TOUT142
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO5
HWOU
T
OCDS; ENx
Table 2-46 Port 33 Functions
Pin
Symbol
Ctrl
Type
Function
AC11
P33.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN22
DSITR0E
DSADC channel 0 input E
General-purpose output
GTM output
P33.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT22
–
Reserved
–
Reserved
–
Reserved
–
Reserved
VADCG2BFL0
–
VADC output
Reserved
Data Sheet
TOC-202
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
P33.1
Ctrl
Type
Function
AD11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN23
PSIRX0C
SENT9C
DSCIN2B
DSITR1E
P33.1
PSI5 input
SENT input
DSADC channel 2 input B
DSADC channel 1 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT23
ASLSO3
SCLK2
ASCLIN3 output
QSPI2 output
DSCOUT2
VADCEMUX02
VADCG2BFL1
–
DSADC channel 2 output
VADC output
VADC output
Reserved
AE11
P33.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN24
SENT8C
DSDIN2B
DSITR2E
P33.2
SENT input
DSADC channel 2 input B
DSADC channel 2 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT24
ASCLK3
SLSO210
PSITX0
ASCLIN3 output
QSPI2 output
PSI5 output
VADCEMUX01
VADCG2BFL2
–
VADC output
VADC output
Reserved
Data Sheet
TOC-203
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
P33.3
Ctrl
Type
Function
AF11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN25
PSIRX1C
SENT7C
DSCIN1B
P33.3
PSI5 input
SENT input
DSADC channel 1 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT25
–
Reserved
–
Reserved
DSCOUT1
VADCEMUX00
VADCG2BFL3
–
DSADC channel 1 output
VADC output
VADC output
Reserved
AC12
P33.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN26
SENT6C
CTRAPC
DSDIN1B
DSITR0F
P33.4
SENT input
CCU61 input
DSADC channel 1 input
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
ASCLIN2 output
QSPI2 output
SLSO212
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
TOC-204
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
P33.5
Ctrl
Type
Function
AD12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN27
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
DSITR1F
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 1 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
AE12
P33.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN28
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
SLSO211
PSITX2
ASCLIN2 output
QSPI2 output
PSI5 output
VADCEMUX10
VADCG1BFL0
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
TOC-205
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
P33.7
Ctrl
Type
Function
AC15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN29
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO47
–
ASCLIN2 output
QSPI4 output
Reserved
–
Reserved
VADCG1BFL1
–
VADC output
Reserved
AD15
P33.8
MP /
HighZ /
VEXT
General-purpose input
GTM input
TIN30
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI4 output
Reserved
SLSO42
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
AF12
P33.9
TIN31
HSIC3INA
P33.9
TOUT31
ATX2
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI4 output
ASCLIN2 output
Reserved
SLSO41
ASCLK2
–
–
Reserved
CC62
CCU61 output
Data Sheet
TOC-206
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
P33.10
TIN32
Ctrl
Type
Function
AE14
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI4A
HSIC3INB
P33.10
TOUT32
SLSO16
SLSO40
ASLSO1
PSISCLK
–
QSPI4 input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
QSPI1 output
QSPI4 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
P33.11
TIN33
CCU61 output
General-purpose input
GTM input
AF14
MP /
PU1 /
VEXT
SCLK4A
P33.11
TOUT33
ASCLK1
SCLK4
–
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC channel output
CCU61 output
General-purpose input
GTM input
AF15
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR4A
P33.12
TOUT34
ATX1
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
ASCLIN1 output
Reserved
MTSR4
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
TOC-207
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
P33.13
TIN35
ARX1F
MRST4A
DSSGNB
INJ11
P33.13
TOUT35
ATX1
Ctrl
Type
Function
AE15
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
QSPI4 input
DSADC channel input B
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
QSPI2 output
Reserved
MRST4
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
General-purpose input
GTM input
AC13
P33.14
TIN143
TGI6
LP /
PU1 /
VEXT
OCDS input
SCLK2D
P33.14
TOUT143
–
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
CC62
CCU60 output
OCDS; ENx
TGO6
HWOU
T
Data Sheet
TOC-208
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-46 Port 33 Functions (cont’d)
Pin
Symbol
P33.15
TIN144
TGI7
Ctrl
Type
Function
AD13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
OCDS input
General-purpose output
GTM output
Reserved
P33.15
TOUT144
–
O0
O1
O2
O3
O4
O5
O6
O7
SLSO211
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
COUT62
TGO7
CCU60 output
OCDS; ENx
HWOU
T
Table 2-47 Port 34 Functions
Pin
Symbol
P34.1
TIN146
P34.1
TOUT146
ATX0
Ctrl
Type
Function
AC9
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
–
TXDCAN0
TXDCANr0
–
CAN node 0 output
CAN node 0 output (MultiCANr+)
Reserved
COUT63
P34.2
TIN147
ARX0D
RXDCAN0G
RXDCANr0C
P34.2
TOUT147
–
CCU60 output
General-purpose input
GTM input
AC10
LP /
PU1 /
VEXT
ASCLIN0 input
CAN node 0 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CC60
CCU60 output
Data Sheet
TOC-209
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-47 Port 34 Functions (cont’d)
Pin
Symbol
P34.3
TIN148
P34.3
TOUT148
–
Ctrl
Type
Function
AF10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
SLSO210
–
QSPI2 output
Reserved
–
Reserved
COUT60
P34.4
TIN149
MRST2D
P34.4
TOUT149
–
CCU60 output
General-purpose input
GTM input
AD10
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
MRST2
–
QSPI2 output
Reserved
–
Reserved
CC61
P34.5
TIN150
MTSR2D
P34.5
TOUT150
–
CCU60 output
General-purpose input
GTM input
AE10
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
MTSR2
–
QSPI2 output
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
TOC-210
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-48 Port 40 Functions
Pin
Symbol
P40.0
Ctrl
Type
Function
AC7
I
S /
General-purpose input
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
CCU60 input
HighZ /
VDDM
VADCG3.0
DS2PB
CCPOS0D
SENT0A
P40.1
SENT input
AD7
I
S /
General-purpose inpu.t
HighZ /
VDDM
VADCG3.1
VADC analog input channel 1 of group 3 (with pull
down diagnostics)
DS2NB
DSADC: negative analog input channel 2, pin B
CCU60 input
CCPOS1B
SENT1A
P40.2
SENT input
AA2
AB2
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADCG3.2
VADC analog input channel 2 of group 3 (with pull
down diagnostics)
CCPOS1D
SENT2A
P40.3
CCU60 input
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
CCPOS2B
SENT3A
P40.4
CCU60 input
SENT input
W3
Y3
V4
I
I
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 0 of group 4
CCU60 input
VADCG4.0
CCPOS2D
SENT4A
P40.5
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 1 of group 4
CCU61 input
VADCG4.1
CCPOS0D
SENT5A
P40.6
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
CCU61 input
VADCG4.4
DS3PA
CCPOS1B
SENT6A
SENT input
Data Sheet
TOC-211
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-48 Port 40 Functions (cont’d)
Pin
V3
Symbol
P40.7
Ctrl
Type
Function
I
S /
General-purpose input
HighZ /
VDDM
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input channel 3, pin A
CCU61 input
CCPOS1D
SENT7A
P40.11
SENT input
V2
W1
U2
V1
I
I
I
I
S /
HighZ /
VDDM
General-purpose input
VADCG10.4
DS8PA
VADC analog input channel 4 of group 10
DSADC: positive analog input of channel 8, pin A
SENT input
SENT11A
P40.12
S /
HighZ /
VDDM
General-purpose input
VADCG10.5
DS8NA
VADC analog input channel 5 of group 10
DSADC: positive analog input of channel 8, pin A
SENT input
SENT12A
P40.13
S /
HighZ /
VDDM
General-purpose input
VADCG10.6
DS9PA
VADC analog input channel 6 of group 10
DSADC: positive analog input of channel 9, pin A
SENT input
SENT13A
P40.14
S /
General-purpose input
HighZ /
VDDM
VADCG10.7
DS9NA
VADC analog input channel 7 of group 10
DSADC: positive analog input of channel 9, pin A
SENT input
SENT14A
Table 2-49 Analog Inputs
Pin
Symbol
AN0
Ctrl
Type
Function
AC5
I
D / HighZ / Analog input 0
VDDM
VADCG0.0
DS1PA
AN1
VADC analog input channel 0 of group 0
DSADC: positive analog input of channel 1, pin A
D / HighZ / Analog input 1
AD5
AE4
AF4
AC2
I
I
I
I
VDDM
VADCG0.1
DS1NA
AN2
VADC analog input channel 1 of group 0
DSADC: negative analog input channel 1, pin A
D / HighZ / Analog input 2
VDDM
VADCG0.2
DS0PA
AN3
VADC analog input channel 2 of group 0
DSADC: positive analog input of channel 0, pin A
D / HighZ / Analog input 3
VDDM
VADCG0.3
DS0NA
AN4
VADC analog input channel 3 of group 0
DSADC: negative analog input channel 0, pin A
D / HighZ / Analog input 4
VDDM
VADCG0.4
VADC analog input channel 4 of group 0
Data Sheet
TOC-212
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-49 Analog Inputs (cont’d)
Pin
Symbol
AN5
Ctrl
Type
Function
AA3
I
D / HighZ / Analog input 5
VDDM
VADCG0.5
AN6
VADC analog input channel 5 of group 0
AD1
AB4
AC4
AD4
AE3
AF3
I
I
I
I
I
I
D / HighZ / Analog input 6
VDDM
VADCG0.6
AN7
VADC analog input channel 6 of group 0
D / HighZ / Analog input 7
VDDM
VADCG0.7
AN8
VADC analog input channel 7 of group 0
D / HighZ / Analog input 8
VDDM
VADCG1.0
AN9
VADC analog input channel 0 of group 1
D / HighZ / Analog input 9
VDDM
VADCG1.1
AN10
VADC analog input channel 1 of group 1
D / HighZ / Analog input 10
VDDM
VADCG1.2
AN11
VADC analog input channel 2 of group 1
D / HighZ / Analog input 11
VDDM
VADCG1.3
VADC analog input channel 3 of group 1 (with pull
down diagnostics)
AC3
AD3
AE2
AF2
AN16
I
I
I
I
D / HighZ / Analog input 16
VDDM
VADCG2.0
AN17
VADC analog input channel 0 of group 2
D / HighZ / Analog input 17
VDDM
VADCG2.1
AN18
VADC analog input channel 1 of group 2
D / HighZ / Analog input 18
VDDM
VADCG2.2
AN19
VADC analog input channel 2 of group 2
D / HighZ / Analog input 19
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
AC8
AD8
AN20
I
I
D / HighZ / Analog input 20
VDDM
VADCG2.4
DS2PA
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 2, pin A
D / HighZ / Analog input 21
AN21
VDDM
VADCG2.5
DS2NA
VADC analog input channel 5 of group 2
DSADC: negative analog input channel 2, pin A
AE8
AF8
AC7
AN22
I
I
I
D / HighZ / Analog input 22
VDDM
VADCG2.6
AN23
VADC analog input channel 6 of group 2
D / HighZ / Analog input 23
VDDM
VADCG2.7
AN24
VADC analog input channel 7 of group 2
Analog input 24
S /
HighZ /
VDDM
VADCG3.0
DS2PB
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
SENT input channel 0, pin A
SENT0A
Data Sheet
TOC-213
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-49 Analog Inputs (cont’d)
Pin
Symbol
AN25
Ctrl
Type
Function
AD7
I
S /
Analog input 24
HighZ /
VDDM
VADCG3.1
VADC analog input channel 1 of group 3 (with pull
down diagnostics)
DS2NB
DSADC: negative analog input channel 2, pin B
SENT input channel 1, pin A
Analog input 26
SENT1A
AN26
AA2
AB2
I
I
S /
HighZ /
VDDM
VADCG3.2
VADC analog input channel 2 of group 3 (with pull
down diagnostics)
SENT2A
AN27
SENT input channel 2, pin A
Analog input 27
S /
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
SENT3A
AN28
SENT input channel 3, pin A
AB1
AC1
W3
I
I
I
D / HighZ / Analog input 28
VDDM
VADCG3.4
VADC analog input channel 4 of group 3 (with pull
down diagnostics)
AN29
D / HighZ / Analog input 29
VDDM
VADCG3.5
VADC analog input channel 5 of group 3 (with pull
down diagnostics)
AN32
S /
Analog input 32
HighZ /
VDDM
VADCG4.0
SENT4A
AN33
VADC analog input channel 0 of group 4
SENT input channel 4, pin A
Analog input 33
Y3
V4
I
I
S /
HighZ /
VDDM
VADCG4.1
SENT5A
AN36
VADC analog input channel 1 of group 4
SENT input channel 5, pin A
Analog input 34
S /
HighZ /
VDDM
VADCG4.4
DS3PA
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
SENT input channel 6, pin A
Analog input 37
SENT6A
AN37
V3
I
S /
HighZ /
VDDM
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input channel 3, pin A
SENT input channel 7, pin A
SENT7A
AN40
U4
U3
T1
I
I
I
D / HighZ / Analog input 40
VDDM
VADCG5.0
AN41
VADC analog input channel 0 of group 5
D / HighZ / Analog input 41
VDDM
VADCG5.1
AN42
VADC analog input channel 1 of group 5
D / HighZ / Analog input 42
VDDM
VADCG5.2
VADC analog input channel 2 of group 5
Data Sheet
TOC-214
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-49 Analog Inputs (cont’d)
Pin
U1
Symbol
AN43
Ctrl
Type
Function
I
D / HighZ / Analog input 43
VDDM
VADCG5.3
VADC analog input channel 3 of group 5 (with pull
down diagnostics)
AD2
AE1
AE6
AN48
I
I
I
D / HighZ / Analog input 48
VDDM
VADCG8.0
AN49
VADC analog input channel 0 of group 8
D / HighZ / Analog input 49
VDDM
VADCG8.1
AN52
VADC analog input channel 1 of group 8 (muxtest)
D / HighZ / Analog input 52
VDDM
VADCG8.4
DS6PA
VADC analog input channel 4 of group 8
DSADC: positive analog input of channel 6, pin A
D / HighZ / Analog input 53
AF6
AE7
AF7
AN53
I
I
I
VDDM
VADCG8.5
DS6NA
VADC analog input channel 5 of group 8
DSADC: negative analog input channel 6, pin A
AN54
D / HighZ / Analog input 5
VDDM
VADCG8.6
DS6PB
VADC analog input channel 6 of group 8
DSADC: positive analog input of channel 6, pin B
D / HighZ / Analog input 50
AN55
VDDM
VADCG8.7
DS6NB
VADC analog input channel 7 of group 8
DSADC: negative analog input channel 6, pin B
AA4
AB3
Y2
AN56
I
I
I
D / HighZ / Analog input 56
VDDM
VADCG9.0
AN57
VADC analog input channel 0 of group 9
D / HighZ / Analog input 57
VDDM
VADCG9.1
AN60
VADC analog input channel 1 of group 9 (muxtest)
D / HighZ / Analog input 60
VDDM
VADCG9.4
DS7PA
VADC analog input channel 4 of group 9
DSADC: positive analog input of channel 7, pin A
D / HighZ / Analog input 61
AA1
AN61
I
VDDM
VADCG9.5
DS7NA
VADC analog input channel 5 of group 9
DSADC: negative analog input channel 7, pin A
W2
Y1
V2
AN64
I
I
I
D / HighZ / Analog input 64
VDDM
VADCG10.0
AN65
VADC analog input channel 0 of group 10
D / HighZ / Analog input 65
VDDM
VADCG10.1
AN68
VADC analog input channel 1 of group 10 (muxtest)
Analog input 68
S /
HighZ /
VDDM
VADCG10.4
DS8PA
VADC analog input channel 4 of group 10
DSADC: positive analog input of channel 8, pin A
SENT input channel 11, pin A
SENT11A
Data Sheet
TOC-215
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-49 Analog Inputs (cont’d)
Pin
W1
Symbol
AN69
Ctrl
Type
Function
I
S /
Analog input 69
HighZ /
VDDM
VADCG10.5
DS8NA
VADC analog input channel 5 of group 10
DSADC: negative analog input channel 8, pin A
SENT input channel 12, pin A
Analog input 70
SENT12A
AN70
U2
V1
I
I
S /
HighZ /
VDDM
VADCG10.6
DS9PA
VADC analog input channel 6 of group 10
DSADC: positive analog input of channel 9, pin A
SENT input channel 13, pin A
Analog input 71
SENT13A
AN71
S /
HighZ /
VDDM
VADCG10.7
DS9NA
VADC analog input channel 7 of group 10
DSADC: negative analog input channel 9, pin A
SENT input channel 14, pin A
SENT14A
Table 2-50 System I/O
Pin
Symbol
Ctrl
Type
Function
B22
PORST
I
PORST /
PD /
Power On Reset Input
Additional strong PD in case of power fail.
VEXT
A23
ESR0
I/O
MP /
OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished.
See also SCU chapter for details.
Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR
register description.
EVRWUP
ESR1
I
EVR Wakeup Pin
A22
I/O
MP /
PU1 /
VEXT
External System Request Reset 1
Default NMI function.
See also SCU chapter ´Reset Control Unit´ and
SCU_IOCR register description.
EVRWUP
VGATE1P
I
EVR Wakeup Pin
AC17
AC21
F24
O
VGATE1P / External Pass Device gate control for EVR13
- /
VEXT
VGATE3P
O
VGATE3P / External Pass Device gate control for EVR33
- /
VEXT
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
Data Sheet
TOC-216
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-50 System I/O (cont’d)
Pin
Symbol
Ctrl
Type
Function
F23
TRST
I
A2 /
JTAG Module Reset/Enable Input
PD /
VDDP3
E24
G26
G25
TCK
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
XTAL1
I
XTAL1 /
- /
VDDP3
Main Oscillator/PLL/Clock Generator Input
XTAL2
O
XTAL2 /
- /
Main Oscillator/PLL/Clock Generator Output
VDDP3
Table 2-51 Supply
Pin
Symbol
Ctrl
Type
Vx
Function
AD6
VAREF1
I
I
I
I
I
I
Positive Analog Reference Voltage 1
AC6
VAGND1
VAREF2
VAGND2
VDDM
Vx
Vx
Vx
Vx
Negative Analog Reference Voltage 1
Positive Analog Reference Voltage 2
Negative Analog Reference Voltage 2
ADC Analog Power Supply (3.3V / 5V)
W4
Y4
AE9, AE5
R1, R4
NC / VDDSB
NCVDD Emulation Device: Emulation SRAM
SB
Vx
Vx
Standby Power Supply (1.3V) (Emulation
Device only).
Production Device: Not Connected.
P23, V23, AB23, AC20, B26, VDD
C25, D9, D24, E23, H4
I
I
Digital Core Power Supply (1.3V)
F26
VDD
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main
XTAL Oscillator/PLL (1.3V) . A higher
decoupling capacitor is therefore
recommended to the VSS pin for better
noise immunity.
A25, B24, C23, D14, D22, K4, VEXT
AC16, AD16, AE16, AF16
I
I
Vx
Vx
External Power Supply (5V / 3.3V)
H24, H25, H26
VDDP3
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power
Supply for VFLEX.
Data Sheet
TOC-217
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-51 Supply (cont’d)
Pin
Symbol
Ctrl
Type
Vx
Function
E26
VDDP3
I
Digital Power Supply for Oscillator,
LVDSH and A2 pads (3.3V).
The supply pin inturn supplies the main
XTAL Oscillator/PLL (3.3V) . A higher
decoupling capacitor is therefore
recommended to the VSS pin for better
noise immunity.
A18, B18
D7
VDDFL3
VFLEX
I
I
I
Vx
Vx
Vx
Flash Power Supply (3.3V)
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
AC18, AC22
VFLEXE
Digital Power Supply for EBU Flex Port
Pads
(5V / 3.3V)
M23, T23, Y23
AF5, AF9
AD9
VEBU
I
I
I
Vx
Vx
Vx
Digital Power Supply for EBU
(3.3V)
VSSM
Analog Ground for VDDM
VEVRSB
Standby Power Supply (3.3V/5V) for the
Standby SRAM (CPU0.DSPR).
If Standby mode is not used: To be
handled like VEXT (3.3V/5V).
A26, B25, C24, D8, D15, D23, VSS
F25, J4, L23, R23, T4, W23,
AC19, AC23
I
I
Vx
Vx
Digital Ground (outer balls)
K10, K11, K12, K13, K14,
K15, K16, K17, L10, L11, L12,
L13, L14, L15, L16, L17
VSS
Digital Ground (center balls)
M10, M11, M12, M13, M14,
M15, M16, M17, N10, N11,
N12, N13, N14, N15, N16, N17
VSS
I
Vx
Digital Ground (center balls)
P11, P12, P13, P14, P15, P16, VSS
R11, R12, R13, R14, R15, R16
I
I
Vx
Vx
Digital Ground (center balls)
Digital Ground (center balls)
T10, T11, T12, T13, T14, T15, VSS
T16, T17, U10, U11, U14, U15,
U16, U17
U12
VSS
I
Vx
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT TX0N
Data Sheet
TOC-218
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
Table 2-51 Supply (cont’d)
Pin
Symbol
Ctrl
Type
Vx
Function
U13
VSS
I
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT TX0P
R10
P10
R17
P17
VSS
I
I
I
I
Vx
Vx
Vx
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT CLKN
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT CLKP
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT ERR
NC / VDDPSB
NCVDD Emulation Device: Power Supply (3.3V)
PSB
for DAP/JTAG pad group. Can be
connected to VDDP or can be left
unsupplied (see document ´AurixED´ /
Aurix Emulation Devices specification.
Production Device:
This pin is not connected on package
level. It can be connected on PCB level
to VDDP or Ground or can be left
unsupplied.
A1, AF1, AF26
NC
I
NC1
Not Connected.
These pins are not connected on
package level and will not be used for
future extensions.
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
Data Sheet
TOC-219
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input
function)
MP = Pad class MP (5V/3.3V)
MP+ = Pad class MP+ (5V/3.3V)
MPR = Pad class MPR (5V/3.3V)
A2 = Pad class A2 (3.3V)
LVDSM = Pad class LVDSM (5V/3.3V)
LVDSH = Pad class LVDSH (3.3V)
S = Pad class S (Class S parameters for digital input and class D parameters for analog input function)
D = Pad class D (VADC / DSADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
2.2.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during Porst active
Control of the Emergency Stop function:
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
•
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
TOC-220
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
•
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O
Ports and Peripheral I/O Lines”, P00 / P01)
•
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.2.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-52 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
TOC-221
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
2.3
TC297x Pin Definition and Functions: BGA292
Figure 2-3 is showing the TC297x Logic Symbol for the package variant: BGA292.
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VSS
P32.3
P32.2
P32.0 P33.13 P33.11
P33.9
P33.7
P33.5
P33.3
P33.1
AN5
AN10 VAGND1 VAREF1 VDDM VSSM
AN20
AN21
NC
Y
W
V
U
T
Y
W
V
U
T
VGATE1
VEXT
P23.0
P23.2
P23.4
P22.2
P22.0
VDDP3
VSS
VEXT
P23.1
P23.3
P22.3
P22.1
VDD
P32.4
P33.12 P33.10
P
P33.8
P33.6
P33.4
P33.2
P33.0
AN2
AN8
AN11
AN13
AN16
AN18
AN19
AN24
AN26
AN28
AN25
AN27
AN29
17
16
15
14
13
12
11
10
9
8
7
6
5
4
VSS
P32.7
P32.6
P33.15
P34.5
P34.3
P34.1
AN1
AN3
AN7
AN9
AN14
AN17
NC
U
T
U
P23.5
P23.6
P22.5
P22.7
P22.9
VSS
P32.5
P33.14
P34.4
VDD
P34.2 VEVRSB AN0
AN4
AN6
AN12
AN15
AN22
AN23
AN34
AN38
AN40
AN42
AN30
AN31
AN32
AN36
AN41
AN43
VAGND2 VAREF2
T
P23.7
P22.4
P22.6
P22.8
AN35
AN37
AN45
AN47
AN33
AN39
AN44
AN46
R
P
N
M
L
Top-View
R
P
N
M
L
R
P
N
M
L
R
P
N
M
L
VSS
(AGBT (AGBT
TX0P)
VSS
VSS
VSS
VSS
VSS
VSS
VDD
TX0N)
VSS
VDD
VSS
VDD
VSS
XTAL1 XTAL2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(AGBT
ERR)
VSS
(AGBT
CLKN)
VSS
TRST
P21.2
P21.3
P20.2
P20.1
P20.7
P22.11 P22.10
VSS
VSS
VSS
VSS
P00.12 P00.11
VSS
(AGBT
CLKP)
NC
(VDDPSB)
P21.4
P21.5
P20.0
P20.3
P20.8
P21.0
P21.1
P21.6
TMS
TCK
P00.10 P00.8
P00.9
P00.5
P00.3
P00.1
P02.7
P02.5
P02.3
P02.1
VSS
P00.7
P00.4
P00.2
P00.0
P02.8
P02.6
P02.4
P02.2
P02.0
K
J
K
J
K
J
K
J
VSS
VDD
VSS
P01.7
P01.5
P01.3
P00.6
P01.6
P01.4
VDD
(VDDSB)
P21.7
VSS
VSS
VSS
VSS
H
G
F
H
G
F
H
G
F
H
G
F
VDD
(VDDSB)
PORST ESR1
VDD
P20.6
P20.9
ESR0
P02.10 P02.11
P20.11 P20.10
P20.13 P20.12
VSS VDDFL3 P15.5
P14.2
P12.0
P12.1
P11.0
P11.1
P11.7
P11.8
P11.13
VSS
P02.9
E
D
C
B
A
E
D
C
B
A
E
D
E
D
VSS VDDFL3 P15.7
P15.8
14
P14.7
13
P14.9 P14.10 P11.4
P11.6
9
P11.5 P11.14 P11.15 VFLEX
VSS
4
17
16
15
12
11
10
8
7
6
5
P20.14
P15.0
P15.2
VSS
VDDP3 P15.3
P14.0
P14.4
P14.3
P14.6
P13.0
P13.2
P11.3 P11.10 P11.12 P10.1
P10.4
P10.5
P10.8
VEXT
VSS
VDDP3 P15.1
19 18
P15.4
P15.6
P14.1
P14.5
P14.8
P13.1
P13.3
P11.2
P11.9 P11.11 P10.0
P10.3
P10.2
P10.6
P10.7
VEXT
NC
20
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 2-3 TC297x Logic Symbol for the package variant BGA292.
Data Sheet
TOC-222
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
2.3.1
TC297x BGA292 Package Variant Pin Configuration
Table 2-53 Port 00 Functions
Pin
G1
Symbol
P00.0
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN9
CTRAPA
T12HRE
INJ00
CCU61 input
CCU60 input
MSC0 input
CIFD9
P00.0
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT9
ASCLK3
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
–
TXDCAN1
–
CAN node 1 output
Reserved
COUT63
ETHMDIOA
CCU60 output
ETH input/output
HWOU
T
Data Sheet
TOC-223
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-53 Port 00 Functions (cont’d)
Pin
G2
Symbol
P00.1
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN10
ARX3E
ASCLIN3 input
CAN node 1 input
PSI5 input
RXDCAN1D
PSIRX0A
SENT0B
CC60INB
CC60INA
DSCIN5A
DS5NA
SENT input
CCU60 input
CCU61 input
DSADC channel 5 input
DSADC positive analog input of channel channel 5,
pin A
DSCIN7B
VADCG7.5
CIFD10
P00.1
DSADC channel 7 input
VADC analog input channel 5 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT10
ATX3
ASCLIN3 output
–
Reserved
DSCOUT5
DSCOUT7
SPC0
DSADC channel 5 output
DSADC channel 7 output
SENT output
CC60
CCU61 output
H1
P00.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN11
SENT1B
DSDIN5A
DSDIN7B
DS5PA
SENT input
DSADC channel 5 input
DSADC channel 7 input
DSADC negative analog input of channel 5, pin A
VADC analog input channel 4 of group 7
CIF input
VADCG7.4
CIFD11
P00.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT11
ASCLK3
TXDCANr1
PSITX0
TXDCAN3
SLSO34
COUT60
ASCLIN3 output
CAN node 1 output (MultiCANr+)
PSI5 output
CAN node 3 output
QSPI3 output
CCU61 output
Data Sheet
TOC-224
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-53 Port 00 Functions (cont’d)
Pin
H2
Symbol
P00.3
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN12
RXDCAN3A
RXDCANr1A
PSIRX1A
PSISRXA
SENT2B
CC61INB
CC61INA
DSCIN3A
VADCG7.3
DSITR5F
CIFD12
P00.3
CAN node 3 input
CAN node 1 input (MultiCANr+)
PSI5 input
PSI5-S input
SENT input
CCU60 input
CCU61 input
DSADC channel 3 input
VADC analog input channel 3 of group 7
DSADC channel 5 input
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT12
ASLSO3
–
ASCLIN3 output
Reserved
DSCOUT3
–
DSADC channel 3 output
Reserved
SPC2
SENT output
CC61
CCU61 output
J1
P00.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN13
REQ7
SCU input
SENT3B
DSDIN3A
DSSGNA
VADCG7.2
CIFD13
P00.4
SENT input
DSADC channel 3 input
DSADC channel input
VADC analog input channel 2 of group 7
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT13
PSISTX
–
PSI5-S output
Reserved
PSITX1
VADCG4BFL0
SPC3
PSI5 output
VADC output
SENT output
COUT61
CCU61 output
Data Sheet
TOC-225
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-53 Port 00 Functions (cont’d)
Pin
J2
Symbol
P00.5
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN14
PSIRX2A
SENT4B
CC62INB
CC62INA
DSCIN2A
VADCG7.1
CIFD14
PSI5 input
SENT input
CCU60 input
CCU61 input
DSADC channel 2 input
VADC analog input channel 1 of group 7
CIF input
P00.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT14
DSCGPWMN
SLSO33
DSCOUT2
VADCG4BFL1
SPC4
DSADC output
QSPI3 output
DSADC channel 2 output
VADC output
SENT output
CC62
CCU61 output
J4
P00.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN15
SENT5B
DSDIN2A
VADCG7.0
SENT input
DSADC channel 2 input A
VADC analog input channel 0 of group 7 (with pull
down diagnostics)
DSITR4F
CIFD15
DSADC channel 4 input F
CIF input
P00.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT15
DSCGPWMP
VADCG4BFL2
PSITX2
DSADC output
VADC output
PSI5 output
VADCEMUX10
SPC5
VADC output
SENT output
COUT62
CCU61 output
Data Sheet
TOC-226
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-53 Port 00 Functions (cont’d)
Pin
K1
Symbol
P00.7
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN16
SENT6B
CC60INC
CCPOS0A
T12HRB
T2INA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSCIN4A
DS4NA
VADCG6.5
CIFCLK
P00.7
DSADC channel 4 input A
DSADC negative analog input channel 4, pin A
VADC analog input channel 5 of group 6
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT16
–
Reserved
VADCG4BFL3
DSCOUT4
VADCEMUX11
SPC6
VADC output
DSADC channel 4 output
VADC output
SENT output
CC60
CCU61 output
K4
P00.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN17
SENT7B
CC61INC
CCPOS1A
T13HRB
T2EUDA
DSDIN4A
DS4PA
SENT input
CCU61 input
CCU61 input
CCU60 input
GPT120 input
DSADC channel 4 input A
DSADC positive analog input of channel 4, pin A
VADC analog input channel 4 of group 6
CIF input
VADCG6.4
CIFVSNC
P00.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT17
SLSO36
–
QSPI3 output
Reserved
–
Reserved
VADCEMUX12
SPC7
VADC output
SENT output
CC61
CCU61 output
Data Sheet
TOC-227
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-53 Port 00 Functions (cont’d)
Pin
K2
Symbol
P00.9
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN18
SENT8B
CC62INC
CCPOS2A
T13HRC
T12HRC
T4EUDA
DSCIN1A
VADCG6.3
DSITR3F
CIFHSNC
P00.9
SENT input
CCU61 input
CCU61 input
CCU60 input
CCU60 input
GPT120 input
DSADC channel 1 input A
VADC analog input channel 3 of group 6
DSADC channel 3 input F
CIF input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT18
SLSO37
ARTS3
DSCOUT1
–
QSPI3 output
ASCLIN3 output
DSADC channel 1 output
Reserved
SPC8
SENT output
CC62
CCU61 output
K5
P00.10
TIN19
LP /
PU1 /
VEXT
General-purpose input
GTM input
SENT9B
DSDIN1A
VADCG6.2
P00.10
TOUT19
–
SENT input
DSADC channel 1 input A
VADC analog input channel 2 of group 6
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
SPC9
SENT output
COUT63
CCU61 output
Data Sheet
TOC-228
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-53 Port 00 Functions (cont’d)
Pin
L1
Symbol
P00.11
TIN20
CTRAPA
T12HRE
DSCIN0A
VADCG6.1
P00.11
TOUT20
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
CCU60 input
CCU61 input
DSADC channel 0 input A
VADC analog input channel 1 of group 6
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
DSCOUT0
–
DSADC channel 0 output
Reserved
–
Reserved
–
Reserved
L2
P00.12
TIN21
ACTS3A
DSDIN0A
VADCG6.0
P00.12
TOUT21
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN3 input
DSADC channel 0 input A
VADC analog input channel 0 of group 6
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
COUT63
CCU61 output
Data Sheet
TOC-229
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-54 Port 01 Functions
Pin
G5
Symbol
P01.3
TIN111
SLSI3B
DSITR7F
P01.3
TOUT111
–
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 7 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
SLSO39
TXDCAN1
–
QSPI3 output
CAN node 1 output
Reserved
–
Reserved
G4
P01.4
TIN112
RXDCAN1C
DSITR7E
P01.4
TOUT112
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
CAN node 1 input
DSADC channel 7 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
SLSO310
–
QSPI3 output
Reserved
–
Reserved
–
Reserved
H5
P01.5
TIN113
MRST3C
DSCIN8A
P01.5
TOUT113
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
DSADC channel 8 input A
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
MRST3
–
QSPI3 output
Reserved
DSCOUT8
–
DSADC channel 8 output
Reserved
Data Sheet
TOC-230
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-54 Port 01 Functions (cont’d)
Pin
H4
Symbol
Ctrl
Type
Function
P01.6
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN114
MTSR3C
QSPI3 input
DSDIN8A
DSADC channel 8 input A
General-purpose output
GTM output
P01.6
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT114
–
Reserved
–
Reserved
MTSR3
QSPI3 output
Reserved
–
–
Reserved
–
Reserved
J5
P01.7
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN115
SCLK3C
QSPI3 input
DSITR8F
DSADC channel 8 input F
General-purpose output
GTM output
P01.7
O0
O1
O2
O3
O4
O5
O6
O7
TOUT115
–
Reserved
–
Reserved
SCLK3
QSPI3 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
TOC-231
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-55 Port 02 Functions
Pin
B1
Symbol
P02.0
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN0
REQ6
SCU input
ARX2G
CC60INA
CC60INB
CIFD0
ASCLIN2 input
CCU60 input
CCU61 input
CIF input
P02.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT0
ATX2
ASCLIN2 output
QSPI3 output
DSADC output
CAN node 0 output
ERAY0 output
CCU60 output
SLSO31
DSCGPWMN
TXDCAN0
TXD0A
CC60
C2
P02.1
LP / PU1 General-purpose input
/ VEXT
TIN1
GTM input
REQ14
ARX2B
RXDCAN0A
RXD0A2
CIFD1
SCU input
ASCLIN2 input
CAN node 0 input
ERAY0 input
CIF input
P02.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT1
SLSO47
SLSO32
DSCGPWMP
–
QSPI4 output
QSPI3 output
DSADC output
Reserved
–
Reserved
COUT60
CCU60 output
Data Sheet
TOC-232
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-55 Port 02 Functions (cont’d)
Pin
C1
Symbol
P02.2
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN2
CC61INA
CC61INB
CIFD2
CCU60 input
CCU61 input
CIF input
P02.2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT2
ATX1
ASCLIN1 output
QSPI3 output
SLSO33
PSITX0
TXDCAN2
TXD0B
CC61
PSI5 output
CAN node 2 output
ERAY0 output
CCU60 output
General-purpose input
GTM input
D2
P02.3
LP /
PU1 /
VEXT
TIN3
ARX1G
RXDCAN2B
RXD0B2
PSIRX0B
DSCIN5B
SDI11
ASCLIN1 input
CAN node 2 input
ERAY0 input
PSI5 input
DSADC channel 5 input B
MSC1 input
CIFD3
CIF input
P02.3
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT3
ASLSO2
SLSO34
DSCOUT5
–
ASCLIN2 output
QSPI3 output
DSADC channel 5 output
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
TOC-233
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-55 Port 02 Functions (cont’d)
Pin
D1
Symbol
P02.4
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN4
SLSI3A
ECTT1
QSPI3 input
TTCAN input
RXDCAN0D
CC62INA
CC62INB
DSDIN5B
SDA0A
CIFD4
CAN node 0 input
CCU60 input
CCU61 input
DSADC channel 5 input B
I2C0 input
CIF input
P02.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT4
ASCLK2
SLSO30
PSISCLK
SDA0
ASCLIN2 output
QSPI3 output
PSI5-S output
I2C0 output
TXEN0A
CC62
ERAY0 output
CCU60 output
General-purpose input
GTM input
E2
P02.5
MP+ /
PU1 /
VEXT
TIN5
MRST3A
ECTT2
QSPI3 input
TTCAN input
PSIRX1B
PSISRXB
SENT3C
DSCIN4B
SCL0A
PSI5 input
PSI5-S input
SENT input
DSADC channel 4 input B
I2C0 input
CIFD5
CIF input
P02.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT5
TXDCAN0
MRST3
DSCOUT4
SCL0
CAN node 0 output
QSPI3 output
DSADC channel 4 output
I2C0 output
TXEN0B
COUT62
ERAY0 output
CCU60 output
Data Sheet
TOC-234
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-55 Port 02 Functions (cont’d)
Pin
E1
Symbol
P02.6
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN6
MTSR3A
SENT2C
CC60INC
CCPOS0A
T12HRB
T3INA
QSPI3 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
CIFD6
DSDIN4B
DSITR5E
P02.6
DSADC channel 4 input B
DSADC channel 5 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT6
PSISTX
MTSR3
PSITX1
VADCEMUX00
–
PSI5-S output
QSPI3 output
PSI5 output
VADC output
Reserved
CC60
CCU60 output
Data Sheet
TOC-235
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-55 Port 02 Functions (cont’d)
Pin
F2
Symbol
P02.7
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN7
SCLK3A
PSIRX2B
SENT1C
CC61INC
CCPOS1A
T13HRB
T3EUDA
CIFD7
QSPI3 input
PSI5 input
SENT input
CCU60 input
CCU60 input
CCU61 input
GPT120 input
CIF input
DSCIN3B
DSITR4E
P02.7
DSADC channel 3 input B
DSADC channel 4 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT7
–
Reserved
SCLK3
QSPI3 output
DSCOUT3
VADCEMUX01
SPC1
DSADC channel 3 output
VADC output
SENT output
CC61
CCU60 output
Data Sheet
TOC-236
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-55 Port 02 Functions (cont’d)
Pin
F1
Symbol
P02.8
Ctrl
Type
Function
I
LP / PU1 General-purpose input
/
TIN8
GTM input
VEXT
SENT0C
CC62INC
CCPOS2A
T12HRC
T13HRC
T4INA
CIFD8
DSDIN3B
DSITR3E
P02.8
SENT input
CCU60 input
CCU60 input
CCU61 input
CCU61 input
GPT120 input
CIF input
DSADC channel 3 input B
DSADC channel 3 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT8
SLSO35
–
QSPI3 output
Reserved
PSITX2
VADCEMUX02
ETHMDC
CC62
PSI5 output
VADC output
ETH output
CCU60 output
E4
P02.9
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN116
P02.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT116
ATX2
ASCLIN2 output
Reserved
–
–
Reserved
TXDCAN1
–
CAN node 1 output
Reserved
–
Reserved
Data Sheet
TOC-237
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-55 Port 02 Functions (cont’d)
Pin
F5
Symbol
Ctrl
Type
Function
P02.10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN117
ARX2C
ASCLIN2 input
CAN node 1 input
General-purpose output
GTM output
Reserved
RXDCAN1E
P02.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT117
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
F4
P02.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN118
P02.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT118
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-56 Port 10 Functions
Pin
A7
Symbol
Ctrl
Type
Function
P10.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN102
T6EUDB
GPT120 input
General-purpose output
GTM output
P10.0
O0
O1
O2
O3
O4
O5
O6
O7
TOUT102
–
Reserved
SLSO110
QSPI1 output
Reserved
–
VADCG6BFL0
VADC output
Reserved
–
–
Reserved
Data Sheet
TOC-238
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-56 Port 10 Functions (cont’d)
Pin
B7
Symbol
P10.1
Ctrl
Type
Function
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN103
MRST1A
T5EUDB
P10.1
QSPI1 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT103
MTSR1
MRST1
EN01
QSPI1 output
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL1
END03
–
A5
P10.2
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN104
SCLK1A
T6INB
QSPI1 input
GPT120 input
SCU input
REQ2
RXDCAN2E
SDI01
CAN node 2 input
MSC0 input
P10.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT104
–
Reserved
SCLK1
EN00
QSPI1 output
MSC0 output
VADC output
MSC0 output
Reserved
VADCG6BFL2
END02
–
Data Sheet
TOC-239
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-56 Port 10 Functions (cont’d)
Pin
A6
Symbol
P10.3
Ctrl
Type
Function
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN105
MTSR1A
REQ3
QSPI1 input
SCU input
T5INB
GPT120 input
General-purpose output
GTM output
P10.3
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT105
VADCG6BFL3
MTSR1
EN00
VADC output
QSPI1 output
MSC0 output
MSC0 output
CAN node 2 output
Reserved
END02
TXDCAN2
–
B6
P10.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN106
MTSR1C
CCPOS0C
T3INB
QSPI1 input
CCU60 input
GPT120 input
General-purpose output
GTM output
P10.4
O0
O1
O2
O3
O4
O5
O6
O7
TOUT106
–
Reserved
SLSO18
MTSR1
EN00
QSPI1 output
QSPI1 output
MSC0 output
MSC0 output
Reserved
END02
–
Data Sheet
TOC-240
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-56 Port 10 Functions (cont’d)
Pin
B5
Symbol
P10.5
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN107
HWCFG4
RXDCANr0A
INJ01
SCU input
CAN node 0 input (MultiCANr+)
MSC0 input
P10.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT107
ATX2
ASCLIN2 output
QSPI3 output
SLSO38
SLSO19
T6OUT
QSPI1 output
GPT120 output
ASCLIN2 output
PSI5 output
ASLSO2
PSITX3
P10.6
A4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN108
ARX2D
ASCLIN2 input
QSPI3 input
MTSR3B
PSIRX3C
HWCFG5
P10.6
PSI5 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT108
ASCLK2
MTSR3
ASCLIN2 output
QSPI3 output
T3OUT
GPT120 output
CAN node 0 output (MultiCANr+)
QSPI1 output
TXDCANr0
MRST1
VADCG7BFL0
VADC output
Data Sheet
TOC-241
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-56 Port 10 Functions (cont’d)
Pin
A3
Symbol
P10.7
Ctrl
Type
Function
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN109
ACTS2A
MRST3B
REQ4
ASCLIN2 input
QSPI3 input
SCU input
CCPOS1C
T3EUDB
P10.7
CCU60 input
GPT120 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT109
–
Reserved
MRST3
VADCG7BFL1
TXDCANr0
–
QSPI3 output
VADC output
CAN node 0 output (MultiCANr+)
Reserved
–
Reserved
B4
P10.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN110
SCLK3B
REQ5
QSPI3 input
SCU input
CCPOS2C
T4INB
RXDCANr0B
P10.8
CCU60 input
GPT120 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT110
ARTS2
SCLK3
–
ASCLIN2 output
QSPI3 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-242
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-57 Port 11 Functions
Pin
Symbol
P11.0
TIN119
ARX3B
P11.0
TOUT119
ATX3
Ctrl
Type
Function
E10
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
ASCLIN3 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
ETHTXD3
–
ETH output
Reserved
E9
P11.1
TIN120
P11.1
TOUT120
ASCLK3
ATX3
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
ASCLIN3 output
Reserved
–
–
Reserved
ETHTXD2
–
ETH output
Reserved
A10
P11.2
TIN95
P11.2
TOUT95
END03
SLSO05
SLSO15
EN01
MPR/
PU1 /
VFLEX
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ETH output
ETHTXD1
COUT63
CCU60 output
Data Sheet
TOC-243
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-57 Port 11 Functions (cont’d)
Pin
Symbol
P11.3
TIN96
MRST1B
SDI03
P11.3
TOUT96
–
Ctrl
Type
Function
B10
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MRST1
TXD0A
–
QSPI1 output
ERAY0 output
Reserved
ETHTXD0
COUT62
P11.4
TIN121
ETHRXCLKB
P11.4
TOUT121
ASCLK3
–
ETH output
CCU60 output
General-purpose input
GTM input
D10
MP+ /
PU1 /
VFLEX
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
Reserved
–
Reserved
–
Reserved
ETHTXER
–
ETH output
Reserved
D8
P11.5
TIN122
ETHTXCLKA
P11.5
TOUT122
–
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-244
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-57 Port 11 Functions (cont’d)
Pin
D9
Symbol
P11.6
TIN97
SCLK1B
P11.6
TOUT97
TXEN0B
SCLK1
TXEN0A
FCLP0
ETHTXEN
COUT61
P11.7
TIN123
ETHRXD3
P11.7
TOUT123
–
Ctrl
Type
Function
I
MPR /
PU1 /
VFLEX
General-purpose input
GTM input
QSPI1 input
General-purpose output
GTM output
ERAY0 output
QSPI1 output
ERAY0 output
MSC0 output
ETH output
O0
O1
O2
O3
O4
O5
O6
O7
I
CCU60 output
General-purpose input
GTM input
E8
LP /
PU1 /
VFLEX
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
E7
P11.8
TIN124
ETHRXD2
P11.8
TOUT124
–
LP /
PU1 /
VFLEX
General-purpose input
GTM input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-245
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-57 Port 11 Functions (cont’d)
Pin
A9
Symbol
P11.9
Ctrl
Type
Function
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
TIN98
MTSR1B
RXD0A1
ETHRXD1
P11.9
QSPI1 input
ERAY0 input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT98
–
Reserved
MTSR1
–
QSPI1 output
Reserved
SOP0
MSC0 output
Reserved
–
COUT60
P11.10
TIN99
REQ12
ARX1E
SLSI1A
RXDCAN3D
RXD0B1
ETHRXD0
SDI00
P11.10
TOUT99
–
CCU60 output
General-purpose input
GTM input
B9
LP /
PU1 /
VFLEX
SCU input
ASCLIN1 input
QSPI1 input
CAN node 3 input
ERAY0 input
ETH input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO03
SLSO13
–
QSPI0 output
QSPI1 output
Reserved
–
Reserved
CC62
CCU60 output
Data Sheet
TOC-246
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-57 Port 11 Functions (cont’d)
Pin
A8
Symbol
P11.11
Ctrl
Type
Function
I
MP+ /
PU1 /
VFLEX
General-purpose input
GTM input
TIN100
ETHCRSDVA
ETHRXDVA
ETHCRSB
P11.11
ETH input
ETH input
ETH input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT100
END02
MSC0 output
QSPI0 output
QSPI1 output
MSC0 output
ERAY0 output
CCU60 output
General-purpose input
GTM input
SLSO04
SLSO14
EN00
TXEN0B
CC61
B8
P11.12
MPR /
PU1 /
VFLEX
TIN101
ETHREFCLK
ETHTXCLKB
ETH input
ETH input
(Not for productive purposes)
ETHRXCLKA
ETH input
(Not for productive purposes)
P11.12
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT101
ATX1
ASCLIN1 output
GTM output
GTMCLK2
TXD0B
ERAY0 output
CAN node 3 output
SCU output
TXDCAN3
EXTCLK1
CC60
CCU60 output
Data Sheet
TOC-247
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-57 Port 11 Functions (cont’d)
Pin
E6
Symbol
Ctrl
Type
Function
P11.13
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN125
ETHRXERA
ETH input
SDA1A
I2C1 input
P11.13
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT125
–
–
Reserved
–
Reserved
–
Reserved
SDA1
I2C1 output
Reserved
–
D7
P11.14
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN126
ETHCRSDVB
ETH input
ETHRXDVB
ETH input
ETHCRSA
ETH input
SCL1A
I2C1 input
P11.14
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT126
–
–
Reserved
–
Reserved
–
Reserved
SCL1
I2C1 output
Reserved
–
D6
P11.15
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN127
ETHCOL
ETH input
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT127
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-248
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-58 Port 12 Functions
Pin
Symbol
Ctrl
Type
Function
E12
P12.0
I
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN128
ETHRXCLKC
ETH input
RXDCAN0C
CAN node 0 input
General-purpose output
GTM output
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT128
–
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDC
ETH output
–
Reserved
E11
P12.1
LP /
PU1 /
VFLEX
General-purpose input
GTM input
TIN129
P12.1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT129
ASLSO3
ASCLIN3 output
Reserved
–
–
Reserved
TXDCAN0
CAN node 0 output
Reserved
–
–
Reserved
ETHMDIOC
HWOU
T
ETH input/output
Table 2-59 Port 13 Functions
Pin
Symbol
P13.0
Ctrl
Type
Function
B12
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN91
P13.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT91
END03
SCLK2N
EN01
MSC0 output
QSPI2 output (LVDS)
MSC0 output
FCLN0
FCLND0
–
MSC0 output (LVDS)
MSC0 output (LVDS)
Reserved
Data Sheet
TOC-249
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-59 Port 13 Functions (cont’d)
Pin
Symbol
P13.1
TIN92
SCL0B
P13.1
TOUT92
–
Ctrl
Type
Function
A12
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SCLK2P
–
QSPI2 output (LVDS)
Reserved
FCLP0
SCL0
–
MSC0 output (LVDS)
I2C0 output
Reserved
B11
P13.2
TIN93
CAPINA
SDA0B
P13.2
TOUT93
–
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
GPT120 input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
MTSR2N
FCLP0
SON0
SDA0
SOND0
P13.3
TIN94
P13.3
TOUT94
–
QSPI2 output (LVDS)
MSC0 output
MSC0 output (LVDS)
I2C0 output
MSC0 output (LVDS)
General-purpose input
GTM input
A11
LVDSM_P /
PU1 /
VEXT
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MTSR2P
–
QSPI2 output (LVDS)
Reserved
SOP0
–
MSC0 output (LVDS)
Reserved
–
Reserved
Data Sheet
TOC-250
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-60 Port 14 Functions
Pin
Symbol
P14.0
Ctrl
Type
Function
B16
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN80
SENT12D
P14.0
SENT input
O0
O1
O2
General-purpose output
GTM output
TOUT80
ATX0
ASCLIN0 output
Recommended as Boot loader pin
TXD0A
O3
O4
O5
ERAY0 output
ERAY0 output
TXD0B
TXDCAN1
CAN node 1 output
Used for single pin DAP (SPD) function
ASCLK0
COUT62
P14.1
O6
O7
I
ASCLIN0 output
CCU60 output
General-purpose input
GTM input
A15
MP /
PU1 /
VEXT
TIN81
REQ15
SENT13D
ARX0A
SCU input
SENT input
ASCLIN0 input
Recommended as Boot loader pin
RXDCAN1B
CAN node 1 input
Used for single pin DAP (SPD) function
RXD0A3
RXD0B3
EVRWUPA
P14.1
ERAY0 input
ERAY0 input
SCU input
O0
O1
O2
General-purpose output
GTM output
TOUT81
ATX0
ASCLIN0 output
Recommended as Boot loader pin.
–
O3
O4
O5
O6
O7
Reserved
Reserved
Reserved
Reserved
CCU60 output
–
–
–
COUT63
Data Sheet
TOC-251
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-60 Port 14 Functions (cont’d)
Pin
Symbol
P14.2
Ctrl
Type
Function
E13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN82
HWCFG2
EVR13
SCU input
Latched at cold power on reset to decide EVR13
activation.
P14.2
TOUT82
ATX2
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
Reserved
SLSO21
–
–
Reserved
ASCLK2
–
ASCLIN2 output
Reserved
B14
P14.3
TIN83
ARX2A
REQ10
HWCFG3_BMI
SDI02
P14.3
TOUT83
ATX2
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN2 input
SCU input
SCU input
MSC0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI2 output
ASCLIN1 output
ASCLIN3 output
Reserved
SLSO23
ASLSO1
ASLSO3
–
–
Reserved
Data Sheet
TOC-252
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-60 Port 14 Functions (cont’d)
Pin
Symbol
P14.4
Ctrl
Type
Function
B15
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN84
HWCFG6
SCU input
Latched at cold power on reset to decide default pad
reset state (PU or HighZ).
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT84
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
A14
P14.5
TIN85
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
HWCFG1
EVR33
SCU input
Latched at cold power on reset to decide EVR33
activation.
P14.5
TOUT85
–
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
TXD0B
TXD1B
P14.6
TIN86
ERAY0 output
ERAY1 output
General-purpose input
GTM input
B13
MP+ /
PU1 /
VEXT
HWCFG0
DCLDO
SCU input
If EVR13 active, latched at cold power on reset to
decide between LDO and SMPS mode.
P14.6
TOUT86
–
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO22
–
QSPI2 output
Reserved
–
Reserved
TXEN0B
TXEN1B
ERAY0 output
ERAY1 output
Data Sheet
TOC-253
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-60 Port 14 Functions (cont’d)
Pin
Symbol
P14.7
TIN87
RXD0B0
RXD1B0
P14.7
TOUT87
ARTS0
SLSO24
–
Ctrl
Type
Function
D13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
ERAY0 input
ERAY1 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
ASCLIN0 output
QSPI2 output
Reserved
–
Reserved
–
Reserved
–
Reserved
A13
P14.8
TIN88
ARX1D
RXDCAN2D
RXD0A0
RXD1A0
P14.8
TOUT88
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
CAN node 2 input
ERAY0 input
ERAY1 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
D12
P14.9
TIN89
ACTS0A
P14.9
TOUT89
END03
EN01
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
MSC0 output
MSC0 output
Reserved
TXEN0B
TXEN0A
TXEN1A
ERAY0 output
ERAY0 output
ERAY1 output
Data Sheet
TOC-254
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-60 Port 14 Functions (cont’d)
Pin
Symbol
P14.10
TIN90
Ctrl
Type
Function
D11
I
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
P14.10
TOUT90
END02
EN00
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
MSC0 output
MSC0 output
ATX1
ASCLIN1 output
CAN node 2 output
ERAY0 output
ERAY1 output
TXDCAN2
TXD0A
TXD1A
Table 2-61 Port 15 Functions
Pin
Symbol
P15.0
TIN71
P15.0
TOUT71
ATX1
Ctrl
Type
Function
B20
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
Reserved
SLSO013
–
TXDCAN2
ASCLK1
–
CAN node 2 output
ASCLIN1 output
Reserved
A18
P15.1
TIN72
REQ16
ARX1A
RXDCAN2A
SLSI2B
EVRWUPB
P15.1
TOUT72
ATX1
LP /
PU1 /
VEXT
General-purpose input
GTM input
SCU input
ASCLIN1 input
CAN node 2 input
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI2 output
Reserved
SLSO25
–
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-255
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-61 Port 15 Functions (cont’d)
Pin
Symbol
P15.2
Ctrl
Type
Function
C19
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN73
SLSI2A
MRST2E
SENT10D
HSIC2INA
P15.2
QSPI2 input
QSPI2 input
SENT input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT73
ATX0
ASCLIN0 output
QSPI2 output
Reserved
SLSO20
–
TXDCAN1
ASCLK0
–
CAN node 1 output
ASCLIN0 output
Reserved
B17
P15.3
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN74
ARX0B
SCLK2A
RXDCAN1A
HSIC2INB
P15.3
ASCLIN0 input
QSPI2 input
CAN node 1 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT74
ATX0
ASCLIN0 output
QSPI2 output
MSC0 output
MSC0 output
Reserved
SCLK2
END03
EN01
–
–
Reserved
Data Sheet
TOC-256
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-61 Port 15 Functions (cont’d)
Pin
Symbol
P15.4
Ctrl
Type
Function
A17
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN75
MRST2A
REQ0
SCL0C
SENT11D
P15.4
QSPI2 input
SCU input
I2C0 input
SENT input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT75
ATX1
ASCLIN1 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
SCL0
I2C0 output
CC62
CCU60 output
General-purpose input
GTM input
E14
P15.5
MP /
PU1 /
VEXT
TIN76
ARX1B
MTSR2A
REQ13
SDA0C
P15.5
ASCLIN1 input
QSPI2 input
SCU input
I2C0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT76
ATX1
ASCLIN1 output
QSPI2 output
MSC0 output
MSC0 output
I2C0 output
MTSR2
END02
EN00
SDA0
CC61
CCU60 output
Data Sheet
TOC-257
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-61 Port 15 Functions (cont’d)
Pin
Symbol
P15.6
TIN77
MTSR2B
P15.6
TOUT77
ATX3
Ctrl
Type
Function
A16
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
QSPI5 output
QSPI2 output
ASCLIN3 output
CCU60 output
General-purpose input
GTM input
MTSR2
SLSO53
SCLK2
ASCLK3
CC60
P15.7
TIN78
ARX3A
MRST2B
P15.7
TOUT78
ATX3
D15
MP /
PU1 /
VEXT
ASCLIN3 input
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI2 output
Reserved
MRST2
–
–
Reserved
–
Reserved
COUT60
P15.8
TIN79
SCLK2B
REQ1
P15.8
TOUT79
–
CCU60 output
General-purpose input
GTM input
D14
MP /
PU1 /
VEXT
QSPI2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
ASCLK3
COUT61
ASCLIN3 output
CCU60 output
Data Sheet
TOC-258
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-62 Port 20 Functions
Pin
Symbol
P20.0
Ctrl
Type
Function
H20
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
TIN59
RXDCAN3C
RXDCANr1C
T6EUDA
REQ9
CAN node 3 input
CAN node 1 input (MultiCANr+)
GPT120 input
SCU input
SYSCLK
TGI0
HSCT input
OCDS input
P20.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT59
ATX3
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
SYSCLK
–
HSCT output
Reserved
–
Reserved
TGO0
HWOU
T
OCDS; ENx
G19
P20.1
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN60
TGI1
OCDS input
General-purpose output
GTM output
Reserved
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
TOUT60
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO1
HWOU
T
OCDS; ENx
Data Sheet
TOC-259
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-62 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
H19
P20.2
I
LP /
General-purpose input
PU1 /
VEXT
This pin is latched at power on reset release to enter
test mode.
TESTMODE
P20.2
–
OCDS input
O0
O1
O2
O3
O4
O5
O6
O7
I
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
Output function not available
General-purpose input
GTM input
–
–
–
–
–
–
G20
P20.3
TIN61
T6INA
ARX3C
P20.3
TOUT61
ATX3
SLSO09
SLSO29
TXDCAN3
TXDCANr1
–
LP /
PU1 /
VEXT
GPT120 input
ASCLIN3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN3 output
QSPI0 output
QSPI2 output
CAN node 3 output
CAN node 1 output (MultiCANr+)
Reserved
F17
P20.6
TIN62
P20.6
TOUT62
ARTS1
SLSO08
SLSO28
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
Reserved
WDT2LCK
–
SCU output
Reserved
Data Sheet
TOC-260
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-62 Port 20 Functions (cont’d)
Pin
Symbol
P20.7
Ctrl
Type
Function
F19
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN63
ACTS1A
RXDCAN0B
P20.7
ASCLIN1 input
CAN node 0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT63
–
Reserved
–
Reserved
–
Reserved
–
Reserved
WDT1LCK
COUT63
P20.8
SCU output
CCU61 output
General-purpose input
GTM input
F20
MP /
PU1 /
VEXT
TIN64
P20.8
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT64
ASLSO1
SLSO00
SLSO10
TXDCAN0
WDT0LCK
CC60
ASCLIN1 output
QSPI0 output
QSPI1 output
CAN node 0 output
SCU output
CCU61 output
General-purpose input
GTM input
E17
P20.9
LP /
PU1 /
VEXT
TIN65
ARX1C
RXDCAN3E
REQ11
SLSI0B
P20.9
ASCLIN1 input
CAN node 3 input
SCU input
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT65
–
Reserved
SLSO01
SLSO11
–
QSPI0 output
QSPI1 output
Reserved
WDTSLCK
CC61
SCU output
CCU61 output
Data Sheet
TOC-261
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-62 Port 20 Functions (cont’d)
Pin
Symbol
P20.10
TIN66
P20.10
TOUT66
ATX1
Ctrl
Type
Function
E19
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI0 output
QSPI2 output
CAN node 3 output
ASCLIN1 output
CCU61 output
General-purpose input
GTM input
SLSO06
SLSO27
TXDCAN3
ASCLK1
CC62
E20
P20.11
TIN67
SCLK0A
P20.11
TOUT67
–
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SCLK0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
COUT60
P20.12
TIN68
MRST0A
P20.12
TOUT68
–
CCU61 output
General-purpose input
GTM input
D19
MP /
PU1 /
VEXT
QSPI0 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
MRST0
MTSR0
–
QSPI0 output
QSPI0 output
Reserved
–
Reserved
COUT61
CCU61 output
Data Sheet
TOC-262
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-62 Port 20 Functions (cont’d)
Pin
Symbol
P20.13
TIN69
SLSI0A
P20.13
TOUT69
–
Ctrl
Type
Function
D20
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
SLSO02
SLSO12
SCLK0
–
QSPI0 output
QSPI1 output
QSPI0 output
Reserved
COUT62
P20.14
TIN70
MTSR0A
P20.14
TOUT70
–
CCU61 output
General-purpose input
GTM input
C20
MP /
PU1 /
VEXT
QSPI0 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
MTSR0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
–
Reserved
Table 2-63 Port 21 Functions
Pin
Symbol
P21.0
TIN51
MRST4DN
HOLD
P21.0
TOUT51
–
Ctrl
Type
Function
K17
I
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
QSPI4 input (LVDS)
EBU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
ETHMDC
BAABA0
ETH output
EBU output
(combined for BAA and BA0)
HSM1
O
HSM output
Data Sheet
TOC-263
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-63 Port 21 Functions (cont’d)
Pin
J17
Symbol
P21.1
Ctrl
Type
Function
I
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
TIN52
ETHMDIOB
ETH input
(Not for production purposes)
MRST4DP
QSPI4 input (LVDS)
EBU input
WAIT
P21.1
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM output
Reserved
TOUT52
–
–
Reserved
–
Reserved
–
Reserved
ETHMDIO
ETH output
(Not for production purposes)
BREQBA1
O7
EBU output
(combined for BREQ and BA1)
HSM2
O
I
HSM output
K19
P21.2
LVDSH_N/
PU1 /
VDDP3
General-purpose input
GTM input
TIN53
MRST2CN
MRST4CN
ARX3GN
EMGSTOPB
RXDN
QSPI2 input (LVDS)
QSPI4 input (LVDS)
ASCLIN3 input (LVDS)
SCU input
HSCT input (LVDS)
General-purpose output
GTM output
P21.2
O0
O1
O2
O3
O4
O5
O6
O7
TOUT53
ASLSO3
–
ASCLIN3 output
Reserved
–
Reserved
ETHMDC
SDRAMA8
–
ETH output
EBU output
Reserved
Data Sheet
TOC-264
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-63 Port 21 Functions (cont’d)
Pin
J19
Symbol
Ctrl
Type
Function
P21.3
I
LVDSH_P/
PU1 /
VDDP3
General-purpose input
GTM input
TIN54
MRST2CP
QSPI2 input (LVDS)
QSPI4 input (LVDS)
ASCLIN3 input (LVDS)
HSCT input (LVDS)
General-purpose output
GTM output
MRST4CP
ARX3GP
RXDP
P21.3
O0
TOUT54
O1
–
O2
Reserved
–
O3
Reserved
–
O4
Reserved
–
O5
Reserved
SDRAMA9
O6
EBU output
–
O7
Reserved
ETHMDIOD
HWOUT
I
ETH input/output
General-purpose input
GTM input
K20
P21.4
LVDSH_N/
PU1 /
VDDP3
TIN55
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
HSCT
I
General-purpose output
GTM output
TOUT55
–
Reserved
–
Reserved
–
Reserved
–
Reserved
SDRAMA10
EBU output
–
Reserved
TXDN
P21.5
TIN56
P21.5
TOUT56
ASCLK3
–
HSCT output (LVDS)
General-purpose input
GTM input
J20
LVDSH_P/
PU1 /
VDDP3
O0
General-purpose output
GTM output
O1
O2
ASCLIN3 output
Reserved
O3
–
O4
Reserved
–
O5
Reserved
SDRAMA11
–
O6
EBU output
O7
Reserved
TXDP
HSCT
HSCT output (LVDS)
Data Sheet
TOC-265
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-63 Port 21 Functions (cont’d)
Pin
Symbol
P21.6
Ctrl
Type
Function
H17
I
A2 /
PU /
VDDP3
General-purpose input
GTM input
TIN57
ARX3F
TGI2
ASCLIN3 input
OCDS input
TDI
OCDS (JTAG) input
GPT120 input
General-purpose output
GTM output
T5EUDA
P21.6
O0
TOUT57
ASLSO3
–
O1
O2
ASCLIN3 output
Reserved
O3
–
O4
Reserved
SYSCLK
SDRAMA12
T3OUT
TGO2
P21.7
O5
HSCT output
O6
EBU output
O7
GPT120 output
OCDS; ENx
HWOUT
I
H16
A2 /
PU /
VDDP3
General-purpose input
GTM input
TIN58
DAP2
OCDS (3-Pin DAP) input
In the 3-Pin DAP mode this pin is used as DAP2.
In the 2-PIN DAP mode this pin is used as P21.7
and controlled by the related port control logic
TGI3
OCDS input
ETHRXERB
T5INA
P21.7
ETH input
GPT120 input
General-purpose output
GTM output
O0
TOUT58
ATX3
O1
O2
ASCLIN3 output
ASCLIN3 output
Reserved
ASCLK3
–
O3
O4
–
O5
Reserved
SDRAMA13
T6OUT
TGO3
TDO
O6
EBU output
O7
GPT120 output
OCDS; ENx
HWOUT
OCDS (JTAG); ENx
The JTAG TDO function is overlayed with P21.7
via a double bond.
In JTAG mode this pin is used as TDO, after
power-on reset it is HighZ.
DAP2
OCDS (3-Pin DAP); ENx
In the 3-Pin DAP mode this pin is used as DAP2.
Data Sheet
TOC-266
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-64 Port 22 Functions
Pin
Symbol
P22.0
Ctrl
Type
Function
P20
I
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN47
MTSR4B
P22.0
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT47
ATX3N
MTSR4
SCLK4N
FCLN1
FCLND1
–
ASCLIN3 output (LVDS)
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
P19
P22.1
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
TIN48
MRST4B
P22.1
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT48
ATX3P
MRST4
SCLK4P
FCLP1
–
ASCLIN3 output (LVDS)
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
R20
P22.2
LVDSM_N /
PU1 /
VEXT
General-purpose input
GTM input
TIN49
SLSI4B
P22.2
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT49
–
Reserved
SLSO43
MTSR4N
SON1
SOND1
–
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
MSC1 output (LVDS)
Reserved
Data Sheet
TOC-267
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-64 Port 22 Functions (cont’d)
Pin
Symbol
P22.3
TIN50
SCLK4B
P22.3
TOUT50
–
Ctrl
Type
Function
R19
I
LVDSM_P /
PU1 /
VEXT
General-purpose input
GTM input
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SCLK4
MTSR4P
SOP1
–
QSPI4 output
QSPI4 output (LVDS)
MSC1 output (LVDS)
Reserved
–
Reserved
P16
P22.4
TIN130
P22.4
TOUT130
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
SLSO012
PSITX4
–
QSPI0 output
PSI5 output
Reserved
–
Reserved
P17
P22.5
TIN131
MTSR0C
PSIRX4B
P22.5
TOUT131
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI0 input
PSI5 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
MTSR0
–
QSPI0 output
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-268
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-64 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
N16
P22.6
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN132
MRST0C
QSPI0 input
General-purpose output
GTM output
Reserved
P22.6
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT132
–
–
Reserved
MRST0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
N17
P22.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN133
SCLK0C
QSPI0 input
General-purpose output
GTM output
Reserved
P22.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT133
–
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
M16
P22.8
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN134
SCLK0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.8
O0
O1
O2
O3
O4
O5
O6
O7
TOUT134
–
–
Reserved
SCLK0
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
TOC-269
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-64 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
M17
P22.9
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN135
MRST0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.9
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT135
–
–
Reserved
MRST0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
L16
P22.10
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN136
MTSR0B
QSPI0 input
General-purpose output
GTM output
Reserved
P22.10
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT136
–
–
Reserved
MTSR0
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
L17
P22.11
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN137
P22.11
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT137
–
–
Reserved
SLSO010
QSPI0 output
Reserved
–
–
–
Reserved
Reserved
Data Sheet
TOC-270
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-65 Port 23 Functions
Pin
Symbol
Ctrl
Type
Function
V20
P23.0
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN41
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT41
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
U19
P23.1
TIN42
SDI10
P23.1
TOUT42
ARTS1
SLSO46
GTMCLK0
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
GTM output
Reserved
EXTCLK0
–
SCU output
Reserved
U20
P23.2
TIN43
P23.2
TOUT43
–
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
Data Sheet
TOC-271
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-65 Port 23 Functions (cont’d)
Pin
Symbol
P23.3
TIN44
INJ10
P23.3
TOUT44
–
Ctrl
Type
Function
T19
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
T20
P23.4
TIN45
P23.4
TOUT45
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
SLSO45
END12
EN10
–
QSPI4 output
MSC1 output
MSC1 output
Reserved
–
Reserved
T17
P23.5
TIN46
P23.5
TOUT46
–
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SLSO44
END13
EN11
–
QSPI4 output
MSC1 output
MSC1 output
Reserved
–
Reserved
Data Sheet
TOC-272
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-65 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
R17
P23.6
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN138
P23.6
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
TOUT138
–
–
Reserved
SLSO011
QSPI0 output
Reserved
–
–
Reserved
–
Reserved
R16
P23.7
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN139
P23.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT139
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-66 Port 32 Functions
Pin
Symbol
P32.0
Ctrl
Type
Function
Y17
I
LP /
PX/
VEXT
General-purpose input
GTM input
TIN36
FDEST
VGATE1N
PMU input
SMPS mode: analog output. External Pass Device
gate control for EVR13
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
TOUT36
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
TOC-273
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-66 Port 32 Functions (cont’d)
Pin
Symbol
P32.2
Ctrl
Type
Function
Y18
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN38
ARX3D
RXDCAN3B
RXDCANr1D
P32.2
ASCLIN3 input
CAN node 3 input
CAN node 1 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT38
ATX3
ASCLIN3 output
Reserved
–
–
Reserved
–
Reserved
DCDCSYNC
–
SCU output
Reserved
Y19
P32.3
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN39
P32.3
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT39
ATX3
ASCLIN3 output
Reserved
–
ASCLK3
TXDCAN3
TXDCANr1
–
ASCLIN3 output
CAN node 3 output
CAN node 1 output (MultiCANr+)
Reserved
W18
P32.4
MP+ /
PU1 /
VEXT
General-purpose input
GTM input
TIN40
ACTS1B
SDI12
P32.4
ASCLIN1 input
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT40
–
Reserved
END12
GTMCLK1
EN10
MSC1 output
GTM output
MSC1 output
EXTCLK1
COUT63
SCU output
CCU60 output
Data Sheet
TOC-274
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-66 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl
Type
Function
T15
P32.5
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN140
P32.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
TOUT140
ATX2
ASCLIN2 output
Reserved
–
–
Reserved
–
Reserved
TXDCAN2
CAN node 2 output
Reserved
–
U15
P32.6
LP /
PU1 /
VEXT
General-purpose input
OCDS input
TGI4
TIN141
GTM input
RXDCAN2C
CAN node 2 input
ASCLIN2 input
General-purpose output
GTM output
ARX2F
P32.6
O0
O1
O2
O3
O4
O5
O6
O7
TOUT141
–
Reserved
–
Reserved
SLSO212
QSPI2 output
Reserved
–
–
Reserved
–
Reserved
TGO4
HWOU
T
OCDS; ENx
U16
P32.7
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN142
TGI5
OCDS input
General-purpose output
GTM output
Reserved
P32.7
O0
O1
O2
O3
O4
O5
O6
O7
TOUT142
–
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
TGO5
HWOU
T
OCDS; ENx
Data Sheet
TOC-275
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-67 Port 33 Functions
Pin
Symbol
P33.0
Ctrl
Type
Function
W10
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN22
DSITR0E
P33.0
DSADC channel 0 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT22
–
Reserved
–
Reserved
–
Reserved
–
Reserved
VADCG2BFL0
–
VADC output
Reserved
Y10
P33.1
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN23
PSIRX0C
SENT9C
DSCIN2B
DSITR1E
P33.1
PSI5 input
SENT input
DSADC channel 2 input B
DSADC channel 1 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT23
ASLSO3
SCLK2
DSCOUT2
VADCEMUX02
VADCG2BFL1
–
ASCLIN3 output
QSPI2 output
DSADC channel 2 output
VADC output
VADC output
Reserved
W11
P33.2
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN24
SENT8C
DSDIN2B
DSITR2E
P33.2
SENT input
DSADC channel 2 input B
DSADC channel 2 input E
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT24
ASCLK3
SLSO210
PSITX0
VADCEMUX01
VADCG2BFL2
–
ASCLIN3 output
QSPI2 output
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
TOC-276
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-67 Port 33 Functions (cont’d)
Pin
Symbol
P33.3
Ctrl
Type
Function
Y11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN25
PSIRX1C
SENT7C
DSCIN1B
P33.3
PSI5 input
SENT input
DSADC channel 1 input B
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT25
–
Reserved
–
Reserved
DSCOUT1
VADCEMUX00
VADCG2BFL3
–
DSADC channel 1 output
VADC output
VADC output
Reserved
W12
P33.4
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN26
SENT6C
CTRAPC
DSDIN1B
DSITR0F
P33.4
SENT input
CCU61 input
DSADC channel 1 input
DSADC channel 0 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT26
ARTS2
ASCLIN2 output
QSPI2 output
SLSO212
PSITX1
VADCEMUX12
VADCG0BFL0
–
PSI5 output
VADC output
VADC output
Reserved
Data Sheet
TOC-277
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-67 Port 33 Functions (cont’d)
Pin
Symbol
P33.5
Ctrl
Type
Function
Y12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN27
ACTS2B
PSIRX2C
PSISRXC
SENT5C
CCPOS2C
T4EUDB
DSCIN0B
DSITR1F
P33.5
ASCLIN2 input
PSI5 input
PSI5-S input
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 1 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT27
SLSO07
SLSO17
DSCOUT0
VADCEMUX11
VADCG0BFL1
–
QSPI0 output
QSPI1 output
DSADC channel 0 output
VADC output
VADC output
Reserved
W13
P33.6
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN28
SENT4C
CCPOS1C
T2EUDB
DSDIN0B
DSITR2F
P33.6
SENT input
CCU61 input
GPT120 input
DSADC channel 0 input B
DSADC channel 2 input F
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
TOUT28
ASLSO2
SLSO211
PSITX2
ASCLIN2 output
QSPI2 output
PSI5 output
VADCEMUX10
VADCG1BFL0
PSISTX
VADC output
VADC output
PSI5-S output
Data Sheet
TOC-278
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-67 Port 33 Functions (cont’d)
Pin
Symbol
P33.7
Ctrl
Type
Function
Y13
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
TIN29
RXDCAN0E
REQ8
CAN node 0 input
SCU input
CCPOS0C
T2INB
CCU61 input
GPT120 input
General-purpose output
GTM output
P33.7
O0
O1
O2
O3
O4
O5
O6
O7
I
TOUT29
ASCLK2
SLSO47
–
ASCLIN2 output
QSPI4 output
Reserved
–
Reserved
VADCG1BFL1
–
VADC output
Reserved
W14
P33.8
MP /
HighZ /
VEXT
General-purpose input
GTM input
TIN30
ARX2E
EMGSTOPA
P33.8
ASCLIN2 input
SCU input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
TOUT30
ATX2
ASCLIN2 output
QSPI4 output
Reserved
SLSO42
–
TXDCAN0
–
CAN node 0 output
Reserved
COUT62
SMUFSP
CCU61 output
SMU
HWOU
T
Y14
P33.9
TIN31
HSIC3INA
P33.9
TOUT31
ATX2
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN2 output
QSPI4 output
ASCLIN2 output
Reserved
SLSO41
ASCLK2
–
–
Reserved
CC62
CCU61 output
Data Sheet
TOC-279
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-67 Port 33 Functions (cont’d)
Pin
Symbol
P33.10
TIN32
Ctrl
Type
Function
W15
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
SLSI4A
HSIC3INB
P33.10
TOUT32
SLSO16
SLSO40
ASLSO1
PSISCLK
–
QSPI4 input
QSPI3 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
QSPI1 output
QSPI4 output
ASCLIN1 output
PSI5-S output
Reserved
COUT61
P33.11
TIN33
CCU61 output
General-purpose input
GTM input
Y15
MP /
PU1 /
VEXT
SCLK4A
P33.11
TOUT33
ASCLK1
SCLK4
–
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
Reserved
–
Reserved
DSCGPWMN
CC61
DSADC channel output
CCU61 output
General-purpose input
GTM input
W16
P33.12
TIN34
MP /
PU1 /
VEXT
MTSR4A
P33.12
TOUT34
ATX1
QSPI4 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
ASCLIN1 output
Reserved
MTSR4
ASCLK1
–
DSCGPWMP
COUT60
DSADC output
CCU61 output
Data Sheet
TOC-280
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-67 Port 33 Functions (cont’d)
Pin
Symbol
P33.13
TIN35
ARX1F
MRST4A
DSSGNB
INJ11
P33.13
TOUT35
ATX1
Ctrl
Type
Function
Y16
I
MP /
PU1 /
VEXT
General-purpose input
GTM input
ASCLIN1 input
QSPI4 input
DSADC channel input B
MSC1 input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN1 output
QSPI4 output
QSPI2 output
Reserved
MRST4
SLSO26
–
DCDCSYNC
CC60
SCU output
CCU61 output
General-purpose input
GTM input
T14
P33.14
TIN143
TGI6
LP /
PU1 /
VEXT
OCDS input
SCLK2D
P33.14
TOUT143
–
QSPI2 input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM output
Reserved
SCLK2
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
CC62
CCU60 output
OCDS; ENx
TGO6
HWOU
T
Data Sheet
TOC-281
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-67 Port 33 Functions (cont’d)
Pin
Symbol
P33.15
TIN144
TGI7
Ctrl
Type
Function
U14
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
OCDS input
General-purpose output
GTM output
Reserved
P33.15
TOUT144
–
O0
O1
O2
O3
O4
O5
O6
O7
SLSO211
–
QSPI2 output
Reserved
–
Reserved
–
Reserved
COUT62
TGO7
CCU60 output
OCDS; ENx
HWOU
T
Table 2-68 Port 34 Functions
Pin
Symbol
P34.1
TIN146
P34.1
TOUT146
ATX0
Ctrl
Type
Function
U11
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
ASCLIN0 output
Reserved
–
TXDCAN0
TXDCANr0
–
CAN node 0 output
CAN node 0 output (MultiCANr+)
Reserved
COUT63
P34.2
TIN147
ARX0D
RXDCAN0G
RXDCANr0C
P34.2
TOUT147
–
CCU60 output
General-purpose input
GTM input
T12
LP /
PU1 /
VEXT
ASCLIN0 input
CAN node 0 input
CAN node 0 input (MultiCANr+)
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
CC60
CCU60 output
Data Sheet
TOC-282
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-68 Port 34 Functions (cont’d)
Pin
Symbol
P34.3
TIN148
P34.3
TOUT148
–
Ctrl
Type
Function
U12
I
LP /
PU1 /
VEXT
General-purpose input
GTM input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM output
Reserved
–
Reserved
SLSO210
–
QSPI2 output
Reserved
–
Reserved
COUT60
P34.4
TIN149
MRST2D
P34.4
TOUT149
–
CCU60 output
General-purpose input
GTM input
T13
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
I
Reserved
–
Reserved
MRST2
–
QSPI2 output
Reserved
–
Reserved
CC61
P34.5
TIN150
MTSR2D
P34.5
TOUT150
–
CCU60 output
General-purpose input
GTM input
U13
LP /
PU1 /
VEXT
QSPI2 input
General-purpose output
GTM output
O0
O1
O2
O3
O4
O5
O6
O7
Reserved
–
Reserved
MTSR2
–
QSPI2 output
Reserved
–
Reserved
COUT61
CCU60 output
Data Sheet
TOC-283
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-69 Port 40 Functions
Pin
W2
Symbol
P40.0
Ctrl
Type
Function
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
CCU60 input
VADCG3.0
DS2PB
CCPOS0D
SENT0A
P40.1
SENT input
W1
I
S /
General-purpose inpu.t
HighZ /
VDDM
VADCG3.1
VADC analog input channel 1 of group 3 (with pull
down diagnostics)
DS2NB
DSADC: negative analog input channel 2, pin B
CCU60 input
CCPOS1B
SENT1A
P40.2
SENT input
V2
V1
I
I
S /
HighZ /
VDDM
General-purpose inpu.t
VADCG3.2
VADC analog input channel 2 of group 3 (with pull
down diagnostics)
CCPOS1D
SENT2A
P40.3
CCU60 input
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
CCPOS2B
SENT3A
P40.4
CCU60 input
SENT input
P4
R1
N4
I
I
I
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 0 of group 4
CCU60 input
VADCG4.0
CCPOS2D
SENT4A
P40.5
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 1 of group 4
CCU61 input
VADCG4.1
CCPOS0D
SENT5A
P40.6
SENT input
S /
HighZ /
VDDM
General-purpose input
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
CCU61 input
VADCG4.4
DS3PA
CCPOS1B
SENT6A
SENT input
Data Sheet
TOC-284
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-69 Port 40 Functions (cont’d)
Pin
P2
Symbol
P40.7
Ctrl
Type
Function
I
S /
General-purpose input
HighZ /
VDDM
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input channel 3, pin A
CCU61 input
CCPOS1D
SENT7A
P40.8
SENT input
N5
P1
I
I
S /
HighZ /
VDDM
General-purpose input
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel 3, pin B
CCU61 input
CCPOS2B
SENT8A
P40.9
SENT input
S /
General-purpose input
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input channel 3, pin B
CCU61 input
CCPOS2D
SENT9A
SENT input
Table 2-70 Analog Inputs
Pin
Symbol
AN0
Ctrl
Type
Function
T10
I
D / HighZ / Analog input 0
VDDM
VADCG0.0
DS1PA
AN1
VADC analog input channel 0 of group 0
DSADC: positive analog input of channel 1, pin A
D / HighZ / Analog input 1
U10
W9
U9
I
I
I
VDDM
VADCG0.1
DS1NA
AN2
VADC analog input channel 1 of group 0
DSADC: negative analog input channel 1, pin A
D / HighZ / Analog input 2
VDDM
VADCG0.2
DS0PA
AN3
VADC analog input channel 2 of group 0
DSADC: positive analog input of channel 0, pin A
D / HighZ / Analog input 3
VDDM
VADCG0.3
DS0NA
AN4
VADC analog input channel 3 of group 0
DSADC: negative analog input channel 0, pin A
T9
Y9
T8
U8
I
I
I
I
D / HighZ / Analog input 4
VDDM
VADCG0.4
AN5
VADC analog input channel 4 of group 0
D / HighZ / Analog input 5
VDDM
VADCG0.5
AN6
VADC analog input channel 5 of group 0
D / HighZ / Analog input 6
VDDM
VADCG0.6
AN7
VADC analog input channel 6 of group 0
D / HighZ / Analog input 7
VDDM
VADCG0.7
VADC analog input channel 7 of group 0
Data Sheet
TOC-285
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-70 Analog Inputs (cont’d)
Pin
W8
Symbol
AN8
Ctrl
Type
Function
I
D / HighZ / Analog input 8
VDDM
VADCG1.0
AN9
VADC analog input channel 0 of group 1
U7
Y8
W7
I
I
I
D / HighZ / Analog input 9
VDDM
VADCG1.1
AN10
VADC analog input channel 1 of group 1
D / HighZ / Analog input 10
VDDM
VADCG1.2
AN11
VADC analog input channel 2 of group 1
D / HighZ / Analog input 11
VDDM
VADCG1.3
VADC analog input channel 3 of group 1 (with pull
down diagnostics)
T7
AN12
I
I
I
I
I
I
I
I
D / HighZ / Analog input 12
VDDM
VADCG1.4
AN13
VADC analog input channel 4 of group 1
W6
U6
T6
D / HighZ / Analog input 13
VDDM
VADCG1.5
AN14
VADC analog input channel 5 of group 1
D / HighZ / Analog input 14
VDDM
VADCG1.6
AN15
VADC analog input channel 6 of group 1
D / HighZ / Analog input 15
VDDM
VADCG1.7
AN16
VADC analog input channel 7 of group 1
W5
U5
W4
W3
D / HighZ / Analog input 16
VDDM
VADCG2.0
AN17
VADC analog input channel 0 of group 2
D / HighZ / Analog input 17
VDDM
VADCG2.1
AN18
VADC analog input channel 1 of group 2
D / HighZ / Analog input 18
VDDM
VADCG2.2
AN19
VADC analog input channel 2 of group 2
D / HighZ / Analog input 19
VDDM
VADCG2.3
VADC analog input channel 3 of group 2 (with pull
down diagnostics)
Y3
Y2
AN20
I
I
D / HighZ / Analog input 20
VDDM
VADCG2.4
DS2PA
VADC analog input channel 4 of group 2
DSADC: positive analog input of channel 2, pin A
D / HighZ / Analog input 21
AN21
VDDM
VADCG2.5
DS2NA
VADC analog input channel 5 of group 2
DSADC: negative analog input channel 2, pin A
T5
R5
AN22
I
I
D / HighZ / Analog input 22
VDDM
VADCG2.6
AN23
VADC analog input channel 6 of group 2
D / HighZ / Analog input 23
VDDM
VADCG2.7
VADC analog input channel 7 of group 2
Data Sheet
TOC-286
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-70 Analog Inputs (cont’d)
Pin
W2
Symbol
AN24
Ctrl
Type
Function
I
S /
Analog input 24
HighZ /
VDDM
VADCG3.0
DS2PB
VADC analog input channel 0 of group 3
DSADC: positive analog input of channel 2, pin B
SENT input channel 0, pin A
Analog input 24
SENT0A
AN25
W1
I
S /
HighZ /
VDDM
VADCG3.1
VADC analog input channel 1 of group 3 (with pull
down diagnostics)
DS2NB
DSADC: negative analog input channel 2, pin B
SENT input channel 1, pin A
Analog input 26
SENT1A
AN26
V2
V1
I
I
S /
HighZ /
VDDM
VADCG3.2
VADC analog input channel 2 of group 3 (with pull
down diagnostics)
SENT2A
AN27
SENT input channel 2, pin A
Analog input 27
S /
HighZ /
VDDM
VADCG3.3
VADC analog input channel 3 of group 3 (with pull
down diagnostics)
SENT3A
AN28
SENT input channel 3, pin A
U2
U1
I
I
D / HighZ / Analog input 28
VDDM
VADCG3.4
VADC analog input channel 4 of group 3 (with pull
down diagnostics)
AN29
D / HighZ / Analog input 29
VDDM
VADCG3.5
VADC analog input channel 5 of group 3 (with pull
down diagnostics)
T4
R4
P4
AN30
I
I
I
D / HighZ / Analog input 30
VDDM
VADCG3.6
AN31
VADC analog input channel 6 of group 3
D / HighZ / Analog input 31
VDDM
VADCG3.7
AN32
VADC analog input channel 7 of group 3
Analog input 32
S /
HighZ /
VDDM
VADCG4.0
SENT4A
AN33
VADC analog input channel 0 of group 4
SENT input channel 4, pin A
Analog input 33
R1
I
S /
HighZ /
VDDM
VADCG4.1
SENT5A
AN34
VADC analog input channel 1 of group 4
SENT input channel 5, pin A
P5
R2
I
I
D / HighZ / Analog input 34
VDDM
VADCG4.2
AN35
VADC analog input channel 2 of group 4
D / HighZ / Analog input 35
VDDM
VADCG4.3
VADC analog input channel 3 of group 4 (with pull
down diagnostics)
Data Sheet
TOC-287
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-70 Analog Inputs (cont’d)
Pin
N4
Symbol
AN36
Ctrl
Type
Function
I
S /
Analog input 34
HighZ /
VDDM
VADCG4.4
DS3PA
VADC analog input channel 4 of group 4
DSADC: positive analog input of channel 3, pin A
SENT input channel 6, pin A
SENT6A
AN37
P2
N5
P1
I
I
I
S /
HighZ /
VDDM
Analog input 37
VADCG4.5
DS3NA
VADC analog input channel 5 of group 4
DSADC: negative analog input channel 3, pin A
SENT input channel 7, pin A
SENT7A
AN38
S /
HighZ /
VDDM
Analog input 38
VADCG4.6
DS3PB
VADC analog input channel 6 of group 4
DSADC: positive analog input of channel 3, pin B
SENT input channel 8, pin A
SENT8A
AN39
S /
Analog input 39
HighZ /
VDDM
VADCG4.7
DS3NB
VADC analog input channel 7 of group 4
DSADC: negative analog input channel 3, pin B
SENT input channel 9, pin A
SENT9A
AN40
M5
M4
L5
L4
I
I
I
I
D / HighZ / Analog input 40
VDDM
VADCG5.0
AN41
VADC analog input channel 0 of group 5
D / HighZ / Analog input 41
VDDM
VADCG5.1
AN42
VADC analog input channel 1 of group 5
D / HighZ / Analog input 42
VDDM
VADCG5.2
AN43
VADC analog input channel 2 of group 5
D / HighZ / Analog input 43
VDDM
VADCG5.3
VADC analog input channel 3 of group 5 (with pull
down diagnostics)
N1
N2
M1
M2
AN44
I
I
I
I
D / HighZ / Analog input 44
VDDM
VADCG5.4
DS3PC
AN45
VADC analog input channel 4 of group 5
DSADC: positive analog input of channel 3, pin C
D / HighZ / Analog input 45
VDDM
VADCG5.5
DS3NC
AN46
VADC analog input channel 5 of group 5
DSADC: negative analog input channel 3, pin C
D / HighZ / Analog input 46
VDDM
VADCG5.6
DS3PD
AN47
VADC analog input channel 6 of group 5
DSADC: positive analog input of channel 3, pin D
D / HighZ / Analog input 47
VDDM
VADCG5.7
DS3ND
VADC analog input channel 7 of group 5
DSADC: negative analog input channel 3, pin D
Data Sheet
TOC-288
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-71 System I/O
Pin
Symbol
Ctrl
Type
Function
G17
PORST
I
PORST /
PD /
Power On Reset Input
Additional strong PD in case of power fail.
VEXT
F16
ESR0
I/O
MP /
OD /
VEXT
External System Request Reset 0
Default configuration during and after reset is open-
drain driver. The driver drives low during power-on
reset. This is valid additionally after deactivation of
PORST until the internal reset phase has finished.
See also SCU chapter for details.
Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR
register description.
EVRWUP
ESR1
I
EVR Wakeup Pin
G16
I/O
MP /
PU1 /
VEXT
External System Request Reset 1
Default NMI function.
See also SCU chapter ´Reset Control Unit´ and
SCU_IOCR register description.
EVRWUP
VGATE1P
I
EVR Wakeup Pin
W17
K16
L19
J16
O
VGATE1P / External Pass Device gate control for EVR13
- /
VEXT
TMS
I
A2 /
PD /
VDDP3
JTAG Module State Machine Control Input
Device Access Port Line 1
DAP1
I/O
TRST
I
A2 /
PD /
VDDP3
JTAG Module Reset/Enable Input
TCK
I
I
A2 /
PD /
VDDP3
JTAG Module Clock Input
Device Access Port Line 0
DAP0
M20
M19
XTAL1
XTAL2
I
XTAL1 /
- /
VDDP3
Main Oscillator/PLL/Clock Generator Input
O
XTAL2 /
- /
Main Oscillator/PLL/Clock Generator Output
VDDP3
Table 2-72 Supply
Pin
Y6
Symbol
Ctrl
Type
Vx
Function
VAREF1
I
Positive Analog Reference Voltage 1
Y7
VAGND1
I
Vx
Negative Analog Reference Voltage 1
Data Sheet
TOC-289
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-72 Supply (cont’d)
Pin
T1
Symbol
Ctrl
Type
Vx
Function
VAREF2
I
Positive Analog Reference Voltage 2
T2
VAGND2
VDDM
I
I
I
Vx
Vx
Vx
Negative Analog Reference Voltage 2
ADC Analog Power Supply (3.3V / 5V)
Y5
G8, H7
VDD / VDDSB
Emulation Device: Emulation SRAM
Standby Power Supply (1.3V) (Emulation
Device only).
Production Device: VDD (1.3V).
P8, P13, N7, N14, H14, G13
N19
VDD
VDD
I
I
Vx
Vx
Digital Core Power Supply (1.3V)
Digital Core Power Supply (1.3V).
The supply pin inturn supplies the main
XTAL Oscillator/PLL (1.3V) . A higher
decoupling capacitor is therefore
recommended to the VSS pin for better
noise immunity.
A2, B3, V19, W20
B18, A19
VEXT
I
I
Vx
Vx
External Power Supply (5V / 3.3V)
VDDP3
Digital Power Supply for Flash (3.3V).
Can be also used as external 3.3V Power
Supply for VFLEX.
N20
VDDP3
I
Vx
Digital Power Supply for Oscillator,
LVDSH and A2 pads (3.3V).
The supply pin inturn supplies the main
XTAL Oscillator/PLL (3.3V) . A higher
decoupling capacitor is therefore
recommended to the VSS pin for better
noise immunity.
E15, D16
D5
VDDFL3
VFLEX
VSSM
I
I
I
I
Vx
Vx
Vx
Vx
Flash Power Supply (3.3V)
Digital Power Supply for Flex Port Pads
(5V / 3.3V)
Y4
Analog Ground for VDDM
T11
VEVRSB
Standby Power Supply (3.3V/5V) for the
Standby SRAM (CPU0.DSPR).
If Standby mode is not used: To be
handled like VEXT (3.3V/5V).
B2, D4, E5, T16, U17, W19,
Y20, E16, D17, B19, A20, L20
VSS
VSS
I
Vx
Vx
Digital Ground (outer balls)
Digital Ground (center balls)
V 1.1 2019-03
P9, P12, N9, N10, N11, N12
I
Data Sheet
TOC-290
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-72 Supply (cont’d)
Pin
Symbol
Ctrl
Type
Vx
Function
M7, M8, M10, M11, M13, M14 VSS
I
Digital Ground (center balls)
L8, L9, L10, L11, L12, L13
K8, K9, K10, K11, K12, K13
J7, J8, J10, J11, J13, J14
VSS
VSS
VSS
I
I
I
I
Vx
Vx
Vx
Vx
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
Digital Ground (center balls)
H9, H10, H11, H12, G9, G10, VSS
G11, G12
P10
P11
L7
VSS
I
I
I
I
I
I
Vx
Vx
Vx
Vx
Vx
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT TX0N
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT TX0P
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT CLKN
K7
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT CLKP
L14
K14
VSS
Digital Ground (center balls)
This ball is used in the Emulation Device
as
AGBT ERR
NC / VDDPSB
NCVDD Emulation Device: Power Supply (3.3V)
PSB
for DAP/JTAG pad group. Can be
connected to VDDP or can be left
unsupplied (see document ´AurixED´ /
Aurix Emulation Devices specification.
Production Device:
This pin is not connected on package
level. It can be connected on PCB level
to VDDP or Ground or can be left
unsupplied.
A1, Y1, U4
NC
I
NC1
Not Connected.
These pins are not connected on
package level and will not be used for
future extensions.
Data Sheet
TOC-291
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Legend:
Column “Ctrl.”:
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Type”:
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input
function)
MP = Pad class MP (5V/3.3V)
MP+ = Pad class MP+ (5V/3.3V)
MPR = Pad class MPR (5V/3.3V)
A2 = Pad class A2 (3.3V)
LVDSM = Pad class LVDSM (5V/3.3V)
LVDSH = Pad class LVDSH (3.3V)
S = Pad class S (Class S parameters for digital input and class D parameters for analog input function)
D = Pad class D (VADC / DSADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active
during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.
Data Sheet
TOC-292
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
2.3.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or High-Z depending on HWCFG[6] level latched during Porst active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O
Ports and Peripheral I/O Lines”, P00 / P01)
•
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.3.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Table 2-73 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
Data Sheet
TOC-293
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Table 2-73 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
ESR1
TDO
PORST = 0
Pull-up3)
Pull-up
PORST = 1
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
TOC-294
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
2.4
TC29x Bare Die Pad Definition
The TC290 / TC297 / TC298 / TC299 BC-Step Bare Die Logic Symbol is shown in Figure 2-4.
Table 2-74 describes the pads of the TC290 / TC297 / TC298 / TC299 bare die. It describes also the mapping of
VADC / DS-ADC channels to the analog inputs (ANx) and the mapping of Port functions to the pads.
The detailed description of the port functions (Px.y) can be found in the User’s Manual chapter “General Purpose
I/O Ports and Peripheral I/O LInes (Ports)“.
Pad 366
Pad 367
Pad 234
Pad 233
Y
0.0
X
Pad 480
Pad 102
Pad 1
Pad 101
Figure 2-4 TC290 / TC297 / TC298 / TC299 Logic Symbol for the Bare Die.
Table 2-74 TC29x Bare Die Pad List
Number
Pad Name
VEXT
Pad Type
X
Y
Comment
1
Vx
-4328000
-4295000
-4186500
-4295000
-4186500
-4295000
-4186500
-4295000
-4186500
-4295000
-4186500
-4295000
-4186500
Must be bonded to VEXT
2
P15.10
P15.2
LP / PU1 / VEXT -4123000
MP / PU1 / VEXT -4193000
LP / PU1 / VEXT -3983000
MP / PU1 / VEXT -4053000
LP / PU1 / VEXT -3863000
LP / PU1 / VEXT -3923000
LP / PU1 / VEXT -3753000
GPIO
3
GPIO
4
P15.11
P15.4
GPIO
5
GPIO
6
P15.12
P15.1
GPIO
7
GPIO
8
P15.13
VSS
GPIO
9
Vx
-3808000
Must be bonded to VSS
10
11
12
P15.14
P15.3
MP / PU1 / VEXT -3603000
MP / PU1 / VEXT -3683000
MP / PU1 / VEXT -3443000
GPIO
GPIO
GPIO
P15.15
Data Sheet
TOC-295
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
13
Pad Name
P15.5
Pad Type
X
Y
Comment
MP / PU1 / VEXT -3523000
MP / PU1 / VEXT -3283000
MP / PU1 / VEXT -3363000
MP / PU1 / VEXT -3153000
-4295000
-4186500
-4295000
-4186500
-4295000
-4295000
-4186500
GPIO
14
P15.6
GPIO
15
P15.7
GPIO
16
P15.8
GPIO
17
VEXT
Vx
-3218000
Must be bonded to VEXT
18
P14.1
MP / PU1 / VEXT -3073000
GPIO
GPIO
19
P14.0
MP+ / PU1 /
VEXT
-2983000
20
21
P14.3
P14.2
LP / PU1 / VEXT -2843000
LP / PU1 / VEXT -2903000
-4186500
-4295000
GPIO
Must be bonded to VEXT if
EVR13 active. Must be
bonded to VSS if EVR13
inactive.
22
23
24
25
26
27
28
29
P14.4
VSS
LP / PU1 / VEXT -2733000
-4186500
-4295000
-4295000
-4295000
-4186500
-4186500
-4295000
-4295000
GPIO
Vx
Vx
Vx
Vx
-2788000
-2674000
-2574000
-2505000
Must be bonded to VSS
Must be bonded to VDD
Must be bonded to VSS
Must be bonded to VDDP3
GPIO
VDD
VSS
VDDFL3
P14.11
VDDFL3
P14.5
LP / PU1 / VEXT -2380000
Vx
-2437500
-2300000
Must be bonded to VDDP3
GPIO
MP+ / PU1 /
VEXT
30
31
P14.12
P14.6
LP / PU1 / VEXT -2220000
-4186500
-4295000
GPIO
GPIO
MP+ / PU1 /
VEXT
-2140000
32
P14.13
MP+ / PU1 /
VEXT
-2040000
-4186500
GPIO
33
34
P14.7
LP / PU1 / VEXT -1960000
-4295000
-4186500
GPIO
GPIO
P14.14
MP+ / PU1 /
VEXT
-1880000
35
36
37
VEXT
P14.8
P14.9
Vx
-1805000
-4295000
-4186500
-4295000
Must be bonded to VEXT
LP / PU1 / VEXT -1750000
GPIO
GPIO
MP+ / PU1 /
VEXT
-1670000
38
39
P14.15
P14.10
LP / PU1 / VEXT -1590000
-4186500
-4295000
GPIO
GPIO
MP+ / PU1 /
VEXT
-1510000
40
41
42
VDDFL3
VSS
Vx
Vx
-1410000
-1345000
-4186500
-4295000
-4186500
Must be bonded to VDDP3
Must be bonded to VSS
GPIO
P13.0
LVDSM_N / PU1 -1270000
/ VEXT
Data Sheet
TOC-296
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
43
P13.1
LVDSM_P / PU1 -940000
/ VEXT
-4186500
GPIO
44
45
VEXT
P13.2
Vx
-865000
-4295000
-4186500
Must be bonded to VEXT
GPIO
LVDSM_N / PU1 -790000
/ VEXT
46
P13.3
LVDSM_P / PU1 -460000
/ VEXT
-4186500
GPIO
47
48
VSS
Vx
-385000
-4295000
-4186500
Must be bonded to VSS
GPIO
P13.4
LVDSM_N / PU1 -310000
/ VEXT
49
P13.5
LVDSM_P / PU1 20000
/ VEXT
-4186500
GPIO
50
51
VEXT
P13.6
Vx
95000
-4295000
-4186500
Must be bonded to VEXT
GPIO
LVDSM_N / PU1 170000
/ VEXT
52
P13.7
LVDSM_P / PU1 500000
/ VEXT
-4186500
GPIO
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
P13.11
P13.12
VDDP3
VDDP3
VEXT
VEXT
VDD
LP / PU1 / VEXT 580000
LP / PU1 / VEXT 640000
-4295000
-4186500
-4295000
-4186500
-4295000
-4186500
-4295000
-4295000
-4186500
-4295000
-4186500
-4295000
-4186500
-4295000
-4295000
GPIO
GPIO
Vx
Vx
Vx
Vx
Vx
Vx
697500
765000
830000
880000
955000
1055000
Must be bonded to VDDP3
Must be bonded to VDDP3
Must be bonded to VEXT
Must be bonded to VEXT
Must be bonded to VDD
Must be bonded to VSS
GPIO
VSS
P13.13
P13.9
P13.14
VEXT
P13.10
VDDFL3
VSS
LP / PU1 / VEXT 1135000
MP / PU1 / VEXT 1205000
LP / PU1 / VEXT 1275000
GPIO
GPIO
Vx
1330000
Must be bonded to VEXT
GPIO
LP / PU1 / VEXT 1385000
Vx
Vx
1455000
1575000
Must be bonded to VDDP3
Must be bonded to VSS
(Double Pad / Center of
Elephant Pad Opening)
68
69
70
VDDFL3
P13.15
P12.0
Vx
1542500
-4186500
-4186500
-4186500
Must be bonded to VDDP3
LP / PU1 / VEXT 1660000
GPIO
GPIO
LP / PU1 /
VFLEX
1790000
71
P12.1
LP / PU1 /
VFLEX
1850000
-4295000
GPIO
Data Sheet
TOC-297
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
72
P11.0
MP+ / PU1 /
VFLEX
1930000
-4186500
GPIO
73
74
VSS
Vx
2005000
2080000
-4295000
-4186500
Must be bonded to VSS
GPIO
P11.1
MP+ / PU1 /
VFLEX
75
VFLEX
Vx
2155000
-4295000
Digital Power Supply for
VFLEX Ports / Pads (5V /
3.3V)
76
77
78
79
80
P11.2
P11.4
P11.3
P11.5
P11.6
MPR/ PU1 /
VFLEX
2230000
2330000
2430000
2510000
2590000
-4186500
-4295000
-4186500
-4295000
-4186500
GPIO
GPIO
GPIO
GPIO
GPIO
MP+ / PU1 /
VFLEX
MPR/ PU1 /
VFLEX
LP / PU1 /
VFLEX
MPR/ PU1 /
VFLEX
81
82
VSS
Vx
2665000
2740000
-4295000
-4186500
Must be bonded to VSS
GPIO
P11.9
MP+ / PU1 /
VFLEX
83
84
P11.7
LP / PU1 /
VFLEX
2820000
2935000
-4295000
-4295000
GPIO
VFLEX
Vx
Digital Power Supply for
VFLEX Ports / Pads (5V /
3.3V)
85
86
87
88
P11.8
LP / PU1 /
VFLEX
2880000
3050000
2990000
3130000
-4186500
-4295000
-4186500
-4186500
GPIO
GPIO
GPIO
GPIO
P11.13
P11.10
P11.11
LP / PU1 /
VFLEX
LP / PU1 /
VFLEX
MP+ / PU1 /
VFLEX
89
90
VSS
Vx
3215000
3300000
-4295000
-4186500
Must be bonded to VSS
GPIO
P11.12
MPR/ PU1 /
VFLEX
91
92
P11.14
P11.15
LP / PU1 /
VFLEX
3390000
3460000
-4295000
-4186500
GPIO
GPIO
LP / PU1 /
VFLEX
93
94
P10.0
VEXT
LP / PU1 / VEXT 3610000
-4295000
-4295000
GPIO
Vx
3775000
Must be bonded to VEXT
Data Sheet
TOC-298
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
95
Pad Name
P10.9
Pad Type
X
Y
Comment
GPIO
LP / PU1 / VEXT 3680000
-4186500
-4186500
96
P10.1
MP+ / PU1 /
VEXT
3865000
GPIO
97
98
P10.3
P10.4
MP / PU1 / VEXT 3970000
-4295000
-4295000
GPIO
GPIO
MP+ / PU1 /
VEXT
4150000
99
P10.10
P10.2
P10.11
P10.13
VSS
LP / PU1 / VEXT 4055000
MP / PU1 / VEXT 4310000
LP / PU1 / VEXT 4240000
LP / PU1 / VEXT 4419500
-4186500
-4295000
-4186500
-4050000
-4105000
-3930000
-3990000
-3810000
-3870000
-3690000
-3750000
-3580000
-3635000
-3520000
-3360000
-3420000
-3280000
GPIO
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
GPIO
GPIO
GPIO
Vx
4528000
Must be bonded to VSS
P10.14
P10.5
P10.15
P10.6
P02.13
P10.8
P10.7
VEXT
VDD
LP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
Vx
4528000
4528000
Must be bonded to VEXT
Must be bonded to VDD
GPIO
P02.12
VSS
LP / PU1 / VEXT 4419500
Vx
4528000
4528000
Must be bonded to VSS
GPIO
P02.0
MP+ / PU1 /
VEXT
116
117
118
P02.14
P02.1
LP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
-3200000
-3140000
-3060000
GPIO
GPIO
GPIO
P02.15
MP+ / PU1 /
VEXT
4419500
119
120
VSS
Vx
4528000
4419500
-2985000
-2910000
Must be bonded to VSS
GPIO
P02.2
MP+ / PU1 /
VEXT
121
122
P02.3
P02.4
LP / PU1 / VEXT 4528000
-2830000
-2750000
GPIO
GPIO
MP+ / PU1 /
VEXT
4419500
123
124
P02.9
P02.5
LP / PU1 / VEXT 4528000
-2670000
-2590000
GPIO
GPIO
MP+ / PU1 /
VEXT
4419500
125
126
127
P02.10
P02.6
VEXT
LP / PU1 / VEXT 4528000
MP / PU1 / VEXT 4419500
-2510000
-2440000
-2375000
GPIO
GPIO
Vx
4528000
Must be bonded to VEXT
Data Sheet
TOC-299
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
128
Pad Name
P02.7
P02.11
P02.8
VDD
Pad Type
X
Y
Comment
MP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
-2310000
-2240000
-2180000
-2095000
-1995000
-1937500
-1910000
GPIO
129
GPIO
130
GPIO
131
Vx
Vx
4528000
4528000
Must be bonded to VDD
Must be bonded to VSS
GPIO
132
VSS
133
P01.0
VSS
LP / PU1 / VEXT 4419500
134
Vx
4528000
Must be bonded to VSS
(Double Pad / Center of
Elephant Pad Opening)
135
136
137
138
139
140
141
142
143
144
145
146
147
148
VDD
Vx
4528000
-1780000
-1715000
-1660000
-1605000
-1545000
-1485000
-1425000
-1365000
-1305000
-1245000
-1190000
-1135000
-1065000
-975000
Must be bonded to VDD
P01.2
VSS
LP / PU1 / VEXT 4419500
Vx 4528000
GPIO
Must be bonded to VSS
P01.1
P01.3
P01.8
P01.4
P01.9
P01.5
P01.10
VEXT
P01.11
P01.6
P01.12
LP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
LP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
4528000
Must be bonded to VEXT
LP / PU1 / VEXT 4419500
MP / PU1 / VEXT 4528000
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
4419500
149
150
151
152
P01.7
VDD
MP / PU1 / VEXT 4528000
-885000
-785000
-685000
-610000
GPIO
Vx
Vx
4528000
4528000
4419500
Must be bonded to VDD
Must be bonded to VSS
GPIO
VSS
P01.13
MP+ / PU1 /
VEXT
153
154
VSS
Vx
4528000
4419500
-535000
-460000
Must be bonded to VSS
GPIO
P01.14
MP+ / PU1 /
VEXT
155
156
157
158
Reserved
P01.15
VEXT
Vx
4528000
-385000
-330000
-265000
-190000
Must be bonded to VSS
GPIO
LP / PU1 / VEXT 4419500
Vx
4528000
4419500
Must be bonded to VEXT
GPIO
P00.13
MP+ / PU1 /
VEXT
159
160
161
P00.0
P00.14
VSS
MP / PU1 / VEXT 4528000
LP / PU1 / VEXT 4419500
-100000
-30000
25000
GPIO
GPIO
Vx
4528000
Must be bonded to VSS
Data Sheet
TOC-300
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
162
P00.15
MP+ / PU1 /
VEXT
4419500
100000
GPIO
163
164
P00.1 (VADC7.5 D
/ DS5NA)
4419500
4528000
250000
310000
Analog input
Analog input
P00.2 (VADC7.4 D
/ DS5PA)
165
166
167
168
169
170
171
P00.3 (VADC7.3) D
4419500
4528000
4419500
4528000
4419500
4528000
4419500
370000
425000
480000
540000
600000
655000
710000
Analog input
VSS
Vx
Must be bonded to VSS
Analog input
P00.4 (VADC7.2) D
P00.5 (VADC7.1) D
P00.6 (VADC7.0) D
Analog input
Analog input
VEXT
Vx
Must be bonded to VEXT
Analog input
P00.7 (VADC6.5 D
/ DS4NA)
172
P00.8 (VADC6.4 D
/ DS4PA)
4528000
770000
Analog input
173
174
P00.9 (VADC6.3) D
4419500
4528000
830000
890000
Analog input
Analog input
P00.10
D
(VADC6.2)
175
P00.11
D
4419500
950000
Analog input
(VADC6.1)
176
177
VSS
Vx
D
4528000
4419500
1005000
1060000
Must be bonded to VSS
Analog input
P00.12
(VADC6.0)
178
179
180
181
182
183
VDD
Vx
Vx
Vx
Vx
Vx
Vx
4528000
4528000
4419500
4528000
4528000
4528000
1115000
1215000
1265000
1315000
1415000
1535000
Must be bonded to VDD
Must be bonded to VSS
Must be bonded to VEXT
Must be bonded to VSS
Must be bonded to VDD
VSS
VEXT
VSS
VDD
VAREF4
Positive Analog Reference
Voltage 4
184
VAGND4
Vx
4419500
1585000
NegativeAnalogReference
Voltage 4
185
186
VDDM
Vx
4528000
4419500
1635000
1685000
Must be bonded to VEXT
Analog input
AN47(VADC5.7/ S
DS3ND)
187
188
AN46(VADC5.6/ S
DS3PD)
4528000
4419500
1735000
1785000
Analog input
Analog input
AN45(VADC5.5/ S
DS3NC)
Data Sheet
TOC-301
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
189
AN44(VADC5.4/ S
DS3PC)
4528000
1835000
Analog input
190
AN43 (VADC5.3) D
4419500
1885000
Analog input (with pull
down diagnostics)
191
192
193
194
AN42 (VADC5.2) D
AN41 (VADC5.1) D
AN40 (VADC5.0) D
4528000
4419500
4528000
4528000
1935000
1985000
2035000
2135000
Analog input
Analog input
Analog input
AN38(VADC4.6/ S
DS3PB), P40.8
(SENT8A)
Analog input, GPI (SENT)
195
196
197
AN39(VADC4.7/ S
DS3NB), P40.9
(SENT9A)
4419500
4528000
4419500
2085000
2235000
2185000
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input
AN36(VADC4.4/ S
DS3PA), P40.6
(SENT6A)
AN37(VADC4.5/ S
DS3NA), P40.7
(SENT7A)
198
199
AN34 (VADC4.2) D
AN35 (VADC4.3) D
4528000
4419500
2335000
2285000
Analog input (with pull
down diagnostics)
200
201
202
AN32
(VADC4.0),
P40.4 (SENT4A)
S
S
S
4528000
4419500
4528000
2435000
2385000
2535000
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
AN33
(VADC4.1),
P40.5 (SENT5A)
AN70
(VADC10.6 /
DS9PA), P40.13
(SENT13A)
203
204
205
AN71
S
S
S
4419500
4528000
4419500
2485000
2635000
2585000
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
(VADC10.7 /
DS9NA), P40.14
(SENT14A)
AN68
(VADC10.4 /
DS8PA), P40.11
(SENT11A)
AN69
(VADC10.5 /
DS8NA), P40.12
(SENT12A)
Data Sheet
TOC-302
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
206
Pad Name
Pad Type
X
Y
Comment
VDDM
Vx
S
4528000
4419500
2735000
2685000
Must be bonded to VEXT
Analog input, GPI (SENT)
207
AN67
(VADC10.3 /
DS8NB), P40.10
(SENT10A)
208
209
210
VSSM
VSS
Vx
Vx
D
4528000
4419500
4528000
2835000
2785000
2935000
Must be bonded to VSS
Must be bonded to VSS
Analog input
AN65
(VADC10.1)
211
AN66
D
4419500
2885000
Analog input
(VADC10.2 /
DS8PB
212
213
214
215
AN63(VADC9.7/ D
DS7NB)
4528000
4419500
4528000
4419500
3035000
2985000
3135000
3085000
Analog input
Analog input
Analog input
Analog input
AN64
D
(VADC10.0)
AN61(VADC9.5/ D
DS7NA)
AN62(VADC9.6/ D
DS7PB)
216
217
AN59 (VADC9.3) D
4528000
4419500
3235000
3185000
Analog input
Analog input
AN60(VADC9.4/ D
DS7PA)
218
219
220
AN57 (VADC9.1) D
AN58 (VADC9.2) D
4528000
4419500
4528000
3335000
3285000
3435000
Analog input
Analog input
VAREF3
Vx
Positive Analog Reference
Voltage 3
221
222
AN56 (VADC9.0) D
4419500
4528000
3385000
3535000
Analog input
VAGND3
Vx
NegativeAnalogReference
Voltage 3
223
224
225
226
227
228
VAREF2
Vx
4419500
4528000
4419500
4528000
4419500
4528000
3485000
3635000
3585000
3735000
3685000
3835000
Positive Analog Reference
Voltage 2
AN55(VADC8.7/ D
DS6NB)
Analog input
VAGND2
Vx
NegativeAnalogReference
Voltage 2
AN53(VADC8.5/ D
DS6NA)
Analog input
Analog input
Analog input
AN54(VADC8.6/ D
DS6PB)
AN51 (VADC8.3) D
Data Sheet
TOC-303
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
229
AN52(VADC8.4/ D
DS6PA)
4419500
3785000
Analog input
230
231
232
233
234
235
236
237
238
AN49 (VADC8.1) D
AN50 (VADC8.2) D
4528000
4419500
4528000
4419500
4278000
4328000
4178000
4228000
4078000
3960000
3897400
4085000
4022600
4186500
4295000
4186500
4295000
4186500
Analog input
Analog input
VDDM
Vx
Must be bonded to VEXT
Analog input
AN48 (VADC8.0) D
AN31 (VADC3.7) D
Analog input
VSSM
Vx
Must be bonded to VSS
Analog input
AN29 (VADC3.5) D
AN30 (VADC3.6) D
Analog input
AN27
S
Analog input (with pull
down diagnostics), GPI
(SENT)
(VADC3.3),
P40.3 (SENT3A)
239
240
AN28 (VADC3.4) D
4128000
3978000
4295000
4186500
Analog input
AN25(VADC3.1/ S
DS2NB), P40.2
(SENT1A)
Analog input, GPI (SENT)
241
AN26
S
4028000
4295000
Analog input, GPI (SENT)
(VADC3.2),
P40.2 (SENT2A)
242
243
AN23 (VADC2.7) D
3878000
3928000
4186500
4295000
Analog input
AN24(VADC3.0/ S
DS2PB), P40.0
(SENT0A)
Analog input, GPI (SENT)
244
AN21(VADC2.5/ D
DS2NA)
3778000
4186500
Analog input
Analog input
245
246
AN22 (VADC2.6) D
AN19 (VADC2.3) D
3828000
3678000
4295000
4186500
Analog input (with pull
down diagnostics)
247
AN20(VADC2.4/ D
DS2PA)
3728000
4295000
Analog input
248
249
250
251
252
AN17 (VADC2.1) D
AN18 (VADC2.2) D
AN15 (VADC1.7) D
AN16 (VADC2.0) D
3578000
3628000
3478000
3528000
3378000
4186500
4295000
4186500
4295000
4186500
Analog input
Analog input
Analog input
Analog input
VAGND0
VAGND1
VAREF0
Vx
NegativeAnalogReference
Voltage 0
253
254
Vx
Vx
3428000
3278000
4295000
4186500
NegativeAnalogReference
Voltage 1
Positive Analog Reference
Voltage 0
Data Sheet
TOC-304
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
255
VAREF1
Vx
3328000
4295000
Positive Analog Reference
Voltage 1
256
257
258
259
260
261
262
263
VSS
Vx
Vx
3178000
3228000
3078000
3128000
2978000
3028000
2878000
2928000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
4295000
Must be bonded to VSS
Must be bonded to VSS
Analog input
VSSM
AN14 (VADC1.6) D
VDDM
Vx
Must be bonded to VEXT
Analog input
AN12 (VADC1.4) D
AN13 (VADC1.5) D
AN10 (VADC1.2) D
AN11 (VADC1.3) D
Analog input
Analog input
Analog input (with pull
down diagnostics)
264
265
266
267
AN8 (VADC1.0)
AN9 (VADC1.1)
AN6 (VADC0.6)
AN7 (VADC0.7)
D
D
D
D
2778000
2828000
2678000
2728000
4186500
4295000
4186500
4295000
Analog input
Analog input
Analog input
Analog input (with pull
down diagnostics)
268
269
270
AN4 (VADC0.4)
AN5 (VADC0.5)
D
D
D
2578000
2628000
2478000
4186500
4295000
4186500
Analog input
Analog input
Analog input
AN2 (VADC0.2 /
DS0PA)
271
272
AN3 (VADC0.3 /
DS0NA)
D
D
2528000
2378000
4295000
4186500
Analog input
Analog input
AN1 (VADC0.1 /
DS1NA)
273
274
VSSM
Vx
D
2428000
2278000
4295000
4186500
Must be bonded to VSS
Analog input
AN0 (VADC0.0 /
DS1PA)
275
276
277
278
279
280
281
282
283
284
285
286
287
VDDM
EVR_OFF
P33.0
VSS
Vx
Vx
2328000
2158000
4295000
4295000
4186500
4295000
4186500
4295000
4186500
4295000
4295000
4186500
4295000
4186500
4295000
Must be bonded to VEXT
Must be bonded to VSS
GPIO
LP / PU1 / VEXT 2103000
Vx 2048000
Must be bonded to VSS
GPIO
P33.1
P34.1
P33.2
VSS
LP / PU1 / VEXT 1993000
LP / PU1 / VEXT 1933000
LP / PU1 / VEXT 1873000
GPIO
GPIO
Vx
Vx
1778000
1678000
Must be bonded to VSS
Must be bonded to VDD
GPIO
VDD
P33.3
VEXT
VEXT
P34.2
LP / PU1 / VEXT 1583000
Vx
Vx
1509000
1440000
Must be bonded to VEXT
Must be bonded to VEXT
GPIO
LP / PU1 / VEXT 1385000
Data Sheet
TOC-305
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
288
Pad Name
P33.4
P34.3
P33.5
P34.4
P33.6
P34.5
P33.7
P33.8
Pad Type
X
Y
Comment
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
LP / PU1 / VEXT 1325000
LP / PU1 / VEXT 1265000
LP / PU1 / VEXT 1205000
LP / PU1 / VEXT 1145000
LP / PU1 / VEXT 1085000
LP / PU1 / VEXT 1015000
LP / PU1 / VEXT 955000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
4295000
289
290
291
292
293
294
295
MP / HighZ /
VEXT
885000
296
297
298
299
300
301
302
303
304
305
306
307
308
P33.9
LP / PU1 / VEXT 815000
Vx 760000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
GPIO
VSS
Must be bonded to VSS
P33.10
P33.14
P33.11
P33.15
P33.12
P32.5
MP / PU1 / VEXT 695000
LP / PU1 / VEXT 625000
MP / PU1 / VEXT 555000
LP / PU1 / VEXT 485000
MP / PU1 / VEXT 415000
LP / PU1 / VEXT 345000
MP / PU1 / VEXT 275000
LP / PU1 / VEXT 205000
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
P33.13
P32.6
GPIO
GPIO
VGATE3P (LDO) VGATE3P
150000
96000
37000
Must be bonded to VSS
Must be bonded to VEXT
GPIO
VEXT
P32.0
Vx
LP / EVR13
SMPS -> PD,
GPIO -> PU1 /
VEXT
309
310
VGATE1N
(SMPS)
VGATE1N
-18000
-68000
-118000
4295000
4186500
Must be bonded to VSS if
EVR13 SMPS is not used.
Must be bonded to NMOS
gate if EVR13 SMPS is
used.
VGATE1P
(SMPS)
VGATE1P
Must be bonded to VEXT if
EVR13 SMPS is not used.
Must be bonded to PMOS
gate if EVR13 SMPS is
used.
311
312
313
314
315
316
VGATE1P (LDO) VGATE1P
4295000
4186500
4295000
4295000
4186500
4295000
VGATE1P (LDO)
GPIO
P32.2
VSS
LP / PU1 / VEXT -173000
Vx
Vx
-268000
-368000
Must be bonded to VSS
Must be bonded to VDD
GPIO
VDD
P32.3
P32.7
LP / PU1 / VEXT -463000
LP / PU1 / VEXT -523000
GPIO
Data Sheet
TOC-306
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
317
P32.4
MP+ / PU1 /
VEXT
-603000
4186500
GPIO
318
319
VSS
Vx
-678000
-823000
4295000
4295000
Must be bonded to VSS
GPIO
P31.0
MP / PU1 /
VFLEXE
320
321
322
P31.1
P31.2
P31.3
MP / PU1 /
VFLEXE
-903000
-983000
-1063000
4186500
4295000
4186500
GPIO
GPIO
GPIO
MP / PU1 /
VFLEXE
MP / PU1 /
VFLEXE
323
324
VSS
Vx
-1128000
-1193000
4295000
4186500
Must be bonded to VSS
GPIO
P31.4
MP / PU1 /
VFLEXE
325
326
327
328
329
330
331
332
333
334
P31.5
MP / PU1 /
VFLEXE
-1273000
-1353000
-1433000
-1513000
-1578000
-1643000
-1723000
-1803000
-1883000
-1963000
4295000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
GPIO
GPIO
GPIO
GPIO
P31.6
MP / PU1 /
VFLEXE
P31.7
MP / PU1 /
VFLEXE
P31.8
MP / PU1 /
VFLEXE
VFLEXE
P31.9
Vx
Must be bonded to VEXT or
VDDP3
MP / PU1 /
VFLEXE
GPIO
GPIO
GPIO
GPIO
GPIO
P31.10
P31.14
P31.15
P31.11
MP / PU1 /
VFLEXE
MP / PU1 /
VFLEXE
MP / PU1 /
VFLEXE
MP / PU1 /
VFLEXE
335
336
337
VSS
Vx
Vx
-2068000
-2168000
-2273000
4295000
4295000
4186500
Must be bonded to VSS
Must be bonded to VDD
GPIO
VDD
P31.12
MP / PU1 /
VFLEXE
338
339
VSS
Vx
-2338000
-2403000
4295000
4186500
Must be bonded to VSS
GPIO
P31.13
MP / PU1 /
VFLEXE
Data Sheet
TOC-307
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
340
P30.0
MP / PU1 /
VFLEXE
-2483000
4295000
GPIO
341
342
343
344
P30.1
MP / PU1 /
VFLEXE
-2563000
-2643000
-2788000
-2723000
4186500
4295000
4295000
4186500
GPIO
GPIO
P30.2
MP / PU1 /
VFLEXE
VFLEXE
P30.3
Vx
Must be bonded to VEXT or
VDDP3
MP / PU1 /
VFLEXE
GPIO
345
346
VSS
Vx
-2918000
-2853000
4295000
4186500
Must be bonded to VSS
GPIO
P30.4
MP / PU1 /
VFLEXE
347
348
349
350
351
352
353
354
355
356
P30.5
MP / PU1 /
VFLEXE
-2983000
-3063000
-3223000
-3143000
-3368000
-3303000
-3513000
-3433000
-3673000
-3593000
4186500
4295000
4295000
4186500
4295000
4186500
4295000
4186500
4295000
4186500
GPIO
GPIO
GPIO
GPIO
P30.6
MP / PU1 /
VFLEXE
P30.8
MP / PU1 /
VFLEXE
P30.7
MP / PU1 /
VFLEXE
VFLEXE
P30.9
Vx
Must be bonded to VEXT or
VDDP3
MP / PU1 /
VFLEXE
GPIO
GPIO
GPIO
GPIO
GPIO
P30.11
P30.10
P30.15
P30.12
MP / PU1 /
VFLEXE
MP / PU1 /
VFLEXE
MP / PU1 /
VFLEXE
MP / PU1 /
VFLEXE
357
358
VSS
Vx
-3818000
-3753000
4295000
4186500
Must be bonded to VSS
GPIO
P30.13
MP / PU1 /
VFLEXE
359
360
361
P26.0
P30.14
VSS
LP / PU1 /
VFLEXE
-3953000
-3883000
-4098000
4295000
4186500
4295000
GPIO
GPIO
MP / PU1 /
VFLEXE
Vx
Must be bonded to VSS
(Double Pad / Center of
Elephant Pad Opening)
Data Sheet
TOC-308
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
362
Pad Name
P25.0
P25.2
P25.1
P25.4
P25.3
P25.5
P25.7
VEBU
Pad Type
X
Y
Comment
GPIO
A2 / PU1 / VEBU -4078000
A2 / PU1 / VEBU -4228000
A2 / PU1 / VEBU -4178000
A2 / PU1 / VEBU -4338000
A2 / PU1 / VEBU -4288000
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4419500
4186500
4295000
4186500
4295000
4186500
4105000
4005000
4055000
363
GPIO
364
GPIO
365
GPIO
366
GPIO
367
GPIO
368
GPIO
369
Vx
-4528000
Must be bonded to VEXT or
VDDP3
370
371
372
373
374
375
376
377
378
379
380
P25.8
VSS
A2 / PU1 / VEBU -4419500
Vx -4528000
3905000
3955000
3805000
3855000
3755000
3605000
3655000
3505000
3555000
3405000
3455000
GPIO
Must be bonded to VSS
P25.10
P25.9
VSS
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
GPIO
GPIO
Vx
A2 / PU1 / VEBU -4419500
Vx -4528000
-4528000
Must be bonded to VSS
P25.11
VDD
GPIO
Must be bonded to VDD
P25.13
P25.12
P25.14
VEBU
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
A2 / PU1 / VEBU -4419500
GPIO
GPIO
GPIO
Vx
-4528000
Must be bonded to VEXT or
VDDP3
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
P25.6
P25.15
P24.1
P24.0
P24.2
VSS
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
A2 / PU1 / VEBU -4419500
3305000
3355000
3205000
3255000
3105000
3155000
3005000
3055000
2905000
2955000
2845000
2685000
2745000
2585000
2635000
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
-4528000
Must be bonded to VSS
P24.4
P24.3
P24.6
P24.5
VSS
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
GPIO
GPIO
GPIO
GPIO
Vx
A2 / PU1 / VEBU -4419500
Vx -4528000
A2 / PU1 / VEBU -4419500
Vx -4528000
-4528000
Must be bonded to VSS
GPIO
P24.7
VDD
Must be bonded to VDD
GPIO
P24.8
VEBU
Must be bonded to VEXT or
VDDP3
396
397
P24.10
P24.9
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
2485000
2535000
GPIO
GPIO
Data Sheet
TOC-309
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
398
Pad Name
P24.12
P24.11
P24.13
VSS
Pad Type
X
Y
Comment
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
A2 / PU1 / VEBU -4419500
2385000
2435000
2285000
2335000
2185000
2235000
2040000
GPIO
399
GPIO
400
GPIO
401
Vx
-4528000
Must be bonded to VSS
402
P24.15
P24.14
P23.5
A2 / PU1 / VEBU -4419500
A2 / PU1 / VEBU -4528000
GPIO
GPIO
GPIO
403
404
MP+ / PU1 /
VEXT
-4419500
405
406
407
408
VSS
Vx
-4528000
1965000
1910000
1855000
1780000
Must be bonded to VSS
GPIO
P23.0
VEXT
P23.1
LP / PU1 / VEXT -4419500
Vx
-4528000
-4419500
Must be bonded to VEXT
GPIO
MP+ / PU1 /
VEXT
409
410
411
412
413
414
415
VDD
Vx
Vx
-4528000
-4528000
1695000
1595000
1510000
1450000
1390000
1330000
1250000
Must be bonded to VDD
VSS
Must be bonded to VSS
P23.2
P23.6
P23.3
P23.7
P23.4
LP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4528000
LP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4528000
GPIO
GPIO
GPIO
GPIO
GPIO
MP+ / PU1 /
VEXT
-4419500
416
417
VSS
Vx
-4528000
1175000
1100000
Must be bonded to VSS
GPIO
P22.0
LVDSM_N / PU1 -4419500
/ VEXT
418
P22.1
LVDSM_P / PU1 -4419500
/ VEXT
770000
GPIO
419
420
421
VSS
Vx
Vx
-4528000
-4528000
688000
588000
513000
Must be bonded to VSS
Must be bonded to VDD
GPIO
VDD
P22.2
LVDSM_N / PU1 -4419500
/ VEXT
422
P22.3
LVDSM_P / PU1 -4419500
/ VEXT
183000
GPIO
423
424
425
426
427
428
429
430
VEXT
P22.4
VSS
Vx
-4528000
108000
53000
Must be bonded to VEXT
GPIO
LP / PU1 / VEXT -4419500
Vx
Vx
-4528000
-4528000
-2000
Must be bonded to VSS
Must be bonded to VDD
GPIO
VDD
-102000
-157000
-217000
-277000
-332000
P22.5
P22.7
P22.6
VSS
LP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4528000
LP / PU1 / VEXT -4419500
GPIO
GPIO
Vx
-4528000
Must be bonded to VSS
Data Sheet
TOC-310
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
431
Pad Name
P22.8
Pad Type
X
Y
Comment
LP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4528000
LP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4528000
-387000
-447000
-507000
-567000
-702000
-802000
-909500
GPIO
432
P22.9
GPIO
433
P22.10
GPIO
434
P22.11
GPIO
435
VDDOSC
VSSOSC
XTAL1
Vx
-4528000
-4528000
-4419500
Must be bonded to VSS
Must be bonded to VSS
436
Vx
437
XTAL1
Main Oscillator/PLL/Clock
Generator Input. Must be
bonded to external quartz
or resonator.
438
XTAL2
XTAL2
-4419500
-1009500
Main Oscillator/PLL/Clock
Generator Input. Must be
bonded to external quartz
or resonator.
439
440
441
442
VSSOSC
VDDOSC3
VDDP3
Vx
Vx
Vx
-4528000
-4419500
-4528000
-1117000
-1167000
-1257000
-1362500
Must be bonded to VSS
Must be bonded to VDDP3
Must be bonded to VDDP3
GPIO
P21.0
LVDSH_N / PU1 -4419500
/ VDDP3
443
P21.1
LVDSH_P / PU1 -4419500
/ VDDP3
-1462500
GPIO
444
445
VSSP
P21.2
Vx
-4528000
-1525000
-1587500
Must be bonded to VSS
GPIO
LVDSH_N / PU1 -4419500
/ VDDP3
446
P21.3
LVDSH_P / PU1 -4419500
/ VDDP3
-1687500
GPIO
447
448
VDDP3
P21.4
Vx
-4528000
-1750000
-1824500
Must be bonded to VDDP3
GPIO
LVDSH_N / PU1 -4419500
/ VDDP3
449
450
VSS
Vx
-4528000
-2020000
-1975500
Must be bonded to VSS
(Double Pad / Center of
Elephant Pad Opening)
P21.5
LVDSH_P / PU1 -4419500
/ VDDP3
GPIO
451
452
453
454
455
VDD
Vx
Vx
-4528000
-4528000
-2150000
-2260000
-2210000
-2360000
-2310000
Must be bonded to VDD
Must be bonded to VSS
GPIO, TDI
VSSP
P21.6
A2 / PU / VDDP3 -4419500
Vx -4528000
A2 / PD / VDDP3 -4419500
VDDP3
TMS /DAP1
Must be bonded to VDDP3
JTAG Module State
Machine Control Input /
Device Access Port Line 1
Data Sheet
TOC-311
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-74 TC29x Bare Die Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
456
TCK /DAP0
A2 / PD / VDDP3 -4528000
-2460000
JTAG Module Clock Input /
Device Access Port Line 0
457
458
P21.7
A2 / PU / VDDP3 -4419500
A2 / PD / VDDP3 -4419500
-2410000
-2520000
GPIO, TDO
TRST (N)
JTAG Module
Reset/Enable Input
459
460
461
462
463
464
Reserved
VEXT
Vx
Vx
-4528000
-4528000
-2650000
-2780000
-2715000
-2890000
-2835000
-3007500
Must be bonded to VSS
Must be bonded to VEXT
GPIO
P20.0
MP / PU1 / VEXT -4419500
Vx -4528000
LP / PU1 / VEXT -4419500
VSS
Must be bonded to VSS
GPIO
P20.1
PORST (N)
PORST / PD /
VEXT
-4528000
Power On Reset Input.
Additional strong PD in
case of power fail.
465
466
P20.2
LP / PU1 / VEXT -4419500
MP / PU1 / VEXT -4528000
-2940000
-3150000
Testmode pin must be
bonded
ESR1 (N)
/EVRWUP
External System Request
Reset 1. Default NMI
function. EVR Wakeup Pin.
467
468
P20.3
LP / PU1 / VEXT -4419500
-3080000
-3290000
GPIO
ESR0 (N)
/EVRWUP
MP / OD
-4528000
External System Request
Reset 0. Default
configuration during and
after reset is open-drain
driver. The driver drives low
duringpower-onreset. EVR
Wakeup Pin.
469
470
471
472
473
474
475
476
477
478
479
480
P20.7
VEXT
P20.8
P20.6
P20.10
P20.9
P20.11
VSS
LP / PU1 / VEXT -4419500
Vx -4528000
-3220000
-3435000
-3370000
-3590000
-3520000
-3750000
-3680000
-3905000
-3820000
-4080000
-3990000
-4186500
GPIO
Must be bonded to VEXT
MP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4528000
MP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4528000
MP / PU1 / VEXT -4419500
GPIO
GPIO
GPIO
GPIO
GPIO
Vx
-4528000
Must be bonded to VSS
P20.12
P20.14
P20.13
P15.0
MP / PU1 / VEXT -4419500
MP / PU1 / VEXT -4528000
MP / PU1 / VEXT -4419500
LP / PU1 / VEXT -4263000
GPIO
GPIO
GPIO
GPIO
Legend:
Column “Number”:
Running number of pads in the pad frame
Data Sheet
TOC-312
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Column “Name”:
Symbolic name of the pad.
The functions mapped on GPIO pads “Px.y” are described in the User’s Manual chapter ”General Purpose I/O
Ports and Peripheral I/O LInes (Ports)”
Column “Type”:
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input
function)
MP = Pad class MP (5V/3.3V)
MP+ = Pad class MP+ (5V/3.3V)
MPR = Pad class MPR (5V/3.3V)
A2 = Pad class A2 (3.3V)
LVDSM = Pad class LVDSM (5V/3.3V)
LVDSH = Pad class LVDSH (3.3V)
S = Pad class S (Class S parameters for digital input and class D parameters for analog input function)
D = Pad class D (VADC / DSADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3)
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3)
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
Column “X” / “Y”:
Pad opening center coordinates
2.4.1
Pad Openings
Two different pad openings are used:
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups are active at GPIOs (Px.y) pins during
and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input
funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality).
3) If HWCFG[6] is connected to ground, port pins are predominantly in HighZ during and after reset. Exceptions are P33.8
(HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7
(port pins overlayed with JTAG functionality).
Data Sheet
TOC-313
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
•
•
Standard Pad Opening is 70um x 75um where 70um is the width of the opening (width as seen from the die
side) and 75um is the depth of the opening (from the die side into the silicon).
Double Pad or Elephant Pad Opening is 130um x 75um where 130um is the width of the opening (width as
seen from the die side) and 75um is the depth of the opening (from the die side into the silicon). Double Pads
are used only for supply and can be identified by the words ´Double Pad´ or ´Elephant Pad´ in the Comment
column.
2.4.2
Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input
signal (EMGSTOPA or EMGSTOPB) into a defined state:
•
•
Input state and
PU or HighZ depending on HWCFG[6] level latched during Porst active
Control of the Emergency Stop function:
•
•
•
The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop
Control”)
The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter “SCU”, “Emergency Stop Control”)
On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O
Lines”, “Emergency Stop Register”).
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
•
•
•
•
Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
Not available for P40.x (analoge input ANx overlayed with GPI)
Not available for P32.0 EVR13 SMPS mode.
Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK)
The Emergency Stop function can be overruled on the following GPIO Ports:
•
P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O
Ports and Peripheral I/O Lines”, P00 / P01)
•
•
P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register
P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00)
P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode).
No Overruling in the DXCM (Debug over can message) mode
•
•
•
•
P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI
P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode
P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI
P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.4.3
Pull-Up/Pull-Down Reset Behavior of the Pins
Data Sheet
TOC-314
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Table 2-75 List of Pull-Up/Pull-Down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
all GPIOs
Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0
Pull-up
TDI, TESTMODE
PORST1)
Pull-down with IPORST relevant
Pull-down with IPDLI relevant
TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is used to
drive low.2)
Pull-up3)
ESR1
TDO
Pull-up3)
Pull-up
High-Z/Pull-up4)
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.
3) See the SCU_IOCR register description.
4) Depends on JTAG/DAP selection with TRST.
In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case
of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.
Data Sheet
TOC-315
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationParameter Interpretation
3
Electrical Specification
3.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC290 / TC297 / TC298 / TC299
and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a
design, they are marked with an two-letter abbreviation in column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of the TC290 / TC297 /
TC298 / TC299 and must be regarded for a system design.
•
SR
Such parameters indicate System Requirements which must provided by the microcontroller system in which
the TC290 / TC297 / TC298 / TC299 designed in.
Data Sheet
3-316
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationAbsolute Maximum Ratings
3.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3-1 Absolute Maximum Ratings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Storage Temperature
T
ST SR
-65
-
170
°C
upto 65h @ TJ =
150°C; upto 15h @ TJ
= 170°C
Voltage at VDD power supply
pins with respect to VSS
V
V
DD SR
-
-
-
-
1.9
V
V
1)
Voltage at VDDP3 and VDDFL3
DDP3 SR
4.43
power supply pins with respect
1)
to VSS
Voltage at VDDM, VEXT and
V
DDM SR
-
-
-
7.0
V
V
V
FLEX power supply pins with
1)
respect to VSS
Voltage on any class A2 and
LVDSH input pin with respect
VIN SR
-0.5
min(
VDDP3
0.6 , 4.23
Whatever is lower
+
1)2)
to VSS
)
Voltage on all other input pins VIN SR
with respect to VSS
-0.5
-10
-
-
-
7.0
10
V
1)2)
Input current on any pin during IIN SR
mA
mA
overload condition 3)
Absolute maximum sum of all ΣIIN SR
input circuit currents during
overload condition 3)
-100
100
1) Valid for cumulated for up to 2.8h and pulse forms following a power supply switch on phase, where the rise and fall times
are releated to the system capacities and coils.
2) Voltages below VINmin have no Impact to the device reliabiltiy as Long as the times and currents defined in section Pin
Reliability in Overload for the affected pad(s) are not violated.
3) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may
damage the device.
Data Sheet
3-317
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPin Reliability in Overload
3.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience overload currents and
voltages that go beyond their own IO power supplies specification.
The following table defines overload conditions that will not cause any negative reliability impact if all the following
conditions are met:
•
•
full operation life-time (24500 h) is not exceeded
Operating Conditions are met for
–
–
pad supply levels
temperature
If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters
functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still
possible in most cases but with relaxed parameters.
Note:An overload condition on one or more pins does not require a reset.
Table 3-2 Overload Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-5
-15 1)
Max.
5
15 1)
Input current on any digital pin IIN
during overload condition
-
-
mA
mA
except LVDS pins
except LVDS pins;
limited to max. 20
pulses with 1ms pulse
length
Input current on LVDS pin
during overload condition
IINLVDS
-3
-
-
3
mA
mA
Absolute maximum sum of all IING
input circuit currents during
overload condition
-50
50
Input current on analog input
pin during overload condition
IINANA
-3
-5
-
-
3
5
mA
mA
limited to 60h over
lifetime
Absolute sum of all ADC inputs IINSCA
during overload condition
-20
-
-
20
mA
mA
Absolute maximum sum of all ΣIINS
input circuit currents during
overload condition
-100
100
Signal voltage over/undershoot VOUS
at GPIOs
V
SS - 2
-
VEXT/FLEX
+ 2
V
limited to 60h over
lifetime; Valid for LP,
MP, MP+, and MPR
pads
Inactive device pin current
during overload condtion 2)
IID
-1
-
-
1
mA
mA
All power supply
voltages VDDx = 0
Sum of all inactive device pin IIDS
-100
100
currents 2)
Data Sheet
3-318
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
digital inputs, negative 3)
KOVDN CC
-
-
4*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
A2 pads of P24.x and
P25.x; -2mA < IIN <
0mA
-
-
2*10-4
-
Overload injected on
GPIO non LVDS pad
and affecting neighbor
LP and A2 (exept
P24.x and P25.x)
pads; -2mA < IIN <
0mA
-
1*10-2
Overload injected on
GPIO non LVDS pad
and affecting neighbor
LP and A2 pads (exept
P25.2 and P25.4); -
5mA < IIN < -2mA
-
-
-
-
6*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
LP and A2 pads; -2mA
< IIN < 0mA
1.7*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
MP, MP+, and MPR
pads; -2mA < IIN <
0mA
-
-
-
-
2*10-2
Overload injected on
GPIO non LVDS pad
and affecting neighbor
MP, MP+, and MPR
pads; -5mA < IIN < -
2mA
1.5*10-2
Overload injected on
GPIO non LVDS pad
and affecting neighbor
pads P25.2 and P25.4;
-5mA < IIN < -2mA
-
-
-
-
0.3
Overload injected on
LVDS pad and
affecting neighbor
LVDS pads
0.93
couplingbetweenpads
21.0, 21.1,21.2 and
V 1.1 2019-03
21.3
Data Sheet
3-319
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
digital inputs, positive 3)
K
OVDP CC
-
-
-
-
-
-
-
1*10-5
Overload injected on
GPIO non LVDS pad
and affecting neighbor
GPIO non LVDS pads
-
-
-
-
-
1.6*10-4
1*10-4
Overload injected on
GPIO pad and
affecting neighbor
P32.0 pad
Overload injected on
GPIO pad and
affecting neighbor
P32.4 and P33.12 pad
5*10-4
Overload injected on
LVDS pad and
affecting neighbor
LVDS pads
Overload coupling factor for
analog inputs, negative
KOVAN CC
6*10-4 4)
Analog Inputs overlaid
with class LP pads or
pull down diagnostics;
-1mA < IIN < 0mA
1*10-2
Analog Inputs overlaid
with class LP pads or
pull down diagnostics;
-5mA < IIN < -1mA
-
-
-
-
1*10-4
1*10-5
else; -5mA < IIN < 0mA
5mA < IIN < 0mA
Overload coupling factor for
analog inputs, positive
KOVAP CC
1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters.
2) Limitations for time and supply levels specified in this section are not valid for this parameter.
3) Overload is measured as increase of pad leakage caused by injection on neighbor pad.
4) For analogue inputs overlaid with DSADC function the VCM holdbuffer shall be enabled, in case DSADCs are enabled.
Note:DSADC input pins count as analog pins as they are overlaid with VADC pins.
Table 3-3 PN-Junction Characteristics for positive Overload
Pad Type
F / A2
IIN = 3 mA
IIN = 5 mA
UIN = VDDP3 + 0.5 V
UIN = VEXT / FLEX + 0.75 V
UIN = VEXT + 0.75 V
UIN = VDDP3 + 0.5 V
UIN = VDDM + 0.75 V
UIN = VDDP3 + 0.6 V
LP / MP / MP+
LVDSM
LVDSH
D
UIN = VEXT / FLEX + 0.8 V
-
-
-
Data Sheet
3-320
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPin Reliability in Overload
Table 3-4 PN-Junction Characteristics for negative Overload
Pad Type
F / A2
IIN = -3 mA
IIN = -5 mA
UIN = VSS - 0.5 V
UIN = VSS - 0.75 V
UIN = VSS - 0.75 V
UIN = VSS - 0.5 V
UIN = VSS - 0.75 V
UIN = VSS - 0.6 V
LP / MP / MP+
LVDSM
LVDSH
D
UIN = VSS - 0.8 V
-
-
-
Data Sheet
3-321
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationOperating Conditions
3.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the
TC290 / TC297 / TC298 / TC299. All parameters specified in the following tables refer to these operating
conditions, unless otherwise noticed.
Digital supply voltages applied to the TC290 / TC297 / TC298 / TC299 must be static regulated voltages.
All parameters specified in the following tables refer to these operating conditions (see table below), unless
otherwise noticed in the Note / Test Condition column.
Table 3-5 Operating Conditions
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
270
300 1)
SRI frequency
f
f
f
f
f
SRI SR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
-
Max System Frequency
CPU0 Frequency
CPU1 Frequency
CPU2 Frequency
MAX SR
CPU0 SR
CPU1 SR
CPU2 SR
PLL SR
-
270
-
300 1)
270
300 1)
-
-
-
270
-
300 1)
270
300 1)
-
-
PLL output frequency
PLL_ERAY output frequency
SPB frequency
f
f
f
20
300
PLLERAY SR 20
400
SPB SR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90
100 1)
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
ASCLIN fast frequency
ASCLIN slow frequency
Baud2 frequency
Baud1 frequency
FSI2 frequency
f
f
f
f
f
f
f
f
ASCLINF SR
ASCLINS SR
BAUD2 SR
BAUD1 SR
FSI2 SR
270
300 1)
90
100 1)
270
300 1)
90
100 1)
270
300 1)
90
100 1)
FSI frequency
FSI SR
GTM frequency
GTM SR
90
100 1)
180
EBU frequency
EBU SR
200
Data Sheet
3-322
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationOperating Conditions
Table 3-5 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
90
100 1)
STM frequency
f
STM SR
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
mA
1.17V < VDD < 1.43V
1.235V < VDD < 1.43V
ERAY frequency
BBB frequency
f
f
f
ERAY SR
BBB SR
CAN SR
80
150
100
100
MultiCAN frequency
Absolute sum of short circuit
currents of the device
ΣISC_D SR
Ambient Temperature
TA SR
-40
-40
-40
-
-
-
125
150
170
°C
°C
°C
valid for all SAK
products
valid for all SAL
products
valid for all SAL
products without
package
Junction Temperature
TJ SR
-40
-
150
°C
°C
V
valid for all SAK
products
-40
-
170
valid for all SAL
products
Core Supply Voltage 2)
V
DD SR
1.17
1.3
1.43 3)
Only required if
externally supplied
ADC analog supply voltage
V
V
DDM SR
EXT SR
2.97
2.97
5.0
-
5.5 4)
4.5
V
V
Digital external supply voltage
for LP, MP, MP+ and LVDSM
pads and EVR 5)
3.3V pad parameters
are valid
4.5
5.0
-
5.5 4)
4.5
V
V
V
V
5V pad parameters are
valid
Digital supply voltage for Flex
port
V
FLEX SR
2.97
4.5
3.3V pad parameters
are valid
5.0
3.3
5.5 4)
3.63 7)
5V pad parameters are
valid
Digital supply voltage for
LVDSH and A2 pads 6)
V
V
DDP3 SR
2.97
3.3V pad parameters
are valid; only required
if externally supplied
Flash supply voltage 3.3V 2)
DDFL3 SR 2.97
3.3
3.63
V
Only required if
externally supplied
Digital ground voltage
V
V
SS SR
0
-
-
V
V
V
V
Analog ground voltage for VDDM
SSM CC
-0.1
0
-
0.1
Voltage to ensure defined pad VDDPPA CC 0.72
-
-
A2 and LVDSH
states 8)
1.4
-
LP, MP, MP+, MPR
and LVDSM
Data Sheet
3-323
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationOperating Conditions
Table 3-5 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Digital supply voltage for EBU
V
V
V
EBU SR
2.97
3.3
3.63
V
3.3V pad parameters
are valid; only required
if externally supplied
Digital external supply voltage
for EVR and during Standby
mode
EVRSB SR 2.97
-
5.5
V
Digital supply voltage for EBU
Flex port
FLEXE SR 2.97
4.5
3.3
5.0
4.5
5.5
V
V
3.3V pad parameters
are valid
5V pad parameters are
valid
1) VDD = 1.33V +- 7.5% (with increased nominal VDD) voltage by +2.5%.
2) No external inductive load permissible if EVR is used. All VDD pins shall be connected together externally on the PCB.
3) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
4) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
5) All VEXT pins shall be connected together externally on the PCB.
6) All VDDP3 pins shall be connected together externally on the PCB.
7) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
8) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-up/power-down
of VDDP3
.
Data Sheet
3-324
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
3.5
5 V / 3.3 V switchable Pads
Pad classes LP, MP and MP+ support both Automotive Level (AL) or TTL level (TTL) operation. Parameters are
defined for AL operation and degrade in TTL operation.
Table 3-6 Standard_Pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pin capacitance (digital
inputs/outputs)
CIO CC
-
6
10
pF
ns
Spike filter always blocked
pulse duration
t
SF1 CC
-
-
80
-
PORST only
PORST only
Spike filter pass-through pulse tSF2 CC
220
-
ns
duration
PORST pad output current 1)
I
PORST CC 11
13
-
-
mA
mA
V
EXT = 3.0V; VPORST
0.9V; TJ = 165°C
EXT = 4.5V; VPORST
1.0V
=
=
-
-
V
1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.
Table 3-7 Class LP 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for LP pad 1) HYSLP CC 0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input Leakage current for LP
pad
I
OZLP CC
-150
150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
-
350
nA
nA
else
Input leakage current for P32.0 IOZP320 CC -4900
4900
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-9400
-
9400
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); for TJ >
150°C
-5800
-
-
-
-
-
5800
nA
nA
µA
µA
µA
else
-12000
12000
else; for TJ > 150°C
Pull-up current for LP pad
I
PUHLP CC
|30|
|43|
-
-
V
V
V
IHmin; AL
-
IHmin; TTL
|107|
ILmax; AL and TTL
Data Sheet
3-325
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-7 Class LP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
|100|
-
Pull-down current for LP pad
I
PDLLP CC
-
µA
V
V
V
IHmin; AL and TTL
ILmax; AL
|46|
|21|
200
-
µA
-
-
µA
ILmax; TTL
On-Resistance for LP pad,
weak driver 2)
RDSONLPW
CC
620
1040
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-Resistance for LP pad,
medium driver 2)
Rise / fall time for LP pad 3)
RDSONLPM
CC
50
-
155
260
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
t
LP CC
-
-
-
-
-
95+2.1 * ns
CL
CL≤50pF; pin out
driver=weak
-
200+2.9 * ns
( CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=weak
-
25+0.5 * ns
CL
CL≤50pF; pin out
driver=medium
-
50+0.75 * ns
( CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=medium
Input high voltage for LP pad
Input low voltage for LP pad
V
V
V
IHLP SR
ILLP SR
ILHLP CC
(0.73*VEX
T/FLEX)-
0.25
2.03 4)
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
-
(0.52*VEX
T/FLEX)-
0.25
0.8 5)
-
-
-
V
V
Hysteresis active, TTL
Input low / high voltage for LP
pad
1.85
3.0
Hysteresis inactive;
not available for P14.2,
P14.4, P15.1, P15.10
and P15.11
Pad set-up time for LP pad
t
SET_LP CC
-
-
-
100
ns
Input leakage current for P02.1 IOZ021 CC
-150
1030
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ >
150°C
-150
-
340
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ =
150°C
-420
-350
-
-
-
-
-
1100
380
|105|
-
nA
nA
µA
µA
µA
else; TJ > 150°C
else; TJ = 150°C
Pull down current for P32_0 pin IPDLP320 CC -
|41|
|16|
V
V
V
IHmin; AL and TTL
ILmax; AL
-
ILmax; TTL
Data Sheet
3-326
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-7 Class LP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull Up Current for P32_0 pin
I
PUHP320 CC |25|
-
-
-
-
-
µA
µA
µA
mA
V
V
V
IHmin; AL
|38|
-
-
IHmin; TTL
|112|
10
ILmax; AL and TTL
Short Circuit current for LP pad ISC SR
-10
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-8 Class LP 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for LP pad 1) HYSLP CC 0.05 *
VEXT/FLEX
Input Leakage current for LP
pad
I
OZLP CC
-150
-
150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
-
350
nA
nA
else
Input leakage current for P32.0 IOZP320 CC -4900
4900
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-9400
-
9400
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); for TJ >
150 °C
-5800
-
5900
nA
nA
µA
µA
µA
µA
µA
µA
Ohm
else
-12000
-
12000
else; for TJ > 150°C
Pull-up current for LP pad
I
I
PUHLP CC
|17|
|19|
-
-
-
V
V
V
V
V
V
IHmin; AL
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for LP pad
PDLLP CC
-
-
|22|
|11|
250
-
-
-
ILmax; TTL
On-Resistance for LP pad,
weak driver 2)
RDSONLPW
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
Data Sheet
3-327
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-8 Class LP 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance for LP pad,
medium driver 2)
RDSONLPM
CC
70
235
400
Ohm
; NMOS/PMOS ;
IOH=1mA; IOL=1mA
Rise / fall time for LP pad 3)
t
LP CC
-
-
-
-
-
-
-
-
-
150+3.4 * ns
CL
CL≤50pF; pin out
driver=weak
320+4.5 * ns
( CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=weak
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
70+1.1 * ( ns
CL - 50 )
CL≥50pF; CL≤200pF;
pin out driver=medium
Input high voltage for LP pad
Input low voltage for LP pad
V
V
V
IHLP SR
ILLP SR
ILHLP CC
(0.73*VEX
T/FLEX)-
0.25
1.6 4)
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Input low / high voltage for LP
pad
1.1
1.9
Hysteresis inactive;
not available for P14.2,
P14.4, P15.1, P15.10
and P15.11
Pad set-up time for LP pad
t
SET_LP CC
-
-
-
100
920
ns
Input leakage current for P02.1 IOZ021 CC
-150
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ >
150°C
-150
-
330
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX); TJ =
150°C
-360
-350
-
-
-
-
-
-
-
-
-
1000
nA
nA
µA
µA
µA
µA
µA
µA
mA
else; TJ > 150°C
else; TJ = 150°C
375
Pull down current for P32_0 pin IPDLP320 CC -
|17|
|80|
V
V
V
V
V
V
IHmin; AL and TTL
ILmax; AL
-
|6|
-
ILmax; TTL
Pull Up Current for P32_0 pin
I
PUHP320 CC |12|
-
IHmin; AL
|14|
-
-
IHmin; TTL
|80|
10
ILmax; AL and TTL
Short Circuit current for LP pad ISC SR
-10
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
Data Sheet
3-328
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-9 Class MP 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for MP pad 1) HYSMP CC 0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input Leakage current for MP
pad
I
I
OZMP CC
-500
500
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1000
-
1000
nA
else
Pull-up current for MP pad
PUHMP CC |30|
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|43|
-
-
-
IHmin; TTL
-
|107|
|100|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP pad
I
PDLMP CC
-
-
|46|
|21|
-
-
-
ILmax; TTL
On-Resistance for MP pad,
weak driver 2)
RDSONMPW 200
CC
620
1040
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-Resistance for MP pad,
medium driver 2)
RDSONMPM
CC
50
20
155
75
260
130
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-Resistance for MP pad,
strong driver 2)
RDSONMPS
CC
PMOS/NMOS ;
IOH=8mA; IOL=8mA
Data Sheet
3-329
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-9 Class MP 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise / fall time for MP pad 3)
t
MP CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF; pin out
driver=weak
L
-
-
-
200+2.9*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
25+0.5*C ns
CL≤50pF; pin out
driver=medium
L
50 + 0.75 ns
CL≥50pF; CL≤200pF;
* ( CL - 50
)
pin out driver=medium
-
-
-
-
17.5+0.25 ns
*CL
CL≤50pF;
edge=medium ; pin out
driver=strong
30+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
7+0.2*CL ns
CL≤50pF; edge=sharp
; pin out driver=strong
17+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
Input high voltage for MP pad
Input low voltage for MP pad
V
V
IHMP SR
(0.73*VEX
T/FLEX)-
0.25
2.03 4)
-
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
ILMP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP VILHMP CC 1.85
3.0
pad
Pad set-up time for MP pad
t
SET_MP CC
-
-
-
100
10
ns
Short Circuit current for MP pad ISC SR
-10
mA
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Data Sheet
3-330
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-10 Class MP 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for MP pad 1) HYSMP CC 0.05 *
VEXT/FLEX
Input Leakage current for MP
pad
I
OZMP CC
-500
-
500
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1000
-
1000
nA
else
Pull-up current for MP pad
I
PUHMP CC |17|
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP pad
I
PDLMP CC
-
-
|22|
|11|
-
-
-
ILmax; TTL
On-Resistance for MP pad,
weak driver 2)
RDSONMPW 250
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
On-Resistance for MP pad,
medium driver 2)
RDSONMPM
CC
70
20
-
235
400
200
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA; IOL=1mA
On-Resistance for MP pad,
strong driver 2)
Rise / fall time for MP pad 3)
RDSONMPS
CC
110
PMOS/NMOS ;
I
OH=4mA; IOL=4mA
t
MP CC
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF; pin out
driver=weak
-
320+4.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
-
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
-
70+1.1*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
-
32.5+0.35 ns
CL≤50pF;
*CL
edge=medium ; pin out
driver=strong
-
-
50+0.45*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
14.5+0.35 ns
*CL
CL≤50pF; edge=sharp
; pin out driver=strong
32+0.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
Data Sheet
3-331
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-10 Class MP 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for MP pad
V
V
IHMP SR
(0.73*VEX
T/FLEX)-
0.25
1.6 4)
-
-
V
Hysteresis active, AL
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP pad
ILMP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP VILHMP CC 1.1
1.9
pad
Pad set-up time for MP pad
t
SET_MP CC
-
-
-
100
10
ns
Short Circuit current for MP pad ISC SR
-10
mA
absolute max value
(PSI5)
6)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-11 Class MP+ 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input hysteresis for MP+ pad 1) HYSMPP
0.09 *
CC
VEXT/FLEX
0.075 *
VEXT/FLEX
-
-
-
V
TTL
Input leakage current for MP+
pad
I
I
OZMPP CC -750
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPP CC |30|
-
-
-
-
-
-
-
1500
nA
µA
µA
µA
µA
µA
µA
else
Pull-up current for MP+ pad
-
V
V
V
V
V
V
IHmin; AL
|43|
-
-
IHmin; TTL
|107|
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP+ pad IPDLMPP CC
-
|100|
|46|
|21|
-
-
ILmax; TTL
Data Sheet
3-332
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-11 Class MP+ 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-resistance for MP+ pad,
weak driver 2)
RDSONMPPW 200
CC
620
1040
Ohm
Ohm
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-resistance for MP+ pad,
medium driver 2)
RDSONMPPM 50
CC
155
260
90
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-resistance for MP+ pad,
strong driver 2)
Rise/fall time for MP+ pad 3)
RDSONMPPS 20
CC
55
-
PMOS/NMOS ;
I
OH=8mA; IOL=8mA
t
MPP CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF; pin out
driver=weak
L
-
200+2.9*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
-
25+0.5*C ns
CL≤50pF; pin out
driver=medium
L
-
50+0.75*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
-
9+0.16*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=strong
-
-
17+0.2*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
4+0.16*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
12+0.21*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
-
-
5
ns
from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out
driver=strong
-
-
4.5
-
ns
V
CL=15pF; edge=sharp
; pin out driver=strong
Input high voltage for MP+ pad VIHMPP SR (0.73*VEX
Hysteresis active, AL
T/FLEX)-
0.25
2.03 4)
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP+ pad
V
ILMPP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP+ VILHMPP CC 1.85
3.0
pad
Pad set-up time for MP+ pad
t
SET_MPP CC -
-
100
ns
Data Sheet
3-333
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-11 Class MP+ 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Short circuit current for MP+
pad 6)
I
SCMPP SR -10
-
10
mA
%
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-12 Class MP+ 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input hysteresis for MP+ pad 1) HYSMPP
0.05 *
CC
VEXT/FLEX
Input leakage current for MP+
pad
I
OZMPP CC -750
-
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPP CC |17|
-
1500
nA
else
Pull-up current for MP+ pad
I
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for MP+ pad IPDLMPP CC
-
-
|22|
|11|
-
-
-
ILmax; TTL
On-resistance for MP+ pad,
weak driver 2)
RDSONMPPW 250
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
On-resistance for MP+ pad,
medium driver 2)
RDSONMPPM 70
CC
235
75
400
130
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA; IOL=1mA
PMOS/NMOS ;
IOH=4mA; IOL=4mA
On-resistance for MP+ pad,
strong driver 2)
RDSONMPPS 20
CC
Data Sheet
3-334
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-12 Class MP+ 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time for MP+ pad 3)
t
MPP CC
-
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF; pin out
driver=weak
-
-
-
-
320+4.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
70+1.1*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
20+0.2*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=strong
-
-
30+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
13+0.2*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
7.65
5.42
7.36
5.32
5.9
ns
ns
ns
ns
ns
ns
CL = 15pF; VEXT/FLEX
3.135V; V = 0V to
=
2.0V; edge=sharp ; pin
out driver=strong
-
-
-
-
-
-
-
-
-
-
-
CL = 15pF; VEXT/FLEX =
3.135V; V = 3.135V to
0.8V; edge=sharp ; pin
out driver=strong
CL = 15pF; VEXT/FLEX
3.201V; V = 0V to
=
2.0V; edge=sharp ; pin
out driver=strong
CL = 15pF; VEXT/FLEX
=
3.201V; V = 3.201V to
0.8V; edge=sharp ; pin
out driver=strong
CL = 15pF; VEXT/FLEX
=
3.63V; V = 0V to 2.0V;
edge=sharp ; pin out
driver=strong
4.8
CL = 15pF; VEXT/FLEX
3.63V; V = 3.63V to
=
0.8V; edge=sharp ; pin
out driver=strong
-
-
23+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
5
ns
ns
from 0.8V to 2.0V
(RMII) ; CL=25pF;
V 1.1 2019-03
edge=sharp ; pin out
Data Sheet
3-335
driver=strong
-
-
4.5
from 0.2 * VEXT/FLEX to
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-12 Class MP+ 3.3V (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for MP+ pad VIHMPP SR (0.73*VEX
-
-
V
Hysteresis active, AL
T/FLEX)-
0.25
1.6 4)
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage for MP+ pad
V
ILMPP SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage for MP+ VILHMPP CC 1.1
1.9
pad
Pad set-up time for MP+ pad
t
SET_MPP CC -
SCMPP SR -10
-
-
100
10
ns
Short circuit current for MP+
pad 6)
I
mA
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.
Table 3-13 Class MPR 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL
150
-
Input Hysteresis for MPR pads HYSMPR
0.09 *
VEXT/FLEX
1)
CC
0.075*
VEXT/FLEX
-
-
-
V
TTL
Input leakage current class
MPR
I
I
OZMPR CC -750
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPR CC |30|
-
-
-
-
-
-
-
1500
nA
µA
µA
µA
µA
µA
µA
else
Pull-up current
-
V
V
V
V
V
V
IHmin; AL
|43|
-
-
IHmin; TTL
|107|
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current
I
PDLMPR CC -
|100|
|46|
|21|
-
-
ILmax; TTL
Data Sheet
3-336
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-13 Class MPR 5V (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
On-resistance of the MPR pad, RDSONMPRW 200
weak driver 2)
CC
On-resistance of the MPR pad, RDSONMPRM 50
medium driver 2)
CC
Max.
620
1040
Ohm
Ohm
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
155
260
90
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-resistance of the MPR pad, RDSONMPRS 20
55
-
PMOS/NMOS ;
strong driver 2)
Rise/fall time 3)
CC
I
OH=8mA; IOL=8mA
t
MPR CC
-
-
-
-
-
95+2.1*C ns
CL≤50pF; pin out
driver=weak
L
-
200+2.9*( ns
CL≥50pF; CL≤200pF;
pin out driver=weak
CL-50)
-
25+0.5*C ns
CL≤50pF; pin out
driver=medium
L
-
50+0.75*( ns
CL≥50pF; CL≤200pF;
pin out driver=medium
CL-50)
-
9+0.16*C ns
CL≥0pF; CL≤50pF;
edge=medium ; pin out
driver=strong
L
-
-
17+0.2*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
4+0.16*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
12+0.21*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
-
-
-
-
5
ns
ns
V
from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out
driver=strong
4.5
from 0.2 * VEXT/FLEX to
0.8 * VEXT/FLEX
;
CL=15pF; edge=sharp
; pin out driver=strong
Input high voltage, class MPR
pads
V
V
V
IHMPR SR (0.73*VEX
-
-
Hysteresis active, AL
T/FLEX)-
0.25
2.03 4)
-
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage, class MPR
pads
ILMPR SR
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.8 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage, class
MPR pads
ILHMPR SR 1.2
2.3
Data Sheet
3-337
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-13 Class MPR 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
100
10
Pad set-up time
t
SET_MPR CC -
-
-
ns
Short circuit current Class MPR ISC SR
-10
mA
absolute max value
(PSI5)
Deviation of symmetry for rising SYM CC
-
-
20
%
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
Table 3-14 Class MPR 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
fIN SR
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
AL and TTL
100
-
Input Hysteresis for MPR pads HYSMPR
0.05 *
VEXT/FLEX
1)
CC
Input leakage current class
MPR
I
OZMPR CC -750
-
750
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-1500
PUHMPR CC |17|
-
1500
nA
else
Pull-up current
I
-
-
µA
µA
µA
µA
µA
µA
Ohm
V
V
V
V
V
V
IHmin; AL
|19|
-
-
-
IHmin; TTL
-
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current
I
PDLMPR CC -
-
|22|
|11|
-
-
-
ILmax; TTL
On-resistance of the MPR pad, RDSONMPRW 250
weak driver 2)
CC
875
1500
; NMOS/PMOS ;
I
OH=0.25mA;
IOL=0.25mA
On-resistance of the MPR pad, RDSONMPRM 70
medium driver 2)
CC
On-resistance of the MPR pad, RDSONMPRS 20
strong driver 2)
CC
235
75
400
130
Ohm
Ohm
; NMOS/PMOS ;
I
OH=1mA; IOL=1mA
PMOS/NMOS ;
OH=4mA; IOL=4mA
I
Data Sheet
3-338
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-14 Class MPR 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time 3)
t
MPR CC
-
-
-
-
-
-
150+3.4* ns
CL
CL≤50pF; pin out
driver=weak
-
-
-
-
320+4.5*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=weak
30+0.8*C ns
CL≤50pF; pin out
driver=medium
L
70+1.1*( ns
CL-50)
CL≥50pF; CL≤200pF;
pin out driver=medium
20+0.2*C ns
CL≥0pF; CL≤50pF;
edge=medium ; pin out
driver=strong
L
-
-
30+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
13+0.2*C ns
CL≤50pF; edge=sharp
; pin out driver=strong
L
23+0.3*( ns
CL-50)
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
-
-
-
-
-
5
ns
ns
V
from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out
driver=strong
4.5
from 0.2 * VEXT/FLEX to
0.8 * VEXT/FLEX
;
CL=15pF; edge=sharp
; pin out driver=strong
Input high voltage, class MPR
pads
V
V
V
IHMPR SR (0.73*VEX
-
-
Hysteresis active, AL
T/FLEX)-
0.25
1.6 4)
-
-
V
V
Hysteresis active, TTL
Hysteresis active, AL
Input low voltage, class MPR
pads
ILMPR SR
-
(0.52*VEX
T/FLEX)-
0.25
-
-
-
0.5 5)
V
V
Hysteresis active, TTL
Hysteresis inactive
Input low / high voltage, class
MPR pads
ILHMPR SR 0.8
1.7
Pad set-up time
t
SET_MPR CC -
-10
-
-
100
10
ns
Short circuit current Class MPR ISC SR
mA
absolute max value
(PSI5)
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
Data Sheet
3-339
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
3) Rise / fall times are defined 10% - 90% of VEXT/FLEX
4) VIHx = 0.27 * VEXT/FLEX + 0.545V
5) VILx = 0.17 * VEXT/FLEX
.
Table 3-15 Class S
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
75
Input frequency
-
-
-
-
-
-
-
-
MHz
MHz
V
Hysteresis active
-
150
-
Hysteresis inactive
Input Hysteresis for S pad 1)
Pull-up current for S pad
HYSS CC
0.3
|30|
-
I
PUHS CC
-
µA
VIHmin
VILmax
VIHmin
VILmax
|107|
|100|
-
µA
Pull-down current for S pad
I
PDLS CC
-
µA
|46|
-350
µA
Input Leakage current Class S IOZS CC
350
nA
Analog Inputs with pull
down diagnostics
-150
-
-
-
150
nA
V
else
Input voltage high for S pad
Input voltage low for S pad
V
V
IHS SR
ILS SR
(0.73*VDD
M)-0.25
Hysteresis active
(0.52*VDD
M)-0.25
-
-
-
V
Hysteresis active
Input low threshold variation for VILSD SR
-50
50
mV
max. variation of 1ms;
VDDM=constant
S pad 2)
Input capacitance for S pad
Pad set-up time for S pad
C
INS CC
-
-
-
-
10
pF
ns
t
SETS CC
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VILSD is implemented to ensure J2716 specification. For details of dedicated pins please see AP32286 for details.
Table 3-16 Class I 5V
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
Input frequency
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
PORST pad only
150
-
Input Hysteresis for I pad 1)
HYSI CC
0.07 *
VEXT/FLEX
0.09 *
VEXT/FLEX
-
-
-
-
V
V
AL
0.075 *
TTL
VEXT/FLEX
Pull-up current for I pad
Data Sheet
I
PUHI CC
|30|
|43|
-
-
-
-
-
µA
µA
µA
V
V
V
IHmin; AL
-
IHmin; TTL
|107|
ILmax; AL and TTL
3-340
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-16 Class I 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
|100|
-
Pull-down current for I pad
I
PDLI CC
-
-
-
-
µA
µA
µA
nA
V
V
V
IHmin; AL and TTL
ILmax; AL
|46|
|21|
-150
-
ILmax; TTL
Input Leakage Current for I pad IOZI CC
150
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
2.03 2)
-
-
-
350
nA
V
else
Input high voltage for I pad
Input low voltage for I pad
V
V
IHI SR
-
-
Hysteresis active, TTL
(0.73*VEX
T/FLEX)-
0.25
V
Hysteresis active; AL;
not available for the
PORST pad
ILI SR
-
-
-
-
0.8 3)
V
V
Hysteresis active, TTL
(0.52*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low / high voltage for I pad VILHI CC
Pad set-up time for I pad SETI CC
1.85
-
-
-
3.0
V
Hysteresis inactive
t
100
ns
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VIHx = 0.27 * VEXT/FLEX + 0.545V
3) VILx = 0.17 * VEXT/FLEX
Table 3-17 Class I 3.3V
Parameter
Symbol
fIN SR
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
50
Input frequency
-
-
-
-
-
MHz
MHz
V
Hysteresis active
Hysteresis inactive
PORST pad only
100
-
Input Hysteresis for I pad 1)
HYSI CC
0.045 *
VEXT/FLEX
0.05 *
-
-
V
AL and TTL
VEXT/FLEX
Pull-up current for I pad
I
I
PUHI CC
|17|
|19|
-
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
µA
nA
V
V
V
V
V
V
IHmin; AL
-
IHmin; TTL
|75|
|75|
-
ILmax; AL and TTL
IHmin; AL and TTL
ILmax; AL
Pull-down current for I pad
PDLI CC
-
|22|
|11|
-150
-
ILmax; TTL
Input Leakage Current for I pad IOZI CC
150
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-350
-
350
nA
else
Data Sheet
3-341
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-17 Class I 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input high voltage for I pad
V
V
IHI SR
1.6 2)
-
-
-
-
V
V
Hysteresis active, TTL
(0.73*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low voltage for I pad
ILI SR
-
-
-
-
0.5 3)
V
V
Hysteresis active, TTL
(0.52*VEX
T/FLEX)-
0.25
Hysteresis active; AL;
not available for the
PORST pad
Input low / high voltage for I pad VILHI CC
Pad set-up time for I pad SETI CC
1.1
-
-
-
1.9
V
Hysteresis inactive
t
100
ns
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) VIHx = 0.27 * VEXT/FLEX + 0.545V
3) VILx = 0.17 * VEXT/FLEX
Table 3-18 Class A2
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input Hysteresis for A2 pad 1) HYSA2 CC 0.1 *
fIN SR
-
-
-
MHz
V
TTL;else
VDDP3
0.06 *
VDDP3
-
-
-
V
valid for P21.6 and
P21.7
Input Leakage current for A2
pad
I
OZA2 CC
-300
300
nA
(0.1*VEXT/FLEX) < VIN <
(0.9*VEXT/FLEX
)
-800
-
-
500
|100|
-
nA
else
Pull-up current for A2 pad
I
I
PUHA2 CC
-
µA
VIHmin
|25|
|23|
-
-
µA
VILmax
Pull-down current for A2 pad
PDLA2 CC
-
-
µA
VIHmin
-
|100|
325
µA
VILmax
On-Resistance for A2 pad,
weak driver 2)
RDSONA2W
CC
100
200
Ohm
PMOS/NMOS ;
I
OH=0.5mA; IOL=0.5mA
On-Resistance for A2 pad,
medium driver 2)
RDSONA2M
CC
40
20
70
35
100
50
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On-Resistance for A2 pad,
strong driver 2)
RDSONA2S
CC
PMOS/NMOS ;
IOH=8mA; IOL=8mA
Data Sheet
3-342
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-18 Class A2 (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise/fall time for A2 pad 3)
t
A2 CC
-
-
-
-
-
-
20+0.8*C ns
CL≤50pF; pin out
driver=weak
L
-
-
-
-
17.5+0.85 ns
*CL
CL≥50pF; CL≤200pF;
pin out driver=weak
12+0.16* ns
CL
CL≤50pF; pin out
driver=medium
11.5+0.17 ns
*CL
CL≥50pF; CL≤200pF;
pin out driver=medium
6+0.06*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=strong
-
-
5.5+0.07* ns
CL
CL≥50pF; CL≤200pF;
edge=medium ; pin out
driver=strong
-
-
-
-
0.0+0.12* ns
CL
CL≤50pF; edge=sharp
; pin out driver=strong
0.0+0.12* ns
CL
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=strong
Input high voltage for A2 pad
Input low voltage for A2 pad
Pad set-up time for A2 pad
V
V
IHA2 SR
2.04 4)
-
-
V
TTL;valid for all A2
pads except
TMS/DAP1, TRST,
and TCK/DAP0
0.7 *
VDDP3
-
-
-
V
V
valid for TMS/DAP1,
TRST, and TCK/DAP0
ILA2 SR
-
0.8 5)
TTL;valid for all A2
pads except
TMS/DAP1, TRST,
and TCK/DAP0
-
-
0.3 *
VDDP3
V
valid for TMS/DAP1,
TRST, and TCK/DAP0
t
SETA2 CC
-
-
-
-
100
20
ns
%
Deviation of symmetry for rising SYM CC
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VDDP3
4) VIHx = 0.57 * VDDP3 - 0.03V
.
5) VILx = 0.25 * VDDP3 + 0.058V
Data Sheet
3-343
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical Specification5 V / 3.3 V switchable Pads
Table 3-19 Driver Mode Selection for LP Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Driver Setting
medium (LPm)
weak (LPw)
X
X
X
X
0
1
Speed grade 1
Speed grade 2
Table 3-20 Driver Mode Selection for MP / MP+ Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Strong sharp edge (MPss / MP+ss)
Strong medium edge (MPsm / MP+sm)
medium (MPm / MP+m)
weak (MPw / MP+w)
Table 3-21 Driver Mode Selection for A2 Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
Strong sharp edge
Strong medium edge
medium
X
X
X
X
0
0
1
1
0
1
0
1
weak
Table 3-22 Driver Mode Selection for F Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Reduced Strong sharp edge
Reduced Strong medium edge
medium
weak
Data Sheet
3-344
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
3.6
High performance LVDS Pads (LVDSH)
This LVDS pad type is used for the high speed chip to chip communication inferface of the new TC290 / TC297 /
TC298 / TC299. It compose out of a LVDSH pad and a Class F pad.
This pad combination is always supplied by the 3.3V supply rail.
Table 3-23 Class F
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
75
-
Input frequency
Input Hysteresis for F pad 1)
fIN SR
-
-
-
MHz
V
HYSF CC 0.1 *
TTL
VDDP3
Input Leakage Current for F
pad
I
OZF CC
-1000
-
-
nA
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.0, P21.1, P21.2
and P21.3; TJ = 150°C
-
-
1000
nA
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.0, P21.1, P21.2
and P21.3; TJ =
150°C
-1500
-
1500
nA
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.0, P21.1, P21.2
and P21.3; TJ =
170°C
-300
-
-
-
-
-
-
300
2000
-
nA
nA
nA
nA
nA
(0.1*VDDP3) < VIN <
(0.9*VDDP3); valid for
P21.4 and P21.5
else; valid for P21.0,
P21.1, P21.2 and
P21.3; TJ = 150°C
-2000
-3000
-600
else; valid for P21.0,
P21.1, P21.2 and
P21.3; TJ = 150°C
3000
600
else; valid for P21.0,
P21.1, P21.2 and
P21.3; TJ = 170°C
else; valid for P21.4
and P21.5
Pull-up current for F pad
I
I
PUHF CC
PDLF CC
|25|
-
-
-
µA
VIHmin
-
|100|
|100|
-
µA
VILmax
Pull-down current for class F
pads
-
-
µA
VIHmin
|25|
100
-
µA
VILmax
On resistance for F pad, weak RDSONFW
200
325
Ohm
PMOS/NMOS ;
driver 2)
CC
I
OH=0.5mA; IOL=0.5mA
Data Sheet
3-345
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-23 Class F (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On resistance for F pad,
medium driver 2)
RDSONFM
CC
40
70
50
-
100
Ohm
Ohm
PMOS/NMOS ;
I
OH=2mA; IOL=2mA
On resistance for F pad, strong RDSONFS CC 20
80
PMOS/NMOS ;
driver 2)
I
OH=4mA; IOL=4mA
Rise/fall time for F pad 3)
t
rfF CC
-
-
-
-
-
20+0.8*C ns
CL≤50pF; pin out
driver=weak
L
-
17.5+0.85 ns
*CL
CL≥50pF; CL≤200pF;
pin out driver=weak
-
12+0.16* ns
CL
CL≤50pF; pin out
driver=medium
-
11.5+0.17 ns
*CL
CL≥50pF; CL≤200pF;
pin out driver=medium
-
7+0.16*C ns
CL≤50pF;
edge=medium ; pin out
L
driver=reduced strong
-
-
-
-
-
-
6.5+0.17* ns
CL
CL≥50pF; CL≤200pF;
edge=meduim ; pin out
driver>reduced strong
4+0.16*C ns
CL≤50pF; edge=sharp
; pin out
driver=reduced strong
L
3.5+0.17* ns
CL
CL≥50pF; CL≤200pF;
edge=sharp ; pin out
driver=reduced strong
Input high voltage for F pad
Input low voltage for F pad
Pad set-up time for F pad
V
V
IHF SR
ILF SR
2.04 4)
-
-
-
-
-
V
TTL
TTL
-
-
-
0.8 5)
100
20
V
t
SETF CC
ns
%
Deviation of symmetry for rising SYM CC
and falling edges
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.
3) Rise / fall times are defined 10% - 90% of VDDP3
4) VIHx = 0.57 * VDDP3 - 0.03V
.
5) VILx = 0.25 * VDDP3 + 0.058V
CL = 2.5 pF for all LVDSH parameters.
Data Sheet
3-346
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
0.5
Output impedance
Rise time 1)
R0 CC
-
-
Ohm
ns
Vcm = 1.0 V and 1.4 V
t
rise20 CC
ZL = 100 Ohm ±5%
@2 pF
Fall time 1)
t
fall20 CC
-
-
0.5
ns
ZL = 100 Ohm ±5% @
2 pF
Output differential voltage
Output voltage high
V
V
OD CC
OH CC
250
-
-
-
400
mV
mV
RT = 100 Ohm ±5%
1475
RT = 100 Ohm ±5%
(400 mV/2) + 1275 mV
Output voltage low
V
OL CC
925
-
-
-
mV
mV
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
Output offset (Common mode) VOS CC
1125
1275
voltage
Input voltage range
VI SR
0
0
-
-
1600
2000
mV
mV
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±10%
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±20%
Input differential threshold
Delta output impedance
V
idth SR
-100
-
-
-
-
-
100
10
25
25
55
mV
%
Driver ground potential
difference < 925 mV
dR0 SR
-
Vcm = 1.0 V and 1.4 V
(mismatch Pd and Pn)
Change in VOS between 0 and dVOS CC
1
-
mV
mV
%
RT = 100 Ohm ±5%
Change in Vod between 0 and dVod CC
1
-
RT = 100 Ohm ±5%
Duty cycle
t
duty CC
45
1) Rise / fall times are defined for 20% - 80% of VOD
Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
140
250
1375
-
Output impedance
R0 CC
-
-
-
-
-
Ohm
mV
mV
mV
mV
Vcm = 1.0 V and 1.4 V
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
RT = 100 Ohm ±5%
Output differential voltage
Output voltage high
Output voltage low
V
V
V
OD CC
OH CC
OL CC
150
-
1025
1125
Output offset (Common mode) VOS CC
1275
voltage
Input voltage range
VI SR
825
-
1575
mV
Driver ground potential
difference < 50 mV
Data Sheet
3-347
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHigh performance LVDS Pads (LVDSH)
Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input differential threshold
V
idth SR
-100
-
-
-
100
mV
mV
mV
Driver ground potential
difference < 50 mV
Change in VOS between 0 and dVOS CC
1
-
-
25
25
RT = 100 Ohm ±5%
Change in Vod between 0 and dVod CC
RT = 100 Ohm ±5%
1
Duty cycle
t
t
duty CC
45
-
-
-
55
%
1)
VOD Fall time
fall10 CC
0.5
ns
ZL = 100 Ohm ±5% @
2pF
1)
VOD Rise time
t
rise10 CC
-
-
0.5
ns
ZL = 100 Ohm ±5% @
2pF
1) Rise / fall times are defined for 10% - 90% of VOD
default after start-up = CMOS function
P
Htotal=5nH
Ctotal=3.5pF
Cext=2pF
LVDSH
Rin
IN
RT=100Ohm
Htotal=5nH
Cext=2pF
N
Ctotal=3.5pF
LVDSH _Input _Pad _Model .vsd
Figure 3-1 LVDSH pad Input model
Data Sheet
3-348
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMedium performance LVDS Pads (LVDSM)
3.7
Medium performance LVDS Pads (LVDSM)
This LVDS pad type is used for the medium speed chip to chip communication inferface of the new TC290 / TC297
/ TC298 / TC299. It compose out of a LVDSM pad and a MP pad.
This pad combination is always supplied by the 5V or 3.3V.
For the parameters of the MP pad please see Chapter 3.5.
Table 3-26 LVDSM
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
2.5
Output impedance
Fall time
RO CC
tF CC
100
-
Ohm
ns
Zload = 100 Ohm;
termination 100 Ohm
±1%
Rise time
tR CC
-
-
2.5
ns
Zload = 100 Ohm;
termination 100 Ohm
±1%
Pad set-up time
tSET_LVDS
CC
-
10
-
13
µs
Output Differential Voltage
Output voltage high
Output voltage low
Output Offset Voltage
V
V
V
V
OD CC
OH CC
OL CC
OS CC
250
-
400
1475
-
mV
mV
mV
mV
termination 100 Ohm
±1%
-
termination 100 Ohm
±1%
925
1125
-
termination 100 Ohm
±1%
-
1275
termination 100 Ohm
±1%
default after start-up = CMOS function
Data Sheet
3-349
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationVADC Parameters
3.8
VADC Parameters
VADC parameter are valid for VDDM = 4.5 V to 5.5 V.
This table also covers the parameters for Class D pads.
Table 3-27 VADC
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Analog reference voltage 1)
Analog reference ground
V
V
V
AREF SR
VAGND
1.0
+
-
VDDM
0.05
+
+
V
V
AGND SR VSSM
-
-
VSSM
0.05
0.05
Analog input voltage range
Converter reference clock
AIN SR
VAGND
-
VAREF
20
V
f
ADCI SR
CONV CC
2
-
-
MHz
pC
Charge consumption per
conversion 2) 3)
Q
50
75
VAIN = 5 V, charge
consumed from
reference pin,
precharging disabled
-
-
-
-
-
10
22
-
pC
VAIN = 5 V, charge
consumed from
reference pin,
precharging enabled
Conversion time for 12-bit
result
t
t
C12 CC
(16 +
Includes sample time
and post calibration
STC) x
tADCI + 2 x
tVADC
Conversion time for 10-bit
result
C10 CC
(14 +
-
Includes sample time
Includes sample time
Includes sample time
STC) x
tADCI + 2 x
tVADC
Conversion time for 8-bit result tC8 CC
(12 +
-
STC) x
tADCI + 2 x
tVADC
Conversion time for fast
compare mode
t
CF CC
(4 + STC) -
x tADCI + 2
x tVADC
Broken wire detection delay
against VAGND
t
t
BWG CC
BWR CC
-
-
-
-
120
cycles Result below 10%
cycles Result above 80%
4)
Broken wire detection delay
-
60
5)
against VAREF
Input leakage at analog inputs IOZ1 CC
-350
350
nA
Analog Inputs overlaid
with class LP pads or
pull down diagnostics
-150
-4 6)
-
-
150
4 6)
nA
else
Total Unadjusted Error 1)
Data Sheet
TUE CC
LSB
12-bit resolution
3-350
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationVADC Parameters
Table 3-27 VADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
3
INL Error
EAINL CC
-3
-
-
-
-
-
LSB
LSB
LSB
LSB
pF
12-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
Gain Error 1)
DNL error 1)
Offset Error 1)
EAGAIN CC -3.5
EADNL CC -3
EAOFF CC -4
3.5
3
4
Total capacitance of an analog CAINT CC
-
30
input
Switched capacitance of an
analog input
CAINS CC
2
4
7
pF
Resistance of the analog input RAIN CC
path
-
-
-
-
1.5
1.8
kOhm else
kOhm valid for analog inputs
mapped to GPIOs
Switched capacitance of a
reference input
CAREFS CC
-
-
30
pF
RMS Noise 7)
ENRMS CC
OZ2 CC
-
0.5
-
0.8 6)8)
7
LSB
Positive reference VAREFx pin
I
-7
µA
µA
µA
µA
µA
µA
µA
µA
V
V
AREFx = VAREF2
AREF>VDDMV;
;
;
;
;
leakage
TJ>150°C
-4
-
-
-
-
-
-
-
4
V
V
AREFx = VAREF2
AREF>VDDMV;
TJ≤150°C
-2
3
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ>150°C
-1
1
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ≤150°C
Negative reference VAGNDx pin IOZ3 CC
leakage
-13
-7
13
7
V
V
AGNDx = VAGND2
AGND<VSSMV;
;
;
;
;
TJ>150°C
V
V
AGNDx = VAGND2
AGND<VSSMV;
TJ≤150°C
-4.5
-2.5
2.5
1
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ>150°C
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ≤150°C
Resistance of the reference
input path
CSD resistance 9)
R
R
AREF CC
CSD CC
-
-
-
-
1
kOhm
kOhm
28
Data Sheet
3-351
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationVADC Parameters
Table 3-27 VADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
35 - 8*VIN kOhm 0 V ≤ VIN ≤ 2.5 V
Resistance of the multiplexer
diagnostics pull-down device
R
R
R
MDD CC
MDU CC
PDD CC
25 + 1*VIN
-
-
-5 +
13*VIN
15 +
16*VIN
kOhm 2.5 V ≤ VIN ≤ VDDM
Resistance of the multiplexer
diagnostics pull-up device
45 - 6*VIN
-
90 -
16*VIN
kOhm 0 V ≥ VIN ≤ 2.5 V
40 - 4*VIN
-
-
65 - 6*VIN kOhm 2.5 V ≤ VIN ≤ VDDM
Resistance of the pull-down
test device 10)
-
0.3
kOhm
CSD voltage accuracy 11) 12)
dVCSD CC -
WU CC
-
-
10
12
%
Wakeup time
t
-
µs
1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor
1/k. VAREF must be decoupled with an external capacitor.
2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx
.
3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual.
4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 500 ms.
5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.
6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
7) This parameter is valid for soldered devices and requires careful analog board design.
8) Value is defined for one sigma Gauss distribution.
9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS
.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad
itself adds another 200-Ohm series resistance, when measuring through the pin.
11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.
12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current
of max. VAREF / 45 kOhm.
The following VADC parameter are valid for VDDM = 2.97 V to 4.5 V.
This table also covers the parameters for Class D pads.
Table 3-28 VADC_33V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Analog reference voltage 1)
Analog reference ground
V
V
V
AREF SR
VAGND
1.0
+
-
VDDM
0.05
+
+
V
V
AGND SR VSSM
-
-
VSSM
0.05
0.05
Analog input voltage range
Converter reference clock
AIN SR
VAGND
-
-
VAREF
V
f
ADCI SR
2
20
MHz
Data Sheet
3-352
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Charge consumption per
conversion 2) 3)
QCONV CC
-
35
50
pC
VAIN = 3.3 V, charge
consumed from
reference pin,
precharging disabled
-
-
-
-
-
8
17
-
pC
VAIN = 3.3 V, charge
consumed from
reference pin,
precharging enabled
Conversion time for 12-bit
result
t
t
C12 CC
(16 +
Includes sample time
and post calibration
STC) x
tADCI + 2 x
tVADC
Conversion time for 10-bit
result
C10 CC
(14 +
-
Includes sample time
Includes sample time
Includes sample time
STC) x
tADCI + 2 x
tVADC
Conversion time for 8-bit result tC8 CC
(12 +
-
STC) x
tADCI + 2 x
tVADC
Conversion time for fast
compare mode
t
CF CC
(4 + STC) -
x tADCI + 2
x tVADC
Broken wire detection delay
against VAGND
t
t
BWG CC
BWR CC
-
-
-
-
120
cycles Result below 10%
cycles Result above 80%
4)
Broken wire detection delay
-
60
5)
against VAREF
Input leakage at analog inputs IOZ1 CC
-350
350
nA
Analog Inputs overlaid
with class LP pads or
pull down diagnostics
-150
-12 6)
-
-
150
12 6)
nA
else
Total Unadjusted Error 1)
TUE CC
EAINL CC
LSB
12-bit Resolution; TJ >
150 °C
-6 6)
-12
-5
-
-
-
-
-
6 6)
12
5
LSB
LSB
LSB
LSB
LSB
12-bit Resolution; TJ ≤
150 °C
INL Error
12-bit Resolution; TJ >
150 °C
12-bit Resolution; TJ ≤
150 °C
Gain Error 1)
EAGAIN CC -6
-5.5
6
12-bit Resolution; TJ >
150 °C
5.5
12-bit Resolution; TJ ≤
150 °C
Data Sheet
3-353
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DNL error 1)
Offset Error 1)
EADNL CC -4
EAOFF CC -6
-
-
4
6
LSB
LSB
12-bit resolution
12-bit Resolution; TJ >
150 °C
-5
-
5
LSB
pF
12-bit Resolution; TJ ≤
150 °C
Total capacitance of an analog CAINT CC
input
-
-
30
7
Switched capacitance of an
analog input
CAINS CC
2
-
4
-
pF
Resistance of the analog input RAIN CC
path
4.5
30
kOhm
pF
Switched capacitance of a
reference input
CAREFS CC
-
-
RMS Noise 7)
ENRMS CC
OZ2 CC
-
-
-
1.7 6)8)
6
LSB
µA
target
Positive reference VAREFx pin
leakage
I
-6
V
V
AREFx = VAREF2
AREF>VDDMV;
;
;
;
;
TJ>150°C
-3.5
-2
-
-
-
-
-
-
-
3.5
2.5
1
µA
µA
µA
µA
µA
µA
µA
V
V
AREFx = VAREF2
AREF>VDDMV;
TJ≤150°C
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ>150°C
-1
V
V
AREFx = VAREF2
AREF≤VDDMV;
TJ≤150°C
Negative reference VAGNDx pin IOZ3 CC
leakage
-12
-6.5
-2.2
-1
12
6.5
2
V
V
AGNDx = VAGND2
AGND<VSSMV;
;
;
;
;
TJ>150°C
V
V
AGNDx = VAGND2
AGND<VSSMV;
TJ≤150°C
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ>150°C
1
V
V
AGNDx = VAGND2
AREF≤VDDMV;
TJ≤150°C
Resistance of the reference
input path
CSD resistance 9)
R
R
AREF CC
CSD CC
-
-
-
-
3
kOhm
kOhm
28
Data Sheet
3-354
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationVADC Parameters
Table 3-28 VADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Resistance of the multiplexer
diagnostics pull-down device
R
MDD CC
25 + 3*VIN
-
40 +
12*VIN
kOhm 0 V ≤ VIN ≤ 1.667 V
0 + 18*VIN
-
-
0 + 18*VIN kOhm 1.667 V ≤ VIN ≤ VDDM
Resistance of the multiplexer
diagnostics pull-up device
R
R
MDU CC
60 -
12*VIN
120 -
kOhm 0 V ≤ VIN ≤ 1.667 V
kOhm 1.667 V ≤ VIN ≤ VDDM
kOhm
30*VIN
55 - 9*VIN
-
-
95 -
15*VIN
Resistance of the pull-down
test device 10)
PDD CC
-
0.9
CSD voltage accuracy 11) 12)
dVCSD CC -
WU CC
-
-
10
12
%
Wakeup time
t
-
µs
1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor
1/k. VAREF must be decoupled with an external capacitor.
2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx
.
3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual.
4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 500 ms.
5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.
6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
7) This parameter is valid for soldered devices and requires careful analog board design.
8) Value is defined for one sigma Gauss distribution.
9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS
.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad
itself adds another 200-Ohm series resistance, when measuring through the pin.
11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.
12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current
of max. VAREF / 45 kOhm.
A/D Converter
RSource
RAIN, On
VAIN
-
CExt
CAINT CAINS
CAINS
MCS05570
Figure 3-2 Equivalent Circuitry for Analog Inputs
Data Sheet
3-355
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDSADC Parameters
3.9
DSADC Parameters
The following DSADC parameter are valid for VDDM = 4.5 V to 5.5 V.
Table 3-29 DSADC
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
5
Analog input voltage range 1)
V
DSIN SR
0
0
-
-
V
V
single ended
10
differential;VDSxP -
VDSxN
Reference load current
I
REF SR
-
4.5
5.5
µA
per twin-modulator (1
or 2 channels)
Modulator clock frequency 2)
Gain error
f
MOD SR
10
-
-
-
-
20
1 3)
3.5 4)
0.2 5)
MHz
%
EDGAIN CC -1
-3.5 4)
-0.2
Calibrated once
Uncalibrated
%
%
calibrated; GAIN = 1;
MODCFG.INCFGx=01
DC offset error
EDOFF CC -5
-
5 5)
50
100 4)
mV
mV
mV
calibrated
-50
-100 4)
-
calibrated once
gain = 1; uncalibrated
04)
500
130
Common Mode Rejection Ratio EDCM CC
Input impedance 6)
200
-
R
DAIN CC
100
170
kOhm Exact value (±1%)
available in UCB
Signal-Noise Ratio 7) 8) 9) 10)
SNR CC
80
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
kHz
fPB = 30 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
78
-
fPB = 50 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
70
-
fPB = 100 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
74
-
fPB = 100 kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
76
-
fPB = 30 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
74
-
fPB = 50 kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
Pass band
f
PB CC
10 11)
100
Output data rate fD =
f
PB * 3
Pass band ripple 8)
dfPB CC
fD CC
-1
-
-
1
%
Output sampling rate
30
330
kHz
Data Sheet
3-356
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDSADC Parameters
Table 3-29 DSADC (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-3
Max.
DC compensation factor
DCF CC
-
-
-
dB
µA
10-5 fD
Positive reference VAREF1 pin
I
OZ5 CC
-2
2
leakage
Negative reference VAGND1 pin IOZ6 CC
-3
-
2
µA
leakage
Stop band attenuation 8)
SBA CC
40
45
50
55
60
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
V
0.5 ... 1 fD
1 ... 1.5 fD
1.5 ... 2 fD
2 ... 2.5 fD
2.5 ... OSR/2 fD
Reference ground voltage
Positive reference voltage
V
V
AGND SR VSSM
-
VSSM
0.05
+
+
0.05
AREF SR
V
DDMnom * -
VDDM
V
0.9
0.05
Common mode voltage
accuracy
dVCM CC
-100
-
-
100
200
mV
mV
from selected voltage
Common mode hold voltage
deviation 12)
dVCMH CC -200
From common mode
voltage
Analog filter settling time
Modulator recovery time
t
t
AFSET CC
MREC CC
-
-
2
4
µs
µs
If enabled
3.5
5.5
After leaving overdrive
state
Modulator settling time 13)
t
MSET CC
-
1
-
-
-
µs
After switching on,
voltage regulator
already running
Spurious Free Dynamic Range SFDR CC 60
dB
V
CM = 2.2 V, DC
7)14)
coupled; VDDM = ±10%
1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external
common mode voltage. In this case the Amplitude is limited to VCM * 2.
2) All modulators must run on the same frequency.
3) The calibration sequence must be executed once after an Application Reset
4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF
5) Recalibration needed in case of a temperature change > 20ºC
6) The variation of the impedance between different channels is < 1.5%.
7) Derating factors:
-2 dB in standard-performance mode.
-3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
8) CIC3, FIR0, FIR1 filters enabled.
9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM
(GAIN = 2).
10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM
.
11) 10 kHz only reachable with 10 MHz modulator clock frequency.
12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM
.
13) The modulator needs to settle after being switched on and after leaving the overdrive state.
14) SFDR = 20 * log(INL / 2N); N = amount of bits
Data Sheet
3-357
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDSADC Parameters
The following DSADC parameter are valid for VDDM = 2.97 V to 4.5 V.
Table 3-30 DSADC_33V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
3.3
Analog input voltage range 1)
V
DSIN SR
0
0
-
-
V
V
single ended
6.6
differential;VDSxP -
VDSxN
Reference load current
I
REF SR
-
4.5
5.5
µA
per twin-modulator (1
or 2 channels)
Modulator clock frequency 2)
Gain error
f
MOD SR
10
-
-
-
-
20
MHz
%
EDGAIN CC -1.5
-10 4)
-0.3
1.5 3)
10 4)
0.3 5)
Calibrated once
Uncalibrated
%
%
calibrated; GAIN = 1;
MODCFG.INCFGx=01
DC offset error
EDOFF CC -5
-
5 5)
50
100 4)
mV
mV
mV
calibrated
-50
-100 4)
-
calibrated once
gain = 1; uncalibrated
04)
500
130
Common Mode Rejection Ratio EDCM CC
Input impedance 6)
200
-
R
DAIN CC
100
170
kOhm Exact value (±1%)
available in UCB
Signal-Noise Ratio 7) 8) 9) 10)
SNR CC
45
63
69
68
74
66
72
-
-
dB
dB
dB
dB
dB
dB
kHz
fPB = 100kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
60
-
fPB = 100kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
60
-
fPB = 30kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
69
-
fPB = 30kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
55
-
fPB = 50kHz; VDDM =
±10%; fMOD = 20 MHz;
GAIN = 1
65
-
fPB = 50kHz; VDDM =
±5%; fMOD = 20 MHz;
GAIN = 1
Pass band
f
PB CC
10 11)
100
Output data rate fD =
f
PB * 3
Pass band ripple 8)
dfPB CC
fD CC
-1
30
-3
-
-
-
1
%
Output sampling rate
DC compensation factor
330
-
kHz
dB
DCF CC
10-5 fD
Data Sheet
3-358
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDSADC Parameters
Table 3-30 DSADC_33V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Positive reference VAREF1 pin
leakage
I
OZ5 CC
-2
-
2
µA
µA
Negative reference VAGND1 pin IOZ6 CC
-3
-
2
leakage
Stop band attenuation 8)
SBA CC
40
45
50
55
60
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
V
0.5 ... 1 fD
1 ... 1.5 fD
1.5 ... 2 fD
2 ... 2.5 fD
2.5 ... OSR/2 fD
Reference ground voltage
Positive reference voltage
V
V
AGND SR VSSM
-
VSSM
0.05
+
+
0.05
AREF SR
V
DDMnom * -
VDDM
V
0.9
0.05
Common mode voltage
accuracy
dVCM CC
-100
-
-
100
200
mV
mV
from selected voltage
Common mode hold voltage
deviation 12)
dVCMH CC -200
From common mode
voltage
Analog filter settling time
Modulator recovery time
t
t
AFSET CC
MREC CC
-
-
2
4
-
µs
µs
If enabled
3.5
After leaving overdrive
state
Modulator settling time 13)
t
MSET CC
-
1
-
µs
After switching on,
voltage regulator
already running
Spurious Free Dynamic Range SFDR CC 52
-
-
-
-
dB
dB
V
CM = 2.2 V, DC
coupled; VDDM = ±10%
CM = 2.2 V, DC
coupled; VDDM = ±5%
7)14)
60
V
1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external
common mode voltage. In this case the Amplitude is limited to VCM * 2.
2) All modulators must run on the same frequency.
3) The calibration sequence must be executed once after an Application Reset
4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF
5) Recalibration needed in case of a temperature change > 20ºC.
6) The variation of the impedance between different channels is < 1.5%.
7) Derating factors:
-2 dB in standard-performance mode.
-3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
8) CIC3, FIR0, FIR1 filters enabled.
9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM
(GAIN = 2).
10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM
.
11) 10 kHz bandwidth only with 10Mhz modulator clock frequency reachable
12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM
.
13) The modulator needs to settle after being switched on and after leaving the overdrive state.
Data Sheet
3-359
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDSADC Parameters
14) SFDR = 20 * log(INL / 2N); N = amount of bits
VCM
Gain
VOFFSET
130 kΩ
130 kΩ
=
Modu-
lator
Gain
MC_DSADC_MODULATORBLOCK
Figure 3-3 DSADC Analog Inputs
Data Sheet
3-360
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMHz Oscillator
3.10
MHz Oscillator
OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 8 MHz to 40 MHz crystals external
outside of the device. Support of ceramic resonators is also provided.
Table 3-31 OSC_XTAL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-25
4
Max.
25
Input current at XTAL1
Oscillator frequency
I
IX1 CC
-
-
µA
VIN>0V; VIN<VDDP3V
f
OSC SR
40
MHz
Direct Input Mode
selected
8
-
40
MHz
External Crystal Mode
selected
Oscillator start-up time 1)
t
OSCS CC
-
-
-
5 2)
ms
V
Input high voltage at XTAL1
V
IHBX SR
0.8
VDDP3
+
If shaper is bypassed
If shaper is bypassed
0.5
Input low voltage at XTAL1
Input voltage at XTAL1
V
ILBX SR
-0.5
-0.5
-
-
0.4
V
V
VIX SR
VDDP3
0.5
+
+
If shaper is not
bypassed
Input amplitude (peak to peak) VPPX SR
at XTAL1
0.3 *
VDDP3
-
-
VDDP3
1.0
V
V
If shaper is not
bypassed; fOSC
>
25MHz
0.4 *
VDDP3
VDDP3
1.0
+
If shaper is not
bypassed; fOSC
25MHz
≤
Internal load capacitor
Internal load capacitor
Internal load capacitor
Internal load capacitor
CL0 CC
CL1 CC
CL2 CC
CL3 CC
2
2.35
2.35
3.5
2.7
2.7
4
pF
pF
pF
pF
2
3
5.1
5.9
6.6
1) tOSCS is defined from the moment when VDDP3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDP3
.
The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended
and specified by crystal suppliers.
2) This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.
Note:It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
Data Sheet
3-361
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationBack-up Clock
3.11
Back-up Clock
The back-up clock provides an alternative clock source.
Table 3-32 Back-up Clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Back-up clock before trimming fBACKUT CC 75
Max.
125
100
100
100
MHz
kHz
V
V
V
EXT≥2.97V
EXT≥2.97V
EXT≥2.97V
Slow speed Back-up clock
Back-up clock after trimming
f
f
BACKSS CC 75
BACKT CC 97.5
125
102.5
MHz
Data Sheet
3-362
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationTemperature Sensor
3.12
Temperature Sensor
Table 3-33 DTS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
100
1
Measurement time
tM CC
-
-
-
µs
°C
Calibration reference accuracy TCALACC CC -1
calibration points @
TJ=-40°C and
TJ=127°C
Non-linearity accuracy over
temperature range
T
T
NL CC
SR SR
-2
-
2
°C
Temperature sensor range
-40
-
-
-
170
20
°C
µs
Start-up time after resets
inactive
tTSST SR
The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the
DTSSTAT register.
(3.1)
DTSSTATRESULT – (607)
Tj = ---------------------------------------------------------------------------
2, 13
Data Sheet
3-363
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current
3.13
Power Supply Current
The total power supply current defined below consists of leakage and switching component.
Application relevant values are typically lower than those given in the following table and depend on the customer's
system operating conditions (e.g. thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
The real (realisic) power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
CPU0 = 200 MHz
SRI = fMAX = fCPU1 = fCPU2 300 MHz
SPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 50 MHz
V
V
V
DD = 1.326 V
DDP3 = 3.366 V
EXT / FLEX = VDDM = 5.1 V
all cores are active including one lockstep core
the following peripherals are inactive: EBU, HSM, HSCT, Ethernet, PSI5, I2C, FCE, MTU, and 50% of the
DSADC channels
The max power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
CPU0 = 200 MHz
SRI = fMAX = fCPU1 = fCPU2 300 MHz
SPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 100 MHz
V
V
V
DD = 1.43 V
DDP3 = 3.63 V
EXT / FLEX = VDDM = 5.5 V
all cores and lockstep cores are active
all peripherals are active
Data Sheet
3-364
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of IDD 1.3 V core and
peripheral supply currents
I
DD CC
-
-
750
mA
max power pattern
with fSRI/CPUx = 270
MHz with VDD = 1.3V +
10%; valid for Feature
Package T, TP, and
TC products
-
-
800
mA
max power pattern
with fSRI/CPUx = 300
MHz with VDD = 1.33V
+ 7.5%. valid for
Feature Package T,
TP, and TC products
-
-
-
-
-
-
-
-
950
930
567
637
mA
mA
mA
mA
max power pattern.
valid for Feature
Package TA and TB
products
max power pattern.
valid for Feature
Package TX and TY
products
real power pattern.
valid for Feature
Package T, TP, and
TC products
real power pattern.
valid for Feature
Package TA, TB, TX
and TY products
Data Sheet
3-365
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DD core current during active IDDPORST
-
-
-
-
-
-
-
-
140
mA
valid for Feature
Package T, TP, and
TC products;
power-on reset (PORST held CC
low)
TJ=125°C
-
-
-
-
-
-
220
176
310
290
405
62
mA
mA
mA
mA
mA
mA
valid for Feature
Package T, TP, and
TC products;
TJ=150°C
valid for Feature
Package TA, TB, TX,
and TY products;
TJ=125°C
valid for Feature
Package T, TP, and
TC products;
TJ=165°C
valid for Feature
Package TA, TB, TX,
and TY products;
TJ=150°C
valid for Feature
Package TA, TB, TX,
and TY products;
TJ=165°C
I
DD core current of CPU1 main IDDC10 CC
real power pattern
core with CPU1 lockstep core
inactive
I
DD core current of CPU1 main IDDC11 CC
core with lockstep core active
DD core current of CPU2 main IDDC20 CC
core
-
-
-
-
-
-
IDDC10
48
+
mA
mA
mA
real power pattern
real power pattern
I
60
20
I
DD core current added by HSM IDDHSM CC
HSM running at
100MHz.
I
I
DD core current added by AMU IDDAMU CC
DD core current added by FFT IDDFFT CC
-
-
-
-
48
40
mA
mA
real power pattern
FFT running at
200MHz
∑ Sum of 3.3 V supply currents IDDx3RAIL CC -
-
104 1)
mA
real power pattern
without pad activity
I
DDFL3 Flash memory current
I
DDFL3 CC
-
-
-
-
84 2)
84 3)
mA
mA
flash read current
flash read current
while programming
Dflash
Data Sheet
3-366
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DDP3 supply current without
I
DDP3 CC
-
-
29 2)
mA
real power pattern;
incl. OSC & flash read
current
pad activity
-
-
-
-
46 3)
46 4)
mA
mA
incl. OSC and flash
programming current
incl. OSC current and
flash 3.3V
programming current
when using external
5V supply
I
DDP3 supply current for LVDSH IDDP3LVDSH
-
-
-
16
98
mA
mA
pads in LVDS mode
CC
Σ Sum of external and ADC
I
EXTRAIL CC -
real power pattern
supply currents (incl.
I
EXTFLEX+IDDM+IEXTLVDSM)
Sum of IEXT and IFLEX supply
current without pad activity
I
EXT/FLEX CC -
-
16
mA
real power pattern;
PORST output
inactive.
I
EXT supply current for LVDSM IEXTLVDSM
pads in LVDS mode CC
DDM supply current DDM CC
-
-
-
-
20 5)
62
mA
mA
real power pattern
I
I
real power pattern;
sum of currents of
DSADC and VADC
modules
-
-
-
-
52
mA
mA
current for DSADC
module only; 50%
DSADC channels
active.
100 6)
max power pattern; All
DSADC channels
active 100% time.
-
-
-
-
10
mA
mA
real pattern; current for
VADC only
20 7)
max power pattern; All
VADC converters are
active 100% time
Σ Sum of all currents (incl.
EXTRAIL+IDDx3RAIL+IDD)
I
DDTOT CC
-
-
-
-
770
840
mA
mA
real power pattern;
valid for Feature
Package T, TP, and
TC products
I
real power pattern;
valid for Feature
Package TA, TB, TX,
and TY products
Data Sheet
3-367
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current
Table 3-34 Power Supply (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Σ Sum of all currents with DC- IDDTOTDC3
-
-
-
-
460
mA
mA
µA
real power pattern;
8)
DC EVR13 regulator active
CC
V
EXT = 3.3V
real power pattern;
EXT = 5V
Σ Sum of all currents with DC- IDDTOTDC5
-
-
370
8)
DC EVR13 regulator active
CC
V
∑ Sum of all currents
I
EVRSB CC
150 9)
Standby RAM is
active. Power to
remaining domains
switched off. TJ =
25°C; VEVRSB = 5V
(STANDBY mode)
∑ Sum of all currents (SLEEP
mode)
I
SLEEP CC
-
-
-
-
24
26
mA
mA
All CPUs in idle, All
peripherals in sleep,
f
SRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C; valid for Feature
Package T, TP, and
TC products
All CPUs in idle, All
peripherals in sleep,
f
SRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C; valid for Feature
Package TA, TB, TX,
and TY products
Maximum power dissipation
PD CC
-
-
-
-
-
-
-
-
-
-
2382
2140
2350
1600
1700
mW
mW
mW
mW
mW
max power pattern ;
valid for Feature
Package TA and TB
products
max power pattern.
valid for Feature
Package T, TP, and
TC products
max power pattern.
valid for Feature
Package TX and TY
products
real power pattern.
valid for Feature
Package T, TP, and
TC products
real power pattern.
valid for Feature
Package TA, TB, TX,
and TY products
1) In case EVR33 is not used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited
to 500 mA if during power sequencing 3.3V is supplied before 5V by external regulator.
Data Sheet
3-368
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current
2) Realistic Pflash read pattern with 70% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common
decoupling capacitor of atleast 100nF for (VDDFL3+VDDP3) is used. Dflash read current is also included. Flash read current
is predominantly drawn from VDDFL3 pin and a minor part drawn from the neighbouring VDDP3 pin.
3) Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Erase currents
of the corresponding flash modules are less than the respective programming currents at VDDP3 pin. Programming and
erasing flash may generate transient current spikes of up to x mA for maximum x us which is handled by the decoupling
and buffer capacitors. This parameter is relevant for external power supply dimensioning and not for thermal
considerations.
4) In addition to the current specified, upto 4 mA is additionally drawn at VEXT supply in burst programming mode with 5V
external supply. Erase currents of the corresponding flash modules are less than the respective programming currents at
V
DDP3 supply. This parameter is relevant for external power supply dimensioning and not for thermal considerations.
5) The current consumption is for 2 pairs of LVDSM differential pads (8 pins). A single pair of LVDSM differential pads (4 pins)
consumes 7 mA.
6) The current consumption is for 6 DS channels with standard performance (MCFG=11b). A single DS channel instance
consumes 6-8 mA.
7) A single converter instance of VADC unit consumes 2 mA.
8) The total current drawn from external regulator is estimated with 72% EVR13 SMPS regulator Efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and
IDDM
.
9) Σ Sum of all currents during RUN mode at VEVRSB supply pin is less than (8 mA + ISCRSB) . It is recommended to have
atleast 100 nF decoupling capacitor at this pin.
3.13.1
Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts:
•
•
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic current consumption
depends of the configured clocking frequencies and the software application executed. These two parts needs to
be added in order to get the rail current consumption.
Valid for Feature Package T, TP, and TC products:
(3.2)
mA
0, 0289 × T
0, 0259 × T
--------
C
I
I
= 0, 894
= 4, 319
× e
× e
[C]
[C]
J
J
0
(3.3)
mA
--------
0
C
Valid for Feature Package TA, TB, TX, and TY products:
(3.4)
(3.5)
mA
0, 0244 × T
0, 0257 × T
--------
C
I
I
= 2, 731
= 5, 832
× e
× e
[C]
[C]
J
J
0
0
mA
--------
C
Data Sheet
3-369
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current
Function 2 / 4 defines the typical static current consumption and Function 3 / 5 defines the maximum static current
consumption. Both functions are valid for VDD = 1.326 V.
Data Sheet
3-370
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
3.14
Power-up and Power-down
External Supply Mode
3.14.1
5 V & 1.3 V supplies are externally supplied. 3.3V is generated internally by EVR33.
•
External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Voltage Ramp-up from a residual threshold (Eg : up to 1 V) should also lead to a normal
startup of the device.
•
The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-4 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supplies
ramp up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR33 regulator is initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR33 regulator
has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge.
Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset
thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
3-371
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
4
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
VDD (externally supplied )
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDDP3 (internally generated
by EVR33)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
Basic Supply & Clock
Infrastructure
EVR33 Ramp-up Phase
Firmware Execution
User Code Execution
fCPU=100MHz default
on firmware exit
Power Ramp-down phase
Startup_Diag_1 v 0.1
Figure 3-4 External Supply Mode - 5 V and 1.3 V externally supplied
Data Sheet
3-372
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
3.14.2
Single Supply Mode
5 V single supply mode. 1.3 V & 3.3 V are generated internally by EVR13 & EVR33.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-5 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR13 and EVR33 regulators are initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 and EVR33
regulators have ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST
rising edge. Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset
thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
3-373
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
4
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDD
(internally generated
by EVR13)
1. 33 V
1.30
V
1. 17 V
Primary Reset Threshold
0 V
VDDP3
(internally generated
by EVR33)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
EVR13 & EVR 33 Ramp-up
Basic Supply & Clock
Infrastructure
User Code Execution
Firmware Execution
Power Ramp-down phase
Phase
fCPU=100MHz default
on firmware exit
Startup_Diag_2 v 0.1
Figure 3-5 Single Supply Mode - 5 V single supply
Data Sheet
3-374
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
3.14.3
External Supply Mode
All supplies, namely 5 V, 3.3 V & 1.3 V, are externally supplied.
•
•
External supplies VEXT ,, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s).
The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-6 is enumerated below
–
T1 refers to the point in time when all supplies are above their primary reset thresholds and basic clock
infrastructure is available. The supply mode is evaluated based on the HWCFG [0:2] pins. PORST (output)
is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated.
–
–
T2 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T3 refers to the point in time during the Ramp-down phase when atleast one of the externally provided
supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
3-375
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
VEXT
(externally supplied )
0
1
2
3
5.5 V
5.0 V
4.5 V
2. 97 V
Primary Reset Threshold
0 V
VDD (externally supplied )
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
VDDP3
(externally supplied)
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
T0
T1
T2
T3
Basic Supply & Clock
Infrastructure
User Code Execution
fCPU=100 MHz default
on firmware exit
Firmware Execution
Power Ramp-down phase
Startup_Diag_3 v 0.1
Figure 3-6 External Supply Mode - 5 V, 3.3 V & 1.3 V externally supplied
Data Sheet
3-376
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
3.14.4
Single Supply Mode
3.3 V single supply mode. 1.3 V is generated internally by EVR13.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V or 3.3 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
The power sequence as shown in Figure 3-7 is enumerated below
–
T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR13 regulator is initiated.
–
T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 regulator
has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge.
Firmware execution is initiated.
–
–
T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V or 3.3 V) drop below their respective primary under-voltage reset thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
3-377
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
VEXT
0
1
2
3
4
(externally supplied )
&
VDDP3 (externally
supplied )
3. 63 V
3.30 V
2. 97 V
Primary Reset Threshold
0 V
PORST (output )
PORST (input)
VDD (internally generated
by EVR 13)
1. 33 V
1.30
1. 17 V
V
Primary Reset Threshold
0 V
T2
T0
T1
T3
T4
Basic Supply & Clock
Infrastructure
User Code Execution
fCPU=100MHz default
on firmware exit
EVR13 Ramp-up Phase
Firmware Execution
Power Ramp-down phase
Startup_Diag_4 v 0.1
Figure 3-7 Single Supply Mode - 3.3 V single supply
Data Sheet
3-378
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationReset Timing
3.15
Reset Timing
Table 3-35 Reset Timings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Application Reset Boot Time 1) tB CC
-
-
350 2)
µs
operating with max.
frequencies.
System Reset Boot Time
Power on Reset Boot Time 3)
t
t
BS CC
BP CC
-
-
-
-
1
ms
ms
2.5 2)
dV/dT=1V/ms.
including EVR ramp-
up and Firmware
execution time
-
-
-
1.11 2)
ms
µs
Firmware execution
time; without EVR
operation (external
supply only)
Minimum PORST hold time
incase of power fail event
issued by EVR primary monitor
t
EVRPOR CC 10
-
EVR start-up or ramp-up time tEVRstartup
-
-
-
1
-
ms
ms
dV/dT=1V/ms. EVR13
and EVR33 active
CC
Minimum PORST active hold
time after power supplies are
stable at operating levels 4)
t
POA CC
1
Configurable PORST digital
filter delay in addition to analog
pad filter delay
t
PORSTDF CC 600
-
1200
ns
HWCFG pins hold time from
ESR0 rising edge
t
t
HDH CC
HDS CC
16 / fSPB
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
HWCFG pins setup time to
ESR0 rising edge
0
-
Ports inactive after ESR0 reset tPI CC
active
-
8/fSPB
Ports inactive after PORST
reset active 5)
t
t
t
PIP CC
POH SR
POS SR
-
150
Hold time from PORST rising
edge
150
0
-
-
Setup time to PORST rising
edge
1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when
the first user instruction has entered the CPU pipeline and its processing starts.
2) The timing values assumes programmed BMI with ESR0CNT inactive.
3) The duration of the boot time is defined by all external supply voltages are inside there operation condictions and the clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
Data Sheet
3-379
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationReset Timing
4) The regulator that supplies VEXT should ensure that VEXT is in the operational region before PORST is externally released
by the regulator. Incase of 5V nominal supply, it should be ensured that VEXT > 4V before PORST is released. Incase of
3.3V nominal supply , it should be ensured that VEXT > 3V before PORST is released. The additional minimum PORST hold
time is required as an additional mechanism to avoid consecutive PORST toggling owing to slow supply slopes or residual
supply ramp-ups. It is also required to activate external PORST atleast 100us before power-fail is recognised to avoid
consecutive PORST toggling on a power fail event.
5) This parameter includes the delay of the analog spike filter in the PORST pad.
VDDPPA
VDDPPA
VDDP
VDD
VDDPR
tPOA
tPOA
Warm
PORST
ESR0
Cold
t PI
tPI
tPIP
Tristate Z / pullup H
Programmed
Z / H
Programmed
Z / H
Programmed
Pads
Pad-
state
undefined
Pad-
state
undefined
tPOS
tPOS
tPOH
tPOH
TRST
TESTMODE
tHDH
tHDH
config
tHDA
tHDH
config
tHDA
HWCFG
power -on config
reset_beh_aurix
Figure 3-8 Power, Pad and Reset Timing
Data Sheet
3-380
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEVR
3.16
EVR
Table 3-36 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-
Max.
5.50
5.50
3.63
3.63
Input voltage range 1)
VIN SR
-
V
V
V
V
pass device=off chip
pass device=on chip
pass device=off chip
pass device=on chip
4
-
Output voltage operational
range including load/line
regulation and aging incase of
LDO regulator
V
OUT CC
2.97
2.97
3.3
3.3
Output VDDx3 static voltage
accuracy after trimming and
aging without dynamic load/line
Regulation incase of LDO
regulator.
V
OUTT CC
3.225
3.225
3.3
3.3
3.375
3.375
V
V
pass device=off chip
pass device=on chip
Output buffer capacitance on
VOUT
C
OUT CC
-
-
-
2.2
2.2
-
-
µF
µF
V
pass device=off chip
pass device=on chip
2)
-
Primary Undervoltage Reset
V
RST33 CC
3.0
by reset release before
EVR trimming on
supply ramp-up.
3)
threshold for VDDx3
Startup time
t
STR CC
-
-
-
-
-
1000
1000
50
µs
µs
pass device=off chip
pass device=on chip
-
External VIN supply ramp 4)
Load step response
dVin/dT
SR
1
1
-
V/ms pass device=off chip
V/ms pass device=on chip
50
dVout/dIout -
CC
240
mV
mV
mV
mV
dI=-100mA;
Tsettle=20µs; pass
device=off chip
-
-
-
-
240
dI=-70mA/20ns;
Tsettle=20us; pass
device=on chip
-240
-
-
dI=100mA;
Tsettle=20µs; pass
device=off chip
-240
dI=50mA/20ns;
Tsettle=20us; pass
device=on chip
Line step response
dVout/dVin -20
CC
-
-
20
20
mV
mV
dV/dT=1V/ms; pass
device=off chip
-20
dV/dT=1V/ms; pass
device=on chip
1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device
operation.
Data Sheet
3-381
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEVR
2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the
resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
3) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold.
This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to
voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated
internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher
voltage of 3.0V at the VDDP3 pin.
4) EVR robust against residual voltage ramp-up starting between 0-1 V.
Table 3-37 1.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2.97
1.17
Max.
5.5
Input voltage range 1)
VIN SR
-
V
V
pass device=off chip
pass device=off chip
Output voltage operational
range including load/line
regulation and aging incase of
LDO regulator
V
V
OUT CC
1.3
1.43
Output VDD static voltage
accuracy after trimming without
dynamic load/line regulation
with aging incase of LDO
regulator.
OUTT CC
1.275
1.3
1.325
V
pass device=off chip
pass device=off chip
Output buffer capacitance on
COUT CC
3
-
4.7
-
6.3
µF
V
2)
VOUT
Primary undervoltage reset
threshold for VDD
V
RST13 CC
1.17
by reset release before
EVR trimming on
3)
supply ramp-up. pass
device=off chip
Startup time
External VIN supply ramp 4)
t
STR CC
-
-
-
1000
50
µs
pass device=off chip
dVin/dT
1
V/ms pass device=off chip
SR
Load step response
dVout/dIout -
CC
-
-
-
100
-
mV
mV
mV
dI=-150mA;
Tsettle=20µs; pass
device=off chip
-100
dI=100mA;
Tsettle=20µs; pass
device=off chip
Line step response
dVout/dVin -10
10
dV/dT=1V/ms; pass
CC
device=off chip
1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device
operation.
2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the
resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
3) The reset release on supply ramp-up is delayed by a time duration 30-60 µs after reaching undervoltage reset threshold.
This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to
voltage drop/current jumps when reset is released.The reset limit of 1,17V at pin is for the case with 1.3V generated
internally from EVR13. In case the 1.3V supply is provided externally, the bondwire drop will cause a reset at a higher
voltage of 1.18V at the VDD pin.
4) EVR robust against residual voltage ramp-up starting between 0-1 V.
Data Sheet
3-382
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEVR
Table 3-38 Supply Monitoring
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
EXT primary undervoltage
VEXTPRIUV
SR
2.86
2.92
2.90
1.15
5.0
2.97
V
V
EXT = Undervoltage
monitor accuracy after
trimming 1)
Reset Threshold
VDDP3 primary undervoltage
VDDP3PRIUV 2.86
SR
2.97
1.17
5.1
V
V
V
DDP3 = Undervoltage
monitor accuracy after
trimming
Reset Threshold
1)
VDD primary undervoltage
VDDPRIUV
SR
1.13
VDD = Undervoltage
Reset Threshold
monitor accuracy after
trimming
1)
VEXT secondary supply monitor VEXTMON CC 4.9
V
SWDxxVAL VEXT
monitoring
accuracy
threshold=5V=DAh
V
DDP3 secondary supply
VDDP3MON
CC
3.23
3.30
1.30
-
3.37
1.33
1.8
V
EVR33xxVAL VDDP3
monitoring
threshold=3.3V=90h
monitor accuracy
VDD secondary supply monitor VDDMON CC 1.27
V
EVR13xxVAL VDD
monitoring
threshold=1.3V=DFh
accuracy
EVR primary and secondary
monitor measurement latency
for a new supply value
t
EVRMON CC -
µs
1) The monitor tolerances constitute the inherent variation of the bandgap and ADC over process, voltage and temperature
operational ranges. The xxxPRIUV parameters are device individually tested in production with ±1% tolerance about the
min and max xxxPRIUV limits. In TQFP100 and QFP80 pin packages, VDDPRIUV is not tested as HWCFG2 pin is absent.
Table 3-39 EVR13 SMPS External components
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
29.7
13.5
50
External output capacitor value COUTDC SR 15.4
22
10
-
µF
µF
I
I
DDDC=1A
1)
6.5
DDDC=400mA
External output capacitor ESR CDC_ESR SR -
mOhm f≥0.5MHz; f≤10MHz
-
-
100
13.5
9.18
50
Ohm
µF
f=10Hz
External input capacitor value 1) CIN SR
6.5
4.42
-
10
6.8
-
I
I
DDDC=1A
µF
DDDC=400mA
External input capacitor ESR
External inductor value 2)
External inductor ESR
C
IN_ESR SR
mOhm f≥0.5MHz; f≤10MHz
-
-
100
4.29
6.11
0.2
Ohm
µH
f=100Hz
L
DC SR
2.31
3.29
3.3
4.7
-
f
f
DCDC=1.5MHz
DCDC=1MHz
µH
L
DC_ESR SR -
LL SR
Ohm
V
P + N-channel MOSFET logic
level
V
-
-
2.5
Data Sheet
3-383
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEVR
Table 3-39 EVR13 SMPS External components (cont’d)
Parameter Symbol Values
Typ.
Unit
Note / Test Condition
Min.
Max.
P + N-channel MOSFET drain |VBR_DS| SR -
-
7
V
source breakdown voltage
P + N-channel MOSFET drain RON SR
source ON-state resistance
-
-
150
mOhm IDDDC=1A;VGS=2.5V ;
TA=25°C
-
-
200
mOhm IDDDC=400mA;VGS=2.5
V ; TA=25°C
P + N-channel MOSFET Gate Qac SR
Charge
-
4
-
nC
nC
ns
V
I
DDDC=1A; MOS-
VGS=5V
IDDDC=400mA; MOS-
-
8
-
VGS=5V
External MOSFET
commutation time
tc SR
RDN SR
10
-
30
0.8
40
-
configurable
N-channel MOSFET reverse
diode forward voltage
V
1) Capacitor min-max range represent typical ±35% tolerance including DC bias effect. The trace resistance from the
capacitor to the supply or ground rail should be limited to 25 mOhm.
2) External inductor min-max range represent typical ±30% tolerance at a DC bias current of 100mA.
Table 3-40 EVR13 SMPS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2.97
2.97
1.17
Max.
3.63
5.5
Input VDDP3 voltage range
Input VEXT Voltage range
VIN CC
VIN SR
-
-
-
V
V
V
SMPS regulator output voltage VDDDC CC
range including load/line
regulation and aging 1)
1.43
V
DD≥2.97V; VDD≤5.5V;
I
DDDC≥1mA; IDDDC≤1A
SMPS regulator static voltage
output accuracy after trimming
without dynamic load/line
Regulation with aging. 2)
V
DDDCT CC 1.275
1.3
1.325
V
V
DD≥2.97V; VDD≤5.5V;
I
DDDC≥1mA; IDDDC≤1A
Programmable switching
frequency
f
DCDC CC
0.4
-
-
-
2.0
2%
15
MHz
MHz
mV
Switching frequency
modulation spread
∆fDCSPR CC -
Maximum ripple at IMAX (peak- ∆VDDDC CC -
VDD≥2.97V; VDD≤5.5V;
to-peak) 3)
I
I
DDDC≥300mA;
DDDC≤1A
No load current consumption of IDCNL CC
-
5
10
mA
fDCDC=1MHz
SMPS regulator
Data Sheet
3-384
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEVR
Table 3-40 EVR13 SMPS (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
SMPS regulator load transient dVout/dIout -25
response CC
Max.
-
25
mV
dI < 200mA ;
f
DCDC=1MHz; tr=0.1µs;
tf=0.1µs; VDDDC=1.3V
-65
-
65
130
1
mV
mV
A
dI < 400mA ;
f
DCDC=1MHz; tr=0.1µs;
tf=0.1µs; VDDDC=1.3V
-130
-
dI < 700mA ;
f
DCDC=1MHz; tr=0.1µs;
tf=0.1µs; VDDDC=1.3V
Maximum output current of the IMAX SR
regulator
-
-
-
limited by thermal
constraints and
component choice
SMPS regulator efficiency
n
DC CC
85
-
%
VIN=3.3V;
I
f
DDDC=300mA;
DCDC=1MHz
VIN=5V; IDDDC=400mA;
DCDC=1.5MHz
VIN=5V; IDDDC=400mA;
DCDC=1MHz
-
-
75
80
-
-
%
%
f
f
1) Incase of SMPS mode, It shall be ensured that the VDD output pin shall be connected on PCB level to all other VDD Input
pins.
2) Incase of fSRI running with max frequency, it shall be ensured that the VDD operating range is limited to 1.235V upto 1.430V.
The DCDC may be configured in this case with a nominal voltage of 1.33V±7.5%. The static accuracy and regulation
parameter ranges remain also valid for this case.
3) If frequency spreading (SDFREQSPRD = 1) is activated, an additional ripple of 1% need to be considered.
Data Sheet
3-385
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPhase Locked Loop (PLL)
3.17
Phase Locked Loop (PLL)
Table 3-41 PLL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
PLLBASE CC 80
Max.
360
800
24
PLL base frequency
VCO frequency range
VCO Input frequency range
Modulation Amplitude
Peak Period jitter
f
f
f
150
MHz
MHz
MHz
%
VCO SR
REF CC
400
8
-
-
-
-
-
-
MA CC
DP CC
0
2
-200
-5
200
5
ps
Peak Accumulated Jitter
Total long term jitter
DPP CC
ns
without modulation
JTOT CC
-
11.5
ns
including modulation;
MA ≤ 1%
System frequency deviation
f
SYSD CC
-
-
0.01
5.4
%
with active modulation
Modulation variation frequency fMV CC
PLL lock-in time tL CC
2
3.6
-
MHz
µs
11.5
200
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
3-386
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationERAY Phase Locked Loop (ERAY_PLL)
3.18
ERAY Phase Locked Loop (ERAY_PLL)
Table 3-42 PLL_ERAY
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
PLL Base Frequency of the
ERAY PLL
fPLLBASE_ERA 50
Y CC
200
320
MHz
MHz
MHz
VCO frequency range of the
ERAY PLL
fVCO_ERAY
400
-
-
480
24
SR
VCO input frequency of the
ERAY PLL
f
REF SR
16
Accumulated_Jitter
DP CC
DPP CC
-0.5
-0.8
-
-
0.5
0.8
ns
ns
Accumulated jitter at SYSCLK
pin
PLL lock-in time
tL CC
5.6
-
200
µs
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
3-387
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationAC Specifications
3.19
AC Specifications
All AC parameters are specified for the complette operating range defined in Chapter 3.4 unless otherwise noted
in colum Note / test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FLEX / VDDP3
90%
90%
10%
10%
VSS
tr
tf
rise_fall
Figure 3-9 Definition of rise / fall times
VEXT/FLEX / VDDP3
Timing
Reference
Points
VEXT/FLEX /VDDP3
V
EXT /FLEX / VDDP3
2
2
VSS
timing_reference
Figure 3-10 Time Reference Point Definition
Data Sheet
3-388
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationJTAG Parameters
3.20
JTAG Parameters
The following parameters are applicable for communication through the JTAG debug interface. The JTAG module
is fully compliant with IEEE1149.1-2000.
Table 3-43 JTAG
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
25
10
10
-
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
TCK low time
-
TCK clock rise time
TCK clock fall time
4
4
-
-
TDI/TMS setup to TCK rising
edge
6.0
TDI/TMS hold after TCK rising t7 SR
6.0
-
-
ns
edge
TDO valid after TCK falling
edge (propagation delay) 1)
t8 CC
3.0
-
-
-
-
-
ns
ns
ns
CL≤20pF
CL≤50pF
16.5
-
TDO hold after TCK falling
edge 1)
t
18 CC
2
TDO high impedance to valid t9 CC
-
-
-
-
17.5
17.5
ns
ns
CL≤50pF
CL≤50pF
from TCK falling edge 1)2)
TDO valid output to high
impedance from TCK falling
edge 1)
t10 CC
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
t1
0.9 VDDP
0.1 VDDP
0.5 VDDP
t5
t4
t2
t3
MC_JTAG_TCK
Figure 3-11 Test Clock Timing (TCK)
Data Sheet
3-389
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationJTAG Parameters
TCK
TMS
TDI
t6
t7
t6
t7
t9
t8
t10
TDO
t18
MC_JTAG
Figure 3-12 JTAG Timing
Data Sheet
3-390
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDAP Parameters
3.21
DAP Parameters
The following parameters are applicable for communication through the DAP debug interface.
Table 3-44 DAP
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DAP0 clock period
DAP0 high time
t
t
t
t
11 SR
12 SR
13 SR
14 SR
6.25
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
2
2
-
-
DAP0 low time
-
DAP0 clock rise time
1
2
1
2
-
f=160MHz
f=80MHz
f=160MHz
f=80MHz
-
DAP0 clock fall time
t
15 SR
-
-
DAP1 setup to DAP0 rising
edge
t
t
t
16 SR
17 SR
19 CC
4
DAP1 hold after DAP0 rising
edge
2
-
-
ns
DAP1 valid per DAP0 clock
period 1)
3
-
-
-
-
-
-
ns
ns
ns
CL=20pF; f=160MHz
CL=20pF; f=80MHz
CL=50pF; f=40MHz
8
10
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t11
0.9 VDDP
0.1 VDDP
0.5 VDDP
t15
t14
t12
t13
MC_DAP0
Figure 3-13 Test Clock Timing (DAP0)
DAP0
t16
t17
DAP1
MC_DAP1_RX
Figure 3-14 DAP Timing Host to Device
Data Sheet
3-391
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDAP Parameters
t11
DAP1
t19
MC_DAP1_TX
Figure 3-15 DAP Timing Device to Host (DAP1 and DAP2 pins)
Note:The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
Data Sheet
3-392
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
3.22
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC290 / TC297 / TC298 / TC299, for 5V power supply.
Note:Pad asymmetry is already included in the following timings.
Table 3-45 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-3
3
0 < CL < 50pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-7
-
-
-
-
6
35
-
ns
ns
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
5
CL=25pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
30
-4.5
CL=25pF
MRST hold from ASCLKO
latching edge
-
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-46 Master Mode MP+sm/MPRsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
-2
3+0.01 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-10
5
-
-
-
-
10
35
-
ns
ns
ns
ns
CL=50pF
ASLSOn delay from the first
ASCLKO edge
CL=50pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
50
-9
CL=50pF
MRST hold from ASCLKO
latching edge
-
CL=50pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-393
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-47 Master Mode MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-2
3.5+0.035 ns
0 < CL < 200pF
2)
* CL
MTSR delay from ASCLKO
shifting edge
t
t
t
51 CC
510 CC
52 SR
-7
-7
-
-
6
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
6
CL=25pF
MRST setup to ASCLKO
latching edge
31
33 3)
-
-
-
-
ns
ns
CL=25pF, else
CL=25pF, for P14.2,
P14.4, and P15.1
MRST hold from ASCLKO
latching edge
t
53 SR
-5
-
-
ns
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
3) Please note that these pins didn't support the hystereses inactive feature.
Table 3-48 Master Mode MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
4+0.04 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-11
-11
60
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-10
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-394
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-49 Master Mode medium output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-8
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
4+0.06 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-20
-20
70
-
-
-
-
18.5
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
20
-
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-10
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-50 Master Mode weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
1000
-30
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
30+0.15 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-75
-65
510
-50
-
-
-
-
75
65
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-395
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
t50
ASCLKO
MTSR
t51
t51
t500
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-16 ASCLIN SPI Master Timing
Data Sheet
3-396
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
3.23
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC290 / TC297 / TC298 / TC299, for 3.3V power supply,
Medium Performance pads, strong sharp edge (MPss), CL=25pF.
Note:Pad asymmetry is already included in the following timings.
Table 3-51 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-5
5
0 < CL < 50pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-12
0
-
-
-
-
12
60
-
ns
ns
ns
ns
CL=25pF
ASLSOn delay from the first
ASCLKO edge
CL=25pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
50
-5
CL=25pF
MRST hold from ASCLKO
latching edge
-
CL=25pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-52 Master Mode MP+sm/MPRsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
7
0 < CL < 200pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-17
0
-
-
-
-
17
60
-
ns
ns
ns
ns
CL=50pF
ASLSOn delay from the first
ASCLKO edge
CL=50pF; pad used =
LPm
MRST setup to ASCLKO
latching edge
85
-5
CL=50pF
MRST hold from ASCLKO
latching edge
-
CL=50pF
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-397
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-53 Master Mode MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=25pF
Deviation from ideal duty cycle t500 CC
-5
7+0.07 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-12
-12
50
-5
-
-
-
-
12
12
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-54 Master Mode MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-5
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
9+0.06 * ns
0 < CL < 200pF
2)
CL
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-19
-19
100
-13
-
-
-
-
17
17
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-55 Master Mode medium output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ASCLKO clock period 1)
t
50 CC
400
-
-
-
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
-6-0.07 *
CL
6+0.07 * ns
CL
0 < CL < 200pF
2)
Data Sheet
3-398
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-55 Master Mode medium output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-33
-
-
-
-
25
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
-35
120
-13
35
-
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-56 Master Mode weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2000
-110
Max.
-
ASCLKO clock period 1)
t
50 CC
-
-
ns
ns
CL=50pF
Deviation from ideal duty cycle t500 CC
150
0 < CL < 200pF
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-170
-170
510
-40
-
-
-
-
170
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
170
MRST setup to ASCLKO
latching edge
-
-
MRST hold from ASCLKO
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-57 Master Mode A2ss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
-3
3
2)
MTSR delay from ASCLKO
shifting edge
t
t
51 CC
-4
-5
-
-
4
4
ns
ns
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
510 CC
Data Sheet
3-399
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-57 Master Mode A2ss output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to ASCLKO
latching edge
t
t
52 SR
53 SR
17
-
-
ns
ns
CL=50pF
CL=50pF
MRST hold from ASCLKO
latching edge
0
-
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-58 Master Mode A2sm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
ASCLKO clock period 1)
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
-4
4
2)
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-8
-8
26
0
-
-
-
-
6
9
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
ASLSOn delay from the first
ASCLKO edge
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX
.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
t50
ASCLKO
t51
t51
t500
MTSR
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-17 ASCLIN SPI Master Timing
Data Sheet
3-400
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
3.24
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC290 / TC297 / TC298 / TC299, for 5V pad power supply.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
•
•
LVDSM output pads,LVDSH input pad, master mode, CL=25pF
Medium Performance Plus Pads (MP+):
–
–
–
–
strong sharp edge (MP+ss), CL=25pF
strong medium edge (MP+sm), CL=50pF
medium edge (MP+m), CL=50pF
weak edge (MP+w), CL=50pF
•
•
Medium Performance Pads (MP):
–
–
strong sharp edge (MPss), CL=25pF
strong medium edge (MPsm), CL=50pF
Medium and Low Performance Pads (MP/LP), the identical output strength settings:
–
–
medium edge (LP/MPm), CL=50pF
weak edge (MPw), CL=50pF
Table 3-59 Master Mode Timing, LVDSM output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20 2)
-1
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 3) 4)
500 CC
1
MTSR delay from SCLKO
shifting edge
t
51 CC
-3
-
3
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
0
-
-
-
-
-
30
7
ns
ns
ns
ns
ns
CL=25pF; MPsm
CL=25pF; MPss
MP+ss; CL=25pF
MP+sm; CL=25pF
-5
-4
7
-1
19 5)
15
-
MRST setup to SCLK latching
edge 5)
t
52 SR
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR
edge
-6 5)
-
-
ns
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
4) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
5) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Data Sheet
3-401
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-60 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-3
3
0 < CL < 50pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-7
-
-
-
-
6
6
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-7
MRST setup to SCLK latching
edge 4)
t
52 SR
27 4)5)
-4.5 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-61 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
3+0.01 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-10
-
10
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-10
-13
0
-
-
-
10
1
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
40
MP+m, MPm, LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-9 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-402
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-62 Master Mode timing MPss output pads for data and clock, CL=50pF
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
3.5+0.035 ns
0 < CL < 200pF
* CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-8
-
8
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-8
-1
0
-
-
-
8
ns
ns
ns
MPss; CL=50pF
15
50
MP+sm; CL=50pF
MP+m, MPm, LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
40 4)5)
-5 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-63 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
4+0.04 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-11
-
-
-
-
10
10
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-11
MRST setup to SCLK latching
edge 4)
t
52 SR
60 4)5)
-10 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
Data Sheet
3-403
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-64 Master Mode timing MPRm/MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-10
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
16+0.04 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-15
-
-
-
-
20
20
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-20
MRST setup to SCLK latching
edge 4)
t
52 SR
70 4)5)
-10 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-65 Master Mode Weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
1000
-30
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
30+0.15 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-65
-
-
-
-
65
65
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-65
MRST setup to SCLK latching
edge 4)
t
52 SR
300 4)5)
-40 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
Data Sheet
3-404
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-66 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
4 x TMAX
40
Max.
SCLK clock period
SCLK duty cycle
t
t
t
54 SR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
%
55/t54 SR
56 SR
60
-
MTSR setup to SCLK latching
edge
4 1)
5 1)
5 1)
3.5 1)
6 1)
9 1)
5 1)
4 1)
8 1)
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hystheresis Inactive
Input Level AL
-
-
Input Level TTL
Hystheresis Inactive
Input Level AL
MTSR hold from SCLK latching t57 SR
edge
-
-
-
Input Level TTL
Hystheresis Inactive
Input Level AL
SLSI setup to first SCLK shift
edge
t
58 SR
-
-
-
Input Level TTL
Only for pin 15.1, AL
Hystheresis Inactive
Input Level AL
-
SLSI hold from last SCLK
latching edge
t
t
59 SR
60 CC
3 1)
4 1)
8 1)
10
-
-
-
Input Level TTL
MRST delay from SCLK shift
edge
70
MP+m/MPRm;
CL=50pF
9
-
-
-
50
ns
ns
ns
MP+sm/MPRsm;
CL=50pF
5
30
MP+ss/MPRss;
CL=25pF
40
300
MP+w/MPRw;
CL=50pF
10
10
5
-
-
-
-
-
70
55
30
300
5
ns
ns
ns
ns
ns
MPm/LPm; CL=50pF
MPsm; CL=50pF
MPss; CL=25pF
40
-
MPw/LPw; CL=50pF
SLSI to valid data on MRST
1) Except pin P15.1.
t
61 SR
Data Sheet
3-405
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-18 Master Mode Timing
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-19 Slave Mode Timing
3.25
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC290 / TC297 / TC298 / TC299, for 3.3V pad power supply.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
•
•
LVDSM output pads,LVDSH input pad, master mode, CL=25pF
Medium Performance Plus Pads (MP+):
–
–
–
–
strong sharp edge (MP+ss), CL=25pF
strong medium edge (MP+sm), CL=50pF
medium edge (MP+m), CL=50pF
weak edge (MP+w), CL=50pF
•
•
Medium Performance Pads (MP):
–
–
strong sharp edge (MPss), CL=25pF
strong medium edge (MPsm), CL=50pF
Medium and Low Performance Pads (MP/LP), the identical output strength settings:
Data Sheet
3-406
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
–
–
medium edge (LP/MPm), CL=50pF
weak edge (MPw), CL=50pF
Table 3-67 Master Mode Timing, LVDSM output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-2
2
MTSR delay from SCLKO
shifting edge
t
51 CC
-5
-
5
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-2
-9
-7
-2
20
-
-
-
-
-
55
12
12
26
-
ns
ns
ns
ns
ns
CL=25pF; MPsm
CL=25pF; MPss
MP+ss; CL=25pF
MP+sm; CL=25pF
MRST setup to SCLK latching
edge 4)
t
52 SR
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
MRST hold from SCLK latching t53 SR
edge
-6
-
-
ns
CL=25pF; LVDSM 5V
output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Table 3-68 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-5
5
0 < CL < 50pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-12
-
-
-
-
12
12
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-12
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-5 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
Data Sheet
3-407
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-69 Master Mode MP+sm/MPRsm output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
100
-3
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
7
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-17
-
17
ns
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-17
-22
0
-
-
-
17
2
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
70
MP+m; MPm; LPm;
CL=50pF
MRST setup to SCLK latching
edge 4)
t
52 SR
85 4)5)
-
-
-
-
ns
ns
CL=50pF
MRST hold from SCLK latching t53 SR
-10 4)5)
CL=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-70 Master Mode timing MPss output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-5
5+0.04 * ns
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-7
-
-
7
ns
ns
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
-10
10
programmed position
Data Sheet
3-408
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-70 Master Mode timing MPss output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to SCLK latching
edge 4)
t
52 SR
50 4)5)
-
-
ns
ns
CL=25pF
CL=25pF
MRST hold from SCLK latching t53 SR
-6 4)5)
-
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-71 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
200
-5
Max.
SCLKO clock period 1)
t
t
50 CC
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
9+0.06 * ns
0 < CL < 200pF
CL
MTSR delay from SCLKO
shifting edge
t
51 CC
-19
-
-
-
-
19
17
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-19
MRST setup to SCLK latching
edge 4)
t
52 SR
100 4)5)
-13 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-72 Master Mode timing MPRm/MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SCLKO clock period 1)
t
t
50 CC
400
-
-
-
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
-6-0.07 *
CL
6+0.095 * ns
CL
0 < CL < 200pF
Data Sheet
3-409
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-72 Master Mode timing MPRm/MP+m/MPm/LPm output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MTSR delay from SCLKO
shifting edge
t
51 CC
-25
-
-
-
-
33
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-35
35
-
MRST setup to SCLK latching
edge 4)
t
52 SR
120 4)5)
-13 4)5)
MRST hold from SCLK latching t53 SR
-
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-73 Master Mode Weak output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2000
-110
Max.
-
SCLKO clock period 1)
t
t
50 CC
-
-
ns
ns
CL=50pF
Deviation from the ideal duty
cycle 2) 3)
500 CC
125
0 < CL < 200pF
MTSR delay from SCLKO
shifting edge
t
51 CC
-170
-
-
-
-
170
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-170
170
MRST setup to SCLK latching
edge 4)
t
52 SR
510 4)5)
-40 4)5)
-
-
MRST hold from SCLK latching t53 SR
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX
.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Data Sheet
3-410
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-74 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
4 x TMAX
40
7 1)
9 1)
7 1)
5 1)
11 1)
16 1)
7 1)
Max.
SCLK clock period
SCLK duty cycle
t
54 SR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
%
t
t
55/t54 SR
56 SR
60
MTSR setup to SCLK latching
edge
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hystheresis inactive
Input Level AL
-
-
Input Level TTL
Hystheresis inactive
Input Level AL
MTSR hold from SCLK latching t57 SR
edge
-
-
-
Input Level TTL
Hystheresis inactive
Input Level AL
SLSI setup to first SCLK shift
edge
t
58 SR
-
7 1)
14 1)
-
-
Input Level TTL
Only for pin P15.1, AL
Hystheresis inactive
Input Level AL
11
5 1)
7 1)
14 1)
-
SLSI hold from last SCLK
latching edge
t
t
59 SR
60 CC
-
-
-
Input Level TTL
MRST delay from SCLK shift
edge
13
120
MP+m/MPRm;
CL=50pF
12.5
5.5
70
-
-
-
85
ns
ns
ns
MP+sm/MPRsm;
CL=50pF
50
MP+ss/MPRss;
CL=25pF
500
MP+w/MPRw;
CL=50pF
13
13
6
-
-
-
-
-
120
100
52
ns
ns
ns
ns
ns
MPm/LPm; CL=50pF
MPsm; CL=50pF
MPss; CL=25pF
70
-
500
9
MPw/LPw; CL=50pF
SLSI to valid data on MRST
1) Except pin P15.1
t
61 SR
Data Sheet
3-411
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-20 Master Mode Timing
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-21 Slave Mode Timing
Data Sheet
3-412
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 5 V Operation
3.26
MSC Timing 5 V Operation
The following section defines the timings for 5V pad power supply.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Table 3-75 LVDS clock/data (LVDS pads in LVDS mode)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-1
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
ns
LVDSM; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
1
LVDSM; 0 < CL < 50pF
4) 5)
SOPx output delay 6)
t
t
44 CC
-3
-
-
-
-
-
4
ns
ns
ns
ns
ns
LVDSM; CL=50pF;
option EN01
-4
4.5
5
LVDSM; CL=50pF;
option EN01D
ENx output delay 6)
45 CC
-4
MP+ss/MPRss; option
EN01; CL=25pF
-3.5
-3
7
MP+ss/MPRss; option
EN01; CL=50pF
11
MP+sm/MPRsm;
option EN01D;
CL=50pF
-2.5
-2.5
-3
-
-
-
-
-
-
-
9
ns
ns
ns
ns
ns
ns
ns
MP+ss/MPRss; option
EN23; CL=25pF
10
11
3
MP+ss/MPRss; option
EN23; CL=50pF
MPss; option EN01;
CL=50pF
-7
MP+ss/MPRss; option
EN01; CL=0pF
-5
3
MP+sm/MPRsm;
option EN01D; CL=0pF
-4
6
MP+ss/MPRss; option
EN23; CL=0pF
-7
4
MPss; option EN01;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
Data Sheet
3-413
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 5 V Operation
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Data Sheet
3-414
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 5 V Operation
Timing Options for t45
The wiring shown in the Figure 3-22 provides three useful timing options for t45. depending on the signals selected
with the alternate output lines (ALT1 to ALT7) in the ports:
•
•
•
EN01 - FCLN, SON, EN0, EN1
EN01D - FCLND, SOND, EN0, EN1 - t45 window shifted to the left
EN23 - FCLN, SON, EN2, EN3 - t45 window shifted to the right
- t45 reference timing
The timings corresponding to EN01, EN01D, and EN23 are defined in the LVDS mode. In order to use the EN23
timings, the application should use the EN2 and EN3 outputs of the MSC module.
ALT1
FCLN ALTx
ALTy
LVDSM
FCLP
FCLN
FCLND
ALT7
PAD
ALT1
SON ALTx
ALTy
LVDSM
SOP
SON
SOND
ALT7
PAD
ALT1
ALTx
ALTy
EN0
EN1
CMOS
ALT7
PAD
EN2
EN3
ALT1
ALTx
ALTy
CMOS
MSC
ALT7
PAD
_DoublePath_4a.vsd
Figure 3-22 Timing Options for t45
Mapping B, CMOS MP Pads
This timing applies for the dedicated CMOS pads, pin Mapping B:
•
•
MP strong sharp (MPss) output pads for the clock and the data signals
MP strong sharp or strong medium (MP+ss or MP+sm) output pads for enable signals
Table 3-76 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
MPss; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
3+0.035 * ns
MPss; 0 < CL < 100pF
4) 5)
CL
Data Sheet
3-415
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 5 V Operation
Table 3-76 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-4
Max.
SOPx output delay 6)
ENx output delay 6)
t
t
44 CC
45 CC
-
-
7
7
ns
ns
MPss; CL=50pF
-6
MP+ss/MPRss;
CL=50pF
-2
-
16.5
ns
MP+sm/MPRsm;
CL=50pF
-4
0
-
-
10
32
ns
ns
MPss; CL=50pF
MPsm; CL=50pF;
except pin P13.0
0
-
-
-
-
32
45
7.5
13
ns
ns
ns
ns
MPsm; CL=50pF; pin
P13.0
5
MPm/MP+m/MPRm;
CL=50pF
-11
-4
MP+ss/MPRss;
CL=0pF
MP+sm/MPRsm;
CL=0pF
-10
-1
-
-
-
7
ns
ns
ns
MPss; CL=0pF
MPsm; CL=0pF
22
25
-2
MP+m/MPm/MPRm;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) FCLP signal high and low can be minimum 1 * TMSC
.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Table 3-77 MP+sm/MPRsm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
MP+sm/MPRsm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-3
-
3+0.01 * ns
CL
MP+sm/MPRsm; 0 <
CL < 200pF
2) 3)
Data Sheet
3-416
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 5 V Operation
Table 3-77 MP+sm/MPRsm clock/data (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-5
Max.
7
2 5)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-
-
-
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
-13
-5
11
MP+sm/MPRsm;
CL=50pF
1
3
-
-
25
37
ns
ns
MPsm; CL=50pF
MP+m/MPm/MPRm;
CL=50pF
-19
-13
-5
-
-
-
-
2
ns
ns
ns
ns
MPss; CL=0pF
MP+sm; CL=0pF
MPsm; CL=0pF
8
17
20
-5
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
5) If EN1 is configured to P13.0 the max limt is increased by 0.5ns to 2.5ns.
Table 3-78 MPm/MP+m/MPRm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
MPm/MP+m/MPRm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-16
-
4+0.04 * ns
CL
MPm/MP+m; 0 < CL <
200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-11
-13
-
-
20
24
ns
ns
MPm/MP+m; CL=50pF
MPm/MP+m/MPRm;
CL=50pF
-33
-
17
ns
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
Data Sheet
3-417
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
t40
t400
FCLP
SOP
t44
t44
t45
t45
0.5 VEXT/FLEX
EN
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-23 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
3.27
MSC Timing 3.3 V Operation
The following section defines the timings for 3.3V pad power supply.
Mapping A, Combo Pads in LVDS Mode or CMOS Mode
The timing applies for the LVDS pads in LVDS operating mode:
•
•
The LVDSM output pads for clock and data signals set in LVDS mode
The CMOS MP pads for enable signals, with strong driver sharp edge (MPss) or strong driver medium edge
(MPsm).
Table 3-79 LVDS clock/data (LVDS pads in LVDS mode)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
ns
LVDSM; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
2
LVDSM; 0 < CL < 50pF
4) 5)
SOPx output delay 6)
t
44 CC
-5
-7
-
-
5
7
ns
ns
LVDSM; CL=50pF;
option EN01
LVDSM; CL=50pF;
option EN01D
Data Sheet
3-418
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-79 LVDS clock/data (LVDS pads in LVDS mode) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ENx output delay 6)
t
45 CC
-7
-
-
-
9.5
ns
ns
ns
MP+ss/MPRss; option
EN01; CL=25pF
-5
-5
13
26
MP+ss/MPRss; option
EN01; CL=50pF
MP+sm/MPRsm;
option EN01D;
CL=50pF
-4
-
-
-
-
-
-
-
16
17
19
5.5
11
9
ns
ns
ns
ns
ns
ns
ns
MP+ss/MPRss; option
EN23; CL=25pF
-4
MP+ss/MPRss; option
EN23; CL=50pF
-5
MPss; option EN01;
CL=50pF
-12
-9
MP+ss/MPRss; option
EN01; CL=0pF
MP+sm/MPRsm;
option EN01D; CL=0pF
-7
MP+ss/MPRss; option
EN23; CL=0pF
-12
7
MPss; option EN01;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Mapping B, CMOS MP Pads
This timing applies for the dedicated CMOS pads, pin Mapping B:
•
•
MP strong sharp (MPss) output pads for the clock and the data signals
MP strong sharp or strong medium (MPss or MPsm) output pads for enable signals
Data Sheet
3-419
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-80 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-5
Max.
FCLPx clock period 1)
t
40 CC
-
-
-
ns
MPss; CL=50pF
2) 3)
Deviation from ideal duty cycle t400 CC
7+0.07 * ns
MPss; 0 < CL < 100pF
4) 5)
CL
SOPx output delay 6)
ENx output delay 6)
t
t
44 CC
45 CC
-7
-9
-
-
12
12
ns
ns
MPss; CL=50pF
MP+ss/MPRss;
CL=50pF
-4
-
26
ns
MP+sm/MPRsm;
CL=50pF
-7
0
-
-
17
56
ns
ns
MPss; CL=50pF
MPsm; CL=50pF;
except pin P13.0
0
-
-
-
-
58
77
8
ns
ns
ns
ns
MPsm; CL=50pF; pin
P13.0
4
MPm/MP+m/MPRm;
CL=50pF
-19
-7
MP+ss/MPRss;
CL=0pF
19
MP+sm/MPRsm;
CL=0pF
-17
-2
-
-
-
8
ns
ns
ns
MPss; CL=0pF
MPsm; CL=0pF
38
41
-4
MP+m/MPm/MPRm;
CL=0pF
SDI bit time
t
t
t
46 CC
48 SR
49 SR
8 * tMSC
-
-
-
-
ns
ns
ns
Upstream Timing
Upstream Timing
Upstream Timing
SDI rise time 7)
SDI fall time 7)
-
-
200
200
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) FCLP signal high and low can be minimum 1 * TMSC
.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Data Sheet
3-420
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-81 MP+sm/MPRsm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
ns
MP+sm/MPRsm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-6
-
7
MP+sm/MPRsm; 0 <
CL < 200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-9
-
-
-
12
4
ns
ns
ns
MP+sm; CL=50pF
MPss; CL=50pF
-20
-9
19
MP+sm/MPRsm;
CL=50pF
0
0
-
-
44
63
ns
ns
MPsm; CL=50pF
MP+m/MPm/MPRm;
CL=50pF
-33
-23
-
-
0
9
ns
ns
MPss; CL=0pF
MP+sm/MPRsm;
CL=0pF
-9
-9
-
-
28
31
ns
ns
MPsm; CL=0pF
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) From FCLP rising edge.
Table 3-82 MPm/MP+m/MPRm clock/data
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
FCLPx clock period 1)
t
40 CC
2 * TA
-
-
ns
MPm/MP+m/MPRm;
CL=50pF
Deviation from ideal duty cycle t400 CC
-6-0.95 *
CL
-
6+0.07 * ns
CL
MPm/MP+m/MPRm; 0
< CL < 200pF
2) 3)
SOPx output delay 4)
ENx output delay 4)
t
t
44 CC
45 CC
-19
-19
-
-
34
38
ns
ns
MPm/MP+m; CL=50pF
MPm/MP+m/MPRm;
CL=50pF
-57
-
27
ns
MPm/MP+m/MPRm;
CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-421
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 3.3 V Operation
4) From FCLP rising edge.
t40
t400
FCLP
t44
t44
SOP
EN
t45
t45
0.5 VEXT/FLEX
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-24 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
Data Sheet
3-422
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.28
Ethernet Interface (ETH) Characteristics
3.28.1
ETH Measurement Reference Points
ETH Clock
ETH I/O
1.4
2.0
V
1.4 V
V
2.0
V
0.8
V
0.8
V
tR
tF
ETH_Testpoints.vsd
Figure 3-25 ETH Measurement Reference Points
Data Sheet
3-423
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.28.2
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 3-83 ETH Management Signal Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
400
160
160
10
Max.
ETH_MDC period
ETH_MDC high time
ETH_MDC low time
t1 CC
t2 CC
t3 CC
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
-
-
ETH_MDIO setup time (output) t4 CC
ETH_MDIO hold time (output) t5 CC
ETH_MDIO data valid (input) t6 SR
-
10
-
0
300
t1
t3
t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4
t5
ETH_MDIO
(output )
Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input )
Valid Data
ETH_Timing-Mgmt.vsd
Figure 3-26 ETH Management Signal Timing
Data Sheet
3-424
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.28.3
ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.
Table 3-84 ETH MII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Clock period
t7 SR
40
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF;
baudrate=100Mbps
400
14
-
CL=25pF;
baudrate=10Mbps
Clock high time
Clock low time
t8 SR
t9 SR
26
CL=25pF;
baudrate=100Mbps
140 1)
14
260 2)
26
CL=25pF;
baudrate=10Mbps
CL=25pF;
baudrate=100Mbps
140 1)
260 2)
CL=25pF;
baudrate=10Mbps
Input setup time
Input hold time
t
t
t
10 SR
11 SR
12 CC
10
10
0
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
-
Output valid time
25
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t7
t9
t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t10
t11
ETH_MII_RXD[3:0]
ETH_MII_RX_DV
ETH_MII_RX_ER
(sourced by PHY )
Valid Data
ETH_MII_TX_CLK
t12
ETH_MII_TXD[3:0]
ETH_MII_TXEN
Valid Data
(sourced by controller )
ETH_Timing-MII.vsd
Figure 3-27 ETH MII Signal Timing
Data Sheet
3-425
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.28.4
ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.
Table 3-85 ETH RMII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ETH_RMII_REF_CL clock
period
t
13 CC
20
-
-
-
-
-
ns
ns
ns
ns
CL=25pF; 50ppm
CL=25pF
ETH_RMII_REF_CL clock high t14 CC
time
7 1)
7 1)
4
13 2)
13 2)
-
ETH_RMII_REF_CL clock low t15 CC
time
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV,
ETHRXER; setup time
t
t
16 CC
17 CC
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV,
ETHRXER; hold time
2
-
-
ns
CL=25pF
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t13
t15
t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t16
t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0],
ETHCRSDV,
ETHRXER
Valid Data
ETH_Timing-RMII.vsd
Figure 3-28 ETH RMII Signal Timing
Data Sheet
3-426
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationE-Ray Parameters
3.29
E-Ray Parameters
The timings of this section are valid for the strong driver and either sharp edge settings of the output drivers with
CL = 25 pF. For the inputs the hysteresis has to be configured to inactive.
Table 3-86 Transmit Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise time of TxEN
Fall time of TxEN
tdCCTxENRise2
5 CC
-
-
-
-
9
ns
ns
ns
CL=25pF
tdCCTxENFall25
CC
-
-
9
9
CL=25pF
Sum of rise and fall time
tdCCTxRise25+
20% - 80%; CL=25pF
dCCTxFall25
CC
Sum of delay between TP1_FF tdCCTxEN01
-
-
-
-
25
25
ns
ns
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxEN
CC
Sum of delay between TP1_FF tdCCTxEN10
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxEN
CC
Asymmetry of sending
t
tx_asym CC -2.45
-
-
2.45
25
ns
ns
CL=25pF
Sum of delay between TP1_FF tdCCTxD01
-
-
-
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxD
CC
Sum of delay between TP1_FF tdCCTxD10
-
-
25
9
ns
ns
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxD
CC
TxD signal sum of rise and fall ttxd_sum CC
time at TP1_BD
Table 3-87 Receive Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -30.5
ept25 SR
-
43.0
ns
ns
%
%
CL=25pF
CL=15pF
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -31.5
ept15 SR
-
-
-
44.0
70
Threshold for detecting logical TuCCLogic1
high SR
Threshold for detecting logical TuCCLogic0
35
30
65
low
SR
Data Sheet
3-427
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationE-Ray Parameters
Table 3-87 Receive Parameters (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sum of delay between TP4_CC tdCCRxD01
-
-
10
ns
and TP4_FF and delays
derived from TP4_FFi, rising
edge of RxD
CC
Sum of delay between TP1_CC tdCCRxD10
-
-
10
ns
and TP1_CC and delays
derived from TP4_FFi, falling
edge of RxD
CC
Data Sheet
3-428
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHSCT Parameters
3.30
HSCT Parameters
Table 3-88 HSCT - Rx/Tx setup timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
60
RX o/p duty cycle
Bias startup time
DCrx CC
-
%
t
bias CC
5
10
µs
Bias distributor waking
up from power down
and provide stable
Bias.
RX startup time
TX startup time
trxi CC
ttx CC
-
-
5
5
-
-
µs
µs
Wake-up RX from
power down.
Wake-up TX from
power down.
Table 3-89 HSCT - Rx parasitics and loads
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Capacitance total budget
Ctotal CC
-
3.5
5
pF
Total Budget for
complete receiver
including silicon,
package, pins and
bond wire
Parasitic inductance budget
Htotal CC
-
5
-
nH
Table 3-90 LVDSH - Reduced TX and RX (RED)
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Output differential voltage
V
OD CC
150
200
285
mV
Rt = 100 Ohm ±20%
@2pF
Output voltage high
Output voltage low
V
V
OH CC
OL CC
-
-
1463
-
mV
mV
V
Rt = 100 Ohm ±20%
Rt = 100 Ohm ±20%
937
1.08
-
Output offset (Common mode) VOS CC
voltage
1.2
1.32
Rt = 100 Ohm ±20%
@2pF
Input voltage range
VI SR
-
-
-
-
1.6
-
V
Absolute max = 1.6 V +
(285mV/2) = 1.743
0.15
-100
V
Absolute min = 0.15 V -
(285 mV /2) = 0 V
Input differential threshold
Data frequency
V
idth SR
100
mV
100 mV for 55% of bit
period; Note Absolute
Value (Vidth - Vidthl)
DR CC
5
-
320
Mbps
Data Sheet
3-429
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHSCT Parameters
Table 3-90 LVDSH - Reduced TX and RX (RED) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
90
80
-
Max.
110
120
2
Receiver differential input
impedance
Rin CC
100
Ohm
Ohm
V/ns
mV
0 V < VI < 1.6V
100
1.6 V < VI < 2.0V
Slew rate
SRtx CC
-
-
Change in VOS between 0 and dVOS CC
1
-
50
Peak to peak
(including DC
transients).
Change in Vod between 0 and dVod CC
1
-
-
50
mV
Peak to peak
(including DC
transients)
Fall time 1)
Rise time 1)
t
t
fall CC
rise CC
0.26
0.26
-
-
1.2
1.2
ns
ns
Rt = 100 Ohm ±20%
@2pF
Rt = 100 Ohm ±20%
@2pF
1) Rise / fall times are defined for 10% - 90% of VOD
Table 3-91 HSCT PLL
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
12.5
10
-
Typ.
Max.
320
PLL frequency range
PLL input frequency
PLL lock-in time
f
f
t
PLL CC
REF CC
LOCK CC
320
MHz
MHz
µs
-
-
-
20
50
Bit Error Rate based on 10 MHz BER10 CC
reference clock at Slave PLL
side
-
10EXP-9
-
Bit Error Rate based
on Slave interface
reference clock at 10
MHz
Bit Error Rate based on 20 MHz BER20 CC
reference clock at Slave PLL
side
-
-
-
-
10EXP-
12
-
Bit Error Rate based
on Slave interface
reference clock at 20
MHz
Absolute RMS Jitter (TX out)
JABS10 CC
-125
-85
125
85
ps
ps
Measured at link TX
out; valid for
Reference frequency
at 10 MHz
Absolute RMS Jitter (TX out)
JABS20 CC
Measured at link TX
out; valid for
Reference frequency
at 20 MHz
Data Sheet
3-430
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHSCT Parameters
Table 3-91 HSCT PLL (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Accumulated RMS Jitter (RX
side)
J
ACC10 CC
-
-
-
-
145
ps
Measured at link RX
input, based on 5000
measures, each 300
clock cycles; valid for
Reference frequency
at 10 MHz
Accumulated RMS Jitter (link
RX side)
JACC20 CC
-
-
115
ps
Measured at link RX
input, based on 5000
measures, each 300
clock cycles; valid for
Reference frequency
at 20 MHz
Total Jitter peak to peak
TJpp CC
2083
ps
Total Jitter as sum of
deterministic jitter and
random jitter
Table 3-92 HSCT Sysclk
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
20
1
Frequency
f
SYSCLK CC 10
-
-
-
-
-
-
MHz
%
Frequency error
Duty Cycle
dfERR CC -1
DCsys CC 45
55
-
%
Load impedance
Load capacitance
Integrated phase noise
R
LOAD CC
LOAD CC
PN CC
10
-
kOhm
pF
C
10
-58
I
-
dB
single sideband phase
noise in 10 kHz to 10
Mhz at 20 MHz SysClk
Data Sheet
3-431
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
3.31
Inter-IC (I2C) Interface Timing
This section defines the timings for I2C in the TC290 / TC297 / TC298 / TC299.
All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-93 I2C Standard Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
-
-
300
ns
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
4.7
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
-
-
-
-
-
-
-
1000
ns
µs
ns
µs
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data hold time
t3
t4
t5
t6
t7
0
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
250
4.7
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Hold time for the (repeated)
START condition
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
3-432
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
Table 3-93 I2C Standard Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Set-up time for (repeated)
START condition
t8
4.7
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
4
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Table 3-94 I2C Fast Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
20+0.1*C -
300
ns
Measured with a pull-
up resistor of 4.7
b
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
1.3
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
20+0.1*C -
300
ns
µs
ns
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
b
Data hold time
t3
t4
t5
t6
0
-
-
-
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
100
1.3
0.6
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
3-433
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
Table 3-94 I2C Fast Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Hold time for the (repeated)
START condition
t7
0.6
-
-
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for (repeated)
START condition
t8
0.6
0.6
-
-
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
t1
t2
t4
70%
SDA
30%
t1
t3
t2
t6
SCL
9th
clock
t7
t5
t10
S
SDA
t8
t7
t9
SCL
9th
clock
Sr
P
S
Figure 3-29 I2C Standard and Fast Mode Timing
Data Sheet
3-434
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings
3.32
EBU Timings
3.32.1
BFCLKO Output Clock Timing
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%,;
CL = 35 pF
Table 3-95 BFCLK0 Output Clock Timing Parameters1)
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Conditi
on
Min.
Max.
BFCLKO clock period
BFCLKO high time
t
BFCLKO CC
13.332)
–
–
ns
ns
ns
ns
ns
%
–
–
–
–
–
–
t5
CC
CC
CC
3
–
–
BFCLKO low time
t6
3
–
–
BFCLKO rise time
t7
–
–
3
BFCLKO fall time
BFCLKO duty cycle t5/(t5 + t6)3)
t8
–
–
3
CC
DC
35
50
55
1) Not subject to production test, verified by design/characterization.
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K divider has to be regarded.
tBFCLKO
0.9 VDD
0.5 VDDP05
BFCLKO
0.1 VDD
t8
t7
t5
t6
MCT04883_mod
Figure 3-30 BFCLKO Output Clock Timing
3.32.2
EBU Asynchronous Timings
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
CL = 35 pF for address/data; CL = 40pF for the control lines.
For each timing, the accumulated PLL jitter of the programed duration in number of clock periods must be added
separately. Operating conditions apply and CL = 35 pF.
Table 3-96 Common Asynchronous Timings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
AD(31:0) output delay to ADV# t13 CC
rising edge, multiplexed read /
write
-5.5
-
2
ns
AD(31:0) output delay to ADV# t14 CC
rising edge, multiplexed read /
write
-5.5
-
2
ns
Data Sheet
3-435
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings
Table 3-96 Common Asynchronous Timings (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Address valid to CS falling
edge (deviation from
programmed value)
t
t
t
15 CC
16 CC
17 CC
-2
-
-
-
2
ns
Address valid -> ADV falling
edge (deviation from
programmed value)
-2
-2
2
2
ns
ns
ADV falling edge -> CS falling
edge (deviation from
programmed value)
Pulse wdih deviation from the ta CC
ideal programmed width due to
pad asymmetry, rise delay - fall
delay
-0.8
-0.8
-
-
0.8
0.8
ns
ns
edge=medium
edge=sharp
Table 3-97 Asynchronous Read Timings
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
A(23:0) output delay to RD
rising edge, deviation from the
ideal programmed value
t0 CC
-2.5
-
2.5
ns
AD(31:0) output delay to ADV# t13 CC
rising edge, multiplexed read /
write
-2.5
-2.5
-
-
10
10
ns
ns
AD(31:0) output delay to ADV# t14 CC
rising edge, multiplexed read /
write
Data input Hold from CS rising t18 CC
edge
-4
-
-
-
-
ns
ns
ns
Data input Setup to CS rising
edge
t
19 CC
12
-
A(23:0) output delay to RD
rising edge, deviation from the
ideal programmed value
t1 CC
t2 CC
t3 CC
t4 CC
-2.5
2.5
CS rising edge to RD rising
edge, deviation from the ideal
programmed value
-2
-
-
-
2.5
4.5
2.5
ns
ns
ns
ADV rising edge to RD rising
edge, deviation from the ideal
programmed value
-1.5
-2.5
BC rising edge to RD rising
edge, deviation from the ideal
programmed value
Data Sheet
3-436
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings
Table 3-97 Asynchronous Read Timings (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
WAIT input setup to RD rising t5 SR
edge
12
-
-
-
-
-
-
ns
ns
ns
ns
ns
WAIT input hold to RD rising
edge
t6 SR
t7 SR
t8 SR
t9 CC
0
-
Data input setup to RD rising
edge
12
0
-
Data input hold to RD rising
edge
-
MR / W output delay to RD#
rising edge, deviation from the
ideal programmed value
-2.5
1.5
Data
Hold Phase
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
EBU
STATE
Control Bitfield:
ADDRC
1...15
AHOLDC
0...15
RDWAIT
1...31
DATAC
0...15
RDRECOVC
0...15
ADDRC
1...15
Duration Limits in
EBU_CLK Cycles
Next
Addr.
A[23:0]
Valid Address
pv +
t30
pv +
t31
pv +
ta
pv +
t32
CS[3:0]
CSCOMB
pv +
pv +
t33
ta
ADV
pv +
ta
RD/WR
BC[3:0]
pv +
ta
pv +
ta
t34
t35
WAIT
t36
t14
t37
pv + t13
pv +
t38
AD[31:0]
MR/W
Data Out
Address Out
pv +
t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
new_MuxWR_Async_10.vsd
Figure 3-31 Multiplexed Read Access
Data Sheet
3-437
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings
Data
Hold Phase
Address
Phase
Address Hold
Phase (opt.)
Command
Phase
Recovery
Phase (opt.)
New Addr.
Phase
EBU
STATE
Control Bitfield:
ADDRC
1...15
AHOLDC
0...15
RDWAIT
1...31
DATAC
0...15
RDRECOVC
0...15
ADDRC
1...15
Duration Limits in
EBU_CLK Cycles
Next
A[23:0]
Valid Address
Addr.
pv +
t30
pv +
t31
pv +
ta
pv +
t32
CS[3:0]
CSCOMB
pv +
pv +
t33
ta
ADV
pv +
ta
RD/WR
BC[3:0]
pv +
ta
pv +
ta
t34
t35
WAIT
t36
t37
pv +
t38
AD[31:0]
MR/W
Data Out
pv +
t39
pv = programmed value,
TEBU_CLK * sum (correponding bitfield values)
new_DemuxWR_Async_10.vsd
Figure 3-32 Demultiplexed Read Access
Table 3-98 Asynchronous Write Timings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
A(23:0) output delay to WR
rising edge, deviation from the
ideal programmed value
t
t
t
30 CC
31 CC
32 CC
-2.5
-
-
-
2.5
ns
A(23:0) output delay to WR
rising edge, deviation from the
ideal programmed value
-2.5
-2
2.5
2
ns
ns
CS rising edge to WR rising
edge, deviation from the ideal
programmed value
Data Sheet
3-438
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings
Table 3-98 Asynchronous Write Timings (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ADV rising edge to WR rising
edge, deviation from the ideal
programmed value
t
t
33 CC
34 CC
-2.5
-
-
-
-
-
-
-
2
ns
BC rising edge to WR rising
edge, deviation from the ideal
programmed value
-2.5
12
2
ns
ns
ns
ns
ns
ns
WAIT input setup to WR rising t35 SR
edge, deviation from the ideal
programmed value
-
WAIT input hold to WR rising
edge, deviation from the ideal
programmed value
t
36 CC
0
-
Data output delay to WR rising t37 CC
edge, deviation from the ideal
programmed value
-5.5
-5.5
-2.5
10
2
Data output delay to WR rising t38 CC
edge, deviation from the ideal
programmed value
MR / W output delay to WR
rising edge, deviation from the
ideal programmed value
t
39 CC
1.5
3.32.3
EBU Burst Mode Access Timing
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%;
CL = 35 pF;
Table 3-99 Burst Read Timings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Output delay from BFCLKO
rising edge
t
t
10 CC
-2
-
-
-
-
-
-
-
2
ns
ns
ns
ns
ns
ns
ns
D(31:0) Output delay from
BFCLKO rising edge
10a CC
-2
10
2
RD and RD/WR active/inactive t12 CC
after BFCLKO active edge
-2
CSx output delay from
BFCLKO active edge
t
t
t
t
21 CC
22 CC
22a CC
23 SR
-2.5
-2
1.5
2
ADV active/inactive after
BFCLKO active edge
BAA active/inactive after
BFCLKO active edge
-2.5
3
4.5
-
Data setup to BFCLKI rising
edge
Data Sheet
3-439
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings
Table 3-99 Burst Read Timings (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Data hold from BFCLKI rising
edge
t
t
t
24 SR
25 SR
26 SR
0
-
-
-
-
ns
ns
ns
WAIT setup (low or high) to
BFCLKI rising edge
3
0
-
-
WAIT hold (low or high) from
BFCLKI rising edge
Address
Phase(s)
Command
Phase(s)
Burst
Phase(s)
Burst
Phase(s)
Recovery
Phase(s)
Next Addr.
Phase(s)
BFCLKI
1)
BFCLKO
t10
t10
Next
Addr.
A[23:0]
Burst Start Address
t22
t22
t22
ADV
t21
t21
t21
CS[3:0]
CSCOMB
t12
t12
t22a
t24
RD
RD/WR
t22a
BAA
t24
t23
t23
D[31:0]
(32-Bit)
Data (Addr+0)
Data (Addr+4)
D[15:0]
(16-Bit)
Data (Addr+0)
Data (Addr+2)
t26
t25
WAIT
1)
Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRDWR_4.vsd
Figure 3-33 EBU Burst Mode Read / Write Access Timing
Data Sheet
3-440
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings
3.32.4
EBU Arbitration Signal Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5% ;
TA = -40°C to +125°C; CL = 35 pF;
Table 3-100 EBU Arbitration Timings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Output delay from BFCLKO
rising edge
t
t
27 CC
28 SR
-
-
-
-
4.5
ns
ns
ns
Data setup to BFCLKO falling
edge
15
2
-
-
Data hold from BFCLKO falling t29 SR
edge
BFCLKO
t27
t27
HLDA Output
BREQ Output
t27
t27
BFCLKO
t28
t29
t28
t29
HOLD Input
HLDA Input
EBUArb_1
Figure 3-34 EBU Arbitration Signal Timing
Data Sheet
3-441
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationCIF Parameters
3.33
CIF Parameters
CIF timings are valid only for temperatures up the TJ = 150°C.
Table 3-101 Timings for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
2.5
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
96 MHz
HSYNC, VSYNC set up time
AL input level,
hysteresis bypass
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TTL input level,
hysteresis bypass
6.5
4
TTL input level,
hysteresis on
AL input level,
hysteresis on
HSYNC, VSYNC hold time
Pixel data set up time
Pixel data hold time
t
t
t
72 SR
73 SR
74 SR
2.5
2.5
7
AL input level,
hysteresis bypass
TTL input level,
hysteresis bypass
TTL input level,
hysteresis on
4
AL input level,
hysteresis on
2.5
2
AL input level,
hysteresis bypass
TTL input level,
hysteresis bypass
6.5
4
TTL input level,
hysteresis on
AL input level,
hysteresis on
2.5
2.5
7
AL input level,
hysteresis bypass
TTL input level,
hysteresis bypass
TTL input level,
hysteresis on
4
AL input level,
hysteresis on
Data Sheet
3-442
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationCIF Parameters
Table 3-102 Timings for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
3.5
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
AL input level,
hysteresis bypass
4.5
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AL input level,
hysteresis on
TTL input level,
hysteresis on
3
TTL input level,
hysteresis bypass
HSYNC, VSYNC hold time
Pixel data set up time
Pixel data hold time
t
t
t
72 SR
73 SR
74 SR
4
AL input level,
hysteresis bypass
5
AL input level,
hysteresis on
10
3.5
3.5
4.5
9
TTL input level,
hysteresis on
TTL input level,
hysteresis bypass
AL input level,
hysteresis bypass
AL input level,
hysteresis on
TTL input level,
hysteresis on
3
TTL input level,
hysteresis bypass
4
AL input level,
hysteresis bypass
5
AL input level,
hysteresis on
10
3.5
TTL input level,
hysteresis on
TTL input level,
hysteresis bypass
Table 3-103 Timings for 0.4V to 2.4V input signals (2.8V imager)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel clock period
t
70 SR
10.42
-
-
ns
Data Sheet
3-443
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationCIF Parameters
Table 3-103 Timings for 0.4V to 2.4V input signals (2.8V imager) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
HSYNC, VSYNC set up time
t
t
t
t
71 SR
72 SR
73 SR
74 SR
3
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hysteresis Bypass,
3.3V±10%
9
-
-
-
-
-
-
-
-
-
-
-
TTL Input Levels,
3.3V±10%
4.5
3.5
10
5
TTL Input Levels,
5V±10%
HSYNC, VSYNC hold time
Pixel data set up time
Pixel data hold time
Hysteresis Bypass,
3.3V±10%
TTL Input Levels,
3.3V±10%
TTL Input Levels,
5V±10%
3
Hysteresis Bypass,
3.3V±10%
9
TTL Input Levels,
3.3V±10%
4.5
3.5
10
5
TTL Input Levels,
5V±10%
Hysteresis Bypass,
3.3V±10%
TTL Input Levels,
3.3V±10%
TTL Input Levels,
5V±10%
Table 3-104 Timings for 0.4V to 2.4V input signals (2.8V imager), ±5% pad power supply
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
3
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
Hysteresis Bypass,
3.3V±5%
9
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
TTL Input Levels,
3.3V±5%
4.5
3.5
10
5
TTL Input Levels,
5V±5%
HSYNC, VSYNC hold time
t
72 SR
Hysteresis Bypass,
3.3V±5%
TTL Input Levels,
3.3V±5%
TTL Input Levels,
5V±5%
Data Sheet
3-444
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationCIF Parameters
Table 3-104 Timings for 0.4V to 2.4V input signals (2.8V imager), ±5% pad power supply (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel data set up time
t
73 SR
3
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Hysteresis Bypass,
3.3V±5%
9
-
-
-
-
-
TTL Input Levels,
3.3V±5%
4.5
3.5
10
5
TTL Input Levels,
5V±5%
Pixel data hold time
t
74 SR
Hysteresis Bypass,
3.3V±5%
TTL Input Levels,
3.3V±5%
TTL Input Levels,
5V±5%
Table 3-105 Timings for 1.8V imager, TTL input level
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
10.42
3
Typ.
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
Input signal 0.1V to
1.7V
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input signal 0.2V to
1.6V
4.5
3.5
3.5
10
5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
HSYNC, VSYNC hold time
t
72 SR
Input signal 0.1V to
1.7V
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Pixel data set up time
t
73 SR
3
Input signal 0.1V to
1.7V
9
Input signal 0.2V to
1.6V
4.5
3.5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
Data Sheet
3-445
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationCIF Parameters
Table 3-105 Timings for 1.8V imager, TTL input level (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel data hold time
t
74 SR
3.5
-
-
-
-
-
ns
ns
ns
ns
Input signal 0.1V to
1.7V
10
5
-
-
-
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Table 3-106 Timings for 1.8V imager, 3.3V±5% pad power supply, TTL input level
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10.42
3
Max.
Pixel clock period
t
t
70 SR
71 SR
-
-
-
-
ns
ns
HSYNC, VSYNC set up time
Input signal 0.1V to
1.7V
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input signal 0.2V to
1.6V
4.5
3.5
3.5
10
5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
HSYNC, VSYNC hold time
t
72 SR
Input signal 0.1V to
1.7V
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Pixel data set up time
t
73 SR
3
Input signal 0.1V to
1.7V
9
Input signal 0.2V to
1.6V
4.5
3.5
Input signal 0.3V to
1.5V
Input signal 0.4V to
1.4V
Data Sheet
3-446
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationCIF Parameters
Table 3-106 Timings for 1.8V imager, 3.3V±5% pad power supply, TTL input level (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pixel data hold time
t
74 SR
3.5
-
-
-
-
-
ns
ns
ns
ns
Input signal 0.1V to
1.7V
10
5
-
-
-
Input signal 0.2V to
1.6V
Input signal 0.3V to
1.5V
4
Input signal 0.4V to
1.4V
Data Sheet
3-447
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationFlash Target Parameters
3.34
Flash Target Parameters
Program Flash program and erase operation is only allowed up the TJ = 150°C. Flash timing parameter are valid
for fFSI = 100 MHz.
Table 3-107 FLASH
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program Flash Erase Time per tERP CC
logical sector
-
-
-
1
-
s
s
cycle count < 1000
0.207 +
0.003 * (S
[KByte]) /
(fFSI
cycle count < 1000, for
sector of size S
[MHz])1)
Program Flash Erase Time per tMERP CC
Multi-Sector Command
-
-
-
1
-
s
s
Forconsecutivelogical
sectors in a physical
sector, cycle count <
1000
0.207 +
0.003 * (S
[KByte]) /
(fFSI
Forconsecutivelogical
sector range of size S
in a physical sector,
cycle count < 1000
[MHz])1)
Program Flash program time
per page in 5 V mode
t
t
t
t
PRP5 CC
PRP3 CC
PRPB5 CC
PRPB3 CC
-
-
-
-
-
-
-
-
-
-
50 +
3000/(fFSI
[MHz])
µs
µs
µs
µs
s
32 Byte
32 Byte
256 Byte
256 Byte
Program Flash program time
per page in 3.3 V mode
81 +
3400/(fFSI
[MHz])
Program Flash program time
per burst in 5 V mode
125 +
9500/(fFSI
[MHz])
Program Flash program time
per burst in 3.3 V mode
410 +
12000/(fF
SI [MHz])
Program Flash program time
for 1 MByte with burst
tPRPB5_1MB
CC
0.9
Derived value for
documentation
programming in 5 V mode
excluding communication
purpose, valid for fFSI
100MHz
=
=
Program Flash program time
for complete PFlash with burst CC
programming in 5 V mode
excluding communication
tPRPB5_PF
-
-
-
-
7.2
s
Derived value for
documentation
purpose, valid for fFSI
100MHz
Write Page Once adder
t
ADD CC
15 +
µs
Adder to Program
500/(fFSI
[MHz])
Time when using Write
Page Once
Data Sheet
3-448
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationFlash Target Parameters
Table 3-107 FLASH (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program Flash suspend to read tSPNDP CC
latency
-
-
12000/(fF µs
SI [MHz])
For Write Burst, Verify
Erased and for multi-
(logical) sector erase
commands
Data Flash Erase Time per
Sector 2)
t
t
ERD CC
-
-
-
0.12 +
0.08/(fFSI
[MHz])1)
-
s
s
s
cycle count < 1000
0.57 +
0.928 +
cycle count < 125000
0.15/(fFSI 0.15/(fFSI
[MHz])1)
[MHz])
Data Flash Erase Time per
Multi-Sector Command 2)
MERD CC
0.12 +
-
Forconsecutivelogical
sector range of size S,
cycle count < 1000
0.01 * (S
[KByte]) /
(fFSI
[MHz])1)
-
0.57 +
0.019 * (S 0.019 * (S
[KByte]) / [KByte]) /
0.928 +
s
Forconsecutivelogical
sector range of size S,
cycle count < 125000
(fFSI
(fFSI
[MHz])
[MHz])1)
Data Flash erase disturb limit
N
DFD CC
-
-
-
-
50
cycles
µs
Program time data flash per
page 3)
t
PRD CC
50 +
2500/(fFSI
[MHz]) 3)
8 Byte
Complete Device Flash Erase
Time PFlash and DFlash 4)
t
ER_Dev CC
-
-
-
-
17
s
Derived value for
documentation
purpose (excl. UCBs
and HSMs), valid for
f
FSI = 100MHz
Data Flash program time per
burst 3)
t
t
PRDB CC
96 +
4400/(fFSI
[MHz]) 3)
µs
32 Bytes
Data Flash suspend to read
latency
SPNDD CC
-
-
-
-
-
-
12000/(fF µs
SI [MHz])
Wait time after margin change tFL_MarginDel
-
10
-
µs
CC
Program Flash Retention Time, tRET CC
Sector
20
years
Max. 1000
erase/program cycles
Data Flash Endurance per
EEPROMx sector 5)
NE_EEP10
CC
125000
-
cycles Max. data retention
time 10 years
Data Flash Endurance per
HSMx sector 5)
N
E_HSM CC 125000
-
cycles Max. data retention
time 10 years
Data Sheet
3-449
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationFlash Target Parameters
Table 3-107 FLASH (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
UCB Retention Time
t
RTU CC
20
-
-
years
Max. 100
erase/program cycles
per UCB, max 400
erase/program cycles
in total
Data Flash access delay
Data Flash ECC Delay
t
t
t
t
DF CC
-
-
-
-
-
-
-
-
100
20
ns
ns
ns
ns
see
PMU_FCON.WSDFLA
SH
DFECC CC
see
PMU_FCON.WSECD
F
Program Flash access delay
Program Flash ECC delay
PF CC
30
see
PMU_FCON.WSPFLA
SH
PFECC CC
10
see
PMU_FCON.WSECP
F
Number of erase operations on NERD0 CC
DF0 over lifetime
-
-
-
-
-
-
750000
500000
150
cycles
cycles
°C
Number of erase operations on NERD1 CC
DF1 over lifetime
Junction temperature limit for
PFlash program/erase
operations
TJPFlash SR
1) All typical values were characterised, but are not tested. Typical values are safe median values at room temperature
2) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase
processes may be increased by up to 50%.
3) Time is not dependent on program mode (5V or 3.3V).
4) Using 512 KByte erase commands.
5) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
Data Sheet
3-450
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPackage Outline
3.35
Package Outline
292x
0.5 ±0 .0 5
M
0.15
0.08
C
C
A B
1.7 MAX
0.1 C
17 ±0.1
B
M
A
20
19
18
17
16
15
14
13
12
11
10
9
CODE
8
7
292x
0.15
6
5
4
3
COPLANARITY
2
1
Y W V U T R P N M L
K J HG F E D C B A
INDEX
INDEX MARKING
(LASERED )
0.8
MARKING
19 x 0.8 = 15.2
C
0.33 MIN
STANDOFF
Figure 3-35 Package Outlines LF-BGA-292-6 / LF-BGA-292-10
d
0.1 2x
25 x 1 .0 = 25
+0.07
27
2 .15 MAX
(0.56)
416 x
0.63
-0 .1 3
M
C A B
2x
0.1
1.0
0.25
0.1
B
d
M
C
(0.95)
26
25
24
23
22
21
20
416x
0.15
C
COPLANARITY
19
18
17
16
15
14
13
CODE
12
11
10
9
0.1
C
8
7
6
5
4
3
2
1
AF AD AB
Y W V U T R P N M L K J H G F E D C B A
AE
AC AA
INDEX MARKING
(LASERED)
1.0
0,41 MIN
STAND OFF
Figure 3-36 Package Outlines PG-BGA-416-26 / PG-BGA-416-29
Data Sheet
3-451
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPackage Outline
d
0.1 2x
29 x 0.8 = 23.2
516 x
25 ±0 .1
1.7 MAX
±0.05
0.5
2x
B
M
C
0.15
A B
0.8
d
0.1
M
0.08
C
30
29
28
27
26
0.8
516x
0.15
25
24
23
22
COPLANARITY
21
20
19
18
17
16
15
CODE
14
13
0.1
C
12
11
10
9
8
7
6
5
4
3
2
1
AJ AG AE AC AA Y W V U T
AH AF AD AB
R
P
N M
L
K
J
H G
F
E D C B A
INDEX
MARKING
AK
0.8
INDEX MARKING
(LASERED)
0,3 MIN
STAND OFF
Figure 3-37 Package Outlines PG-LFBGA-516-5 / PG-LFBGA-516-10
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
3.35.1
Package Parameters
Table 3-108 Thermal Characteristics of the Package
Device
Package
RQJCT1)
RQJCB1) RQJA
Unit
Note
TC297
LF-BGA-292-6 / LF-BGA-
292-10
3,0
4,3
5,4
4,3
15,1
12,8
15,1
K/W
TC298
TC299
PG-BGA-416-26 / PG-BGA- 2,9
416-29
K/W
K/W
PG-LFBGA-516-5 / PG-
LFBGA-516-10
2,8
1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the
thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal
resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT
,
R
TCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTJA * PD, where the RTJA is the total
thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from
the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
3.35.2
TC290 Carrier Tape
Data Sheet
3-452
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPackage Outline
Figure 3-38 Carrier Tape Dimenions
Table 3-109 TC290 Chip Dimenions
Device
A
B
T
TC290
8,770 mm
9,357 mm
0,3 mm
Data Sheet
3-453
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQuality Declarations
3.36
Quality Declarations
Table 3-110 Quality Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
24500
2000
Operation Lifetime
tOP
-
-
-
-
hour
V
ESD susceptibility according to VHBM
Conforming to
Human Body Model (HBM)
JESD22-A114-B
ESD susceptibility of the LVDS VHBM1
pins
-
-
-
-
500
500
V
V
ESD susceptibility according to VCDM
for all other balls/pins;
conforming to
Charged Device Model (CDM)
JESD22-C101-C
-
-
-
-
750
3
V
for corner balls/pins;
conforming to
JESD22-C101-C
Moisture Sensitivity Level
MSL
Conforming to Jedec
J-STD--020C for 240C
Data Sheet
3-454
V 1.1 2019-03
TC290 / TC297 / TC298 / TC299 BC-Step
HistoryChanges from TC29xBB_v1.1 to TC29xBC_v1.0
4
History
4.1
Changes from TC29xBB_v1.1 to TC29xBC_v1.0
•
VADC
–
–
–
Add parameter tWU
Add parameter RMDU
Add parameter RMDD
•
•
•
•
Changes in table 'Class LP 3.3V' of Standard_Pads
–
Change note of VILHLP from 'Hysteresis inactive; not available for P14.2, P14.4, and P15.1' to 'Hysteresis
inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11'
Changes in table 'Class LP 5V' of Standard_Pads
–
Change note of VILHLP from 'Hysteresis inactive; not available for P14.2, P14.4, and P15.1' to 'Hysteresis
inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11'
ERAY
Add statement ‘The timings of this section are valid for the strong driver and either sharp edge settings of
the output drivers with CL = 25 pF. For the inputs the hysteresis has to be configured to inactive.’
Package Outline
–
–
change values in table ‘TC290 Chip Dimenions’
4.2
Changes from v1.0 to v1.1
•
•
•
add package type version PG-LFBGA-516-10
add package type version PG-BGA-416-29
add package type version LF-BGA-292-10
Data Sheet
455
V 1.1 2019-03
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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