SAK-XC886C-6FFA [INFINEON]
8-Bit Single-Chip Microcontroller; 8位单芯片微控制器型号: | SAK-XC886C-6FFA |
厂家: | Infineon |
描述: | 8-Bit Single-Chip Microcontroller |
文件: | 总119页 (文件大小:1532K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet, V0.1, Feb. 2006
XC886/888CLM
8-Bit Single-Chip Microcontroller
Microcontrollers
Edition 2006-02
Published by Infineon Technologies AG,
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
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be endangered.
Data Sheet, V0.1, Feb. 2006
XC886/888CLM
8-Bit Single-Chip Microcontroller
Microcontrollers
XC886/888 Data Sheet
Revision History:
2006-02
V0.1
Previous Version:
Page
Subjects (major changes since last revision)
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8-Bit Single-Chip Microcontroller
XC886/888
1
Summary of Features
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 12 Kbytes of Boot ROM
– 256 bytes of RAM
– 1.5 Kbytes of XRAM
– 24/32 Kbytes of Flash; or
24/32 Kbytes of ROM, with additional 4 Kbytes of Flash
(includes memory protection strategy)
• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)
(more features on next page)
Flash or ROM1)
24K/32K x 8
On-Chip Debug Support
UART
SSC
Port 0
Port 1
Port 2
Port 3
Port 4
8-bit Digital I/O
8-bit Digital I/O
Boot ROM
12K x 8
Capture/Compare Unit
16-bit
XC800 Core
.
XRAM
1.5K x 8
Compare Unit
16-bit
8-bit Digital/
Analog Input
ADC
Watchdog
10-bit
RAM
256 x 8
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
8-bit Digital I/O
8-bit Digital I/O
Timer
8-channel
Timer 21
16-bit
MDU
CORDIC
MultiCAN
UART1
Port 5
8-bit Digital I/O
1) All ROM devices come with an additional 4K x 8 Flash
Figure 1
XC886/888 Functional Units
Data Sheet
Prelimary
1
V0.1, 2006-02
XC886/888CLM
Summary of Features
Features (continued):
• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Six ports
– 34/48 pins as digital I/O
– 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Four 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 and Timer 21
• Multiplication/Division Unit for arithmetic operations (MDU)
• CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear
functions
• MultiCAN with 2 nodes, 32 message objects (MCAN)
• Capture/compare unit for PWM signal generation (CCU6)
• Two full-duplex serial interfaces (UART and UART1)
• Synchronous serial channel (SSC)
• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM)
– 64 bytes of monitor RAM
• Packages:
– PG-TQFP-48
– PG-TQFP-64
• Temperature range TA:
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
Data Sheet
Prelimary
2
V0.1, 2006-02
XC886/888CLM
Summary of Features
XC886/888 Variant Devices
The XC886/888 product family features devices with different configurations, program
memory sizes, package options, temperature and quality profiles (Automotive or
Industrial), to offer cost-effective solutions for different application requirements.
The list of XC886/888 device configurations are summarized in Table 1. For each
configuration, 2 types of packages are available:
• PG-TQFP-48, which is denoted by XC886 and;
• PG-TQFP-64, which is denoted by XC888.
Table 1
Device Configuration
Device Name
CAN
Module
LIN BSL
Support
MDU
Module
XC886/888
No
No
No
XC886/888C
XC886/888CM
XC886/888LM
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
Yes
XC886/888CLM
Yes
From these 10 different combinations of configuration and package type, each are
further made available in 6 sales types, which are grouped according to program
memory sizes, temperature and quality profiles (Automotive or Industrial), as shown in
Table 2.
Table 2
Device Profile
Device
Type
Sales Type
ProgramMemory Temperature Quality
Size (Kbytes)
Profile (°C) Profile
SAK-XC886*/888*-8FFA Flash
SAK-XC886*/888*-6FFA Flash
SAF-XC886*/888*-8FFA Flash
SAF-XC886*/888*-6FFA Flash
32
24
32
24
32
24
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Automotive
Automotive
Automotive
Automotive
Industrial
SAF-XC886*/888*-8FFI
SAF-XC886*/888*-6FFI
Flash
Flash
Industrial
Note: The asterisk (*) above denotes the device configuration letters from Table 1.
Corresponding ROM derivatives will be available on request.
Data Sheet
Prelimary
3
V0.1, 2006-02
XC886/888CLM
Summary of Features
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code indentifies:
• The derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery
For the available ordering codes for the XC886/888, please refer to the “Product
Catalog Microcontrollers” which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
Prelimary
4
V0.1, 2006-02
XC886/888CLM
General Device Information
2
General Device Information
2.1
Block Diagram
XC886/888
Internal Bus
12-Kbyte
Boot ROM1)
P0.0 - P0.7
P1.0 - P1.7
P2.0 - P2.7
XC800 Core
256-byte RAM
+
64-byte monitor
RAM
T0 & T1
UART
TMS
MBC
RESET
VDDP
CORDIC
MDU
UART1
SSC
1.5-Kbyte XRAM
VSSP
VDDC
VSSC
24/32-Kbyte
Flash or ROM2)
WDT
Timer 2
Timer 21
CCU6
VAREF
VAGND
ADC
Clock Generator
XTAL1
XTAL2
OCDS
9.6 MHz
On-chip OSC
P3.0 - P3.7
P4.0 - P4.7
P5.0 - P5.7
PLL
MCAN
1) Includes 1-Kbyte monitor ROM
2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash
Figure 2
XC886/888 Block Diagram
Data Sheet
Prelimary
5
V0.1, 2006-02
XC886/888CLM
General Device Information
2.2
Logic Symbol
VDDP
VSSP
VDDP
VSSP
Port 0 8-Bit
Port 1 8-Bit
Port 2 8-Bit
Port 3 8-Bit
Port 4 8-Bit
Port 5 8-Bit
VAREF
VAGND
VAREF
VAGND
Port 0 7-Bit
Port 1 8-Bit
Port 2 8-Bit
Port 3 8-Bit
Port 4 3-Bit
RESET
MBC
RESET
MBC
XC886
XC888
TMS
TMS
XTAL1
XTAL2
XTAL1
XTAL2
VDDC
VSSC
VDDC
VSSC
Figure 3
XC886/888 Logic Symbol
Data Sheet
Prelimary
6
V0.1, 2006-02
XC886/888CLM
General Device Information
2.3
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25
P3.2
P3.3
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VAREF
VAGND
P2.6
P2.5
P2.4
P2.3
VSSP
VDDP
P2.2
P3.4
P3.5
RESET
VSSP
VDDP
MBC
P4.0
XC886
P2.
P4.1
1
P0.7
P2.0
P0.1
P0.3
1
2
3
4
5
6
7
8
9 10 11 12
Figure 4
XC886 Pin Configuration, PG-TQFP-48 Package (top view)
Data Sheet
Prelimary
7
V0.1, 2006-02
XC886/888CLM
General Device Information
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P3.2
P3.3
P3.4
P3.5
RESET
VSSP
VDDP
NC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VAREF
VAGND
P2.6
P2.5
P2.4
P2.3
VSSP
VDDP
P2.2
XC888
NC
P2.
MBC
P4.0
P4.1
P4.2
P0.7
P0.3
P0.4
1
P2.0
P0.1
P5.7
P5.6
P0.2
P0.0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Note: The pins shaded in blue are not available in the PG-TQFP-48 package.
Figure 5
XC888 Pin Configuration, PG-TQFP-64 Package (top view)
Data Sheet
Prelimary
8
V0.1, 2006-02
XC886/888CLM
General Device Information
2.4
Pin Definitions and Functions
Pin Definitions and Functions
Table 3
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P0
I/O
Port 0
Port 0 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, UART1, Timer 2,
Timer 21, MCAN and SSC.
P0.0
11/17
Hi-Z
TCK_0
JTAG Clock Input
T12HR_1
CCU6 Timer 12 Hardware Run
Input
CC61_1
Input/Output of Capture/
Compare channel 1
CLKOUT_0 Clock Output
RXDO_1
UART Transmit Data Output
P0.1
13/21
Hi-Z
TDI_0
T13HR_1
JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
RXD_1
RXDC1_0
UART Receive Data Input
MCAN Node 1 Receiver Input
COUT61_1 Output of Capture/Compare
channel 1
EXF2_1
Timer 2 External Flag Output
P0.2
P0.3
12/18
48/63
PU
CTRAP_2
TDO_0
TXD_1
CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Data Output/
Clock Output
MCAN Node 1 Transmitter
Output
TXDC1_0
Hi-Z
SCK_1
SSC Clock Input/Output
COUT63_1 Output of Capture/Compare
channel 3
RXDO1_0 UART1 Transmit Data Output
Data Sheet
Prelimary
9
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P0.4
P0.5
1/64
Hi-Z
MTSR_1
CC62_1
TXD1_0
SSC Master Transmit Output/
Slave Receive Input
Input/Output of Capture/
Compare channel 2
UART1 Transmit Data Output/
Clock Output
2/1
Hi-Z
MRST_1
SSC Master Receive Input/
Slave Transmit Output
EXINT0_0 External Interrupt Input 0
T2EX1_1
RXD1_0
Timer 21 External Trigger Input
UART1 Receive Data Input
COUT62_1 Output of Capture/Compare
channel 2
P0.6
P0.7
–/2
PU
PU
GPIO
47/62
CLKOUT_1 Clock Output
Data Sheet
Prelimary
10
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P1
I/O
Port 1
Port 1 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, Timer 0, Timer 1,
Timer 2, Timer 21, MCAN and SSC.
P1.0
P1.1
26/34
27/35
PU
PU
RXD_0
T2EX
RXDC0_0
UART Receive Data Input
Timer 2 External Trigger Input
MCAN Node 0 Receiver Input
EXINT3
T0_1
External Interrupt Input 3
Timer 0 Input
TDO_1
TXD_0
JTAG Serial Data Output
UART Transmit Data Output/
Clock Output
TXDC0_0
MCAN Node 0 Transmitter
Output
P1.2
P1.3
28/36
29/37
PU
PU
SCK_0
SSC Clock Input/Output
MTSR_0
SSC Master Transmit Output/
Slave Receive Input
MCAN Node 1 Transmitter
Output
TXDC1_3
MRST_0
P1.4
P1.5
30/38
31/39
PU
PU
SSC Master Receive Input/
Slave Transmit Output
EXINT0_1 External Interrupt Input 6
RXDC1_3 MCAN Node 1 Receiver Input
CCPOS0_1 CCU6 Hall Input 0
EXINT5
T1_1
External Interrupt Input 5
Timer 1 Input
EXF2_0
RXDO_0
Timer 2 External Flag Output
UART Transmit Data Output
Data Sheet
Prelimary
11
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P1.6
P1.7
8/10
PU
CCPOS1_1 CCU6 Hall Input 1
T12HR_0
CCU6 Timer 12 Hardware Run
Input
EXINT6_0 External Interrupt Input 6
RXDC0_2
T21_1
MCAN Node 0 Receiver Input
Timer 21 Input
9/11
PU
CCPOS2_1 CCU6 Hall Input 2
T13HR_0
CCU6 Timer 13 Hardware Run
Input
T2_1
Timer 2 Input
TXDC0_2
MCAN Node 0 Transmitter
Output
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
Data Sheet
Prelimary
12
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P2
I
Port 2
Port 2 is an 8-bit general purpose input-only
port. It can be used as alternate functions for
the digital inputs of the JTAG and CCU6. It is
also used as the analog inputs for the ADC.
P2.0
14/22
Hi-Z
CCPOS0_0 CCU6 Hall Input 0
EXINT1_0 External Interrupt Input 1
T12HR_2
CCU6 Timer 12 Hardware Run
Input
TCK_1
CC61_3
JTAG Clock Input
Input of Capture/Compare
channel 1
AN0
Analog Input 0
P2.1
15/23
Hi-Z
CCPOS1_0 CCU6 Hall Input 1
EXINT2_0 External Interrupt Input 2
T13HR_2
CCU6 Timer 13 Hardware Run
Input
TDI_1
CC62_3
JTAG Serial Data Input
Input of Capture/Compare
channel 2
AN1
Analog Input 1
P2.2
16/24
Hi-Z
CCPOS2_0 CCU6 Hall Input 2
CTRAP_1
CC60_3
CCU6 Trap Input
Input of Capture/Compare
channel 0
AN2
AN3
AN4
AN5
AN6
AN7
Analog Input 2
P2.3
P2.4
P2.5
P2.6
P2.7
19/27
20/28
21/29
22/30
25/33
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Analog Input 3
Analog Input 4
Analog Input 5
Analog Input 6
Analog Input 7
Data Sheet
Prelimary
13
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P3
I/O
Port 3
Port 3 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, UART1, Timer 21 and MCAN.
P3.0
P3.1
35/43
36/44
Hi-Z
Hi-Z
CCPOS1_2 CCU6 Hall Input 1
CC60_0
Input/Output of Capture/
Compare channel 0
RXDO1_1 UART1 Transmit Data Output
CCPOS0_2 CCU6 Hall Input 0
CC61_2
Input/Output of Capture/
Compare channel 1
COUT60_0 Output of Capture/Compare
channel 0
TXD1_1
UART1 Transmit Data Output/
Clock Output
P3.2
37/49
Hi-Z
CCPOS2_2 CCU6 Hall Input 2
RXDC1_1
RXD1_1
CC61_0
MCAN Node 0 Receiver Input
UART1 Receive Data Input
Input/Output of Capture/
Compare channel 1
P3.3
P3.4
P3.5
38/50
39/51
40/52
Hi-Z
Hi-Z
Hi-Z
COUT61_0 Output of Capture/Compare
channel 1
TXDC1_1
MCAN Node 1 Transmitter
Output
CC62_0
Input/Output of Capture/
Compare channel 2
RXDC0_1
T2EX1_0
MCAN Node 0 Receiver Input
Timer 21 External Trigger Input
COUT62_0 Output of Capture/Compare
channel 2
EXF21_0
TXDC0_1
Timer 21 External Flag Output
MCAN Node 0 Transmitter
Output
P3.6
33/41
PD
CTRAP_0
CCU6 Trap Input
Data Sheet
Prelimary
14
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P3.7
34/42
Hi-Z
EXINT4
External Interrupt Input 4
COUT63_0 Output of Capture/Compare
channel 3
P4
I/O
Port 4
Port 4 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, Timer 0, Timer 1, Timer 21 and
MCAN.
P4.0
P4.1
45/59
46/60
Hi-Z
Hi-Z
RXDC0_3
CC60_1
MCAN Node 0 Receiver Input
Output of Capture/Compare
channel 0
TXDC0_3
MCAN Node 0 Transmitter
Output
COUT60_1 Output of Capture/Compare
channel 0
P4.2
P4.3
–/61
PU
EXINT6_1 External Interrupt Input 6
T21_0
Timer 21 Input
32/40
Hi-Z
EXF21_1
Timer 21 External Flag Output
COUT63_2 Output of Capture/Compare
channel 3
P4.4
P4.5
P4.6
P4.7
–/45
–/46
–/47
–/48
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CCPOS0_3 CCU6 Hall Input 0
T0_0
Timer 0 Input
CC61_4
Output of Capture/Compare
channel 1
CCPOS1_3 CCU6 Hall Input 1
T1_0 Timer 1 Input
COUT61_2 Output of Capture/Compare
channel 1
CCPOS2_3 CCU6 Hall Input 2
T2_0
Timer 2 Input
CC62_2
Output of Capture/Compare
channel 2
CTRAP_3
CCU6 Trap Input
COUT62_2 Output of Capture/Compare
channel 2
Data Sheet
Prelimary
15
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P5
I/O
Port 5
Port 5 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART, UART1 and JTAG.
P5.0
P5.1
P5.2
P5.3
–/8
PU
PU
PU
PU
EXINT1_1 External Interrupt Input 1
EXINT2_1 External Interrupt Input 2
–/9
–/12
–/13
RXD_2
TXD_2
UART Receive Data Input
UART Transmit Data Output/
Clock Output
P5.4
P5.5
–/14
–/15
PU
PU
RXDO_2
UART Transmit Data Output
TDO_2
TXD1_2
JTAG Serial Data Output
UART1 Transmit Data Output/
Clock Output
P5.6
P5.7
VDDP
–/19
–/20
PU
PU
–
TCK_2
JTAG Clock Input
RXDO1_2 UART1 Transmit Data Output
TDI_2
RXD1_2
JTAG Serial Data Input
UART1 Receive Data Input
7, 17, 43/
7, 25, 55
–
I/O Port Supply (3.3 or 5.0 V)
VSSP
VDDC
VSSC
18, 42/26, 54
–
–
–
–
–
I
–
I/O Port Ground
6/6
5/5
–
Core Supply Monitor (2.5 V)
Core Supply Ground
ADC Reference Voltage
ADC Reference Ground
–
VAREF 24/32
VAGND 23/31
XTAL1 4/4
–
–
Hi-Z
External Oscillator Input
(backup for on-chip OSC, normally NC)
XTAL2 3/3
O
Hi-Z
External Oscillator Output
(backup for on-chip OSC, normally NC)
TMS
10/16
I
PD
PU
PU
–
Test Mode Select
RESET 41/53
I
Reset Input
MBC
NC
44/58
I
Monitor & BootStrap Loader Control
No Connection
–/21, 59, 60
–
Data Sheet
Prelimary
16
V0.1, 2006-02
XC886/888CLM
Functional Description
3
Functional Description
3.1
Processor Architecture
The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU)
that is compatible with the standard 8051 processor. While the standard 8051 processor
is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock
machine cycle. This allows fast access to ROM or RAM memories without wait state.
Access to the Flash memory, however, requires an additional wait state (one machine
cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte
instructions.
The XC886/888 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and SFRs.
Figure 6 shows the CPU functional blocks.
Data Sheet
Prelimary
17
V0.1, 2006-02
XC886/888CLM
Functional Description
Internal Data
Memory
Core SFRs
Register Interface
External Data
Memory
External SFRs
16-bit Registers &
Memory Interface
ALU
Program Memory
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
fCCLK
Memory Wait
Reset
State Machine &
Power Saving
UART
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Interrupt
Controller
Non-Maskable Interrupt
Figure 6
3.2
CPU Block Diagram
Memory Organization
The XC886/888 CPU operates in the following five address spaces:
• 12 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 1.5 Kbytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
• a 128-byte Special Function Register area
• 24/32 Kbytes of Flash program memory (Flash devices); or
24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash
(ROM devices)
Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the
24-Kbyte Flash devices, the shaded banks are not available.
Data Sheet
Prelimary
18
V0.1, 2006-02
XC886/888CLM
Functional Description
FFFFH
F600H
FFFFH
F600H
1)
In 24-Kbyte Flash devices, the upper 2-
Kbyte of Banks 4 and 5 are not available.
XRAM
XRAM
1.5 Kbytes
1.5 Kbytes
F000H
F000H
Boot ROM
12 Kbytes
C000H
B000H
A000H
D-Flash Bank 1
4 Kbytes
D-Flash Bank 0
4 Kbytes
8000H
7000H
D-Flash Bank 0
4 Kbytes
D-Flash Bank 1
4 Kbytes
6000H
5000H
4000H
Indirect
Address
Direct
Address
P-Flash Banks 4 and 5
2 x 4 Kbytes1)
FFH
Special Function
Registers
Internal RAM
P-Flash Banks 2 and 3
2 x 4 Kbytes
80H
2000H
0000H
7FH
00H
P-Flash Banks 0 and 1
2 x 4 Kbytes
Internal RAM
0000H
Program Space
External Data Space
Internal Data Space
Figure 7
Memory Map of XC886/888 Flash Device
Data Sheet
Prelimary
19
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.1
Memory Protection Strategy
The XC886/888 memory protection strategy includes:
• Read-out protection: The user is able to protect the contents in the Flash (for Flash
devices) and ROM (for ROM devices) memory from being read
• Flash program and erase protection (for Flash devices only)
Flash memory protection modes are available only for Flash devices:
• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 4.
Table 4
Flash Protection Modes
Mode
0
1
Activation
Selection
Program a valid password via BSL mode 6
MSB of password = 0 MSB of password = 1
P-Flashcontents Read instructions in the
can be read by P-Flash
Read instructions in the
P-Flash or D-Flash
P-Flash program Not possible
Not possible
and erase
D-Flashcontents Read instructions in any program
Read instructions in the
P-Flash or D-Flash
can be read by
D-Flash program Possible
D-Flash erase Possible, on the condition that bit
memory
Not possible
Not possible
DFLASHEN in register MISC_CON
is set to 1 prior to each erase
operation
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. A
password match triggers an automatic erase of the protected P-Flash and D-Flash
contents, including the programmed password. The Flash protection is then disabled
upon the next reset.
Although no protection scheme can be considered infallible, the XC886/888 memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Data Sheet
Prelimary
20
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.2
Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
• Mapping
• Paging
3.2.2.1 Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number
of addressable SFRs to 256. The extended address range is not directly controlled by
the CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.
SYSCON0
System Control Register 0
Reset Value: 00H
7
6
5
4
3
2
1
0
0
IMODE
0
RMAP
r
rw
r
rw
The functions of the shaded bits are not described here
Field
RMAP
Bits
Type Description
rw Special Function Register Map Control
0
0
The access to the standard SFR area is
enabled.
1
The access to the mapped SFR area is
enabled.
0
[7:5],
[3:1]
r
Reserved
Returns 0 if read; should be written with 0.
Data Sheet
Prelimary
21
V0.1, 2006-02
XC886/888CLM
Functional Description
Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of
SYSCON0 should not be modified.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
Standard Area (RMAP = 0)
FFH
Module 1 SFRs
SYSCON0.RMAP
Module 2 SFRs
rw
Module n SFRs
80H
FFH
SFR Data
(to/from CPU)
Mapped Area (RMAP = 1)
Module (n+1) SFRs
Module (n+2) SFRs
Module m SFRs
80H
Direct
Internal Data
Memory Address
Figure 8
Address Extension by Mapping
Data Sheet
Prelimary
22
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.2.2 Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC886/888 has a 256-SFR address range. However, this is
still less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 9.
SFR Address
(from CPU)
PAGE 0
MOD_PAGE.PAGE
rw
SFR0
SFR1
SFRx
PAGE 1
SFR0
SFR Data
(to/from CPU)
SFR1
SFRy
PAGE q
SFR0
SFR1
SFRz
Module
Figure 9
Address Extension by Paging
Data Sheet
Prelimary
23
V0.1, 2006-02
XC886/888CLM
Functional Description
In order to access a register located in a page different from the actual one, the current
page must be left. This is done by reprogramming the bit field PAGE in the page register.
Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and finally, the old page
setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and
restore action of the current page setting. By indicating which storage bit field should be
used in parallel with the new page value, a single write operation can:
• Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to
the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
PAGE
value update
from CPU
Figure 10
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC886/888 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers
Data Sheet
Prelimary
24
V0.1, 2006-02
XC886/888CLM
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
Reset Value: 00H
7
6
5
4
3
2
1
0
OP
STNR
0
PAGE
w
w
r
rw
Field
Bits Type Description
[2:0] rw Page Bits
PAGE
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10 ,
B
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11 ,
B
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
Data Sheet
Prelimary
25
V0.1, 2006-02
XC886/888CLM
Functional Description
Field
OP
Bits Type Description
[7:6] w Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
Data Sheet
Prelimary
26
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.3
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11 , writing 10011 to the
Bit Protection Scheme
B
B
bit field PASS opens access to writing of all protected bits, and writing 10101 to the bit
B
field PASS closes access to writing of all protected bits. Note that access is opened for
maximum 32 CCLKs if the “close access” password is not written. If “open access”
password is written again before the end of 32 CCLK cycles, there will be a recount of
32 CCLK cycles. The protected bits include the N- and K-Divider bits, NDIV and KDIV;
the Watchdog Timer enable bit, WDTEN; and the power-down and slow-down enable
bits, PD and SD.
PASSWD
Password Register
Reset Value: 07H
7
6
5
4
3
2
1
0
PROTECT
_S
PASS
MODE
wh
rh
rw
Field
Bits Type Description
[1:0] rw Bit Protection Scheme Control bits
MODE
00
11
Scheme Disabled
Scheme Enabled (default)
Others: Scheme Enabled
These two bits cannot be written directly. To change
the value between 11 and 00 , the bit field PASS
B
B
must be written with 11000 ; only then, will the
B
MODE[1:0] be registered.
PROTECT_S
PASS
2
rh
Bit Protection Signal Status bit
This bit shows the status of the protection.
0
1
Software is able to write to all protected bits.
Software is unable to write to any protected
bits.
[7:3] wh
Password bits
The Bit Protection Scheme only recognizes three
patterns.
11000 Enables writing of the bit field MODE.
B
10011 Opens access to writing of all protected bits.
B
10101 Closes access to writing of all protected bits.
B
Data Sheet
Prelimary
27
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.4
XC886/888 Register Overview
The SFRs of the XC886/888 are organized into groups according to their functional units.
The contents (bits) of the SFRs are summarized in Table 5 to Table 18, with the
addresses of the bitaddressable SFRs appearing in bold typeface.
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 5
CPU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
81
82
83
87
88
89
SP
Reset: 07
Reset: 00
Reset: 00
Bit Field
Type
SP
rw
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Stack Pointer Register
DPL
Bit Field
Type
DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0
rw rw rw rw rw rw rw rw
DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0
Data Pointer Register Low
DPH
Bit Field
Type
Data Pointer Register High
rw
SMOD
rw
rw
rw
0
rw
rw
GF1
rw
rw
GF0
rw
IT1
rw
0
rw
0
rw
IDLE
rw
PCON
Power Control Register
Reset: 00
Bit Field
Type
r
r
TCON
Timer Control Register
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
Type
TF1
TR1
rw
0
TF0
rwh
TR0
rw
IE1
IE0
rwh
IT0
rw
rwh
rwh
TMOD
Timer Mode Register
Bit Field
Type
GATE1
rw
T1M
rw
GATE0
rw
T0M
rw
r
r
8A
8B
TL0
Bit Field
Type
VAL
H
Timer 0 Register Low
rwh
VAL
rwh
VAL
rwh
VAL
rwh
TL1
Bit Field
Type
H
Timer 1 Register Low
8C
8D
TH0
Bit Field
Type
H
Timer 0 Register High
TH1
Bit Field
Type
H
Timer 1 Register High
98
SCON
Bit Field
Type
SM0
rw
SM1
rw
SM2
rw
REN
rw
TB8
rw
RB8
rwh
TI
RI
H
Serial Channel Control Register
rwh
rwh
99
SBUF
Reset: 00
Bit Field
Type
VAL
rwh
TRAP_
H
Serial Data Buffer Register
A2
EO
Reset: 00
Bit Field
0
0
DPSEL
0
H
Extended Operation Register
EN
Type
r
0
r
rw
r
rw
EX0
rw
A8
B8
IEN0
Reset: 00
Bit Field
Type
EA
rw
ET2
rw
ES
rw
ET1
rw
EX1
rw
ET0
rw
H
H
H
H
Interrupt Enable Register 0
IP
Reset: 00
Bit Field
Type
0
PT2
rw
PS
rw
PT1
rw
PX1
rw
PT0
rw
PX0
rw
H
Interrupt Priority Register
r
0
r
B9
D0
IPH
Reset: 00
Bit Field
Type
PT2H PSH PT1H PX1H PT0H PX0H
H
H
H
H
Interrupt Priority Register High
rw
F0
rw
rw
RS1
rw
rw
RS0
rw
rw
OV
rwh
rw
F1
rw
rw
P
PSW
Reset: 00
Bit Field
Type
CY
AC
H
H
H
Program Status Word Register
rwh
rwh
rh
E0
E8
ACC
Reset: 00
Bit Field
Type
ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
rw rw rw rw rw rw rw rw
ECCIP ECCIP ECCIP ECCIP EXM EX2 ESSC EADC
Accumulator Register
IEN1
Reset: 00
Bit Field
Interrupt Enable Register 1
3
2
1
0
Type
rw
rw
rw
rw
rw
rw
rw
rw
Data Sheet
Prelimary
28
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 5
CPU Register Overview (cont’d)
Addr Register Name
Bit
Bit Field
7
B7
rw
6
B6
rw
5
B5
rw
4
B4
rw
3
B3
2
B2
1
B1
0
B0
F0
B
Reset: 00
H
H
H
B Register
Type
rw
rw
rw
rw
F8
IP1
Reset: 00
Bit Field
PCCIP PCCIP PCCIP PCCIP PXM
3
PX2 PSSC PADC
rw rw rw
H
Interrupt Priority Register 1
2
1
0
Type
rw
rw
rw
rw
rw
F9
IPH1
Reset: 00
Bit Field
PCCIP PCCIP PCCIP PCCIP PXMH PX2H PSSCH PADC
H
H
Interrupt Priority Register 1 High
3H
2H
1H
0H
H
Type
rw
rw
rw
rw
rw
rw
rw
rw
The MDU SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6 MDU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
B0
MDUSTAT
MDU Status Register
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
Type
0
r
BSY
rh
IERR IRDY
rwh rwh
H
H
H
H
H
H
H
H
H
H
H
H
H
H
B1
B2
MDUCON
MDU Control Register
Bit Field
Type
IE
rw
IR
rw
RSEL START
OPCODE
rw
rw
rwh
DATA
MD0
Bit Field
Type
MDU Data Register 0
rw
DATA
rh
MR0
Bit Field
Type
MDU Data Register 0
B3
B4
B5
B6
MD1
Bit Field
Type
DATA
rw
H
H
H
H
MDU Data Register 1
MR1
Bit Field
Type
DATA
rh
MDU Data Register 1
MD2
Bit Field
Type
DATA
rw
MDU Data Register 2
MR2
Bit Field
Type
DATA
rh
MDU Data Register 2
MD3
Bit Field
Type
DATA
rw
MDU Data Register 3
MR3
Bit Field
Type
DATA
rh
MDU Data Register 3
MD4
Bit Field
DATA
MDU Data Register 4
Multiplication/Division
Shift/Normalization
Type
rw
0
SLR
rw
SCTR
rw
rw
MR4
Reset: 00
Bit Field
Type
DATA
rh
H
MDU Data Register 4
Multiplication/Division
Shift/Normalization
0
SCTR
rh
rh
B7
MD5
Reset: 00
Reset: 00
Bit Field
Type
DATA
rw
H
H
MDU Data Register 5
MR5
Bit Field
Type
DATA
rh
H
MDU Data Register 5
Data Sheet
Prelimary
29
V0.1, 2006-02
XC886/888CLM
Functional Description
The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 7 CORDIC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
9A
CD_CORDXL
CORDIC X Data Low Byte
Reset: 00
Reset: 00
Bit Field
Type
DATAL
H
H
H
H
H
H
H
H
rw
DATAH
rw
9B
CD_CORDXH
CORDIC X Data High Byte
Bit Field
Type
H
9C
9D
CD_CORDYL
CORDIC Y Data Low Byte
Reset: 00
Bit Field
Type
DATAL
rw
H
H
H
H
CD_CORDYH
CORDIC Y Data High Byte
Reset: 00
Bit Field
Type
DATAH
rw
9E
9F
CD_CORDZL
CORDIC Z Data Low Byte
Reset: 00
Bit Field
Type
DATAL
rw
CD_CORDZH
CORDIC Z Data High Byte
Reset: 00
Bit Field
Type
DATAH
rw
A0
CD_STATC
CORDIC Status and Data Control
Register
Reset: 00
Bit Field
KEEPZ KEEPY KEEPX DMAP INT_E EOC ERRO BSY
H
H
N
R
Type
rw
rw
rw
rw
rw
rwh
rh
rh
A1
CD_CON
CORDIC Control Register
Reset: 00
Bit Field
MPS
rw
X_USI ST_MO ROTVE
MODE
ST
H
GN
DE
C
Type
w
rw
rw
rw
rwh
The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 8 System Control Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
8F
SYSCON0
System Control Register 0
Reset: 00
Reset: 00
Reset: 00
Bit Field
Type
0
r
IMODE
rw
0
r
RMAP
rw
H
H
RMAP = 0
BF
SCU_PAGE
Bit Field
Type
OP
w
STNR
0
r
PAGE
rw
H
H
Page Register
w
RMAP = 0, PAGE 0
B3
B4
B5
B6
B7
MODPISEL
Peripheral Input Select Register
Bit Field
0
URRIS JTAGT JTAGT EXINT EXINT EXINT URRIS
H
H
H
H
H
H
H
H
H
H
DIS
CKS
2IS
1IS
0IS
Type
r
rw
rw
rw
rw
rw
rw
rw
IRCON0
Interrupt Request Register 0
Reset: 00
Bit Field
0
EXINT EXINT EXINT EXINT EXINT EXINT EXINT
6
5
4
3
2
1
0
Type
r
rwh
rwh
rwh
rwh
rwh
RIR
rwh
TIR
rwh
EIR
IRCON1
Interrupt Request Register 1
Reset: 00
Bit Field
0
CANS CANS ADCS ADCS
RC2
rwh
0
RC1
RC1
RC0
Type
r
rwh
rwh
rwh
rwh
0
rwh
rwh
IRCON2
Interrupt Request Register 2
Reset: 00
Bit Field
CANS
RC3
CANS
RC0
Type
r
rwh
r
rwh
EXICON0
External Interrupt Control Register 0
Reset: F0
Bit Field
Type
EXINT3
EXINT2
EXINT1
EXINT0
H
H
rw
0
rw
EXINT6
rw
rw
EXINT5
rw
rw
EXINT4
rw
BA
EXICON1
External Interrupt Control Register 1
Reset: 3F
Bit Field
Type
H
r
Data Sheet
Prelimary
30
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 8
System Control Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
BB
NMICON
NMI Control Register
Reset: 00
Reset: 00
Reset: 00
Bit Field
0
NMI
NMI
NMI
NMI
NMI
NMI
NMI
WDT
H
H
ECC VDDP VDD OCDS FLASH PLL
Type
r
rw rw rw rw rw rw
rw
BC
NMISR
NMI Status Register
Bit Field
0
FNMI FNMI FNMI FNMI FNMI FNMI FNMI
ECC VDDP VDD OCDS FLASH PLL
H
H
WDT
rwh
R
Type
r
rwh
BGSEL
rw
rwh
rwh
BRDIS
rw
rwh
rwh
BRPRE
rw
rwh
BD
BCON
Bit Field
Type
0
r
H
H
H
H
H
H
Baud Rate Control Register
rw
BE
BG
Reset: 00
Bit Field
Type
BR_VALUE
rwh
Baud Rate Timer/Reload Register
E9
FDCON
Reset: 00
Bit Field
BGS SYNEN ERRSY EOFSY BRK NDOV FDM FDEN
Fractional Divider Control Register
N
N
Type
rw
rw
rwh
rwh
rwh
rwh
rw
rw
EA
EB
FDSTEP
Fractional Divider Reload Register
Reset: 00
Bit Field
Type
STEP
H
H
rw
RESULT
rh
FDRES Reset: 00
Fractional Divider Result Register
Bit Field
Type
H
H
RMAP = 0, PAGE 1
B3
B4
ID
Reset: 09
Reset: 00
Bit Field
Type
PRODID
r
VERID
r
H
H
Identity Register
PMCON0
Power Mode Control Register 0
Bit Field
0
WDT WKRS WK
SD
rw
PD
WS
H
H
RST
SEL
Type
r
rwh
rwh
rw
rwh
rw
B5
B6
B7
PMCON1
Power Mode Control Register 1
Reset: 00
Bit Field
0
CDC_D CAN_D MDU_ T2_DIS CCU
SSC
_DIS
ADC
_DIS
H
H
H
H
H
H
H
H
IS
rw
0
IS
DIS
_DIS
Type
r
rw
rw
rw
rw
rw
rw
OSC_CON
OSC Control Register
Reset: 08
Bit Field
OSC
PD
XPD
OSC ORDR OSCR
SS
ES
Type
r
rw
rw
rw
rwh
rh
PLL_CON
PLL Control Register
Reset: 90
Reset: 10
Reset: 07
Reset: 00
Bit Field
NDIV
rw
VCOB OSC RESLD LOCK
YP
DISC
Type
rw
rw
rwh
rh
BA
CMCON
Clock Control Register
Bit Field
VCO
SEL
KDIV
0
FCCFG
rw
CLKREL
H
H
Type
rw
rw
r
rw
PROTE
BB
PASSWD
Password Register
Bit Field
PASS
MODE
rw
CT_S
Type
wh
rh
BC
BD
FEAL
Bit Field
Type
ECCERRADDR
H
H
H
H
H
H
Flash Error Address Register Low
rh
ECCERRADDR
rh
FEAH Reset: 00
Bit Field
Type
Flash Error Address Register High
COCON Reset: 00
BE
Bit Field
0
r
TLEN COUT
S
COREL
rw
Clock Output Control Register
Type
rw
rw
0
E9
MISC_CON
Reset: 00
Bit Field
DFLAS
H
H
Miscellaneous Control Register
HEN
Type
r
rwh
RMAP = 0, PAGE 3
B3
XADDRH
Reset: F0
Bit Field
Type
ADDRH
rw
H
H
On-chip XRAM Address Higher Order
Data Sheet
Prelimary
31
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 8
System Control Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
B4
B5
B7
IRCON3
Interrupt Request Register 3
Reset: 00
Bit Field
0
CANS CCU6S
0
CANS CCU6S
H
H
H
H
H
H
RC5
R1
RC4
R0
Type
r
rwh
rwh
r
rwh
rwh
IRCON4
Interrupt Request Register 4
Reset: 00
Bit Field
0
CANS CCU6S
0
CANS CCU6S
RC7
R3
RC6
R2
Type
r
rwh
rwh
r
rwh
rwh
MODPISEL1
Peripheral Input Select Register 1
Reset: 00
Bit Field
EXINT
6IS
0
UR1RIS
T21EXI JTAGT JTAGT
S
DIS1 CKS1
Type
rw
r
0
r
rw
rw
rw
T1IS
rw
rw
T0IS
rw
BA
BB
MODPISEL2
Peripheral Input Select Register 2
Reset: 00
Bit Field
Type
T21IS T2IS
H
H
H
rw
rw
PMCON2
Reset: 00
Bit Field
0
r
UART1 T21
H
Power Mode Control Register 2
_DIS
_DIS
Type
rw
rw
BD
MODSUSP
Module Suspend Control Register
Reset: 00
Bit Field
0
r
T21SU T2SUS T13SU T12SU WDTS
H
H
SP
P
SP
SP
USP
Type
rw
rw
rw
rw
rw
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 9 WDT Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
BB
WDTCON
Watchdog Timer Control Register
Reset: 00
Bit Field
0
r
WINB WDT
0
WDT
EN
WDT
RS
WDT
IN
H
H
EN
PR
Type
rw
rh
r
rw
rwh
rw
BC
BD
WDTREL
Watchdog Timer Reload Register
Reset: 00
Bit Field
Type
WDTREL
rw
H
H
H
WDTWINB
Reset: 00
Bit Field
WDTWINB
H
Watchdog Window-Boundary Count
Register
Type
rw
WDT[7:0]
rh
BE
WDTL
Reset: 00
Bit Field
Type
H
H
Watchdog Timer Register Low
BF
WDTH
Reset: 00
Bit Field
Type
WDT[15:8]
rh
H
H
Watchdog Timer Register High
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10 Port Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
B2
PORT_PAGE
Page Register for PORT
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
RMAP = 0, Page 0
80
86
90
P0_DATA
P0 Data Register
Reset: 00
Reset: 00
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
P0_DIR
P0 Direction Register
Bit Field
Type
P1_DATA
P1 Data Register
Bit Field
Type
Data Sheet
Prelimary
32
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
91
92
93
P1_DIR
P1 Direction Register
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
H
H
H
H
H
Type
P5_DATA
P5 Data Register
Bit Field
Type
P5_DIR
P5 Direction Register
Bit Field
Type
A0
P2_DATA
P2 Data Register
Bit Field
Type
H
H
A1
B0
P2_DIR
P2 Direction Register
Bit Field
Type
P3_DATA
P3 Data Register
Bit Field
Type
H
B1
P3_DIR
P3 Direction Register
Bit Field
Type
H
C8
P4_DATA
P4 Data Register
Bit Field
Type
H
C9
P4_DIR
P4 Direction Register
Bit Field
Type
H
RMAP = 0, Page 1
80
86
90
91
92
93
P0_PUDSEL
P0 Pull-Up/Pull-Down Select Register
Reset: FF
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
P0_PUDEN Reset: C4
P0 Pull-Up/Pull-Down Enable Register
Bit Field
Type
H
P1_PUDSEL Reset: FF
P1 Pull-Up/Pull-Down Select Register
Bit Field
Type
H
P1_PUDEN Reset: FF
P1 Pull-Up/Pull-Down Enable Register
Bit Field
Type
H
P5_PUDSEL Reset: FF
P5 Pull-Up/Pull-Down Select Register
Bit Field
Type
H
P5_PUDEN Reset: FF
P5 Pull-Up/Pull-Down Enable Register
Bit Field
Type
H
A0
P2_PUDSEL Reset: FF
P2 Pull-Up/Pull-Down Select Register
Bit Field
Type
H
H
A1
P2_PUDEN Reset: 00
P2 Pull-Up/Pull-Down Enable Register
Bit Field
Type
H
H
B0
P3_PUDSEL Reset: BF
P3 Pull-Up/Pull-Down Select Register
Bit Field
Type
H
H
B1
P3_PUDEN Reset: 40
P3 Pull-Up/Pull-Down Enable Register
Bit Field
Type
H
H
C8
P4_PUDSEL Reset: FF
P4 Pull-Up/Pull-Down Select Register
Bit Field
Type
H
H
C9
P4_PUDEN Reset: 04
P4 Pull-Up/Pull-Down Enable Register
Bit Field
Type
H
H
RMAP = 0, Page 2
80
86
90
P0_ALTSEL0
P0 Alternate Select 0 Register
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
P0_ALTSEL1
P0 Alternate Select 1 Register
Reset: 00
Bit Field
Type
P1_ALTSEL0
P1 Alternate Select 0 Register
Reset: 00
Bit Field
Type
Data Sheet
Prelimary
33
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
91
92
93
P1_ALTSEL1
P1 Alternate Select 1 Register
Reset: 00
Bit Field
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
H
H
H
Type
P5_ALTSEL0
P5 Alternate Select 0 Register
Reset: 00
Bit Field
Type
P5_ALTSEL1
P5 Alternate Select 1 Register
Reset: 00
Bit Field
Type
B0
P3_ALTSEL0
P3 Alternate Select 0 Register
Reset: 00
Bit Field
Type
H
B1
P3_ALTSEL1
P3 Alternate Select 1 Register
Reset: 00
Bit Field
Type
H
C8
P4_ALTSEL0
P4 Alternate Select 0 Register
Reset: 00
Bit Field
Type
H
C9
P4_ALTSEL1
P4 Alternate Select 1 Register
Reset: 00
Bit Field
Type
H
RMAP = 0, Page 3
80
90
92
P0_OD
Reset: 00
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
H
H
H
H
H
H
H
H
P0 Open Drain Control Register
P1_OD
Reset: 00
Bit Field
Type
P1 Open Drain Control Register
P5_OD
Reset: 00
Bit Field
Type
P5 Open Drain Control Register
B0
C8
P3_OD
Reset: 00
Bit Field
Type
H
H
P3 Open Drain Control Register
P4_OD
Reset: 00
Bit Field
Type
P4 Open Drain Control Register
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11 ADC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D1
ADC_PAGE
Page Register for ADC
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
RMAP = 0, Page 0
CA
ADC_GLOBCTR
Global Control Register
Reset: 30
Reset: 00
Bit Field
Type
ANON DW
rw rw
CTC
rw
0
r
H
H
CB
ADC_GLOBSTR
Global Status Register
Bit Field
0
CHNR
0
r
SAM BUSY
PLE
H
H
Type
r
rh
rh
rh
CC
CD
ADC_PRAR
Priority and Arbitration Register
Reset: 00
Bit Field
Type
ASEN1 ASEN0
rw rw
0
r
ARBM CSM1 PRIO1 CSM0 PRIO0
rw rw rw rw rw
BOUND0
H
H
H
H
H
H
H
H
ADC_LCBR
Limit Check Boundary Register
Reset: B7
Bit Field
Type
BOUND1
rw
rw
CE
CF
ADC_INPCR0
Input Class Register 0
Reset: 00
Bit Field
Type
STC
rw
ADC_ETRCR
External Trigger Control Register
Reset: 00
Bit Field
SYNEN SYNEN
ETRSEL1
ETRSEL0
rw
1
0
Type
rw
rw
rw
RMAP = 0, Page 1
Data Sheet
Prelimary
34
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
Bit Field
7
0
r
6
5
LCC
rw
4
3
2
1
0
CA
ADC_CHCTR0
Reset: 00
0
r
RESRSEL
H
H
H
H
H
H
H
H
H
Channel Control Register 0
Type
rw
CB
ADC_CHCTR1
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
Channel Control Register 1
CC
CD
ADC_CHCTR2
Channel Control Register 2
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
H
H
H
H
H
H
ADC_CHCTR3
Channel Control Register 3
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
CE
CF
ADC_CHCTR4
Channel Control Register 4
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
ADC_CHCTR5
Channel Control Register 5
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
D2
D3
ADC_CHCTR6
Channel Control Register 6
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
ADC_CHCTR7
Reset: 00
Bit Field
Type
0
r
LCC
rw
0
r
RESRSEL
rw
Channel Control Register 7
RMAP = 0, Page 2
CA
ADC_RESR0L
Result Register 0 Low
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
Type
RESULT[1:0]
rh
0
r
VF
rh
DRC
rh
CHNR
H
H
H
H
H
H
H
H
H
rh
CB
ADC_RESR0H
Result Register 0 High
Bit Field
Type
RESULT[9:2]
rh
H
CC
CD
ADC_RESR1L
Result Register 1 Low
Bit Field
Type
RESULT[1:0]
rh
0
r
VF
rh
DRC
rh
CHNR
rh
H
H
H
H
H
H
ADC_RESR1H
Result Register 1 High
Bit Field
Type
RESULT[9:2]
rh
CE
CF
ADC_RESR2L
Result Register 2 Low
Bit Field
Type
RESULT[1:0]
rh
0
r
VF
rh
DRC
rh
CHNR
rh
ADC_RESR2H
Result Register 2 High
Bit Field
Type
RESULT[9:2]
rh
D2
D3
ADC_RESR3L
Result Register 3 Low
Bit Field
Type
RESULT[1:0]
rh
0
r
VF
rh
DRC
rh
CHNR
rh
ADC_RESR3H
Result Register 3 High
Bit Field
Type
RESULT[9:2]
rh
RMAP = 0, Page 3
CA
ADC_RESRA0L
Result Register 0, View A Low
Reset: 00
Bit Field
Type
RESULT[2:0]
rh
VF
rh
DRC
rh
CHNR
rh
H
H
H
H
H
H
H
H
H
CB
ADC_RESRA0H
Result Register 0, View A High
Reset: 00
Bit Field
Type
RESULT[10:3]
rh
H
CC
CD
ADC_RESRA1L
Result Register 1, View A Low
Reset: 00
Bit Field
Type
RESULT[2:0]
rh
VF
rh
DRC
rh
CHNR
rh
H
H
H
H
H
H
ADC_RESRA1H
Result Register 1, View A High
Reset: 00
Bit Field
Type
RESULT[10:3]
rh
CE
CF
ADC_RESRA2L
Result Register 2, View A Low
Reset: 00
Bit Field
Type
RESULT[2:0]
rh
VF
rh
DRC
rh
CHNR
rh
ADC_RESRA2H
Result Register 2, View A High
Reset: 00
Bit Field
Type
RESULT[10:3]
rh
D2
D3
ADC_RESRA3L
Result Register 3, View A Low
Reset: 00
Bit Field
Type
RESULT[2:0]
rh
VF
rh
DRC
rh
CHNR
rh
ADC_RESRA3H
Result Register 3, View A High
Reset: 00
Bit Field
Type
RESULT[10:3]
rh
Data Sheet
Prelimary
35
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0, Page 4
CA
CB
ADC_RCR0
Result Control Register 0
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Reset: 00
Bit Field
VFCTR WFR
FEN
IEN
0
DRCT
R
H
H
H
H
H
H
Type
rw
rw
rw
rw
r
rw
ADC_RCR1
Result Control Register 1
Bit Field
VFCTR WFR
FEN
IEN
0
DRCT
R
H
Type
rw
rw
rw
rw
r
rw
CC
ADC_RCR2
Result Control Register 2
Bit Field
VFCTR WFR
FEN
IEN
0
DRCT
R
H
H
H
Type
rw
rw
rw
rw
r
rw
CD
ADC_RCR3
Result Control Register 3
Bit Field
VFCTR WFR
FEN
IEN
0
DRCT
R
Type
rw
rw
rw
rw
r
rw
CE
ADC_VFCR
Valid Flag Clear Register
Bit Field
Type
0
r
VFC3 VFC2 VFC1 VFC0
w
w
w
w
RMAP = 0, Page 5
CA
ADC_CHINFR
Channel Interrupt Flag Register
Reset: 00
Bit Field
CHINF CHINF CHINF CHINF CHINF CHINF CHINF CHINF
H
H
H
H
H
H
H
H
H
7
6
5
4
3
2
1
0
Type
rh
rh
rh
rh
rh
rh
rh
rh
CB
ADC_CHINCR
Channel Interrupt Clear Register
Reset: 00
Bit Field
CHINC CHINC CHINC CHINC CHINC CHINC CHINC CHINC
H
7
6
5
4
3
2
1
0
Type
w
w
w
w
w
w
w
w
CC
CD
ADC_CHINSR
Channel Interrupt Set Register
Reset: 00
Bit Field
CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS
H
H
H
H
H
H
7
6
5
4
3
2
1
0
Type
w
w
w
w
w
w
w
w
ADC_CHINPR
Channel Interrupt Node Pointer
Register
Reset: 00
Bit Field
CHINP CHINP CHINP CHINP CHINP CHINP CHINP CHINP
7
6
5
4
3
2
1
0
Type
rw
rw
rw
rw
rw
rw
rw
rw
CE
ADC_EVINFR
Event Interrupt Flag Register
Reset: 00
Bit Field
EVINF EVINF EVINF EVINF
0
EVINF EVINF
7
6
5
4
1
0
Type
rh
rh
rh
rh
r
rh
rh
CF
ADC_EVINCR
Event Interrupt Clear Flag Register
Reset: 00
Bit Field
EVINC EVINC EVINC EVINC
0
EVINC EVINC
7
6
5
4
1
0
Type
w
w
w
w
r
w
w
D2
D3
ADC_EVINSR
Event Interrupt Set Flag Register
Reset: 00
Bit Field
EVINS EVINS EVINS EVINS
0
EVINS EVINS
7
6
5
4
1
0
Type
w
w
w
w
r
w
w
ADC_EVINPR
Reset: 00
Bit Field
EVINP EVINP EVINP EVINP
0
EVINP EVINP
Event Interrupt Node Pointer Register
7
6
5
4
1
0
Type
rw
rw
rw
rw
r
rw
rw
RMAP = 0, Page 6
CA
ADC_CRCR1
Conversion Request Control Register 1
Reset: 00
Bit Field
CH7
rwh
CH6
rwh
CH5
rwh
CH4
rwh
0
H
H
Type
r
CB
ADC_CRPR1
Reset: 00
Bit Field
CHP7 CHP6 CHP5 CHP4
0
H
H
Conversion Request Pending
Register 1
Type
rwh
Rsv
rwh
rwh
rwh
r
CC
CD
ADC_CRMR1
Reset: 00
Bit Field
LDEV CLR SCAN ENSI ENTR
PND
ENGT
H
H
Conversion Request Mode Register 1
Type
r
w
w
rw
rw
0
rw
ENTR
rw
rw
ENGT
rw
ADC_QMR0
Queue Mode Register 0
Reset: 00
Bit Field
Type
CEV TREV FLUSH CLRV
H
H
w
w
w
w
r
Data Sheet
Prelimary
36
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
Bit Field
7
Rsv
r
6
0
r
5
4
3
2
1
0
CE
ADC_QSR0
Queue Status Register 0
Reset: 20
Reset: 00
Reset: 00
Reset: 00
EMPTY EV
0
r
FILL
rh
H
H
H
H
H
H
H
H
Type
rh
RF
rh
rh
V
CF
ADC_Q0R0
Queue 0 Register 0
Bit Field
Type
EXTR ENSI
rh rh
EXTR ENSI
rh rh
EXTR ENSI
0
r
REQCHNR
rh
V
rh
REQCHNR
rh
D2
D2
ADC_QBUR0
Queue Backup Register 0
Bit Field
Type
RF
rh
0
r
rh
ADC_QINR0
Bit Field
Type
RF
w
0
r
REQCHNR
w
Queue Input Register 0
w
w
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 12 Timer 2 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
C0
T2_T2CON
Timer 2 Control Register
Reset: 00
Reset: 00
Reset: 00
Bit Field
TF2
EXF2
0
r
EXEN2 TR2
0
CP/
RL2
H
H
H
H
Type
rwh
T2
rwh
T2
rw
rwh
r
rw
C1
T2_T2MOD
Timer 2 Mode Register
Bit Field
EDGE PREN
T2PRE
DCEN
H
REGS RHEN SEL
Type
rw rw rw
rw
rw
rw
C2
C3
C4
C5
T2_RC2L
Timer 2 Reload/Capture Register Low
Bit Field
Type
RC2
rwh
H
H
H
H
T2_RC2H Reset: 00
Timer 2 Reload/Capture Register High
Bit Field
Type
RC2
rwh
H
T2_T2L
Timer 2 Register Low
Reset: 00
Bit Field
Type
THL2
rwh
H
H
T2_T2H
Timer 2 Register High
Reset: 00
Bit Field
Type
THL2
rwh
The Timer 21 SFRs can be accessed in the standard memory area (RMAP = 1).
Table 13 T21 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
C0
T2CON
Timer 2 Control Register
Reset: 00
Reset: 00
Reset: 00
Bit Field
TF2
EXF2
0
r
0
EXEN2 TR2
C/T2
rw
CP/
RL2
H
H
H
H
Type
rwh
T2
rwh
T2
r
rw
rwh
rw
C1
T2MOD
Timer 2 Mode Register
Bit Field
EDGE PREN
T2PRE
DCEN
H
REGS RHEN SEL
Type
rw rw rw
rw
rw
rw
C2
C3
C4
C5
RC2L
Bit Field
Type
RC2
rwh
H
H
H
H
Timer 2 Reload/Capture Register Low
RC2H Reset: 00
Timer 2 Reload/Capture Register High
Bit Field
Type
RC2
rwh
H
T2L
Reset: 00
Bit Field
Type
THL2
rwh
H
H
Timer 2 Register Low
T2H
Reset: 00
Bit Field
Type
THL2
rwh
Timer 2 Register High
Data Sheet
Prelimary
37
V0.1, 2006-02
XC886/888CLM
Functional Description
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 14 CCU6 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A3
CCU6_PAGE
Page Register for CCU6
Reset: 00
Bit Field
Type
OP
w
STNR
w
0
r
PAGE
rw
H
H
H
RMAP = 0, Page 0
9A
CCU6_CC63SRL
Capture/Compare Shadow Register for
Channel CC63 Low
Reset: 00
Bit Field
CC63SL
H
H
Type
rw
9B
CCU6_CC63SRH
Reset: 00
Bit Field
CC63SH
H
Capture/Compare Shadow Register for
Channel CC63 High
Type
rw
9C
9D
CCU6_TCTR4L
Timer Control Register 4 Low
Reset: 00
Bit Field
T12
STD
T12
STR
0
r
DTRES T12 T12RS T12RR
RES
H
H
H
H
H
H
H
Type
w
w
w
w
w
w
CCU6_TCTR4H
Timer Control Register 4 High
Reset: 00
Bit Field
T13
STD
T13
STR
0
r
T13 T13RS T13RR
RES
Type
w
w
0
w
w
w
9E
CCU6_MCMOUTSL
Multi-Channel Mode Output Shadow
Register Low
Reset: 00
Bit Field
STRM
CM
MCMPS
Type
w
STRHP
w
r
0
r
rw
9F
CCU6_MCMOUTSH
Multi-Channel Mode Output Shadow
Register High
Reset: 00
Bit Field
Type
CURHS
rw
EXPHS
rw
H
A4
A5
A6
A7
CCU6_ISRL
Capture/Compare Interrupt Status
Reset Register Low
Reset: 00
Bit Field
RT12P RT12O RCC62 RCC62 RCC61 RCC61 RCC60 RCC60
H
H
H
H
H
H
H
M
M
F
R
F
w
0
R
F
R
Type
w
w
w
w
w
w
w
CCU6_ISRH
Capture/Compare Interrupt Status
Reset Register High
Reset: 00
Bit Field
RSTR RIDLE RWHE RCHE
RTRPF RT13 RT13
PM
CM
Type
w
0
w
w
w
0
r
w
w
w
CCU6_CMPMODIFL
Compare State Modification Register
Low
Reset: 00
Bit Field
MCC63
S
MCC62 MCC61 MCC60
S
S
S
Type
r
w
r
w
w
w
CCU6_CMPMODIFH
Compare State Modification Register
High
Reset: 00
Bit Field
0
MCC63
R
0
MCC62 MCC61 MCC60
H
R
R
R
Type
r
w
r
w
w
w
FA
FB
CCU6_CC60SRL
Capture/Compare Shadow Register for
Channel CC60 Low
Reset: 00
Bit Field
CC60SL
H
H
H
Type
rwh
CCU6_CC60SRH
Reset: 00
Bit Field
CC60SH
H
Capture/Compare Shadow Register for
Channel CC60 High
Type
rwh
FC
FD
CCU6_CC61SRL
Capture/Compare Shadow Register for
Channel CC61 Low
Reset: 00
Bit Field
CC61SL
H
H
H
H
H
Type
rwh
CCU6_CC61SRH
Capture/Compare Shadow Register for
Channel CC61 High
Reset: 00
Bit Field
CC61SH
H
Type
rwh
FE
CCU6_CC62SRL
Capture/Compare Shadow Register for
Channel CC62 Low
Reset: 00
Bit Field
CC62SL
H
Type
rwh
FF
CCU6_CC62SRH
Reset: 00
Bit Field
CC62SH
H
Capture/Compare Shadow Register for
Channel CC62 High
Type
rwh
Data Sheet
Prelimary
38
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0, Page 1
9A
9B
CCU6_CC63RL
Capture/Compare Register for Channel
CC63 Low
Reset: 00
Bit Field
CC63VL
H
H
Type
rh
CCU6_CC63RH
Reset: 00
Bit Field
CC63VH
H
H
Capture/Compare Register for Channel
CC63 High
Type
rh
T12PVL
rwh
9C
9D
CCU6_T12PRL
Timer T12 Period Register Low
Reset: 00
Bit Field
Type
H
H
H
H
H
H
H
H
H
CCU6_T12PRH
Timer T12 Period Register High
Reset: 00
Bit Field
Type
T12PVH
rwh
9E
9F
CCU6_T13PRL
Timer T13 Period Register Low
Reset: 00
Bit Field
Type
T13PVL
rwh
CCU6_T13PRH
Timer T13 Period Register High
Reset: 00
Bit Field
Type
T13PVH
rwh
A4
CCU6_T12DTCL
Reset: 00
Bit Field
Type
DTM
H
H
Dead-Time Control Register for Timer
T12 Low
rw
A5
CCU6_T12DTCH
Dead-Time Control Register for Timer
T12 High
Reset: 00
Bit Field
0
r
DTR2 DTR1 DTR0
rh rh rh
0
r
DTE2 DTE1 DTE0
H
Type
rw
rw
rw
A6
A7
CCU6_TCTR0L
Timer Control Register 0 Low
Reset: 00
Bit Field
CTM CDIR STE12 T12R
T12
PRE
T12CLK
H
H
H
H
H
Type
rw
rh
rh
rh
rw
rw
CCU6_TCTR0H
Timer Control Register 0 High
Reset: 00
Bit Field
0
r
STE13 T13R
T13
PRE
T13CLK
Type
rh
rh
rw
rw
FA
FB
CCU6_CC60RL
Capture/Compare Register for Channel
CC60 Low
Reset: 00
Bit Field
CC60VL
H
H
Type
rh
CCU6_CC60RH
Reset: 00
Bit Field
CC60VH
H
Capture/Compare Register for Channel
CC60 High
Type
rh
FC
FD
CCU6_CC61RL
Capture/Compare Register for Channel
CC61 Low
Reset: 00
Bit Field
CC61VL
H
H
H
H
H
Type
rh
CCU6_CC61RH
Capture/Compare Register for Channel
CC61 High
Reset: 00
Bit Field
CC61VH
H
Type
rh
FE
CCU6_CC62RL
Capture/Compare Register for Channel
CC62 Low
Reset: 00
Bit Field
CC62VL
H
Type
rh
FF
CCU6_CC62RH
Reset: 00
Bit Field
CC62VH
H
Capture/Compare Register for Channel
CC62 High
Type
rh
RMAP = 0, Page 2
9A
CCU6_T12MSELL
Reset: 00
Bit Field
MSEL61
MSEL60
H
H
T12 Capture/Compare Mode Select
Register Low
Type
rw
HSYNC
rw
9B
CCU6_T12MSELH
Reset: 00
Bit Field
DBYP
rw
MSEL62
H
H
T12 Capture/Compare Mode Select
Register High
Type
rw
rw
Data Sheet
Prelimary
39
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
9C
CCU6_IENL
Capture/Compare Interrupt Enable
Register Low
Reset: 00
Bit Field
ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC
H
H
H
H
H
H
H
H
H
PM
OM
62F
62R
61F
rw
0
61R
60F
60R
Type
rw
rw
rw
rw
rw
rw
rw
9D
CCU6_IENH
Capture/Compare Interrupt Enable
Register High
Reset: 00
Bit Field
ENSTR EN
IDLE
EN
WHE
EN
CHE
EN
TRPF
ENT13 ENT13
PM
CM
Type
rw
rw
rw
rw
r
rw
rw
rw
9E
CCU6_INPL
Capture/Compare Interrupt Node
Pointer Register Low
Reset: 40
Bit Field
INPCHE
INPCC62
INPCC61
INPCC60
Type
rw
0
rw
rw
rw
9F
CCU6_INPH
Capture/Compare Interrupt Node
Pointer Register High
Reset: 39
Bit Field
INPT13
INPT12
INPERR
Type
r
rw
rw
rw
A4
A5
CCU6_ISSL
Capture/Compare Interrupt Status Set
Register Low
Reset: 00
Bit Field
ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60
H
M
M
F
R
F
R
F
R
Type
w
w
w
w
w
w
w
w
CCU6_ISSH
Reset: 00
Bit Field
SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13
H
H
Capture/Compare Interrupt Status Set
Register High
PM
CM
Type
w
w
0
r
w
w
w
w
w
w
A6
A7
CCU6_PSLR
Reset: 00
Bit Field
Type
PSL63
rwh
PSL
rwh
H
H
Passive State Level Register
CCU6_MCMCTR Reset: 00
Multi-Channel Mode Control Register
Bit Field
Type
0
r
SWSYN
rw
0
r
SWSEL
rw
H
H
FA
FB
CCU6_TCTR2L
Timer Control Register 2 Low
Reset: 00
Bit Field
0
r
T13TED
T13TEC
T13
SSC
T12
SSC
H
H
H
Type
rw
0
rw
rw
rw
CCU6_TCTR2H
Timer Control Register 2 High
Reset: 00
Bit Field
Type
T13RSEL
rw
T12RSEL
rw
H
r
FC
FD
CCU6_MODCTRL
Modulation Control Register Low
Reset: 00
Bit Field
MC
MEN
0
T12MODEN
H
H
Type
rw
r
rw
CCU6_MODCTRH
Modulation Control Register High
Reset: 00
Bit Field
ECT13
O
0
T13MODEN
H
H
Type
rw
r
rw
FE
CCU6_TRPCTRL
Trap Control Register Low
Reset: 00
Bit Field
Type
0
r
TRPM2 TRPM1 TRPM0
H
H
rw
TRPEN
rw
rw
FF
CCU6_TRPCTRH
Reset: 00
Bit Field
TRPPE TRPEN
H
H
Trap Control Register High
N
13
Type
rw
rw
rw
RMAP = 0, Page 3
9A
9B
CCU6_MCMOUTL
Multi-Channel Mode Output Register
Low
Reset: 00
Bit Field
0
r
R
MCMP
rh
H
H
Type
rh
CCU6_MCMOUTH
Multi-Channel Mode Output Register
High
Reset: 00
Bit Field
0
r
CURH
rh
EXPH
rh
H
H
Type
9C
9D
CCU6_ISL
Capture/Compare Interrupt Status
Register Low
Reset: 00
Bit Field
T12PM T12OM ICC62F ICC62 ICC61F ICC61 ICC60F ICC60
H
H
H
H
H
H
R
R
R
Type
rh
rh
rh
rh
rh
rh
rh
rh
CCU6_ISH
Capture/Compare Interrupt Status
Register High
Reset: 00
Bit Field
STR
IDLE
WHE
CHE TRPS TRPF T13PM T13CM
Type
rh
rh
rh
rh
rh
ISCC61
rw
rh
rh
rh
9E
CCU6_PISEL0L
Port Input Select Register 0 Low
Reset: 00
Bit Field
Type
ISTRP
rw
ISCC62
rw
ISCC60
rw
Data Sheet
Prelimary
40
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
9F
CCU6_PISEL0H
Reset: 00
Bit Field
IST12HR
ISPOS2
ISPOS1
ISPOS0
H
H
Port Input Select Register 0 High
Type
rw
rw
0
rw
rw
IST13HR
rw
A4
CCU6_PISEL2
Port Input Select Register 2
Reset: 00
Bit Field
Type
H
H
H
H
H
H
H
r
FA
FB
CCU6_T12L
Timer T12 Counter Register Low
Reset: 00
Bit Field
Type
T12CVL
rwh
H
H
CCU6_T12H
Timer T12 Counter Register High
Reset: 00
Bit Field
Type
T12CVH
rwh
FC
FD
CCU6_T13L
Timer T13 Counter Register Low
Reset: 00
Bit Field
Type
T13CVL
rwh
H
H
H
CCU6_T13H
Timer T13 Counter Register High
Reset: 00
Bit Field
Type
T13CVH
rwh
FE
CCU6_CMPSTATL
Reset: 00
Bit Field
0
r
CC63 CCPO CCPO CCPO CC62 CC61 CC60
Compare State Register Low
ST
S2
S1
S0
ST
ST
ST
Type
rh
rh
rh
rh
rh
rh
rh
FF
CCU6_CMPSTATH
Reset: 00
Bit Field
T13IM COUT COUT CC62 COUT CC61 COUT CC60
H
H
Compare State Register High
63PS 62PS
PS
61PS
PS
60PS
PS
Type
rwh
rwh rwh
rwh
rwh
rwh
rwh
rwh
The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 15 UART1 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
C8
SCON
Reset: 00
Bit Field
Type
SM0
rw
SM1
rw
SM2
rw
REN
rw
TB8
rw
RB8
rwh
TI
RI
H
H
H
H
H
Serial Channel Control Register
rwh
rwh
C9
SBUF
Reset: 00
Bit Field
Type
VAL
rwh
H
Serial Data Buffer Register
CA
CB
BCON
Reset: 00
Bit Field
Type
0
r
BRPRE
rw
R
H
H
Baud Rate Control Register
rw
BG
Reset: 00
Bit Field
Type
BR_VALUE
rwh
Baud Rate Timer/Reload Register
CC
CD
FDCON
Reset: 00
Bit Field
Type
0
r
NDOV FDM FDEN
H
H
H
H
H
H
Fractional Divider Control Register
rwh
rw
rw
FDSTEP
Fractional Divider Reload Register
Reset: 00
Bit Field
Type
STEP
rw
CE
FDRES Reset: 00
Fractional Divider Result Register
Bit Field
Type
RESULT
rh
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 16 SSC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A9
SSC_PISEL
Port Input Select Register
Reset: 00
Bit Field
Type
0
r
CIS
rw
SIS
rw
MIS
rw
H
H
Data Sheet
Prelimary
41
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 16
SSC Register Overview
AA
SSC_CONL
Control Register Low
Programming Mode
Reset: 00
Bit Field
LB
rw
PO
rw
PH
rw
HB
rw
BM
rw
H
H
Type
Operating Mode
Bit Field
Type
0
r
BC
rh
AB
SSC_CONH
Reset: 00
Bit Field
EN
MS
0
AREN BEN
PEN
REN
TEN
H
H
Control Register High
Programming Mode
Type
rw
EN
rw
rw
MS
rw
r
0
r
rw
BSY
rh
rw
BE
rwh
rw
PE
rwh
rw
RE
rwh
rw
TE
rwh
Operating Mode
Bit Field
Type
AC
AD
SSC_TBL
Transmitter Buffer Register Low
Reset: 00
Bit Field
Type
TB_VALUE
H
H
H
H
H
H
H
rw
RB_VALUE
rh
SSC_RBL
Receiver Buffer Register Low
Reset: 00
Bit Field
Type
AE
AF
SSC_BRL
Baudrate Timer Reload Register Low
Reset: 00
Bit Field
Type
BR_VALUE
rw
SSC_BRH Reset: 00
Baudrate Timer Reload Register High
Bit Field
Type
BR_VALUE
rw
H
The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).
Table 17 MultiCAN Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D8
ADCON
Reset: 00
Bit Field
Type
V3
rw
V2
rw
V1
rw
V0
rw
AUAD
rw
BSY RWEN
H
H
H
H
H
CAN Address/Data Control Register
rh
rw
D9
ADL Reset: 00
CAN Address Low Register
Bit Field
Type
CA9
rwh
CA8
rwh
CA7
rwh
CA6
rwh
CA5
rwh
CA4
rwh
CA3
rwh
CA2
rwh
H
DA
DB
ADH
Reset: 00
Bit Field
Type
0
r
CA13 CA12 CA11 CA10
H
H
CAN Address High Register
rwh
rwh
rwh
rwh
DATA0
CAN Data Register 0
Reset: 00
Reset: 00
Bit Field
Type
CD
rwh
CD
rwh
CD
rwh
CD
rwh
DC
DD
DATA1
CAN Data Register 1
Bit Field
Type
H
H
H
H
H
H
DATA2
CAN Data Register 2
Reset: 00
Reset: 00
Bit Field
Type
DE
DATA3
CAN Data Register 3
Bit Field
Type
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 18 OCDS Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
E9
MMCR2
Reset: 1U
Bit Field
STMO EXBC DSUSP MBCO ALTDI MMEP MMOD JENA
H
H
Monitor Mode Control 2 Register
DE
N
E
Type
rw
rw
rw
0
rwh
rw
rwh
rh
rh
F1
MMCR
Reset: 00
Bit Field
MEXIT MEXIT
_P
MSTEP MRAM MRAM TRF
RRF
H
H
Monitor Mode Control Register
S_P
S
Type
w
hw
r
rw
w
rwh
rh
rh
Data Sheet
Prelimary
42
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 18
OCDS Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
F2
F3
F4
F5
MMSR
Reset: 00
Bit Field
MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWB0
H
H
H
H
H
H
H
Monitor Mode Status Register
M
F
F
F
F
Type
rw
rwh
rwh
rwh
rwh
rwh
rwh
rwh
MMBPCR
BreakPoints Control Register
Reset: 00
Bit Field
SWBC
HWB3C
HWB2C
HWB1
C
HWB0C
Type
rw
rw
rw
rw
rw
MMICR
Reset: 00
Bit Field
DVECT DRETR COM
RST
MST MMUIE MMUIE RRIE_ RRIE
Monitor Mode Interrupt Control Register
SEL
_P
P
Type
rwh
rwh
rwh
rh
w
rw
w
rw
MMDR
Reset: 00
Bit Field
MMRR
H
Monitor Mode Data Transfer Register
Receive
Type
rh
Transmit
Bit Field
MMTR
Type
w
F6
F7
HWBPSR
Hardware Breakpoints Select Register
Reset: 00
Bit Field
0
r
BPSEL
_P
BPSEL
rw
H
H
Type
w
HWBPDR
Reset: 00
Bit Field
HWBPxx
H
H
Hardware Breakpoints Data Register
Type
rw
EB
MMWR1
Monitor Work Register 1
Reset: 00
Reset: 00
Bit Field
MMWR1
H
H
H
Type
rw
EC
MMWR2
Bit Field
MMWR2
H
Monitor Work Register 2
Type
rw
Data Sheet
Prelimary
43
V0.1, 2006-02
XC886/888CLM
Functional Description
3.3
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The sectorization of the Flash memory allows each
sector to be erased independently.
Features:
• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program and erase operations for CPU load minimization
• Support for aborting erase operation
1)
• Minimum program width of 32-byte for D-Flash and 64-byte for P-Flash
• 1-sector minimum erase width
• 1-byte read access
• 135.1 ns minimum read access time (3 × t
• Operating supply voltage: 2.5 V ± 7.5 %
• Program time: 2.3 ms
• Erase time: 120 ms
2)
@ f
= 24 MHz ± 7.5 % )
CCLK
CCLK
3)
3)
4)
Table 19 shows the Flash data retention and endurance targets .
Table 19
Flash Data Retention and Endurance Targets
Retention up to
Endurance up to
Programming
Temperature
Size
20 years
5 years
2 years
2 years
1,000 cycles
0 – 100°C
15 Kbytes
896 bytes
512 bytes
128 bytes
10,000 cycles
70,000 cycles
100,000 cycles
-40 – 125°C
-40 – 125°C
-40 – 125°C
1)
P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed.
D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.
2)
3)
f
f
= 96 MHz ± 7.5% (f
= 24 MHz ± 7.5 %) is the maximum frequency range for Flash read access.
sys
CCLK
= 96 MHz ± 7.5% is the only frequency range for Flash programming and erasing. f
is used for
sys
sysmin
obtaining the worst case timing.
Specification according to operating temperature profile with 0.2ppm error rate.
4)
Data Sheet
Prelimary
44
V0.1, 2006-02
XC886/888CLM
Functional Description
3.3.1
Flash Bank Sectorization
The XC886/888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes
of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash)
bank(s) and a single Data Flash (D-Flash) bank with different sectorization shown in
Figure 11. Both types can be used for code and data storage. The label “Data” neither
implies that the D-Flash is mapped to the data memory region, nor that it can only be
used for data storage. It is used to distinguish the different Flash bank sectorizations.
The XC886/888 ROM devices offer a single 4-Kbyte D-Flash bank.
Sector 2: 128-byte
Sector 1: 128-byte
Sector 9: 128-byte
Sector 8: 128-byte
Sector 7: 128-byte
Sector 6: 128-byte
Sector 5: 256-byte
Sector 4: 256-byte
Sector 3: 512-byte
Sector 2: 512-byte
Sector 0: 3.75-Kbyte
Sector 1: 1-Kbyte
Sector 0: 1-Kbyte
P-Flash
D-Flash
Figure 11
Flash Bank Sectorization
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
Data Sheet
Prelimary
45
V0.1, 2006-02
XC886/888CLM
Functional Description
3.3.2
Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be
reprogrammed as the Flash cells can only withstand one gate disturb. This means that
the entire sector containing the WL must be erased since it is impossible to erase a
single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required
as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to
program the same WL, for example, with 16 bytes of data in two times (see Figure 12).
32 bytes (1 WL)
0000 ….. 0000 H
16 bytes
16 bytes
Program 1
Program 2
0000 ….. 0000 H
1111 ….. 1111 H
1111 ….. 1111 H
0000 ….. 0000 H
1111 ….. 1111H
0000 ….. 0000 H
1111 ….. 0000 H
1111 ….. 0000 H
0000 ….. 0000H
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
Flash memory cells
32-byte write buffers
Figure 12
D-Flash Programming
Note: When programming a D-Flash WL the second time, the previously programmed
Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain
its original contents and to prevent “over-programming”.
Data Sheet
Prelimary
46
V0.1, 2006-02
XC886/888CLM
Functional Description
3.4
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC886/888 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1
Interrupt Source
Figure 13 to Figure 17 give a general overview of the interrupt sources and illustrates
the request and control flags.
WDT Overflow
FNMIWDT
NMIISR.0
NMIWDT
NMICON.0
PLL Loss of Lock
FNMIPLL
NMIISR.1
NMIPLL
NMICON.1
Flash Operation
Complete
FNMIFLASH
NMIISR.2
NMIFLASH
>=1
Non
Maskable
Interrupt
0073
FNMIVDD
NMIISR.4
H
VDD Pre-Warning
VDDP Pre-Warning
Flash ECC Error
NMIVDD
NMICON.4
FNMIVDDP
NMIISR.5
NMIVDDP
NMICON.5
FNMIECC
NMIISR.6
NMIECC
NMICON.6
Figure 13
Non-Maskable Interrupt Request Sources
Data Sheet
Prelimary
47
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Timer 0
Overflow
TF0
Lowest
Priority Level
TCON.5
000B
ET0
H
IP.1/
IPH.1
IEN0.1
Timer 1
Overflow
TF1
P
o
l
TCON.7
001B
H
ET1
IP.3/
IPH.3
IEN0.3
l
i
n
g
RI
SCON.0
>=1
UART
S
e
q
u
e
n
c
0023
TI
ES
H
IP.4/
IPH.4
IEN0.4
SCON.1
EINT0
EXINT0
IE0
TCON.1
e
IRCON0.0
0003
EX0
H
IT0
IP.0/
IPH.0
IEN0.0
EXINT0
TCON.0
EXICON0.0/1
EINT1
EXINT1
IE1
IRCON0.1
TCON.3
0013
EA
EX1
H
IT1
IP.2/
IEN0.2
IPH.2
EXINT1
TCON.2
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 14
Interrupt Request Sources (Part 1)
Data Sheet
Prelimary
48
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Timer 2
TF2
Overflow
Lowest
Priority Level
T2_T2CON.7
>=1
T2EX
EXF2
T2_T2CON.6
EXEN2
T2_T2CON.3
EDGES
EL
Normal Divider
NDOV
T2_T2MOD.5
Overflow
>=1
FDCON.2
002B
End of
Syn Byte
ET2
P
o
l
l
i
n
g
EOFSYN
H
IP.5/
IPH.5
IEN0.5
FDCON.4
SYNEN
FDCON.6
Syn Byte Error
ERRSYN
FDCON.5
MCAN_0
CANSRC0
IRCON2.0
S
e
q
u
e
n
c
ADC_0
ADC_1
ADCSRC0
IRCON1.3
ADCSRC1
IRCON1.4
>=1
MCAN_1
MCAN_2
CANSRC1
IRCON1.5
0033
EA
EADC
IEN1.0
H
IP1.0/
IPH1.0
e
CANSRC2
IRCON1.6
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 15
Interrupt Request Sources (Part 2)
Data Sheet
Prelimary
49
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Lowest
Priority Level
SSC_EIR
SSC_TIR
SSC_RIR
EIR
IRCON1.0
>=1
TIR
IRCON1.1
003B
ESSC
IEN1.1
H
IP1.1/
IPH1.1
RIR
IRCON1.2
P
o
l
EXINT2
EINT2
IRCON0.2
l
i
n
g
EXINT2
EXICON0.4/5
RI
S
e
q
u
e
n
c
UART1_SCON.0
>=1
UART1
TI
UART1_SCON.1
Timer 21
Overflow
TF2
>=1
0043
EX2
H
T21_T2CON.7
e
IP1.2/
IPH1.2
>=1
IEN1.2
T21EX
EXF2
T21_T2CON.6
EXEN2
T21_T2CON.3
Normal Divider
Overflow
EDGES
EL
NDOV
T21_T2MOD.5
UART1_FDCON.2
Cordic
EOC
CDSTATC.2
MDU_0
MDU_1
IRDY
MDUSTAT.0
IERR
EA
IEN0.7
MDUSTAT.1
Bit-addressable
Request flag is cleared by hardware
Figure 16
Interrupt Request Sources (Part 3)
Data Sheet
Prelimary
50
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Lowest
Priority Level
EXINT3
EINT3
IRCON0.3
EXINT3
EXICON0.6/7
EXINT4
EINT4
P
o
l
l
i
IRCON0.4
EXINT3
EXICON1.0/1
n
g
>=1
EXINT5
EINT5
004B
EXM
H
IRCON0.5
S
e
q
u
e
n
c
IP1.3/
IPH1.3
IEN1.3
EXINT5
EXICON1.2/3
EXINT6
EINT6
e
IRCON0.6
EXINT6
EXICON1.4/5
MCAN_3
CANSRC3
IRCON2.4
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 17
Interrupt Request Sources (Part 4)
Data Sheet
Prelimary
51
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Lowest
CCU6 interrupt node 0
MCAN_4
CCU6SR0
IRCON3.0
Priority Level
>=1
MCANSRC4
IRCON3.1
P
o
l
l
i
0053
005B
0063
H
ECCIP0
IEN1.4
IP1.4/
IPH1.4
CCU6 interrupt node 1
MCAN_5
CCU6SR1
IRCON3.4
n
g
>=1
MCANSRC5
IRCON3.5
H
ECCIP1
IEN1.5
IP1.5/
IPH1.5
S
e
q
u
e
n
c
CCU6 interrupt node 2
MCAN_6
CCU6SR2
IRCON4.0
>=1
H
ECCIP2
IEN1.6
MCANSRC6
IRCON4.1
IP1.6/
IPH1.6
e
CCU6 interrupt node 3
MCAN_7
CCU6SRC3
IRCON4.4
>=1
006B
H
MCANSRC7
IRCON4.5
ECCIP3
IEN1.7
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 18
Interrupt Request Sources (Part 5)
Data Sheet
Prelimary
52
V0.1, 2006-02
XC886/888CLM
Functional Description
ICC60R
ISL.0
ENCC60R
IENL.0
CC60
CC61
>=1
>=1
ICC60F
ISL.1
ENCC60F
IENL.1
INPL.1
INPL.3
INPL.0
INPL.2
ICC61R
ISL.2
ENCC61R
IENL.2
ICC61F
ISL.3
ENCC61F
IENL.3
ICC62R
ISL.4
ENCC62R
IENL.4
CC62
>=1
ICC62F
ISL.5
ENCC62F
IENL.5
INPL.5
INPL.4
T12
One match
T12OM
ISL.6
ENT12OM
IENL.6
>=1
>=1
>=1
T12
Period match
T12PM
ISL.7
ENT12PM
IENL.7
INPH.3 INPH.2
INPH.5 INPH.4
INPH.1 INPH.0
T13
T13CM
ISH.0
Compare match
ENT13CM
IENH.0
T13
Period match
T13PM
ISH.1
ENT13PM
IENH.1
TRPF
ISH.2
CTRAP
ENTRPF
IENH.2
Wrong Hall
Event
WHE
ISH.5
ENWHE
IENH.5
Correct Hall
Event
CHE
ENCHE
IENH.4
ISH.4
>=1
Multi-Channel
Shadow
Transfer
STR
ENSTR
IENH.7
ISH.7
INPL.7
INPL.6
CCU6 Interrupt node 0
CCU6 Interrupt node 1
.
CCU6 Interrupt node 2
CCU6 Interrupt node 3
Figure 19
Interrupt Request Sources (Part 6)
Data Sheet
Prelimary
53
V0.1, 2006-02
XC886/888CLM
Functional Description
3.4.2
Interrupt Source and Vector
Each interrupt source has an associated interrupt vector address. This vector is
accessed to service the corresponding interrupt source request. The interrupt service of
each interrupt source can be individually enabled or disabled via an enable bit. The
assignment of the XC886/888 interrupt sources to the interrupt vector addresses and the
corresponding interrupt source enable bits are summarized in Table 20.
Table 20
Interrupt Vector Addresses
Interrupt
Source
Vector
Address
Assignment for XC886/
888
Enable Bit
SFR
NMI
0073
Watchdog Timer NMI
PLL NMI
NMIWDT
NMIPLL
NMIFLASH
NMIVDD
NMIVDDP
NMIECC
EX0
NMICON
H
Flash NMI
VDDC Prewarning NMI
VDDP Prewarning NMI
Flash ECC NMI
External Interrupt 0
Timer 0
XINTR0
XINTR1
XINTR2
XINTR3
XINTR4
XINTR5
0003
IEN0
H
000B
ET0
H
0013
External Interrupt 1
Timer 1
EX1
H
001B
ET1
H
0023
UART
ES
H
002B
T2
ET2
H
UART Fractional Divider
(Normal Divider Overflow)
MultiCAN Node 0
LIN
Data Sheet
Prelimary
54
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 20
Interrupt Vector Addresses (cont’d)
XINTR6
0033
MultiCAN Nodes 1 and 2
EADC
IEN1
H
ADC[1:0]
SSC
XINTR7
XINTR8
003B
ESSC
EX2
H
0043
External Interrupt 2
T21
H
CORDIC
UART1
UART1 Fractional Divider
(Normal Divider Overflow)
MDU[1:0]
XINTR9
004B
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
MultiCAN Node 3
CCU6 INP0
EXM
H
XINTR10
XINTR11
XINTR12
XINTR13
0053
ECCIP0
ECCIP1
ECCIP2
ECCIP3
H
MultiCAN Node 4
CCU6 INP1
005B
H
MultiCAN Node 5
CCU6 INP2
0063
H
MultiCAN Node 6
CCU6 INP3
006B
H
MultiCAN Node 7
Data Sheet
Prelimary
55
V0.1, 2006-02
XC886/888CLM
Functional Description
3.4.3
Interrupt Priority
Each interrupt source, except for NMI, can be individually programmed to one of the four
possible priority levels. The NMI has the highest priority and supersedes all other
interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are
available to program the priority level of each non-NMI interrupt vector.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another
interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot
be interrupted by any other interrupt source.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 21.
Table 21
Source
Priority Structure within Interrupt Level
Level
Non-Maskable Interrupt (NMI)
External Interrupt 0
Timer 0 Interrupt
(highest)
1
2
3
4
5
6
External Interrupt 1
Timer 1 Interrupt
UART Interrupt
Timer 2,UART Fractional Divider, MCAN, LIN
Interrupt
ADC, MCAN Interrupt
SSC Interrupt
7
8
9
External Interrupt 2, Timer 21, UART1, UART1
Fractional Divider, MDU, CORDIC Interrupt
External Interrupt [6:3], MCAN Interrupt
10
CCU6 Interrupt Node Pointer 0, MCAN interrupt 11
CCU6 Interrupt Node Pointer 1, MCAN Interrupt 12
CCU6 Interrupt Node Pointer 2, MCAN Interrupt 13
CCU6 Interrupt Node Pointer 3, MCAN Interrupt 14
Data Sheet
Prelimary
56
V0.1, 2006-02
XC886/888CLM
Functional Description
3.5
Parallel Ports
The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4),
while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 6
(P6). Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1, P3, P4 and P5 are bidirectional and can be used as
general purpose input/output (GPIO) or to perform alternate input/output functions for the
on-chip peripherals. When configured as an output, the open drain mode can be
selected. Port P2 is an input-only port, providing general purpose input functions,
alternate input functions for the on-chip peripherals, and also analog inputs for the
Analog-to-Digital Converter (ADC).
Bidirectional Port Features:
• Configurable pin direction
• Configurable pull-up/pull-down devices
• Configurable open drain mode
• Transfer of data through digital inputs and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals
Input Port Features:
• Configurable input driver
• Configurable pull-up/pull-down devices
• Receive of data through digital input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module
Data Sheet
Prelimary
57
V0.1, 2006-02
XC886/888CLM
Functional Description
Px_PUDSEL
Pull-up/Pull-down
Select Register
Internal Bus
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_OD
Open Drain
Control Register
Px_DIR
Direction Register
Px_ALTSEL0
Alternate Select
Register 0
VDDP
Px_ALTSEL1
Alternate Select
Register 1
Pull
Up
Device
enable
AltDataOut 3
enable
11
Output
Driver
AltDataOut 2
AltDataOut1
10
01
00
Pin
enable
Out
In
Input
Driver
Px_Data
Data Register
Schmitt Trigger
AltDataIn
Pull
Down
Device
enable
Pad
Figure 20
General Structure of Bidirectional Port
Data Sheet
Prelimary
58
V0.1, 2006-02
XC886/888CLM
Functional Description
Internal Bus
Px_PUDSEL
Pull-up/Pull-down
Select Register
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_DIR
Direction Register
VDDP
Pull
Up
enable
Device
enable
Input
In
Driver
Px_DATA
Data Register
Pin
Schmitt Trigger
AltDataIn
AnalogIn
Pull
Down
enable
Device
Pad
Figure 21
General Structure of Input Port
Data Sheet
Prelimary
59
V0.1, 2006-02
XC886/888CLM
Functional Description
3.6
Power Supply System with Embedded Voltage Regulator
The XC886/888 microcontroller requires two different levels of power supply:
• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 22 shows the XC886/888 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps to reduce the power consumption of the
whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
Memory
On-chip
OSC
Peripheral
logic
ADC
FLASH
PLL
VDDC (2.5V)
XTAL1&
XTAL2
GPIO Ports
(P0-P5)
EVR
VDDP (3.3V/5.0V)
VSSP
Figure 22
XC886/888 Power Supply System
EVR Features:
• Input voltage (V
): 3.3 V/5.0 V
DDP
• Output voltage (V
): 2.5 V ± 7.5%
DDC
• Low power voltage regulator provided in power-down mode
• V
• V
and V
brownout detection
prewarning detection
DDC
DDC
DDP
Data Sheet
Prelimary
60
V0.1, 2006-02
XC886/888CLM
Functional Description
3.7
Reset Control
The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC886/888 is first powered up, the status of certain pins (see Table 23) must
be defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until V
reaches 0.9*V
. The delay of external reset can be realized by an external
DDC
DDC
capacitor at RESET pin. This capacitor value must be selected so that V
reaches
RESET
0.4 V, but not before V
reaches 0.9* V
DDC
DDC.
A typical application example is shown in Figure 23. For a voltage regulator with IDD
max
= 100 mA, the V
capacitor value is 10 µF. V
capacitor value is 220 nF. The
DDP
DDC
capacitor connected to RESET pin is 100 nF.
Typically, the time taken for V
to reach 0.9*V
is less than 50 µs once V
DDP
DDC
DDC
reaches 2.3V. Hence, based on the condition that 10% to 90% V
(slew rate) is less
DDP
than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 24.
3 - 5V /
e.g. 100mA
Vin
VR
220nF
e.g. 10uF
VDDC
EVR
VSSC
VSSP VDDP
RESET
typ.
100nF
30k
XC886/888
Figure 23
Reset Circuitry
Data Sheet
Prelimary
61
V0.1, 2006-02
XC886/888CLM
Functional Description
Voltage
5V
VDDP
VDDC
2.5V
2.3V
0.9*VDDC
Time
Voltage
5V
RESET with
capacitor
< 0.4V
0V
Time
typ. < 50 us
Figure 24
VDDP, VDDC and VRESET during Power-on Reset
The second type of reset in XC886/888 is the hardware reset. This reset function can be
used during normal operation or when the chip is in power-down mode. A reset input pin
RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
Data Sheet
Prelimary
62
V0.1, 2006-02
XC886/888CLM
Functional Description
3.7.1
Module Reset Behavior
Table 22 shows how the functions of the XC886/888 are affected by the various reset
types. A “ ” means that this function is reset to its default state.
Table 22
Effect of Reset on Device Functions
Module/
Function
Wake-Up
Reset
Watchdog Hardware
Reset Reset
Power-On
Reset
Brownout
Reset
CPU Core
Peripherals
On-Chip
Not affected, Not affected, Not affected, Affected, un- Affected, un-
Static RAM
reliable
reliable
reliable
reliable
reliable
Oscillator,
PLL
Not affected
Port Pins
EVR
The voltage Not affected
regulator is
switched on
FLASH
NMI
Disabled
Booting Scheme
Disabled
3.7.2
When the XC886/888 is reset, it must identify the type of configuration with which to start
the different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 23
shows the available boot options in the XC886/888.
Table 23
XC886/888 Boot Selection
MBC TMS P0.0 Type of Mode
PC Start Value
1
0
0
0
0
1
x
x
0
User Mode; on-chip OSC/PLL non-bypassed 0000
H
H
H
BSL Mode; on-chip OSC/PLL non-bypassed 0000
OCDS Mode; on-chip OSC/PLL non-
0000
bypassed
1)
1
1
0
User (JTAG) Mode ; on-chip OSC/PLL non- 0000
bypassed (normal)
H
1)
Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Data Sheet
Prelimary
63
V0.1, 2006-02
XC886/888CLM
Functional Description
3.8
Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC886/888. The power consumption is indirectly proportional to the frequency, whereas
the performance of the microcontroller is directly proportional to the frequency. During
user program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features:
• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support
The CGU consists of an oscillator circuit and a PLL. In the XC886/888, the oscillator can
be from either of these two sources: the on-chip oscillator (9.6 MHz) or the external
oscillator (3 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip
oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip
oscillator will be used by default.The external oscillator can be selected via software. In
addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock
detection. This allows emergency routines to be executed for system recovery or to
perform system shut down.
Data Sheet
Prelimary
64
V0.1, 2006-02
XC886/888CLM
Functional Description
osc fail
detect
OSCR
LOCK
lock
detect
OSC
P:1
fsys
PLL
core
fvco
fosc
K:1
fp
fn
N:1
PLLBYP
OSCDISC
VCOBYP
NDIV
Figure 25
CGU Block Diagram
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external
clock source. For the XC886/888, the PLL bypass cannot be set active. Hence, the direct
drive mode is not available for use.
fSYS = fOSC
PLL Base Mode
The system clock is derived from the VCO base frequency clock divided by the K factor.
Both VCO bypass and PLL bypass must be inactive for this PLL mode.
1
K
---
fSYS = fVCObase
×
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided
by the P and K factors.
1
-------------
fSYS = fOSC
×
P × K
Data Sheet
Prelimary
65
V0.1, 2006-02
XC886/888CLM
Functional Description
PLL Mode
The system clock is derived from the oscillator clock, multiplied by the N factor, and
divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for
this PLL mode. The PLL mode is used during normal system operation. .
N
P × K
-------------
fSYS = fOSC
×
System Frequency Selection
For the XC886/888, the value of P is fixed to 1. In order to obtain the required fsys, the
value of N and K can be selected by bits NDIV and KDIV respectively for different
oscillator inputs. The output frequency must always be configured for 96 MHz. Table 24
provides examples on how f = 96 MHz can be obtained for the different oscillator
sys
sources.
Table 24
Oscillator
On-chip
System frequency (fsys = 96 MHz)
fosc
N
P
1
1
1
1
K
2
2
2
2
fsys
9.6 MHz
8 MHz
6 MHz
4 MHz
20
24
32
48
96 MHz
96 MHz
96 MHz
96 MHz
External
Table 25 shows the VCO range for the XC886/888.
Table 25
fVCOmin
150
VCO Range
fVCOmax
200
fVCOFREEmin
fVCOFREEmax
Unit
MHz
MHz
20
10
80
80
100
150
3.8.1
Resonator Circuitry
Figure 26 shows the recommended ceramic resonator circuitry. When using an external
resonator, its frequency can be within the range of 3 MHz to 12 MHz. A resonator load
circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists
of two load capacitances C and C , and in some cases, a feedback (R ) and/or damp
1
2
f
(R ) resistor might be necessary.
d
Data Sheet
Prelimary
66
V0.1, 2006-02
XC886/888CLM
Functional Description
C1
XTAL1
Ceramic
Resonator
Rf
XC886/888
C2
Rd
XTAL2
Figure 26
External Ceramic Resonator Circuitry
Note: The manufacturer of the ceramic resonator should check the resonator circuitry
and make recommendations for the C1, C2, Rf and Rd values to be used for stable
start-up behavior.
Data Sheet
Prelimary
67
V0.1, 2006-02
XC886/888CLM
Functional Description
3.8.2
Clock Management
The CGU generates all clock signals required within the microcontroller from a single
clock, f . During normal system operation, the typical frequencies of the different
sys
modules are as follow:
• CPU clock: CCLK, SCLK = 24 MHz
• Fast clock (used by MCAN): FCLK = 24 or 48 MHz
• Peripheral clock: PCLK = 24 MHz
• Flash Interface clock: CCLK2 = 96 MHz and CCLK = 24 MHz
In addition, different clock frequency can output to pin CLKOUT(P0.0 or P0.7). The clock
output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the
resulting output frequency has 50% duty cycle. Figure 27 shows the clock distribution of
the XC886/888.
FCCFG
FCLK
MCAN
CLKREL
PCLK
Peripherals
SCLK
fsys=
96MHz
/2
CORE
fosc
CCLK
OSC
PLL
FLASH
Interface
CCLK2
COREL
N,P,K
TLEN
Toggle
Latch
CLKOUT
COUTS
Figure 27
Clock Generation from fsys
Data Sheet
Prelimary
68
V0.1, 2006-02
XC886/888CLM
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 26.
Table 26
System frequency (fsys = 96 MHz)
Power Saving Mode Action
Idle
Clock to the CPU is disabled.
Slow-down
Clocks to the CPU and all the peripherals are divided by a
common programmable factor defined by bit field
CMCON.CLKREL.
Power-down
Oscillator and PLL are switched off.
Data Sheet
Prelimary
69
V0.1, 2006-02
XC886/888CLM
Functional Description
3.9
Power Saving Modes
The power saving modes of the XC886/888 provide flexible power consumption through
a combination of techniques, including:
• Stopping the CPU clock
• Stopping the clocks of individual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 28) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode
ACTIVE
any interrupt
& SD=0
EXINT0/RXD pin
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
clear SD
bit
POWER-DOWN
IDLE
set IDLE
bit
set PD
bit
any interrupt
& SD=1
EXINT0/RXD pin
& SD=1
SLOW-DOWN
Figure 28
Transition between Power Saving Modes
Data Sheet
Prelimary
70
V0.1, 2006-02
XC886/888CLM
Functional Description
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC886/888 system reset. Hence, routine service of the WDT
confirms that the system is functioning properly. This ensures that an accidental
malfunction of the XC886/888 will be aborted in a user-specified time period. In debug
mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh
the WDT during debugging.
Features:
• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f
/2 or f
/128
PCLK
PCLK
• Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of f
/2 or f
/128. This
PCLK
PCLK
16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT
can be preset to a user-programmable value via a watchdog service access in order to
modify the watchdog expire time period. The lower 8 bits are reset on each service
access. Figure 29 shows the block diagram of the WDT unit.
WDT
Control
WDTREL
Clear
WDT Low Byte
1:2
MUX
WDT High Byte
fPCLK
1:128
Overflow/Time-out Control &
Window-boundary control
WDTTO
WDTRST
WDTIN
ENWDT
Logic
ENWDT_P
WDTWINB
Figure 29
WDT Block Diagram
Data Sheet
Prelimary
71
V0.1, 2006-02
XC886/888CLM
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is
entered. The prewarning period lasts for 30 count, after which the system is reset
H
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000 to the value obtained from the concatenation of WDTWINB and
H
00 .
H
8
After being serviced, the WDT continues counting up from the value (<WDTREL> * 2 ).
The time period for an overflow of the WDT is programmable in two ways:
• the input frequency to the WDT can be selected to be either f
/2 or f
/128
PCLK
PCLK
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
The period, P
, between servicing the WDT and the next overflow can be determined
WDT
by the following formula:
2
(1 + WDTIN × 6) × (216 – WDTREL × 28)
PWDT = -----------------------------------------------------------------------------------------------------
fPCLK
If the Window-Boundary Refresh feature of the WDT is enabled, the period P
WDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 30. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not
be smaller than WDTREL.
Count
FFFFH
WDTWINB
WDTREL
time
No refresh
Refresh allowed
allowed
Figure 30
WDT Timing Diagram
Data Sheet
Prelimary
72
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 27 lists the possible watchdog time range that can be achieved for different
module clock frequencies . Some numbers are rounded to 3 significant digits.
Table 27
Watchdog Time Ranges
Reload value
in WDTREL
Prescaler for fPCLK
2 (WDTIN = 0)
24 MHz
128 (WDTIN = 1)
24 MHz
FF
21.3 µs
1.37 ms
H
7F
2.75 ms
176 ms
H
H
00
5.46 ms
350 ms
Data Sheet
Prelimary
73
V0.1, 2006-02
XC886/888CLM
Functional Description
3.11
UART and UART1
The XC886/888 provides two Universal Asynchronous Receiver/Transmitter (UART and
UART1) modules for full-duplex asynchronous reception/transmission. Both are also
receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features:
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception
The UART modules can operate in four asynchronous modes as shown in Table 28.
Data is transmitted on TXD and received on RXD.
Table 28
UART Modes
Operating Mode
Baud Rate
f /2
PCLK
Mode 0: 8-bit shift register
Mode 1: 8-bit shift UART
Mode 2: 9-bit shift UART
Mode 3: 9-bit shift UART
Variable
/32 or f
1)
f
/64
PCLK
PCLK
Variable
1)
For UART1 module, the baud rate is fixed at f
/64.
PCLK
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
f
/2. In mode 2, the baud rate is generated internally based on the UART input clock
PCLK
and can be configured to either f
/32 or f
/64. For UART1 module, only f
/64
PCLK
PCLK
PCLK
is available. The variable baud rate is set by the underflow rate on the dedicated baud-
rate generator. For UART module, the variable baud rate alternatively can be set by the
overflow rate on Timer 1.
Data Sheet
Prelimary
74
V0.1, 2006-02
XC886/888CLM
Functional Description
3.11.1
Baud-Rate Generator
Both UART modules have their own dedicated baud-rate generator, which is based on
a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and
fractional divider) for generating a wide range of baud rates based on its input clock
f
, see Figure 31.
PCLK
Fractional Divider
8-Bit Reload Value
FDSTEP
1
FDEN&FDM
FDM
1
0
Adder
fDIV
00
01
11
0
1
fBR
8-Bit Baud Rate Timer
0
fMOD
FDRES
(overflow)
10
FDEN
R
fDIV
fPCLK
Prescaler
clk
11
10
NDOV
01
00
‘0’
Figure 31
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (f ) if the fractional divider is enabled (FDCON.FDEN = 1), or the
MOD
output of the prescaler (f ) if the fractional divider is disabled (FDEN = 0). For baud rate
DIV
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (f ) value is dependent on the following parameters:
BR
• Input clock f
• Prescaling factor (2
PCLK
BRPRE
) defined by bit field BRPRE in register BCON
Data Sheet
Prelimary
75
V0.1, 2006-02
XC886/888CLM
Functional Description
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
fPCLK
where 2BRPRE × (BR_VALUE + 1) > 1
-----------------------------------------------------------------------------------
baud rate =
16 × 2BRPRE × (BR_VALUE + 1)
fPCLK
STEP
256
----------------------------------------------------------------------------------- --------------
baud rate =
×
16 × 2BRPRE × (BR_VALUE + 1)
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 29 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 29
Typical Baud rates for UART with Fractional Divider disabled
Baud rate
Prescaling Factor Reload Value
(2BRPRE
(BR_VALUE + 1)
1 (BRPRE=000 ) 78 (4E )
Deviation Error
)
19.2 kBaud
9600 Baud
4800 Baud
2400 Baud
0.17 %
0.17 %
0.17 %
0.17 %
B
H
1 (BRPRE=000 )
156 (9C )
H
B
2 (BRPRE=001 )
156 (9C )
H
B
4 (BRPRE=010 )
156 (9C )
H
B
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 30 lists the resulting deviation errors from generating a baud rate of
115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
Prelimary
76
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 30
fPCLK
Deviation Error for UART with Fractional Divider enabled
Prescaling Factor Reload Value
STEP
Deviation
Error
(2BRPRE
)
(BR_VALUE + 1)
24 MHz
12 MHz
6.67 MHz
1
1
1
10 (A )
197 (C5 )
+0.20 %
+0.03 %
+0.03 %
H
H
6 (6 )
236 (EC )
H
H
3 (3 )
236 (EC )
H
H
Data Sheet
Prelimary
77
V0.1, 2006-02
XC886/888CLM
Functional Description
3.11.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
[3.1]
2
SMOD × fPCLK
Mode 1, 3 baud rate= ----------------------------------------------------
32 × 2 × (256 – TH1)
3.12
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 31). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.
The output frequency in normal divider mode is derived as follows:
[3.2]
1
-----------------------------
fMOD = fDIV
×
256 – STEP
Data Sheet
Prelimary
78
V0.1, 2006-02
XC886/888CLM
Functional Description
3.13
LIN Protocol
The UART module can be used to support the Local Interconnect Network (LIN) protocol
for both master and slave operations. This option is not available with UART1 module.
The LIN baud rate detection feature provides the capability to detect the baud rate within
LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud
rate for data transmission and reception.
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multiple-
slave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 32. The frame consists of the:
• header, which comprises a Break (13-bit time low), Synch Byte (55 ), and ID field
H
• response time
• data bytes (according to UART protocol)
• checksum
Frame slot
Frame
Inter-
frame
space
Response
space
Header
Response
Checksum
Data 2 Data N
Protected
identifier
Data 1
Synch
Figure 32
3.13.1
Structure of LIN Frame
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
Data Sheet
Prelimary
79
V0.1, 2006-02
XC886/888CLM
Functional Description
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet
Prelimary
80
V0.1, 2006-02
XC886/888CLM
Functional Description
3.14
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data Sheet
Prelimary
81
V0.1, 2006-02
XC886/888CLM
Functional Description
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 33 shows the block diagram of the SSC.
PCLK
SS_CLK
MS_CLK
Baud-rate
Generator
Clock
Control
Shift
Clock
RIR
TIR
Receive Int. Request
Transmit Int. Request
Error Int. Request
SSC Control Block
Register CON
EIR
Status
Control
TXD(Master)
RXD(Slave)
Pin
16-Bit Shift
Register
Control
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 33
SSC Block Diagram
Data Sheet
Prelimary
82
V0.1, 2006-02
XC886/888CLM
Functional Description
3.15
Timer 0 and Timer 1
Timer 0 and Timer 1 can function as both timers or counters. When functioning as a
timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input
clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are
incremented in response to a 1-to-0 transition (falling edge) at their respective external
input pins, T0 or T1.
Timer 0 and 1 are fully compatible and can be configured in four different operating
modes for use in a variety of applications, see Table 31. In modes 0, 1 and 2, the two
timers operate independently, but in mode 3, their functions are specialized.
Table 31
Mode
0
Timer 0 and Timer 1 Modes
Operation
13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
1
2
3
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet
Prelimary
83
V0.1, 2006-02
XC886/888CLM
Functional Description
3.16
Timer 2 and Timer 21
Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible
and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel
capture mode. As a timer, the timers count with an input clock of PCLK/12 (if prescaler
is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the counter mode,
the maximum resolution for the count is PCLK/24 (if prescaler is disabled).
Table 32
Mode
Timer 2 Modes
Description
Auto-reload Up/Down Count Disabled
• Count up only
• Start counting from 16-bit reload value, overflow at FFFF
H
• Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event
Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up
– Start counting from 16-bit reload value, overflow at FFFF
– Reload event triggered by overflow condition
– Programmble reload value in register RC2
• Count down
H
– Start counting from FFFF , underflow at value defined in register
H
RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFF
H
Channel
capture
• Count up only
• Start counting from 0000 , overflow at FFFF
H
H
• Reload event triggered by overflow condition
• Reload value fixed at 0000
H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value stored in register RC2
• Interrupt is generated with reload or capture event
Data Sheet
Prelimary
84
V0.1, 2006-02
XC886/888CLM
Functional Description
3.17
Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which
can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor
control. The CCU6 also supports special control modes for block commutation and
multi-phase machines.
The timer T12 can function in capture and/or compare mode for its three channels. The
timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
Timer T12 Features:
• Three capture/compare channels, each channel can be used either as a capture or as
a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for
highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode
Timer T13 Features:
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at period-match and compare-match
• Supports single-shot mode
Additional Features:
• Implements block commutation for Brushless DC-drives
• Position detection via Hall-sensor pattern
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP)
• Control modes for multi-channel AC-drives
• Output levels can be selected and adapted to the power stage
Data Sheet
Prelimary
85
V0.1, 2006-02
XC886/888CLM
Functional Description
The block diagram of the CCU6 module is shown in Figure 34.
module kernel
compare
channel 0
channel 1
channel 2
address
decoder
1
1
1
dead-
time
control
multi-
trap
T12
channel
control
control
clock
control
start
T13
channel 3
compare
1
interrupt
control
3
2
2
2
3
1
input / output control
port control
CCU6_block_diagram
Figure 34
CCU6 Block Diagram
Data Sheet
Prelimary
86
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XC886/888CLM
Functional Description
3.18
Analog-to-Digital Converter
The XC886/888 includes a high-performance 10-bit Analog-to-Digital Converter (ADC)
with eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at Port 2.
Features:
• Successive approximation
• 8-bit or 10-bit resolution
(TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access
(wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter
(accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes
Data Sheet
Prelimary
87
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XC886/888CLM
Functional Description
3.18.1
ADC Clocking Scheme
A common module clock f
generates the various clock signals used by the analog
ADC
and digital parts of the ADC module:
• f
• f
is input clock for the analog part.
is internal clock for the analog part (defines the time base for conversion length
ADCA
ADCI
and the sample time). This clock is generated internally in the analog part, based on
the input clock f to generate a correct duty cycle for the analog components.
ADCA
• f
is input clock for the digital part.
ADCD
The internal clock for the analog part f
is limited to a maximum frequency of 10 MHz.
ADCI
Therefore, the ADC clock prescaler must be programmed to a value that ensures f
ADCI
does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register
GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of
the ADC is not required.
fADC = fPCLK
fADCD
arbiter
registers
interrupts
digital part
fADCA
CTC
MUX
÷32
÷ 4
÷3
fADCI
analog
components
÷ 2
clock prescaler
analog part
1
fADCI
Condition: fADCI 10 MHz, where t ADCI =
≤
Figure 35
ADC Clocking Scheme
Data Sheet
Prelimary
88
V0.1, 2006-02
XC886/888CLM
Functional Description
For module clock f
= 24 MHz, the analog clock f
frequency can be selected as
ADC
ADCI
shown in Table 33.
Table 33
fADCI Frequency Selection
Module Clock fADC
24 MHz
CTC
Prescaling Ratio Analog Clock fADCI
00
01
10
÷ 2
÷ 3
12 MHz (N.A)
8 MHz
B
B
B
÷ 4
6 MHz
11 (default)
÷ 32
750 kHz
B
As f
cannot exceed 10 MHz, bit field CTC should not be set to 00 when f
is
ADC
ADCI
B
24 MHz. During slow-down mode where f
may be reduced to 12 MHz, 6 MHz etc.,
ADC
CTC can be set to 00 as long as the divided analog clock f
does not exceed
B
ADCI
10 MHz. However, it is important to note that the conversion error could increase due to
loss of charges on the capacitors, if f becomes too low during slow-down mode.
ADC
3.18.2
The analog-to-digital conversion procedure consists of the following phases:
• Synchronization phase (t
ADC Conversion Sequence
)
SYN
• Sample phase (t )
S
• Conversion phase
• Write result phase (t
)
WR
conversion start
trigger
Source
interrupt
Channel
interrupt
Result
interrupt
Sample Phase
Conversion Phase
fADCI
BUSY Bit
SAMPLE Bit
tSYN
tS
Write Result Phase
tWR
tCONV
Figure 36
ADC Conversion Timing
Data Sheet
Prelimary
89
V0.1, 2006-02
XC886/888CLM
Functional Description
3.19
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
• use the built-in debug functionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of the operations by a Monitor Program
• use standard interfaces to communicate with the Host (a Debugger)
Features:
• Set breakpoints on instruction address and on address range within the Program
Memory
• Set breakpoints on internal RAM address range
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks via JTAG and upon activating a dedicated pin
• Step through the program code
The OCDS functional blocks are shown in Figure 37. The Monitor Mode Control (MMC)
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals.
After processing memory address and control signals from the core, the MMC provides
proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and
a Monitor RAM (for work-data and Monitor-stack).
1)
The OCDS system is accessed through the JTAG , which is an interface dedicated
exclusively for testing and debugging activities and is not normally used in an
application. The dedicated MBC pin is used for external configuration and debugging
control.
Note: All the debug functionality described here can normally be used only after XC886/
888 has been started in OCDS mode.
1)
The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports
(Ports 1 and 2/Port 5).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet
Prelimary
90
V0.1, 2006-02
XC886/888CLM
Functional Description
JTAG Module
Memory
Control
Unit
TMS
TCK
TCK
TDI
TDO
Debug
Interface
JTAG
TDI
User
Boot/
TDO
Program Monitor
Control
Memory
ROM
Reset
Monitor Mode Control
MBC
Monitor &
Bootstrap loader
Control line
User
Internal
RAM
Monitor
RAM
Suspend
Control
System
Control
Unit
Reset
Clock
Reset Clock Debug PROG PROG Memory
Interface & IRAM Data Control
Addresses
- parts of
OCDS
XC800 Core
OCDS_XC886C-Block_Diagram-UM-v0.2
Figure 37
3.19.1
OCDS Block Diagram
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04 ), and the same is
H
also true immediately after reset.
The JTAG ID register contents for the XC886/888 Flash devices are given in Table 34.
Table 34
Device Type
Flash
JTAG ID Summary
Device Name
JTAG ID
XC886/888*-8FF
XC886/888*-6FF
1012 0083
1012 5083
H
H
Note: The asterisk (*) above denotes all possible device configurations.
Data Sheet
Prelimary
91
V0.1, 2006-02
XC886/888CLM
Functional Description
3.20
Identification Register
The XC886/888 identity register is located at Page 1 of address B3 .
H
ID
Identity Register
Reset Value: 0000 1001B
7
6
5
4
3
2
1
0
PRODID
VERID
r
r
Field
Bits Type Description
VERID
[2:0]
r
Version ID
001
B
PRODID
[7:3]
r
Product ID
00001
B
Data Sheet
Prelimary
92
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4
Electrical Parameters
4.1
General Parameters
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XC886/
888 and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
• CC
These parameters indicate Controller Characteristics, which are distinctive features of
the XC886/888 and must be regarded for a system design.
• SR
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC886/888 designed in.
Data Sheet
Prelimary
93
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XC886/888CLM
Electrical Parameters
4.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC886/888 can be subjected to
without permanent damage.
Table 35
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
min.
-40
max.
125
150
150
6
Ambient temperature
Storage temperature
Junction temperature
TA
°C
°C
°C
V
under bias
TST
TJ
-65
-40
under bias
Voltage on power supply pin with VDDP
respect to VSS
-0.5
Input current on any pin during
overload condition
IIN
-10
–
10
mA
mA
Absolute sum of all input currents Σ|IIN|
tbd
during overload condition
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS
)
the voltage on VDDP pin with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
Prelimary
94
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.1.3
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC886/888. All parameters mentioned in the following table refer to
these operating conditions, unless otherwise noted.
Table 36
Operating Condition Parameters
Symbol Limit Values
Parameter
Unit Notes/
Conditions
min.
4.5
max.
5.5
Digital power supply voltage VDDP
V
5V range
3.0
3.6
V
3.3V range
Digital ground voltage
VSS
VDDC
fSYS
TA
0
V
Digital core supply voltage
2.3
2.7
V
1)
System Clock Frequency
88.8
-40
103.2
85
MHz
°C
Ambient temperature
SAF-XC886/
888...
-40
125
°C
SAK-XC886/
888...
1)
f
is the PLL output clock. During normal operating mode, CPU clock is f
/ 4. Please refer to Figure 27
SYS
SYS
for detailed description.
Data Sheet
Prelimary
95
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.2
DC Parameters
4.2.1
Input/Output Characteristics
Table 37
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
VDDP = 5V Range
Output low voltage
VOL CC
–
–
1.0
0.4
V
V
V
IOL = 15 mA
IOL = 5 mA
Output high voltage
VOH CC VDDP - –
IOH = -15 mA
1.0
VDDP - –
0.4
V
V
IOH = -5 mA
Input low voltage on
port pins
VILP SR
–
0.3 ×
CMOS Mode
VDDP
(all except P0.0 & P0.1)
Input low voltage on
P0.0 & P0.1
VILP0 SR -0.2
0.3 ×
VDDP
V
V
CMOS Mode
CMOS Mode
Input high voltage on
port pins
VIHP SR 0.7 ×
–
VDDP
(all except P0.0 & P0.1)
Input high voltage on
P0.0 & P0.1
VIHP0 SR 0.7 × VDDP
V
V
CMOS Mode
CMOS Mode
VDDP
1)
Input Hysteresis
HYS CC 0.08 ×
–
VDDP
Pull-up current
IPU SR
IPD SR
–
-10
–
µA VIH,min
-150
–
µA VIL,max
Pull-down current
10
–
µA VIL,max
150
µA VIH,min
2)
Input leakage current
IOZ1 CC -1
1
µA 0 < VIN < VDDP
,
T
≤ 125°C
A
Overload currenton any IOV SR -5
pin
5
mA
mA
3)
Absolute sum of
overload currents
Σ|IOV
|
–
tbd
SR
Data Sheet
Prelimary
96
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Table 37
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
min.
max.
VDDP = 3.3V Range
Output low voltage
VOL CC
–
–
1.0
0.4
V
V
V
IOL = 8 mA
IOL = 2.5 mA
IOH = -8 mA
Output high voltage
VOH CC VDDP - –
1.0
VDDP - –
0.4
V
V
IOH = -2.5 mA
Input low voltage on
port pins
VILP SR
–
0.3 ×
CMOS Mode
VDDP
(all except P0.0 & P0.1)
Input low voltage on
P0.0 & P0.1
VILP0 SR -0.2
0.3 ×
VDDP
V
V
CMOS Mode
CMOS Mode
Input high voltage on
port pins
VIHP SR 0.7 ×
–
VDDP
(all except P0.0 & P0.1)
Input high voltage on
P0.0 & P0.1
Input Hysteresis1)
VIHP0 SR 0.7 × VDDP
V
V
CMOS Mode
CMOS Mode
VDDP
HYS CC 0.03 ×
–
VDDP
Pull-up current
IPU SR
IPD SR
–
-5
–
µA VIH,min
-50
–
µA VIL,max
Pull-down current
5
µA VIL,max
50
–
µA VIH,min
Input leakage current2) IOZ1 CC -1
1
µA 0 < VIN < VDDP,
T
≤ 125°C
A
Overload currenton any IOV SR -5
pin
5
mA
mA
3)
Absolute sum of
overload currents
Σ|IOV
|
–
tbd
SR
1)
Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching
due to external system noise.
2)
An additional error current (I ) will flow if an overload current flows through an adjacent pin. TMS pin and
INJ
RESET pin have internal pull devices and are not included in the input leakage current characteristic.
Data Sheet
Prelimary
97
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XC886/888CLM
Electrical Parameters
3)
Not subjected to production test, verified by design/characterization.
4.2.2
Supply Threshold Characteristics
5.0V
VDDPPW
VDDP
2.5V
VDDCPW
VDDCBO
VDDCRDR
VDDCBOPD
VDDC
VDDCPOR
Figure 38
Supply Threshold Parameters
Table 38
Supply Threshold Parameters (Operating Conditions apply)
Symbol Limit Values
Parameters
Unit
min.
CC 2.2
typ.
2.3
2.1
max.
1)
V
V
prewarning voltage
V
V
2.4
2.2
V
V
DDC
DDCPW
brownout voltage in
CC 2.0
DDC
DDCBO
active mode1)
RAM data retention voltage
V
V
CC 0.9
CC 1.3
1.0
1.5
1.1
1.7
V
V
DDCRDR
V
brownout voltage in
DDC
DDCBOPD
2)
power-down mode
3)
V
prewarning voltage
V
V
CC 3.4
CC 1.3
4.0
1.5
4.6
1.7
V
V
DDP
DDPPW
Power-on reset voltage2)4)
DDCPOR
1)
Detection is disabled in power-down mode.
2)
3)
Detection is enabled in both active and power-down mode.
Detection is enabled for external power supply of 5.0V.
Detection must be disabled for external power supply of 3.3V.
4)
The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
Data Sheet
Prelimary
98
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XC886/888CLM
Electrical Parameters
4.2.3
ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (V ) must be
SS
externally connected to one single star point in the system. The voltage difference
between the ground pins must not exceed 200mV.
Table 39
Parameter
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Symbol
Limit Values
typ . max.
Unit
Test Conditions/
Remarks
min.
Analog reference
voltage
V
V
V
V
V
V
–
V
DDP
+ 0.05
V
V
V
AREF
AGND
AGND
DDP
SR + 1
Analog reference
ground
V
V
AREF
- 1
SS
SS
SR - 0.05
Analog input
voltage range
SR
V
V
AREF
AIN
AGND
ADC clocks
f
f
–
–
24
–
25.8
10
MHz module clock
ADC
MHz internal analog clock
ADCI
See Figure 35
Sample time
t
CC (2 + INPCR0.STC) ×
µs
S
t
ADCI
Conversion time
t
CC See Section 4.2.3.1
µs
C
1)
2)
Total unadjusted
error
TUE CC –
–
–
±1
±2
20
LSB
LSB
pF
8-bit conversion.
–
10-bit conversion.
2)3)
Switched
C
C
R
–
–
10
AREFSW
capacitance at the
reference voltage
input
CC
2)4)
Switched
5
7
pF
AINSW
capacitance at the
analog voltage
inputs
CC
2)
2)
Input resistance of
the reference input
CC –
CC –
1
1
2
kΩ
kΩ
AREF
Input resistance of
theselectedanalog
channel
R
1.5
AIN
Data Sheet
Prelimary
99
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
1)
2)
3)
TUE is tested at V
= 5.0 V, V
= 0 V , V
= 5.0 V.
DDP
AREF
AGND
Not subject to production test, verified by design/characterization
This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
4)
The sampling capacity of the conversion C-Network is pre-charged to V
/2 before connecting the input to
AREF
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than V
/2.
AREF
Analog Input Circuitry
REXT
RAIN, On
ANx
VAIN
CEXT
CAINSW
VAGNDx
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFSW
VAGNDx
Figure 39
ADC Input Circuits
Data Sheet
Prelimary
100
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.2.3.1 ADC Conversion Timing
Conversion time, t = t × ( 1 + r × (3 + n + STC) ) , where
C
ADC
r = CTC + 2 for CTC = 00 , 01 or 10 ,
B
B
B
r = 32 for CTC = 11 ,
B
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
t
= 1 / f
ADC
ADC
Data Sheet
Prelimary
101
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.2.4
Power Supply Current
Table 40
Power Supply Current Parameters (Operating Conditions apply;
DDP = 5V range )
V
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
V
DDP = 5V Range
3)
Active Mode
Idle Mode
IDDP
IDDP
IDDP
29
tbd
tbd
tbd
mA
mA
mA
4)
5)
21.1
tbd
Active Mode with slow-down
enabled
6)
7)
Idle Mode with slow-down
enabled
IDDP
IPDP
tbd
tbd
mA
Power-Down Mode
10
tbd
µA
1)
The typical IDDP values are based on prelimary measurements and are to be used as reference only. These
values are periodically measured at TA = + 25 °C and VDDP = 5.0 V.
2)
3)
The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 5.5 V).
I
(active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by
DDP
on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001 ), RESET = VDDP
.
B
4)
5)
6)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 24 MHz, RESET = VDDP
.
I
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
DDP
running at 8 MHz by setting CLKREL in CMCON to 0110 , RESET = VDDP
.
B
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110 ,
B
RESET = VDDP
.
7)
I
(power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs.
Data Sheet
Prelimary
102
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Table 41
Power Supply Current Parameters (Operating Conditions apply;
VDDP = 3.3V range)
Parameter
Symbol
Limit Values Unit Test Condition
typ.1) max.2)
V
DDP = 3.3V Range
3)
Active Mode
Idle Mode
IDDP
IDDP
IDDP
tbd
tbd
tbd
tbd
tbd
tbd
mA
mA
mA
4)
5)
Active Mode with slow-down
enabled
6)
7)
Idle Mode with slow-down
enabled
IDDP
IPDP
tbd
tbd
mA
Power-Down Mode
tbd
tbd
µA
1)
The typical IDDP values are periodically measured at TA = + 25 °C and VDDP = 3.3 V.
2)
3)
The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 3.6 V).
I
(active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by
DDP
on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001 ), RESET = VDDP
.
B
4)
5)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 24 MHz, RESET = VDDP
.
I
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
DDP
running at 8 MHz by setting CLKREL in CMCON to 0110 , RESET = VDDP
.
B
6)
7)
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110 ,,
RESET = VDDP
B
.
I
(power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0= VDDP; rest of the ports
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs
Data Sheet
Prelimary
103
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3
AC Parameters
4.3.1
Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 40, Figure 41 and Figure 42.
VDDP
90%
90%
10%
10%
VSS
tF
tR
Figure 40
Rise/Fall Time Parameters
VDDP
VDDE / 2
VDDE / 2
Test Points
VSS
Figure 41
Testing Waveform, Output Delay
VLoad + 0.1 V
VLoad - 0.1 V
VOH - 0.1 V
VOL - 0.1 V
Timing
Reference
Points
Figure 42
Testing Waveform, Output High Impedance
Data Sheet
Prelimary
104
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3.2
Output Rise/Fall Times
Table 42
Output Rise/Fall Times Parameters (Operating Conditions apply)
Parameter
Symbol
Limit
Unit Test Conditions
Values
min. max.
V
DDP = 5V Range
1) 2)
3)
Rise/fall times
t , t
–
10
ns
ns
20 pF.
20 pF.
R
F
F
VDDP = 3.3V Range
1) 2)
4)
Rise/fall times
t , t
R
–
10
1)
Rise/Fall time measurements are taken with 10% - 90% of the pad supply.
2)
3)
4)
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Additional rise/fall time valid for C = 20pF - 100pF @ 0.125 ns/pF.
L
Additional rise/fall time valid for C = 20pF - 100pF @ 0.225 ns/pF.
L
V
DDP
90%
90%
10%
10%
V
SS
t
t
R
F
Figure 43
Rise/Fall Times Parameters
Data Sheet
Prelimary
105
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3.3
Power-on Reset and PLL Timing
Power-On Reset and PLL Timing (Operating Conditions apply)
Table 43
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Pad operating voltage VPAD CC 2.3
–
–
–
V
On-Chip Oscillator
start-up time
tOSCST
CC
–
500
ns
Flash initialization time tFINIT CC
–
–
160
500
–
–
µs
1)
RESET hold time
tRST SR
µs
VDDP rise time
(10% – 90%) ≤ 500µs
PLL lock-in in time
tLOCK CC
–
–
–
–
200
tbd
µs
ns
2)
PLL accumulated jitter
D
P
1)
RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V).
2)
PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.
Data Sheet
Prelimary
106
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
VDDP
VDDC
VPAD
tOSCST
OSC
PLL
PLL unlock
tLOCK
PLL lock
Flash State
Reset
Initialization
tFINIT
Ready to Read
tRST
RESET
Pads
3)
1)Pad state undefined 2)ENPS control 3)As Programmed
2)
1)
I)until EVR is stable
III) until Flash go IV) CPU reset is released; Boot
to Ready-to-Read ROM software begin execution
II)until PLL is locked
Figure 4-1
Power-on Reset Timing
Data Sheet
Prelimary
107
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3.4
On-Chip Oscillator Characteristics
On-chip Oscillator Characteristics (Operating Conditions apply)
Table 44
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Nominal frequency
fNOM CC –
9.6
–
MHz under nominal
1)
conditions after
IFX-backend trimming
Chip-to-chipfrequency ∆fCC CC -2.5
deviation
–
–
2.5
5.0
%
%
with respect to fNOM
Long term frequency
deviation
∆fLT CC -5.0
with respect to fNOM, over
lifetime and temperature,
for one given device after
trimming
Short term frequency ∆fST CC -1.0
deviation
–
1.0
%
with respect to fNOM,
within one LIN message
(<10 ms .... 100 ms)
1)
Nominal condition: V
= 2.5 V, T = + 25°C.
A
DDC
Data Sheet
Prelimary
108
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3.5
JTAG Timing
Table 45
TCK Clock Timing (Operating Conditions apply; CL = 50 pF)
Symbol Limits
min max
Parameter
Unit
TCK clock period
TCK high time
tTCK SR 50
t1 SR tbd
t2 SR tbd
−
ns
ns
ns
ns
ns
−
TCK low time
−
TCK clock rise time
TCK clock fall time
t3 SR
t4 SR
−
−
tbd
tbd
0.9 V DDP
0.1 V DDP
0.5 V DDP
TCK
t1
t2
t4
t3
tTCK
Figure 44
TCK Clock Timing
Data Sheet
Prelimary
109
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Table 46
JTAG Timing (Operating Conditions apply; CL = 50 pF)
Symbol Limits
min max
Parameter
Unit
TMS setup to TCK
t1 SR tbd
t2 SR tbd
t1 SR tbd
t2 SR tbd
−
ns
ns
ns
ns
ns
ns
ns
TMS hold to TCK
−
TDI setup to TCK
−
TDI hold to TCK
−
TDO valid output from TCK
TDO high impedance to valid output from TCK
TDO valid output to high impedance from TCK
t3 CC
t4 CC
t5 CC
−
−
−
tbd
tbd
tbd
TCK
t2
t1
TMS
t2
t1
TDI
t4
t3
t5
TDO
Figure 45
JTAG Timing
Data Sheet
Prelimary
110
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3.6
SSC Master Mode Timing
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
Table 47
Parameter
Symbol
Limit Values
max.
Unit
min.
CC 2*T
1)
SCLK clock period
t0
t1
t2
t3
–
ns
ns
ns
ns
SSC
MTSR delay from SCLK
MRST setup to SCLK
CC
0
tbd
SR tbd
SR tbd
–
–
MRST hold from SCLK
1)
T
= T
= 1/f
. When f
= 24MHz, t = 83.3ns. T
is the CPU clock period.
SSCmin
CPU
CPU
CPU
CPU
0
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
valid
MRST1)
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 46
SSC Master Mode Timing
Data Sheet
Prelimary
111
V0.1, 2006-02
XC886/888CLM
Package and Quality Declaration
5
Package and Quality Declaration
5.1
Package Outline
Figure 47
PG-TQFP-48-4 Package Outline
Data Sheet
Prelimary
112
V0.1, 2006-02
XC886/888CLM
Package and Quality Declaration
Figure 48
PG-TQFP-64-8 Package Outline
Data Sheet
Prelimary
113
V0.1, 2006-02
XC886/888CLM
Package and Quality Declaration
5.2
Quality Declaration
Table 48 shows the characteristics of the quality parameters in the XC886/888.
Table 48
Quality Parameters
Symbol
Parameter
Limit Values Unit
Notes
Min.
Max.
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
–
2000
V
V
Conforming to
EIA/JESD22-
A114-B
ESD susceptibility
VCDM
–
500
Conforming to
according to Charged
Device Model (CDM) pins
JESD22-C101-C
Data Sheet
Prelimary
114
V0.1, 2006-02
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