SAL-TC377TX-96F300S AB [INFINEON]
The SAL-TC377TX-96F300S AB belongs to the AURIX™ TC37xTX family . AURIX™ second generation comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. In terms of performance, T37xTX offers 3 cores running at 300 MHz and up to 4.3 MBytes embedded RAM, and consuming below 2 W.;
| 型号： | SAL-TC377TX-96F300S AB |
| 厂家： | 
Infineon |
| 描述： | The SAL-TC377TX-96F300S AB belongs to the AURIX™ TC37xTX family . AURIX™ second generation comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. In terms of performance, T37xTX offers 3 cores running at 300 MHz and up to 4.3 MBytes embedded RAM, and consuming below 2 W. |
| 文件： | 总341页 (文件大小：13021K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Bit
Microcontroller
TC37x
32-Bit Single-Chip Microcontroller
AA-Step
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.1, 2021-03
Microcontroller
OPEN MARKET VERSION
Edition 2021-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2021 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
OPEN MARKET VERSION
TC37x AA-Step
Revision History
Page or Item
Subjects (major changes since previous revision)
Version 0.4 is the first version of this document
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
The history is documented in the last chapter
V 0.4, 2018-01
V 0.6, 2018-10
V 0.61, 2019-01
V 0.7, 2019-05
V 1.0, 2020-01
V 1.1, 2021-03
Data Sheet
3
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
4
V 1.1, 2021-03
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TC37x AA-Step
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
TC37x Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LFBGA-292 Package Pinning of TC37x TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LQFP-176 Package Pinning of TC37x T and TP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Sequence of Pads in Pad Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
2.1
2.2
2.3
2.4
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
High performance LVDS Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Calculating the 1.25 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Power Supply Infrastructure and Supply Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Supply Ramp-up and Ramp-down Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Single Supply mode (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Single Supply mode (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
External Supply mode (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
External Supply mode (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
PMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
System Phase Locked Loop (SYS_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Peripheral Phase Locked Loop (PER_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 301
ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
ETH RGMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
3.8
3.9
3.10
3.11
3.12
3.12.1
3.13
3.13.1
3.13.1.1
3.13.1.2
3.13.1.3
3.13.1.4
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.24.1
3.24.2
3.24.3
3.24.4
3.24.5
3.25
3.26
3.27
3.28
3.29
3.30
Data Sheet
5
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TC37x AA-Step
3.30.1
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
4
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Changes from Version 0.4 to Version 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Changes from Version 0.6 to Version 0.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Changes from Version 0.61 to Version 0.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Changes from Version 0.7 to Version 0.71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Changes from Version 0.71 to Version 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Changes from Version 1.0 to Version 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
4.1
4.2
4.3
4.4
4.5
4.6
Data Sheet
6
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TC37x AA-Step
Summary of Features
1
Summary of Features
The TC37x product family has the following features:
•
•
High Performance Microcontroller with three CPU cores
Three 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features:
–
–
–
–
–
–
–
–
–
–
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Multiply-accumulate unit able to sustain 2 MAC operations per cycle
Fully pipelined Floating point unit (FPU)
up to 300 MHz operation at full temperature range
up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR)
up to 64 Kbyte Instruction Scratch-Pad RAM (PSPR)
32 Kbyte Instruction Cache (ICACHE)
16 Kbyte Data Cache (DCACHE)
•
•
Lockstepped shadow cores for up to two TC1.6.2P
Multiple on-chip memories
–
–
–
–
All embedded NVM and SRAM are ECC protected
up to 6 Mbyte Program Flash Memory (PFLASH)
up to 256 Kbyte Data Flash Memory (DFLASH 0) usable for EEPROM emulation
BootROM (BROM)
•
•
•
128-Channel DMA Controller with safe data transfer
Sophisticated interrupt system (ECC protected)
High performance on-chip bus structure
–
–
–
64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
SRI to SPB bus bridges (SFI Bridge)
•
•
•
•
•
Optional Hardware Security Module (HSM) on some variants
Safety Management Unit (SMU) handling safety monitor alarms
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
Hardware I/O Monitor (IOM) for checking of digital I/O
Versatile On-chip Peripheral Units
–
12 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
–
–
–
–
–
–
–
5 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
1 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
2 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
2 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering
15 Single Edge Nibble Transmission (SENT) channels for connection to sensors
1 FlexRayTM module with 2 channels (E-Ray) supporting V2.1
One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management
–
One Capture / Compare 6 module (Two kernels CCU60 and CCU61)
Data Sheet
7
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TC37x AA-Step
Summary of Features
–
–
–
–
–
One General Purpose 12 Timer Unit (GPT120)
2 channel Peripheral Sensor Interface conforming to V1.3 (PSI5)
1 Peripheral Sensor Interface with Serial PHY (PSI5-S)
1 Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1
1 IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)
•
•
Versatile Successive Approximation ADC (VADC)
–
–
Cluster of 12 independent ADC kernels
Input voltage range from 0 V to 5.5V (ADC supply)
Delta-Sigma ADC (DSADC)
6 channels
–
•
•
•
•
•
•
•
•
Digital programmable I/O ports
On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface
Power Management System and on-chip regulators
Clock Generation Unit with System PLL and Peripheral PLL
Embedded Voltage Regulator
Qualified for automotive application according to AEC-Q100 (only applicable after delivery release of the
corresponding sales codes)
•
ISO 26262 Safety Element out of Context for safety requirements up to ASIL D (only applicable for sales codes
listed within a released Safety Package Release Note from IFX)
Data Sheet
8
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TC37x AA-Step
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering
code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply voltage
The package and the type of delivery
Table 1-1 Platform Feature Overview
Feature
TC37x
CPUs
Type
TC1.6.2
Cores / Checker Cores
3 / 2
Max. Freq.
300 MHz
Cache per CPU
SRAM per CPU
Program
32 KB
Data
16 KB
PSPR
64 KB
DSPR
240 KB for CPU0,1/ 96 KB else
DLMU
64 KB
SRAM global
DAM
32 KB
Extension Memory
TCM
-
-
XCM
-
XTM
Program Flash
Size
6 MB
Banks
2 x 3 MB
Data Flash
DMA
Size (single-ended)
Channels
256 KB (DF0) + 128 KB (DF1)
128
1
CONVCTRL
EVADC
Modules
Primary Groups/Channels
Secondary Groups/Channels
Fast Compare Channels
Channels
4 / 32
4 / 64
4
EDSADC
6
Data Sheet
9
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TC37x AA-Step
Summary of Features
Table 1-1 Platform Feature Overview (cont’d)
Feature
TC37x
GTM
Clusters
6 (5 @ 200 MHz + 1 @ 100 MHz)
TIM (8 ch)
TOM (16 ch)
ATOM (8 ch)
MCS (8 ch)
CMU / ICM
PSM
6
3
6
5
1 / 1
1
TBU channels1)
4 (TBU0-3)
SPE
2
CMP / MON
BRC / DPLL
CDTM modules
DTM modules
GPT12
1 / 1
1 / 1
5
16 (6 on TOM, 10 on ATOM)
Timer
1
CCU6
1
STM
Modules
3
FlexRay
Modules
1
Channels
2
CAN
Modules
2
Nodes
2 x 4
1
of which support TT-CAN
Modules
QSPI
5
HSCI Channels
Modules
0
ASCLIN
12
1
I2C
Interfaces
SENT
Channels
15
2
PSI5
Modules
PSI5-S
Modules
1
HSSL
Channels
1
MSC
Channels
2
SDMMC
eMMC/SD Interface
Camera Interface
Modules
-
CIF
-
Ethernet (10/100Mbit/1Gbit)
1
FCE
Modules
SMU
1
Safety Support
yes
yes
1
IOM
Security
HSM+
Data Sheet
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TC37x AA-Step
Summary of Features
Table 1-1 Platform Feature Overview (cont’d)
Feature
TC37x
yes
no
Debug
OCDS
MCDS
miniMCDS
miniMCDS TRAM
AGBT
yes
8 KB
no
Low Power Features
Packages
Standby RAM
SCR
2
yes
Type
Pad Position Configuration /
LFBGA-292 / LQFP-176 /
5 V CMOS / 3.3 V CMOS / LVDS
−40 … +150°C
I/O
Type
Tambient
Range
1) TBU3 has special purpose as angle clock.
Data Sheet
11
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TC37x AA-Step
TC37x Pin Definition and Functions
2
TC37x Pin Definition and Functions
The following figures show the TC37x package variants:
•
•
•
LFBGA-292 for feature package TP (Figure 2-1)
LQFP-176 for feature package T and TP (Figure 2-2)
Sequence of Pads in Pad Frame (Chapter 2.3)
Data Sheet
12
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
2.1
LFBGA-292 Package Pinning of TC37x TP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
NC1
VEXT
P10.7
P10.6
P10.2
P10.3
P10.0
P11.11
P11.9
P11.2
P13.3
P13.1
P14.8
P14.5
P14.1
P15.6
P15.4
P15.1
VDDP3
VSS
A
B
C
D
E
F
P02.0
P02.2
P02.4
P02.6
P02.8
P00.0
P00.2
P00.4
P00.7
VSS
VEXT
P10.8
P10.5
P10.4
P10.1
P11.12
P11.10
P11.3
P13.2
P13.0
P14.6
P14.3
P14.4
P14.0
P15.3
VDDP3
VSS
P15.0
P02.1
P02.3
P02.5
P02.7
P00.1
P00.3
P00.5
P00.9
P15.2
P20.14
VSS
VFLEX P11.15
P11.14
P11.8
P11.5
P11.7
P11.6
P11.1
P11.4
P11.0
P14.10
P12.1
P14.9
P12.0
P14.7
P14.2
P15.8
P15.5
P15.7
VDD
VDD
VSS
VSS
P20.9
P20.6
PORST
P20.12 P20.13
P20.10 P20.11
P02.9
VSS
P11.13
P02.11 P02.10
ESR0
ESR1
P20.7
P20.1
P20.2
P21.3
P21.2
TRST
XTAL2
VDD
P20.8
P20.3
P20.0
P21.5
P21.4
VSS
G
H
J
P01.4
P01.6
P00.6
P00.8
AN43
AN41
P01.3
P01.5
P01.7
P00.10
AN42
AN40
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
G
H
J
P21.7 / P21.6 /
TDO
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VSS
NC
TDI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TCK
P21.1
K
L
VSS
VSS
VSS
VSS
TMS
P21.0
K
L
P00.11 P00.12
VSS
VSS
VDD
P22.10 P22.11
M
N
P
R
T
AN46
AN44
AN47
AN45
P22.8
P22.6
P22.4
P23.7
VSS
P22.9
P22.7
P22.5
P23.6
P23.5
VSS
XTAL1
VEXT
P22.0
P22.2
P23.4
P23.2
P23.0
VEXT
M
N
P
R
T
AN36 /
P40.6
AN38 /
P40.8
VSS
VSS
VSS
VSS
AN39 /
P40.9
AN37 /
P40.7
AN32 /
P40.4
AN34
AN23
AN22
VDD
VDD
P22.1
P22.3
P23.3
P23.1
VEXT
VSS
AN33 /
P40.5
AN35
AN31
AN30
NC1
VAREF VAGND
2
VEVRS
B
AN15
AN14
AN12
AN9
AN6
AN7
AN4
AN3
AN0
AN1
P34.2
P34.3
P34.4
P34.5
P33.14
P33.15
P32.5
P32.6
2
AN29 /
P40.14 P40.13
AN28 /
AN17 /
P40.10
U
V
W
Y
P34.1
P32.7
U
V
AN27 /
P40.3
AN26 /
P40.2
P32.1 /
AN25 /
P40.1
AN24 /
P40.0
AN19 /
P40.12 P40.11
AN18 /
AN16
AN13
AN11
AN8
AN2
P33.0
P33.2
P33.4
P33.6
P33.8
P33.10 P33.12 VGATE
1P
P32.4
W
Y
P32.0 /
P33.11 P33.13 VGATE
1N
VAREF VAGND
1
NC1
AN21
AN20
VSSM
VDDM
AN10
AN5
P33.1
P33.3
P33.5
P33.7
P33.9
P32.2
P32.3
VSS
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TC37xpd - (top view)
Figure 2-1 TC37x TP package variant LFBGA-292
Data Sheet
13
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G1
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Trap input capture
GTM_TIM5_IN4_10
GTM_TIM3_IN0_1
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
External timer start 12
Injection signal from port
MDIO Input
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Shift clock output
Transmit output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
O
MDIO Output
Data Sheet
14
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
G2
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
T12 capture input 60
GTM_TIM5_IN5_11
GTM_TIM3_IN1_1
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
EDSADC_DSCIN5A
CAN10_RXDA
PSI5_RX0A
Receive input
Modulator clock input, channel 5
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
CCU61_CC60INA
SENT_SENT0B
EVADC_G9CH11
EDSADC_EDS5NA
P00.1
Receive input channel 0
Analog input channel 11, group 9
Negative analog input channel 5, pin A
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT5
—
Modulator clock output
Reserved
SENT_SPC0
Transmit output
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
15
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H1
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Digital datastream input, channel 5
Receive input channel 1
Analog input channel 10, group 9
Positive analog input channel 5, pin A
General-purpose output
GTM muxed output
GTM_TIM5_IN6_11
GTM_TIM3_IN1_2
GTM_TIM2_IN1_2
EDSADC_DSDIN5A
SENT_SENT1B
EVADC_G9CH10
EDSADC_EDS5PA
P00.2
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
—
Reference input 0
O2
O3
O4
Shift clock output
Reserved
PSI5_TX0
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
IOM_MON2_8
IOM_REF2_8
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 2
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
16
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H2
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
T12 capture input 61
GTM_TIM5_IN7_10
GTM_TIM3_IN2_1
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
EDSADC_ITR5F
PSI5_RX1A
Modulator clock input, channel 3
Trigger/Gate input, channel 5
RXD inputs (receive data) channel 1
CAN receive input node 3
RX data input
CAN03_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
EVADC_G9CH9
EDSADC_EDS5NB
P00.3
Receive input channel 2
T12 capture input 61
AI
Analog input channel 9, group 9
Negative analog input channel 5, pin B
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Reserved
EDSADC_DSCOUT3
—
Modulator clock output
Reserved
SENT_SPC2
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
17
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J1
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN3_1
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
EVADC_G9CH8
EDSADC_EDS5PB
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
AI
Analog input channel 8, group 9
Positive analog input channel 5, pin B
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
CAN11_TXD
PSI5_TX1
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
18
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J2
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN4_1
GTM_TIM3_IN0_11
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
GTM_DTMT1_1
EVADC_G9CH7
P00.5
Mux input channel 4 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 2
T12 capture input 62
Modulator clock input, channel 2
T12 capture input 62
Receive input channel 4
CAN receive input node 1
CDTM1_DTM0
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
19
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J4
P00.6
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN5_1
GTM_TIM3_IN1_14
GTM_TIM2_IN5_1
EDSADC_ITR4F
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
EVADC_G9CH6
P00.6
Mux input channel 5 of TIM module 3
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 2
Trigger/Gate input, channel 4
Digital datastream input, channel 2
Receive input channel 5
Receive input
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
O5
O6
O7
Positive carrier generator output
Reserved
—
Reserved
EVADC_EMUX10
SENT_SPC5
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
20
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K1
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN6_1
GTM_TIM3_IN2_11
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
EDSADC_DSCIN4A
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
EDSADC_EDS4NA
P00.7
Mux input channel 6 of TIM module 3
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 2
T12 capture input 60
Receive input channel 6
Modulator clock input, channel 4
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
Negative analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
EVADC_FC2BFLOUT
EDSADC_DSCOUT4
EVADC_EMUX11
SENT_SPC6
Transmit output
Boundary flag output, FC channel 2
Modulator clock output
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC60
T12 PWM channel 60
IOM_MON1_8
Monitor input 1
IOM_REF1_13
Reference input 1
Data Sheet
21
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K4
P00.8
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN7_1
GTM_TIM3_IN3_11
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
EDSADC_DSDIN4A
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
EDSADC_EDS4PA
P00.8
Mux input channel 7 of TIM module 3
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 2
T12 capture input 61
Receive input channel 7
Digital datastream input, channel 4
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
Positive analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
22
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K2
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM4_IN0_7
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
EVADC_G9CH3
EDSADC_EDS4NB
P00.9
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
AI
Analog input channel 3, group 9
Negative analog input channel 4, pin B
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
23
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K5
P00.10
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input channel 9
Digital datastream input, channel 1
Analog input channel 2, group 9
Positive analog input channel 4, pin B
General-purpose output
GTM muxed output
GTM_TIM4_IN1_11
GTM_TIM1_IN1_1
GTM_TIM0_IN1_1
SENT_SENT9B
EDSADC_DSDIN1A
EVADC_G9CH2
EDSADC_EDS4PB
P00.10
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT19
ASCLIN4_ASCLK
—
Shift clock output
Reserved
—
Reserved
—
Reserved
SENT_SPC9
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P00.11
Transmit output
T13 PWM channel 63
Monitor input 1
Reference input 1
L1
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trap input capture
GTM_TIM4_IN2_11
GTM_TIM1_IN2_1
GTM_TIM0_IN2_1
CCU60_CTRAPA
EDSADC_DSCIN0A
CCU61_T12HRE
SENT_SENT10B
EVADC_G9CH1
EVADC_FC3CH0
P00.11
Modulator clock input, channel 0
External timer start 12
Receive input channel 10
Analog input channel 1, group 9
Analog input FC channel 3
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT20
ASCLIN4_ASLSO
—
Slave select signal output
Reserved
EDSADC_DSCOUT0
—
Modulator clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
24
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-1 Port 00 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L2
P00.12
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
GTM_TIM4_IN3_11
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
SENT_SENT11B
EVADC_G9CH0
EVADC_FC2CH0
P00.12
Digital datastream input, channel 0
Receive input
Receive input channel 11
Analog input channel 0, group 9
Analog input FC channel 2
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
25
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-2 Port 01 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
G5
P01.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 0 of TIM module 2
Mux input channel 5 of TIM module 0
Slave select input
GTM_TIM4_IN5_2
GTM_TIM2_IN0_14
GTM_TIM0_IN5_8
QSPI3_SLSIB
EVADC_G9CH14
P01.3
AI
Analog input channel 14, group 9
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
GTM_TOUT111
—
Reserved
—
Reserved
QSPI3_SLSO9
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
—
Master slave select output
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
G4
P01.4
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 1 of TIM module 2
Mux input channel 6 of TIM module 0
CAN receive input node 1
Analog input channel 13, group 9
General-purpose output
GTM muxed output
GTM_TIM4_IN6_2
GTM_TIM2_IN1_14
GTM_TIM0_IN6_8
CAN01_RXDC
EVADC_G9CH13
P01.4
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT112
—
Reserved
ASCLIN9_ASLSO
QSPI3_SLSO10
—
Slave select signal output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
26
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H5
P01.5
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 3 of TIM module 2
Mux input channel 2 of TIM module 2
Master SPI data input
Receive input
GTM_TIM5_IN3_2
GTM_TIM2_IN3_7
GTM_TIM2_IN2_7
QSPI3_MRSTC
ASCLIN9_ARXA
EVADC_G9CH12
P01.5
AI
Analog input channel 12, group 9
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT113
—
—
Reserved
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
H4
P01.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 5 of TIM module 5
Mux input channel 5 of TIM module 2
Slave SPI data input
General-purpose output
GTM muxed output
Reserved
GTM_TIM5_IN6_2
GTM_TIM5_IN5_3
GTM_TIM2_IN5_7
QSPI3_MTSRC
P01.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT114
—
ASCLIN9_ASCLK
QSPI3_MTSR
—
Shift clock output
Master SPI data output
Reserved
—
Reserved
—
Reserved
Data Sheet
27
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-2 Port 01 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
J5
P01.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
Receive input
GTM_TIM5_IN7_2
GTM_TIM2_IN7_7
QSPI3_SCLKC
ASCLIN9_ARXB
P01.7
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT115
—
ASCLIN9_ATX
QSPI3_SCLK
—
Transmit output
Master SPI clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
28
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
29
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C2
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT1
IOM_REF0_1
QSPI4_SLSO7
QSPI3_SLSO2
EDSADC_CGPWMP
—
O2
O3
O4
O5
O6
O7
Master slave select output
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
30
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C1
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
Receive input channel 14
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
SENT_SENT14B
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
31
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D2
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Modulator clock input, channel 5
Receive Channel B2
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
EDSADC_DSCIN5B
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
MSC1_SDI1
CAN receive input node 2
Receive input
Upstream assynchronous input signal
RXD inputs (receive data) channel 0
Receive input channel 13
General-purpose output
GTM muxed output
PSI5_RX0B
SENT_SENT13B
P02.3
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
EDSADC_DSCOUT5
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Modulator clock output
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
32
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D1
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
EDSADC_DSDIN5B
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Digital datastream input, channel 5
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
SENT_SENT12B
P02.4
CAN receive input node 1
External CAN time trigger input
Receive input channel 12
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
33
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E2
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Modulator clock input, channel 4
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
EDSADC_DSCIN4B
I2C0_SCLA
PSI5_RX1B
RXD inputs (receive data) channel 1
RX data input
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
EDSADC_DSCOUT4
I2C0_SCL
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Modulator clock output
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
34
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E1
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM3_IN0_10
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
EDSADC_DSDIN4B
EDSADC_ITR5E
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Digital datastream input, channel 4
Trigger/Gate input, channel 5
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
35
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F2
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN1_10
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
EDSADC_ITR4E
GPT120_T3EUDA
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Mux input channel 1 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
Receive input channel 1
Modulator clock input, channel 3
Trigger/Gate input, channel 4
Count direction control input of core timer T3
Hall capture input 1
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
Reference input 0
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
36
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F1
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM3_IN2_10
GTM_TIM3_IN0_2
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
Reference input 0
QSPI3_SLSO5
ASCLIN8_ASCLK
—
O2
O3
O4
O5
O6
O7
Master slave select output
Shift clock output
Reserved
EVADC_EMUX02
GETH_MDC
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
37
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E4
P02.9
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 3 of TIM module 3
Mux input channel 2 of TIM module 0
Receive input
GTM_TIM4_IN2_2
GTM_TIM3_IN3_10
GTM_TIM0_IN2_10
ASCLIN8_ARXA
P02.9
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT116
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
ASCLIN8_ATX
—
Monitor input 2
Reference input 2
O3
O4
O5
Transmit output
Reserved
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
—
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
F5
P02.10
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM4_IN3_2
GTM_TIM3_IN4_11
GTM_TIM0_IN3_10
ASCLIN2_ARXC
CAN01_RXDE
ASCLIN8_ARXB
P02.10
CAN receive input node 1
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT117
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
38
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-3 Port 02 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F4
P02.11
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 5 of TIM module 3
Mux input channel 7 of TIM module 0
Analog input channel 15, group 9
General-purpose output
GTM muxed output
GTM_TIM4_IN4_3
GTM_TIM3_IN5_12
GTM_TIM0_IN7_7
EVADC_G9CH15
AI
P02.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT118
—
Reserved
ASCLIN8_ASLSO
Slave select signal output
Reserved
—
—
—
—
Reserved
Reserved
Reserved
Table 2-4 Port 10 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
A7
P10.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of core timer T6
Receive input
GTM_TIM4_IN0_12
GTM_TIM1_IN4_2
GTM_TIM0_IN4_2
GPT120_T6EUDB
ASCLIN11_ARXA
GETH_RXERC
P10.0
Receive Error MII
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT102
ASCLIN11_ATX
QSPI1_SLSO10
—
Transmit output
Master slave select output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
39
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B7
P10.1
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN4_12
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
Mux input channel 4 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Chip Select
EVADC_FC1BFLOUT
—
Boundary flag output, FC channel 1
Reserved
—
Reserved
A5
P10.2
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN5_12
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 5 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMT2_2
P10.2
CDTM2_DTM0
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI1_SCLK
MSC0_EN0
EVADC_FC3BFLOUT
—
Master SPI clock output
Chip Select
Boundary flag output, FC channel 3
Reserved
—
Reserved
Data Sheet
40
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A6
P10.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN6_10
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
Mux input channel 6 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
B6
P10.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
Trigger/gate input of core timer T3
Receive input
GTM_TIM4_IN7_3
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
P10.4
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT106
IOM_MON2_11
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
—
Master slave select output
Master SPI data output
Chip Select
Reserved
—
Reserved
Data Sheet
41
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B5
P10.5
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM4_IN3_13
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
MSC0_INJ1
Injection signal from port
General-purpose output
GTM muxed output
P10.5
O0
O1
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
Reference input 2
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
—
O6
O7
I
Slave select signal output
Reserved
A4
P10.6
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM4_IN2_13
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
P10.6
Slave SPI data input
HWCFG5 pin input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
—
O5
O6
Reserved
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O7
Data Sheet
42
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-4 Port 10 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A3
P10.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_3
GTM_TIM0_IN0_3
GPT120_T3EUDB
ASCLIN2_ACTSA
QSPI3_MRSTB
SCU_E_REQ0_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Count direction control input of core timer T3
Clear to send input
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS1C
P10.7
Hall capture input 1
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT109
IOM_REF2_11
—
Reference input 2
O2
O3
Reserved
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
B4
P10.8
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 2
Trigger/gate input of timer T4
Slave SPI clock inputs
GTM_TIM4_IN0_13
GTM_TIM1_IN5_2
GTM_TIM0_IN5_2
CAN12_RXDB
GPT120_T4INB
QSPI3_SCLKB
SCU_E_REQ1_2
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS2C
Hall capture input 2
General-purpose output
GTM muxed output
Ready to send output
Master SPI clock output
Reserved
P10.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT110
ASCLIN2_ARTS
QSPI3_SCLK
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
43
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
E10
P11.0
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN0_4
GTM_TIM2_IN0_7
ASCLIN3_ARXB
GTM_DTMA2_1
P11.0
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 2
Receive input
CDTM2_DTM4
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
GTM_TOUT119
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 2
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
CAN11_TXD
GETH_TXD3
—
CAN transmit output node 1
Transmit Data
Reserved
E9
P11.1
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN1_5
GTM_TIM2_IN1_6
P11.1
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Shift clock output
Transmit output
O0
O1
O2
O3
GTM_TOUT120
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
Reserved
O4
O5
O6
O7
CAN12_TXD
GETH_TXD2
—
CAN transmit output node 2
Transmit Data
Reserved
Data Sheet
44
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A10
P11.2
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN1_3
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P11.3
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
B10
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN2_2
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Transmit Channel A
Reserved
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
45
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D10
P11.4
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM4_IN2_5
GTM_TIM2_IN2_6
GETH_RXCLKB
P11.4
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 2
Receive Clock MII
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT121
ASCLIN3_ASCLK
—
Shift clock output
Reserved
—
Reserved
CAN13_TXD
GETH_TXER
GETH_TXCLK
P11.5
CAN transmit output node 3
Transmit Error MII
Transmit Clock Output for RGMII
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 2
Transmit Clock Input for MII
D8
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM4_IN3_5
GTM_TIM2_IN3_8
GETH_TXCLKA
GETH_GREFCLK
Gigabit Reference Clock input for RGMII (125 MHz high
precission)
P11.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT122
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
46
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D9
P11.6
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN3_2
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
P11.7
GTM muxed output
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
I
Monitor input 1
Reference input 1
E8
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM4_IN4_5
GTM_TIM2_IN4_7
GETH_RXD3A
Mux input channel 4 of TIM module 4
Mux input channel 4 of TIM module 2
Receive Data 3 MII and RGMII (RGMII can use RXD3A
only)
CAN11_RXDD
CAN receive input node 1
General-purpose output
GTM muxed output
Reserved
P11.7
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT123
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
47
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E7
P11.8
I
SLOW /
RGMII_In
put / PU1
/ VFLEX /
ES
General-purpose input
GTM_TIM4_IN5_5
GTM_TIM2_IN5_8
GETH_RXD2A
Mux input channel 5 of TIM module 4
Mux input channel 5 of TIM module 2
Receive Data 2 MII and RGMII (RGMII can use RXD2A
only)
CAN12_RXDD
CAN receive input node 2
General-purpose output
GTM muxed output
Reserved
P11.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT124
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
A9
P11.9
FAST /
General-purpose input
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN4_2
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT98
—
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
48
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B9
P11.10
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN5_2
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
49
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A8
P11.11
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN6_2
GTM_TIM3_IN0_14
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
Reserved
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
Master slave select output
Master slave select output
Chip Select
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P11.12
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
B8
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN7_2
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
50
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E6
P11.13
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 6 of TIM module 4
Mux input channel 6 of TIM module 2
Receive Error MII
GTM_TIM4_IN6_5
GTM_TIM2_IN6_7
GETH_RXERA
CAN13_RXDD
CAN receive input node 3
General-purpose output
GTM muxed output
Reserved
P11.13
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT125
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
D7
P11.14
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
GTM_TIM4_IN7_4
GTM_TIM2_IN7_8
GETH_CRSDVB
GETH_RXDVB
GETH_CRSA
P11.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT126
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
51
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-5 Port 11 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D6
P11.15
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 0
Collision MII
GTM_TIM4_IN7_5
GTM_TIM0_IN7_8
GETH_COLA
P11.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT127
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Table 2-6 Port 12 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
E12
P12.0
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 3
CAN receive input node 0
Receive Clock MII
CDTM4_DTM4
GTM_TIM4_IN0_5
GTM_TIM3_IN0_7
CAN00_RXDC
GETH_RXCLKC
GTM_DTMA4_0
P12.0
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT128
—
—
Reserved
—
Reserved
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
Data Sheet
52
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-6 Port 12 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E11
P12.1
I
SLOW /
PU1 /
VFLEX /
ES
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 3
MDIO Input
GTM_TIM4_IN1_6
GTM_TIM3_IN1_6
GETH_MDIOC
P12.1
O0
O1
O2
O3
O4
O5
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT129
ASCLIN3_ASLSO
—
—
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
Reserved
O6
O7
O
—
Reserved
GETH_MDIO
MDIO Output
Table 2-7 Port 13 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B12
P13.0
I
LVDS_TX General-purpose input
/ FAST /
PU1 /
VEXT /
ES6
GTM_TIM3_IN5_3
GTM_TIM2_IN5_3
ASCLIN10_ARXC
P13.0
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
MSC0_FCLN
—
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
CAN transmit output node 0
Data Sheet
53
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A12
P13.1
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN6_3
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 6 of TIM module 2
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
Shift-clock direct part of the differential signal
Serial Clock Output
—
Reserved
B11
P13.2
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN7_3
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 7 of TIM module 2
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
P13.2
Serial Data Input 1
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
—
Reserved
Data Sheet
54
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-7 Port 13 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A11
P13.3
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN0_3
GTM_TIM2_IN0_3
P13.3
Mux input channel 0 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 2
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT94
ASCLIN10_ASLSO
QSPI2_MTSRP
—
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
—
Reserved
Table 2-8 Port 14 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B16
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
55
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A15
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
E13
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
56
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
B14
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
B15
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
57
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A14
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
CDTM2_DTM4
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT85
—
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
—
Transmit Channel B
Reserved
B13
P14.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
—
Transmit Enable Channel B
Reserved
Data Sheet
58
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D13
P14.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive Channel B0
CAN receive input node 0
CAN receive input node 3
Receive input
GTM_TIM4_IN7_10
GTM_TIM1_IN0_5
GTM_TIM0_IN0_5
ERAY0_RXDB0
CAN10_RXDB
CAN13_RXDA
ASCLIN9_ARXC
P14.7
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT87
ASCLIN0_ARTS
QSPI2_SLSO4
ASCLIN9_ATX
—
Ready to send output
Master slave select output
Transmit output
Reserved
—
Reserved
—
Reserved
A13
P14.8
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Receive Channel A0
CAN receive input node 2
Receive input
GTM_TIM3_IN2_3
GTM_TIM2_IN2_3
ERAY0_RXDA0
CAN02_RXDD
ASCLIN1_ARXD
P14.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT88
ASCLIN5_ASLSO
ASCLIN7_ASLSO
—
Slave select signal output
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
59
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-8 Port 14 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D12
P14.9
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN3_3
GTM_TIM2_IN3_3
ASCLIN0_ACTSA
QSPI2_MRSTFN
ASCLIN9_ARXD
P14.9
Mux input channel 3 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 3 of TIM module 2
Clear to send input
Master SPI data input (LVDS N line)
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT89
—
Reserved
MSC0_EN1
CAN10_TXD
ERAY0_TXENB
ERAY0_TXENA
—
Chip Select
CAN transmit output node 0
Transmit Enable Channel B
Transmit Enable Channel A
Reserved
D11
P14.10
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN4_3
GTM_TIM2_IN4_3
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 4 of TIM module 2
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT90
—
MSC0_EN0
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
—
Chip Select
Transmit output
Monitor input 2
Reference input 2
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel A
Reserved
Data Sheet
60
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-9 Port 15 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
B20
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
GTM_TIM3_IN3_4
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
A18
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM3_IN4_4
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
61
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
C19
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Slave select input
GTM_TIM3_IN5_4
GTM_TIM2_IN5_4
QSPI2_SLSIA
SENT_SENT10D
QSPI2_MRSTE
P15.2
Receive input channel 10
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
B17
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM3_IN6_4
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI clock output
Reserved
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
62
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
A17
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN7_4
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT11D
P15.4
Receive input channel 11
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
O0
O1
O2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
63
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E14
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM3_IN0_4
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
A16
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
P15.6
O0
O1
O2
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
64
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-9 Port 15 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D15
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
P15.7
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
D14
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
65
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-10 Port 20 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
H20
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
Shift clock output
Reserved
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
Trigger output
G19
P20.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Trigger input
GTM_TIM4_IN4_11
GTM_TIM3_IN3_5
GTM_TIM2_IN3_5
CBS_TGI1
GTM_DTMA1_1
CDTM1_DTM4
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT60
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CBS_TGO1
Trigger output
Data Sheet
66
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H19
P20.2
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
P20.3
Testmode Enable Input
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
G20
I
SLOW /
PU1 /
VEXT /
ES
GTM_TIM4_IN5_11
GTM_TIM3_IN4_5
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
F17
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM3_IN6_5
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
Ready to send output
Master slave select output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
67
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F19
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
CAN receive input node 0
Clear to send input
GTM_TIM3_IN7_5
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
F20
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
68
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E17
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN5_5
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
E19
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM3_IN6_6
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
69
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
E20
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN7_6
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
D19
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN0_5
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Master SPI data output
Reserved
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
70
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-10 Port 20 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
D20
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM3_IN1_4
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
C20
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN2_4
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
71
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-11 Port 21 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
K17
P21.0
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN0_11
Mux input channel 0 of TIM module 4
PU1 /
VEXT /
ES
GTM_TIM3_IN4_6
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Master SPI data input (LVDS N line)
Enter destructive debug mode
Receive input
GTM_TIM2_IN4_6
QSPI4_MRSTDN
DMU_FDEST
ASCLIN11_ARXC
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT51
ASCLIN11_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM1
Pin Output Value
J17
P21.1
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN1_13
Mux input channel 1 of TIM module 4
PU1 /
VEXT /
ES
GTM_TIM3_IN5_6
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Master SPI data input (LVDS P line)
Receive input
GTM_TIM2_IN5_6
QSPI4_MRSTDP
ASCLIN11_ARXD
GTM_DTMA4_1
CDTM4_DTM4
P21.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT52
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM2
Pin Output Value
Data Sheet
72
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K19
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN4_11
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 4 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
QSPI4_MRSTCN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Master SPI data input (LVDS N line)
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
J19
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN5_12
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
QSPI4_MRSTCP
P21.3
Mux input channel 5 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Shift clock output
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT54
ASCLIN11_ASCLK
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
73
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
K20
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN6_12
Mux input channel 6 of TIM module 5
PU1 /
VEXT /
ES6
GTM_TIM1_IN2_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TIM0_IN2_6
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT55
ASCLIN11_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
J20
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN7_11
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 7 of TIM module 5
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
74
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H17
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ. DAPE: DAPE1 Data I/O.
Mux input channel 2 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM4_IN2_12
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
75
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-11 Port 21 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
H16
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
DAP: DAP2 Data I/O; DAPE: DAPE2 Data I/O.
GTM_TIM4_IN3_12
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
Mux input channel 3 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Data Sheet
76
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-12 Port 22 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
P20
P22.0
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
QSPI4_MTSRB
ASCLIN6_ARXE
P22.0
Mux input channel 1 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 1 of TIM module 0
Slave SPI data input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT47
ASCLIN3_ATXN
QSPI4_MTSR
QSPI4_SCLKN
MSC1_FCLN
—
Differential Transmit output (low active)
Master SPI data output
Master SPI clock output (LVDS N line)
Shift-clock inverted part of the differential signal
Reserved
ASCLIN6_ATX
P22.1
Transmit output
P19
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
QSPI4_MRSTB
ASCLIN7_ARXE
P22.1
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 0
Master SPI data input
Receive input
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT48
ASCLIN3_ATXP
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI4_SCLKP
MSC1_FCLP
—
Differential Transmit output (high active)
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Master SPI clock output (LVDS P line)
Shift-clock direct part of the differential signal
Reserved
ASCLIN7_ATX
Transmit output
Data Sheet
77
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R20
P22.2
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
QSPI4_SLSIB
P22.2
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Slave select input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT49
ASCLIN5_ATX
QSPI4_SLSO3
QSPI4_MTSRN
MSC1_SON
—
Transmit output
Master slave select output
Master SPI data output (LVDS N line)
Data output - inverted part of the differential signal
Reserved
—
Reserved
R19
P22.3
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
QSPI4_SCLKB
ASCLIN5_ARXC
P22.3
Mux input channel 4 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 4 of TIM module 0
Slave SPI clock inputs
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT50
—
Reserved
QSPI4_SCLK
QSPI4_MTSRP
MSC1_SOP
—
Master SPI clock output
Master SPI data output (LVDS P line)
Data output - direct part of the differential signal
Reserved
—
Reserved
P16
P22.4
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Receive input
GTM_TIM3_IN0_8
ASCLIN7_ARXF
GTM_DTMA3_0
P22.4
CDTM3_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT130
ASCLIN4_ASLSO
—
Slave select signal output
Reserved
QSPI0_SLSO12
—
Master slave select output
Reserved
CAN13_TXD
—
CAN transmit output node 3
Reserved
Data Sheet
78
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
P17
P22.5
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 3
Slave SPI data input
CAN receive input node 3
General-purpose output
GTM muxed output
Transmit output
GTM_TIM3_IN1_7
QSPI0_MTSRC
CAN13_RXDC
P22.5
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT131
ASCLIN4_ATX
—
Reserved
QSPI0_MTSR
Master SPI data output
Reserved
—
—
Reserved
—
Reserved
N16
P22.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 2
Master SPI data input
Receive input
GTM_TIM3_IN2_6
GTM_TIM2_IN6_14
QSPI0_MRSTC
ASCLIN4_ARXC
P22.6
O0
O1
O2
O3
O4
General-purpose output
GTM muxed output
Reserved
GTM_TOUT132
—
—
Reserved
QSPI0_MRST
Slave SPI data output
Monitor input 2
IOM_MON2_0
IOM_REF2_0
Reference input 2
Reserved
—
O5
O6
O7
I
—
Reserved
—
Reserved
N17
P22.7
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Shift clock output
Reserved
GTM_TIM3_IN3_7
QSPI0_SCLKC
P22.7
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT133
ASCLIN4_ASCLK
—
QSPI0_SCLK
Master SPI clock output
Reserved
—
—
—
Reserved
Reserved
Data Sheet
79
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
M16
P22.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 5
Mux input channel 4 of TIM module 3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Shift clock output
Reserved
GTM_TIM5_IN0_4
GTM_TIM3_IN4_7
QSPI0_SCLKB
P22.8
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT134
ASCLIN5_ASCLK
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
M17
P22.9
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 5 of TIM module 3
Master SPI data input
Receive input
GTM_TIM5_IN1_10
GTM_TIM3_IN5_7
QSPI0_MRSTB
ASCLIN4_ARXD
GTM_DTMA3_1
P22.9
CDTM3_DTM4
O0
O1
O2
O3
O4
General-purpose output
GTM muxed output
Reserved
GTM_TOUT135
—
—
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O5
O6
O7
—
Reserved
—
Reserved
Data Sheet
80
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-12 Port 22 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
L16
P22.10
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 5
Mux input channel 6 of TIM module 3
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM5_IN2_8
GTM_TIM3_IN6_7
QSPI0_MTSRB
P22.10
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT136
ASCLIN4_ATX
—
Reserved
QSPI0_MTSR
Master SPI data output
Reserved
—
—
Reserved
—
Reserved
L17
P22.11
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 7 of TIM module 3
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TIM5_IN3_10
GTM_TIM3_IN7_7
P22.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT137
ASCLIN4_ASLSO
—
QSPI0_SLSO10
Master slave select output
Reserved
—
—
—
Reserved
Reserved
Data Sheet
81
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-13 Port 23 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
V20
P23.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_4
GTM_TIM0_IN5_4
CAN10_RXDC
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT41
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
U19
P23.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Upstream assynchronous input signal
Receive input
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
MSC1_SDI0
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
CGM generated clock
CAN transmit output node 0
External Clock 0
GTM_TOUT42
ASCLIN1_ARTS
QSPI4_SLSO6
GTM_CLK0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
P23.2
Shift clock output
U20
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_5
GTM_TIM0_IN6_5
ASCLIN7_ARXC
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT43
—
—
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
—
Reserved
Data Sheet
82
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-13 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T19
P23.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
Injection signal from port
Receive input
GTM_TIM1_IN7_4
GTM_TIM0_IN7_4
MSC1_INJ0
ASCLIN6_ARXA
CAN12_RXDC
P23.3
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT44
ASCLIN7_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
T20
P23.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Master slave select output
Reserved
GTM_TIM1_IN7_5
GTM_TIM0_IN7_5
P23.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT45
ASCLIN6_ASLSO
QSPI4_SLSO5
—
MSC1_EN0
—
Chip Select
Reserved
—
Reserved
T17
P23.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN2_7
GTM_TIM0_IN2_7
P23.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT46
ASCLIN6_ATX
QSPI4_SLSO4
—
Master slave select output
Reserved
MSC1_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
83
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-13 Port 23 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
R17
P23.6
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 1
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN2_7
GTM_TIM1_IN2_10
P23.6
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT138
—
—
Reserved
QSPI0_SLSO11
Master slave select output
CAN transmit output node 1
Reserved
CAN11_TXD
—
—
Reserved
R16
P23.7
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 1
CAN receive input node 1
General-purpose output
GTM muxed output
Reserved
GTM_TIM4_IN3_7
GTM_TIM1_IN3_10
CAN11_RXDC
P23.7
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT139
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
84
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-14 Port 32 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
Y17
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM3_IN2_5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN2_5
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
W17
P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
GTM_TIM3_IN3_15
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
Reserved
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT37
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
85
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-14 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y18
P32.2
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 3
Receive input
GTM_TIM1_IN3_8
GTM_TIM0_IN3_8
CAN03_RXDB
ASCLIN3_ARXD
P32.2
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT38
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
Y19
P32.3
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN4_5
GTM_TIM0_IN4_5
P32.3
O0
O1
O2
GTM_TOUT39
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN3_ASCLK
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Shift clock output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Reserved
—
Reserved
Data Sheet
86
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-14 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W18
P32.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
GTM_TIM1_IN5_5
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
MSC1_SDI2
P32.4
Upstream assynchronous input signal
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT40
—
Reserved
—
Reserved
GTM_CLK1
MSC1_EN0
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
PMS_DCDCSYNCO
P32.5
CGM generated clock
Chip Select
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
O
I
DC-DC synchronization output
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 1 of TIM module 4
Mux input channel 5 of TIM module 3
Receive input channel 10
General-purpose output
GTM muxed output
T15
SLOW /
PU1 /
VEXT /
ES
GTM_TIM5_IN5_9
GTM_TIM4_IN1_14
GTM_TIM3_IN5_8
SENT_SENT10C
P32.5
O0
O1
O2
GTM_TOUT140
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
Reserved
—
Reserved
—
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
Reserved
Data Sheet
87
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-14 Port 32 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U15
P32.6
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 4 of TIM module 4
Mux input channel 6 of TIM module 3
CAN receive input node 2
Trigger input
GTM_TIM5_IN6_9
GTM_TIM4_IN4_15
GTM_TIM3_IN6_8
CAN02_RXDC
CBS_TGI4
ASCLIN2_ARXF
ASCLIN6_ARXC
SENT_SENT11C
P32.6
Receive input
Receive input
Receive input channel 11
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT141
—
—
Reserved
QSPI2_SLSO12
—
Master slave select output
Reserved
—
Reserved
—
Reserved
CBS_TGO4
P32.7
Trigger output
U16
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 0 of TIM module 4
Mux input channel 7 of TIM module 3
Trigger input
GTM_TIM5_IN7_8
GTM_TIM4_IN0_15
GTM_TIM3_IN7_8
CBS_TGI5
SENT_SENT12C
P32.7
Receive input channel 12
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT142
ASCLIN6_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CBS_TGO5
Trigger output
Data Sheet
88
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
W10
P33.0
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 13
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM3_IN0_13
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
SENT_SENT13C
IOM_PIN_0
GTM_DTMT1_2
EVADC_G10CH7
P33.0
AI
Analog input channel 7, group 10
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
EVADC_FC2BFLOUT
—
Boundary flag output, FC channel 2
Reserved
Data Sheet
89
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y10
P33.1
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN1_15
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
Receive input
GPIO pad input to FPC
EVADC_G10CH6
P33.1
AI
Analog input channel 6, group 10
General-purpose output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
O2
O3
O4
O5
O6
O7
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
90
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W11
P33.2
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN2_14
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
Digital datastream input, channel 2
GPIO pad input to FPC
EVADC_G10CH5
P33.2
AI
Analog input channel 5, group 10
General-purpose output
O0
O1
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
EVADC_FC3BFLOUT
—
Monitor input 1
Reference input 1
O5
O6
O7
Control of external analog multiplexer interface 0
Boundary flag output, FC channel 3
Reserved
Data Sheet
91
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y11
P33.3
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN3_12
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
SENT_SENT7C
EDSADC_DSCIN1B
IOM_PIN_3
Modulator clock input, channel 1
GPIO pad input to FPC
EVADC_G10CH4
P33.3
AI
Analog input channel 4, group 10
General-purpose output
O0
O1
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
ASCLIN5_ASCLK
QSPI4_SLSO2
EDSADC_DSCOUT1
EVADC_EMUX00
—
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Master slave select output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
92
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W12
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN4_10
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
IOM_PIN_4
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
GPIO pad input to FPC
GTM_DTMT2_0
EVADC_G10CH3
P33.4
CDTM2_DTM0
AI
Analog input channel 3, group 10
General-purpose output
O0
O1
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
Monitor input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
93
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y12
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN5_10
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 5 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
Clear to send input
Hall capture input 2
Receive input channel 5
CAN receive input node 3
GPIO pad input to FPC
EVADC_G10CH2
P33.5
AI
Analog input channel 2, group 10
General-purpose output
O0
O1
GTM_TOUT27
IOM_MON0_5
GTM muxed output
Monitor input 0
IOM_GTM_5
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
EVADC_FC2BFLOUT
ASCLIN5_ASLSO
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 2
Slave select signal output
Data Sheet
94
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W13
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
GTM_DTMT2_1
EVADC_G10CH1
P33.6
CDTM2_DTM0
AI
Analog input channel 1, group 10
General-purpose output
O0
O1
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
Reserved
ASCLIN2_ASLSO
QSPI2_SLSO11
—
O2
O3
O4
O5
O6
O7
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
95
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y13
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT14C
IOM_PIN_7
Receive input channel 14
GPIO pad input to FPC
Analog input channel 0, group 10
General-purpose output
GTM muxed output
EVADC_G10CH0
P33.7
AI
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
QSPI4_SLSO7
ASCLIN8_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Master slave select output
Transmit output
Reserved
EVADC_FC3BFLOUT
—
Boundary flag output, FC channel 3
Reserved
Data Sheet
96
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W14
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO2
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
O
FSP[1..0] Output Signals - Generated by SMU_core
Data Sheet
97
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y14
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO1
ASCLIN2_ASCLK
CAN01_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Shift clock output
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
98
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W15
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN4_14
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
QSPI4_SLSIA
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave select input
CAN receive input node 1
Receive input
GPIO pad input to FPC
P33.10
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
QSPI4_SLSO0
ASCLIN1_ASLSO
PSI5S_CLK
Monitor input 0
O2
O3
O4
O5
Master slave select output
Master slave select output
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GPIO pad input to FPC
General-purpose output
GTM muxed output
Y15
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
QSPI4_SCLKA
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
QSPI4_SCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Master SPI clock output
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
99
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W16
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Slave SPI data input
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
GTM_TIM3_IN0_6
GTM_TIM2_IN0_6
QSPI4_MTSRA
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MTSR
ASCLIN1_ASCLK
—
Monitor input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Shift clock output
Reserved
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
100
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
Y16
P33.13
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM3_IN1_5
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
QSPI4_MRSTA
MSC1_INJ1
Carrier sign signal input
Master SPI data input
Injection signal from port
General-purpose output
GTM muxed output
Transmit output
P33.13
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
101
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-15 Port 33 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T14
P33.14
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 5
Mux input channel 5 of TIM module 4
Mux input channel 0 of TIM module 2
Slave SPI clock inputs
Trigger input
GTM_TIM5_IN0_8
GTM_TIM4_IN5_14
GTM_TIM2_IN0_8
QSPI2_SCLKD
CBS_TGI6
P33.14
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT143
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
CBS_TGO6
P33.15
T12 PWM channel 62
Monitor input 1
Reference input 1
O
I
Trigger output
U14
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 5
Mux input channel 6 of TIM module 4
Mux input channel 1 of TIM module 2
Trigger input
GTM_TIM5_IN1_9
GTM_TIM4_IN6_12
GTM_TIM2_IN1_7
CBS_TGI7
P33.15
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT144
—
QSPI2_SLSO11
—
Master slave select output
Reserved
—
Reserved
—
Reserved
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
CBS_TGO7
T12 PWM channel 62
Monitor input 1
Reference input 1
O
Trigger output
Data Sheet
102
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-16 Port 34 Functions
Ball
Symbol
Ctrl. Buffer
Type
Function
U11
P34.1
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 3 of TIM module 5
Mux input channel 4 of TIM module 3
Mux input channel 3 of TIM module 2
Analog input channel 11, group 10
General-purpose output
GTM muxed output
GTM_TIM5_IN3_9
GTM_TIM3_IN4_12
GTM_TIM2_IN3_9
EVADC_G10CH11
P34.1
AI
O0
O1
O2
O3
O4
GTM_TOUT146
ASCLIN4_ATX
—
Transmit output
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O5
O6
O7
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P34.2
T13 PWM channel 63
Monitor input 1
Reference input 1
T12
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 5 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
GTM_TIM5_IN4_9
GTM_TIM3_IN5_13
GTM_TIM2_IN4_8
ASCLIN4_ARXB
CAN00_RXDG
EVADC_G10CH10
P34.2
CAN receive input node 0
Analog input channel 10, group 10
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT147
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
103
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-16 Port 34 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U12
P34.3
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 6 of TIM module 3
Mux input channel 5 of TIM module 2
Analog input channel 9, group 10
General-purpose output
GTM muxed output
GTM_TIM5_IN5_10
GTM_TIM3_IN6_13
GTM_TIM2_IN5_9
EVADC_G10CH9
P34.3
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT148
ASCLIN4_ASCLK
—
Shift clock output
Reserved
QSPI2_SLSO10
—
Master slave select output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P34.4
T12 PWM channel 60
Monitor input 1
Reference input 1
T13
I
SLOW /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 7 of TIM module 3
Mux input channel 6 of TIM module 2
Master SPI data input
Analog input channel 8, group 10
General-purpose output
GTM muxed output
GTM_TIM5_IN6_10
GTM_TIM3_IN7_12
GTM_TIM2_IN6_8
QSPI2_MRSTD
EVADC_G10CH8
P34.4
AI
O0
O1
O2
O3
O4
GTM_TOUT149
ASCLIN4_ASLSO
—
Slave select signal output
Reserved
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Slave SPI data output
Monitor input 2
Reference input 2
O5
O6
O7
Reserved
—
Reserved
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
104
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-16 Port 34 Functions (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U13
P34.5
I
FAST /
PU1 /
VEVRSB
/ ES
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 7 of TIM module 4
Mux input channel 7 of TIM module 2
Slave SPI data input
Receive input
GTM_TIM5_IN7_9
GTM_TIM4_IN7_12
GTM_TIM2_IN7_9
QSPI2_MTSRD
ASCLIN8_ARXE
P34.5
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT150
ASCLIN8_ATX
—
Reserved
QSPI2_MTSR
—
Master SPI data output
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Table 2-17 Analog Inputs
Ball
Symbol
Ctrl. Buffer
Type
Function
T10
AN0
I
I
I
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
U10
W9
U9
T9
D / HighZ Analog Input 1
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
AN3
Analog input channel 2, group 0
Positive analog input channel 0, pin A
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
D / HighZ Analog Input 4
/ VDDM
EVADC_G11CH0
EVADC_G0CH4
AN5
Analog input channel 0, group 11
Analog input channel 4, group 0
Y9
D / HighZ Analog Input 5
/ VDDM
EVADC_G11CH1
EVADC_G0CH5
Analog input channel 1, group 11
Analog input channel 5, group 0
Data Sheet
105
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-17 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
T8
AN6
I
I
I
I
I
I
I
I
I
I
I
I
D / HighZ Analog Input 6
/ VDDM
EVADC_G11CH2
EVADC_G0CH6
AN7
Analog input channel 2, group 11
Analog input channel 6, group 0
D / HighZ Analog Input 7
U8
W8
U7
Y8
W7
T7
/ VDDM
EVADC_G11CH3
EVADC_G0CH7
AN8
Analog input channel 3, group 11
Analog input channel 7, group 0
D / HighZ Analog Input 8
/ VDDM
EVADC_G11CH4
EVADC_G1CH0
AN9
Analog input channel 4, group 11
Analog input channel 0, group 1
D / HighZ Analog Input 9
/ VDDM
EVADC_G11CH5
EVADC_G1CH1
AN10
Analog input channel 5, group 11
Analog input channel 1, group 1
D / HighZ Analog Input 10
/ VDDM
EVADC_G11CH6
EVADC_G1CH2
AN11
Analog input channel 6, group 11
Analog input channel 2, group 1
D / HighZ Analog Input 11
/ VDDM
EVADC_G11CH7
EVADC_G1CH3
AN12
Analog input channel 7, group 11
Analog input channel 3, group 1
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
EDSADC_EDS0PB
AN13
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
W6
U6
T6
/ VDDM
EVADC_G1CH5
EDSADC_EDS0NB
AN14
Analog input channel 5, group 1
Negative analog input channel 0, pin B
D / HighZ Analog Input 14
/ VDDM
EVADC_G1CH6
EDSADC_EDS3PB
AN15
Analog input channel 6, group 1
Positive analog input channel 3, pin B
D / HighZ Analog Input 15
/ VDDM
EVADC_G1CH7
EDSADC_EDS3NB
AN16
Analog input channel 7, group 1
Negative analog input channel 3, pin N
W5
U5
D / HighZ Analog Input 16
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
AN17/P40.10
SENT_SENT10A
EVADC_G2CH1
EVADC_FC1CH0
Analog input channel 0, group 2
Analog input FC channel 0
S / HighZ Analog Input 17
/ VDDM
Receive input channel 10
Analog input channel 1, group 2
Analog input FC channel 1
Data Sheet
106
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-17 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
W4
AN18/P40.11
I
S / HighZ Analog Input 18
/ VDDM
SENT_SENT11A
EVADC_G11CH8
EVADC_G2CH2
AN19/P40.12
Receive input channel 11
Analog input channel 8, group 11
Analog input channel 2, group 2
W3
I
S / HighZ Analog Input 19
/ VDDM
SENT_SENT12A
EVADC_G11CH9
EVADC_G2CH3
AN20
Receive input channel 12
Analog input channel 9, group 11
Analog input channel 3, group 2
Y3
Y2
I
I
D / HighZ Analog Input 20
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
AN22
Analog input channel 5, group 2
Negative analog input channel 2, pin A
T5
I
I
I
D / HighZ Analog Input 22
/ VDDM
EVADC_G2CH6
AN23
Analog input channel 6, group 2
R5
W2
D / HighZ Analog Input 23
/ VDDM
EVADC_G2CH7
AN24/P40.0
Analog input channel 7, group 2
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
W1
V2
V1
I
I
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN26/P40.2
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
S / HighZ Analog Input 26
/ VDDM
SENT_SENT2A
EVADC_G3CH2
CCU60_CCPOS1D
EVADC_G11CH10
AN27/P40.3
Receive input channel 2
Analog input channel 2, group 3
Hall capture input 1
Analog input channel 10, group 11
S / HighZ Analog Input 27
/ VDDM
SENT_SENT3A
EVADC_G3CH3
CCU60_CCPOS2B
EVADC_G11CH11
Receive input channel 3
Analog input channel 3, group 3
Hall capture input 2
Analog input channel 11, group 11
Data Sheet
107
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-17 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
U2
AN28/P40.13
I
I
S / HighZ Analog Input 28
/ VDDM
SENT_SENT13A
EVADC_G3CH4
AN29/P40.14
Receive input channel 13
Analog input channel 4, group 3
S / HighZ Analog Input 29
U1
/ VDDM
SENT_SENT14A
EVADC_G3CH5
AN30
Receive input channel 14
Analog input channel 5, group 3
T4
R4
P4
I
I
I
D / HighZ Analog Input 30
/ VDDM
EVADC_G3CH6
AN31
Analog input channel 6, group 3
D / HighZ Analog Input 31
/ VDDM
EVADC_G3CH7
AN32/P40.4
Analog input channel 7, group 3
S / HighZ Analog Input 32
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
EVADC_G11CH12
AN33/P40.5
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
Analog input channel 12, group 11
R1
I
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
EVADC_G11CH13
AN34
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
Analog input channel 13, group 11
P5
R2
N4
I
I
I
D / HighZ Analog Input 34
/ VDDM
EVADC_G8CH2
EVADC_G11CH14
AN35
Analog input channel 2, group 8
Analog input channel 14, group 11
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
EVADC_G11CH15
AN36/P40.6
Analog input channel 3, group 8
Analog input channel 15, group 11
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
AN37/P40.7
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
P2
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
Data Sheet
108
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-17 Analog Inputs (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
N5
AN38/P40.8
I
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
P1
I
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
AN40
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
M5
M4
L5
I
I
I
I
I
D / HighZ Analog Input 40
/ VDDM
EVADC_G8CH8
AN41
Analog input channel 8, group 8
D / HighZ Analog Input 41
/ VDDM
EVADC_G8CH9
AN42
Analog input channel 9, group 8
D / HighZ Analog Input 42
/ VDDM
EVADC_G8CH10
AN43
Analog input channel 10, group 8
L4
D / HighZ Analog Input 43
/ VDDM
EVADC_G8CH11
AN44
Analog input channel 11, group 8
N1
D / HighZ Analog Input 44
/ VDDM
EVADC_G8CH12
EDSADC_EDS1PC
AN45
Analog input channel 12, group 8
Positive analog input channel 1, pin C
D / HighZ Analog Input 45
N2
M1
M2
I
I
I
/ VDDM
EVADC_G8CH13
EDSADC_EDS1NC
AN46
Analog input channel 13, group 8
Negative analog input channel 1, pin C
D / HighZ Analog Input 46
/ VDDM
EVADC_G8CH14
EDSADC_EDS1PD
AN47
Analog input channel 14, group 8
Positive analog input channel 1, pin D
D / HighZ Analog Input 47
/ VDDM
EVADC_G8CH15
EDSADC_EDS1ND
Analog input channel 15, group 8
Negative analog input channel 1, pin D
Data Sheet
109
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
1. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
2. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-18 System I/O
Ball
Symbol
Ctrl. Buffer
Type
Function
Y17
VGATE1N
O
—
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
W17
M20
M19
K16
VGATE1P
XTAL1
XTAL2
TMS
O
I
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
O
I
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
TMS: JTAG Module State Machine Control Input. DAP:
DAP1 Data I/O.
DAP1
TRST
I/O
I
DAP: DAP1 Data I/O
L19
J16
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
TRST_N: JTAG Module Reset/Enable Input. DAPE:
DAPE0 Clock Input
TCK
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
TCK: JTAG Module Clock Input. DAP: DAP0 Clock Input.
DAP0
ESR1
I
I
DAP: DAP0 Clock Input
G16
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
PORST
I
ESR1 pin input
G17
I/O
PORST / PORST pin
PD /
VEXT
Power On Reset Input. Additional strong PD in case of
power fail.
Data Sheet
110
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-18 System I/O (cont’d)
Ball
Symbol
Ctrl. Buffer
Type
Function
F16
ESR0
I
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
Table 2-19 Supply
Ball
Symbol
Ctrl. Buffer
Type
Function
D5
VFLEX
I
I
—
—
Digital Power Supply for Flex Port Pads (5V / 3.3V)
Digital Core Power Supply (1.25V)
P8, P13, N7, VDD
N14, E15,
H14, D16,
G13, G8, H7
A2, B3, V19, VEXT
W20
I
—
External Power Supply (5V / 3.3V)
Y5
VDDM
I
I
I
—
—
—
ADC Analog Power Supply (5V / 3.3V)
Flash Power Supply (3.3V)
Digital Ground
B18, A19
VDDP3
B2, D4, E5, VSS
T16, U17,
W19, Y20,
E16, D17,
B19, A20
Y4
VSSM
I
—
Analog Ground for VDDM
Data Sheet
111
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TC37x AA-Step
TC37x Pin Definition and Functions LFBGA-292 Package Pinning of TC37x TP
Table 2-19 Supply (cont’d)
Ball Symbol
Ctrl. Buffer
Type
Function
P9, P12, N9, VSS
N10, N11,
N12, M7,
I
—
Digital Ground
M8, M10,
M11, M13,
M14, L8, L9,
L10, L11,
L12, L13,
K8, K9, K10,
K11, K12,
K13, J7, J8,
J10, J11,
J13, J14, H9,
H10, H11,
H12, G9,
G10, G11,
G12, L14,
P10, P11,
K7, L7
L20
Y6
VSS
I
I
I
I
I
I
—
—
—
—
—
—
Oscillator Ground, VSS(OSC)
VAREF1
VAGND1
VAREF2
VAGND2
NC
Positive Analog Reference Voltage 1
Negative Analog Reference Voltage 1
Positive Analog Reference Voltage 2
Negative Analog Reference Voltage 2
Y7
T1
T2
K14
Not connected. These pins are reserved for future
extensions and shall not be connected externally
A1, Y1, U4
T11
NC1
I
I
—
—
Not connected. These pins are not connected on
package level and will not be used for future
extensions
VEVRSB
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
N19
N20
VDD
I
I
—
—
Digital Power Supply for Oscillator (1.25V), VDD(OSC)
VEXT
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT), VEXT(OSC)
Data Sheet
112
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
2.2
LQFP-176 Package Pinning of TC37x T and TP
Note:In the following QFP package the VFLEX supply is internally connected to VEXT supply and thus does not
show up in the corresponding package drawings neither supply tables as a dedicated pin.
P02.0
P02.1
P02.2
P02.3
P02.4
P02.5
P02.6
P02.7
P02.8
VDD
P00.0
P00.1
P00.2
P00.3
P00.4
P00.5
P00.6
P00.7
P00.8
P00.9
P00.10
P00.11
P00.12
VDD
VEXT
VAREF2
VAGND2
AN47
AN46
AN45
1
2
3
4
5
6
7
8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
P20.14
P20.13
P20.12
P20.11
P20.10
P20.9
P20.8
P20.7
P20.6
VDD
ESR0
PORST
ESR1
P20.3
P20.2
P20.1
P20.0
TCK
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TRST
P21.7 / TDO
TMS
P21.6 / TDI
P21.5
P21.4
P21.3
P21.2
P21.1
P21.0
VEXT
XTAL2
XTAL1
VSS
TC37xpd
(Top View)
AN44
AN39 / P40.9
AN38 / P40.8
AN37 / P40.7
AN36 / P40.6
AN35
AN33 / P40.5
AN32 / P40.4
AN29 / P40.14
AN28 / P40.13
AN27 / P40.3
AN26 / P40.2
AN25 / P40.1
AN24 / P40.0
VDD
VEXT
P22.3
P22.2
P22.1
P22.0
P23.5
P23.4
P23.3
P23.2
P23.1
P23.0
98
97
96
95
94
93
92
91
90
89
Figure 2-2 TC37x T and TP package variant LQFP-176
Data Sheet
113
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
11
P00.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 5
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Trap input capture
GTM_TIM5_IN4_10
GTM_TIM3_IN0_1
GTM_TIM2_IN0_1
CCU61_CTRAPA
CCU60_T12HRE
MSC0_INJ0
External timer start 12
Injection signal from port
MDIO Input
GETH_MDIOA
P00.0
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT9
IOM_REF0_9
ASCLIN3_ASCLK
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
O2
O3
Shift clock output
Transmit output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
CAN10_TXD
—
CAN transmit output node 0
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
GETH_MDIO
T13 PWM channel 63
Monitor input 1
Reference input 1
O
MDIO Output
Data Sheet
114
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
12
P00.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
T12 capture input 60
GTM_TIM5_IN5_11
GTM_TIM3_IN1_1
GTM_TIM2_IN1_1
CCU60_CC60INB
ASCLIN3_ARXE
EDSADC_DSCIN5A
CAN10_RXDA
PSI5_RX0A
Receive input
Modulator clock input, channel 5
CAN receive input node 0
RXD inputs (receive data) channel 0
T12 capture input 60
CCU61_CC60INA
SENT_SENT0B
EVADC_G9CH11
EDSADC_EDS5NA
P00.1
Receive input channel 0
Analog input channel 11, group 9
Negative analog input channel 5, pin A
General-purpose output
GTM muxed output
AI
O0
O1
GTM_TOUT10
IOM_REF0_10
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Reserved
EDSADC_DSCOUT5
—
Modulator clock output
Reserved
SENT_SPC0
Transmit output
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
115
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
13
P00.2
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 6 of TIM module 5
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Digital datastream input, channel 5
Receive input channel 1
Analog input channel 10, group 9
Positive analog input channel 5, pin A
General-purpose output
GTM muxed output
GTM_TIM5_IN6_11
GTM_TIM3_IN1_2
GTM_TIM2_IN1_2
EDSADC_DSDIN5A
SENT_SENT1B
EVADC_G9CH10
EDSADC_EDS5PA
P00.2
AI
O0
O1
GTM_TOUT11
IOM_REF0_11
ASCLIN3_ASCLK
—
Reference input 0
O2
O3
O4
Shift clock output
Reserved
PSI5_TX0
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN03_TXD
Reference input 1
O5
CAN transmit output node 3
Monitor input 2
IOM_MON2_8
IOM_REF2_8
QSPI3_SLSO4
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Reference input 2
O6
O7
Master slave select output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
116
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
14
P00.3
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 7 of TIM module 5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
T12 capture input 61
GTM_TIM5_IN7_10
GTM_TIM3_IN2_1
GTM_TIM2_IN2_1
CCU60_CC61INB
EDSADC_DSCIN3A
EDSADC_ITR5F
PSI5_RX1A
Modulator clock input, channel 3
Trigger/Gate input, channel 5
RXD inputs (receive data) channel 1
CAN receive input node 3
RX data input
CAN03_RXDA
PSI5S_RXA
SENT_SENT2B
CCU61_CC61INA
EVADC_G9CH9
EDSADC_EDS5NB
P00.3
Receive input channel 2
T12 capture input 61
AI
Analog input channel 9, group 9
Negative analog input channel 5, pin B
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT12
IOM_REF0_12
ASCLIN3_ASLSO
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Reserved
EDSADC_DSCOUT3
—
Modulator clock output
Reserved
SENT_SPC2
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
117
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
15
P00.4
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN3_1
GTM_TIM2_IN3_1
SCU_E_REQ2_2
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT3B
EDSADC_DSDIN3A
EDSADC_SGNA
ASCLIN10_ARXA
EVADC_G9CH8
EDSADC_EDS5PB
P00.4
Receive input channel 3
Digital datastream input, channel 3
Carrier sign signal input
Receive input
AI
Analog input channel 8, group 9
Positive analog input channel 5, pin B
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT13
IOM_REF0_13
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
CAN11_TXD
PSI5_TX1
CAN transmit output node 1
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
—
O5
O6
O7
Reserved
SENT_SPC3
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
Transmit output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
118
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
16
P00.5
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN4_1
GTM_TIM3_IN0_11
GTM_TIM2_IN4_1
CCU60_CC62INB
EDSADC_DSCIN2A
CCU61_CC62INA
SENT_SENT4B
CAN11_RXDB
Mux input channel 4 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 2
T12 capture input 62
Modulator clock input, channel 2
T12 capture input 62
Receive input channel 4
CAN receive input node 1
CDTM1_DTM0
GTM_DTMT1_1
EVADC_G9CH7
P00.5
AI
Analog input channel 7, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT14
IOM_REF0_14
EDSADC_CGPWMN
QSPI3_SLSO3
EDSADC_DSCOUT2
EVADC_FC0BFLOUT
SENT_SPC4
Reference input 0
O2
O3
O4
O5
O6
O7
Negative carrier generator output
Master slave select output
Modulator clock output
Boundary flag output, FC channel 0
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
119
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
17
P00.6
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN5_1
GTM_TIM3_IN1_14
GTM_TIM2_IN5_1
EDSADC_ITR4F
EDSADC_DSDIN2A
SENT_SENT5B
ASCLIN5_ARXA
EVADC_G9CH6
P00.6
Mux input channel 5 of TIM module 3
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 2
Trigger/Gate input, channel 4
Digital datastream input, channel 2
Receive input channel 5
Receive input
AI
Analog input channel 6, group 9
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT15
IOM_REF0_15
EDSADC_CGPWMP
—
Reference input 0
O2
O3
O4
O5
O6
O7
Positive carrier generator output
Reserved
—
Reserved
EVADC_EMUX10
SENT_SPC5
Control of external analog multiplexer interface 1
Transmit output
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
120
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
18
P00.7
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN6_1
GTM_TIM3_IN2_11
GTM_TIM2_IN6_1
CCU61_CC60INC
SENT_SENT6B
EDSADC_DSCIN4A
GPT120_T2INA
CCU61_CCPOS0A
CCU60_T12HRB
GTM_DTMT0_2
EVADC_G9CH5
EDSADC_EDS4NA
P00.7
Mux input channel 6 of TIM module 3
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 2
T12 capture input 60
Receive input channel 6
Modulator clock input, channel 4
Trigger/gate input of timer T2
Hall capture input 0
External timer start 12
CDTM0_DTM0
AI
Analog input channel 5, group 9
Negative analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT16
ASCLIN5_ATX
EVADC_FC2BFLOUT
EDSADC_DSCOUT4
EVADC_EMUX11
SENT_SPC6
Transmit output
Boundary flag output, FC channel 2
Modulator clock output
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC60
T12 PWM channel 60
IOM_MON1_8
Monitor input 1
IOM_REF1_13
Reference input 1
Data Sheet
121
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
19
P00.8
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM3_IN7_1
GTM_TIM3_IN3_11
GTM_TIM2_IN7_1
CCU61_CC61INC
SENT_SENT7B
EDSADC_DSDIN4A
GPT120_T2EUDA
CCU61_CCPOS1A
CCU60_T13HRB
ASCLIN10_ARXB
EVADC_G9CH4
EDSADC_EDS4PA
P00.8
Mux input channel 7 of TIM module 3
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 2
T12 capture input 61
Receive input channel 7
Digital datastream input, channel 4
Count direction control input of timer T2
Hall capture input 1
External timer start 13
Receive input
AI
Analog input channel 4, group 9
Positive analog input channel 4, pin A
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT17
QSPI3_SLSO6
ASCLIN10_ATX
—
Master slave select output
Transmit output
Reserved
EVADC_EMUX12
SENT_SPC7
Control of external analog multiplexer interface 1
Transmit output
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
122
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
20
P00.9
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
GTM_TIM4_IN0_7
GTM_TIM1_IN0_1
GTM_TIM0_IN0_1
CCU61_CC62INC
SENT_SENT8B
CCU61_CCPOS2A
EDSADC_DSCIN1A
EDSADC_ITR3F
GPT120_T4EUDA
CCU60_T13HRC
CCU60_T12HRC
EVADC_G9CH3
EDSADC_EDS4NB
P00.9
Mux input channel 0 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 62
Receive input channel 8
Hall capture input 2
Modulator clock input, channel 1
Trigger/Gate input, channel 3
Count direction control input of timer T4
External timer start 13
External timer start 12
AI
Analog input channel 3, group 9
Negative analog input channel 4, pin B
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT18
QSPI3_SLSO7
ASCLIN3_ARTS
EDSADC_DSCOUT1
ASCLIN4_ATX
SENT_SPC8
Master slave select output
Ready to send output
Modulator clock output
Transmit output
Transmit output
CCU61_CC62
T12 PWM channel 62
IOM_MON1_10
IOM_REF1_11
Monitor input 1
Reference input 1
Data Sheet
123
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
21
P00.10
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 1 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input channel 9
Digital datastream input, channel 1
Analog input channel 2, group 9
Positive analog input channel 4, pin B
General-purpose output
GTM muxed output
GTM_TIM4_IN1_11
GTM_TIM1_IN1_1
GTM_TIM0_IN1_1
SENT_SENT9B
EDSADC_DSDIN1A
EVADC_G9CH2
EDSADC_EDS4PB
P00.10
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT19
ASCLIN4_ASCLK
—
Shift clock output
Reserved
—
Reserved
—
Reserved
SENT_SPC9
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P00.11
Transmit output
T13 PWM channel 63
Monitor input 1
Reference input 1
22
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trap input capture
GTM_TIM4_IN2_11
GTM_TIM1_IN2_1
GTM_TIM0_IN2_1
CCU60_CTRAPA
EDSADC_DSCIN0A
CCU61_T12HRE
SENT_SENT10B
EVADC_G9CH1
EVADC_FC3CH0
P00.11
Modulator clock input, channel 0
External timer start 12
Receive input channel 10
Analog input channel 1, group 9
Analog input FC channel 3
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT20
ASCLIN4_ASLSO
—
Slave select signal output
Reserved
EDSADC_DSCOUT0
—
Modulator clock output
Reserved
—
Reserved
—
Reserved
Data Sheet
124
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-20 Port 00 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
23
P00.12
I
SLOW /
PU1 /
VEXT /
ES1
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Clear to send input
GTM_TIM4_IN3_11
GTM_TIM1_IN3_1
GTM_TIM0_IN3_1
ASCLIN3_ACTSA
EDSADC_DSDIN0A
ASCLIN4_ARXA
SENT_SENT11B
EVADC_G9CH0
EVADC_FC2CH0
P00.12
Digital datastream input, channel 0
Receive input
Receive input channel 11
Analog input channel 0, group 9
Analog input FC channel 2
General-purpose output
GTM muxed output
AI
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT21
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
T13 PWM channel 63
Monitor input 1
Reference input 1
Data Sheet
125
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
1
P02.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_2
GTM_TIM0_IN0_2
CCU61_CC60INB
ASCLIN2_ARXG
CCU60_CC60INA
SCU_E_REQ3_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
T12 capture input 60
Receive input
T12 capture input 60
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMA0_0
P02.0
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT0
IOM_REF0_0
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO1
EDSADC_CGPWMN
CAN00_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Negative carrier generator output
CAN transmit output node 0
Monitor input 2
IOM_MON2_5
IOM_REF2_5
ERAY0_TXDA
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Reference input 2
O6
O7
Transmit Channel A
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
126
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
2
P02.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN1_2
GTM_TIM0_IN1_2
ERAY0_RXDA2
ASCLIN2_ARXB
CAN00_RXDA
SCU_E_REQ2_1
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive Channel A2
Receive input
CAN receive input node 0
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P02.1
O0
O1
General-purpose output
GTM muxed output
Reference input 0
GTM_TOUT1
IOM_REF0_1
QSPI4_SLSO7
QSPI3_SLSO2
EDSADC_CGPWMP
—
O2
O3
O4
O5
O6
O7
Master slave select output
Master slave select output
Positive carrier generator output
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
127
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
3
P02.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
T12 capture input 61
T12 capture input 61
Receive input channel 14
General-purpose output
GTM muxed output
GTM_TIM1_IN2_2
GTM_TIM0_IN2_2
CCU61_CC61INB
CCU60_CC61INA
SENT_SENT14B
P02.2
O0
O1
GTM_TOUT2
IOM_REF0_2
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI3_SLSO3
PSI5_TX0
Reference input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
Master slave select output
TXD outputs (send data)
Monitor input 1
IOM_MON1_14
IOM_REF1_14
CAN02_TXD
Reference input 1
O5
CAN transmit output node 2
Monitor input 2
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
Reference input 2
O6
O7
Transmit Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
128
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
4
P02.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Modulator clock input, channel 5
Receive Channel B2
GTM_TIM1_IN3_2
GTM_TIM0_IN3_2
EDSADC_DSCIN5B
ERAY0_RXDB2
CAN02_RXDB
ASCLIN1_ARXG
MSC1_SDI1
CAN receive input node 2
Receive input
Upstream assynchronous input signal
RXD inputs (receive data) channel 0
Receive input channel 13
General-purpose output
GTM muxed output
PSI5_RX0B
SENT_SENT13B
P02.3
O0
O1
GTM_TOUT3
IOM_REF0_3
ASCLIN2_ASLSO
QSPI3_SLSO4
EDSADC_DSCOUT5
—
Reference input 0
O2
O3
O4
O5
O6
O7
Slave select signal output
Master slave select output
Modulator clock output
Reserved
—
Reserved
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
129
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
5
P02.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
T12 capture input 62
GTM_TIM1_IN4_1
GTM_TIM0_IN4_1
CCU61_CC62INB
EDSADC_DSDIN5B
QSPI3_SLSIA
CCU60_CC62INA
I2C0_SDAA
Digital datastream input, channel 5
Slave select input
T12 capture input 62
Serial Data Input 0
CAN11_RXDA
CAN0_ECTT1
SENT_SENT12B
P02.4
CAN receive input node 1
External CAN time trigger input
Receive input channel 12
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT4
IOM_REF0_4
ASCLIN2_ASCLK
QSPI3_SLSO0
PSI5S_CLK
Reference input 0
O2
O3
O4
Shift clock output
Master slave select output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
I2C0_SDA
O5
O6
O7
Serial Data Output
Transmit Enable Channel A
T12 PWM channel 62
Monitor input 1
ERAY0_TXENA
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
130
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
6
P02.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Modulator clock input, channel 4
Serial Clock Input 0
GTM_TIM1_IN5_1
GTM_TIM0_IN5_1
EDSADC_DSCIN4B
I2C0_SCLA
PSI5_RX1B
RXD inputs (receive data) channel 1
RX data input
PSI5S_RXB
QSPI3_MRSTA
SENT_SENT3C
CAN0_ECTT2
P02.5
Master SPI data input
Receive input channel 3
External CAN time trigger input
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT5
IOM_REF0_5
CAN11_TXD
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
EDSADC_DSCOUT4
I2C0_SCL
Reference input 0
O2
O3
CAN transmit output node 1
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Modulator clock output
Serial Clock Output
ERAY0_TXENB
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Enable Channel B
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
131
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
7
P02.6
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
T12 capture input 60
GTM_TIM3_IN0_10
GTM_TIM1_IN6_1
GTM_TIM0_IN6_1
CCU60_CC60INC
SENT_SENT2C
EDSADC_DSDIN4B
EDSADC_ITR5E
GPT120_T3INA
CCU60_CCPOS0A
CCU61_T12HRB
QSPI3_MTSRA
P02.6
Receive input channel 2
Digital datastream input, channel 4
Trigger/Gate input, channel 5
Trigger/gate input of core timer T3
Hall capture input 0
External timer start 12
Slave SPI data input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT6
IOM_REF0_6
PSI5S_TX
Reference input 0
O2
O3
O4
TX data output
QSPI3_MTSR
PSI5_TX1
Master SPI data output
TXD outputs (send data)
Monitor input 1
IOM_MON1_15
EVADC_EMUX00
—
O5
O6
O7
Control of external analog multiplexer interface 0
Reserved
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
132
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
8
P02.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN1_10
GTM_TIM1_IN7_1
GTM_TIM0_IN7_1
CCU60_CC61INC
SENT_SENT1C
EDSADC_DSCIN3B
EDSADC_ITR4E
GPT120_T3EUDA
CCU60_CCPOS1A
QSPI3_SCLKA
CCU61_T13HRB
P02.7
Mux input channel 1 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
T12 capture input 61
Receive input channel 1
Modulator clock input, channel 3
Trigger/Gate input, channel 4
Count direction control input of core timer T3
Hall capture input 1
Slave SPI clock inputs
External timer start 13
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT7
IOM_REF0_7
Reference input 0
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI3_SCLK
Master SPI clock output
Modulator clock output
Control of external analog multiplexer interface 0
Transmit output
EDSADC_DSCOUT3
EVADC_EMUX01
SENT_SPC1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
133
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-21 Port 02 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
9
P02.8
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
T12 capture input 62
GTM_TIM3_IN2_10
GTM_TIM3_IN0_2
GTM_TIM2_IN0_2
CCU60_CC62INC
SENT_SENT0C
CCU60_CCPOS2A
EDSADC_DSDIN3B
EDSADC_ITR3E
GPT120_T4INA
CCU61_T12HRC
CCU61_T13HRC
GTM_DTMA0_1
P02.8
Receive input channel 0
Hall capture input 2
Digital datastream input, channel 3
Trigger/Gate input, channel 3
Trigger/gate input of timer T4
External timer start 12
External timer start 13
CDTM0_DTM4
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT8
IOM_REF0_8
Reference input 0
QSPI3_SLSO5
ASCLIN8_ASCLK
—
O2
O3
O4
O5
O6
O7
Master slave select output
Shift clock output
Reserved
EVADC_EMUX02
GETH_MDC
Control of external analog multiplexer interface 0
MDIO clock
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
134
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-22 Port 10 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
168
P10.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of core timer T6
Receive input
GTM_TIM4_IN0_12
GTM_TIM1_IN4_2
GTM_TIM0_IN4_2
GPT120_T6EUDB
ASCLIN11_ARXA
GETH_RXERC
P10.0
Receive Error MII
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT102
ASCLIN11_ATX
QSPI1_SLSO10
—
Transmit output
Master slave select output
Reserved
—
Reserved
—
Reserved
—
Reserved
169
P10.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Count direction control input of timer T5
Master SPI data input
CDTM0_DTM0
GTM_TIM4_IN4_12
GTM_TIM1_IN1_3
GTM_TIM0_IN1_3
GPT120_T5EUDB
QSPI1_MRSTA
GTM_DTMT0_1
P10.1
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT103
QSPI1_MTSR
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
MSC0_EN1
EVADC_FC1BFLOUT
—
Master SPI data output
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Chip Select
Boundary flag output, FC channel 1
Reserved
—
Reserved
Data Sheet
135
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-22 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
170
P10.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN5_12
GTM_TIM1_IN2_3
GTM_TIM0_IN2_3
CAN02_RXDE
MSC0_SDI1
Mux input channel 5 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
CAN receive input node 2
Upstream assynchronous input signal
Slave SPI clock inputs
QSPI1_SCLKA
GPT120_T6INB
SCU_E_REQ2_0
Trigger/gate input of core timer T6
ERU Channel 2 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GTM_DTMT2_2
P10.2
CDTM2_DTM0
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT104
IOM_MON2_9
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI1_SCLK
MSC0_EN0
EVADC_FC3BFLOUT
—
Master SPI clock output
Chip Select
Boundary flag output, FC channel 3
Reserved
—
Reserved
Data Sheet
136
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-22 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
171
P10.3
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM4_IN6_10
GTM_TIM1_IN3_3
GTM_TIM0_IN3_3
QSPI1_MTSRA
SCU_E_REQ3_0
Mux input channel 6 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Slave SPI data input
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T5INB
P10.3
Trigger/gate input of timer T5
General-purpose output
GTM muxed output
Monitor input 2
O0
O1
GTM_TOUT105
IOM_MON2_10
—
O2
O3
O4
O5
O6
Reserved
QSPI1_MTSR
MSC0_EN0
—
Master SPI data output
Chip Select
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O7
I
Reserved
172
P10.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Slave SPI data input
Hall capture input 0
Trigger/gate input of core timer T3
Receive input
GTM_TIM4_IN7_3
GTM_TIM1_IN6_2
GTM_TIM0_IN6_2
QSPI1_MTSRC
CCU60_CCPOS0C
GPT120_T3INB
ASCLIN11_ARXB
P10.4
O0
O1
General-purpose output
GTM muxed output
Monitor input 2
GTM_TOUT106
IOM_MON2_11
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI1_SLSO8
QSPI1_MTSR
MSC0_EN0
—
Master slave select output
Master SPI data output
Chip Select
Reserved
—
Reserved
Data Sheet
137
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-22 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
173
P10.5
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 4
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
HWCFG4 pin input
GTM_TIM4_IN3_13
GTM_TIM1_IN2_4
GTM_TIM0_IN2_4
PMS_HWCFG4IN
MSC0_INJ1
Injection signal from port
General-purpose output
GTM muxed output
P10.5
O0
O1
GTM_TOUT107
IOM_REF2_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI3_SLSO8
QSPI1_SLSO9
GPT120_T6OUT
Reference input 2
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
External output for overflow/underflow detection of
core timer T6
ASCLIN2_ASLSO
—
O6
O7
I
Slave select signal output
Reserved
174
P10.6
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 4
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
GTM_TIM4_IN2_13
GTM_TIM1_IN3_4
GTM_TIM0_IN3_4
ASCLIN2_ARXD
QSPI3_MTSRB
PMS_HWCFG5IN
P10.6
Slave SPI data input
HWCFG5 pin input
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT108
IOM_REF2_10
ASCLIN2_ASCLK
QSPI3_MTSR
GPT120_T3OUT
Reference input 2
O2
O3
O4
Shift clock output
Master SPI data output
External output for overflow/underflow detection of
core timer T3
—
O5
O6
Reserved
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
—
Slave SPI data output
Monitor input 2
Reference input 2
Reserved
O7
Data Sheet
138
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-22 Port 10 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
175
P10.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN0_3
GTM_TIM0_IN0_3
GPT120_T3EUDB
ASCLIN2_ACTSA
QSPI3_MRSTB
SCU_E_REQ0_2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Count direction control input of core timer T3
Clear to send input
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS1C
P10.7
Hall capture input 1
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT109
IOM_REF2_11
—
Reference input 2
O2
O3
Reserved
QSPI3_MRST
IOM_MON2_3
IOM_REF2_3
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
I
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
176
P10.8
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 2
Trigger/gate input of timer T4
Slave SPI clock inputs
GTM_TIM4_IN0_13
GTM_TIM1_IN5_2
GTM_TIM0_IN5_2
CAN12_RXDB
GPT120_T4INB
QSPI3_SCLKB
SCU_E_REQ1_2
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
CCU60_CCPOS2C
Hall capture input 2
General-purpose output
GTM muxed output
Ready to send output
Master SPI clock output
Reserved
P10.8
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT110
ASCLIN2_ARTS
QSPI3_SCLK
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
139
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-23 Port 11 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
160
P11.2
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN1_3
GTM_TIM2_IN1_3
P11.2
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT95
—
QSPI0_SLSO5
QSPI1_SLSO5
MSC0_EN1
GETH_TXD1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P11.3
Master slave select output
Master slave select output
Chip Select
Transmit Data
T13 PWM channel 63
Monitor input 1
Reference input 1
161
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN2_2
GTM_TIM2_IN2_2
MSC0_SDI3
QSPI1_MRSTB
P11.3
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Upstream assynchronous input signal
Master SPI data input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
GTM_TOUT96
—
QSPI1_MRST
IOM_MON2_1
IOM_REF2_1
ERAY0_TXDA
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Transmit Channel A
Reserved
GETH_TXD0
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Transmit Data
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
140
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-23 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
162
P11.6
I
RFAST / General-purpose input
PU1 /
VFLEX /
ES
GTM_TIM3_IN3_2
GTM_TIM2_IN3_2
QSPI1_SCLKB
P11.6
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Slave SPI clock inputs
O0
O1
O2
O3
O4
O5
O6
General-purpose output
GTM muxed output
GTM_TOUT97
ERAY0_TXENB
QSPI1_SCLK
ERAY0_TXENA
MSC0_FCLP
GETH_TXEN
GETH_TCTL
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
P11.9
Transmit Enable Channel B
Master SPI clock output
Transmit Enable Channel A
Shift-clock direct part of the differential signal
Transmit Enable MII and RMII
Transmit Control for RGMII
T12 PWM channel 61
O7
I
Monitor input 1
Reference input 1
163
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN4_2
GTM_TIM2_IN4_2
QSPI1_MTSRB
ERAY0_RXDA1
GETH_RXD1A
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Slave SPI data input
Receive Channel A1
Receive Data 1 MII, RMII and RGMII (RGMII can use
RXD1A only)
P11.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT98
—
QSPI1_MTSR
—
Master SPI data output
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
141
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-23 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
165
P11.10
I
FAST /
General-purpose input
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN5_2
GTM_TIM2_IN5_2
GTM_TIM2_IN0_9
CAN03_RXDD
ERAY0_RXDB1
ASCLIN1_ARXE
SCU_E_REQ6_3
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Mux input channel 0 of TIM module 2
CAN receive input node 3
Receive Channel B1
Receive input
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
MSC0_SDI0
Upstream assynchronous input signal
GETH_RXD0A
Receive Data 0 MII, RMII and RGMII (RGMII can use
RXD0A only)
QSPI1_SLSIA
P11.10
Slave select input
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT99
—
QSPI0_SLSO3
QSPI1_SLSO3
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
142
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-23 Port 11 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
166
P11.11
I
FAST /
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 0 of TIM module 3
Mux input channel 6 of TIM module 2
Carrier Sense / Data Valid combi-signal for RMII
Receive Data Valid MII
Carrier Sense MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN6_2
GTM_TIM3_IN0_14
GTM_TIM2_IN6_2
GETH_CRSDVA
GETH_RXDVA
GETH_CRSB
GETH_RCTLA
P11.11
Receive Control for RGMII
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT100
—
Reserved
QSPI0_SLSO4
QSPI1_SLSO4
MSC0_EN0
Master slave select output
Master slave select output
Chip Select
ERAY0_TXENB
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P11.12
Transmit Enable Channel B
T12 PWM channel 61
Monitor input 1
Reference input 1
167
I
FAST /
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Reference Clock input for RMII (50 MHz)
Transmit Clock Input for MII
Receive Clock MII
RGMII_In
put / PU1
/ VFLEX /
ES
GTM_TIM3_IN7_2
GTM_TIM2_IN7_2
GETH_REFCLKA
GETH_TXCLKB
GETH_RXCLKA
P11.12
O0
O1
O2
General-purpose output
GTM muxed output
GTM_TOUT101
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
GTM_CLK2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
CGM generated clock
Transmit Channel B
ERAY0_TXDB
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
CCU_EXTCLK1
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
External Clock 1
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
143
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-24 Port 13 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
156
P13.0
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN5_3
GTM_TIM2_IN5_3
ASCLIN10_ARXC
P13.0
Mux input channel 5 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 5 of TIM module 2
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT91
ASCLIN10_ATX
QSPI2_SCLKN
MSC0_EN1
MSC0_FCLN
—
Transmit output
Master SPI clock output (LVDS N line)
Chip Select
Shift-clock inverted part of the differential signal
Reserved
CAN10_TXD
P13.1
CAN transmit output node 0
157
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN6_3
GTM_TIM2_IN6_3
I2C0_SCLB
CAN10_RXDD
ASCLIN10_ARXD
P13.1
Mux input channel 6 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 6 of TIM module 2
Serial Clock Input 1
CAN receive input node 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT92
—
Reserved
QSPI2_SCLKP
—
Master SPI clock output (LVDS P line)
Reserved
MSC0_FCLP
I2C0_SCL
Shift-clock direct part of the differential signal
Serial Clock Output
—
Reserved
Data Sheet
144
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-24 Port 13 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
158
P13.2
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN7_3
GTM_TIM2_IN7_3
GPT120_CAPINA
Mux input channel 7 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 7 of TIM module 2
Trigger input to capture value of timer T5 into CAPREL
register
I2C0_SDAB
P13.2
Serial Data Input 1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM_TOUT93
ASCLIN10_ASCLK
QSPI2_MTSRN
MSC0_FCLP
MSC0_SON
I2C0_SDA
—
GTM muxed output
Shift clock output
Master SPI data output (LVDS N line)
Shift-clock direct part of the differential signal
Data output - inverted part of the differential signal
Serial Data Output
Reserved
159
P13.3
LVDS_TX General-purpose input
/ FAST /
GTM_TIM3_IN0_3
GTM_TIM2_IN0_3
P13.3
Mux input channel 0 of TIM module 3
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 2
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT94
ASCLIN10_ASLSO
QSPI2_MTSRP
—
Slave select signal output
Master SPI data output (LVDS P line)
Reserved
MSC0_SOP
—
Data output - direct part of the differential signal
Reserved
—
Reserved
Data Sheet
145
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-25 Port 14 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
142
P14.0
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN3_5
GTM_TIM0_IN3_5
P14.0
O0
O1
O2
GTM_TOUT80
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
ERAY0_TXDA
ERAY0_TXDB
CAN01_TXD
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Transmit Channel A
Transmit Channel B
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
CCU60_COUT62
IOM_MON1_5
IOM_REF1_1
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
146
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-25 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
143
P14.1
I
FAST /
PU1 /
VEXT /
ES2
General-purpose input
GTM_TIM1_IN4_3
GTM_TIM0_IN4_3
ERAY0_RXDA3
ASCLIN0_ARXA
ERAY0_RXDB3
CAN01_RXDB
SCU_E_REQ3_1
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive Channel A3
Receive input
Receive Channel B3
CAN receive input node 1
ERU Channel 3 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
PMS_PINAWKP
P14.1
PINA ( P14.1) pin input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT81
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
—
Monitor input 2
Reference input 2
Reserved
O3
O4
O5
O6
O7
—
Reserved
—
Reserved
—
Reserved
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
P14.2
T13 PWM channel 63
Monitor input 1
Reference input 1
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
HWCFG2 pin input
General-purpose output
GTM muxed output
Transmit output
144
I
SLOW /
PU2 /
VEXT /
ES
GTM_TIM1_IN5_3
GTM_TIM0_IN5_3
PMS_HWCFG2IN
P14.2
O0
O1
O2
GTM_TOUT82
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO1
—
Monitor input 2
Reference input 2
Master slave select output
Reserved
O3
O4
O5
O6
O7
—
Reserved
ASCLIN2_ASCLK
—
Shift clock output
Reserved
Data Sheet
147
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-25 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
145
P14.3
I
SLOW /
PU2 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_3
GTM_TIM0_IN6_3
PMS_HWCFG3IN
ASCLIN2_ARXA
MSC0_SDI2
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
HWCFG3 pin input
Receive input
Upstream assynchronous input signal
SCU_E_REQ1_0
ERU Channel 1 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P14.3
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT83
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI2_SLSO3
ASCLIN1_ASLSO
ASCLIN3_ASLSO
—
Monitor input 2
Reference input 2
Master slave select output
Slave select signal output
Slave select signal output
Reserved
O3
O4
O5
O6
O7
I
—
Reserved
146
P14.4
SLOW /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
HWCFG6 pin input
CDTM0_DTM0
GTM_TIM1_IN7_2
GTM_TIM0_IN7_2
PMS_HWCFG6IN
GTM_DTMT0_0
P14.4
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT84
—
—
Reserved
—
Reserved
—
Reserved
GETH_PPS
—
Pulse Per Second
Reserved
Data Sheet
148
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-25 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
147
P14.5
I
FAST /
PU2 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
HWCFG1 pin input
CDTM2_DTM4
GTM_TIM1_IN0_4
GTM_TIM0_IN0_4
PMS_HWCFG1IN
GTM_DTMA2_0
P14.5
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Reserved
GTM_TOUT85
—
—
Reserved
—
Reserved
—
Reserved
ERAY0_TXDB
—
Transmit Channel B
Reserved
148
P14.6
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN1_4
GTM_TIM0_IN1_4
P14.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT86
—
QSPI2_SLSO2
CAN13_TXD
—
Master slave select output
CAN transmit output node 3
Reserved
ERAY0_TXENB
—
Transmit Enable Channel B
Reserved
Data Sheet
149
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-25 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
149
P14.7
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Receive Channel B0
CAN receive input node 0
CAN receive input node 3
Receive input
GTM_TIM4_IN7_10
GTM_TIM1_IN0_5
GTM_TIM0_IN0_5
ERAY0_RXDB0
CAN10_RXDB
CAN13_RXDA
ASCLIN9_ARXC
P14.7
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT87
ASCLIN0_ARTS
QSPI2_SLSO4
ASCLIN9_ATX
—
Ready to send output
Master slave select output
Transmit output
Reserved
—
Reserved
—
Reserved
150
P14.8
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Receive Channel A0
CAN receive input node 2
Receive input
GTM_TIM3_IN2_3
GTM_TIM2_IN2_3
ERAY0_RXDA0
CAN02_RXDD
ASCLIN1_ARXD
P14.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT88
ASCLIN5_ASLSO
ASCLIN7_ASLSO
—
Slave select signal output
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
150
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-25 Port 14 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
151
P14.9
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN3_3
GTM_TIM2_IN3_3
ASCLIN0_ACTSA
QSPI2_MRSTFN
ASCLIN9_ARXD
P14.9
Mux input channel 3 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 3 of TIM module 2
Clear to send input
Master SPI data input (LVDS N line)
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT89
—
Reserved
MSC0_EN1
CAN10_TXD
ERAY0_TXENB
ERAY0_TXENA
—
Chip Select
CAN transmit output node 0
Transmit Enable Channel B
Transmit Enable Channel A
Reserved
152
P14.10
LVDS_R General-purpose input
X / FAST /
GTM_TIM3_IN4_3
GTM_TIM2_IN4_3
QSPI2_MRSTFP
P14.10
Mux input channel 4 of TIM module 3
PU1 /
VEXT /
ES
Mux input channel 4 of TIM module 2
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Reserved
O0
O1
O2
O3
O4
GTM_TOUT90
—
MSC0_EN0
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ERAY0_TXDA
—
Chip Select
Transmit output
Monitor input 2
Reference input 2
O5
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
Transmit Channel A
Reserved
Data Sheet
151
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-26 Port 15 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
133
P15.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
General-purpose output
GTM muxed output
GTM_TIM3_IN3_4
GTM_TIM2_IN3_4
P15.0
O0
O1
O2
GTM_TOUT71
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO13
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN02_TXD
IOM_MON2_7
IOM_REF2_7
ASCLIN1_ASCLK
—
CAN transmit output node 2
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
134
P15.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM3_IN4_4
GTM_TIM2_IN4_4
CAN02_RXDA
ASCLIN1_ARXA
QSPI2_SLSIB
SCU_E_REQ7_2
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.1
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
Reference input 2
Master slave select output
Reserved
GTM_TOUT72
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_SLSO5
O3
O4
O5
O6
O7
—
—
—
—
Reserved
Reserved
Reserved
Data Sheet
152
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-26 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
135
P15.2
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Slave select input
GTM_TIM3_IN5_4
GTM_TIM2_IN5_4
QSPI2_SLSIA
SENT_SENT10D
QSPI2_MRSTE
P15.2
Receive input channel 10
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT73
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SLSO0
—
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN01_TXD
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ASCLK
—
CAN transmit output node 1
Monitor input 2
Reference input 2
O6
O7
I
Shift clock output
Reserved
136
P15.3
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 1
Receive input
GTM_TIM3_IN6_4
GTM_TIM2_IN6_4
CAN01_RXDA
ASCLIN0_ARXB
QSPI2_SCLKA
P15.3
Slave SPI clock inputs
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT74
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
QSPI2_SCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI clock output
Reserved
MSC0_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
153
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-26 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
137
P15.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN7_4
GTM_TIM2_IN7_4
I2C0_SCLC
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Serial Clock Input 2
QSPI2_MRSTA
SCU_E_REQ0_0
Master SPI data input
ERU Channel 0 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT11D
P15.4
Receive input channel 11
General-purpose output
GTM muxed output
Transmit output
Monitor input 2
O0
O1
O2
GTM_TOUT75
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Reference input 2
Slave SPI data output
Monitor input 2
O3
Reference input 2
Reserved
O4
O5
O6
O7
—
Reserved
I2C0_SCL
Serial Clock Output
T12 PWM channel 62
Monitor input 1
CCU60_CC62
IOM_MON1_0
IOM_REF1_4
Reference input 1
Data Sheet
154
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-26 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
138
P15.5
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Receive input
GTM_TIM3_IN0_4
GTM_TIM2_IN0_4
ASCLIN1_ARXB
I2C0_SDAC
Serial Data Input 2
QSPI2_MTSRA
SCU_E_REQ4_3
Slave SPI data input
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.5
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT76
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
MSC0_EN0
Chip Select
I2C0_SDA
Serial Data Output
T12 PWM channel 61
Monitor input 1
CCU60_CC61
IOM_MON1_1
IOM_REF1_5
P15.6
Reference input 1
139
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 2
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave SPI data input
General-purpose output
GTM muxed output
Transmit output
GTM_TIM2_IN2_14
GTM_TIM1_IN0_6
GTM_TIM0_IN0_6
QSPI2_MTSRB
P15.6
O0
O1
O2
GTM_TOUT77
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MTSR
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Reserved
QSPI2_SCLK
ASCLIN3_ASCLK
CCU60_CC60
IOM_MON1_2
IOM_REF1_6
Master SPI clock output
Shift clock output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
155
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-26 Port 15 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
140
P15.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Receive input
GTM_TIM1_IN1_5
GTM_TIM0_IN1_5
ASCLIN3_ARXA
QSPI2_MRSTB
P15.7
Master SPI data input
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT78
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI2_MRST
IOM_MON2_2
IOM_REF2_2
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
CCU60_COUT60
IOM_MON1_3
IOM_REF1_3
P15.8
T12 PWM channel 60
Monitor input 1
Reference input 1
141
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GTM_TIM1_IN2_5
GTM_TIM0_IN2_5
QSPI2_SCLKB
SCU_E_REQ5_0
ERU Channel 5 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P15.8
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT79
—
QSPI2_SCLK
—
Master SPI clock output
Reserved
—
Reserved
ASCLIN3_ASCLK
CCU60_COUT61
IOM_MON1_4
IOM_REF1_2
Shift clock output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
156
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-27 Port 20 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
116
P20.0
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM1_IN6_7
GTM_TIM1_IN4_9
GTM_TIM0_IN6_7
CAN03_RXDC
CCU_PAD_SYSCLK
CBS_TGI0
Mux input channel 6 of TIM module 1
Mux input channel 4 of TIM module 1
Mux input channel 6 of TIM module 0
CAN receive input node 3
Sysclk input
Trigger input
SCU_E_REQ6_0
ERU Channel 6 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
GPT120_T6EUDA
P20.0
Count direction control input of core timer T6
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
GTM_TOUT59
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
Shift clock output
Reserved
O3
O4
HSCT0_SYSCLK_OUT O5
sys clock output
Reserved
—
O6
O7
O
—
Reserved
CBS_TGO0
Trigger output
117
P20.1
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 4
Mux input channel 3 of TIM module 3
Mux input channel 3 of TIM module 2
Trigger input
GTM_TIM4_IN4_11
GTM_TIM3_IN3_5
GTM_TIM2_IN3_5
CBS_TGI1
GTM_DTMA1_1
CDTM1_DTM4
P20.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT60
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
CBS_TGO1
Trigger output
Data Sheet
157
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-27 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
118
P20.2
I
S / PU /
VEXT
General-purpose input
This pin is latched at power on reset release to enter test
mode.
TESTMODE
P20.3
Testmode Enable Input
General-purpose input
Mux input channel 5 of TIM module 4
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Receive input
119
I
SLOW /
PU1 /
VEXT /
ES
GTM_TIM4_IN5_11
GTM_TIM3_IN4_5
GTM_TIM2_IN4_5
ASCLIN3_ARXC
GPT120_T6INA
P20.3
Trigger/gate input of core timer T6
General-purpose output
GTM muxed output
O0
O1
O2
GTM_TOUT61
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
QSPI0_SLSO9
QSPI2_SLSO9
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
I
Reserved
—
Reserved
124
P20.6
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
CAN receive input node 2
Receive input
GTM_TIM3_IN6_5
GTM_TIM2_IN6_5
CAN12_RXDA
ASCLIN9_ARXE
P20.6
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT62
ASCLIN1_ARTS
QSPI0_SLSO8
QSPI2_SLSO8
—
Ready to send output
Master slave select output
Master slave select output
Reserved
—
Reserved
—
Reserved
Data Sheet
158
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-27 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
125
P20.7
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Mux input channel 5 of TIM module 1
CAN receive input node 0
Clear to send input
GTM_TIM3_IN7_5
GTM_TIM2_IN7_5
GTM_TIM1_IN5_8
CAN00_RXDB
ASCLIN1_ACTSA
ASCLIN9_ARXF
P20.7
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT63
ASCLIN9_ATX
—
Transmit output
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
CCU61_COUT63
IOM_MON1_7
IOM_REF1_7
P20.8
T13 PWM channel 63
Monitor input 1
Reference input 1
126
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
GTM_TIM1_IN7_3
GTM_TIM0_IN7_3
P20.8
O0
O1
O2
O3
O4
O5
GTM_TOUT64
ASCLIN1_ASLSO
QSPI0_SLSO0
QSPI1_SLSO0
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Slave select signal output
Master slave select output
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
159
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-27 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
127
P20.9
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
GTM_TIM3_IN5_5
GTM_TIM2_IN5_5
CAN03_RXDE
ASCLIN1_ARXC
QSPI0_SLSIB
SCU_E_REQ7_0
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
CAN receive input node 3
Receive input
Slave select input
ERU Channel 7 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
P20.9
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT65
—
QSPI0_SLSO1
QSPI1_SLSO1
—
Master slave select output
Master slave select output
Reserved
—
Reserved
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
P20.10
T12 PWM channel 61
Monitor input 1
Reference input 1
128
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 3
Mux input channel 6 of TIM module 2
General-purpose output
GTM muxed output
Transmit output
GTM_TIM3_IN6_6
GTM_TIM2_IN6_6
P20.10
O0
O1
O2
GTM_TOUT66
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI0_SLSO6
QSPI2_SLSO7
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
ASCLIN1_ASCLK
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Master slave select output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Shift clock output
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
160
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-27 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
129
P20.11
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 3
Mux input channel 7 of TIM module 2
Slave SPI clock inputs
General-purpose output
GTM muxed output
Reserved
GTM_TIM3_IN7_6
GTM_TIM2_IN7_6
QSPI0_SCLKA
P20.11
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT67
—
QSPI0_SCLK
—
Master SPI clock output
Reserved
—
Reserved
—
Reserved
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
P20.12
T12 PWM channel 60
Monitor input 1
Reference input 1
130
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Master SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN0_5
GTM_TIM2_IN0_5
QSPI0_MRSTA
IOM_PIN_13
P20.12
O0
O1
GTM_TOUT68
IOM_MON0_13
—
O2
O3
Reserved
QSPI0_MRST
IOM_MON2_0
IOM_REF2_0
QSPI0_MTSR
—
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Master SPI data output
Reserved
—
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
161
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-27 Port 20 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
131
P20.13
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Slave select input
GTM_TIM3_IN1_4
GTM_TIM2_IN1_4
QSPI0_SLSIA
IOM_PIN_14
P20.13
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT69
IOM_MON0_14
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_SLSO2
QSPI1_SLSO2
QSPI0_SCLK
—
Master slave select output
Master slave select output
Master SPI clock output
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
P20.14
T12 PWM channel 62
Monitor input 1
Reference input 1
132
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
Slave SPI data input
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM3_IN2_4
GTM_TIM2_IN2_4
QSPI0_MTSRA
IOM_PIN_15
P20.14
O0
O1
GTM_TOUT70
IOM_MON0_15
—
O2
O3
O4
O5
O6
O7
Reserved
QSPI0_MTSR
—
Master SPI data output
Reserved
—
Reserved
—
Reserved
—
Reserved
Data Sheet
162
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-28 Port 21 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
105
P21.0
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN0_11
Mux input channel 0 of TIM module 4
PU1 /
VEXT /
ES
GTM_TIM3_IN4_6
Mux input channel 4 of TIM module 3
Mux input channel 4 of TIM module 2
Master SPI data input (LVDS N line)
Enter destructive debug mode
Receive input
GTM_TIM2_IN4_6
QSPI4_MRSTDN
DMU_FDEST
ASCLIN11_ARXC
P21.0
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT51
ASCLIN11_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM1
Pin Output Value
106
P21.1
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM4_IN1_13
Mux input channel 1 of TIM module 4
PU1 /
VEXT /
ES
GTM_TIM3_IN5_6
Mux input channel 5 of TIM module 3
Mux input channel 5 of TIM module 2
Master SPI data input (LVDS P line)
Receive input
GTM_TIM2_IN5_6
QSPI4_MRSTDP
ASCLIN11_ARXD
GTM_DTMA4_1
CDTM4_DTM4
P21.1
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Reserved
GTM_TOUT52
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSM_HSM2
Pin Output Value
Data Sheet
163
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-28 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
107
P21.2
I
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN4_11
GTM_TIM1_IN0_7
GTM_TIM0_IN0_7
QSPI2_MRSTCN
Mux input channel 4 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Master SPI data input (LVDS N line)
Emergency stop Port Pin B input request
SCU_EMGSTOP_POR
T_B
ASCLIN3_ARXGN
HSCT0_RXDN
QSPI4_MRSTCN
ASCLIN11_ARXE
GTM_DTMA1_0
P21.2
Differential Receive input (low active)
Rx data
Master SPI data input (LVDS N line)
Receive input
CDTM1_DTM4
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TOUT53
ASCLIN3_ASLSO
—
—
Reserved
GETH_MDC
—
MDIO clock
Reserved
—
Reserved
108
P21.3
LVDS_R General-purpose input
X / FAST /
GTM_TIM5_IN5_12
GTM_TIM1_IN1_6
GTM_TIM0_IN1_6
QSPI2_MRSTCP
ASCLIN3_ARXGP
GETH_MDIOD
HSCT0_RXDP
QSPI4_MRSTCP
P21.3
Mux input channel 5 of TIM module 5
PU1 /
VEXT /
ES
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Master SPI data input (LVDS P line)
Differential Receive input (high active)
MDIO Input
Rx data
Master SPI data input (LVDS P line)
General-purpose output
GTM muxed output
Shift clock output
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT54
ASCLIN11_ASCLK
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
GETH_MDIO
MDIO Output
Data Sheet
164
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-28 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
109
P21.4
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN6_12
Mux input channel 6 of TIM module 5
PU1 /
VEXT /
ES6
GTM_TIM1_IN2_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Reserved
GTM_TIM0_IN2_6
P21.4
O0
O1
O2
O3
O4
O5
O6
O7
O
GTM_TOUT55
ASCLIN11_ASLSO
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDN
P21.5
Tx data
110
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM5_IN7_11
GTM_TIM1_IN3_6
GTM_TIM0_IN3_6
ASCLIN11_ARXF
P21.5
Mux input channel 7 of TIM module 5
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
O
General-purpose output
GTM muxed output
Shift clock output
Transmit output
Reserved
GTM_TOUT56
ASCLIN3_ASCLK
ASCLIN11_ATX
—
—
Reserved
—
Reserved
—
Reserved
HSCT0_TXDP
Tx data
Data Sheet
165
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-28 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
111
P21.6/TDI
I
FAST /
General-purpose input
PD / PU2 PD during Reset and in DAP/DAPE or JTAG mode. After
/ VEXT / Reset release and when not in DAP/DAPE or JTAG mode:
ES3
PU. In Standby mode: HighZ. DAPE: DAPE1 Data I/O.
Mux input channel 2 of TIM module 4
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Count direction control input of timer T5
Receive input
GTM_TIM4_IN2_12
GTM_TIM1_IN4_8
GTM_TIM0_IN4_8
GPT120_T5EUDA
ASCLIN3_ARXF
CBS_TGI2
TDI
Trigger input
JTAG Module Data Input
General-purpose output
GTM muxed output
P21.6
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT57
ASCLIN3_ASLSO
—
Slave select signal output
Reserved
—
Reserved
—
Reserved
—
Reserved
GPT120_T3OUT
External output for overflow/underflow detection of
core timer T3
CBS_TGO2
DAP3
O
Trigger output
I/O
DAP: DAP3 Data I/O
Data Sheet
166
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-28 Port 21 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
113
P21.7/TDO
I
FAST /
PU2 /
VEXT /
ES4
General-purpose input
DAP: DAP2 Data I/O; DAPE: DAPE2 Data I/O.
GTM_TIM4_IN3_12
GTM_TIM1_IN5_7
GTM_TIM0_IN5_7
GPT120_T5INA
CBS_TGI3
Mux input channel 3 of TIM module 4
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/gate input of timer T5
Trigger input
GETH_RXERB
P21.7
Receive Error MII
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT58
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
ASCLIN3_ASCLK
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Shift clock output
Reserved
—
Reserved
—
Reserved
GPT120_T6OUT
External output for overflow/underflow detection of
core timer T6
CBS_TGO3
DAP2
O
Trigger output
I/O
O
DAP: DAP2 Data I/O
JTAG Module Data Output
TDO
Data Sheet
167
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-29 Port 22 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
95
P22.0
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN1_7
GTM_TIM0_IN1_7
QSPI4_MTSRB
ASCLIN6_ARXE
P22.0
Mux input channel 1 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 1 of TIM module 0
Slave SPI data input
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT47
ASCLIN3_ATXN
QSPI4_MTSR
QSPI4_SCLKN
MSC1_FCLN
—
Differential Transmit output (low active)
Master SPI data output
Master SPI clock output (LVDS N line)
Shift-clock inverted part of the differential signal
Reserved
ASCLIN6_ATX
P22.1
Transmit output
96
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN0_8
GTM_TIM0_IN0_8
QSPI4_MRSTB
ASCLIN7_ARXE
P22.1
Mux input channel 0 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 0 of TIM module 0
Master SPI data input
Receive input
O0
O1
O2
O3
General-purpose output
GTM muxed output
GTM_TOUT48
ASCLIN3_ATXP
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI4_SCLKP
MSC1_FCLP
—
Differential Transmit output (high active)
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
O6
O7
Master SPI clock output (LVDS P line)
Shift-clock direct part of the differential signal
Reserved
ASCLIN7_ATX
Transmit output
Data Sheet
168
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-29 Port 22 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
97
P22.2
I
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN3_7
GTM_TIM0_IN3_7
QSPI4_SLSIB
P22.2
Mux input channel 3 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 3 of TIM module 0
Slave select input
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
GTM_TOUT49
ASCLIN5_ATX
QSPI4_SLSO3
QSPI4_MTSRN
MSC1_SON
—
Transmit output
Master slave select output
Master SPI data output (LVDS N line)
Data output - inverted part of the differential signal
Reserved
—
Reserved
98
P22.3
LVDS_TX General-purpose input
/ FAST /
GTM_TIM1_IN4_4
GTM_TIM0_IN4_4
QSPI4_SCLKB
ASCLIN5_ARXC
P22.3
Mux input channel 4 of TIM module 1
PU1 /
VEXT /
ES6
Mux input channel 4 of TIM module 0
Slave SPI clock inputs
Receive input
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
GTM_TOUT50
—
Reserved
QSPI4_SCLK
QSPI4_MTSRP
MSC1_SOP
—
Master SPI clock output
Master SPI data output (LVDS P line)
Data output - direct part of the differential signal
Reserved
—
Reserved
Data Sheet
169
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-30 Port 23 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
89
P23.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
CAN receive input node 0
General-purpose output
GTM muxed output
Reserved
GTM_TIM1_IN5_4
GTM_TIM0_IN5_4
CAN10_RXDC
P23.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT41
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
90
P23.1
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Upstream assynchronous input signal
Receive input
GTM_TIM1_IN6_4
GTM_TIM0_IN6_4
MSC1_SDI0
ASCLIN6_ARXF
P23.1
O0
O1
O2
O3
O4
O5
O6
O7
I
General-purpose output
GTM muxed output
Ready to send output
Master slave select output
CGM generated clock
CAN transmit output node 0
External Clock 0
GTM_TOUT42
ASCLIN1_ARTS
QSPI4_SLSO6
GTM_CLK0
CAN10_TXD
CCU_EXTCLK0
ASCLIN6_ASCLK
P23.2
Shift clock output
91
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Receive input
GTM_TIM1_IN6_5
GTM_TIM0_IN6_5
ASCLIN7_ARXC
P23.2
O0
O1
O2
O3
O4
O5
O6
O7
General-purpose output
GTM muxed output
Reserved
GTM_TOUT43
—
—
Reserved
—
Reserved
CAN12_TXD
—
CAN transmit output node 2
Reserved
—
Reserved
Data Sheet
170
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-30 Port 23 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
92
P23.3
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
Injection signal from port
Receive input
GTM_TIM1_IN7_4
GTM_TIM0_IN7_4
MSC1_INJ0
ASCLIN6_ARXA
CAN12_RXDC
P23.3
CAN receive input node 2
General-purpose output
GTM muxed output
Transmit output
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT44
ASCLIN7_ATX
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
93
P23.4
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
General-purpose output
GTM muxed output
Slave select signal output
Master slave select output
Reserved
GTM_TIM1_IN7_5
GTM_TIM0_IN7_5
P23.4
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT45
ASCLIN6_ASLSO
QSPI4_SLSO5
—
MSC1_EN0
—
Chip Select
Reserved
—
Reserved
94
P23.5
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN2_7
GTM_TIM0_IN2_7
P23.5
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT46
ASCLIN6_ATX
QSPI4_SLSO4
—
Master slave select output
Reserved
MSC1_EN1
—
Chip Select
Reserved
—
Reserved
Data Sheet
171
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-31 Port 32 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
84
P32.0
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
GTM_TIM3_IN2_5
Mux input channel 2 of TIM module 3
Mux input channel 2 of TIM module 2
General-purpose output
GTM muxed output
Reserved
GTM_TIM2_IN2_5
P32.0
O0
O1
O2
O3
O4
O5
O6
O7
I
GTM_TOUT36
—
—
Reserved
—
Reserved
—
Reserved
—
Reserved
—
Reserved
85
P32.1
SLOW /
PU1 /
VEXT /
ES
General-purpose input
P32.1 / External Pass Device gate control for EVRC
GTM_TIM3_IN3_15
Mux input channel 3 of TIM module 3
General-purpose output
GTM muxed output
Reserved
P32.1
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT37
—
—
—
—
—
—
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
172
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-31 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
86
P32.2
I
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 3
Receive input
GTM_TIM1_IN3_8
GTM_TIM0_IN3_8
CAN03_RXDB
ASCLIN3_ARXD
P32.2
O0
O1
O2
General-purpose output
GTM muxed output
Transmit output
GTM_TOUT38
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
I
Reserved
—
Reserved
—
Reserved
PMS_DCDCSYNCO
—
DC-DC synchronization output
Reserved
87
P32.3
SLOW /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
General-purpose output
GTM muxed output
Transmit output
GTM_TIM1_IN4_5
GTM_TIM0_IN4_5
P32.3
O0
O1
O2
GTM_TOUT39
ASCLIN3_ATX
IOM_MON2_15
IOM_REF2_15
—
Monitor input 2
Reference input 2
O3
O4
O5
Reserved
ASCLIN3_ASCLK
CAN03_TXD
IOM_MON2_8
IOM_REF2_8
—
Shift clock output
CAN transmit output node 3
Monitor input 2
Reference input 2
O6
O7
Reserved
—
Reserved
Data Sheet
173
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-31 Port 32 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
88
P32.4
I
FAST /
PU1 /
VEXT /
ES
General-purpose input
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Clear to send input
GTM_TIM1_IN5_5
GTM_TIM0_IN5_5
ASCLIN1_ACTSB
MSC1_SDI2
P32.4
Upstream assynchronous input signal
General-purpose output
GTM muxed output
O0
O1
O2
O3
O4
O5
O6
O7
GTM_TOUT40
—
Reserved
—
Reserved
GTM_CLK1
MSC1_EN0
CCU_EXTCLK1
CCU60_COUT63
IOM_MON1_6
IOM_REF1_0
PMS_DCDCSYNCO
CGM generated clock
Chip Select
External Clock 1
T13 PWM channel 63
Monitor input 1
Reference input 1
O
DC-DC synchronization output
Data Sheet
174
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions
Pin
Symbol
Ctrl. Buffer
Type
Function
70
P33.0
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 13
GPIO pad input to FPC
CDTM1_DTM0
GTM_TIM3_IN0_13
GTM_TIM1_IN4_6
GTM_TIM0_IN4_6
EDSADC_ITR0E
SENT_SENT13C
IOM_PIN_0
GTM_DTMT1_2
EVADC_G10CH7
P33.0
AI
Analog input channel 7, group 10
General-purpose output
GTM muxed output
O0
O1
GTM_TOUT22
IOM_MON0_0
IOM_GTM_0
ASCLIN5_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Transmit output
O2
O3
O4
O5
O6
O7
Reserved
—
Reserved
—
Reserved
EVADC_FC2BFLOUT
—
Boundary flag output, FC channel 2
Reserved
Data Sheet
175
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
71
P33.1
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN1_15
GTM_TIM1_IN5_6
GTM_TIM0_IN5_6
EDSADC_ITR1E
PSI5_RX0C
Mux input channel 1 of TIM module 3
Mux input channel 5 of TIM module 1
Mux input channel 5 of TIM module 0
Trigger/Gate input, channel 1
RXD inputs (receive data) channel 0
Modulator clock input, channel 2
Receive input channel 9
EDSADC_DSCIN2B
SENT_SENT9C
ASCLIN8_ARXC
IOM_PIN_1
Receive input
GPIO pad input to FPC
EVADC_G10CH6
P33.1
AI
Analog input channel 6, group 10
General-purpose output
O0
O1
GTM_TOUT23
IOM_MON0_1
IOM_GTM_1
ASCLIN3_ASLSO
QSPI2_SCLK
EDSADC_DSCOUT2
EVADC_EMUX02
—
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master SPI clock output
O2
O3
O4
O5
O6
O7
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
176
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
72
P33.2
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN2_14
GTM_TIM1_IN6_6
GTM_TIM0_IN6_6
EDSADC_ITR2E
SENT_SENT8C
EDSADC_DSDIN2B
IOM_PIN_2
Mux input channel 2 of TIM module 3
Mux input channel 6 of TIM module 1
Mux input channel 6 of TIM module 0
Trigger/Gate input, channel 2
Receive input channel 8
Digital datastream input, channel 2
GPIO pad input to FPC
EVADC_G10CH5
P33.2
AI
Analog input channel 5, group 10
General-purpose output
O0
O1
GTM_TOUT24
IOM_MON0_2
IOM_GTM_2
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
ASCLIN3_ASCLK
QSPI2_SLSO10
PSI5_TX0
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_14
IOM_REF1_14
EVADC_EMUX01
EVADC_FC3BFLOUT
—
Monitor input 1
Reference input 1
O5
O6
O7
Control of external analog multiplexer interface 0
Boundary flag output, FC channel 3
Reserved
Data Sheet
177
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
73
P33.3
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM3_IN3_12
GTM_TIM1_IN7_6
GTM_TIM0_IN7_6
PSI5_RX1C
Mux input channel 3 of TIM module 3
Mux input channel 7 of TIM module 1
Mux input channel 7 of TIM module 0
RXD inputs (receive data) channel 1
Receive input channel 7
SENT_SENT7C
EDSADC_DSCIN1B
IOM_PIN_3
Modulator clock input, channel 1
GPIO pad input to FPC
EVADC_G10CH4
P33.3
AI
Analog input channel 4, group 10
General-purpose output
O0
O1
GTM_TOUT25
IOM_MON0_3
IOM_GTM_3
ASCLIN5_ASCLK
QSPI4_SLSO2
EDSADC_DSCOUT1
EVADC_EMUX00
—
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Master slave select output
Modulator clock output
Control of external analog multiplexer interface 0
Reserved
—
Reserved
Data Sheet
178
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
74
P33.4
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN4_10
GTM_TIM1_IN0_10
GTM_TIM0_IN0_10
EDSADC_ITR0F
SENT_SENT6C
EDSADC_DSDIN1B
CCU61_CTRAPC
ASCLIN5_ARXB
IOM_PIN_4
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Trigger/Gate input, channel 0
Receive input channel 6
Digital datastream input, channel 1
Trap input capture
Receive input
GPIO pad input to FPC
GTM_DTMT2_0
EVADC_G10CH3
P33.4
CDTM2_DTM0
AI
Analog input channel 3, group 10
General-purpose output
O0
O1
GTM_TOUT26
IOM_MON0_4
IOM_GTM_4
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Ready to send output
ASCLIN2_ARTS
QSPI2_SLSO12
PSI5_TX1
O2
O3
O4
Master slave select output
TXD outputs (send data)
IOM_MON1_15
EVADC_EMUX12
EVADC_FC0BFLOUT
CAN13_TXD
Monitor input 1
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 0
CAN transmit output node 3
Data Sheet
179
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
75
P33.5
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN5_10
GTM_TIM1_IN1_8
GTM_TIM0_IN1_8
EDSADC_DSCIN0B
EDSADC_ITR1F
GPT120_T4EUDB
PSI5S_RXC
Mux input channel 5 of TIM module 4
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
Modulator clock input, channel 0
Trigger/Gate input, channel 1
Count direction control input of timer T4
RX data input
ASCLIN2_ACTSB
CCU61_CCPOS2C
SENT_SENT5C
CAN13_RXDB
IOM_PIN_5
Clear to send input
Hall capture input 2
Receive input channel 5
CAN receive input node 3
GPIO pad input to FPC
EVADC_G10CH2
P33.5
AI
Analog input channel 2, group 10
General-purpose output
O0
O1
GTM_TOUT27
IOM_MON0_5
GTM muxed output
Monitor input 0
IOM_GTM_5
GTM-provided inputs to EXOR combiner
Master slave select output
Master slave select output
Modulator clock output
QSPI0_SLSO7
QSPI1_SLSO7
EDSADC_DSCOUT0
EVADC_EMUX11
EVADC_FC2BFLOUT
ASCLIN5_ASLSO
O2
O3
O4
O5
O6
O7
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 2
Slave select signal output
Data Sheet
180
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
76
P33.6
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN2_9
GTM_TIM0_IN2_9
EDSADC_ITR2F
GPT120_T2EUDB
SENT_SENT4C
CCU61_CCPOS1C
EDSADC_DSDIN0B
ASCLIN8_ARXD
IOM_PIN_6
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Trigger/Gate input, channel 2
Count direction control input of timer T2
Receive input channel 4
Hall capture input 1
Digital datastream input, channel 0
Receive input
GPIO pad input to FPC
GTM_DTMT2_1
EVADC_G10CH1
P33.6
CDTM2_DTM0
AI
Analog input channel 1, group 10
General-purpose output
O0
O1
GTM_TOUT28
IOM_MON0_6
IOM_GTM_6
GTM muxed output
Monitor input 0
GTM-provided inputs to EXOR combiner
Slave select signal output
Master slave select output
Reserved
ASCLIN2_ASLSO
QSPI2_SLSO11
—
O2
O3
O4
O5
O6
O7
EVADC_EMUX10
EVADC_FC1BFLOUT
PSI5S_TX
Control of external analog multiplexer interface 1
Boundary flag output, FC channel 1
TX data output
Data Sheet
181
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
77
P33.7
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM1_IN3_9
GTM_TIM0_IN3_9
CAN00_RXDE
GPT120_T2INB
CCU61_CCPOS0C
SCU_E_REQ4_0
Mux input channel 3 of TIM module 1
Mux input channel 3 of TIM module 0
CAN receive input node 0
Trigger/gate input of timer T2
Hall capture input 0
ERU Channel 4 inputs 0 to 5 (0 is the LSB and 5 is the
MSB)
SENT_SENT14C
IOM_PIN_7
Receive input channel 14
GPIO pad input to FPC
Analog input channel 0, group 10
General-purpose output
GTM muxed output
EVADC_G10CH0
P33.7
AI
O0
O1
GTM_TOUT29
IOM_MON0_7
IOM_GTM_7
ASCLIN2_ASCLK
QSPI4_SLSO7
ASCLIN8_ATX
—
Monitor input 0
GTM-provided inputs to EXOR combiner
Shift clock output
O2
O3
O4
O5
O6
O7
Master slave select output
Transmit output
Reserved
EVADC_FC3BFLOUT
—
Boundary flag output, FC channel 3
Reserved
Data Sheet
182
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
78
P33.8
I
FAST /
General-purpose input
HighZ /
VEVRSB
GTM_TIM1_IN4_7
GTM_TIM0_IN4_7
ASCLIN2_ARXE
Mux input channel 4 of TIM module 1
Mux input channel 4 of TIM module 0
Receive input
SCU_EMGSTOP_POR
T_A
Emergency stop Port Pin A input request
IOM_PIN_8
P33.8
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
O0
O1
GTM_TOUT30
IOM_MON0_8
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO2
—
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Reserved
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_COUT62
IOM_MON1_13
IOM_REF1_8
SMU_FSP0
T12 PWM channel 62
Monitor input 1
Reference input 1
O
FSP[1..0] Output Signals - Generated by SMU_core
Data Sheet
183
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
79
P33.9
I
SLOW /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 1
Mux input channel 1 of TIM module 0
GPIO pad input to FPC
General-purpose output
GTM muxed output
Monitor input 0
GTM_TIM1_IN1_9
GTM_TIM0_IN1_9
IOM_PIN_9
P33.9
O0
O1
GTM_TOUT31
IOM_MON0_9
ASCLIN2_ATX
IOM_MON2_14
IOM_REF2_14
QSPI4_SLSO1
ASCLIN2_ASCLK
CAN01_TXD
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
Master slave select output
Shift clock output
CAN transmit output node 1
Monitor input 2
IOM_MON2_6
IOM_REF2_6
ASCLIN0_ATX
IOM_MON2_12
IOM_REF2_12
CCU61_CC62
IOM_MON1_10
IOM_REF1_11
Reference input 2
O6
O7
Transmit output
Monitor input 2
Reference input 2
T12 PWM channel 62
Monitor input 1
Reference input 1
Data Sheet
184
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
80
P33.10
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
GTM_TIM4_IN4_14
GTM_TIM1_IN0_9
GTM_TIM0_IN0_9
QSPI4_SLSIA
CAN01_RXDD
ASCLIN0_ARXD
IOM_PIN_10
Mux input channel 4 of TIM module 4
Mux input channel 0 of TIM module 1
Mux input channel 0 of TIM module 0
Slave select input
CAN receive input node 1
Receive input
GPIO pad input to FPC
P33.10
O0
O1
General-purpose output
GTM muxed output
GTM_TOUT32
IOM_MON0_10
QSPI1_SLSO6
QSPI4_SLSO0
ASCLIN1_ASLSO
PSI5S_CLK
Monitor input 0
O2
O3
O4
O5
Master slave select output
Master slave select output
Slave select signal output
PSI5S CLK is a clock that can be used on a pin to drive
the external PHY.
—
O6
O7
Reserved
CCU61_COUT61
IOM_MON1_12
IOM_REF1_9
SMU_FSP1
P33.11
T12 PWM channel 61
Monitor input 1
Reference input 1
O
I
FSP[1..0] Output Signals - Generated by SMU_core
General-purpose input
Mux input channel 2 of TIM module 1
Mux input channel 2 of TIM module 0
Slave SPI clock inputs
GPIO pad input to FPC
General-purpose output
GTM muxed output
81
FAST /
PU1 /
VEVRSB
/ ES5
GTM_TIM1_IN2_8
GTM_TIM0_IN2_8
QSPI4_SCLKA
IOM_PIN_11
P33.11
O0
O1
GTM_TOUT33
IOM_MON0_11
ASCLIN1_ASCLK
QSPI4_SCLK
—
Monitor input 0
O2
O3
O4
O5
O6
O7
Shift clock output
Master SPI clock output
Reserved
—
Reserved
EDSADC_CGPWMN
CCU61_CC61
IOM_MON1_9
IOM_REF1_12
Negative carrier generator output
T12 PWM channel 61
Monitor input 1
Reference input 1
Data Sheet
185
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
82
P33.12
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 0 of TIM module 3
Mux input channel 0 of TIM module 2
Slave SPI data input
CAN receive input node 0
PINB (P33.12) pin input
GPIO pad input to FPC
General-purpose output
GTM muxed output
GTM_TIM3_IN0_6
GTM_TIM2_IN0_6
QSPI4_MTSRA
CAN00_RXDD
PMS_PINBWKP
IOM_PIN_12
P33.12
O0
O1
GTM_TOUT34
IOM_MON0_12
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MTSR
ASCLIN1_ASCLK
—
Monitor input 0
O2
Transmit output
Monitor input 2
Reference input 2
O3
O4
O5
O6
O7
Master SPI data output
Shift clock output
Reserved
EDSADC_CGPWMP
CCU61_COUT60
IOM_MON1_11
IOM_REF1_10
Positive carrier generator output
T12 PWM channel 60
Monitor input 1
Reference input 1
Data Sheet
186
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-32 Port 33 Functions (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
83
P33.13
I
FAST /
PU1 /
VEVRSB
/ ES5
General-purpose input
Mux input channel 1 of TIM module 3
Mux input channel 1 of TIM module 2
Receive input
GTM_TIM3_IN1_5
GTM_TIM2_IN1_5
ASCLIN1_ARXF
EDSADC_SGNB
QSPI4_MRSTA
MSC1_INJ1
Carrier sign signal input
Master SPI data input
Injection signal from port
General-purpose output
GTM muxed output
Transmit output
P33.13
O0
O1
O2
GTM_TOUT35
ASCLIN1_ATX
IOM_MON2_13
IOM_REF2_13
QSPI4_MRST
IOM_MON2_4
IOM_REF2_4
QSPI2_SLSO6
CAN00_TXD
IOM_MON2_5
IOM_REF2_5
—
Monitor input 2
Reference input 2
O3
Slave SPI data output
Monitor input 2
Reference input 2
O4
O5
Master slave select output
CAN transmit output node 0
Monitor input 2
Reference input 2
O6
O7
Reserved
CCU61_CC60
IOM_MON1_8
IOM_REF1_13
T12 PWM channel 60
Monitor input 1
Reference input 1
Table 2-33 Analog Inputs
Pin
Symbol
Ctrl. Buffer
Type
Function
67
AN0
I
I
I
D / HighZ Analog Input 0
/ VDDM
EVADC_G0CH0
EDSADC_EDS3PA
AN1
Analog input channel 0, group 0
Positive analog input channel 3, pin A
66
65
D / HighZ Analog Input 1
/ VDDM
EVADC_G0CH1
EDSADC_EDS3NA
AN2
Analog input channel 1, group 0
Negative analog input channel 3, pin A
D / HighZ Analog Input 2
/ VDDM
EVADC_G0CH2
EDSADC_EDS0PA
Analog input channel 2, group 0
Positive analog input channel 0, pin A
Data Sheet
187
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-33 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
64
AN3
I
I
I
I
I
I
I
I
I
I
I
I
D / HighZ Analog Input 3
/ VDDM
EVADC_G0CH3
EDSADC_EDS0NA
AN4
Analog input channel 3, group 0
Negative analog input channel 0, pin A
D / HighZ Analog Input 4
63
62
61
60
59
58
57
56
55
50
49
/ VDDM
EVADC_G11CH0
EVADC_G0CH4
AN5
Analog input channel 0, group 11
Analog input channel 4, group 0
D / HighZ Analog Input 5
/ VDDM
EVADC_G11CH1
EVADC_G0CH5
AN6
Analog input channel 1, group 11
Analog input channel 5, group 0
D / HighZ Analog Input 6
/ VDDM
EVADC_G11CH2
EVADC_G0CH6
AN7
Analog input channel 2, group 11
Analog input channel 6, group 0
D / HighZ Analog Input 7
/ VDDM
EVADC_G11CH3
EVADC_G0CH7
AN8
Analog input channel 3, group 11
Analog input channel 7, group 0
D / HighZ Analog Input 8
/ VDDM
EVADC_G11CH4
EVADC_G1CH0
AN10
Analog input channel 4, group 11
Analog input channel 0, group 1
D / HighZ Analog Input 10
/ VDDM
EVADC_G11CH6
EVADC_G1CH2
AN11
Analog input channel 6, group 11
Analog input channel 2, group 1
D / HighZ Analog Input 11
/ VDDM
EVADC_G11CH7
EVADC_G1CH3
AN12
Analog input channel 7, group 11
Analog input channel 3, group 1
D / HighZ Analog Input 12
/ VDDM
EVADC_G1CH4
EDSADC_EDS0PB
AN13
Analog input channel 4, group 1
Positive analog input channel 0, pin B
D / HighZ Analog Input 13
/ VDDM
EVADC_G1CH5
EDSADC_EDS0NB
AN16
Analog input channel 5, group 1
Negative analog input channel 0, pin B
D / HighZ Analog Input 16
/ VDDM
EVADC_G2CH0
EVADC_FC0CH0
AN17/P40.10
SENT_SENT10A
EVADC_G2CH1
EVADC_FC1CH0
Analog input channel 0, group 2
Analog input FC channel 0
S / HighZ Analog Input 17
/ VDDM
Receive input channel 10
Analog input channel 1, group 2
Analog input FC channel 1
Data Sheet
188
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-33 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
48
AN18/P40.11
I
S / HighZ Analog Input 18
/ VDDM
SENT_SENT11A
EVADC_G11CH8
EVADC_G2CH2
AN19/P40.12
Receive input channel 11
Analog input channel 8, group 11
Analog input channel 2, group 2
47
I
S / HighZ Analog Input 19
/ VDDM
SENT_SENT12A
EVADC_G11CH9
EVADC_G2CH3
AN20
Receive input channel 12
Analog input channel 9, group 11
Analog input channel 3, group 2
46
45
44
I
I
I
D / HighZ Analog Input 20
/ VDDM
EVADC_G2CH4
EDSADC_EDS2PA
AN21
Analog input channel 4, group 2
Positive analog input channel 2, pin A
D / HighZ Analog Input 21
/ VDDM
EVADC_G2CH5
EDSADC_EDS2NA
AN24/P40.0
Analog input channel 5, group 2
Negative analog input channel 2, pin A
S / HighZ Analog Input 24
/ VDDM
SENT_SENT0A
EVADC_G3CH0
CCU60_CCPOS0D
EDSADC_EDS2PB
AN25/P40.1
Receive input channel 0
Analog input channel 0, group 3
Hall capture input 0
Positive analog input channel 2, pin B
43
42
41
40
I
I
I
I
S / HighZ Analog Input 25
/ VDDM
SENT_SENT1A
EVADC_G3CH1
CCU60_CCPOS1B
EDSADC_EDS2NB
AN26/P40.2
Receive input channel 1
Analog input channel 1, group 3
Hall capture input 1
Negative analog input channel 2, pin B
S / HighZ Analog Input 26
/ VDDM
SENT_SENT2A
EVADC_G3CH2
CCU60_CCPOS1D
EVADC_G11CH10
AN27/P40.3
Receive input channel 2
Analog input channel 2, group 3
Hall capture input 1
Analog input channel 10, group 11
S / HighZ Analog Input 27
/ VDDM
SENT_SENT3A
EVADC_G3CH3
CCU60_CCPOS2B
EVADC_G11CH11
AN28/P40.13
Receive input channel 3
Analog input channel 3, group 3
Hall capture input 2
Analog input channel 11, group 11
S / HighZ Analog Input 28
/ VDDM
SENT_SENT13A
EVADC_G3CH4
Receive input channel 13
Analog input channel 4, group 3
Data Sheet
189
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-33 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
39
AN29/P40.14
I
I
S / HighZ Analog Input 29
/ VDDM
SENT_SENT14A
EVADC_G3CH5
AN32/P40.4
Receive input channel 14
Analog input channel 5, group 3
S / HighZ Analog Input 32
38
37
/ VDDM
SENT_SENT4A
EVADC_G8CH0
CCU60_CCPOS2D
EVADC_G11CH12
AN33/P40.5
Receive input channel 4
Analog input channel 0, group 8
Hall capture input 2
Analog input channel 12, group 11
I
S / HighZ Analog Input 33
/ VDDM
SENT_SENT5A
EVADC_G8CH1
CCU61_CCPOS0D
EVADC_G11CH13
AN35
Receive input channel 5
Analog input channel 1, group 8
Hall capture input 0
Analog input channel 13, group 11
36
35
I
I
D / HighZ Analog Input 35
/ VDDM
EVADC_G8CH3
EVADC_G11CH15
AN36/P40.6
Analog input channel 3, group 8
Analog input channel 15, group 11
S / HighZ Analog Input 36
/ VDDM
SENT_SENT6A
EVADC_G8CH4
CCU61_CCPOS1B
EDSADC_EDS1PA
AN37/P40.7
Receive input channel 6
Analog input channel 4, group 8
Hall capture input 1
Positive analog input channel 1, pin A
34
33
32
I
I
I
S / HighZ Analog Input 37
/ VDDM
SENT_SENT7A
EVADC_G8CH5
CCU61_CCPOS1D
EDSADC_EDS1NA
AN38/P40.8
Receive input channel 7
Analog input channel 5, group 8
Hall capture input 1
Negative analog input channel 1, pin A
S / HighZ Analog Input 38
/ VDDM
SENT_SENT8A
EVADC_G8CH6
CCU61_CCPOS2B
EDSADC_EDS1PB
AN39/P40.9
Receive input channel 8
Analog input channel 6, group 8
Hall capture input 2
Positive analog input channel 1, pin B
S / HighZ Analog Input 39
/ VDDM
SENT_SENT9A
EVADC_G8CH7
CCU61_CCPOS2D
EDSADC_EDS1NB
Receive input channel 9
Analog input channel 7, group 8
Hall capture input 2
Negative analog input channel 1, pin B
Data Sheet
190
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-33 Analog Inputs (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
31
AN44
I
I
I
I
D / HighZ Analog Input 44
/ VDDM
EVADC_G8CH12
EDSADC_EDS1PC
AN45
Analog input channel 12, group 8
Positive analog input channel 1, pin C
D / HighZ Analog Input 45
30
29
28
/ VDDM
EVADC_G8CH13
EDSADC_EDS1NC
AN46
Analog input channel 13, group 8
Negative analog input channel 1, pin C
D / HighZ Analog Input 46
/ VDDM
EVADC_G8CH14
EDSADC_EDS1PD
AN47
Analog input channel 14, group 8
Positive analog input channel 1, pin D
D / HighZ Analog Input 47
/ VDDM
EVADC_G8CH15
EDSADC_EDS1ND
Analog input channel 15, group 8
Negative analog input channel 1, pin D
Note: Port Pins P32.0 and P32.1 are bidirectional pads and are having the following two functionalities
implemented:
3. In case the pins are used as standard GPIOs the functions defined in the pin configuration tables of P32.0 and
P32.1 are available.
4. In case the pins are used as pre-drivers for external MOSFETs (internal DCDC usecase) P32.0 and P32.1 act
as analog IOs named VGATE1N and VGATE1P.
Table 2-34 System I/O
Pin
Symbol
Ctrl. Buffer
Type
Function
84
VGATE1N
O
—
DCDC N ch. MOSFET gate driver output
P32.0 / SMPS mode: analog output. External Pass Device
gate control for EVRC
85
VGATE1P
XTAL1
XTAL2
TMS
O
I
—
DCDC P ch. MOSFET gate driver output
P32.1 / External Pass Device gate control for EVRC
102
103
112
XTAL /
VEXT
XTAL pad1
XTAL1. Main Oscillator/PLL/Clock Generator Input.
O
I
XTAL /
VEXT
XTAL pad2
XTAL2. Main Oscillator/PLL/Clock Generator OUTPUT
FAST /
PD2 /
VEXT
JTAG Module State Machine Control Input
TMS: JTAG Module State Machine Control Input. DAP:
DAP1 Data I/O.
DAP1
TRST
I/O
I
DAP: DAP1 Data I/O
114
FAST /
PU2 /
VEXT
JTAG Module Reset/Enable Input
TRST_N: JTAG Module Reset/Enable Input. DAPE:
DAPE0 Clock Input
Data Sheet
191
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-34 System I/O (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
115
TCK
I
FAST /
PD2 /
VEXT
JTAG Module Clock Input
TCK: JTAG Module Clock Input. DAP: DAP0 Clock Input.
DAP0
ESR1
I
I
DAP: DAP0 Clock Input
120
FAST /
PU1 /
VEXT
ESR1 Port Pin input - can be used to trigger a reset or
an NMI
ESR1: External System Request Reset 1. Default NMI
function. See also SCU chapter for details. Default after
power-on can be different. See also SCU chapter ´Reset
Control Unit´ and SCU_IOCR register description.
PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR1WKP
PORST
I
ESR1 pin input
121
122
I/O
PORST / PORST pin
PD /
VEXT
Power On Reset Input. Additional strong PD in case of
power fail.
ESR0
I
FAST /
OD /
ESR0 Port Pin input - can be used to trigger a reset or
an NMI
VEXT
ESR0: External System Request Reset 0. Default
configuration during and after reset is open-drain driver.
The driver drives low during power-on reset. This is valid
additionally after deactivation of PORST_N until the
internal reset phase has finished. See also SCU chapter for
details. Default after power-on can be different. See also
SCU chapter ´Reset Control Unit´ and SCU_IOCR register
description. PMS_EVRWUP: EVR Wakepup Pin
PMS_ESR0WKP
I
ESR0 pin input
Table 2-35 Supply
Pin
Symbol
Ctrl. Buffer
Type
Function
164
54
VFLEX
I
I
I
I
I
I
—
—
—
—
—
—
Digital Power Supply for Flex Port Pads (5V / 3.3V)
ADC Analog Power Supply (5V / 3.3V)
Flash Power Supply (3.3V)
VDDM
154
52
VDDP3
VAREF1
VAREF2
VEVRSB
Positive Analog Reference Voltage 1
Positive Analog Reference Voltage 2
26
69
Standby Power Supply (5V / 3.3V) for the Standby
SRAM
155
10
VDD
VDD
VDD
VDD
VDD
VDD
I
I
I
I
I
I
—
—
—
—
—
—
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
Digital Core Power Supply (1.25V)
24
68
100
123
Data Sheet
192
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TC37x AA-Step
TC37x Pin Definition and Functions LQFP-176 Package Pinning of TC37x T
Table 2-35 Supply (cont’d)
Pin
Symbol
Ctrl. Buffer
Type
Function
153
25
VEXT
I
I
I
I
I
I
I
I
—
—
—
—
—
—
—
—
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
External Power Supply (5V / 3.3V)
Digital Ground (Exposed PAD), VSS
Analog Ground for VDDM
VEXT
99
VEXT
E-PAD
53
VSS
VSSM
VAGND1
VAGND2
VEXT
51
Negative Analog Reference Voltage 1
Negative Analog Reference Voltage 2
27
104
Digital Power Supply for Oscillator (shall be supplied
with same level as used for VEXT), VEXT(OSC)
101
VSS
I
—
Oscillator Ground, VSS(OSC)
Data Sheet
193
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TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
2.3
Sequence of Pads in Pad Frame
Table 2-36 Pad List
Number
Pad Name
Pad Type
X
Y
Comment
1
P15.0
P15.1
P15.2
P15.3
P15.4
P15.5
P15.6
P15.7
P15.8
P14.0
FAST / PU1 / 277299
VEXT / ES
185148
General-purpose I/O
2
FAST / PU1 / 378099
VEXT / ES
185148
185148
362646
185148
362646
185148
362646
185148
362646
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
3
FAST / PU1 / 478899
VEXT / ES
4
FAST / PU1 / 529299
VEXT / ES
5
FAST / PU1 / 579699
VEXT / ES
6
FAST / PU1 / 630099
VEXT / ES
7
FAST / PU1 / 680499
VEXT / ES
8
FAST / PU1 / 729999
VEXT / ES
9
FAST / PU1 / 779499
VEXT / ES
10
FAST / PU1 / 828999
VEXT / ES2
11
12
VDD
Vx
899199
185148
362646
Supply Voltage
P14.1
FAST / PU1 / 961497
VEXT / ES2
General-purpose I/O
13
14
VSS
Vx
1027197
185148
362646
Supply Voltage
P14.2
SLOW / PU2 / 1096695
VEXT / ES
General-purpose I/O
15
16
VSS
Vx
1150893
185148
362646
Supply Voltage
P14.3
SLOW / PU2 / 1199691
VEXT / ES
General-purpose I/O
17
18
VEXT
P14.4
Vx
1254069
179145
362646
Supply Voltage
SLOW / PU2 / 1306467
VEXT / ES
General-purpose I/O
19
20
21
22
P14.5
P14.6
P14.7
P14.8
FAST / PU2 / 1355967
VEXT / ES
185148
362646
185148
362646
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 1405467
VEXT / ES
SLOW / PU1 / 1454967
VEXT / ES
SLOW / PU1 / 1504467
VEXT / ES
Data Sheet
194
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TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
23
Pad Name
VSS
Pad Type
X
Y
Comment
—
1558467
1633518
185148
362646
Supply Voltage
General-purpose I/O
24
P14.9
LVDS_RX /
FAST / PU1 /
VEXT / ES
25
P14.10
LVDS_RX /
FAST / PU1 /
VEXT / ES
1736514
362646
General-purpose I/O
26
27
28
29
30
31
32
33
34
35
36
37
38
39
VSS
Vx
Vx
Vx
Vx
Vx
1807065
1861065
1918863
1968363
2017863
2067363
2251863
2331063
2409561
2472561
2535867
2599065
2662263
2769066
185148
362646
185148
362646
185148
362646
362646
185148
362646
185148
362646
185148
362646
185148
Supply Voltage
Supply Voltage
OTPMust be bonded to VSS
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
RESERVED
VEXT
VEXT
VDD_EXT_IO Vx
VDDP3
VDDP3
VDDP3
VSS
Vx
Vx
Vx
—
VDD
Vx
Vx
Vx
VDD
VDD
P13.0
LVDS_TX /
FAST / PU1 /
VEXT / ES6
40
P13.1
LVDS_TX /
FAST / PU1 /
VEXT / ES6
2872062
185148
General-purpose I/O
41
42
VSS
Vx
2979063
3086964
185148
185148
Supply Voltage
P13.2
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
43
P13.3
LVDS_TX /
FAST / PU1 /
VEXT / ES6
3189960
185148
General-purpose I/O
44
45
46
47
48
VDDP3
VEXT
VDD
Vx
Vx
Vx
Vx
3296961
3346461
3401559
3451059
362646
179145
362646
185148
356643
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VSS
P12.0
SLOW / PU1 / 3525975
VFLEX / ES
49
P12.1
SLOW / PU1 / 3575475
VFLEX / ES
179145
General-purpose I/O
Data Sheet
195
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TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
50
P11.0
RFAST / PU1 / 3681981
VFLEX / ES
356643
General-purpose I/O
51
52
VFLEX
P11.1
Vx
3728979
179145
356643
Supply Voltage
RFAST / PU1 / 3802491
VFLEX / ES
General-purpose I/O
53
54
VSS
Vx
3851181
185148
362646
Supply Voltage
P11.2
RFAST / PU1 / 3926385
VFLEX / ES
General-purpose I/O
55
56
VDD
Vx
3973383
179145
362646
Supply Voltage
P11.4
RFAST / PU1 / 4089087
VFLEX / ES
General-purpose I/O
57
58
VSS
Vx
4176585
185148
362646
Supply Voltage
P11.3
RFAST / PU1 / 4251789
VFLEX / ES
General-purpose I/O
59
60
VFLEX
P11.6
Vx
4298787
179145
362646
Supply Voltage
RFAST / PU1 / 4372299
VFLEX / ES
General-purpose I/O
61
62
VSS
Vx
4420989
4469679
185148
356643
Supply Voltage
P11.5
SLOW /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
63
64
P11.7
P11.9
SLOW /
4520475
4571271
179145
362646
General-purpose I/O
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
FAST /
RGMII_Input /
PU1 / VFLEX /
ES
65
66
VFLEX
P11.8
Vx
4621671
4670541
185148
356643
Supply Voltage
SLOW /
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
67
68
P11.10
P11.11
FAST /
4720959
4771557
185148
362646
General-purpose I/O
General-purpose I/O
RGMII_Input /
PU1 / VFLEX /
ES
FAST /
RGMII_Input /
PU1 / VFLEX /
ES
Data Sheet
196
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TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
69
Pad Name
VSS
Pad Type
X
Y
Comment
Vx
4822155
4870845
185148
362646
Supply Voltage
General-purpose I/O
70
P11.12
FAST /
RGMII_Input /
PU1 / VFLEX /
ES
71
72
73
VSS
Vx
Vx
4944051
5028849
185148
356643
179145
Supply Voltage
VDD
Supply Voltage
P11.14
SLOW / PU1 / 5098347
VFLEX / ES
General-purpose I/O
74
75
76
77
78
79
80
81
82
83
84
P11.13
P11.15
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P10.8
SLOW / PU1 / 5149827
VFLEX / ES
356643
179145
362646
185148
362646
185148
362646
185148
362646
185148
185148
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 5196825
VFLEX / ES
SLOW / PU1 / 5271723
VEXT / ES
FAST / PU1 / 5321223
VEXT / ES
FAST / PU1 / 5370723
VEXT / ES
FAST / PU1 / 5420223
VEXT / ES
FAST / PU1 / 5470218
VEXT / ES
SLOW / PU2 / 5521588
VEXT / ES
SLOW / PU2 / 5571583
VEXT / ES
SLOW / PU1 / 5658813
VEXT / ES
SLOW / PU1 / 5763663
VEXT / ES
85
86
87
88
VSS
Vx
Vx
Vx
5837292
5837292
5659794
286299
387099
487899
540999
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VEXT
VDD
P02.0
FAST / PU1 / 5837292
VEXT / ES
89
90
91
P02.1
P02.2
P02.3
SLOW / PU1 / 5659794
VEXT / ES
591399
641799
696699
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 5837292
VEXT / ES
SLOW / PU1 / 5659794
VEXT / ES
Data Sheet
197
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
92
P02.4
FAST / PU1 / 5837292
VEXT / ES
746199
General-purpose I/O
93
94
95
96
P02.5
P02.6
P02.7
P02.8
FAST / PU1 / 5659794
VEXT / ES
805599
855999
906399
956799
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 5837292
VEXT / ES
FAST / PU1 / 5659794
VEXT / ES
SLOW / PU1 / 5837292
VEXT / ES
97
VDD
VDD
VDD
VSS
VSS
P02.9
Vx
Vx
Vx
—
5659794
5837292
5659794
5837292
5837292
1025199
1116999
1206999
1296999
1404999
1481499
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
98
99
100
101
102
Vx
SLOW / PU1 / 5665797
VEXT / ES
103
104
P02.10
P02.11
SLOW / PU1 / 5843295
VEXT / ES
1529199
1576197
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 5665797
VEXT / ES
105
106
VSS
—
5837292
1650195
1717695
Supply Voltage
P01.3
SLOW / PU1 / 5665797
VEXT / ES
General-purpose I/O
107
108
109
110
VEXT
VDD
Vx
Vx
Vx
5837292
5659794
5837292
1776195
1849095
1912095
1961595
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VSS
P01.4
SLOW / PU1 / 5665797
VEXT / ES
111
112
VSS
Vx
5837292
2038095
2137095
Supply Voltage
P01.5
SLOW / PU1 / 5837292
VEXT / ES
General-purpose I/O
113
114
115
P01.6
P01.7
P00.0
FAST / PU1 / 5665797
VEXT / ES
2185893
2238291
2285289
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 5843295
VEXT / ES
FAST / PU1 / 5659794
VEXT / ES
116
117
118
VSS_EXT_IO
VDD_EXT_IO
VSS
—
—
Vx
5837292
5659794
5837292
2335095
2425095
2520495
Supply Voltage
Supply Voltage
Supply Voltage
Data Sheet
198
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
119
Pad Name
VSS
Pad Type
X
Y
Comment
Vx
Vx
Vx
Vx
5837292
5659794
5837292
5659794
2619495
2718495
2814093
2911491
3030430
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
120
VDD
121
VDD
122
VDD
123
P00.1
SLOW / PU1 / 5837292
VEXT / ES
124
125
126
127
128
129
130
131
132
133
134
P00.2
P00.3
P00.4
P00.5
P00.6
P00.7
P00.8
P00.9
P00.10
P00.11
P00.12
SLOW / PU1 / 5659794
VEXT / ES1
3085430
3140428
3195428
3250426
3305426
3360424
3415424
3470422
3525422
3580420
3635420
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 5837292
VEXT / ES1
SLOW / PU1 / 5659794
VEXT / ES1
SLOW / PU1 / 5837292
VEXT / ES1
SLOW / PU1 / 5659794
VEXT / ES1
SLOW / PU1 / 5837292
VEXT / ES1
SLOW / PU1 / 5659794
VEXT / ES1
SLOW / PU1 / 5837292
VEXT / ES1
SLOW / PU1 / 5659794
VEXT / ES1
SLOW / PU1 / 5837292
VEXT / ES1
SLOW / PU1 / 5659794
VEXT / ES1
135
136
137
138
139
140
141
142
143
144
VSS
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
5837292
5837292
5837292
5837292
5837292
5837292
5837292
5659794
5837292
5837292
3690418
3789518
3888616
3987716
4086814
4225730
4324828
4379828
4434826
4533926
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Analog Input 47
VSS
VDD
VDD
VEXT
VAREF3
VAGND3
VAREF2
VAGND2
AN47
D / HighZ /
VDDM
145
AN46
D / HighZ /
VDDM
5659794
4588924
Analog Input 46
Data Sheet
199
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
146
AN45
D / HighZ /
VDDM
5837292
4643924
Analog Input 45
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
AN44
D / HighZ /
VDDM
5659794
5837292
5659794
5837292
5659794
5837292
5659794
5837292
5659794
5837292
5659794
5837292
5659794
5837292
5659794
5837292
5659794
5837292
5659794
5837292
4698922
4753922
4808920
4863920
4918918
5083916
5138914
5193914
5248912
5303912
5358910
5413910
5468908
5523908
5578906
5633906
5688904
5743904
5798902
5853902
Analog Input 44
Analog Input 43
Analog Input 42
Analog Input 41
Analog Input 40
Analog Input 39
Analog Input 38
Analog Input 37
Analog Input 36
Analog Input 35
Analog Input 34
Analog Input 33
Analog Input 32
Analog Input 31
Analog Input 30
Analog Input 29
Analog Input 28
Analog Input 27
Analog Input 26
Analog Input 25
AN43
D / HighZ /
VDDM
AN42
D / HighZ /
VDDM
AN41
D / HighZ /
VDDM
AN40
D / HighZ /
VDDM
AN39/P40.9
AN38/P40.8
AN37/P40.7
AN36/P40.6
AN35
S / HighZ /
VDDM
S / HighZ /
VDDM
S / HighZ /
VDDM
S / HighZ /
VDDM
D / HighZ /
VDDM
AN34
D / HighZ /
VDDM
AN33/P40.5
AN32/P40.4
AN31
S / HighZ /
VDDM
S / HighZ /
VDDM
D / HighZ /
VDDM
AN30
D / HighZ /
VDDM
AN29/P40.14 S / HighZ /
VDDM
AN28/P40.13 S / HighZ /
VDDM
AN27/P40.3
AN26/P40.2
AN25/P40.1
S / HighZ /
VDDM
S / HighZ /
VDDM
S / HighZ /
VDDM
Data Sheet
200
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
167
AN24/P40.0
S / HighZ /
VDDM
5837292
5977300
Analog Input 24
168
169
170
171
172
173
174
175
176
AN23
AN22
AN21
AN20
D / HighZ /
VDDM
5752440
5629140
5574141
5519142
5464143
5409144
5354145
5299146
5244147
6062292
6062292
5884794
6062292
5884794
6062292
5884794
6062292
5884794
Analog Input 23
Analog Input 22
Analog Input 21
Analog Input 20
Analog Input 19
Analog Input 18
Analog Input 17
Analog Input 16
Analog Input 15
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
AN19/P40.12 S / HighZ /
VDDM
AN18/P40.11 S / HighZ /
VDDM
AN17/P40.10 S / HighZ /
VDDM
AN16
D / HighZ /
VDDM
AN15
D / HighZ /
VDDM
177
178
179
180
181
182
183
184
185
186
187
VAGND1
VAREF1
VAGND0
VAREF0
VSSM
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
Vx
5189148
5134149
5079150
5024151
4969152
4914153
4859154
4804155
4749156
4694157
4639158
6062292
5884794
6062292
5884794
6062292
5884794
6062292
5884794
6062292
5884794
6062292
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Analog Input 14
VDDM
VSSM
VDDM
VSSM
VDDM
AN14
D / HighZ /
VDDM
188
189
190
191
192
AN13
AN12
AN11
AN10
AN9
D / HighZ /
VDDM
4584159
4529160
4474161
4419162
4364163
5884794
6062292
5884794
6062292
5884794
Analog Input 13
Analog Input 12
Analog Input 11
Analog Input 10
Analog Input 9
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
Data Sheet
201
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
193
AN8
D / HighZ /
VDDM
4309164
6062292
Analog Input 8
194
195
196
197
198
199
200
201
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
D / HighZ /
VDDM
4254165
4199166
4144167
4089168
4034169
3979170
3924171
3869172
5884794
6062292
5884794
6062292
5884794
6062292
5884794
6062292
Analog Input 7
Analog Input 6
Analog Input 5
Analog Input 4
Analog Input 3
Analog Input 2
Analog Input 1
Analog Input 0
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
D / HighZ /
VDDM
202
203
204
205
206
207
208
209
VSS
Vx
Vx
Vx
Vx
Vx
Vx
Vx
3617253
3509055
3429657
3339459
3289860
3206574
3157074
6062292
5884794
6062292
5884794
6062292
5884794
6062292
5884794
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
VDD
VDD
VSS
VEVRSB
VEVRSB
P33.0
SLOW / PU1 / 3098574
VEVRSB /
ES5
210
211
212
213
VSS
VDD
VSS
P33.1
Vx
Vx
Vx
3049074
2986974
2937375
6062292
5884794
6062292
5884794
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
SLOW / PU1 / 2852874
VEVRSB /
ES5
214
215
P33.2
P33.3
SLOW / PU1 / 2803374
VEVRSB /
ES5
6062292
5884794
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 2753874
VEVRSB /
ES5
Data Sheet
202
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
216
P34.1
SLOW / PU1 / 2704176
6068295
General-purpose I/O
VEVRSB /
ES5
217
P33.4
SLOW / PU1 / 2654478
5884794
General-purpose I/O
VEVRSB /
ES5
218
219
P34.2
P33.5
SLOW / PU1 / 2604978
VEVRSB / ES
6068295
5884794
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 2552976
VEVRSB /
ES5
220
221
P34.3
P33.6
SLOW / PU1 / 2503476
VEVRSB / ES
6068295
5884794
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 2451474
VEVRSB /
ES5
222
P34.4
SLOW / PU1 / 2399076
VEVRSB / ES
6068295
General-purpose I/O
223
224
225
VDD
VSS
Vx
Vx
2352078
2302479
5884794
6062292
5890797
Supply Voltage
Supply Voltage
P34.5
FAST / PU1 / 2178378
VEVRSB / ES
General-purpose I/O
226
P33.7
SLOW / PU1 / 2129580
6062292
General-purpose I/O
VEVRSB /
ES5
227
228
P33.8
P33.9
FAST / HighZ / 2080080
VEVRSB
5884794
6062292
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 2030580
VEVRSB /
ES5
229
230
231
VDD
Vx
Vx
1981080
1931481
5884794
6062292
6062292
Supply Voltage
VSS
Supply Voltage
P33.10
FAST / PU1 / 1796184
General-purpose I/O
VEVRSB /
ES5
232
233
234
P33.14
P33.11
P33.15
FAST / PU1 / 1692684
VEVRSB /
ES5
6068295
6062292
6068295
General-purpose I/O
General-purpose I/O
General-purpose I/O
FAST / PU1 / 1593684
VEVRSB /
ES5
SLOW / PU1 / 1494684
VEVRSB /
ES5
Data Sheet
203
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
235
P33.12
FAST / PU1 / 1445184
5884794
General-purpose I/O
VEVRSB /
ES5
236
237
238
VSS
Vx
Vx
1395684
1346184
6062292
5890797
6062292
Supply Voltage
VEVRSB
P33.13
Supply Voltage
FAST / PU1 / 1296684
General-purpose I/O
VEVRSB /
ES5
239
240
241
242
243
VSS
Vx
Vx
Vx
Vx
1193670
1137672
1085472
1025172
6062292
5884794
6062292
5890797
6062292
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
VSS
VEXT
P32.0
SLOW / PU1 / 964872
VEXT / ES
244
245
246
247
248
249
250
251
252
VGATE1N
P32.1
Vx
915372
5884794
6062292
5884794
6062292
5884794
6062292
5890797
6068295
6068295
DCDC N ch. MOSFET gate
driver output
SLOW / PU1 / 861174
VEXT / ES
General-purpose I/O
VGATE1P
P32.2
Vx
811674
DCDC P ch. MOSFET gate
driver output
SLOW / PU1 / 762174
VEXT / ES
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
P32.3
SLOW / PU1 / 712674
VEXT / ES
P32.4
FAST / PU1 / 663174
VEXT / ES
P32.5
SLOW / PU1 / 613674
VEXT / ES
P32.6
SLOW / PU1 / 562374
VEXT / ES
P32.7
SLOW / PU1 / 462375
VEXT / ES
253
254
255
256
257
VSS
Vx
Vx
Vx
Vx
362376
261576
185148
185148
6062292
6062292
5961141
5854743
5744943
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VDD
VEXT
VSS
P23.0
SLOW / PU1 / 185148
VEXT / ES
258
259
P23.1
P23.2
FAST / PU1 / 362646
VEXT / ES
5653143
5603643
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 185148
VEXT / ES
Data Sheet
204
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
260
P23.3
SLOW / PU1 / 362646
VEXT / ES
5554143
General-purpose I/O
261
P23.4
FAST / PU1 / 185148
VEXT / ES
5504643
General-purpose I/O
262
263
264
VDD
VSS
Vx
Vx
356643
185148
5455143
5386743
5303043
Supply Voltage
Supply Voltage
P23.5
FAST / PU1 / 362646
VEXT / ES
General-purpose I/O
265
266
267
268
269
270
271
272
273
274
P23.7
P23.6
P22.4
P22.6
P22.7
P22.5
P22.8
P22.9
P22.10
P22.11
SLOW / PU1 / 179145
VEXT / ES
5252643
5205645
5158647
5111649
5064651
5017653
4970655
4923657
4876659
4829661
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
SLOW / PU1 / 356643
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
SLOW / PU1 / 356643
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
SLOW / PU1 / 356643
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
SLOW / PU1 / 356643
VEXT / ES
SLOW / PU1 / 179145
VEXT / ES
SLOW / PU1 / 356643
VEXT / ES
275
276
VDD
Vx
179145
185148
4782663
4675662
Supply Voltage
P22.0
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
277
P22.1
LVDS_TX /
FAST / PU1 /
VEXT / ES6
185148
4572666
General-purpose I/O
278
279
VSS
Vx
185148
185148
4461165
4351914
Supply Voltage
P22.2
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
280
P22.3
VSS
LVDS_TX /
FAST / PU1 /
VEXT / ES6
185148
4244418
4139667
General-purpose I/O
Supply Voltage
281
Vx
185148
205
Data Sheet
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
282
Pad Name
VEXT
VEXT
VEXT
VDD
Pad Type
X
Y
Comment
Vx
Vx
Vx
Vx
Vx
Vx
—
362646
185148
362646
185148
362646
362646
185148
4081563
4014063
3946563
3856563
3770163
3666159
3616749
3459600
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
283
284
285
286
VDD
287
VDD
288
VSS
289
XTAL1
XTAL / VEXT 185148
XTAL pad1
XTAL1. Main
Oscillator/PLL/Clock
Generator Input.
290
XTAL2
XTAL / VEXT 185148
3360600
XTAL pad2
XTAL2. Main
Oscillator/PLL/Clock
Generator OUTPUT
291
292
293
294
295
296
VSS
—
185148
362646
362646
185148
185148
362646
3203451
3154041
3009663
2960163
2861163
2788110
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
VEXT
VEXT
VSS
Vx
Vx
Vx
Vx
VSS
P21.0
LVDS_RX /
FAST / PU1 /
VEXT / ES
297
P21.1
LVDS_RX /
FAST / PU1 /
VEXT / ES
362646
2685114
General-purpose I/O
298
299
VDD
Vx
185148
362646
2611863
2529810
Supply Voltage
P21.2
LVDS_RX /
FAST / PU1 /
VEXT / ES
General-purpose I/O
300
P21.3
LVDS_RX /
FAST / PU1 /
VEXT / ES
362646
2426814
General-purpose I/O
301
302
VDD
Vx
185148
185148
2347263
2237760
Supply Voltage
P21.4
LVDS_TX /
FAST / PU1 /
VEXT / ES6
General-purpose I/O
303
P21.5
LVDS_TX /
FAST / PU1 /
VEXT / ES6
185148
2134764
General-purpose I/O
Data Sheet
206
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
304
P21.6/TDI
FAST / PD /
PU2 / VEXT /
ES3
362646
2027763
General-purpose I/O
PD during Reset and in
DAP/DAPE or JTAG mode.
After Reset release and when
not in DAP/DAPE or JTAG
mode: PU. In Standby mode:
HighZ. DAPE: DAPE1 Data
I/O.
305
TMS
FAST / PD2 / 185148
VEXT
1977363
JTAG Module State Machine
Control Input
TMS: JTAG Module State
Machine Control Input. DAP:
DAP1 Data I/O.
306
307
P21.7/TDO
TRST
FAST / PU2 / 362646
VEXT / ES4
1927863
1877643
General-purpose I/O
DAP: DAP2 Data I/O; DAPE:
DAPE2 Data I/O.
FAST / PU2 / 185148
VEXT
JTAG Module Reset/Enable
Input
TRST_N: JTAG Module
Reset/Enable Input. DAPE:
DAPE0 Clock Input
308
309
TCK
FAST / PD2 / 362646
VEXT
1827891
1777743
JTAG Module Clock Input
TCK: JTAG Module Clock
Input. DAP: DAP0 Clock
Input.
P20.0
FAST / PU1 / 185148
VEXT / ES
General-purpose I/O
310
311
312
VEXT
VSS
Vx
Vx
356643
185148
1723743
1665243
1615743
Supply Voltage
Supply Voltage
P20.1
SLOW / PU1 / 362646
VEXT / ES
General-purpose I/O
313
P20.2
P20.3
S / PU / VEXT 185148
1566243
General-purpose I/O
This pin is latched at power
on reset release to enter test
mode.
314
SLOW / PU1 / 362646
VEXT / ES
1516743
General-purpose I/O
Data Sheet
207
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
315
ESR1
FAST / PU1 / 185148
VEXT
1467243
ESR1 Port Pin input - can be
used to trigger a reset or an
NMI
ESR1: External System
Request Reset 1. Default NMI
function. See also SCU
chapter for details. Default
after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
316
317
PORST
ESR0
PORST / PD / 362646
VEXT
1417743
1368243
PORST pin
Power On Reset Input.
Additional strong PD in case
of power fail.
FAST / OD /
VEXT
185148
ESR0 Port Pin input - can be
used to trigger a reset or an
NMI
ESR0: External System
Request Reset 0. Default
configuration during and after
reset is open-drain driver.
The driver drives low during
power-on reset. This is valid
additionally after deactivation
of PORST_N until the internal
reset phase has finished. See
also SCU chapter for details.
Default after power-on can be
different. See also SCU
chapter ´Reset Control Unit´
and SCU_IOCR register
description.
PMS_EVRWUP: EVR
Wakepup Pin
318
319
320
321
322
VDD
VDD
VDD
VSS
P20.6
Vx
Vx
Vx
Vx
362646
185148
362646
185148
1280745
1195245
1109745
1060146
966105
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
General-purpose I/O
SLOW / PU1 / 362646
VEXT / ES
323
P20.7
FAST / PU1 / 185148
VEXT / ES
916605
General-purpose I/O
Data Sheet
208
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Sequence of Pads in Pad Frame
Table 2-36 Pad List (cont’d)
Number
Pad Name
Pad Type
X
Y
Comment
324
P20.8
FAST / PU1 / 362646
VEXT / ES
867105
General-purpose I/O
325
326
327
328
329
330
P20.9
FAST / PU1 / 185148
VEXT / ES
817605
768105
718605
669105
619605
570105
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
P20.10
P20.11
P20.12
P20.13
P20.14
FAST / PU1 / 362646
VEXT / ES
FAST / PU1 / 185148
VEXT / ES
FAST / PU1 / 362646
VEXT / ES
FAST / PU1 / 185148
VEXT / ES
FAST / PU1 / 362646
VEXT / ES
331
332
333
334
VSS
VDD
VEXT
VSS
Vx
Vx
Vx
Vx
185148
362646
179145
185148
520110
455805
382005
281205
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Whenever in table of section 3 ’Electrical Specification’ the term ‘neighbor pads’ is used, the detailed definition is
provided by Figure 2-36. This statement is also valid for next/nearest neighbor pads.
In order to find out who is affecting operation on a target pad (interfering) a number of active close-neighbor pads
(ACNP) has to be defined.
Finding close-neighbor pads.
The Pad Ring has four edges: bottom, left, top, right. Each edge is limited, i.e. it has two ends.
Each pad has two direct (first) neighbors unless it is located at the end of the edge. In that case it only has one
neighbor. Similarly, each pad has two indirect (second) neighbors unless it or its first neighbor is located at the
end of the edge. These first and second neighbors we will collectively call Close-Neighbor pads. Therefore each
pad has 2 to 4 close-neighbor pads.
Finding close-neighbors can be done with the following sequence:
1.) Choose a target pad and lookup its “X” and “Y” coordinates in table Figure 2-36.
2.) Find first and second neighbors by calculating “X” and “Y” distance from the selected pad. Figure 2-36 is sorted
by “Y” coordinate, which might help locate the 4 close-neighbor candidates (if the pad is near the edge, it might
end up with less than 4 close-neighbors).
Defining active pads:
Pad is active if it is currently in use and if it doesn’t have “Vxx” in the name.
Figuring out number of active close-neighbor pads follow next rules:
- If the first neighbor is active, then we count it and also check if second neighbor (on the same side of selected
pad) is active.
- If the first neighbor is not active, then we do not check the second on the same side.
Data Sheet
209
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Legend
2.4
Legend
The data in this chapter 2 for TP match with the file TC37xpd_IO_Spirit_v1.0.0.1.18.xml.
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field Selection PCx = 0XXXB)
O = Output (for GPIO port lines the ´O´ represents in most cases the port HWOUT function)
O0 = Output with IOCR bit field selection PCx = 1X000B
O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1)
O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2)
O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3)
O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4)
O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5)
O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6)
O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column “Buffer Type”:
RFAST = Pad class RFAST (5V/3.3V)
FAST = Pad class FAST (5V/3.3V)
SLOW = Pad class SLOW (5V/3.3V)
LVDS_TX = Pad class LVDS Transmit
LVDS_RX = Pad class LVDS Receive
S = Pad class S (Analog Input overlayed with General Purpose Input)
D = Pad class D (Analog Input)
Porst = Porst input Pad
XTAL1 = XTAL1 input Pad
XTAL2 = XTAL2 input Pad
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)1)
PU2 = with pull-up device connected during startup and reset, HighZ in Standby mode
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)1)
PD2 = with pull-down device connected during startup and reset, HighZ in Standby mode
OD = open drain during reset (PORST = 0)
ES = Supports Emergency Stop
ES1 = ES. ES can be overruled by VADC, control via P00_PCSR
ES2 = ES. ES can be overruled by DXCPL - DAP over CAN physical layer, No overruling for DXCM - Debug over
CAN message
ES3 = ES. ES can be overruled by JTAG mode if this pin is used as TDI
ES4 = ES. ES can be overruled by JTAG or Three Pin DAP mode
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG6 (P14.4). Pls. see also chapter
PMS, HWCFG[6].
Data Sheet
210
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OPEN MARKET VERSION
TC37x AA-Step
TC37x Pin Definition and Functions Legend
ES5 = ES. ES can be overruled by the Standby Controller - SCR - if implemented. Overruling can be disabled via
the control register P33_PCSR and P34_PCSR
ES6 = ES. On LVDS TX pads the ES affects the pads only in CMOS mode, not in LVDS mode. Thus, only when
LPCRx.TX_EN selects the CMOS Mode, the output is switched off in the ES event
Data Sheet
211
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Parameter Interpretation
3
Electrical Specification
3.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC37x and partly its requirements
on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with
an two-letter abbreviation in column “Symbol”:
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of the TC37x and must be
regarded for a system design.
•
SR
Such parameters indicate System Requirements which must be provided by the microcontroller system in
which the TC37x designed in.
Data Sheet
212
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Absolute Maximum Ratings
3.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 3-1 Absolute Maximum Ratings
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
150
Storage Temperature
T
ST SR
DD SR
-65
-
-
-
-
°C
V
upto 65h @ TJ = 150°C
upto 2.8h
Voltage at VDD power supply
pins with respect to VSS
V
-
-
-
1.65
1.45
4.43
1) 2)
V
upto 72h
Voltage at VDDP3 power supply VDDP3 SR
pins with respect to VSS
V
Voltage at VDDM, VEXT, VFLEX
and VEVRSB power supply pins
with respect to VSS
V
DDM SR
-
-
-
-
6.75
5.6
V
V
upto 2.8h
upto 72h
Voltage on all analog and class VIN SR
-0.7
-
6.75
V
S input pins with respect to VSS
3)
Voltage on all other input pins VIN SR
with respect to VSS
-0.7
-10
-
-
-
6.75
10
V
3)
Input current on any pin during IIN SR
mA
mA
4) 5)
overload condition
Absolute maximum sum of all ΣIIN SR
input circuit currents during
overload condition. 4)
-100
100
1) Valid for cumulated for up to 2.8h and pulse forms followed a power supply switch on phase, where the rise
and fall times are related to the system capacities and coils.
2) Due to EVRC output voltage oscillation during switch off phase VDD can drop down to -0.72V. For VDD an input level down
to -0.72V during switch off phase will not cause any damage or reliability problem.
3) Voltages below VINmin have no Impact to the device reliability as Long as the times and currents defined in section Pin
Reliability in Overload for the affected pad(s) are not violated.
4) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may
damage the device.
5) The specified min. and max. values represent the current limits, which have to be maintained, in case of a short circuit
condition on the output of any Fast, RFast, Slow and Class S pad, not being used during operation.
This covers also output currents due to switching in operation for CL=200pF.
Data Sheet
213
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Pin Reliability in Overload
3.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience overload currents and
voltages that go beyond their own IO power supplies specification.
The following table defines overload conditions that will not cause any negative reliability impact if all the following
conditions are met:
•
allowed time interval (defined in Note column) for overload condition is not exceeded. If no time limit is defined
the allowed time includes both ‘Operation Lifetime hours’ and ‘Inactive Lifetime hours’. The number of hours
in Table 3-67 and Table 3-68 are examples only and the applicable numbers are defined by the customer
profiles accepted by Infineon.
•
Operating Conditions are met for
–
–
pad supply levels
temperature
If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters
functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still
possible in most cases but with relaxed parameters.
Table 3-2 Overload Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-5
-15 1)
Max.
5
15 1)
Input current on any digital pin IIN
during overload condition
-
-
mA
mA
except LVDS pins
except LVDS pins;
limited to max. 20
pulses with 1ms pulse
length
Input current on LVDS pin
during overload condition
IINLVDS
IINANA
-3
-
3
mA
Input current on analog input
pin during overload condition
-3
-5
-
-
3
5
mA
mA
limited to 60h over
lifetime
Absolute sum of all analog
input currents for analog inputs
during overload condition
IINSA
-20
-
-
20
mA
mA
Absolute maximum sum of all ΣIINS
input circuit currents during
overload condition (digital and
analog combined)
-100
100
Signal voltage over/undershoot VOUS
at GPIOs
V
SS - 2
-
VEXT/FLEX/F
LEX2 + 2
V
limited to 60h over
lifetime; Valid for non
LVDS and analoge
pads
Sum of all inactive device pin IIDS
currents
-100
-
-
-
100
2.5
5
mA
mA
mA
Static pin output current
I
OUT CC
-
-
100% duty cycle;
output driver = medium
100% duty cycle;
output driver = strong
Data Sheet
214
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TC37x AA-Step
Electrical Specification Pin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
digital inputs, negative
KOVDN CC
-
-
3*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
fast pads; -5mA < IIN <
0mA
-
-
-
2*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
slow pads VGASTE1N
and VGATE1P; -5mA
< IIN < 0mA
-
1*10-4
Overload injected on
GPIO non LVDS pad
and affecting neighbor
slow pads; -5mA < IIN <
0mA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
0.5
Overload injected on
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for
digital inputs, positive
K
OVDP CC
1.5*10-3
Overload injected on
GPIO non LVDS pad
and affecting neighbor
GPIO non LVDS pads
1
Overload injected on
LVDS RX pad and
affecting neighbor
LVDS pads
5*10-3
1*10-4
1*10-5
Overload injected on
LVDS TX pad and
affecting neighbor
LVDS pads
Overload coupling factor for
analog inputs, negative 2)
KOVAN CC
Analog inputs overlaid
with slow pads or pull
down diagnostics; -
5mA < IIN < 0mA
else; -5mA < IIN < 0mA
Data Sheet
215
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Pin Reliability in Overload
Table 3-2 Overload Parameters (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Overload coupling factor for
analog inputs, positive 2)
KOVAP CC
-
-
2*10-4
Analoge inputs
overlaidwithslowpads
or pull down
diagnostics; 0mA < IIN
< 5mA
-
-
2*10-5
else; 0mA < IIN < 5mA
1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters.
2) Overload coupling on analog inputs is caused by parasitic effects between pads, input multiplexers and surrounding
structures.
The given parameters have been verified for all permutations of channels. Also watch multiple connections of a pin to
several channels.
Data Sheet
216
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TC37x AA-Step
Electrical Specification Operating Conditions
3.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the
TC37x. All parameters specified in the following tables refer to these operating conditions, unless otherwise
noticed.
Digital supply voltages applied to the TC37x must be static regulated voltages.
All parameters specified in the following tables refer to these operating conditions (see table below), unless
otherwise noticed in the Note / Test Condition column.
Table 3-3 Operating Conditions
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
300
300
300
100
300
100
200
100
-
SRI frequency
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SRI SR
-
-
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CPU Frequency (All CPUs)
PLL0 output frequency
SPB frequency
CPUx SR
PLL0 SR
SPB SR
FSI2 SR
FSI SR
-
-
20
-
-
-
FSI2 frequency
-
-
FSI frequency
20
-
-
GTM frequency
GTM SR
STM SR
ERAY SR
BBB SR
ADC SR
ASCLINx SR
CAN SR
I2C SR
-
STM frequency
-
-
ERAY frequency
BBB frequency
-
80
-
-
150
160
200
80
VADC frequency
ASCLIN Operating Frequency
CAN frequency
-
-
-
-
-
-
I2C frequency
-
-
100
200
320
Operating MSC Frequency
MSC SR
PLL1 SR
-
-
PLL1 output frequency from
PER PLL
20
-
PLL2 output frequency from
PER PLL
f
PLL2 SR
20
-
200
MHz
QSPI Frequency
f
f
f
f
QSPI SR
-
-
-
-
-
-
200
300
100
150
125
MHz
MHz
MHz
MHz
°C
ADAS clock frequency
MCANH frequency
GETH frequency
ADAS CC
MCANH CC
GETH CC
200
-
100
-40
Ambient Temperature
TA SR
valid for all SAK
products
-40
-40
-
-
150
170
°C
°C
valid for all SAL
products with package
valid for all SAL
products without
package
Data Sheet
217
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Operating Conditions
Table 3-3 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Junction Temperature
TJ SR
-40
-
150
°C
°C
valid for all SAK
products
-40
-
170
valid for all SAL
products
Core Supply Voltage
V
V
V
DD SR
1.125 1)
2.97
1.25
5.0
1.375 2)
5.5 3)
5.5 3)
V
V
V
ADC analog supply voltage
DDM SR
EXT SR
Digital external supply voltage
for pads and EVR
4.5
5.0
Nominal 5V Pad / Port
Pin supply range. 5V
pad parameters are
valid.
2.97
3.6
3.3
3.63
4.5
V
V
Nominal 3.3V Pad /
Port Pin supply range
with VDDP3 supplied
externally and EVR33
inactive. 3.3V pad
parameters are valid.
-
Flash configured in
cranking mode; Flash
read operation with
reduced performance.
EVR33 active in low
voltage mode. 3.3V
pad parameters are
valid.
2.97
-
3.6
V
Incase EVR33 is
active, Flash
configured in sleep
mode and execution
switched to RAM. 3.3V
pad parameters are
valid.
Digital supply voltage for Flex
port
V
FLEX SR
2.97
4.5
-
4.0
V
V
3.3V pad parameters
are valid; also vaild for
VFLEX2
5.0
5.5 3)
5V pad parameters are
valid; also vaild for
VFLEX2
Digital supply voltage for Flash VDDP3 SR
2.97
2.6
3.3
-
3.63 4)
3.63
V
V
Flash configured in
cranking mode; Flash
read operation with
reduced performance.
Digital ground voltage
V
V
SS SR
0
-
-
V
V
Analog ground voltage for VDDM
SSM CC
-0.1
0
0.1
Data Sheet
218
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TC37x AA-Step
Electrical Specification Operating Conditions
Table 3-3 Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
EVRSB SR 2.97 5)
Max.
Digital external supply voltage
for EVR and during Standby
mode
V
-
5.5
V
Voltage to ensure defined pad VDDPPA CC 1.3 6)
states
-
-
V
V
V
Digital supply voltage for Flex2 VFLEX2 SR 2.97
port
3.3
5
3.63
5.5
3.3V pad parameters
are valid
3.63
5V pad parameters are
valid
1) For VDD 1.08V ≤ VDD < 1.125V operation is still possible but with relaxed parameters.
2) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
3) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
4) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.
5) VEVRSB supply voltage can drop down upto 2.6V during Standby mode. It is required to have a capictor of 100nF on VEVRSB
supply pin.
6) HWCFG[6] pin is latched and pull-up or tristate is activated at Port pins when VEXT has reached this level.
Limitation of Supply Voltage over Time
The maximum operation voltage for VEXT/FLEX/DDM supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-4 Example Voltage Profile
VEXT/FLEX/DDM
=
Duration [h]
5.4 V < VEXT/FLEX/DDM ≤ 5.5 V
5.15 V < VEXT/FLEX/DDM ≤ 5.4 V
4.85 V < VEXT/FLEX/DDM ≤ 5.15 V
4.6 V < VEXT/FLEX/DDM ≤ 4.85 V
4.5 V < VEXT/FLEX/DDM ≤ 4.6 V
≤ 5% of lifetime
≤ 15% of lifetime
≤ 60% of lifetime
≤ 15% of lifetime
≤ 5% of lifetime
The maximum operation voltage for VDD supply rails is limited over the complete lifetime.
The following voltage profile is an example. Application specific voltage profiles need to be aligned and approved
by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-5 Example Voltage Profile
VDD=
Duration [h]
1.325 V < VDD ≤ 1.375 V
1.275 V < VDD ≤ 1.325 V
1.225 V < VDD ≤ 1.275 V
≤ 5% of lifetime
≤ 15% of lifetime
≤ 60% of lifetime
Data Sheet
219
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TC37x AA-Step
Electrical Specification Operating Conditions
Table 3-5 Example Voltage Profile
VDD=
Duration [h]
1.175 V < VDD ≤ 1.225 V
1.125 V < VDD ≤ 1.175 V
≤ 15% of lifetime
≤ 5% of lifetime
Data Sheet
220
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TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
3.5
5 V / 3.3 V switchable Pads
Pad classes slow GPIO and fast GPIO support both Automotive Level (AL) or TTL level (TTL) operation.
Parameters are defined for AL operation and degrade in TTL operation.
Table 3-6 PORST Pad
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
PORST CC 13
Max.
PORST pad Output current
I
-
-
-
-
mA
ns
VEXT = 2.97V; VPORST =
0.9V
Spike filter always blocked
pulse duration
t
t
SF1 CC
SF2 CC
-
80
-
Spike filter pass-through
blocked pulse duration
260
ns
without additional
PORST Digtial Filter
active (PORSTDF =
0).
Input hysteresis 1)
Pull-down current 2)
HYS CC
0.055 *
VEXT
-
-
V
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
I
I
PDL CC
-
-
-
-
|130|
-
µA
µA
nA
VIH; TTL (degraded,
used for CIF)
|15|
-450
VIL; TTL (degraded,
used for CIF)
Input leakage current
OZ CC
450
TJ≤150°C ; (0.1 * VEXT
)
)
< VIN < (0.9 * VEXT
)
-500
-900
-
-
500
900
nA
nA
TJ≤150°C ;else
TJ≤170°C ; (0.1 * VEXT
< VIN < (0.9 * VEXT
)
-950
1.4
-
-
950
-
nA
V
TJ≤170°C ; else
Input high voltage level
Input low voltage level
Pin capacitance
VIH SR
VIL SR
CIO CC
TTL (degraded, used
for CIF); VEXT = 2.97V
2.0
-
-
-
-
V
V
TTL; VEXT = 4.5V
0.5
TTL (degraded, used
for CIF); VEXT = 2.97V
-
-
-
0.8
3
V
TTL; VEXT = 4.5V
2
pF
in addition 2.5pF from
package to be added
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Data Sheet
221
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-7 Fast 5V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL
= 2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
3.2
CL = 25pF; driver =
strong sharp edge;
from 0.2 *
V
EXT/FLEX/FLEX2/EVRSB to
0.8 *
VEXT/FLEX/FLEX2/EVRSB
4+0.55*C 4+0.75*C 12+1.0*C ns
driver = medium;
CL≤200pF
L
L
L
1.0+0.18* 2.5+0.27* 5.0+0.35* ns
driver = strong edge =
CL
CL
CL
medium; CL≤200pF
0.5+0.08* 0.5+0.11* 1.0+0.17* ns
driver = strong edge =
CL
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.09 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/F
LEX2/EVRSB
0.075 *
VEXT/FLEX/F
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
LEX2/EVRSB
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
Pull-down current 5)
-
|130|
|30|
|28|
-
-
VIL; TTL
Data Sheet
222
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-7 Fast 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input leakage current
I
OZ CC
-1100
-
1100
nA
TJ ≤ 150°C ; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-2500
-
2500
nA
TJ ≤ 150°C ; (0.1 *
V
EXT/FLEX/FLEX2) < VIN <
(0.9 * VEXT/FLEX/FLEX2) ;
LVDS_TX / Fast pad
type
-6000
-3200
-
-
6000
3200
nA
nA
TJ ≤ 150°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 150°C ; LVDS_TX
/ Fast pad type ; else
-1500
-2000
-
-
1500
2000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-4000
-
4000
nA
TJ ≤ 170°C ; (0.1 *
V
EXT/FLEX/FLEX2) < VIN <
(0.9 * VEXT/FLEX/FLEX2) ;
LVDS_TX / Fast pad
type
-13500
-5100
-2500
-
-
13500
5100
nA
nA
TJ ≤ 170°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 170°C ; LVDS_TX
/ Fast pad type ; else
-
-
2500
-
nA
V
TJ ≤ 170°C ; else
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 *
AL
VEXT/FLEX/F
LEX2/EVRSB
2.0
-
-
-
V
V
TTL
AL
-
0.44 *
VEXT/FLEX/F
LEX2/EVRSB
-
-
-
0.8
V
TTL
Input low threshold variation
V
ILD SR
-50
50
mV
max. variation of 1ms;
VEXT/FLEX/FLEX2/EVRSB
=
constant; AL
Data Sheet
223
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-7 Fast 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pin capacitance
CIO CC
SET CC
-
2
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
-
-
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-8 Fast 3.3V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL
= 2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
4.5
CL = 25pF; driver =
strong sharp edge;
from 0.2 *
V
EXT/FLEX/FLEX2/EVRSB to
0.8 *
VEXT/FLEX/FLEX2/EVRSB
-
-
5
ns
CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
2+0.57*C 5.5+0.75* 10+1.25* ns
CL CL
1.5+0.18* 1.5+0.28* 8+0.4*CL ns
CL CL
driver = medium;
CL≤200pF
L
driver = strong edge =
medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns
driver = strong edge =
*CL
*CL
CL
sharp ; CL≤200pF
Asymmetry of sending
Input frequency
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
fIN CC
-
-
160
MHz
Data Sheet
224
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-8 Fast 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 3)
HYS CC
0.055 *
VEXT/FLEX/F
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
LEX2/EVRSB
0.09 *
VEXT/FLEX/F
-
-
V
V
non of the neighbor
pads are used as
output; TTL
LEX2/EVRSB
0.055 *
VEXT/FLEX/F
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
LEX2/EVRSB
125
-
-
-
-
mV
µA
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
|17|
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
VIH; TTL
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF)
Pull-down current 5)
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Data Sheet
225
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-8 Fast 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input leakage current
I
OZ CC
-1100
-
1100
nA
TJ ≤ 150°C ; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-2500
-
2500
nA
TJ ≤ 150°C ; (0.1 *
V
EXT/FLEX/FLEX2) < VIN <
(0.9 * VEXT/FLEX/FLEX2) ;
LVDS_TX / Fast pad
type
-6000
-3200
-
-
6000
3200
nA
nA
TJ ≤ 150°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 150°C ; LVDS_TX
/ Fast pad type ; else
-1500
-2000
-
-
1500
2000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-4000
-
4000
nA
TJ ≤ 170°C ; (0.1 *
V
EXT/FLEX/FLEX2) < VIN <
(0.9 * VEXT/FLEX/FLEX2) ;
LVDS_TX / Fast pad
type
-13500
-5100
-2500
-
-
13500
5100
nA
nA
TJ ≤ 170°C ; LVDS_RX
/ Fast pad type ; else
TJ ≤ 170°C ; LVDS_TX
/ Fast pad type ; else
-
-
2500
-
nA
V
TJ ≤ 170°C ; else
Input high voltage level
Input low voltage level
VIH SR
0.7 *
AL
VEXT/FLEX/F
LEX2/EVRSB
2.0
-
-
-
-
V
V
TTL
1.4
TTL (degraded, used
for CIF)
VIL SR
-
-
0.42 *
V
AL
VEXT/FLEX/F
LEX2/EVRSB
-
-
-
-
0.8
V
V
TTL
0.5
TTL (degraded, used
for CIF)
Input low/high voltage level
Data Sheet
V
ILH SR
1.0
-
1.9
V
RGMII; no hysteresis
available
226
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-8 Fast 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low threshold variation
V
ILD SR
-33
-
33
mV
max. variation of 1ms;
VEXT/FLEX/FLEX2/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-9 Slow 5V GPIO
Parameter
Symbol
Values
Typ.
225
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
Rise / Fall time 1) 2)
R
DSON CC
125
320
Ohm
medium driver; IOH / OL
= 2mA
t
RF CC
4+0.55*C 4+0.75*C 12+1*CL ns
driver = medium edge
= medium ; CL≤200pF
L
L
1.5+0.25* 2.5+0.40* 7+0.55*C ns
driver = medium edge
CL
CL
= sharp ; CL≤200pF
L
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.09 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/F
LEX2/EVRSB
0.075 *
VEXT/FLEX/F
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
LEX2/EVRSB
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet
227
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-9 Slow 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull-up current 4)
I
PUH CC
|30|
-
-
µA
VIH;AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
-
-
|130|
µA
VIL; AL or TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
Pull-down current 5)
Input leakage current
I
I
PDL CC
-
-
-
-
-
|130|
µA
µA
µA
nA
VIH; AL or TTL
VIL; AL
|30|
|28|
-300
-
-
VIL; TTL
OZ CC
300
TJ ≤ 150°C; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-400
-600
-
-
400
600
nA
nA
TJ ≤ 150°C; else
TJ ≤ 170°C; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-750
-
-
750
nA
nA
TJ ≤ 170°C; else
-18000
18000
P32.0 and
P32.1;TJ≤150°C
-38000
-
-
38000
-
nA
V
P32.0 and
P32.1;TJ≤170°C
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 *
AL
VEXT/FLEX/F
LEX2/EVRSB
2.0
-
-
-
V
V
TTL
AL
-
0.44 *
VEXT/FLEX/F
LEX2/EVRSB
-
-
-
0.8
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
-50
50
mV
max. variation of 1ms;
VEXT/FLEX/FLEX2/EVRSB
constant; AL
=
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
Data Sheet
228
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-10 Slow 3.3V GPIO
Parameter
Symbol
Values
Typ.
225
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
Rise / Fall time 1) 2)
R
DSON CC
125
320
Ohm
medium driver; IOH / OL
= 2mA
t
RF CC
2+0.57*C 5.5+0.75* 10+1.25* ns
CL CL
driver = medium edge
= medium ; CL≤200pF
L
2+0.30*C 3.5+0.50* 5+0.70*C ns
driver = medium edge
CL
= sharp ; CL≤200pF
L
L
Asymmetry of sending
t
TX_ASYM CC -1
-
1
ns
valid for all data rates
excluding clock
tolerance
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
160
-
MHz
V
HYS CC
0.055 *
non of the neighbor
pads are used as
output; AL
VEXT/FLEX/F
LEX2/EVRSB
0.09 *
VEXT/FLEX/F
-
-
-
-
V
V
non of the neighbor
pads are used as
output; TTL
LEX2/EVRSB
0.055 *
VEXT/FLEX/F
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
LEX2/EVRSB
125
-
-
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Data Sheet
229
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-10 Slow 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Pull-up current 4)
I
PUH CC
|17|
-
-
µA
VIH; AL and TTL
(degraded, used for
CIF); exept VGATE1P;
except VGATE1N and
TJ > 150°C
|11|
-
-
-
-
µA
µA
VIH; TTL; exept
VGATE1P; except
VGATE1N and TJ >
150°C
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF); exept
VGATE1P; except
VGATE1N and TJ >
150°C
Pull-down current 5)
I
I
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
OZ CC
-300
-
300
nA
TJ ≤ 150°C; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-400
-600
-
-
400
600
nA
nA
TJ ≤ 150°C; else
TJ ≤ 170°C; (0.1 *
V
EXT/FLEX/FLEX2/EVRSB) <
VIN < (0.9 *
VEXT/FLEX/FLEX2/EVRSB
)
-750
-
-
750
nA
nA
TJ ≤ 170°C; else
-18000
18000
P32.0 and
P32.1;TJ≤150°C
-38000
-
-
38000
-
nA
V
P32.0 and
P32.1;TJ≤170°C
Input high voltage level
VIH SR
0.7 *
AL
VEXT/FLEX/F
LEX2/EVRSB
2.0
-
-
-
-
V
V
TTL
1.4
TTL (degraded, used
for CIF)
Data Sheet
230
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-10 Slow 3.3V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VEXT/FLEX/F
LEX2/EVRSB
-
-
-
-
0.8
V
V
TTL
0.5
1.9
33
TTL (degraded, used
for CIF)
Input low/high voltage level
Input low threshold variation
V
V
ILH SR
ILD SR
1.0
-33
-
-
V
RGMII; no hysteresis
available
mV
max. variation of 1ms;
VEXT/FLEX/FLEX2/EVRSB
=
constant; AL
Pin capacitance
CIO CC
SET CC
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-11 RFast 5V GPIO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
125
225
55
-
320
Ohm
Ohm
ns
medium driver; IOH / OL
= 2mA
31
80
strong driver; IOH / OL =
8mA
Rise / Fall time 1) 2)
t
RF CC
1.6
3.2
CL = 25pF; driver =
strong sharp edge;
from 0.2 * VFLEX/FLEX2 to
0.8 * VFLEX/FLEX2
4+0.55*C 4+0.75*C 12+1.0*C ns
driver = medium;
CL≤200pF
L
L
L
1.0+0.18* 2.5+0.27* 5.0+0.35* ns
driver = strong edge =
CL
CL
CL
medium; CL≤200pF
0.5+0.08* 0.5+0.11* 1.0+0.17* ns
driver = strong edge =
CL
CL
CL
sharp ; CL≤200pF
Asymmetry of sending
Data Sheet
t
TX_ASYM CC -0.5
-
0.5
ns
valid for all data rates
excluding clock
tolerance
231
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-11 RFast 5V GPIO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input hysteresis 3)
fIN CC
-
-
-
MHz
V
HYS CC
0.09 *
VFLEX/FLEX
non of the neighbor
pads are used as
output; AL
2
0.075 *
VFLEX/FLEX
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
2
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
nA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
|130|
-
Pull-down current 5)
-
|30|
|28|
-1700
-
VIL; TTL
Input leakage current
I
OZ CC
1700
TJ ≤ 150°C ; (0.1 *
V
FLEX/FLEX2) < VIN < (0.9
* VFLEX/FLEX2
)
-2100
-3000
-
-
2100
3000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
V
FLEX/FLEX2) < VIN < (0.9
* VFLEX/FLEX2
)
-4000
-
-
4000
-
nA
V
TJ ≤ 170°C ; else
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7 *
AL
VFLEX/FLEX
2
2.0
-
-
-
V
V
TTL
AL
-
0.44 *
VFLEX/FLEX
2
-
-
-
0.8
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
-50
50
mV
max. variation of 1ms;
V
AL
FLEX/FLEX2 = constant;
CIO CC
SET CC
-
-
2
-
3.5
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
Data Sheet
232
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-12 RFast 3.3V pad
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
On-Resistance of pad output
R
DSON CC
8
20
30
Ohm
Ohm
Ohm
Driver = RGMII; IOH / OL
= 8mA
125
31
225
55
320
80
medium driver; IOH / OL
= 2mA
strong driver; IOH / OL
=
8mA
Input Duty Cycle
Rise / Fall time 1) 2)
fD SR
tRF CC
47.5
1.6
50
-
52.5
4.5
ns
ns
ns
CL = 25pF; driver =
strong sharp edge;
from 0.2 * VFLEX/FLEX2 to
0.8 * VFLEX/FLEX2
-
-
-
-
5
1
CL = 25pF; driver =
strong sharp edge;
from 0.8V to 2.0V
(RMII)
Driver = RGMII; from
20%V to 80%V;
CL=15pF
2+0.57*C 5.5+0.75* 10+1.25* ns
CL CL
1.5+0.18* 1.5+0.28* 8+0.4*CL ns
CL CL
driver = medium;
CL≤200pF
L
driver = strong edge =
medium; CL≤200pF
0.75+0.08 0.75+0.11 2.5+0.21* ns
driver = strong edge =
*CL
*CL
CL
sharp ; CL≤200pF
Asymmetry of sending
Input frequency
t
TX_ASYM CC -0.4
-
0.4
ns
valid for all data rates
excluding clock
tolerance
fIN CC
-
-
160
MHz
Data Sheet
233
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TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-12 RFast 3.3V pad (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 3)
HYS CC
0.055 *
VFLEX/FLEX
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
2
0.09 *
VFLEX/FLEX
-
-
V
V
non of the neighbor
pads are used as
output; TTL
2
0.055 *
VFLEX/FLEX
non of the neighbor
pads are used as
output;TTL (degraded,
used for CIF)
2
125
-
-
-
-
mV
µA
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 4)
I
I
PUH CC
|17|
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
VIH; TTL
|80|
VIL; AL and TTL and
TTL (degraded, used
for CIF)
Pull-down current 5)
PDL CC
-
-
|105|
µA
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
I
OZ CC
-1700
-
1700
nA
TJ ≤ 150°C ; (0.1 *
V
FLEX/FLEX2) < VIN < (0.9
* VFLEX/FLEX2
)
-2100
-3000
-
-
2100
3000
nA
nA
TJ ≤ 150°C ; else
TJ ≤ 170°C ; (0.1 *
V
FLEX/FLEX2) < VIN < (0.9
* VFLEX/FLEX2
)
-4000
-
-
4000
-
nA
V
TJ ≤ 170°C ; else
Input high voltage level
VIH SR
0.7 *
AL
VFLEX/FLEX
2
2.0
-
-
-
-
V
V
TTL
1.4
TTL (degraded, used
for CIF)
Data Sheet
234
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-12 RFast 3.3V pad (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VFLEX/FLEX
2
-
-
-
-
0.8
V
V
TTL
0.5
TTL (degraded, used
for CIF)
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-33
-
33
mV
pF
ns
max. variation of 1ms;
V
FLEX = constant; AL
-
-
2
-
3.5
100
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
1) In the formulas the value of CL needs to be entered in pF to obtain results in ns.
2) Rise / fall times are defined 10% - 90% of pad supply voltage.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
4) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
5) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-13 Class S 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
160
-
Input frequency
Input hysteresis 1)
fIN CC
-
-
-
MHz
V
HYS CC
0.09 *
VDDM
non of the neighbor
pads are used as
output; AL
0.075 *
VDDM
-
-
-
-
V
non of the neighbor
pads are used as
output; TTL
75
mV
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 2)
I
I
PUH CC
PDL CC
|30|
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
VIH; AL or TTL
VIL; AL or TTL
VIH; AL or TTL
VIL; AL
|130|
Pull-down current 3)
-
|130|
|30|
|28|
-
-
VIL; TTL
Data Sheet
235
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TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-13 Class S 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-150
-300
Max.
150
Input leakage current
I
OZ CC
-
-
nA
nA
TJ ≤ 150°C; else
300
TJ ≤ 150°C; PDD
option available, or
AltRef option available
and EDSADC channel
connected
-300
-600
-
-
300
600
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD
option available, or
AltRef option available
and EDSADC channel
connected
Input high voltage level
Input low voltage level
VIH SR
VIL SR
0.7*VDDM
-
-
-
-
-
V
V
V
AL
2.0
-
TTL
AL
0.44 *
VDDM
-
-
-
0.8
50
V
TTL
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-50
mV
max. variation of 1ms;
V
DDM = constant; AL
-
-
2
-
3
pF
ns
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
3) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-14 Class S 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input frequency
fIN CC
-
-
160
MHz
Data Sheet
236
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TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-14 Class S 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input hysteresis 1)
HYS CC
0.055 *
VDDM
-
-
-
-
V
non of the neighbor
pads are used as
output; AL
0.09 *
VDDM
-
-
V
V
non of the neighbor
pads are used as
output; TTL
0.065 *
VDDM
non of the neighbor
pads are used as
output; TTL (degraded
used for CIF)
125
|17|
-
-
-
-
mV
µA
two of the neighbor
pads are used as
output with
driver=strong and
edge=sharp; AL
Pull-up current 2)
I
I
PUH CC
VIH; AL and TTL
(degraded, used for
CIF)
|11|
-
-
-
-
µA
µA
µA
VIH; TTL
-
-
|80|
|105|
VIL
Pull-down current 3)
PDL CC
VIH; AL and TTL
(degraded, used for
CIF)
-
-
-
-
|115|
µA
µA
µA
VIH; TTL
|19|
|15|
-
-
VIL; AL and TTL
VIL; TTL (degraded,
used for CIF)
Input leakage current
I
OZ CC
-150
-300
-
-
150
300
nA
nA
TJ ≤ 150°C; else
TJ ≤ 150°C; PDD
option available, or
AltRef option available
and EDSADC channel
connected
-300
-600
-
-
300
600
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD
option available
Input high voltage level
VIH SR
0.7*VDDM
2.0
-
-
-
-
-
-
V
V
V
AL
TTL
1.4
TTL (degraded, used
for CIF)
Data Sheet
237
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-14 Class S 3.3V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input low voltage level
VIL SR
-
-
0.42 *
V
AL
VDDM
-
-
-
-
0.8
0.5
V
V
TTL
TTL (degraded, used
for CIF)
Input low threshold variation
Pin capacitance
V
ILD SR
CIO CC
SET CC
-33
-
33
3
mV
pF
ns
max. variation of 1ms;
V
DDM = constant; AL
-
-
2
-
in addition 2.5pF from
package to be added
Pad set-up time to get an
software update of the
configuration active
t
100
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed
that it suppresses switching due to external system noise.
2) Values for Pull-up resistor is defined via parameter RMDU in table VADC 5V.
3) Values for Pull-down resistor is defined via parameter RMDD in table VADC 5V.
Table 3-15 Class D
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
150
300 1)
Input leakage current
I
OZ CC
-150
-300 1)
-
-
nA
nA
TJ ≤ 150°C; else
TJ ≤ 150°C; PDD
option available, or
AltRef option available
and EDSADC channel
connected
-300
-600 2)
-
-
300
600 2)
nA
nA
TJ ≤ 170°C; else
TJ ≤ 170°C; PDD
option available, or
AltRef option available
and EDSADC channel
connected
Pin capacitance
CIO CC
-
2
3
pF
in addition 2.5pF from
package to be added
1) For AN11 100 nA need to be added.
2) For AN11 200 nA need to be added.
Data Sheet
238
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TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-16 ADC Reference Pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input leakage current for VAREF
I
OZ2 CC
-1
-
-
-
1
µA
µA
µA
TJ ≤ 150°C; VAREF <
V
DDM; used for EVADC
-2
2
TJ ≤ 170°C; VAREF <
V
DDM; used for EVADC
-3.5
3.5
TJ ≤ 150°C; VAREF
≤
V
DDM+50mV; used for
EVADC
-7
-
7
µA
TJ ≤ 170°C; VAREF
≤
V
DDM+50mV; used for
EVADC
-2 1)
-4 1)
-6 1)
-
-
-
2 1)
4 1)
6 1)
µA
µA
µA
TJ ≤ 150°C; VAREF <
V
DDM; for EDSADC
TJ ≤ 170°C; VAREF
<
V
DDM; for EDSADC
TJ ≤ 150°C; VAREF
≤
V
DDM+50mV; for
EDSADC
-12 1)
-
12 1)
µA
TJ ≤ 170°C; VAREF
≤
V
DDM+50mV; for
EDSADC
1) Limit is valid for VAREF1 pin.
Table 3-17 Driver Mode Selection for Slow Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Driver Setting
X
X
X
X
0
1
medium sharp edge (sm)
medium medium edge (m)
Table 3-18 Driver Mode Selection for Fast Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Speed grade 3
Speed grade 4
Driver Setting
X
X
X
X
0
0
1
1
0
1
0
1
Strong sharp edge (ss)
Strong medium edge (sm)
medium (m)
Reserved, do not use this combination
Table 3-19 Driver Mode Selection for RFast Pads
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 1
Speed grade 2
Driver Setting
X
X
0
0
0
1
Strong sharp edge (ss)
Strong medium edge (sm)
Data Sheet
239
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TC37x AA-Step
Electrical Specification 5 V / 3.3 V switchable Pads
Table 3-19 Driver Mode Selection for RFast Pads (cont’d)
PDx.2
PDx.1
PDx.0
Port Functionality
Speed grade 3
Speed grade 4
Driver Setting
medium (m)
X
X
1
1
0
1
RGMII function active
Data Sheet
240
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification High performance LVDS Pads
3.6
High performance LVDS Pads
This LVDS pad type is used for the high speed chip to chip communication interface of the new TC37x. It
composes out of a LVDSH pad and a fast pad.
CL = 2.5 pF for all LVDSH parameters.
Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
40
-
Max.
140
0.75 1)
Output impedance
R0 CC
-
-
Ohm
ns
Vcm = 1.0 V and 1.4 V
Rise time (20% - 80%)
t
rise20 CC
ZL = 100 Ohm ±20%
@2pF external load
Fall time (20% - 80%)
t
fall20 CC
-
-
-
-
-
-
0.75 2)
330
ns
ZL = 100 Ohm ±20%
@2pF external load
Output differential voltage 3)
V
OD CC
240
280
320
380
mV
mV
mV
mV
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=00
370
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=01
410
RT = 100 Ohm ±1%;
LPCRx.VDIFFADJ=10
500
RT = 100 Ohm ± 1%;
LPCRx.VDIFFADJ=11
; Multi slave operation
Output voltage high
Output voltage low
V
V
OH CC
-
-
-
-
-
-
-
1475
1500
-
mV
mV
mV
mV
mV
mV
RT = 100 Ohm +/- 1%
VDIFFADJ=00 and 01
-
RT = 100 Ohm ± 1%
VDIFFADJ=10 and 11
OL CC
925
900
1125
0
RT = 100 Ohm ± 1%
VDIFFADJ=00 and 01
-
RT = 100 Ohm +/- 1%
VDIFFADJ=10 and 11
Output offset (Common mode) VOS CC
voltage
1275
1600
RT = 100 Ohm ± 1%
Input voltage range
VI SR
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±10%
0
-
-
-
2400
100
mV
mV
mV
Driver ground potential
difference < 925 mV;
RT = 100 Ohm ±20%
Input differential threshold
V
idth SR
-100
-100
Driver ground potential
difference < 900 mV;
VDIFFADJ=10 and 11
100
Driver ground potential
difference < 925 mV;
VDIFFADJ=00 and 01
Data Sheet
241
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification High performance LVDS Pads
Table 3-20 LVDS - IEEE standard LVDS general purpose link (GPL) (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Receiver differential input
impedance
Rin CC
80
-
120
Ohm
mV
VI ≤ 2400 mV
Output differential voltage
Sleep Mode 4)
V
ODSM CC -5
-
20
RT = 100 Ohm ± 20%;
LPCRx.VDIFFADJ=xx
Delta output impedance
dR0 SR
-
-
-
-
10
25
%
Vcm = 1.0 V and 1.4 V
Change in VOS between 0 and dVOS CC
mV
RT = 100 Ohm ±1%
1
Change in Vod between 0 and dVod CC
1
-
-
25
13
55
mV
µs
%
RT = 100 Ohm ±1%
Pad set-up time
tSET_LVDS
-
10
-
CC
Duty cycle
t
duty CC
45
1) trise20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load.
2) tfall20 = 0.75ns + (CL - 2)[pF]*20ps. CL defines the external load.
3) Potential violations of the IEEE Std 1596.3 are intended for the new multislave support feature. To be compliant to IEEE
Std 1596.3 LPCRx.VDIFFADJ has to be configured to 01.
4) Common Mode voltage of Tx is maintained.
Note:Driver ground potential difference is defined as driver-receiver potentital difference, that can result in a
voltage shift when comparing driver output voltage level and receiver input voltage level of a transmitted
signal.
Note:RT in table ‘LVDS - IEEE standard LVDS general purpose Link (GPL)’ is as termination resistor of the
receiver according to figure 3-5 in IEEE Std 1596.3-1996 and is represent in Figure 3-1 either by RIN or by
RT=100Ohm but not both.
default after start-up = CMOS function
Data Sheet
242
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification High performance LVDS Pads
P
Htotal=5nH
Ctotal=3.5pF
LVDS
Cext=2pF
Rin
IN
RT=100Ohm
N
Htotal=5nH
Ctotal=3.5pF
Cext=2pF
LVDS_Input_Pad_Model.vsd
Figure 3-1 LVDS pad Input model
Data Sheet
243
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification VADC Parameters
3.7
VADC Parameters
The accuracy of the converter results depends on the reference voltage range. The parameters in the table below
are valid for a reference voltage range of (VAREF - VAGND) >= 4.5 V. If the reference voltage range is below 4.5 V
by a factor of k (e.g. 3.3 V), the accuracy parameters increase by a factor of 1.1/k (e.g. 1.1 × 4.5 / 3.3 = 1.5).
Noise on the voltage supply influences the conversion. The accuracy parameters are defined for a supply voltage
ripple of below 20 mVpp up to 10 MHz (below 5 mVpp above 10 MHz).
Digital functions overlapping analog inputs influence accuracy.
The total unadjusted error (TUE) is defined without noise. The overall deviation depends on TUE and ENRMS
(depending on the noise distribution). Example: For a noise distribution of 4 sigma and ENRMS = 1.0 the additional
peak-peak noise error is 8 LSB.
Fast compare operations are executed with 10-bit values.
The noise reduction feature improves the result by adding additional conversion steps. The conversion times,
therefore, increase accordingly (4 × tADCI + 3 × tADC for each of 1, 3, or 7 steps).
Table 3-21 VADC 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
EVADC IVR output voltage
V
DDK CC
1.15
-
1.35
V
%
V
V
V
V
Measured at low
temperature.
Deviation of IVR output voltage dVDDK CC -2
VDDK
Analog reference voltage 1)
-
2
Based on device-
specific value
V
AREF SR
4.5
5.0
3.3
VSSM
-
VDDM
0.05
+
+
4.5 V ≤ VDDM ≤ 5.5 V
2.97
VDDM
0.05
2.97 V ≤ VDDM < 4.5 V
Analog reference ground
Analog input voltage range
V
V
AGND SR VSSM
VSSM
V
SSM and VAGND are
connected together
AIN is limited by the
AIN SR
VAGND
VAREF
V
respective pad supply
voltage; see pin
configuration (buffer
type)
Converter reference clock
Total Unadjusted Error 2) 3)
f
ADCI SR
16
16
-4
40
20
-
53.33
26.67
4
MHz
MHz
LSB
4.5 V ≤ VDDM ≤ 5.5 V
2.97 V ≤ VDDM < 4.5 V
TUE CC
12-bit resolution for
primary/secondary
groups, 10-bit
resolution for fast
compare channels
INL Error 2)
DNL error 2)4)
Gain Error 2)
Offset Error 2)3)
RMS Noise 2)5) 6)
EAINL CC
-3
-
3
LSB
LSB
LSB
LSB
LSB
LSB
EADNL CC -1
EAGAIN CC -3.5
EAOFF CC -4
-
3
-
3.5
4
-
ENRMS CC
-
-
0.5
0.5
0.8
1.0
Noise reduction level 3
Standard conversion
Data Sheet
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TC37x AA-Step
Electrical Specification VADC Parameters
Table 3-21 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Reference input charge
QCONV CC
-
-
20
pC
VAIN = 0 V (worst
consumption per conversion
case), precharging
disabled
7) 8) 9)
(from VAREF
)
-
-
10
pC
VAIN = 0 V (worst
case), precharging
enabled, VDDM - 5% <
V
AREF < VDDM + 50 mV
Switched capacitance of an
analog input
C
AINS CC
-
-
2.5
-
3.4
3.5
pF
pC
Input buffer disabled
Analog input charge
consumption 10)
Q
AINS CC
Primary groups and
fast compare
channels;VAIN = VAREF
;
;
V
DDM = 5.0 V; input
buffer enabled; TJ ≤
150°C
-
-
3.8
pC
Primary groups and
fast compare
channels;VAIN = VAREF
V
DDM = 5.0 V; input
buffer enabled; TJ >
150°C
-
-
-
-
4.4
4.8
pC
pC
Secondary groups;
V
AIN = VAREF; VDDM
=
5.0 V; input buffer
enabled; TJ ≤ 150 °C
Secondary groups;
V
AIN = VAREF; VDDM
5.0 V; input buffer
enabled; TJ > 150°C
=
Data Sheet
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TC37x AA-Step
Electrical Specification VADC Parameters
Table 3-21 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sampling time
tS SR
100
-
-
ns
Primary group or fast
compare channel, 4.5
V ≤ VDDM ≤ 5.5 V; input
buffer disabled
300
-
-
ns
Primary group or fast
compare channel, 4.5
V ≤ VDDM ≤ 5.5 V; input
buffer enabled
500
700
200
-
-
-
-
-
-
ns
ns
ns
Secondary group, 4.5
V ≤ VDDM ≤ 5.5 V; input
buffer disabled
Secondary group, 4.5
V ≤ VDDM ≤ 5.5 V; input
buffer enabled
Primary Group or fast
comparechannel, 2.97
V ≤ VDDM < 4.5 V; input
buffer disabled
400
-
-
ns
Primary group or fast
comparechannel, 2.97
V ≤ VDDM < 4.5 V; input
buffer enabled
1000
1200
-
-
-
-
ns
ns
Secondary group, 2.97
V ≤ VDDM < 4.5 V; input
buffer disabled
Secondary group, 2.97
V ≤ VDDM < 4.5 V; input
buffer enabled
Sampling time for calibration
t
SCAL SR
50
-
-
ns
ns
µs
µs
µs
4.5 V ≤ VDDM ≤ 5.5 V
2.97 V ≤ VDDM < 4.5 V
100
-
-
Input buffer switch-on time
Wakeup time
t
t
BUF CC
WU CC
-
-
-
-
0.4
0.1
1.6
100
1
0.2
3
-
Fast standby mode
Slow standby mode
Broken wire detection delay
against VAREF
t
t
BWR CC
cycles Result above 80% of
fullscalerange, analog
input buffer disabled
Broken wire detection delay
against VAGND
BWG CC
-
100
-
cycles Result below 10% of
fullscalerange, analog
input buffer disabled
Converter diagnostics unit
resistance 11)
R
CSD CC
45
-
-
75
10
kOhm
Converter diagnostics voltage dVCSD CC -10
%
Percentage refers to
accuracy
VDDM
Data Sheet
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TC37x AA-Step
Electrical Specification VADC Parameters
Table 3-21 VADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Resistance of the multiplexer
diagnostics pull-up device
R
R
R
MDU CC
MDD CC
PDD CC
30
-
-
-
-
-
42
kOhm 0 V ≤ VIN ≤ 0.9* VDDM
,
,
Automotive Levels
56
43
18
-
78
58
25
0.3
kOhm 0 V ≤ VIN ≤ 0.9* VDDM
TTL Levels
Resistance of the multiplexer
diagnostics pull-down device
kOhm 0.1*VDDM ≤ VIN ≤ VDDM
,
,
Automotive level
kOhm 0.1*VDDM ≤ VIN ≤ VDDM
TTL level
Resistance of the pull-down
test device
kOhm Measured at pad input
voltage VIN = VDDM / 2.
1) These limits apply to the standard reference input as well as to the alternate reference input.
2) Parameter depends on reference voltage range and supply ripple, see introduction.
Resulting worst case combined error is arithmetic combination of TUE and ENRMS
.
Tests are done with postcalibration disabled, after completing the startup calibration.
3) Analog inputs mapped to pads of the type SLOW influence accuracy. The values for this parameter increase by 3 LSB12.
4) Monotonic characteristic, no missing codes when calibrated.
5) Parameter ENRMS refers to a 1 sigma distribution.
6) Analog inputs mapped to pads of the type SLOW the RMS noise (ENRMS) can be up to 2 LSB 12 (soft switching for DC/DC
enabled).
7) For reduced reference voltages VAREF < 3.375V, the consumed charge QCONV is reduced by the factor of k2 = VAREF
[V] / 3.375. For reduced reference voltages 4.5V < VAREF ≤ 3.375V, QCONV is not reduced.
8) Maximum charge increases by 15 pC when BWD (Broken Wire Detection) is active.
9) Fast compare channels only consume 1/3 of the charge for a primary/secondary group.
10) For analog inputs with overlaid digital GPIOs or with PDD function this value increases by 1 pC.
11) Use a sample time of at least 1.1 µs to enable proper settling of the test voltage.
Figure 3-2 Equivalent Circuitry for Analog Inputs
Data Sheet
247
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TC37x AA-Step
Electrical Specification DSADC Parameters
3.8
DSADC Parameters
The DSADC parameters are valid only for voltage range 4.5 V <= VDDM <= 5.5 V.
These parameters describe the product properties and do not include external circuitry. The values are valid for
junction temperatures TJ <= 150°C if not defined explicitly.
Calibration is specified for gain factors 1 and 2, calibrated values refer to these settings.
The signal-noise ratio (SNR) is specified for differential inputs. For single ended operation the resulting signal-
noise ratio is reduced by 6 dB. For quasi-differential mode (i.e. using VCM) its reduced by 3dB with gain=2 (6dB
with gain=1).
Table 3-22 DSADC 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Common mode voltage bias
resistance
R
V
V
BIAS CC
AREF SR
105
130
155
kOhm On-chip variation ≤
±2.5%.
Positive reference voltage
Reference ground voltage
Reference load current
4.5
-
-
VDDM
0.05
+
V
AGND SR VSSM
VSSM
V
VSSM and VAGND are
connected together
I
REF CC
-
-
10
-
12
14
µA
µA
Per modulator
Per modulator,
TJ>150°C
Common mode voltage
accuracy 1)
dVCM CC
-100
-
-
100
mV
V
Deviation from
selected voltage
Analog input voltage range
V
DSIN SR
VSSM
2 * VDDM
Differential;VDSxP -
VDSxN
VSSM
-
VDDM
V
Single ended
Input current 2)
I
RMS CC
7
10
13
µA
Exact value (±1%)
available in UCB; valid
for gain = 1 and fMOD
=
26.7 MHz
On-chip modulator clock
frequency
Gain error 3) 4)
f
MOD SR
16
-
40
MHz
%
EDGAIN CC -0.2 5)
±0.15)
0.2 5)
TJ≤150°C; Target,
calibrated, VAREF
constant after
calibration; fMOD
=
26.67 MHz
-
±0.25
-
%
TJ>150°C; VAREF
constant after
calibration; fMOD
=
26.67 MHz
-1
-
-
1
%
%
Calibrated once; fMOD
= 26.67 MHz
-2.5
2.5
Uncalibrated; fMOD =
26.67 MHz
Data Sheet
248
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TC37x AA-Step
Electrical Specification DSADC Parameters
Table 3-22 DSADC 5V (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DC offset error 3)
EDOFF CC -5 5)
-
-
-
-
-
-
-
5 5)
mV
mV
mV
dB
dB
dB
dB
Calibrated; fMOD =
26.67 MHz
-10
-30
10
30
-
Calibrated once; fMOD
= 26.67 MHz
Uncalibrated; fMOD
26.67 MHz
=
Signal-Noise Ratio for
differential input signals 2)6) 7)
SNR CC
80
78
74
-
TJ≤150°C; fPB = 30
kHz; fMOD = 26.67 MHz
-
TJ≤150°C; fPB = 50
kHz; fMOD = 26.67 MHz
-
TJ≤150°C; fPB = 100
kHz; fMOD = 26.67 MHz
Signal-NoiseRatiodegradation DSNR CC
3
TJ>150°C; Resulting
Signal-Noise Ratio
value is SNR - DSNR
Spurious-free dynamic range 3) SFDR CC 60
-
-
-
dB
fMOD = 26.67 MHz
Output sampling rate
fD CC
3.906
300
kHz
16 MHz / 4096, without
integrator
Pass band
f
PB CC
1.302
-
-
100
10
kHz
kHz
Output data rate: fD =
f
PB * 3; without
integrator
1.302
Output data rate: fD =
f
PB * 6; without
integrator
Pass band ripple
dfPB CC
SBA CC
-0.08
40
-
-
-
-
-
-
-
0.08
dB
dB
dB
dB
dB
dB
dB
FIR filters enabled
0.5 fD ... 1.0 fD
1.0 fD ... 1.5 fD
1.5 fD ... 2.0 fD
2.0 fD ... 2.5 fD
2.5 fD ... OSR/2 fD
10-5 fD, offset
compensation filter
enabled
Stop band attenuation
-
-
-
-
-
-
45
50
55
60
DC compensation factor
Modulator settling time
DCF CC
-3
(FCFGMx.OCEN =
001B)
t
MSET CC
-
-
20
µs
After switching on,
voltage regulator
already running
1) On pins with overlaid GPIO function the max. limit increases by up to 25 mV due to leakage current for TJ > 150°C.
2) For detailed information, refer to the User Manual chapter.
3) This parameter is valid within the defined range of fMOD
.
4) Gain mismatch error between the different EDSADC channels is within ±0.5% if they have the same calibration strategy
Data Sheet
249
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TC37x AA-Step
Electrical Specification DSADC Parameters
5) Recalibration needed in case of a temperature change >20ºC
6) These values are valid for an analog gain factor of 1. Subtract 3 dB for each higher gain factor.
7) For single ended input signals and gain1, the SNR is reduced by 6 dB.
Data Sheet
250
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TC37x AA-Step
Electrical Specification MHz Oscillator
3.9
MHz Oscillator
OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 16 MHz to 40 MHz crystals external
outside of the device. Support of ceramic resonators is also provided.
Table 3-23 OSC_XTAL
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
-70
4
Max.
70
Input current at XTAL1
Oscillator frequency
I
IX1 CC
-
-
µA
VIN>0V ; VIN<VEXT
f
OSC SR
40
MHz
Direct Input Mode
selected, if shaper is
not bypassed
16
-
-
-
-
40
MHz
ms
External Crystal Mode
selected
Oscillator start-up time
t
OSCS CC
-
3 1)
20MHz ≤ fOSC and 8pF
load capacitance
Input voltage at XTAL1 2)
VIX SR
-0.7
V
V
EXT + 0.5 V
EXT + 1.0 V
If shaper is not
bypassed
Input amplitude (peak to peak) VPPX SR
0.3*VEXT
If shaper is not
at XTAL1
bypassed; fOSC
25MHz
>
≤
0.35*VEXT
-
V
EXT + 1.0 V
If shaper is not
bypassed; fOSC
25MHz
Internal load capacitor
Internal load capacitor
Internal load capacitor
Internal load capacitor
C
C
C
C
C
C
L0 CC
L1 CC
L2 CC
L3 CC
1.30
3.05
7.85
12.05
1.40
3.35
8.70
13.35
1.20
2.5
1.55
3.70
9.55
14.65
1.25
4
pF
pF
pF
pF
pF
pF
enabled via bit
OSCCON.CAP0EN
enabled via bit
OSCCON.CAP1EN
enabled via bit
OSCCON.CAP2EN
enabled via bit
OSCCON.CAP3EN
Internal load stray capacitor
between XTAL1 and XTAL2
XINTS CC 1.15
Internal load stray capacitor
between XTAL1 and ground
XTAL1 CC
-
Duty cycle at XTAL1 3)
Absolute RMS jitter at XTAL1 3)
Slew rate at XTAL1 3)
DCX1 SR
ABSX1 SR
35
-
-
-
-
65
28
-
%
VXTAL1 = 0.5*VPPX
J
ps
10 KHz to fOSC/2
SRXTAL1 SR 0.3
V/ns
Maximum 30%
difference between
rising and falling slew
rate
1) tOSCS is defined from the moment when the Oscillator Mode is set to External Crystal Mode until the oscillations reach an
amplitude at XTAL1 of 0.3 * VEXT.
This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.
2) For Supply (VEXT < 5.3V VIX) min could be down to -0.9V. For XTAL1 an input level down to -0.9V will not cause a damage
or a reliability problem operating with an external crystal.
Data Sheet
251
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TC37x AA-Step
Electrical Specification MHz Oscillator
3) Square wave input signal for XTAL1.
Note:It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target
system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits
specified by the crystal or ceramic resonator supplier.
Data Sheet
252
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TC37x AA-Step
Electrical Specification Back-up Clock
3.10
Back-up Clock
The back-up clock provides an alternative clock source.
Table 3-24 Back-up Clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Back-up clock accuracy before fBACKUT CC 70
trimming
100
100
70
130
MHz
MHz
kHz
V
V
V
EXT≥2.97V
EXT≥2.97V
EXT≥2.97V
Back-up clock accuracy after
trimming 1)
f
f
BACKT CC
98
102
Standby clock
SB CC
25
110
1) A short term trimming providing the accuracy required by LIN communication is possible by periodic trimming every 2 ms
for temperature and voltage drifts up to temperatures of 125 celcius
Data Sheet
253
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TC37x AA-Step
Electrical Specification Temperature Sensor
3.11
Temperature Sensor
Table 3-25 DTS PMS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Measurement time for each
conversion 1)
tM CC
-
-
2.7
ms
°C
Measured from cold
power-on reset release
Calibration reference accuracy TCALACC CC -1
-
1
calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature
range
T
T
NL CC
SR SR
-2
-
-
2
°C
°C
TCALACC has to be
added in addition
DTS temperature range
-40
170
1) After warm reset tM is not restarted and is measured from last conversion.
Table 3-26 DTS Core
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Measurement time for each
conversion 1)
tM CC
-
-
2.7
ms
°C
Measured from cold
power-on reset release
Temperature difference
between on chip temperature
sensors
ΔT CC
-3
-
3
2
Calibration reference accuracy TCALACC CC -2
-
°C
calibration points @
TJ=-40°C and
TJ=127°C
Accuracy over temperature
range
T
T
NL CC
SR SR
-2
-
-
2
°C
°C
T
CALACC has to be
added in addition
DTS temperature range
-40
170
1) After warm reset tM is not restarted and is measured from last conversion.
Data Sheet
254
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TC37x AA-Step
Electrical Specification Power Supply Current
3.12
Power Supply Current
The total power supply current defined below consists of leakage and switching component.
Application relevant values are typically lower than those given in the following table and depend on the customer's
system operating conditions (e.g. thermal connection or used application configurations).
The operating conditions for the parameters in the following table are:
The real (realistic) power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
SRI = fCPUx = 300 MHz
GTM = 200 MHz
SPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz
V
V
V
DD = 1.275 V
DDP3 / FLEX = 3.366 V
EXT / EVRSB = VDDM = 5.1 V
all cores are active including two lockstep core (IPC=0.6)
the following peripherals are inactive: HSM, HSCT, GETH, Ethernet, PSI5, I2C, FCE, and MTU
The max power pattern defines the following conditions:
•
•
•
•
•
•
•
•
•
TJ = 150 °C
f
f
f
SRI = fCPUx = 300 MHz
GTM = 200 MHz
SPB = fSTM = fBAUD1 = fBAUD2 = fASCLINx = 100 MHz
V
V
V
DD = 1.375 V
DDP3 / FLEX = 3.63 V
EXT / EVRSB = VDDM = 5.5 V
all cores are active including three lockstep cores (IPC=1.2)
the following modules are inactive: GETH, FCE, and MTU
Data Sheet
255
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TC37x AA-Step
Electrical Specification Power Supply Current
Table 3-27 Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of IDD core and
peripheral supply currents (incl.
I
DDRAIL CC
-
-
-
-
-
-
-
-
-
-
-
775
mA
max power pattern;
valid for Feature
Package T, and TP
products
I
I
DDPORST+ ∑ IDDCx0+ ∑ IDDCxx
+
DDGTM+IDDSB
)
-
-
-
-
-
-
-
-
-
960 1)
630
775
190
132
220
315
315
425
mA
mA
mA
mA
mA
mA
mA
mA
mA
max power pattern;
valid for Feature
Package TE, and TX
products
real power pattern;
valid for Feature
Package T, and TP
products
real power pattern;
valid for Feature
Package TE, and TX
products
I
DD core current during active IDDPORST
VDD = 1.275V;
power-on reset (PORST pin
held low). Leakage current of
core domain. 2)
CC
TJ=125°C; valid for
Feature Package TE,
and TX products
V
DD = 1.275V;
TJ=125°C; valid for
Feature Package T,
and TP products
V
DD = 1.275V;
TJ=150°C; valid for
Feature Package T,
and TP products
V
DD = 1.275V;
TJ=165°C; valid for
Feature Package T,
and TP products
V
DD = 1.275V;
TJ=150°C; valid for
Feature Package TE,
and TX products
V
DD = 1.275V;
TJ=165°C; valid for
Feature Package TE,
and TX products
Data Sheet
256
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Power Supply Current
Table 3-27 Current Consumption (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of IDDP3 3.3 V supply
currents
IDDP3RAIL
CC
-
-
45 2)
mA
max power pattern
incl. Flash read current
and Dflash
programming current.
-
-
36 3)
mA
real power pattern incl.
Flash read current and
Dflash programming
current.
∑ Sum of external IEXT supply
currents (incl.
I
I
EXTRAIL CC -
-
-
50
35 4)
mA
mA
max power pattern
real power pattern
-
I
EXTFLEX+IEVRSB+IEXTLVDS)
I
EXT and IFLEX supply current
EXTFLEX CC -
-
11 5) 6)
mA
real power pattern with
port activity absent;
PORST output
inactive.
I
EVRSB supply current 2)
I
EVRSB CC
-
-
8.5
mA
real power pattern;
PMS/EVR module
current considered
without SCR and
Standby RAM during
RUN mode.
∑ Sum of external IDDM supply IDDM CC
currents (incl.
-
-
-
-
-
-
-
-
-
-
-
-
27
mA
mA
mA
mA
mA
mA
real power pattern;
sum of currents of
EDSADC and EVADC
modules
I
DDMEVADC+IDDMEDSADC)
∑ Sum of all currents (incl.
EXTRAIL+IDDMRAIL+IDDx3RAIL+IDD)
I
DDTOT CC
728
873
796
1015
430
real power pattern;
TJ=150°C; valid for
Feature Package T,
and TP products
I
real power pattern;
TJ=150°C; valid for
Feature Package TE,
and TX products
real power pattern;
TJ=160°C; valid for
Feature Package T,
and TP products
real power pattern;
TJ=160°C; valid for
Feature Package TE,
and TX products
∑ Sum of all currents with DC- IDDTOTDC3
real power pattern;
EVRC reset settings
with 72% efficiency;
7)
DC EVRC regulator active
CC
V
EXT = 3.3V; TJ=150°C
Data Sheet
257
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Power Supply Current
Table 3-27 Current Consumption (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of all currents with DC- IDDTOTDC5
-
-
320
mA
real power pattern;
EVRC reset settings
with 72% efficiency;
7)
DC EVRC regulator active
CC
V
EXT = 5V; TJ=150°C
∑ Sum of all currents (SLEEP
mode) 2)
I
I
SLEEP CC
-
-
25
mA
µA
All CPUs in idle, All
peripherals in sleep,
f
SRI/SPB = 1 MHz via
LPDIV divider; TJ =
25°C
∑ Sum of all currents
STANDBY CC -
-
130 9)
32 kB Standby RAM
block active. SCR
inactive. Power to
remaining domains
switched off. TJ =
25°C; VEVRSB = 5V
(STANDBY mode) drawn at
V
EVRSB supply pin 8)
Maximum power dissipation 10) PD SR
-
-
-
-
-
-
-
-
1600
1855
1240
1425
mW
mW
mW
mW
max power pattern;
valid for Feature
Package T, and TP
products
max power pattern;
valid for Feature
Package TE, and TX
products
real power pattern;
valid for Feature
Package T, and TP
products
real power pattern;
valid for Feature
Package TE, and TX
products
1) In QFP package for TC37xED emulation device, the total (IDDED + IDD) current need to be limited to 700 mA. The
maximum (IDDED + IDD) current for TC37xED is supported only in BGA packages.
2) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
3) Realistic Pflash read pattern with 50% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common
decoupling capacitor of atleast 100nF for (VDDP3) is used. Continuous Dflash programming in burst mode with 3.3 V supply
and realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective
programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to 45 mA
/ 20 ns
which are handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply
dimensioning and not for thermal considerations.
4) Limits are defined for real power pattern. For ADAS power pattern limit sum up to 42mA.
5) The current consumption includes only minimal port activity.
6) Limits are defined for real power pattern. For ADAS power pattern limit has to be multiplied by the factor 0.7.
7) The total current drawn from external regulator is estimated with 72% EVRC SMPS regulator efficiency. IDDTOTDCx is
calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents
and IDDM.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Current
8) The same current limits apply also for the other power pattern.
9) ∑ Sum of all currents during RUN mode at VEVRSB supply pin is less than (IEVRSB + 4 mA Standby RAM current +
ISCRSB if SCR active). ∑ It is recommended to have atleast 100 nF decoupling capacitor at this pin. 32kB of Standby
SRAM contributes less than 10uA to ISTANDBY current.
10) The values are only valid if all supplies are applied from external and do not contain the power losses of EVR33 and EVRC.
Table 3-28 Module Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DDP3 supply current for
IDDP3PROG
CC
-
-
-
-
-
25
mA
Pflash 3.3V
programming of a Pflash or
Dflash bank 1)
programming current
adder when using
external 3.3V supply.
-
9 2)
mA
mA
mA
Pflash 3.3V
programming current
adder when using
external 5V supply.
I
EXT supply current added by
I
EXTLVDS CC -
16
real power pattern; 4
pairs of LVDS pins
active with transmit
function
LVDS pads in LVDS mode 1)
-
9 3)
real power pattern; 6
pairs of LVDS pins
active with receive
function
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Current
Table 3-28 Module Current Consumption (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
∑ Sum of external IDDM supply IDDM CC
currents (incl.
-
-
14
mA
real power pattern;
current for EDSADC
modules only and
EVADC modules are
inactive; 4 EDSADC
channels active
I
DDMEVADC+IDDMEDSADC)
continuously.
-
-
22 4)
mA
max power pattern;
current for EDSADC
modules only and
EVADC modules are
inactive; all EDSADC
channels active
continuously.
-
-
-
-
13 5)
mA
mA
real power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; 8 EVADC
modules active.
15 6)
max power pattern;
current for EVADC
modules only and
EDSADC modules are
inactive; all EVADC
modules active.
I
DDP3 supply current for erasing IDDP3ERASE
-
-
-
-
25
mA
mA
Pflash 3.3V erasing
current adder when
using external 3.3V
supply.
of a Pflash or Dflash bank
CC
SCR 8-bit Standby Controller
current incl. PMS in STANDBY
Mode drawn at VEVRSB supply
pin
I
SCRSB CC
7 7)
SCR power pattern
incl. PMS current
consumption with
fback clock active;
f
SYS_SCR = 20MHz;
TJ=150°C
-
0.150
-
mA
mA
SCR power pattern
incl. PMS current
consumption with
fback inactive;
fSYS_SCR = 70kHz;
TJ=25°C
SCR 8-bit Standby Controller
CPU in IDLE mode 8)
I
SCRIDLE CC -
-
3.5
real power pattern.
CPU set into idle
mode.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Current
1) The same current limits apply also for the other power pattern.
2) During Pflash programming at 5V, additional 2 mA is drawn at VEXT supply rail.
3) A single LVDS pair with receive function is limited to 1.5mA (tEXTLVDS).
4) A single DS channel instance consumes 4 mA.
5) EVADC current is limited to 3mA in "ADAS power pattern with 2 EVADC" at (IDDM).
6) A single VADC unit consumes 1.3 mA.
7) If SCR ADCOMP is activated, an additional 0.6 mA adder is to be considered.
8) Limits are defined for real power pattern (VDD=1.275V). For max power pattern limit has to be multiplied by the factor 1.22.
Table 3-29 Module Core Current Consumption
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
I
DD core current of CPUx main IDDCx0 CC
-
-
-
-
-
72
mA
mA
mA
mA
max power pattern;
IPC=1.2
core with CPUx lockstep core
inactive
-
-
-
48
real power pattern;
IPC=0.6
I
DD core current of CPUx main IDDCxx CC
IDDCx0
48
+
+
max power pattern;
IPC=1.2
core with CPUx lockstep core
active
IDDCx0
37
real power pattern;
IPC=0.6
I
DD core current added by GTM IDDGTM CC
-
-
-
-
110
90
mA
mA
max power pattern
real power pattern;
TIMx, TOMx, ATOMx ,
MCSx active. 2
clusters at 200 MHz.
-
-
-
50
mA
mA
TIMx, TOMx active at
100MHz. ATOMx ,
MCSx, DPLL inactive.
2 clusters at 100 MHz.
I
DD core current added by HSM IDDHSM CC
-
-
20 1)
max power pattern;
HSM running at
100MHz.
I
I
DD core current added by CIF
I
DDCIF CC
-
-
48
200 2)
mA
mA
conditions t.b.d.
DD core dynamic current added IDDLBIST CC -
LBISTConfigurationA;
by LBIST
DD core dynamic current added IDDMBIST CC -
by MBIST
1.2V ≤ VDD
I
-
225
mA
fMBIST = 300MHz;
tMBIST < 6ms. MTU
Ganging procedure for
SRAM test and
initialization; VDD =
1.375V.
1) The current consumption includes basic HSM activity incl. AES module.
2) LBIST is executed either during start-up phase or can be triggered by application software. Secondary voltage monitors
are inactive during the LBIST execution time (tLBIST).
During the start-up phase externally supplied VDD voltage has to be equal or greater than 1.2V (VDD nominal - 4%) for static
accuracy.
If VDD is supplied internally by EVRC, EVRC takes care not to violate the VDD 1.2V static under voltage limit.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Current
3.12.1
Calculating the 1.25 V Current Consumption
The current consumption of the 1.25 V rail compose out of two parts:
•
•
Static current consumption
Dynamic current consumption
The static current consumption is related to the device temperature TJ and the dynamic current consumption
depends of the configured clocking frequencies and the software application executed. These two parts needs to
be added in order to get the rail current consumption.
(3.1)
mA
0, 024 × T
--------
C
I
= 3, 974
= 6, 01
× e
[C]
J
0
(3.2)
mA
--------
0, 024 × T
I
× e
[C]
J
0
C
Equation (3.1) defines the typical static current consumption and Equation (3.2) defines the maximum static
current consumption. Both functions are valid for VDD = 1.275 V.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13
Power Supply Infrastructure and Supply Start-up
3.13.1
Supply Ramp-up and Ramp-down Behavior
Start-up slew rates for supply rails shall comply to SR (see Table 3-33 Supply Ramp).
3.13.1.1 Single Supply mode (a)
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
VEXT (externally supplied)
0
1
2
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDD
(internally generated
by EVRC)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
EVRC_tSTR
0 V
VDDP3
(internally generated
by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVR33_tSTR
0 V
tBP (incl. tEVRstartup)
T3
T0
T1
T2
T4
User Code Execution
fCPU0=100MHz default
T5
EVRC & EVR33 Ramp-up
Phase
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_2 v 0.3
on firmware exit
Figure 3-3 Single Supply mode (a) - VEXT (5 V) single supply
VEXT = 5 V single supply mode. VDD and VDDP3 are generated internally by the EVRC and EVR33 internal
regulators.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited during the basic
infrastructure and EVRx regulator start-up phase (T0 up to T2) to a maximum of 100 mA with 100 us settling
time. Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is defined as the
maximal tangential slope between 0% to 100% voltage level. Actual waveform may not represent the
specification.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
•
Furthermore it is also ensured that the current drawn from the regulator (dIDD/dt) is limited during the Firmware
start-up phase (T3 up to T4) to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of up to 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-3 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started .The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVRC and EVR33 regulators are initiated.
PORST (input) does not have any affect on EVR33 or EVRC output and regulators continue to generate
the respective voltages though PORST is asserted and the device is in reset state. The generated voltage
follows a soft ramp-up over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC and EVR33 regulators have ramped up.
PORST (output) is de-asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU.
Firmware execution is initiated. The time between T1 and T3 is documented as tEVRstartup (datasheet
parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.2 Single Supply mode (e)
0
1
2
3
4
5
VEXT/VDDP3
(externally supplied)
LVD Reset release
HWCFG[1,2] latch
3.63 V
3.30 V
VRST5/
VRST33 Primary cold PORST Reset Threshold
VLVDRST5
LVD Reset Threshold
VDDPPA
HWCFG[6] latch
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDD (internally generated
by EVRC)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVRC is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVRC_tSTR
0 V
tBP (incl. tEVRstartup)
T3
T0
T2
T4
User Code Execution
fCPU0=100MHz default
T5
T1
EVRC Ramp-up
Phase
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_4 v 0.3
on firmware exit
Figure 3-4 Single Supply mode (e) - (VEXT & VDDP3) 3.3 V single supply
VEXT = VDDP3 = 3.3 V single supply mode. VDD is generated internally by the EVRC regulator.
•
The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 100 mA with 100 us settling time. Start-up slew rates for supply rails shall comply to datasheet
parameter SR. The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual
waveform may not represent the specification.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary
reset threshold.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-4 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started .The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVRC regulator is initiated. PORST (input)
does not have any affect on EVRC output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVRC regulator has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.3 External Supply mode (d)
VEXT (externally supplied)
0
1
2
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
PORST (output driven by PMS)
PORST (input driven by external regulator)
PORST input deasserted by external
regulator when all input voltages have
reached their minimum operational level
VDDP3 (internally generated
by EVR33)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
tEVRstartup
(incl. tSTR)
EVR33 is started with a delay after
VLVDRST5 level is reached at VEXT &
VLVDRSTC level is reached at VDDPD
EVR33_tSTR
0 V
tBP (incl. tEVRstartup)
T1
T0
T3
T2
T4
User Code Execution
fCPU0=100MHz default
T5
Basic Supply & Clock
Infrastructure
EVR33 Ramp-up Phase
Firmware Execution
Power Ramp-down phase
on firmware exit
Startup_Diag_1 v 0.3
Figure 3-5 External Supply mode (d) - VEXT and VDD externally supplied
VEXT = 5 V and VDD supplies are externally supplied. 3.3V is generated internally by the EVR33 regulator.
•
External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The slope is
defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDD rail. If VDD voltage
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
rail is ramped up before VEXT; VDD supply overshoots during start-up shall be limited within the operational
voltage range.
•
The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-5 is enumerated below
–
T1 up to T2 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
T2 refers to the point in time where consequently a soft start of EVR33 regulator is initiated. PORST (input)
does not have any affect on EVR33 output and regulators continue to generate the respective voltages
though PORST is asserted and the device is in reset state. The generated voltage follows a soft ramp-up
over the tSTR (datasheet parameter) time to avoid overshoots.
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. EVR33 regulators has ramped up. PORST (output) is de-
asserted and HWCFG[3:5] pins are latched on PORST rising edge by SCU. Firmware execution is initiated.
The time between T1 and T3 is documented as tEVRstartup (datasheet parameter).
–
–
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided or
generated supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset
thresholds.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
3.13.1.4 External Supply mode (h)
VEXT (externally supplied)
0
1
3
4
5
5.5 V
5.0 V
4.5 V
LVD Reset release
HWCFG[1,2] latch
VRST5
Primary cold PORST Reset Threshold
LVD Reset Threshold
VLVDRST5
VDDPPA
0 V
HWCFG[6] latch
VDD (externally supplied)
1.375 V
1.25 V
VRSTC
Primary Reset Threshold
0 V
VDDP3
(externally supplied)
3.63 V
3.30 V
VRST33
Primary Reset Threshold
0 V
PORST output deasserted when VDD,
VDDP3 and VEXT voltage above
respective primary reset thresholds
tPOA time to ensure adequate time between reset releases
PORST (input driven by external regulator)
PORST (output driven by PMS)
tBP
T3
T0
T1
T4
T5
User Code Execution
fCPU0=100MHz default
on firmware exit
Basic Supply & Clock
Infrastructure
Firmware Execution
Power Ramp-down phase
Startup_Diag_3 v 0.4
Figure 3-6 External Supply mode (h) - VEXT, VDDP3 & VDD externally supplied
All supplies, namely VEXT, VDDP3 & VDD are externally supplied.
•
External supplies VEXT, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s). Start-up slew rates for supply rails shall comply to datasheet parameter SR. The
slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification. It is expected that during start-up, VEXT ramps up before VDDP3 and VDD rails.
If smaller voltage rails are ramped up before VEXT; VDD and VDDP3 supply overshoots during start-up shall
be limited within the operational voltage ranges of the respective rails.
Data Sheet
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TC37x AA-Step
Electrical Specification Power Supply Infrastructure and Supply Start-up
•
The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 100 mA with 100 us settling time.
•
•
PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
•
PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when at least one among
the three supply domains (VDD, VDDP3 or VEXT) violate their primary under-voltage reset thresholds.The
PORST (output) is de-asserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available. During reset release at T3, the load jump of upto 150 mA
(dIDD) is expected.
•
The power sequence as shown in Figure 3-6 is enumerated below
–
T1 up to T3 refers to the period in time when basic supply and clock infrastructure components are
available as the external supply ramps up. The bandgap and internal clock sources are started. The supply
mode is evaluated based on the HWCFG[2:1,4,5,6] and TESTMODE pins. T1 up to T2 refers to the period
in time when basic supply and clock infrastructure components are available as the external supply ramps
up. The bandgap and internal clock sources are started .The supply mode is evaluated based on the
HWCFG[2:1,6] pins. These events are initiated after LVD reset release at T1. LVD reset is released the
both input voltages VEXT and VEVRSB are above VLVDRST5 and VLVDRSTSB levels correspondingly.
Internal pre-regulator VDDPD output voltage is above VLVDRSTC level.
–
–
–
T3 refers to the point in time when all supplies are above their primary reset thresholds denoted by VRST5,
VRST33 and VRSTC supply voltage levels. PORST (output) is de-asserted and HWCFG[3:5] pins are
latched on PORST rising edge by SCU. Firmware execution is initiated.
T4 refers to the point in time when Firmware execution is completed and User code execution starts with
CPU0 at a default frequency of 100 MHz. The time between T0 and T4 is documented as tBP (datasheet
parameter).
T5 refers to the point in time during the ramp-down phase when at least one of the externally provided
supplies (VDD, VDDP3 or VEXT) drop below their respective primary under-voltage reset thresholds.
Data Sheet
271
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Reset Timing
3.14
Reset Timing
Table 3-30 Reset
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Application Reset Boot Time
System Reset Boot Time
tB CC
-
-
400
µs
operating with max.
frequencies, with valid
BMI header
t
t
BS CC
-
-
-
1.1
3.1
ms
ms
RAM initialization and
HSM boot time are not
included, with valid
BMI header
Cold Power on Reset Boot
Time 1)
BP CC
-
dVEXT/dT=1V/ms.
VEXT>VLVDRST5.
Boot time after Cold
PORST including EVR
ramp-up and Firmware
execution time; RAM
initialization and HSM
boot time are not
included.
-
-
-
1.6
ms
Firmware execution
time after PORST
release without EVR
ramp-up; RAM
initialization and HSM
boot time is not
included
Minimum cold PORST reset
hold time in case of power fail
event issued by EVR primary
monitors
t
EVRPOR CC 10 2)
-
µs
PMS Infrastructure, EVRC and tEVRstartup
EVR33 overall start-up time till CC
cold PORST reset release
-
-
-
1
-
ms
ms
dV/dT=1V/ms. EVRC
and EVR33 active
Minimum PORST active hold
time externally after power
supplies are stable at operating
levels after start-up
t
POA SR
1 3)
Configurable PORST digital
filter delay in addition to analog
pad filter delay
t
PORSTDF CC 600
-
1200
ns
WarmResetSequencingDelay tWARMRSTSEQ
-
-
-
180
-
µs
ns
CC
HWCFG pins hold time from
ESR0 rising edge
t
HDH CC
16 / fSPB
Data Sheet
272
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Reset Timing
Table 3-30 Reset (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
HWCFG pins setup time to
ESR0 rising edge
t
HDS CC
0
-
-
-
-
-
-
-
-
ns
s
Ports inactive after ESR0 reset tPI CC
active
8000/fBAC
18000/fBA
KT
CKT
Ports inactive after PORST
reset active
t
t
t
t
t
t
PIP CC
-
160
ns
ns
ns
ms
ms
Hold time from PORST rising
edge
POH SR
POS SR
BWP CC
LBIST CC
SCR CC
150
-
Setup time to PORST rising
edge
0
-
-
Warm PORST reset boot time
1.5
6
without RAM
initalization
LBIST execution time
extending the boot time
-
LBISTConfigurationA;
1.2V ≤ VDD
SCR reset boot time
-
-
-
-
5
µs
µs
µs
User Mode 0
User Mode 1
-
16
-
13.3
WDT double bit ECC,
soft reset
Minimum external supplies
hold time after warm reset
assertion
t
SUPHOLD CC -
-
250
µs
external supplies are
V
V
V
EVRSB, VEXT,
FLEX/FLEX2, VDDM
DDP3 and VDD
,
1) RAM initialization add 500µs in addition.
2) Cold PORST reset is driven by uC and maintained in an extended voltage range between VDDPPA limit and absolute
maximum rating voltage limits.
3) The reset release on supply ramp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above
the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple
consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released.
Data Sheet
273
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Reset Timing
VDDPPA
VDDPPA
VDDP
VDD
VDDPR
tPOA
tPOA
Warm
PORST
ESR0
Cold
t PI
Programmed
tPI
tPIP
Tristate Z / pullup H
Programmed
Z / H
Z / H
Programmed
Pads
Pad-
state
undefined
Pad-
state
undefined
tPOS
tPOS
tPOH
tPOH
TRST
TESTMODE
tHDH
tHDH
tHDA
tHDH
config
tHDA
HWCFG
power -on config
config
reset_beh_aurix
Figure 3-7 Power, Pad and Reset Timing
Data Sheet
274
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
3.15
PMS
Table 3-31 EVR33 LDO
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
5.50
5.50
Input voltage range
VIN SR
3.60 1)
2.97 2)
-
-
V
V
Normal RUN mode
Low voltage cranking
mode
Output voltage operational
range including load/line
regulation and aging 3)
V
V
OUT CC
2.97
2.60
3.3
3.3
3.63
3.63
V
V
Normal RUN mode
Low voltage cranking
mode; IDDP3=50mA
Output VDDx3 static voltage
accuracy after trimming and
aging without dynamic load/line
regulation.
OUTT CC
3.225
2.78
3.3
3.3
3.375
3.375
V
V
Normal RUN mode
Low voltage cranking
mode; IDDP3=50mA
Output buffer capacitance on
COUT SR
1.45
2.2
3
µF
VOUT
Output buffer capacitor ESR
C
OUTESR SR -
-
-
100 4)
-
mOhm f > 0.5MHz; f < 10MHz
Maximum output current of the IMAX CC
60 5)
mA
Normal RUN mode
regulator
Startup time
External VIN supply ramp 6)
t
STR CC
-
500
1000
-
µs
Normal RUN mode
dVin/dt SR -
1
-
V/ms
mV
Ripple on Output Voltage
ΔVOUTTC
CC
-
33
V
EXT ≥ 2.97V ; VEXT
5.5V ; IOUTTC ≥ 10mA ;
OUTTC ≤ 60mA;
≤
I
ΔVOUTTC = (peak to
peak ripple / 2)
Load step response 7)
dVout/dIout -165
CC
-
-
-
-
-
mV
mV
mV
mV
Normal RUN mode;
dI=10 to 60mA;
dt=20ns; Tsettle=20us
-
165
-
Normal RUN mode;
dI=60 to 10mA;
dt=20ns; Tsettle=20us
-180
-
Low voltage cranking
mode; dI=10 to 50 mA;
dt=20ns; Tsettle=20us
180
Low voltage cranking
mode; dI=50 to 10mA;
dt=20ns; Tsettle=20us
Data Sheet
275
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-31 EVR33 LDO (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
dVout/dVin -
CC
Max.
Line step response
-
40
mV
mV
dVin/dT=1V/ms; dV=
3.6 to 5V; IMAX=60mA;
ΔVOUTTC is included
-40
-
-
dVin/dT=1V/ms; dV= 5
to 3.6V; IMAX=60mA;
ΔVOUTTC is included
-
-
-
280
-
mV
mV
dVin/dT=50V/ms; dV=
3.6 to 5V; IMAX=60mA
-165
dVin/dT=50V/ms; dV=
5 to 3.6V; IMAX=60mA
1) A maximum pass device dropout voltage of 300mV is included in the minimum input voltage to ensure optimal pass device
performance during normal operation.
2) VEXT Input voltage drop up to 2.97V leading to VDDP3 output voltage drop upto 2.6V can be tolerated if Flash is switched
before to low performance mode.
3) No external inductive load permissible if EVR33 is used.
4) It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100
mOhm. An additional decoupling capacitor of 100nF shall be located close to the pin before Cout.
5) IMAX is limited to 40 mA incase of Low voltage mode (cranking case) with on chip pass devices. In case EVR33 is not
used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during
power sequencing 3.3V is supplied before 5V by external regulator.
6) EVR is robust against residual voltage ramp-up starting between 0 - 2.97 V. A VEXT voltage ramp range between 0.5V/min
upto 120V/ms is covered in robustness validation. The generated voltage itself follows a soft ramp-up over the tSTR time
to avoid overshoots.
7) Settling time is defined until output voltage is within +-1% of the mean(VOUTT) of the individual device.
Table 3-32 Supply Monitors
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Primary Undervoltage Reset
threshold for VDDP3 before
trimming 1)
V
V
RST33 CC
-
-
3.00
V
by reset release before
EVR trimming on
supply ramp-up
Primary undervoltage reset
threshold for VDD before
trimming
RSTC CC
-
-
1.138
V
by reset release before
trimming on supply
ramp-up including 2
LSB voltage
Hysteresis
V
EXT primary undervoltage
VEXTPRIUV
CC
2.86
2.92
2.90
2.97
2.97
V
V
VEXT = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after
trimming 2)
VDDP3 primary undervoltage
VDDP3PRIUV 2.86 3)
VDDP3 =
monitor accuracy after
trimming
CC
Undervoltage cold
PORST Primary
Monitor Threshold
2)
Data Sheet
276
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-32 Supply Monitors (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
DD primary undervoltage
VDDPRIUV
CC
1.08 3)
1.105
1.125
V
VDD = Undervoltage
cold PORST Primary
Monitor Threshold
monitor accuracy after
trimming
2)
EVR primary monitor
measurement latency for a new
supply value
t
PRIUV CC
-
-
300
5.5
ns
The supply ramp / line
jump slope is limited to
50V/ms for VEXT, VDDP3
and VDD rails.
VEXT, VDDM & VEVRSB secondary VEXTMON CC 5.3
5.4
5.4
3.3
3.3
V
V
V
V
SWDxxVAL,
supply monitor accuracy after
trimming 4) 5)
VDDMxxVAL &
SBxxVAL monitoring
threshold=5.4V=EBh(
UV)/ECh(OV). For
BGA packages:
EVRMONFILT.SWDFI
L=1
5.3
3.2
3.2
5.5
3.4
3.4
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5.4V=EBh(
UV)/ECh(OV). For
QFP packages:
EVRMONFILT.SWDFI
L=2
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=3.3V=90h(
OV,UV). For BGA
packages:
EVRMONFILT.SWDFI
L=1.
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=3.3V=90h(
OV,UV). For QFP
packages:
EVRMONFILT.SWDFI
L=2
Data Sheet
277
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-32 Supply Monitors (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
EXT, VDDM & VEVRSB secondary VEXTMON CC 4.5
4.6
4.6
5.0
5.0
4.7
V
V
V
V
SWDxxVAL,
supply monitor accuracy after
trimming (cont’d)
VDDMxxVAL &
SBxxVAL monitoring
threshold=4.6V=C8h(
UV)/C9h(OV). For
BGA packages:
EVRMONFILT.SWDFI
L=1
4.5
4.9
4.9
4.7
5.1
5.1
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=4.6V=C8h(
UV)/C9h(OV). For
QFP packages:
EVRMONFILT.SWDFI
L=2
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5V=D9h(UV
)/DAh(OV). For BGA
packages:
EVRMONFILT.SWDFI
L=1
SWDxxVAL,
VDDMxxVAL &
SBxxVAL monitoring
threshold=5V=D9h(UV
)/DAh(OV). For QFP
packages:
EVRMONFILT.SWDFI
L=2
Data Sheet
278
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-32 Supply Monitors (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
V
DDP3 secondary supply
VDDP3MON
CC
2.97
3.035
3.30
3.565
1.15
1.25
1.35
3.1
V
V
V
V
V
V
EVR33xxVAL
monitoring
threshold=3.035V=CB
h(UV)/CCh(OV).
EVRMONFILT.EVR33
FIL = 3.
monitor accuracy after
trimming 5)
3.235
3.365
3.63
EVR33xxVAL
monitoring
threshold=3.3V=DDh(
OV,UV).
EVRMONFILT.EVR33
FIL = 3.
3.5
EVR33xxVAL
monitoring
threshold=3.565V=EE
h(UV)/EFh(OV).
EVRMONFILT.EVR33
FIL = 3.
VDD & VDDPD secondary supply VDDMON CC 1.125
1.175
1.275
1.375
EVRCxxVAL &
monitor accuracy after
trimming 5)
PRExxVAL monitoring
threshold=1.15V=C7h(
UV)/C8h(OV).
EVRMONFILT.EVRC
FIL = 1.
1.225
1.325
EVRCxxVAL &
PRExxVAL monitoring
threshold=1.25V=D9h(
OV,UV).
EVRMONFILT.EVRC
FIL = 1.
EVRCxxVAL &
PRExxVAL monitoring
threshold=1.35V=EAh
(UV)/EBh(OV).
EVRMONFILT.EVRC
FIL = 1.
V
EXT LVD Primary
VLVDRST5
CC
2.3
2.4
-
-
2.72
2.75
V
V
Power-down
Power-up
undervoltage reset Monitor
threshold
V
EVRSB LVD Primary
VLVDRSTSB
CC
2.18
2.21
-
-
2.47
2.5
V
V
Power-down
Power-up
undervoltage reset Monitor
threshold
VEXT and VEVRSB PBIST primary VPBIST5 CC 5.63
-
-
V
overvoltage Monitor threshold
Data Sheet
279
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-32 Supply Monitors (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Primary undervoltage reset
threshold for VEXT before
trimming
V
RST5 CC
-
-
3.0
V
by last cold PORST
release on supply
ramp-up including
voltage hysteresis.
EVR secondary monitor
measurement latency for all 6
supply rails
t
MON CC
-
-
3.2
µs
HPOSC and SHPBG
bandgap trimmed.
Filter inactive.
1) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold
and by a voltage hysteresis of 1.5% above the undervoltage reset limit. These mechanisms serve as hysteresis to avoid
multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is
released. The reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply
is provided externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin.
2) The monitor tolerances constitute the inherent variation of the band gap and ADC over process, voltage and temperature
operational ranges. The VxxPRIUV parameters are device individually tested in production with +-1% tolerance about the
VxxPRIUV limits. All voltages are measured on pins.
3) VRSTxx parameters are relevant only for the first cold PORST release. Later the reset levels are trimmed by the Firmware
and reflected as VxxPRIUV parameters before device is used with full performance. The cold PORST is released with a
voltage hysteresis on all the primary monitors to avoid consecutive PORST toggling behavior.
4) In case the application is using 3.3V single supply (Single Supply mode (e), i.e. VEXT and VDDP3 are shorted together),
it is recommended to use secondary supply monitoring on channel VDDP3, because of the better accuracy of parameter
VDDP3MON.
5) To monitor voltage level not provided in conditions the values for OV and UV thresholds can be generated by a linear
interpolation or extrapolation based on the given points.
Table 3-33 Supply Ramp
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
External VEXT & VEVRSB supply dVEXT/dt 8.3E-6
1
100
V/ms
ramp-up and ramp-down slope SR
1) 2) 3)
External VDDP3 supply ramp-up dVDDP3/dt 8.3E-6
1
1
1
100
100
100
V/ms
V/ms
V/ms
and ramp-down slope 1)3)
SR
External VDD supply ramp-up
dVDD/dt
SR
8.3E-6
and ramp-down slope 1)3)
External VDDM supply ramp-up dVDDM/dt 8.3E-6
and ramp-down slope 1)3)
SR
1) The device is robust against residual voltage ramp-up starting between 0 - 2.97 V for VEXT, VEVRSB, VDDP3 and VDDM
and 0-1 V for VDD. A voltage ramp range between 0.5V/min upto 120V/ms is covered in robustness validation.
2) Also valid in case EVR33 or EVRC is used. The generated voltage itself follows a soft ramp-up over the tSTR time to avoid
overshoots.
3) The slope is defined as the maximal tangential slope between 0% to 100% voltage level. Actual waveform may not
represent the specification.
•
Up to 1000000 power-cycles, matching the limits defined in the table ’Supply Ramp’ are allowed for TC37x
without any restriction to reliability.
Data Sheet
280
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-34 EVRC SMPS
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input VEXT Voltage range
VIN SR
2.97
-
5.5
V
V
Start-up VEXT voltage
> 2.6 V
SMPS regulator output voltage VDDDC CC
range including load/line
regulation and aging
1.125
-
1.375
1.275
2.0
V
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 1mA ;
DDDC ≤ 1.5A ;
untrimmed
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 1mA ;
DDDC ≤ 1.5A
≤
I
SMPS regulator static voltage
output accuracy after trimming
without dynamic load/line
regulation.
V
DDDCT CC 1.225
1.25
1.82
V
V
≤
I
Programmable switching
frequency
f
DCDC SR
1.6
MHz
Start-up frequency
switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation.
-
0.8
-
MHz
Start-up frequency
switches from 500 KHz
in open loop operation
to 1.82 MHz in closed
loop Operation. 0.8
MHz to be set in SW.
Startup time
t
STRDC CC
-
-
900
µs
SMPS Start-up Mode.
It is is defined beween
V
EXTPRIUV reset
threshold till PORST
release, on condition
that all other PORST
requirements were
released before. ISTART
< 700mA.
Switching frequency
modulation spread
ΔfDCSPR CC -
ΔVDDDC CC -
1.8%
-
-
MHz
mV
Maximum ripple at IMAX
16
V
EXT ≥ 2.97V ; VEXT
5.5V ; IDDDC ≥ 300mA ;
DDDC ≤ 1.5A ; ΔVDDDC
≤
I
= (Peak to Peak ripple
/ 2)
No load current consumption of IDCNL CC
SMPS regulator
-
-
15
5
19
-
mA
mA
f
I
DCDC=1.82MHz;
DDDC=ISLEEP; VEXT
>
>
2.97 V; TJ=25°C
LPM mode;
I
DDDC=ISLEEP; VEXT
2.97 V; TJ=25°C
Data Sheet
281
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-34 EVRC SMPS (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
SMPS regulator load transient dVDDDCT
/
-50
-
-
-
-
75
mV
mV
mV
mV
dI < -250mA ;
response
dlOUT CC
I
DDDC=280-1500mA;
tr=0.1us; tf=0.1us;
DDDC=1.25V;
settle=100 us
dI < -450mA ;
DDDC=500-1500mA;
tr=0.1us; tf=0.1us;
DDDC=1.25V;
settle=100 us
dI < -700mA ;
DDDC=750-1500mA;
tr=0.1us; tf=0.1us;
DDDC=1.25V;
settle=100 us
dI < 100mA ;
DDDC=50-1500mA;
tr=0.1us; tf=0.1us;
DDDC=1.25V;
settle=20us;
V
T
-50
87
I
V
T
-100
-26
145
26
I
V
T
I
V
T
Maximum output current
I
MAX CC
100
1.5
-75
-12.5
-
-
-
mA
A
LPM mode. Typical
current in LPM Mode =
ISLEEP
-
-
limited by thermal
constraints and
component choice
SMPS regulator line transient dVDDDCT
response
/
-
75
12.5
-
mV
mV
%
dV/dT=120V/ms; dV <
2.97 - 5.5V ; IDDDC=50-
1500mA;
dVIN CC
-
dV/dT=1V/ms; dV <
2.97 - 5.5V ; IDDDC=50-
1500mA;
SMPS regulator efficiency
n
DC CC
80
75
1.82
VIN=3.3V;
I
DDDC=1500mA;
DCDC=1.82MHz
VIN=5V;
DDDC=1500mA;
DCDC=1.82MHz
f
-
-
%
I
f
Input Synchronisation
frequency
fDCDCSYNC
SR
1.6
2.0
MHz
Data Sheet
282
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OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification PMS
Table 3-35 EVRC SMPS External components
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
External output capacitor value COUT SR
20.8
32
43.2
µF
I
DDDC=1.5A; fDDDC
0.8MHz
DDDC=1.5A; fDDDC
1.82MHz
mOhm f≥0.5MHz ; f≤10MHz
=
1)
15.4
22
29.7
µF
I
=
External output capacitor ESR COUT_ESR
-
-
50
SR
-
-
100
13.5
9.18
50
Ohm
µF
f=10Hz
External input capacitor value 1) CIN SR
6.5
4.42
-
10
6.8
-
I
I
DDDC=1.5A
µF
DDDC=500mA
External input capacitor ESR
External inductor value
External inductor DCR
CIN_ESR SR
mOhm f≥0.5MHz ; f≤10MHz
-
-
100
6.11
4.29
0.2
Ohm
f=100Hz
L
DC SR
3.29
2.31
4.7
3.3
-
f
f
DCDC=0.8MHz
DCDC=1.82MHz
µH
Ohm
V
L
DC_DCR SR -
LL SR
P + N-channel MOSFET logic
level
V
-
-
2.5
P + N-channel MOSFET drain |VBR_DS| SR +7
-
-
V
V
NMOS - VGS = 0.
PMOS - VGS = 0.
source breakdown voltage
-
-
-7
-
P + N-channel MOSFET drain RON SR
source ON-state resistance
-
-
-
150
mOhm IDDDC=1.5A;
|VGS|=2.5V ; TA=25°C
mOhm IDDDC=500mA;
|VGS|=2.5V ; TA=25°C
DDDC=1.5A; NMOS-
200
-
-
P + N-channel MOSFET Gate QG SR
8
nC
nC
nC
nC
mA
I
Charge
|VGS|=5V; 1.5A pulsed
drain current
-8
-
-
-
-
-
-
IDDDC=1.5A; PMOS-
|VGS|=5V; 1.5A pulsed
drain current
4
-
IDDDC=500mA; NMOS-
|VGS|=5V; 0.5A pulsed
drain current
-4
400
IDDDC=500mA; PMOS-
|VGS|=5V; 0.5A pulsed
drain current
External Inductor Saturation
Current Margin
ΔISAT SR
-
The saturation current
of the coil must be
larger than IDDDC
ΔISAT
+
Data Sheet
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TC37x AA-Step
Electrical Specification PMS
Table 3-35 EVRC SMPS External components (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
P + N-channel MOSFET Gate
threshold voltage
V
V
GSTH SR
-
-
-
1
-
-
-
V
V
V
NMOS
PMOS
-1
0.8
N-channel MOSFET reverse
diode forward voltage
RDN SR
1) Capacitor min-max range represent typical +-35% tolerance including DC bias effect. The trace resistance from the
capacitor to the supply or ground rail should be limited to 25 mOhm.
Data Sheet
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TC37x AA-Step
Electrical Specification System Phase Locked Loop (SYS_PLL)
3.16
System Phase Locked Loop (SYS_PLL)
Table 3-36 PLL System
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
10
Max.
40
DCO Input frequency range
Modulation Amplitude
Peak Period jitter
f
REF CC
-
-
-
MHz
%
MA CC
DP CC
0
2
-200
200
ps
without modulation
(PLL output frequency)
Peak Accumulated Jitter
Total long term jitter
D
PP CC
-5
-
-
-
5
ns
ns
without modulation
JTOT CC
11.5
including modulation;
MA 1.25%; fREF 20MHz
System frequency deviation
DCO frequency range
PLL lock-in time
f
f
SYSD CC
DCO CC
-
-
-
-
0.01
800
100
%
with active modulation
400
4
MHz
µs
tL CC
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
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TC37x AA-Step
Electrical Specification Peripheral Phase Locked Loop (PER_PLL)
3.17
Peripheral Phase Locked Loop (PER_PLL)
Table 3-37 PLL Peripheral
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Peak Accumulated jitter at
SYSCLK pin
DPP CC
-1000
-
1000
ps
Peak only
Peak accumulated jitter
RMS Accumulated jitter
D
PPI CC
-700
-100
-
-
700
100
ps
ps
Peak only
DRMS CC
measured over 1 µs;
f
REF = 20 MHz and fDCO
= 640 MHz or fREF = 25
MHz and fDCO = 800
MHz
Peak Period jitter
DP CC
-200
-125
-85
-
-
-
-
200
125
85
ps
ps
ps
ps
f
DCO = 640 MHz or fDCO
= 800 MHz
REF = 10 MHz; fDCO
640 MHz
REF = 20 MHz; fDCO
640 MHz
REF = 25 MHz; fDCO
800 MHz
Absolute RMS jitter (PLL out)
Absolute RMS jitter (PLL out)
Absolute RMS jitter (PLL out)
JABS10 CC
JABS20 CC
JABS25 CC
f
=
=
=
f
-85
85
f
DCO frequency range
DCO input frequency range
PLL lock-in time
f
f
DCO CC
REF CC
400
10
4
-
-
-
800
40
MHz
MHz
µs
tL CC
100
Note:The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note:The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
V
PP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the
supply pins and using PCB supply and ground planes.
Data Sheet
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TC37x AA-Step
Electrical Specification AC Specifications
3.18
AC Specifications
All AC parameters are specified for the complete operating range defined in Chapter 3.4 unless otherwise noted
in column Note / Test Condition.
Unless otherwise noted in the figures the timings are defined with the following guidelines:
VEXT/FLEX / VDDP3
90%
90%
10%
10%
VSS
tr
tf
rise_fall
Figure 3-8 Definition of rise / fall times
VEXT/FLEX/ VDDP3
Timing
Reference
Points
VEXT/FLEX /VDDP3
VEXT /FLEX / VDDP3
2
2
VSS
timing_reference
Figure 3-9 Time Reference Point Definition
Data Sheet
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TC37x AA-Step
Electrical Specification JTAG Parameters
3.19
JTAG Parameters
The following parameters are applicable for communication through the JTAG debug interface. The JTAG module
is fully compliant with IEEE1149.1-2000.
Table 3-38 JTAG
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
10
10
-
Max.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
TCK low time
-
TCK clock rise time
TCK clock fall time
4
4
-
-
TDI/TMS setup to TCK rising
edge
6.0
TDI/TMS hold after TCK rising t7 SR
6.0
-
-
ns
edge
TDO valid after TCK falling
edge (propagation delay)
t8 CC
3.0
-
-
-
-
-
ns
ns
ns
CL≤20pF
CL≤50pF
25
-
TDO hold after TCK falling
edge
t
18 CC
2
TDO high impedance to valid t9 CC
from TCK falling edge
-
-
-
-
25
25
ns
ns
CL≤50pF
CL≤50pF
TDO valid output to high
impedance from TCK falling
edge
t10 CC
t1
0.9 VEXT
0.1 VEXT
0.5 VEXT
t5
t4
t2
t3
MC_JTAG_TCK
Figure 3-10 Test Clock Timing (TCK)
Data Sheet
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TC37x AA-Step
Electrical Specification JTAG Parameters
TCK
TMS
TDI
t6
t7
t6
t7
t9
t8
t10
TDO
t18
MC_JTAG
Figure 3-11 JTAG Timing
Data Sheet
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TC37x AA-Step
Electrical Specification DAP Parameters
3.20
DAP Parameters
The following parameters are applicable for communication through the DAP debug interface.
Table 3-39 DAP
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
DAP0 clock rise time
t
t
t
14 SR
15 SR
16 SR
-
-
-
-
-
-
-
-
-
-
1
4
2
1
4
2
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
f=160MHz
f=40MHz
f=80MHz
f=160MHz
f=40MHz
f=80MHz
-
-
DAP0 clock fall time
-
-
-
DAP1 setup to DAP0 rising
edge
4
5
2
-
f=40MHz
DAP1 hold after DAP0 rising
edge
t
t
17 SR
19 CC
-
DAP1 valid per DAP0 clock
period
4
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=20pF ; f=160MHz
CL=20pF ; f=80MHz
CL=50pF ; f=40MHz
8
10
2
DAP0 high time
DAP0 low time
t
t
t
12 SR
13 SR
11 SR
2
DAP0 clock period
6.25
Table 3-40 SCR DAP
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
DAP0 clock rise time
DAP0 clock fall time
t
t
t
14 SR
15 SR
16 SR
-
-
-
-
8
8
-
ns
ns
ns
f=20MHz
f=20MHz
-
DAP1 setup to DAP0 rising
edge
10
DAP1 hold after DAP0 rising
edge
t
t
17 SR
19 CC
10
30
-
-
-
-
ns
ns
DAP1 valid per DAP0 clock
period
CL=20pF ; f=20MHz
DAP0 high time
DAP0 low time
t
t
t
12 SR
13 SR
11 SR
15
15
50
-
-
-
-
-
-
ns
ns
ns
DAP0 clock period
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TC37x AA-Step
Electrical Specification DAP Parameters
t11
t15
t14
t13
t12
0.9 VEXT
0.1 VEXT
0.5 VEXT
DAP0
t16
t17
DAP1
(Host to Device)
t11
DAP11),2)
(Device to Host)
t19
1) The DAP1 and DAP2 device to host timing is individual for both pins.
There is no guaranteed max. signal skew.
2) No explicite setup and hold times are given for DAP1 for the direction Device to Host.
Only t11 and t19 are guaranteed and the tool may set the sample point freely.
Figure 3-12 DAP Timing
Note:The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.
Data Sheet
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TC37x AA-Step
Electrical Specification ASCLIN SPI Master Timing
3.21
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC37x.
Note:Pad asymmetry is already included in the following timings.
Table 3-41 Master Mode strong sharp (ss) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20
Max.
ASCLKO clock period
t
50 CC
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
Deviation from ideal duty cycle t500 CC
-2
2
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-3.5
3.5
ASLSOn delay from the first
ASCLKO edge
-3
25
-2
-
-
-
3.5
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
MRST setup to ASCLKO
latching edge
-
-
MRST hold from ASCLKO
latching edge
Table 3-42 Master Mode strong medium (sm) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
ASCLKO clock period
t
50 CC
-
-
-
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
-5
5
7
MTSR delay from ASCLKO
shifting edge
t
t
t
t
51 CC
510 CC
52 SR
53 SR
-7
ASLSOn delay from the first
ASCLKO edge
-7
35
-5
-
-
-
7
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
MRST setup to ASCLKO
latching edge
MRST hold from ASCLKO
latching edge
-
Table 3-43 Master Mode medium (m) output pads
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
160
-10
Typ.
Max.
-
ASCLKO clock period
t
50 CC
-
-
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle t500 CC
10
20
MTSR delay from ASCLKO
shifting edge
t
51 CC
-20
ASLSOn delay from the first
ASCLKO edge
t
510 CC
-20
-
20
ns
CL=50pF
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Electrical Specification ASCLIN SPI Master Timing
Table 3-43 Master Mode medium (m) output pads (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
MRST setup to ASCLKO
latching edge
t
t
52 SR
53 SR
80
-
-
ns
ns
CL=50pF
CL=50pF
MRST hold from ASCLKO
latching edge
-15
-
-
t50
ASCLKO
MTSR
t51
t51
t500
t52
t53
MRST
Data valid
Data valid
t510
ASLSO
ASCLIN_TmgMM.vsd
Figure 3-13 ASCLIN SPI Master Timing
Data Sheet
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TC37x AA-Step
Electrical Specification QSPI Timings, Master and Slave Mode
3.22
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC37x.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
Note:Pad asymmetry is already included in the following timings.
Table 3-44 Master Mode Timing, LVDS output pads for data and clock
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
20 1)
-1 1)
Max.
-
1 1)
SCLKO clock period
t
t
50 CC
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle
500 CC
MTSR delay from SCLKO
shifting edge
t
51 CC
-3 1)
-
-
-
-
-
4 1)
ns
ns
ns
ns
ns
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-4 1)
5.5 1)
10 1)
30 1)
-
CL=25pF, driver
strength ss
-10 1)
-30 1)
18 1)
CL=25pF, driver
strength sm
CL=25pF, driver
strength m
MRST setup to SCLK latching
edge
t
52 SR
CL=25pF; valid for
LVDS Input pads of
QSPI2 only
19.5 1)
-
-
-
-
ns
ns
CL=25pF; valid for
LVDS Input pads of
QSPI4 only
MRST hold from SCLK latching t53 SR
-1 1)
CL=25pF; valid for
edge
LVDS Input pads only
1) The load (CL=25pF) defined in the condition list is a load definition for the single end signal SLSO and does not intend to
add an additional load inside the differential signal lines. For single end signals the load definition defines the max length
of the signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-45 Master Mode Strong Sharp (ss) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period
t
t
50 CC
-
-
-
ns
ns
CL=25pF
CL=25pF
Deviation from the ideal duty
cycle
500 CC
-2
2
MTSR delay from SCLKO
shifting edge
t
51 CC
-4
-
-
-
-
5
5
-
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
SLSOn deviation from the ideal t510 CC
programmed position
-4
MRST setup to SCLK latching
edge
t
52 SR
25 1) 2)
-2 1)2)
MRST hold from SCLK latching t53 SR
-
edge
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TC37x AA-Step
Electrical Specification QSPI Timings, Master and Slave Mode
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-46 Master Mode Strong Medium (sm) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
50
Max.
SCLKO clock period
t
t
50 CC
-
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle
500 CC
-5
5
MTSR delay from SCLKO
shifting edge
t
51 CC
-7
-
-
-
-
7
7
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-7
MRST setup to SCLK latching
edge
t
52 SR
35 1) 2)
-5 1)2)
MRST hold from SCLK latching t53 SR
-
edge
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-47 Master Mode Medium (m) output pads
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
160
-10
Max.
-
SCLKO clock period
t
t
50 CC
-
-
ns
ns
CL=50pF
CL=50pF
Deviation from the ideal duty
cycle
500 CC
10
MTSR delay from SCLKO
shifting edge
t
51 CC
-20
-
-
-
20
20
-
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
SLSOn deviation from the ideal t510 CC
programmed position
-20
MRST setup to SCLK latching
edge
t
52 SR
80 1) 2)
MRST hold from SCLK latching t53 SR
edge
-15 1)2)
-13 1)2)
-
-
-
-
ns
ns
CL=50pF
CL=50pF; SCR SSC
1) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
2) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-48 Slave mode timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
-
SCLK clock period
SCLK duty cycle
t
t
54 SR
4 x TMAX
40
-
-
ns
%
55/t54 SR
60
Data Sheet
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TC37x AA-Step
Electrical Specification QSPI Timings, Master and Slave Mode
Table 3-48 Slave mode timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
6
Max.
MTSR setup to SCLK latching
edge
t
56 SR
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
Input Level AL
Input Level TTL
6
-
MTSR hold from SCLK latching t57 SR
edge
4
-
6
-
SLSI setup to first SCLK shift
edge
t
t
t
58 SR
59 SR
60 CC
4
-
6
-
SLSI hold from last SCLK
latching edge
3
-
6
-
MRST delay from SCLK shift
edge
5
35
driver = strong edge =
medium ; CL=50pF
2
-
-
-
24
80
-
ns
ns
ns
driver = strong edge =
sharp ; CL=50pF
15
14
medium driver ;
CL=50pF
medium driver ;
CL=50pF; SCR SSC
t50
t500
0.5 VEXT/FLEX
SCLK1)2)
MTSR1)
t51
SAMPLING POINT
0.5 VEXT/FLEX
t52
t53
MRST1)
Data valid
Data valid
t510
SLSOn2)
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-14 Master Mode Timing
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Electrical Specification QSPI Timings, Master and Slave Mode
t54
Last latching
SCLK edge
First latching
SCLK edge
SCLKI1)
First shift
SCLK edge
0.5 VEXT/FLEX
t55
t55
t56
t56
t57
t57
Data
valid
Data
valid
MTSR1)
MRST1)
SLSI
t60
t60
0.5 VEXT/FLEX
t58
t59
t61
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0.
QSPI_TmgSM.vsd
Figure 3-15 Slave Mode Timing
Data Sheet
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TC37x AA-Step
Electrical Specification MSC Timing 5 V Operation
3.23
MSC Timing 5 V Operation
The following section defines the timings.
Note:Pad asymmetry is already included in the following timings.
Note:Load for LVDS pads are defined as differential loads in the following timings.
Table 3-49 LVDS clock/data (LVDS pads in LVDS mode) valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
1) 2)
FCLPx clock period
t
40 CC
2 * TA
-
-
ns
LVDS; CL=50pF
3)
Deviation from ideal duty cycle t400 CC
-1 3)
-3 3)
-4 3)
-
-
-
1 3)
3 3)
5 3)
ns
ns
ns
LVDS; 0 < CL < 50pF
SOPx output delay
ENx output delay
t
t
44 CC
45 CC
CL=50pF
ss; CL=50pF; ABRA
block bypassed
-4 3)
-
4 3)
ns
ss; CL=50pF; ABRA
block used
-2 3)
-30 3)
-
-
10 3)
30 3)
ns
ns
sm; CL=50pF
m; CL=50pF
1) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
3) The load (CL=50pF) defined in the condition list is a load definition for the single end signal EN and does not intend to add
an additional load inside the differential signal lines. For single end signals the load definition defines the max length of the
signal on the PCB layout. For the LVDS pads the IEEE Std 1596.3-1996 load definitions apply.
Table 3-50 Strong sharp (ss) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-2
Max.
-
FCLPx clock period
t
40 CC
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle t400 CC
2
SOPx output delay
ENx output delay
t
t
44 CC
45 CC
-4
3.5
3.5
-4
Table 3-51 Strong medium (sm) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-5
Max.
FCLPx clock period
t
40 CC
-
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle t400 CC
5
7
7
SOPx output delay
ENx output delay
t
t
44 CC
45 CC
-7
-7
Data Sheet
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TC37x AA-Step
Electrical Specification MSC Timing 5 V Operation
Table 3-52 Medium (m) driver for clock/data valid for 5V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
2 * TA
-10
Max.
-
FCLPx clock period
t
40 CC
-
-
-
-
ns
ns
ns
ns
CL=50pF
CL=50pF
CL=50pF
CL=50pF
Deviation from ideal duty cycle t400 CC
10
20
20
SOPx output delay
ENx output delay
t
t
44 CC
45 CC
-20
-20
Table 3-53 Upstream Interface
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
-
SDI bit time
SDI rise time
SDI fall time
t
t
t
46 SR
48 SR
49 SR
8 * tMSC
-
-
-
ns
ns
ns
-
-
200
200
t40
t400
FCLP
SOP
t44
t44
t45
t45
0.5 VEXT/FLEX
EN
t48
t49
0.9 VEXT/FLEX
0.1 VEXT/FLEX
SDI
t46
t46
MSC_Timing_A.vsd
Figure 3-16 MSC Interface Timing
Note:The SOP data signal is sampled with the falling edge of FCLP in the target device.
Data Sheet
299
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TC37x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24
Ethernet Interface (ETH) Characteristics
3.24.1
ETH Measurement Reference Points
ETH Clock
ETH I/O
1.4
2.0
V
1.4 V
V
2.0
V
0.8
V
0.8
V
tR
tF
ETH_Testpoints.vsd
Figure 3-17 ETH Measurement Reference Points
Data Sheet
300
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TC37x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.2
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 3-54 ETH Management Signal Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
400
160
160
10
Max.
ETH_MDC period
ETH_MDC high time
ETH_MDC low time
t1 CC
t2 CC
t3 CC
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
CL=25pF
-
-
ETH_MDIO setup time (output) t4 CC
ETH_MDIO hold time (output) t5 CC
ETH_MDIO data valid (input) t6 SR
-
10
-
0
300
t1
t3
t2
ETH_MDC
ETH_MDIO
sourced by controller :
ETH_MDC
t4
t5
ETH_MDIO
(output )
Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input )
Valid Data
ETH_Timing-Mgmt.vsd
Figure 3-18 ETH Management Signal Timing
Data Sheet
301
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TC37x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.3
ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.
Table 3-55 ETH MII Signal Timing Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Clock period
t7 SR
-
40
-
ns
ns
ns
ns
ns
ns
CL=25pF ;
baudrate=100Mbps
-
400
-
CL=25pF ;
baudrate=10Mbps
Clock high time
Clock low time
t8 SR
t9 SR
14
-
-
-
-
26
CL=25pF ;
baudrate=100Mbps
140 1)
14
260 2)
26
CL=25pF ;
baudrate=10Mbps
CL=25pF ;
baudrate=100Mbps
140 1)
260 2)
CL=25pF ;
baudrate=10Mbps
Input setup time
Input hold time
t
t
t
10 SR
11 SR
12 CC
10
10
0
-
-
-
-
ns
ns
ns
CL=25pF
CL=25pF
CL=25pF
-
Output valid time
25
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
t7
t9
t8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
ETH_MII_RX_CLK
t10
t11
ETH_MII_RXD[3:0]
ETH_MII_RX_DV
ETH_MII_RX_ER
(sourced by PHY )
Valid Data
ETH_MII_TX_CLK
t12
ETH_MII_TXD[3:0]
ETH_MII_TXEN
Valid Data
(sourced by controller )
ETH_Timing-MII.vsd
Figure 3-19 ETH MII Signal Timing
Data Sheet
302
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TC37x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.4
ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.
Table 3-56 ETH RMII Signal Timing Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
ETH_RMII_REF_CL clock
period
t
13 SR
-
20
-
ns
ns
ns
ns
50ppm ; CL=25pF
CL=25pF
ETH_RMII_REF_CL clock high t14 SR
time
7 1)
7 1)
4
-
13 2)
13 2)
-
ETH_RMII_REF_CL clock low t15 SR
time
-
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV;
setup time 3)
t
t
16 CC
17 CC
-
CL=25pF
ETHTXEN, ETHTXD[1:0],
ETHRXD[1:0], ETHCRSDV;
hold time 3)
2
-
-
ns
CL=25pF
1) Defined by 35% of clock period.
2) Defined by 65% of clock period.
3) For ETHRXD and ETHCRSDV signals this parameter is a SR.
t13
t15
t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t16
t17
ETHTXEN,
ETHTXD[1:0],
ETHRXD[1:0],
ETHCRSDV,
ETHRXER
Valid Data
ETH_Timing-RMII.vsd
Figure 3-20 ETH RMII Signal Timing
Data Sheet
303
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TC37x AA-Step
Electrical Specification Ethernet Interface (ETH) Characteristics
3.24.5
ETH RGMII Parameters
In the following, the parameters of the RGMII are described.
Table 3-57 ETH RGMII Signal Timing Parameters valid for 3.3V
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
36
Max.
44
TX Clock period
t
19 CC
40
400
8
ns
ns
ns
ps
ns
100Mbps
10Mbps
Gigabit
360
7.2
-500
1
440
8.8
Data to Clock Output skew
t
t
20 CC
21 SR
0
500
2.6
Data to Clock input skew (at
receiver)
1.8
Clock duty cycle
t
duty CC
40
50
50
-
60
%
%
%
%
10/100Mbps
Gigabit
45
55
GREFCLK duty cycle
t
duty_in SR
45
55
GREFCLK Input accuracy
ACC SR
-0.005
-
0.005
Figure 3-21 ETH RGMII TX Signal Timing (Delay on Destination (DoD))
Figure 3-22 ETH RGMII RX Signal Timing (Delay on Source (DoS))
Data Sheet
304
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TC37x AA-Step
Electrical Specification E-Ray Parameters
3.25
E-Ray Parameters
The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL =
25 pF.
Table 3-58 Transmit Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Rise time of TxEN
Fall time of TxEN
tdCCTxENRise2
5 CC
-
-
-
-
9
ns
ns
ns
CL=25pF
tdCCTxENFall25
CC
-
-
9
9
CL=25pF
Sum of rise and fall time
tdCCTxRise25+
20% - 80% ; CL=25pF
dCCTxFall25
CC
Sum of delay between TP1_FF tdCCTxEN01
-
-
-
-
25
25
ns
ns
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxEN
CC
Sum of delay between TP1_FF tdCCTxEN10
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxEN
CC
Asymmetry of sending
t
tx_asym CC -2.45
-
-
2.45
25
ns
ns
CL=25pF
Sum of delay between TP1_FF tdCCTxD01
-
-
-
and TP1_CC and delays
derived from TP1_FFi, rising
edge of TxD
CC
Sum of delay between TP1_FF tdCCTxD10
-
-
25
9
ns
ns
and TP1_CC and delays
derived from TP1_FFi, falling
edge of TxD
CC
TxD signal sum of rise and fall ttxd_sum CC
time at TP1_BD
Table 3-59 Receive Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -30.5
ept25 SR
-
43.0
ns
ns
%
%
CL=25pF
CL=15pF
Acceptance of asymmetry at
receiving part
tdCCTxAsymAcc -31.5
ept15 SR
-
-
-
44.0
70
Threshold for detecting logical TuCCLogic1
high SR
Threshold for detecting logical TuCCLogic0
35
30
65
low
SR
Data Sheet
305
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TC37x AA-Step
Electrical Specification E-Ray Parameters
Table 3-59 Receive Parameters (cont’d)
Parameter Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Sum of delay between TP4_CC tdCCRxD01
-
-
10
ns
and TP4_FF and delays
derived from TP4_FFi, rising
edge of RxD
CC
Sum of delay between TP4_CC tdCCRxD10
-
-
10
ns
and TP4_FF and delays
derived from TP4_FFi, falling
edge of RxD
CC
Data Sheet
306
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TC37x AA-Step
Electrical Specification HSCT Parameters
3.26
HSCT Parameters
Table 3-60 HSCT - Rx parasitics and loads
Parameter
Symbol
Values
Typ.
3.5
Unit
Note / Test Condition
Min.
Max.
Capacitance total budget
Ctotal CC
-
5
pF
Total Budget for
complete receiver
including silicon,
package, pins and
bond wire
Parasitic inductance budget
Htotal CC
-
5
-
nH
Table 3-61 HSCT - Rx/Tx setup timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
60
RX o/p duty cycle
DCrx CC
40
-
-
-
-
-
%
Disable time of the LVDS pad
Enable time of the LVDS pad
t
t
LVDSDIS CC -
20
ns
ns
ns
ns
LVDSEN CC
-
-
-
400
250
0.2
Wakeup time from Sleep Mode tSWU CC
Maximum length of a wake-up tWUP CC
glitch that does not wake-up
the receiver
Bias startup time
t
bias CC
-
5
10
µs
Bias distributor waking
up from power down
and provide stable
Bias.
RX startup time
TX startup time
trxi CC
ttx CC
-
-
-
-
600
280
ns
ns
Wake-up RX from
power down.
Wake-up TX from
power down.
Data Sheet
307
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TC37x AA-Step
Electrical Specification Inter-IC (I2C) Interface Timing
3.27
Inter-IC (I2C) Interface Timing
This section defines the timings for I2C in the TC37x.
All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-62 I2C Standard Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
-
-
300
ns
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
4.7
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
-
-
-
-
-
-
-
1000
ns
µs
ns
µs
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data hold time
t3
t4
t5
t6
t7
0
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
250
4.7
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Hold time for the (repeated)
START condition
4
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
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TC37x AA-Step
Electrical Specification Inter-IC (I2C) Interface Timing
Table 3-62 I2C Standard Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Set-up time for (repeated)
START condition
t8
4.7
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
4
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Table 3-63 I2C Fast Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
20+0.1*C -
300
ns
Measured with a pull-
up resistor of 4.7
b
kohms at each of the
SCL and SDA line
Capacitive load for each bus
line
Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
1.3
Measured with a pull-
up resistor of 4.7
and ATART condition
kohms at each of the
SCL and SDA line
Rise time of both SDA and SCL t2
20+0.1*C -
300
ns
µs
ns
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
b
Data hold time
t3
t4
t5
t6
0
-
-
-
-
-
-
-
-
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data set-up time
100
1.3
0.6
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Data Sheet
309
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TC37x AA-Step
Electrical Specification Inter-IC (I2C) Interface Timing
Table 3-63 I2C Fast Mode Timing (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Hold time for the (repeated)
START condition
t7
0.6
-
-
-
-
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for (repeated)
START condition
t8
0.6
0.6
-
-
µs
µs
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7
kohms at each of the
SCL and SDA line
Table 3-64 I2C High Speed Mode Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Capacitive load for each bus
line
Cb SR
-
-
400
pF
Fall time of SCL
t11
t12
t13
t14
t3
10 1)
10 1)
10 1)
10 1)
0 1)
10 1)
160 1)
60 1)
160 1)
-
-
-
-
-
-
-
-
-
40 1)
80 1)
40 1)
80 1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
bus line load of 100pF
Fall time of SDA
Rise time of SCL
Rise time of SDA
Data hold time
70 1)
Data set-up time
t4
-
-
-
-
Low period of SCL clock
High period of SCL clock
t5
t6
Hold time for the (repeated)
START condition
t7
Set-up time for (repeated)
START condition
t8
160 1)
-
-
-
-
ns
ns
bus line load of 100pF
bus line load of 100pF
Set-up time for STOP condition t9
160 1)
1) Values are defined for Cb = 100pF, for the Timing of Cb = 400pF see the I2C Standard.
Data Sheet
310
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TC37x AA-Step
Electrical Specification Inter-IC (I2C) Interface Timing
t1
t2
t4
70%
30%
SDA
SCL
t1
t3
t2
t6
9th
clock
t7
t5
t10
S
SDA
SCL
t8
t7
t9
9th
clock
Sr
P
S
Figure 3-23 I2C Standard and Fast Mode Timing
Data Sheet
311
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TC37x AA-Step
Electrical Specification Flash Target Parameters
3.28
Flash Target Parameters
Table 3-65 Flash
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program Flash Erase Time per tERP CC
-
-
0.5
s
s
cycle count < 1000
logical sector 1)
Program Flash Erase Time per tMERP CC
-
-
0.5
Forconsecutivelogical
sectors in a physical
sector with total range
≤ 512 kByte; cycle
count < 1000
Multi-Sector Command 1)
Program Flash program time
per page in 5 V mode 1)
t
t
t
t
PRP5 CC
PRP3 CC
PRPB5 CC
PRPB3 CC
-
-
-
-
-
-
-
-
-
-
80
µs
µs
µs
µs
s
32 Byte
32 Byte
256 Byte
256 Byte
Program Flash program time
per page in 3.3 V mode 1)
115
220
530
2.2
Program Flash program time
per burst in 5 V mode 1)
Program Flash program time
per burst in 3.3 V mode 1)
Program Flash program time
for 1 MByte with burst
programming in 3.3 V mode
excluding communication 1)
tPRPB3_1MB
CC
Derived value for
documentation
purpose
Program Flash program time
for 1 MByte with burst
programming in 5 V mode
excluding communication 1)
tPRPB5_1MB
CC
-
-
-
-
1
6
s
s
Derived value for
documentation
purpose
Program Flash program time
for complete PFlash with burst CC
programming in 5 V mode
excluding communication 1)
tPRPB5_PF
Derived value for
documentation
purpose
Write Page Once adder 1)
t
ADD CC
-
-
-
-
20
µs
µs
Adder to Program
Time when using Write
Page Once
Program Flash suspend to read tSPNDP CC
120
For Write Burst, Verify
Erased and for multi-
(logical) sector erase
commands
latency 1)
Data Flash Erase Disturb Limit NDFD CC
(single ended sensing mode)
-
-
-
-
-
-
50
cycles
cycles
cycles
Data Flash Erase Disturb Limit NDFDC CC
(complement sensing mode)
500
500
UCB Erase Disturb Limit
Data Sheet
NUCBD CC
312
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TC37x AA-Step
Electrical Specification Flash Target Parameters
Table 3-65 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Program time data flash per
page 1)2)
t
t
PRD CC
-
-
75
µs
s
8 Byte
Complete Device Flash Erase
ER_Dev CC
-
4.3
7
Valid for less than
1000 cycles, w/o UCB.
Derived value for
documentation
purpose.
Time PFlash and DFlash 1)3) 4)
5)
Data Flash program time per
burst 1)2)
t
t
PRDB CC
-
-
-
-
-
-
-
-
140
120
2
µs
µs
µs
32 Byte
Data Flash suspend to read
latency 1)
SPNDD CC
Wait time after margin change tFL_MarginDel
CC
Program Flash Endurance per NE_P CC
Logical Sector
1000
cycles Replace logical sector
command shall be
used if a sector fails
during erase or
program
Number of erase operations
per physical sector in program
flash
NERP CC
-
-
16000
cycles
Program Flash Retention Time, tRET CC
Sector
20
20
-
-
-
-
years Max. 1000
erase/program cycles
UCB Retention Time
t
RTU CC
years Max. 100
erase/program cycles
per UCB, max 500
erase/program cycles
for all UCBs together
Data Flash access delay
Data Flash ECC Delay
t
t
t
t
DF CC
-
-
-
-
-
-
-
-
100
20
ns
ns
ns
ns
see RFLASH of DMU
register HF_DWAIT
DFECC CC
PF CC
see RECC of DMU
register HF_DWAIT
Program Flash access delay
Program Flash ECC delay
30
see RFLASH of DMU
register HF_PWAIT
PFECC CC
10
see RECC and CECC
of DMU register
HF_PWAIT
Number of erase operations on NERD0C CC
DF0 over lifetime (complement
sensing mode) 6)
-
-
-
-
4000000 cycles
Number of erase operations on NERD0S CC
DF0 over lifetime (single ended
sensing mode) 7)
750000
cycles
Data Sheet
313
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Flash Target Parameters
Table 3-65 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
2000000 cycles
Number of erase operations on NERD1C CC
DF1 over lifetime (complement
sensing mode) 6)
-
-
-
-
-
Number of erase operations on NERD1S CC
DF1 over lifetime (single ended
sensing mode) 7)
-
-
-
500000
500000
125000
cycles
Data Flash Endurance per
EEPROMxsector(complement CC
sensing mode) 8)
NE_EEP10C
cycles Max. data retention
time 10 years
DataFlash Endurance per
EEPROMx sector (single
ended sensing mode) 8)
NE_EEP10S
CC
cycles Retention time and Tj
according below
example temperature
profile
-
-
-
-
-
125000
125000
250000
cycles max data retention
time 20y, Tj=110°C
cycles max data retention
time 8.2y, Tj=125°C
Data Flash Endurance per
HSMx sector (complement
sensing mode) 8)
N
E_HSMC CC -
cycles Max. data retention
time 10 years
Data Flash Endurance per
HSMx sector (single ended
sensing mode) 8)
NE_HSMS CC -
-
125000
cycles Retention time and Tj
according below
example temperature
profile
-
-
-
-
-
-
125000
125000
150
cycles max data retention
time 20y, Tj=110°C
cycles max data retention
time 8.2y, Tj=125°C
Junction temperature limit for
PFlash program/erase
operations
T
JPFlash SR
°C
Data Flash Erase Time per
Sector 1)3)5)
t
t
ERD1 CC
ERDM CC
-
-
-
-
0.5
1.5
s
s
Max. 1000
erase/program cycles
Data Flash Erase Time per
Max allowed cycles,
see NE_EEP10 and
NE_HSM parameters
1)3)5)
Sector
DataFlash Adder on Erase
Time per 32kByte erase size
when using complement
sensing mode 1)
tER_ADDC32C
CC
-
-
50
ms
Adder per 32 kByte on
erase time; applicable
only when using
complement mode
Data Sheet
314
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Flash Target Parameters
Table 3-65 Flash (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Data Flash Erase Time per
Multi-Sector Command 1)3)5)
t
t
MERD1 CC
-
-
0.5
s
Max 1000
erase/program cycles;
Forconsecutivelogical
sectors ≤ 256KBytes
Data Flash Erase Time per
Multi-Sector Command 1)3)5)
MERDM CC
-
-
1.5
s
Max allowed cycles,
see NE_EEP10x and
NE_HSMx
Parameters; For
consecutive logical
sectors ≤ 256 kByte
Program Flash Access Delay at tPF_low_VDDP3
reduced VDDP3 voltage supply CC
during cranking
-
-
-
-
-
-
-
-
-
-
60
10
10
10
200
ns
µs
µs
µs
µs
see register
DMU_HF_PWAIT.CFL
ASH
Data Flash Erase Verify time
per page (Complement
Sensing) 2)
tVER_PAGE_D
C CC
Time per 8 Byte page
for Verify Erased Page
command
Data Flash Erase Verify time
per page (Single Ended
Sensing) 1)
tVER_PAGE_D
S CC
Time per 8 Byte page
for Verify Erased Page
command
Program Flash Erase Verify
time per page 1)
tVER_PAGE_P
CC
Time per 32 Byte page
for Verify Erased Page
command
Data Flash Erase Verify time
per sector (Complement
Sensing) 1)
tVER_SEC_DC
CC
Time per 2 KB sector
for Verify Erased
Logical Sector Range
command
Data Flash Erase Verify time
per sector (Single Ended
Sensing) 1)
tVER_SEC_DS
CC
-
-
-
-
360
360
µs
µs
Time per 4 KB sector
for Verify Erased
Logical Sector Range
command
Program Flash Erase Verify
time per sector 1)
tVER_SEC_P
CC
Time per 16KB sector
for Verify Erased
Logical Sector Range
command
Data Flash Erase Verify time
per wordline (Complement
Sensing) 1)
tVER_WL_DC
CC
-
-
-
-
-
-
30
50
30
µs
µs
µs
Data Flash Erase Verify time
per wordline (Single Ended
Sensing) 1)
tVER_WL_DS
CC
Program Flash Erase Verify
time per wordline 1)
tVER_WL_P
CC
1) Only vaild for fFSI = 100MHz.
2) Time is not dependent on program mode (5V or 3.3V).
Data Sheet
315
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Flash Target Parameters
3) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase
processes may be increased by up to 50%.
4) Using 512 kByte / 256 kByte erase commands (PFlash / DFlash).
5) If the DataFlash is operated in Complement Sensing Mode the erase time is increased by erase_size / 32kByte x
tER_ADDC32C
6) Allows segmentation of addressable memory into 8 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD
7) Allows segmentation of addressable memory into 6 logical sectors; round robin cycling must still be done to consider erase
disturb limit NDFD
8) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.
.
.
Data Sheet
316
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Quality Declarations
3.29
Quality Declarations
Table 3-66 Quality Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Moisture Sensitivity Level
MSL CC
-
-
3
Conforming to Jedec
J-STD--020C for 240C
ESD susceptibility according to VCDM SR
Charged Device Model (CDM)
-
-
-
500 1)
750
V
V
for all other balls/pins;
conforming to
JESD22-C101-C
-
for corner balls/pins;
conforming to
JESD22-C101-C
ESD susceptibility according to VHBM SR
Human Body Model (HBM)
-
-
-
-
2000 2)
2000
V
V
Conforming to
JESD22-A114-B
ESD susceptibility of the LVDS VHBM1 SR
pins according to Human Body
Model (HBM)
Operation Lifetime
t
OP CC
-
-
24500
hour
see belowtemperature
profile as an example
1) Pads of the AGBT interface are limited to a maximum value of 250V.
2) Pads of the AGBT interface are limited to a maximum value of 1000V.
Example Temperature Profile
The following temperature profile is an example. Application specific temperature profiles need to be aligned and
approved by Infineon Technologies for the fulfillment of quality and reliability targets.
Table 3-67 Example Temperature Profile
TJ=
Duration [h]
≤ 30
Comment
≤ 170°C
≤ 160°C
≤ 150°C
≤ 140°C
≤ 130°C
≤ 120°C
≤ 110°C
≤ 100°C
≤ 90°C
≤ 80°C
≤ 70°C
≤ 120
≤ 220
≤ 350
≤ 780
≤ 1600
≤ 3000
≤ 7000
≤ 8000
≤ 2400
≤ 1000
≤ 24500
total time
Data Sheet
317
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Package Outline
Table 3-68 Example Inactive Lifetime Temperature Profile
TJ=
Duration [h]
Comment
≤ 55°C
≤ 150700
3.30
Package Outline
Figure 3-24 Package Outlines LFBGA-292
Data Sheet
318
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Package Outline
Figure 3-25 Package Outlines LQFP-176
Table 3-69 Exposed Pad Dimensions
Ex; nominal EPad size
8.7 mm ± 50 μm
8.7 mm ± 50 μm
7.9 mm ± 50 μm
7.9 mm ± 50 μm
Ey; nominal EPad size
Ax; solderable EPad size
Ay; solderable EPad size
You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/packages.
3.30.1
Package Parameters
Table 3-70 Package Parameters
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
22
17
4.5
2
Thermal resistance (junction to RTH_JA
ambient) 1)
-
-
-
-
-
-
-
-
-
-
-
-
K/W
K/W
K/W
K/W
K/W
K/W
LFBGA-292
LQFP-176
LFBGA 292
LQFP-176
LFBGA-292
LQFP-176
CC
Thermal resistance (junction to RTH_JCB
case bottom) 1)
CC
Thermal resistance (junction to RTH_JCT
case top) 1)
5
CC
10
Data Sheet
319
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
Electrical Specification Package Outline
1) The top and bottom thermal resistances between the case and the ambient (RTH_CTA, RTH_CBA) are to be combined
with the thermal resistances between the junction and the case given above (RTH_JCT, RTH_JCB), in order to calculate
the total thermal resistance between the junction and the ambient (RTH_JA). The thermal resistances between the case
and the ambient (RTH_CTA, RTH_CBA) depend on the external system (PCB, case) characteristics and are under user
responsibility.
The junction temperature can be calculated using the following equation: TJ = TA + RTH_JA * PD, where the RTH_JA is
the total thermal resistance between the junction and the ambient.
Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1).
Data Sheet
320
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
4
History
Version 0.4 is the first version of this document.
4.1
Changes from Version 0.4 to Version 0.6
Changes in chapter “Pin Definition and Functions”
•
Changes in chapter TC37x T and TP - Pin Definition and Functions for package variant LFBGA-292
–
Changes in LFBGA-292 Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4,
P00.5, P00.6, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12
–
–
Changes in LFBGA-292 Package Variant 'Port 01 Functions' table; P01.5
Changes in LFBGA-292 Package Variant 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4,
P02.5, P02.6, P02.7, P02.8,
–
–
Changes in LFBGA-292 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6, P10.7, P10.8
Changes in LFBGA-292 Package Variant 'Port 11 Functions' table; P11.0, P11.1, P11.2, P11.3, P11.4,
P11.5, P11.6, P11.10, P11.12, P11.14
–
–
Changes in LFBGA-292 Package Variant 'Port 13 Functions' table; P13.1, P13.2
Changes in LFBGA-292 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5, P14.9,
P14.10
–
–
–
–
Changes in LFBGA-292 Package Variant 'Port 15 Functions' table; P15.4, P15.5
Changes in LFBGA-292 Package Variant 'Port 20 Functions' table; P20.0, P20.3, P20.14
Changes in LFBGA-292 Package Variant 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5
Changes in LFBGA-292 Package Variant 'Port 22 Functions' table; P22.0, P22.1, P22.2, P22.4, P22.5,
P22.6, P22.7, P22.8, P22.9, P22.10, P22.11
–
–
–
Changes in LFBGA-292 Package Variant 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5,
P23.6, P23.7
Changes in LFBGA-292 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.2, P32.3, P32.4,
P32.6, P32.7
Changes in LFBGA-292 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10,
P33.12, P33.13
–
–
–
Changes in LFBGA-292 Package Variant 'Port 34 Functions' table; P34.1, P34.2
Changes in LFBGA-292 Package Variant; Buffer Type changed for all Ports
Changes in LFBGA-292 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all
balls
–
–
–
–
Changes in LFBGA-292 Package Variant 'System I/O' table; Buffer Type changed for all balls
Changes in LFBGA-292 Package Variant 'System I/O' table; Symbol changed for balls Y17, W17
Changes in LFBGA-292 Package Variant 'System I/O' table; Function changed for balls Y17, W17,
Changes in LFBGA-292 Package Variant; 'Supply' table; Symbol and Function changed for balls L20, N19,
N20
•
Changes in chapter TC37x TE - Pin Definition and Functions for package variant LFBGA-292
–
Changes in LFBGA-292 Package Variant 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.7,
P00.8, P00.9, P00.10, P00.11, P00.12
–
–
Changes in LFBGA-292 Package Variant 'Port 01 Functions' table; P01.5
Changes in LFBGA-292 Package Variant 'Port 02 Functions' table; P02.3, P02.4, P02.5
Data Sheet
321
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
Changes in LFBGA-292 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6
Changes in LFBGA-292 Package Variant 'Port 11 Functions' table; P11.0, P11.1, P11.2, P11.3, P11.4,
P11.5, P11.10, P11.12
–
–
–
–
–
–
–
–
–
–
Changes in LFBGA-292 Package Variant 'Port 13 Functions' table; P13.1, P13.2
Changes in LFBGA-292 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5
Changes in LFBGA-292 Package Variant 'Port 15 Functions' table; P15.4, P15.5
Changes in LFBGA-292 Package Variant 'Port 20 Functions' table; P20.0, P20.6
Changes in LFBGA-292 Package Variant 'Port 21 Functions' table; P21.2, P21.3, P21.4, P21.5
Changes in LFBGA-292 Package Variant 'Port 23 Functions' table; P23.1
Changes in LFBGA-292 Package Variant 'Port 32 Functions' table; P32.1, P32.2, P32.4
Changes in LFBGA-292 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10
Changes in LFBGA-292 Package Variant; Buffer Type changed for all Ports
Changes in LFBGA-292 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all
balls
–
–
Changes in LFBGA-292 Package Variant 'System I/O' table; Buffer Type changed for all balls
Changes in LFBGA-292 Package Variant 'System I/O' table; Symbol changed for balls Y17, W17, M20,
M19
–
Changes in LFBGA-292 Package Variant; 'Supply' table; Symbol and Function changed for balls L20, N19,
N20
•
Changes in chapter TC37x T and TP - Pin Definition and Functions for package variant LQFP-176
–
Changes in LQFP-176 Package Variant 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.7,
P00.8, P00.9, P00.10, P00.11, P00.12
–
–
–
–
–
–
–
–
–
–
–
–
–
Changes in LQFP-176 Package Variant 'Port 02 Functions' table; P02.3, P02.4, P02.5
Changes in LQFP-176 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6
Changes in LQFP-176 Package Variant 'Port 11 Functions' table; P11.2, P11.3, P11.6, P11.10, P11.12
Changes in LQFP-176 Package Variant 'Port 13 Functions' table; P13.1, P13.2
Changes in LQFP-176 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5
Changes in LQFP-176 Package Variant 'Port 15 Functions' table; P15.4, P15.5
Changes in LQFP-176 Package Variant 'Port 20 Functions' table; P20.0
Changes in LQFP-176 Package Variant 'Port 21 Functions' table; P21.2, P21.3, P21.4, P21.5
Changes in LQFP-176 Package Variant 'Port 23 Functions' table; P23.1
Changes in LQFP-176 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.2, P32.4
Changes in LQFP-176 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10
Changes in LQFP-176 Package Variant; Buffer Type changed for all Ports
Changes in LQFP-176 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all
pins
–
–
–
Changes in LQFP-176 Package Variant 'System I/O' table; Buffer Type changed for all pins
Changes in LQFP-176 Package Variant 'System I/O' table; Symbol and function changed for pins 84, 85
Changes in LQFP-176 Package Variant; 'Supply' table; Symbol and Function changed for pins e_pad, 101,
104
•
Changes in chapter TC37x TE - Pin Definition and Functions for package variant LQFP-176
–
Changes in LQFP-176 Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4,
P00.5, P00.6, P00.7, P00.8, P00.9, P00.10, P00.11, P00.12
Data Sheet
322
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
Changes in LQFP-176 Package Variant 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4,
P02.5, P02.6, P02.7, P02.8
–
–
–
–
Changes in LQFP-176 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6, P10.7, P10.8
Changes in LQFP-176 Package Variant 'Port 11 Functions' table; P11.2, P11.3, P11.6, P11.10, P11.12
Changes in LQFP-176 Package Variant 'Port 13 Functions' table; P13.1, P13.2
Changes in LQFP-176 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5, P14.9,
P14.10
–
–
–
–
–
–
–
Changes in LQFP-176 Package Variant 'Port 15 Functions' table; P15.4, P15.5
Changes in LQFP-176 Package Variant 'Port 20 Functions' table; P20.0, P20.3,
Changes in LQFP-176 Package Variant 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5
Changes in LQFP-176 Package Variant 'Port 22 Functions' table; P22.0, P22.1, P22.2
Changes in LQFP-176 Package Variant 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5
Changes in LQFP-176 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.2, P32.3, P32.4
Changes in LQFP-176 Package Variant 'Port 33 Functions' table; P33.0, P33.2, P33.5, P33.7, P33.10,
P33.12, P33.13
–
–
Changes in LQFP-176 Package Variant; Buffer Type changed for all Ports
Changes in LQFP-176 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all
pins
–
–
–
–
–
Changes in LQFP-176 Package Variant 'System I/O' table; Buffer Type changed for all pins
Changes in LQFP-176 Package Variant 'System I/O' table; Symbol and function changed for pins 84, 85
Changes in LQFP-176 Package Variant 'System I/O' table; function changed for pins 102, 103
Changes in LQFP-176 Package Variant; 'Supply' table; Symbols and Functions changed for pins 101, 104
Changes in LQFP-176 Package Variant; 'Supply' table; Symbol and Function added for pin 177
•
Changes in chapter TC37x TE - Pin Definition and Functions for package variant LQFP-144
–
Changes in LQFP-144 Package Variant 'Port 00 Functions' table; P00.0, P00.1, P00.2, P00.3, P00.4,
P00.5, P00.6, P00.7, P00.8, P00.9, P00.12
–
Changes in LQFP-144 Package Variant 'Port 02 Functions' table; P02.0, P02.1, P02.2, P02.3, P02.4,
P02.5, P02.6, P02.7, P02.8
–
–
–
–
–
–
–
–
–
–
–
–
–
Changes in LQFP-144 Package Variant 'Port 10 Functions' table; P10.2, P10.5, P10.6
Changes in LQFP-144 Package Variant 'Port 11 Functions' table; P11.2, P11.3, P11.6, P11.10, P11.12
Changes in LQFP-144 Package Variant 'Port 13 Functions' table; P13.1, P13.2
Changes in LQFP-144 Package Variant 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5
Changes in LQFP-144 Package Variant 'Port 15 Functions' table; P15.4, P15.5
Changes in LQFP-144 Package Variant 'Port 20 Functions' table; P20.0, P20.3
Changes in LQFP-144 Package Variant 'Port 21 Functions' table; P21.2, P21.3, P21.4, P21.5
Changes in LQFP-144 Package Variant 'Port 22 Functions' table; P22.0, P22.1, P22.2
Changes in LQFP-144 Package Variant 'Port 23 Functions' table; P23.1
Changes in LQFP-144 Package Variant 'Port 32 Functions' table; P32.0, P32.1, P32.4
Changes in LQFP-144 Package Variant 'Port 33 Functions' table; P33.5, P33.7, P33.10, P33.12, P33.13
Changes in LQFP-144 Package Variant; Buffer Type changed for all Ports
Changes in LQFP-144 Package Variant 'Analog Inputs' table; Buffer Type and Functions changed for all
pins
–
Changes in LQFP-144 Package Variant 'System I/O' table; Buffer Type changed for all pins
Data Sheet
323
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
–
–
Changes in LQFP-144 Package Variant 'System I/O' table; Symbol and function changed for pins 70, 71
Changes in LQFP-144 Package Variant 'System I/O' table; function changed for pins 81,82
Changes in LQFP-144 Package Variant; 'Supply' table; Symbols and Functions changed for pins 83, 80
Changes in LQFP-144 Package Variant; 'Supply' table; Symbol and Function added for pin 145
•
Changes in chapter “Pad Position Configuration of TC37x”
Changes in table “Pad List” for all positions
Changes in chapter 'Pad Position Definition'
Changed description in sub-chapter 'Legend' - Column “Buffer Type”: PU2
Changes in chapter “Electrical Specification”
• Changes in table 'Absolute Maximum Ratings'
–
•
–
–
–
Changed max value of VIN from 7.0 V to 6.75 V
Changed description of VDDM from 'Voltage at VDDM, VEXT and VFLEX power supply pins with respect to VSS'
to 'Voltage at VDDM, VEXT, VFLEX and VEVRSB power supply pins with respect to VSS'
–
–
–
Changed note of VDDM from '7.0 V' to '6.75 V'
Added footnote 2) to VDD
Changed order of footnotes
•
Changes in table 'Overload Parameters'
–
–
–
–
–
Changed note of IINANA
Removed parameters of IID
Changed note of KOVAN
Changed parameter conditions of KOVAP
Added footnote 2) to KOVAP and KOVAN
•
•
Changes in 'Operating Conditions' table
–
–
Added footnote 1) to VDD
Changed order of footnotes
Changes in table 'PORST Pad' of Standard Pads
–
–
–
–
–
Change value name of parameter HYS
Changed notes of parameter IOZ
Added value of parameter VIH
Added value of parameter VIL
Add footnote 2) to IPDL
•
Changes in table 'Fast 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
Changed values and conditions of parameter IOZ
Combined equal values of IOZ in single lines
Changed conditions of parameter tRF
Changed value names of parameter of VIH
Changed value names of parameter HYS
Changed value names of parameter VIL
Changed conditions of parameter VILD
Changed parameter tSET
Added footnote 1) for tRF
Changed footnote 2) for tRF
Data Sheet
324
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
–
Added footnote 4) for IPUH
Added footnote 5) for IPDL
Changed order of footnotes
•
•
•
Changes in table 'Fast 3.3V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
–
–
–
Changed value names of parameter HYS
Changed condition of parameter tRF
Changed value names of parameter VIH
Changed value of parameter VIL
Changed condition of parameter VILD
Changed values and conditions of parameter IOZ
Combined equal values of IOZ in single lines
Changed parameter tSET
Added footnote 1) for tRF
Changed footnote 2) for tRF
Added footnote 4) for IPUH
Added footnote 5) for IPDL
Changed order of footnotes
Changes in table 'Slow 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
–
–
–
Changed value names of parameter HYS
Changed conditions of parameter IPUH
Changed values and conditions of parameter IOZ
Combined equal values of IOZ in single line
Changed value names of parameter VIL
Changed value names of parameter VIH
Changed conditions of parameter VILD
Changed parameter tSET
Added footnote 1) for tRF
Changed footnote 2) for tRF
Added footnote 4) for IPUH
Added footnote 5) for IPDL
Changed order of footnotes
Changes in table 'Slow 3.3V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
Changed value names of parameter HYS
Changed conditions of parameter IPUH
Changed values and conditions of parameter IOZ
Combined equal values of IOZ in single line
Removed parameter of IOZ
Changed value and name of parameter VIL
Changed value names of parameter VIH
Changed conditions of parameter VILD
Changed parameter of tSET
Added footnote 1) for tRF
Data Sheet
325
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
–
–
Changed footnote 2) for tRF
Added footnote 4) for IPUH
Added footnote 5) for IPDL
Changed order of footnotes
•
•
•
Changes in table 'RFast 5V GPIO' of Standard Pads
–
–
–
–
–
–
–
–
–
–
–
–
Changed condition of parameter tRF
Changed value names of parameter HYS
Changed conditions of parameter IOZ
Changed value names of parameter VIH
Changed value names of parameter VIL
Changed conditions of parameter VILD
Changed parameter of tSET
Added footnote 1) for tRF
Changed footnote 2) for tRF
Added footnote 4) for IPUH
Added footnote 5) for IPDL
Changed order of footnotes
Changes in table 'RFast 3.3V pad' of Standard Pads
–
–
–
–
–
–
–
–
–
–
–
–
Changed condition of parameter tRF
Changed value names of parameter HYS
Changed conditions of parameter IOZ
Changed value name of parameter VIH
Changed value and name of parameter VIL
Changed conditions of parameter VILD
Changed parameter tSET
Added footnote 1) for tRF
Changed footnote 2) for tRF
Added footnote 4) for IPUH
Added footnote 5) for IPDL
Changed order of footnotes
Changes in table 'Class S 5V' of Standard Pads
–
–
–
–
–
–
–
Changed value names of parameter HYS
Changed values of parameter IOZ
Changed value name of parameter VIH
Changed value name of parameter VIL
Changed parameter of tSET
Added footnote 2) for IPUH
Added footnote 3) for IPDL
•
•
Changes in table 'Class D' of Standard Pads
Changed values of parameter IOZ
Changes in table 'ADC Reference Pads' of Standard Pads
Changed notes of parameter IOZ2
–
–
Data Sheet
326
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
Added footnote 1) for IOZ2
•
•
Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)' of LVDS Pads
–
–
–
–
–
Changed condition of parameter Rin
Added parameter tSET_LVDS
Added footnote 1) for tRISE20
Added footnote 2) for tFALL20
Changed order of footnotes
Changes in table 'VADC 5V'
–
–
–
–
–
–
–
–
–
–
Added conditions of parameter VDDK
Changed parameter naming of dVDDK
Added conditions of parameter VAREF
Changed values and conditions of VAREF
Added note for parameter RPDD
Added footnote 1) for VAREF
Changed footnote 2) for TUE, EAINL, EADNL, EAGAIN, EAOFF, ENRMS
Added footnote 9) for QCONV
Changed order of footnotes
Changed figure 'Equivalent Circuitry for Analog Inputs'
•
Changes in table 'DSADC 5V'
–
–
–
–
–
–
–
–
–
–
Added parameter for RBIAS
Changed parameters of VAREF
Changed parameters of IREF
Added parameters of IREF
Changed parameters of IRMS
Changed parameters of EDGAIN
Changed parameters of EDOFF
Added footnote 2) for IRMS, SNR
Added footnote 3) for SFDR, EDGAIN, EDOFF,
Changed order of footnotes
•
Changes in table 'OSC_XTAL'
–
–
–
–
–
–
Removed parameter for VIHBX
Removed parameter for VILBX
Added parameter for DCX1
Added parameter for JABSX1
Added parameter for SRXTAL1
Added footnote 3) for DCX1, JABSX1, SRXTAL1
•
Changes in table 'Back-up Clock'
–
–
Changed value of fSB
Changed footnote 1) for fBACKT
•
•
Changes in table 'DTS PMS'
Added parameter conditions for TNL
Changes in table 'DTS Core'
–
Data Sheet
327
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
Added parameter ΔT
Added parameter conditions for TNL
•
Current Consumption
–
–
–
–
–
–
–
–
–
Added values and notes for IDDRAIL
Changed values for IDDRAIL
Added values and notes for IDDPORST
Changed values and notes for IDDPORST
Changed value and note for ISTANDBY
Changed value for IDDTOT
Changed values for PD
Changed footnote 4) for IEXTFLEX
Changed footnote 7) ISTANDBY
•
Changes in table 'Module Current Consumption'
–
–
–
–
–
–
–
Changed value of parameters of IDDP3PROG
Changed value of parameters of IEXTLVDS
Changed value of IDDP3ERASE
Changed value of parameter ISCRSB
Changed value of parameter ISCRIDLE
Added footnote 5) for ISCRSB
Changed order of footnotes
•
Changes in table 'Module Core Current Consumption'
–
–
–
–
–
Changed naming of IDDSPU1
Changed condition of parameter IDDLBIST
Changed value and condition of parameter IDDLMBIST
Changed footnote 1) for IDDHSM
Added footnote 2) for IDDLBIST
•
•
Changes in chapter “Single Supply mode”
–
–
–
–
Changed figure and description for 'Single Supply Mode (a)'
Changed figure and description for 'Single Supply Mode (e)'
Changed figure and description for 'Single Supply Mode (d)'
Changed figure and description for 'Single Supply Mode (h)'
Changes in table 'Reset'
–
–
–
–
–
–
–
Changed value of parameter tB
Changed value of parameter tBS
Added parameter tWARMRSTSEQ
Changed value of parameter tBWP
Changed naming and condition of parameter tLBIST
Added footnote 2) for tEVRPOR
Changed order of footnotes
•
Changes in table 'EVR33 LDO'
–
–
Changed condition of parameter tSTR
Added parameter for '∆VOUTTC
'
Data Sheet
328
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.4 to Version 0.6
–
–
Changed values and conditions of parameter dVOUT / dVIN
Added footnote 7) for dVOUT / dIOUT
•
Changes in table 'Supply Monitors'
–
–
–
–
–
–
–
Changed value of VRSTC
Changed values of parameter VEXTMON
Changed condition of parameter tMON
Changed footnote 2) for VEXTPRIUV, VDDP3PRIUV, VDDPRIUV,
Changed footnote 3) for VDDP3PRIUV, VDDPRIUV,
Added footnote 4) for VEXTMON
Added footnote 5) for VEXTMON, VDDP3MON, VDDMON
•
Changes in table 'EVRC SMPS'
–
–
–
–
–
Changed values and notes of parameter of 'fDCDC
'
Changed value of parameter of '∆VDDDC
'
Removed values and notes of parameter COUT
Added values of parameter 'LDC'
Changed condition of parameter dVDDDCT / dlOUT
•
•
Changed chapter naming from 'Phase Locked Loop (PLL)' to 'System Phase Locked Loop (SYS_PLL)'
Changes in table 'PLL System'
–
Removed parameter values of 'fMV'
•
Changes in table 'PLL Peripheral'
–
–
–
–
–
Changed description and values of parameter DPP
Added parameter DPPI
Changed notes of parameter DRMS
Changed notes of parameter DP
Added parameter JABS25
•
•
•
•
Changes in table 'Master Mode Timing'
Added footnote 1) for all parameters
Changes in table 'LVDS clock/data'
Added footnote 3) for all parameters
Changes in table 'Receive Parameters' of ERAY
Changed description of tdCCRxD10
Changes in table 'Flash'
–
–
–
–
–
–
–
–
–
–
–
–
–
Changed description of parameter of NDFD
Added parameter NDFDC
Added parameter NUCBD
Changed condition of parameter for NE_EEP10S
Added values for parameter NE_EEP10S
Changed condition of parameter for NE_HSMS
Added values for parameter NE_HSMS
Added parameter tVER_PAGE_DC
Added parameter tVER_PAGE_DS
Removed parameter tVER_PAGE_D
Data Sheet
329
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.6 to Version 0.61
–
Changed order of footnotes
•
Changes in table 'Quality Parameters'
–
–
–
Changed condition of parameter VHBM1
Added footnote 1) for VCDM
Added footnote 2) for VHBM
•
•
Changes in table 'Package Outline'
–
–
Added figures for Package Outline
Added tables 'Exposed Pad Dimensions'
Changes in table 'Package Parameters'
–
–
Added table 'Package Parameters'
Added footnote 1) for all parameters
4.2
Changes from Version 0.6 to Version 0.61
Changes in chapter “Summary of Features”
Changes in table “Platform Feature Overview” for Debug/AGBT and package variants
Changes in chapter “TC37x Pin Definition and Functions”
•
•
•
•
•
•
Changes in overview list: spelling of LFBGA-292
Changes in overview list for package types of LFBGA-292
Pad Position Configuration for TP, TE and TX variants added
Package variant LQFP-144 deleted
Changes in chapter TC37x TP - Pin Definition and Functions for package variant LFBGA-292
–
Changes in 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.7, P00.8, P00.9,
P00.10, P00.11, P00.12
–
–
–
–
–
–
–
–
–
–
–
Changes in 'Port 01 Functions' table; P01.6
Changes in 'Port 02 Functions' table; P02.3, P02.4, P02.5, P02.6, P02.7, P02.8
Changes in 'Port 10 Functions' table; P10.3, P10.4, P10.5, P10.6
Changes in 'Port 11 Functions' table; P11.5, P11.7, P11.8, P11.9, P11.10, P11.11, P11.12, P11.15
Changes in 'Port 12 Functions' table; P12.0
Changes in 'Port 13 Functions' table; P13.1, P13.2
Changes in 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5
Changes in 'Port 15 Functions' table; P15.4, P15.5, P15.6
Changes in 'Port 20 Functions' table; P20.0, P20.8, P20.14
Changes in 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5, P21.6, P21.7
Changes in 'Port 22 Functions' table; P22.0, P22.1, P22.4, P22.5, P22.6, P22.7, P22.8, P22.9, P22.10,
P22.11
–
–
–
–
–
–
Changes in 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5, P23.6, P23.7
Changes in 'Port 32 Functions' table; P32.2, P32.4
Changes in 'Port 33 Functions' table; P33.0, P33.1, P33.2, P33.3, p33.4, P33.5, P33.6, P33.10, P33.12
Changes in 'Port 34 Functions' table; P34.5
Changes in table “System I/O”
Changes in table “Supply”
Data Sheet
330
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.6 to Version 0.61
•
Changes in chapter TC37x TE and TX - Pin Definition and Functions for package variant LFBGA-292
–
–
–
–
–
–
–
–
–
Changed order of Port Function tables
Changed spelling of LFBGA-292
Changes in 'Port 00 Functions' table; P00.8
Changes in 'Port 02 Functions' table; P02.4, P02.5
Changes in 'Port 11 Functions' table; P11.5, P11.12
Changes in 'Port 13 Functions' table; P13.1, P13.2
Changes in 'Port 20 Functions' table; P20.0
Changes in 'Port 23 Functions' table; P23.1
Changes in 'Port 32 Functions' table; P32.4
•
Changes in chapter TC37x T and TP - Pin Definition and Functions for package variant LQFP-176
–
Changes in 'Port 00 Functions' table; P00.1, P00.2, P00.3, P00.4, P00.5, P00.6, P00.7, P00.8, P00.9,
P00.10, P00.11, P00.12
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Changes in 'Port 02 Functions' table; P02.3, P02.4, P02.5, P02.6, P02.7, P02.8
Changes in 'Port 10 Functions' table; P10.3, P10.4, P10.5, P10.6
Changes in 'Port 11 Functions' table; P11.9, P11.10, P11.11, P11.12
Changes in 'Port 13 Functions' table; P13.1, P13.2
Changes in 'Port 14 Functions' table; P14.2, P14.3, P14.4, P14.5
Changes in 'Port 15 Functions' table; P15.4, P15.5, P15.6
Changes in 'Port 20 Functions' table; P20.0, P20.8, P20.14
Changes in 'Port 21 Functions' table; P21.0, P21.2, P21.3, P21.4, P21.5, P21.6, P21.7
Changes in 'Port 22 Functions' table; P22.0, P22.1
Changes in 'Port 23 Functions' table; P23.1, P23.2, P23.3, P23.4, P23.5
Changes in 'Port 32 Functions' table; P32.2, P32.4
Changes in 'Port 33 Functions' table; P33.0, P33.1, P33.2, P33.3, P33.4, P33.5, P33.6, P33.10, P33.12
Changes in table “System I/O”
Changes in table “Supply”
•
Changes in chapter TC37x TE - Pin Definition and Functions for package variant LQFP-176
–
–
–
–
–
–
–
–
–
Changes in 'Port 00 Functions' table; P00.8
Changes in 'Port 02 Functions' table; P02.4, P02.5
Changes in 'Port 11 Functions' table; P11.12
Changes in 'Port 13 Functions' table; P13.1, P13.2
Changes in 'Port 15 Functions' table; P15.4, P15.5
Changes in 'Port 20 Functions' table; P20.0
Changes in 'Port 23 Functions' table; P23.1
Changes in 'Port 32 Functions' table; P32.4
Changes in table “Supply”
•
•
Deleted chapter TC37x TE - Pin Definition and Functions for package variant LQFP-144
Changes in chapter “Pad Position Configuration of TC37x TP”
–
Changes in table “Pad List” for different positions
•
•
Added chapter “Pad Position Configuration of TC37x TE and TX”
Changes in chapter “Legend”
Data Sheet
331
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.6 to Version 0.61
–
Added description concerning pinning DB versions for packages
Changes in chapter “Electrical Specification”
•
•
•
Changes in table 'RFast 3.3V pad'
Added parameter for fIND
Changes in table 'VADC 5V'
Added conditions for parameter VAIN
Changes in table 'DSADC 5V'
–
–
–
–
–
Added / changed values for parameter IRMS and EDGAIN
Added footnote 4)
Changed order of footnotes
•
Changes in table “Current Consumption”
–
–
–
–
–
–
–
Added footnotes for IEXTFLEX
Changed footnote for IDDTOTDC3
Changed footnote for IDDTOTDC5
Changed footnote for ISTANDBY
Changed footnote 2)
Added footnote 4) and 6)
Changed order of footnotes
•
Changes in table 'Module Current Consumption'
–
–
–
–
–
–
Changed condition of IEXTLVDS
Changed footnotes of IDDM
Changed footnote of ISCRSB
Changed footnote of ISCRIDLE
Added footnote 3) and 5)
Changed order of footnotes
•
•
Changes in table 'Module Core Current Consumption'
Changed / added values of parameter IDDGTM
Changes in table 'Reset'
–
–
–
Changed value of of parameter TBWP
Changed values of of parameter TSCR
•
•
•
Changes in table 'Supply Monitors'
–
–
Changed condition of parameter VRST33
Changed condition of parameter VRSTC
Changes in table 'Package Outline'
–
–
Changed spelling for figure from LF-BGA-292 to LFBGA-292
Deleted figure and table for QFP144
Changes in table 'Package Parameters'
–
–
Deleted values and notes for QFP144
Changed value for RTH_JACC
Data Sheet
332
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.61 to Version 0.7
4.3
Changes from Version 0.61 to Version 0.7
Changes in chapter “Summary of Features”
Changes in table “Platform Feature Overview”
•
–
–
added package LQFP-144
change package name from LFBGA-292-10 to LFBGA-292
Changes in chapter “TC37x Pin Definition and Functions”
•
Changes in overview list - package variants of LFBGA-292
–
–
–
Split of package variant description for LFBGA-292 - TE and TX version
Added package variant LQFP-144
Changed package variant figure numbering
•
Changes in chapter “LFBGA-292 Package Pinning of TC37x TE”
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Changes in 'Port 00 Functions' table; P00.3, P00.4, P00.8, P00.9, P00.10
Changes in ‘Port 01 Functions’ table; P01.6
Changes in ‘Port 02 Functions’ table; P02.4, P02.5, P02.6, P02.7, P02.8, P02.11
Changes in ‘Port 10 Functions’ table; P10.3, P10.4, P10.6
Changes in ‘Port 11 Functions’ table; P11.9, P11.15
Changes in ‘Port 13 Functions’ table; P13.1, P13.2
Changes in ‘Port 14 Functions’ table; P14.4
Changes in ‘Port 15 Functions’ table; P15.4, P15.5, P15.6
Changes in ‘Port 20 Functions’ table; P20.0, P20.8, P20.14
Changes in ‘Port 21 Functions’ table; P21.2, P21.3, P21.4, P21.5
Changes in ‘Port 22 Functions’ table; P22.0, P22.5, P22.10
Changes in ‘Port 23 Functions’ table; P23.3, P23.4
Changes in ‘Port 32 Functions’ table; P32.2, P32.4
Changes in ‘Port 33 Functions’ table; P33.3, P33.10, P33.12
Changes in ‘Port 34 Functions’ table; P34.5
Changes in table “Analog Inputs”; ball U6, EDSADC; ball T6, EDSADC; ball W2, EDSADC; ball W1,
EDSADC; ball M1, EDSADC; ball M2, EDSADC
–
Changes in table “System I/O”; ball L7, K7, P10, P11, L14, G11, K14
Added chapter “LFBGA-292 Package Pinning of TC37x TX”
Changes in chapter “LQFP-176 Package Pinning of TC37x TE”
•
–
–
–
–
–
–
–
–
–
–
Changes in 'Port 00 Functions' table; P00.3, P00.4, P00.8, P00.9, P00.10
Changes in ‘Port 02 Functions’ table; P02.4, P02.5, P02.6, P02.7, P02.8
Changes in ‘Port 10 Functions’ table; P10.3, P10.4, P10.6
Changes in ‘Port 11 Functions’ table; P11.9
Changes in ‘Port 13 Functions’ table; P13.1, P13.2
Changes in ‘Port 14 Functions’ table; P14.4
Changes in ‘Port 15 Functions’ table; P15.4, P15.5, P15.6
Changes in ‘Port 20 Functions’ table; P20.0, P20.8, P20.14
Changes in ‘Port 21 Functions’ table; P21.2, P21.3, P21.4, P21.5
Changes in ‘Port 22 Functions’ table; P22.0
Data Sheet
333
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.61 to Version 0.7
–
–
–
–
Changes in ‘Port 23 Functions’ table; P23.3, P23.4
Changes in ‘Port 32 Functions’ table; P32.2, P32.4
Changes in ‘Port 33 Functions’ table; P33.3, P33.10, P33.12
Changes in table “Analog Inputs”; pin 44, EDSADC; pin 43, EDSADC; pin 29, EDSADC; pin 28, EDSADC;
Added chapter “LQFP-144 Package Pinning of TC37x TE”
Changes in chapter “Pad Position Configuration of TC37x TE/TX”
–
–
Changes in table “Pad List”, number 34, 35, 219, 220, 223, 224, 225, 307,
Added comment concerning “neighbor pads”
Changes in chapter “Legend”
Changed refering IO_Spirit_file version
Changes in chapter “Electrical Specification”
–
•
Changes in table 'Operating Conditions'
Deleted parameter for fEBU
Changes in table 'LVDS - IEEE standard LVDS general purpose link (GPL)'
–
•
–
–
–
–
–
Changed value for parameter VI
Changed test condition for parameter Vidth
Added values for parameter Vidth
Changed test condition for parameter Rin
Added notes to LVDS table
•
Changes in table 'Current Consumption'
–
–
–
–
–
–
–
–
–
–
–
–
Deleted values for parameter IDDRAIL
Deleted value for parameter IDDPORST
Changed value of parameter IEXTRAIL
Changed test condition for parameter IDDTOT
Added values and test condition for parameter IDDTOT
Added value for parameter IDDTOTDC3
Changed test parameter for IDDTOTDC3
Added value for parameter IDDTOTDC5
Changed test conditions for IDDTOTDC5
Changed test conditions for parameter PD
Added values for parameter PD
Modified footnote 9) for parameter PD
•
Changes in table 'Module Core Current Consumption'
–
–
–
–
Changed values for parameter IDDCx0
Changed values for parameter IDDCxx
Deleted parameter for IDDSPU1
Added value for parameter IDDCIF
•
•
Added sub-chapter 'Calculating the 1.25 V Current Consumption'
Changes in table 'Reset'
–
Changed value for parameter tPIP
Changes in table 'PLL System'
Changed value for parameter fREF
•
–
Data Sheet
334
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.7 to Version 0.71
•
Changes in sub-chapter 'ETH RGMII Parameters'
Added figures for ETH RGMII TXand RX signals
–
•
•
Added sub-chapter 'SDMMC Interface Timing'
Changes in table 'Flash'
–
–
Changed value for parameter tPRPB5_PF
Changed values for parameter tER_Dev
•
•
Added figure for Package Outlines LQFP-144
Changes in table 'Package Parameters'
–
–
–
Added value for parameter RTH_JA - QFP144
Added value for parameter RTH_JCB - QFP144
Added value for parameter RTH_JCT - QFP144
4.4
Changes from Version 0.7 to Version 0.71
•
General changes in Data Sheet TC37x: Data Sheet splitted and renamed to TC37xEXT for feature package
TE/TX and TC37x for feature package T/TP
•
•
Changed Data Sheet version 0.7 to 0.71
Changes in table “Platform Feature Overview”
–
–
–
–
–
–
–
–
–
Changed GTM features
ASIL Level deleted
Debug features deleted
SDMMC features deleted
Changed packages name spelling
Changed numbers of GBit Ethernet instance
CIF features deleted
Changed CAN features
Changed Data Flash size
•
Changes in chapter “TC37x Pin Definition and Functions”
–
–
–
–
–
Deleted Package Pinning for LFBGA-292-10, TC37x TE and TX
Deleted Package Pinning for LQFP-176, TC37x TE
Deleted Package Pinning for LQFP-144, TC37x TE
Deleted Pad Position Configuration of TC37x TE and TX
Changed package name spelling (LFBGA-292)
•
•
Changes in table "Legend"
Spirit version for feature package TC37x TE and TX has been deleted
Changes in chapter "Electrical Specification"
–
–
–
–
–
–
–
Changed description in table “Absolute Maximum Ratings” for parameter ΣIIN
Added footnote to table “Absolute Maximum Ratings”
Added footnote in table “Absolute Maximum Ratings” for parameter IIN
Changed value in table “Overload Parameters” for parameter VOUS
Changed conditions in table “Operating Conditions” for parameter VFLEX
Added parameter in table “Operating Conditions” for VFLEX2
Data Sheet
335
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.7 to Version 0.71
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Changed conditions in table “Fast 5V GPIO” for parameter tRF
Changed values in table “Fast 5V GPIO” for parameter HYS
Changed conditions in table “Fast 5V GPIO” for parameter IOZ
Changed value in table “Fast 5V GPIO” for parameter VIH
Changed value in table “Fast 5V GPIO” for parameter VIL
Changed condition in table “Fast 5V GPIO” for parameter VILD
Changed conditions in table “Fast 3.3V GPIO” for parameter tRF
Changed values in table “Fast 3.3V GPIO” for parameter HYS
Changed conditions in table “Fast 3.3V GPIO” for parameter IOZ
Changed value in table “Fast 3.3V GPIO” for parameter VIH
Changed value in table “Fast 3.3V GPIO” for parameter VIL
Changed condition in table “Fast 5V GPIO” for parameter VILD
Changed values in table “Slow 5V GPIO” for parameter HYS
Changed conditions in table “Slow 5V GPIO” for parameter IOZ
Changed value in table “Slow 5V GPIO” for parameter VIH
Changed value in table “Slow 5V GPIO” for parameter VIL
Changed condition in table “Slow 5V GPIO” for parameter VILD
Changed values in table “Slow 3.3V GPIO” for parameter HYS
Changed conditions in table “Slow 3.3V GPIO” for parameter IOZ
Changed value in table “Slow 3.3V GPIO” for parameter VIH
Changed value in table “Slow 3.3V GPIO” for parameter VIL
Changed condition in table “Slow 3.3V GPIO” for parameter VILD
Changed conditions in table “RFast 5V GPIO” for parameter tRF
Changed values in table “RFast 5V GPIO” for parameter HYS
Changed conditions in table “RFast 5V GPIO” for parameter IOZ
Changed value in table “RFast 5V GPIO” for parameter VIH
Changed value in table “RFast 5V GPIO” for parameter VIL
Changed condition in table “RFast 5V GPIO” for parameter VILD
Changed conditions in table “RFast 3.3V pad” for parameter tRF
Changed values in table “RFast 3.3V pad” for parameter HYS
Changed conditions in table “RFast 3.3V pad” for parameter IOZ
Changed value in table “RFast 3.3V pad” for parameter VIH
Changed value in table “RFast 3.3V pad” for parameter VIL
Added table for “Class S 3.3V” parameters to sub-chapter “5V/ 3.3V switchable Pads”
Changed footnote 1) at table “OSC_XTAL”
Added power pattern information to sub-chapter “Power Supply Current”
Deleted values in table “Current Consumption” for parameter IDDRAIL
Deleted values in table “Current Consumption” for parameter IDDPORST
Changed footnote numbering in table “Current Consumption” for parameter IDDP3RAIL
Changed value in table “Current Consumption” for parameter IEXTRAIL
Changed footnote numbering in table “Current Consumption” for parameter IEXTRAIL
Changed footnote numbering in table “Current Consumption” for parameter IEXTFLEX
Data Sheet
336
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 0.71 to Version 1.0
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Changed value in table “Current Consumption” for parameter IEVRSB
Changed footnote numbering in table “Current Consumption” for parameter IEVRSB
Deleted values in table “Current Consumption” for parameter IDDTOT
Changed footnote numbering in table “Current Consumption” for parameter IDDTOTDC3
Changed footnote numbering in table “Current Consumption” for parameter IDDTOTDC5
Changed footnote numbering in table “Current Consumption” for parameter ISLEEP
Changed footnote numbering in table “Current Consumption” for parameter ISTANDBY
Deleted values in table “Current Consumption” for parameter PD
Deleted footnote 1) at table “Current Consumption”
Deleted parameter IDDCIF in table “Module Core Current Consumption”
Changed equations in sub-chapter “Calculating the 1.25V Current Consumption”
Changed condition in table “Reset” for parameter tSUPHOLD
Added values and conditions in table “Supply Monitors” for parameter VEXTMON
Changed conditions in table “Supply Monitors” for parameter VDDP3MON
Changed conditions in table “Supply Monitors” for parameter VDDMON
Added note regarding power-cycles to table "Supply Ramp"
Changed symbol in table “EVRC SMPS” for parameter ∆fDCSPR
Changed symbol in table “EVRC SMPS” for parameter nDC
Deleted sub-chapter “SDMMC Interface Timing”
Changed value in table “Quality Parameters” for parameter VHBM1
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Changes in “Package Outline”
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Changed package name spelling for figure titles
Deleted figure for Package Outline LQFP-144
Deleted values for package LQFP-144 in table Package Parameters
Changed packages name spelling in table “Package Parameter”
4.5
Changes from Version 0.71 to Version 1.0
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Changed Data Sheet version from 0.71 to version 1.0
Changes in chapter "TC37x Pin Definition and Functions”
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Typo corrected in footnote for table "Pad List"
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Changes in chapter "Electrical Specification"
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Typo corrected in note for table "Overload Parameters"
Typo corrected in notes for table "PORST Pad"
Typo corrected in notes for table "Fast 5V GPIO"
Typo corrected in notes for table "Fast 3.3V GPIO"
Typo corrected in notes for table "Slow 5V GPIO"
Typo corrected in notes for table "Slow 3.3V GPIO"
Typo corrected in notes for table "RFast 5V GPIO"
Typo corrected in notes for table "RFast 3.3V pad"
Typo corrected in notes for table "Class S 5V"
Typo corrected in notes for table "Class S 3.3V"
Data Sheet
337
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 1.0 to Version 1.1
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Changed wording in footnote 2 for table "OSC_XTAL"
Changed figure "Equivalent Circuitry for Analog Inputs" in chapter "VADC Parameters"
Changed footnote 4) for table DSADC 5V in chapter "DSADC Parameters"
Deleted values in table “Current Consumption” for parameter IDDRAIL
Deleted values in table “Current Consumption” for parameter IDDPORST
Deleted values in table “Current Consumption” for parameter IDDTOT
Deleted values in table “Current Consumption” for parameter PD
Changed footnote numbers in table “Current Consumption” for parameter IDDP3RAIL
Changed footnote number in table “Current Consumption” for parameter IEXTRAIL
Changed footnote number in table “Current Consumption” for parameter IEXTFLEX
Changed footnote number in table “Current Consumption” for parameter IEVRSB
Changed footnote number in table “Current Consumption” for parameter IDDTOTDC3
Changed footnote number in table “Current Consumption” for parameter IDDTOTDC5
Changed footnote number in table “Current Consumption” for parameter ISLEEP
Changed footnote numbers in table “Current Consumption” for parameter ISTANDBY
Deleted footnote 1) at table “Current Consumption”
Changed footnote numbering at table “Current Consumption”
Changed note in table “Supply Monitors” for parameter VEXTMON
Changed wording in footnote regarding power-cycles at table "Supply Ramp"
Changed frequency variable for parameter tPI in table “Reset”
Deleted note for parameter t21 in table "ETH RGMII Signal Timing Parameters valid for 3.3V"
4.6
Changes from Version 1.0 to Version 1.1
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Changes in Chapter Revision History
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Chronology completed
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Changes in chapter “Summary of Features”
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Changed wording for “DFLASH”
Added description for “AEC-Q100”
Added description for “ISO 26262 Safety Element”
Added description for Data Flash in table “Platform Feature Overview”
Added details for parameter GTM/ Clusters in table “Platform Feature Overview”
•
Changes in chapter “TC37x Pin Definition and Functions”
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Changed wording from “Pad Position Configuration of TC37x TP” to “Sequence of Pads in Pad Frame”
Added notes to table “System I/O” for “LFBGA-292 Package Pinning of TC37x TP”
Added note to sub-chapter “LQFP-176 Package Pinning of TC37x T and TP”
Added notes to table “System I/O” for “LQFP-176 Package Pinning of TC37x TP”
Changed wording for sub-chapter “Pad Position Configuration of TC37x TP” to “Sequence of Pads in Pad
Frame”
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Data Sheet
338
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 1.0 to Version 1.1
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Changes in chapter “Legend”
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Changed version number of “TC37xpd_IO_Spirit” file
Changes in chapter “Electrical Specification”
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Typos corrected in footnotes for sub-chapter “Absolute Maximum Ratings”
Extended introduction for sub-chapter “Pin Reliability in Overload”
Typo corrected for parameter IINSA in table “Overload Parameters” of sub-chapter “Pin Reliability in
Overload”
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Changed values for parameter GETH frequency in table “Operating Conditions”
Changed note for parameter tTX_ASYM in table “Fast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Note typos corrected for different parameters in tables “PORST Pad”, “Fast 5V GPIO”, “Fast 3.3V GPIO”,
“Slow 5V GPIO”, “Slow 3.3V GPIO”, “RFast 5V GPIO”, “RFast 3.3V pad”, “Class S 5V”, “Class S 3.3V”
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Changed note for parameter tTX_ASYM in table “Fast 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Slow 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “Slow 3.3V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “RFast 5V GPIO” of sub-chapter “5V/3.3V switchable Pads”
Changed note for parameter tTX_ASYM in table “RFast 3.3V pad” of sub-chapter “5V/3.3V switchable Pads”
Typos corrected in footnote 3) for table “LVDS – IEEE standard LVDS general purpose link (GPL)” in sub-
chapter “High performance LVDS Pads”
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Typo corrected for parameter dVCSD in table “VADC 5V” in sub-chapter “VADC Parameters”
Changed footnote 3) and 6) of table “VADC 5V” in sub-chapter “VADC Parameters”
Changed footnote 7) of table “VADC 5V” in sub-chapter “VADC Parameters”
Changed value of parameter IRMS in table “DSADC 5V” in sub-chapter “DSADC Parameters”
Changed intro wording for VEXT description of sub-chapter “Power Supply Current”
Added values and notes for parameter IDDRAIL in table “Current Consumption” of sub-chapter “Power
Supply Current”
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Added values and notes for parameter IDDPORST in table “Current Consumption” of sub-chapter “Power
Supply Current”
Changed numbering of footnotes for parameter IDDP3RAIL, IEXTRAIL, IEXTFLEX, IEVRSB, IDDTOTDC3, IDDTOTDC5
,
I
SLEEP, ISTANDBY, PD, in table “Current Consumption” of sub-chapter “Power Supply Current”
Added values and notes for parameter IDDTOT in table “Current Consumption” of sub-chapter “Power Supply
Current”
Added values and notes for parameter PD in table “Current Consumption” of sub-chapter “Power Supply
Current”
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Added footnote 1) to table “Current Consumption” of sub-chapter “Power Supply Current”
Changed footnote 3) for table “Current Consumption” in sub-chapter “Power Supply Current”
Changed footnote numbering for table “Current Consumption” in sub-chapter “Power Supply Current”
Added footnote 10) to table “Current Consumption” of sub-chapter “Power Supply Current”
Added sentence to sub-chapter “Supply Ramp-up and Ramp-down Behavior”
Changed/added value for parameter tPI in table “Reset” for sub-chapter “Reset Timing”
Changed value of parameter RON (from Max. to Typ.) in table “EVRC SMPS External components” for sub-
chapter “PMS”
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Changed values (from Min. to Typ.) for parameter t7 in table “ETH MII Signal Timing Parameters” for sub-
chapter “ETH MII Parameters”
Data Sheet
339
V 1.1, 2021-03
OPEN MARKET VERSION
TC37x AA-Step
History Changes from Version 1.0 to Version 1.1
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Changed symbols for parameters t13, t14, t15 in table “ETH RMII Signal Timing Parameters valid for 3.3V”
in sub-chapter “ETH RMII Parameters”
Changed value (from Min. to Typ.) for parameter t13 in table “ETH RMII Signal Timing Parameters valid for
3.3V” in sub-chapter “ETH RMII Parameters”
Added footnote 3) to parameters t16, t17 in table “ETH RMII Signal Timing Parameters valid for 3.3V” in sub-
chapter “ETH RMII Parameters”
Added footnote 3) to table “ETH RMII Signal Timing Parameters valid for 3.3V” in sub-chapter “ETH RMII
Parameters”
Added table “Example Inactive Lifetime Temperature Profile” to sub-chapter “Quality Declaration”
Data Sheet
340
V 1.1, 2021-03
OPEN MARKET VERSION
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