SFH6319 [INFINEON]

LOW CURRENT, HIGH GAIN OPTOCOUPLER; 低电流,高增益光耦合器
SFH6319
型号: SFH6319
厂家: Infineon    Infineon
描述:

LOW CURRENT, HIGH GAIN OPTOCOUPLER
低电流,高增益光耦合器

光电
文件: 总3页 (文件大小:42K)
中文:  中文翻译
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SFH6318  
SFH6319  
LOW CURRENT, HIGH GAIN  
OPTOCOUPLER  
Package Dimensions in Inches (mm)  
.120±.002  
(3.05±.05)  
NC  
8
7
1
2
VCC  
VB  
FEATURES  
Anode  
• Industry Standard SOIC-8 Surface Mountable  
Package  
• High Current Transfer Ratio, 800%  
• Low Input Current, 0.5mA  
.154±.002  
(.391±.05)  
C
.240  
(6.10)  
L
6
5
3
4
Cathode  
NC  
V0  
GND  
.016  
(.41)  
Pin 1  
• High Output Current, 60mA  
• Isolation Test Voltage, 2500 VACRMS  
• TTL Compatible Output, VOL=0.1 V  
• Adjustable Bandwidth-Access to Base  
• Underwriters Lab File #E52744  
7°  
40°  
.058±.005  
(1.49±.13)  
.015±.002  
(.38±.05)  
.192±.005  
(4.88±.13)  
.004 (.10)  
.008 (.20)  
.125±.005  
(3.18±.13)  
.008 (.20)  
5° max.  
R.010  
Lead  
APPLICATIONS  
• Logic Ground Isolation-TTL/TTL, TTL/CMOS,  
CMOS/CMOS, CMOS/TTL  
Coplanarity  
±.0015 (.04)  
max.  
.021  
(.53)  
.050  
(1.27)  
typ.  
.020±.004  
(.15±.10)  
2 plcs.  
(.25)  
max.  
• EIA RS 232C Line Receiver  
• Low Input Current Line Receiver-Long Lines,  
Party Lines  
TOLERANCE: ±.005 (unless otherwise noted)  
Maximum Ratings (25°)  
• Telephone Ring Detector  
Emitter  
Reverse Input Voltage....................................................................... 3 V  
Supply and Output Voltage, VCC (pin 8-5), VO (pin 6-5)  
SFH6318........................................................................... –0.5 to 7 V  
SFH6319......................................................................... –0.5 to 18 V  
Input Power Dissipation .............................................................. 35 mW  
Derate Linearly above 50°C  
Free Air Temperature......................................................... 0.7 mW/°C  
Average Input Current.................................................................. 20 mA  
Peak Input Current....................................................................... 40 mA  
(50% Duty Cycle-1 ms pulse width)  
Peak Transient Input Current  
(tp1 µsec, 300 pps) .................................................................. 1.0 A  
Detector (Si Photodiode + Photodarlington)  
Output Current IO (pin 6)............................................................. 60 mA  
Emitter-Base Reverse Voltage (pin 5-7)......................................... 0.5 V  
Output Power Dissipation ......................................................... 150 mW  
Derate Linearly from 25°C ................................................... 2 mW/°C  
Package  
• 117 VAC Line Voltage Status Indication-Low  
Input Power Dissipation  
• Low Power Systems-Ground Isolation  
DESCRIPTION  
Very high current ratio together with 2500 VAC isolation  
are achieved by coupling an LED with an integrated high  
gain photodetector in a SOIC-8 package. Separate pins  
for the photodiode and output stage enable TTL compat-  
ible saturation voltages with high speed operation. Pho-  
todarlington operation is achieved by tying the VCC and  
VO terminals together. Access to the base terminal  
allows adjustment to the gain bandwidth.  
The SFH6318 is ideal for TTL applications since the  
300% minimum current transfer ratio with an LED current  
of 1.6 mA enables operation with one unit load-in and  
one unit load-out with a 2.2 KW pull-up resistor.  
Storage Temperature .................................................. –55°C to +125°C  
Operating Temperature................................................. –40°C to +85°C  
Lead Soldering Temperature (t=10 sec.) ..................................... 260°C  
Junction Temperature .................................................................. 100°C  
Ambient Temperature Range...................................... –55°C to +100°C  
Isolation Test Voltage between  
Emitter and Detector ...................................................2500 VACRMS  
(refer to climate DIN 40046, part 2, Nov. 74)  
Pollution Degree (DIN VDE 0110).........................................................2  
Creepage Distance......................................................................4 mm  
Clearance ....................................................................................4 mm  
Comparative Tracking Index  
The SFH6319 is best suited for low power logic applica-  
tions involving CMOS and low power TTL. A 400% cur-  
rent transfer ratio with only 0.5 mA of LED current is  
guaranteed from 0°C to 70°C.  
Caution:  
Due to the small geometries of this device, it should be handled  
with Electrostatic Discharge (ESD) precautions. Proper ground-  
ing would prevent damage further and/or degradation which  
may be induced by ESD.  
per DIN IEC 112/VDE 0303, part 1.............................................. 175  
Isolation Resistance  
VIO=500 V, TA=25°C RISOL .................................................1012W  
VIO=500 V, TA=100°C RISOL ...............................................1011W  
1
Electro-Optical Characteristics (T =0°C to 70°C, T =25°C-Typical, unless otherwise specified)  
A
A
Parameter  
Symbol  
Device  
Min Typ  
Max  
Units Test Conditions  
Note  
Current Transfer Ratio  
CTR  
SFH6318  
SFH6319  
300  
1600  
2600  
%
%
I =1.6 mA, V =0.4 V, V =4.5 V 1,2  
F
O
CC  
400  
500  
1600  
2000  
2600  
3500  
I =0.5 mA, V =0.4 V, V =4.5 V 1,2  
F O CC  
I =1.6 mA, V =0.4 V, V =4.5 V  
F
O
CC  
Logic Low  
Output Voltage  
V
SFH6318  
SFH6319  
0.1  
0.4  
V
V
I =1.6 mA, I =4.8 mA, V =4.5  
V
2
2
OL  
F
O
CC  
0.1  
0.15  
0.25  
0.4  
0.4  
0.4  
I =1.6 mA, I =8 mA, V =4.5 V  
F O CC  
I =5 mA, I =15 mA, V =4.5 V  
F O CC  
I =12 mA, I =24 mA, V =4.5 V  
F
O
CC  
Logic High  
Output Current  
I
I
SFH6318  
SFH6319  
0.1  
250  
100  
1.5  
µA  
µA  
mA  
I =0 mA, V =V =7 V  
2
2
2
OH  
F
O
CC  
0.05  
0.2  
I =0 mA, V =V =18 V  
F O CC  
Logic Low Supply Current  
I =1.6 mA, V =OPEN, V =18  
CCL  
F
O
CC  
V
Logic High Supply Current  
Input Forward Voltage  
I
0.01  
1.4  
10  
µA  
I =0 mA, V =OPEN, V =18 V  
2
CCH  
F
O
CC  
V
1.7  
V
I =1.6 mA, T =25°C  
F A  
F
Temperature Coefficient,  
Forward Voltage  
V /T  
–1.8  
mV/  
°C  
I =1.6 mA  
F
F
A
Input Capacitance  
C
R
25  
pF  
f=1 MHz, V =0  
F
IN  
12  
Resistance (Input-Output)  
10  
V
V
=500 VDC, T =25°C  
=500 VDC, T =100°C  
3
3
I-O  
IO  
IO  
A
A
11  
10  
Capacitance (Input-Output)  
C
0.6  
pF  
f=1 MHz  
I-O  
Switching Specifications (T =25°C)  
A
Parameter  
Symbol  
Device  
Min  
Typ  
Max  
Units  
Test Conditions  
I =1.6 mA, R =2.2 KΩ  
Note  
Propagation Delay Time  
To Logic Low at Output  
t
SFH6318  
SFH6319  
2
10  
µs  
µs  
PHL  
F
L
6
0.6  
25  
1
I =0.5 mA, R =4.7 KΩ  
2,4  
F
L
I =12 mA, R =270 Ω  
F L  
Propagation Delay Time  
To Logic High at Output  
t
SFH6318  
SFH6319  
2
35  
µs  
µs  
I =1.6 mA, R =2.2 KΩ  
F L  
PLH  
4
1.5  
60  
7
I =0.5 mA, R =4.7 KΩ  
2,4  
5,6  
5,6  
F
L
I =12 mA, R =270 Ω  
F L  
Common Mode Transient Immunity  
at Logic High Level Output  
| CM  
|
1 K  
V/µs  
V/µs  
I =0 mA, R =2.2 KΩ  
H
F
CM  
L
p-p  
V
=10 V  
Common Mode Transient Immunity  
at Logic Low Level Output  
| CM |  
1 K  
I =1.6 mA, R =2.2 KΩ  
F L  
L
V
=10 V  
CM  
p-p  
Notes  
1. DC current transfer ratio is defined as the ratio of output collector current, I , to the forward LED input current, I times 100%.  
O
F
2. Pin 7 open.  
3. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together.  
4. Using a resistor between pin 5 and 7 will decrease gain and delay time.  
5. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV /dt on the leading edge of the common mode pulse,  
cm  
V
, to assure that the output will remain in a logic high state (i.e. V >2.0 V) common mode transient immunity in logic low level is the maximum  
CM  
O
tolerable (negative) dV /dt on the trailing edge of the common mode pulse signal, V , to assure that the output will remain in a logic low state  
cm  
CM  
(i.e. V <0.8 V).  
O
6. In applications where dv/dt may exceed 50,000 V/µs (such as state discharge) a series resistor, R should be included to protect IC from destruc  
CC  
tively high surge currents. The recommended value is RCC  
IV  
k. Refer to Figure 2.  
0.15 IF(mA)  
SFH6318/6319  
2
Figure 1. Switching test circuit  
IF  
0
10% Duty Cycle  
1/f<100 µs  
+5 V  
8
7
1
2
5 V  
VO  
(Saturated  
Response)  
Pulse  
IF  
Generator  
ZO=50  
RL  
1.5 V  
1.5 V  
t =5 ns  
r
VOL  
6
5
3
4
VO  
0.1 µF  
tPLH  
tPHL  
IF=Monitor  
CL=15pF  
5 V  
VO  
90%  
90%  
10%  
Rm  
(Non-Saturated  
Response)  
10%  
t
t
r
f
Figure 2.Test circuit for transient immunity and typical waveforms  
RCC (see Note 6)  
+5 V  
8
7
1
2
VCM  
90%  
90%  
220  
0.1 µF  
IF  
10%  
0 V  
10%  
RL  
t
t
r
f
t + t =16 ns  
f
f
6
5
3
4
VO  
A
B
VO  
5 V  
Switch at A: I =0 mA  
F
VFF  
VCM  
VO  
+
VOL  
Switch at B: I =1.6 mA  
F
Pulse Generator  
SFH6318/6319  
3

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