TC1910_技术文档

Data Sheet, V 1.0, Oct. 2003

TC1910

32-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2003-10

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address

list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

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be endangered.

Data Sheet, V 1.0, Oct. 2003

TC1910

32-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

TC1910

PRELIMINARY

Revision History:

2003-10

V 1.0

Previous Version:

Page

Subjects (major changes since last revision)

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TC1910

PRELIMINARY

TC1910 Features

The TC1910 offers a 32 bit TriCore based microcontroller/DSP, which is mainly designed

for automotive telematics applications. Due to its high integration, this microcontroller/

DSP offers high system performance at minimized cost. Typical telematics functions

processed by RISC-, DSP- and speech- (CODEC) modules are now combined in one

component. This combination of dedicated speech peripherals (CODEC) and standard

peripherals (SSC/SPI, ASC and IIC), makes this microcontroller/DSP the engine tailored

for a wide variety of telematics applications such as navigation, emergency call, speech

interface or communication interface.

• TriCore CPU/DSP with 4-Stage Pipeline:

– 66 MHz max. CPU clock frequency, 50 MHz max. FPI Bus clock frequency.

– 32-bit super-scalar TriCore main CPU

– 4-GByte unified memory space support

– Fast context-switching

– Dual 16 x 16 Multiply-accumulate (MAC) unit

– 64-bit Local Memory Bus (LMB)

– 32-bit Flexible Peripheral Interface Bus (FPI)

– 32-bit wide External Bus Unit (EBU)

• On-chip memories:

– 24 KByte Code Scratch-Pad RAM (CSRAM)

– 8 KByte Instruction Cache (ICACHE)

– 24 KByte Data Scratch-Pad RAM (DSRAM)

– 8 KByte Data Cache (DCACHE)

– 64 KByte fast LMB SRAM

– 16 KByte FPI SRAM (of which 8 KByte Stand-By SRAM)

• Product Specific Peripherals:

– 14-bit double CODEC with flexible sample rates and FIFO support

– 8 External Interrupt Inputs

• Standard Peripherals:

– 2 x asynchronous serial interface (ASC) with IrDa-support

– 1 SPI-compatible synchronous serial interface

– IIC module

– 3 x 32 bit timer

• General Peripherals:

– Real time clock (RTC)

– Watchdog timer (WDT)

• Clock Generation Unit with PLL

• Debug Support: OCDS Level 1 with JTAG interface

• Dual voltage supply (1.8V core, 3.3V I/O)

• Power saving features

• -40°C to +85°C temperature range

• LBGA-208 package

Data Sheet

1

V 1.0, 2003-10

TC1910

PRELIMINARY

Block Diagram.

LFI

Bridge

SRAM

64 kB

EBU

CODEC

(IIS)

64-bit Local Memory Bus (LM B)

IIC

GPTU

PMU

DMU

24KB

D SRAM

8KB

ASC0

ASC1

SSC

24KB

CSRAM

8KB

TriCore

(TC1.3)

Port

Control

ICACHE

DCACHE

CPS

OCDS

Debug/

JTAG

32-bit Flexible Peripheral Interface (FPI)Bus

SRAM

16kB

RTC

STM

SCU

TC1910

Figure 1

TC1910 Device Block Diagram

Target applications

• Bluetooth gateway (host for BT stack e.g. for Handsfree with EC/NR or remote

diagnostics)

• Stand-alone speech Human Machine Interface

• Basic communication gateway

• Digital Audio processing (MP3 player, shock proof controller etc.)

Data Sheet

2

V 1.0, 2003-10

TC1910

PRELIMINARY

Logic Symbol

GPIO /EXIx,

PLL_CTRL

Port 0

8-bit

Codec Bypass

TEST

Port 1

8-bit

GPIO

CLKOU T

G eneral

Control

IIC, SSC

Port 2

16-bit

HDRST

PO RST

ASC 0

ASC 1

GPTU

Port 3

16-bit

NMI

BYPASS

XTAL1

XTAL2

XTAL3

10

CO DEC 0/1

External Bus

XTAL4

V_{DDO SC 1}

O scillators

PLL

83

V_{SSO S C1}

V_{DDO SC 2}

V_{SSO S C2}

V_DDPLL

TC1910

V_SSPLL

8

O CD S/JTAG

Control

V_{D D}

V_DDP

V_{DD SB}

V_SS

D igital C ircuitry

Pow er Supply

V_{DD_CO D0}

V_{SS_CO D0}

V_{DD_CO D1}

V_{SS_CO D1}

V_{REF_CO D}

V_{G ND_CO D}

CO DEC

Analog Power

Supply

Figure 2

TC1910 Device Logic Symbol

Data Sheet

3

V 1.0, 2003-10

TC1910

PRELIMINARY

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

V_{DD _}

V_{S S}

_

V_{DD _}

V_{D D_}V_{S S A _}

BY

PASS

CLK

OU T

AD20

AD 26 AD 28

P2.3

AD 29

XTAL1 XT AL2

N MI

P2.0

A

B

C

D

E

F

A

B

C

D

E

F

R TC

PL L

P LL

C OD 0/1 C OD 0/1

V_{S SA}V_{D DP _}V _{SS P}

_

V_{D D}_

AD 25

AD17

AD 27

AD 24

AD 30

AD 31

AI0-

AI1-

AO1+ AO0- H R ST EXIN4 P2.5 P3.15

_32K

P LL

GU A RD

T M_

C TR L1

IIC _

SD A

TM _

C T RL0

V_{S S}

_

V_{A GN D _}

C ODE POR S SSC _

C _DIS

AD13 AD 23

XTAL4

AI1+ AO0+

V_{A RE F_}

EXIN 7

T

M TSR

GU A RD

C O D

V_{D D _}

V_{D D _}PLLC T

V_{DD _}SSC _ A SC0_ ASC 1_

AD 9

AD 8

AD 7

AD 5

AD 2

AD 21 AD 22

XTAL3 V_{D D R}

A I0+

AO1- CE XT

R L_A0

SC LK

R X

TX

P W R

O S C I

CO D

P W R

SSC _ ASC 0_ IIC _

AD 18 AD 16 AD 19

AD 15 AD 14 AD 12

P3.11

M RST

P 2.8

TX

SC L

P2.9

P2.4 EXIN 5

V_{D D _}

V_{S S _}

V _{SS _}

V_{D D_}

AD 11 AD 10

AD 6

AD 0

A21

A19

A13

A11

P 2.1

P2.2 EXIN 6 P3.10

G

H

J

G

H

J

P W R 2

G N D

P W R2

V_{D D _}

V_{S S _}

V _{SS _}

GPT U . GPTU . GPTU . ASC 1_

HS5

HS4

AD4

AD1

A22

A18

A14

A9

AD 3

A23

A20

A16

A12

A8

4

5

7

R X

P W R

G N D

V_{S S _}

V _{SS _}

E BU

C LK

SC AN

MOD E

GPT U .

0

GPTU . GPTU .

6

H S15

3

G N D

V_{D D _}

V_{D D_}

BF

CLK0

GPTU . GPTU .

2

H S14 H S13

LR C K MU TE1

K

L

K

L

1

P W R 2

P W R2

A17

A15

A10

A7

M UT E0

V_{D DS B}EXIN3 SC LK

EXIN 2

P1.6

P 1.7 EXIN0 EXIN 1

V_{DD _}

M

N

P

R

T

M

N

P

R

T

V_{D D _}

R AS

BC0

C S1 C SGLB A DV

P1.4

P1.0

TD O

P1.5

P1.2

TC K

H S11

H S10

ALE

H S7

H S6

H S8

H S0

P W R

BR K

OU T

A6

A5

A 1 R D /W R CS6

C S2

C S0

BAA

C KE

TMS

P1.3

C S

EMU

B RK

IN

A4

A3

A0

R D

BC 1

CS4

MR /W

C M

H S2

P1.1

C S

A2

1

C AS

2

BC 3

3

BC 2

4

C S5

5

CS3

6

W AIT

7

O CDSE

14

TR ST

16

TD I

15

H S12

10

H S9

11

H S3

12

H S1

13

OVL D ELAY

8

9

TO P VIEW

LBG A 208

Figure 3

TC1910 Pinning

Data Sheet

4

V 1.0, 2003-10

TC1910

PRELIMINARY

Pin List

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

External Bus Unit Interface

external address/data bus (multiplexed bus mode) or

data bus (demultiplexed bus mode) for the EBU:

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

H4

J2

I/O,s AD0

I/O,s AD1

I/O,s AD2

I/O,s AD3

I/O,s AD4

I/O,s AD5

I/O,s AD6

I/O,s AD7

I/O,s AD8

I/O,s AD9

I/O,s AD10

I/O,s AD11

I/O,s AD12

I/O,s AD13

I/O,s AD14

I/O,s AD15

I/O,s AD16

I/O,s AD17

I/O,s AD18

I/O,s AD19

I/O,s AD20

I/O,s AD21

I/O,s AD22

I/O,s AD23

I/O,s AD24

I/O,s AD25

I/O,s AD26

I/O,s AD27

I/O,s AD28

I/O,s AD29

I/O,s AD30

I/O,s AD31

Address/data bus / Data bus line 0

Address/data bus / Data bus line 1

Address/data bus / Data bus line 2

Address/data bus / Data bus line 3

Address/data bus / Data bus line 4

Address/data bus / Data bus line 5

Address/data bus / Data bus line 6

Address/data bus / Data bus line 7

Address/data bus / Data bus line 8

Address/data bus / Data bus line 9

Address/data bus / Data bus line 10

Address/data bus / Data bus line 11

Address/data bus / Data bus line 12

Address/data bus / Data bus line 13

Address/data bus / Data bus line 14

Address/data bus / Data bus line 15

Address/data bus / Data bus line 16

Address/data bus / Data bus line 17

Address/data bus / Data bus line 18

Address/data bus / Data bus line 19

Address/data bus / Data bus line 20

Address/data bus / Data bus line 21

Address/data bus / Data bus line 22

Address/data bus / Data bus line 23

Address/data bus / Data bus line 24

Address/data bus / Data bus line 25

Address/data bus / Data bus line 26

Address/data bus / Data bus line 27

Address/data bus / Data bus line 28

Address/data bus / Data bus line 29

Address/data bus / Data bus line 30

Address/data bus / Data bus line 31

H1

H3

H2

G1

G4

F1

E1

D1

G3

G2

F4

C1

F3

F2

E3

B1

E2

E4

A1

D2

D3

C2

C3

B2

A2

B3

A3

A4

B4

C4

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

Data Sheet

5

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

External Bus Unit Interface (continued)

external address bus for the EBU or chip select

output lines.

A0

A1

A2

A3

A4

A5

A6

A7

R3

P4

T1

R2

R1

P3

P2

P1

N3

N2

N1

M4

M3

L4

I/O,s A0

I/O,s A1

I/O,s A2

I/O,s A3

I/O,s A4

I/O,s A5

I/O,s A6

I/O,s A7

I/O,s A8

I/O,s A9

I/O,s A10

I/O,s A11

I/O,s A12

I/O,s A13

I/O,s A14

I/O,s A15

I/O,s A16

I/O,s A17

I/O,s A18

I/O,s A19

I/O,s A20

I/O,s A21

I/O,s A22

I/O,s A23

Address bus line 0

Address bus line 1

Address bus line 2

Address bus line 3

Address bus line 4

Address bus line 5

Address bus line 6

Address bus line 7

Address bus line 8

Address bus line 9

Address bus line 10

Address bus line 11

Address bus line 12

Address bus line 13

Address bus line 14

Address bus line 15

Address bus line 16

Address bus line 17

Address bus line 18

Address bus line 19

Address bus line 20

Address bus line 21

Address bus line 22

Address bus line 23

Chip select output 0

Chip select output 1

Chip select output 2

Chip select output 3

Chip select output 4

Chip select output 5

Chip select output 6

Chip select for emulator region

Chip select for emulator overlay

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CSEMU

CSOVL

M2

M1

L3

L1

L2

K4

K3

J4

K2

J3

R7

N7

P7

T6

R6

T5

P6

R8

T8

O,u

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CSEMU

CSOVL

memory

Data Sheet

6

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

External Bus Unit Interface (continued)

control bus for the EBU control lines.

RD

RD/WR

ALE

ADV

BC0

BC1

BC2

BC3

WAIT

BAA

EBUCLK

BFCLK0

CSGLB

CMDELAY

MR/W

CKE

R4

P5

R10

N9

N6

R5

T4

T3

T7

P8

J1

K1

N8

T9

R9

P9

N5

T2

I/O,u RD

I/O,u RD/WR

Read control line

Write control line

O,d

O,u

ALE

ADV

Address latch enable

Address valid output

Byte control line 0

Byte control line 1

Byte control line 2

Byte control line 3

Wait input

Burst address advance output

External Bus Clock

Additional clock

I/O,u BC0

I/O,u BC1

I/O,u BC2

I/O,u BC3

I/O,u WAIT

O,u

I,u

BAA

EBUCLK

BFCLK0

CSGLB

Chip Select Global

CMDELAY Command Delay

O,u

MR/W

CKE

RAS

CAS

Motorola-style Read/Write

Clock Enable

Row Address Strobe

Column Address Strobe

RAS

CAS

P0

Port 0

Port 0 is an 8-bit general purpose I/O port, overlaid

with codec digital signals and external interrupt

inputs (P0.[3:0]).

P0.0

P0.1

P0.2

M14

M15

M16

I/O

EXI0IN

EXI1IN

EXI2IN

External Interrupt Input 0

External Interrupt Input 1 or DATA_IN

External Interrupt Input 2 or

DATA_OUT

P0.3

P0.4

P0.5

P0.6

P0.7

L14

L15

K13

L16

K14

I/O

EXI3IN

SCLK

LRCK

MUTE0

MUTE1

External Interrupt Input 3 or MCLK

Data Sheet

7

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

P1

Port 1

Port 1 is a 8-bit bidirectional General Purpose I/O

port

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P14

R16

P15

P16

N14

N15

N16

M13

I/O

GPIO only

P2

Port 2

Port 2 is a 16-bit bidirectional general purpose I/O

port and input/output for serial interfaces (IIC, ASC0,

SSC)

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

A16

G13

G14

A15

F15

B15

E15

C15

F13

F14

D15

E14

D14

E13

C14

B14

I/O

GPIO only

SCL

SDA

Open Drain GPIO

RXD0

TXD0

SCLK

MRST

MTSR

IIC Serial Port Clock

IIC Serial Port Data

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

ASC0 receiver input/output

ASC0 transmitter output

SSC clock line

SSC Master Receive / Slave Transmit

SSC Master Transmit / Slave Receive

GPIO/EXI4IN/PLL_CLC.LOCK Monitoring of the

PLL_CLC.LOCK

Data Sheet

8

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

P3

Port 3

Port 3 is a 16-bit bidirectional general purpose I/O

port which is also used as input/output for serial

interfaces (ASC1) and timer (GPTU)

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

J13

I/O

GPTU.0

GPTU.1

GPTU.2

GPTU.3

GPTU.4

GPTU.5

GPTU.6

GPTU.7

RXD1

GPTU I/O line 0

GPTU I/O line 1

GPTU I/O line 2

GPTU I/O line 3

GPTU I/O line 4

GPTU I/O line 5

GPTU I/O line 6

GPTU I/O line 7

K16

K15

J16

H13

H14

J15

H15

H16

D16

G16

E16

F16

G15

C16

B16

P3.8

P3.9

ASC1 receiver input/output

ASC1 transmitter output

TXD1

GPIO only

P3.10

P3.11

P3.12

P3.13

P3.14

P3.15

GPIO only / OSCBYP Latch-In Input Pin

EXI5IN/ HWCFG0 Latch-InExternal Interrupt Input 5

EXI6IN/ HWCFG1 Latch-InExternal Interrupt Input 6

EXI7IN/ HWCFG2 Latch-InExternal Interrupt Input 7

GPIO only

CODEC

AI0+

AI0-

D9

B9

I

CODEC 0 Non-Inverting Input

CODEC 0 Inverting Input

AO0+

AO0-

AI1+

AI1-

AO1+

AO1-

C11

B12

C10

B10

B11

D11

D12

C12

O

I

CODEC 0 Non-Inverting Output

CODEC 0 Inverting Output

CODEC 1 Non-Inverting Input

CODEC 1 Inverting Input

CODEC 1 Non-Inverting Output

CODEC 1 Inverting Output

Codec External Clock Input

Codec Disable (power saving)

I

O

I

CEXT

CODEC_DIS

I

Data Sheet

9

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

DEBUG

DEBUG (OCDS/JTAG Control)

TRST

TCK

TDI

TDO

TMS

OCDSE

BRKIN

BRKOUT

T16

R15

T15

R14

P13

T14

R13

P12

I,d

I,u

O

I,u

O

Reset/module enable

JTAG clock input

Serial data input

Serial data output

State machine control signal

OCDS enable input

OCDS break input

OCDS break output

Test

Test Pins

SCAN_MODE J14

PLLCTRL_AO D8

I

Scan Mode

Control current of different analog stages

Test Mode Control 0

Test Mode Control 1

TM_CTRL0

TM_CTRL1

C7

C5

Reserved Pins

Reserved Internal Test and Heat Sink Pins.

Must be routed as isolated pads on the PCB.

Heat Sink 0

Heat Sink 1

Heat Sink 2

Heat Sink 3

Heat Sink 4

Heat Sink 5

Heat Sink 6

Heat Sink 7

HS0

HS1

HS2

HS3

HS4

HS5

HS6

HS7

N12

T13

R12

T12

J10

H10

P11

N11

R11

T11

P10

N10

T10

K9

IO

HS8

HS9

Heat Sink 8

Heat Sink 9

HS10

HS11

HS12

HS13

HS14

HS15

Heat Sink 10

Heat Sink 11

Heat Sink 12

Heat Sink 13

Heat Sink 14

Heat Sink 15

K8

J7

BYPASS

NMI

A12

A13

B13

I,d

I,u

PLL Bypass Control Input

Non-Maskable Interrupt Input

HRST

I/O,u Bidirectional Hardware Reset

Data Sheet

10

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

PORST

C13

A14

I,u

O

Power-on Reset Input (must be active during power

up)

CLKOUT

CPU Clock Output

XTAL1

XTAL2

A6

A7

I

O

PLL/Oscillator Input/Output

XTAL3

XTAL4

D5

C6

I

O

Real Time Clock Oscillator input/output (32 KHz)

V

D10

C9

A10

A11

B8

-

Codec 0,1 Reference Voltage

Codec 0,1 Reference Ground

Codec Pad and Analog Power Supply (3.3V)

Codec Pad and Analog Ground

Guard Ring Supply (1.8V)

AREF_COD

AGND_COD

DD_COD0/1

SSA_COD0/1

DD_GUARD

SS_GUARD

DD_OSCI

DD_RTC

SSA_32K

DDP_PLL

SSP_PLL

DDPLL

C8

D7

A5

Guard Ring Ground (1.8V)

Main Oscilator Power Supply (1.8V)

RTC Oscilator Core Supply (1.8V)

RTC and Main Osc. Core Ground (1.8V)

RTC and Main Osc. Supply (3.3V)

RTC and Main Osc. Ground (3.3V)

PLL Supply (1.8V)

B5

B6

B7

A9

A8

PLL Ground (1.8V)

SSPLL

D6

L13

SRAM Power Supply (1.8V)

SRAM Stand-By Power Supply (1.8V)

3.3V Power Supply

DDR

DDSB

D4

D13

H7

N4

N13

-

DD_PWR

V

G7

G10

K7

-

1.8V Power Supply

DD_PWR2

K10

Data Sheet

11

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 0-1

Symbol

Pin Definitions and Functions

BGA

In/

Functions

1)

BALL Out

V

G8

G9

H8

H9

J8

-

Digital Power Ground

SS_GND

J9

1)

The notification ’,u’ after the input/output type defines an internal pull-up resistor. An internal pull-down resistor

is indicated by ’,d’. For the lines AD[31:0] and A[23:0], the type of the pull device can be selected ’s’.

Data Sheet

12

V 1.0, 2003-10

TC1910

PRELIMINARY

System Architecture and Control

32-Bit TriCore CPU

• 32-bit architecture with 4-GByte unified data, program and input/output address space

• Fast automatic context-switch

• Dual 16 x 16 Multiply-accumulate (MAC) unit

• Saturating integer arithmetic

• Register based design with multiple variable register banks

• Bit handling

• Packed data operations

• Zero overhead loop

• Precise exceptions

• Flexible power management

Instruction Set with High Efficiency:

• 16/32-bit instructions for reduced code size

• Little endian byte ordering with support for big and little endian byte ordering at bus

interface

• Boolean, array of bits, character, signed and unsigned integer, integer with saturation,

signed fraction, double word integers and IEEE-754 single precision floating-point

data types

• Bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats

• Powerful instruction set

• Flexible and efficient addressing mode for high code density

Data Sheet

13

V 1.0, 2003-10

TC1910

PRELIMINARY

On-chip Code Memories

Local Memory Bus Memory (LMBRAM):

Address range of the 64 KByte Local Memory Bus Memory:

• C000 0000 - C000 FFFF (in segment 12 for cached operation)

H

• E800 0000 - E800 FFFF (in segment 14 for non-cached operation)

H

PMU Scratch-Pad SRAM (CSRAM):

The Program Memory Unit (PMU) memory consists of 24-KByte Code Scratchpad RAM

(CSRAM) and 8-KByte Instruction Cache (ICACHE).

Address range of the CSRAM:

• D400 0000 - D400 5FFF

H

On-chip Data Memories

DMU Scratch-Pad SRAM (DSRAM):

The Data Memory Unit (DMU) memory consists of 24-KByte Data Scratchpad RAM

(DSRAM) and 8-KByte Data Cache (DCACHE).

Address range of the DSRAM:

• D000 0000 - D000 5FFF

H

FPI-Bus Data Memory (FPIDRAM):

The FPI-Bus Data Memory (FPIDRAM) is a 16-KByte static RAM located on the FPI-

Bus. It contains two parts: FPIDRAM0 and FPIDRAM1. One half of it (FPIDRAM1) can

be used for standby power operation.

Address range of the FPI Data Memory:

• 9FFF 8000 - 9FFF BFFF (in segment 9 for cached operation)

H

• BFFF 8000 - BFFF BFFF (in segment 11 for non-cached operation)

H

Data Sheet

14

V 1.0, 2003-10

TC1910

PRELIMINARY

System Control Unit (SCU)

The System Control Unit of the TC1910 basically handles all system control tasks. All

these system functions are tightly coupled and therefore they are handled physically by

one unit, the SCU. The system tasks of the SCU are:

• Clock Generation and Control

• Reset control

• Power Management control and wake-up

• Watchdog timer

• Device identification

• Standby SRAM control

• External interrupt capability (8 sources)

System timer (STM)

The System Timer is designed for global system timing applications requiring both high

precision and long range. It is used by the CPU for software operating system issues.

Features:

• Free-running 56-bit counter

• All 56 bits can be read synchronously

• Different 32-bit portions of the 56-bit counter can be read synchronously

• Driven by clock, f

(normally identical with the system clock).

STM

• Counting begins at power-on reset

• Continuous operation is not affected by any reset condition except power-on reset

External Bus Interface (EBU_LMB)

EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1910 and also to the

FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus.

Any LMB masters thus can access external memories or devices through EBU_LMB.

Currently the maximum length of the bursts are according to the size of program and

data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8-

bit, 16-bit and 32-bit wide access.

Data Sheet

15

V 1.0, 2003-10

TC1910

PRELIMINARY

EBU_LM B

XBC

LM B Bus 64-bit

Buffer

SDRAM

Slower

Devices

50 M Hz

DM E

XM I

FPI Bus 32-bit

External

M aster

External Bus Unit

EBUL3045_L

Figure 4

EBU_LMB block diagram

Features supported in EBU_LMB:

• Local Memory Bus (LMB 64-bit) support.

• External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4.

• Highly programmable access parameters.

• Intel-style and Motorola-style peripheral/device support.

• SDRAM support (burst access, multibanking, precharge, refresh).

• 16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices.

• Burst flash support.

• Multiplexed access (address & data on the same bus) when DRAM is not present on

the External Bus.

• Data Buffering: Code Prefetch Buffer, Read/Write Buffer.

• External master arbitration (compatible to C166 and other TriCore devices).

• 8 programmable address regions (1 dedicated for emulator).

• Little-Endian and Big-Endian support.

• CSglb signal, dedicated pin, bit programmable to combine one or more CS lines, for

buffer control.

• RMW signal reflecting a read-modify-write action.

• Signal for controlling data flow of slow-memory buffer.

• Slave unit for external (off-chip) master to access devices on the FPI bus.

• Master unit for FPI master to access external (off-chip) devices.

• Data Mover Engine.

Data Sheet

16

V 1.0, 2003-10

TC1910

PRELIMINARY

Interrupt System

• Flexible interrupt prioritizing scheme with 256 interrupt priority levels

• Fast interrupt response

C PU Interrupt

Arbitration Bus

Module A

n Service

M odule

Request

Nodes

Kernel

M ain Interrupt Control

CPU

Interrupt

C ontrol

Unit

Module B

n Service

M odule

Kernel

CPU

Core

(ICU)

Request

Nodes

4 Service

Request

Nodes

4

Module C

n Service

Request

Nodes

M odule

Kernel

Figure 5

Block Diagram Interrupt System

Data Sheet

17

V 1.0, 2003-10

TC1910

PRELIMINARY

FPI-Bus

The Flexible Peripheral Interconnect Bus is designed with the requirements of high-

performance Systems-on-Chip in mind.

Key Features:

• Core independent

• Multi-master capability

• Demultiplexed operation

• Clock synchronous

• Peak transfer rate of up to 200 MBytes/s (@ 50 MHz bus clock)

• Address and data bus scalable (32 bit address bus, 32 bit data bus )

• 8-/16- and 32 bit data transfers

• Broad range of transfer types from single to multiple data transfers

• Burst transfer capability

• EMI and power consumption minimized

LMB-Bus

The Local Memory Bus is a synchronous, pipelined, split bus with variable block size

transfer support. All signals relate to the positive clock edge.

The protocol supports 8,16,32 & 64 bits single beat transactions and variable length 64

bits block transfers.

Key Features:

The LMB provides the following features:

• Optimized for high speed and high performance

• 32 bit address, 64 bit data busses

• Central simple per cycle arbitration

• Slave controlled wait state insertion

• Address pipelining (max depth - 2)

• Split transactions

• Variable block length - 2, 4 or 8 beats of 64 bit data

Data Sheet

18

V 1.0, 2003-10

TC1910

PRELIMINARY

On-Chip Debug System (OCDS)

The TC1910 architecture is supporting OCDS Level 1. This means access to FPI Bus

and the whole FPI address space via the JTAG interface pins.

On-Chip Peripheral Units

The TC1910 offers several on-chip peripheral units such as serial controllers, timer units,

and Codec module. Within the TC1910 all these peripheral units are connected to the

TriCore CPU/system via the FPI (Flexible Peripheral Interconnect) Bus. Several IO lines

on the TC1910 ports are reserved for these peripheral units to communicate with the

external world.

Peripheral Units of the TC1910:

• Three Asynchronous/Synchronous Serial Channels with baudrate generator, parity,

framing and overrun error detection, IrDA mode, FIFO buffers.

• One High Speed Synchronous Serial Channels with programmable data length and

shift direction

• IIC module

• One multi-functional General Purpose Timer Units with three 32-bit timer/counter

• Dual channel Codec interface

• GPIO blocks

Table 1

Module

Peripheral Modules

Address Range

I/O Lines

Interrupt Nodes

Asynchronous

Serial Channel 0

(ASC0)

F000 0A00 -

RDX0, TDX0

ASC0_TSRC

ASC0_RSRC

ASC0_ESRC

ASC0_TBSRC

H

F000 0AFF

H

Asynchronous

Serial Channel 1

(ASC1)

F000 0B00 -

RDX1, TDX1

ASC1_TSRC

ASC1_RSRC

ASC1_ESRC

ASC1_TBSRC

H

F000 0BFF

H

Synchronous Serial F000 0800 -

SCLK, MRST,

MTSR

SSC_TSRC

SSC_RSRC

SSC_ESRC

H

Channel (SSC)

F000 08FF

H

Inter-IC Bus (IIC)

F000 0500 -

SCL,

SDA

IIC_XP0SRC

IIC_XP1SRC

IIC_XP2SRC

H

F000 05FF

H

Real Time Clock

(RTC)

F000 0100 -

-

RTC_SRC

H

F000 01FF

H

Data Sheet

19

V 1.0, 2003-10

TC1910

PRELIMINARY

Table 1

Module

Peripheral Modules (cont’d)

Address Range

I/O Lines

Interrupt Nodes

System Timer Unit F000 0300 -

-

H

(STM)

F000 03FF

H

General Purpose

Timer (GPTU)

F000 0700 -

GPTU

GPTU_SRC0..7

H

F000 07FF

H

Speech Interface

(Codec)

F000 2400 -

2*2 analog IN,

2*2 analog OUT,

CEXT,

CODEC_SRC0..5

H

F000 24FF

H

CODEC_DIS

Data Sheet

20

V 1.0, 2003-10

TC1910

PRELIMINARY

Asynchronous/Synchronous Serial Interfaces (ASC 0/1)

The Asynchronous/Synchronous Serial Interface ASC provides serial communication

between the TriCore and other microcontrollers, microprocessors or external

peripherals.

Features:

• Full duplex asynchronous operating modes

– 8- or 9-bit data frames, LSB first

– Parity bit generation/checking

– One or two stop bits

– Baudrate from 3.125 MBaud to 0.74 Baud (@ 50 MHz module clock)

– Multiprocessor mode for automatic address/data byte detection

– Loop-back capability

• Half-duplex 8-bit synchronous operating mode

– Baudrate from 6.25 MBaud to 637 Baud (@ 50 MHz module clock)

• Double buffered transmitter/receiver

• Interrupt generation

– on a transmitter buffer empty condition

– on a transmit last bit of a frame condition

– on a receiver buffer full condition

– on an error condition (frame, parity, overrun error)

• Support for IrDA

• Automatic Baudrate Detection

• 8 Byte FIFO

f_{hw _clk}

C lock

C ontrol

Address

Decoder

RXD

TXD

ASC

M odule

(Kernel)

Port

Control

TXD

TIR

TBIR

R IR

Interrupt

C ontrol

EIR

ABSTIR

ABDETIR

M CA 05253

Figure 6

General Block Diagram of the ASC Interface

Data Sheet

21

V 1.0, 2003-10

TC1910

PRELIMINARY

High-Speed Synchronous Serial Interface (SSC)

The High Speed Synchronous Serial Interface SSC provides serial communication

between microcontrollers, microprocessors or external peripherals. The SSC supports

full-duplex and half-duplex synchronous communication up to 25 MBaud (@ 50 MHz

module clock). The serial clock signal can be generated by the SSC itself (master mode)

or be received from an external master (slave mode). Data width, shift direction, clock

polarity and phase are programmable. This allows communication with SPI-compatible

devices. Transmission and reception of data are double-buffered. A 16-bit baud rate

generator provides the SSC with a separate serial clock signal.

Features:

• Master and slave mode operation

– Full-duplex or half-duplex operation

• Flexible data format

– Programmable number of data bits : 2 to 16 bit

– Programmable shift direction : LSB or MSB shift first

– Programmable clock polarity : idle low or high state for the shift clock

– Programmable clock/data phase : data shift with leading or trailing edge of SCLK

• Maximum baudrate: 25 MBaud in Master, 12.5 in Slave mode (@ 50 MHz module

clock)

Interrupt generation

– on a transmitter empty condition

– on a receiver full condition

– on an error condition (receive, phase, baudrate, transmit error)

• Three pin interface

f_{hw_clk}

C lock

C ontrol

R XD

M TSR

M R ST

SCLK

TXD

Address

Decoder

SSC

M odule

(Kernel)

R XD

TXD

Port

Control

EIR

R IR

TIR

Slave

M aster

Interrupt

C ontrol

M C B04505_m od

Figure 7

General Block Diagram of the SSC Interface

Data Sheet

22

V 1.0, 2003-10

TC1910

PRELIMINARY

Inter-IC Interface (IIC)

IIC supports a certain protocol to allow devices to communicate directly with each other

via two wires. One line is responsible for clock transfer and synchronization (SCL), the

other is responsible for the data transfer (SDA).

The on-chip IIC Bus module connects the platform buses to other external controllers

and/or peripherals via the two-line serial IIC interface. The IIC Bus module provides

communication at data rates of up to 400 kBit/s and features 7-bit addressing as well as

10-bit addressing. This module is fully compatible to the IIC bus protocol.

The module can operate in three different modes:

Master mode, where the IIC controls the bus transactions and provides the clock signal.

Slave mode, where an external master controls the bus transactions and provides the

clock signal.

Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can

be master or slave.

The on-chip IIC bus module allows efficient communication via the common IIC bus. The

module unloads the CPU of low level tasks like:

• (De)Serialization of bus data.

• Generation of start and stop conditions.

• Monitoring the bus lines in slave mode.

• Evaluation of the device address in slave mode.

• Bus access arbitration in multimaster mode.

IIC Features:

• Extended buffer allows up to 4 send/receive data bytes to be stored.

• Selectable baud rate generation.

• Support of standard 100 kBaud and extended 400 kBaud data rates.

• Operation in 7-bit addressing mode or 10-bit addressing mode.

• Flexible control via interrupt service routines or by polling.

Data Sheet

23

V 1.0, 2003-10

TC1910

PRELIMINARY

Timer Unit (GPTU)

Figure 8 shows a global view of all functional blocks of the GPTU module.

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IO 0

IO 1

IO 2

IO 3

IO 4

IO 5

IO 6

IO 7

P0.0 / G PT0

f_{G PTU}

C lock

C ontrol

P0.1 / G PT1

P0.2 / G PT2

P0.3 / G PT3

P0.4 / G PT4

P0.5 / G PT5

P0.6 / G PT6

Address

Decoder

G PTU

M odule

(Kernel)

Port

C ontrol

SR0

SR1

SR2

SR3

SR4

SR5

SR6

SR7

O U T0

O U T1

O U T2

O U T3

O U T4

O U T5

O U T6

O U T7

Interrupt

C ontrol

P0.7 / G PT7

M CB05052_m odified

Figure 8

General Block Diagram of the GPTU Interface

The GPTU consists of three 32-bit timers designed to solve such application tasks as

event timing, event counting, and event recording. The GPTU communicates with the

external world via eight inputs and eight outputs.

The three timers of the GPTU module T0, T1, and T2, can operate independently from

each other, or can be combined:

General Features:

• All timers are 32-bit precision timers with a maximum input frequency of f

• Events generated in T0 or T1 can be used to trigger actions in T2

• Timer overflow or underflow in T2 can be used to clock either T0 or T1

• T0 and T1 can be concatenated to form one 64-bit timer

/2.

GPTU

Features of T0 and T1:

• Each timer has a dedicated 32-bit reload register with automatic reload on overflow

• Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload

registers

• Overflow signals can be selected to generate service requests, pin output signals, and

T2 trigger events

• Two input pins can determine a count option

Data Sheet

24

V 1.0, 2003-10

TC1910

PRELIMINARY

Features of T2:

• Optionally count up or down

• Operating modes:

– Timer

– Counter

– Incremental Interface Mode

• Options:

– External start/stop, one-shot operation, timer clear on external event

– Count direction control through software or an external event

– Two 32-bit reload/capture registers

• Reload modes:

– Reload on overflow or underflow

– Reload on external event: positive transition, negative transition, or both transitions

• Capture modes:

– Capture on external event: positive transition, negative transition, or both

transitions

– Capture and clear timer on external event: positive transition, negative transition, or

both transitions

• Can be split into two 16-bit counter/timers

• Timer count, reload, capture, and trigger functions can be assigned to input pins. T0

and T1 overflow events can also be assigned to these functions.

• Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle

output pins

• T2 events are freely assignable to the service request nodes.

Real Time Clock Unit RTC

The Real Time Clock (RTC) module is basically an independent timer chain and counts

clock ticks. The base frequency of the RTC can be programmed via a reload counter.

The RTC can work fully asynchronous to the system frequency and is optimized on low

power consumption.

Features:

The RTC serves different purposes:

• Absolute system clock to determine the current time and date

• Cyclic time based interrupt

• Alarm interrupt for wake up on a defined time

• 48-bit timer for long term measurements

Data Sheet

25

V 1.0, 2003-10

TC1910

PRELIMINARY

Codec Interface

The speech A/D and D/A converters (called codec) is designed for telephone and

speech recognition quality. They can be used for microphone / earpiece applications.

The TC1910 configuration implements a dual channel speech codec connected to the

FPI bus.

V_DDV_{S S}

V_DDV_SS

CO D0

COD0

CO D1 CO D1

ch0 non-inv. input

ch0 inv. input

AI0+

f_per

Clock

Control

AI0-

ch0 non-inv. output

ch0 inv. output

AO0+

AO0-

Address

Decoder

ch1 non-inv. input

ch1 inv. input

AI1+

AI1-

SR0

SR1

SR2

SR3

CO DEC

M odule

Kernel

ch1 non-inv. output

ch1 inv. output

AO1+

AO1-

Interrupt

Control

clock disable

SR4

SR5

CO DEC_DIS

CEXT

external clock input

m ute channel 0

m ute channel 1

V_{RE F}

M UTE0

M UTE1

COD

V_{G ND}

COD

Codec bypass

5

IIS

signals

Figure 9

General Codec Overview

General Purpose I/Os (GPIO)

• Push/pull output drivers

• 3.3 Volt operation for GPIO

• Programmable pull-up/-down devices at all pins

• Optional Open Drain Output Mode

Data Sheet

26

V 1.0, 2003-10

TC1910

PRELIMINARY

ID Register Table

Table 2

List of TC1910 ID registers

Short Name Description

Address

Reset Value

0019 C002

SCU_ID

MANID

CHIPID

RTID

SCU Identification Register

F000 0008

F000 0070

F000 0074

H

Manufacturer Identification Register

Chip Identification Register

0000 1820

0000 8902

0000 0000

H

Redesign Tracing Identification Register F000 0078

RTC_ID

BCU_ID

STM_ID

RTC Module Identification Register

BCU Identification Register

F000 0108

F000 0208

F000 0308

0000 5A04

0000 6A06

H

System Timer Module Identification

Register

0000 C002

H

JDP_ID

JTAG/OCDS Module Identification

Register

F000 0408

0000 6305

0000 4604

H

IIC_ID

IIC Module Identification Register

GPTU Module Identification Register

SSC Module Identification Register

ASC Module Identification Register

F000 0508

F000 0708

F000 0808

H

GPTU_ID

SSC_ID

ASC0_ID

ASC1_ID

0001 C002

H

0000 4503

H

F000 0A08

F000 0B08

0000 44E1

H

CODEC_ID Codec Identification Register

F000 2408

001C C002

H

CPS_ID

CPU_ID

EBU_ID

CPU Module Identification Register

CPU Identification Register

F7E0 FF08

0015 C004

H

F7E1 FE18

000A C003

H

EBU_LMB Module Identification

Register

F800 0008

0014 C003

H

DMU_ID

PMU_ID

LCU_ID

LFI_ID

DMU Identification Register

PMU Module Identification Register

LCU Identification Register

LFI Identification Register

F87F FC08

F87F FD08

0008 C002

H

000B C002

H

F87F FE08

F87F FF08

000F C003

000C C003

H

Data Sheet

27

V 1.0, 2003-10

TC1910

PRELIMINARY

Power Supply

Figure 10 shows the TC1910 power supply concept, where certain logic modules are

individually supplied with power. In this way, the noise margin is improved in the

especially sensitive modules, like the A/D converter and the CODEC.

V_{D DA}

V_{SS A}

V_{D DA}

V_SSA

V_{DD A}

V_SSA

V_{DD A}

V_SSA

V_{D DA}

V_{SS A}

V_{DD A}

V_SSA

RTC

OSC

PLL

(analog)

ADC

(analog)

CO DEC 0

(analog)

CO DEC 1

(analog)

M AIN

O SC

V_{D DP}

V_{SS P}

B attery

ALL DIG ITAL CORE

CO MPO NENTS

B acked

S tand- By

S RAM

X

V_{D DP}

V_{SS P}

Y

V_{D D_SB}

V_{D DR}

V_SS

V_DD

V_SS

V_{D D}

V_SS

Figure 10

TC1910 Power Supply Concept

Data Sheet

28

V 1.0, 2003-10

TC1910

PRELIMINARY

Power-Up Sequence

During Power-Up reset pin PORST has to be held active until both power supply

voltages have reached at least their minimum values.

During the Power-Up time (rising of the supply voltages from 0 to their regular operating

values) it has to be ensured, that the core V power supply reaches its operating value

DD

first, and then the GPIO V

power supply. During the rising time of the core voltage it

DDP

must be ensured that 0< V -V

<0.5 V.

DD DDP

During power-down, the core and GPIO power supplies V

and V

respectively,

DDP

DD

have to be switched off until all capacitances are discharged to zero, before the next

power-up.

Note: The states of the pins are undefined when only the port voltage V

is on.

DDP

Data Sheet

29

V 1.0, 2003-10

TC1910

PRELIMINARY

Electrical characteristics

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the TC1910

and partly its demands on the system. To aid in interpreting the parameters right, when

evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the TC1910 will provide signals with the respective characteristics.

SR (System Requirement):

The external system must provide signals with the respective characteristics to the

TC1910.

Data Sheet

30

V 1.0, 2003-10

TC1910

PRELIMINARY

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

min. max.

Unit Notes

Ambient temperature

Storage temperature

Junction temperature

T_A

-40

-65

–

85

°C

V

under bias

T_ST

T_J

150

125

4.2

Voltage on I/O Supply pins with V_DDP

respect to ground (V_SS)

-0.5

Voltage on Core Supply pins

with respect to ground (V_SS)

V_DD

-0.3

2.1

4.2

10

V

Voltage on PLL Supply pins

with respect to ground (V_SS)

V_DDPLL

V

PLL

Voltage between Oscillator

Supply Pins and ground (V_SS).

V_DDOSC-0.3

V

Voltage on any pin with respect V_IN

to ground (V_SS)

-0.5

-10

–

V

Input current on any pin during I

overload condition

mA

W

OV

Absolute sum of all input

currents at overload condition

ΣI

|100|

1.0

OV

Power dissipation

P_DISS

–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN>V_DDor V_IN<V_SS) the

voltage on V_DDpins with respect to ground (V_SS) must not exceed the values

defined by the absolute maximum ratings.

Data Sheet

31

V 1.0, 2003-10

TC1910

PRELIMINARY

Package Parameters (P-LBGA-208)

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

1.0

Power dissipation

Thermal resistance

P_DISS

R_THA

–

W

–

30

K/W Chip to ambient

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct

operation of the TC1910. All parameters specified in the following sections refer to these

operating conditions, unless otherwise noted.

Parameter

Symbol

Limit Values

min. max.

Unit Notes

1)

Supply voltage

V_DDP

V_DD

3.0

3.6

V

I/O supply

2)

1.71

1.89

V

Core supply

PLL supply

V_DDPLL

V

V_DDOSC1.71

V

Oscillator supply

Ground voltage

V_SS

0

V

Input current on any pin

during overload

condition

I

-5

–

5

mA

V

> V_DDP+ 0.3V

< V_SS- 0.3V

OV

Absolute sum of all input Σ| I

currents at overload

condition

|

|50|

85

mA

°C

OV

Ambient temperature

under bias

T_A

-40

CPU clock

f_CPU

C_L

–

66

50

MHz

pF

External Load

Capacitance

1)

Voltage overshoot to 4 V is permissible, provided the pulse duration is less than 100 µs and the cumulated

summary of the pulses does not exceed 1 h

2)

Voltage overshoot to 2 V is permissible, provided the pulse duration is less than 100 µs and the cumulated

summary of the pulses does not exceed 1 h

Data Sheet

32

V 1.0, 2003-10

TC1910

PRELIMINARY

DC Characteristics

GPIO pins

Parameter

Symbol

Limit values

Unit Test

Conditions

min.

max.

Output low voltage

(strong driver)

V

-

1

0.4

V

I

= 10 mA

= 2.5 mA

OL

OH

OL

OH

OL

OH

OL

Output high voltage

(strong driver)

2.4

-

I

= - 2.5 mA

OH

OL

OH

OL

OH

Output low voltage

0.4

-

= 1 mA

1)

(medium driver)

Output high voltage

2.4

-

= - 1 mA

= 100 µA

= - 100 µA

1)

(medium driver)

Output low voltage

0.4

-

1)

(weak driver)

Output high voltage

2.4

1)

(weak driver)

Input low voltage

Input high voltage

V

-0.3

2.0

0.8

V

LVTTL

IL

V

+0.3 V

whatever is

lower

IH

DDP

or

3.7V

Input leakage current

I

-

±500

nA

0V< V <

in

OZ1

V

DDP

OUT

2)

Pull-up current

|I

|

-

1

µA

pF

= 2.0V

= 0.8V

= 2.0V

PUH

3)

Pull-up current

|

20

-

PUL

PDL

Pull-down current

|

0.8

-

|

20

-

PDH

1)

Pin capacitance

C

10

f = 1MHz @

IO

o

T = 25 C

A

1)

Not subject to production test, verified by design/characterization.

2)

3)

The maximum current that may be drawn while the respective signal line remains inactive.

The minimum current that must be drawn in order to drive the respective signal line active.

Data Sheet

33

V 1.0, 2003-10

TC1910

PRELIMINARY

NMI Pin

NMI Pin is an input pin with different Pull-Up characteristics than other pins. The related

characteristics are given in the following table

Parameter

Symbol

Limit values

Unit Test

Conditions

min.

max.

Max. current allowed

through the Pull-Up

device while pin (input)

voltage remains still at the

high level

|I

|

-

4

uA

V

=2.0V

PUH

PUL

OUT

Min. current needed

|

100

-

uA

V

=0.8V

OUT

through the Pull-Up

device so that pin voltage

is driven to the low level.

Note: NMI Pin does not have a Pull-Down device.

Oscillator Pins

Parameter

Symbol Limit values

min.

Unit Test

Conditions

max.

Input leakage current

(analog input) at

XTAL1

I

-

±200

nA

0V< V < V

OZ1

in

DDP

CC

1)

Input low voltage

XTAL1

V

SR

-

0.3

V

-

ILX

Input high voltage

V

0.8

V

-0.3

-0.35

-0.4

f

=4MHz

=8MHz

=12MHz

=16MHz

IHX

DD

OSC

2)

XTAL1

SR

-0.43

XTAL1 input current

I

-

± 20

µA

0V < V < V

IN

IX1

DD

CC

2)

XTAL3 input current

I

± 0.5

0V < V < V

IN

IX3

DD

CC

1)

Only applicable in deep sleep mode

2)

Not subject to production test, verified by design/characterization.

Data Sheet

34

V 1.0, 2003-10

TC1910

PRELIMINARY

IIC Pins

Each IIC Pin is an open drain output pin with different characteristics than other pins. The

related characteristics are given in the following table

Parameter

Symbol

Limit values

Unit Test

Conditions

min.

max.

Output low voltage

V

CC

-

0.4

0.6

V

3 mA

6 mA

OL

1)

Input high voltage

V

0.7V

3.6

V

-

IH

DDP

SR

1)

Input low voltage

V

-0.3

0.3V

V

-

IL

DDP

SR

Input leakage current

I

-

+ - 500

10

nA

pF

OZ2

CC

1)

Pin capacitance

C

f=1MHz@

IO

o

CC

T =25 C

A

1)

Not subject to production test, verified by design/characterization.

Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.60

V must be applied to these pads.

Note: IIC pins have no Pull-Up and Pull-Down devices.

Data Sheet

35

V 1.0, 2003-10

TC1910

PRELIMINARY

Codec Electrical Characteristics

Parameter

Symbol Limit values

min. typ.

Unit

Test

Conditions

max.

1.89

3.6

Digital supply voltage

Analog supply voltage

Analog supply ground

V

1.71

3.0

1.8

3.3

0.0

1.2

V

DD

DDA

SSA

AREF

-0.1

1.14

+0.1

+1.26

1)

2)

External reference voltage V

Analog reference ground

V

0.05

- V

V

+

AGND

AIN

SSA

0.05

3)

Analog input voltage

(RMS)

0.775

-

V

rms

Analog output voltage

(RMS)

AOUT

Input Resistace of the

Analog Inputs

Rain

-

30

15

60

30

1.2

kOhm differential

input, gain:

4)

-12,-6, 0 dB

-

kOhm single-ended

input, gain:

-12,-6, 0 dB

-

kOhm differential

input, gain:

6 to 30 dB

-

kOhm single-ended

input, gain:

6 to 30 dB

Internal Reference

V

1.1

1.3

V

AGCCR.

BGPSEL[1,0]

=00

BGP

Voltage Vref (Bandgap

5)

Voltage)

1)

Reference voltage outside the nominal range causes reduced dynamic range, decreased distortion/clipping

margins, increased/decreased gain.

2)

3)

4)

5)

V_SSA=V_AGND=0V

Please take the gain settings of the analog preamplifier into account, therefore V_imaxreal=V_imax/gain

Simulation value.

For external usage, Bandgap reference voltage is strongly dependent on the external load (<500 MOhm). In

this case, high impedance buffer must be used.

Data Sheet

36

V 1.0, 2003-10

TC1910

PRELIMINARY

Codec ADC and DAC path characteristics

Test conditions¹⁾

Parameters

min.

typ.

max.

Unit

0

< 0.025

Attenuation distortion

(ref. freq. 1014 Hz)

(ref. level 0dBm0)²⁾

dB

-0.25

0

0.025-0.0375

0.0375-0.3

0.3-0.425

> 0.425

0.25

0.45

-55

-45

dB

at 0dBm0

Signal to total distor-

tion

-0.3

-0.6

-1.6

0.3

0.6

1.6

dB

+3 to -40 dBm0

-40 to -50 dBm0

-50 to -55 dBm0

Gain tracking

(ref. freq. 1014 Hz)

(ref. level 0dBm0)²⁾

-80

-75

dBm

0

receive &transmit

Idle channel noise

-80

-60

0

-75

-50

0.8

dB

Cross talk

at 0dBm0

Harmonic distortion

-0.8

-

receive &transmit

Gain

(ref. freq. 1014 Hz)

(ref. level 0dBm0)²⁾

3)

-60

-40

-35

dB

Receive (0.0375-0.425)

Transmit(0.0375-0.425)

Power supply

3)

rejection ratio (PSRR)

1)

2)

3)

Values given in this table are valid for all sampling frequencies.

0dBm0 is equivalent to -12dBm is equal to 194.7 mV_RMS.

Supply ripple 70 mV.

Note: Numbers without units in the test conditions column are relative frequency values

to the chosen sampling frequency. e.g. 0.425 equals 3.4 kHz @ 8 kHz sampling

frequency.

Data Sheet

37

V 1.0, 2003-10

TC1910

PRELIMINARY

Power Supply Current

Parameter

Symbol

Limit values

Unit

Test Conditions

1)

typ.

max.

Active mode supply

current

I_DD

180

–

mA

Sum of all I_DD.

Idle mode supply current I_ID

90

–

mA

at 1.8V Core Supply

Deep sleep mode supply I_DS

0.25

current

1)

Typical values are measured at 25°C, CPU clock at 66 MHz and nominal supply voltage, i.e. 3.3V for V_DDP

and 1.8V for V_DD, V_DDPLL, V_DDOSC

Note: The Power Supply Current values refer to the total current at 1.8V power supply,

at LMB/FPI bus frequency ratio of 2:1, while running an average application.

These numbers are estimation based on average device measurements.

Data Sheet

38

V 1.0, 2003-10

TC1910

PRELIMINARY

AC Characteristics

Operating Conditions apply.

Output Rise/Fall Times

GPIO pins

Rise/fall time measurements are made between 10% and 90%.

The following table is valid for the GPIO pins pad drivers. Output pad characteristics are

controllable via DRVCTRx registers.

Pad Modus

Symbol

Limit values

Temp Unit Test

rise / fall time

Comp

Conditions

min.

max.

Strong driver

• sharp edge

• medium edge

SF

SM

SS

-

3

6

12

yes

ns

@50pF

1)

• soft edge

1)

Not subject to production test, verified by design/characterization.

Data Sheet

39

V 1.0, 2003-10

TC1910

PRELIMINARY

Timing Characteristics

(Operating Conditions apply)

Note: Timing parameters are not subject to production test, they are verified by design/

characterization.

2.4V

2.0V

0.8V

2.0V

0.8V

Test Points

0.4V

M CT04880

AC inputs during testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”.

Timing measurements are made at V for a logic “1” and V for a logic “0”.

IHmin

ILmax

Figure 11

Input/Output Waveforms for AC Tests

- for GPIO, Dedicated and EBU pins

Data Sheet

40

V 1.0, 2003-10

TC1910

PRELIMINARY

External Oscillator at XTAL1 Timing Requirements

(Operating Conditions apply)

Parameter

Symbol

Limits

min. max.

Unit

1)

Main Oscillator XTAL frequency

with/without

PLL

f_OSCSR

4

16

MHz

3)

Frequency of an external oscillator with PLL

f_OSCDD

4

-

25

2)

4)

driving at XTAL1

without PLL

SR

Input Clock high time

Input Clock low time

Input Clock rise time

t₁

t₂

t₃

t₄

SR 16

−

7

ns

SR 16

SR −

Input Clock fall time

1)

Oscillator Bypass Pin P3.11 latch-in value high. Internal oscillator provides the input clock signal.

2)

Oscillator Bypass Pin P3.11 latch-in value low. Internal oscillator disabled. External oscillator provides the input

clock signal.

3)

4)

Internal PLL provides the system clock. BYPASS pin latch-in value low. PLL prescaler value P=1.

Internal PLL bypassed. BYPASS pin latch-in value high. External oscillator provides the system clock directly.

When CODEC modules is active its frequency limitations must be taken into consideration. Otherwise,

minimum frequency in this mode can go as low as zero.

t_OSC

V_{IH X}

Input C lock

at XTAL1

0.5 V_{DD OSC}

V_ILX

t₄

t₃

t₁

t₂

M CT04882

Figure 12

External Clock at XTAL1 Requirements

, V and V are defined in the Oscillator Pins DC Characteristics

Note: V

DDOSC

IHX

IHL

Chapter.

Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters

for the oscillator operation. Please refer to the limits specified by the crystal

supplier.

Data Sheet

41

V 1.0, 2003-10

TC1910

PRELIMINARY

CPU Clock Timing

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

CLKOUT period

t_CLKOUT15

−

ns

CC

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

t₁CC 6

t₂CC 6

t₃CC −

t₄CC −

−

3

ns

t_CPUCLK

0.9 V _DD

0.1 V _DD

0.5 V_DD

CLKOUT

t₄

t₃

t₁

t₂

M CT04883

Figure 13

CLKOUT Timing

Data Sheet

42

V 1.0, 2003-10

TC1910

PRELIMINARY

PLL Parameters

1)

Parameter

Symbol

Limit Values

min. max.

Unit

Accumulated jitter

D_N

see Figure 14

–

2)

VCO frequency range

f_VCO

100

150

200

250

300

MHz

µs

3)

4)

5)

150

200

250

20

2)

PLL base frequency

f_PLLBASE

80

3)

20

130

180

230

200

4)

5)

20

PLL lock-in time

t_L

–

1)

Not subject to production test, verified by design/characterization.

2)

3)

4)

5)

@ vcosel = ’00’

@ vcosel = ’01’

@ vcosel = ’10’

@ vcosel = ’11’

Note: When TC1910 starts-up with the PLL not bypassed, first user instructions are

executed with the frequency defined by the VCO free-running frequency

(f_PLLBASE) and by the reset value of the PLL_CLC register (the K-divider and

VCOSEL bitfields). It is software responsibility to initialize its own appropriate

values in the bitfields in this register, before giving the command for the VCO to

lock to the input frequency. For more information, see the Users Manual, System

Units, System Control Unit chapter.

Data Sheet

43

V 1.0, 2003-10

TC1910

PRELIMINARY

TC191x_pll_jitter

±5.0

ns

D_N

±4.0

±3.0

±2.0

±1.0

f_SYS= 66 MHz(K = 4)

f_SYS= 60 MHz (K = 5)

f_SYS= 50 MHz (K = 6)

f_SYS= 40 MHz (K = 7)

f_SYS= 33 MHz (K = 8)

±0.0

0

5

10

15

20

25

30

35

P

D_N= Max. jitter

P = Number of consecutive f_SYSperiods

K

= K-divider of PLL

Figure 14

Approximated Maximum Accumulated PLL Jitter

The following two formulas define the (absolute) approximate maximum value of jitter D_N

in [ns] dependent on the K-factor, the system clock frequency f_SYSin [MHz], and the

number P of consecutive f_SYSperiods.

P

×

735

[1]

+ 0.5 ]

D_N[ns] = ± [(

+ 0.9)

×

for P <

0.25× f_SYS

f_SYS

0.25

f_SYS

×

K

735

for P >

[2]

D_N[ns] = ±

[

0.25× f_SYS

+ 1.4 ]

f_SYS

×

K

With rising number P of clock cycles the maximum jitter increases linearly up to a specific

value of P. Beyond this value of P the maximum accumulated jitter remains at a constant

value.

Data Sheet

44

V 1.0, 2003-10

TC1910

PRELIMINARY

Timing for EBU_LMB Clock Outputs

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

EBUCLK period

EBUCLK high time

EBUCLK low time

EBUCLK rise time

EBUCLK fall time

BFCLK0 period

t₁CC 15

t₂CC 6

t₃CC 6

t₄CC −

t₅CC −

t₆CC 20

t₇CC 9

t₈CC 9

t₉CC −

t₁₀CC −

−

ns

−

2.5

−

BFCLK0 high time

BFCLK0 low time

BFCLK0 rise time

BFCLK0 fall time

−

3.5

2.5

t₁(t₆)

0.9 V _DD

0.1 V _DD

EBUCLK/

0.5 V _DD

BFCLK0

t₂(t₇)

t₃(t₈)

t₅(t₁₀)

t₄(t₉)

M CT04884

Figure 15

EBU_LMB Clock Output Timing

Data Sheet

45

V 1.0, 2003-10

TC1910

PRELIMINARY

Timing for SDRAM Access Signals

(Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

CKE high from EBUCLK

t₁CC -

7.0

-

ns

CKE low from EBUCLK

t₂CC 2.0

t₃CC -

A(23:0) output valid from EBUCLK

A(23:0) output hold from EBUCLK

CS(6:0) low from EBUCLK

CS(6:0) high from EBUCLK

RAS low from EBUCLK

7.0

-

t₄CC 2.0

t₅CC -

7.0

-

t₆CC 2.0

t₇CC -

7.0

-

RAS high from EBUCLK

t₈CC 2.0

t₉CC -

CAS low from EBUCLK

7.0

-

CAS high from EBUCLK

t₁₀CC 2.0

t₁₁CC -

RD/WR low from EBUCLK

RD/WR high from EBUCLK

BC(3:0) low from EBUCLK

BC(3:0) high from EBUCLK

AD(31:0) output valid from EBUCLK

AD(31:0) output hold from EBUCLK

AD(31:0) input setup to EBUCLK

7.0

-

t₁₂CC 2.0

t₁₃CC -

7.0

-

t₁₄CC 2.0

t₁₅CC -

7.7

-

t₁₆CC 2.0

t₁₇SR 2.0

-

AD(31:0) input hold from EBUCLK

t₁₈SR 4.0

-

ns

Data Sheet

46

V 1.0, 2003-10

TC1910

PRELIMINARY

Write Access:

EBUCLK

t₁

CKE

t₃

t₅

t₄

Row

Column

A(23:0)

t₆

CSx

t₈

RAS

t₇

t₁₀

CAS

t₉

t₁₂

RD/WR

BC(3:0)

AD(31:0)

t₁₁

t₁₃

t₁₄

Data

(0)

Data

(n-1)

t₁₅

t₁₆

Read Access:

EBUCLK

t₂

CKE

t₃

t₄

Row

Column

A(23:0)

t₆

CSx

RAS

t₁₀

t₉

CAS

RD/WR

BC(3:0)

t₁₃

t₁₄

t₁₈

t₁₇

Data

(0)

Data

(n-1)

AD(31:0)

MCT05319

Figure 16

SDRAM Access Timing

Data Sheet

47

V 1.0, 2003-10

TC1910

PRELIMINARY

Timing for Burst Flash Access Signals

Operating Conditions apply; C = 50 pF)

L

Parameter

Symbol

Limits

min. max.

Unit

A(23:0) output valid from BFCLK0

A(23:0) output hold from BFCLK0

CS(6:0) low from BFCLK0

ADV low from BFCLK0

t₁CC −

11.0

−

ns

t₂CC 0.0

t₃CC −

t₅CC −

t₆CC 3.0

t₇CC −

t₈CC 3.0

t₉CC −

t₁₁SR 6.0

t₁₂SR 3.0

9.0

10.0

−

ADV high from BFCLK0

BAA low from BFCLK0

10.0

−

BAA high from BFCLK0

RD low from BFCLK0

10.0

−

AD(31:0) input setup to BFCLK0

AD(31:0) input hold from BFCLK0

−

Data Sheet

48

V 1.0, 2003-10

TC1910

PRELIMINARY

BFCLK0

A[23:0]

ADV

t₁

t₅

t₃

t₂

Address Valid

t₆

CSx

RD

t₉

t₇

t₈

BAA

t₁₁

t₁₂

Valid

D[31:0]

Note: Between the end of the Address Phase (ADV goes high) and the beginning of the Command

Phase (RD goes low) several cycles of Command Delay Phase can be inserted.

mct04889_mod_la

Figure 17

Burst Flash Access Timing (Instruction Read)

Data Sheet

49

V 1.0, 2003-10

TC1910

PRELIMINARY

1)

Timing for Demultiplexed Access Signals

(Operating Conditions apply; C_L= 50 pF)

Parameter

Symbol

Limits

min. max.

Unit

ALE low from EBUCLK

t₁CC −

8.0

−

ns

ALE high from EBUCLK

t₂CC 2.0

t₃CC −

A(23:0) output valid from EBUCLK

A(23:0) output hold from EBUCLK

CS(6:0) low from EBUCLK

CS(6:0) high from EBUCLK

MR/W low from EBUCLK

8.0

−

t₄CC 2.0

t₅CC −

8.0

−

t₆CC 2.0

t₇CC −

8.0

−

MR/W high from EBUCLK

RMW low from EBUCLK

t₈CC 2.0

t₉CC −

8.0

−

RMW high from EBUCLK

t₁₀CC 1.0

t₁₁CC −

RD low from EBUCLK

8.0

−

RD high from EBUCLK

t₁₂CC 0.0

t₁₃CC −

RD/WR low from EBUCLK

RD/WR high from EBUCLK

CMDELAY input setup to EBUCLK

CMDELAY hold from EBUCLK

WAIT input setup to EBUCLK

WAIT hold from EBUCLK

8.0

t₁₄CC 2.0

t₁₅SR 4.0

t₁₆SR 3.0

t₁₇SR 4.0

t₁₈SR 3.0

t₁₉CC −

−

BC(3:0) low from EBUCLK

BC(3:0) high from EBUCLK

AD(31:0) output valid from EBUCLK

AD(31:0) output hold from EBUCLK

AD(31:0) input setup to EBUCLK

AD(31:0) input hold from EBUCLK

8.0

−

t₂₀CC 2.0

t₂₁CC −

8.0

−

t₂₂CC 0.0

t₂₃SR 4.0

t₂₄SR 4.0

−

1)

It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase

length according to the particular asynchronous memory/peripheral device specification.

Data Sheet

50

V 1.0, 2003-10

TC1910

PRELIMINARY

EBUCLK

ALE

t₁

t₂

t₃

t₄

Address

A(23:0)

CSx

t₅

t₆

t₇

MR/W

t₁₄

RD/WR

CMDELAY

t₁₆

t₁₅

t₁₃

t₁₈

t₁₇

WAIT

t₂₀

t₁₉

t₂₀

BC(3:0)

AD(31:0)

t₂₁

t₂₂

Data Out

MCT05320

Figure 18

Demultiplexed Write Access

Data Sheet

51

V 1.0, 2003-10

TC1910

PRELIMINARY

EBUCLK

ALE

t₁

t₂

t₃

t₄

Address

A(23:0)

CSx

t₆

t₅

MR/W

RMW

t₈

t₁₀

t₉

t₁₂

RD

t₁₆

t₁₅

t₁₁

CMDELAY

t₁₈

t₁₇

WAIT

t₁₉

t₂₀

BC(3:0)

AD(31:0)

t₂₃

t₂₄

Data

Note: RMW signal is available only during Read-Modify-Write Access.

MCT05321

Figure 19

Demultiplexed Read Access

Data Sheet

52

V 1.0, 2003-10

TC1910

PRELIMINARY

1)

Timing for Multiplexed Access Signals

(Operating Conditions apply; C_L= 50 pF)

Parameter

Symbol

Limits

min. max.

Unit

ALE high from EBUCLK

t₁CC −

8.0

−

ns

ALE low from EBUCLK

t₂CC 2.0

t₃CC −

AD(31:0) output valid from EBUCLK

AD(31:0) output hold from EBUCLK

AD(31:0) input setup to EBUCLK

AD(31:0) input hold from EBUCLK

CS(6:0) low from EBUCLK

CS(6:0) high from EBUCLK

MR/W low from EBUCLK

8.0

−

t₄CC 0.0

t₅SR 4.0

t₆SR 4.0

t₇CC −

−

8.0

−

t₈CC 1.0

t₉CC −

8.0

−

MR/W high from EBUCLK

RMW low from EBUCLK

t₁₀CC 2.0

t₁₁CC −

8.0

−

RMW high from EBUCLK

t₁₂CC 1.0

t₁₃CC −

RD/WR low from EBUCLK

RD/WR high from EBUCLK

RD low from EBUCLK

8.0

−

t₁₄CC 2.0

t₁₅CC −

8.0

−

RD high from EBUCLK

t₁₆CC 0.0

t₁₇SR 4.0

t₁₈SR 3.0

t₁₉SR 4.0

t₂₀SR 3.0

t₂₁CC −

CMDELAY input setup to EBUCLK

CMDELAY hold from EBUCLK

WAIT input setup to EBUCLK

WAIT hold from EBUCLK

−

BC(3:0) low from EBUCLK

BC(3:0) high from EBUCLK

8.0

−

t₂₂CC 2.0

1)

It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase

length according to the particular asynchronous memory/peripheral device specification.

Data Sheet

53

V 1.0, 2003-10

TC1910

PRELIMINARY

EBUCLK

ALE

t₁

t₂

t₃

t₄

Address

Data

AD(31:0)

CSx

t₇

t₄

t₈

t₃

t₉

MR/W

t₁₄

RD/WR

CMDELAY

WAIT

t₁₈

t₁₇

t₁₃

t₂₀

t₁₉

t₂₂

t₂₁

t₂₂

BC(3:0)

MCT05322

Figure 20

Multiplexed Write Access

Data Sheet

54

V 1.0, 2003-10

TC1910

PRELIMINARY

EBUCLK

ALE

t₁

t₂

t₅

t₃

t₆

Address

Data

AD(31:0)

CSx

t₄

t₈

t₇

t₁₀

t₁₁

MR/W

RMW

t₁₂

t₁₆

RD

t₁₈

t₁₇

t₁₅

CMDELAY

t₂₀

t₁₉

WAIT

t₂₁

t₂₂

BC(3:0)

Note: RMW signal is only available during Read-Modify-Write Access.

MCT05323

Figure 21

Multiplexed Read Access

Data Sheet

55

V 1.0, 2003-10

TC1910

PRELIMINARY

Timing for External Bus Arbitration Signals

(Operating Conditions apply; C_L= 50 pF)

Parameter

Symbol

Limits

min. max.

Unit

HOLD input setup to EBUCLK

HOLD input hold from EBUCLK

HLDA low from EBUCLK

t₁SR 6.0

t₂SR 8.0

t₃CC −

t₄CC −

t₅SR 8.0

t₆SR 8.0

t₇CC −

t₈CC −

−

ns

−

10.0

9.0

−

HLDA high from EBUCLK

HLDA input setup to EBUCLK

HLDA input hold from EBUCLK

BREQ low from EBUCLK

−

10.0

9.0

BREQ high from EBUCLK

Note: The signals HOLD, HLDA and BREQ are alternate function of the CS5, CS6 and

CSOVL Pins.

Data Sheet

56

V 1.0, 2003-10

TC1910

PRELIMINARY

External Master Mode

EBU C LK

t₁

t₂

H OLD

t₄

H LDA

t₃

t₈

BR EQ

t₇

External Slave Mode

EBU C LK

t₇

t₈

BR EQ

H LDA

H OLD

t₅

t₆

t₁

t₂

M CT05324_m od

Figure 22

External Bus Arbitration Timing

Data Sheet

57

V 1.0, 2003-10

TC1910

PRELIMINARY

SSC Master Mode Timing

(Operating Conditions apply; C_L= 50 pF)

Parameter

Symbol

Limit Values

max.

Unit

min.

CC 40

CC

SCLK period

t

ns

SCLK

MTSR low/high from SCLK edge

MRST setup to SCLK edge

MRST hold from SCLK edge

-

2.0

5

6

7

SR 15

-

t_SCLK

0.9 V_DD

SCLK

0.5 V_DD

(CON.PO,CON.PH=00 or 11)

0.1 V_DD

t₂

t₄

t₃

0.9 V_DD

0.1 V_DD

SCLK

0.5 V_DD

(CON.PO,CON.PH=01 or 10)

t₃

t₄

t₅

MTSR

MRST

State n-1

State n

State n+1

t₆

t₇

Data valid

MCT04885

Figure 23

SSC Master Mode Timing

Data Sheet

58

V 1.0, 2003-10

TC1910

PRELIMINARY

Package Outlines

Figure 24

P-LBGA-208 Package

You can find all of our packages, sorts of packing and other in our Infineon Internet Page

“Products”: http://www.infineon.com/products

•

Data Sheet

59

V 1.0, 2003-10

TC1910

PRELIMINARY

Data Sheet

60

V 1.0, 2003-10

((49))

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	TC1910
厂家：	Infineon
描述：	32-Bit Single-Chip Microcontroller 32位单芯片微控制器微控制器
文件：	总66页 (文件大小：2746K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC1910 [INFINEON]

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