TDA5220XUMA1_技术文档

Preliminary Specification, V 1.1, October 2004

TDA 5220

ASK/FSK Single Conversion Receiver

Version 1.1

Wireless Control

Components

N e v e r s t o p t h i n k i n g .

Edition 2004-10-20

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

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characteristics.

Terms of delivery and rights to technical change reserved.

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circuits, descriptions and charts stated herein.

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Preliminary Specification, V 1.1, October 2004

TDA 5220

ASK/FSK Single Conversion Receiver

Version 1.1

Wireless Control

Components

N e v e r s t o p t h i n k i n g .

TDA 5220

Revision History:

2004-10-20

V 1.1

Previous Version:

none

Page

Subjects (major changes since last revision)

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TDA 5220

Page

Table of Contents

1

Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

1.3

2

2.1

2.2

2.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4

2.4.1

2.4.2

2.4.3

2.4.4

2.4.5

2.4.6

2.4.7

2.4.8

2.4.9

2.4.10

3

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Crystal Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Crystal Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ASK/FSK-Data Path Functional Description . . . . . . . . . . . . . . . . . . . . . . . 25

FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4

4.1

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

AC/DC Characteristics at T_AMB= 25°C . . . . . . . . . . . . . . . . . . . . . . . . . 33

AC/DC Characteristics at T_AMB= -40 to 105°C . . . . . . . . . . . . . . . . . . . . 40

Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.1.1

4.1.2

4.1.3

4.1.4

4.2

4.3

4.4

5

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Preliminary Specification

5

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TDA 5220

Product Description

1

Product Description

1.1

Overview

The IC is a very low power consumption single chip FSK/ASK Superheterodyne

Receiver (SHR) for the frequency bands 810 to 870 MHz and 400 to 440 MHz. The IC

offers a high level of integration and needs only a few external components. The device

contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a

PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK

demodulator, a data filter, an advanced data comparator (slicer) with selection between

two threshold modes and a peak detector. Additionally there is a power down feature to

save current and extend battery life, and two selectable alternatives of generating the

data slicer threshold.

1.2

Features

•

Low supply current (Is = 5.7/5.9 mA typ. in FSK mode, Is = 5.0/5.2 mA typ. in ASK

mode for 434/868 MHz)

•

Supply voltage range 5V ±10%

Power down mode with very low supply current (50nA typ.)

FSK and ASK demodulation capability

Fully integrated VCO and PLL Synthesiser

ASK sensitivity better than -106 dBm over specified temperature range (- 40 to

+105°C)

•

FSK sensitivity better than -100 dBm over specified temperature range (- 40 to

+105°C)

•

Selectable frequency ranges 810-870 MHz and 400-440 MHz

Limiter with RSSI generation, operating at 10.7MHz

2nd order low pass data filter with external capacitors

Data slicer with selection between two threshold modes (see Section 2.4.8)

1.3

Application

•

Keyless Entry Systems

Remote Control Systems

Alarm Systems

Low Bitrate Communication Systems

Preliminary Specification

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TDA 5220

Functional Description

2

Functional Description

2.1

Pin Configuration

CRST1

VCC

LNI

1

2

3

4

5

6

7

8

9

28 CRST2

27 PDWN

26 PDO

25 DATA

24 3VOUT

23 THRES

22 FFB

TAGC

AGND

LNO

VCC

MI

TDA 5220

21 OPP

20 SLN

MIX

AGND 10

FSEL 11

IFO 12

19 SLP

18 LIMX

17 LIM

DGND 13

VDD 14

16 SSEL

15 MSEL

Figure 1

Pin Configuration

Preliminary Specification

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TDA 5220

Functional Description

2.2

Pin Definition and Functions

Pin Defintion and Function

Table 1

No.

Symbol

Equivalent I/O Schematic

Function

1

CRST1

External Crystal

Connector 1

4.15V

1

50uA

2

3

VCC

LNI

5V Supply

LNA Input

57uA

3

500uA

4k

1k

Preliminary Specification

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TDA 5220

Functional Description

Function

No.

Symbol

Equivalent I/O Schematic

4

TAGC

AGCTimeConstant

Control

4.3V

3uA

4

1k

1.4uA

1.7V

5

6

AGND

LNO

Analogue Ground

Return

LNA Output

5V

1k

6

7

VCC

5V Supply

Preliminary Specification

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TDA 5220

Functional Description

Function

No.

Symbol

Equivalent I/O Schematic

8

MI

Mixer Input

1.7V

2k

9

MIX

Complementary

Mixer Input

9

8

400uA

10

11

AGND

FSEL

Analogue Ground

Return

868/434 MHz

Operating

Frequency Selector

750

1.2V

2k

11

12

IFO

10.7 MHz IF Mixer

Output

300uA

2.2V

60

12

4.5k

13

DGND

Digital Ground

Return

Preliminary Specification

10

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TDA 5220

Functional Description

Function

No.

Symbol

VDD

Equivalent I/O Schematic

14

5V Supply (PLL

Counter Circuity)

15

MSEL

ASK/FSK

Modulation Format

Sector

1.2V

40k

15

16

SSEL

Data Slicer

Reference Level

Sector

1.2V

40k

16

17

18

LIM

Limiter Input

2.4V

15k

LIMX

Complementary

Limiter Input

17

75uA

330

18

15k

Preliminary Specification

11

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TDA 5220

Functional Description

Function

No.

Symbol

Equivalent I/O Schematic

19

SLP

Data Slicer Positive

Input

15uA

100

3k

19

80µA

20

SLN

Data Slicer

Negative Input

5uA

10k

20

21

OPP

OpAmp

Noninverting Input

5uA

200

21

22

FFB

Data Filter

Feedback Pin

5uA

100k

22

Preliminary Specification

12

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TDA 5220

Functional Description

Function

No.

Symbol

Equivalent I/O Schematic

23

THRES

AGC Threshold

Input

5uA

10k

23

24

3VOUT

3V Reference

Output

24

20kΩ

3.1V

25

DATA

Data Output

500

25

40k

26

PDO

Peak Detector

Output

26

446k

Preliminary Specification

13

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TDA 5220

Functional Description

Function

No.

Symbol

Equivalent I/O Schematic

27

PDWN

Power Down Input

27

220k

28

CRST2

External Crystal

Connector 2

4.15V

28

50uA

Preliminary Specification

14

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TDA 5220

Functional Description

2.3

Functional Block Diagram

VCC

IF

Filter

MSEL

H=ASK

L=FSK

MI

FFB

LNO

MIX

9

IFO

12

LIM

LIMX

18

OPP

SLP

19

SLN

20

22

21

6

8

17

15

16

25

SSEL

DATA

Logic

CM

-

LNI

+

3

4

LNA

RF

CP

+

-

+

-

+

FSK

PLL Demod

FSK

ASK

+

LIMITER

DATA-

SLICER

OP

-

TAGC

TDA 5220

PEAK

DETECTOR

PDO

26

23 THRES

OTA

U _REF

3VOUT

24

AGC

Reference

: 1

: 2

Φ

DET

CRYSTAL

OSC

VCO

: 64

VCC

14

13

Bandgap

Reference

Loop

Filter

DGND

11

1

28

27

2,7

5,10

VCC AGND

PDWN

FSEL

Crystal

Figure 2

2.4

Block Diagram

Functional Block Description

Low Noise Amplifier (LNA)

2.4.1

The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain

figure is determined by the external matching networks situated ahead of LNA and

between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9).

The noise figure of the LNA is approximately 3dB, the current consumption is 500µA.

The gain can be reduced by approximately 18dB. The switching point of this AGC action

can be determined externally by applying a threshold voltage at the THRES pin (Pin 23).

This voltage is compared internally with the received signal (RSSI) level generated by

the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the

LNA gain is reduced and vice versa. The threshold voltage can be generated by

attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a

temperature stable 3V output generated from the internal bandgap voltage and the

THRES pin as described in Section 3.1. The time constant of the AGC action can be

determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen

along with the appropriate threshold voltage according to the intended operating case

and interference scenario to be expected during operation. The optimum choice of AGC

time constant and the threshold voltage is described in Section 3.1.

Preliminary Specification

15

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TDA 5220

Functional Description

2.4.2

Mixer

The Double Balanced Mixer downconverts the input frequency (RF) in the range of 400-

440MHz/810-870MHz to the intermediate frequency (IF) at 10.7MHz with a vol-tage gain

of approximately 21dB by utilising either high- or low-side injection of the local oscillator

signal. In case the mixer is interfaced only single-ended, the unused mixer input has to

be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner

frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin).

The IF output is internally consisting of an emitter follower that has a source impedance

of approximately 330Ω to facilitate interfacing the pin directly to a standard 10.7MHz

ceramic filter without additional matching circuitry.

2.4.3

PLL Synthesizer

The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain,

a phase detector with charge pump and a loop filter and is fully implemented on-chip.

The VCO is including spiral inductors and varactor diodes. The tuning range of the VCO

guarantee over production spread and the specified temperature range is 820 and

860MHz. The oscillator signal is fed both to the synthesiser divider chain and to the

downconverting mixer. In case of operation in the 400 to 440MHz range the signal is

divided by two before it is fed to the Mixer. Depending on whether high- or low-side

injection of the local oscillator is used, the receiving frequency ranges are 810 to

840MHz and 840 to 870MHz or 400 to 420MHz and 420 to 440MHz - see also Section

3.4. To be able to switch between two different frequency channels a divider ratio of

either 32 or 32.25 can be selected via the FSEL-Pin.

Table 2

FSEL-Pin Operating States

FSEL

Open

GND

RF

400-440MHz

810-870MHz

2.4.4

Crystal Oscillator

The calculation of the value of the necessary crystal load capacitance is shown in

Section 3.3, the crystal frequency calculation is explained in Section 3.4.

2.4.5

Limiter

The Limiter is an AC coupled multistage amplifier with a cumulative gain of

approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It

has a typical input impedance of 330 Ω to allow for easy interfacing to a 10.7 MHz

ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator

(RSSI) generator which produces a DC voltage that is directly proportional to the input

Preliminary Specification

16

V 1.1, 2004-10-20

TDA 5220

Functional Description

signal level as can be seen in Figure 4. This signal is used to demodulate ASK-

modulated receive signals in the subsequent baseband circuitry. The RSSI output is

applied to the modulation format switch, to the Peak Detector input and to the AGC

circuitry.

In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state as

described in the next chapter.

2.4.6

FSK Demodulator

To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is

contained fully on chip. The Limiter output differential signal is fed to the linear phase

detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain

is typically 200µV/kHz. The passive loop filter output that is comprised fully on chip is fed

to both the VCO and the modulation format switch described in more detail below. This

signal is representing the demodulated signal with low frequencies applied to the

demodulator demodulated to logic zero and high frequencies demodulated to logic ones.

However this is only valid in case the local oscillator is low-side injected to the mixer

which is applicable to receive frequencies above 840 or 420MHz. In case of receive

frequencies below 840 or 420MHz high frequencies are demodulated as logical zeroes

due to a sign inversion in the downconversion mixing process as the L0 is high-side

injected to the mixer. See also Section 3.4.

The modulation format switch is actually a switchable amplifier with an AC gain of 11 that

is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was

chosen to facilitate detection in the subsequent circuits. The DC gain is 1 in order not to

saturate the subsequent Data Filter wih the DC offset produced by the demodulator in

case of large frequency offsets of the IF signal. The resulting frequency characteristic

and details on the principle of operation of the switch are described in Section 3.6.

Table 3

MSEL Pin Operating States

MSEL

Modulation Format

Open

ASK

FSK

Shorted to ground

The demodulator circuit is switched off in case of reception of ASK signals.

2.4.7 Data Filter

The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage

follower and two 100kΩ on-chip resistors. Along with two external capacitors a 2nd order

Preliminary Specification

17

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TDA 5220

Functional Description

Sallen-Key low pass filter is formed. The selection of the capacitor values is described

in Section 3.2.

2.4.8

Data Slicer

The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a

maximum receive data rate of up to 100kBaud. The maximum achievable data rate also

depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs

are accessible. The output delivers a digital data signal (CMOS-like levels) for

subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RC-

term. In ASK-mode alternatively a scaled value of the voltage at the PDO-output (approx.

87%) can be used as the slicer-threshold as shown in Table 4. The data slicer threshold

generation alternatives are described in more detail in Section 3.5.

Table 4

SSEL Pin Operating States

SSEL

X

MSEL

Low

Selected Slicing Level (SL)

external SL on Pin 20 (RC-term, e.g.)

87% of PDO-output (approx.)

High

Low

High

2.4.9

Peak Detector

The peak detector generates a DC voltage which is proportional to the peak value of the

receive data signal. A capacitor is necessary. The input is connected to the output of the

RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This output

can be used as an indicator for the received signal strength to use in wake-up circuits

and as a reference for the data slicer in ASK mode. Note that the RSSI level is also

output in case of FSK mode.

2.4.10

Bandgap Reference Circuitry

A Bandgap Reference Circuit provides a temperature stable reference voltage for the

device. A power down mode is available to switch off all subcircuits which is controlled

by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in

this case is typically 50nA.

Table 5

PDWN

PDWN Pin Operating States

Operating State

Powerdown Mode

Receiver On

Open or tied to ground

Tied to Vs

Preliminary Specification

18

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TDA 5220

Applications

3

Applications

3.1

Application Circuit

C 1 8

R 4

R 5

U

th r e s h

o ld

3 V O U T

2 4

T H R E S

2 3

R S S I ( 0 . 8

- 2 . 8 V )

2 0 k Ω

O

T A

V C C

+ 3 . 1

V

I _lo

a

d

L N A

G

a in c o n tr o l

v o lta g e

R S S I

>

<

U

: I_{lo d}= 4 . 2 µ A

a

th re

s

h

o

ld

:

I_lo=

a d

-1 .5 µ A

th r e s h

o

4

T A G

C 5

C

U

_c:< 2 . 6 V

_c:> 2 . 6 V

:

G

a in h ig h

a in lo w

U

C

U

=

V

-

0 . 7 V

c

m

a x

1 .^C6^C7 V

in

Figure 3

LNA Automatic Gain Control Circuity

The LNA automatic gain control circuitry consists of an operational transimpedance

amplifier that is used to compare the received signal strength signal (RSSI) generated

by the Limiter with an externally provided threshold voltage U_thres. As shown in the

following figure the threshold voltage can have any value between approximately 0.8 and

2.8V to provide a switching point within the receive signal dynamic range.

This voltage U_thresis applied to the THRES pin (Pin 23) The threshold voltage can be

generated by attaching a voltage divider between the 3VOUT pin

(Pin 24) which provides a temperature stable 3V output generated from the internal

bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher

than U_thres, the OTA generates a positive current I_load. This yields a voltage rise on the

TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do

not have the same values in order to achieve a fast-attack and slow-release action of the

Preliminary Specification

19

V 1.1, 2004-10-20

TDA 5220

Applications

AGC and are used to charge an external capacitor which finally generates the LNA gain

control voltage.

3

2.5

2

RSSI Level

1.5

1

0.5

0

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

Input Level at LNA Input [dBm]

Figure 4

RSSI Level and Permissive AGC Threshold Levels

The switching point should be chosen according to the intended operating scenario. The

determination of the optimum point is described in the accompanying Application Note,

a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the

output of the 3VOUT pin is capable of driving up to 50µA, but that the THRES pin input

current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly

related to the receiver power consumption, the power divider resistors should have high

impedance values. The sum of R1 and R2 has to be 600kΩ in order to yield 3V at the

3VOUT pin. R1 can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT

output current of 5µA¹⁾and a threshold voltage of 1.8V

Note: If the LNA gain shall be kept in either high or low gain mode this has to be

accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain

mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as

a short to the 3VOLT pin. In order to achieve low gain mode operation THRES has to be

connected to GND.

As stated above the capacitor connected to the TAGC pin is generating the gain control

voltage of the LNA due to the charging and discharging currents of the OTA and thus is

also responsible for the AGC time constant. As the charging and discharging currents

are not equal two different time constants will result. The time constant corresponding to

the charging process of the capacitor shall be chosen according to the data rate.

According to measurements performed at Infineon the capacitor value should be greater

than 47nF.

1) note the 20kΩ resistor in series with the 3.1V internal voltage source

Preliminary Specification

20

V 1.1, 2004-10-20

TDA 5220

Applications

3.2

Data Filter Design

Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a 2nd order

Sallen-Key low pass data filter can be constructed by adding 2 external capacitors

between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following

figure and described in the following formulas¹⁾.

C14

C12

FFB

OPP

SLP

22

21

19

R_{F1 int}

100k

R_{F2 int}

100k

Figure 5

Data Filter Design

with R_F1int=R_F2int=R

2Q b

b

C14=

C12 =

R2πf_3dB

4QRπf_3dB

with

b

a

Q =

Q is the qualify factor of the poles where, in case of a Bessel filter a=1.3617, b=0.618

and thus Q=0.577

and in case of a Butter worth filter a=1.414, b=1

and thus Q=0.71

Example: Butter worth filter with f_3dB=5kHz and R=100kΩ:

C14=450pF, C12=225pF

1) taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999

Preliminary Specification

21

V 1.1, 2004-10-20

TDA 5220

Applications

3.3

Crystal Load Capacitance Calculation

The value of the capacitor necessary to achieve that the crystal oscillator is operating at

the intended frequency is determined by the reactive part of the negative resistance of

the oscillator circuit as shown in Section 4.1.3 and by the crystal specifications given by

the crystal manufacturer.

C_S

CRST2

28

Input

Crystal

impedance

TDA521X

Z_1-28

1

CRST1

Figure 6

Determination of Series Capacitance Vale for the Quartz Oscillator

The required series capacitor for a crystal with specified load capacitance C_Lcan be

calculated as

1

C_S

=

1

+2π f X _L

C_L

C_Lis the nominal load capacitance specified by the crystal manufacturer.

Example:

13.4 MHz: C_L= 12 pF

X_L=1010 Ω

C_S= 5.9 pF

This value may be obtained by putting two capacitors in series to the crystal, such as

22pF and 8.2pF for 13.4MHz.

But please note that the calculated C_S-value includes all parasitic.

3.4

Crystal Frequency Calculation

As described in Section 2.4.3 the operating range of the on-chip VCO is wide enough to

guarantee a receive frequency range between 810 and 870MHz or between 400 and

440MHz. The VCO signal is divided by 2 before applied to the mixer in case of operation

at 434MHz. This local oscillator signal can be used to downconvert the RF signals both

Preliminary Specification

22

V 1.1, 2004-10-20

TDA 5220

Applications

with high- or low-side injection at the mixer. High-side injection of the local oscillator has

to be used for receive frequencies between 810 and 840MHz or beteween 400 and

420MHz. In this case the local oscillator frequency is calculated by adding the IF

frequency (10.7 MHz) to the RF frequency. Thus the higher frequency of a FSK-

modulated signal is demodulated as a logical zero (low).

Low-side injection has to be used for receive frequencies above 840 MHz or above

420 MHz. The local oscillator frequency is calculated by subtracting the IF frequency

(10.7 MHz) from the RF frequency then. In this case no sign-inversion occurs and the

higher frequency of a FSK-modulated signal is demodulated as a logical one (high). The

overall division ratios in the PLL are 32 or 64 depending on whether the FSEL-pin is left

open or tied to ground.

Therefore the crystal frequency may be calculated by using the following formula:

f_RF±10.7

f_QU

=

r

with

ƒ_RFreceive frequency

ƒ_LOlocal oscillator (PLL) frequency (ƒ_RF± 10.7)

ƒ_QUquartz crystal oscillator frequency

r ratio of local oscillator (PLL) frequency and crystal frequency as

shown in the subsequent table

Table 6

Dependence of PLL Overall Division Ratio on FSEL

FSEL

open

GND

Ratio r=(f_LO/f_QU)

32

64

This yields the following examples:

FSEL is „Low“:

868 .4MHz − 10.7MHz

f_QU

=

= 13.4015625 MHz

= 13.234375 MHz

64

FSEL is „High“:

434 .2MHz − 10.7MHz

f_QU

=

32

Preliminary Specification

23

V 1.1, 2004-10-20

TDA 5220

Applications

3.5

Data Slicer Threshold Generation

The threshold of the data slicer can be generated using an external R-C integrator as

shown in Figure 7.

The time constant T_Aof this circuit including also the internal resistors R_F3intand R_F4int

(see Figure 9) has to be significantly larger than the longest period of no signal change

T_Lwithin the data sequence.

In order to keep distortion low, the minimum value for R is 20kΩ.

T_Ahas to be calculated as

R1 (R_F3int+ R_{F 4int}

)

T_A=

and

C13

= R1II(R_F3int+ R_{F 4int}) C13

... for ASK

... for FSK

R1+ R_F3int+ R_{F 4int}

R1 R_{F 4int}

R1II(R_F3int+ R_F4int)

T_A=

=

C13

R1+ R_F3int+ R_{F 4int}

v

R1, R_{F3 int}, R_{F4 int}and C13 see also Figure 7 and .Figure 9

19

20

U

threshold

25

CM

data slicer

data

filter

Figure 7

Data Slicer Threshold Generation with External R-C Integrator

In case of ASK operation another possibility for threshold generation is to use the peak

detector in connection with an internal resistive divider and one capacitor as shown in

the following Figure 8. For selecting the peak detector as reference for the slicing level

a logic low as to be applied on the SSEL pin.

In case of MSEL is high (or open), which means that ASK-Mode is selected, a logic low

on the SSEL pin yields a logic high on the AND-output and thus the peak-detector is

selected (see Figure 9).

In case of FSK the MSEL-pin and furthermore the one input of the AND-gate is low, so

the peak detector can not be selected.

The capacitor value is depending on the coding scheme and the protocol used.

Preliminary Specification

24

V 1.1, 2004-10-20

TDA 5220

Applications

C

Pins:

26

25

peak detector

56k

390k

data slicer

CP

U

threshold

Figure 8

3.6

Data Slicer Threshold Generation Utilising the Peak Detector

ASK/FSK-Data Path Functional Description

The TDA5220 is containing an ASK/FSK switch which can be controlled via Pin 15

(MSEL). This switch is actually consisting of 2 operational amplifiers that are having a

gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in

order to achieve an appropriate demodulation gain characteristic. In order to

compensate for the DC-offset generated especially in case of the FSK PLL demodulator

there is a feedback connection between the threshold voltage of the bit slicer comparator

(Pin 20) to the negative input of the FSK switch amplifier.

In ASK-mode alternatively to the voltage at Pin 20 (SLN) a value of approx. 87% of the

peak-detector output-voltage at Pin 26 (PDO) can be used as the slicer-reference level.

The slicing reference level is generated by an internal voltage divider (R_T1int, R_T2int),

which is applied on the peak detector output.

The selection between these modes is controlled by Pin 16 (SSEL), as described in

Section 3.5.

This is shown in the following Figure 9.

Preliminary Specification

25

V 1.1, 2004-10-20

TDA 5220

Applications

MSEL

15

H=ASK

L=FSK

PEAK

DETECTOR

PDO

from RSSI Gen

(ASK signal)

26

C15

R

56k

T1 int

ASK/FSK Switch

100nF

R

390k

T2

Data Filter

v = 1

Comp

-

+

-

R_{F2 int}

100k

R

F1 int

FSK PLL Demodulator

0.18 mV/kHz

+

CP

CM

ASK

FSK

25

DATA Out

+

-

+

-

100k

H=CP

L=CM

R

F3 int

300k

R

F4 int

typ. 2 V

1.5 V......2.5 V

30k

22

21

19

20

16

ASK mode: v=1

FSK mode: v=11

FFB

C12

OOP

SLP

SLN

SSEL

R1

C14

C13

Figure 9

3.7

ASK/FSK mode datapath

FSK Mode

The FSK datapath has a bandpass characterisitc due to the feedback shown above

(highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by

the external RC-combination. The upper cutoff frequency f3 is determined by the data

filter bandwidth.

The demodulation gain of the FSK PLL demodulator is 200µV/kHz. This gain is

increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic

gain of this circuit is 2.2mV/kHz within the bandpass. The gain for the DC content of FSK

signal remains at 200µV/kHz. The cut-off frequencies of the bandpass have to be chosen

such that the spectrum of the data signal is influenced in an acceptable amount.

In case that the user data is containing long sequences of logical zeroes the effect of the

drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at

the negative input of the slicer comparator (Pin20) is used. The comparator has no

hysteresis built in.

This offset voltage is generated by the bias current of the negative input of the

comparator (i.e. 20nA) running over the external resistor R. This voltage raises the

voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain benefit of this

Preliminary Specification

26

V 1.1, 2004-10-20

TDA 5220

Applications

asymmetrical offset for the demodulation of long zeros the lower of the two FSK

frequencies should be chosen in the transmitter as the zero-symbol frequency.

In the following figure the shape of the above mentioned bandpass is shown.

gain (pin19)

v

v-3dB

20dB/dec

-40dB/dec

3dB

0dB

f

DC

f1

f2

f3

0.18mV/kHz

2mV/kHz

Figure 10

Frequency characteristic in case of FSK mode

The cutoff frequencies are calculated with the following formulas:

1

f₁=

R1×330kΩ

2π

×C13

R1+ 330kΩ

f₂= v× f₁=11× f₁

f₃= f_3dB

f₃is the 3dB cutoff frequency of the data filter - see Section 3.2.

Example:

R1 = 100kΩ, C13 = 47nF

This leads tof₁= 44Hz and f₂= 485Hz

Preliminary Specification

27

V 1.1, 2004-10-20

TDA 5220

Applications

3.8

ASK Mode

In case the receiver is operated in ASK mode the datapath frequency charactersitic is

dominated by the data filter alone, thus it is lowpass shaped.The cutoff frequency is

determined by the external capacitors C₁₂and C₁₄and the internal 100k resistors as

described in Section 3.2

0dB

-3dB

-40dB/dec

f

f3dB

Figure 11

3.9

Frequency characteristic in case of ASK mode

Principle of the Precharge Circuit

In case the data slicer threshold shall be generated with an external RC network as

described in Section 3.5 it is necessary to use large values for the capacitor C attached

to the SLN pin (pin 20) in order to achieve long time constants. This results also from the

fact that the choice of the value for R1 connected between the SLP and SLN pins (pins

19 and 20) is limited by the 330kΩ resistor appearing in parallel to R1 as can be seen in

Figure 9. Apart from this a resistor value of 100kΩ leads to a voltage offset of 1mv at the

comparator input. The resulting startup time constant τ₁can be calculated with:

τ₁=

(

R1|| 330kΩ ×C13

)

In case R1 is chosen to be 100kΩ and C13 is chosen as 47nF this leads to

τ₁= 100kΩ || 330kΩ ×47nF = 77kΩ×47nF = 3.6ms

(

)

When the device is turned on this time constant dominates the time necessary for the

device to be able to demodulate data properly. In the powerdown mode the capacitor is

only discharged by leakage currents.

Preliminary Specification

28

V 1.1, 2004-10-20

TDA 5220

Applications

In order to reduce the turn-on time in the presence of large values of C a precharge

circuit was included in the TDA5220 as shown in the following figure.

C18

R4+R5=600k

R5

R4

C13

R1

U_threshold

24

23

Uc>Us

19

20

Uc

ASK/FSK Switch

I_load

Data Filter

Uc<Us

-

U2

+

0 / 240uA

OTA

Us

U2<2.4V : I=240uA

U2>2.4V : I=0

-

20k

+2.4V

+3.1V

Figure 12

Principle of the precharge circuit

This circuit charges the capacitor C13 with an inrush current I_loadof typically 220µA for a

duration of T₂until the voltage U_cappearing on the capacitor is equal to the voltage U_s

at the input of the data filter. This voltage is limited to 2.5V. As soon as these voltages

are equal or the duration T₂is exceeded the precharge circuit is disabled.

τ₂is the time constant of the charging process of C18 which can be calculated as

τ ₂≈ 20kΩ×C2

as the sum of R4 and R5 is sufficiently large and thus can be neglected. T₂can then be

calculated according to the following formula:









1

2.4V

3V





T₂=τ ₂ln

≈τ ₂×1.6









1−

Preliminary Specification

29

V 1.1, 2004-10-20

TDA 5220

Applications

The voltage transient during the charging of C₂is shown in the following figure:

U2

3V

2.4V

T2

2

Figure 13

Voltage appearing on C18 during precharging process

The voltage appearing on the capacitor C13 connected to pin 20 is shown in the following

figure. It can be seen that due to the fact that it is charged by a constant current source

it exhibits is a linear increase in voltage which is limited to U_Smax= 2.5V which is also the

approximate operating point of the data filter input. The time constant appearing in this

case can be denoted as T₃, which can be calculated with:

U

_Smax×C13

220µA

2.5V

T₃=

=

×C13

220µA

Preliminary Specification

30

V 1.1, 2004-10-20

TDA 5220

Applications

Uc

Us

T3

Figure 14

Voltage transient on capacitor C13 attached to pin 20

As an example the choice of C18 = 22nF and C13 = 47nF yields

τ₂= 0.44ms

T₂= 0.71ms

T₃= 0.53ms

This means that in this case the inrush current could flow for a duration of 0.64ms but

stops already after 0.49ms when the U_Smaxlimit has been reached. T₃should always be

chosen to be shorter than T₂.

It has to be noted finally that during the turn-on duration T₂the overall device power

consumption is increased by the 220µA needed to charge C13.

The precharge circuit may be disabled if C18 is not equipped. This yields a T₂close to

zero. Note that the sum of R₄and R₅has to be 600kΩ in order to produce 3V at the

THRES pin as this voltage is internally used also as the reference for the FSK

demodulator.

Preliminary Specification

31

V 1.1, 2004-10-20

TDA 5220

Reference

4

Reference

4.1

Electrical Data

4.1.1

Absolute Maximum Ratings

Attention: The maximum ratings may not be exceeded under any circumstances,

not even momentarily and individually, as permanent damage to the IC

may result. The AC/DC characteristic limits are not guaranteed.

Table 7

Absolute Maximum Ratings, T_amb= -40 °C … +105 °C

#

Parameter

Symbol

Limit Values

Unit Remarks

min.

max.

5.5

1

Supply Voltage

V_s

T_j

-0.3

-40

V

°C

2

3

4

5

Junction Temperature

Storage Temperature

Thermal Resistance

+125

+150

114

T_s

°C

R_thJA

V_ESD

K/W

ESD integrity, all pins

excl. Pins 1,3, 6, 28

ESD integrity Pins

1,3,6,28

+2

kV

HBM according to

MIL STD 883D,

method 3015.7

+1.5

kV

4.1.2

Operating Range

Within the operational range the IC operates as explained in the circuit description.

Currents flowing into the device are denoted as positive currents and vice versa. The

device parameters with ■ are not part of the production test, but either verified by design

or measured in the Infineon Evalboard as described in Section 4.2.

Supply voltage: VCC = 4.5V .. 5.5V

Preliminary Specification

32

V 1.1, 2004-10-20

TDA 5220

Reference

Table 8

Operating Range, T_amb= -40 °C … +105 °C

#

Parameter

Symbol Limit Values Unit

Test Conditions/

Notes

L

min.

max.

1

Supply Current

I_SF868

I_SF434

3.9

3.7

3.2

3.0

7.9

7.7

7.2

7.0

mA

f

_RF=868MHz, FSK Mode

f_RF=434MHz, FSK Mode

f_RF=868MHz, ASK Mode

I

_SA868

I_SA434

f_RF=434MHz, ASK Mode

2

Receiver Input Level

ASK

FSK, frequ. dev. ± 50kHz

@source impedance

50Ω

BER 2E-3, average

power level, Manchester

encoded datarate 4kBit,

280KHz IF Bandwidth

■

RF_in

-106

-100

-13

dBm

3

4

5

LNI Input Frequency

MI/X Input Frequency

f_RF

f_MI

400/810 440/870 MHz

3dB IF Frequency Range

ASK

FSK

■

f_{IF -3dB}

5

23

11

MHz

10.4

6

7

8

Powerdown Mode On

Powerdown Mode Off

PWDN_ON

PWDN_OFF

V_THRES

2

V_S

0.8

V_S

V

0

Gain Control Voltage,

LNA high gain state

2.8

9

Gain Control Voltage,

LNA low gain state

V_THRES

0

0.7

V

■ Not part of the production test - either verified by design or measured in the Infineon

Evalboard as described in Section 4.2.

4.1.3

AC/DC Characteristics at T_AMB= 25°C

AC/DC characteristics involve the spread of values guaranteed within the specified

voltage and ambient temperature range. Typical characteristics are the median of the

production. Currents flowing into the device are denoted as po-sitive currents and vice

versa. The device performance parameters marked with ■ are not part of the production

test - either verified by design or measured in the Infineon Evalboard as described in

Section 4.2.

Preliminary Specification

33

V 1.1, 2004-10-20

TDA 5220

Reference

Table 9

AC/DC Characteristics with T_A25°C, V_VCC=4.5 ... 5.5 V

#

Parameter

Symbol

Limit Values

Unit Test Conditions/

L

Notes

min. typ. max.

SUPPLY

Supply Current

1

Supply current,

standby mode

I_{S PDWN}

50

100

6.7

nA

Pin 27 (PDWN)

open or tied to 0 V

2

Supply current, device I_{SF 868}

operating in 868 MHz

range, FSK mode

5.1

4.9

4.4

4.2

5.9

mA

Pin 11 (FSEL) tied to

GND, Pin 15 (MSEL)

tied to GND

3

4

5

Supply current, device I_{SA 434}

operating in 434 MHz

range, FSK mode

5.7

5.2

5.

6.5

6

mA

Pin 11 (FSEL) open,

Pin 15 (MSEL) tied

to GND

Supply current, device I_{SA 868}

operating in 868 MHz

range, ASK mode

Pin 11 (FSEL) tied to

GND, Pin 15

(MSEL) open

Supply current, device I_{SA 434}

operating in 434 MHz

range, ASK mode

5.8

Pin 11 (FSEL) open,

Pin 15 (MSEL) open

LNA

Signal Input LNI (PIN 3), V_THRES>2.8V, high gain mode

1

Average Power Level RF_in

at BER = 2E-3

(Sensitivity)

-110

dBm Manchester

encoded datarate

■

4kBit, 280kHz IF

Bandwidth

2

Average Power Level RF_in

at BER = 2E-3

-103

dBm Manchester enc.

datarate 4kBit,

(Sensitivity) FSK

280kHz IF Bandw., ±

50kHz pk. dev.

3

4

5

Input impedance,

= 434 MHz

S

0.873 / -34.7 deg

0.738 / -73.5 deg

-15

■

11 LNA

f

RF

Input impedance,

= 869 MHz

11 LNA

f

RF

Input level @ 1dB

compression

P1dB

dBm

LNA

Preliminary Specification

34

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

min. typ. max.

-10

Unit Test Conditions/

L

Notes

6

Input3^rdorderintercept IIP3

dBm matched input

■

LNA

point f = 434 MHz

RF

7

8

Input3^rdorderintercept IIP3

-14

dBm matched input

dBm

point f = 869 MHz

RF

LO signal feedthrough LO

-73

LNI

at antenna port

Signal Output LNO (PIN 6), V_THRES>2.8V, high gain mode

1

2

3

Gain f = 434 MHz

RF

S

1.509/ 138.2 deg

1.419/ 101.7 deg

0.886 / -12.9 deg

■

21 LNA

22 LNA

Gain f = 869 MHz

RF

Output impedance,

f

= 434 MHz

RF

4

5

6

Output impedance,

= 869 MHz

S

0.866 / -24.2 deg

■

22 LNA

f

RF

Voltage Gain Antenna

G

42

40

dB

AntMI

to MI f = 434 MHz

RF

Voltage Gain Antenna

G

to MI f = 869 MHz

RF

Signal Input LNI, V_THRES=GND, lwo gain mode

1

2

3

4

5

6

Input impedance,

= 434 MHz

S

0.873 / -34.7 deg

■

11 LNA

f

RF

Input impedance,

= 869 MHz

S

0.738 / -73.5 deg

11 LNA

f

RF

Input level @ 1dB C. P. P1dB

-18

-6

dBm matched input

LNA

f

= 434 MHz

RF

Input level @ 1dB C. P. P1dB

= 869 MHz

f

RF

Input3^rdorderintercept IIP3

-10

-5

LNA

point f = 434 MHz

RF

Input3^rdorderintercept IIP3

LNA

point f = 869 MHz

RF

Signal Output LNO, V_THRES=GND, lwo gain mode

1

2

3

Gain f = 434 MHz

RF

S

0.183 / 140.6 deg

0.179 / 109.1 deg

0.897 / -13.6 deg

■

21 LNA

22 LNA

Gain f = 869 MHz

RF

Output impedance,

f

= 434 MHz

RF

Preliminary Specification

35

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

min. typ. max.

0.868 / -26.3 deg

Unit Test Conditions/

L

Notes

4

Output impedance,

S

■

22 LNA

f

= 869 MHz

RF

5

6

Voltage Gain Antenna

G

22

19

dB

AntMI

to MI f = 434 MHz

RF

Voltage Gain Antenna

G

AntMI

to MI f = 869 MHz

RF

Signal 3VOUT (PIN 24)

1

2

Output voltage

Current out

V_3VOUT

I_3VOUT

2.9

-3

3.1

-5

3.3

-10

V

3VOUT Pin open

see Section 4.1

µA

Signal THRES (PIN 23)

1

2

3

4

Input Voltage range

LNA low gain mode

LNA high gain mode

Current in

V_THRES

I_{THRES_in}

0

3

V -1

S

V

see Section 4.1

0

V

V -1

S

V

or shorted to Pin 24

5

nA

■

Signal TAGC (PIN 4)

1

Current out,

LNA low gain state

I_{TAGC_out}

-3.6

1

-4.2

1.6

-5.5

2.2

µA

RSSI > V

THRES

2

Current in,

I

RSSI < V

THRES

TAGC_in

LNA high gain state

MIXER

Signal Input MI/MIX (PINS 8/9)

1

2

3

4

Input impedance,

= 434 MHz

S

0.942 / -14.4 deg

■

11 MIX

f

RF

Input impedance,

= 869 MHz

S

0.918 / -28.1 deg

11 MIX

f

RF

Input3^rdorderintercept IIP3

-28

-26

dBm

MIX

point f = 434 MHz

RF

Input3^rdorderintercept IIP3

point f = 869 MHz

RF

Signal Output IFO (PIN 12)

1

2

Output impedance

Z

330

19

Ω

■

IFO

Conversion Voltage

G

dB

MIX

Gain f = 434 MHz

RF

Preliminary Specification

36

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

min. typ. max.

18

Unit Test Conditions/

L

Notes

3

Conversion Voltage

G

dB

MIX

Gain f = 869 MHz

RF

LIMITER

Signal Input LIM/X (PINS 17/18)

1

2

3

4

Input Impedance

RSSI dynamic range

RSSI linearity

Z

264

5

330

70

396

23

Ω

■

LIM

DR

dB

MHz

RSSI

LIN

f

±1

10.7

■

RSSI

Operating frequency

(3dB points)

LIM

DATA FILTER

1

Useable bandwidth

BW

100

kHz

V

■

BB

FILT

2

RSSI Level at Data

Filter Output SLP,

RSSI

1.1

LNA in high gain

mode at 868 MHz

low

RF =-103dBm

IN

3

RSSI Level at Data

Filter Output SLP,

RSSI

2.65

V

LNA in high gain

mode at 868 MHz

high

RF =-30dBm

IN

SLICER

Signal Output DATA (PIN 25)

1

Maximum Datarate

DR

100

0.1

kBps NRZ, 20pF

capacitive loading

■

max

2

3

LOW output voltage

HIGH output voltage

V

0

V

SLIC_L

SLIC_H

V

V -

S

V -1

S

V -

S

output

1.3

0.7

current=200µA

Slicer, Negative Input (PIN 20)

Precharge Current Out

1

I

-100

-220

-300

µA

see Section 4.2.

PCH_SLN

Preliminary Specification

37

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

Unit Test Conditions/

L

Notes

min. typ. max.

PEAK DETECTOR

Signal Output PDO (PIN 26)

1

Load current

I

-500

µA

static load current

must not exceed

-500µA

load

2

Internal resistive load

R

357

446

535

kΩ

CRYSTAL OSCILLATOR

Signals CRSTL 1, CRSTL 2 (PINS 1/28)

1

2

3

Operating frequency

f

6

14

MHz fundamental mode,

series resonance

CRSTL

Input Impedance

^@~13MHz

Z

-600 +

j 1010

Ω

■

1-28

Serial Capacity

C

=C1

5.9

pF

S10

^@~13MHz

ASK/FSK Signal Switch

Signal MSEL (PIN 15)

1

2

3

ASK Mode

FSK Mode

V

1.4

0

4

V

or open

MSEL

V

I

0.2

19

V

Input Bias Current

MSEL

-11

µA

MSEL tied to GND

MSEL

FSK DEMODULATOR

1

Demodulation Gain

G

200

µV/

FMDEM

kHz

2

Useable IF Bandwidth BW

10.2

10.7

11.2

MHz

IFPLL

POWER DOWN MODE

Signal PDWN (PIN 27)

1

2

Powerdown Mode On PWDN

2.8

0

V

S

V

ON

Off

Powerdown Mode Off PWDN

0.8

Preliminary Specification

38

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

min. typ. max.

19

Unit Test Conditions/ L

Notes

3

Input bias current

PDWN

I

µA

ms

Power On Mode

PDWN

4

Start-up Time until

valid IF signal is

detected

T

<1

depends on the

used crystal

SU

VCO MULTIPLEXER

Signal FSEL (PIN 11)

1

2

f

_RFrange 434 MHz

V

1.4

0

4

V

or open

FSEL

f_RFrange 869 MHz

V

0.2

FSEL

3

Input bias current

FSEL

I

-160 -200 -240 µA

FSEL tied to GND

FSEL

DATA-SLICER REFERENCE-LEVEL

Signal SSEL (PIN 16), ASK-Mode

1

Slicer-Reference is

voltage at Pin 20 (SLN)

V

1.4

4

V

or open

SSEL

2

Slicer-Reference is

approx. 87% of the

voltage at Pin 26

(PDO)

V

0

0.2

SSEL

3

Input bias current

SSEL

I

-10

-19

µA

SSEL tied to GND

SSEL

■ Not part of the production test - either verified by design or measured in the Infineon

Evalboard as described in Section 4.2.

Preliminary Specification

39

V 1.1, 2004-10-20

TDA 5220

Reference

4.1.4

AC/DC Characteristics at T_AMB= -40 to 105°C

Currents flowing into the device are denoted as positive currents and vice versa.

Table 10

AC/DC Characteristics with T_AMB= -40°C ...+105°C, V_VCC=4.5 ... 5.5 V

#

Parameter

Symbol

Limit Values

Unit Test Conditions/

Notes

■

min. typ. max.

SUPPLY

Supply Current

1

Supply current,

standby mode

I_{S PDWN}

I_{SF 868}

50

400

7.9

nA

Pin 27 (PDWN) open

or tied to 0 V

2

Supply current,

device operating in

868 MHz range, FSK

mode

3.9

3.7

3.2

3

5.9

mA

Pin 11 (FSEL) tied to

GND, Pin 15 (MSEL)

tied to GND

3

4

5

Supply current,

device operating in

434 MHz range, FSK

mode

I_{SA 434}

I_{SA 868}

I_{SA 434}

5.7

5.2

5.

7.7

7.2

7

mA

Pin 11 (FSEL) open,

Pin 15 (MSEL) tied

to GND

Supply current,

device operating in

868 MHz range, ASK

mode

Pin 11 (FSEL) tied to

GND, Pin 15

(MSEL) open

Supply current,

device operating in

434 MHz range, ASK

mode

Pin 11 (FSEL) open,

Pin 15 (MSEL) open

Signal Input 3VOUT (PIN 24)

1

2

Output voltage

Current out

V

I

2.9

-3

3.1

-5

3.3

-10

V

3VOUT Pin open

see Section 4.1

3VOUT

µA

3VOUT

Signal THRES (PIN 23)

1

2

3

4

Input Voltage range

LNA low gain mode

LNA high gain mode

Current in

V

0

3

V -1

S

V

see Section 4.1

THRES

V

0

V

V -1

S

V

or shorted to Pin 24

I_{THRES_in}

5

nA

■

Signal TAGC (PIN 4)

1

Current out,

I_{TAGC_out}

-1

-4.2

-8

µA

RSSI > V

THRES

LNA low gain state

Preliminary Specification

40

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

Unit Test Conditions/

■

Notes

min. typ. max.

2

Current in, LNA high

gain state

V

0.5

1.5

5

µA

RSSI < V

TAGC_in

THRES

MIXER

1

Conversion Voltage

G

+19

+18

dB

MIX

Gain f = 434 MHz

RF

2

Conversion Voltage

G

MIX

Gain f = 868 MHz

RF

LIMITER

Signal Input LIM/X (PINS 17/18)

1

2

RSSI dynamic range DR

70

dB

V

RSSI

low

RSSI Level at Data

Filter Output SLP,

RSSI

1.1

LNA in high gain

mode at 868 MHz

RF = -103dBm

IN

3

RSSI Level at Data

Filter Output SLP,

RSSI

2.65

V

LNA in high gain

mode at 868 MHz

high

RF = -30dBm

IN

DATA FILTER

Slicer, Signal Output DATA (PIN 25)

1

Maximum Datarate

DR

100

0.1

kBps NRZ, 20pF

capacitive loading

■

max

2

3

LOW output voltage

HIGH output voltage

V

0

V

SLIC_L

SLIC_H

V

V -

S

V -1

S

V -

S

output

1.5

0.5

current=200µA

Slicer, Negative Input (PIN 20)

1

Precharge Current

Out

I

-100

-220

-300

µA

see Section 4.2

PCH_SLN

Preliminary Specification

41

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

Unit Test Conditions/

■

Notes

min. typ. max.

PEAK DETECTOR

Signal Output PDO (PIN 26)

1

Load current

I

-400

µA

static load current

must not exceed

-500µA

load

2

Internal resistive load

R

356

446

575

kΩ

CRYSTAL OSCILLATOR

Signals CRSTL 1, CRSTL 2 (PINS 1/28)

Operating frequency

1

f

6

14

MHz fundamental mode,

series resonance

CRSTL

ASK/FSK Signal Switch

Signal MSEL (PIN 15)

1

2

3

ASK Mode

FSK Mode

V

I

1.4

0

4

V

or open

MSEL

0.2

-20

MSEL

Input bias current

MSEL

-11

µA MSEL tied to GND

MSEL

FSK DEMODULATOR

1

Demodulation Gain

G

200

µV/

FMDEM

kHz

2

Useable IF

Bandwidth

BW

10.2

10.7

11.2

MHz

IFPLL

POWER DOWN MODE

Signal PDWN (PIN 27)

1

2

Powerdown Mode On PWDN

Powerdown Mode Off PWDN

2.8

0

V

S

V

ON

Off

0.8

Preliminary Specification

42

V 1.1, 2004-10-20

TDA 5220

Reference

#

Parameter

Symbol

Limit Values

min. typ. max.

<1

Unit Test Conditions/

■

Notes

3

Start-up Time until

valid signal is

T

ms

depends on the used

crystal

SU

detected at IF

VCO MULTIPLEXER

Signal FSEL (PIN 11)

1

2

f

_RFrange 434 MHz

V

1.4

0

4

V

or open

FSEL

f_RFrange 869 MHz

V

0.2

FSEL

3

Input bias current

FSEL

I

-110

-200

-340

µA

FSEL tied to GND

FSEL

DATA-SLICER REFERENCE-LEVEL

Signal SSEL (PIN 16), ASK-Mode

1

Slicer-Reference is

voltage at Pin 20

(SLN)

V

1.4

4

V

or open

SSEL

2

Slicer-Reference is

approx. 87% of the

voltage at Pin 26

(PDO)

V

0

0.2

SSEL

3

Input bias current

SSEL

I

-11

-20

µA

SSEL tied to GND

SSEL

■ Not part of the production test - either verified by design or measured in the Infineon

Evalboard as described in Section 4.2.

4.2

Test Circuit

The device performance parameters marked with ■ in Section 4.1 were either verified

by design or measured on an Infineon evaluation board. This evaluation board can be

obtained together with evaluation boards of the accompanying transmitter device

TDK5110 in an evaluation kit that may be ordered on the INFINEON Webpage

www.infineon.com/Products. More information on the kit is available on request.

Preliminary Specification

43

V 1.1, 2004-10-20

TDA 5220

Reference

Figure 15

4.3

Schematic of the Evaluation Board

Test Board Layouts

Figure 16

Top Side of the Evaluation Board

Preliminary Specification

44

V 1.1, 2004-10-20

TDA 5220

Reference

Figure 17

Bottom Side of the Evaluation Board

Figure 18

Component Placement on the Evaluation Board

Preliminary Specification

45

V 1.1, 2004-10-20

TDA 5220

Reference

4.4

Bill of Materials

The following components are necessary for evaluation of the TDA5220.

Table 11

Bill of Materials (cont’d)

Ref.

C1

Value 434MHz

1pF

Value 868MHz

1pF

Specification

0805, COG, +/-0.1pF

0805, COG, +/-5%

1206, X7R, +/-10%

Toko, PTL2012-F10N0G

0805, COG, +/-5%

0805, X7R, +/-10%

0805, COG, +/-5%

0805, X7R, +/-10%

0805, COG, +/-5%

0805, COG, +/-0.1pF

0805, COG, +/-1%

0805, X7R, +/-5%

1206, X7R, +/-10%

Infineon

C2

4.7pF

3.9pF

C3

6.8pF

5.6pF

C4

100pF

47nF

100pF

C5

47nF

C6

10nH

3.9pF

C7

100pF

33pF

100pF

C8

22pF

C9

100pF

10nF

100pF

C10

C11

C12

C13

C14

C15

C16

C17

C18

C21

IC1

L1

10nF

220pF

47nF

220pF

47nF

470pF

47nF

470pF

47nF

8.2pF

18pF

22nF

100nF

TDA5220

15nH

100nF

TDA5220

3.3nH

Toko, PTL2012-F15N0G

0805, COG, +/-0.1pF

1053-922

L2

8.2pF

3.9pF

Q1

13.234375 MHz

SFE_10.7MA5-A

100kΩ

240kΩ

360kΩ

13.4015625 MHz

SFE_10.7MA5-A

100kΩ

240kΩ

360kΩ

Q2

Murata

R1

0805, +/-5%

R4

0805, +/-5%

R5

0805, +/-5%

Preliminary Specification

46

V 1.1, 2004-10-20

TDA 5220

Reference

Ref.

R6

S1

S2

S3

S6

X1

X2

Value 434MHz

10kΩ

Value 868MHz

10kΩ

Specification

0805, +/-5%

2-pole pin connector

SOL_JUMP

STL_2POL

SOL_JUMP

STL_2POL

SOL_JUMP

STL_2POL

SOL_JUMP

2-pole pin connector

A107-900A (1.6mm

gold plated)

A107-900A (1.6mm

gold plated)

INPUT OUTPUT

ENTERPRISE CORP

X3

A107-900A (1.6mm

gold plated)

A107-900A (1.6mm

gold plated)

INPUT OUTPUT

ENTERPRISE CORP

Please note that in case of operation at 434MHz a capacitor has to be soldered in place

L2 and an inductor in place C6.

Preliminary Specification

47

V 1.1, 2004-10-20

TDA 5220

Package Outlines

5

Package Outlines

P_TSSOP_28.eps

Figure 19

Table 12

<Dev_Package1>

Order Information

Type

Ordering Code

Package

<Dev_Package1>

TDA 5220

Q67100-H2049

You can find all of our packages, sorts of packing and others in our

Infineon Internet Page “Products”: http://www.infineon.com/products.

Dimensions in mm

V 1.1, 2004-10-20

SMD = Surface Mounted Device

Preliminary Specification

48

TDA 5220

Page

List of Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

Table 11

Table 12

Pin Defintion and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FSEL-Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MSEL Pin Operating States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Dependence of PLL Overall Division Ratio on FSEL. . . . . . . . . . . . . . 23

Absolute Maximum Ratings, T_amb= -40 °C … +105 °C . . . . . . . . . . . . 32

Operating Range, T_amb= -40 °C … +105 °C . . . . . . . . . . . . . . . . . . . . 33

AC/DC Characteristics with T_A25°C, V_VCC=8.5V /. . . . . . . . . . . . . . . . 34

AC/DC Characteristics with T_AMB= -40°C ...+105°C, V_VCC=5.5V . . . . 40

Bill of Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Order Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Preliminary Specification

49

V 1.1, 2004-10-20

TDA 5220

Page

List of Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

LNA Automatic Gain Control Circuity. . . . . . . . . . . . . . . . . . . . . . . . . . 19

RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . 20

Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Determination of Series Capacitance Vale for the Quartz Oscillator . . 22

Data Slicer Threshold Generation with External R-C Integrator . . . . . 24

Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . 25

ASK/FSK mode datapath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Frequency characteristic in case of FSK mode . . . . . . . . . . . . . . . . . . 27

Frequency characteristic in case of ASK mode . . . . . . . . . . . . . . . . . . 28

Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Voltage appearing on C18 during precharging process. . . . . . . . . . . . 30

Voltage transient on capacitor C13 attached to pin 20 . . . . . . . . . . . . 31

Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Bottom Side of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . 45

Component Placement on the Evaluation Board. . . . . . . . . . . . . . . . . 45

P-TSSOP-28-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Preliminary Specification

50

V 1.1, 2004-10-20

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	TDA5220XUMA1
厂家：	Infineon
描述：	Telecom Circuit, 1-Func, PDSO28, PLASTIC, TSSOP-28 电信光电二极管电信集成电路
文件：	总51页 (文件大小：845K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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