TLD5541-1QU_技术文档

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Infineon^®LITIX™ Power Flex

Package

Marking

PG-VQFN-48-31

TLD55411QV

PG-TQFP-48-9

TLD55411QU

TLD5541-1QU

Sales Name TLD5541-1QV

1

Overview

Features

•

Single Inductor high power Buck-Boost controller

Wide LED forward voltage Range (2 V up to 55 V)

Wide VIN Range (IC 4.5 V to 40 V, Power 4.5 V to 55 V)

Switching Frequency Range from 200 kHz to 700 kHz

SPI for diagnostics and control

Maximum Efficiency in every condition (up to 96%)

Constant Current (LED) and Constant Voltage Regulation

Drives Multiple Load with a single IC thanks to the Fast Output Discharge operation

Limp Home Function (Fail Safe Mode)

EMC optimized device: Features an auto Spread Spectrum

LED and Input current sense with dedicated monitor Outputs

Advanced protection features for device and load

Enhanced Dimming features: Analog and PWM dimming

LED current accuracy +/- 3%

Available in a small thermally enhanced PG-VQFN-48-31 or PG-TQFP-48-9 package

Automotive AEC Qualified

V_IN

R_IIN

C_IN2

IVCC

C_IN1

C_IVCC

VIN

IIN2

IVCC_ext

IVCC

R_filter

C_filter

D₂

D₁

IIN1

SET

C_OUT2

C_OUT3

BST1

BST2

R_FB

LIMPHOME

FAIL SAFE Circuit

C_OUT1

C_BST1C_BST2

V_DD

M₁

M₂

M₄

LHI

EN/INUVLO

HSGD1

SWN1

L_OUT

R_EN

I/O

INOVLO

C_COMP

M₃

LSGD1

SWCS

R_COMP

C_{SOFT_START}

COMP

SOFT_START

FAIL SAFE Circuit

Micro

controller

PWMI_LH

R_FREQ

FREQ

PWMI

SGND

PGND1

PGND2

LSGD2

SWN2

HSGD2

VFB

R_PWMI

R_SENSE

A/D

IINMON

IOUTMON

SYNC

R_SYNC

I/O

V_DD

VDD

R_CSN

CSN

SI

SO

FBH

R_SI

SPI

R_SO

FBL

R_SCLK

SCLK

VSS AGND

GND

Figure 1

Application Drawing - TLD5541-1 as current regulator

Datasheet

www.infineon.com

1

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Overview

Description

The TLD5541-1 is a synchronous MOSFET H-Bridge DC/DC controller with built in protection features and SPI

interface. This concept is beneficial for driving high power LEDs with maximum system efficiency and

minimum number of external components. The TLD5541-1 offers both analog and digital (PWM) dimming.The

switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an external

clock source. A built in programable Spread Spectrum switching frequency modulation and the forced

continuous current regulation mode improve the overall EMC behavior. Furthermore the current mode

regulation scheme provides a stable regulation loop maintained by small external compensation

components. The adjustable soft start feature limits the current peak as well as voltage overshoot at start-up.

The TLD5541-1 is suitable for use in the harsh automotive environment.

Table 1

Product Summary

Power Stage input voltage range

Device Input supply voltage range

V_POW

4.5 V … 55 V

4.5 V … 40 V

V_VIN

Maximum output voltage (depending by the

application conditions)

V_OUT(max)

55 V as LED Driver Boost Mode

50 V as LED Driver Buck Mode

50 V as Voltage regulator

Switching Frequency range

f_SW

200 kHz... 700 kHz

Typical NMOS driver on-state resistance at

R_{DS(ON_PU)}

2.3 Ω

T_j= 25°C (Gate Pull Up)

Typical NMOS driver on-state resistance at

T_j= 25°C (Gate Pull Down)

R_{DS(ON_PD)}

f_SCLK(MAX)

1.2 Ω

SPI clock frequency

5 MHz

Protective Functions

•

Over load protection of external MOSFETs

Shorted load, open load, output overvoltage protection

Input overvoltage and undervoltage protection

Thermal shutdown of device with autorestart behavior

Electrostatic discharge protection (ESD)

Diagnostic Functions

•

Latched diagnostic information via SPI

Open load detection in ON-state

Device Overtemperature shutdown and Temperature Prewarning

Smart monitoring and advanced functions provide I_LEDand I_INinformation

Limp Home Function

Limp Home activation via LHI pin

•

Applications

•

Especially designed for driving high power LEDs in automotive applications

Automotive Exterior Lighting: full LED headlamp assemblies (Low Beam, High Beam, Matrix Beam, Pixel

Light)

•

General purpose current/voltage controlled DC/DC LED driver

Datasheet

2

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Block Diagram

2

Block Diagram

IVCC

Internal Supply

Power

On Reset

LDO

VIN

IVCC_EXT

GATE

DRIVER

SYNC

FREQ

Oscillator

BST1

Auto-Spread

Spectrum

Generator

HSGD1

SWN1

BUCK

LOGIC

Slope Comp.

IVCC_EXT

VIN

EN/INUVLO

INOVLO

Voltage

Protection

+ Enable

Thermal Protection

+ Prewarning

LSGD1

PGND1

PWM

Generator

Diagnosis Open Load + Short

to GND

IVCC_EXT

Soft Start

SOFT_START

Limp Home Mode

Digital Dimming

LSGD2

PGND2

LHI

PWMI

BOOST

LOGIC

Analog Dimming Pin

SET

SWN2

HSGD2

BST2

Fast Output

Discharge

Operation

Mode

Output

current

accuracy

calibration

SWCS

SGND

Switch Current

Error Amplifier

VDD

8 Bit DAC

Analog

Dimming

CSN

SCLK

SI

SPI

Voltage Loop

Feedback

VFB

SO

Input

Current

Monitor

LED

Current

Monitor

FBH

FBL

Input/diagnosis

register

Feedback Error Amplifier

IIN1 IIN2

VSS

AGND

COMP

Figure 2

Block Diagram - TLD5541-1

Datasheet

3

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

Figure 3

Pin Configuration - TLD5541-1

Datasheet

4

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Pin Configuration

3.2

Pin Definitions and Functions

1)

Symbol

I/O

-

Function

Power Supply

1, 12,

n.c.

Not connected, tie to AGND on the Layout;

15, 21,

32, 33,

45, 48

44

31

47

VIN

-

I

Power Supply Voltage;

Supply for internal biasing.

VDD

Digital GPIO Supply Voltage;

Connect to reverse voltage protected 5 V or 3.3 V supply.

IVCC_EXT

PD External LDO input;

Input to alternatively supply internal Gate Drivers via an external LDO.

Connect to IVCC pin to use internal LDO to supply gate drivers. Must not

be left open.

5, 8

26

40

-

PGND1, 2

VSS

-

Power Ground;

Ground for power potential. Connect externally close to the chip.

Digital GPIO Ground;

Ground for GPIO pins.

AGND

EP

Analog Ground;

Ground Reference

Exposed Pad;

Connect to external heatspreading Cu area (e.g. inner GND layer of

multilayer PCB with thermal vias).

Gate Driver Stages

2

HSGD1

O

Highside Gate Driver Output 1;

Drives the top n-channel MOSFET with a voltage equal to V_{IVCC_EXT}

superimposed on the switch node voltage SWN1. Connect to gate of

external switching MOSFET.

11

HSGD2

Highside Gate Driver Output 2;

Drives the top n-channel MOSFET with a voltage equal to V_{IVCC_EXT}

superimposed on the switch node voltage SWN2. Connect to gate of

external switching MOSFET.

6

7

LSGD1

LSGD2

O

Lowside Gate Driver Output 1;

Drives the lowside n-channel MOSFET between GND and V_{IVCC_EXT}

Connect to gate of external switching MOSFET.

.

Lowside Gate Driver Output 2;

Drives the lowside n-channel MOSFET between GND and V_{IVCC_EXT}

Connect to gate of external switching MOSFET.

4

9

SWN1

SWN2

IO

Switch Node 1;

SWN1 pin swings from a diode voltage drop below ground up to V_IN.

Switch Node 2;

SWN2 pin swings from ground up to a diode voltage drop above V_OUT

.

Datasheet

5

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Pin Configuration

1)

46

Symbol

IVCC

I/O

O

Function

Internal LDO output;

Used for internal biasing and gate driver supply. Bypass with external

capacitor close to the pin. Pin must not be left open.

Inputs and Outputs

37

23

25

41

LHI

I

-

I

PD Limp Home Input Pin;

Used to enter in Limp Home state during Fail Safe condition.

TEST1

TEST2

EN/INUVLO

Test Pin;

Used for Infineon end of line test, connect to GND in application.

Test Pin;

Used for Infineon end of line test, connect to GND in application.

PD Enable/Input Under Voltage Lock Out;

Used to put the device in a low current consumption mode, with

additional capability to fix an undervoltage threshold via external

components. Pin must not be left open.

35

34

FREQ

SYNC

I

Frequency Select Input;

Connect external resistor to GND to set frequency.

PD Synchronization Input;

Apply external clock signal for synchronization.

24

13

PWMI

FBH

I

PD Control Input; Digital input 5 V or 3.3 V.

Output current Feedback Positive;

Non inverting Input (+).

14

3

FBL

I

Output current Feedback Negative;

Inverting Input (-).

BST1

IO

Bootstrap capacitor;

Used for internal biasing and to drive the Highside Switch HSGD1.

Bypass to SWN1 with external capacitor close to the pin. Pin must not be

left open.

10

BST2

IO

Bootstrap capacitor;

Used for internal biasing and to drive the Highside Switch HSGD2.

Bypass to SWN2 with external capacitor close to the pin. Pin must not be

left open.

17

18

SWCS

SGND

I

Current Sense Input;

Inductor current measurement - Non Inverting Input (+).

Current Sense Ground;

Inductor current sense - Inverting Input (-).

Route as Differential net with SWCS on the Layout.

42

IIN1

I

Input Current Monitor Positive;

Non Inverting Input (+), connect to VIN if input current monitor is not

needed.

43

19

IIN2

I

Input Current Monitor Negative;

Inverting Input (-), connect to VIN if input current monitor is not needed.

COMP

O

Compensation Network Pin;

Connect R and C network to pin for stability phase margin adjustment.

Datasheet

6

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Pin Configuration

1)

38

Symbol

I/O

O

Function

SOFT_START

Softstart configuration Pin;

Connect a capacitor C_{SOFT_START}to GND to fix a soft start ramp default

time.

36

20

INOVLO

VFB

I

Input Overvoltage Protection Pin;

Define an upper voltage threshold and switches OFF the device in case

of overvoltages on the VIN supply. Must not be left open.

Voltage Loop Feedback Pin;

VFB is intended to set output protection functions.

22

39

SET

I

Analog current sense adjustment Pin;

IINMON

O

Input current monitor output;

Monitor pin that produces a voltage that is 20 times the voltage V_IN1-IN2

IINMON will be equal 1 V when V_IIN1-V_IIN2= 50 mV.

.

16

IOUTMON

O

Output current monitor output;

Monitor pin that produces a voltage that is 200 mV + 8 times the voltage

V_FBH-FBL. IOUTMON will be equal 1.4 V when V_FBH-FBL= 150 mV.

SPI

30

29

28

27

SI

I

PD Serial data in; Digital input 5 V or 3.3 V.

PD Serial clock; Digital input 5 V or 3.3 V.

SCLK

CSN

SO

I

PU SPI chip select; Digital input 5 V or 3.3 V. Active LOW.

O

Serial data out; Digital output, referenced to V_DD.

1) O: Output, I: Input,

PD: pull-down circuit integrated,

PU: pull-up circuit integrated

Datasheet

7

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 2

Absolute Maximum Ratings¹⁾

T_J= -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Supply Voltages

VIN

Supply Input

V_VIN

-0.3

–

60

6

V

–

P_4.1.1

P_4.1.2

P_4.1.3

VDD

V_VDD

V_IVCC

–

Digital supply voltage

IVCC

6

Internal Linear Voltage Regulator

Output voltage

IVCC_EXT

V_{IVCC_EXT}-0.3

–

6

V

–

P_4.1.4

External Linear Voltage Regulator Input

voltage

Gate Driver Stages

LSGD1,2 - PGND1,2

Lowside Gatedriver voltage

V_LSGD1,2--0.3

–

5.5

60

6

V

–

P_4.1.54

P_4.1.55

P_4.1.6

P_4.1.7

P_4.1.8

P_4.1.9

P_4.1.10

P_4.1.11

PGND1,2

HSGD1,2 - SWN1,2

Highside Gatedriver voltage

V_HSGD1,2--0.3

SWN1,2

SWN1, SWN2

switching node voltage

V_{SWN1, 2}

-1

(BST1-SWN1), (BST2-SWN2)

Boostrap voltage

V_BST1,2-

-0.3

-0.5

SWN1,2

BST1, BST2

Boostrap voltage related to GND

V_{BST1, 2}

65

0.3

0.5

SWCS

V_SWCS

V_SGND

Switch Current Sense Input voltage

SGND

Switch Current Sense GND voltage

SWCS-SGND

V_SWCS-

Switch Current Sense differential

voltage

SGND

PGND1,2

Power GND voltage

V_PGND1,2

-0.3

–

0.3

60

V

–

P_4.1.28

P_4.1.12

High voltage Pins

IIN1, IIN2

V_{IIN1, 2}

-0.3

Input Current monitor voltage

Datasheet

8

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

General Product Characteristics

Table 2

Absolute Maximum Ratings¹⁾(cont’d)

T_J= -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

P_4.1.13

Min.

-0.5

Typ. Max.

IIN1-IIN2

V_IIN1-IIN2

–

0.5

V

–

Input Current monitor differential

voltage

FBH, FBL

Feedback Error Amplifier voltage

V_{FBH, FBL}-0.3

V_FBH-FBL-0.5

–

60

V

–

P_4.1.14

P_4.1.15

FBH-FBL

0.5

Feedback Error Amplifier differential

voltage

EN/INUVLO

V_EN/INUVLO-0.3

–

60

V

–

P_4.1.16

Device enable/input undervoltage

lockout

Digital (I/O) Pins

PWMI

Digital Input voltage

V_PWMI

V_CSN

V_SCLK

V_SI

-0.3

–

5.5

V

–

P_4.1.17

P_4.1.18

P_4.1.19

P_4.1.20

P_4.1.21

P_4.1.22

P_4.1.58

CSN

Voltage at Chip Select pin

SCLK

Voltage at Serial Clock pin

SI

Voltage at Serial Input pin

SO

V_SO

Voltage at Serial Output pin

SYNC

V_SYNC

V_LHI

Synchronization Input voltage

LHI

Limp Home Input Voltage

Analog Pins

VFB

V_VFB

-0.3

–

5.5

3.6

V

–

P_4.1.25

P_4.1.26

P_4.1.29

P_4.1.30

P_4.1.31

P_4.1.32

Loop Input voltage

INOVLO

Input overvoltage lockout

V_INOVLO

V_SET

SET

Analog dimming Input voltage

COMP

V_COMP

Compensation Input voltage

SOFT_START

Softstart Voltage

V_{SOFT_STAR}-0.3

T

FREQ

V_FREQ

-0.3

Voltage at frequency selection pin

Datasheet

9

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

General Product Characteristics

Table 2

Absolute Maximum Ratings¹⁾(cont’d)

T_J= -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

-0.3

Typ. Max.

IINMON

Voltage at input monitor pin

V_IINMON

–

3.6

V

–

P_4.1.33

P_4.1.34

IOUTMON

V_IOUTMON-0.3

–

5.5

V

–

Voltage at output monitor pin

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

T_j

-40

-55

–

150

°C

–

P_4.1.35

P_4.1.36

T_stg

ESD Resistivity of all Pins

ESD Resistivity to GND

ESD Resistivity of corner Pins to GND

V_ESD,HBM-2

V_ESD,CDM-500

V_{ESD,CDM_c}-750

orner

–

2

kV HBM²⁾

P_4.1.37

P_4.1.38

P_4.1.39

500

750

V

CDM³⁾

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1

Note:

Stresses above the ones listed here may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Integrated protection functions are designed to prevent IC destruction under fault conditions

described in the datasheet. Fault conditions are considered as “outside” normal operating range.

Protection functions are not designed for continuous repetitive operation.

4.2

Functional Range

Table 3

Functional Range

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

4.5

Typ. Max.

1)

Device Extended Supply Voltage

Range

V_VIN

–

40

V

P_4.2.1

P_4.2.2

Device Nominal Supply Voltage

Range

8

–

36

V

–

1)

Power Stage Voltage Range

Digital Supply Voltage

Junction Temperature

V_POW

V_DD

T_j

4.5

3

–

55

V

P_4.2.5

P_4.2.3

P_4.2.4

5.5

150

V

–

-40

°C

1) Not subject to production test, specified by design.

Datasheet

10

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

General Product Characteristics

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

4.3

Thermal Resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 4

Parameter

Symbol

Values

Typ.

0.9

Unit Note or

Test Condition

Number

Min.

Max.

1) 2)

Junction to Case

R_thJC

R_thJA

–

K/W

K/W ³⁾2s2p

P_4.3.1

P_4.3.2

Junction to Ambient

–

25

1) Not subject to production test, specified by design.

2) Specified R_thJCvalue is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed

to ambient temperature). Ta = 25°C; The IC is dissipating 1 W.

3) Specified R_thJAvalue is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area

at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5 mm board. The 2s2p board has

2 outer copper layers (2 x 70 µm Cu) and 2 inner copper layers (2 x 35 µm Cu). A thermal via (diameter = 0.3 mm and

25 µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner

layer and second outer layer (bottom) of the JEDEC PCB. Ta = 25°C; The IC is dissipating 1 W.

Datasheet

11

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Power Supply

5

Power Supply

The TLD5541-1 is supplied by the following pins:

•

VIN (main supply voltage)

VDD (digital supply voltage)

IVCC_EXT (supply for internal gate driver stages)

The VIN supply, in combination with the VDD supply, provides internal supply voltages for the analog and

digital blocks. In situations where VIN voltage drops below VDD voltage, an increased current consumption

may be observed at the VDD pin.

The SPI and IO interfaces are supplied by the VDD pin.

IVCC_EXT is the supply for the low side driver stages. This supply is used also to charge, through external

Schottky diodes, the bootstrap capacitors which provide supply voltages to the high side driver stages. If no

external voltage is available this pin must be shorted to IVCC, which is the output of an internal 5 V LDO.

The supply pins VIN, VDD and IVCC_EXT have undervoltage detections.

Undervoltage on VDD supply voltage prevents the activation of the gate driver stages and any SPI

communication (the SPI registers are reset). Undervoltage on IVCC_EXT or IVCC voltages forces a deactivation

of the driver stages, thus stopping the switching activity, but has no effect on the SPI register settings.

Moreover the double function pin EN/INUVLO can be used as an input undervoltage protection by placing a

resistor divider from VIN to GND (refer to Chapter 10.3).

If EN/INUVLO undervoltage is detected, it will turn-off the IVCC voltage regulator, stop switching, stop

communications and reset all the registers.

Figure 4 shows a basic concept drawing of the supply domains and interactions among pins VIN, VDD and

IVCC/IVCC_EXT.

VIN

VREG (5V)

R₁

IVCC

Internal pre-regulated

EN/INUVLO

voltage Supply

Undervoltage

detection

R₂

IVCC_EXT

VREG

digital

VREG

analog

LS - Drivers

HS - Drivers

PGND

BSTx

Undervoltage

detection

Bandgap

Reference

Register

Banks

VDD

SPI & I/O

LOGIC

SWNx

Figure 4

Power Supply Concept Drawing

Datasheet

12

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Power Supply

Usage of EN/INUVLO pin in different applications

The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption

mode. An undervoltage threshold should be fixed by placing an external resistor divider (A) in order to avoid

low voltage operating conditions. This pin can be driven by a µC-port as shown in (B) .

A

B

V_in

VIN

R₁

R₂

R₁

R₂

EN/INUVLO

GND

EN/INUVLO

GND

µC Port

Figure 5

Usage of EN/INUVLO pin in different applications

Datasheet

13

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Power Supply

5.1

Different Power States

TLD5541-1 has the following power states:

•

SLEEP state

IDLE state

LIMP HOME state

ACTIVE state

The transition between the power states is determined according to these variables after a filter time of max.

3 clock cycles:

•

VIN level

EN/INUVLO level

IVCC level

IVCC_EXT level

VDD level

LHI level

DVCCTRL.IDLEbit state

The state diagram including the possible transitions is shown in Figure 6.

The Power-up condition is entered when the supply voltage V_VINexceed its minimum supply voltage threshold

V_VIN(ON)

.

SLEEP

When the device is powered it enters the SLEEP state, all outputs are OFF and the SPI registers are reset,

independently from the supply voltages at the pins VIN , VDD, IVCC, and IVCC_EXT. The current consumption

is low. Refer to parameters: I_VDD(SLEEP), and I_VIN(SLEEP)

.

The transition from SLEEP to ACTIVE state requires a specified time: t_ACTIVE

.

IDLE

In IDLE state, the current consumption of the device can reach the limits given by parameter I_VDD(P_5.3.4). The

internal voltage regulator is working. Not all diagnosis functions are available (refer to Chapter 10 for

additional informations). In this state there is no switching activity, independently from the supply voltages

V_IN, V_DD, IVCC and IVCC_EXT. When V_DDis available, the SPI registers are working and SPI communication is

possible.

Limp Home

The Limp Home state is beneficial to fulfill system safety requirements and provides the possibility to

maintain a defined current/voltage level on the output via a backup control circuitry. The backup control

circuitry turns on required loads during a malfunction of the µC. For detailed info, refer to Chapter 8.

When Limp Home state is entered, SPI registers are reset to their default values and SPI communication is

possible but only in read mode (SPI registers can be read but cannot be written). In order to regulate the

output current/voltage, it is necessary that V_INand IVCC_EXT are present and above their undervoltage

threshold.

ACTIVE

In active state the device will start switching activity to provide power at the output only when PWMI = HIGH.

To start the Highside gate drivers HSGD1,2 the voltage level V_BST1,2- V_SWN1,2needs to be above the threshold

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H-Bridge DC/DC Controller with SPI Interface

Power Supply

V_BST1,2- V_{SWN1,2_UVth}. In ACTIVE state the device current consumption via V_INand V_DDis dependent on the

external MOSFET used and the switching frequency f_SW

.

Power-up

LHI = LOW

EN/INUVLO = LOW

& EN/INUVLO = HIGH

SLEEP

EN/INUVLO = LOW

LHI = HIGH

& EN/INUVLO = HIGH

EN/INUVLO = LOW

LHI = HIGH

IDLE

LIMP HOME

VIN = LOW

or IVCC = LOW

VIN = HIGH

& IVCC = HIGH

EN/INUVLO = LOW

or IVCC_EXT = LOW

or VDD = LOW

& IVCC_EXT = HIGH

& VDD = HIGH

or DVCCTRL.IDLE = HIGH

& DVCCTRL.IDLE = LOW

LHI = LOW

LHI = HIGH

ACTIVE

Figure 6

Simplified State Diagram

5.2

Different Possibilities to RESET the device

There are several reset triggers implemented in the device.

After any kind of reset, the Transmission Error Flag (TER) is set to HIGH.

Under Voltage Reset:

EN/INUVLO: When EN/INUVLO is below V_EN/INUVLOth(P_5.3.7), the SPI interface is not working and all the

registers are reset to their default values. In addition, the device enters SLEEP mode and the current

consumption is minimized.

VDD: When V_VDDis below V_VDD(UV)(P_5.3.6), the SPI interface is not working and all the registers are reset to their

default values.

Reset via SPI command:

There is a command (DVCCTRL.SWRST= HIGH) available to RESET all writeable registers to their default

values. Note that the result coming from the Calibration routine, which is readable by the SPI when

DVCCTRL.ENCAL= HIGH, is not reset by the SWRST.

Reset via Limp Home:

When Limp Home state is detected the registers are reset to the default values.

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H-Bridge DC/DC Controller with SPI Interface

Power Supply

5.3

Electrical Characteristics

Table 5

EC Power Supply

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Power Supply V_IN

Input Voltage Startup

V_VIN(ON)

–

4.7

4.5

V

V_INincreasing;

P_5.3.1

V

_EN/INUVLO= HIGH;

_DD= 5 V;

IVCC = IVCC_EXT =

10 mA;

Input Undervoltage switch OFF V_VIN(OFF)

V_INdecreasing;

P_5.3.14

V

_EN/INUVLO= HIGH;

_DD= 5 V;

IVCC = IVCC_EXT =

10 mA;

Device operating current

I_VIN(ACTIVE)

–

4.4

–

6

mA ¹⁾ACTIVE mode;

_PWMI= 0 V;

V_EN/INUVLO= 0 V;

_CSN= V_DD= 5 V;

P_5.3.2

P_5.3.3

V

V_INSleep mode supply current I_VIN(SLEEP)

1.5

µA

V

V_IN= 13.5 V;

V_IVCC= V_{IVCC_EXT}= 0 V;

Digital Power Supply V_DD

Digital supply current

I_VDD

–

0.5

1.5

mA V_IN= 13.5 V;

_SCLK= 0 Hz;

V_PWMI= 0 V;

_EN=V_CSN= V_DD= 5 V;

V_EN/INUVLO= 0 V;

_CSN= V_DD= 5 V;

P_5.3.4

P_5.3.5

f

V

Digital Supply Sleep mode

current

I_VDD(SLEEP)

µA

V

V_IN= 13.5 V;

V_IVCC= V_{IVCC_EXT}= 0 V;

Undervoltage shutdown

threshold voltage

V_VDD(UV)

1

–

3

V

V_CSN= V_DD

;

P_5.3.6

V_SI= V_SCLK= 0 V;

SO from LOW to HIGH

impedance;

EN/INUVLO Pin characteristics

Input Undervoltage falling

Threshold

V_EN/INUVLOth1.6

1.75 1.9

90

V

–

P_5.3.7

P_5.3.8

P_5.3.9

1)

EN/INUVLO Rising Hysteresis

V_EN/INUVLO(hy

–

mV

st)

EN/INUVLO input Current LOW I_EN/INUVLO(LO0.45 0.89 1.34 µA

V_EN/INUVLO= 0.8 V;

W)

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H-Bridge DC/DC Controller with SPI Interface

Power Supply

Table 5

EC Power Supply (cont’d)

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

P_5.3.10

Min. Typ. Max.

EN/INUVLO input Current HIGH I_EN/INUVLO(HI1.1

2.2

3.3

µA

V_EN/INUVLO= 2 V;

GH)

LHI Pin characteristics

LOW level

V_LHI(L)

V_LHI(H)

I_LHI(L)

I_LHI(H)

0

-

0.8

5.5

18

V

–

P_5.3.16

P_5.3.17

P_5.3.18

P_5.3.19

HIGH level

2.0

6

-

V

–

L-Input pull-down current

H-Input pull-down current

Timings

12

30

μA

V_LHI= 0.8 V;

V_LHI= 2.0 V;

15

45

1)

SLEEP mode to ACTIVE time

t_ACTIVE

–

0.7

ms

P_5.3.11

V_IVCC= V_{IVCC_EXT}

_IVCC= 10 µF;

;

C

V_IN= 13.5 V;

V_DD= 5 V;

1) Not subject to production test, specified by design.

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

6

Regulator Description

The TLD5541-1 includes all of the functions necessary to provide constant current to the output as usually

required to drive LEDs. A voltage mode regulation can also be implemented (Refer to Chapter 6.7).

It is designed to control 4 gate driver outputs in a H-Bridge topology by using only one inductor and 4 external

MOSFETs. This topology is able to operate in high power BOOST, BUCK-BOOST and BUCK mode applications

with maximum efficiency.

The transition between the different regulation modes is done automatically by the device itself, with respect

to the application boundary conditions.

The transition phase between modes is seamless.

A SPI flag provides mode feedback to the µC (refer to SPI bits REGUSETMON.REGUMODFB).

6.1

Regulator Diagram Description

The TLD5541-1 includes two analog current control inputs (IIN1, IIN2) to limit the maximum Input current

(Block A1 and A7 in Figure 7).

A second analog current control loop (A5, A6 with complessive gain = IFBx_gm) connected to the sensing pins

FBL, FBH regulates the output current.

The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error

in the output current loop is used to determine the appropriate duty cycle to get a constant output current.

An external compensation network (R_COMP, C_COMP) is used to adjust the control loop to various application

boundary conditions.

The inductor current for the current mode loop is sensed by the R_SWCSresistor.

R_SWCSis used also to limit the maximum external switches / inductor current.

If the Voltage across R_SWCSexceeds its overcurrent threshold (V_{SWCS_buck}or V_{SWCS_boost}for buck or boost

operation respectively) the device reduces the duty cycle in order to bring the switches current below the

imposed limit.

The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations.

The control loop logic block (LOGIC) provides a PWM signal to four internal gate drivers. The gate drivers

(HSGD1,2 and LSGD1,2) are used to drive external MOSFETs in an H-Bridge setup . Once the soft start expires

a forced CCM regulation mode is performed.

The control loop block diagram displayed in Figure 7 shows a typical constant current application. The voltage

across R_FBsets the output current. R_INis used to fix the maximum input current.

The output current is fixed via the SPI parameter (LEDCURRADIM.ADIMVAL= 11110000_B= default at 100%)

plus an offset trimming (LEDCURRCAL.CALIBVAL= 0000_B= default in the middle of the range). Refer to

Chapter 8.1 for more details.

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Regulator Description

R_IN

I_IN

R_FB

I_OUT

V_IN

R_filter

M4

M3

M1

M2

C_OUT

HSGD2

LSGD2

HSGD1

LSGD1

FBH

FBL

V_OUT

C_filter

L_OUT

+

-

A₅

IIN1

IIN2

I_SWCSx

SWCS

SGND

BOOST

+

-

A₂

A₁

A₈

A₉

HSGD1

HSGD2

R_SWCS

SLOPE SELECTION

& Compensation

LOGIC

CLK

LSGD1

LSGD2

A₃

BUCK

A₆

A₇

SET

V_{i_REF}

COMP

R_COMP

C_COMP

V_COMP

Figure 7

Regulator Block Diagram - TLD5541-1

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

6.2

Adjustable Soft Start Ramp

The soft start routine limits the current through the inductor and the external MOSFET switches during

initialization to minimize potential overshoots at the output.

The soft start routine is applied:

•

At first turn on (first PWM rise after EN = High)

After Output Short to GND or Open Load detection

After Input Overvoltage detection

The soft start rising edge gradually increases the current of the inductor (L_OUT) over t_{SOFT_START}by clamping the

COMP voltage . The soft start ramp is defined by a capacitor placed at the SOFT_START pin.

Selection of the SOFT_START capacitor (C_{SOFT_START}) can be done according to the approximate formula

described in Equation (6.1):

V_{ss _ th _ eff}

(6.1)

t_{SOFT _ START}

=

⋅C_{SOFT _ START}

I_{SOFT _ START(PU )}

Note:

V_{ss_th_eff}is the soft start effectiveness threshold, that depends on load condition. Its value is about

0.7 V for the buck mode and 1.4 V for the boost mode

The SOFT START pin is also used to implement a fault mask and wait-before-retry time, on rising and falling

edge respectively, see and chapter Chapter 10.2 for details.

If an open load or a short on the output is detected, a pull-down current source I_{SOFT_START_PD}(P_6.4.20) is

activated. This current brings down the V_{SOFT_START}until V_{SOFT_START_RESET}(P_6.4.22) is reached, then the pull-up

current source I_{SOFT_START_PU}(P_6.4.19) turns on again. If the fault condition hasn’t been removed until

V_{SOFT_START_LOFF}(P_6.4.21) is reached, the pull-down current source turns back on again, initiating a new cycle.

This will continue until the fault is removed.

If an input overvoltage is detected the soft start is kept low as long as the overvoltage remains.

At first PWMI rise after EN = High, the internal PWM is extended till one of the 2 following condition is reached:

•

Until V_{SOFT_START}exceeds V_{Soft_Start1,2_LOFF}

Until V_FBH-FBLexceeds V_{FBH_FBL_OL}

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

8 clock cycles

VFB1

VVFB_S2G

SWN

SHORT

DETECTION

I

SOFT_START_PU

SOFT_START_PD

I_{SOFT_START}

V_{SOFT_START}

I

V

soft_Start_reg

V

soft_Start_LOFF

Vsoft_Start_RESET

Application

Status

Normal

Operation

Normal

Operation

Vout shorted to GND

Event

Vout short to GND

applied

Event

Vout short to GND

removed

Figure 8

Soft Start timing diagram on a short to ground detected by the VFB pin

6.3

Switching Frequency setup

The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ

pin to GND or by supplying a sync signal as specified in chapter Chapter 11.2. Select the switching frequency

with an external resistor according to the graph in Figure 9 or the following approximate formulas.

f_SW[kHz] = 5375*(R_FREQ[kΩ])^−0.8

R_FREQ[kΩ]= 46023*(f_SW[kHz])^−1.25

(6.2)

(6.3)

Figure 9

Switching Frequency f_SWversus Frequency Select Resistor to GND R_FREQ

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

6.4

Operation of 4 switches H-Bridge architecture

Inductor L_OUTconnects in an H-Bridge configuration with 4 external N channel MOSFETs (M1, M2, M3 & M4)

•

Transistor M1 and M3 provides a path between V_INand ground through L_OUTin one direction (Driven by top

and bottom gate drivers HSGD1 and LSGD2)

Transistor M2 and M4 provides a path between VOUT and ground through L_OUTin the other direction

(Driven by top and bottom gate drivers HSGD2 and LSGD1)

Nodes SWN1, SWN2, voltage across R_SWCS, input and load currents are also monitored by the TLD5541-1

BOOST

BUCK-BOOST

BUCK

MODE

M1

M2

M3

M4

ON

PWM

OFF

ON

OFF

PWM

Figure 10 4 switches H-Bridge architecture Transistor Status summary

V_IN

V_OUT

M1

M4

M3

HSGD2

LSGD2

HSGD1

LSGD1

L_OUT

SWN1

SWN2

M2

R_SWCS

Figure 11 4 switches H-Bridge architecture overview

6.4.1

Boost mode (V_IN< V_OUT)

•

M1 is always ON, M2 is always OFF

Every cycle M3 turns ON first and inductor current is sensed (peak current control)

M3 stays ON until the upper reference threshold is reached across R_SWCS(Energizing)

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

•

M3 turns OFF, M4 turns ON until the end of the cycle (Recirculation)

Switches M3 and M4 alternate, behaving like a typical synchronous boost Regulator (see Figure 12)

V_IN

V_OUT

ON

M1

M4

(2) Recirculation

I_LOUT

HSGD2

LSGD2

HSGD1

LSGD1

L_OUT

SWN1

SWN2

(1) Energizing

OFF

M2

M3

t

M1

+

M4

M1

+

M4

M1

+

M4

M1+M3

R_SWCS

Figure 12 4 switches H-Bridge architecture in BOOST mode

Simplified comparison of 4 switches H-Bridge architecture to traditional asynchronous Boost approach.

•

M2 is always OFF in this mode (open)

M1 is always ON in this mode (closed connection of inductor to V_IN)

M4 acts as a synchronous diode, with significantly lower conduction power losses (I²x R_DSONvs. 0.7 V x I)

Note:

Diode is source of losses and lower system efficiency!

L_OUT

D1

M1 (ON)

M4

V_IN

V_OUT

V_IN

M2

(OFF)

HSGD2

LSGD2

HSGD1

M3

LSGD1

R_SWCS

b) standard asynchronous BOOSTER

a) 4 switch architecture BOOSTER

Figure 13 4 switches H-Bridge architecture in BOOST mode compared to standard async Booster

6.4.2

Buck mode (V_IN> V_OUT)

•

M4 is always ON, M3 is always OFF

Every cycle M2 turns ON and inductor current is sensed (valley current control)

M2 stays ON until the lower reference threshold is reached across R_SWCS(Recirculation)

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Regulator Description

•

M2 turns OFF, M1 turns ON until the end of the cycle (Energizing)

Switches M1 and M2 alternate, behaving like a typical synchronous BUCK Regulator (see Figure 14)

V_IN

V_OUT

I_LOUT

ON

M1

M4

(3) Energizing

HSGD2

LSGD2

HSGD1

LSGD1

L_OUT

SWN1

SWN2

(4) Recirculation

t

OFF

M1

+

M4

M1

+

M4

M1

+

M4

M2

M3

M2+M4

R_SWCS

Figure 14 4 switches H-Bridge architecture in BUCK mode

Simplified comparison of 4 switches architecture to traditional asynchronous Buck approach.

•

M3 is always OFF in this mode (open).

M4 is always ON in this mode (closed connection inductor to V_OUT).

M2 acts as a synchronous diode, with significantly lower conduction losses (I²x R_DSONvs. 0.7 V x I)

L_OUT

M4

(ON)

L_OUT

M1

V_IN

V_OUT

V_IN

V_OUT

HSGD1

LSGD1

M3

(OFF)

HSGD1

HSGD2

M2

LSGD2

D1

R_SWCS

b) standard asynchronous BUCK

a) 4 switch architecture BUCK

Figure 15 4 switches H-Bridge architecture in BUCK mode compared to standard async BUCK

6.4.3

Buck-Boost mode (V_IN~ V_OUT)

•

When V_INis close to V_OUTthe controller is in Buck-Boost operation

All switches are switching in buck-boost operation. The direct energy transfer from the Input to the output

(M1+M4 = ON) is beneficial to reduce ripple current and improves the energy efficiency of the Buck-Boost

control scheme

•

The two buck boost waveforms and switching behaviors are displayed in Figure 16 below

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

VIN ≤ VOUT

I_LOUT

V_IN

V_OUT

M1

M4

(2) Direct Transfer

HSGD2

LSGD2

HSGD1

LSGD1

(4) Direct Transfer

M1

+

M3

M1

+

M4

M1

+

M4

M1

+

M3

M1

+

M4

M1

+

M4

M1

+

M3

M1

+

M4

M1

+

M4

t

SWN1

SWN2

L_OUT

(3) Recirculation

(1) Energizing

VIN ≥ VOUT

I_LOUT

M2

M3

R_SWCS

M2

+

M1

+

M1

+

M2

+

M1

+

M1

+

M2

+

M1

+

M1

+

t

M4

Figure 16 4 switches H-Bridge architecture in BUCK-BOOST mode

6.5

Fast Output Discharge Operation Mode - Multi Floating Switches Topology

Multiple light functions can be driven by a single DC/DC converter adopting a Multi Floating Switch (MFS)

topology. In a MFS topology, each LED Function is connected in series and can be independently turned off via

a bypass switch. Because of the series connections, all the functions are driven with the same current .

Different brightness can be achieved with individual PWM duty cycles.

In order to drive different LED functions in this topology, a Buck Boost converter is probably needed. A single

stage buck boost topology has high efficiency buts requires several µF of output capacitance (C_OUT). The extra

voltage present on this capacitor, when shorting one function to turn it off, may create a current spike in the

LEDs that have to remain on.

The TLD5541-1 has a dedicated state machine which controls a fast discharge of the output cap to a desired

fraction of the initial output voltage. This Fast Output Discharge feature (F.D.), if carefully configured, limits

the current spike during load jump events preventing LED damage.

An Example of the Multi Floating Switch topology architecture and operation are shown in Figure 17

INITIAL CONDITION

FAST DISCHARGE

FINAL CONDITION

Vout

Disharging

Vout

Initial

Vout

Final

C_OUT

C_IN

C_OUT

C

I

Disch

OUT

V_BAT

DC/DC

LITIX FLEX

DC/DC

LITIX FLEX

DC/DC

LITIX FLEX

F1

OFF

F1

OFF

To VFB

F1

ON

External MOSFET

Control via µC

External MOSFET

Control via µC

External MOSFET

Control via µC

(A)

(B)

(C)

F2

OFF

F2

ON

F2

ON

External MOSFET

Control via µC

External MOSFET

Control via µC

External MOSFET

Control via µC

Figure 17 Multi Floating Switch topology: operation sequence on 2 Functions: (F1+F2) to (F2)

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

The F.D. operation consists of discharging the capacitor C_OUTto the final load voltage (Figure 17-B) before the

bypass switch closure. The external Microcontroller Software has to take care of the synchronization between

the TLD5541-1 F.D. operation and the bypass Switches activation.

The discharged energy from C_OUTis recovered back to the Input capacitor C_INwhich could cause a small

overshoot on the C_INitself. This feature allows high efficiency designs also when PWM operation with repetitive

Load Jumps is needed.

The F.D. feature is needed when a negative V_OUTstep is performed, so when one or more LED functions are

switched off. If additional LED functions are turned on, increasing the output voltage, the F.D. does not have

to be used. In MFS topologies, a short interruption of the current is observed during the Load Transitions

(either positive or negative) in all the functions, until V_OUTis stable and the device control loop is able to

provide the target output current.

We will refer to any Voltage-Current or Load configuration just before the Load Jump as "Initial" (Figure 17-A),

while we will refer to any value after the system is in the new Load configuration as "Final" (Figure 17-C).

Set the Target C_OUTdischarge voltage

The Target output voltage (V_OUTFinal) of an F.D. operation is communicated to the TLD5541-1 as a fraction of the

V_OUTat the beginning of the Jump (V_OUTInitial), and not as an absolute Value.

In order to quickly discharge the output Capacitor to a desired Ratio of the initial voltage, two SPI commands

have to be sent to the TLD5541-1 register MFSSETUP1.

•

The first is to write in the MFSSETUP1.LEDCHAIN the Ratio Denominator

The second is to write in the MFSSETUP1 register the Ratio Numerator and the Start Of Multi Floating

Switch, respectively in the LEDCHAIN and SOMFS bitfields

After the second command, as soon as the Chip select is raised the F.D. begins. The final output voltage of the

F.D. operation, after a MFS routine is correctly performed, will be approximately:

RatioNumerator

(6.4)

V_OUTFinal

=

⋅V_OUTInitial

RatioDenominator

The MFSSETUP1.LEDCHAIN registers sets both the LED Ratio during F.D and the short circuit threshold. For

this reason both the correct V_OUTRatio and correct short circuit protection voltage have to be set according to

the LED Load. See Table 10 for reference.

To have the correct short circuit protection on a F.D. operation, the first LEDCHAIN value sent via SPI (Ratio

Denominator), should also guarantee an adequate short circuit detection for the Initial Load. The second

LEDCHAIN value (Ratio Numerator + SOMFS) should guarantee correct Short circuit detection for the Final

Load. For more information about short circuit protection, see Chapter 10.2.1.

Example:

If the VFB voltage divider for the Short circuit detection is set like in Table 10.

In order to jump from 6LED (18 V) to 2LEDs (6 V), the Ratio is 1/3 of initial voltage.

So the 2 SPI commands that have to be sent are:

Spi command 1: set MFSSETUP1 to 0x06 (Ratio Denominator = 6, V_{Short_LED}= 16.8 V)

Spi command 2: set MFSSETUP1 to 0x22 (Ratio Numerator+SOMFS = 0x02+0x20, V_{Short_LED}= 4.6 V )

Preparation time t_prep

:

The TLD5541-1 enables the user to set a delay between the beginning of the Load Jump and the moment in

which the switching activity will restart to provide output current. This delay is needed to safely close the

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

bypass switches (to short the LEDs) for the new Light configuration, after the Final V_OUTis reached and before

the normal switching activity would again raise the output voltage. See Figure 18.

The Preparation time has to be sufficient for the capacitors C_OUTand C_COMPto be discharged to the desired

value. The C_OUTdischarge time depends heavily on: I_DISCH, C_OUTsize, V_OUTInitial, V_OUTFinaland V_IN, so all those

values have to be considered when setting the preparation time. In order to set a preparation time on the

TLD5541-1, a SPI command has to be sent to the register MFSSETUP2.MFSDLY).

The Equation (6.5) below describes the relationship between the switching frequency f_SWand the

MFSSETUP2.MFSDLY register value.

1

(6.5)

t_prep

=

⋅

[2 + (MFSDLY )_dec

]

f_SW

For SPI command details refer to Chapter 12.6.

Fast Discharge Phase

After programming the desired output voltage Ratio via SPI , the right Preparation Time and activating the

state machine (MFSSETUP1.SOMFS= HIGH) the TLD5541-1 inverts the inductor current I_Land keeps it at the

switch current limit I_SwLimuntil the V_OUTreaches the desired target.

V_{SWCS _ boost}

(6.6)

I_SwLim

=

R_SWCS

Figure 18 displays the relation of inductor current I_Land the output voltage V_OUTduring a fast output discharge

operation mode.

External

Mosfet

Closure

I F1

No current at the Load

I F2

during F.O.D.

EOMFS

LED N. FINAL

+ SOMF

LED N. INITIAL

TPREP

SPI COMMANDS

SPI CSN

Break

Low

I_L

T_PREP

T_DISCHARGE

I_SwLim

V_OUT

V_INITIAL

V_FINAL

Current

Recovery

Normal Switching

activity F1 on

Fast Output Discharge

Normal Switching

activity F1+F2 on

Figure 18 Fast Output Discharge timing diagram

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H-Bridge DC/DC Controller with SPI Interface

Regulator Description

If the discharge current limit I_SwLimneeds to be reduced, the MFSSETUP1.ILIM_HALF_MFSbit can be used

to cut it in half (only during the F.D. phase and not in normal operation), see SPI Chapter for further details

Chapter 12.6.

Setting the EA_IOUT_MFS bit will reduce (only during the F.D. phase) the saturation current of the error

amplifier A6 that discharges the Comp capacitor.

Once V_OUTreaches the desired target, the current recovery phase brings I_Lfrom a negative value back to 0 A.

When the current recovery phase has ended, an internal SPI flag (MFSSETUP1.EOMFS) is set to HIGH and the

device stays in “Brake-Low condition” (both Lowside gatedrivers = ON) until the programmed preparation

time (MFSSETUP2.MFSDLY) expires and the TLD5541-1 starts automatically switching again. Figure 18

displays one Fast Output Discharge cycle.

The effective C_OUTdischarge current is smaller than the Inductor current and it depends on the application

condition, see Equation (6.7).

2

⎛

⎞

V

i

o

(6.7)

⎜

⎟

I_DISCH

=

⋅I_swLim

−

⋅

V +V

2Lf_SWV +V

o

i

⎝

i

o

⎠

Sequence of operations to perform a Fast Output Discharge

In order to perform a F.D operation, the user has to :

•

Set via SPI an adequate Preparation Time

Send via SPI to MFSSETUP1.LEDCHAINthe Ratio Denominator.

Send via SPI to MFSSETUP1.LEDCHAINthe Ration Numerator + SOMFS

Wait until the preparation time is expired (so the Vout has reached the target value)

Adjust the Floating switches to the new configuration

6.6

Flexible current sense

The flexible current sense implementation enables highside and lowside current sensing.

The Figure 19 displays the application examples for the highside and lowside current sense concept.

V_IN

Highside

Sensing

Lowside

Sensing

FBH

FBL

FBH

FBL

Figure 19 Highside and lowside current sensing - TLD5541-1

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Regulator Description

6.7

Programming Output Voltage (Constant Voltage Regulation)

For a voltage regulator, the output voltage can be set by selecting the values R_FB1, R_FB2and R_FB3according to

the following Equation (6.8):

⎛

⎞

⎛

⎞

V_{FBH − FBL}

⎜

⎟

⎜

⎟

V_OUT= I_FBH

+

⋅ R_FB1

+

− I_FBL⋅ R_{FB 3}+ V_{FBH − FBL}

(6.8)

⎜

⎝

⎟

⎠

R_{FB 2}

⎠

⎝

After the output voltage is fixed via the resistor divider, the value can be changed via the Analog Dimming bits

ADIMVAL.

If Analog dimming is performed, due to the variations on the I_FBL(I_{FBL_HSS}(P_6.4.9) and I_{FBL_LSS}(P_6.4.40))

current on the entire voltage spanning, a non linearity on the output voltage may be observed. To minimize

this effect RFBx resistors should be properly dimensioned.

V_OUT

R_FB1

I_FBH

FBH

R_FB2

I_FBL

FBL

R_FB3

Figure 20 Programming Output Voltage (Constant Voltage Regulation)

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Regulator Description

6.8

Electrical Characteristics

Table 6

EC Regulator

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Regulator:

V_(FBH-FBL)threshold

V_(FBH-FBL)145.5 150

154.5 mV ADIM.ADIMVAL= P_6.4.1

11110000_B;

V_(FBH-FBL)threshold @ analog

dimming 10%

V_(FBH-

12

15

18

mV ADIM.ADIMVAL= P_6.4.5

00011000_B;

Calibration

Procedure not

performed

1)

FBL)_10

FBH Bias current @ highside

sensing setup

I_{FBH_HSS}

I_{FBL_HSS}

I_{FBH_LSS}

I_{FBL_LSS}

65

17

-7.5

-45

-

110

30

155

43

-2.5

-20

-

µA

V

= 7 V;

P_6.4.8

P_6.4.9

P_6.4.39

P_6.4.40

P_6.9.1

P_6.9.2

FBL

V

_{FBH - FBL}= 150 mV;

1)

FBL Bias current @ highside

sensing setup

V

= 7 V;

FBL

V

_{FBH - FBL}= 150 mV;

1)

FBH Bias current @ lowside

sensing setup

-4

V

= 0 V;

FBL

V

_{FBH - FBL}= 150 mV;

1)

FBL Bias current @ lowside

sensing setup

-30

2

V

= 0 V;

FBL

V_{FBH - FBL}= 150 mV;

1)

FBH-FBL High Side sensing

entry threshold

V_{FBH_HSS_in}

V

increasing;

FBH1

c

FBH-FBL High Side sensing exit V_{FBH_HSS_d}

threshold

-

1.75

-

V

decreasing;

FBH

ec

OUT Current sense Amplifier g_mIFBx_gm

–

890

1.4

91

–

µS

V

P_6.4.10

P_6.4.11

P_6.4.12

Output Monitor Voltage

V_IOUTMON1.33

1.47

93

V_{FBH - FBL}= 150 mV;

1)

Maximum BOOST Duty Cycle

D_{BOOST_MA}89

%

f = 300 kHZ;

sw

X

Input Current Sense threshold V_IIN1-IIN2

V_IIN1-IIN2

46

–

50

54

mV

mS

V

–

P_6.4.13

P_6.4.14

P_6.4.15

1)

Input Current sense Amplifier I_{IN_gm}

g_m

2.12

1

–

1)

Input current Monitor Voltage V_IINMON

0.95

1.05

60

V

= 50 mV;

IIN1 - IIN2

V_IIN1= V_VIN(ON)to 55 V;

1)

Switch Peak Over Current

Threshold - BOOST

V_{SWCS_boost}40

50

mV

P_10.8.1

5

1)

Switch Peak Over Current

Threshold - BUCK

V_{SWCS_buck}-60

-50

-40

P_10.8.1

6

Soft Start

Soft Start pull up current

I_{Soft_Start_P}22

26

32

µA

V_{Soft_Start}= 1 V;

P_6.4.19

U

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Regulator Description

Table 6

EC Regulator (cont’d)

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)

Parameter

Symbol

Values

Typ.

2.6

Unit Note or

Test Condition

Number

Min.

Max.

3.2

Soft Start pull down current

I_{Soft_Start_P}2.2

µA

V_{Soft_Start}= 1 V;

P_6.4.20

P_6.4.21

P_6.4.22

P_6.9.3

D

Soft Start Latch-OFF Threshold V_{Soft_Start_L}1.65

1.75

0.2

2

1.85

0.3

V

–

OFF

Soft Start Reset Threshold

V_{Soft_Start_R}0.1

V

–

ESET

Soft Start Voltage during

regulation

V_{Soft_Start_r}1.9

2.1

V

¹⁾No Faults

eg

Oscillator

Switching Frequency

f_SW

285

300

315

kHz T_j= 25°C;

P_6.4.23

R_FREQ= 37.4 kΩ;

SYNC Frequency

f_SYNC

200

2

–

700

–

kHz

V

–

P_6.4.24

P_6.4.25

SYNC

V_SYNC,ON

Turn On Threshold

SYNC

Turn Off Threshold

V_SYNC,OFF

I_SYNC,H

–

0.8

45

18

V

–

P_6.4.26

P_6.4.62

P_6.4.63

SYNC

High Input Current

15

6

30

12

µA

V_SYNC= 2.0 V;

V_SYNC= 0.8 V;

SYNC

I_SYNC,L

Low Input Current

Gate Driver for external Switch

Gate Driver undervoltage

threshold VBST1,2-

VSWN1,2_UVth

V_BST1,2

V_{SWN1,2_UVt}

-

3.4

–

4

V

V_BST1,2- V_SWN1,2

decreasing;

P_6.4.64

h

HSGD1,2 NMOS driver on-state R_{DS(ON_PU)}1.4

2.3

1.2

2.3

1.2

–

3.7

2.2

3.7

1.8

–

Ω

V_BST1,2- V_SWN1,2= 5 V; P_6.4.28

_source= 100 mA;

_BST1,2- V_SWN1,2= 5 V; P_6.4.29

resistance (Gate Pull Up)

I

HS

HSGD1,2 NMOS driver on-state R_{DS(ON_PD)}0.6

Ω

V

resistance (Gate Pull Down)

I_sink= 100 mA;

HS

LSGD1,2 NMOS driver on-state R_{DS(ON_PU)}1.4

Ω

V_{IVCC_EXT}= 5 V;

I_source= 100 mA;

P_6.4.30

P_6.4.31

P_6.4.32

resistance (Gate Pull Up)

LS

LSGD1,2 NMOS driver on-state R_{DS(ON_PD)L}0.4

Ω

V_{IVCC_EXT}= 5 V;

I_sink= 100 mA;

1)

resistance (Gate Pull Down)

S

HSGD1,2 Gate Driver peak

sourcing current

I_{HSGD1,2_SR}380

mA

V_HSGD1,2- V_SWN1,2= 1 V

C

to 4 V;

V_BST1,2- V_SWN1,2= 5 V

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Regulator Description

Table 6

EC Regulator (cont’d)

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

P_6.4.33

Min.

Max.

–

1)

HSGD1,2 Gate Driver peak

sinking current

I_{HSGD1,2_SN}410

mA

V_HSGD1,2- V_SWN1,2= 4 V

K

to 1 V;

V

_BST1,2- V_SWN1,2= 5 V

1)

LSGD1,2 Gate Driver peak

sourcing current

I_{LSGD1,2_SRC}370

–

mA

P_6.4.34

P_6.4.35

V_LSGD1,2= 1 V to 4 V;

V_{IVCC_EXT}= 5 V;

1)

LSGD1,2 Gate Driver peak

sinking current

I_{LSGD1,2_SN}550

V_LSGD1,2= 4 V to 1 V;

K

V

_{IVCC_EXT}= 5 V;

1)

LSGD1,2 OFF to HSGD1,2 ON

delay

t_LSOFF-

15

35

30

60

40

75

ns

P_6.4.36

P_6.4.37

HSON_delay

1)

HSGD1,2 OFF to LSGD1,2 ON

delay

t_HSOFF-

LSON_delay

1) Not subject to production test, specified by design

Datasheet

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Digital Dimming Function

7

Digital Dimming Function

PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming

achieves brightness reduction by varying the duty cycle of a constant current in the LED string.

7.1

Description

A PWM signal can be transmitted to the TLD5541-1 as described below.

PWM via direct interface

The PWMI pin can be fed with a pulse width modulated (PWM) signals, this enables when HIGH and disables

when LOW the gate drivers of the main switches.

µC

PWM

Digital dimming

PWMI

+3.3V or +5V

VDD

CSN

SI

SPI

SO

SCLK

VSS AGND

Figure 21 Digital Dimming Overview

Note:

In Register REGUSETMON.REGUMODFB the regulation mode can be read. During PWMI = LOW the

SPI will always deliver the Regulation mode which was present at PWMI = HIGH as actual regulation

mode, instead of “no Regulation”.

To avoid unwanted output overshoots due to not soft start assisted startups, PWM dimming in LOW state

should not be used to suspend the output current for long time intervals. To stop in a safe manner

DVCCTRL.IDLE=HIGH or EN/INUVLO=LOW can be used.

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Digital Dimming Function

t_ACTIVE

V_EN/INUVLO

V_EN/INUVLOth

t

V_{IVCC_EXT_RTH,d}

+V_{IVCCX_HYST}

t_PWMI,H

T_PWMI

V_PWMI

V_PWMI,ON

V_PWMI,OFF

t

Switching

activity

t

I_LED

V_IOUTMON

200mV

t

Softstart

Normal

Gate ON

Diag ON

Normal

Dim

Normal

Gate ON

Diag ON

Dim

Power ON

Gate ON

Gate OFF

Diag OFF

Gate OFF

Diag OFF

Gate OFF

Diag OFF

Diagnosis ON

Figure 22 Timing Diagram LED Dimming and Start up behavior example ( V_VDDand V_VINstable in the

functional range and not during startup)

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Digital Dimming Function

7.2

Electrical Characteristics

Table 7

EC Digital Dimming

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or Test Condition Number

Min.

Max.

PWMI Input:

PWMI

Turn On Threshold

V_PWMI,ON

V_PWMI,OFF

I_PWMI,H

2

–

V

–

P_7.2.1

P_7.2.2

P_7.2.4

P_7.2.5

PWMI

Turn Off Threshold

–

0.8

45

18

V

–

PWMI

High Input Current

15

6

30

12

µA

V_PWMI= 2.0 V;

V_PWMI= 0.8 V;

PWMI

I_PWMI,L

Low Input Current

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Analog Dimming

8

Analog Dimming

The analog dimming feature allows further control of the output current. This approach is used to:

•

Reduce the default current in a narrow range to adjust to different binning classes of the used LEDs.

Adjust the load current to enable the usage of one hardware for several LED types where different current

levels are required.

•

Reduce the current at high temperatures (protect LEDs from overtemperature).

Reduce the current at low input voltages (for example, cranking-pulse breakdown of the supply or power

derating).

8.1

Description

The analog dimming feature is adjusting the average load current level via the control of the feedback error

Amplifier voltage (V_FBH-FBL).

The current adjustment is done via a 8BIT SPI parameter (LEDCURRADIM.ADIMVAL). Refer to Figure 23.

V_FBH-FBL

150mV

Bitcode

b´11110000

8 BIT SPI adjustment

0

Figure 23 Analog Dimming Overview

Analog dimming adjustment during Limp Home state:

To enter in Limp Home state the LHI pin must be HIGH.

Note:

If the PWMI and the EN/INUVLO are not set to HIGH, it is not possible to enable switching, even during

Limp Home state.

In Limp Home state the analog dimming control is done via the SET pin. A Resistor divider between

IVCC/IVCC_EXT, SET and GND is used to fix a default load current/voltage value (refer to Figure 24 below).

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Analog Dimming

C_IN

> V_IN(PO)

> V_{IVCC_EXT_RTH,d}

IVCC

C_IVCC

IVCC_ext

IVCC

VIN

EN/INUVLO

Current

Regulation

R_FB

D₂

D₁

default output

current/voltage

adjustment

BST1

BST2

SET

C_OUT

C_BST1C_BST2

M₁

M₂

M₄

HSGD1

SWN1

L_OUT

LIMPHOME

FAIL SAFE Circuit

M₃

LHI

HIGH

LSGD1

SWCS

Load

PWMI_LH

FAIL SAFE Circuit

SGND

PGND1

PGND2

Set HIGH to

activate output

PWMI

LSGD2

SWN2

HSGD2

VFB

CSN

SI

SO

SPI Writing

disabled during

Limp Home state

FBH

FBL

SCLK

VSS AGND

Figure 24 Limp Home state schematic overview

Using the SET pin to adjust the output current:

The SET pin is ignored if the device is not in Limp Home state.

For the calculation of the output current I_OUTthe following Equation (8.1) is used:

V_FBH− V_FBL

I_OUT

=

(8.1)

R_FB

A decrease of the average output current can be achieved by controlling the voltage at the SET pin (V_SET

between 0.2 V and 1.4 V. The mathematical relation is given in the Equation (8.2) below:

)

V _SET− 200 mV

I _OUT

=

(8.2)

R _FB⋅ 8

If V_SETis 200 mV (typ.) the LED current is only determined by the internal offset voltages of the comparators.

To assure the switching activity is stopped and I_OUT= 0, V_SEThas to be < 100 mV, see Figure 25.

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Analog Dimming

V_FBH-FBL

150mV

100mV

0mV

V_SET

200mV

1.4V 1.5V

Analog Dimming

Disabled

Analog Dimming Enabled

Figure 25 Analog Dimming Overview

8.2

LED current calibration procedure

The LED current calibration procedure improves the accuracy during analog dimming. In order to be most

effective, this routine has to be performed in the application, when the TLD5541-1 temperature and the output

voltage are the ones in which the driver has to be accurate. The output current must be 0 during the procedure

run. The optimum should be to re-calibrate the output periodically every time the application has PWMI=LOW

for a sufficent long time .

Current calibration procedure:

•

Power the Load with a low analog dimming value (for example 10%)

Set PWMI = LOW and disconnect the Load at the same time (to avoid Vout drifts from operating conditions

and bring the output current to 0)

•

Quickly (to avoid Vout drifts) µC enables the calibration routine: DVCCTRL.ENCAL= HIGH

Quickly (to avoid Vout drifts) µC starts the calibration: LEDCURRCAL.SOCAL= HIGH

Waiting time (needed to internally perform the calibration routine) → aprox. 200 µs

TLD5541-1 will set the FLAG: LEDCURRCAL.EOCAL= HIGH, when calibration routine has finished

Reconnect the load

The Output current is automatically adjusted to a low offset and more accurate analog dimming value

Once the Calibration routine is correctly performed, the output current accuracy with analog dimming = 10%

(LEDCURRADIM.ADIMVAL= 24) is 10%.

The Calibration routine is not affecting the accuracy at 100% analog dimming.

The ENCAL Bits affect both device operation and CALIBVAL reading result:

•

ENCAL = HIGH: the calibration result coming from the routine is used by internal circuitry and can be read

back from CALIBVAL

•

ENCAL = LOW: SPI value written in CALIBVAL is used by internal circuitry and can be read back; calibration

routine start is inhibited

As a result, μC can use a stored result from a previously performed calibration to directly impose the desired

value without waiting for a new routine to finish.

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Analog Dimming

OUT H-Bridge

V_{int_supply}

FBH

+

V_sense_in

FBL

R_FB

V_FBH-FBL

I_{OUT_sense}

V_sense_out

-

+

Latch

I_{DC_offset}

ADC out

-

to LED

Load

I_{IN_feedback}

ADC CLK

+

-

EA

ADC Latch

8 bit resolution

4 bit calibration

DAC

COMP

V_{ref_int}

2Bit Monitoring

Logic

ADC CLK

Figure 26 LED current Accuracy Calibration Overview

8.3

Electrical Characteristics

Table 8

EC Analog Dimming

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

1)

Source current on SET Pin

I_{SET_source}

–

1

µA

V

= 0.2 V to 1.4 V; P_8.3.4

SET

1) Specified by design: not subject to production test.

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Linear Regulator

9

Linear Regulator

The TLD5541-1 features an integrated voltage regulator for the supply of the internal gate driver stages.

Furthermore an external voltage regulator can be connected to the IVCC_EXT pin to achieve an alternative

gate driver supply if required.

9.1

IVCC Description

When the IVCC pin is connected to the IVCC_EXT pin, the internal linear voltage regulator supplies the internal

gate drivers with a typical voltage of 5 V and current up to I_LIM(P_9.2.2). An external output capacitor with low

ESR is required on pin IVCC for stability and buffering transient load currents. During normal operation the

external MOSFET switches will draw transient currents from the linear regulator and its output capacitor

(Figure 27, drawing A). Proper sizing of the output capacitor must be considered to supply sufficient peak

current to the gate of the external MOSFET switches. A minimum capacitance value is given in parameter C_IVCC

(P_9.2.4).

Alternative IVCC_EXT Supply Concept:

The IVCC_EXT pin can be used for an external voltage supply to alternatively supply the MOSFET Gate drivers.

This concept is beneficial in the high input voltage range to avoid power losses in the IC (Figure 27, drawing B).

Integrated undervoltage protection for the external switching MOSFET:

An integrated undervoltage reset threshold circuit monitors the linear regulator output voltage. This

undervoltage reset threshold circuit will turn OFF the gate drivers in case the IVCC or IVCC_EXT voltage falls

below their undervoltage Reset switch OFF Thresholds V_{IVCC_RTH,d}(P_9.2.9) and V_{IVCC_EXT_RTH,d}(P_9.2.5).

In Limp Home state the Undervoltage Reset switch OFF threshold for the IVCC has no impact on the switching

activity.

The Undervoltage Reset threshold for the IVCC and the IVCC_EXT pins help to protect the external switches

from excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of the

external logic level N-channel MOSFETs.

A

B

IVCC

Power

IVCC

Internal

VREG

Internal

VREG

V_IN

Power

On Reset

External

VREG

IVCC_EXT

Gate Drivers

Figure 27 Voltage Regulator Configurations

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Linear Regulator

9.2

Electrical Characteristics

Table 9

EC Line Regulator

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or Test Condition Number

Min.

Max.

IVCC

Output Voltage

V_IVCC

I_LIM

4.8

70

–

5

5.2

V

V_IN= 13.5 V;

0.1 mA ≤ I_IVCC≤ 50 mA;

1)

P_9.2.1

P_9.2.2

P_9.2.3

Output Current

Limitation

90

200

110

350

mA

mV

V_IVCC= 4 V;

V_IN= 5 V;

Drop out Voltage (V_IN-

V_DR

V_IVCC

)

I_IVCC= 10 mA;

1) 2)

IVCC Buffer Capacitor

C_IVCC

10

–

µF

V

P_9.2.4

P_9.2.5

3)

IVCC_EXT Undervoltage V_{IVCC_EXT_R}3.7

3.9

4.1

Reset switch OFF

V_{IVCC_EXT}decreasing;

TH,d

Threshold

3)

IVCC Undervoltage Reset V_{IVCC_RTH,d}3.7

switch OFF Threshold

3.9

4.1

V

P_9.2.9

P_9.2.6

V_IVCCdecreasing;

V_IVCCincreasing;

IVCC and IVCC_EXT

V_{IVCCX_HYST}0.3

0.33

0.36

Undervoltage Hysterisis

V_{IVCC_EXT}increasing;

1) Not subject to production test, specified by design

2) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum.

Use capacitors with LOW ESR.

3) Selection of external switching MOSFET is crucial. V_{IVCC_EXT_RTH,d}and V_{IVCC_RTH,d}min. as worst case V_GSmust be

considered.

Datasheet

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

10

Protection and Diagnostic Functions

10.1

Description

The TLD5541-1 has integrated circuits to diagnose and protect against overvoltage, open load, short circuits

of the load and overtemperature faults. Furthermore, the device provides a 2 Bit information of I_LED, I_INby the

SPI to the µC.

In IDLE state, only the Over temperature Shut Down, Over Temperature Warning, IVCC or IVCC_EXT

Undervoltage Monitor, V_DDor V_EN/INUVLOUndervoltage Monitor are reported according to specifications.

In Figure 28 a summary of the protection, diagnostic and monitor functions is displayed.

Protection and Diagnostic

SPI STD

Diagnosis

Overvoltages

SPI

Open Load

SPI

No output current

OR

Short at the Load

SPI

Linear Regulators

OFF

(only IVCC disabled

Device

Overtemperature

OR

in case of

Input

overtemperature)

Undervoltage

Monitoring

2BIT data

IOUT

Read-back via

SPI

IIN

Mode Indication

IOUT

IOUTMON

IINMON

KILIS Factor 8

KILIS Factor 20

IIN

Figure 28 Protection, Diagnostic and Monitoring Overview - TLD5541-1

Note:

A device Overtemperature event overrules all other fault events!

Datasheet

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Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

10.2

Output Overvoltage, Open Load, Short circuit protection

The VFB pin measures the voltage on the application output and in accordance with the populated resistor

divider, short to ground, open load and output overvoltage thresholds are set. Refer to Figure 30 and Figure 29

for more details.

V_FB

Overvoltage

V_{FB_OVTH}= fixed

Open LOAD

V_{FB_OL,rise}= fixed

Normal Operation

V_{FB_S2G}= adjustable

Short

Circuit

e.g. 50V

V_OUT

Threshold can be

adjusted via SPI

Figure 29 Definition of Protection Ranges

V_IN

C_IVCC

IVCC

D₂

D₁

V_OUT

R_FB

BST1

BST2

C_BST1C_BST2

M₁

M₂

M₄

V_{VFB_OVTH}

V_{VFB_OL,rise}

R_VFBH

C_OUT

HSGD1

SWN1

L_OUT

M₃

LSGD1

SWCS

R_VFBL

V_{VFB_S2G}

R_SWCS

SGND

PGND

LSGD2

SWN2

HSGD2

VFB

FBH

FBL

Figure 30 VFB Protection Pin - Overview

10.2.1

Short Circuit protection

The device detects a short circuit at the output if this condition is verified:

The pin VFB falls below the threshold voltage V_{VFB_S2G}for at least 8 clock cycles

•

Datasheet

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Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

During the rising edge of the Soft Start the short circuit detection via VFB is ignored until V_{SOFT_START_LOFF}(see

Figure 8).

After a short circuit detection, the SPI flag (SHRTLED) in the STD diagnosis register is set to HIGH and the gate

drivers stop delivering output current (Break-Low condition, both LS MOSFETs ON). The Device will auto

restart with the soft start routine described in Chapter 6.2. The dedicated diagnosis flag (SHRTLED) will be

cleared after the next reading cycle of the STD diagnosis.

A voltage divider between V_OUT, VFB pin and AGND is used to adjust the application short circuit thresholds

following Equation (10.1).

R_VFBH+ R_VFBL

V_short

= V_VFB

⋅

(10.1)

_ led

_ S 2 G

R_VFBL

The short circuit threshold voltage V_{VFB_S2G}(P_10.8.1) is set by 4-Bits in the SPI register

MFSSETUP1.LEDCHAINas shown in Table 10.

The configurable short circuit threshold is especially useful in 2 types of applications:

1) Multifloat switch applications:

Multifloat switch applications are applications with a series connection of LEDs and parallel transistors to

switch ON and OFF single (or multiple) LEDs in a string. The built in feature “fast output discharge operation

mode” enables such applications but the short circuit threshold has to be adjusted in accordance to the LED

changes. This synchronization is needed to avoid wrong short circuit detection during load step variations.

For this reason the register MFSSETUP1.LEDCHAINselects the short circuit threshold register but is also

related to the “fast dynamic behavior feature”. For more Info on the “fast output discharge operation mode”

please refer to Chapter 6.5.

2) Standard applications which require a large output voltage range:

The adjustable short circuit threshold V_{VFB_S2G}enables applications with a large V_OUToperation range.

The MFSSETUP1.LEDCHAIN register allows configuration of the short circuit threshold in 16 Steps.

The step size depends on the sizing of the R_VFBHand R_VFBLresistors.

In order to have proper short circuit detection MFSSETUP1.LEDCHAIN should be calculated as shown in

Equation (10.2).

ꢈ

∙ ꢐ_ꢈꢑꢒ− 38ꢓꢈ

75ꢓꢈ

ꢉℎꢊꢋꢌ _ꢍꢎꢏ

(10.2)

ꢀꢁꢂꢃꢄꢅꢆꢇ =

+ 1

Where K_VFB=R_VFBL/(R_VFBH+ R_VFBL) and V_{short_led}is the desired short circuit threshold value at V_OUT

The Table 10 below displays the relationship between the bitcode and the short circuit threshold voltage

_{VFB_S2G}based on an example (resistor divider R_VFBH= 59 kΩ, R_VFBL= 1.5 kΩ).

.

V

The application overvoltage protection is instead not dependent by LEDCHAIN and, based on the

Equation (10.3) for this particular resistor divider is fixed to 59.3 V.

Table 10

Adjustable Short Circuit threshold overview

LEDCHAIN

V_{OUT_OVLO}

k = R_VFBL/ (R_VFBHV_{open_load}V_{short_led}(V)

V_{VFB_S2G}(V)

Default

+ R_VFBL

0.025

)

(V_{FB_S2G}/ k)

Condition

1

2

3

4

5

59.3

54.4

1.5

0.038

0.113

0.188

0.263

0.338

4.6

7.6

10.7

13.7

Datasheet

44

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

Table 10

Adjustable Short Circuit threshold overview

LEDCHAIN

V_{OUT_OVLO}

k = R_VFBL/ (R_VFBHV_{open_load}V_{short_led}(V)

V_{VFB_S2G}(V)

Default

+ R_VFBL

0.025

)

(V_{FB_S2G}/ k)

Condition

6

59.3

54.4

16.8

0.413

0.488

0.563

0.638

0.713

0.788

0.863

0.938

1.013

1.088

1.163

7

19.8

8

22.8

default

9

25.9

10

11

12

13

14

15

0

28.9

32.0

35.0

38.1

41.1

44.2

47.2

During Limp Home state the short circuit threshold V_{VFB_S2G}is fixed at the default value (V_{VFB_S2G}/ V_{VFB_OVTH}),

approx. 1/3 of the fixed overvoltage protection circuit in the application. There is no relationship between the

analog dimming feature at VSET pin and the V_{VFB_S2G}threshold. The customer must take care by adjusting the

default voltage at SET pin to program the V_OUTbe higher than the default short circuit threshold.

During start-up the TLD5541-1 ignores the detection of a short circuit or an open load until the soft-start

capacitor reaches 1.75 V. To prevent false tripping after startup, a large enough soft-start capacitor must be

used to allow the output to get up to approximately 50% of the final value.

Note:

If the short circuit condition disappears, the device will re-start with the soft start routine as

described in Chapter 6.2.

10.2.2

Overvoltage Protection

A voltage divider between V_OUT, VFB pin and AGND is used to adjust the overvoltage protection threshold (refer

to Figure 30).

To fix the overvoltage protection threshold the following Equation (10.3) is used:

R_VFBH+ R_VFBL

V_{OUT _ OV _ protected}=V_{VFB _ OVTH}

⋅

(10.3)

R_VFBL

If V_VFBgets higher than its overvoltage threshold V_{VFB_OVTH}, the SPI flag (OUTOV) in the STD diagnosis set to

HIGH and the gate drivers stop switching for output regulation (Break-Low condition both LS MOSFETs ON).

When V_{VFB_OVTH}- V_{VFB_OVTH,HYS}threshold is reached the device will auto restart. The dedicated diagnosis flag

(OUTOV) will be cleared after the next reading cycle of the STD diagnosis.

If the SWTMOD.OUTOVLATbit is set to HIGH the overvoltage protection is changed into latched behavior and

the µC has to set the DVCCTRL.CLRLATbit to reset the OUTOV flag and restart the switching activities.

10.2.3

Open Load Protection

To reliably detect an open load event, two conditions need to be observed:

1) Voltage threshold: V_VFB> V_{VFB_OL,rise}

2) Output current information: V_(FBH-FBL)< V_{FBH_FBL_OL}

During the rising edge of the Soft Start the open load detection is ignored until V_{SOFT_START_LOFF}

.

Datasheet

45

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

After an open load detection, the SPI flag (OL) in the STD diagnosis register is set to HIGH and the gate drivers

stop switching (Break-Low condition). The Device will auto restart with a soft start routine. The dedicated

diagnosis flag (OL) will be cleared after the next reading cycle of the STD diagnosis.

After an Open Load error the TLD5541-1 is autorestarting the output control accordingly to the implemented

Softstart routine. An Open Load error causes an increase of the output voltage as well. An Overvoltage

condition could be reported in combination with an Open Load error (in general, multiple error detection may

happen if more error detection thresholds are reached during the autorestart funcion, as possible

consequence of reactive behavior at the output node during open load).

The COMP capacitor is discharged during an Open Load condition to prevent spikes if load reconnects. This

measure could artificially generate Short Circuit detections after open loads events.

10.3

Input voltage monitoring, protection and power derating

Input overvoltage and undervoltage shutdown levels can both be defined through an external resistor divider,

as shown in Figure 31.

Both INOVLO and EN/INUVLO pin voltages are internally compared to their respective thresholds by means of

hysteretic comparators.

Neglecting the hysteresis, the following equations hold:

⎛

⎞

R₁

⎜

⎟

UV_th= 1 +

⋅ EN / INUVLO

(10.4)

(10.5)

th

⎜

⎝

R₂+ R₃

⎠

⎛

⎞

R₁+ R₂

⎜

⎟

OV_th= 1 +

⋅ INOVLO

th

⎜

⎝

R₃

⎠

V_OUT⋅ I_OUT

P_IN

=

(10.6)

η

⎛

⎞

V_OUT⋅ I_OUT

⎜

⎟

I _IN

⎝

⎠

(10.7)

(10.8)

(10.9)

V_{IN _ boundary}

=

η

V _{IN 1− IN 2}

I _IN

=

R _IN

V_{FBH −FBL}

I_OUT

=

R_FB

Datasheet

46

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

Figure 31 Input Voltage Protection

In case of overvoltage event at the input, the STD bit VINOVLO is set. The softstart capacitor will be discharged

by an internal pull down switch.

After the overvoltage event disappeared the device will auto restart with the softstart function.

10.4

Input current Monitoring and Limiter

The two inputs (IIN1, IIN2) can be used to limit and monitor the Input current (Block A1 and A7 in Figure 7).

The control loop reduces the Comp voltage when the voltage accross the pins reaches Input Current Sense

threshold V_IIN1-IIN2to keep the input current below I_INMax Equation (10.10)

(10.10)

V_{IIN1 – IIN2}

I_INMax = ---------------------------

R_IIN

The input current, measured via IIN1 and IIN2 pins, can be monitored through an analog output pin and an SPI

routine.

The IINMON pin provides a linear indication of the current flowing through the input. The following

Equation (10.11) is applicable:

V_IINMON= I _IN⋅ R_IN⋅ 20

(10.11)

Note:

If the R_INvalue is choosen in a way that the current limitiation is much bigger than the nominal input

current during the application the current measurement becomes inaccurate. Best results for an

accurate current measurement via the V_IINMONpin is to set the current limit only slightly above the

specific application related nominal input current.

Purpose of the input current monitoring routine is to verify if the system is in current limitation.

•

The output of the Input Current Sense is compared to the internal precise reference voltage

The comparator works like a 2 bit window ADC referred to the internal precise reference voltage

To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready

when CURRMON.EOMON is read HIGH.

Datasheet

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Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

The result of the input monitor routine is reported on the CURRMON.INCURR bit.

Figure 32 Input Current Monitoring General Overview

10.5

Output current Monitoring

The output current can be monitored through an analog output pin and an SPI routine.

The IOUTMON pin provides a linear indication of the current flowing through the LEDs. The following

Equation (10.12) is applicable:

(10.12)

V_IOUTMON= 200 mV + I_OUT⋅ R_FB⋅ 8

Purpose of the SPI current monitor routine is to verify if the system is in loop.

•

The output of the Led Current Sense is compared to the output of the Analog Dimming DAC

The comparator works like a 2 bit window ADC around 8 bit DAC output

To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready

when CURRMON.EOMON is read HIGH.

When CURRMON.SOMON bit is set to HIGH both input and output current monitor routines are executed in

parallel.

The result of the monitor routine is reported on the CURRMON.LEDCURR bit.

OUT H-Bridge

ADC out

2Bit Monitoring

IOUTMON

V_{int_supply}

11b

10b

00b 01b

FBH

feedback

Logic

+

V_sense_in

V_FBH-FBL

R_FB

I_{OUT_sense}

-

FBL

ADC CLK

V_sense_out

+

Latch

I_{DC_offset}

ADC in

ADC out

-

to LED

Load

I_{IN_feedback}

ADC CLK

+

-

ADC Latch

EA

8 bit resolution

4 bit calibration

DAC

COMP

V_{ref_int}

Figure 33 Output Current Monitoring General Overview

Datasheet

48

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

10.6

Device Temperature Monitoring

A temperature sensor is integrated on the chip. The temperature monitoring circuit compares the measured

temperature to the warning and shutdown thresholds. If the internal temperature sensor reaches the warning

temperature, the temperature warning bit TWis set to HIGH. This bit is not latched (i.e. if the temperature falls

below the warning threshold (with hysteresis), the TWbit is reset to LOW again).

If the internal temperature sensor reaches the shut-down temperature, the Gate Drivers plus the IVCC

regulator are shut down as described in Figure 34 and the temperature shut-down bit: TSDis set to HIGH. The

TSDbit is latched while the Gate Drivers plus the IVCC regulator have an auto restart behavior.

Note:

The Device will start up with a soft start routine after a TSD condition disappear.

T_j

T_jSD,hyst

T_jSD

T_jW

T_{jSD_exit}

T_{jW_exit}

T_jW,Hyst

t

xSGDx

Gate Drivers

autorestart

Operating

OFF

t

IVCC

5V

IVCC

autorestart

OFF

t

TW bit

1

NO ERROR

TW bit is reset automatically

0

t

TSD error bit

1

0

TSD error bit latched until next reset or CLRLAT

Figure 34 Device Overtemperature Protection Behavior

Datasheet

49

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Protection and Diagnostic Functions

10.7

Electrical Characteristics

Table 11

EC Protection and Diagnosis

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or Test Condition Number

Min.

0.53

Max.

0.59

Short Circuit Protection

Short to GND threshold

V_{VFB_S2G}

0.563

V

V_VFBdecreasing;

MFSSETUP1.LEDCHA

IN= 1000_B

P_10.8.1

Temperature Protection:

1)

Thermal Warning

junction temperature

T_j,W

125

–

140

10

155

–

°C

P_10.8.2

P_10.8.3

P_10.8.4

P_10.8.5

Temperature warning T_j,W,hyst

Hysteresis

Over Temperature

Shutdown

T_j,SD

160

–

175

10

190

–

Over Temperature

T_j,SD,hyst

Shutdown Hysteresis

Overvoltage Protection:

VFB Over Voltage

Feedback Threshold

V_{VFB_OVTH}1.42

1.46

40

1.50

58

V

P_10.8.6

P_10.8.7

Output Over Voltage

Feedback Hysteresis

V_{VFB_OVTH,}25

mV

Output Voltage

decreasing;

HYS

Open Load and Open Feedback Diagnostics

Open Load rising

Threshold

V_{VFB_OL,rise}1.29

1.34

15

1.39

22.5

1.33

V

V_FBH-FBL= 0 V;

V_FB= 1.4 V;

P_10.8.9

P_10.8.10

P_10.8.11

Open Load reference

Voltage V_FBH-FBL

V_{FBH_FBL_O}

–

mV

V

L

Open Load falling

Threshold

V_{VFB_OL,fall}1.23

1.28

V_FBH-FBL= 0 V;

Input Overvoltage protection

Input Overvoltage rising V_INOVLOth1.9

Threshold

2

2.1

62

V

–

P_10.8.12

P_10.8.13

Input Overvoltage

V_INOVLO(hys18

40

mV

Threshold Hysteresis

t)

1) Specified by design; not subject to production test.

Note:

Integrated protection functions are designed to prevent IC destruction under fault conditions

described in the datasheet. Fault conditions are considered as “outside” normal operating range.

Protection functions are not designed for continuous repetitive operation.

Datasheet

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Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Infineon FLAT SPECTRUM Feature set

11

Infineon FLAT SPECTRUM Feature set

11.1

Description

The Infineon FLAT SPECTRUM feature set has the target to minimize external additional filter circuits. The goal

is to provide several beneficial concepts to provide easy adjustments for EMC improvements after the layout

is already done and the HW designed.

11.2

Synchronization Function

The TLD5541-1 features a SYNC input pin which can be used by a µC pin to define an oscillator switching

frequency. The µC is responsible to synchronize with various devices by applying appropriate SYNC signals to

the dedicated DC/DC devices in the system. Refer to Figure 35

Note:

The Synchronization function can not be used when the Spread Spectrum is active.

H-Bridge DCDC

MASTER

BUCK-

BOOST

SYNC

GATE

LOGIC

CONTROL

e.g. 400kHz

Phaseshift A

H-Bridge DCDC

Slave

BUCK-

BOOST

GATE

SYNC1

SYNC2

defined phase shift between

Outputs of different devices

SYNC

µC

LOGIC

INPUT

e.g. 400kHz

Phaseshift B

CONTROL

Figure 35 Synchronization Overview

Datasheet

51

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Infineon FLAT SPECTRUM Feature set

11.3

Spread Spectrum

The Spread Spectrum modulation technique significantly improves the lower frequency range of the

spectrum (f < 30 MHz).

By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and

also pass the average limits (average emission limits are -20dB lower than the peak emission limits). By using

spread spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor

is important for the low frequency filter characteristic. This can be an economic benefit if there is a strong

requirement for average limits.

The TLD5541-1 features a built in Spread Spectrum function which can be enabled (SWTMOD.ENSPREAD)

and adjusted via the SPI interface. Dedicated SPI-Bits are used to adjust the modulation frequency f_FM

,

(P_11.6.3) and (P_11.6.4) (SWTMOD.FMSPREAD) and the deviation frequency f_dev, (P_11.6.1) and (P_11.6.2)

(SWTMOD.FDEVSPREAD) accordingly to specific application needs. Refer to Figure 36 for more details.

The following adjustments can be programmed when SWTMOD.ENSPREAD= HIGH:

SWTMOD.FMSPREAD= LOW: 12 kHz

SWTMOD.FMSPREAD= HIGH: 18 kHz

SWTMOD.FDEVSPREAD= HIGH: ±8% of f_SW

SWTMOD.FDEVSPREAD= LOW: ±16% of f_SW

Note:

The Spread Spectrum function can not be used when the synchronization pin is used.

f_SW

f_dev

t

1

f

FM

Figure 36 Spread Spectrum Overview

Datasheet

52

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Infineon FLAT SPECTRUM Feature set

11.4

EMC optimized schematic

Figure 37 below displays the Application circuit with additional external components for improved EMC

behavior.

L_PI

C_IN2

V_IN

R_IIN

D_VS

Alternative

external

VREG supply

C_PI1C_PI2

C_PI3C_PI4

IVCC_EXT

IVCC

C_IVCC

VIN

IIN2

C_IN1

D₁

D₂

L_PO

R_FB

R_filter

C_filter

R_M4

BST1

BST2

C_OUT

D_HSG1

R_M1

C_BST2

R₁

R₂

R₃

M₄

IIN1

EN/INUVLO

M₁

R_VFBH

C_BST1

HSGD1

SWN1

C_M1

R_M2

C_M4

R_M3

C_M3

R_HSG1

C_PO1C_PO2

C_PO3C_PO4

L_OUT

R_HSG2

M₃

R_VFBL

D_LSG1

INOVLO

COMP

M₂

C_COMP

R_COMP

LSGD1

SWCS

C_M2

R_LSG1

C_{SOFT_START}

R_FREQ

D_LSG2

R_LSG2

D_HSG2

SOFT_START

FREQ

R_SWCS

4LED in

series /

1A

SGND

PGND1

PGND2

µC SYNC signal

Digital dimminig

SYNC

PWMI

LSGD2

IINMON

IOUTMON

Advanced monitoring via µC

+3.3V or +5V

SWN2

HSGD2

VFB

VDD

CSN

SI

SO

SCLK

FBH

FBL

C_FBH-FBL

C_FBH

Spread Spectrum ON /OFF via SPI

VSS AGND

C_FBL

R_SPI

Figure 37 Application Drawing Including Additional Components for an Improved EMC Behavior

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Datasheet

53

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Infineon FLAT SPECTRUM Feature set

11.5

Electrical Characteristics

Table 12

EC Spread Spectrum

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

–

Max.

–

Spread Spectrum Parameters

Frequency Deviation

1)

f_dev

f_FM

±8

%

P_11.6.1

P_11.6.2

P_11.6.3

P_11.6.4

SWTMOD.FDEV

SPREAD= HIGH;

1)

Frequency Deviation

Frequency Modulation

–

±16

12

–

%

SWTMOD.FDEV

SPREAD= LOW;

1)

kHz

SWTMOD.FMSP

READ= LOW;

1)

18

SWTMOD.FMSP

READ= HIGH;

1) Specified by design; not subject to production test.

Datasheet

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

12

Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines:

SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of

CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted

out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo

8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits.

Otherwise, a TER (i.e. Transmission Error) bit is asserted. In this way the interface provides daisy chain

capability with 16 bit as well as with 8 bit SPI devices.

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

SO

SI

CSN

SCLK

time

SPI_16bit.emf

Figure 38 Serial Peripheral Interface

12.1

SPI Signal Description

CSN - Chip Select

The system microcontroller selects the TLD5541-1 by means of the CSN pin. Whenever the pin is in LOW state,

data transfer can take place. When CSN is in HIGH state, any signals at the SCLK and SI pins are ignored and

SO is forced into a high impedance state.

CSN HIGH to LOW Transition

•

The requested information is transferred into the shift register.

SO changes from high impedance state to HIGH or LOW state depending on the signal level at pin SI.

If the device is in SLEEP mode, the SO pin remains in high impedance state and no SPI transmission will

occur.

•

TERFlag will set the Bit number 10 in the STD diagnosis Frame. This Bit is set to HIGH after an undervoltage

contition, reset via SPI command, on Limp Home state entering or after an incorrect SPI transmission. TER

Flag can be read also direcly on the SO line between the falling edge of the CSN and the first rising edge of

the SCLK according to the Figure 39.

Datasheet

55

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

STDDIAG.TER

SI

SO

OR

1

0

SO

S

SI

SPI

CSN

SCLK

S

SPI_16bitTER .emf

Figure 39

Combinatorial Logic for TER bit

CSN LOW to HIGH Transition

•

Command decoding is only done, when after the falling edge of CSN exactly a multiple (0,1, 2, 3, …) of eight

SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the

transmission error bit (TER) is set and the command is ignored.

Data from shift register is transferred into the addressed register.

SCLK - Serial Clock

This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the

falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the

serial clock. It is essential that the SCLK pin is in LOW state whenever chip select CSN makes any transition,

otherwise the command may be not accepted.

SI - Serial Input

Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling

edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to

Chapter 12.5 for further information.

SO Serial Output

Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN

pin goes to LOW state. New data will appear at the SO pin following the rising edge of SCLK.

Please refer to Chapter 12.5 for further information.

12.2

Daisy Chain Capability

The SPI of the TLD5541-1 provides daisy chain capability. In this configuration several devices are activated by

the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see

Figure 40), in order to build a chain. The end of the chain is connected to the output and input of the master

device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the

SCLK line of each device in the chain.

Datasheet

56

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

device 1

device 2

SPI

device 3

SPI

SI

SO SI

SO

MO

SPI

MI

MCSN

MCLK

SPI_DaisyChain_1.emf

Figure 40 Daisy Chain Configuration

In the SPI block of each device, there is one shift register where each bit from the SI line is shifted in with each

SCLK. The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is

finished. In single chip configuration, the CSN line must turn HIGH to make the device acknowledge the

transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2.

When using three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices

(depending on how many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must

turn HIGH (see Figure 41).

SO device 3

SI device 3

SO device 2

SI device 2

SO device 1

SI device 1

MI

MO

MCSN

MCLK

SPI_DaisyChain_2.emf

Figure 41 Data Transfer in Daisy Chain Configuration

Datasheet

57

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

12.3

Timing Diagrams

t_CS(lead)

t_CS(lag)

t_CS(td)

t_{SCLK(P )}

0.7V_DD

0.2V_DD

CSN

SCLK

SI

t_{SCLK (H)}

t_{SCLK (L)}

0.7V^DD

0.2V_DD

t_{SI (s u)}

t_{SI (h)}

0.7V_DD

0.2V_DD

t_SO(en)

t_{SO(v )}

t_{SO (dis)}

0.7V

cc

SO

0.2V

cc

SPI_Timings.emf

Figure 42 Timing Diagram SPI Access

Datasheet

58

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

12.4

Electrical Characteristics

V_IN= 8 V to 36 V, T_J= -40°C to +150°C, V_DD= 3 V to 5.5 V, all voltages with respect to ground; (unless otherwise

specified)

Table 13

EC Serial Peripheral Interface (SPI)

Symbol

Parameter

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Input Characteristics (CSN, SCLK, SI) - LOW level of pin

Max.

CSN

SCLK

SI

V_CSN(L)

V_SCLK(L)

V_SI(L)

0

–

0.8

V

–

P_12.4.1

P_12.4.2

P_12.4.3

–

Input Characteristics (CSN, SCLK, SI) - HIGH level of pin

CSN

SCLK

SI

V_CSN(H)

V_SCLK(H)

V_SI(H)

2

–

V_DD

94

V

–

P_12.4.4

P_12.4.5

P_12.4.6

P_12.4.7

2

–

V

2

–

V

L-input pull-up current at CSN pin -I_CSN(L)

H-input pull-up current at CSN pin -I_CSN(H)

L-Input Pull-Down Current at Pin

31

63

μA

V_DD= 5 V;

V_CSN= 0.8 V;

22

45

67

μA

V_DD= 5 V;

V_CSN= 2 V;

P_12.4.8

SCLK

I_SCLK(L)

I_SI(L)

6

12

18

μA

V_SCLK= 0.8 V;

V_SI= 0.8 V;

P_12.4.9

SI

P_12.4.10

H-Input Pull-Down Current at Pin

SCLK

I_SCLK(H)

I_SI(H)

15

30

45

μA

V_SCLK= 2 V;

V_SI= 2 V;

P_12.4.11

P_12.4.12

SI

Output Characteristics (SO)

L level output voltage

H level output voltage

V_SO(L)

V_SO(H)

0

–

0.4

V

I_SO= -2 mA;

I_SO= 2 mA;

P_12.4.13

P_12.4.14

V_DD

-

V_DD

0.4 V

V

_DD= 5 V;

V_CSN= V_DD

_SO= 0 V or

Output tristate leakage current

I_SO(OFF)

-1

–

1

μA

;

P_12.4.15

V

V_SO= V_DD

;

Timings

1)

Enable lead time (falling CSN to t_CSN(lead)200

rising SCLK)

–

ns

P_12.4.17

P_12.4.18

P_12.4.19

P_12.4.20

Enable lag time (falling SCLK to

rising CSN)

t_CSN(lag)

200

250

–

Transfer delay time (rising CSN to t_CSN(td)

falling CSN)

–

Output enable time (falling CSN to t_SO(en)

200

SO valid)

C_L= 20 pF at SO

pin;

Datasheet

59

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

Table 13

EC Serial Peripheral Interface (SPI) (cont’d)

Parameter

Symbol

Min.

Values

Typ.

–

Unit Note or

Test Condition

Number

Max.

200

1)

Output disable time (rising CSN to t_SO(dis)

–

ns

P_12.4.21

SO tristate)

C_L= 20 pF at SO

pin;

1)

Serial clock frequency

Serial clock period

f_SCLK

–

5

–

MHz

ns

P_12.4.22

P_12.4.24

P_12.4.25

P_12.4.26

P_12.4.27

1)

t_SCLK(P)

t_SCLK(H)

t_SCLK(L)

200

75

20

Serial clock HIGH time

Serial clock LOW time

ns

Data setup time (required time SI t_SI(su)

ns

to falling SCLK)

1)

Data hold time (falling SCLK to SI) t_SI(h)

20

–

ns

P_12.4.28

P_12.4.29

1)

Output data valid time with

capacitive load

t_SO(v)

100

C_L= 20 pF;

1) Not subject to production test, specified by design

Datasheet

60

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

12.5

SPI Protocol

The relationship between SI and SO content during SPI communication is shown in Figure 43. The SI line

represents the frame sent from the µC and the SO line is the answer provided by the TLD5541-1. The first SO

response is the response from the previous command.

SI

frame A

frame B

frame C

(previous

response)

response to

frame A

response to

frame B

SO

SPI_SI2SO.emf

Figure 43 Relationship between SI and SO during SPI communication

The SPI protocol will provide the answer to a command frame only with the next transmission triggered by the

µC. Although the biggest majority of commands and frames implemented in TLD5541-1 can be decoded

without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous

transmission to decode TLD5541-1 response frame completely.

More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows:

SI

write register A

read register A

(new command)

(previous

response)

Standard

diagnostic

register A

content

SO

SPI_RWseq.emf

Figure 44 Register content sent back to µC

There are 3 special situations where the frame sent back to the µC doesn't depend on the previously received

frame:

•

in case an error in transmission happened during the previous frame (for instance, the clock pulses were

not multiple of 8 with a minimum of 16 bits), shown in Figure 45

when TLD5541-1 logic supply comes out of an Undervoltage reset condition (V_DD< V_DD(UV)as shown in

Figure 46 or EN/INUVLO < V_EN/INUVLOth

)

in case of a read or write command for a “not used” or “reserved” register (in this case TLD5541-1 answers

with Standard Diagnosis at the next SPI transmission)

Datasheet

61

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

frame A

SI

(new

command)

(error in trans .)

(previous

response)

Standard diag +

TER

SO

SPI_SO_TER.emf

Figure 45 TLD5541-1 response after an error in transmission

V

_DD≥ V_DD(UV)

SI

frame A

frame B

frame C

Standard diag + TER

SO

(SO = „Z“)

response to frame B

Figure 46 TLD5541-1 response after coming out of Power-On reset at V_DD

Datasheet

62

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

12.6

SPI Registers Overview

15 14

Frame W/R RB ADDR

Write Register in bank 0

ADDR

Read Register in bank 0

ADDR

Read Standard Diagnosis

13

12 11 10

9

8

7

6

5

4

3

2

1

0

Data

SI

1

0

Data

0

x

0

1

0

x

Reading a register needs two SPI frames. In the first frame the read command is sent. In the second frame the

output at SPI signal SO will contain the requested information. The MSB will be HIGH (while in case of standard

diagnosis is LOW). A new command can be executed in the second frame.

12.6.1

Standard Diagnosis

The Standard Diagnosis reports several diagnostic informations and the status of the device and the utility

routines.

The bits UVLORST, TER, VINOVLO, OUTOV, IVCCUVLO, OL and SHRTLED are latched and automatically cleared

after a STD diagnosis reading (default condition if OUTOVLT is not set).

A CLRLAT command resets the diagnostic Latched Flags and Latched protections for the OUTOV, TSD bits,

restarting the switching activity if this was halted due the previously mentioned faults.

The TSD bit is always latched and clearable only via explicit CLRLAT command. Note that the OUTOV has

latched behavior only when SWTMOD.OUTOVLAT=1, see Chapter 10.2.2 for further details.

The STD bits which are real time status monitors or mirror of internal registers are not cleared after a STD

diagnosis reading or via explicit CLRLAT command:

•

The STATE bits and TW are real time status flags

The bits EOMON, EOMFS and EOCAL are mirror of internal register

The SWRST_BSTUV bit is the logic OR of:

•

latched SWRST flag after a DVCSTRL.SWRST command (clearable via STD Diagnosis reading )

real time monitor of gate driver undervolage (VBSTx-VSWNx_UVth)

In standard operating condition (active state, no Limp Home), if no special routines have been executed and

no faults have been detected, the readout of the STD should be 1000_H.

15

14

13

12 11 10

9

8

7

6

5

4

3

2

1

0

SWRST_ UVLO STATE TER EO

EOM EOC VINOV OUTOV IVCCU OL SHRTL TSD TW

BSTUV RST MON FS

AL

LO

VLO

ED

Datasheet

63

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

Field

Bits

14

Type

r

Description

SWRST_BSTUV

SWRST OR VBSTx-VSWNx_UVth Monitor

0_B, no SWRST or undervoltage on the Gate Drivers occured

1_B, there was at least one SWRST since last readout OR an

undervoltage condition at the gate drivers is occurring

UVLORST

STATE

13

r

V_DDOR V_EN/INUVLOUndervoltage Monitor

0_B, there was no V_DDOR V_EN/INUVLOundervoltage since last readout

1_B, there was at least one V_DDundervoltage OR V_EN/INUVLO

undervoltage condition since last readout

12:11

Operative State Monitor

00_B, (reserved)

01_B, Limp Home Mode

10_B, Active Mode

11_B, Idle Mode

TER

10

9

r

Transmission Error

0_B, Previous transmission was successful

(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)

1_B, Previous transmission failed or first transmission after reset

EOMON

End of LED/Input Current Monitor Routine Bit

0_B, Current monitoring routine not completed, not successfully

performed or never run.

1_B, Current Monitor routine successfully performed (is reset to 0_B

when SOMON is set to 1_B)

EOMFS

EOCAL

8

7

6

r

End of MFS Routine Bit

0_B, MFS routine not completed, not successfully performed or

never run.

1_B, MFS routine successfully performed (is reset to 0_Bwhen

SOMOFS is set to 1_B)

End of Calibration Routine

0_B, Calibration routine not completed, not successfully

performed or never run.

1_B, Calibration routine successfully performed (is reset to 0_B

when SOCAL is set to 1_B)

VINOVLO

V_INOVLOVoltage Monitor

0_B, V_INOVLObelow V_INOVLOththreshold since last readout

1_B, There was at least one V_INOVLOovervoltage condition since last

readout

OUTOV

5

4

r

Output overvoltage Monitor

0_B, Output overvoltage not detected since last readout

1_B, Output overvoltage was detected since last readout

IVCCUVLO

IVCC or IVCC_EXT Undervoltage Lockout Monitor

0_B, IVCC and IVCC_EXT above V_{IVCC_RTH,d}or V_{IVCC_EXT_RTH,d}threshold

since last readout

1_B, Undervoltage on IVCC or IVCC_EXT occurred since last

readout

Datasheet

64

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

Field

OL

Bits

3

Type

r

Description

Open Load in ON state Diagnosis

0_B, Open Load condition not detected since last readout

1_B, Open Load condition detected since last readout

SHRTLED

TSD

2

1

0

r

Shorted LED Diagnosis

0_B, Short circuit condition not detected since last readout

1_B, Short circuit condition detected since last readout

Over Temperature Shutdown

0_B, T_jbelow temperature shutdown threshold

1_B, Overtemperature condition detected since last readout

TW

Over Temperature Warning

0_B, T_jbelow temperature warning threshold

1_B, T_jexceeds temperature warning threshold

Datasheet

65

Rev. 1.1

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

12.6.2

Register structure

Table 15 describes in detail the available registers with their bit-fields function, size and position

Table 14 shows register addresses and summarize bit-field position inside each register

Table 14

Bit

Register Bank 0

15 14 13 12 11 10 9 8

W/ R ADDR

7

6

5

4

3

2

1

0

Name

Data

R

B

LEDCURR W/ 0

ADIM

LEDCURR W/ 0

CAL

0

1

0

1

0

0 0 ADIMVAL

R

1 1 x

0 1 x

1 0 x

x

SOCAL EOCAL CALIBVAL

R

SWTMOD W/ 0

R

x

OUTOV

LAT

x

ENSP FMSP FDEVSP

READ READ READ

DVCCTRL W/ 0

R

ENCAL CLRLA SWRS IDLE

T

MFSSETU W/ 0

0 1 EA_IO ILIM_ SOMFS EOMFS LEDCHAIN

UT_MF HALF

P1

R

S

_MFS

MFSSETU W/ 0

P2

0

1

0

1

1 0 MFSDLY

R

CURRMON W/ 0

R

0 0 x

1 1 x

x

SOMO EOMON INCURR

N

LEDCURR

x

REGUSET W/ 0

x

REGUMODFB

MON

R

A write to a non existing address is ignored, a read to a non existing register is ignored and the STD Diagnosis

Frame is send out.

Table 15

Register description

Field

Register name

Bits Type Purpose

LEDCURRADIM ADIMVAL

7:0 r/w LED Current Configuration Register

00000000_B, analog dimming @ 0% of LED current fixed via

R_FB

11110000_B, (default) analog dimming @ 100% of LED

current fixed via R_FB

Datasheet

66

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

Table 15

Register description (cont’d)

Register name

Field

Bits Type Purpose

LEDCURRCAL

CALIBVAL

3:0 r/w LED Current Accuracy Trimming Configuration Register

LED current calibration value definition, the first bit is the

calibration sign:

0000_B, (default) Initial state in the middle of the range

0111_B, maximum calibration value positive

1111_B, maximum calibration value negative

EOCAL

4

r

End of calibration routine signalling bit:

0_B, (default) calibration routine not completed, not

successfully performed or never run.

1_B, calibration successfully performed (is reset to 0_B

when SOCALis set to 1_B)

SOCAL

5

0

r/w Start of calibration routine signalling bit:

0_B, (default) no calibration routine started

1_B, calibration routine start (autoclear)

SWTMOD

FDEVSPREAD

r/w Switching Mode Configuration Register

Deviation Frequency f_DEVdefinition:

0_B, (default) ±16% of f_SW

1_B, ±8% of f_SW

FMSPREAD

ENSPREAD

OUTOVLAT

1

2

4

r/w Frequency Modulation Frequency f_FMdefinition:

0_B, (default) 12 kHz

1_B, 18 kHz

r/w Enable Spread Spectrum feature:

0_B, (default) Spread Spectrum modulation disabled

1_B, Spread Spectrum modulation enabled

r/w Output latch after overvoltage error enable Bit

0_B, (default) gate driver outputs are autorestarting

after an overvoltage event

1_B, gate drivers are latched in brake low condition and

bit is latched after an overvoltage event

DVCCTRL

IDLE

0

r/w Device Control Register

IDLE mode configuration bit:

0_B, ACTIVE mode (default)

1_B, IDLE mode

SWRST

CLRLAT

ENCAL

1

2

3

r/w Software reset bit:

0_B, (default) normal operation

1_B, execute reset command

r/w Clear Latch bit:

0_B, (default) normal operation

1_B, execute CLRLAT command

r/w Enable automatic output current calibration bit:

0_B, (default) DAC takes CALIBVAL from SPI registers

1_B, DAC takes CALIBVAL from last completed automatic

calibration procedure; SOCAL Bit can be set.

Datasheet

67

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

Table 15

Register description (cont’d)

Register name

Field

Bits Type Purpose

MFSSETUP1

LEDCHAIN

3:0 r/w Multifloat Switch and Short Circuit configuration Register

Short circuit threshold and MFS ratio bits: change the

V_{VFB_S2G}threshold and set the MFS jump ratio

0001_B, smallest Value 1 Step

0010_B, 2 Steps

1000_B, (default) 8 Steps

1111_B, 15 Steps

0000_B, largest Value 16 Steps

EOMFS

4

r

End of MFS routine bit:

0_B, (default) MFS routine not completed, not

successfully performed or never run.

1_B, MFS routine successfully performed (is reset to 0_B

when SOMFSis set to 1_B).

SOMFS

5

6

r/w Start of MFS routine bit:

0_B, (default) MFS routine not activated

1_B, MFS routine activated

ILIM_HALF

r/w Adjust Current Limit (Switch Peak Over Current Threshold)

during MFS operation:

0_B, (default) Switch Peak Over Current Threshold 100%

1_B, Switch Peak Over Current Threshold 50%

EA_IOUT_MFS

MFSDLY

7

r/w Bit to decrease the saturation current of the error

amplifier (A6) in current mode control loop only during

MFS routine:

0_B, (default) inactive

1_B, active: error amplifier current reduced to 20%

MFSSETUP2

7:0 r/w Multifloatswitch configuration register 2 (delay time

programming)

00000000_B, smallest delay time in respect to f_SW

11111111_B, largest delay time in respect to f_SW

00100000_B, (default) delay time in respect to f_SW

Datasheet

68

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Serial Peripheral Interface (SPI)

Table 15

Register description (cont’d)

Register name

Field

Bits Type Purpose

CURRMON

LEDCURR

1:0

3:2

4

r

Current Monitor Register

Status of the LED Current bits:

00_B, (default) LED current between Target and +25%

01_B, LED current above +25% of Target

10_B, LED current between Target and -25%

11_B, LED current below -25% of Target

INCURR

EOMON

Status of the Input Current bits:

00_B, (default) Input current between 75% and 90% of

Limit

01_B, Input current between 90% and the Limit

10_B, Input current between 60% and 75% of Limit

11_B, Input current below 60% of Limit

End of LED/Input Current Monitoring bit:

0_B, (default) Current monitoring routine not

completed, not successfully performed or never run.

1_B, Current Monitor routine successfully performed (is

reset to 0_Bwhen SOMONis set to 1_B)

SOMON

5

r/w Start of LED/Input Current Monitoring bit:

0_B, (default) Current monitor routine not started

1_B, Start of the current monitor routine

REGUSETMON

REGUMODFB

3:2

r

Regulation Setup And Monitor Register

Feedback of Regulation Mode bits:

01_B, (default) Buck

10_B, Boost

11_B, Buck-Boost

Datasheet

69

Rev. 1.1

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Application Information

13

Application Information

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Figure 47 Application Drawing - TLD5541-1 as current regulator

Table 16

BOM - TLD5541-1 as current regulator (I_OUT= 1 A, f_SW= 300 kHz)

Reference Designator

Value

Manufacturer

--

Part Number

Type

D₁, D₂

C_IN1

BAT46WJ

1 µF, 100 V

4.7 µF, 100 V

470 nF, 100 V

22 nF, 16 V

4.7 µF, 100 V

100 nF, 100 V

10 µF, 16 V

100 nF, 16 V

--

BAT46WJ

Diode

TDK

X7R

Capacitor

IC

C_IN2

TDK

X7R

C_filter

TDK

X7R

C_COMP

C_{SOFT_START}

C_OUT1

TDK

X7R

TDK

X7R

TDK

X7R

C_OUT2, C_OUT3

TDK

X7R

C_IVCC

TDK

X7R

C_BST1, C_BST2

IC₁

TDK

X7R

Infineon

Coilcraft

Panasonic

TLD5541-1

L_OUT

10 µH

XAL1010-103MEC

Inductor

Resistor

R_filter

50 Ω, 1%

--

R_FB

0.150 Ω, 1%

Datasheet

70

Rev. 1.1

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TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Application Information

Table 16

BOM - TLD5541-1 as current regulator (I_OUT= 1 A, f_SW= 300 kHz)

Reference Designator

Value

Manufacturer

Panasonic

Part Number

Type

R_IN

0.003 Ω, 1%

--

Resistor

R₁, R₂, R₃, R_PD, R_EN, R_PWMIxx kΩ, 1%

Panasonic

, R_Sense1, R_Sense2, R_SYNC

R_SCLK, R_SI, R_SO, R_CSN

,

R_VFBL, R_VFBH

R_COMP

1.5 kΩ, 56 kΩ, 1%

0 Ω, 1%

Panasonic

Infineon

--

Resistor

Transistor

--

R_FREQ

37.4 kΩ, 1%

0.005 Ω, 1%

--

R_SWCS

ERJB1CFR05U

IPG20N10S4L-35

M₁, M₂, M₃, M₄

Dual MOSFET:

100 V / 35 mΩ N-ch

V_BAT

D_TVS

M_RP

R_gate

Voltage Regulator

C_{VREG_OUT}

C_IN2

R_IIN

OUT

VS

Alternative external

VREG supply

GND

C_IN1

IVCC

C_IVCC

IVCC_ext

VIN

IIN2

R_filter

IVCC

D₂

D₁

C_filter

C_OUT2

IIN1

SET

C_OUT3

BST1

BST2

LIMPHOME

FAIL SAFE Circuit

C_OUT1

C_BST1C_BST2

V_DD

M₁

M₂

M₄

LHI

EN/INUVLO

V_OUT

HSGD1

SWN1

L_OUT

R_EN

I/O

INOVLO

C_COMP

M₃

LSGD1

SWCS

R_COMP

C_{SOFT_START}

COMP

PWMI_LH

FAIL SAFE Circuit

SOFT_START

Micro

controller

R_FREQ

FREQ

PWMI

SGND

PGND1

PGND2

R_PWMI

R_SENSE

C_FF

A/D

IINMON

IOUTMON

LSGD2

R_SYNC

SYNC

I/O

SWN2

HSGD2

VFB

V_DD

VDD

R_CSN

CSN

SI

FBH

R_SI

SPI

R_SO

SO

SCLK

FBL

R_SCLK

VSS AGND

GND

Figure 48 Application Drawing - TLD5541-1 as adjustable voltage regulator

Note:

Max Vout set to 20V by RFB1 and RFB2, input current limiter resistor R_INcan be moved at the output

to control the output current.

Table 17

BOM - TLD5541-1 as voltage regulator

Reference Designator

Value

Manufacturer

Part Number

BAT46WJ

X7R

Type

D₁, D₂

C_IN1

BAT46WJ

1 µF, 100 V

4.7 µF, 100 V

470 nF, 100 V

--

Diode

TDK

Capacitor

C_IN2

X7R

C_filter

X7R

Datasheet

71

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Application Information

Table 17

BOM - TLD5541-1 as voltage regulator

Reference Designator

Value

Manufacturer

TDK

Part Number

Type

C_COMP

C_FF

22 nF, 16 V

10 nF, 50 V

22 nF, 16 V

4.7 µF, 100 V

100 nF, 100 V

10 µF, 16 V

100 nF, 16 V

--

X7R

Capacitor

IC

TDK

X7R

C_{SOFT_START}

C_OUT1

_OUT2, C_OUT3

TDK

X7R

TDK

X7R

C

TDK

X7R

C_IVCC

TDK

X7R

C_BST1, C_BST2

IC₁

TDK

X7R

Infineon

Coilcraft

Panasonic

TLD5541-1

L_OUT

10 µH

XAL1010-103MEC

Inductor

Resistor

R_FF

1.5 kΩ, 1%

50 Ω, 1%

--

R_filter

R_FB1, R_FB2

150Ω, 20.5kΩ, 1%

0.005 Ω, 1%

xx kΩ, 1%

R_IN

R₁, R₂, R₃, R_PD, R_EN

,

R_PWMI, R_Sense1, R_Sense2,

R_SYNC, R_SCLK, R_SI, R_SO

,

R_CSN

R_VFBL, R_VFBH

R_COMP

1.5 kΩ, 24 kΩ, 1%

0 Ω, 1%

Panasonic

Infineon

--

Resistor

Transistor

--

R_FREQ

37.4 kΩ, 1%

0.005 Ω, 1%

--

R_SWCS

ERJB1CFR05U

IPG20N10S4L-35

M₁, M₂, M₃, M₄

Dual MOSFET:

100 V / 35 mΩ N-ch

Datasheet

72

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Application Information

13.1

Further Application Information

Typical Performance Characteristics of Device

TJꢁ=ꢁ25°C,ꢁV_IN=12Vꢁunlessꢁotherwiseꢁspecified

IVCCꢁDropoutꢁvsꢁCurrentꢁ

IVCCꢁVoltageꢁvsꢁTemperature

5,20

5,15

5,10

5,05

5,00

4,95

4,90

4,85

4,80

2,5

2

I_IVCC=10mA

Tj=ꢀ40°C

Tj=150°C

Tj=25°C

1,5

1

0,5

0

10

20

30

40

50

ꢀ40

10

60

110

LDOꢁcurrentꢁ[mA]

Temperatureꢁ[°C]

IVCCꢁLoadꢁregulationꢁ

V_{(FBHꢀFBL)ꢁ}ThresholdꢁvsꢁV_FBH

5,2

154

153

152

151

150

149

148

147

146

5,15

5,1

AnalogꢁDim.ꢁ=ꢁ100%

5,05

5

4,95

4,9

4,85

4,8

0

10

20

30

40

50

0

10

20

30

40

50

60

I_IVCC[mA]

VFBHꢁ[V]

V_{(FBHꢀFBL)ꢁ}ThresholdꢁvsꢁTemp

IOUTMONꢁVoltageꢁvsꢁTemp

1,44

1,43

1,42

1,41

1,4

154

153

152

151

150

149

148

147

146

AnalogꢁDim.=100%,ꢁFBH=0,15V

AnalogꢁDim.=100%,ꢁFBH=12V

AnalogꢁDim.=100%,ꢁFBH=60V

V_(FBHꢀFBL)=ꢁꢁ150mV

1,39

1,38

1,37

1,36

ꢀ40

10

60

110

ꢀ40

10

60

110

Temperatureꢁ[°C]

Figure 49 Characterization Diagrams 1

Datasheet

73

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Application Information

TJꢁ=ꢁ25°C,ꢁV_IN=12Vꢁunlessꢁotherwiseꢁspecified

IOUTMONꢁVoltageꢁvsꢁV_(FBHꢀFBL)

V_{(IIN1ꢀIIN2)ꢁ}ThresholdꢁvsꢁTemp

1,4

1,2

1

53

52

51

50

49

48

47

VIIN1=8V

VIIN1=13.5V

VIIN1=55V

V_IN=ꢁ12Vꢁ

I_VCC=10mA

0,8

0,6

0,4

0,2

0

20

40

60

80

100

120

140

ꢀ40

10

60

110

V_(FBHꢀFBL)[mV]

Temperatureꢁ[°C]

IINMONꢁVoltageꢁvsꢁTemp

I_FBH,ꢁI_FBLvsꢁV_FBH

120

100

80

1,04

1,03

1,02

1,01

1

I_FBLꢁ[uA]

I_FBHꢁ[uA]

V_{(IIN1ꢀIIN2)ꢁ}=ꢁ50mV

V_(FBHꢀFBL)=ꢁꢁ150mV

60

40

20

0,99

0,98

0,97

0,96

0

ꢀ20

ꢀ40

0

5

10 15 20 25 30 35 40 45 50 55 60

ꢀ40

10

60

110

VFBHꢁ[V]

Temperatureꢁ[°C]

OscillatorꢁFrequencyꢁvsꢁTemp

V_{(BSTxꢀSWNx)ꢁ}vsꢁTemp

800

700

600

500

400

300

200

100

4

3,9

3,8

3,7

3,6

3,5

3,4

3,3

3,2

3,1

V_IN=ꢁ12Vꢁ

R_FREQ=61.9ꢁkOhm

R_FREQ=37.4ꢁkOhm

R_FREQ=12.7ꢁkOhm

V

_(FBHꢀFBL)=ꢁꢁ150mV

VBSTxꢀVSWNx_decꢁ[V]

VBSTxꢀVSWNx_incꢁ[V]

ꢀ40

10

60

110

ꢀ40

10

60

110

Temperatureꢁ[°C]

Figure 50 Characterization Diagrams 2

Datasheet

74

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Application Information

TJ = 25°C, V_IN=12V unless otherwise specified

LSGDx on-state resistance vs Temp

HSGDx on resistance vs Temp

4,5

4

4,5

4

HSGDx_Pull-up

3,5

3

3,5

3

HSGDx_Pull-down

V_IN= 12V

I_VCC=10mA

LSGDx_Pull-Up

2,5

2

2,5

2

LSGDx_Pull-down

1,5

1

1,5

1

0,5

0

0,5

0

-40

10

60

110

-40

10

60

110

Temperature [°C]

V_COMPVoltage vs LSGD Duty Cycle

V_(SWCS-SGND)Treshold vs Temp

120

100

80

60

40

20

0

60

40

Boost

Buck

LSGD1_Buck [%]

LSGD2_Boost [%]

20

V_(SWCS-SGND)=0

fsw=300kHz

V_IN= 12V

0

-20

-40

-60

0,6

0,8

1

1,2

1,4

1,6

-40

10

60

110

V_COMP[V]

Temperature [°C]

Figure 51 Characterization Diagrams 3

For further information you may contact http://www.infineon.com/

•

Datasheet

75

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Package Outlines

14

Package Outlines

0ꢀ9 MAXꢀ

(0ꢀ65)

11 x 0ꢀ5 = 5ꢀ5

0ꢀ1

7

A

0ꢀ5

0ꢀ26

0ꢀ03

6ꢀ8

0ꢀ1

+0ꢀ03¹⁾

2)

37

B

0ꢀ05

36

25

0ꢀ13

24

48x

0ꢀ08

48

13

1

12

Index Marking

48x

0ꢀ1

0ꢀ4 x 45°

0ꢀ05

Index Marking

0ꢀ23

(0ꢀ35)

M

A B C

(0ꢀ2)

0ꢀ05 MAXꢀ

(5ꢀ2)

(6)

C

1) Vertical burr 0ꢀ03 maxꢀ, all sides

2) These four metal areas have exposed diepad potential

PG-VQFN-48-29, -31-PO V05

Figure 52 PG-VQFN-48-31 (with LTI)

Datasheet

76

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Package Outlines

H

C

0.6±0.15

SEATING

PLANE

0.08

48x

C

COPLANARITY

9

0.2 A-B D

48x

BOTTOMVIEW

1)

7

2)

0.2 A-B D H

4x

5

EXPOSEDDIEPAD

D

A

B

48

1

48

1

INDEXMARKING

0.5

0.22±0.05

0.08

A-B D C

48x

1)DOESNOTINCLUDEPLASTICORMETALPROTRUSIONO0F.25MAX.PERSIDE

2)EXPOSEDPADFORSOLDERINGPURPOSE

Figure 53 PG-TQFP-48-9

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Datasheet

77

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Revision History

15

Revision History

Revision

Rev. 1.0

Rev. 1.1

Date

Changes

2016-05-20 Released Datasheet

2018-02-08 LED number set to 0x22 on the MFS example register Chapter 6.5

2018-02-08 Added: CCM on regulator description Chapter 6.1

2018-02-08 Added item to Chapter 6.5

2018-02-08 Added TQFP package

2018-02-08 Changed R_VFBHto 59 kΩ and R_VFBLto 1.5 kΩ

2018-02-08 Corrected graph V_COMPvs DUTY

2018-02-08 Corrected soft start behavior Chapter 6.2 “if an open load”

2018-02-08 MFSSETUP2default value Chapter 12.6

2018-02-08 Divided In and out overvoltage protection def. Chapter 10.2 Chapter 10.3

2018-02-08 Modified Voltage regulator application Drawing and note, see Figure 48

2018-02-08 Specified Complessive gain of error amp Chapter 6.1

2018-02-08 Improved description of soft start Chapter 6.2

2018-02-08 Improved description of calibration Routine Chapter 8.2

2018-02-08 Added Soft Start mask in the Short circuit description Chapter 10.2

2018-02-08 Added input current limiter description Chapter 10.4

2018-02-08 Removed Parameter 6.4.2 covered now by updated 6.4.1 Chapter 6.7

Datasheet

78

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

Table of Content

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

3.1

3.2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

4.2

4.3

5

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Different Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Different Possibilities to RESET the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1

5.2

5.3

6

Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Regulator Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Adjustable Soft Start Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Switching Frequency setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operation of 4 switches H-Bridge architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Boost mode (V_IN< V_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Buck mode (V_IN> V_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Buck-Boost mode (V_IN~ V_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Fast Output Discharge Operation Mode - Multi Floating Switches Topology . . . . . . . . . . . . . . . . . . . . 25

Flexible current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Programming Output Voltage (Constant Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1

6.2

6.3

6.4

6.4.1

6.4.2

6.4.3

6.5

6.6

6.7

6.8

7

7.1

7.2

Digital Dimming Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8

Analog Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

LED current calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1

8.2

8.3

9

9.1

9.2

Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

IVCC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10

Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Output Overvoltage, Open Load, Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Short Circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Open Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Input voltage monitoring, protection and power derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Input current Monitoring and Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Output current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Device Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1

10.2

10.2.1

10.2.2

10.2.3

10.3

10.4

10.5

10.6

Datasheet

79

Rev. 1.1

2018-02-08

TLD5541-1

H-Bridge DC/DC Controller with SPI Interface

10.7

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11

Infineon FLAT SPECTRUM Feature set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Synchronization Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

EMC optimized schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.1

11.2

11.3

11.4

11.5

12

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12.1

12.2

12.3

12.4

12.5

12.6

12.6.1

12.6.2

13

13.1

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

14

15

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table of Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Datasheet

80

Rev. 1.1

2018-02-08

Please read the Important Notice and Warnings at the end of this document

Trademarks of Infineon Technologies AG

µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,

DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,

HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,

OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,

SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.

Trademarks updated November 2015

Other Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2018-02-08

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

WARNINGS

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

Document reference

(doc_number)


型号：	TLD5541-1QU
厂家：	Infineon
描述：	H-Bridge DC/DC Controller with SPI Interface
文件：	总81页 (文件大小：3396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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