TLE4473GV55_技术文档

Dual Low Drop Voltage Regulator

TLE 4473 GV55

Features

• Stand-by output 190 mA; 5 V ± 2%

• Main output: 300 mA, 5 V tracked to the stand-by

output

• Low quiescent current consumption

• Disable function separately for both outputs

• Wide operation range: up to 42 V

• Very low dropout voltage

P-DSO-12-2, -3, -6

• 2 independent reset circuits

• Watchdog

• Output protected against short circuit

• Wide temperature range: -40 °C to 150 °C

• Overtemperature protection

• Overload protection

Functional Description

The TLE 4473 is a monolithic integrated voltage regulator with two very low drop outputs,

a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum

of 190 mA. The stand-by regulator transforms an input voltage V_Iin the range of 5.6 V ≤

V_I≤ 42 V to V_Q2= 5.0 V (±2%) output voltage. The main output is tracked to the stand by

output voltage and provides also 5 V. Versions of the device with 5 V/3.3 V and 5 V/2.6 V

are available, please refer to the data sheet TLE 4473 G V53/TLE 4473 G V52. Two

Inhibit Pins allow to use either both output voltages or to disable only Q1 or to switch off

both outputs, the latter causing the current consumption to drop below 1 µA. The

TLE 4473 is designed to supply microprocessor systems and sensors under the severe

conditions of automotive applications and is therefore equipped with additional

protection functions against overload, short circuit and overtemperature. The device

operates in the wide junction temperature range of -40 °C to 150 °C.

Type

Ordering Code

Package

TLE 4473 GV55

Q67007-A9647

P-DSO-12-6

Data Sheet

1

Rev. 1.2, 2004-01-01

TLE 4473 GV55

The device features a reset with adjustable power on delay for each of the outputs. In

addition the output for the microcontroller supply comes up with a watchdog in order to

supervise a connected microcontroller

Reset and Watchdog Behavior

The reset output RO2 is in high-state if the voltage on the delay capacitor C_D2is greater

or equal V_DU2. The delay capacitor C_D2is charged with the current I_DC2for output

voltages greater than the reset threshold V_RT2. If the output voltage gets lower than V_RT2

(‘reset condition’) a fast discharge of the delay capacitor C_D2sets in and as soon as V_D2

gets lower than V_DL2the reset output RO2 is set to low-level. The time for the delay

capacitor charge is the reset delay time. For the power-on case the charging process of

C_D2starts from 0 V, which leads to the equation:

C

_D2× V_DU2

I_DC2

t_{D, on}= ----------------------------

(1)

for the power-on reset delay time.

When the voltage on the delay capacitor has reached V_DU2and reset was set to high, the

watchdog circuit is enabled and discharges C_D2with the constant current I_DD2

.

If there is no rising edge observed at the watchdog input, C_D2will be discharge down to

V_DL2. Then reset output RO2 will be set to low and C_D2will be charged again with the

current I_DC2until V_D2reaches V_DU2and reset will be set high again.

If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge

period C_D2is charged again and the reset output stays high. After V_D2has reached V_DU2

,

the periodical cycle starts again.

The watchdog timing is shown in Figure 1. The maximum duration between two

watchdog pulses corresponds to the minimum watchdog trigger time T_WI,tr. Higher

capacitances on pin D2 result in longer watchdog trigger times:

T_WI,tr

= 0.34 ms/nF × C_D2

(2)

max

If the output voltage Q1 decreases below V_RT1(typ. 4.65 V), the external capacitor C_D1

is discharged by the reset generator of the main output. If the voltage on this capacitor

drops below V_DL1, a reset signal is generated on pin 2 (RO1). If the output voltage rises

above the reset threshold, C_D1will be charged with the constant current I_DC1. After the

power-on-reset time the voltage on the capacitor reaches V_DU1and the reset output will

be set high again. The value of the power-on-reset time can be set within a wide range

depending of the capacitance of C_D1using the above given equation (1) analogous for

Q1.

Data Sheet

2

Rev. 1.2, 2004-01-01

TLE 4473 GV55

V_W

Ι

t

V

Ι

V_Q

T_{WD, p}

V_D2

T_{WI, tr}

V_DU2

V_DL2

t_{WD, L}

V_RO2

(V_DU2-V_DL2

)

(V_DU2-V_DL2) (Ι _DC2

+

Ι _DD2

)

(V_DU2-V_DL2)

T_{WI, tr}

=

C_D2; T_{WD, p}

=

C_D2

;

t_{WD, L}

=

C_D2

Ι _DD2

Ι _DC2

x

Ι _DD2

Ι _DC2

AED03099_4473

Figure 1

Watchdog Timing Schedule

Data Sheet

3

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Q2

4

7

9

I

µC

V_Bat

Supply

10

µF

C_I

100 nF

Overtemperature

Shutdown

Current and

Saturation

Control,

4.7 kΩ

Bandgap

RO2

WI

3

Reset

µC

Overcurrent

Protection

Reference

Generator

Reset

INH2

Inhibit

Ignition

1

Watchdog

(from µC)

Watchdog

D2 11

100 nF

Q1

5

e.g. Sensor

Supply

10

µF

Current and

Saturation

Control,

4.7 kΩ

e.g. Sensor

Reset

RO1

2

Overcurrent

Protection

Reset

Generator

(to µC)

8

INH1

Inhibit

µC

D1 10

100 nF

6, 12

GND

AEA03298.VSD

Figure 2

Block Diagram (TLE 4473 GV55) with Typical External Components

Data Sheet

4

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Application Information

The output voltage is divided by a voltage divider and compared to an internal reference

voltage. A regulation loop controls the Q2 output in order to achieve a stable output

voltage at the Q2 pin. A second regulation loop controls the Q1 output. The reference

voltage for the Q1 is the regulated Q2 potential (tracking regulator).

Figure 2 includes the components needed for a typical application. Maintaining the

stability of the regulation loops requires a capacitor of 10 µF both outputs. A maximum

ESR of 5 Ω is permissible for the Q2 output, while the Q1 output requires a capacitor with

a maximum ESR of 3 Ω. For both output blocking capacitors it is recommended to use

tantalum types in order to stay in the permissible ESR range over the full operating

temperature range.

At the input of the regulator a capacitor is necessary for compensating line influences. A

minimum of 100 nF (ceramic capacitor) is recommended. In addition for compensation

of long input lines of several meters an electrolytic input capacitor of 47 µF … 220 µF

should be placed at the input.

TLE 4473

(P-DSO-12-6)

WI

RO1

RO2

Q2

1

2

3

4

5

6

12

11

10

9

GND

D2

D1

INH2

INH1

I

Q1

8

N.C.

7

AEP03318.VSD

Pin 6 and heat slug should be connected to GND

Figure 3

Pin Configuration (top view)

Data Sheet

5

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Table 1

Pin Definitions and Functions

Function

Pin No. Symbol

1

WI

Watchdog input; input for watchdog pulses, positive edge

triggered

2

3

4

RO1

RO2

Q2

Reset and watchdog output for Q1; open collector output

Reset output 2; open collector output

Stand-by regulator output voltage; block to GND with a

capacitor C_Q2≥ 10 µF, ESR < 5 Ω at 10 kHz

5

Q1

Main regulator output voltage; output voltage tracked to Q2

voltage; block to GND with a capacitor C_Q1≥ 10 µF, ESR < 3 Ω

at 10 kHz

6

7

N.C.

I

Not connected; connect to GND

Input voltage; block to ground directly at the IC with a ceramic

capacitor

8

INH1

INH2

D1

Inhibit input 1; low level disables Q1, integrated pull-down

resistor

9

Inhibit input 2; low level at INH2 and INH1 disables Q2 and Q1,

integrated pull-down resistor

10

11

12

Reset Delay 1; connect to ground via a capacitor to set reset

delay for Q1

D2

Reset Delay 2; connect to ground via a capacitor to set reset

delay and watchdog timing for Q2

GND

Ground

Data Sheet

6

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Table 2

Absolute Maximum Ratings

-40 °C < T_j< 150 °C

Parameter

Symbol

Limit Values Unit

Remarks

Min.

Max.

Input I

Voltage

V_I

I_I

-42

45

V

–

Current

–

mA

Internally limited

Stand-by Output Q2

Voltage

V_Q2

I_Q2

-0.3

18

V

–

Current

–

mA

Internally limited

Main Output Q1

Voltage

V_Q1

I_Q1

-0.3

18

V

–

Current

–

mA

Internally limited

Inhibit Input INH1

Voltage

V_INH1

I_INH1

-42

-2

45

2

V

–

Current

mA

Inhibit Input INH2

Voltage

V_INH2

I_INH2

-42

-2

45

2

V

–

Current

mA

Reset Output RO1

Voltage

V_RO1

I_RO1

-0.3

18

V

–

Current

–

mA

Internally limited

Reset Output RO2

Voltage

V_RO2

I_RO2

-0.3

18

V

–

Current

–

mA

Internally limited

Reset Delay D1

Voltage

V_D1

I_D1

-0.3

-5

7

5

V

–

Current

mA

Reset Delay D2

Voltage

V_D

I_D

-0.3

-5

7

5

V

–

Current

mA

Data Sheet

7

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Table 2

Absolute Maximum Ratings (cont’d)

-40 °C < T_j< 150 °C

Parameter

Symbol

Limit Values Unit

Remarks

Min.

Max.

Watchdog Input WI

Voltage

V_RADJ

I_RADJ

-0.3

-5

7

5

V

–

Current

mA

Temperatures

Junction temperature

Storage temperature

T_j

-50

150

°C

–

T_stg

Table 3

Operating Range

Parameter

Symbol

Limit Values Unit

Remarks

Min.

Max.

42

Input voltage

V_I

T_j

5.6

-40

V

–

Junction temperature

150

°C

Thermal Resistances P-DSO-12-6

Junction pin

R_thj-pin

–

4

K/W

–

Junction ambient

R_thj-a

115

PCB Heat Sink

Area 0 mm^{2 1)}

Junction ambient

–

100

60

K/W

PCB Heat Sink

Area 100 mm^{2 1)}

PCB Heat Sink

Area 300 mm²

1)

48

PCB Heat Sink

Area 600 mm^{2 1)}

1) Package mounted on PCB 80 × 80 × 1.5 mm³; 35µ Cu; 5µ Sn; zero airflow.

Note: In the operating range the functions given in the circuit description are fulfilled.

Integrated protection functions are designed to prevent IC destruction under fault

conditions. Protection functions are not designed for continuous repetitive

operation.

Data Sheet

8

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Table 4

Electrical Characteristics

V_I1= 13.5 V; V_INH1= V_INH2= 5 V; -40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

Min. Typ. Max.

Stand-by Regulator

Output Q2

Output voltage

V_Q2

I_Q2

4.90 5.0

5.10

550

600

V

1 mA < I_Q2< 190 mA;

6 V < V_I< 28 V

Output current

limitation

200

300

200

mA V_Q2= 4.5 V

Output drop voltage; V_DRQ2

_DRQ1= V_I1- V_Q1

–

mV I_Q2= 100 mA¹⁾

V

Load regulation

Line regulation

∆V_Q2,Lo

∆V_Q2,Li

–

15

5

50

20

mV 1 mA < I_Q2< 200 mA

mV I_Q2= 1 mA;

6 V < V_I< 28 V

PowerSupplyRipple PSRR

Rejection

–

65

–

dB f_r= 100 Hz;

V_r= 1 Vpp

Current Consumption

Quiescent current;

stand-by

I_q= I_I- I_Q2

I_q

–

170

–

220

245

280

5

µA I_Q2= 500 µA; T_j= 25 °C;

V

_INH1< V_{INH1 OFF}(Q1 off)

µA I_Q2= 500 µA; T_j= 85 °C;

_INH1< V_{INH1 OFF}(Q1 off)

µA I_Q2= 500 µA;

V

–

V_INH1< V_{INH1 OFF}(Q1 off)

4.5

0.1

mA I_Q2= 100 mA;

V_INH1< V_{INH1 OFF}(Q1 off)

Quiescent current;

inhibited

I_q

1

µA

V

_INH1= V_INH2= 0 V;

T_j< 85 °C

V_INH1= V_INH2= 0 V

15

Data Sheet

9

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Table 4

Electrical Characteristics (cont’d)

V_I1= 13.5 V; V_INH1= V_INH2= 5 V; -40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

Min. Typ. Max.

Inhibit Input INH2

Turn-on Voltage

Turn-off Voltage

H-input current

V_{INH2 ON}

–

2.3

–

V

V_Q2on

V_Q2off

V_{INH2 OFF}0.65

I_{INH2 ON}-1

–

V

3.2

6

µA

V

_INH2= 5.0 V (see

Page 13)

µA 0 V < V_INH2< 0.8 V

L-input current

I_{INH2 OFF}-1

0.1

1

Watchdog and Reset Timing D2

Charge current

I_DC2

I_DD2

V_DU2

6.5

2.0

1.5

9.0

3.5

12.5 µA V_D2= 1 V

5.0 µA V_D2= 1 V

Discharge current

Upper timing

threshold

1.85 2.4

V

–

Lower timing

threshold

V_DL2

0.3

0.4

0.5

V

–

Saturation Voltage

V_D2,SAT

T_WI,tr

–

100

51

mV V_Q2< V_RT2

Watchdog trigger

time

34

42

ms C_D2= 100 nF

Reset delay time

T_RD2

15

20

25

ms C_D2= 100 nF

Reset reaction time T_rr

–

5.0

µs

C_D2= 100 nF

Reset Output RO2

Reset switching

threshold

V_RT2

4.5

4.65 4.8

V

–

V

_RT2/V_Q290

93

96

%

Reset threshold

headroom

V_R2HEAD200

350

500

mV V_Q2- V_RT2

Reset output current I_RO2

–

1.6

mA V_Q2= 5 V, V_D2= 0 V;

V_RO2= 0.3 V

Reset output low

voltage

V_RO2L

–

0.15 0.3

V

_Q2≥ 1 V

Reset high voltage V_RO2H

4.5

–

R_RO2,ext= 4.7 kΩ

Data Sheet

10

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Table 4

Electrical Characteristics (cont’d)

V_I1= 13.5 V; V_INH1= V_INH2= 5 V; -40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

Min. Typ. Max.

Main (Tracked) Regulator

Output Q1

Output voltage

V_Q1

4.875 5.0

5.125 V

1 mA < I_Q1< 200 mA;

6 V < V_I< 28 V

Output voltage

tracking accuracy

∆V_Q=

V_Q2- V_Q1

-25

350

–

5

25

–

mV 1 mA < I_Q1< 200 mA;

6 V < V_I< 28 V

Output voltage

tracking accuracy

∆V_Q=

V_Q2- V_Q1

5

mV 1 mA < I_Q1< 300 mA;

8 V < V_I< 28 V

Output current

limitation

I_Q1

500

300

mA V_Q1= 4.5 V

Output drop voltage V_DRQ1

_DRQ1= V_I- V_Q1

600

mV I_Q1= 200 mA¹⁾

V

Load regulation

Line regulation

∆V_Q1,Lo

∆V_Q1,Li

–

5

50

25

mV 5 mA < I_Q1< 300 mA

mV I_Q1= 5 mA;

6 V < V_I< 28 V

PowerSupplyRipple PSRR

Rejection

–

65

–

dB f_r= 100 Hz;

V_r= 1 Vpp

Current Consumption

Quiescent current;

I_q= I_I- I_Q1- I_Q2

I_q

–

10

20

mA I_Q1= 300 mA;

I_Q2= 500 µA;

V_Q1and V_Q2on

Quiescent current;

I_q= I_I- I_Q1- I_Q2

I_q

250

500

µA I_Q2= I_Q1= 500 µA;

V_Q1and V_Q2on

Inhibit Input INH1

Turn-on Voltage

Turn-off Voltage

H-input current

V_{INH1 ON}

–

2.3

–

V

V_Q1on

V_Q1off

V_{INH1 OFF}0.7

I_{INH1 ON}-1

–

3.5

5

µA 3.0 V < V_INH1< 5 V;

(see Page 14)

L-input current

I_{INH1 OFF}-1

0.1

11

1

µA 0 V < V_INH1< 0.8 V

Data Sheet

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Table 4

Electrical Characteristics (cont’d)

V_I1= 13.5 V; V_INH1= V_INH2= 5 V; -40 °C < T_j< 150 °C; unless otherwise specified

Parameter

Symbol

Limit Values

Unit Test Condition

Min. Typ. Max.

Reset Timing D1

Charge current

I_DC1

4.0

1.6

8.0

1.8

12.0 µA V_D1= 1 V

Upper timing

threshold

V_DU1

2.2

V

–

Lower timing

threshold

V_DL2

0.3

0.4

0.6

V

–

Saturation Voltage

Reset delay time

V_D1,SAT

T_RD1

–

100

30

mV V_Q1< V_RT1

14

–

20

–

ms C_D1= 100 nF

Reset reaction time T_rr

10

µs

C_D1= 100 nF

Reset Output RO1

Reset switching

threshold

V_RT1

4.5

4.65 4.8

V

–

V

_RT1/V_Q190

93

96

%

Reset threshold

headroom

V_R1HEAD200

350

500

mV V_Q1- V_RT1

Reset output current I_RO1

–

1.6

mA V_Q1= 5.0 V; V_Q2= 5.0 V;

V_D1= 0 V; V_RO1= 0.3 V

Reset output low

voltage

V_RO1L

V_RO1H

–

0.15 0.3

V

_Q1≥ 1 V

Reset output high

voltage

4.5

–

V

R_RO1,ext= 4.7 kΩ

1) Drop voltage = V_I- V_Q(measured when the output voltage has dropped 100 mV from the nominal value

obtained at 13.5 V input)

Data Sheet

12

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Typical Performance Characteristics

Output Voltage V_Q2versus

Input Voltage V_I

Output Voltage V_Q2versus

Junction Temperature T_J

AED03353.VSD

AED03352.VSD

8

5.15

V

V_Q2

R

V

_Load= 50 Ω

7

6

5

4

3

2

1

0

_INH2= 5 V

5.10

5.05

5.00

4.95

4.90

0

1

2

3

4

5

6

V 8

V_I

-40

0

40

80

°C 160

T_j

Reset Thresholds V_RT1, V_RT2versus

Junction Temperature T_J

INH2 Input Current versus

Inhibit Voltage

AED03354.VSD

AED03351.VSD

4.80

8

µA

V

I_INH2

7

6

5

4

3

2

1

0

4.75

4.70

4.65

4.60

4.55

-40

0

40

80

°C 160

0

1

2

3

4

5

6

V 8

T_j

V_INH2

Data Sheet

13

Rev. 1.2, 2004-01-01

TLE 4473 GV55

INH1 Input Current versus

Inhibit Voltage

AED03350.VSD

8

µA

I_INH1

7

6

5

4

3

2

1

0

1

2

3

4

5

6

V 8

V_INH1

Data Sheet

14

Rev. 1.2, 2004-01-01

TLE 4473 GV55

Package Outlines

1)

±0.1

6.4

7.5

A

B

(Mold)

1

5

±0.3

10.3

0.1

0.25 B

5 x

=

1

12x

0.25

0.4 ^+0.13

M

C A B

±0.1

5.1

(Metal)

7

12

1

7

12

Index Marking

6

±0.1

6

1

7.8

Heatslug

(Heatslug)

1) Does not include plastic or metal protrusion of 0.15 max. per side

GPS09349

Figure 4

P-DSO-12-6 (Plastic Dual Small Outline)

You can find all of our packages, sorts of packing and others in our

Infineon Internet Page “Products”: http://www.infineon.com/products.

Dimensions in mm

SMD = Surface Mounted Device

Data Sheet

15

Rev. 1.2, 2004-01-01

Edition 2004-01-01

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.


型号：	TLE4473GV55
厂家：	Infineon
描述：	Fixed Positive LDO Regulator, 2 Output, 5V1, 5V2, PDSO12, PLASTIC, SO-12 光电二极管输出元件调节器
文件：	总16页 (文件大小：255K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLE4473GV55 [INFINEON]

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