TLE6286GNT [INFINEON]
Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, BCDMOS, PDSO16, PLASTIC, SOP-16;
| 型号： | TLE6286GNT |
| 厂家： | 
Infineon |
| 描述： | Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, BCDMOS, PDSO16, PLASTIC, SOP-16 |
| 文件： | 总19页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LIN-Transceiver LDO
TLE 6286
Target Data Sheet
1
Overview
1.1
Features
• Single-wire transceiver, suitable for LIN protocol
• Transmission rate up to 20 kBaud
• Compatible to LIN specification
• Compatible to ISO 9141 functions
• Very low current consumption in sleep mode
• Control output for voltage regulator
• Short circuit proof to ground and battery
• Overtemperature protection
P-DSO-16-4
• Output voltage tolerance ≤ 2 %
• 200 mA output current capability
• Low-drop voltage
• Very low standby current consumption
• Overtemperature protection
• Reverse polarity protection
• Short-circuit proof
• Watchdog
• Wide temperature range
• Suitable for use in automotive electronics
Type
Ordering Code
Package
P-DSO-16-4
TLE 6286 G
on request
1.2
Description
The TLE 6286 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit
in a P-DSO-16-4 package. It works as an interface between the protocol controller and
the physical bus. The TLE 6286 is especially suitable to drive the bus line in LIN systems
in automotive and industrial applications. Further it can be used in standard ISO9141
systems.
In order to reduce the current consumption the TLE 6286 offers a sleep operation mode.
In this mode a voltage regulator can be controlled in order to minimize the current
consumption of the whole application. The on-chip voltage regulator is designed for this
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Target Data TLE 6286
application but it is also possible to use an external voltage regulator. A wake-up caused
by a message on the bus enables the voltage regulator and sets the RxD output low until
the device is switched to normal operation mode.
®
The IC is based on the Smart Power Technology SPT which allows bipolar and CMOS
control circuitry in accordance with DMOS power devices existing on the same
monolithic circuit.
The TLE 6286 is designed to withstand the severe conditions of automotive applications.
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Target Data TLE 6286
1.3
Pin Configuration (top view)
GND
RD
1
2
3
4
5
16
15
14
13
GND
RO
WD
INHI
VBAT
BUS
TxD
VCC
INHO
RxD
ENLIN
GND
12
6
7
11
10
VS
8
9
GND
P-DSO-16-4
Leadframe
1
16
15
14
13
12
11
10
9
GND
GND
2
RO
RD
Chip:
Voltage
Regulator
3
4
5
6
7
WD
INHI
VBAT
BUS
VCC
INHO
RxD
Chip:
Transceiver
TxD
VS
ENLIN
GND
8
GND
P-DSO-16-4
Figure 1 Pinout
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Target Data TLE 6286
1.4
Pin Definitions and Functions:
Pin No. Symbol Function
1,8,9,16 GND
Ground; place to cooling tabs to improve thermal behavior
Reset delay; connected to ground with capacitor
2
3
RD
WD
Window Watchdog; rising-edge triggered, for monitoring a
microcontroller
4
5
6
VCC
5V Output; connected to GND with 22µF capacitor, ESC<3Ω
Inhibit LIN Output; to control a voltage regulator
INHO
RxD
Receive Data Output; internal 30kΩ pull up to Vs, LOW in
dominat state
7
ENLIN
Enable LIN Input; integrated 30kΩ pull down, transceiver in
normal operation mode when HIGH
10
11
VS
5V Supply Input; VCC input to supply the LIN transceiver
TxD
Transmit Data Input; internal 30kΩ pull up to Vs, LOW in
dominant state
12
13
BUS
VBAT
LIN BUS Output/Input; internal 30kΩ pull up to Vs, LOW in
dominant state
Battery Supply Input; a reverse current protection diode is
required, block GND with 100nF ceramic capacitor and 22µF
capacitor
14
15
INHI
RO
Inhibit Voltage Regulator Input; TTL compatible, low active
input
Reset Output; open collector output connected to the output via
a resistor of 30kΩ
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1.5
Functional Block Diagram
13
5
VBAT
INHO
10
VS
Mode
Control
7
ENLIN
Output
Stage
30 k
Ω
Driver
30 k
Ω
12
Bus
Temp.-
Protection
11
TxD
Receiver
6
RxD
TLE 6259 G
5
GND
WD
3
Saturation
Control
and
Temperature
Sensor
Watchdog
Protection
Circuit
13
4
VBAT
VCC
Control
Amplifier
Buffer
2
RD
RO
Reset
Generator
Bandgap
Reference
15
Adjustment
TLE 4263 G
14
1
INHI
GND
Figure 2 Block Diagram
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Target Data TLE 6286
2
Circuit Description
The TLE 6286 is a single-wire transceiver combined with a LDO. It is a chip by chip
integrated circuit in a P-DSO-16-4 package. It works as an interface between the
protocol controller and the physical bus. The TLE 6286 is especially suitable to drive the
bus line in LIN systems in automotive and industrial applications. Further it can be used
in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed
for sleep mode applications but it is also possible to use an external voltage regulator.
Start Up
Power Up
Normal Mode
ENLIN INHO VCC
high high
ON
ENLIN high
low
ENLIN
Stand-By
INHO
ENLIN
RxD VCC
low1)
ON
low high
3)
ENLIN
(VCC
high
ON)
high
Wake Up
t > tWAKE
Sleep Mode
ENLIN INHO VCC
low floating OFF2)
1)
after wake-up via bus
ON when INHO not connected to INHI
after start up
2)
3)
Figure 3 Operation Mode State Diagram
2.1 Operation Modes
In order to reduce the current consumption the TLE 6286 offers a sleep operation mode.
This mode is selected by switching the enable input EN low (see figure 3, state
diagram). In the sleep mode a voltage regulator can be controlled via the INH output in
order to minimize the current consumption of the whole application. A wake-up caused
by a message on the communication bus automatically enables the voltage regulator by
switching the INH output high. In parallel the wake-up is indicated by setting the RxD
output low. When entering the normal mode this wake-up flag is reset and the RxD
output is released to transmit the bus data.
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In case the voltage regulator control input is not connected to INH output or the
microcontroller is active respectively, the TLE6286 can be set in normal operation mode
without a wake-up via the communication bus.
2.2
LIN Transceiver
The LIN Transceiver has already a pull up resistor of 30kΩ as termination implemented.
There is also a diode in this path, to protect the circuit from feedback of voltages from
the bus line to the power supply. To configure the TLE 6286 as a master node, an
additional external termination resistor of 1kΩ is required. To avoid reverse currents from
the bus line into the battery supply line in case of an unpowered node, it is also
recommended to place a diode in series to the external pull up. For small systems (low
bus capacitance) the EMC performance of the system is supported by an additional
capacitor of at least 1nF in the master node (see figure 6, application circuit).
An capacitor of 10µF at the supply voltage input VS buffers the input voltage. In
combination with the required reverse polarity diode this prevents the device from
detecting power down conditions in case of negative transients on the supply line.
2.3
Voltage Regulator
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element. If the externally scaled down
output voltage at the reset threshold input drops below 1.35 V, the external reset delay
capacitor is discharged by the reset generator. When the voltage of the capacitor
reaches the lower threshold VDRL, a reset signal occurs at the reset output and is held
until the upper threshold VDU is exceeded. If the reset threshold input is connected to
GND, reset is triggered at an output voltage of typ. 4.65 V. A connected microcontroller
will be monitored through the watchdog logic. In case of missing pulses at pin W, the
reset output is set to low. The pulse sequence time can be set in a wide range with the
reset delay capacitor. The IC can be switched at the TTL-compatible, low-active inhibit
input. The IC also incorporates a number of internal circuits for protection against
overload, overtemperature, reverse polarity
2.4
Input Capacitor
The input capacitor CI is necessary for compensation of line influences. Using a resistor
of approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and
input capacitance can be damped. The output capacitor is necessary for the stability of
the regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 3 Ω
within the operating temperature range. For small tolerances of the reset delay the
spread of the capacitance of the delay capacitor and its temperature coefficient should
be noted.
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2.5
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
CD which can be calculated as follows:
CD = (trd × ID,ch)/∆V
Definitions:CD = delay capacitor
trd = reset delay time
I
D,ch = charge current, typical 60 µA
∆V = VDU, typical 1.70 V
VDU = upper delay switching threshold at CD for reset delay time
2.6
Watchdog Timing
The frequency of the watchdog pulses has to be higher than the minimum pulse
sequence which is set by the external reset delay capacitor CD. Calculation can be done
according to the formulas given in Figure 5.
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3
Electrical Characteristics
Absolute Maximum Ratings
3.1
Parameter
Symbol Limit Values Unit
Remarks
min.
max.
Voltages
Supply voltage
VCC
VS
-0.3
-0.3
-20
6
V
V
V
V
V
Battery supply voltage
Bus input voltage
Bus input voltage
40
32
40
Vbus
Vbus
VI
-20
t < 1 s
Logic voltages at
EN, TxD, RxD
-0.3
VCC
+ 0.3
0 V < VCC < 5.5 V
Input voltages at INH
VINH
-0.3
VS
V
+ 0.3
Output current at INH
Reset output voltage
Reset delay voltage
Output voltage Vcc
INHIBIT voltage
IINH
VR
1
mA
V
– 0.3
– 0.3
– 0.3
– 42
– 0.3
-4
42
42
7
–
VD
V
VQ
V
–
–
–
VINH
VW
45
6
V
Watchdog voltage
V
Electrostatic discharge
voltage at Vs, Bus
VESD
4
kV
human body model
(100 pF via 1.5 kΩ)
Electrostatic discharge
voltage
VESD
-2
2
kV
human body model
(100 pF via 1.5 kΩ)
Temperatures
Junction temperature
Tj
-40
150
°C
–
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause
irreversible damage to the integrated circuit.
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3.2
Operating Range
Parameter
Symbol Limit Values Unit
Remarks
min.
4.5
6
max.
5.5
Supply voltage
VCC
VS
Tj
V
Battery Supply Voltage
Junction temperature
20
V
–
– 40
150
°C
Thermal Shutdown (junction temperature)
Thermal shutdown temp.
Thermal shutdown hyst.
TjSD
150
170
10
190
°C
∆T
–
–
K
Thermal Resistances
–
Junction ambient
Rthj-a
–
115
K/W
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Target Data TLE 6286
3.3
Electrical Characteristics
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Current Consumption
recessive state;
Current consumption
ICC
IS
0.5
0.5
0.7
0.7
20
1.5
1.0
2.0
1.5
30
mA
V
TxD = VCC
recessive state;
Current consumption
Current consumption
Current consumption
Current consumption
Current consumption
mA
mA
mA
µA
V
TxD = VCC
dominant state;
ICC
IS
V
TxD = 0 V
dominant state;
V
TxD = 0 V
sleep mode;
Tj = 25 °C
IS
sleep mode
IS
20
40
µA
Receiver Output R×D
VRD = 0.8 x VCC
,
,
HIGH level output current
LOW level output current
IRD,H
IRD,L
-0.7 -0.4 mA
VRD = 0.2 x VCC
0.4
0.7
mA
Bus receiver
-8 V < Vbus < Vbus,dom
Vbus,rec < Vbus < 20 V
Receiver threshold voltage, Vbus,rd 0.44 0.48
V
V
recessive to dominant edge
x VS x VS
0.52 0.56
x VS x VS
Receiver threshold voltage, Vbus,dr
dominant to recessive edge
Vbus,hys
=
Receiver hysteresis
Vbus,hys 0.02 0.04 0.06 mV
x VS x VS x VS
V
bus,rec - Vbus,dom
wake-up threshold voltage
Vwake
0.40 0.55 0.70
V
x VS x VS x VS
Transmission Input T×D
recessive state
HIGH level input voltage
threshold
VTD,H
2.9
0.7 x V
VCC
TxD input hysteresis
VTD,hys 300 600
mV
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Target Data TLE 6286
3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
dominant state
LOW level input voltage
threshold
VTD,L
ITD
0.3 x 2.1
VCC
V
VTxD < 0.3 Vcc
TxD pull up current
-150 -110 -80
µA
Bus transmitter
VTxD = VCC
Bus recessive output voltage Vbus,rec 0.9 x
VS
V
VS
VTxD = 0 V;
Bus dominant output voltage Vbus,dom
0
1.5
V
Vbus,short = 13.5 V
Bus short circuit current
Leakage current
Ibus,sc
Ibus,lk
40
85
125
mA
VCC = 0 V, VS = 0 V,
-350 -100
µA
Vbus = -8 V, Tj < 85 °C
VCC = 0 V, VS = 0 V,
5
20
47
µA
kΩ
Vbus = 20 V, Tj < 85 °C
Bus pull up resistance
Rbus
20
30
Enable input (pin ENLIN)
normal mode
HIGH level input voltage
threshold
VEN,on
2.8
0.7 x V
VCC
low power mode
LOW level input voltage
threshold
VEN,off 0.3 x 2.2
V
VCC
EN input hysteresis
VEN,hys 300 600
mV
EN pull down resistance
REN
15
30
60
kΩ
Inhibit output (pin INHO)
IINH = - 0.15 mA
HIGH level drop voltage
∆VINH = VS − VINH
Leakage current
∆VINH
0.5
1.0
5.0
V
sleep mode;
VINHO = 0 V
IINH,lk
- 5.0
µA
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3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Vcc Output (pin Vcc)
5 mA ≤ IQ ≤ 150 mA;
Output voltage
VQ
VQ
4.90 5.00 5.10
4.90 5.00 5.10
V
V
6 V ≤ VI ≤ 28 V
6 V ≤ VI ≤ 32 V;
IQ = 100 mA;
Tj = 100 °C
Output voltage
Output current
1)
IQ
Iq
200
250
0
–
mA
VINH = 0
Current consumption;
Iq = II – IQ
–
50
µA
IQ = 0 mA
IQ = 150 mA
IQ = 150 mA; VI = 4.5 V
Iq
Iq
Iq
–
–
–
900
10
15
1300 µA
18
23
mA
mA
IQ = 150 mA1)
Drop voltage
Vdr
–
–
–
0.35 0.50
V
IQ = 5 mA to 150 mA
Load regulation
Line regulation
∆VQ,lo
∆VQ.li
–
25
25
mV
mV
VI = 6 V to 28 V;
IQ = 150 mA
3
fr = 100 Hz; Vr =
0.5 VPP
Power Supply Ripple
Rejection
PSRR
–
54
–
dB
Reset Genarator (pin RD)
Switching threshold
Reset adjust threshold
Reset low voltage
VQ,rt
4.5
4.65 4.8
V
VQ > 3.5 V
VRADJ,th 1.26 1.35 1.44
V
IRO = 1 mA
VRO,l
VD,sat
VDU
–
–
0.10 0.40
50 100
V
VQ < VR,th
Saturation voltage
mV
V
–
Upper timing threshold
1.45 1.70 2.05
0.20 0.35 0.55
–
Lower reset timing threshold VDRL
V
–
Charge current
ID,ch
trd
40
60
85
4.1
4
µA
ms
µs
CD = 100 nF
CD = 100 nF
Reset delay time
Reset reaction time
1.3
0.5
2.8
1.2
trr
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Target Data TLE 6286
3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Watchdog (pin WD)
VD = 1.0 V
Discharge current
ID,wd
VDU
4.40 6.25 9.10 µA
–
Upper timing threshold
Lower timing threshold
Watchdog trigger time
1.45 1.70 2.05
0.20 0.35 0.55
V
–
VDWL
TWI,tr
V
CD = 100 nF
16
22.5 27
ms
Inhibit Input (INHI)
IC turned on
IC turned off
VINH = 5 V
Switching voltage
Turn-OFF voltage
Input current
VINH,ON
VINH,OFF
IINH
3.6
–
–
–
V
–
0.8
25
V
5
10
µA
Note: The reset output is low within
the range VQ = 1 V to VQ,rt
1)Drop voltage = Vi – VQ (measured
when the output voltage has
dropped 100 mV
from the nominal value obtained at
6 V input)
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Target Data TLE 6286
3.3
Electrical Characteristics (cont’d)
4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect
to ground; positive current flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values
Unit Remarks
min. typ. max.
Dynamic Transceiver Characteristics
80% > Vbus > 20%
falling edge slew rate
Sbus(L)
-3
-2.0 -1
V/µs
C
bus= 3.3 nF;
ambient < 85 °C;
CC = 5 V; VS = 13.5 V
T
V
20% < Vbus < 80%
rising edge slew rate
Sbus(H)
td(L),TR
1
2
1.5
5
3
V/µs
µs
C
bus= 3.3 nF;
V
CC = 5 V; VS = 13.5 V
Cbus = 3.3nF;
CC = 5 V; VS = 13.5 V
RxD = 20 pF
Propagation delay
TxD-to-RxD LOW (recessive
to dominant)
10
V
C
Cbus = 3.3 nF;
CC = 5 V; VS = 13.5 V
RxD = 20 nF
Propagation delay
TxD-to-RxD HIGH (dominant
to recessive)
td(H),TR
2
5
10
µs
V
C
VCC = 5 V
VCC = 5 V
VCC = 5V;
Propagation delay
TxD LOW to bus
td(L),T
td(H),T
td(L),R
td(H),R
tsym,R
1
1
1
1
4
4
4
4
µs
µs
µs
µs
Propagation delay
TxD HIGH to bus
Propagation delay
bus dominant to RxD LOW
CRxD = 20pF
VCC = 5 V;
RxD = 20 pF
Propagation delay
bus recessive to RxD HIGH
C
tsym,R = td(L),R - td(H),R
tsym,T = td(L),T - td(H),T
Receiver delay symmetry
-2
-2
30
2
µs
µs
µs
Transmitter delay symmetry tsym,T
Wake-up delay time
2
twake
100
200
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Target Data TLE 6286
4
Diagrams
V
I
<
trr
t
VQ
VQ, rt
ID, ch
d
d
V
t
t
t
t
=
VD
CD
VDU
VDRL
trd
trr
VRO
Power-ON
Reset
Over-
temperature
Voltage Drop Under-
at Input voltage
Secondary
Spike
Load
Bounce
AET03066
Figure 4
Time Response, Watchdog with High-Frequency Clock
VW
t
t
t
t
t
V
Ι
VQ
VD
TWD, p
TWI, tr
VDU
VDWL
VRO
tWD, L
(VDU -VDWL
)
(VDU -VDWL ) (Ι D, wc
+
Ι D, wd
)
(VDU -VDWL )
TWI, tr
=
CD
;
T
=
C
;
t
=
C
Ι D, wd
03099
Figure 5
Timing of the Watchdog FunctionReset
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Target Data TLE 6286
5
Application
Vbat LIN bus
master node
WD
RO
3
15
7
VBAT
13
ENLIN
22 µF
6
11
10
RxD
TxD
VS
µP
100 nF
1 k
12 Bus
5
INHO
GND
TLE 6286 G
100 nF
100 nF
5V
4
VCC
14
INHI
RD
22 µF
2
GND
1,8,9,16
CD
100 nF
ECU 1
slave node
WD
RO
3
15
7
VBAT
13
ENLIN
22 µF
6
11
10
RxD
TxD
VS
µP
100 nF
12 Bus
5
INHO
GND
TLE 6286 G
100 nF
100 nF
5V
4
VCC
14
INHI
RD
22 µF
2
GND
1,8,9,16
CD
100 nF
ECU X
Figure 6
Application Circuit
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Target Data TLE 6286
6
Package Outlines
P-DSO-16-4
(Plastic Dual Small Outline Package)
Pictures of the housing will be added in near future!
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Dimensions in mm
Version 1.02
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Target Data TLE 6286
Edition 1999-10-12
Published by Infineon Technologies AG
St.-Martin-Strasse 53
D-81541 München
© Infineon Technologies AG1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and
charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
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For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide (see address list).
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Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Tech-
nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to
support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
Version 1.02
19
2001-10-15
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