TLE7186FXUMA1 [INFINEON]
Brushless DC Motor Controller, PQCC48, VQFN-48;
| 型号： | TLE7186FXUMA1 |
| 厂家： | 
Infineon |
| 描述： | Brushless DC Motor Controller, PQCC48, VQFN-48 |
| 文件： | 总39页 (文件大小：1382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE7186F
System IC for B6 motor drives
Data Sheet
Rev. 1.1, 2011-04-08
Automotive Power
TLE7186F
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1
2
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment TLE7186F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Default State of Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
5
MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Inputs and Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bootstrap Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Currents at SH pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
5.2
5.3
5.4
5.5
6
Shunt Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
5 V Low Drop Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Interface, VDH Switch and INH Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PWM Interface (IFMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VDHS Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Digital Output INHD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1
8.2
8.3
8.4
9
9.1
9.2
Description of Modes, Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Description of modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Protection and Diagnosis Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Over Temperature Shut Down (OTSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Over Temperature Prewarning (OTPW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Analog Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VS Under Voltage Lockout (VS_UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VDD Under Voltage Diagnosis (VDD_UVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VDD Under Voltage Shut Down (VDD_UVSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VREG Under Voltage Diagnosis (VREG_UVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VREG Under Voltage Shut Down (VREG_UVSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IOV and VDH Over Voltage Shut Down (IOV_OVSD, VDH_OVSD) . . . . . . . . . . . . . . . . . . . . . . . . 29
Dead Time and Shoot Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Short Circuit Protection (SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SCDL Pin Open Detection (SCDL_open) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Over Current Shut Down (OCSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VDD Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Passive Gxx Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.2.11
9.2.12
9.2.13
9.2.14
9.2.15
9.3
Data Sheet
2
Rev. 1.1, 2011-04-08
TLE7186F
Table of Contents
9.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Phase voltage feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11
12
13
Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data Sheet
3
Rev. 1.1, 2011-04-08
System IC for B6 motor drives
TLE7186F
1
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Drives 6 N-Channel Power MOSFETs
Integrated 5V Vreg-Controller to power µC
Integrated switch for VDH voltage
Separate control input for each MOSFET
Adjustable dead time
Shoot through protection
Analog adjustable Short Circuit Protection levels
Low quiescent current mode
1 bit diagnosis ERR
Over Temperature shut down and analog temperature output
Over Temperature pre-warning
Under Voltage shut down
Adjustable Over Voltage shut down
Current sense OpAmp
PG-VQFN-48
Over current shut down based on Current sense OpAmp, fixed shut down level
0 …94% duty cycle at 25 kHz PWM frequency
Digital phase voltage feedback
Green Product (RoHS compliant)
AEC Qualified
Description
The TLE7186F is a system IC for Brushless Motor Control. It incorporates a voltage supply for a µC, a bridge driver
for a B6 configuration, an application typical PWM interface and some other smaller features. Target is to reduce
the number of discrete components in typical BLDC automotive applications and give enough flexibility for custom
specific adaptations.
It works with 3-phase motors and brush DC motors. Its exposed pad package allows the usage even at high
ambient temperatures.
Type
Package
Marking
TLE7186F
PG-VQFN-48
TLE7186F
Data Sheet
4
Rev. 1.1, 2011-04-08
TLE7186F
Block Diagram
2
Block Diagram
___ ____
VS
VDD
GND INH INHD VREG
VDHS
VDH
switch
5V voltage
regulator
VREG
U_fb
V_fb
W_fb
BH1
GH1
SH1
SH1
Digital phase
voltage feedback
Floating HS driver
Short circuit detection
SH2
SH3
IOV
Diagnostic logic
____
Under voltage
Over voltage
Overtemperature
Short circuit
Reset
ERR
____
RGS
Floating LS driver
Short circuit detection
GL1
SCDL
TEMP
Over current
L
E
V
E
L
BH2
GH2
SH2
Floating HS driver
Short circuit detection
IFuC
Interface
IFMA
S
H
I
Floating LS driver
Short circuit detection
DT
F
T
E
R
GL2
IL1
___
IH1
Input control
Shoot through
protection
BH3
GH3
SH3
IL2
Floating HS driver
Short circuit detection
___
dead time
IH2
IL3
___
IH3
Floating LS driver
Short circuit detection
GL3
SL
AGND
ISP
ISN
OCTH
GND
ISO
Figure 1
Block Diagram
Data Sheet
5
Rev. 1.1, 2011-04-08
TLE7186F
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment TLE7186F
____
RGS
____
ERR
GND
32
N.C
30
GND
26
IOV
28
GND
35
TEMP
33
VDD
31
V_fb
29
W_fb
27
VDH
25
36
34
___
IH1
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
BH1
IL1
GH1
SH1
___
IH2
IL2
GL1
BH2
GH2
SH2
GL2
BH3
GH3
___
IH3
TLE 7186 F
Topview
IL3
AGND
ISN
ISP
ISO
____
INHD
SH3
GL3
IFuC
1
2
3
4
5
6
7
8
9
10
11
12
GND
IFMA
VS
VREG
SCDL
DT
___
INH
NC
VDHS
U_fb
SL
GND
Figure 2
Pin Configuration
Data Sheet
6
Rev. 1.1, 2011-04-08
TLE7186F
Pin Configuration
3.2
Pin Definitions and Functions
Pin
5
Symbol
Function
VS
Supply Pin
7
VREG
VDD
INH
Output of supply for driver output stages - connect to capacitor
Output of 5V supply for µC - connect to capacitor
Input pin wake up the complete system IC
Digital output 5V for INH state (high when INH is high)
Switched output of VDH voltage; switch open in sleep mode
Output pin for analog temperature signal
31
2
47
4
INHD
VDHS
TEMP
RGS
33
36
Reset and Go-to-Sleep input pin for reset of error registers, set HIGH to avoid to go-
to-sleep
38
37
40
39
42
41
11
9
IL1
Input for low side switch 1 (active high)
IH1
IL2
Input for high side switch 1 (active low)
Input for low side switch 2 (active high)
IH2
IL3
Input for high side switch 2 (active low)
Input for low side switch 3(active high)
IH3
DT
Input for high side switch 3(active low)
Input pin for adjustable dead time function, connect to GND via resistor
SCDL
Analog input pin for adjustable Short Circuit Detection function, connect to voltage
divider
28
34
25
24
23
22
21
20
19
18
17
16
15
14
13
10
44
45
46
43
3
IOV
Input pin for Over Voltage detection.
ERR
VDH
BH1
GH1
SH1
GL1
BH2
GH2
SH2
GL2
BH3
GH3
SH3
GL3
SL
Open drain error output
Voltage input common drain high side for short circuit detection
Pin for + terminal of the bootstrap capacitor of phase 1
Output pin for gate of high side MOSFET 1
Pin for source connection of high side MOSFET 1
Output pin for gate of low side MOSFET 1
Pin for + terminal of the bootstrap capacitor of phase 2
Output pin for gate of high side MOSFET 2
Pin for source connection of high side MOSFET 2
Output pin for gate of low side MOSFET 2
Pin for + terminal of the bootstrap capacitor of phase 3
Output pin for gate of high side MOSFET 3
Pin for source connection of high side MOSFET 3
Output pin for gate of low side MOSFET 3
Pin for common source connection of low side MOSFETs
Input for OpAmp - terminal
ISN
ISP
Input for OpAmp + terminal
ISO
Output of OpAmp
AGND
IFMA
IFuC
Analog GND for Opamp and analog temperature output
Interface to master ECU (used for wake up)
Interface to µC
48
Data Sheet
7
Rev. 1.1, 2011-04-08
TLE7186F
Pin Configuration
Pin
6
Symbol
U_fb
V_fb
W_fb
GND
GND
GND
GND
GND
NC
Function
Digital phase voltage feedback output of SH1
29
27
1
Digital phase voltage feedback output of SH2
Digital phase voltage feedback output of SH3
Ground pin
12
26
32
35
8
Ground pin
Ground pin
Ground pin
Ground pin
connect to GND
connect to GND
30
NC
Exposed pad to be connected to GND
Data Sheet
8
Rev. 1.1, 2011-04-08
TLE7186F
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
Voltages
4.1.1
Voltage range at VS, IFMA, INH, IOV
Voltage range at IFMA, INH
Voltage range at VS
VVS1
VIFMA
VVS2
-0.3
-6.0
-3.0
45
45
45
V
V
V
–
4.1.2
R >= 10kΩ
4.1.3
R
VS >= 4.7Ω;
60s, 5x;
RVS >= 2.0Ω;;
4.1.4
Voltage range at VS
VVS3
-3.0
45
V
200ms, 5x;
4.1.5
4.1.6
4.1.7
Voltage range at VREG output
Voltage range at VDH, VDHS
Voltage range at VDH
VVREG
VVDHx
VVDH1
-0.3
-0.3
-3.0
15
55
55
V
V
V
–
With RVDH
>=10Ω; 60s, 5x;
Tj<=150°C
4.1.8
Voltage range at IHx, ILx, RGS, ERR,
IFuC, TEMP, DT, VDD, ISO, INHD,
SCDL, U_fb, V_fb, W_fb
VDP
-0.3
6
V
–
–
4.1.9
Voltage range at ISP, ISN
VOPI
-5.0
-5.0
-0.3
-0.3
-7.0
-2.0
-7.0
-0.3
-7.0
5.0
5.0
55
55
55
45
45
18
18
V
V
V
V
V
V
V
V
V
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.1.16
4.1.17
Voltage difference between ISP and ISN VOPD
Voltage range at BHx
Voltage range at GHx
Voltage range at GHx
Voltage range at SHx
Voltage range at SHx
Voltage range at GLx
Voltage range at GLx
VBH
–
VGH
VGHP
VSH
–
tP < 1µs; f=50kHz
–
VSHP
VGL
tP < 1µs; f=50kHz
–
VGLP
tP < 0.5µs;
f=50kHz
4.1.18
4.1.19
Voltage range at SL
Voltage range at SL
VSL
-0.3
-7.0
5.0
5.0
V
V
–
VSLP
tP < 0.5µs;
f=50kHz
4.1.20
4.1.21
4.1.22
4.1.23
4.1.24
Voltage difference Gxx-Sxx
VGS
-0.3
-0.3
330
1
15
15
–
V
–
–
Voltage difference BHx-SHx
Minimum bootstrap capacitor CBS
Minimum buffer capacitor CVREG
VBS
V
CBS
nF
µF
pF
-10% tolerance
allowed
CVREG
–
Maximum load capacitance for voltage CX_FB
–
25
–
feedback output X_FB
Temperatures
4.1.25
Junction temperature
Tj
-40
150
°C
–
Data Sheet
9
Rev. 1.1, 2011-04-08
TLE7186F
General Product Characteristics
Absolute Maximum Ratings (cont’d)1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Pos.
Parameter
Symbol
Limit Values
Max.
Unit Conditions
Min.
-55
–
4.1.26
4.1.27
Storage temperature
Case temperature2)
Tstg
150
°C
–
–
TCase
145
°C
ESD Susceptibility
4.1.28
4.1.29
ESD Resistivity3)
VESD
VCDM
-2
–
+2
kV
V
–
–
CDM
500
1) Not subject to production test, specified by design.
2) Calculation based on Tjmax, RthJC and the assumption of 1W power dissipation
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
Note:Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note:Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Functional Range
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
4.2.1
4.2.2
Supply voltage at VS
Quiescent current
VVS
IQ
6.0
45
V
below 7V reduced
functionality1) 2)
–
–
50
19
µA
VS<16V;
sleep mode
VVS=VVDH=VIFMA
(IVS + IVDH + IIFMA
)
4.2.3
Supply current at VS (device
enabled)
IVS(0)
mA
Vs=8...18V;
no load3);
f
PWM=25kHz;
4.2.4
4.2.5
Duty cycle HS
Duty cycle LS
DHS
DLS
0
0
94
%
%
f
PWM=25kHz;
continuous
operation
100
4.2.6
Junction temperature
TJ
-40
150
°C
–
1) MOS driver output deactivated and ERROR pin set to low if VREG is lower UVVR
2) MOS driver output stage will operate at Vs=6.7V with 5mA load current at VREG
3) no load at VDD, ERR, ISO, IFµC, VDHS, GXX, TEMP, DT
The limitations in the PWM frequency are given by thermal constraints and limitations in the duty cycle (charging
time of bootstrap capacitor).
All maximum ratings have to be considered
All basic functions will work between TJ=150°C and Over Temperature shut down. In this temperature range, the
parameters might leave the specified range.
Data Sheet
10
Rev. 1.1, 2011-04-08
TLE7186F
General Product Characteristics
Note:Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note:This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
–
Max.
4.3.1
4.3.2
Junction to Case1)
Junction to Ambient1)
RthJC
RthJA
–
–
5
–
K/W
K/W
–
2)
29
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.4
Default State of Inputs
Table 1
Default State of Inputs
Characteristic
State
Low
Remark
Default state of ILx (if ILx left open -pull down)
Default state of IHx (if IHx left open - pull up)
Default state of RGS (if RGS left open - pull down)
Low side MOSFETs off
High side MOSFETs off
High
Low
Error signal is reset and
the TLE7186F goes to
sleep
Default state of INH (if INH left open - pull down)
Default state of SCDL (if SCDL left open - pull up)
Low
no wake up by INH
High
Error signal is set; all
MOSFETs switched off
Default state of IFMA (if IFMA left open - pull up)1)
Default state of IOV (if IOV left open - pull down)
High
Low
no wake up by IFMA
no Over Voltage detection
by IOV
Default state of DT (if DT left open)
1) external capacitance < 25pF
max. dead time
max. dead time
Data Sheet
11
Rev. 1.1, 2011-04-08
TLE7186F
MOSFET Driver
5
MOSFET Driver
5.1
Inputs and Dead Time
There are 6 independent control inputs to control the 6 MOSFETs individually. However, the control inputs for the
High Side MOSFETs IHx are inverted. Hence, the control inputs for High Side IHx and Low Side MOSFETs ILx of
the same half bridge can be tight together to control one half bridge by one control signal. To avoid shoot through
currents within the half bridges, a dead time is provided by the TLE7186F.
For more details about the dead time please see Chapter 9.2.10
5.2
Output Stages
The 3 low side and 3 high side powerful push-pull output stages of the TLE7186F are all floating blocks.
All 6 output stages have the same output power and thanks to the bootstrap principle used, all MOSFETs can be
switched up to high frequencies.
Each output stage has its own short circuit detection block. For more details about short circuit detection see
Chapter 9.2.11.1)
___
INH
VS
VREG
VDH
Voltage regulator
BHx
____
ERR
+
-
VREG
VDH
GHx
Error logic
Reset
Power On Reset
VSCP
____
RGS
blanking
SHx
Level
shifter
SCD
SCD
SCD
Floating HS driver 3x
VREG
lock/
unlock
Short Circuit
Detection Level
___
IH1
short circuit filter
IL1
+
-
___
GLx
SL
Input Logic
ON/OFF
ON/OFF
IH2
Shoot Through
Protection
IL2
___
IH3
VSCP
Level
shifter
Dead Time
IL3
Floating LS driver 3x
DT
GND
SCDL
Figure 3
Block Diagram of Driver Stages including Short Circuit Detection
1) The high side outputs are not designed to be used for low side MOSFETs; the low side outputs are not designed to be used
for high side MOSFETs
Data Sheet
12
Rev. 1.1, 2011-04-08
TLE7186F
MOSFET Driver
5.3
Bootstrap Principle
The TLE7186F provides a bootstrap based supply for its high side output stages. The benefit of this principle is a
fast switching of the high side switches - supporting active freewheeling in high side.
The bootstrap capacitors are charged by switching on the external low side MOSFETs connecting the bootstrap
capacitor to GND. Under this condition the bootstrap capacitor will be charged from the VREG capacitor. If the low
side MOSFET is switched off and the high side MOSFET is switched on, the bootstrap capacitor will float together
with the SHx voltage to the supply voltage of the bridge. Under this condition the supply current of the high side
output stage will discharge the bootstrap capacitor. This current is specified. The size of the capacitor together
with this current will determine how long the high side MOSFET can be kept on without recharging the bootstrap
capacitor.
When all external MOSFETs are switched off, the SHx voltage can be undefined. Under this condition, the
bootstrap capacitors can be discharged, dependent on the SHx voltage.
5.4
Currents at SH pins
The currents at the SH pins can be used for diagnostic purposes to check the health state of the power stage.
The simplified structure related to the SH currents the TLE7186F is described by Figure 4.
BHx
VDH
IBSH
40µA
SHx
SL
RSHGN
80kΩ
Figure 4
Block Diagram of SHx pin configuration
5.5
Electrical Characteristics
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 33 V, Tj = -40 °C to +150 °C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Inputs
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Low level input voltage of ILx; IHx VI_LL
High level input voltage of ILx; IHx VI_HL
–
–
–
–
–
–
1.6
–
V
–
–
–
–
–
2.8
V
Input hysteresis of IHx; ILx2)
IHx pull-up resistors to VDD
ILx pull-down resistors to GND
dVI
RIH
RIL
100
28.5
178.5
–
mV
kΩ
kΩ
76.5
564
Data Sheet
13
Rev. 1.1, 2011-04-08
TLE7186F
MOSFET Driver
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 33 V, Tj = -40 °C to +150 °C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
MOSFET driver output
5.5.6
5.5.7
5.5.8
Output source resistance
RSou
RSink
VGxx1
2
2
–
–
13.5
9
Ω
Ω
V
I
I
load=20mA
load=20mA
Output sink resistance
–
High level output voltage Gxx vs.
Sxx
11
14
13,5V
<=VVS<=45V3),
V
V
IOV<=VOVIOV
VDH<=VOVVDH
,
I
load=37,5mA
VVs=8V,
load=20nF,
dc=95%;
PWM=20kHz
VVs=8V,
load=20nF,
dc=95%;
PWM=20kHz;
5.5.9
High level output voltage GHx vs. VGxx2
6
–
–
–
–
V
V
SHx2)
C
f
5.5.10 High level output voltage GHx vs. VGxx3
6
SHx2)4)
+Vdiode
C
f
passive
freewheeling
5.5.11 High level output voltage GLx vs. VGxx4
6.7
–
–
V
VVS=8V,
GND
C
load=20nF,
dc=95%;
PWM=20kHz;
Load=11nF;
Load=1Ω
f
5.5.12 Rise time
Tj = -40°C
trise
ns
ns
V
C
R
100
150
–
–
230
350
Tj = 150°C
VVS=7V
20-80%
5.5.13 Fall time
Tj = -40°C
tfall
80
150
–
–
210
290
Tj = 150°C
5.5.14 High level output voltage (in
passive clamping)
VGUV
–
–
1.2
sleep mode or
VS_UVLO2) 5)
5.5.15 Pull-down resistor at BHx to GND RBHUV
5.5.16 Pull-down resistor at VREG to GND RVRUV
–
–
–
–
–
–
80
kΩ
kΩ
µA
30
5.5.17 Bias current into BHx
IBH
150
V
BHx-VSHx=5...13V;
no switching
5.5.18 Current between BHx and SHx
IBSH
15
40
60
µA
V
V
BHx-VSHx=5...13V;
SHX = GND
5.5.19 Resistor between SHx and GND
5.5.20 Bias current out of SL
RSHGN
ISL
48
–
80
–
112
2
kΩ
mA
0V<=VSH<=VS+1
V; no switching;
V
CBS>5V
Data Sheet
14
Rev. 1.1, 2011-04-08
TLE7186F
MOSFET Driver
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 33 V, Tj = -40 °C to +150 °C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
50
50
50
50
–
Typ.
Max.
5.5.21 Input propagation time (low on)
5.5.22 Input propagation time (low off)
5.5.23 Input propagation time (high on)
5.5.24 Input propagation time (high off)
tP(ILN)
tP(ILF)
tP(IHN)
tP(IHF)
tP(diff)
–
–
–
–
–
200
200
200
200
100
ns
ns
ns
ns
ns
CLoad=11nF;
R
Load=1Ω
5.5.25 Absolute input propagation time
difference between above
propagation times
VREG
5.5.26 VREG output voltage
VVREG
11
12.5
–
14
V
V
VS >= 13,5V;
I
load=37,5mA
5.5.27 VREG over current limitation
IVREGOCL 100
VVsVREG
500
0.5
mA
V
no activation of
error; VVREG>VVRSD
5.5.28 Voltage drop between Vs and
VREG
–
–
VVS>= 7V;
I
load=37,5mA;
Ron operation
1) RLoad and CLoad in series
2) Not subject to production test; specified by design
3) Values above 33V not subjected to production test; specified by design
4) Vdiode is the bulk diode of the external low side MOSFET
5) see Chapter 9.2.15
Data Sheet
15
Rev. 1.1, 2011-04-08
TLE7186F
Shunt Signal Conditioning
6
Shunt Signal Conditioning
The TLE7186F incorporates a fast and precise operational amplifier for conditioning and amplification of the
current sense shunt signal. The gain of the OpAmp is adjustable by external resistors within a range higher than 5.
The usage of higher gains in the application might be limited by required settling time and band width.
It is recommended to apply a small offset to the OpAmp, to avoid operation close to the lower rail at low currents.
The output of the OpAmp ISO is not short-circuit proof.
In addition to the integrated operational amplifier, the TLE7186F incorporates a comparator to detect over current
situations. The output voltage VISO is compared to a reference voltage VOCTH close to the upper rail of the 5V
OpAmp supply (VDD). If VISO reaches this level an error is set.
VDD
Rfb2
VDD
ASIC
internal
RS1
ISP
ISN
+
-
µC
ISO
Rshunt
RS2
+
-
330pF
Rfb3
ERR
VOCTH
external
Rfb2 Rfb3 = Rfb1
Rfb1
fc < 1 Mhz
Figure 5
Shunt Signal Conditioning Block Diagram and Over Current Limitation
Over current shut down see Chapter 9.2.13.
6.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
VS = 6.0 to 33 V, Tj = -40 °C to +150 °C, gain = 5 to 75, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)1)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
100
2000
5
Typ.
500
7500
–
Max.
6.1.1
6.1.2
6.1.3
Series resistors
RS
1000
Ω
Ω
–
–
Feedback resistor
Rfb
–
–
–
Resistor ratio (gain ratio),
Rfb/RS
RL>3kΩ
max. gain limited by settling time
6.1.4
6.1.5
Input differential voltage (ISP - ISN) VIDR
-800
-800
–
–
800
mV
mV
–
–
Input voltage (Both Inputs - GND) VLL
2000
(ISP - GND) or (ISN -GND)
6.1.6
6.1.7
Input offset voltage of the I-DC link VIO
OpAmp, including temperature drift
–
–
–
+/-2
–
mV
µA
RS=500Ω; VCM=0V;
V
ISO=1.65V;
Input bias current (ISN,ISP to
GND)
IIB
-300
V
CM=0V; VISO=open
Data Sheet
16
Rev. 1.1, 2011-04-08
TLE7186F
Shunt Signal Conditioning
Electrical Characteristics - Current sense signal conditioning (cont’d)
VS = 6.0 to 33 V, Tj = -40 °C to +150 °C, gain = 5 to 75, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)1)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
6.1.8
6.1.9
High level output voltage of ISO
Low level output voltage of ISO
VOH
VVDD
0.2
-
–
VVDD
V
IO=-3mA
VOL
-0.1
5
–
–
0.2
–
V
IO=3mA
6.1.10 Guaranteed output current
capability
IGOC
mA
–
6.1.11 Differential input resistance2)
6.1.12 Common mode input capacitance2) CCM
RI
100
–
–
–
kΩ
pF
dB
–
–
10
–
10kHz
–
6.1.13 Common mode rejection ratio at
CMRR
80
100
DC
CMRR =
20*Log((Vout_diff/Vin_diff) *
(Vin_CM/Vout_CM))
6.1.14 Common mode suppression3)2)
CMS
–
–
dB
VIN=360mV*
with
sin(2*π*freq*t);
Rs=500Ω; Rfb=7500Ω
CMS = 20*Log(Vout_CM/Vin_CM)
Freq =100kHz
Freq = 1MHz
62
43
33
Freq = 10MHz
6.1.15 Slew rate
dV/dt
AOL
–
10
–
–
V/µs
dB
Gain>= 5;
RL=1.0kΩ; CL=500pF
6.1.16 Large signal open loop voltage
gain (DC)
80
100
–
6.1.17 Unity gain bandwidth
6.1.18 Phase margin 2)
GBW
FM
10
–
20
50
–
–
MHz
°
RL=1kΩ; CL=100pF
Gain>= 5;
RL=1kΩ; CL=100pF
6.1.19 Gain margin 2)
6.1.20 Bandwidth
AM
–
12
–
–
–
dB
RL=1kΩ; CL=100pF
BWG
1.6
MHz
Gain=15;
RL=1kΩ; CL=500pF;
Rs=500Ω
6.1.21 Output settle time to 98%
Rfb/RS=15
tset1
µs
RL=1kΩ;
CL=500pF;
0.3<VISO< VDD-0.3V;
Rs=500Ω
–
–
1
4.6
1.8
8
Rfb/RS=75
1) A minimum capacitance of 100pF is needed at the output of the OpAmp (parasitic or real capacitor); RL is the total load
resistance including the feedback network; In the application it is not recommended to apply a resistor from the output ISO
to GND directly in addition to the feedback network.
2) Not subject to production test; specified by design
3) Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external
resistors.
Data Sheet
17
Rev. 1.1, 2011-04-08
TLE7186F
5 V Low Drop Voltage Regulator
7
5 V Low Drop Voltage Regulator
The TLE7186F incorporates a 5V LDO for µC supply. The voltage regulator is protected against Over Temperature
by the central temperature sensor (see Chapter 9.2.1 and Chapter 9.2.2). It has an integrated current limitation
and Under Voltage detection.
Parameters for Under Voltage detection see Chapter 9.2.5.
VDD
VS
temperature
5V LDO
sensor
Error logic and
Wake-up logic
Figure 6
Block diagram of 5V LDO
7.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
VS = 6.0 to 45 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Output voltage
VDD1
VDD2
IOCL
4.85
–
5.25
5.20
270
100
–
V
2mA<=Iload<=70mA;
C
load= 1...22uF1)
Output voltage
4.90
130
–
–
V
5mA <=Iload<=25mA;
load= 1...22uF1)
C
LDO over current limitation
Load regulation
–
mA
mV
dB
no activation of error
by current limitation
DVDD
PSRR
50
–
l
C
oad step 0...20mA;
VDD=1uF
Power supply ripple rejection2)
50
100Hz sine wave;
0.5Vpp
VVS>=7V
7.1.6
Power supply ripple rejection2)
PSRR
–
31
–
dB
100Hz sine wave;
0.5Vpp
6V<=VVS<7V
1) ceramic C with 100nF with ESR<0.1Ω in parallel
Data Sheet
18
Rev. 1.1, 2011-04-08
TLE7186F
5 V Low Drop Voltage Regulator
2) Not subject to production test; specified by design
5,150
5,100
5,050
5,000
4,950
25°C
-40°C
+150°C
0,000
0,010
0,020
0,030
0,040
0,050
0,060
0,070
0,080
I_VDD [A]
Figure 7
Typ. VDD output voltage vs. load current
Data Sheet
19
Rev. 1.1, 2011-04-08
TLE7186F
5 V Low Drop Voltage Regulator
5,07
5,065
5,06
5,055
5,05
25°C
5,045
5,04
5,035
5,03
0
5
10
15
20
25
30
35
40
45
50
U_VS [V]
Figure 8
Typ. VDD output voltage vs. supply voltage
Data Sheet
20
Rev. 1.1, 2011-04-08
TLE7186F
Interface, VDH Switch and INH Digital Output
8
Interface, VDH Switch and INH Digital Output
8.1
PWM Interface (IFMA)
The TLE7186F has an integrated interface supporting the typical PWM interface between a remote master ECU
and the µC. The link to the external master ECU is a single wire communication based on the battery voltage and
running typ. with about 10 to 400 Hz. The information is encoded in the duty cycle of the signal.
This communication line requires a signal conditioning to connect to the on board µC.
The integrated circuit supports the incoming data path.
The outgoing data path is formed by external components
interface
uC
TLE 7184 F
ECU
VDD
VS
VS
KL 30
Wake up
Pull up
IFuC
340k
700k
IFMA
T3
Interface_uC
R1
10k
VCC
T1
GND
T2
Figure 9
The integrated circuitry is described in Figure 9.
The main task of this interface is level shifting and protection of the µC.
Structure PWM Interface
The IFuC signal is following the IFMA signal, passing the duty cycle information from IFMA to the IFuC.
The µC port is used as input and is listening to the IFuC signal. The voltage at IFMA is monitored. If IFMA is low
the IFuC open drain output is switched on - forcing the IFuC signal to low.
If IFMA is high, the IFuC open drain output is deactivated and the IFuC signal is pulled to high by the internal pull-
up resistor.
The IFMA input is used as well for wake-up. See Chapter 9.1
Influence of serial resistor at IFMA pin
As shown in Figure 9 a 10k resistor R1 is recommended to protect the IFMA pin against negative voltage levels
coming from the interface signal. The integrated pull down and pull up resistors at the IFMA pin form a voltage
divider together with the resistor R1. This will influence the resulting switching level of the IFMA interface in the
application compared to the levels specified directly at the IFMA pin.
In this datasheet an additional parameter is provided to calculate the influence of the 10k resistor. The specified
IFMA input current divided by Vs allows to calculate the drop over R1 with the following formula:
I
Voltage _ drop _ over _ R1= IFMA *VVS *R1
VVS
Data Sheet
21
Rev. 1.1, 2011-04-08
TLE7186F
Interface, VDH Switch and INH Digital Output
8.2
VDHS Switch
The System IC has an integrated switch connecting the VDH pin to the VDHS pin. This allows to place an external
voltage divider for VDH voltage monitoring at the VDHS pin and to disconnect this voltage divider from VDH during
sleep mode to assure low current consumption. The VDHS switch is only deactivated when the VDD regulator is
switched off.
8.3
Digital Output INHD
The System IC provides a digital output INHD showing the logic state of INH (e.g. KL15) after a complete wake-
up of the driver (approx. 1ms). The input levels of INH for the INHD output are defined separately from the levels
for wake-up. Voltage levels for INH wake-up function please see Chapter 9.4 section Wake-up and go-to-sleep.
The output stage consists of an integrated low side switch with a pull-up resistor to VDD.
8.4
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 6.0 to 20V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Interface - static parameters
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
IFMA input voltage high level
(for IFµC high)
VIMHL
VIMLL
VIMhy
VIMWH
59
–
–
–
–
–
–
–
%
%
%
V
of VVS; IC not in
Sleep Mode
IFMA input voltage low level
(for IFµC low)
46
9
of VVS; IC not in
Sleep Mode;
IFMA input hysteresis
(for IFµC)
0.5
2
of VVS; IC not in
Sleep Mode
IFMA wake up voltage high level
= VS-VIFMA
4
valid in Sleep Mode
IFMA low time to guarantee wake- tIFlow
100
–
µs
VVS=7...20V
up
8.4.6
8.4.7
IFMA internal pull-up resistor to VS RIMu
210
420
340
700
495
980
kΩ
kΩ
–
IFMA internal pull-down resistor to RIMd
GND
not active in Sleep
Mode
8.4.8
IFMA input current related to VS
I
IFMA/VVS
µA/V
–
V
V
IFMA = 59% of VVS
IFMA = 46% of VVS
-2.0
-3.0
–
–
+2.0
+1.0
8.4.9
IFµC output low voltage
VIuLL
–
–
–
0.5
23
V
no external load
–
8.4.10 IFµC internal pull-up resistor to VDD RIu
8.5
kΩ
Interface - dynamic parameters
8.4.11 IFµC duty cycle
dIu
0
–
–
–
100
6
%
–
8.4.12 Propagation time rising edge IFµC tPRE
µs
Including rise time
to 80% of VVDD
load=100pF
Including fall time to
20% of VVDD
load=100pF
;
C
8.4.13 Propagation time falling edge IFµC tPFE
–
–
5
µs
;
C
Data Sheet
22
Rev. 1.1, 2011-04-08
TLE7186F
Interface, VDH Switch and INH Digital Output
Electrical Characteristics - Protection and diagnostic functions (cont’d)
VS = 6.0 to 20V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Cload=100pF
Min.
Typ.
Max.
8.4.14 Deviation between rising and falling tPD
–
–
4
µs
IFµC
VDH switch
8.4.15 Ron VDH switch
RVDH
VINHDL
VINHDH
–
–
150
Ω
Load current = 1mA
INHD digital output
8.4.16 Low level input voltage INH
(for INHD=low)
–
–
–
1.5
–
V
V
–
–
8.4.17 High level input voltage INH
(for INHD=high)
2.2
8.4.18 Input hysteresis of INH for INHD1) dVINHD
100
–
–
–
–
–
mV
V
–
8.4.19 INHD low level output voltage
VINHD
RINHD
0.5
115
no external load
–
8.4.20 INHD Internal pull-up resistor to
42.5
kΩ
VDD
1) Not subject to production test; specified by design
Data Sheet
23
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
9
Description of Modes, Protection and Diagnostic Functions
9.1
Description of modes
The operation of TLE7186F can be described by different operation modes
Error conditions TLE7184F and used abbreviations:
VREG Under Voltage Diagnosis ( VREG_UVD)
VDD Under Voltage Diagnosis ( VDD_UVD)
Over Current Shut Down( OCSD)
VDH Over Voltage Shut Down ( VDH_OVSD)
IOV Over Voltage Shut Down ( IOV_OVSD))
Short Circuit Detection ( SCD)
Over Temperature Pre-Warning ( OTPW)
Over Temperature Shut Down( OTSD)
Sleep Mode
VDD Under Voltage Shut Down( VDD_UVSD)
VREG Under Voltage Shut Down( VREG_UVSD)
- low quiescent current
- all supplies switched off
SCDL Pin Open Detection ( SCDLPOD)
VS Under Voltage Lockout ( VS_UVLO)
/INH = High
“OR”
VS Under Voltage Lockout ( VS_UVLO) leads from every mode into the Sleep Mode
IFMA= Low
Over Temperature Shut Down( OTSD) leads from every mode except Dead Lock Mode into the Sleep
Mode
Wake-up Mode
- ramp-up of
int5V, VREG and VDD
VREG_UVSD (no OTPW)
Wake-up time
expired
VDD_UVSD “OR” (VREG_UVSD “AND” OTPW)
Reset by /RGS “AND“ OTPW
OTPW “OR” VDD_UVSD
Normal Mode
with
Error Mode
VREG Shut-down
Mode
Deadlock Mode
*2)
OT-Prewarning
- latched error is reported
- MOSFets switched-off
- VREG and VDD on
- latched error is reported
- MOSFets switched-off
- VREG off
- VREG and VDD off
- latched error is reported
- driver stages are active
- latched error is reported
- MOSFets switched-off
- only 5Vint supply is on
Error condition
occures*1)
Error
condition
Reset of
error
occures*1)
Reset of OTPW error
Normal Mode
without
VDD_UVSD
“OR”
Error Conditions
VREG_UVSD
- no error is reported
- driver stages are active
OTPW
VDD_UVSD “OR” (VREG_UVSD “AND” OTPW)
VREG_UVSD (no OTPW)
/RGS = Low
for t > tsleep
/RGS = Low for t>
t
sleep
Go-to-Sleep Mode
- VDD andVREG are
switched off
*1) Error conditions:
VREG_UVD, VDD_UVD, OCSD, VDH_OVSD,
- latched error is reported
IOV_OVSD, SCD, SCDLPOD
*2) only way to leave this mode is VS_UVLO
VDD <= VDDsleep
Figure 10 State diagram TLE7186F
Data Sheet
24
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
Sleep Mode:
The sleep mode is entered if the device is in the Go-to-sleep Mode and the VDD voltage is lower than VDDsleep
.
The complete chip is deactivated beside the wake-up function (see Wake-up Mode). This mode is designed for
lowest current consumption from the power net of the car. The passive clamping is active. For details see the
description of passive clamping, see Chapter 9.2.15.
The only way to leave the Sleep Mode is to go to the Wake-up Mode.
Wake-up Mode:
The TLE7186F wakes up if INH (=KL15) is high or if IFMA is low and VVS is higher than VVSLO
.
In this mode all supplies are ramping up. As soon as the internal 5V is available, a so called wake-up timer starts
to run. If the IC reaches this state, the wake-up will continue even if the wake-up signals at INH or IFMA disappear.
The PWM interface (IFMA) is active as soon as the VDD voltage is sufficiently high. During this time it is expected
that the supplies are powered up and the µC sets the RGS to high. All external MOSFETs are switched off actively
or passively. When the wake up timer is expired the IC goes into the Error mode.
In this mode all errors will be ignored beside Over Temperature Shut Down or VS Under Voltage Lockout.
Error Mode
The Error Mode can be reached in 3 different ways:
1. The device is in Wake-up Mode and the wake up timer expires
2. The device is in Normal Mode and one or more of the following errors occur: VREG Under Voltage Shut Down,
VDD Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down, IOV Over Voltage
Shut Down, Short Circuit Detection or SCDL Open Detection.
3. The device is in Normal Mode with OT-Prewarning and one or more of the following errors occur: VREG Under
Voltage Shut Down, VDD Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down,
IOV Over Voltage Shut Down, Short Circuit Detection or SCDL Open Detection.
In this mode an Error is set at the ERROR Pin and all external MOSFETs are actively switched off as long as the
bootstrap voltages allows it. The interface is active. VDHS switch is on and the current sense functions are
working. VDD and VREG are active. Passive clamping is not active.
The Error mode can be left in the following ways:
1. If no error is present, the IC can be sent to Normal Mode by a reset with the RGS pin.
2. If a VREG Under Voltage Shut Down occurs and no Over Temperature Prewarning is present, the device will
go to VREG Shut-down Mode.
3. If VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down together with a Over
Temperature Prewarning occurs, the device will go into Deadlock Mode.
4. If Over Temperature Prewarning is present, the IC can be sent to Normal Mode with OT-Prewarning by a reset
with the RGS pin.
Normal Mode
The Normal Mode can be reached in two different ways:
1. The device is in Error Mode, no error is present and a reset is performed by the RGS pin.
2. The device is in Normal Mode with OT-Prewarning, the chip temperature is below the OT-Prewarning level and
a reset is performed by the RGS pin.
In the Normal Mode all functions are active and available with the regular limitations of the bootstrap principle. The
gate drive output stages can be controlled with the input pins.
The Normal Mode can be left in 5 ways:
1. The devices goes to the Go-To-Sleep Mode by setting RGS to low for a time longer than tsleep
.
2. If a Over Temperature Prewarning occurs the device goes into the Normal Mode with OT-Prewarning.
Data Sheet
25
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
3. If a VREG Under Voltage Shut Down occurs and no Over Temperature Prewarning is present, the device will
go to VREG Shut-down Mode.
4. If VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down together with a Over
Temperature Prewarning occurs, the device will go into Deadlock Mode.
5. If one or more of the following errors occur, the device goes to the Error Mode: VREG Under Voltage Shut
Down, VDD Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down, IOV Over
Voltage Shut Down, Short Circuit Detection or SCDL Open Detection.
Go-To-Sleep Mode
The Go-To-Sleep Mode can be reached in 2 different ways:
1. The device is in Normal Mode and RGS is set to low for a time longer than tsleep
.
2. The device is in VREG Shut-down Mode and RGS is set to low for a time longer than tsleep
.
In this mode all external MOSFETs are actively or passively switched off. An Error is set and is shown as long as
VDD is sufficient high. In this mode VDD and VREG is switched off. As soon as VDD voltage reaches the VVDDsleep
level the IC goes into the Sleep Mode.
Normal Mode with Over Temperature Prewarning
This mode can be reached in 2 different ways:
1. The device is in Error Mode, the chip temperature is above the prewarning level while a reset is performed by
the RGS pin.
2. The device is in Normal Mode and the chip temperature increases above the prewarning level.
In this mode all functions are active and available. The gate drive output stages can be controlled with the input
pins with the regular limitations of the bootstrap principle.
The ERR pin is set to low and this error is latched.
There are 3 possibilities to leave this mode:
1. This mode can be left into the Normal Mode by applying a reset at RGS if the temperature has dropped below
the Over Temperature pre-warning level.
2. The device goes into Error Mode if one of the following errors occurs: VREG Under Voltage Shut Down, VDD
Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down, IOV Over Voltage Shut
Down, Short Circuit Detection or SCDL Open Detection.
3. The device goes into Deadlock Mode if either a VREG Under Voltage Shut Down or a VDD Under Voltage Shut
Down occurs.
If the temperature is still in the pre-warning range and RGS is low, the ERR pin gets high only during the time were
RGS is low and the IC stays in the “Normal Mode with Over Temperature Prewarning”.
Deadlock Mode
This mode is intended to prevent the IC for long time toggling in Over Temperature if a short is present at the VDD
pin.
There are 4 ways to enter this mode:
1. The IC is in Error Mode and a VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down
together with a Over Temperature Prewarning occurs
2. The IC is in Normal Mode with Over Temperature Prewarning and a VDD Under Voltage Shut Down or a VREG
Under Voltage Shut Down occurs.
3. The IC is in Normal Mode and a VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down
together with a Over Temperature Prewarning occurs.
4. The IC is in VREG Shut Down Mode and a VDD Under Voltage Shut Down or a Over Temperature Prewarning
occurs.
Data Sheet
26
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
In this mode the VDD and VREG regulators are switched off. The gates of the external MOSFETs are passively
clamped.
The VDHS switch is deactivated.
The IC will not react to IFMA or INH signals. Even a Over Temperature Shut Down detection will have no influence.
The internal logic is supplied and prevents the IC from going into “Go to sleep mode”.
The only way to leave this state is that VS is lower than VVSLO, means a VS Under Voltage Lockout occurs. In this
case the IC goes to Sleep Mode.
VREG Shut Down Mode
This mode is intended to prevent the IC from long time toggling in Over Temperature if a short is present at the
VREG pin.
There are 2 ways to enter this mode:
1. The IC is in the Error Mode and a VREG Under Voltage Shut-down occurs without an Over Temperature
Prewarning.
2. The IC is in the Normal Mode and a VREG Under Voltage Shut-down occurs without an Over Temperature
Prewarning.
In this mode VREG is switched off, but VDD is still present. The VDHS switch is still active and the PWM interface
(IFMA) is working.
The IC will not react to IFMA or INH signals.
In this situation the µC is still able to provide diagnostic information by the interface. It can prevent the IC from Go-
to-Sleep Mode and can avoid unintended toggling as long there is no Over Temperature Shut Down.
This state can be left by 2 ways:
1. The µC has to set RGS to low for a time longer than tsleep. In this case the IC goes to Sleep Mode.
2. If a VDD Under Voltage Shut Down or an Over Temperature Prewarning occurs the IC will go into the Deadlock
Mode.
9.2
Protection and Diagnosis Functions
Over Temperature Shut Down (OTSD)
9.2.1
If the junction temperature is exceeding the Over Temperature shut down level an error signal is set. The driver
IC will pull down the gate-source voltage of all external MOSFETs, deactivate the VDD and VREG supply and go
directly into the Sleep Mode.
In the Sleep Mode the regular wake-up conditions will be used. Over Temperature cycling is possible and will lead
to accelerated aging of the IC.
In Deadlock Mode an Over Temperature Shut Down is ignored.
9.2.2
Over Temperature Prewarning (OTPW)
The IC provides a digital Over Temperature Pre-Warning. If no other errors are present, the IC goes into “Normal
Mode with Over Temperature Prewarning”. This function is not available in Deadlock Mode.
9.2.3
Analog Temperature Monitoring
The TEMP output of the TLE7186F provides an analog voltage signal proportional to the chip temperature. This
function is not available in Deadlock Mode.
Data Sheet
27
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
9.2.4
VS Under Voltage Lockout (VS_UVLO)
The TLE7186F has an integrated VS Under Voltage Lockout to assure that the behavior of the complete IC is
predictable in all supply voltage ranges.
If the supply voltage at VS reaches the Under Voltage shut down level VVSLO for a minimum specified filter time
the IC goes into Go-to-Sleep Mode and finally into Sleep Mode.
9.2.5
VDD Under Voltage Diagnosis (VDD_UVD)
The TLE7186F has an integrated VDD Under Voltage Diagnosis to assure that the behavior of the bridge driver
output stages is predictable in all supply voltage ranges.
If the voltage at VDD reaches the Under Voltage diagnosis level VUVVDD for a minimum specified filter time, an error
is set and the IC goes into Error Mode.
VS
VVDD
< TRR
VRT
TRR
ERR
____
RGS
Figure 11 Timing of VDD Under Voltage Diagnosis
9.2.6
VDD Under Voltage Shut Down (VDD_UVSD)
The TLE7186F has an integrated VDD Under Voltage Shut Down to avoid operation with VDD shorted to GND.
If the supply voltage at VDD reaches the Under Voltage shut down level VVDDsleep and the wake-up time is expired,
VREG and VDD will be switched off and the IC will go to Deadlock Mode.
9.2.7
VREG Under Voltage Diagnosis (VREG_UVD)
The TLE7186F has an integrated VREG Under Voltage Diagnosis to assure that the behavior of the bridge driver
output stages is predictable in all supply voltage ranges.
Data Sheet
28
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
If the voltage at VREG reaches the Under Voltage diagnosis level VUVVR for a minimum specified filter time, an
error is set and the IC goes into Error Mode.
As long as the VS Under Voltage Lock Out is not reached, the low side MOSFETs will stay actively switched off.
The status of the high side MOSFET drivers is dependent on the bootstrap voltage - which depends on the SHx
voltage. It is expected that the SHx nodes will be pulled to VDH level by the high side MOSFETs and this will switch
off the high side MOSFETs passively.
In this situation the short circuit detection of this output stage is deactivated to avoid wrong error reporting.
9.2.8
VREG Under Voltage Shut Down (VREG_UVSD)
The TLE7186F has an integrated VREG Under Voltage Shut Down to avoid operation with VREG shorted to GND.
If the supply voltage at VREG reaches the Under Voltage shut down level VVRSD, “AND” no Over Temperature
Prewarning is set “AND” the wake up time is expired, VREG will be switched off and the IC will go to the VREG
Shut Down Mode. In this condition the µC is still supplied and can communicate via the PWM interface (IFMA),
the MOSFETs are switched off and an error is set. The only way to leave this mode is to go to “Sleep Mode”.
If the supply voltage at VREG reaches the Under Voltage shut down level VVRSD “AND” Over Temperature
Prewarning is set “AND” the wake-up time is expired, VREG and VDD will be switched off and the IC will go to the
“Dead Lock Mode”.
The only way to leave this Deadlock Mode is to provoke a VS Under Voltage Shut Down, for example by removing
the battery voltage.
9.2.9
IOV and VDH Over Voltage Shut Down (IOV_OVSD, VDH_OVSD)
The TLE7186F has an integrated Over Voltage shut down to minimize the risk of destruction of the IC at high
supply voltages caused by violation of the maximum ratings.
The voltages are observed at the Over Voltage input pin IOV and at the VDH pin. If the voltage at the IOV pin or
at the VDH pin exceeds the Over Voltage shut down level for more than the specified filter time, the IC goes into
Error Mode.
The effective Over Voltage level can be adjusted by a voltage divider at the IOV pin. This voltage devider is
normally supplied by the VDHS pin. The Over Voltage level at VDH is fix.
9.2.10
Dead Time and Shoot Through Protection
In bridge applications it has to be assured that the external high side and low side MOSFETs are not “on” at the
same time, connecting the battery voltage directly to GND. The dead time generated in the TLE7186F is set to a
minimum value if the DT pin is connected to GND. This function assures a minimum dead time if a common input
signal for ILx and IHx is used.
The dead time can be increased by connecting the DT pin via a dead time resistor RDT to GND. Larger dead time
resistors result in a longer dead time.
The typical dead time can be calculated with the following formula:
0.081
tdeadtime
=
µs
2.4
0.02 +
4+Rdt
Please put in the Rdt in kΩ.
If an exact dead time of the bridge is needed, the use of the µC PWM generation unit is recommended.
In case of an open DT pin, the dead time is set to the internal maximum value.
In addition to this dead time, the TLE7186F provides a locking mechanism avoiding that both external MOSFETs
of one half bridge can be switched on at the same time. This functionality is called shoot through protection.
Data Sheet
29
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
If the command to switch on both high and low side switches in the same half bridge is given at the input pins, the
command will be ignored. The outputs will stay in the state like before the conflicting input.
9.2.11
Short Circuit Protection (SCP)
The TLE7186F provides a short circuit protection for the external MOSFETs. It is monitoring the drain-source
voltage of the external MOSFETs. (see Figure 3 )
The drain-source voltage monitoring for a certain external MOSFET is active as soon as the corresponding driver
output stage is set to “on” and the dead time and the blanking time is expired.
The blanking time starts when the dead time is expired and assures that the switch on process of the MOSFET is
not taken into account. It is recommended to keep the switching times of the MOSFETs below the blanking time.
The short circuit detection level is adjustable in an analogue way by the voltage setting at the SCDL pin. There is
a 1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the
SCD circuit at 1 V drain-source voltage, the SCDL pin must be set to 1 V as well. The drain-source voltage limit
can be chosen between 0.3 ... 2 V.
In the case that after the expiration of the blanking time the drain source voltage of the observed MOSFET is still
higher then the SCDL level, the SCD filter time tSCP starts to run. A capacitor is charged with a current. If the
capacitor voltage reaches a specific level (filter time tSCP), the error signal is set and the IC goes into Error Mode.
If the SCD condition is removed before the SC is detected, the capacitor is discharged with the same current. The
discharging of the capacitor happens as well when the MOSFET is switched off. It has to be considered that the
high side and the low side outputs of one phase are working with the same capacitor.
9.2.12
SCDL Pin Open Detection (SCDL_open)
For safety reasons a pull-up resistor at the SCDL pin assures that in case of an open pin the SCDL voltage is
pulled to a high level. In this case an error is set and the IC goes into Error Mode.
9.2.13
Over Current Shut Down (OCSD)
The TLE7186F is monitoring the output signal of the operational amplifier. If the output signal reaches a specified
level close to the upper rail (VDD) for a specified time, the System IC detects an over current condition and sets
an error signal. The driver output pulls down the gate-source voltage of all external MOSFETs actively and stays
in the Error Mode.
9.2.14
VDD Current Limitation
The TLE7186F has an integrated voltage supply for an external µC. The output current of the supply is limited to
a specified value. This limitation does not cause any error reporting. In this situation a VDD Under Voltage
detection is likely. If the current is limited for a longer time, the Over Temperature protection will react.
9.2.15
Passive Gxx Clamping
If VS Under Voltage Lock Out is detected or the device is in Sleep Mode, a passive clamping is active as long as
the voltage at VS or VDH is higher than 3V. Even below 3V it is assured that the MOSFET driver stage will not
switch on the MOSFET actively.
The passive clamping means that the BHx and the VREG pin are pulled to GND with specified pull down resistors.
Together with the intrinsic diode of the push stage of the output stages which connect the gate output to BHx
respectively VREG, this assures that the gate of the external MOSFETs are not floating.
9.3
ERR Pin
The TLE7186F has a status pin to provide diagnostic feedback to the µC. The logical output of this pin is an open
drain output with integrated pull-down resistor to GND (see Figure 12).
Data Sheet
30
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
Reset of error registers and Disable
The TLE7186F can be reset by the enable pin RGS. If the RGS pin is pulled to low for a specified minimum time,
the error registers are cleared. If the error is still existing when the RGS pin is pulled to low, no reset will be
performed and the ERR pin stays low. The only exemption of this behavior is the Over Temperature Prewarning.
Even if the junction temperature is exceeding the over temperature prewarning level, the error signal goes to high
when RGS is pulled low.
Figure 13 describes the timing behavior during error reset:
For more details see description of Error Mode and Normal Mode with Over Temperature Pre-Warning in
Chapter 9.1.
Internal
5V
internal
Error
Logic
uC
ERR
Interface_uC
GND
GND
Figure 12 Structure of ERR output
TLE 7184 F
releases signal
Error occurs
5V
Error reset
Normal operation
Sleep mode
ERR
0V
No driver
reset
undefined
tnres-min
t
res-min
5V
RGS
0V
Short glitches are
ignored
tsleep
Figure 13 Enable / Disable timing
Data Sheet
31
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
9.4
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 7.0 to 33V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Typ. Max.
Unit
Conditions
Min.
Dead time
9.4.1
Programmable internal dead time tDT
0.095 0.14
0.18
0.55
1.55
2.6
µs
RDT=0 Ω
0.29
0.85
1.2
0.42
1.21
1.88
3.62
RDT=10 kΩ
RDT=47 kΩ
RDT=100 kΩ
RDT=1000 kΩ
2.1
5.1
9.4.2
9.4.3
Max. internal dead time
tDT_MAX
dtDT
2.0
-20
-15
-14
-12
-14
-12
4.0
–
6.0
20
15
14
12
14
12
µs
%
%
%
%
%
%
DT pin open
Dead time deviation between
channels
–
–
RDT<=47 kΩ
9.4.4
9.4.5
Dead time deviation between
channels LSoff -> HS on
dtDTH
dtDTL
–
–
–
RDT<=47 kΩ
–
Dead time deviation between
channels HSoff -> LS on
–
–
RDT<=47 kΩ
Short circuit protection
9.4.6
9.4.7
9.4.8
9.4.9
Short circuit protection detection
level
VSCPDL
ASCP
0.3
-20
-10
–
–
–
2
V
programmed by
SCDL pin
Short circuit protection detection
Accuracy
+20
+10
%
%
0.3V<= VSCDL<0.9V
Short circuit protection detection
Accuracy
ASCP
0.9V<=
V
SCDL<=2.0V
Filter time of short circuit protection tSCP(off)
2.3
4
–
–
4.3
8
µs
µs
Ixx static on
9.4.10 Blanking time plus filter time of
short circuit detection
tSCPTT
Ixx switching “off”
to “on”
9.4.11 Internal pull-up resistor SCDL to
VDD
RSCDL
180
300
420
kΩ
–
9.4.12 SCDL open pin detection level
9.4.13 Filter time of SCDL open pin
VSCPOP
tSCPOP
VSCOPH
2.0
1
–
2.5
3.4
–
V
–
–
–
–
µs
V
9.4.14 SCDL open pin detection level
hysteresis2)
–
0.3
Over- and Under Voltage monitoring
9.4.15 Over Voltage shut down at IOV
VOVIOV
4.15
–
4.4
V
IOV voltage
increasing
9.4.16 Pull down resistor at IOV to GND RIOV
300
33
–
–
–
700
37
kΩ
V
–
9.4.17 Over Voltage shut down at VDH
VOVVDH
VDH increasing
–
9.4.18 Over Voltage shut down filter time tOV
13
23
µs
for IOV or VDH
9.4.19 Under Voltage diagnosis at VREG VUVVR
5.5
–
6.5
V
VREG decreasing
Data Sheet
32
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
Electrical Characteristics - Protection and diagnostic functions (cont’d)
VS = 7.0 to 33V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
9.4.20 Under Voltage diagnosis filter time tUVVR
10
–
30
µs
–
for VREG
9.4.21 Under Voltage shut down at VREG VVRSD
1.5
4.4
1
–
2.3
5.5
3
V
VREG decreasing
9.4.22 Under Voltage lockout at VS
VVSLO
5.0
–
V
V
VS decreasing
9.4.23 Under Voltage lockout filter time for tUVLO
µs
–
VS
ERR pin1)
9.4.24 ERR output voltage
VERR
4.4
–
–
–
–
V
No external load
9.4.25 Rise time ERR (20 - 80% of internal tf(ERR)
3.5
µs
CLOAD=1nF;
5V)
9.4.26 Internal pull-down resistor ERR to Rf(ERR)
21.2
–
60
kΩ
–
GND
Reset and Enable
9.4.27 Low time of uC RGS signal without tnres
–
3
–
–
0.5
–
µs
µs
–
–
reset
9.4.28 Low time of uC RGS pin necessary tres
to trigger reset and to clear error
registers
Wake-up and go-to-sleep
9.4.29 Low level input voltage of RGS
9.4.30 High level input voltage of RGS
9.4.31 Input hysteresis of RGS2)
VRGSLL
VRGSHL
dRGS
–
–
–
–
–
–
1.6
–
V
–
–
–
–
–
2.8
100
100
–
V
–
mV
kΩ
V
9.4.32 RGS pull-down resistors to GND
9.4.33 Low level input voltage of INH3) for VINHL
RRGS
210
0.75
wake up
9.4.34 High level input voltage of INH3) for VINHH
2.1
–
–
–
–
V
–
–
–
wake up
9.4.35 INH high time to guarantee wake- tIHhigh
100
µs
up
9.4.36 INH pull-down resistors to GND
9.4.37 Wake up delay time
RINH
twake
tsleep
100
9
–
–
–
–
210
17
kΩ
ms
µs
V
9.4.38 RGS low time for go-to-sleep
20
50
9.4.39
V
DD voltage for changing
VDDsleep 1.5
2.3
–
–
from Go-to-Sleep Mode to Sleep
Mode
9.4.40
V
DD Under Voltage Shut Down
VUVSDVDD 1.5
–
2.3
V
1) ERR pin and Reset & Enable functional between VVS=6 ... 7V, but characteristics might be out of specified range
2) Not subject to production test; specified by design
3) These levels are valid for wake up of the IC. The input levels for INH deciding the output state of INHD are shown in
Chapter 8.4
Data Sheet
33
Rev. 1.1, 2011-04-08
TLE7186F
Description of Modes, Protection and Diagnostic Functions
Electrical Characteristics - Protection and diagnostic functions
VS = 6.0 to 33V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Temperature monitoring
1)
–
9.4.41 Over Temperature shut down
9.4.42 Over Temperature pre-warning
Tj(SD)
Tj(PW)
160
130
170
140
30
180
150
40
°C
°C
°C
1)
–
1)
–
9.4.43 Difference between Over
Temperature shut down level and
Over Temperature pre-Warning
level
dTj(SDPW) 20
9.4.44 Analog temperature output at 25°C VATRT
1.32
4.57
0
–
–
–
–
1.65
5.20
+6
V
C
load<=1.5nF;
Tj=25°C
9.4.45 Analog temperature output
coefficient
KATRT
VATRTd
TAT
mV/K
mV
°C
C
C
–
load<=1.5nF 1)
9.4.46 Analog temperature output drift
over lifetime1)
load<=1.5nF
9.4.47 Analog temperature range1)
-40
175
Over current detection
9.4.48 Over current detection level in% of VOCTH
92
–
–
96.5
4.2
%
–
–
VVDD
9.4.49 Filter time for over current detection tOC
1.8
µs
Under Voltage monitoring VDD
2)
9.4.50 Under Voltage shut down at VDD
VUVVDD
3.7
15
–
–
4.2
45
V
V
VDD decreasing
9.4.51 Under Voltage shut down filter time tUVVDD
µs
–
1) Not subject to production test; specified by design
2) For Under Voltage detection level during go-to-sleep see VDDsleep
Data Sheet
34
Rev. 1.1, 2011-04-08
TLE7186F
Phase voltage feedback
10
Phase voltage feedback
The TLE7186F incorporates a fast conversion of the phase voltages into logic signals. The threshold values are proportional
to VDH. The outputs are 5V push pull stages. When they are not used they can be left open.
5V
SHx
-
X_fb
+
VDH
Voltage feed back 3x
Figure 14 Block diagram phase voltage feedback
10.1
Electrical Characteristics
Electrical Characteristics - Phase Voltage Feedback
VS = 7 to 20V, Tj = -40 °C to +150 °C, FPWM < 25kHz, CLOAD<25pF, all voltages with respect to ground, positive current
flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
Low level threshold
High level threshold
Threshold difference
VILfb
VIHfb
dVIxfb
44.7
48.75
52.8
55.2
–
% of
VDH
VDH>7V
V
10.1.1
10.1.2
10.1.3
SHX decreasing1)
46.8
–
51.0
2.25
% of
VDH
VDH>7V
SHX decreasing1)
VDH>7V
SHX decreasing
V
% of
VDH
V
10.1.4
10.1.5
10.1.6
High level output voltage of x_fb
Low level output voltage of x_fb
VOHfb
VOLfb
4.0
-0.1
–
–
–
–
5.2
0.2
250
V
I= -40uA
I= 40uA
V
Propagation delay time incl. rise or fall tPDfb
time
ns
CLOAD<25pF
10.1.7
Matching of propagation delay time
tdPDfb
–
–
100
ns
1) Not subjected to production test; specified by design
Data Sheet
35
Rev. 1.1, 2011-04-08
TLE7186F
Application Description
11
Application Description
In the automotive sector there are more and more applications requiring high performance motor drives, such as
HVAC fans, engine cooling fans, pumps etc.. In these applications synchronous and asynchronous 3-phase
motors are used, combining high output performance, low space requirements and high reliability.
R
2,2kΩ
KL 15
R
33Ω
L
2,2µH
interface
R
1,2kΩ
C
1nF
L
2,2µH
VBAT
R
RVS
1,6kΩ
10 Ω
CBR
CBR
1µF
4,7mF
CVS
100 nF
CVS
2µF
PGND
PGND
R
R
10kΩ
10kΩ
CREG
2µF
___
INH
VDHS
RVDH
IFMA
VS VREG
VDH
CBS1
470nF
BH1
RVDH1
ROV1
THS1
GH1
SH1
RGH1
IOV
ROV2
CBS2
470nF
RVDH2
BH2
THS2
GH2
SH2
IFuC
____
RGS
____
INHD
____
ERR
RGH2
CBS3
470nF
BH3
THS3
TLE
7186
GH3
SH3
TEMP
RGH3
U_fb
V_fb
W_fb
IL1
TLS1
GL1
GL2
___
RGL1
IH1
µC
IL2
___
IH2
TLS2
IL3
___
RGL2
IH3
RSC1
SCDL
GL3
TLS3
RGL3
RSC2
VDD
DT
+
Rfb2
CVDD2
CVDD1
100nF 2.2nF
SL
ISP
RS
RS
RDT
Rfb3
Shunt
AGND
RLP
ISN
ISO
GND
AGND
GND
Rfb1
CLP
CISO
For details of the current sense feature
please see the dedicated chapter
GND
AGND
GND
PGND
Figure 15 Application Circuit TLE7186F
This is a simplified example of an application circuit. The function must be verified in the real application.
Data Sheet
36
Rev. 1.1, 2011-04-08
TLE7186F
Package Outlines
12
Package Outlines
11 x 0.65 = 7.15
0.65
0.1
0.9 MAX.
(0.65)
9
A
0.05
24
0.55
0.1
8.75
48x
0.08
B
25
36
37
13
48
Index Marking
48x
1
12
0.05
0.35
Index Marking
M
0.1 A B C
C
(0.2)
0.15
6.8
0.05 MAX.
GVQ01049
STANDOFF
Figure 16 PG-VQFN-48
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Dimensions in mm
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet 37
Rev. 1.1, 2011-04-08
TLE7186F
Revision History
13
Revision History
Revision
Date
Changes
Rev. 1.1
2011-04-08
- Voltage difference between ISP and ISN specified
- Minimum buffer capacitor CVREG specified
- Description of SH currents added
- Fig. 4 new
- Pull up and pull down resistors at IHx and ILx expanded
- Rise and fall times specified
- Propagation time tolerance reduced
- Limit the lower load current of VDD to 2mA
- Fig. 5 updated
- Steady state differential input voltage range across VIN removed
- Common mode suppression, footnote added
- IFMA low time to guarantee wake-up added
- Matching of IFMA pull up / pull down resistors replaced by
IFMA input current / VS
- Pull up resistor at IFuC output expanded
- Pull up resistor at INHD expanded
- High level input voltage INH (for INHD=high) adapted
- Dead time description improved
- Short circuit detection accuracy improved
- SCDL open pin detection level hysteresis, footnote added
- Rise time ERR adapted
- Pull down resistor at ERR output expanded
- INH high time to guarantee wake-up added
- Analog temperature output tolerance at 25°C improved
Data Sheet
38
Rev. 1.1, 2011-04-08
Edition 2011-04-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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