TLE8080-3EM_技术文档

TLE8080EM

Engine Management IC for Small Engines

TLE8080EM

TLE8080-2EM

Data Sheet

Rev. 1.1, 2012-10-19

Automotive Power

TLE8080EM

Table of Contents

1

2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3

3.1

3.2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5

5V Supply, Reset and Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power On Reset and Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical Characteristics 5V Supply, Reset and Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1

5.2

5.3

5.4

6

6.1

6.2

Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical Characteristics Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7

Variable Reluctance Sensor (VRS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.1

Electrical Characteristics VR Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8

8.1

8.2

8.2.1

8.2.2

8.3

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SPI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Set and Reset of Diagnosis Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Electrical Characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9

9.1

9.2

K-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electrical Characteristics K-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10

11

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Data Sheet

2

Rev. 1.1, 2012-10-19

Engine Management IC for Small Engines

TLE8080EM

1

Overview

Features

•

Supply 5V (+/-2%), 250mA

K-line transceiver (ISO 9141)

Serial Peripheral Interface (SPI)

4 low side driver for inductive loads with overtemperature and

overcurrent protection and open load/short to GND in off diagnosis:

– 2 low side switches with maximum operation of 2.6A

– 2 low side switches with maximum operation of 350mA

1 low side driver for resistive loads with maximum operation current

of 3A including overtemperature and overcurrent protection

Configurable variable reluctance sensor interface

Reset output and 5V undervoltage detection

Watchdog

PG-SSOP24

•

Green product (RoHS compliant)

AEC qualified

Description

The TLE8080EM is an engine management IC based on Infineon Smart Power Technology (SPT). It is protected

by embedded protection functions and integrates a power supply, K-line, SPI, variable reluctance sensor interface

and power stages to drive different loads in an engine management system. It provides a compact and cost

optimized solution for engine management systems. It is very suitable for one cylinder motorcycle engine

management systems.

TLE8080-2EM

This version differs from the main version in the parameters “V5DD Reset Threshold for TLE8080-2EM” and

“Power On Reset Delay Time” in Chapter 5.4.

For ordering conditions please contact the nearest Infineon Technologies office.

Type

Package

Marking

TLE8080EM

TLE8080-2EM

PG-SSOP24

TLE8080EM

TLE8080-2EM

Data Sheet

3

Rev. 1.1, 2012-10-19

TLE8080EM

Block Diagram

2

Block Diagram

VS

5V Voltage

Supply

V5DD

Undervoltage

Detection

WD_DIS

4

CSN; SI;

SPI

Watchdog

Reset

NRO

SO; SCLK

LS Driver

inductive loads

OUT5

OUT4

OUT3

OUT2

OUT1

350mA

LS Driver

inductive loads

350mA

LS Driver

inductive loads

2.6A

IN3

LS Driver

resistive loads

3A

LS Driver

inductive loads

2.6A

IN1

2

VR Sensor

K-Line

VR_OUT

KIO

VR_IN1; VR_IN2

RX; TX

Figure 1

Block Diagram

Data Sheet

4

Rev. 1.1, 2012-10-19

TLE8080EM

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

KIO

1

2

3

4

24

23

22

TX

VS

RX

OUT5

AGND

V5DD

NRO

OUT4

OUT3

21

20

5

25

PGND

6

PGND

OUT2

OUT1

19

18

17

IN3

7

IN1

8

CSN

SCLK

9

PGND

VR_IN1

VR_IN2

WD_DIS

16

15

14

13

10

11

12

SI

SO

VR_OUT

Pg-ssop-24.vsd

Figure 2

Pin Configuration

3.2

Pin Definitions and Functions

1

Symbol

Function

K-Line Bus Connection

KIO

VS

2

Battery Voltage: Block to AGND directly at the IC with min. 100nF ceramic

capacitor

3

OUT5

OUT4

OUT3

PGND

OUT2

OUT1

PGND

VR_IN1

VR_IN2

WD_DIS

VR_OUT

SO

Output Channel 5

4

Output Channel 4

5

Output Channel 3

6

Power Ground: internally connected to pin 9, connect externally to pin 9

Output Channel 2

7

8

Output Channel 1

9

Power Ground: internally connected to pin 6, connect externally to pin 6

VR Sensor Interface Input 1

10

11

12

13

14

15

16

17

VR Sensor Interface Input 2

Watchdog Disable: high active; internal pull down

VR Sensor Output

SPI Slave Output: high impedance

SPI Slave Input: internal pull down

SPI Clock Input: internal pull down

SPI Chip Select Input: low active; internal pull up

SI

SCLK

CSN

Data Sheet

5

Rev. 1.1, 2012-10-19

TLE8080EM

Pin Configuration

18

19

20

21

22

23

24

Symbol

IN1

Function

Control Input Channel 1: internal pull down

Control Input Channel 3: internal pull down

Reset Output: low active, open drain

IN3

NRO

V5DD

AGND

RX

5V Supply Output: connected to external blocking capacitor

Analog Ground: connected to system logic ground

K-Line Receive Output: logic output of data received from the K-Line bus KIO

TX

K-Line Transmit Input: logic level input for data to be transmitted on the K-Line bus

KIO; internal pull up

25

Exposed Pad

Substrate Connection: must be connected to PGND externally on PCB

Data Sheet

6

Rev. 1.1, 2012-10-19

TLE8080EM

General Product Characteristics

4

General Product Characteristics

Table 1

Absolute Maximum Ratings ¹⁾

T_j= -40°C to +150°C: All voltages with respect to ground unless otherwise specified.

Positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Voltages

Supply Voltage VS

Supply Voltage V5DD

V_VS

V_V5DD

V_x

-0.3

–

40

V

–

4.1.1

4.1.2

4.1.3

5.5

–

Input Voltage on Pins IN1,

IN3, SCLK, SI, WD_DIS

Input Voltage on Pins CSN, V_x

TX

-0.3

–

V5DD

+0.3V

V

–

4.1.3

4.1.4

4.1.5

Input Voltage VR_IN1,

VR_IN2

V_{VR_IN1/2}

5.5

see also 4.2.1

and 4.2.2

respect to PGND

all channels and

KIO are switched

off

DC Voltage on Pins OUT1-5, V_x

KIO

30

DC Voltage on Pins

V_x

-0.3

–

5.5

V

I_x<1mA

4.1.6

VR_OUT, SO, RX, NRO

DC Voltage AGND to PGND V_x

-0.3

–

0.3

35

V

4.1.7

4.1.8

respect to PGND

KIO is switched off

DC Voltage on Pin KIO

V_KIO

Currents

Input Current between

VR_IN1 and VR_IN2

I_{VR_IN1,VR_IN2}-–

I_{VR_IN1/2,GND}-–

–

50

10

mA

–

4.2.1

4.2.2

Input Current VR_IN1,

VR_IN2 to GND

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

T_j

-40

–

150

°C

–

4.3.1

4.3.2

T_stg

-55

ESD Resistivity all Pins to

GND

V_ESD

-2

–

2

kV

V

HBM²⁾

CDM³⁾

4.4.1

4.4.2

4.4.3

ESD Resistivity all Pins to

GND

-500

500

750

ESD Resistivity Pin 1, 12, 13, V_{ESD1,19,20,36}-750

24 (corner pins) to GND

V

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to EIA/JESD 22-A114B

3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1

Data Sheet

7

Rev. 1.1, 2012-10-19

TLE8080EM

General Product Characteristics

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not

designed for continuous repetitive operation.

Table 2

Functional Range

Parameter

Symbol

Values

Unit Note /

Test Condition

Number

Min.

6

Typ.

Max.

18

Supply Voltage

V_S

T_j

–

V

–

4.5.1

4.5.2

Junction Temperature

-40

150

°C

–

Note:Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

Table 3

Thermal Resistance

Parameter

Symbol

Values

Typ.

7

Unit Note /

Test Condition

Number

Min.

Max.

1)

Junction to Case

R_thJC

R_thJA

–

K/W

4.6.1

4.6.2

1) 2)

Junction to Ambient

29

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

Data Sheet

8

Rev. 1.1, 2012-10-19

TLE8080EM

5V Supply, Reset and Supervision

5

5V Supply, Reset and Supervision

5.1

5V Supply

The TLE8080EM integrates a voltage regulator for load currents up to 250mA. The input voltage at VS is regulated

to 5V on V5DD with a precision of ±2%. The design allows to achieve stable operation even with ceramic output

capacitors down to 470 nF. It is protected against overload, short circuit, and over temperature conditions. For low

drop operation, a charge pump is implemented.

VS

I_VS

Vref

+

-

I_V5DD

V5DD

e.g. µC

Figure 3

5V Supply

5.2

Power On Reset and Reset Output

The reset output NRO is an open drain output. When the level of V_V5DDreaches the reset threshold (V_RT)

(increasing voltage V_V5DD) the signal at NRO remains low for the power-up reset delay time (t_RD). The reset

function and timing is illustrated in Figure 4. The reset reaction time (t_RR) avoids wrong triggering caused by short

“glitches” on the V5DD-line. In case of V5DD power down (decreasing voltage; V_V5DD< V_RTfor t > t_RR) a logic low

signal is generated at the pin NRO to reset an external micro controller. The level of the reset threshold for

increasing V_V5DDis for the hysteresis (V_RH) higher than the level for decreasing V_V5DD

.

With an active reset all power stages and the K-Line output are disabled and SPI commands are ignored.

Data Sheet

9

Rev. 1.1, 2012-10-19

TLE8080EM

5V Supply, Reset and Supervision

Vs

t

V_V5DD

<

t_RR

V_RT

t_RR

t_RD

t_RR

V_NRO

t_RD

V_{NRO_H}

V_{NRO_L}

t

Figure 4

Reset Timing Diagram

5.3

Watchdog Operation

The TLE8088EE integrates a watchdog function which monitors the correct SPI communication with the micro

controller. A watchdog disable pin ( WD_DIS ) with an internal pull down current source is implemented. With a

high level the watchdog function is disabled.

For enabled watchdog function after power-up reset delay time ( t_RD), valid SPI communication from the micro

controller must occur within the watchdog period ( t_WP) specified in the electrical characteristics. A restart of the

watchdog period is done with a low to high transition of the CSN pin of a valid transmission of a 16 bit message.

A reset is generated (NRO goes LOW) for the time ( t_WR) if there is no restart during the watchdog period as shown

in Figure 5.

Status after watchdog overflow:

•

all outputs are switched off

SPI registers are not influenced

Watchdog Time Out bit in SPI status register is set

first answer to SPI communication is the content of the status register

Switching of Outputs and reset of Watchdog Time Out Bit after watchdog overflow:

•

Outputs 1 and 3 will be switched on with an positive edge at IN1 respectively IN3

Outputs 2, 4 and 5 will be switched on with a write command to CMD register

the watchdog time out bit will be reset with the rising edge of CSN of the first read command of the status

register

Data Sheet

10

Rev. 1.1, 2012-10-19

TLE8080EM

5V Supply, Reset and Supervision

Vs

t

V_5DD

V_RT

t

V_NRO

t_WR

t_RD

Normal operation

t_rr

t

Watchdog

Period

t

restart

t_WP

CSN

SI

t

e.g. 4 Bits

No correct SPI

communication

within the

16 Bits

1. correct SPI

communication

16 Bits

Watchdog Period

causing reset

Figure 5

Watchdog Timing Diagram

Data Sheet

11

Rev. 1.1, 2012-10-19

TLE8080EM

5V Supply, Reset and Supervision

5.4

Electrical Characteristics 5V Supply, Reset and Supervision

Table 4

Electrical Characteristics: 5V Supply, Reset and Supervision

V_S=13.5V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

5V Supply

Output Voltage

V_V5DD

4.9

5

5.1

V

0 mA < I_V5DD

<

5.1.1

250mA

6V < V_S< 18V

_V5DD= 0V

Output Current Limitation

Load Regulation

I_V5DD

250

–

650

50

mA

mV

V

5.1.2

5.1.3

ΔV_{V5DD, Lo}

1 mA < I_V5DD<

250mA

Line Regulation

ΔV_{V5DD, Li}

–

10

–

mV

dB

I

_V5DD= 1mA

5.1.4

5.1.5

10V < V_S< 18V

Power Supply Rejection

PSRR

60

f = 100Hz

V

_{S, ripple}= 0.5

Vpp¹⁾

1)

Output Capacitor

C_V5DD

470

–

nF

Ω

5.1.6

5.1.7

5.1.8

1)

Output Capacitor ESR

Current Consumption

ESR(C_V5DD) –

–

10

8

I_VS

–

5.5

mA

I_V5DD= 0mA, all

channels and K-

Line off

Low Drop Voltage

V_V5DD

4.8

–

5

V

I

_V5DD= 1mA

V_S=5V

_V5DD= 250mA

5.1.9

4.15

I

5.1.10

V_S=5V;

after device

ramp-up (V_S>9V)

Over Temperature Protection

Over Temperature Threshold T_OT

Over Temperature Hysteresis T_OT,Hys

Under Voltage Detection

1)

150

–

200

–

°C

5.2.1

5.2.2

20

V5DD Reset Threshold

V_RT

4.00

4.25

4.50

V

V_V5DDdecreasing 5.3.1

only at version

TLE8080EM

Reset Hysteresis

V_RH

V_RT

10

–

150

3.9

mV

V

5.3.2

V5DD Reset Threshold for

TLE8080-2EM

3.4

3.65

V_V5DDdecreasing 5.3.3

only at version

TLE8080-2EM

Data Sheet

12

Rev. 1.1, 2012-10-19

TLE8080EM

5V Supply, Reset and Supervision

Table 4

Electrical Characteristics: 5V Supply, Reset and Supervision (cont’d)

V_S=13.5V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Power On Reset

Power On Reset Delay Time t_RD

10

30

10

15

40

15

20

50

20

ms

μs

only at version

TLE8080EM

5.4.1

5.4.2

5.4.3

only at version

TLE8080-2EM

Reset Reaction Time

Reset Output NRO

Low Level Output Voltage

Watchdog

t_RR

V_NRO,L

–

1.1

V

I

_NRO= 1mA

5.5.1

Watchdog Period

t_WP

t_WR

50

60

70

ms

5.6.1

5.6.2

Watchdog Reset Time

120

240

360

μs

Input Characteristics WD_DIS

Low Level Input Voltage

High Level Input Voltage

Pull Down Current

Hysteresis

V_{WD_DIS,L}

–

1

V

5.7.1

5.7.2

5.7.3

5.7.4

5.7.5

V_{WD_DIS,H}

I_{WD_DIS,pd}

2

–

V

20

2.4

50

–

100

–

μA

mV

at V_IN= 5V

at V_IN= 0.6V

V_{WD_DIS,Hys}30

250

1) Not subject to production test, specified by design

Data Sheet

13

Rev. 1.1, 2012-10-19

TLE8080EM

Power Stages

6

Power Stages

6.1

Low Side Switches

The power stages are built by N-channel power MOSFET transistors. The channels are universal multi channel

switches, but are mostly suitable to be used in engine management systems. Within an engine management

system, the best fit of the channels to the typical loads is:

•

Channel 1 and 3 for injector valves or similar sized solenoids with a maximum operation current requirement

of 2.6A

•

Channel 2 for malfunction indication lamps or other resistive loads with a maximum current requirement of 3A

Channel 4 and 5 for relays or other inductive loads with a maximum current requirement of 350mA

The channels are switched off while reset is active (pin NRO is low). After an power on reset the channels will be

switched on with a positive edge at IN1 respectively IN3 or with a switch on command over SPI.

V_bat

L,

R_L

R

I_D

OUT

V_DS

V

DScl

GND

Channel1, 3, 4, 5

Channel2

Figure 6

Low Side Switches

In Table 5 the control concept, typical loads, the implemented protection and monitor functions are illustrated.

Table 5

Overview Diagnosis Function

Channel Control

Recommended

Load

Over

Temperature

Over Current

Open

Load/Short

to GND

1

2

Pin IN1

Injector Valve

x

Latch¹⁾

x

SPI CMD Register MIL (max. 3W)

Bit 0

repetitive switching;

off time t_oc,off

–

1)

3

4

Pin IN3

Valve

x

Latch¹⁾

x

SPI CMD Register Relay

Bit 1

one

temperature

sensor for

channel4and

channel 5

5

SPI CMD Register Relay

Bit 2

one

Latch¹⁾

x

temperature

sensor for

channel4and

channel 5

1)Reset behavior of the diagnosis bits see Chapter 8.2

Data Sheet

14

Rev. 1.1, 2012-10-19

TLE8080EM

Power Stages

In overcurrent condition the affected channel will be switched off. There are two different implementations for

switching on again after an over current event.

For channels 1, 3, 4 and 5 the switch off state is latched. The input pins IN1, IN3 must be set to low to reset the

latch before the channel can be switched on again.

For channels 4 and 5 the over current status is reset with a write command to the CMD register. The switching

state is according to the status of bit 1 and 2.

Channel 2 will be switched off and after t_{oc_off}= 5ms typically the channel will be switched on again automatically.

The result is repetitive switching with a fixed off time of t_oc,off. The overcurrent status of channel 2 is internally

latched. For releasing the over current diagnosis bit after over current condition, channel 2 must stay switched on

for at least t_oc,St

.

The bits 0 to 4 in the Stat register reflect the actual switching status of the channels.

For detailed description see Chapter 8.2.2.

All the channels are protected from over temperature. In an overtemperature situation the affected channel will be

switched off. The channel will restart operation if the junction temperature decreases by thermal shutdown

hysteresis T_OT,Hys. Channels 4 and 5 are using a common temperature sensor. Therefore, the two channels are

switched together during over temperature.

For channels 1, 3, 4 and 5 an open load/short to GND in off detection with a pull down current source (active in

off) and a comparator is implemented. In case of switch off and the output voltage is below the open load detection

threshold (V_outx< V_ol,th), the open load in off timer is started. After the open load in off delay time t_ol,d, the open

load is detected (timing see Figure 9 and Figure 10).

The diagnosis status of the channels is monitored in the SPI Diagnosis Register DIAG (see Chapter 8.2).

Data Sheet

15

Rev. 1.1, 2012-10-19

TLE8080EM

Power Stages

6.2

Electrical Characteristics Low Side Switches

Table 6

Electrical Characteristics: Power Stage

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Output Channel 1 and 3

On Resistance

R_{OUTx_on}

–

0.6

0.7

Ω

I

_{OUTx_nom}= 1.3A; 6.1.1

T_j= 150°C

_OUTx= 0.02A

Output Clamping Voltage

V_{OUTx_cl}

I_{OUTx_oc}

30

35

–

40

5

V

A

I

6.1.2

6.1.3

Over-current Switch Off

Threshold

2.6

Over-current Switch Off Filter t_oc,f

0.5

–

3

μs

6.1.4

Time

Over Temperature Switch Off T_OT

Over Temperature Hysteresis T_OT,Hys

150

–

200

–

°C

V

6.1.5

6.1.6

6.1.7

20

2.8

Open Load in Off Detection V_ol,th

2

3.2

Threshold

Open Load in Off Pull Down I_ol

Diagnosis Current

50

100

–

100

–

150

200

1

μA

μs

V

_OUTx= 13.5V

6.1.8

6.1.9

6.1.10

Open Load in Off Diagnosis t_ol,d

Delay Time

Turn On Delay Time

Turn Off Delay Time

Turn On Time

t_d,ON

0.25

V_OUTx= 13.5V

I

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

T_j= 150°C²⁾

t_d,OFF

–

0.9

0.6

–

1.5

1.2

3

μs

μA

V

I

6.1.11

6.1.12

6.1.13

6.1.14

t_s,ON

V

I

Turn Off Time

t_s,OFF

V

I

Output Leakage Current in

Off Mode

I_{OUTx_off}

V

Output Channel 2

On Resistance

R_{OUTx_on}

I_{OUTx_oc}

–

1.1

–

1.2

6.5

3

Ω

I

_{OUTx_nom}= 0.3A; 6.2.1

T_j= 150°C

Over-current Switch Off

Threshold

3

A

6.2.2

6.2.3

6.2.4

Over-current Switch Off Filter t_oc,f

Time

0.5

3

–

μs

ms

Over-current Switch Off Time t_oc,off

–

8

Data Sheet

16

Rev. 1.1, 2012-10-19

TLE8080EM

Power Stages

Table 6

Electrical Characteristics: Power Stage (cont’d)

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified).

Parameter

Symbol

Values

Typ.

–

Unit Note /

Test Condition

Number

Min.

1

Max.

12

Over-current Status Time

t_oc,St

ms

°C

μs

6.2.5

6.2.6

6.2.7

6.2.8

Over Temperature Switch Off T_OT

Over Temperature Hysteresis T_OT,Hys

150

–

200

–

20

Turn On Delay Time

Turn Off Delay Time

Turn On Time

t_d,ON

–

0.6

1.2

V

_OUTx= 13.5V

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 1.3A,

resistive load¹⁾

_OUTx= 13.5V

T_j= 150°C

I

t_d,OFF

–

0.7

0.4

–

1.5

1

μs

μA

V

I

6.2.9

t_s,ON

V

I

6.2.10

6.2.11

6.2.12

Turn Off Time

t_s,OFF

1

V

I

Output Leakage Current in

Off Mode

I_{OUTx_off}

3

V

Output Channel 4 and 5

On Resistance

R_{OUTx_on}

–

3.3

3.6

Ω

I

_{OUTx_nom}= 0.3A; 6.3.1

T_j= 150°C

_OUTx= 0.02A

Output Clamping Voltage

V_{OUTx_cl}

I_{OUTx_oc}

30

35

–

40

V

I

6.3.2

6.3.3

Over-current Switch Off

Threshold

350

600

mA

Over-current Switch Off Filter t_oc,f

0.8

–

2.4

μs

6.3.4

Time

Over Temperature Switch Off T_OT

Over Temperature Hysteresis T_OT,Hys

150

–

200

–

°C

V

6.3.5

6.3.6

6.3.7

20

2.8

Open Load in Off Detection V_ol,th

2

3.2

Threshold

Open Load in Off Pull Down I_ol

Diagnosis Current

50

100

–

100

–

150

200

1.2

μA

μs

V

_OUTx= 13.5V

6.3.8

6.3.9

6.3.10

Open Load in Off Diagnosis t_ol,d

Delay Time

Turn On Delay Time

t_d,ON

0.5

V_OUTx= 13.5V

I

_OUTx= 0.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 0.3A,

resistive load¹⁾

Turn Off Delay Time

t_d,OFF

–

0.7

1.5

μs

V

I

6.3.11

Data Sheet

17

Rev. 1.1, 2012-10-19

TLE8080EM

Power Stages

Table 6

Electrical Characteristics: Power Stage (cont’d)

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified).

Parameter

Symbol

Values

Typ.

0.1

Unit Note /

Test Condition

Number

Min.

Max.

Turn On Time

t_s,ON

–

0.8

μs

μA

V

I

_OUTx= 13.5V

_OUTx= 0.3A,

resistive load¹⁾

_OUTx= 13.5V

_OUTx= 0.3A,

resistive load¹⁾

6.3.12

Turn Off Time

t_s,OFF

–

0.1

–

0.8

2

V

I

6.3.13

6.3.14

Output Leakage Current in

Off Mode

I_{OUTx_off}

V_OUTx= 13.5V

T_j= 150°C²⁾

Input Characteristic IN1 and IN3

Low Level Input Voltage

High Level Input Voltage

Input Voltage Hysteresis

Pull Down Current

V_IN,L

–

1

V

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

V_IN,H

V_IN,Hys

I_IN,PD

2

–

V

50

20

2.4

110

50

–

250

100

–

mV

μA

V_IN= 5V

Pull Down Current

V_IN= 0.6V

1)definition of timing see Figure 7 or Figure 8

2) in OFF mode open load diagnosis pull down current active

V_INx

50%

V_OUTx

t

V_BATT

80%

20%

t

t_d,ON

t_{s, ON}

t_d,OFF

t_{s, OFF}

Figure 7

Timing Low Side Switches Channel 1 and 3

Data Sheet

18

Rev. 1.1, 2012-10-19

TLE8080EM

Power Stages

V_CSN

50%

t

V_OUTx

V_BATT

80%

20%

t

t_d,OFF

t_{s, OFF}

t_d,ON

t_{s, ON}

Figure 8

Timing Low Side Switches Channel 2,4 and 5

V_INx

50%

t

V_OUTx

open

V_BATT

V_ol.th

t_ol.d

CHx_OL

Figure 9

Timing Open Load/Short to GND in Off Detection Channel 1 and 3

Data Sheet

19

Rev. 1.1, 2012-10-19

TLE8080EM

Power Stages

V_CSN

50%

t

V_OUTx

open

V_BATT

V_ol.th

t

t_ol.d

CHx_OL

t

Figure 10 Timing Open Load/Short to GND in Off Detection Channel 2,4 and 5

Data Sheet

20

Rev. 1.1, 2012-10-19

TLE8080EM

Variable Reluctance Sensor ( VRS ) Interface

7

Variable Reluctance Sensor ( VRS ) Interface

The variable reluctance (VR) sensor interface converts an output signal of a VR sensor into a logic level signal

suited for µC 5V input ports. The voltage difference between the two input pins, VR_IN1 and VR_IN2, which are

connected to the two output pins of the VR sensor, is detected and the output pin VR_OUT is switched depending

on the sign of the voltage difference ( see Figure 12 )The amplitude of the VR sensor signal is limited by an internal

clamping circuit to avoid damage of the device due to over voltage caused by the VR sensor signal.

VR_IN1

Select Load

Clamp

2,5V

&

VR_OUT

Detection

Buffer

Load

VR_IN2

Select Threshold

Figure 11 VR Sensor Interface Block Diagram

Data Sheet

21

Rev. 1.1, 2012-10-19

TLE8080EM

Variable Reluctance Sensor ( VRS ) Interface

7.1

Electrical Characteristics VR Sensor Interface

Table 7

Electrical Characteristics: VR Sensor Interface

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Input Characteristics:

positive VR Sensor Interface V_{VR,th_pos}

Detection Threshold

-30

-80

0

30

mV

7.1.1

7.1.2

negative VR Sensor Interface V_{VR,th_neg}

Detection Threshold

-50

-20

CMD Register:

VR_T[1:0] = “00”

Reset State

-130

-550

-1.1

30

-100

-500

-1

-70

mV

V

CMD Register:

VR_T[1:0] = “01”

7.1.3

7.1.4

7.1.5

7.1.6

-450

-0.9

120

CMD Register:

VR_T[1:0] = “10”

CMD Register:

VR_T[1:0] = “11”

VR Sensor Interface Load

Selection

R_VR,Load

75

kΩ

T_j= 25°C;

CMD Register:

VR_L[1:0] = “00”

Reset State

90

60

kΩ

T_j= -40°C;

CMD Register:

VR_L[1:0] = “00”

Reset State

T_j= 150°C;

CMD Register:

VR_L[1:0] = “00”

Reset State

3

4.5

2.2

1.2

–

8

kΩ

mA

V

CMD Register:

VR_L[1:0] = “01”

7.1.7

7.1.8

7.1.9

7.1.10

1.5

0.7

–

3.3

1.9

±50

±3.5

CMD Register:

VR_L[1:0] = “10”

CMD Register:

VR_L[1:0] = “11”

VR Sensor Interface Input

Clamping Current

I_VR,clamp

V_VR,clamp

VR Sensor Interface Input

Clamping Voltage

±2.5

±3

I_VR,clamp= ±50mA 7.1.11

Output Characteristics:

Low Level Output Voltage

High Level Output Voltage

V_{VR_OUT,L}

V_{VR_OUT,H}

–

0.3

–

V

I_{VR_OUT}= 100μA 7.2.1

I_{VR_OUT}= -100μA 7.2.2

V5DD-

0.3

Data Sheet

22

Rev. 1.1, 2012-10-19

TLE8080EM

Variable Reluctance Sensor ( VRS ) Interface

Table 7

Electrical Characteristics: VR Sensor Interface (cont’d)

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Transfer Characteristics:

Delay Time Input to VR_OUT t_dr

falling edge

1

1.5

2.5

μs

7.3.1

7.3.2

Delay Time Input to VR_OUT t_df

rising edge

V_{VR_IN1 –}

VR_IN2

V_{VRT h_pos}=0V

V_{VRT h_neg}

t

t_dr

t_df

V_{VR_OUT}

50%

t

Figure 12 Timing Characteristics of the VR Sensor Interface

Data Sheet

23

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

8

Serial Peripheral Interface (SPI)

The diagnosis and control interface is based on a serial peripheral interface (SPI).

The SPI is a 16 bit full duplex synchronous serial slave interface, which uses four lines: SI, SO, SCLK and CSN.

8.1

SPI Signal Description

CSN - Chip Select:

The system micro controller selects the IC by means of the CSN pin. Whenever the pin is in low state, data transfer

can take place. As long as CSN is in high state, all signals at the SCLK and SI pins are ignored and SO is forced

to high impedance.

CSN - High to Low Transition:

SO changes from high impedance to high or low state depending on the Status Flag (see Chapter 8.2).

CSN - Low to High Transition:

End of transmission, the validation check of the communication is done (number of bits and valid command) and

valid commands are executed.

SCLK - Serial Clock:

This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling

edge of SCLK while the serial output (SO) shifts information out on the rising edge of the serial clock. It is essential

that the SCLK pin is in low state whenever chip select CSN makes any transition.

SI - Serial Input:

Serial input data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read on the falling

edge of SCLK. Please refer to Section 8.2 for further information.

SO - Serial Output:

Data is shifted out serially at this pin, the MSB first. SO is in high impedance until the CSN pin goes to low. The

output level before the first rising edge of SCLK depends on the status flag. New data will appear at the SO pin

following the rising edge of SCLK. Please refer to Section 8.2 for further information.

8.2

SPI Protocol

The principle of the SPI communication is shown in Figure 13. The message from the micro controller must be

sent MSB first. The data from the SO pin is sent MSB first. The TLE8080EM samples data from the SI pin on the

falling edge of SCLK and shifts data out of the SO pin on the rising edge of SCLK. Each access must be terminated

by a rising edge of CSN.

All SPI messages must be exactly 16-bits long, otherwise the SPI message is discarded.

There is a one message delay in the response to each message (i.e. the response for message N will be returned

during message N+1).

The SPI protocol of the TLE8080EM provides three registers. The control register, the diagnosis, and the status

register. The control register contains the set up bits for the VR sensor interface and the control bits of channels

2, 4 and 5. The diagnosis register contains the diagnosis bits of the five low side switches. The status register

contains the status bits of the five low side switches, the watchdog status bit, and the watchdog time out bit. After

power-on reset, all register bits are set to reset state (see Chapter 8.2.1).

Data Sheet

24

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

There are four ways of valid access:

•

Write access to the command register: the answer is 1 for the R/W bit, 00 for the address and the content of

the register

Read access to the command register: the answer is 0 for the R/W bit, 00 for the address and the content of

the register

Read access to the diagnosis register: the answer is 0 for the R/W bit, 01 for the address and the content of

the register

Read access to the status register: the answer is 0 for the R/W bit, 10 for the address and the content of the

register

Any other access is recognized as an invalid message.

Status Flag Indication: after the falling edge of CSN and before the first rising edge of SCLK, the level of the SO

indicates the status of the diagnosis register:

•

SO = “0”: no error condition detected; all diagnosis register bits are “0”

SO = “1”: one or more error conditions are detected; one or more diagnosis register bits are “1”

With this feature during every SPI communication a check of the diagnosis status can be done without additional

read access of the diagnosis register.

CSN

time

)

clock

1

clock

2

clock

3

clock

15

clock

16

don’t care

SCLK

SI

*

time

Bit15

MSB

Bit0

LSB

don’t care

Bit14

Bit13

Bit1

don’t care

time

tristate

Bit 15

MSB

Bit 0

LSB

tristate

Status

Flag

Bit14

Bit13

Bit1

time

SO

⁾active clock edge for reading data at SI

*

Figure 13 SPI Protocol

SPI Answers:

•

during power on reset: SPI commands are ignored, SO is always low

after power on reset: the content of the command register is transmitted with the next SPI transmission

during watchdog reset: SPI commands are ignored, SO has the value of the status flag

after watchdog overflow: the content of the status register is transmitted with the first SPI transmission after

the low to high transition of NRO

•

after a read or write command: the content of the selected register is transmitted with the next SPI transmission

after an invalid communication: the content of the diagnosis register is transmitted with the next SPI

transmission

Data Sheet

25

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

8.2.1

SPI Register

Overview

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

AD1

AD0

Field

Bits

Type

Description

AD1:AD0]

[14:13]

w

Address Bits:

00_BControl Register

01_BDiagnosis Register

10_BStatus Register

R/W

15

w

Read - Write Bit:

0_BRead Access

1_BWrite Access

CMD Register

Command Register (Identifier x00x xxxx xxxx xxxx_B)Reset Value: 0_H

15

R/W AD1 AD0 VR_T1 VR_T0 VR_L1 VR_L0

rw rw rw rw

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CTR5 CTR4 CTR2

rw rw rw

Field

Bits

Type

Description

CTR2

0

rw

Control Bit Channel 2:

0_BChannel 2 is switched off (Reset State)

1_BChannel 2 is switched on

CTR4

1

2

Control Bit Channel 4:

0_BChannel 4 is switched off (Reset State)

1_BChannel 4 is switched on

CTR5

Control Bit Channel 5:

0_BChannel 5 is switched off (Reset State)

1_BChannel 5 is switched on

VR_L1: VR_L0

[10:9]

Load Register of VR Interface:

( c.f. VR Sensor Interface Load Selection )

00_BR_Load= 75kΩ (Reset State)

01_BR_Load= 4.5kΩ

10_BR_Load= 2.2kΩ

11_BR_Load= 1.2kΩ

Data Sheet

26

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

Field

Bits

Type

Description

VR_T1: VR_T0

[12:11]

rw

Threshold Register of VR Interface:

00_B-50mV (Reset State)

01_B−100mV

10_B−500mV

11_B−1V

Diag Register

Diagnosis Register (Identifier x01x xxxx xxxx xxxx_B)Reset Value: 0_H

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

CH45_ CH5_ CH5_ CH4_ CH4_ CH3_ CH3_ CH3_ CH2_ CH2_ CH1_ CH1_ CH1_

R/W AD1 AD0

OT

OC

OL

OC

OL

OT

OC

OL

OT

OC

OT

OC

OL

r

Field

CH1_OL

Bits

Type

Description

Open Load Diagnosis Bit of Channel 1:

0_Bno open load in off detected (Reset State)

1_Bopen load in off detected

0

r

CH1_OC

CH1_OT

CH2_OC

CH2_OT

CH3_OL

CH3_OC

CH3_OT

CH4_OL

CH4_OC

1

2

3

4

5

6

7

8

9

Over Current Diagnosis Bit of Channel 1:

0_Bno over current detected (Reset State)

1_Bover current detected

Over Temperature Diagnosis Bit of Channel 1:

0_Bno over temperature detected (Reset State)

1_Bover temperature detected

Over Current Diagnosis Bit of Channel 2:

0_Bno over current detected (Reset State)

1_Bover current detected

Over Temperature Diagnosis Bit of Channel 2:

0_Bno over temperature detected (Reset State)

1_Bover temperature detected

Open Load Diagnosis Bit of Channel 3:

0_Bno open load in off detected (Reset State)

1_Bopen load in off detected

Over Current Diagnosis Bit of Channel 3:

0_Bno over current detected (Reset State)

1_Bover current detected

Over Temperature Diagnosis Bit of Channel 3:

0_Bno over temperature detected (Reset State)

1_Bover temperature detected

Open Load Diagnosis Bit of Channel 4:

0_Bno open load in off detected (Reset State)

1_Bopen load in off detected

Over Current Diagnosis Bit of Channel 4:

0_Bno over current detected (Reset State)

1_Bover current detected

Data Sheet

27

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

Field

Bits

Type

Description

CH5_OL

10

r

Open Load Diagnosis Bit of Channel 5:

0_Bno open load in off detected (Reset State)

1_Bopen load in off detected

CH5_OC

11

12

r

Over Current Diagnosis Bit of Channel 5:

0_Bno over current detected (Reset State)

1_Bover current detected

CH45_OT

Over Temperature Diagnosis Bit of Channel 4 and 5:

0_Bno over temperature detected (Reset State)

1_Bover temperature detected

Stat Register

Status Register (Identifier x10x xxxx xxxx xxxx_B)Reset Value: 0_H

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

R/W AD1 AD0 WD_DIS WD_TO

ST5

ST4

ST3

ST2

ST1

r

Field

ST1

Bits

Type

Description

Status Bit Channel 1:

0

r

0_BChannel 1 is switched off (Reset State)

1_BChannel 1 is switched on

ST2

1

r

Status Bit Channel 2:

0_BChannel 2 is switched off (Reset State)

1_BChannel 2 is switched on

ST3

2

Status Bit Channel 3:

0_BChannel 3 is switched off (Reset State)

1_BChannel 3 is switched on

ST4

3

Status Bit Channel 4:

0_BChannel 4 is switched off (Reset State)

1_BChannel 4 is switched on

ST5

4

Status Bit Channel 5:

0_BChannel 5 is switched off (Reset State)

1_BChannel 5 is switched on

WD_TO

WD_DIS

11

12

Watchdog Time Out Bit:

0_Bno watchdog time out

1_Bwatchdog time out occurred

Watchdog Status Bit:

0_BWatchdog enabled (V_{WD_DIS}= 0V)

1_BWatchdog disabled (V_{WD_DIS}= 5V)

8.2.2

Set and Reset of Diagnosis Register Bits

Set of the over current diagnosis bits of channels 1, 3, 4 and 5:

The over current diagnosis bits of channels 1, 3, 4 and 5 are set asynchronously of the internal clock with the

output signal of the detection circuit (details see Chapter 6.1).

Data Sheet

28

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

Reset of the over current diagnosis bits of channels 1 and 3:

•

Diagnosis register was read out:

– input pin INx remains high: no reset of the over current diagnosis bit, the channel remains switched off

– input pin INx transition from high to low: the over current diagnosis bit is reset, the channel could be switched

on again

•

Diagnosis register was not read out

– channel remains switched off and no reset of the over current diagnosis bit is done

– input pin INx is low: with the next read access of the diagnosis register the diagnosis bits are reset

Reset of the over current diagnosis bits of channels 4 and 5:

•

Diagnosis register was not read out

– channel remains switched off and no reset of the over current diagnosis bit is done

Diagnosis register was read out:

•

– SPI command register write command is not sent: no reset of the over current diagnosis bit, the channel

remains switched off

– SPI command register write command is sent: the over current diagnosis bit is reset, the channel will be

switched according the status of the control bit

Set and Reset of the over current diagnosis bit of channel 2:

The over current diagnosis register bit for channel 2 is set asynchronously of the internal clock with the output

signal of the detection circuit. With this signal the output is switched off and the counter for the off time t_oc,offof the

repetitive switching cycle starts. After t_oc,offthe channel will be switched on again. With an remaining over current

condition the channel will be switched on repetitively. This internal overcurrent status of the channel is latched

internally. The internal over current status is reset in two situations.

•

over current condition exists no longer: the internal over current status is reset after the time t_oc,St

over current condition remains and the channel is switched off: the internal over current status is reset after

the time t_oc,off

The reset of the over current diagnosis register bit for channel 2 is related to the internal over current status. In

Figure 14 and Figure 15 the behavior of the diagnosis with temporary and permanent over current condition is

drawn.

Data Sheet

29

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

Over Current

No Over Current

Cont Reg.

Bit 1

t_oc,f

I_OUT2

I_D,oc

t_oc,off

t_oc,St

Internal Over

Current Status

Diag Reg.

Bit 3

SPI Diag Reg.

Read Out

SPI Diag Reg.

Read Out

SPI Diag Reg.

Read Out

Figure 14 Behavior of diagnosis with temporary over current condition at channel 2

Permanent Over Current

Cont Reg.

Bit 1

t_oc,f

I_OUT2

I_D,oc

t_oc,off

Internal Over

Current Status

Diag Reg.

Bit 3

SPI Diag Reg.

Read Out

SPI Diag SPI Diag

Reg. Reg.

Read Out Read Out

Figure 15 Behavior if diagnosis with permanent over current condition at channel 2

Reset of the over temperature diagnosis bits:

Data Sheet

30

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

The over temperature diagnosis bits will be reset with read access of the diagnosis register if no over temperature

condition is detected.

Reset of the open load in off diagnosis bits:

The open load in off diagnosis bits will be reset with read access of the diagnosis register if no open load condition

is detected.

Data Sheet

31

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

8.3

Electrical Characteristics SPI

Table 8

Electrical Characteristics: SPI

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

Max.

Input Characteristics (CSN, SCLK, SI):

Low Level Input Voltage

High Level Input Voltage

Hysteresis

V_x,L

–

1

V

8.1.1

8.1.2

V_x,H

V_x,Hys

I_x,pu

I_x.pu

2

–

V

50

-25

250

-100

–

mV

μA

Pull Up Current CSN

-50

–

at V_IN= 0V

8.1.3

8.1.4

at V_IN= V_V5DD

-

0.6V

Pull Down Current SCLK, SI I_x,pu

Pull Down Current SCLK, SI I_x.pu

Output Characteristics (SO):

20

50

–

100

–

μA

at V_IN= V_V5DD

at V_IN= 0.6V

8.1.5

8.1.6

2.4

Low Level Output Voltage

High Level Output Voltage

V_So,L

–

0.4

–

V

I_x= 100μA

I_x= -100μA

8.2.1

8.2.2

V_SO,H

V5DD-

0.4

Output High Impedance

Leakage Current

I_SO,TRI

-3

–

3

μA

0V < V_SO< 5V

8.2.3

Timings:

Lead Time

t₁

t₂

t₃

210

75

–

ns

CSN falling to

SCLK rising

8.3.1

8.3.2

8.3.3

Lag Time

SCLK falling to

CSN rising

CSN High Time

550

CSN rising to

CSN falling

Period of SCLK

t₄

t₅

200

10

–

ns

8.3.4

8.3.5

SCLK to CSN Set Up Time

SCLK falling to

CSN falling

SCLK Low Time

t₇

t₈

60

15

–

ns

8.3.6

8.3.7

CSN to SCLK Hold Time

CSN rising to

SCLK rising

SI Set Up Time

SI Hold Up Time

SO Enable Time

SO Valid Time

t₉

30

–

ns

SI set up time to 8.3.8

SCLK falling

t₁₀

t₁₁

t₁₂

–

SI holdup time

8.3.9

after SCLK falling

165

120

CSN falling to SO 8.3.10

active

–

SO data valid

8.3.11

after SCLK rising

Data Sheet

32

Rev. 1.1, 2012-10-19

TLE8080EM

Serial Peripheral Interface (SPI)

Table 8

Electrical Characteristics: SPI (cont’d)

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified).

Parameter

Symbol

Values

Typ.

–

Unit

Note /

Test Condition

Number

Min.

Max.

SO Disable Time

t₁₃

–

165

ns

SO high

8.3.12

impedance after

CSN rising

Number of Clock Pulses while

CSN = low

16

–

16

75

pulses

ns

8.3.13

8.3.14

8.3.15

SO Rise Time

t_{SO_rise}

t_{SO_fall}

20% to 80%,

C

_load=1.6pF

SO Fall Time

–

ns

80% to 20%

C

_load=1.6pF

t₁

t₂

t₃

CSN

time

t₄

t₅

t₆

t₇

t₈

clock

1

clock

2

clock

3

clock

15

clock

16

don’t care

SCLK

SI

time

t₉

t₁₀

Bit15

MSB

Bit0

LSB

don’t care

Bit14

Bit13

Bit1

don’t care

time

t₁₁

t₁₂

t₁₃

tristate

Bit 15

MSB

Bit 0

LSB

tristate

Status

Flag

Bit14

Bit13

Bit1

time

SO

Figure 16 SPI Timing Diagram

Data Sheet

33

Rev. 1.1, 2012-10-19

TLE8080EM

K-Line

9

K-Line

9.1

K-Line

The K-Line module is a serial link bus interface device designed to provide bi-directional half-duplex

communication interfacing. It is designed to interface vehicles via the special ISO K-Line and meets the ISO

standard 9141. The device’s K-Line bus driver’s output is protected against bus shorts.

VS

RX

KIO

V5DD

TX

Driver &

Protection

Figure 17 K-Line Block Diagram

Data Sheet

33

Rev. 1.1, 2012-10-19

TLE8080EM

K-Line

9.2

Electrical Characteristics K-Line

Table 9

Electrical Characteristics: K-Line

V_S=13.5V, T_j= -40°C to +150°C: All voltages with respect to ground.

Positive current flowing into pin (unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Number

Min.

Max.

Output RX

Low Level Output Voltage

High Level Output Voltage

V_RX,L

V_RX,H

–

0,4

–

V

I

_RX= 100μA

_RX= -100μA

9.1.1

9.1.2

V5DD-

0.4

Input TX

Low Level Input Voltage

High Level Input Voltage

Hysteresis

V_TX,L

V_TX,H

V_TX,Hys

I_{PU_L}

–

1

V

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

3.2

280

-70

-30

–

V

500

-100

–

700

-150

–

mV

μA

Pull Up Current

at V_TX= 0V

I_{PU_L}

at V_TX= V_V5DD-

0.6V

K-Line Bus Driver Input/Output KIO

Low Level Output Voltage

V_KIO,O,L

–

1.4

V

TX = low,

9.3.1

R

_KIO=480Ω

Current Limitation

Low Level Input Voltage

High Level Input Voltage

Hysteresis

I_KIO(lim)

V_KIO,I,L

V_KIO,I,H

V_KIO,I,Hys

40

–

140

mA

9.3.2

9.3.3

9.3.4

9.3.5

0.4*VS V

0.6*VS –

–

V

0.02

–

0.175

*VS

Pull Down Current

I_KIO,pd

5

10

15

μA

9.3.6

Transfer Characteristics

C

_RX= 25pF; R_KIO= 540Ω; C_KIO≤ 1.3nF

Receive Frequency

Transmit Frequency

f_KIO,rec

f_KIO,tran

–

500

100

0.5

kHz

μs

C_KIO= 0pF

9.4.1

9.4.2

9.4.3

–

Delay Time KIO -> RX rising t_drR

0.05

C_RX,load= 1.6pF

edge¹⁾

Delay Time KIO -> RX falling t_dfR

0.05

–

0.5

μs

9.4.4

edge¹⁾

Delay Time TX -> KIO rising t_drT

C_KIO,load= 1.6pF 9.4.5

C_KIO,load= 1.6pF 9.4.6

edge¹⁾²⁾

Delay Time TX -> KIO falling t_dfT

edge¹⁾

1) For definition see Figure 18

2) Not subject of production test, behavior defined by external devices

Data Sheet

34

Rev. 1.1, 2012-10-19

TLE8080EM

K-Line

V_TxD

V_V5DD

0.5*V_V5DD

t

V_bus

t_dfT

t_drT

V_S

0.7*V_S

0.3*V_S

t

V_RxD

t_drR

t_dfR

V_V5DD

0.5*V_V5DD

Figure 18 K-Line Transfer Characteristics

Data Sheet

35

Rev. 1.1, 2012-10-19

TLE8080EM

Package Outlines

10

Package Outlines

0.35 x 45˚

2x

1)

0.1

3.9

0.1 C D

0.08

Seating Plane

C

0.65

2)

0.05

0.2

0.25

6

M

0.2

D

0.2

C A-B D 24x

D

Bottom View

A

24

1

12

13

1

12

24

13

B

0.25

6.4

0.1 C A-B 2x

0.1

8.65

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Does not include dambar protrusion of 0.13 max.

PG-SSOP-24-4-PO V01

Figure 19 PG-SSOP24

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products, and to be compliant with

government regulations, the device is available as a green product. Green products are RoHS-Compliant (i.e

Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

36

Rev. 1.1, 2012-10-19

TLE8080EM

Revision History

11

Revision History

Revision

1.0

Date

Changes

2012-09-12 Data sheet

1.1

2012-12-19 parameter 5.4.3, page 13 reset reaction time increased

Data Sheet

37

Rev. 1.1, 2012-10-19

Edition 2012-10-19

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.


型号：	TLE8080-3EM
厂家：	Infineon
描述：	It provides a compact and cost optimized solution for 1 cylinder combustion engine management systems It integrates a power supply, K-line, SPI control and diagnosis , variable reluctance sensor interface and power stages into one power interface integrated circuits and includes embedded protection functions. The TLE8080 represents the interface between micro controller and actuators. With its's featue set the TLE8080 can cover the requirements of a one cylinder motorcycle engine management system.
文件：	总39页 (文件大小：1422K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLE8080-3EM [INFINEON]

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