TLE8201RAUMA1 [INFINEON]
Consumer Circuit, CMOS, PDSO36, PLASTIC, SOP-36;
| 型号： | TLE8201RAUMA1 |
| 厂家： | 
Infineon |
| 描述： | Consumer Circuit, CMOS, PDSO36, PLASTIC, SOP-36 光电二极管 商用集成电路 |
| 文件： | 总45页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Door Module Power IC
TLE 8201R
Data Sheet Rev. 2.0
Features
• Full bridge (150mΩ) for main doorlock motor
• Two half-bridges (400mΩ) for deadbolt and mirror
position motor or mirror fold motor
• Two half-bridges (800mΩ) for mirror position
• High-side switch (100mΩ) for mirror defrost
• Four high-side switches (500mΩ) for 5W and 10W
lamps
• Current sense analog output with multiplex
• All outputs with short circuit protection and diagnosis
• Over-temperature protection with warning
• Open load diagnosis for all outputs
• Charge pump-Output for n-channel MOS-FET reverse-polarity protection
• Very low current consumption in sleep mode
• Standard 16-bit SPI for control and diagnosis
• Over-and Undervoltage Lockout
• Power-SO package with full-size heatslug for excellent low thermal resistance
Type
Ordering Code
Package/Shipment
TLE 8201R
-
PG-DSO-36-27
Functional Description
The TLE 8201R is an Application Specific Standard Product for automotive door-module
applications. It includes all the power stages necessary to drive the loads in a typical front
door application, i.e. central lock, deadlock or mirror fold, mirror position, mirror defrost
and 5W or 10W lamps, e.g for turn signal, courtesy/warning or control panel illumination.
It is designed as a monolithic circuit in Infineons mixed technology SPT which combines
bipolar and CMOS control circuitry with DMOS power devices.
Short circuit and over-temperature protection and a detailed diagnosis are in line with the
safety requirements of automotive applications. The current sense output allows to
improve the total system performance. The standard SPI interface saves microcontroller
I/O lines while still giving flexible control of the power stages and a detailed diagnosis.
Data Sheet Rev. 2.0
1
2006-06-07
TLE 8201R
Page
Table of Contents
1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
2.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
4
4.1
Block Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . 9
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sleep-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reverse Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register Address selection and Reset . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-Outputs 1-6 (Bridge Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-Output 7 (Mirror heater driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-Outputs 8 - 11 (Lamp drivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Protection and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Logic In- and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.7
4.7.1
5
6
Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Sheet Rev. 2.0
2
2006-06-07
TLE 8201R
Block Diagram
1
Block Diagram
Vs
GO CP
Charge-
pump
Vcc
OUT1
OUT2
OUT3
Biasing
RevPol
MOS driver
INH
CSN
CLK
Fault-
Detect
SPI
DI
DO
PWM1
PWM2
Logicand Latch
LogicIN
ISO
current
OUT4
OUT5
OUT6
sense MUX
OUT8
OUT9
OUT10
OUT11
OUT7
GND
Figure 1
Block Diagram
Data Sheet Rev. 2.0
3
2006-06-07
TLE 8201R
Pin Configuration
2
Pin Configuration
2.1
Pin Assignment
cooling tab
(GND)
GND 1
OUT5 2
36 GND
35 n.c.
34 OUT4
33 Vs
32 OUT7
3
4
OUT6
Vs
INH 5
6
7
31
30
PWM1
PWM2
OUT7
Vs
ISO 8
29 OUT8
28
27
9
Vcc
OUT9
CP
DO 10
CLK 11
CSN 12
DI 13
26 Vs
25 OUT10
24 OUT11
23 Vs
GO 14
Vs 15
22 OUT3
21 OUT2
20 OUT2
19 GND
OUT1 16
OUT1 17
GND 18
Figure 2
Pin Configuration PG-DSO-36-27
Data Sheet Rev. 2.0
4
2006-06-07
TLE 8201R
Pin Configuration
2.2
Pin
Pin Definitions and Functions
Symbol Function
cooling
tab
GND
Cooling tab, internally connected to GND; to reduce thermal
resistance place cooling areas and thermal vias on PCB.
1, 18,
GND
Ground; internally connected to cooling tab (heat slug).
19, 36
2
3
OUT5
OUT6
Power-Output of half-bridge 5; DMOS half-bridge
Power-Output of half-bridge 6; DMOS half-bridge.
4, 15, 23, Vs
26, 30, 33
Power supply; needs decoupling capacitors to GND. > 47µF
electrolytic in parallel with 100nF ceramic is recommended. All
Vs pins must be connected externally
5
6
7
INH
Inhibit; active low. Sets the device in sleep mode with low
current consumption when left open or pulled to LOW. Has an
internal pull down current source
PWM1
PWM2
Logic Input for direct power stage control; direct input to
control the high-side switches selected by the SPI xsel1 bits in
control register CtrlReg01
Logic Input for direct power stage control; direct input to
control the switches selected by the SPI xsel2 bits in control
register CtrlReg11
8
9
ISO
Vcc
Current sense output; Mirrors the current of the high-side
switch selected by the current sense multiplexer control bits ISx
Logic Supply Voltage; needs decoupling capacitors to GND
(pin 1). 10µF electrolytic in parallel with 10nF ceramic is
recommended
10
DO
Serial Data Output; Transfers data to the master when the chip
is selected by CSN=LOW. Data transmission is synchronized by
CLK, DO state is changed on the rising edge of CLK. The most
significant bit (MSB) is transferred first. The pin is tristated as
long as CSN=HIGH
11
12
CLK
CSN
Serial Data Clock Input; Receives the clock signal from the
master and clocks the SPI shift register. Has an internal pull
down current source
Serial Port Chip Select Not Input; SPI communication is
enabled by pulling CSN to LOW. CLK must be LOW during the
transition of CSN. The CSN-pin has an internal pull-up current
source
Data Sheet Rev. 2.0
5
2006-06-07
TLE 8201R
Pin Configuration
Pin
Symbol Function
13
DI
Serial Data Input; Receives serial data from the master when
the chip is selected by CSN=LOW. Data transmission is
synchronized by CLK. Data are accepted on the falling edge of
CLK. The LSB is transferred first. The DI-pin has an internal pull-
down current source.
14
GO
Gate Out; Charge pump output to drive the gate of external n-
channel MOS-FET for reverse polarity protection
16, 17
20, 21
22
OUT1
OUT2
OUT3
OUT11
OUT10
CP
Power-Output of half-bridge 1; DMOS half-bridge.
Power-Output of half-bridge 2; DMOS half-bridge.
Power-Output of half-bridge 3; DMOS half-bridge
Power Output of high-side switch 11; DMOS high-side switch
Power Output of high-side switch 10; DMOS high-side switch
24
25
27
Charge Pump; pin for optional external charge-pump reservoir
capacitor. 3.3 nF to Vs is recommended
28
OUT9
OUT8
OUT7
OUT4
n.c.
Power-Output of high-side switch 9; DMOS high-side switch
Power-Output of high-side switch 8; DMOS high-side switch
Power Output of high-side switch 7; DMOS high-side switch
Power-Output of half-bridge 4; DMOS half-bridge
Not connected
29
31, 32
34
35
Data Sheet Rev. 2.0
6
2006-06-07
TLE 8201R
Electrical Characteristics
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Pos. Parameter
Symbol Limit Values Unit Remarks
min.
-0.3
-0.3
-0.3
max.
40
3.1.1 Supply voltage
VS
VCC
V
V
V
–
–
–
3.1.2 Logic supply Voltage
5.5
3.1.3 Logic input- and output
Voltages
5.5
3.1.4 Voltage at GO-pin
3.1.5 Junction temperature
3.1.6 Storage temperature
VGO
Tj
Tstg
-16
-40
-50
–
VS + 5 V
–
–
–
150
150
4
°C
°C
3.1.7 ESD capability of power VESD
kV
Human Body Model
according to ANSI
EOS\ESD S5.1
standard (eqv. to
MIL STD 883D and
JEDEC JESD22-
A114)
stage output and VS
pins
3.1.8 ESD capability of logic VESD
–
2
kV
pins and ISO pin
Note: Stresses above the ones listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction
under fault conditions described in the data sheet. Fault conditions are
considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet Rev. 2.0
7
2006-06-07
TLE 8201R
Electrical Characteristics
3.2
Operating Range
Pos.
3.2.1
Parameter
Symbol Limit Values Unit
Remarks
min.
max.
Supply voltage
VS
5
40
V
Including over-
voltage lockout
3.2.2
3.2.3
Supply voltage
Supply voltage
VS
VS
5
8
20
20
V
V
Functional
Parameter
Specification
3.2.4
3.2.5
3.2.6
Logic supply voltage
SPI clock frequency
VCC
fCLK
4.75
–
5.5
2
V
–
–
–
MHz
°C
Junction temperature Tj
-40
150
Note: Within the functional range the IC operates as described in the circuit description.
The electrical characteristics are specified within the limit given at the table.
3.3
Thermal Resistance
Pos.
Parameter
Symbol Limit Values Unit Conditions
min.
max.
1.5
3.3.1
3.3.2
Junction pin
RthjC
RthjA
–
–
K/W –
Junction ambient
50
K/W minimal footprint
Data Sheet Rev. 2.0
8
2006-06-07
TLE 8201R
Block Description and Electrical Characteristics
4
Block Description and Electrical Characteristics
4.1
Power Supply
4.1.1
General
The TLE 8201R has two power supply inputs: All power drivers are connected to the
supply voltage VS which is connected to the automotive 12 V board-net. The internal
logic part is supplied by a separate Voltage VCC = 5 V.
The advantage of this system is that information stored in the logic remains intact in the
event of short-term failures in the supply voltage VS. The system can therefore continue
to operate after VS has recovered, without having to be reprogrammed.
A rising edge on VCC triggers an internal Power-On Reset (POR) to initialize the IC at
power-on. All data stored internally is deleted, and the outputs are switched to high-
impedance status (tristate).
4.1.2
Sleep-Mode
The TLE 8201R can be put in a low current-consumtion mode by setting the input INH
to LOW. The INH pin has an internal pull-down current source. In sleep-mode, all output
transistors are turned off and the SPI is not operating. When enabling the IC by setting
INH from L to H, a Power-On Reset is performed as described above.
4.1.3
Reverse Polarity
The TLE 8201R requires an external reverse polarity protection. The gate-driver
(charge-pump output) for an external n-channel logic-level MOS-FET is integrated. The
gate voltage is provided at pin GO which should be connected as shown in the
application diagram.
4.1.4
Electrical Characteristics
Electrical Characteristics
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
Current Consumption
4.1.1 Supply current
I
I
–
–
3.0
5
7.0
10
mA
–
S
4.1.2 Logic supply current
mA SPI not active
CC
Data Sheet Rev. 2.0
9
2006-06-07
TLE 8201R
Block Description and Electrical Characteristics
Electrical Characteristics
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
4.1.3 Quiescent current
I
I
–
–
–
2.5
0.2
3
5
1
6
µA
µA
µA
INH = L,
S
V = 14 V,
S
4.1.4 Logic quiescent current
4.1.5 Total quiescent current
CC
V
j
OUT7-11 = 0V;
T < 85 °C
I + I
S
cc
Charge Pump-output for Reverse-Polarity Protection FET (GO)
4.1.6 Gate-Voltage
V
V
-
5
–
8
V
I
GO = 50 µA
GO
S
4.1.7 Setup-time
t
I
–
–
–
–
1
5
ms
–
GO
4.1.8 Reverse leakage current
µA
V = 0 V
V
lkGO
S
GO = -14 V
Data Sheet Rev. 2.0
10
2006-06-07
TLE 8201R
4.2
Monitoring Functions
4.2.1
Power Supply Monitoring
The power supply Voltage VS is monitored for over- and under voltage.
• Under Voltage
If the supply voltage VS drops below the switch off voltage VUV OFF, all output
transistors are switched off and the power supply fail bit PSF is set. The error is not
latched, i.e. if VS rises again and reaches the switch on voltage VUV ON, the power
stages are restarted and the error bit is reset.
• Over Voltage
If the supply voltage VS rises above the switch off voltage VOV OFF, all output
transistors are switched off and the power supply fail bit (bit 7 of the SPI diagnosis
word) is set. The error is not latched, i.e. if VS falls again and reaches the switch on
voltage VOV ON, the power stages are restarted and the error is reset.
4.2.1.1 Characteristics Power Supply Monitoring
Electrical Characteristics
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
4.2.1 UV-Switch-ON voltage
4.2.2 UV-Switch-OFF voltage
4.2.3 UV-ON/OFF-Hysteresis
4.2.4 OV-Switch-OFF voltage
VUVON
VUVOFF 4.0
VUVHY
VOVOF 21
F
–
–
5.2
5.0
–
V
V
V
V
VS increasing
VS decreasing
VUVON - VUVOFF
–
–
0.25
–
25
VS increasing
4.2.5 OV-Switch-ON voltage
4.2.6 OV-ON/OFF-Hysteresis
VOVON 20
VOVHY 0.5
–
1
24
–
V
V
VS decreasing
VOVOFF
VOVON
-
Data Sheet Rev. 2.0
11
2006-06-07
TLE 8201R
4.2.2
Temperature Monitoring
Temperature sensors are integrated in the power stages. The temperature monitoring
circuit compares the measured temperature to the warning and shutdown thresholds. If
one or more temperature sensors reach the warning temperature, the temperature
warning bit TW is set to HIGH. This bit is not latched (i.e. if the temperature falls below
the warning threshold (with hysteresis), the TW bit is reset to LOW again).
If one or more temperature sensors reach the shut-down temperature, the outputs are
shut down as described in the next paragraph and the temperature shut-down bit TSD
is set to HIGH. The shutdown is latched (i.e. the output stages remain off and the TSD
bit set high until a SRR command is sent or a power-on reset is performed).
The power-stages are subdivided into two groups for over-temperature shut-down:
• Group1: OUT 1, OUT 2 and OUT 3
• Group2: OUT 4 to 11
If one or more temperature sensors within a group reaches the shutdown threshold, all
outputs within the group are switched off, while the other outputs continue normal
operation.
4.2.2.1 Characteristics Temperature Monitoring
Electrical Characteristics
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
4.2.7 Thermal warning junction
temperature1)
TjW
∆T
120
145
170
°C
K
–
–
–
–
–
–
4.2.8 Temperature warning
hysteresis1)
–
30
–
4.2.9 Thermal shutdown junction
temperature1)
TjSD
TjSO
∆T
150
120
–
175
–
200
170
–
°C
°C
K
4.2.10 Thermal switch-on junction
temperature1)
4.2.11 Temperature shutdown
hysteresis1)
4.2.12 Ratio of SD to W temperature1) TjSD
30
/
1.05 1.20
–
–
TjW
1)
Not subject to production test, specified by design
Data Sheet Rev. 2.0
12
2006-06-07
TLE 8201R
4.2.3
Current Sense
A current proportional to the output current that flows from the selected power output to
GND is provided at the ISO (I sense out) pin. The output selection is done via the SPI.
The sense current can be transformed into a voltage by an external sense resistor and
provided to an A/D converter input (see section application).
4.2.3.1 Characteristics Current Sense
Electrical Characteristics
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
HS1, HS2 (Register IS = 000, 001)
4.2.13 Output voltage range
4.2.14 Current Sense Ratio
VISO12
kILIS12
kILISacc
12
0
–
–
–
3
V
–
V
CC = 5 V
ILIS = IOUT/IISO
OUT > 3 A
2000
–
–
k
I
4.2.15 Current Sense accuracy
10
%
4.2.16 Matching
∆kILIS1 -6
2
1
2
%
∆kILIS12 = (kILIS1
- kILIS2) / kILIS1
HS3, HS4 (Register IS = 010, 011)
4.2.17 Output voltage range
4.2.18 Current Sense Ratio
4.2.19 Current Sense accuracy
HS7 (Register IS = 100)
VISO34
kILIS34
kILISacc
0
–
–
–
3
V
–
V
CC = 5 V
ILIS = IOUT/IISO
OUT > 1.5 A
1000
–
–
k
I
10
%
4.2.20 Output voltage range
4.2.21 Current Sense Ratio for HS7
4.2.22 Current Sense accuracy
VISO7
kILIS7
kILISacc
0
–
–
–
3
V
–
V
CC = 5 V
ILIS = IOUT/IISO
OUT > 2A
2000
–
–
k
I
10
%
Data Sheet Rev. 2.0
13
2006-06-07
TLE 8201R
4.3
SPI
4.3.1
General
The SPI is used for bidirectional communication with a control unit. The TLE 8201R acts
as SPI-slave and the control unit acts as SPI-master. The 16-bit control word is read via
the DI serial data input. The status word appears synchronously at the DO serial data
output. The communication is synchronized by the serial clock input CLK.
Standard data transfer timing is shown in Figure 3. The clock polarity is data valid on
falling edge. CLK must be low during CSN transition. The transfer is MSB first.
The transmission cycle begins when the chip is selected with the chip-select-not (CSN)
input (H to L). Then the data is clocked through the shift register. The transmission ends
when the CSN input changes from L to H and the word which has been read into the shift
register becomes the control word. The DO output switches then to tristate status,
thereby releasing the DO bus circuit for other uses. The SPI allows to parallel multiple
SPI devices by using multiple CSN lines. The SPI can also be used with other SPI-
devices in a daisy-chain configuration.
CSN High to Low & rising edge of SCLK: SDO is enabled. Status information is transfered to Output Shift Register
CSN
time
CSN Low to High: Data from Shift-Register is transfered to Output Driver Logic
CLK
DI
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14
actual Data
new Data
15 14
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SDI: Data will be accepted on the falling edge of CLK-Signal
previous Status
actual Status
15 14
DO
EF 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 0
SDO: State will change on the rising edge of CLK-Signal
Figure 3
4.3.2
SPI standard data transfer timing
Register Address
The 16-bit SPI frame is composed of an addressable block, an address-independent
block and a 2-bit address as shown in Figure 4.
The control word transmitted from the master to the TLE 7201R is executed at the end
of the SPI transmission (CSN L -> H) and remains valid until a different control word is
transmitted or a power on reset occurs. At the beginning of the SPI transmission (CSN
Data Sheet Rev. 2.0
14
2006-06-07
TLE 8201R
H ->L), the diagnostic data currently valid are latched into the SPI and transferred to the
master. For Status Register address handling, please refer to Section 4.3.4
CSN
time
15
14 13
12 11
10
9
8
7
6
5
4
3
2
1
0
bit
DI
Input data
Data for selected register address
Register
Address
generic data
output data
Data from selected register address
DO
generic data
Figure 4
SPI structure
Data Sheet Rev. 2.0
15
2006-06-07
TLE 8201R
4.3.3
SPI bit definitions
4.3.3.1 Control - word
Table 1
Input (Control) Data Register
Bit
CtrlReg 00
CtrlReg 01
CtrlReg 10
CtrlReg 11
Lock and Mirror PWM1 input
Mirror and Lamp- PWM2 input
heat control
select
driver control
LS4ON
select
15
14
13
12
11
10
9
LS1ON
HS7sel1
HS8sel1
HS9sel1
HS10sel1
HS11sel1
LS1sel1
LS2sel1
LS3sel1
OpL7ON
Testmode
HS7sel2
HS8sel2
HS9sel2
HS10sel2
HS11sel2
LS1sel2
HS1ON
HS4ON
LS5ON
LS2ON
HS2ON
HS5ON
LS6ON
LS3ON
HS3ON
HS6ON
HS8ON
HS9ON
HS10ON
HS11ON
HS7ON
LS2sel2
8
Testmode
Testmode
Testmode
LS3sel2
7
OpL89ON
OpL1011ON
6
Address - independent data
5
4
3
2
IS_2
IS_1
IS_0
SRR
IS_2
IS_2
IS_1
IS_0
SRR
IS_2
IS_1
IS_0
SRR
IS_1
IS_0
SRR
Address - bits
1
0
RA_1 = 0
RA_0 = 0
RA_1 = 0
RA_0 = 1
RA_1 = 1
RA_0 = 0
RA_1 = 1
RA_0 = 1
Note: Testmode-bits must be set to L for normal operation
Data Sheet Rev. 2.0
16
2006-06-07
TLE 8201R
Table 2
Control bit definitions
Definition
Control Bit
LSxON
low-side switch no. x is turned ON (OFF) if this bit is set to HIGH
(LOW)
HSxON
high-side switch no. x is turned ON (OFF) if this bit is set to HIGH
(LOW)
xsel1
power switch x is selected to be switched by the PWM1 input.
power switch x is selected to be switched by the PWM2 input
xsel2
OpL7ON
the pull-up current for open-load detection on output 7 is switched
on (off) if this bit is set to HIGH (LOW)
OpL89ON
OpL1011ON
IS_x
the pull-up currents for open-load detection on outputs 8 and 9 are
switched on (off) if this bit is set to HIGH (LOW)
the pull-up currents for open-load detection on outputs 10 and
11are switched on (off) if this bit is set to HIGH (LOW)
the output for the current sense multiplexer is selected by these
bits:
IS_2 IS_1 IS_0 Power stage selected for current sense
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
HS1
HS2
HS3
HS4
HS7
all others
no output selected (IISO = 0)
SRR
Status Register Reset. If set to high, the error bits of the selected
status register are reset after transmission of the data in the next
SPI frame (see <Fett>Section 4.3.4)
RA_x
Register Address, selects the control-register address for the
current SPI transmission and the status-register address for the
next SPI transmission
Data Sheet Rev. 2.0
17
2006-06-07
TLE 8201R
4.3.3.2 Diagnosis
Table 3
Output (Status) Data Register
StatReg 00 StatReg 01
Lock and Mirror Lock and Mirror Mirror and Lamp- Mirror and Lamp-
heat overload heat open load driver overload driver open load
valid for input data valid for input data valid for input data valid for input data
Bit
StatReg 10
StatReg 11
RA = 00
LS1OvL
HS1OvL
LS2OvL
HS2OvL
LS3OvL
HS3OvL
HS7OvL
n.c.
RA = 01
LS1OpL
n.c.
RA = 10
LS4OvL
HS4OvL
LS5OvL
HS5OvL
LS6OvL
HS6OvL
HS8OvL
HS9OvL
HS10OvL
HS11OvL
RA = 11
LS4OpL
n.c.
15
14
13
12
11
10
9
LS2OpL
n.c
LS5OpL
n.c.
LS3OpL
n.c.
LS6OpL
n.c.
HS7OpL
n.c.
HS8OpL
HS9OpL
HS10OpL
HS11OpL
8
7
n.c.
n.c.
6
n.c.
n.c.
Address - independent data
5
4
3
PSF
TSD
TW
PSF
PSF
TSD
TW
PSF
TSD
TW
TSD
TW
Error Flags
2
1
0
EF_11
EF_10
EF_01
EF_11
EF_10
EF_00
EF_11
EF_01
EF_00
EF_10
EF_01
EF_00
Note: n.c. bits are fixed LOW
Data Sheet Rev. 2.0
18
2006-06-07
TLE 8201R
Table 4
Status bit definitions
Status Bit Definition
LSxOvL
HSxOvL
LSxOpL
HSxOpL
PSF
Low-Side switch Over Load. Set to HIGH if low-side switch no. x is shut
down due to overcurrent or over temperature
High-Side switch Over Load. Set to HIGH if high-side switch no. x is shut
down due to overcurrent or over temperature
Low-Side switch open load. Set to HIGH if open load (undercurrent) is
detected in low-side switch x
High-Side switch Open Load. Set to HIGH if open load is detected in high-
side switch x
Power Supply Fail. Set to HIGH if the Voltage at the Vs pin is below the Vs
under-voltage threshold or above the Vs over-voltage threshold
TSD
TW
one or more powerstages are shut down due to over temperature
one or more powerstages have reached the warning temperature
Error Flag for StatReg xy. Set to HIGH if any bit is set to HIGH StatReg xy
EF_xy
n.c.
not connected. These bits may be used for test-mode purposes. They are
set to fixed LOW in normal operation
Data Sheet Rev. 2.0
19
2006-06-07
TLE 8201R
4.3.4
Status Register Address selection and Reset
The SPI is using a standard shift-register concept with daisy-chain capability. Any data
transmitted to the SPI will be available to the internal logic part at the end of the SPI
transmission (CSN L -> H). To read a specific register, the address of the register is sent
by the master to the SPI in a first SPI frame. The data that corresponds to this address
is transmitted by the SPI DO during the following (second) SPI frame to the master. The
default address for Status Register transmission after Power-ON Reset is 00.
The Status-Register-Reset command-bit is executed after the next SPI transmission.
The three bits RA_0, RA_1 and SRR act as command to read and reset (or not reset)
the addressed Status-Register. This is also explained in Figure 5.
The TSD status bit is not part of the adressable data but of the address independent
data. When any of the status registers is reset, the TSD bit is reset, too.
CSN
SI
x x x x x
x x x x x
0
x
0
x
1
x
x x x x x
x x x x x
1
x
1
x
0
x
x x x x x
x x x x x
0
x
1
x
1
x
StatReg10 is reset
after CSN
L->H
SO
Status Register 01 is transferred to
SPI master, but not reset after
transmission
Status Register 10 is transferred to
SPI master, and reset after
transmission
Com-
ment
After Power-ONReset, Status
Register 00 is sent by default
t
Figure 5
Status Register Addressing and Reset
Data Sheet Rev. 2.0
20
2006-06-07
TLE 8201R
4.3.4.1 Error-Flag
In addition to the 16 bits transferred from the TLE 7201R to the SPI master, an additional
Error Flag (EF) is transmitted at the DO pin. The EF status is shown on the DO pin after
CSN H->L, before the first rising edge at CLK, as shown in Figure 6.
The Error flag is set to H if any of the Status Registers contains an error message (i.e.
EF = EF_00 or EF_01 or EF_10 or EF_11)
.
CSN
CLK
DO
Z
EF
bit15
bit14
bit13
bit12
CSN
CLK
DO
Z
EF
Z
Figure 6
4.3.5
Error Flag transmission on DO during standard SPI transmission
(top), or without additional SPI transmission, CLK low (bottom)
Electrical Characteristics
Electrical Characteristics - SPI-timing
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
4.3.1 CSN lead time
4.3.2 CSN lag time
t
t
100
100
–
–
–
–
–
ns
ns
ns
11)
21)
31)
lead
–
lag
4.3.3 Fall time for CSN, CLK, DI, t
25
f
DO
4.3.4 Rise time for CSN, CLK,
DI, DO
t
–
–
25
ns
41)
r
Data Sheet Rev. 2.0
21
2006-06-07
TLE 8201R
Electrical Characteristics - SPI-timing
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
4.3.5 DI data setup time
4.3.6 DI data hold time
4.3.7 DI data valid time
4.3.8 DO data setup time
4.3.9 DO data hold time
t
t
t
t
40
40
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
µs
51)
61)
SU
–
h
1)
50
60
–
–
v
0
7 and 81)
91)
101)
DOsetup
t
50
5
DOhold
4.3.10 No-data-time between SPI t
–
nodata
commands
1)
4.3.11 Clock frequency
f
–
–
–
–
2
MHz
%
CL
1)
4.3.12 Duty cycle of incoming
40
60
–
clock at CLK
1)
SPI Timing is not subject to production test - specified by design. SPI functional test is performed at 5 MHz CLK
frequency. Timing specified with an external load of 30pF at pin [DO].
10
CSN
4
3
1
1
2
2
CLK
DI
5
6
not defined
MSB
LSB
LSB
7
8
9
DO
Flag
MSB
Figure 7
4.3.6
Timing Diagram
PWM inputs
The PWM inputs PWM1 and PWM2 are direct power stage control inputs that can be
used to switch on and off one or more of the power transistors with a PWM signal
supplied to this pin. The setting of the SPI Registers CtrlReg_01 and CtrlReg_11 defines
which of the power stages will be controlled by the PWM inputs. If the selection-bits of
Data Sheet Rev. 2.0
22
2006-06-07
TLE 8201R
power Stage x, xsel1 and xsel2 are LOW, the power stage x is controlled only via the SPI
control bit xON. If the selection bit xsel1 is HIGH and the control bit xON is also high, the
power stage x is controlled by the PWM1 pin (xsel2 and PWM2, respectively). The
behavior is shown in the pricipal schematic and truth table below. In terms of power
dissipation due to switching loss, a PWM frequency below 200 Hz is recommended.
CSN
DI
S
xON
CLK
P
DO
xsel1
xsel2
I
x
{LS1, LS2, LS3, HS7, HS8, HS9,
HS10, HS11}
&
&
&
PWM1
1
1
>=1
Gate
driver
OUT x
PWM2
power
transistor x
control logic of power transistor x
Figure 8
PWM input and SPI control registers
Data Sheet Rev. 2.0
23
2006-06-07
TLE 8201R
Truth-table for PWM inputs
xON
0
xsel1 xsel2 PWM1 PWM2 power stage x
x
0
1
1
0
0
1
1
1
x
0
0
0
1
1
1
1
1
x
x
0
1
x
x
1
x
0
x
x
x
x
0
1
x
1
0
OFF
ON
1
1
OFF
ON
1
1
OFF
ON
1
1
ON
1
ON
1
OFF
Data Sheet Rev. 2.0
24
2006-06-07
TLE 8201R
4.4
Power-Outputs 1-6 (Bridge Outputs)
Protection and Diagnosis
4.4.1
4.4.1.1 Short Circuit of Output to Ground or Vs
The low-side switches are protected against short circuit to supply and the high-side
switches against short to GND.
If a switch is turned on and the current rises above the shutdown threshold ISD for longer
than the shutdown delay time tdSD, the output transistor is turned off and the
corresponding diagnosis bit is set. During the delay time, the current is limited to ISC as
shown in Figure 9.
ISC
short to Vs
OUTx
ISD
IOUT
tdSD
short to GND
t
Figure 9
Short circuit protection
The delay time ia relatively short (typ. 25 µs) to limit the energy that is dissipated in the
device during a short circuit. This scheme allows high peak-currents as required in
motor-applications.
The output stage stays off and the error bit set until a status register reset is sent to the
SPI or a power-on reset is performed.
4.4.1.2 Cross-Current
If for instance HS1 is ON and LS1 is OFF, you can turn OFF HS1 and turn ON LS1 with
the same SPI command. To ensure that there is no overlap of the switching slopes that
would lead to a cross current, the dead-time H to L and L to H is specified.
In the control registers, it is also possible to turn ON high- and low-side switches of the
same half-bridge (e.g. LS1ON = H and HS1ON = H). To prevent a cross-current through
the bridge, such a command is not executed. Instead, both switches are turned OFF and
the Over-Load bit is set High for both switches (e.g. LS1OvL = H and HS1OvL = H).
Data Sheet Rev. 2.0
25
2006-06-07
TLE 8201R
4.4.1.3 Open Load
Open-load detection in ON-state is implemented in the low-side switches of the bridge
outputs: When the current through the low side transistor is lower than the reference
current IOCD in ON-state for longer than the open-load detection delay time tdOC, the
according open-load diagnosis bit is set. The output transistor, however, remains ON.
The open load error bit is latched and can be reset by the SPI status register reset or by
a power-on reset.
As an example, if a motor is connected between outputs OUT 1 and OUT 2 with a broken
wire as shown in Figure 10, the resulting diagnostic information is shown in Table 5
HS1
OUT 1
LS1
Door
Lock
Open Load
HS2
LS2
OUT 2
Figure 10
Table 5
Open load example
Open load diagnosis example
Control
Diagnostic information
motor
motor
Remark on Open
connected disconnected Load Detection
LS1 HS1 LS2 HS2 motor
ON ON ON ON rotation
LS1 LS2 LS1
OpL OpL OpL
LS2
OpL
0
1
0
0
0
1
0
0
1
0
1
0
motor off
0
0
0
0
0
1
0
0
0
1
not detectable
detected
clock-wise 0
counter
0
detected
clock-wise
0
1
1
0
0
1
1
0
brake high 0
brake low 1
0
1
0
1
0
1
not detectable
not detectable.
Data Sheet Rev. 2.0
26
2006-06-07
TLE 8201R
4.4.2
Electrical Characteristics
Electrical Characteristics OUT 1 and 2 (driver for door latch)
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
Static Drain-source ON-Resistance
4.4.1 High- and low-side switch
RDSON12
–
–
–
–
150
260
mΩ
mΩ
I
OUT = 3 A;
Tj = 25 °C
I
OUT = 3 A
Switching Times
4.4.2 high-side ON delay-time
4.4.3 high-side OFF delay time
4.4.4 low-side ON delay-time
4.4.5 low-side OFF delay time
4.4.6 dead-time H to L
tdONH12
tdOFFH12
tdONL12
tdOFFL12
tDHL12
–
–
–
–
3
50
25
50
25
–
100
50
µs
µs
µs
µs
µs
VS = 14 V,
resistive load of
10 Ω, see
100
50
Figure 11 and
Figure 12
–
tdONL12
-
tdOFFH12
4.4.7 dead-time L to H
tDLH12
3
–
–
µs
tdONH12
tdOFFL12
-
Short Circuit Protection
4.4.8 Over-current shutdown
threshold
ISD12
8
–
15
A
high- and low-
side
4.4.9 Shutdown delay time
4.4.10 Short circuit current1)
tdSD12
ISC12
10
–
25
20
50
–
µs
A
Open Load Detection
4.4.11 Detection current
4.4.12 Delay time
IOCD12
tdOC12
40
–
200
600
mA
low-side
200
350
µs
Leakage Current
4.4.13 OFF-state output current
IQL
–
–
25
µA
V
OUT = GND
1)
Not subject to production test - specified by design
Data Sheet Rev. 2.0
27
2006-06-07
TLE 8201R
Electrical Characteristics OUT3, 4 (Driver for deadbolt, mirror fold and mirror xy)
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
Static Drain-source ON-Resistance
High- and low-side switch
RDSON34
–
–
–
–
0.4
0.7
Ω
Ω
I
OUT = ±1 A;
Tj = 25 °C
4.4.14
I
OUT = ±1 A
Switching Times
4.4.15 high-side ON delay-time
4.4.16 high-side OFF delay time
4.4.17 low-side ON delay-time
4.4.18 low-side OFF delay time
4.4.19 dead-time H to L
tdONH34
tdOFFH34
tdONL34
tdOFFL34
tDHL34
–
–
–
–
3
50
25
50
25
–
100
50
µs
µs
µs
µs
µs
VS = 14 V,
resistive load of
14 Ω, see
100
50
Figure 11and
Figure 12
–
tdONL34
-
tdOFFH34
4.4.20 dead-time L to H
tDLH34
3
–
–
µs
tdONH34
tdOFFL34
-
Short Circuit Protection
4.4.21 Over-current shutdown
threshold
ISD34
3
4
8
A
high- and low-
side
4.4.22 Shutdown delay time
4.4.23 Short Circuit current1)
tdSD34
ISC34
10
–
25
6
50
–
µs
A
Open Load Detection
4.4.24 Detection current
4.4.25 Delay time
IOCD34
tdOC34
12
200
25
350
40
600
mA
µs
low-side
Leakage Current
4.4.26 OFF-state output current
IQL
–
–
10
µA
V
OUT = 0.2V
1)
Not subject to production test - specified by design
Data Sheet Rev. 2.0
28
2006-06-07
TLE 8201R
Electrical Characteristics OUT 5, 6
(driver for mirror x-y position)
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
Static Drain-source ON-Resistance
4.4.27 High- and low-side switch
RDSON56
–
–
–
–
0.8
1.3
Ω
Ω
I
OUT = ±0.5 A;
Tj = 25 °C
I
OUT = ±0.5 A
Switching Times
4.4.28 high-side ON delay-time
4.4.29 high-side OFF delay time
4.4.30 low-side ON delay-time
4.4.31 low-side OFF delay time
4.4.32 dead-time H to L
tdONH56
tdOFFH56
tdONL56
tdOFFL56
tDHL56
–
–
–
–
3
50
25
50
25
–
100
50
µs
µs
µs
µs
µs
VS = 14 V,
resistive load of
25 Ω, see
100
50
Figure 11and
Figure 12
–
tdONL56
-
tdOFFH56
4.4.33 dead-time L to H
tDLH56
3
–
–
µs
tdONH56
tdOFFL56
-
Short Circuit Protection
4.4.34 Over-current shutdown
threshold
ISD56
1.25
1.5
2.5
A
high- and low-
side
4.4.35 Shutdown delay time
4.4.36 Short Circuit current1)
tdSD56
ISC56
10
–
25
50
–
µs
3.0
A
Open Load Detection
4.4.37 Detection current
4.4.38 Delay time
IOCD56
tdOC56
12
25
40
mA
low-side
200
350
600
µs
Leakage Current
4.4.39 OFF-state output current
IQL
–
–
10
µA
V
OUT = 0.2V
1)
Not subject to production test - specified by design
Data Sheet Rev. 2.0
29
2006-06-07
TLE 8201R
CSN
ON -> OFF
OFF
high-side OFF
delay time
OUTx
tdOFFH
10%
tDHL
OFF
90%
low-side ON
delay time
OUTx
tdONL
OFF -> ON
Figure 11
Timing bridge outputs high to low
CSN
OFF
low-side OFF
delay time
90%
OUTx
OUTx
tdOFFL
ON -> OFF
tDLH
OFF -> ON
OFF
high-side ON
delay time
tdONH
10%
Figure 12
Timing bridge outputs low to high
Data Sheet Rev. 2.0
30
2006-06-07
TLE 8201R
4.5
Power-Output 7 (Mirror heater driver)
Output 7 is a high-side switch intended to drive ohmic loads like the heater of an exterior
mirror.
4.5.1
Protection and Diagnosis
4.5.1.1 Short Circuit of Output to Ground
If the high-side switch is turned on and the current rises above the shutdown threshold
I
SD for longer than the shutdown delay time tdSD, the output transistor is turned off and
the corresponding diagnosis bit is set. During the delay time, the current is limited to ISC
as shown in Figure 13.
ISC
OUT7
ISD
IOUT
tdSD
short toGND
t
Figure 13
Short circuit protection
The output stage stays off and the error bit set until a status register reset is sent to the
SPI or a power-on reset is performed.
4.5.1.2 Open Load
For the high-side switches, an open-load in OFF-state scheme is used as shown in
Figure 14. The output is pulled up by a current source IOpL. In OFF-state, the output
voltage is monitored and compared to the threshold VOpL. If the voltage rises above this
threshold, the open-load signal is set to high. This is equivalent to comparing the load
resistance to the value VOpL / IOpL. The open load error bit is latched and can be reset
by the SPI status register reset or by a power-on reset.
The pull-up current can be switched on and off by the OpLxON bits. This bit should be
set to LOW (i.e. pull-up current switched off) if an output is used to drive LEDs because
they may emit light if biased with the pull-up current.
Data Sheet Rev. 2.0
31
2006-06-07
TLE 8201R
OpL7ON
IOpL
Gate
OUT 7
switch ON HS7
HS7OpL
driver
high-side
switch 7
1
&
+
-
Filter
RLoad
+
-
VOpL
Figure 14
Open load in OFF-state scheme
Data Sheet Rev. 2.0
32
2006-06-07
TLE 8201R
4.5.2
Electrical Characteristics
Electrical Characteristics OUT 7 (mirror heater driver)
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
Static Drain-source ON-Resistance
4.5.1 High-side switch
RDSON7
–
–
–
–
100
170
mΩ
mΩ
I
OUT = 2.5 A;
Tj = 25 °C
OUT = 2.5 A
I
Switching Times
4.5.2 Turn-ON delay time
4.5.3 Output rise-time
4.5.4 Turn-OFF delay time
4.5.5 Output fall-time
tdONH7
trise7
tdOFFH7
tfall7
–
–
–
–
5
15
40
40
10
µs
µs
µs
µs
VS = 14 V,
resistive load of
10 Ω, see
15
20
5
Figure 15
Short Circuit Protection
4.5.6 Over-current shutdown
threshold
ISD7
6.25
8
11
A
–
4.5.7 Shutdown delay time
4.5.8 Short Circuit current1)
tdSD7
ISC7
10
–
25
12
50
–
µs
–
–
A
Open Load Detection
4.5.9 Pull-up current
4.5.10 Detection Threshold
4.5.11 Delay time
IOpL
VOpL
tdOC
100
2
–
–
–
300
4
µA
V
V
–
–
OUT = 4V
–
200
µs
Leakage Current
4.5.12 OFF-state output current
IQL
–
–
5
µA
V
OUT = GND
1)
Not subject to production test - specified by design
Data Sheet Rev. 2.0
33
2006-06-07
TLE 8201R
PWM
tFALL
tRISE
PWM
90%
90%
OUT7
tdON
tdOFF
10%
10%
Figure 15
Timing OUT 7
Data Sheet Rev. 2.0
34
2006-06-07
TLE 8201R
4.6
Power-Outputs 8 - 11 (Lamp drivers)
Outputs 8 - 11 are a high-side switches intended to drive ohmic loads 5W or 10W lamp
(bulb) loads.
4.6.1
Protection and Diagnosis
4.6.1.1 Short Circuit of Output to Ground
The high-side switches are protected against short to GND.
The high-side switches Out 8 - 11 are protected against short to GND.
Short Circuit during switch-on
During switch-on of an output a current an voltage level is used to check for a short
circuit. If a switch is turned on and the short circuit condition is valid after tdSDon8 the
output transistor is turned off and the corresponding diagnosis bit is set. A short circuit
condition is valid if the current rises above the shutdown threshold ISD8 and the voltage
at the output stays below VSD8. During the delay time, the current is limited to ISC8 as
shown in Figure 16
ISC8
OUT 8...11
IOUT
ISD8
IOUT
tdSDon8
short toGND
VOUT
t
VSD8
VOUT
Figure 16
Short circuit protection during switch-on
Data Sheet Rev. 2.0
35
2006-06-07
TLE 8201R
Short Circuit in On-state
If a switch is already on and the current rises above the shutdown threshold ISD for
longer than the shutdown delay time tdSD the output transistor is turned off and the
corresponding diagnosis bit is set. This is independent of the voltage Vout. See
Figure 17
ISC8
OUT 8...11
IOUT
ISD8
IOUT
tdSD8
short toGND
t
Figure 17
Short circuit protection in on-state
4.6.1.2 Open Load
For the high-side switches, an open-load in OFF-state scheme is used as shown in
Figure 18. The output is pulled up by a current source IOpL. In OFF-state, the output
voltage is monitored and compared to the threshold VOpL. If the voltage rises above this
threshold, the open-load signal is set to high. This is equivalent to comparing the load
resistance to the value VOpL / IOpL. The open load error bit is latched and can be reset
by the SPI status register reset or by a power-on reset.
The pull-up current can be switched on and off by the OpLxON bits. This bit should be
set to LOW (i.e. pull-up current switched off) if an output is used to drive LEDs because
they may emit light if biased with the pull-up current.
Data Sheet Rev. 2.0
36
2006-06-07
TLE 8201R
OpLxON
IOpL
Gate
driver
OUT x
switch ON HSx
HSxOpL
high-side
switch 7
1
&
+
-
Filter
RLoad
+
-
VOpL
Figure 18
Open load in OFF-state scheme
Data Sheet Rev. 2.0
37
2006-06-07
TLE 8201R
4.6.2
Electrical Characteristics
Electrical Characteristics OUT 8 - 11 (Lamp drivers)
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
Static Drain-source ON-Resistance
4.6.1 High-side switch
RDSON8
–
–
–
–
0.5
0.8
Ω
Ω
I
OUT = +0.5 A;
Tj = 25 °C
OUT = +0.5 A
I
Switching Times
4.6.2 Turn-ON delay time
4.6.3 Output rise-time
4.6.4 Turn-OFF delay time
4.6.5 Output fall-time
tdONH8
trise8
tdOFFH8
tfall8
–
5
–
7
5
15
30
50
30
µs
µs
µs
µs
VS = 14 V,
resistive load of
25 Ω, see
10
25
15
Figure 19
Short Circuit Protection
4.6.6 Over-current shutdown
threshold
ISD8
1.8
1.5
2.9
2,5
3.5
3.3
A
V
4.6.7 Over-current shutdown
threshold voltage
VSD8
4.6.8 Short circuit current1)
4.6.9 Shutdown delay time
4.6.10 Shutdown delay time
ISC8
tdSDon8
tdSD8
-
4.2
200
25
-
A
125
10
350
60
µs
µs
at switching-on
in on-state
Open Load Detection
4.6.11 Pull-up current
4.6.12 Detection Threshold
4.6.13 Delay time
IOpL8
VOpL8
tdOC8
100
2
–
–
–
250
4
µA
V
V
–
–
OUT = 4V
–
200
µs
Leakage Current
4.6.14 OFF-state output current
IQL
–
–
5
µA
V
OUT = GND
1)
Not subject to production test - specified by design.
Data Sheet Rev. 2.0
38
2006-06-07
TLE 8201R
PWM
tFALL
tRISE
PWM
90%
90%
OUT8-11
tdON
tdOFF
10%
10%
Figure 19
Timing OUT 8 - 11
Data Sheet Rev. 2.0
39
2006-06-07
TLE 8201R
4.7
Logic In- and Outputs
The threshold specifications of the logic inputs are compatible to both 5V and 3.3V
standard CMOS micro controller outputs. The logic output DO is a 5V CMOS output
4.7.1
Electrical Characteristics
Electrical Characteristics Diagnostics
8 V < VS < 20 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open;
-40 °C < Tj < 150 °C; unless otherwise specified
Pos. Parameter
Sym-
bol
Limit Values
Unit Conditions
min. typ. max.
Inhibit Input
4.7.15 H-input voltage threshold
4.7.16 L-input voltage threshold
4.7.17 Hysteresis of input voltage
4.7.18 Pull down current
VIH
VIL
VIHY
IIINH
–
–
–
–
–
2
V
VIN rising
VIN falling
–
1
–
V
100
–
600
50
mV
µA
V
IINH = 2 V
Logic Inputs DI, CLK, CSN, PWM1 and PWM2
4.7.19 H-input voltage threshold
4.7.20 L-input voltage threshold
4.7.21 Hysteresis of input voltage
4.7.22 Pull up current at pin CSN
VIH
VIL
VIHY
IICSN
IInput
–
–
2
V
VIN rising
VIN falling
–
1
–
–
V
100
-50
10
–
600
-10
50
mV
µA
µA
-25
25
V
V
CSN = 1 V
Input = 2 V
4.7.23 Pull down current at pins
PWM1, PWM2, DI, CLK
4.7.24 Input capacitance at pin CSN, CI
–
10
15
pF
V
0 V < VCC
<
DI, CLK, PWM1, PWM21)
5.25 V
Logic Output DO
4.7.25 H-output voltage level
VDOH
V
CC - VCC - –
I
I
SDOH = 1 mA
SDOL = -1.6 mA
1.0
–
0.7
0.2
–
4.7.26 L-output voltage level
VDOL
IDOLK
0.4
10
V
4.7.27 Tri-state leakage current
-10
µA
VCSN = VCC
0 V < VSDO
<
VCC
4.7.28 Tri-state input capacitance1)
CDO
–
10
15
pF
VCSN = VCC
0 V < VCC
<
5.25 V
1)
Not subject to production test, specified by design
Data Sheet Rev. 2.0
40
2006-06-07
TLE 8201R
Application Description
5
Application Description
Vbat
3.3nF
CP
47uF //
2 x 100nF
<40V
GO
Vs
Vcc
To5V supply
OUT1
10nF
main lock
M
M
INH
CSN
CLK
OUT2
safety-lock
DI
OUT3
DO
PWM1
PWM2
ISO
OUT4
mirror-x
Rsense
700
M
OUT5
mirror-y
M
OUT8
OUT9
OUT10
OUT6
OUT11
OUT7
mirror-heat
GND
Figure 20
Application example with two-motor (safety-) lock
Data Sheet Rev. 2.0
41
2006-06-07
TLE 8201R
Application Description
Vbat
3.3nF
CP
47uF //
2 x 100nF
<40V
GO
Vs
Vcc
To5V supply
OUT1
10nF
main lock
M
M
INH
CSN
CLK
OUT2
OUT3
DI
DO
PWM1
PWM2
mirror fold
ISO
OUT4
Rsense
700
mirror-x
OUT5
M
M
OUT8
OUT9
OUT10
mirror-y
OUT6
OUT11
OUT7
mirror heat
GND
Figure 21
Application example with mirror-fold
Data Sheet Rev. 2.0
42
2006-06-07
TLE 8201R
Package Outlines
6
Package Outlines
PG-DSO-36-27
(Plastic Dual Small Outline Package)
1)
±0.15
11
B
2.8
±0.1
1.1
±0.1
15.74
6.3
(Heatslug)
Heatslug
0.65
0.1 C
(Mold)
±0.15
0.95
36x
0.25 A B C
0.25 +0.13
M
±0.3
14.2
0.25 B
Bottom View
36
19
18
19
36
Index Marking
1 x 45˚
Heatslug
1
1
10
13.7 -0.2
(Metal)
1)
±0.1
15.9
A
(Mold)
1) Does not include plastic or metal protrusion of 0.15 max. per side
GPS09181
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
2006-06-07
SMD = Surface Mounted Device
Data Sheet Rev. 2.0
43
TLE 8201R
Edition 2006-06-07
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-
infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet Rev. 2.0
44
2006-06-07
TLE 8201R
Revision History
TLE 8201R
Revision History:
2006-06-07
Previous Version:
Preliminary Data Sheet Rev. 1.0
Page
Subjects (major changes since last revision)
No changes
Data Sheet Rev. 2.0
45
2006-06-07
相关型号：
TLE8242-2
8 Channel Fixed Frequency Constant Current Control With Current Profile Detection
INFINEON
©2020 ICPDF网 联系我们和版权申明