TLE9185QX_技术文档

TLE9185QX

BLDC Driver

1

Overview

Features

•

Low-drop voltage regulator 5 V, 250 mA for main supply

Three half-bridge gate drivers for external N-channel MOSFETs

Adaptive MOSFET gate control:

–

Regulation of the MOSFET switching time

Reduced switching losses in PWM mode

High efficient constant gate charge

•

Control of reverse battery protection MOSFET

One low-side capable current sense amplifier (CSA) with configurable gain for protection and diagnosis

Configurable wake-up sources

Six PWM inputs

–

High-side and low-side PWM capable

Active free-wheeling

Up to 25 kHz PWM frequency

•

32 bit serial peripheral interface (SPI) with cyclic redundancy check (CRC)

Very low quiescent current consumption in Stop Mode and Sleep Mode

Periodic cyclic wake in Normal Mode, Stop Mode and Sleep Mode

Reset and interrupt output

Drain-source monitoring and open-load detection

Configurable time-out and window watchdog

Overtemperature and short circuit protection features

Leadless power package with support of optical lead tip inspection

Green Product (RoHS compliant)

Datasheet

www.infineon.com

Rev. 1.0

2021-01-21

1

TLE9185QX

BLDC Driver

Overview

Potential applications

•

Auxiliary pumps (fuel, water, etc.)

Blower motor

Engine cooling fan

Sunroof module

Transfer case

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100.

Description

The TLE9185QX is a multifunctional IC with integrated power supply, multiple half-bridges and support

features in an exposed pad PG-VQFN-48 power package. The device is designed for various motor control

automotive applications.

To support these applications, the BLDC Driver provides the main functions, such as a 5 V low-dropout voltage

regulator, three half-bridges for BDLC motor control, one current sense amplifier and one 32 bit serial

peripheral interface (SPI).

The device includes diagnostic and supervision features, such as drain-source monitoring and open-load

detection, short circuit protection, configurable time-out and window watchdog, as well as overtemperature

protection.

The device is intended to operate with 5.0 V microcontroller.

Type

Package

Marking

TLE9185QX

PG-VQFN-48

TLE9185QX

Datasheet

2

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Table of Contents

1

2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Hints for not functional pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

3.2

3.3

4

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

4.2

4.3

4.4

5

5.1

5.2

5.3

System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Short State Machine Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Description of State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

State Machine Modes Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Software Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Transition Between States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Transition into Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Init Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Normal Mode -> Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Normal Mode -> Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Stop Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Sleep Mode -> Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Restart Mode -> Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Fail-Safe Mode -> Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reaction on Detected Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Stay in Current State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Transition into Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Transition into Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Internal Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

VS Supply Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.5

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

5.5.7

5.5.8

5.6

5.6.1

5.6.2

5.6.3

5.7

5.7.1

5.7.2

5.8

6

Voltage Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1

6.2

6.3

Datasheet

3

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

7

High-Voltage Wake Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1

7.2

7.2.1

7.2.2

7.3

Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

High-Voltage Wake Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8

8.1

8.2

Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.3.1

9.3.3.2

9.3.3.3

9.3.3.4

9.3.3.5

9.3.4

9.3.5

9.3.6

9.4

Gate Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

MOSFET control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Static activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Static activation of a high-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Static activation of a low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Turn-off of the high-side and low-side MOSFETs of a half-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Determination of the active and freewheeling MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Configurations in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PWM operation with 3 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Control signals with active free-wheeling (AFWx = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Control signals with passive free-wheeling (AFWx = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Time modulation of pre-charge and pre-discharge times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Operation at high and low duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Measurements of the switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

PWM operation with 6 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Status bits for regulation of turn-on and turn-off delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Gate driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Passive discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Slam mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Parking braking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Electrical characteristics gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.5

9.6

9.7

9.8

9.9

10

10.1

Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Watchdog during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

VSINT Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

VSINT Under- and Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

VSINT Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

VSINT Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

10.1.1

10.1.2

10.2

10.2.1

10.2.2

10.2.3

10.2.4

10.3

10.4

10.4.1

10.4.2

Datasheet

4

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

10.5

VS Under- and Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.5.1

10.5.2

10.6

10.6.1

10.6.2

10.7

VS Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

VS Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

VCC1 Over-/ Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

VCC1 Undervoltage and Undervoltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

VCC1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

VCC1 Short Circuit Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Bridge driver supervision with activated charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Drain-source voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Cross-current protection and drain-source overvoltage blank time . . . . . . . . . . . . . . . . . . . . . . 104

OFF-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Charge pump undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Switching parameters of MOSFETs in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Low-side drain-source voltage monitoring during braking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

VS or VSINT Overvoltage braking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Unidirectional and bidirectional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Gain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

CSO output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.8

10.8.1

10.8.2

10.8.3

10.9

10.9.1

10.9.1.1

10.9.1.2

10.9.1.3

10.9.1.4

10.9.1.5

10.9.2

10.9.3

10.10

10.10.1

10.10.2

10.10.3

10.10.4

10.11

11

11.1

11.2

11.3

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

SPI Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

SPI control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Device Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Control registers bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

SPI status information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Device Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Status registers bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Family and product information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

11.3.1

11.4

11.4.1

11.5

11.5.1

11.5.2

11.6

11.6.1

11.6.2

11.6.3

11.7

12

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

ESD according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.1

12.2

12.2.1

12.3

12.4

Datasheet

5

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

13

14

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Datasheet

6

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Block Diagram

2

Block Diagram

VSINT

VS

VCC1

CP

VS

VCC1

MUX(VSINT,VS)

CP

Charge pump

SDI

Control Logic

CPC1N

SDO

SPI

CPC1P

CPC2N

CPC2P

CLK

CSN

state machine

watchdog

VCC1

CP

VS

Reset

RSTN

GH1

SH1

GH2

SH2

Interrupt

INTN/TEST

Interrupt

Generation

GH3

SH3

Gate

Drivers

Reset

Generation

GL1

GL2

GL3

CSA logic

MUX(VSINT,VS)

SL

PWM1/CRC

PWM2

Wake-up input

WK4/SYNC

Wake Logic

Fail Safe

PWM3

PWM

inputs

PWM4

PWM5

PWM6

CP/VCC1

CSA

CSAP

CSAN

CSO

MUX(VSINT,VS): multiplexed VSINT & VS

GND

Figure 1

Block Diagram

Datasheet

7

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Pin Configuration

3

Pin Configuration

3.1

Pin Assignment

N.U. 37

24 SH2

23 GH2

22 PWM2

21 GL1

20 GL2

19 SL

18 CSN

17 N.U.

16 GND

15 N.U.

14 N.U.

13 N.U.

N.U. 38

PWM4 39

GL3 40

N.U. 41

WK4/SYNC 42

N.U. 43

TLE9185

PG-VQFN-48

N.U. 44

N.U. 45

PWM5 46

PWM6 47

VSINT 48

Figure 2

Pin Configuration

3.2

Pin Definitions and Functions

1

Symbol

Function

VCC1

Voltage reference for CSA, SPI and PWM inputs. Output voltage 1

2

RSTN

Reset Output. Active LOW, internally passive pull-up with open-drain output

3

INTN/TEST

Interrupt Output. Active LOW output, push-pull structure

TEST. Connect to GND (via pull-down) to activate Software Development Mode

4

5

6

7

SDO

SDI

SPI Data Output to Microcontroller (=MISO). Push-pull structure

SPI Data Input from Microcontroller (=MOSI). Internal pull-down

Ground. Analog/digital ground

GND

CSAP

Not Inverting input of Current Sense Amplifier.

Datasheet

8

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Pin Configuration

8

Symbol

CSAN

CSO

Function

Inverting input of Current Sense Amplifier.

Current Sense Amplifier Output.

SPI Clock Input. Internal passive pull-down

Not used.

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

CLK

N.U.

Not used.

N.U.

Not used.

N.U.

Not used.

N.U.

Not used.

GND

N.U.

Ground

Not used.

CSN

SPI Chip Select Not input. Internal passive pull-up

Source Low Side.

SL

GL2

Gate Low Side 2.

GL1

Gate Low Side 1.

PWM2

GH2

PWM input 2. Internal passive pull-up

Gate High Side 2.

SH2

Source High Side 2.

Source High Side 1.

Gate High Side 1.

SH1

GH1

PWM1/CRC

PWM input 1. Internal passive pull-down

CRC. Connect to GND (via pull-down) to activate CRC functionality

28

29

30

31

32

CPC2N

CPC2P

CPC1P

CPC1N

VS

Negative connection to Charge Pump Capacitor 2.

Positive connection to Charge Pump Capacitor 2.

Positive connection to Charge Pump Capacitor 1.

Negative connection to Charge Pump Capacitor 1.

Supply voltage for Bridge Drivers and Charge pump. Connected to the

battery voltage after reverse protection.

33

34

35

36

37

38

39

40

41

42

43

44

CP

Charge Pump output voltage.

PWM input 3. Internal passive pull-down

Gate High Side 3.

PWM3

GH3

SH3

Source High Side 3.

Not used.

N.U.

Not used.

PWM4

GL3

PWM input 4. Internal passive pull-down

Gate Low Side 3.

N.U.

Not used.

WK4/SYNC

N.U.

Wake-up input 4/Sync.

Not used.

N.U.

Not used.

Datasheet

9

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Pin Configuration

45

46

47

48

Symbol

N.U.

Function

Not used.

PWM5

PWM6

VSINT

PWM input 5. Internal passive pull-down

PWM input 6. Internal passive pull-down

Voltage regulator and main supply voltage. Connected to the battery voltage

after reverse protection

Cooling GND

Tab

Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an

electrical ground¹⁾

1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the device via the

PCB. The exposed die pad is not connected to any active part of the IC. However, it should be connected to GND for

the best EMC performance.

Note:

The GND pin as well as the Cooling Tab must be connected to one common GND potential.

3.3

Hints for not functional pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that

they are disabled via SPI. Unused pins should be handled as follows:

•

N.U.: not used; internally bonded for testing purpose; leave open except pin 17. Pin 17 to be connected to

VS.

•

RSVD: must be connected to GND.

Datasheet

10

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

General Product Characteristics

4

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Voltages

Supply Voltage VS

Supply Voltage VSINT

Voltage Regulator 1

V_{S, max}

-0.3

–

28

V

–

P_4.1.1

P_4.1.2

P_4.1.3

P_4.1.4

P_4.1.7

V_{S, max}

-0.3

40

Load Dump

–

V_{SINT, max}

V_{CC1, max}

V_{CP, max}

-0.3

28

-0.3

40

Load Dump

-0.3

5.5

V_S+ 17

Charge Pump Output Pin

(CP)

V_S- 0.8

I_CP> - 200 µA if CP P_4.1.8

is disabled

CPC1P, CPC2P

CPC1N, CPC2N

V_{CPCxP, max}

- 0.3

–

V_S+ 17

V_S+ 0.3

40

V

P_4.1.38

P_4.1.39

V_{CPCxN, max}- 0.3

Bridge Driver Gate High Side V_{GHx, max}

(GHx)

-8.0

-0.3

–

P_4.1.11

P_4.1.12

P_4.1.13

Bridge Driver Gate Low Side V_{GLx, max}

(GLx)

–

24

16

V

Voltage difference between V_GS

GHx-SHx and between GLx-

SLx

Bridge Driver Source High

(SHx)

V_{SHx, max}

-8.0

-0.3

-8.0

-0.3

–

40

V

–

P_4.1.14

P_4.1.15

P_4.1.16

P_4.1.17

P_4.1.18

Bridge Driver Source Low

Side SL

V_{SL, max}

6.0

+8.0

Current Sense Amplifier

inputs (CSAP, CSAN)

V_{CSx, max}

V_CSA,Diff

V_{WKx, max}

Current Sense Amplifier

Output CSO

V_CC1

+ 0.3

Differential input voltage

range CSAPx - CSANx

8.0

Wake Input WKx

–

40

V

–

P_4.1.19

P_4.1.25

PWM1/CRC, PWM2, PWM3, V_{PWM1-2-3-4-5-}-0.3

PWM4, PWM 5, PWM6 Input

6, max

Pins

Logic Input Pins (SDI, CLK, ) V_{I, max}

-0.3

–

V_CC1

V

–

P_4.1.28

+ 0.3

Datasheet

11

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

General Product Characteristics

Table 1

Absolute Maximum Ratings¹⁾(cont’d)

T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

-0.3

Typ. Max.

CSN

V_CSN

–

40

V

–

P_4.1.29

P_4.1.30

Logic Output Pins (SDO,

RSTN, INTN, )

V_{O, max}

V_CC1

+ 0.3

–

Temperatures

Junction Temperature

Storage Temperature

ESD Susceptibility

ESD Resistivity

T_j

-40

-55

–

150

°C

–

P_4.1.32

P_4.1.33

T_stg

V_ESD,11

V_ESD,12

V_ESD,21

V_ESD,22

-2

–

2

kV

V

HBM²⁾

HBM²⁾³⁾

CDM⁴⁾

P_4.1.34

P_4.1.35

P_4.1.36

P_4.1.37

ESD Resistivity to GND

-8

8

-500

-750

500

750

ESD Resistivity Pin 1,

12,13,24,25,36,37,48 (corner

pins) to GND

V

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).

3) For ESD “GUN” Resistivity (according to IEC61000-4-2 “gun test” (150 pF, 330 Ω)), is shown in Application Information

and test report will be provided from IBEE.

4) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1.

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

4.2

Functional Range

Table 2

Functional Range¹⁾

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

V_POR,f

6.0

Typ.

Max.

28

2)

Supply Voltage

V_SINT,func

V_S,func

T_j

–

V

P_4.2.1

P_4.2.2

P_4.2.6

Bridge Supply Voltage

28

V

–

Junction Temperature

-40

150

°C

1) Not subject to production test, specified by design.

2) Including Power-On Reset, Over- and Undervoltage Protection.

Note:

Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

Datasheet

12

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

General Product Characteristics

Device Behavior Outside of Specified Functional Range

•

28 V < V_SINT,func< 40 V: Device will still be functional including the state machine; the specified electrical

characteristics might not be ensured anymore. The V_CC1is working properly, however, a thermal shutdown

might occur due to high power dissipation. The specified SPI communication speed is ensured; the

absolute maximum ratings are not violated, however the device is not intended for continuous operation

of V_SINT> 28 V and a thermal shutdown might occur due to high power dissipation. The device operation at

high junction temperatures for long periods might reduce the operating life time.

V

_POR,f< V_SINT< 5.5 V (given the fact that the device was powered up correctly before with V_SINT> 5.5 V):

Device will still be functional; the specified electrical characteristics might not be ensured anymore:

–

A reset could be triggered depending on the Vrthx settings.

The specified SPI communication speed is ensured.

Note:

V_S,UV< V_S< 6.0 V: the charge pump might be deactivated due to a charge pump undervoltage

detection, resulting in a turn-off of the external MOSFETs.

4.3

Thermal Resistance

Table 3

Thermal Resistance¹⁾

Parameter

Symbol

Values

Typ.

7.2

Unit Note or

Test Condition

Number

Min.

Max.

Junction to Soldering Point R_th(JSP)

Junction to Ambient R_th(JA)

–

K/W Exposed Pad

P_4.3.1

P_4.3.2

2)

–

27

K/W

1) Not subject to production test, specified by design.

2) Specified R_th(JA)value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for a power

dissipation of 1.5 W; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 with 2 inner copper layers

(2 x 70 µm Cu, 2 x 35 µm C); where applicable a thermal via array under the exposed pad contacted the first inner

copper layer and 300 mm2 cooling areas on the top layer and bottom layers (70 µm).

4.4

Current Consumption

Table 4

Current Consumption

Current consumption values are specified at T_j= 25°C, V_SINT= V_S= 13.5 V, all outputs open

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Normal Mode

1)

Normal Mode current

consumption

I_Normal

–

4.5

5.5

mA

µA

V

= 5.5 V to 28 V; P_4.4.1

SINT

T_j= -40°C to +150°C;

CP=off

Stop Mode current

consumption

(low active peak threshold)

I_{Stop_1,25}

–

50

65

¹⁾²⁾CSA=off;

WKx=CP=off:

Cyclic Wak.=off

Watchdog = off;

P_4.4.2

no load on V_CC1

;

I_PEAK_TH = 0_B

Datasheet

13

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_SINT= V_S= 13.5 V, all outputs open

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

55

Unit Note or

Test Condition

Number

Min.

Max.

Stop Mode current

consumption

I_{Stop_1,85}

–

80

µA

¹⁾²⁾³⁾T_j= 85°C;

CSA=off;

P_4.4.3

(low active peak threshold)

WKx=CP=off:

Cyclic Wak.=off

Watchdog = off;

no load on V_CC1

;

I_PEAK_TH = 0_B

Stop Mode current

consumption

(high active peak threshold)

I_{Stop_2,25}

–

70

75

95

µA

¹⁾²⁾CSA=off;

WKx=CP=off: Cyclic

Wak.=off Watchdog =

off;

no load on V_CC1

I_PEAK_TH = 1_B

P_4.4.4

P_4.4.5

;

Stop Mode current

consumption

I_{Stop_2,85}

105

¹⁾²⁾³⁾T_j= 85°C;

CSA=off;

(high active peak threshold)

Cyclic Wak.=off;

Watchdog = off;

no load on V_CC1

;

I_PEAK_TH = 1_B

Sleep Mode

Sleep Mode current

consumption

I_Sleep,25

–

18

28

30

40

µA

¹⁾CSA=off;

WKx=HSx=CP=off:

Cyclic Wak.= off

¹⁾³⁾T_j= 85°C;

CSA=off;

P_4.4.6

P_4.4.7

Sleep Mode current

consumption

I_Sleep,85

WKx=HSx=CP=off:

Cyclic Wak.=off

Feature Incremental Current Consumption

Current consumption for

each WK input

I_WK,wake,25

–

0.2

0.5

2

3

µA

^1)4)5)6)Sleep Mode; WK P_4.4.22

wake capable;

no activity on WK pin;

^1)3)4)5)6)Sleep Mode; T_jP_4.4.23

= 85°C;

Current consumption for

each WK input

I_WK,wake,85

–

WK wake capable;

no activity on WK pin;

Current consumption for

watchdog active in Stop

Mode

I_Stop,WD25

–

18

19

23

25

µA

³⁾⁷⁾Stop Mode;

Watchdog running;

P_4.4.28

P_4.4.29

Current consumption for

watchdog active in Stop

Mode

I_Stop,WD85

³⁾⁷⁾Stop Mode;

T_j= 85°C;

Watchdog running;

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TLE9185QX

BLDC Driver

General Product Characteristics

Table 4

Current Consumption (cont’d)

Current consumption values are specified at T_j= 25°C, V_SINT= V_S= 13.5 V, all outputs open

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Current Sense Amplifier

I_CSA1

–

4

mA ⁷⁾CSA_OFF = 0_B; VCSP P_4.4.31

= VCSAP = VCSAN = 0 V;

CSO_CAP = 0_B;

CCSO = 330 pF

Current Sense Amplifier

I_CSA2

–

10

mA ⁷⁾CSA_OFF = 0_B; VCSP P_4.4.36

= VCSAP = VCSAN = 0 V;

CSO_CAP = 1_B;

CCSO = 2.2 nF

Current consumption in

parking braking mode

(LSx ON)

I_parking

–

10

7

14

10

40

µA

³⁾⁷⁾Stop Mode or Sleep P_4.4.32

Mode; T_j< 85°C;

PARK_BRK_EN = 1_B

³⁾⁷⁾Stop Mode or Sleep P_4.4.34

Mode; T_j< 85°C;

OV_BRK_EN = 1_B

Current consumption Over I_{OV,LS_OFF}

voltage braking mode

(LSx OFF)

Current consumption in VS I_CP,BD

for Charge Pump and Bridge

Driver

30

mA Normal Mode;

T_j= -40°C to +150°C;

CPEN = 1; All HB OFF

P_4.4.35

1) Measured at V_SINT

.

2) If the load current on V_CC1will exceed the configured V_CC1active peak threshold, the current consumption will increase

by typ. 2.9 mA to ensure optimum dynamic load behavior. See also Chapter 6.

3) Not subject to production test, specified by design.

4) Current consumption adders of features defined for Stop Mode also apply for Sleep Mode and vice versa. Wake input

signals are stable (i.e. not toggling), cyclic wake & watchdog are OFF (unless otherwise specified).

5) No pull-up or pull-down configuration selected.

6) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are

activated.

7) Additional current will be drawn from V_SINT

.

Notes

1. There is no additional current consumption contribution in Normal Mode due to PWM generators or Timers.

2. The quiescent current consumption in Stop Mode and Sleep Mode will increase for V_SINT< 9 V.

Datasheet

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BLDC Driver

System Features

5

System Features

This chapter describes the system features and behavior of the TLE9185QX:

•

State machine

Device configuration

State machine modes and mode transitions

Wake-up features such as cyclic wake

5.1

Short State Machine Description

The BLDC Driver offers six operating modes:

•

Init Mode: Power-up of the device and after a soft reset.

Normal Mode: The main operating mode of the device.

Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled.

Sleep Mode: The second-level power saving mode with VCC1 disabled.

Restart Mode: An intermediate mode after a wake event from Sleep Mode or Fail-Safe Mode or after a

failure (e.g. WD failure, VCC1 under voltage reset).

•

Fail-Safe Mode: A safe-state mode after critical failures (e.g. Temperature shutdown) to bring the system

into a safe state and to ensure a proper restart of the system.

A special mode, called Software Development Mode, is available during software development or debugging

of the system. All above mentioned operating modes can be accessed in this mode. However, the watchdog is

still running. Watchdog failures are indicated over INTN pin instead.

However, the watchdog reset signaling can be reactivated again in Software Development Mode. The

Watchdog will start always with the Long Open Windows (t_low).

The BLDC Driver is controlled via a 32-bit SPI interface (refer to Chapter 11 for detailed information). The

configuration as well as the diagnosis is handled via the SPI.

The device offers various supervision features to support functional safety requirements. Refer to Chapter 10

for more information.

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BLDC Driver

System Features

5.2

Device Configuration

Two features on the BLDC Driver can be configured by hardware:

•

The selection of the normal device operation or the Software Development Mode.

Enabling/disabling the CRC on the SPI interface.

The configurations are done monitoring the follow pins:

•

INTN/TEST

PWM1/CRC

The hardware configuration can be done typically at device power-up, where the device is in Init Mode or (only

in case of CRC setting) in Restart Mode.

Software development Mode configuration detail

After the RSTN is released, the INTN/TEST pin is internally pulled HIGH with a weak pull-up resistor. Therefore

the default configuration is the device in normal operation.

In order to configure the Software Development Mode, the following conditions have to be fulfilled:

•

Init Mode from power-up

VCC1>Vrtx

POR=1

RSTN = HIGH

The Software Development Mode is configured using the following scheme:

•

Only one external pull-down on INTN/TEST pin followed by an arbitrary SPI command, the device latches

the Software Development Mode.

•

External pull-up or no pull-down on INTN/TEST pin enable the device in normal operation.

To enter Software Development Mode, a pull-down resistor to GND might be used.

Soft. Dev.

Mode OFF for t_{SDM_F}to avoid supply glitches

The INTN/TEST is externally pulled-down

INTN/TEST

Soft. Dev.

Mode ON

t_{SDM_F}

Intn_filt

RSTN

LATCHED (first SPI frame)

Entry in Software Development Mode

(not latched )

Mode

Successful latched Software Development Mode

Normal Mode

Init Mode

Time/us

Intn_filt: internal filtered INTN/TEST signal

Figure 3

Software Development Mode Selection Timing

Intn_filt is a filtered signal from INTN/TEST, with the filter time t_{SMD_F}(P_11.2.7). Intn_filt starts (at the rising

edge if RSNT) wit the value 1.

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BLDC Driver

System Features

Note:

If during monitoring the INTN/TEST pin for Software Development Mode entry, the device changes

the mode without SPI command, the device will not enter/stay in Software Development Mode.

CRC configuration detail

The CRC is configured using the following scheme:

•

Pull-down on PWM1/CRC enable the CRC.

No external components on PWM1/CRC disables the CRC.

In order to configure the CRC, the follow conditions have to be full filled:

•

Init Mode (from power-up) or Restart Mode

VCC1>Vrtx

POR=1

RSTN = LOW

The configuration selection is done during the reset delay time t_RD1with a continuous filter time of t_{CFG_F}and

the configuration (depending on the voltage level at PWM1/CRC) is latched at the rising edge of RSTN.

VS_INT

V_POR,r

t

VCC1

V_RT1,r

t

RSTN

t_{CFG_F}

Continuous Filtering with

t

t_RD1

Configuration selection monitoring period

Figure 4

CRC configuration Selection Timing Diagram at the device power-up.

In case of mismatch between CRC setting between the device and µC (CRC_STAT), the device can accept two

recovery SPI commands (static patterns).

The pattern 67AA AA0E_H(addr + rw_bit = 67 ; data = AAAA ; CRC = 0E ) enables the CRC.

The pattern E7AA AAC3_H(addr + rw_bit = E7 ; data = AAAA ; CRC = C3) disables the CRC.

The patterns shall be send only in Normal Mode.

For additional details about the CRC setting and configuration, refer also to Chapter 11.3.1.

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BLDC Driver

System Features

5.3

Block Description of State Machine

The state machine describes the different states of operation, the device may get into. The following figure

shows the state machine flow diagram.

First battery connection

Soft Reset

* The Software Development Mode is a super set of

state machine where the WD reset is not signaled.

Config.: settings can be changed in

this device mode;

CSA

Init Mode *

OFF

(Long open window)

Fixed: settings stay as defined in

Normal Mode

(1) After Fail-Safe Mode entry, the device will stay for at

least typ. 1s in this mode (with RSTN low) after a TSD2

event and min. typ. 100ms after other Fail-Safe Events.

Only then the device can leave the mode via a wake-up

event. Wake events are stored during this time.

VCC1

ON

CP⁽²⁾

OFF

BD⁽²⁾

OFF

Cyc.

Wake

OFF

WD

fixed

(2) HB Passive off due to gate-source resistors.

Any SPI

command

CSA

config.

Normal Mode

VCC1

ON

CP

config.

BD

config.

WD trigger

Cyc.

Wake

config.

WD

config.

ꢀꢁReset is released

ꢀꢁWD starts with long open window

Automatic

SPI cmd

CSA

OFF

CSA

OFF

Sleep Mode

Stop Mode

VCC1

OFF

CP⁽²⁾

OFF

BD⁽²⁾

OFF

VCC1

ON

CP⁽²⁾

OFF

BD⁽²⁾

OFF

Cyc.

Wake

fixed

Cyc.

Wake

fixed

VCC1 over voltage

(depend from VCC1_OV_MOD setting)

WD

OFF

WD

fixed

Wake up event

LS short circuit during

VS_OV event

CSA

OFF

Restart Mode

(RO pin is asserted)

Sleep Mode entry without any

wake source enabled

CP⁽²⁾

OFF

BD⁽³⁾

OFF

VCC1

ON/

ramping

Watchdog Failure

After 4x consecutive VCC1

After 4x consecutive

Watchdog failure

Cyc.

Wake

OFF

under voltage events

VCC1 Under voltage

WD

OFF

(if VS_INT > VS_INT_UV)

VCC1 over voltage

(depend from VCC1_OV_MOD setting)

CSA

OFF

Fail-Safe Mode ⁽¹⁾

TSD2 event

VCC1

OFF

CP⁽²⁾

OFF

BD⁽²⁾

WK wake-up event

OR

Release of overtemperature TSD2

after a time depending on TSD2_DEL

OFF

Cyc.

Wake

OFF

VCC1 Short to GND

WD

OFF

Figure 5

State Diagram showing the operating modes

Description:

•

ON /OFF:= Indicate if the module is enabled or disabled either via SPI or from the device itself

config:= Settings can be changed in this mode

fixed:= Settings stay as defined in Normal Mode or Init Mode

active/inactive:= Indicate if the device activates/deactivates one specific feature

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BLDC Driver

System Features

5.4

State Machine Modes Description

5.4.1

Init Mode

The device starts up in Init Mode after crossing the power-on reset V_POR,rthreshold (see also Chapter 10.3) and

the watchdog will start with a long open window (t_LW) after RSTN is released (High level).

In Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence.

Init Mode

(Long open window)

VCC1

ON

CP

OFF

BD

OFF

Cyc.

Wake

OFF

CSA

OFF

WD

fixed

Figure 6

Table 5

Init Mode

Init Mode Settings

Part/Function

Value

ON

Description

•

The VCC1 is ON

VCC1

WD

Watchdog is fixed and set with a long open window (t_LW

Bridge Drivers is OFF

)

fixed

OFF

BD

Charge Pump is OFF

CP

Current Sense Amplifier is OFF

Cycle Wake is OFF

CSA

Cyc Wake

5.4.2

Normal Mode

The Normal Mode is the standard operating mode for the device. The VCC1 is active and all features are

configurable. Supervision and monitoring features are enabled.

Normal Mode

VCC1

ON

CP

config.

BD

config.

Cyc.

Wake

config.

CSA

config.

WD

config.

Figure 7

Normal Mode

Datasheet

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TLE9185QX

BLDC Driver

System Features

Table 6

Part/Function

VCC1

Normal Mode Settings

Value

ON

Description

•

VCC1 is active

Watchdog may be configured by SPI

WD

config

The Bridge Drivers and Charge Pump may be configured and switched

ON or OFF by SPI

BD/CP

•

Current Sense Amplifier may be configurable and switched ON or OFF by

SPI

Cyclic wake can be configured with the Timer1 or Timer 2

CSA

config

Cyc. Wake

5.4.3

Stop Mode

The Stop Mode is the first level technique to reduce the overall current consumption VCC1 into a low-power

mode.

Note:

All settings have to be done before entering Stop Mode.

In Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to

Normal Mode, triggering a device Soft Reset, refreshing the watchdog as well as for reading and clearing the

SPI status registers.

Note:

A wake-up event on , WKx, Low-Side short circuit detection in parking braking mode or overvoltage

brake detection, could generate an interrupt on pin INTN (based on INTN masking configuration;

refer to Chapter 8) however, no change of the device mode will occur.

Stop Mode

VCC1

ON

CP

OFF

BD

OFF

Cyc.

Wake

fixed

WD

fixed

CSA

OFF

Figure 8

Table 7

Stop Mode

Stop Mode Settings

Part/Function

VCC1

Value

ON

Description

•

VCC1 is ON

Watchdog is fixed as configured in Normal Mode

The Bridge Drivers and Charge Pump are OFF

Current Sense Amplifier is OFF

WD

fixed

OFF

BD/CP

CSA

OFF

Cyclic wake is fixed as configured in Normal Mode

Cyc. Wake

fixed

Datasheet

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TLE9185QX

BLDC Driver

System Features

Note:

In Stop Mode, it is possible to activate the Low-Side of Bridge Drivers (e.g. in case of parking braking

mode or overvoltage brake detection). Refer to Chapter 10.9 for additional details.

5.4.4

Sleep Mode

The Sleep Mode is the second level technique to reduce the overall current consumption to a minimum

needed to react on wake-up events or for the device to perform autonomous actions .

Note:

All settings have to be done before entering Sleep Mode.

Sleep Mode

VCC1

OFF

CP

OFF

BD

OFF

Cyc.

Wake

fixed

WD

OFF

CSA

OFF

Figure 9

Table 8

Sleep Mode

Sleep Mode Settings

Part/Function

VCC1

Value

OFF

Description

•

VCC1 is OFF

Watchdog is OFF

WD

OFF

The Bridge Drivers and Charge Pump are OFF

Current Sense Amplifier is OFF

Cyclic wake is fixed

BD/CP

OFF

CSA

OFF

Cyc. Wake

fixed

Note:

In Sleep Mode, it is possible to activate the Low-Side’s of Bridge Drivers (e.g. in case of parking

braking mode or overvoltage braking). Refer to Chapter 10.9 for additional details.

5.4.5

Restart Mode

The Restart Mode is a transition state where the RSNT pin is asserted.

Restart Mode

(RO pin is asserted)

VCC1

ON/

CP

OFF

BD

OFF

ramping

Cyc.

Wake

OFF

WD

OFF

CSA

OFF

Figure 10 Restart Mode

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BLDC Driver

System Features

Table 9

Restart Mode Settings

Part/Function

VCC1

Value

Description

•

VCC1 is ON or ramping up

ON/

ramping

•

WD will be disabled if it was activated before

The Bridge Drivers and Charge Pump are OFF

Current Sense Amplifier is OFF

WD

OFF

BD/CP

CSA

Cyclic wake will be disabled if it was activated before

Cyc. Wake

5.4.6

Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning OFF VCC1 .

After a wake event the system is then able to restart again.

Fail-Safe Mode

VCC1

OFF

CP

OFF

BD

OFF

Cyc.

Wake

OFF

WD

OFF

CSA

OFF

Figure 11 Fail-Safe Mode

Table 10 Fail-Safe Mode Settings

Part/Function

VCC1

Value

OFF

Description

•

VCC1 is switched OFF

WD is switched OFF

WD

The Bridge Drivers and Charge Pump are OFF

Current Sense Amplifier is OFF

BD/CP

CSA

Cyclic wake is switched OFF

Cyc. Wake

Note

•

In Fail-Safe Mode, the default wake sources WKx (if configured as wake inputs) are activated automatically

and all wake event bits will be cleared.

•

The Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid any

fast toggling behavior a filter time of typ. 100ms (t_FS,min) is implemented. Wake events during this time will

be stored and will automatically lead to entering Restart Mode after the filter time.

In case of an VCC1 overtemperature shutdown (TSD2) the Restart Mode will be reached automatically after

a filter time of typ. 1s (t_TSD2) without the need of a wake event once the device temperature has fallen below

the TSD2 threshold.

•

The parking braking mode is automatically disabled in Fail-Safe Mode.

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BLDC Driver

System Features

5.4.7

Software Development Mode

The Software Development Mode is a dedicated device configuration especially useful for software

development.

Compared to the default device user mode operation, this mode is a super set of the state machine. The device

will start also in Init Mode and it is possible to use all the modes and functions with following differences:

•

Restart Mode or Fail-Safe Mode (depending on the configuration) is not reached due to watchdog failure

but the other reasons to enter these modes are still valid.

Table 11 Normal Mode Settings (Software Development Mode active)

Part/Function

Default

State

Description

•

VCC1 is active

VCC1

WD

ON

WD is on, but will not trigger transition to Fail-Safe Mode or Restart

Mode

•

The Bridge Drivers and Charge Pump may be configured and switched

ON or OFF by SPI

Can be configured

BD/CP

OFF

Cyc. Wake

Software Development Mode entry

For timing and configuration details, refer to Chapter 5.2.

Note

•

After Init Mode, the pull-up is released as the INTN/TEST pin acts as output then to drive the INTN signal.

If the device enters Fail-Safe Mode due to VCC1 short circuit to GND during the Init Mode, the Software

Development Mode will not be entered and can only be reached at the next power-up of the device after

the VCC1 short circuit is removed.

•

The absolute maximum ratings of the pin INTN must be observed. To increase the robustness of this pin

during debugging or programming a series resistor between INTN and the connector can be added.

Watchdog in Software Development Mode

The Watchdog is enabled in Software Development Mode as default state. One INTN event is generated due

to wrong watchdog trigger.

It is possible to deactivate the integrated Watchdog module using the WD_SDM_DISABLE bit. After disabling

the Watchdog, no INTN events are generated and the WD_FAIL bit will also not be set anymore in case of a

trigger failure. It is also possible only to mask / unmask the INTN event of the WD in Software Development

Mode by using the bit WD_SDM. In case of unmasking, a WD trigger fail will only lead to WD_FAIL bit set.

5.5

Transition Between States

This chapter describes the transition between the modes triggered by power-up, SPI commands or wake-up

events.

5.5.1

Transition into Init Mode

The device goes into Init Mode in case of a power-up or after sending a soft-reset in Normal or Stop Mode.

Prerequisites:

•

Power OFF

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BLDC Driver

System Features

•

Device in Normal Mode or Stop Mode with follow conditions:

–

VSINT > VPOR,r

RSTN High

Triggering Events:

A Soft Reset command (MODE = ‘11’). All SPI registers will be changed to their respective Soft Reset values.

•

Note

•

In case of Soft Reset command, a hardware RSTN event can be generated depending on the configuration.

An external Reset will be generated in case of SOFT_RESET_RO = 0_B. In case of SOFT_RESET_RO = 1_B, no

RSTN hardware event is generated in case of Soft Reset.

•

At power-up, the SPI bit VCC1_UV will not be set as long as VCC1 is below the VRT,x threshold and if VSINT

is below the VSINT,UV threshold. The RSTN pin will be kept LOW as long as VCC1 is below the selected

VRT1,r threshold. The reset delay counter will start after VRT1,r threshold is reached. After the first

threshold crossing of VCC1 > V_RT1,Rand RSTN transition from low to high, all subsequent undervoltage

events will lead to Restart Mode.

•

Wake events are ignored during Init Mode and will be lost.

The bit VSINT_UV will only be updated in Init Mode once RSTN resumes a high level.

5.5.2

Init Mode -> Normal Mode

This transition moves the device in the mode where all configurations are accessable via SPI command.

Prerequisites:

•

VSINT > VPOR,r

Init Mode

RSTN High

Triggering Events:

•

Any valid SPI command (from SPI protocol point of view) will bring the device to Normal Mode (i.e. any

register can be written, cleared and read) during the long open window where the watchdog has to be

triggered (refer also Chapter 11.2). The CRC is not taken into account for this transition.

•

For example:

–

A SPI Sleep Mode command will still bring the device into Normal Mode. However, as this is an invalid

state transition, the SPI bit SPI_FAIL is set.

–

Any invalid SPI command (from content point of view) will still bring the device into Normal Mode. The

SPI bit SPI_FAIL is set.

Note

It is recommended to use the first SPI command to trigger and to configure the watchdog.

•

5.5.3

Normal Mode -> Stop Mode

This transition is intended as first measure to reduce the current consumption. All the device features needed

in Stop Mode shall be configured in Normal Mode.

Prerequisites:

•

VCC1>Vrtx

Device in Normal Mode

Triggering Events:

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BLDC Driver

System Features

•

State transition is only initiated by specific SPI command.

Note

•

An interrupt is triggered on the pin INTN when Stop Mode is entered and not all wake source signalization

flags were cleared.

If high-side switches are kept enabled during Stop Mode, then the device current consumption will

increase.

It is not possible to switch directly from Stop Mode to Sleep Mode. Doing so will also set the SPI_FAIL flag

and will bring the device into Restart Mode.

5.5.4

Normal Mode -> Sleep Mode

This transition is intended to reduce as much as possible the current consumption keeping active only wake-

up sources. All wake-up sources configurations shall be done in Normal Mode.

Prerequisites:

•

VCC1>Vrtx

Device in Normal Mode

All wake source signalization flags were cleared (including the LSxDSOV_BRK bit)

At least one wake-up source activated

Triggering Events:

State transition is only initiated by specific SPI command.

•

Note

•

If VCC1_UV or VCC1_OV (with Config to go to Restart Mode) occurs at the border of the Sleep Mode entry:

The device will go immeditaley into Restart Mode.

•

If TSD2 or VCC1_OV (with Config to go to Fail-Safe Mode) occurs at the border of the Sleep Mode entry: The

device will enter immediately Fail-Safe Mode.

•

As soon as the Sleep Mode command is sent, the Reset will go low.

It is not possible to switch all wake sources off in Sleep Mode. Doing so will set the SPI_FAIL flag and will

bring the device into Restart Mode.

5.5.5

Stop Mode -> Normal Mode

This transition is intented to set the device in Normal Mode where all the device integrated features are

availbale and configurable.

Prerequisites:

•

VCC1>Vrtx

Device in Stop Mode

Triggering Events:

State transition is only initiated by SPI command.

•

Note

•

None

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BLDC Driver

System Features

5.5.6

Sleep Mode -> Restart Mode

This transition is the consequence of a detection of wake-up event by the device. This transition is used to

ramp up VCC1 after a wake in a defined way.

Prerequisites:

•

Device in Sleep Mode

At least one wake-up source active

Triggering Events:

•

A wake-up event on WKx, Cyclic Wake.

Bridge driver low-side short circuit detected during overvoltage braking or in parking braking mode.

Note

•

It is not possible to switch off all wake sources in Sleep Mode. Doing so will set the SPI_FAIL flag and will

bring the device into Restart Mode.

•

RSTN is pulled low during Restart Mode.

The Restart Mode entry is signalled in the SPI register DEV_STAT.

The wake-up events are flaged in WK_STAT register or DSOV register.

5.5.7

Restart Mode -> Normal Mode

From Restart Mode, the device goes automatically to Normal Mode.

Prerequisites:

•

Device in Sleep Mode or Fail-Safe Mode

Triggering Events:

•

Automatic

Reset is released

Note

The watchdog timer will start with a long open window starting from the moment of the rising edge of

•

RSTN and the watchdog period setting in the register WD_CTRL will be changed to the respective default

value.

5.5.8

Fail-Safe Mode -> Restart Mode

This transition is similar to device from Sleep Mode to Restart Mode and consequence of a detection of wake-

up event by the device. This transition is used to ramp up VCC1 after a wake in a defined way.

Prerequisites:

•

Device in Fail-Safe Mode

Triggering Events:

•

A wake-up event on WKx, TSD2 (released over temperature TDS2 after t_TSD2).

Bridge Driver Low Side short circuit detected during VS/VSINT overvoltage braking mode or in parking

braking mode.

Note:

After leaving Fail-Safe Mode, the FAILURE bit in DEV_STAT register is set.

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BLDC Driver

System Features

5.6

Reaction on Detected Faults

The device can react at some critical events either signalling the specific failure or changing the device mode.

The chapter describes actions taken from the device in case of critical events in particular related the device

mode change.

5.6.1

Stay in Current State

The following failures will not trigger any device mode changes, but will indicate the failures by an INTN event

(depending from the Interrupt Masking) and in dedicated status registers:

•

Failures in Bridge Driver and/or Charge Pump

5.6.2

Transition into Restart Mode

The Restart Mode can be entered in case of failure as shown in following figure.

VCC1 over voltage

(depend from VCC1_OV_MOD setting)

Restart Mode

(RO pin is asserted)

Sleep Mode entry without any

wake source enabled

VCC1

ON/

CP

OFF

BD

OFF

Watchdog Failure

ramping

Cyc.

Wake

OFF

VCC1 Under voltage

CSA

OFF

WD

OFF

Figure 12 Move into Restart Mode

Prerequisites

•

In case of wake-up event from Sleep Mode or Fail Safe Mode

In case of Normal Mode

In case of Stop Mode

Trigger Events

•

VCC1 Undervoltage in case of Normal Mode or Stop Mode.

Watchdog trigger failure in case of Normal Mode or Stop Mode.

VCC1 Overvoltage (based on VCC1_OV_MOD) in case of Normal Mode or Stop Mode.

Sleep Mode entry without any wake-up sources enabled in Normal Mode or Stop Mode.

Note

•

None

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BLDC Driver

System Features

5.6.3

Transition into Fail-Safe Mode

The Fail-Safe Mode can be entered in case of critical event as shown in the following figure.

After 4x consecutive VCC1

After 4x consecutive

under voltage events

Watchdog failure

(if VS_INT > VS_INT_UV)

VCC1 over voltage

(depend from VCC1_OV_MOD setting)

Fail-Safe Mode

TSD2 event

VCC1

OFF

CP

OFF

BD

OFF

Cyc.

Wake

OFF

VCC1 Short to GND

CSA

OFF

WD

OFF

Figure 13 Move into Fail-Safe Mode

Prerequisites:

•

Critical events on VCC1

Watchdog trigger failures

Trigger Events:

•

Device thermal shutdown (TSD2) (see also Chapter 10.8.3).

VCC1 is shorted to GND (see also Chapter 10.7).

VCC1 over voltage (based on VCC1_OV_MOD).

4 consecutive Watchdog trigger failure.

4 consecutive VCC1 under voltage events.

5.7

Wake Features

Following wake sources are implemented in the device:

•

Static Sense: WKx inputs are permanently active as wake sources.

Cyclic Wake: wake controlled by internal timers, wake inputs are not used for cyclic wake.

5.7.1

Cyclic Wake

For the cyclic wake feature one timer is configured as internal wake-up source and will periodically trigger an

interrupt on INTN in Normal Mode and Stop Mode. During Sleep Mode, the timer triggers and wakes up the

device again. The device enters via Restart Mode the Normal Mode.

The correct sequence to configure the cyclic wake is shown in Figure 14. The sequence is as follows:

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BLDC Driver

System Features

Cyclic Wake Configuration

Disable Timer1 and Timer2 as a wake

To avoid unintentional interrupts

source in TIMER_CTRL

No interrupt will be generated,

if the timer is not enabled as a wake source

Select Timer1 or Timer2 as a wake

source in TIMER_CTRL

Periods: 10, 20, 50, 100, 200ms, 1s, 2s

On-times: any

(OFF/LOW & OFF/HIGH are not allowed)

Select Timer Period and any

On-Time in TIMER_CTRL

Cyclic Wake starts / ends by

setting / clearing On-time

INTN is pulled low at every rising

edge of On-time except first one

Figure 14 Cyclic Wake: Configuration and Sequence

Note:

The on-time is only used to enable the cyclic wake function regardless of the value of the on time, i.e.

the on time value has no meaning to the cyclic wake function as long as it is not ‘000’ or ‘110’ or ‘111’.

The cyclic wake function will start as soon as the on-time is configured. An interrupt is generated for every start

of the on-time except for the very first time when the timer is started.

5.7.2

Internal Timers

Two integrated timers can be used to control the below features:

Cyclic Wake, i.e. to wake up the microcontroller periodically in Normal Mode, Stop Mode and Sleep Mode.

•

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BLDC Driver

System Features

5.8

VS Supply Multiplexing

VMAX SWITCH

+

-

1

0

VSINT

VS

INTERNAL SUPPLY

MUX

Figure 15 VS Supply Multiplexing

The internal supply voltage is multiplexed from VSINT and VS, choosing continuously the larger of both. In

case of transient low VBAT, the buffered supply voltage takes over the internal supply, avoiding loss of power.

Note:

Only the internal digital logic of the device is supplied by the VMAX SWITCH. In case of a power loss

of either VS or VSINT, the internal register values will not be lost.

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BLDC Driver

Voltage Regulator 1

6

Voltage Regulator 1

VCC1 is a voltage reference for the current sense amplifier, for the SPI interface and for the PWM inputs. VCC1

has its own internal voltage regulator and may not be connected to the output of another voltage regulator.

6.1

Block Description

VCC1

VSINT

Vref

1

Overtemperature

Shutdown

State

Machine

Bandgap

Reference

INH

GND

Figure 16 Module Block Diagram

Functional Features

•

5 V low-drop voltage regulator.

Undervoltage monitoring with adjustable reset level and VCC1 undervoltage prewarning (refer to

Chapter 10.6 and Chapter 10.7 for more information).

•

Short circuit detection and switch off with undervoltage fail threshold, device enters Fail-Safe Mode.

Effective capacitance must be ≥ 1 µF at nominal voltage output for stability. A 2.2 µF ceramic capacitor

(MLCC) is recommended for best transient response.

•

Output current capability up to I_VCC1,lim.

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BLDC Driver

Voltage Regulator 1

6.2

Functional Description

The Voltage Regulator 1 (=VCC1) is “ON” in Normal Mode and Stop Mode and is disabled in Sleep Mode and in

Fail-Safe Mode. The regulator can provide an output current up to I_VCC1,lim

.

For low-quiescent current reasons, the output voltage tolerance is decreased in Stop Mode because only the

less accurate low-power mode regulator will be active for small loads. If the load current on VCC1 exceeds the

selected threshold (I_{VCC1,Ipeak1,r}or I_{VCC1,Ipeak2,r}) then the high-power mode regulator will be also activated to

support an optimum dynamic load behavior. The current consumption will then increase (approx. 2.8 mA

additional quiescent current). The device mode stays unchanged.

If the load current on VCC1 falls below the selected threshold (I_{VCC1,Ipeak1,f}or I_{VCC1,Ipeak2,f}), then the low-quiescent

current mode is resumed again by disabling the high-power mode regulator.

Both regulators (low-power mode and high-power mode) are active in Normal Mode.

Two different active peak thresholds can be selected via SPI:

•

I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current

consumption in Stop Mode.

•

I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current

consumption in Stop Mode.

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BLDC Driver

Voltage Regulator 1

6.3

Electrical Characteristics

Table 12 Electrical Characteristics

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified).

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Output Voltage including Line V_CC1,out1

and Load Regulation

4.9

5.0

–

5.1

V

¹⁾Normal Mode; 10 µA < P_6.3.1

I_VCC1< 150 mA;

Output Voltage including Line V_CC1,out2

and Load Regulation

(Full Load Current Range)

4.9

5.1

¹⁾Normal Mode;

P_6.3.2

6 V < V_SINT< 28 V;

10 µA < I_VCC1< 250 mA

²⁾Normal Mode; 20 mA P_6.3.3

< I_VCC1< 80 mA;

Output Voltage including Line V_CC1,out3

and Load Regulation

4.95

5.05

(Higher Accuracy Rage)

8 V < V_SINT< 18 V;

25°C < T_j< 150°C

Output Voltage including Line V_CC1,out4

and Load Regulation

4.9

5.05 5.2

V

Stop Mode;

10 µA < I_VCC1< I_VCC1,Ipeak

P_6.3.4

(low-power mode)

Output Drop Voltage

V_CC1,d1

V_CC1,d2

–

200

300

400

500

mV

mA

I_VCC1= 50 mA,

V_SINT= 5 V

P_6.3.9

I_VCC1= 150 mA,

V_SINT= 5 V

2)

P_6.3.10

P_6.3.17

VCC1 Active Peak Threshold 1 I_{VCC1,Ipeak1,r}

(Transition threshold

3.25 5.0

I

rising;

CC1

V_SINT= 13.5 V;

between low-power and high-

power mode regulator)

I_PEAK_TH = ‘0’

2)

VCC1 Active Peak Threshold 1 I_{VCC1,Ipeak1,f}1.2

(Transition threshold

between high-power and low-

power mode regulator)

1.7

–

mA

I

falling;

P_6.3.18

P_6.3.19

P_6.3.20

CC1

V

_SINT= 13.5V;

I_PEAK_TH = ‘0’

2)

VCC1 Active Peak Threshold 2 I_{VCC1,Ipeak2,r}

(Transition threshold

between low-power and high-

power mode regulator)

6

5

20

15

500

I

rising;

CC1

V

_SINT= 13.5 V;

I_PEAK_TH = ‘1’

2)

VCC1 Active Peak Threshold 2 I_{VCC1,Ipeak2,f}

(Transition threshold

between high-power and low-

power mode regulator)

–

I

falling;

CC1

V

_SINT= 13.5V;

I_PEAK_TH = ‘1’

Overcurrent Limitation

I_VCC1,lim

260 360

current following out of P_6.3.21

pin, VCC1= 0V ²⁾

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BLDC Driver

Voltage Regulator 1

Table 12 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified).

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

2)

MinimumOutputCapacitance C_VCC1,min

for stability

1³⁾

–

µF

P_6.3.22

P_6.3.23

2)

Maximum Output

Capacitance

C_VCC1,max

–

47

µF

1) In Stop Mode, the specified output voltage tolerance applies when I_VCC1has exceeded the selected active peak

threshold (I_{VCC1,Ipeak1,r}or I_{VCC1,Ipeak2,r}) but with increased current consumption.

2) Not subject to production test, specified by design.

3) Value is meant to be an effective value at rated output voltage level.

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BLDC Driver

High-Voltage Wake Input

7

High-Voltage Wake Input

The WK4 pin is used to wake up the device.

7.1

Block Description

Internal Supply

I_{PU_WK}

WKx

+

-

t_WK

I_{PD_WK}

V_Ref

Logic

Figure 17 Wake Input Block Diagram

Features

•

High-Voltage inputs with a 3 V (typ.) threshold voltage.

Wake-up capability for power saving modes.

Edge sensitive wake feature low to high and high to low.

Pull-up and Pull-down current sources, configurable via SPI.

In Normal Mode and Stop Mode the level of the WKx pin can be read via SPI.

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BLDC Driver

High-Voltage Wake Input

7.2

High-Voltage Wake Function

7.2.1

Functional Description

The wake inputs pin are edge-sensitive inputs with a switching threshold of typically 3 V. Both transitions, high

to low and low to high, result in a signalization by the device. The signalization occurs either in triggering the

interrupt in Normal Mode and Stop Mode or by a wake up of the device in Sleep Mode and Fail-Safe Mode.

A filter time tFWKx is implemented to avoid an unintentional wake-up due to transients or EMC disturbances

in static sense configuration.

The filter time (tFWKx) is triggered by a level change crossing the switching threshold and a wake signal is

recognized if the input level will not cross again the threshold during the selected filter time.

Figure 18 shows a typical wake-up timing and filtering of transient pulses.

V_WKx

V_WKTh,f

V_WKth,f

t

V_INTN

t_FWK

t_INTN

No Wake Event

Wake Event

Figure 18 Wake-up Filter Timing for Static Sense

The wake-up capability for the WKx pin can be enabled or disabled via SPI command.

A wake event via the WKx pin can always be read in the register WK_STAT.

The actual voltage level of the WKx pin (low or high) can always be read in Normal Mode, Stop Mode and Init

Mode in the register WK_LVL_STAT.

7.2.2

Wake Input Configuration

To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure

integrated current sources via the SPI register WK_CTRL.

Table 13 Pull-Up / Pull-Down Resistor

WKx_PUPD_ WKx_PUPD_ Current Sources Note

1

0

no current

source

WK input is floating if left open (default setting)

0

1

pull-down

WK input internally pulled to GND

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TLE9185QX

BLDC Driver

High-Voltage Wake Input

Table 13 Pull-Up / Pull-Down Resistor (cont’d)

WKx_PUPD_ WKx_PUPD_ Current Sources Note

1

0

1

pull-up

WK input internally pulled to internal 5V supply

Automatic

switching

If a high level is detected at the WK input the pull-up source is

activated, if low level is detected the pull down is activated.

Note:

If a WK input is not used, the respective WK input must be tied to GND on board to avoid unintended

floating state of the pin.

One additional configuration is related the filter time of each Wake-up module. The bits WK_FILT permit to set

the filter time in static sensing.

Note:

When the device mode is changed to normal (from INIT), in case of static sense, if the WK pin is set,

the WK_STAT register is set in this time (also the interrupt pin).

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BLDC Driver

High-Voltage Wake Input

7.3

Electrical Characteristics

Table 14 Electrical Characteristics

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

WK4 Input Pin Characteristics

Wake-up/monitoring V_{WKx_th,f}2.5

threshold voltage

falling

3

3.5

V

without external

serial resistor R_S

P_10.3.1

P_10.3.2

P_10.3.3

Wake-up/monitoring V_{WKx_th,r}

threshold voltage

rising

3

3.5

0.6

4

without external

serial resistor R_S

Threshold hysteresis

V_{WKx_th,hys}0.4

0.85

without external

serial resistor R_S

WK pin Pull-up Current I_{PU_WKx}

-20

3

-10

10

-3

µA

V_WKx= 4 V

P_10.3.4

P_10.3.5

WK pin Pull-down

Current

I_{PD_WKx}

20

V_WKx= 2.5 V

Input leakage current I_LK,lx

-2

2

µA

0 V < V_WKx< 40 V;

Pull-up / Pull-down

disabled

P_10.3.6

Timing

1)

Wake-up filter time 1 t_FWK1

12

50

16

64

22

80

µs

P_10.3.16

P_10.3.17

Wake-up filter time 2 t_FWK2

1) Not subject to production test, tolerance defined by internal oscillator tolerance.

Datasheet

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TLE9185QX

BLDC Driver

Interrupt Function

8

Interrupt Function

8.1

Block and Functional Description

V_cc1

Time

out

INTN

Interrupt logic

INTERRUPT BLOCK.VSD

Figure 19 Interrupt Block Diagram

The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is

designed as a push/pull output stage as shown in Figure 19. An interrupt is triggered and the INTN pin is pulled

low (active low) for t_INTNin Normal Mode and Stop Mode and it is released again once t_INTNis expired. The

minimum high-time of INTN between two consecutive interrupts is t_INTND. An interrupt does not cause a device

mode change.

Two different interrupt generation methods are implemented:

•

Interrupt Mask: One dedicated register (INT_MASK) is intended to enable or disable set of interrupt

sources. The interrupt sources follow the SPI Status Information Field.

In details:

–

SUPPLY_STAT: “OR” of all bits on SUP_STAT register except POR, VCC1_UV, VCC1_SC, VCC1_OV

TEMP_STAT: “OR” of all bits on THERM_STAT register except TSD2

BD_STAT: “OR” of all bits on DSOV register

SPI_CRC_FAIL: or between SPI_FAIL and CRC_FAIL bits on DEV_STAT register.

•

Wake-up events: all wake-up events stored in the wake status SPI register WK_STAT only in case the

corresponding input was configured as wake-up source.

The wake-up sources are:

–

via WK pin

via TIMERx (cyclic wake)

via LSx_DSOV_BRK if any of the brake-feature is enabled

The methods are both available at the same time.

Note:

The errors which will cause Restart or Fail-Safe Mode (VCC1_UV, VCC1_SC, VCC1_OV, TSD2) are the

exceptions of an INTN generation. Also the bit POR will not generate interrupts. If the above

mentioned bits are not cleared after the device is back in Normal Mode or Stop Mode, the INTN is

periodically generated (Register based cyclic interrupt generation).

Note:

Periodical interrupts are only generated by CRC fail and SPI fail from DEV_STAT register.

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BLDC Driver

Interrupt Function

Note:

During Restart Mode the SPI is blocked and the microcontroller is in reset. Therefore the INTN will not

be in Restart Mode, which is the same behavior in Fail-Safe Mode or Sleep Mode.

In addition to this behavior, INTN will be triggered when Stop Mode is entered and not all wake source bits

were cleared in the WK_STAT register and also the LSx_DSOV_BRK bits in the DSOV register..

The SPI status registers are updated at every falling edge of the INTN pulse. All interrupt events are stored in

the respective register until the register is cleared via SPI command. A second SPI read after reading out the

respective status register is optional but recommended to verify that the interrupt event is not present

anymore. The interrupt behavior is shown in Figure 20.

The INTN pin is also used during Init Mode to select the Software Development Mode entry. See Chapter 5.2

for further information.

In case of pending INTN event (SPI Status registers are not cleared after INTN event), additional periodical

INTN events are generated as shown in Figure 21.

The periodical INTN events generation can be disabled via SPI command using INTN_CYC_EN bit.

WKx

INTN

t_INTD

t_INTN

Update of

WK_STAT register

Update of

WK_STAT register

optional

no WK

SPI

Read & Clear

WK_STAT

contents

WKx

no WK

SPI

Read & Clear

No SPI Read & Clear

Command sent

WK_STAT

contents

WKx

no WK

Figure 20 Interrupt Signalization Behavior

Note:

For two or more interrupt events at the same time, when INTN pin is low the same time, it will not

start multiple toggling.

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BLDC Driver

Interrupt Function

WKx

INTN

t_INTN

t_{INTN_PULSE}

Update of

WK_STAT register

SPI

Read & Clear

No SPI Read & Clear

Command sent

No SPI Read & Clear

Command sent

WK_STAT

contents

WKx

Figure 21 Interrupt Signalization Behavior in case of pending INTN events

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BLDC Driver

Interrupt Function

8.2

Electrical Characteristics

Table 15 Electrical Characteristics

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Interrupt Output; Pin INTN

1)

INTN High Output Voltage V_INTN,H0.8 ×

–

V

I

= -2 mA;

P_11.2.1

P_11.2.2

INTN

V_CC1

INTN = off

1)

INTN Low Output Voltage V_INTN,L

–

0.2 ×

I

= 2mA;

INTN

V_CC1

INTN = on

2)

INTN Pulse Width

t_INTN

80

100

120

µs

P_11.2.3

P_11.2.4

INTN Pulse Minimum

Delay Time

t_INTND

²⁾between

consecutive pulses

Pulse in case of pending t_{INTN_PUL}

4

5

6

ms

²⁾between

P_11.2.5

INTN

consecutive pulses

SE

SDM Select; Pin INTN

Config Pull-up Resistance R_SDM

30

50

60

64

100

80

kΩ

V_INTN= 5 V

2)

P_11.2.6

P_11.2.7

Config Select Filter Time t_{SDM_F}

µs

1) Output Voltage Value also determines device configuration during Init Mode.

2) Not subject to production test, tolerance defined by internal oscillator tolerance.

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

9

Gate Drivers

The TLE9185QX integrates six floating gate drivers capable of controlling a wide range of N-channel MOSFETs.

They are configured as three high-sides and three low-sides, building three half-bridges.

VCP

VS

GHx

Highside

Gate-Driver

V_DSMONTH

Current-Steering

DACs

SHx

High-Speed

Comparators

VCP

GLx

Lowside

Gate-Driver

V_DSMONTH

Current-Steering

DACs

SL

Figure 22 Half-bridge gate driver - Block diagram

This section describes the MOSFET control in static activation and during PWM operation.

Note:

PWMx mentioned in this chapter refer to the PWMx pins and signal used by the bridge driver to

control the external MOSFETs.

9.1

MOSFET control

Depending on the configuration bits HBxMODE[1:0] (refer to HBMODE), CPEN, each high-side and low-side

MOSFETs can be:

•

Kept off with the passive discharge.

Kept off actively.

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TLE9185QX

BLDC Driver

Gate Drivers

•

Activated (statically, no PWM, HBx_PWM_EN = 0).

Activated in PWM mode (HBx_PWM_EN = 1).

Refer to Table 16 for details.

Table 16

CPEN

Half-bridge mode selection

HBxMODE[1:0]¹⁾Configuration of HSx/LSx¹⁾

CPEN = 0

CPEN = 1

Don’t care

00_B

All MOSFETs are kept off by the passive discharge

HBx MOSFETs are kept off by the passive discharge

LSx MOSFET is ON, HSx MOSFET is actively kept OFF

HSx MOSFET is ON, LSx MOSFET is actively kept OFF

LSx and HSx MOSFETs are actively kept OFF with IHOLD

01_B

10_B

CPEN = 1

11_B

1) x = 1 … 3

9.2

Static activation

In this section, we consider the static activation of the high-side and low-side MOSFET of the half-bridge x:

HBx_PWM_EN= 0 (in ST_ICHG) and CPEN = 1.

The low-side or high-side MOSFET of HBx is statically activated (no PWM) by setting HBxMODE[1:0] to

respectively (0,1) or (1,0).

The configured active cross-current protection and the Drain-Source overvoltage blank times for the Half-

Bridge x are noted t_{HBxCCP ACTIVE}and t_{HBxBLANK ACTIVE}

.

The charge and discharge currents applied to the static controlled Half-Bridge x are noted ICHGSTx

(ST_ICHG).

IHARDOFF is the maximum current that the gate drivers can sink (150 mA typ.). This current is used to keep a

MOSFET off, when the opposite MOSFET of the same half-bridge is being turned on. This feature reduces the

risk of parasitic cross-current conduction.

ICHGSTx is the current sourced, respectively sunk, by the gate driver to turn-on the high-side x or low-side x.

ICHGSTx is configured in the control register ST_ICHG.

Table 17

Static charge currents

ICHGSTx[3:0]

Nom. charge current

[mA]

Nom. discharge current

[mA]

Max. deviation to typ. values

0000_B

0001_B

0010_B

0011_B

0100_B

0101_B

0110_B

0111_B

0.5 (I_CHG0

1.8 (I_CHG4

4.7 (I_CHG8

)

0.5 (I_DCHG0

1.8 (I_DCHG4

4.7 (I_DCHG8

)

+/- 60%

+/- 60 %

+/- 40 %

+/- 40%

9.4 (I_CHG12

15.3 (I_CHG16

23 (I_CHG20

)

9.4 (I_DCHG12)

)

15.1 (I_DCHG16

22.5 (I_DCHG20

30.9 (I_DCHG24

40.8 (I_DCHG28

)

31.6 (I_CHG24

41.6 (I_CHG28

)

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BLDC Driver

Gate Drivers

Table 17

Static charge currents (cont’d)

ICHGSTx[3:0]

Nom. charge current

[mA]

Nom. discharge current

[mA]

Max. deviation to typ. values

1000_B

1001_B

1010_B

1011_B

1100_B

1101_B

1110_B

1111_B

52.5 (I_CHG32

63.6 (I_CHG36

75.2 (I_CHG40

87.1 (I_CHG44

99.5 (I_CHG48

)

51.5 (I_DCHG32

62.4 (I_DCHG36

73.7 (I_DCHG40

85.5 (I_DCHG44

97.7 (I_DCHG48

)

+/- 30 %

112.2 (I_CHG52

125.3 (I_CHG56

)

110.8 (I_DCHG52

124.5 (I_DCHG56

138.7 (I_DCHG60

)

139 (I_CHG60

)

IHOLD is the hold current used to keep the gate of the external MOSFETs in the desired state. This parameter

is configurable with the IHOLD control bit in GENCTRL.

If the control bit IHOLD = 0:

•

A MOSFET is kept ON with the current I_CHG15

.

A MOSFET is kept OFF with the current I_DCHG15

.

If the control bit IHOLD = 1:

•

A MOSFET is kept ON with the current I_CHG20

.

A MOSFET is kept OFF with the current I_DCHG20

.

9.2.1

Static activation of a high-side MOSFET

Turn-on with cross-current protection

If LSx is ON (HBxMODE[1:0] = 01_B), before the activation of HSx (HBxMODE[1:0] = 10_B) then the high-side

MOSFET is turned on after a cross-current protection time (refer to Figure 23):

•

After the CSN rising edge and for the duration t_{HBxCCP ACTIVE}:

–

The high-side MOSFET is kept OFF with the current -ICHGSTx.

The gate of the low-side MOSFET is discharged with the current -ICHGSTx.

At the end of t_{HBxCCP ACTIVE}and for the duration t_{HBxBLANK ACTIVE}+ t_FVDS

:

–

The gate of the high-side MOSFET is charged with the current ICHGSTx.

Low-side MOSFET is kept OFF with the current -IHARDOFF (hard off phase).

At the end of t_FVDS

:

–

The drive current of the high-side MOSFET is reduced to IHOLD.

The drive current of the low-side MOSFET is set to -IHOLD.

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SPI Frame accepted

Turn on HSx

CSN

Previous State

HSx OFF

LSx ON



New State

HSx ON

LSx OFF

t

VS

tHBxCCP

Active

tHBxBLANK

Active

IGHx

tFVDS

ICHGSTx

HSx

GHx

SHx

0

t

IGHx

HSx internal

drive signal

ICHGSTx

LSx

GLx

SL

IHOLD

-IHOLD

IGLx

t

-ICHGSTx

IGLx

t

-ICHGSTx

LSx internal

drive signal

IHOLD

-IHOLD

t

-ICHGSTx

Hard off

-IHARDOFF

Figure 23 Turn-on of a high-side MOSFET with cross-current protection

Note:

The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are

executed with a delay of up to 3 µs after the CSN rising edge.

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Turn-on without cross-current protection

If LSx is OFF (HBxMODE[1:0] = 11_B), before the activation of HSx (HBxMODE[1:0] = 10_B), then the high-side

MOSFET is turned on without cross-current protection (refer to Figure 24):

•

right after the CSN rising edge and for a duration t_{HBxBLANK ACTIVE}+ t_FVDS:

–

The gate of the high-side MOSFET is charged with the current ICHGSTx.

The low-side MOSFET is kept OFF with the current -IHARDOFF.

•

At the end of t_FVDS

:

–

The drive current of the high-side MOSFET is reduced to IHOLD.

The drive current of the low-side MOSFET is set to -IHOLD.

SPI Frame accepted

Turn on HSx

CSN

Previous State

HSx OFF

LSx OFF



New State

HSx ON

LSx OFF

t

tHBxBLANK

Active

IGHx

tFVDS

ICHGSTx

0

t

HSx internal

drive signal

ICHGSTx

VS

IHOLD

-IHOLD

t

HSx

GHx

IGHx

IGLx

0

SHx

t

LSx

GLx

SL

IGLx

LSx internal

drive signal

IHOLD

-IHOLD

t

Hard off

-IHARDOFF

Figure 24 Turn-on of a high-side MOSFET without cross-current protection

Note:

The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are

executed with a delay of up to 3 µs after the CSN rising edge.

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9.2.2

Static activation of a low-side MOSFET

The description of the static activation of a low-side x differs from the description of Chapter 9.2.1 only by

exchanging high-side x and low-side x.

9.2.3

Turn-off of the high-side and low-side MOSFETs of a half-bridge

When the TLE9185QX receives a SPI command to turn-off both the high-side and low-side MOSFETs of the half-

bridge x (HBxMODE[1:0] = (0,0) or (1,1)):

•

The gate of HSx and LSx are discharged with the current -ICHGSTx for the duration t_{HBxCCP ACTIVE}(Figure 25).

At the end of t_{HBxCCP ACTIVE}, the drive current of HSx and LSx are reduced to -IHOLD.

SPI Frame accepted

Turn off HSx and LSx

VS

CSN

HSx

t

GHx

IGHx

SHx

0

LSx

t

GLx

-ICHGSTx

IGLx

SL

HSx internal

drive signal

tHBxCCP

Active

IHOLD

-IHOLD

t

-ICHGSTx

IGLx

LSx internal

drive signal

t

-IHOLD

-ICHGSTx

Figure 25 Turn-off of the high-side and low-side MOSFETs of a half-bridge

Note:

The CSN rising edge must be synchronized with the device logic. Therefore SPI commands are

executed with a delay of up to 3 µs after the CSN rising edge.

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9.3

PWM operation

The half-bridge can be controlled in PWM using either three or six PWM inputs.

The TLE9185QX offers the possibility to detect the active and the freewheeling (FW) MOSFET in each half-

bridge.

9.3.1

Determination of the active and freewheeling MOSFET

If EN_GEN_CHECK = 1, right before each MOSFET activation, the device detects which MOSFET of the half-

bridge is the active MOSFET and which MOSFET is the free-wheeling (FW) MOSFET:

•

If VSHx > VS - VSHH: The high-side MOSFET is the FW MOSFET and the low-side MOSFET is the active

MOSFET.

If VSHx < VSHL: Then the low-side MOSFET is the FW MOSFET and the high-side MOSFET is the active

MOSFET.

If VSHL < VSHx < VSHH: No clear distinction between the active FW MOSFET and the active MOSFET. The

next MOSFET to be turned on is turned on as if it was the active MOSFET.

If EN_GEN_CHECK = 0, the detection of the active and FW MOSFET is disabled. The PWM MOSFET is considered

as the active MOSFET.

Figure 26 shows the detection of the active and of the FW MOSFET.

HS and LS off

Freewheeling through

high-side MOSFET body diode

VSHx > VSHH

HS and LS are off

Freewheeling through

low-side MOSFET body diode

VSHx < VSHL

HS = FW MOSFET

LS = FW MOSFET

LS = Active MOSFET

HS = Active MOSFET

VCP

VS

GHx

Highside

Gate-Driver

SHx

VSHH

High-Speed

Comparators

High-Speed

Comparators

VSHL

VCP

GLx

Lowside

Gate-Driver

SL

Figure 26 Detection of the active and FW MOSFET - Principle

9.3.2

Configurations in PWM mode

The following sections describe the different control schemes in PWM mode.

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BLDC Driver

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Active gate control (AGC)

The active gate control is configured by the control bits AGC[1:0]. The control scheme during the pre-charge

and pre-discharge phases of:

•

The active MOSFET (EN_GEN_CHECK=1).

The PWM MOSFET (EN_GEN_CHECK=0).

can be selected.

The following settings are possible:

•

Adaptive gate control (AGC[1:0] = (1,0) or (1,1), see GENCTRL): In this mode a pre-charge current and a pre-

discharge current are applied to the gate of the controlled MOSFET. These currents are used to regulate

effective the turn-on and turn-off delays to the respective target values.

•

No adaptive gate control (AGC[1;0] = (0,0)): in this mode, the pre-charge and pre-discharge phases are

deactivated.

No adaptive gate control (AGC[1;0] = (0,1)). In this mode:

–

During the pre-charge phase, the MOSFET is discharged with the configured current IPCHGINIT

(HB_PCHG_INIT).

–

During the pre-discharge phase, the MOSFET is discharged with the configured current IPDCHGINIT

(HB_PCHG_INIT).

Note:

It is recommended to configure tPCHGx < tHBxBLANK Active and tPDCHGx < tHBxCCP Active (Refer to

TPRECHG and CCP_BLK) independently from the AGC settings.

Active free-wheeling (AFW)

The active free-wheeling is activated for HBx if these conditions are fulfilled:

•

AFWx = 1 (HBMODE)

HBx_PWM_EN = 1 (HBMODE)

PWM_NB = 0

If AFWx = 1, a cross-current protection time is applied to HBx (set by CCP_BLK) during the PWM operation.

If AFWx = 0, no cross current protection is applied to HBx during the PWM operation.

The active free-wheeling reduces the power dissipation of the free-wheeling MOSFET. If an active MOSFET is

OFF, the opposite MOSFET of the same half-bridge is actively turned on. Refer to Figure 30 and Figure 31.

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Post-charge

A post-charge is initiated if POCHGDIS is set to 0 (GENCTRL) to reach the minimum MOSFET Rdson:

•

POCHGDIS = 0: After the charge phase, the control signal for the charge current of LSx is increased by one

current step at every bridge driver clock cycle (BDFREQ) to ICHGMAXx. Refer to Figure 27

•

POCHGDIS = 1: The post-charge phase is disabled. The charge current is kept to the ICHGx

Turn-on of:

Turn-off of:

PWM MOSFET if EN_GEN_CHECK = 0

Active MOSFET if EN_GEN_CHECK =1

PWM MOSFET if EN_GEN_CHECK = 0

Active MOSFET if EN_GEN_CHECK =1

Precharge

Post-charge

IGS

tPCHGx

Predischarge

ICHGMAXx

IPRECHGx

tPDCHGx

ICHGx

0

t

- IDCHGx

tBLANK active

- IPREDCHGx

tHBxCPP active

Figure 27 PWM overview - AGC = 10_Bor 11_B, POCHGDIS=0 (post-charge enabled)

Turn-on of:

Turn-off of:

PWM MOSFET if EN_GEN_CHECK = 0

Active MOSFET if EN_GEN_CHECK =1

PWM MOSFET if EN_GEN_CHECK = 0

Active MOSFET if EN_GEN_CHECK =1

Precharge

IGS

tPCHGx

Predischarge

tPDCHGx

IPRECHGx

ICHGx

0

t

- IDCHGx

tBLANK Active

- IPREDCHGx

tHBxCPP Active

Figure 28 PWM overview - AGC = 10_Bor 11_B, POCHGDIS=1 (post-charge disabled)

Table 18

Abbreviation

Suffix x

Abbreviations for adaptive turn-on and turn-off phases in PWM configuration

Definition

Related to the half-bridge x.

VGS_HSx

IGS_HSx

Gate-Source voltage of high-side MOSFET x.

Gate current of high-side MOSFET x.

IGS_HSx is positive when the current flows out of GHx.

VGS_LSx

IGS_LSx

Gate-Source voltage of low-side MOSFET x.

Gate current of low-side MOSFET x.

IGS_LSx is positive when the current flows out of GLx.

tPWM_SYNCH

Synchronization delay between external and internal PWM signal.

tHBxCCP ACTIVE Active cross-current protection time of HBx. See control register CCP_BLK.

tHBxBLANK ACTIVE Active Drain-source overvoltage blank time of HBx. See control register and CCP_BLK.

tHBxCCP FW

Freewheeling cross-current protection time of HBx. See control register CCP_BLK.

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BLDC Driver

Gate Drivers

Table 18

Abbreviations for adaptive turn-on and turn-off phases in PWM configuration (cont’d)

Abbreviation

tHBxBLANK FW

Definition

Freewheeling drain-source overvoltage blank time of HBx. See control register and

CCP_BLK.

PWMz

External PWM signal applied to the input pin PWMz.

ICHGMAXx

Maximum drive current of the half-bridge x during the pre-charge and pre-discharge

phases. See control register HB_ICHG_MAX.

IPRECHGx and IPREDCHGx are limited to ICHGMAXx.

IPRECHGx

Pre-charge current sourced by the gate driver to the active MOSFET of the half-bridge

x during tPCHGx (TPRECHG).

Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL).

IPRECHGx is clamped between I_CHG0(0.5 mA typ.) and ICHGMAXx.

IPCHGINITx

IPREDCHGx

Initial value of IPRECHGx. Refer to HB_PCHG_INIT.

Pre-discharge-current sunk by the gate driver mapped to the half-bridge x during

tPDCHGx.

Internal and self-adaptive parameter (if AGC[1:0] = (1,0) or (1,1), GENCTRL).

IPREDCHGx is clamped between I_DCHG0(0.5 mA typ.) and ICHGMAXx.

IPDCHGINITx

ICHGx

Initial value of IPREDCHGx. Refer to HB_PCHG_INIT.

Current sourced by the gate driver to the active MOSFET of the half-bridge x during the

charge phase. See control register HB_ICHG.

IDCHGx

Current sunk by the gate driver to turn-off the active MOSFET of the half-bridge x

during the discharge phase. See control register HB_ICHG.

ICHGFWx

tPCHGx

tPDCHGx

Current sourced or sunk by the gate driver to turn on / turn off the freewheeling

MOSFET of the half-bridge x . See control register HB_ICHG.

Duration of the pre-charge phase of half-bridge x.

tPCHGx is configurable by SPI. See control register TPRECHG.

Duration of the pre-discharge phase of half-bridge x.

tPDCHGx is configurable by SPI. See control register TPRECHG.

tDONx

tDOFFx

IHOLD

Turn-on delay of the active MOSFET of HBx.

Turn-off delay of the active MOSFET of HBx.

Hold current sourced or sunk by the gate driver to keep the MOSFET in the desired

state. See IHOLD control bit in GENCTRL.

IHARDOFF

TFVDS

IHARDOFF is the maximum current that the gate drivers can sink. It corresponds to the

discharge current when IDCHGx[5:0] = 63_D(150 mA typ.).

Drain-Source overvoltage filter time. See LS_VDS.

9.3.3

PWM operation with 3 PWM inputs

Each half bridge are controlled by one input if PWM_NB = 0 (see CSA) and HBx_PWM_EN (see HBMODE):

•

PWM1/CRC controls HB1

PWM3 controls HB2

PWM5 controls HB3

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BLDC Driver

Gate Drivers

CP

VS

HS1

PWM1

PWM2

µC_PWM1

µC_PWM3

µC_PWM5

LS1

SL

CP

VS

PWM3

PWM4

HS2

CP

LS2

SL

CP

VS

PWM5

PWM6

HS3

CP

SL

LS3

Figure 29 Half-bridge PWM control with three PWM inputs, PWM_NB = 0

Table 19

Half-bridge PWM settings with 3 PWM inputs

PWM_NB HBxPWM_ HBxMODE¹⁾AFW

Half-bridge x settings¹⁾

EN¹⁾

0

Don’t care 00_B

Don’t care

0

LSx and HSx MOSFETs are kept OFF by the passive

discharge

1

01_B

10_B

PWM signal applied to LSx

PWM signal = 1: LSx, ON, HSx OFF

PWM signal = 0: LSx OFF, HS x OFF

0

1

PWM signal applied to HSx

PWM signal= 1: HSx, ON, LSx OFF

PWM signal = 0: HSx OFF, LS x ON

0

Don’t care 11_B

Don’t care

LSx and HSx MOSFETs are actively kept OFF

1) x = 1 to 3

9.3.3.1 Control signals with active free-wheeling (AFWx = 1)

This section describes the MOSFET control signals with active freewheeling and HS PWM:

•

The HS PWM MOSFET is the active MOSFET (Chapter 9.3.3.1.1).

The HS PWM MOSFET is the free-wheeling MOSFET (Chapter 9.3.3.1.2).

9.3.3.1.1

The PWM MOSFET is the active MOSFET

This section shows the control signals of the MOSFET when the PWM is the active MOSFET.

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BLDC Driver

Gate Drivers

tPWM_SYNCH

External

PWM signal

t

VSHx < VSHL right before activation of HSx

HSx detected as active MOSFET

Synchronized intern.

PWM signal

tHBxCCP

Charge

t

Postcharge Phase

FW

phase

IGS_HSx

tPCHGx

ICHGMAXx

IPRECHGx

ICHGx

0

t

HSx internal

drive signal

tFVDS

tHBxBLANK Active

ICHGMAXx

IPRECHGx

IHOLD

ICHGx

0

-

IHOLD

VGS_HSx

t

tRISEx

VSHx

VS

VSHH

VSHL

tDONx

VSHL

IDS_HSDx

IPHASE

t

tHBxCCP

FW

LSx internal

drive signal

IHOLD

t

-

IHOLD

-

IHOLD

Hard off

-

ICHGFWx

-

IHARDOFF

Figure 30 Turn-on of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active

MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10_B(HS PWM),

AGC = 01_Bor 10_B(Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET),

AFWx = 1 (active freewheeling for HBx is activated)

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External

PWM signal

t

Synchronized intern.

PWM signal

tPWM_SYNCH

tPDCHGx

VSHx < VSHL right before activation of LSx

LSx detected as FW MOSFET

HSx internal

drive signal

Discharge phase

IHOLD

0

t

- IHOLD

- IDCHGx

- IHOLD

- IDCHGx

- IPREDCHGx

tHBxCCP Active

Hard off

- IHARDOFF

VGS_HSx

t

tFALLx

VSHx

tDOFFx

VS

VSHH

VSHL

IDS_HSDx

IPHASE

t

tHBx_BLANK FW

LSx internal

drive signal

tFVDS

ICHGFWx

IHOLD

t

- IHOLD

Figure 31 Turn-off of an active MOSFET in PWM mode with active gate control, HS PWM, HS as active

MOSFET, LS as FW MOSFET. PWM_NB =0 (one PWM input per HB), HBxMODE = 10_B(HS PWM),

AGC = 01_Bor 10_B(Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET),

AFWx = 1 (active freewheeling for HBx is activated)

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9.3.3.1.2

The PWM MOSFET is the free-wheeling MOSFET

This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET.

External

PWMz

t

tPWM_SYNCH

Synchronized

intern. PWMz

IGS_LSx

Discharge phase

tPDCHGx

t

0

- IDCHGx

- IPREDCHGx

tHBxCCP Active for cross current

protection

LSx internal

drive signal

IHOLD

0

t

-

IHOLD

- IDCHGx

- IHOLD

- IDCHGx

- IPREDCHGx

Hard off

-

IHARDOFF

tFVDS

VGS_LSx

t

VSHx

tDOFFx tFALLx

VS

VSHH

VSHL

Detection of the active MOSFET

(EN_GEN_CHECK= 1). VSH > VSHH: LS

MOSFET is the active MOSFET

IDS_LSDx

IPHASE

t

IGS_HSx

ICHGFWx

t

tHBxBLANK FW

HSx internal

drive signal

tFVDS

ICHGFWx

IHOLD

t

-

IHOLD

\G

D i

\fi

\BLDC

Figure 32 PWM rising edge - PWM mode with active gate control, HS PWM (HBxMODE = 10_B) , LS as

active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01_Bor 10_B

(Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active

freewheeling for HBx is activated)

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Gate Drivers

External

PWMz

Synchronized

intern. PWMz

t

tPWM_SYNCH

Charge

phase

Postcharge Phase

IGS_LSx

tPCHGx

ICHGMAXx

IPRECHGx

ICHGx

0

t

tHBxBLANK Active

tHBxCCP FW

LSx internal

drive signal

tFVDS

ICHGMAXx

IPRECHGx

IHOLD

ICHGx

t

0

-

IHOLD

VGS_LSx

t

tRISEx

VSHx

tDONx

VS

VSHH

VSHL

Detection of the active MOSFET

(EN_GEN_CHECK= 1). VSH > VSHH: LS

MOSFET is the active MOSFET

IDS_LSDx

IPHASE

t

IGS_HSx

-

ICHGFWx

HSx internal

drive signal

tFVDS

IHOLD

t

-

IHOLD

-

IHOLD

-

ICHGFWx

Hard off

-

IHARDOFF

Figure 33 PWM falling edge - PWM mode with active gate control, HS PWM (HBxMODE = 10_B) , LS as

active MOSFET, HS as FW MOSFET. PWM_NB =0 (one PWM input per HB), AGC = 01_Bor 10_B

(Active Gate Control), EN_GEN_CHECK=1 (detection of active / FW MOSFET), AFWx = 1 (active

freewheeling for HBx is activated)

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9.3.3.2 Control signals with passive free-wheeling (AFWx = 0)

This section describes the MOSFET control signals with active freewheeling and HS PWM:

•

The HS PWM MOSFET is the active MOSFET (Chapter 9.3.3.2.1).

The HS PWM MOSFET is the free-wheeling MOSFET (Chapter 9.3.3.2.2).

9.3.3.2.1

The PWM MOSFET is the active MOSFET

This section shows the control signals of the MOSFET when the PWM is the active MOSFET.

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External

PWMz

Synchronized

intern. PWMz

t

tPWM_SYNCH

Charge

phase

Postcharge Phase

IGS_HSx

tPCHGx

ICHGMAXx

IPRECHGx

ICHGx

0

t

tHBxBLANK

HSx internal

drive signal

tFVDS

ICHGMAXx

IPRECHGx

IHOLD

ICHGx

t

0

-

IHOLD

VGS_HSx

t

tRISEx

VSHx

VS

VSHH

VSHL

tDONx

VSHL

IDS_HSDx

IPHASE

t

IGS_LSx

t

LSx internal

drive signal

tFVDS

-

IHOLD

-

IHOLD

Hard off

-

IHARDOFF

Figure 34 Adaptive turn-on with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the

PWM MOSFET is the active MOSFET. PWM_NB=0.

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External

PWMz

t

tPWM_SYNCH

Synchronized

intern. PWMz

IGS_HSx

Discharge phase

tPDCHGx

t

0

- IDCHGx

- IPREDCHGx

tHBxCCP Active

HSx internal

drive signal

IHOLD

0

t

-

IHOLD

- IDCHGx

- IHOLD

- IDCHGx

- IPREDCHGx

VGS_HSx

VSHx

t

tFALLx

tDOFFx

VS

VSHH

VSHL

IDS_HSDx

IPHASE

t

IGS_LSx

0

LSx internal

drive signal

t

-

IHOLD

Figure 35 Adaptive turn-off with high-side PWM, AGC[1:0] = (1,0) or (1,1), AFWx=0, POCHGDIS=0, the

PWM MOSFET is the active MOSFET.PWM_NB=0.

9.3.3.2.2

The PWM MOSFET is the free-wheeling MOSFET

This section shows the control signals of the MOSFET when the PWM is the free-wheeling MOSFET.

Datasheet

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BLDC Driver

Gate Drivers

External

PWMz

t

tPWM_SYNCH

Synchronized

intern. PWMz

IGS_LSx

Discharge phase

tPDCHGx

t

0

- IDCHGx

- IPREDCHGx

tHBxCCP Active for cross current

protection

LSx internal

drive signal

IHOLD

0

t

-

IHOLD

- IDCHGx

- IHOLD

- IDCHGx

- IPREDCHGx

VGS_LSx

VSHx

t

tDOFFx tFALLx

VS

VSHH

VSHL

Detection of the active MOSFET

IDS_LSDx

IPHASE

(EN_GEN_CHECK= 1). VSH > VSHH: LS

MOSFET is the active MOSFET

t

IGS_HSx

t

HSx internal

drive signal

t

-

IHOLD

\G t

D i

\fi

\BLDC\

Figure 36 PWM rising edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0] =

(1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0.

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BLDC Driver

Gate Drivers

Detection of the active MOSFET

(EN_GEN_CHECK= 1). VSH > VSHH: LS

MOSFET is the active MOSFET

External

PWMz

Synchronized

intern. PWMz

t

tPWM_SYNCH

Charge

phase

Postcharge Phase

IGS_LSx

tPCHGx

ICHGMAXx

IPRECHGx

ICHGx

0

t

tHBxBLANK Active

LSx internal

drive signal

tFVDS

ICHGMAXx

IPRECHGx

IHOLD

ICHGx

t

0

-

IHOLD

VGS_LSx

t

tRISEx

VSHH

VSHx

VS

VSHH

tDONx

VSHL

IDS_LSDx

IPHASE

t

IGS_HSx

HSx internal

drive signal

tFVDS

t

-

IHOLD

-

IHOLD

Hard off

-

IHARDOFF

Figure 37 PWM falling edge with adaptive control, EN_GEN_CHECK = 1 with high-side PWM, AGC[1:0]

= (1,0) or (1,1), AFWx=0, POCHGDIS=0. The PWM MOSFET is the FW MOSFET. PWM_NB=0.

9.3.3.3 Time modulation of pre-charge and pre-discharge times

If DEEP_ADAP =0:

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

•

one single precharge current is applied during tPCHGx to regulate TDON

one single precharge current is applied during tPDCHGx to regulate TDOFF

If DEEP_ADAP = 1 (“deep adaptation” or “time modulation”) it is possible to:

•

to divide the precharge phase in two parts, during which two different precharge currents can be applied

to divide the predischarge phase in two parts, during which two different precharge currents can be

applied

Figure 38 describes the principle of the time modulation applied to the precharge phase. The same principle

is also applied for the regulation of the pre-discharge phase.

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

TDON adaptation

with two current

steps (IPCHGADT =

1)

Current i+2

No

3 consecutive sign changes of (TDON

EFF- TDON TARGET) or No error for 3

consecutive PWM cycles

Current i

Yes

tPCHG

TDON adaptation

with one current step

i+1

i

3 consecutive sign changes

of (TDON EFF- TDON

TARGET)

No

tPCHG

Yes

i+1

i

Precharge phase splitted in 2

sub-phases

50% 50%

tPCHG

Yes

TDON EFF = TDON

TARGET

No

Precharge splitted:

75%-25% if TDON EFF > TDON TARGET

25%-75% if TDON EFF < TDON TARGET

i+1

i

i+1

i

or

25%

75%

tPCHG

25%

tPCHG

Yes

TDON EFF = TDON

TARGET

No

Precharge splitted:

E.g 87.5%-12.5%

1) Precharge further split either:

- until TDON EFF = TDON TARGET

Etc... 1)

- Or until no further split of tPCHG is possible. Refer to 2).

No 2)

TDON EFF = TDON TARGET

2) Exit time modulation:

- tPCHG cannot be further divided due to the limitation of the resolution

- and the regulation of TDON is still not possible

 One single current is applied during tPCHG

Figure 38

Principle of the time modulation of the precharge phase, DEEP_ADAP = 1, AGC = 10_Bor 11_B

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BLDC Driver

Gate Drivers

9.3.3.4 Operation at high and low duty cycles

In the particular cases where the on-time is shorter than tHBxCCP FW or the off-time of the PWM signal is

shorter than tHBxCCP Active:

•

No distinction between active MOSFET and FW MOSFET is possible. Therefore PWM MOSFET (selected by

HBxMODE[1:0]) is controlled as active MOSFET.

•

The MOSFET opposite to the PWM MOSFET stays off (passive FW)

9.3.3.5 Measurements of the switching times

The effective switching times in PWM operation:

•

of the PWM MOSFET if EN_GEN_CHECK = 0

of the active MOSFET if EN_GEN_CHECK = 1

are reported in the registers:

EFF_TDON_OFF1,EFF_TDON_OFF2,EFF_TDON_OFF3.

If the end of the rise time for a given MOSFET is not detected before t_HBxBLANKActive elapses, then the

corresponding status register reports an effective rise time equal to zero.

If the end of the fall time for a given MOSFET is not detected before t_HBxCCPActive active elapses, then the

corresponding status register reports an effective fall time equal to zero.

The device cannot measure the switching times t_DON, t_DOFF, t_RISEand t_FALLat very high and very low duty cycles:

t_ON< t_HBxCCPFW and t_OFF< t_HBxCCPactive. In this case, the corresponding registers report effective t_DON, t_DOFF, t_RISE

and t_FALLequal to zero.

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TLE9185QX

BLDC Driver

Gate Drivers

9.3.4

PWM operation with 6 PWM inputs

Each high-side MOSFET and each low-side MOSFET is controlled by one PWM input. if PWM_NB is set to 1 (see

CSA) and HBx_PWM_EN are set to 1 (see HBMODE). Refer to Table 20.

CP

VS

PWM2

HS1

µC_PWM2

CP

PWM1

µC_PWM1

LS1

SL

CP

VS

PWM4

PWM3

µC_PWM4

µC_PWM3

HS2

LS2

CP

SL

CP

PWM6

PWM5

HS3

LS3

µC_PWM6

µC_PWM5

CP

SL

Figure 39 Half-bridge PWM control with six PWM inputs, PWM_NB = 1

Table 20

PWM_NB

Half-bridge PWM settings with 6 PWM inputs (PWM_NB = 1)FW and Active MOSFET

HBx_PWM HBxMODE¹⁾

Half-bridge x settings¹⁾

_EN¹⁾

1

Don’t care 00_B

LSx and HSx MOSFETs are kept OFF by the passive

discharge (default)

1

01_B

HBx is controlled by its PWM inputs

•

If EN_GEN_CHECK = 0: LSx is always considered as the

active MOSFET

•

If EN_GEN_CHECK = 1: The active and the FW MOSFETs

are detected according to Chapter 9.3.1,

independently from HBxMODE

1

10_B

HBx is controlled by its PWM inputs

•

If EN_GEN_CHECK = 0: HSx is always considered as the

active MOSFET

•

If EN_GEN_CHECK = 1: The active and the FW MOSFETs

are detected according to Chapter 9.3.1

independently from HBxMODE

1

Don’t care 11_B

LSx and HSx MOSFETs are actively kept OFF

1) x = 1 to 3

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

Table 21

PWM Control of HS1 and LS1, PWM_NB = 1, HB1_PWM_EN = 1

HB1MODE[1:0]

PWM1/CRC

Low

PWM2

Low

HS1

OFF

ON

LS1

OFF

ON

01

10

Low

High

Low

High

OFF

ON

High

Low

OFF

ON

Low

High

Low

High

OFF

High

OFF

Table 22

PWM Control of HS2 and LS2, PWM_NB = 1, HB2_PWM_EN = 1

HB2MODE[1:0]

PWM3

Low

PWM4

Low

HS2

OFF

ON

LS2

OFF

ON

01

10

Low

High

Low

High

Low

OFF

ON

High

Low

OFF

ON

Low

High

Low

High

OFF

High

OFF

Table 23

PWM Control of HS3 and LS3, PWM_NB = 1, HB3_PWM_EN = 1

HB3MODE[1:0]

PWM5

Low

PWM6

Low

HS3

OFF

ON

LS3

OFF

ON

01

10

Low

High

Low

High

Low

OFF

ON

High

Low

OFF

ON

Low

High

Low

High

OFF

High

OFF

Figure 40 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the FW MOSFET (low-side

MOSFET in this case) followed by the activation of the active MOSFET (high-side MOSFET in this case)¹⁾with

PWM_NB = 1, AGC[1:0]=01_Bor 10_B, POCHGDIS = 0 (post-charge enabled).

This control scheme is applicable for the following cases:

1) If the synchronized HS PWM rising edge occurs after tHBxCCP FW and before the end of tOFF timeout FW, then the LS MOSFET is

discharged with IHARDOFF and the HS is turned on, when the HS PWM rising edge is detected

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10_B(HS MOSFET is

considered as active MOSFET by default).

2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET;

HBxMODE[1:0] = 01_Bor10_B.

Note:

If the synchronized HS PWM rising edge occurs before the end of tHBxCCP active, then the device

prevents an activation of the HS MOSFET until tHBxCCP FW elapses. In other words, the HS PWM

rising edge is ignored until the end of tHBxCCP FW.

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

External HSx PWM

signal

Synchronized HSx

PWM signal

tPWM_SYNCH

Charge

phase

t

Postcharge Phase

IGS_HSx

tPCHGx

ICHGMAXx

IPRECHGx

ICHGx

0

t

HSx internal

drive signal

tFVDS

tHBxBLANK Active

ICHGMAXx

IPRECHGx

IHOLD

ICHGx

t

0

- IHOLD

VGS_HSx

VSHx < VSHL right before the activation of HSx

tRISEx

VSHx

HSx detected as active MOSFET

VS

VSHH

VSHL

tDONx

VSHL

IDS_HSDx

IPHASE

t

Synchronized LSx

PWM signal

tHBxCCP FW

t

tOFF Timeout

FW

LSx internal

drive signal

tFVDS

IHOLD

t

- IHOLD

- ICHGFWx

Hard off

- IHARDOFF

Figure 40 Turn-on of an active MOSFET in PWM mode with active gate control, HS as active MOSFET,

LS as FW MOSFET. Two PWM inputs per half-bridge, active gate control enabled. PWM_EN =1

Datasheet

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BLDC Driver

Gate Drivers

Figure 41 shows the PWM control of HBx in PWM (HBx_PWM_EN = 1): Turn-off of the active MOSFET (high-side

MOSFET in this case) followed by the activation of the FW MOSFET low-side MOSFET in this case) with PWM_NB

= 1, AGC[1:0] = 01_Bor 10_B, POCHGDIS = 0 (post-charge enabled).

This control scheme is applicable for the following cases:

1. EN_GEN_CHECK = 0 (detection of FW/Active MOSFET disabled); HBxMODE[1:0] = 10_B(HS MOSFET is

considered as active MOSFET by default).

2. EN_GEN_CHECK = 1 (detection of active / FW MOSFET enabled); HS MOSFET detected as active MOSFET;

HBxMODE[1:0] = 01_Bor 10_B.

Note:

If the synchronized LS PWM rising edge occurs before the end of tHBxCCP active, then the device

prevents an activation of the LS MOSFET until tHBxCCP active elapses. In other words, the LS PWM

rising edge is ignored until the end of tHBxCCP active.

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

External HSx PWM

signal

t

tPWM_SYNCH

tPDCHGx

Synchronized HSx

PWM signal

Discharge phase

HSx internal

drive signal

tHBxCCP Active

IHOLD

t

0

- IHOLD

- IDCHGx

- IPREDCHGx

tOFF timeout

Active

Hard off

- IHARDOFF

VGS_HSx

t

tFALLx

VSHH

VSHx

VSHx < VSHL right before the activation of HSx

HSx detected as active MOSFET

tDOFFx

VS

VSHH

VSHL

IDS_HSDx

IPHASE

t

Synchronized LSx

PWM signal

t

tHBxBLANK FW

LSx internal

tFVDS

drive signal

ICHGFWx

IHOLD

t

- IHOLD

Figure 41 Turn-off of an active MOSFET in PWM mode with active gate control, HS as active MOSFET,

LS as FW MOSFET. two PWM inputs per half-bridge, active gate control enabled. PWM_NB=1.

9.3.5

Status bits for regulation of turn-on and turn-off delay times

The control bits TDREGx (TDREG) indicate if tDONx and tDOFFx of the half-bridge x, using the adaptive control

scheme (AGC = 10_Bor 11_B), are in regulation.

Datasheet

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BLDC Driver

Gate Drivers

The half-bridge x is considered in regulation if one of the following conditions is met:

•

Condition 1: The effective turn-on and turn-off delays are equal to the configured delays for at least eight

cumulative PWM cycle (HBx tDON counter ≥ 8 and HBx tDOFF counter ≥ 8). For each PWM cycle

–

if tDONxEFF¹⁾= TDONx²⁾, x = 1.. 3, HBx tDON counter is incremented

if tDONxEFF¹⁾≠ TDONx²⁾, x = 1.. 3, HBx tDON counter is decremented

if tDOFFxEFF¹⁾= TDOFFx³⁾, x = 1.. 3, HBx tDOFF counter is incremented

if tDOFFxEFF ¹⁾≠ TDOFFx³⁾, x = 1.. 3, HBx tDOFF counter is decremented

Condition 2: The error between the effective delays ((tDONxEFF-TDONx) and(tDOFFxEFF-TDOFFx ))

changes its sign three times consecutively

1) Refer to EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3

2) Refer to TDON_HB_CTRL

3) Refer to TDOFF_HB_CTRL

Datasheet

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BLDC Driver

Gate Drivers

9.3.6

Gate driver current

Each gate driver is able to source and sink currents from 0.5 mA to 150 mA, with 64 steps.

150

140

130

120

110

100

90

80

70

60

50

40

30

20

10

0

5

10

15

20

25

30

35

40

45

50

55

60

ICHG[5:0]dec

Figure 42 Configurable discharge currents in PWM operation

Datasheet

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BLDC Driver

Gate Drivers

Table 24

Charge currents and initial precharge currents

Parameter Nom. current

ICHGx[5:0],

Max. deviation to nominal

values [%]

PCHGINITx[5:0]

name

[mA]

000000_B

000001_B

000010_B

000011_B

000100_B

000101_B

000110_B

000111_B

001000_B

001001_B

001010_B

001011_B

001100_B

001101_B

001110_B

001111_B

010000_B

010001_B

010010_B

010011_B

010100_B

010101_B

010110_B

010111_B

011000_B

011001_B

011010_B

011011_B

011100_B

011101_B

011110_B

011111_B

100000_B

100001_B

100010_B

100011_B

I_CHG0

0.5

+/- 60%

+/- 60 %

+/- 55%

+/- 40%

+/- 40 %

+/- 40%

+/- 40 %

+/- 40%

+/- 40 %

+/- 30 %

I_CHG1

0.7

I_CHG2

1.0

I_CHG3

1.4

I_CHG4

1.8

I_CHG5

2.4

I_CHG6

3.0

I_CHG7

3.8

I_CHG8

4.7

I_CHG9

5.8

I_CHG10

I_CHG11

I_CHG12

I_CHG13

I_CHG14

I_CHG15

I_CHG16

I_CHG17

I_CHG18

I_CHG19

I_CHG20

I_CHG21

I_CHG22

I_CHG23

I_CHG24

I_CHG25

I_CHG26

I_CHG27

I_CHG28

I_CHG29

I_CHG30

I_CHG31

I_CHG32

I_CHG33

I_CHG34

I_CHG35

6.9

8.1

9.4

10.8

12.2

13.7

15.3

17.1

19

21

23

25

27.1

29.3

31.6

34

36.5

39

41.6

44.2

46.9

49.7

52.5

55.3

58.1

60.8

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

Table 24

Charge currents and initial precharge currents (cont’d)

Parameter Nom. current

ICHGx[5:0],

Max. deviation to nominal

values [%]

PCHGINITx[5:0]

name

I_CHG36

I_CHG37

I_CHG38

I_CHG39

I_CHG40

I_CHG41

I_CHG42

I_CHG43

I_CHG44

I_CHG45

I_CHG46

I_CHG47

I_CHG48

I_CHG49

I_CHG50

I_CHG51

I_CHG52

I_CHG53

I_CHG54

I_CHG55

I_CHG56

I_CHG57

I_CHG58

I_CHG59

I_CHG60

I_CHG61

I_CHG62

I_CHG63

[mA]

63.6

66.5

69.4

72.3

75.2

78.1

81.1

84.1

87.1

90.2

93.3

96.4

99.5

102.7

105.8

109

100100_B

100101_B

100110_B

100111_B

101000_B

101001_B

101010_B

101011_B

101100_B

101101_B

101110_B

101111_B

110000_B

110001_B

110010_B

110011_B

110100_B

110101_B

110110_B

110111_B

111000_B

111001_B

111010_B

111011_B

111100_B

111101_B

111110_B

111111_B

+/- 30 %

112.2

115.4

118.7

122

125.3

128.7

132.1

135.5

139

142.5

146

150

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BLDC Driver

Gate Drivers

150

140

130

120

110

100

90

80

70

60

50

40

30

20

10

0

5

10

15

20

25

30

35

40

45

50

55

60

IDCHG[5:0]dec

Figure 43 Configurable discharge currents in PWM operation

Datasheet

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TLE9185QX

BLDC Driver

Gate Drivers

Table 25

Discharge currents and initial predischarge currents

IDCHG[5:0],

PDCHGINITx[5:0]

Parameter

name

Nom. current

[mA]

Max. deviation to nominal

values [%]

000000_B

000001_B

000010_B

000011_B

000100_B

000101_B

000110_B

000111_B

001000_B

001001_B

001010_B

001011_B

001100_B

001101_B

001110_B

001111_B

010000_B

010001_B

010010_B

010011_B

010100_B

010101_B

010110_B

010111_B

011000_B

011001_B

011010_B

011011_B

011100_B

011101_B

011110_B

011111_B

100000_B

100001_B

100010_B

100011_B

I_DCHG0

0.5

+/- 60%

+/- 60 %

+/- 40%

+/- 40 %

+/- 40%

+/- 40 %

+/- 40%

+/- 40 %

+/- 30 %

I_DCHG1

0.7

I_DCHG2

1.0

I_DCHG3

1.4

I_DCHG4

1.8

I_DCHG5

2.4

I_DCHG6

3.0

I_DCHG7

3.8

I_DCHG8

4.7

I_DCHG9

5.8

I_DCHG10

I_DCHG11

I_DCHG12

I_DCHG13

I_DCHG14

I_DCHG15

I_DCHG16

I_DCHG17

I_DCHG18

I_DCHG19

I_DCHG20

I_DCHG21

I_DCHG22

I_DCHG23

I_DCHG24

I_DCHG25

I_DCHG26

I_DCHG27

I_DCHG28

I_DCHG29

I_DCHG30

I_DCHG31

I_DCHG32

I_DCHG33

I_DCHG34

I_DCHG35

6.9

8.1

9.4

10.7

12.1

13.5

15.1

16.8

18.6

20.5

22.5

24.5

26.5

28.7

30.9

33.2

35.7

38.2

40.8

43.4

46.1

48.8

51.5

54.2

56.9

59.6

Datasheet

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BLDC Driver

Gate Drivers

Table 25

Discharge currents and initial predischarge currents (cont’d)

IDCHG[5:0],

PDCHGINITx[5:0]

Parameter

name

Nom. current

[mA]

Max. deviation to nominal

values [%]

100100_B

100101_B

100110_B

100111_B

101000_B

101001_B

101010_B

101011_B

101100_B

101101_B

101110_B

101111_B

110000_B

110001_B

110010_B

110011_B

110100_B

110101_B

110110_B

110111_B

111000_B

111001_B

111010_B

111011_B

111100_B

111101_B

111110_B

111111_B

I_DCHG36

I_DCHG37

I_DCHG38

I_DCHG39

I_DCHG40

I_DCHG41

I_DCHG42

I_DCHG43

I_DCHG44

I_DCHG45

I_DCHG46

I_DCHG47

I_DCHG48

I_DCHG49

I_DCHG50

I_DCHG51

I_DCHG52

I_DCHG53

I_DCHG54

I_DCHG55

I_DCHG56

I_DCHG57

I_DCHG58

I_DCHG59

I_DCHG60

I_DCHG61

I_DCHG62

I_DCHG63

62.4

65.2

68

+/- 30 %

70.8

73.7

76.6

79.5

82.5

85.5

88.5

91.5

94.6

97.7

100.9

104.2

107.5

110.8

114.2

117.6

121

124.5

128

131.5

135.1

138.7

142.3

145.8

150

9.4

Passive discharge

Resistors (R_GGND) between the gate of GHx and GND, and between GLx and GND, ensure that the external

MOSFETs are turned off in the following conditions:

•

V_CC1undervoltage

HBxMODE = 00_Bin Normal Mode

CPEN = 0 in Normal Mode

CSA Overcurrent detection with OCEN = 1 in normal mode

Datasheet

79

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

•

VS overvoltage or VSINT overvoltage

Charge pump undervoltage and charge pump blank time (t_CPUVBLANK

)

Charge pump overtemperature (CP_OT)

VDS overvoltage after active discharge in Normal Mode

In Init Mode, Stop Mode, Fail Safe Mode, Restart Mode and Sleep Mode (exceptions for low-sides in parking

braking and VS / VSINT overvoltage braking , refer to Chapter 9.6 and Chapter 10.9.3)

9.5

Slam mode

The slam mode is applicable in Normal Mode.

If the SLAM bit is set in BRAKE register:

1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static

discharge current during their respective tHBxCCP Active.

2. Then charge pump is deactivated independently from CPEN

3. Then PWM1/CRC input pin is mapped to LS1, LS2, LS3, independently from PWM_NB, HBxMODE and

HBx_PWM_EN

a) If PWM1/CRC is High, then the low-side MOSFETs are turned on within t_{ON_BRAKE}

.

b) If PWM1/CRC is Low, then the low-side MOSFETs are turned off within t_{OFF_BRAKE}

.

There is also the possibility to disable selectively the LSx in SLAM mode.

9.6

Parking braking mode

If PARK_BRK_EN bit is set, while the device goes in Sleep Mode or in Stop Mode:

1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static

discharge current during their respective tHBxCCP Active.

2. Then charge pump is deactivated independently from CPEN bit.

3. Then the passive discharge (R_GGND) of the low-sides is deactivated, the passive discharge of the high-sides

are activated

4. If PWM1/CRC is High, then the low-side MOSFETs are turned on within t_{ON_BRAKE}

.

Refer to Chapter 10.9.2 for the protection of the of low-side MOSFETs against short circuits when the parking

braking mode is activated.

Datasheet

80

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

9.7

Charge pump

A dual-stage charge pump supplies the gate drivers for the high-side and low-side MOSFETs. It requires three

external capacitors connected between CPC1N and CPC1P, CPC2N and CPC2P, VS and CP.

The buffer capacitor between VS and CP must have a capacitance equal or higher than 470 nF.

C_CP≥ 470 nF

C_CP1

C_CP2

VS

CP

Single/dual stage

charge pump

Precharge

Logic

Figure 44 Charge pump - Block diagram

Logic or normal level MOSFETs

The regulation of the charge pump outputs voltage can be configured depending on the type of MOSFET.

FET_LVL = 0: Logic level MOSFETs are selected:

•

VCP - VS = V_CP3(11 V typ. at VS > 8 V).

The high-side gate-source voltage GHx - SHx is V_GH4(V_S> 8 V).

The low-side gate-source voltage GLx - SL is V_GH3(V_S> 8 V).

FET_LVL = 1: Normal level MOSFETs are selected:

•

VCP - VS = V_CP1(15 V typ. at VS > 8 V).

The high-side and low-side gate-source voltage GHx - SHx or GLx - SL is V_GH1(V_S> 8 V).

CPSTGA = 0 (default, see GENCTRL), the device operates with the dual-stage charge pump.

If CPSTGA = 1, the device switches to single-stage or dual-stage charge pump automatically:

•

If V_S> V_{CPSO DS}: the TLE9185QX switches from a dual-stage to a single-stage charge pump.

If V_S< V_{CPSO SD}: the TLE9185QX switches from single-stage to dual-stage charge pump.

The operation with the single-stage charge pump reduces the current consumption from the VS pin.

Datasheet

81

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

9.8

Frequency modulation

A modulation of the charge pump frequency can be activated to reduce the peak emission.

The modulation frequency is set by the control bit FMODE in GENCTRL:

•

FMODE = 0: No modulation.

FMODE = 1: Modulation frequency = 15.6 kHz (default).

Datasheet

82

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

9.9

Electrical characteristics gate driver

The electrical characteristics related to the gate driver are valid for V_CP> V_S+ 8.5 V

Table 26

Electrical characteristics: gate drivers

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Comparators

SHx High Threshold

SHx Low Threshold

SHx comparator delay

MOSFET Driver Output

V_SHH

V_SHL

t_SHx

V_S- 2.6

1.9

–

V_S- 1.9

2.6

V

P_12.11.1

P_12.11.2

P_12.11.3

–

V

Referred to GND

1)

–

12

30

ns

High Level Output Voltage V_GH1

GHx vs. SHx and GLx vs. SL

10

7

11.5

–

12.5

V

²⁾V_S≥ 8 V ,

C_Load= 10 nF,

I_CP= -12 mA,

FET_LVL = 1

P_12.11.4

High Level Output Voltage V_GH2

V_S= 6 V,

P_12.11.5

GHx vs. SHx and GLx vs. SL

C

_Load= 10 nF,

I_CP= -6 mA,

FET_LVL = 1

High Level Output Voltage V_GH3

GLx vs. SL

10

–

12.5

V

³⁾V_S≥ 6 V ,

C_Load= 10 nF,

FET_LVL = 0

P_12.11.6

P_12.11.7

High Level Output Voltage V_GH4

8.5

10

²⁾V_S≥ 8 V ,

GHx vs. SHx

C

_Load= 10 nF,

I_CP= -12 mA,

FET_LVL = 0

High Level Output Voltage V_GH5

7

–

12.5

V

V_S= 6 V,

P_12.11.8

GHx vs. SHx

C_LOAD= 10 nF,

I_CP= -6 mA,

FET_LVL =0

1)

Charge current

I_CHG0

I_CHG8

I_CHG16

I_CHG32

-60% 0.5

-55% 4.7

-40% 15.3

-30% 52.5

+60% mA

+55% mA

+40% mA

+30% mA

ICHG = 0_D

P_12.11.70

P_12.11.71

P_12.11.72

P_12.11.73

C_Load= 2.2 nF

4)

V_S≥8V, V_GS≤V_GS(ON)

1)

ICHG =8 _D

C_Load= 2.2 nF

V_S≥8V, V_GS≤V_GS(ON)

1)

ICHG =16 _D

C_Load= 2.2 nF

V_S≥8V, V_GS≤V_GS(ON)

1)

ICHG =32 _D

C_Load= 10 nF

V_S≥8V, V_GS≤V_GS(ON)

Datasheet

83

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

Table 26

Electrical characteristics: gate drivers (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

1)

Charge current

I_CHG48

-30% 99.5

-30% 150

-60% -0.5

-55% -4.7

-40% -15.1

-30% -51.5

-30% -97.7

-30% -150

+30% mA

ICHG =48 _D

P_12.11.74

C_Load= 10 nF

V_S≥8V, V_GS≤V_GS(ON)

4)

1)

Charge current

I_CHG63

+30% mA

+60% mA

ICHG =63 _D

P_12.11.75

P_12.11.76

P_12.11.77

P_12.11.78

P_12.11.79

P_12.11.80

P_12.11.81

C_Load= 22 nF

V_S≥8V, V_GS≤V_GS(ON)

1)

Discharge current

I_DCH0

IDCHG =0 _D

C_Load= 2.2 nF

V_S≥8V,V_GS≥V_GS(OFF1)

1)

I_DCH8

55%

mA

IDCHG =8 _D

C_Load= 2.2 nF

V_S≥8V,V_GS≥V_GS(OFF1)

1)

I_DCHG16

I_DCHG32

I_DCHG48

I_DCHG63

+40% mA

+30% mA

IDCHG =16 _D

C_Load= 2.2 nF

V_S≥8V,V_GS≥V_GS(OFF1)

1)

IDCHG =32 _D

C_Load= 10 nF

V_S≥8V,V_GS≥V_GS(OFF2)

1)

IDCHG = 48_D

C_Load= 10 nF

V_S≥8V,V_GS≥V_GS(OFF2)

1)

IDCHG = 63_D

C_Load= 22 nF

V_S≥8V,V_GS≥V_GS(OFF2)

1)5)

Charge current

temperature drift

I_CHG0,TDrift

I_CHG8,TDrift

-37% -12% 15%

ICHG = 0_D

P_12.11.119

P_12.11.120

P_12.11.121

P_12.11.122

P_12.11.123

P_12.11.124

P_12.11.125

1)5)

Charge current

temperature drift

-17% 1%

20%

18%

9%

ICHG = 8_D

1)5)

Charge current

temperature drift

I_CHG16,TDrift-12% 3%

I_CHG32,TDrift-11% -1%

I_CHG48,TDrift-7.5% 0.5%

I_CHG63,TDrift-5.5% 1.5%

ICHG = 16_D

1)5)

Charge current

temperature drift

ICHG = 32_D

1)5)

Charge current

temperature drift

8%

ICHG = 48_D

1)5)

Charge current

temperature drift

8.5%

IDCHG = 63_D

1)5)

Discharge current

temperature drift

I_DCHG0,TDrift-29% -4.5% 20%

IDCHG = 0_D

Datasheet

84

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

Table 26

Electrical characteristics: gate drivers (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

1)5)

Discharge current

temperature drift

I_DCHG8,TDrift-8%

I_{DCHG16,TDrift}-4%

I_{DCHG32,TDrift}-4%

I_{DCHG48,TDrift}-4%

8.5%

26%

IDCHG = 8_D

P_12.11.126

P_12.11.127

P_12.11.128

P_12.11.129

P_12.11.130

1)5)

Discharge current

temperature drift

9.5%

4.5%

3.5%

23%

13%

10%

9.5%

IDCHG = 16_D

IDCHG = 32_D

IDCHG = 48_D

IDCHG = 63_D

Discharge current

temperature drift

Discharge current

temperature drift

Discharge current

temperature drift

I_{DCHG63,TDrift}-3.5% 3.5%

1)6)

Charge current V_Sdrift

I_CHG0,VsDrift

I_CHG8,VsDrift

3%

4.5%

6%

ICHG = 0_D

P_12.11.131

P_12.11.132

P_12.11.133

P_12.11.134

P_12.11.135

P_12.11.136

P_12.11.137

P_12.11.138

P_12.11.139

P_12.11.140

P_12.11.141

P_12.11.142

P_12.11.22

1)6)

4.5%

7.5%

5.8%

4.5%

2.8%

ICHG = 8_D

1)6)

I_{CHG16,VsDrift}4%

I_{CHG32,VsDrift}2%

5.8%

3.8%

ICHG = 16_D

ICHG = 32_D

ICHG = 48_D

ICHG = 63_D

IDCHG = 0_D

IDCHG = 8_D

1)6)

I_{CHG48,VsDrift}-0.5% 2%

I_{CHG63,VsDrift}-2.3% 0.3%

Discharge current V_Sdrift I_{DCHG0,VsDrift}-3%

Discharge current V_Sdrift I_{DCHG8,VsDrift}-3%

-1.5% 0%

-0.5% 2%

1)6)

Discharge current V_Sdrift I_{DCHG16,VsDrift}-3.3% -0.3% 2.3%

IDCHG = 16_D

IDCHG = 32_D

IDCHG = 48_D

Discharge current V_Sdrift I_{DCHG32,VsDrift}-2%

0%

2%

Discharge current V_Sdrift I_{DCHG48,VsDrift}-1.5% 0%

Discharge current V_Sdrift I_{DCHG63,VsDrift}-1.5% 0.2%

1.5%

30

IDCHG = 63_D

1)

Passive discharge

resistance between

GHx/GLx and GND

R_GGND

10

20

kΩ

1)7)

Resistor between SHx and R_SHGND

GND

10

–

20

22

30

35

kΩ

P_12.11.23

P_12.11.24

Low RDSON mode

R_ONCCP

Ω

¹⁾V_S= 13.5 V

V

_CP= V_S+ 14 V

I_CHG= I_DCHG= 63_D

Gate Drivers Dynamic Parameters

Datasheet

85

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

Table 26

Electrical characteristics: gate drivers (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Gate Driver turn-on delay t_{DGDRV_ON1}

–

400

ns

⁸⁾From PWM⁹⁾

P_12.11.25

Time

rising edge to 20%

of I_CHGx

x = 0 to 63,

_Load= 10 nF,

,

C

BDFREQ = 0

Gate Driver turn-on delay t_{DGDRV_ON2}

–

300

ns

⁸⁾From PWM⁹⁾

P_12.11.93

Time

rising edge to 20%

of I_CHGx

x = 0 to 63,

_Load= 10 nF,

BDFREQ = 1

⁸⁾From 20% of I_CHGxP_12.11.26

to I_CHGx

x = 0 to 63,

_Load= 10 nF

,

C

Gate Driver current turn-on t_{GDRV_RISE(ON)}

rise time

–

30

–

50

ns

,

C

Gate Driver turn-off delay t_{DGDRV_OFF1}

Time

400

⁸⁾From PWM⁹⁾

rising edge to 20%

P_12.11.27

P_12.11.94

P_12.11.28

of I_DCHGx

x = 0 to 63,

_Load= 10 nF,

,

C

BDFREQ = 0

⁸⁾From PWM⁹⁾

rising edge to 20%

Gate Driver turn-off delay t_{DGDRV_OFF2}

Time

–

300

50

ns

of I_DCHGx

x = 0 to 63,

_Load= 10 nF,

,

C

BDFREQ = 1

Gate Driver current turn-off t_{GDRV_RISE(OFF}

30

⁸⁾From 20% of

I_DCHGxto I_DCHGx

x = 0 to 63,

rise time

,

)

C

_Load= 10 nF

External MOSFET gate-to- V_GS(ON)1

source voltage - ON

7

–

V

¹⁾V_S≥ 8 V,

FET_LVL=1

¹⁾V_S≥ 8 V,

FET_LVL=1

¹⁾V_S≥ 8 V,

FET_LVL=0

¹⁾IDCHGx ≤ 24_D(≤ P_12.11.30

P_12.11.29

P_12.11.102

P_12.11.103

External MOSFET gate-to- V_GS(ON)1

source voltage - ON

7

–

External MOSFET gate-to- V_GS(ON)2

source voltage - ON

5.5

–

External MOSFET gate-to- V_GS(OFF)1

1.5

source voltage - OFF

41 mA typ.)

Datasheet

86

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

Table 26

Electrical characteristics: gate drivers (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

External MOSFET gate-to- V_GS(OFF)2

source voltage - OFF

–

5

V

¹⁾IDCHGx > 28_D(>

41 mA typ.)

P_12.11.101

P_12.11.33

P_12.11.82

PWM synchronization

delay

t_{PWM_SYNCH0}80

t_{PWM_SYNCH1}40

–

200

100

ns

¹⁾BDFREQ = 0

PWM synchronization

delay

¹⁾BDFREQ= 1

Bridge driver frequency

Pre-charge time

t_BDFREQ0

t_BDFREQ1

t_PCHG000

16.8

33.7

80

18.75 20.7

MHz ¹⁾BDFREQ= 0

MHz ¹⁾BDFREQ= 1

P_12.11.83

P_12.11.84

P_12.11.34

37.5

107

42.3

140

ns

¹⁾TPCHG = 000,

BDFREQ= 0 or 1

¹⁾TPCHG = 001,

BDFREQ= 0 or 1

¹⁾TPCHG = 010,

BDFREQ= 0 or 1

¹⁾TPCHG = 011,

BDFREQ= 0 or 1

¹⁾TPCHG = 100,

BDFREQ= 0 or 1

¹⁾TPCHG = 101,

BDFREQ= 0 or 1

¹⁾TPCHG = 110,

BDFREQ= 0 or 1

¹⁾TPCHG = 111,

BDFREQ= 0 or 1

¹⁾TPDCHG = 000,

BDFREQ= 0 or 1

¹⁾TPDCHG = 001,

BDFREQ= 0 or 1

¹⁾TPDCHG = 010,

BDFREQ= 0 or 1

¹⁾TPDCHG = 011,

BDFREQ= 0 or 1

¹⁾TPDCHG = 100,

BDFREQ= 0 or 1

¹⁾TPDCHG = 101,

BDFREQ= 0 or 1

Pre-charge time

Pre-discharge time

t_PCHG001

t_PCHG010

t_PCHG011

t_PCHG100

t_PCHG101

t_PCHG110

t_PCHG111

t_PDCHG000

t_PDCHG001

t_PDCHG010

t_PDCHG011

t_PDCHG100

t_PDCHG101

t_PDCHG110

130

170

210

250

420

600

840

80

160

214

267

320

533

747

1067

107

160

214

267

320

533

747

190

260

330

390

630

900

1260

140

190

260

330

390

630

900

P_12.11.35

P_12.11.36

P_12.11.37

P_12.11.85

P_12.11.86

P_12.11.87

P_12.11.88

P_12.11.38

P_12.11.39

P_12.11.40

P_12.11.41

P_12.11.89

P_12.11.90

P_12.11.91

130

170

210

250

420

600

¹⁾TPDCHG = 110,

BDFREQ= 0 or 1

Datasheet

87

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

Table 26

Electrical characteristics: gate drivers (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Pre-discharge time

Discharge timeout

t_PDCHG111

840

1067

1260

ns

¹⁾TPDCHG = 111,

BDFREQ= 0 or 1

¹⁾PWM_NB=1_B

P_12.11.92

P_12.11.9

t_{OFF_TIMEOUT}3.2

4

4.8

µs

Low-side gate driver, CP off - Slam mode, parking braking and VS overvoltage braking

LS turn-on time, CP off

t_{ON_BRAKE}

t_{OFF_BRAKE}

V_{GLx_BRAKE}

–

5

4.5

0.7

–

9

µs

V

C_LOAD= 10 nF

VGLx-VSL = 5 V,

V_S> 8 V or V_SINT> 8 V

P_12.11.42

P_12.11.43

LS turn-off time, CP off

2

C_LOAD= 10 nF

VGLx-VSL = 1.5 V,

V_S> 8 V or V_SINT> 8 V

High output voltage

GLx - SL

10

V_S> 8 V or V_SINT> 8 V P_12.11.48

Charge pump

1)

Charge Pump Frequency

f_CP

–

250

–

kHz

V

P_12.11.49

Output Voltage VCP vs. VS V_CPmin1

8.5

V_S= 6 V, I_CP= - 6 mA, P_12.11.50

FET_LVL =1

Output Voltage VCP vs. VS V_CPmin2

7.5

12

–

V

V_S= 6 V, I_CP= - 6 mA, P_12.11.51

FET_LVL =0

Regulated CP output

voltage, VCP vs. VS

V_CP1

15

17

8 V < V_S< 23 V

I_CP= - 12 mA¹¹⁾

CPSTGA = 0,

FET_LVL =1

P_12.11.52

P_12.11.53

P_12.11.54

P_12.11.55

,

Regulated CP output

voltage, VCP vs. VS

V_CP2

12

7.5

5

15

11

–

17

13

60

V

18 V < V_S< 23 V

I

_CP= - 12 mA¹¹⁾

,

CPSTGA = 1,

FET_LVL =1

Regulated CP output

voltage, VCP vs. VS

V_CP3

V

8 V < V_S< 23 V

I

_CP= - 12 mA¹¹⁾

,

CPSTGA = 0,

FET_LVL =0

Regulated CP output

voltage, VCP vs. VS

V_CP4

V

13 V < V_S< 23 V

I

_CP= - 12 mA¹¹⁾

,

CPSTGA = 0,

FET_LVL =0

^1)10)11)18 V<V_S< 23 V P_12.11.56

(25%), I_CP= 0 ,

Turn-on time

t_{ON_VCP1}

µs

CPSTGA = 1,

FET_LVL =1

Datasheet

88

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Gate Drivers

Table 26

Electrical characteristics: gate drivers (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

30

Unit Note or

Test Condition

Number

Min.

Max.

Rise time

t_{RISE_VCP1}

5

60

µs

^1)10)11)18 V < V_S< 23 P_12.11.57

V (25%-75%)

I_CP= 0 , CPSTGA = 1,

FET_LVL =1

^1)10)11)13 V < V_S<23 P_12.11.58

V (25%), I_CP= 0,

CPSTGA = 1,

FET_LVL =0

Turn-on time

Rise time

t_{ON_VCP2}

20

5

60

30

17

120

60

t_{RISE_VCP2}

^1)10)11)13 V < V_S< 23 P_12.11.59

V (25%-75%)

I_CP= 0 , CPSTGA = 1,

FET_LVL =0

Automatic switch over dual V_{CPSO DS}

to single stage charge

pump

16

18

V

CPSTGA = 1,

FET_LVL =1,

VS rising

P_12.11.60

P_12.11.61

P_12.11.62

P_12.11.64

Automatic switch over dual V_{CPSO DS}

to single stage charge

pump

11.5

15.5

11

12.25 13

CPSTGA = 1,

FET_LVL = 0,

VS rising

Automatic switch over

single to dual stage charge

pump

V_{CPSO SD}

16.5

17.5

CPSTGA = 1,

FET_LVL =1,

VS falling

Automatic switch over

single to dual stage charge

pump

V_{CPSO SD}

11.75 12.5

CPSTGA = 1,

FET_LVL = 0,

VS falling

Charge pump switch over V_{CPSO HY}

hysteresis

–

0.5

–

V

¹⁾CPSTGA = 1

V_{CPSO DS}- V_{CPSO SD}

¹¹⁾8 V < V_S< 28 V

CPSTGA = 0

P_12.11.65

P_12.11.68

Charge pump minimum

output current

I_CPOC1

–

-12

mA

FET_LVL =1

Charge pump minimum

output current

I_CPOC2

–

-12

mA

¹¹⁾8 V < V_S< 28 V

CPSTGA = 0

P_12.11.69

FET_LVL =0

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BLDC Driver

Gate Drivers

Table 26

Electrical characteristics: gate drivers (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C,

V_CP> V_S+ 8.5 V, V_S= 6 to 19V, all voltages with respect to ground, positive current flowing into pin except for I_GLx

and I_GHx(unless otherwise specified).

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Digital PWMx Inputs

High Level Input Voltage

Threshold

V_PWMH

–

0.7 ×

V_cc1

V

–

P_12.11.95

P_12.11.96

P_12.11.97

P_12.11.98

Low Level Input Voltage

Threshold

V_PWML

0.3 ×

V_cc1

–

V

–

1)

PWMx Input Hysteresis

V_PWM,hys

R_{PD_PWM}

–

0.12 ×

V_cc1

–

V

PWMx Pull-down

Resistance

20

40

80

kΩ

–

CRC Select; Pin PWM1/CRC

12)

1)

Config Pull-up Resistance R_CFG

100

10

kΩ

P_12.11.99

Config Select Filter Time t_{CFG_F}

5

14

µs

P_12.11.105

1) Not subject to production test, specified by design.

2) Independent from CPSTGA.

3) ICP = -12 mA for VS ≥ 8 V, ICP = 6 mA for VS = 6 V.

4) V_GS(ON)= V_GS(ON)1if FET_LVL = 1, V_GS(ON)= V_GS(ON)2if FET_LVL = 0.

5) Tj reference = 25°C

6) Valid for V_S= 8 to 19 V, V_Sreference = 13.5 V

7) This resistance is the resistance between GHx and GND connected through a diode to SHx. As a consequence, the

voltage at SHx can rise up to 0.6 V typ. before it is discharged through the resistor.

8) Not subject to production test, specified by design.

9) External PWM signal.

10) Parameter dependent on the capacitance C_CP

.

11) C_CPC1= C_CPC2= 220 nF, C_CP= 470 nF. Other C_CPvalues higher than 470 nF can be used. Note that this capacitor

influences the charge pump rise and turn-on times, and the charge , V_CPripple voltage when charging the gate of a

MOSFET.

12) Config Pull-up will be only active during startup-phase for checking external pull-down. After checking, the typ. 40 kΩ

Pull-down resistance will be present.

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BLDC Driver

Supervision Functions

10

Supervision Functions

10.1

Reset Function

VCC1

RSTN

Resetlogic

Incl. filter & delay

Figure 45 Reset Block Diagram

10.1.1

Reset Output Description

The reset output pin RSTN provides a reset information to the microcontroller, for example, in the event that

the output voltage has fallen below the undervoltage threshold V_RTx. In case of a reset event, the reset output

RSTN is pulled to low after the filter time t_RFand stays low as long as the reset event is present plus a reset

delay time t_RD1or t_RD2depending on the value in RSTN_DEL. When connecting the device to battery voltage,

the reset signal remains low initially. When the output voltage VCC1 has reached the reset default threshold

V_RT1,r, the reset output RSTN is released to high after the reset delay time t_RD1. A reset can also occur due to a

watchdog trigger failure. The reset threshold can be adjusted via SPI, the default reset threshold is V_RT1,f. The

RSTN pin has an integrated pull-up resistor. In case reset is triggered, it will be pulled low for VCC1 ≥ 1V and

for VSINT ≥ V_POR,f(see also Chapter 10.3).

The timings for the RSTN triggering regarding VCC1 undervoltage and watchdog trigger is shown in Figure 46.

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VCC1

V_RT1

t < t_RF

The reset threshold can be

configured via SPI in

Normal Mode, default is V_RT1

undervoltage

t

t_CW

t_OW

t_RD1

t_RDx(config)

t_CW

t_LW

t_CW

t_OW

SPI

Init

WD

Trigger

WD

Trigger

SPI

Init

t

t_RF

RSTN

t

_LW= long open window

_CW= closed window

_OW= open window

Init

Normal

Restart

Normal

Reset_timing.vsd

Figure 46 Reset Timing Diagram

10.1.2

Soft Reset Description

In Normal Mode and Stop Mode, it is also possible to trigger a device internal reset via a SPI command in order

to bring the device into a defined state in case of failures. In this case the microcontroller must send a SPI

command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid,

the device is set back to Init Mode and all SPI registers are set to their default values (see SPI Chapter 11.5.1

and Chapter 11.6.1).

Two different soft reset configurations are possible via the SPI bit SOFT_RESET_RO:

•

SOFT_RESET_RO = ‘0’: The reset output (RSTN) is triggered when the soft reset is executed (default

setting) The configured reset delay time t_RD1or t_RD2is applied depending on the value in RSTN_DEL).

SOFT_RESET_RO = ‘1’: The reset output (RSTN) is not triggered when the soft reset is executed.

Note:

The device must be in Normal Mode or Stop Mode when sending this command.

Otherwise, the command will be ignored.

Note:

Allow CRC configuration after software-reset - or better check once again via SPI after software

reset.

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Supervision Functions

10.2

Watchdog Function

The watchdog is used to monitor the communication with the microcontroller and to trigger a reset or move

the device to Fail Safe Mode, if the microcontroller stops serving the watchdog.

Two different types of watchdog functions are implemented and can be selected via the bit WD_CFG:

•

Time-Out Watchdog (default value)

Window Watchdog

The respective watchdog functions can be selected and programmed in Normal Mode. The configuration stays

unchanged in Stop Mode.

Please refer to Table 27 to match the device modes with the respective watchdog modes.

Table 27 Watchdog Functionality by modes

Mode

Watchdog Mode

Remarks

Init Mode

Starts with Long Open

Window

Watchdog starts with Long Open Window after RSTN

is released.

Normal Mode

WD Programmable

Window Watchdog, Time-Out watchdog or switched

off for Stop Mode.

Stop Mode

Sleep Mode

Watchdog is fixed or off

Off

Device will start with Long Open Window when

entering Normal Mode.

Restart Mode

Off

Device will start with Long Open Window when

entering Normal Mode.

The watchdog timing is programmed via SPI command in the register WD_CTRL. As soon as the watchdog is

programmed, the timer starts with the new setting and the watchdog must be served. The watchdog is

triggered by sending a valid SPI-write command to the watchdog configuration register. The watchdog trigger

command is executed when the SPI command is interpreted.

When coming from Init Mode, Restart Mode or in certain cases from Stop Mode, the watchdog timer is always

started with a long open window. The long open window (t_LW) allows the microcontroller to run its

initialization sequences and then to trigger the watchdog via SPI.

The watchdog timer period can be selected via SPI (WD_TIMER).The timer setting is valid for both watchdog

types.

The following watchdog timer periods are available:

•

WD Setting 1: 10 ms

WD Setting 2: 20 ms

WD Setting 3: 50 ms

WD Setting 4: 100 ms

WD Setting 5: 200 ms

WD Setting 6: 500 ms

WD Setting 7: 1 s

WD Setting 8: 10 s

In case of a reset, Restart Mode or Fail-Safe Mode is entered according to the configuration and the SPI bits

WD_FAIL are set. Once the RSTN goes high again the watchdog immediately starts with a long open window

the device enters automatically Normal Mode.

The Watchdog behaviour in Software Development Mode is described in Chapter 5.4.7.

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In case a watchdog-trigger was missed in Software Development Mode, the watchdog will start with the long-

open-window once again.

The WD_FAIL bits will be set after a watchdog trigger failure.

The WD_FAIL bits are cleared automatically when following conditions apply:

•

After a successful watchdog trigger.

When the watchdog is off: in Stop Mode after successfully disabling it, in Sleep Mode, or in Fail-Safe Mode

(except for a watchdog failure).

10.2.1

Time-Out Watchdog

The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog

trigger can be done at any time within the configured watchdog timer period.

A correct watchdog service immediately results in starting a new watchdog timer period. Taking the

tolerances of the internal oscillator into account leads to the safe trigger area as defined in Figure 47.

If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RSTN low and

the device switches to Restart Mode or Fail-Safe Mode.

Typical timout watchdog trigger period

t_WDx 1.50

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t_WDx 1.20

t_WDx 1.80

t / [t_{WD_TIMER}

]

safe trigger area

Figure 47 Time-out Watchdog Definitions

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Supervision Functions

10.2.2

Window Watchdog

Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer

period is divided between a closed and an open window. The watchdog must be triggered within the open

window.

A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an

open window.

The watchdog timer period is at the same time the typical trigger time and defines the middle of the open

window. Taking the oscillator tolerances into account leads to a safe trigger area of:

t_WD× 0.72 < safe trigger area < t_WD× 1.20.

The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking

the tolerances of the internal oscillator into account leads to the timings as defined in Figure 48.

A correct watchdog service immediately results in starting the next closed window.

If the trigger signal meet the closed window or if the watchdog timer period elapses, then a watchdog reset is

triggered (RSTN low) and the device switches to Restart Mode or Fail-Safe Mode.

t_WDx 0.6

t_WDx 0.9

Typ. closed window

Typ. open window

t_WDx 0.48

t_WDx 0.72

t_WDx 1.0

t_WDx 1.20

t_WDx 1.80

closed window

uncertainty

open window

uncertainty

Watchdog Timer Period (WD_TIMER)

t / [t_{WD_TIMER}

]

safe trigger area

Figure 48 Window Watchdog Definitions

10.2.3

Watchdog Setting Check Sum

A check sum bit is part of the SPI command to trigger the watchdog and to set the watchdog setting.

The sum of the 16 data bits in the register WD_CTRL needs to have even parity (see Equation (10.1)). This is

realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is

ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set.

The written value of the reserved bits of the WD_CTRL register is considered (even if read as ‘0’ in the SPI

output) for checksum calculation, i.e. if a 1 is written on the reserved bit position, then a 1 will be used in the

checksum calculation.

(10.1)

Bit(CHECKSUM) = Bit22 ⊕ … ⊕ Bit8

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BLDC Driver

Supervision Functions

10.2.4

Watchdog during Stop Mode

The watchdog can be disabled for Stop Mode in Normal Mode. For safety reasons, there is a special sequence

to be followed in order to disable the watchdog as described in Figure 49. Two different SPI bits

(WD_STM_EN_0, WD_STM_EN_1) in the registers HW_CTRL and WD_CTRL need to be set.

Correct WD disabling

Sequence Errors

sequence

ꢀMissing to set bit

WD_STM_EN_0 with the

next watchdog trigger after

having set WD_STM_EN_1

Set bit

WD_STM_EN_1 = 1

with next WD Trigger

ꢀStaying in Normal Mode

instead of going to Stop

Mode with the next trigger

Set bit

WD_STM_EN_0 = 1

Before subsequent WD Trigger

Will enable the WD:

Change to

Stop Mode

ꢀSwitching back to

Normal Mode

ꢀTriggering the watchdog

WD is switched off

Figure 49 Watchdog disabling sequence in Stop Mode

If a sequence error occurs, then the bit WD_STM_EN_1 will be cleared and the sequence has to be started

again.

The watchdog can be enabled by triggering the watchdog in Stop Mode or by switching back to Normal Mode

via SPI command. In both cases the watchdog will start with a long open window and the bits WD_STM_EN_1

and WD_STM_EN_0 are cleared. After the long open window the watchdog has to be served as configured in

the WD_CTRL register.

Note:

The bit WD_STM_EN_0 will be cleared automatically when the sequence is started and it was 1

before. WD_STM_EN_0 can also not be set if WD_STM_EN_1 isn't yet set.

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Supervision Functions

10.3

VSINT Power On Reset

At power up of the device, the Power on Reset is detected when VSINT > V_POR,rand the SPI bit POR is set to

indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be

kept low and will only be released once VCC1 has crossed V_RT1,rand after t_RD1has elapsed.

In case VSINT < V_POR,f, an device internal reset will be generated and the device is switched off and will restart

in Init Mode at the next VSINT rising. This is shown in Figure 50.

VSINT

V_POR,r

V_POR,f

t

VCC1

V_RT1,r

The reset threshold can be

configured via SPI in

Normal Mode, default is V_RT1

V_RTx,f

RSTN

Restart Mode is entered

whenever the Reset is

triggered

t

t_RD1

Mode

Re-

start

OFF

INIT MODE

Any MODE

OFF

t

SPI

Command

Figure 50 Ramp up / down example of Supply Voltage

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Supervision Functions

10.4

VSINT Under- and Overvoltage

10.4.1

VSINT Undervoltage

The VSINT under-voltage monitoring is always active in Init Mode, Restart Mode, Normal Mode. If the supply

voltage VSINT drops below V_SINT,UVfor more than t_{VSUV_FILT}, then the device does the following measures:

•

The VCC1 short circuit diagnosis becomes inactive (see Chapter 10.7). However, the thermal protection of

the device remains active. If the undervoltage threshold is exceeded (VSINT rising) then the function will

be automatically enabled again.

•

The status bit VSINT_UV is set and latched until a clear command of SUP_STAT is received.

Note:

VSINT under-voltage monitoring is not available in Stop Mode due to current consumption saving

requirements except if the VCC1 load current is above the active peak threshold (I_PEAK_TH) or if

VCC1 is below the VCC1 prewarning threshold.

10.4.2

VSINT Overvoltage

The VSINT over-voltage monitoring is always active in Init Mode, Restart Mode and Normal Mode. If VSINT rises

above V_S,OVD1, V_S,OVD2for more than t_{VSOV_FILT}then the device does the following measures:

1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static

discharge current during their respective tHBxCCP Active.

2. Then the charge pump is turned off and the passive discharge is activated.

3. The status bits VSINT_OV is set and latched until a clear command of SUP_STAT is received.

If VS or VSINT fall below V_S,OVD1or V_S,OVD2

:

•

If CPEN = 0 : the charge pumps stays and the bridge driver stay off.

If CPEN = 1 :

–

If BDOV_REC = 0 : Then the charge pump is reactivated but the bridge driver stays off until VS_OV and

VSINT_OV are cleared. The current sense amplifier is reactivated (provided that CSA_OFF = 0)

–

If BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge

driver is enabled if VCP > V_CPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is

according to the control registers.

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Supervision Functions

10.5

VS Under- and Overvoltage

10.5.1

VS Undervoltage

The VS under-voltage monitoring is always active in Init-, Restart Mode and Normal Mode. If VS drops below

V_S,UVfor more than t_{VSUV_FILT}, then the device does the following measures:

1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static

discharge current during their respective tHBxCCP Active.

2. Then the charge pump is turned off and the passive discharge is activated and the current sense amplifier

is turned off.

3. The status bits VS_UV is set and latched until a clear command of SUP_STAT is received.

If VS rises above V_S,UV, then the charge pump is reactivated (provided that CPEN is set) and the current sense

amplifier is reactivated (provided CSA_OFF = 0) but the bridge driver stays off until VS_UV is cleared. The

bridge driver will be reactivated once the VS_UV bit is cleared.

10.5.2

VS Overvoltage

The VS over-voltage monitoring is always active in Init-, Restart Mode and Normal Mode or when the charge

pump is enabled. If VS rises above V_S,OVD1or V_S,OVD2for more than t_{VSOV_FILT}, then the device does the following

measures:

1. If HBxMODE = 01b or 10b , then the corresponding MOSFETs are actively turned off with their static

discharge current during their respective tHBxCCP Active.

2. Then the charge pump is turned off and the passive discharge is activated and current sense amplifier is

turned off .

3. The status bits VS_OV is set and latched until a clear command of SUP_STAT is received.

If VS and VSINT fall below V_S,OVD1or V_S,OVD2

:

•

If CPEN = 0 : the charge pumps and the bridge driver stay off.

If CPEN = 1 :

–

If BDOV_REC = 0 : Then the charge pump is reactivated (provided that CPEN = 1 and CP_UV = 0) but the

bridge driver stays off until VS_OV and VSINT_OV are cleared. The current sense amplifier is

reactivated provided that CSA_OFF = 0

–

If BDOV_REC = 1 : Then the charge pump and the current sense amplifier are reactivated and the bridge

driver is enabled if VCP > V_CPUVx, even if VS_OV or VSINT_OV is set. The state of the external MOSFETs is

according to the control registers.

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Supervision Functions

10.6

VCC1 Over-/ Undervoltage and Undervoltage Prewarning

10.6.1

VCC1 Undervoltage and Undervoltage Prewarning

This function is always active when the VCC1 voltage regulator is enabled.

A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The

prewarning event is signaled with the bit VCC1_WARN. No other actions are taken.

As described in Chapter 10.1 and Figure 51, a reset will be triggered (RSTN pulled low) when the V_CC1output

voltage falls below the selected undervoltage threshold (V_RTx). The device will enter Restart Mode and the bit

VCC1_UV is set when RSTN is released again.

The hysteresis of the VCC1 undervoltage threshold can be increased by setting the bit RSTN_HYS. In this case

always the highest rising threshold (V_RT1,R) is used for the release of the undervoltage reset. The falling reset

threshold remains as configured.

An additional safety mechanism is implemented to avoid repetitive VCC1 undervoltage resets due to high

dynamic loads on VCC1:

•

A counter is increased for every consecutive VCC1 undervoltage event (regardless on the selected reset

threshold).

•

The counter is active in Init Mode, Normal Mode and Stop Mode.

For VS < V_SINT,UVthe counter will be stopped in Normal Mode (i.e. the VS UV comparator is always enabled

in Normal Mode).

•

A 4th consecutive VCC1 undervoltage event will lead to Fail-Safe Mode entry and to setting the bit

VCC1_UV_FS.

This counter is cleared:

–

When Fail-Safe Mode is entered.

When the bit VCC1_UV is cleared.

When a Soft-Reset is triggered.

Note:

After 4 consecutive VCC1_UV events, the device will enter Fail-Safe Mode and the VCC1_UV_FS bit is

set.

The VCC1_WARN or VCC1_UV bits are not set in Sleep Mode as V_CC1= 0 V in this case.

VCC1

V_RTx

t

t_RF

t_RDx(config)

RSTN

t

Normal Mode

Restart Mode

Normal Mode

Figure 51 VCC1 Undervoltage Timing Diagram

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Supervision Functions

Note:

It is recommended to clear the VCC1_WARN and VCC1_UV bit once it is detected by the

microcontroller software to verify if the undervoltage still exists or not.

10.6.2

VCC1 Overvoltage

For fail-safe reasons a configurable VCC1 over voltage detection feature is implemented. It is active when the

VCC1 voltage regulator is enabled.

In case the V_CC1,OV,rthreshold is crossed, the device triggers following measures depending on the

configuration:

•

The bit VCC1_OV is always set.

Based on the configuration of VCC1_OV_MOD, different kind of event are generated from device.

If the VCC1_OV_MOD=11_B, in case of the device enters in Fail Safe Mode.

VCC1

V_CC1,OV

t

t_{OV_filt}

RSTN

t_RDx(config)

t

Normal Mode

Restart Mode

Normal Mode

Figure 52 VCC1 Over Voltage Timing Diagram

10.7

VCC1 Short Circuit Diagnostics

The short circuit protection feature for V_CC1is implemented as follows:

•

The short circuit detection is only enabled if VS > V_SINT,UV.

If VCC1 is not above the V_RTxwithin t_VCC1,SCafter device power up or after waking from Sleep Mode or Fail-

Safe Mode (i.e. after VCC1 is enabled) then the SPI bit VCC1_SC bit is set, VCC1 is turned off, the FO pin is

enabled, FAILURE is set and Fail-Safe Mode is entered. The device can be activated again via a wake-up

sources.

•

The same behavior applies, if V_CC1falls below V_RTxfor longer than t_VCC1,SC.

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Supervision Functions

10.8

Thermal Protection

Three independent and different thermal protection features are implemented in the device according to the

system impact:

•

Individual thermal shutdown of specific blocks

Temperature prewarning of VCC1 voltage regulator

Device thermal shutdown due to VCC1 overtemperature

10.8.1

Individual Thermal Shutdown

As a first-level protection measure, the charge pump is independently switched off if the respective block

reaches the temperature threshold T_jTSD1. Then the TSD1 bit is set. This bit can only be cleared via SPI once

the overtemperature is not present anymore. Independent of the device mode the thermal shutdown

protection is only active if the respective block is ON.

The respective modules behave as follows:

•

Charge pump: If the charge pump reaches T_jTSD1, then CP_OT is set, CPEN is cleared and the activated

MOSFETs are actively discharged with their respective static currents during their respective active cross

current protection times (tHBxCCP active). When all tHBxCCP active elapsed, then the charge pump and

the MOSFETs active discharge are disabled and the current sense amplifier is deactivated. Once the over

temperature condition is not present anymore, then CPEN has to be configured again by SPI.

Note:

The diagnosis bits are not cleared automatically and have to be cleared via SPI once the

overtemperature condition is not present anymore.

10.8.2

Temperature Prewarning

As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1

reaches the thermal prewarning temperature threshold T_jPW. Then the status bit TPW is set. This bit can only

be cleared via SPI once the overtemperature is not present anymore.

10.8.3

Thermal Shutdown

As a highest level of thermal protection a temperature shutdown of the device is implemented if the main

supply VCC1 reaches the thermal shutdown temperature threshold T_jTSD2. Once a TSD2 event is detected Fail-

Safe Mode is entered. Only when device temperature falls below the TSD2 threshold then the device remains

in Fail-Safe Mode for t_TSD2to allow the device to cool down. After this time has expired, the device will

automatically change via Restart Mode to Normal Mode (see also Chapter 5.4.6).

When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in Normal

Mode once the overtemperature is not present anymore.

For increased robustness requirements it is possible to extend the TSD2 waiting time by 64x of t_TSD2after 16

consecutive TSD2 events by setting the SPI bit TSD2_DEL. The counter is incremented with each TSD2 event

even if the bit TSD2 is not cleared. Once the counter has reached the value 16, then the bit TSD2_SAFE is set

and the extended TSD2 waiting time is active. The extended waiting time will be kept until TSD2_SAFE is

cleared. The TSD counter is cleared when TSD2 or TSD2_DEL is cleared.

Note:

In case a TSD2 overtemperature occurs while entering Sleep Mode then Fail-Safe Mode is still

entered.

Note:

In case of a TSD2 event, the FAILURE bit is set to ‘1’ and the DEV_STAT field is set to ‘01’ inside the

DEV_STAT register.

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BLDC Driver

Supervision Functions

10.9

Bridge driver

This section describes the supervision functions related to the bridge driver.

10.9.1

Bridge driver supervision with activated charge pump

This section describes the supervision functions when the charge pump is activated.

10.9.1.1 Drain-source voltage monitoring

Voltage comparators monitor the activated MOSFETs to protect high-side MOSFETs and low-side MOSFETs

against a short circuit respectively to ground and to the battery during ON-state.

A drain-source overvoltage is detected on a low-side MOSFET if the voltage difference between VSHx and SL

exceeds the threshold voltage configured by LS_VDS (see Table 28). Consequently, the corresponding half-

bridge is latched off with the static discharge current.

A drain-source overvoltage is detected on a high-side MOSFET if the voltage difference between VS and VSHx

exceeds the threshold voltage configured by HS_VDS (see Table 29). Consequently, the corresponding half-

bridge is latched off with the static discharge current.

Table 28 Low-side drain-source overvoltage threshold

LSxVDSTH[2:0]

000_B

Drain-Source overvoltage threshold for LSx (typical)

160 mV

200 mV (default)

300 mV

400 mV

500 mV

600 mV

800 mV

2 V

001_B

010_B

011_B

100_B

101_B

110_B

111_B

Table 29 High-side drain-source overvoltage threshold

HSxVDSTH[2:0]

000_B

Drain-Source overvoltage threshold for HSx (typical)

160 mV

200 mV (default)

300 mV

400 mV

500 mV

600 mV

800 mV

2 V

001_B

010_B

011_B

100_B

101_B

110_B

111_B

Attention: 2 V threshold is dedicated for the diagnostic in off-state. It is highly recommended to select

another drain-source overvoltage threshold once the routine of the diagnostic in off-state has

been performed to avoid additional current consumption from VS and from the charge pump.

The device reports a Drain-Source overvoltage error if both conditions are met:

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BLDC Driver

Supervision Functions

•

After expiration of the blank time .

If the Drain-Source voltage monitoring exceeds the configured threshold for a duration longer than the

configured filter time (refer to Table 30 and LS_VDS TFVDS bits).

Table 30 Drain-Source overvoltage filter time

TFVDS[2:0]

Drain-Source overvoltage filter time (typical)

00_B

01_B

10_B

11_B

0.5 µs (default)

1 µs

2 µs

6 µs

If a short circuit is detected by the Drain-Source voltage monitoring:

•

The impacted half-bridge is latched off with the static discharge current for the configured cross-current

protection time.

•

The corresponding bit in the status register DSOV is set.

The DSOV bit in Global Status Register GEN_STAT is set.

If a Drain-Source overvoltage is detected for one of the MOSFETs, then the status register DSOV must be

cleared in order to re-enable the faulty half-bridge.

10.9.1.2 Cross-current protection and drain-source overvoltage blank time

All gate drivers feature a cross-current protection time and a Drain-Source overvoltage blank time.

The cross-current protection avoids the simultaneous activation of the high-side and the low-side MOSFETs

of the same half-bridge.

During the blank time, the drain-source overvoltage detection is disabled, to avoid a wrong fault detection

during the activation phase of a MOSFET.

Note:

The setting of the cross-current protection and of the blank times may be changed by the

microcontroller only if all HBx_PWM_EN bits are reset.

Note:

Changing the Drain-Source overvoltage of a half-bridge x (HBx) in on-state (HBxMODE[1:0]=(0,1) or

(1,0)) may result in a wrong VDS overvoltage detection on HBx. Therefore it is highly recommended

to change this threshold when HBxMODE[1:0]=(0,0) or (1,1)

10.9.1.2.1

Cross-current protection

The active and freewheeling cross-current protection times of each half-bridge is configured individually with

the control register CCP_BLK.

The typical cross-current protection time applied to the freewheeling MOSFET of the half-bridge x is 587 ns +

266 ns x TCCP[3:0]_D, where TCCP[3:0]_Dis the decimal value of the control bits TCCP.

10.9.1.2.2

Drain-source overvoltage blank time

A configurable blank time for the Drain-Source monitoring is applied at the turn-on of the MOSFETs. During

the blank time, a Drain-Source overvoltage error is masked.

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BLDC Driver

Supervision Functions

For Half-Bridges in PWM mode with AFWx = 1:

•

the blank time of the PWM MOSFET starts at the expiration of the cross-current protection time of the PWM

MOSFET. Refer to Figure 53.

•

the blank time of the free-wheeling MOSFET starts after expiration of the cross-current protection time at

turn-off of the PWM MOSFET. Refer to Figure 53.

PWM

t

IGS_PWM

MOSFET

Post-charge

tPCHGz

ICHGMAXz

tPDCHGz

IPRECHGz

ICHGz

t

0

- IDCHGz

tBLANK for

PWM MOSFET

- IPREDCHGz

tHBxCPP for

symmetrisation

tHBxCPP

IGS Freewheeling

MOSFET

ICHGMAXz

t

tBLANK for

freewheeling MOSFET

-

ICHGMAXz

Figure 53 Blank time for half-bridges in PWM operation with AFW = 1

For statically activated half-bridges, the blank time starts:

•

Case1: at expiration of the cross-current protection (Figure 23), if the opposite MOSFET was previously

activated.

•

Case 2: right after the decoding of the SPI command to turn on a MOSFET, if the half-bridge was in high

impedance (Figure 24).

The blank times of the active and FW MOSFETs can be configured with the control register CCP_BLK.

The typical blank is 587 ns + 266 ns x TBLK[3:0]_D).

Note:

The blank time is implemented at every new activation of a MOSFET, including a recovery from VS

undervoltage, VS overvoltage, VSINT overvoltage, CP UV, CP OT.

10.9.1.3 OFF-state diagnostic

In order to support the off-state diagnostic (HBxMODE= 11 and CPEN = 1), the gate driver of each MOSFET

provides pull-up (I_PUDiag) and a pull-down currents (I_PDDiag) at the SHx pins. This function requires an activated

charge pump.

The pull-up current source of a given half-bridge is on when the half-bridge is active: HBxMODE= 01, 10 or 11

and CPEN = 1.

The pull-down current of each low-side gate driver is activated by the control bits HBx (HB_ICHG_MAX

register).

During the off-state diagnostic routine performed by the microcontroller, the drain-source overvoltage

threshold of the relevant half-bridges must be set to 2V nominal. Refer to Table 28. Once the routine is

finished, it is highly recommended to decrease the drain-source overvoltage threshold to a lower value,

avoiding additional current consumption from the VS input.

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BLDC Driver

Supervision Functions

The following failures can be detected:

•

MOSFET short circuit to GND

MOSFET short circuit the battery

Open load (disconnected motor)

The status of the output voltages VOUTx, can be read back with status bit HBxVOUT (register GEN_STAT) when

the corresponding half-bridge is in off-state (HBxMODE[1:0] = 11).

Note:

HBxVOUT = 0 if the half-bridge x is not actively off (HBxMODE[1:0] = (0,0), (0,1) or (1,0) and CPEN=1)

or when the charge pump is deactivated (CPEN=0).

10.9.1.4 Charge pump undervoltage

The voltage of the charge pump output (VCP) is monitored in order to ensure a correct control of the external

MOSFETs.

The charge pump undervoltage threshold is configurable by the control bits FET_LVL and CPUVTH.

Table 31 Charge pump undervoltage thresholds

FET_LVL = 0

FET_LVL = 1

CPUVTH = 0

CPUVTH = 1

V

_CPUV1(6 V typ. referred to VS)

_CPUV2(6.5 V typ. referred to VS)

V_CPUV3(7.5 V typ. referred to VS)

V_CPUV4(8 V typ. referred to VS)

V

If VCP falls below the configured charge pump undervoltage threshold while CPEN = 1:

•

If one of the MOSFET is on, then all MOSFETs are actively turned off with their configured static discharge

current during their respective tHBxCCP active.

•

Then the gate drivers are turned off and CSA is turned off .

CP_UV is set and latched.

The CP_UV is reset and the normal operation is resumed once SUP_STAT is cleared and VCP > VCPUV.

The charge pump undervoltage detection is blanked (t_CPUVBLANK) during each new activation of the charge

pump¹⁾.

10.9.1.5 Switching parameters of MOSFETs in PWM mode

The effective switching parameters of the active MOSFETs (EN_GEN_CHECK=1), respectively PWM MOSFET

(EN_GEN_CHECK=0)can be read out with dedicated status registers:

•

The turn-on and turn off delays, noted tDON and tDOFF are reported by the status register

EFF_TDON_OFF1, EFF_TDON_OFF2, EFF_TDON_OFF3.

•

The rise and fall times, noted tRISE and tFALL, are reported by the status register TRISE_FALL1,

TRISE_FALL2, TRISE_FALL3.

10.9.2

Low-side drain-source voltage monitoring during braking

The low-side MOSFETs are turned-on while the charge pump is deactivated in the following conditions:

The slam mode is activated and PWM1/CRC is High.

•

1) Including CPEN set to 1, recovery from VS under/overvoltage, VSINT overvoltage and CP_ OT

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BLDC Driver

Supervision Functions

•

The parking braking mode is activated and the device is in Sleep Mode or Stop Mode.

VS overvoltage brake is activated and (VS > VS Overvoltage braking or VSINT > VSINT Overvoltage braking)

in all device modes if OV_BRK_EN is set.

Under these conditions, the drain-source voltage of the low-sides are monitored and the applied drain-source

overvoltage thresholds are according to VDSTH_BRK.

The applied blank time, which starts at the beginning of the brake activation, is:

•

t

_{BLK_BRAKE1}if TBLK_BRK = 0

_{BLK_BRAKE2}if TBLK_BRK = 1

During the blank time, a drain-source overvoltage of the low-sides is masked.

The applied filter time is t_{FVDS_BRAKE}

.

If a drain-source overvoltage is detected during braking , then all low-side MOSFETs are turned off (latched)

within t_{OFF_BRAKE}. SLAM_LSx_DIS (BRAKE, SLAM, PARK_BRK_EN, OV_BRK_EN are unchanged. The

corresponding status bit LSxDSOV_BRK is set in DSOV.

The low-sides can be reactivated only if all LSxDSOV_BRK bits (DSOV) are cleared (even in slam mode with the

respective LSx disabled by the SLAM_LSx_DIS bit).

If any of the status bits LSxDSOV_BRK is set, then the charge pump stays off (CPEN=1 command is accepted

but the charge pump stays disabled until all LSxDSOV_BRK are cleared).

10.9.3

VS or VSINT Overvoltage braking

The VS and VSINT overvoltage braking is activated if the OV_BRK_EN bit in BRAKE register is set regardless of

the device mode.

If VS, respectively VSINT, exceeds V_OVBR,cfgx,r(x = 0 to 7), then all low-sides MOSFETs are turned-on within

t_{ON_BRAKE}. The status bits VSOVBRAKE_ST, respectively VSINTOVBRAKE_ST, is set and latched (see DSOV

register).

If VS and VSINT decrease below V_OVBR,cfgx,r- V_HYS,cfgx(x = 0 to 7), then all low-sides MOSFETs are turned-off within

t_{OFF_BRAKE}after the filter time t_{OV_BR_FILT}.

If (VSHx - VSL) exceeds the configured threshold, then all low-sides MOSFETs are turned-off within t_{OFF_BRAKE}

after the filter time t_{FVDS_BRAKE}. The threshold is:

•

V

_{VDSMONTH0_BRAKE}if VDSTH_BRK = 0

_{VDSMONTH1_BRAKE}if VDSTH_BRK = 1

10.10

Current sense amplifier

The current sense amplifier (CSA) allows current measurements with external shunt resistor in low-side

configuration. The CSA is supplied by the charge pump (CP). Therefore, if the CP is off, then the CSA is

deactivated.

10.10.1 Unidirectional and bidirectional operation

The current sense amplifier (CSA) can work either as unidirectional or bi-directional operation. Refer to CSA

register.

Unidirectional operation CSD = 0

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BLDC Driver

Supervision Functions

In unidirectional operation, the CSA is optimized to measure the current flowing through the external shunt

resistor when VCSAP ≥ VCSAN.

VCSO = V_{REF Unidir}+ (VCSAP - VCSAN + V_OS) × G_DIFFprovided that VCSO is in the linear range^{1) 2)}

.

Bidirectional operation CSD = 1

In bidirectional operation, the CSA measures the current flowing through the external shunt resistor in both

directions: VCSAP ≥ VCSAN or VCSAP ≤ VCSAN.

The output CSO works at half-scale range: VCSO = V_{REF Bidir}+ (VCSAP - VCSAN + V_OS) × G_DIFF, provided that VCSO

is in the linear range ²⁾.

10.10.2 Gain configuration

The gain of the current sense amplifier is configurable by the configuration bits CSAG bits. Refer to Table 32.

Table 32 Configuration of the current sense amplifier gain

CSAG[1:0]

00_B

Current sense amplifier gain G_DIFF

G_DIFF10

G_DIFF20

G_DIFF40

G_DIFF60

01_B

10_B

11_B

10.10.3 Overcurrent Detection

A comparator at CSO detects overcurrent conditions. The overcurrent threshold is configurable with the OCTH

bits. Refer to Table 33 for unidirectional operation and Table 34 for bidirectional operation.

Table 33 Overcurrent detection thresholds in unidirectional operation (CSD = 0)

OCTH[1:0]

00_B

Typical Overcurrent Detection Threshold

V_CSO> V_CC1/2

01_B

V_CSO> V_CC1/2+ V_CC1/10

10_B

V_CSO> V_CC1/2+ 2 × V_CC1/10

V_CSO> V_CC1/2/2+ 3 × V_CC1/10

11_B

1) Valid if 0.5 V ≤ VCSO ≤ VCC1 - 0.5 V.

2) VCSO is clamped between VCC1 and GND.

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BLDC Driver

Supervision Functions

CSO unidirectional overcurrent detection threshold

VCSO

V_CC1

OCTH[1:0]

V_CC1/ 2 + 3 x V_CC1/ 10

V_CC1/ 2 + 2 x V_CC1/ 10

V_{OCTH4 Unidir}

V_{OCTH3 Unidir}

(1,1)

(1,0)

(0,1)

(0,0)

V_CC1/ 2 + V_CC1/ 10

V_CC1/ 2

V_{OCTH2 Unidir}

V_{OCTH1 Unidir}

V_{REF Unidir}

Typ. V_CC1/5

0V

Figure 54 Overcurrent detection thresholds in unidirectional operation (CSD = 0)

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BLDC Driver

Supervision Functions

Table 34 Overcurrent detection thresholds in bidirectional operation (CSD = 1)

OCTHx[1:0]

Typical Overcurrent Detection Threshold

00_B

01_B

10_B

11_B

V_CSO> V_CC1/2 + 2 × V_CC1/20 or V_CSO< V_CC1/2 -2 × V_CC1/20

V_CSO> V_CC1/2 + 4 × V_CC1/20 or V_CSO< V_CC1/2 - 4 × V_CC1/20

V_CSO> V_CC1/2+ 5 × V_CC1/20 or V_CSO< V_CC1/2 - 5 × V_CC1/20

V_CSO> V_CC1/2+ 6 × V_CC1/20 or V_CSO< V_CC1/2 - 6 × V_CC1/20

VCSO

V_CC1

CSO bidirectional overcurrent detection threshold

OCTH[1:0]

V_{OCTH4 BidirH}

V_{OCTH3 BidirH}

V_{OCTH2 BidirH}

V_CC1/ 2 + 6 x V_CC1/ 20

V_CC1/ 2 + 5 x V_CC1/ 20

V_CC1/ 2 + 4 x V_CC1/ 20

(1,1)

(1,0)

(0,1)

V_{OCTH1 BidirH}(0,0)

V_CC1/ 2 + 2 x V_CC1/ 20

V_{REF Bidir}

Typ. V_CC1/2

V_{OCTH1 BidirL}(0,0)

V_CC1/ 2 - 2 x V_CC1/ 20

V_{OCTH2 BidirL}

V_{OCTH3 BidirL}

V_{OCTH4 BidirL}

(0,1)

V

_CC1/ 2 - 4 x V_CC1/ 20

_CC1/ 2 - 5 x V_CC1/ 20

V

(1,0)

(1,1)

V_CC1/ 2 - 6 x V_CC1/ 20

0V

Figure 55 Overcurrent detection thresholds in bidirectional operation (CSD = 1)

It is possible to program the device behavior when an overcurrent condition is detected:

•

OCEN bit = 0 (see CSA): the device only reports the overcurrent event ( bit is set), without any change of the

gate driver states.

•

OCEN bit = 1 (see CSA): the device reports the overcurrent event ( bit is set) and actively turns off all

MOSFETs with static discharge curent:

–

The MOSFETs can be reactivated by clearing OC_CSA or by resetting the OCEN bit.

The overcurrent filter time is configurable (refer to t_FOC) by the OCFILT control bits.

_FOCrefers to the output of the current sense amplifier. The CSO settling time (2 µs max, t_SET) and the analog

t

propagation delay (< 1 µs) are not taken into account by the overcurrent filter time.

10.10.4 CSO output capacitor

The capacitor connected to CSO (CCSO) must be between 10 pF and 2.2 nF. The control bit CSO_CAP

optimizes the current consumption for CCSO < 400 pF or 400 pF < CCSO < 2.2 nF¹⁾.

Datasheet

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BLDC Driver

Supervision Functions

10.11

Electrical Characteristics

Table 35 Electrical Characteristics

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

VCC1 Monitoring; VCC1 = 5.0V Version

Undervoltage Prewarning V_PW,f

Threshold Voltage PW,f

4.53

4.60

30

4.70

4.75

50

4.84

4.90

90

V

VCC1 falling,

SPI bit is set

P_13.12.1

P_13.12.2

P_13.12.3

Undervoltage Prewarning V_PW,r

Threshold Voltage PW,r

V

VCC1 rising

6)

Undervoltage Prewarning V_PW,hys

Threshold Voltage

mV

hysteresis

VCC1 UV Prewarning

Detection Filter Time

t_{VCC1,PW_F}

V_RT1,f

V_RT1,r

V_RT2,f

V_RT2,r

V_RT3,f

V_RT3,r

V_RT4,f

5

10

14

us

V

²⁾rising and falling P_13.12.4

Reset Threshold

Voltage RT1,f

4.45

4.58

3.70

3.85

3.24

3.39

2.49

2.65

4.6

4.75

4.90

4.00

4.15

3.55

3.70

2.8

default setting;

VCC1 falling

P_13.12.5

P_13.12.6

P_13.12.7

P_13.12.8

P_13.12.9

P_13.12.10

P_13.12.11

P_13.12.12

Reset Threshold

Voltage RT1,r

4.74

3.85

4.0

default setting;

VCC1 rising

Reset Threshold

Voltage RT2,f

VCC1 falling

Reset Threshold

Voltage RT2,r

VCC1 rising

Reset Threshold

Voltage RT3,f

3.40

3.54

2.65

2.76

VS ≥ 4 V;

VCC1 falling

Reset Threshold

Voltage RT3,r

VS ≥ 4 V;

VCC1 rising

Reset Threshold

Voltage RT4,f

VS ≥ 4 V;

VCC1 falling

Reset Threshold

Voltage RT4,r

V_RT4,r

2.95

VS ≥ 4 V;

VCC1 rising

6)

Reset Threshold Hysteresis V_RT,hys

70

140

220

5.8

mV

V

P_13.12.13

P_13.12.26

VCC1 Over Voltage

Detection Threshold

Voltage

V_CC1,OV,r

V_CC1,OV,f

t_{VCC1,OV_F}

5.5

5.65

¹⁾⁶⁾rising VCC1

VCC1 Over Voltage

Detection Threshold

Voltage

5.4

51

5.55

64

5.7

80

V

⁶⁾falling VCC1

P_13.12.27

P_13.12.31

2)

VCC1 OV Detection Filter

Time

us

1) for 400 pF < CCSO < 2.2 nF, a seial resistor of min. 45 Ohm between the CSO pin and the CCSO capacitor is required,

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BLDC Driver

Supervision Functions

Table 35 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

4

Unit Note or

Test Condition

Number

Min.

Max.

VCC1 Short to GND Filter

Time

t_VCC1,SC

3.2

4.8

ms

²⁾blanking time

during power-up,

short circuit

P_13.12.32

detection for

VS ≥ VS,UV

Reset Generator; Pin RSTN

Reset Low Output Voltage V_RSTN,L

–

0.2

–

0.4

V

I_RSTN= 1 mA for

V_CC1≥ 1 V &

V_S≥ V_POR,f

P_13.12.33

P_13.12.34

Reset High Output Voltage V_RSTN,H

0.8 x

V_CC1

+

I_RSTN= -20 µA

V_CC1

0.3 V

Reset Pull-up Resistor

Reset Filter Time

R_RSTN

t_RF

10

4

20

10

40

26

kΩ

V_RSTN= 0 V

P_13.12.35

P_13.12.36

2)

µs

V

< V_RT1x

CC1

to RSTN = L see

also Chapter 10.3

Reset Delay Time 1

Reset Delay Time 2

t_RD1

t_RD2

8

10

2

12

ms

²⁾RSTN_DEL = 0

²⁾RSTN_DEL = 1

P_13.12.37

P_13.12.64

1.6

2.4

Watchdog Generator / Internal Oscillator

2)

Long Open Window

t_LW

160

0.8

200

1.0

240

1.2

ms

P_13.12.42

P_13.12.43

Internal Clock Generator

Frequency

f_CLKSBC,1

MHz

–

Minimum Waiting time during Fail-Safe Mode

Min. waiting time Fail-Safe t_FS,min80

2)3)

100

120

ms

P_13.12.45

Power-on Reset, Over / Undervoltage Protection

VSINT Power on reset rising V_POR,r

–

4.5

3

V

VSINT increasing P_13.12.46

VSINT decreasing P_13.12.47

VSINT Power on reset

falling

V_POR,f

VSINT Undervoltage

Detection Threshold

V_SINT,UV

5.3

–

6.0

V

Supply UV

P_13.12.48

threshold for VCC1

SC detection;

hysteresis

included; includes

rising and falling

threshold

Charge Pump Undervoltage

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BLDC Driver

Supervision Functions

Table 35 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

5.9

Unit Note or

Test Condition

Number

Min.

Max.

Charge Pump

Undervoltage Referred to

VS

V_CPUV1

5.4

6.4

V

FET_LVL = 0

CPUVTH = 0

falling threshold,

VS ≥6 V

P_13.12.59

Charge Pump

Undervoltage Referred to

VS

V_CPUV2

V_CPUV3

V_CPUV4

5.85

6.85

7.5

6.35

7.35

8

6.85

7.85

8.5

FET_LVL = 0

CPUVTH = 1

falling threshold,

VS ≥ 6 V

P_13.12.60

P_13.12.61

P_13.12.62

Charge Pump

Undervoltage Referred to

VS

FET_LVL = 1

CPUVTH = 0

falling threshold,

VS ≥ 6 V

Charge Pump

Undervoltage Referred to

VS

FET_LVL = 1

CPUVTH = 1

falling threshold,

VS ≥ 6 V

Charge Pump

Undervoltage Filter Time

t_CPUV

51

64

80

µs

⁶⁾VS ≥ 6 V

P_13.12.63

Charge Pump

t_CPUVBLANK

400

500

600

⁶⁾VS ≥ 6 V

P_13.12.175

Undervoltage Blank Time

VS monitoring

VS undervoltage threshold V_S,UV

4.7

19

–

5.4

V

hysteresis

included

P_13.12.66

P_13.12.68

VS overvoltage threshold V_S,OVD1

22.5

hysteresis

detection 1

included,

VS_OV_SEL = 0

VS overvoltage threshold V_S,OVD2

27.75

–

31.25

V

hysteresis

P_13.12.65

detection 2

included,

VS_OV_SEL = 1

VS undervoltage filter time t_{VSUV_FILT}

VS overvoltage filter time t_{VSOV_FILT}

Off-state open load diagnosis

5

10

14

µs

²⁾rising and falling P_13.12.71

²⁾rising and falling P_13.12.72

Pull-up diagnosis current I_PUDiag

-600

-400

-270

µA

VS ≥ 6 V

P_13.12.73

P_13.12.74

Pull-down diagnosis

current

I_PDDiag

1600

2200

2800

Diagnosis current ratio

I_{Diag_ratio}

4.25

5.25

6.25

Ratio

P_13.12.302

I_PDDiag/ I_PUDiag

Drain-source monitoring CP activated

Datasheet

113

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Supervision Functions

Table 35 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Blank time

t_BLANK

typ-

20%

587

+266

xTBLK

typ+20 ns

%

⁶⁾TBLK: decimal

valueofTBLK[3:0],

VS ≥ 6 V

P_13.12.75

Cross-current protection

time

t_CCP

typ-

20%

587

+266

xTCCP

typ+20 ns

%

⁶⁾TCCP: decimal

value of

TCCPx[3:0],

VS ≥ 6 V

P_13.12.76

HS/LS Drain-source

overvoltage 0

V_{VDSMONTH0_}0.115 0.16

0.195

0.25

0.36

0.48

0.6

V

VDSTH[2:0] = 000_B, P_13.12.77

VS≥6 V, TFVDS=00_B

CPON

HS/LS Drain-source

overvoltage 1

V_{VDSMONTH1_}0.16

0.2

0.3

0.4

0.5

0.6

0.8

2.0

VDSTH[2:0] = 001_B, P_13.12.78

VS≥6 V, TFVDS=00_B

CPON

HS/LS Drain-source

overvoltage 2

V_{VDSMONTH2_}0.24

VDSTH[2:0] = 010_B, P_13.12.79

VS≥6 V, TFVDS=00_B

CPON

HS/LS Drain-source

overvoltage 3

V_{VDSMONTH3_}0.32

VDSTH[2:0] = 011_B, P_13.12.80

VS≥6 V, TFVDS=00_B

CPON

HS/LS Drain-source

overvoltage 4

V_{VDSMONTH4_}0.4

VDSTH[2:0] = 100_B, P_13.12.81

VS≥6 V, TFVDS=00_B

CPON

HS/LS Drain-source

overvoltage 5

V_{VDSMONTH5_}0.48

0.72

0.96

2.25

VDSTH[2:0] = 101_B, P_13.12.82

VS≥6 V, TFVDS=00_B

CPON

HS/LS Drain-source

overvoltage 6

V_{VDSMONTH6_}0.64

VDSTH[2:0] = 110_B, P_13.12.83

VS≥6 V, TFVDS=00_B

CPON

HS/LS Drain-source

overvoltage 7

V_{VDSMONTH7_}1.75

VDSTH[2:0] = 111_B, P_13.12.84

VS≥6 V, TFVDS=00_B

CPON

Drain-Source monitoring - Slam mode, parking braking and VS overvoltage braking, VS or VSINT ≥ 8V

Blank time

t_{BLK_BRAKE1}4.5

7

9.5

µs

TBLK_BRK = 0,

P_13.12.85

VS or VSINT ≥ 8 V

Blank time

t_{BLK_BRAKE2}

9

11

13

µs

TBLK_BRK = 1,

P_13.12.86

VS or VSINT ≥ 8 V

VDS Filter time

t_{FVDS_BRAKE}0.5

V_{VDSMONTH0_}0.56

1

2.5

µs

V

VS or VSINT ≥ 8 V P_13.12.87

LS Drain-source

monitoring thresholds

0.8

1.05

VS or VSINT ≥ 8 V P_13.12.89

VDSTH_BRK = 0

BRAKE

LS Drain-source

monitoring thresholds

V_{VDSMONTH1_}0.15

0.22

0.29

V

VS or VSINT ≥ 8 V P_13.12.90

VDSTH_BRK = 1

BRAKE

VS Overvoltage Braking Mode

VS Overvoltage braking

config 0 rising

V_OVBR,cfg0,r

25.65 27

26.60 28

28.35

29.40

V

OV_BRK_TH=000_BP_13.12.97

OV_BRK_TH=001_BP_13.12.98

VS Overvoltage braking

config 1 rising

V_OVBR,cfg1,r

Datasheet

114

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Supervision Functions

Table 35 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

VS Overvoltage braking

config 2 rising

V_OVBR,cfg2,r

V_OVBR,cfg3,r

V_OVBR,cfg4,r

V_OVBR,cfg5,r

V_OVBR,cfg6,r

V_OVBR,cfg7,r

V_HYS,cfg0

27.55 29

28.50 30

29.45 31

30.40 32

31.35 33

32.30 34

30.45

V

µs

OV_BRK_TH=010_BP_13.12.99

OV_BRK_TH=011_BP_13.12.100

OV_BRK_TH=100_BP_13.12.101

OV_BRK_TH=101_BP_13.12.102

OV_BRK_TH=110_BP_13.12.103

OV_BRK_TH=111_BP_13.12.104

OV_BRK_TH=000_BP_13.12.105

OV_BRK_TH=001_BP_13.12.109

OV_BRK_TH=010_BP_13.12.113

OV_BRK_TH=011_BP_13.12.117

OV_BRK_TH=100_BP_13.12.121

OV_BRK_TH=101_BP_13.12.125

OV_BRK_TH=110_BP_13.12.129

OV_BRK_TH=111_BP_13.12.133

VS Overvoltage braking

config 3 rising

31.50

32.55

33.60

34.65

35.70

0.85

0.9

VS Overvoltage braking

config 4 rising

VS Overvoltage braking

config 5 rising

VS Overvoltage braking

config 6 rising

VS Overvoltage braking

config 7 rising

VS Overvoltage braking

config 0

0.64

0.74

0.80

0.85

0.93

0.97

1.03

1.1

0.75

VS Overvoltage braking

config 1

V_HYS,cfg1

0.82

0.89

0.95

1.03

1.08

1.15

1.23

15

VS Overvoltage braking

config 2

V_HYS,cfg2

0.98

1.05

1.13

1.19

1.27

1.36

20

VS Overvoltage braking

config 3

V_HYS,cfg3

VS Overvoltage braking

config 4

V_HYS,cfg4

VS Overvoltage braking

config 5

V_HYS,cfg5

VS Overvoltage braking

config 6

V_HYS,cfg6

VS Overvoltage braking

config 7

V_HYS,cfg7

6)

VS and VSINT overvoltage t_{OV_BR_FILT}

10

P_13.12.200

braking filter time

Current sense amplifier⁴⁾

Operating common mode V_CM

input voltage range

-2.0

–

2.0

V

P_13.12.138

referred to GND (CSAP -

GND) or (CSAN- GND)

Datasheet

115

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Supervision Functions

Table 35 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Common Mode Rejection CMRR

Ratio

63

69

75

77

–

dB

⁶⁾CSAG = (0,0)

CSAG = (0,1)

CSAG = (1,0)

CSAG = (1,1)

DC to 50 kHz

P_13.12.139

V

_CM= -2 … 2 V

V_CSAP= V_CSAN

6)

Settling time to 98%

t_SET

–

1500

–

2000

5000

ns

P_13.12.140

P_13.12.141

Settling time to 98% after t_{SET_GAIN}

⁶⁾After gain

gain change

change from CSN

rising edge

Input Offset voltage

V_OS

-1

0

1

mV

P_13.12.142

P_13.12.143

Current Sense Amplifier DC G_DIFF10

Gain (uncalibrated)

9.91

10.04 10.17 V/V

CSAG = (0,0)

CSAG = (0,1)

CSAG = (1,0)

CSAG = (1,1)

Current Sense Amplifier DC G_DIFF20

Gain (uncalibrated)

19.79 20.05 20.31 V/V

39.53 40.05 40.57 V/V

59.34 60.12 60.91 V/V

P_13.12.144

P_13.12.145

P_13.12.146

Current Sense Amplifier DC G_DIFF40

Gain (uncalibrated)

Current Sense Amplifier DC G_DIFF60

Gain (uncalibrated)

Gain drift

G_DRIFT

V_CSO

-0.5

0.5

–

0.5

%

V

⁶⁾Gain drift after P_13.12.151

calibration

6)

CSO single ended output

voltage range (linear

range)

V_CC1

0.5

-

P_13.12.152

Reference voltage for

unidirectional CSAx

V_{REF Unidir}

V_{REF Bidir}

-1.25% V_CC1/5 +1.25% V

CSD = 0

V_CSAP= V_CSAN

P_13.12.153

P_13.12.154

Reference voltage for

bidirectional CSAx

-1%

V_CC1/2 +1%

V

CSD = 1

V

_CSAP= V_CSAN

Overcurrent detection

5)6)

Overcurrent filter time

t_FOC

4

6

8

µs

OCFILT = 00_B

P_13.12.155

7

40

80

10

50

100

13

60

120

OCFILT = 01_B

OCFILT = 10_B

OCFILT = 11_B

OC threshold,

unidirectional

V_{OCTH1 Unidir}-4%

V_CC1/2 +4%

V

CSD = 0,

OCTH[1:0]= 00_B

P_13.12.156

P_13.12.157

OC threshold,

unidirectional

V_{OCTH2 Unidir}-4%

V_CC1/2 +4%

+

CSD = 0,

OCTH[1:0]= 01_B

V

_CC1/10

Datasheet

116

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Supervision Functions

Table 35 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

OC threshold,

unidirectional

V_{OCTH3 Unidir}-4%

V_CC1/2 +4%

V

CSD = 0,

OCTH[1:0]= 10_B

P_13.12.158

+ 2x

VCC1/1

0

OC threshold,

unidirectional

V_{OCTH4 Unidir}-4%

V_{OCTH1 BidirH}-4%

V_{OCTH2 BidirH}-4%

V_{OCTH3 BidirH}-4%

V_{OCTH4 BidirH}-4%

V_{OCTH1 BidirL}-4%

V_{OCTH2 BidirL}-4%

V_{OCTH3 BidirL}-4%

V_{OCTH4 BidirL}-4%

V_CC1/2 +4%

+ 3x

V

CSD = 0,

OCTH[1:0]= 11_B

P_13.12.159

P_13.12.160

P_13.12.161

P_13.12.162

P_13.12.163

P_13.12.164

P_13.12.165

P_13.12.166

P_13.12.167

V

_CC1/10

High OC threshold,

bidirectional

V_CC1/2 +4%

+ 2x

CSD = 1,

OCTH[1:0]= 00_B

V

_CC1/20

High OC threshold,

bidirectional

V_CC1/2 +4%

+ 4x

CSD = 1,

OCTH[1:0]= 01_B

V

_CC1/20

High OC threshold,

bidirectional

V_CC1/2 +4%

+ 5x

CSD = 1,

OCTH[1:0]= 10_B

V

_CC1/20

High OC threshold,

bidirectional

VCC1/2 +4%

+ 6x

CSD = 1,

OCTH[1:0]= 11_B

V

_CC1/20

Low OC threshold,

bidirectional

V_CC1/2 - +4%

2x

CSD = 1,

OCTH[1:0]= 00_B

V

_CC1/20

Low OC threshold,

bidirectional

V_CC1/2 - +4%

4x

CSD = 1,

OCTH[1:0]= 01_B

V

_CC1/20

Low OC threshold,

bidirectional

V_CC1/2 - +4%

5x

CSD = 1,

OCTH[1:0]= 10_B

V

_CC1/20

Low OC threshold,

bidirectional

V_CC1/2 - +4%

6x

CSD = 1,

OCTH[1:0]= 11_B

V

_CC1/20

Current Sense Amplifier Dynamic Parameters

Power Supply Rejection

Ratio

PSRR

60

–

dB

⁶⁾VCP modulated P_13.12.168

with sinewave

(100 kHz, 1 Vpp

Overtemperature Shutdown⁶⁾

Thermal Prewarning

Temperature

T_jPW

125

145

165

°C

T_jrising

P_13.12.169

Thermal Shutdown TSD1 T_jTSD1

Thermal Shutdown TSD2 T_jTSD2

170

185

200

°C

T_jrising

P_13.12.170

P_13.12.171

Datasheet

117

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Supervision Functions

Table 35 Electrical Characteristics (cont’d)

V_SINT= 5.5 V to 28 V; T_j= -40°C to +150°C; Normal Mode; all voltages with respect to ground; positive current

defined flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Typ.

25

Unit Note or

Test Condition

Number

Min.

Max.

6)

Thermal Shutdown

hysteresis

T_jTSD,hys

–

°C

P_13.12.172

TSD/TPW Filter Time

t_{TSD_TPW_F}

5

10

15

us

rising and falling, P_13.12.173

applies to all

thermal sensors

(TPW, TSD1, TSD2)

2)

Deactivation time after

thermal shutdown TSD2

t_TSD2

0.8

1

1.2

s

P_13.12.174

1) It is ensured that the threshold V_CC1,OV,ris always higher than the highest regulated V_CC1output voltage V_CC1,out4

.

2) Not subject to production test, tolerance defined by internal oscillator tolerance.

3) This time applies for all failure entries except a device thermal shutdown (TSD2 has a typ. 1 s waiting time t_TSD2).

4) 6 V ≤ V_S≤ 23 V

5)

t

_FOCrefers to the output of the current sense amplifier. The CSO settling time (2 µs max, t_SET) and the analog

propagation delay (< 1 µs)are not taken into account by the overcurrent filter time.

6) Not subject to production test, specified by design.

Datasheet

118

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

11

Serial Peripheral Interface

The Serial Peripheral Interface is the communication link between the device and the microcontroller.

The TLE9185QX is supporting multi-slave operation in full-duplex mode with 32-bit data access.

The SPI behavior for the different device modes is as follows:

•

The SPI is enabled in Init Mode, Normal Mode and Stop Mode.

The SPI is OFF in Sleep Mode, Restart Mode and Fail-Safe Mode.

11.1

SPI Block Description

The Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided

by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 56 with a

32-bit data access example).

The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After

the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content.

The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for

other use.The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is

shifted out of the output register after every rising edge on CLK. The SPI of the device is not daisy chain

capable.

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN

time

CSN low to high: data from shift register is transferred to output functions

CLK

time

Actual data

New data

LSB

MSB

0 1

SDI

0 1 2 3 4 5 6

27 28 29 30 31

+ +

time

SDI: will accept data on the falling edge of CLK signal

Actual status

New status

LSB

MSB

0

1

ERR

SDO

ERR

0 1 2 3 4 5 6

27 28 29 30 31

-

+

time

SDO: will change state on the rising edge of CLK signal

Figure 56 SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure

compared to the register description)

Datasheet

119

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.2

Failure Signalization in the SPI Data Output

When the microcontroller sends a wrong SPI command to the device, the device ignores the information.

Wrong SPI commands are either invalid device mode commands or commands which are prohibited by the

state machine to avoid undesired device or system states (see below). In this case the diagnosis bit SPI_FAIL

is set and the SPI Write command is ignored (no partial interpretation). This bit can be only reset by actively

clearing it via a SPI command.

Invalid SPI Commands leading to SPI_FAIL are listed below (in this case the SPI command is ignored):

•

Illegal state transitions:

- Going from Stop Mode to Sleep Mode. In this case the device enters Restart Mode.

- Trying to go to Stop Mode or Sleep Mode from Init Mode¹⁾. In this case Normal Mode is entered.

•

Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored and/or

the new watchdog settings are ignored respectively.

In Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration is ignored;

only WD trigger, returning to Normal Mode, triggering a device soft reset, and read & clear status registers

commands are valid SPI commands in Stop Mode; Note: No failure handling is done for the attempt to go

to Stop Mode when all bits in the register WK_CTRL is cleared because the microcontroller can leave this

mode via SPI.

•

When entering Stop Mode and WK_STAT is not cleared; SPI_FAIL will not be set but the INTN pin will be

triggered.

Changing from Stop Mode to Normal Mode and changing the other bits of the M_S_CTRL register. The

other modifications will be ignored.

Sleep Mode: attempt to go to Sleep Mode without any wake source set, i.e. when all bits in the WK_CTRL

register is cleared. In this case the SPI_FAIL bit is set and the device enters Restart Mode.

Even though the Sleep Mode command is not entered in this case, the rest of the command is executed but

restart values apply during Restart Mode; Note: At least one wake source must be activated in order to

avoid a deadlock situation in Sleep Mode.

If the only wake source is a timer and the timer is OFF, then the device will wake immediately from Sleep

Mode and enter Restart Mode.

•

Setting a longer or equal on-time than the timer period of the respective timer.

SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’.

Note:

There is no SPI fail information for unused addresses.

In case that the register or banking are accessed but they are not valid as address or banks, the

SPI_FAIL is not triggered and the cmd is ignored.

Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 56):

The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set

for following conditions:

•

in case the number of received SPI clocks is not 0 or 32.

in case RSTN is LOW and SPI frames are being sent at the same time.

1) If the device is externally configured to use SPI with CRC (by PWM1/CRC pin), the attempt to go to Stop or Sleep from Init , will

generate SPI_FAIL even if it is a SPI command with correct CRC. Still, the first SPI command will put the device from Init to Normal

Mode even if CRC is not correct (CRC_FAIL status bit will be set).

Datasheet

120

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Note:

In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is

not valid if the CLK is high on a falling edge of CSN.

The number of received SPI clocks is not 0 or 32:

The number of received input clocks is supervised to be 0 or 32 clock cycles and the input word is discarded in

case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high

during CSN edges. Both errors ( 0 or 32 bit CLK mismatch or CLK high during CSN edges ) are flagged in the

following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the clock

is received. The complete SPI command is ignored in this case.

RSTN is LOW and SPI frames are being sent at the same time:

The ERR flag will be set when the RSTN pin is triggered (during device restart) and SPI frames are being sent to

the device at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below

conditions:

•

If the command begins when RSTN is HIGH and it ends when RSTN is LOW.

If a SPI command will be sent while RSTN is LOW.

If a SPI command begins when RSTN is LOW and it ends when RSTN is HIGH.

And the SDO output will behave as follows:

•

Always when RSTN is LOW then SDO will be HIGH.

When a SPI command begins when RSTN is LOW and ends when RSTN is HIGH, then the SDO should be

ignored because wrong data will be sent.

Note:

It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled

low and SDO is observed - no SPI Clocks are sent in this case.

Note:

The ERR flag could also be set after the device has entered Fail-Safe Mode because the SPI

communication is stopped immediately.

Datasheet

121

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.3

SPI Programming

For the TLE9185QX, 7 bits are used for the address selection (BIT 6...0). Bit 7 is used to decide between Read

Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the

actual configuration and status information, 16 data bits (BIT 23...8) are used.

Writing, clearing and reading is done word wise. The SPI status bits are not cleared automatically and must be

cleared by the microcontroller. Some of the configuration bits will automatically be cleared by the device

(refer to the respective register descriptions for detailed information). In Restart Mode, the device ignores all

SPI communication, i.e. it does not interpret it.

There are two types of SPI registers:

•

Control registers: These registers are used to configure the device, e.g. mode, watchdog trigger, etc.

Status registers: These registers indicate the status of the device, e.g. wake events, warnings, failures, etc.

For the status registers, the requested information is given in the same SPI command in the data out (SDO).

For the control registers, the status of each byte is shown in the same SPI command as well. However,

configuration changes of the same register are only shown in the next SPI command (configuration changes

inside the device become valid only after CSN changes from low to high). See Figure 57.

Writing of control registers is possible in Init and Normal Mode. During Stop Mode only the change to Normal

Mode and triggering the watchdog is allowed as well as reading and clearing the status registers.

No status information can be lost, even if a bit changes right after the first 7 SPI clock cycles before the SPI

frame ends. In this case the status information field will be updated with the next SPI command. However, the

flag is already set in the relevant status register.The device status information from the SPI status registers is

transmitted in a compressed format with each SPI response on SDO in the so-called Status Information Field

register (see also Table 36). The purpose of this register is to quickly signal changes in dedicated SPI status

registers to the microcontroller.

Table 36 Status Information Field

Bit in Status

Information Field

Corresponding

Address Bit

Status Register Description

0

1

2

3

4

5

SUPPLY_STAT = OR of all bits on SUP_STAT register

TEMP_STAT = OR of all bits on THERM_STAT register

Reserved

WAKE_UP = OR of all bits on WK_STAT register

Reserved

DEV_STAT = OR of all bits on DEV_STAT except

CRC_STAT and SW_DEV

6

7

BD_STAT = OR of all bits on DSOV register

SPI_CRC_FAIL = (SPI_FAIL) OR (CRC_FAIL)

Datasheet

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MSB

LSB

DI

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R/W

Address Bits

Data Bits

CRC or Static Pattern

x

Register content of

selected address

DO

0

1

2

3

4

5

6

7

8

x

9

x

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Status Information Field

Data Bits

CRC or Static Pattern

x

time

LSB is sent first in SPI message

Figure 57 SPI Operation Mode

11.3.1

CRC

The SPI interface includes also 8 Bits (bits 24 to 31) used for Cyclic Redundancy Check (CRC) to ensure data

integrity on sent or received SPI command.

The implemented CRC is based on Autosar specification of CRC Routines revision 4.3.0 and in particular the

function CRC8-2FH.

The specification are based on the follow table:

Table 37 CRC8x2FH definition

CRC result width:

Polynomial

8 bits

2F_H

FF_H

No

Initial Value

Input data reflected

Result data reflected

XOR value

No

FF_H

DF_H

42_H

Check

Magic check

Some examples of CRC calculation are shown in the follow table:

Table 38 CRC8x2FH calculation example

Data Bytes (hexadecimal)

CRC

12

00

F2

0F

00

33

92

FF

00

01

AA

FF

22

6B

FF

00

83

00

55

FF

00

C2

C6

77

55

11

AA

BB

CC

DD

EE

FF

11

33

FF

6C

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Polynominal

The polynomial is:

x⁸+ x⁵+ x³+ x²+ x¹+ x⁰

(11.1)

Calculation in SDI and SDO

The calculation of the CRC is done considering the first 24 bits (BIT 0..23) either of SDI or SDO.

The content of SDO Payload (BIT 8..23) is referring the previous data written at the addressed register via SDI.

SDI

r

Add.

Payload - Configuration

CRC

w

PASS/FAIL

∑

SDO

Status Info. Field

From previous SPI cmd

∑

Figure 58 CRC calculation

CRC Activation and status information

For CRC activation, refer to Chapter 5.2.

The CRC status (CRC_STAT)and failure (CRC_FAIL) are readable on DEV_STAT.

Read out of the register which contains the CRC_STAT and CRC_FAIL is done ignoring the CRC field and no

failure flag are set.

The DEV_STAT register shall be cleared considering the CRC setting (ON or OFF).

The CRC_STAT bit is read only.

The CRC_FAIL is set in the follow conditions:

•

If the CRC is enabled and the µC sends wrong CRC field.

If the CRC is disabled and the µC sends wrong static pattern (no A5_H).

CRC field in case of CRC disabled

In case that the CRC is not activated, the bits needed for CRC field have to be filled with static pattern.

In case of SDI, the CRC field has to be filled with A5_H(bits 24:31).

In case of SDO, the device will always answer with 5A_H(bits 24:31).

The status of the CRC is updated accordingly in CRC_STAT bit.

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11.4

SPI Bit Mapping

The following figures show the mapping of the registers and the SPI bits of the respective registers.

The Control Registers are Read/Write Register with the following structure:

•

Device Control Registers from 000 0001_Bto 000 1011_B.

Bridge Driver Control Registers from 001 0000_Bto 001 1101_B.

Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting

of the bit after a write can be seen with a new read / write command.

The Status Registers are Read/Clear with the following structure:

•

Device Status Registers from 100 0000_Bto 100 0110_B.

Bridge Driver Status Registers from 101 0000_Bto 101 1011_B.

Product Family is 111 0000_B.

The registers can be read or can be cleared (if clearing is possible) depending on bit 7. To clear the payload of

one of the Status Registers bit 7 must be set to 1.

The registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at

the respective WKx pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared.

It is recommended for proper diagnosis to clear respective status bits for wake events or failure.

When changing to a different device mode, certain configurations bits will be cleared automatically or

modified:

•

The device mode bits are updated to the actual status, e.g. when returning to Normal Mode.

When changing to a low-power mode (Stop Mode or Sleep Mode), the diagnosis bits of the integrated

module are not cleared.

•

When changing to Stop Mode, the control bits will not be modified.

When changing to Sleep Mode, the control bits will be modified if they were not OFF or wake capable

before.

Note:

The detailed behavior of the respective SPI bits and control functions is described in Chapter 11.5,

Chapter 11.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the

device will modify respective control bits.

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Reg.

Type

7 Address Bits [bits 6...0]

16 Data Bits [bits 23...8]

for Register Selection

for Configuration & Status Information

Addresses:

0 0 0 0 0 0 1

.

0 0 0 1 0 1 1

Addresses:

0 0 1 0 0 0 0

.

0 0 1 1 1 0 1

Addresses:

1 0 0 0 0 0 0

.

1 1 1 0 0 0 0

The most important status registers are represented in the

Status Information Field

Figure 59 SPI Register Mapping Structure

The detailed register mappings for control registers and status registers are shown in Table 39 and Table 61

respectively.

11.4.1

Register Banking

In order to minimize the number of configuration registers, seven registers follow a bank structure.

The banked registers are:

•

WK_CTRL

CCP_BLK

TPRECHG

HB_ICHG

HB_PCHG_INIT

TDON_HB_CTRL

TDOFF_HB_CTRL

In these register, the first 3 bits of the payload (bit 8 to 10) select the bank that has to be configured. The rest

of the payload is used to configure the selected bank (for more details refer to the specific banked register).

In case that CRC is used, the CRC calculation is done considering the first 24 bits (from bit 0 to 23).

The banked registers can be read like the other configuration registers but in the SDO one ‘0’ is automatically

added after the status information field. Figure 60 shows the structure of SDO in banked register.

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SDI

B

K

0

B

K

1

B

K

2

R

e

s

Configuration of selected Bank

Selected Bank Content

r

w

Add.

CRC

SDO

B

K

0

B

K

1

B

K

2

Status Info. Filed

0

Figure 60 Register read Out of banked register (3 bit banking)

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11.5

SPI control registers

READ/WRITE Operation (see also Chapter 11.3):

•

The ‘POR / Soft Reset Value’ defines the register content after POR or device reset.

The ‘Restart Value’ defines the register content after device restart, where ‘x’ means the bit is unchanged.

There are different bit types:

–

‘r’ = READ: read only bits (or reserved bits).

‘rw’ = READ/WRITE: readable and writable bits.

‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the device

hardware.

•

Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be

programmed as “0”.

•

Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only).

SPI control bits are in general not cleared or changed automatically. This must be done by the

microcontroller via SPI programming. Exceptions to this behavior are stated at the respective register

description and the respective bit type is marked with a ‘h’ meaning that the device is able to change the

register content.

The registers are addressed wordwise.

Table 39 Register Overview

Register Short Name

Register Long Name

Offset Address Page

Number

SPI control registers, Device Control Registers

M_S_CTRL

HW_CTRL

Mode and Supply Control

0000001_B

0000010_B

0000011_B

0000101_B

0000110_B

0001001_B

0001011_B

130

Hardware Control

132

134

135

137

139

141

WD_CTRL

Watchdog Control

WK_CTRL

Wake-up Control

TIMER_CTRL

INT_MASK

SYS_STAT_CTRL

Timer 1 and Timer 2 Control and Selection

Interrupt Mask Control

System Status Control

SPI control registers, Control registers bridge driver

GENCTRL

CSA

General Bridge Control

0010000_B

0010001_B

0010010_B

0010011_B

0010100_B

0010101_B

0010110_B

0010111_B

0011000_B

0011001_B

142

144

146

148

150

151

153

154

155

156

Current sense amplifier

LS_VDS

Drain-Source monitoring threshold

CCP and times selection

HS_VDS

CCP_BLK

HBMODE

TPRECHG

ST_ICHG

HB_ICHG

HB_ICHG_MAX

Half-Bridge MODE

PWM pre-charge and pre-discharge time

Static charge/discharge current

PWM charge/discharge current

PWM max. pre-charge/pre-discharge current

and diagnostic pull-down

HB_PCHG_INIT

PWM pre-charge/pre-discharge initialization

0011010_B

158

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Table 39 Register Overview (cont’d)

Register Short Name

Register Long Name

Offset Address Page

Number

159

TDON_HB_CTRL

TDOFF_HB_CTRL

BRAKE

PWM inputs TON configuration

PWM inputs TOFF configuration

Brake control

0011011_B

0011100_B

0011101_B

160

161

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11.5.1

Device Control Registers

Mode and Supply Control

M_S_CTRL

Mode and Supply Control

(000 0001_B)

Reset Value: see Table 40

15

MODE

rwh

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VCC1_OV_MO

D

RSTN_

HYS

I_PEA

K_TH

RES

VCC1_RT

r

rwh

r

rw

r

rw

r

rw

Field

Bits

15:14

Type

Description

Device Mode Control

MODE

rwh

00_BNORMAL, Normal Mode

01_BSLEEP, Sleep Mode

10_BSTOP, Stop Mode

11_BRESET, Device reset: Soft reset is executed

(configuration of RSTN triggering in bit

SOFT_RESET_RO)

RES

13:11

10:9

r

Reserved, always reads as 0

VCC1_OV_MOD

rwh

Reaction in case of VCC1 Over Voltage

00_BNO, no reaction

01_BINTN, INTN event is generated

10_BRSTN, RSTN event is generated

11_BFAILSAFE, Fail-Safe Mode is entered

RES

8

7

r

Reserved, always reads as 0

RSTN_HYS

rw

VCC1 Undervoltage Reset Hysteresis Selection (see

also Chapter 10.6.1 for more information)

0_BDEFAULT, default hysteresis applies as specified

in the electrical characteristics table

1_BHIGHEST, the highest rising threshold (VRT1,R) is

always used for the release of the undervoltage

reset

RES

6

5

r

Reserved, always reads as 0

I_PEAK_TH

rw

VCC1 Active Peak Threshold Selection

0_BLOW, low VCC1 active peak threshold selected

1_BHIGH, high VCC1 active peak threshold selected

RES

4:2

1:0

r

Reserved, always reads as 0

VCC1_RT

rw

VCC1 Reset Threshold Control

00_BVRT1, Vrt1 selected (highest threshold)

01_BVRT2, Vrt2 selected

10_BVRT3, Vrt3 selected

11_BVRT4, Vrt4 selected

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Table 40 Reset of M_S_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0000 0000 x0x0 00xx_B

Notes

1. It is not possible to change from Stop Mode to Sleep Mode via SPI Command. See also the State Machine

Chapter.

2. After entering Restart Mode, the MODE bits will be automatically set to Normal Mode.

3. The SPI output will always show the previously written state with a Write Command (what has been

programmed before) .

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Hardware Control

HW_CTRL

Hardware Control

(000 0010_B)

Reset Value: see Table 41

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SOFT_

RESET RES

_RO

WD_S

TM_E

N_1

TSD2_ VS_OV SH_DI RSTN_

DEL _SEL SABLE DEL

RES

r

rw

r

rw

r

rwh

r

Field

RES

Bits

Type

Description

Reserved, always reads as 0

TSD2 minimum Waiting Time Selection

15:13

12

r

TSD2_DEL

rw

0_B1s, Minimum waiting time until TSD2 is released

again is always 1 s

1_B64s, Minimum waiting time until TSD2 is released

again is 1 s, after >16 TSD2 consecutive events, it

will extended x 64

VS_OV_SEL

SH_DISABLE

RSTN_DEL

RES

11

10

9

rw

VS OV comparator threshold change

0_B20V, Default threshold setting (V_S,OVD1

1_B30V, increased threshold setting (V_S,OVD2

)

Sample and hold circuitry disable

0_BENABLED, Gate driver S&H circuitry enabled

1_BDISABLED, Gate driver S&H circuitry disabled

Reset delay time

0_B10ms, Reset delay time 10 ms (t_RD1

1_B2ms, Reset delay time to 2 ms (t_RD2

Reserved, always reads as 0

Soft Reset Configuration

)

8:7

6

r

SOFT_RESET_RO

rw

0_BRSTN, RSTN will be triggered (pulled low) during

a Soft Reset

1_BNO_RSTN, no RSTN trigger during a Soft Reset

RES

5

r

Reserved, always reads as 0

RES

4:3

2

r

WD_STM_EN_1

rwh

Watchdog Deactivation during Stop Mode, bit1

0_BACTIVE, Watchdog is active in Stop Mode

1_BINACTIVE, Watchdog is deactivated in Stop Mode

RES

1:0

r

Reserved, always reads as 0

Table 41 Reset of HW_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR

0000 0000 0000 0000_B

Soft reset

Restart

0000 00x0 0000 0000_B

000x 00x0 0x00 0000_B

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Notes

1. WD_STM_EN_1 will also be cleared when changing from Stop Mode to Normal Mode .

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Watchdog Control

WD_CTRL

Watchdog Control

(000 0011_B)

Reset Value: see Table 42

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

WD_S

TM_E

N_0

CHEC

KSUM

WD_C

FG

RES

RES RES

rwh

WD_TIMER

rw

r

rwh

rw

r

rwh

Field

Bits

Type

Description

Watchdog Setting Check Sum Bit

CHECKSUM

15

rw

0_B0, Counts as 0 for checksum calculation

1_B1, Counts as 1 for checksum calculation

RES

14:7

6

r

Reserved, always reads as 0

WD_STM_EN_0

rwh

Watchdog Deactivation during Stop Mode, bit0

0_BACTIVE, Watchdog is active in Stop Mode

1_BINACTIVE, Watchdog is deactivated in Stop Mode

WD_CFG

5

rw

Watchdog Configuration

0_BTIMEOUT, Watchdog works as a Time-Out

watchdog

1_BWINDOW, Watchdog works as a Window

watchdog

RES

4

rwh

r

Reserved, to be set to ‘0’

RES

3

Reserved, always reads as 0

WD_TIMER

2:0

rwh

Watchdog Timer Period

000_B10ms, 10ms

001_B20ms, 20ms

010_B50ms, 50ms

011_B100ms, 100ms

100_B200ms, 200ms

101_B500ms, 500ms

110_B1s, 1s

111_B10s, 10s

Table 42 Reset of WD_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0001 0100_B

0000 0000 000x 0100_B

Notes

1. See also Chapter 10.2.4 for more information on disabling the watchdog in Stop Mode.

2. See chapter Chapter 10.2.3 for calculation of checksum.

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Wake-up Control

WK_CTRL

Wake-up Control

(000 0101_B)

Reset Value: see Table 43

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES RES

WK_FILT

WK_PUPD

RES

WK_EN

rw

RES

WK_BNK

r

rw

r

rw

Field

RES

Bits

Type

Description

15

r

Reserved, always reads as 0

RES

14

r

WK_FILT

13:11

rw

Wake-up Filter Time Configuration

000_B16us, Filter with 16 µs filter time (static sensing)

001_B64us, Filter with 64 µs filter time (static sensing)

010_BTIMER1, Filtering at the end of the on-time; filter

time of 16 µs (cyclic sensing) is selected, Timer1

011_BTIMER2, Filtering at the end of the on-time; filter

time of 16 µs (cyclic sensing) is selected, Timer2

100_B, reserved

101_B, reserved

110_B, reserved

111_B, reserved

WK_PUPD

10:9

rw

WKx Pull-Up/Pull-Down Configuration

00_BNO, No pull-up/pull-down selected

01_BPULL_DOWN, Pull-down resistor selected

10_BPULL_UP, Pull-up resistor selected

11_BAUTO, Automatic switching to pull-up or pull-

down

RES

8:7

6:5

r

Reserved, always reads as 0

WK_EN

rw

WKx Enable ,to be set to 01B¹⁾

00_BWK_OFF, WKx module OFF

01_BWK_ON, WKx module ON

10_BRES, reserved

11_BOFF, OFF

RES

4:3

2:0

r

Reserved, always reads as 0

WK_BNK

rw

WKs input Banking, to be set to 011B

011_BWK4, WK4 Module (Bank 4)

100_B, reserved

101_B, reserved

110_B, reserved

111_B, reserved

1) Warning: if WK_EN is not set to 01_B, then the device cannot wake up upon an edge of WK4.

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Table 43 Reset of WK_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0010 0000_B

00xx xxx0 0xx0 0000_B

Notes

1. At Fail-Safe Mode entry WK_EN will be automatically changed (by the device) in “01”.

2. During Fail-Safe Mode the WK_FILT bits are ignored and static-sense with 16 µs filter time is used by default.

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Timer 1 and Timer2 Control and Selection

TIMER_CTRL

Timer 1 and Timer2 Control and Selection

(000 0110_B)

Reset Value: see Table 44

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TIMER2_ON

RES

TIMER2_PER

CYCWK

rwh

TIMER1_ON

RES

TIMER1_PER

rwh

r

rwh

r

rwh

Field

Bits

Type

Description

TIMER2_ON

15:13

rwh

Timer2 On-Time Configuration

000_BOFF, OFF

001_B100us, 0.1ms on-time

010_B300us, 0.3ms on-time

011_B1ms, 1.0ms on-time

100_B10ms, 10ms on-time

101_B20ms, 20ms on-time

110_B, reserved

111_B, reserved

RES

12

r

Reserved, always reads as 0

TIMER2_PER

11:9

rwh

Timer2 Period Configuration

000_B10ms, 10ms

001_B20ms, 20ms

010_B50ms, 50ms

011_B100ms, 100ms

100_B200ms, 200ms

101_B500ms, 500ms

110_B1s, 1s

111_B2s, 2s

CYCWK

8:7

6:4

rwh

Cyclic Wake Configuration

00_BDISABLED, Timer1 and Timer2 disabled as wake-

up sources

01_BTIMER1, Timer1 is enabled as wake-up source

(Cyclic Wake)

10_BTIMER2, Timer2 is enabled as wake-up source

(Cyclic Wake)

11_B, reserved

TIMER1_ON

Timer1 On-Time Configuration

000_BOFF, OFF

001_B100us, 0.1ms on-time

010_B300us, 0.3ms on-time

011_B1ms, 1.0ms on-time

100_B10ms, 10ms on-time

101_B20ms, 20ms on-time

110_B, reserved

111_B, reserved

RES

3

r

Reserved, always reads as 0

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Field

Bits

Type

Description

TIMER1_PER

2:0

rwh

Timer1 Period Configuration

000_B10ms, 10ms

001_B20ms, 20ms

010_B50ms, 50ms

011_B100ms, 100ms

100_B200ms, 200ms

101_B500ms, 500ms

110_B1s, 1s

111_B2s, 2s

Table 44 Reset of TIMER_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

Notes

1. The timer must be first assigned and is then automatically activated as soon as the on-time is configured.

2. Timer accuracy is linked to the oscillator accuracy (see Parameter P_13.12.43).

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Interrupt Mask Control¹⁾

INT_MASK

Interrupt Mask Control

(000 1001_B)

Reset Value: see Table 45

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

INTN_ WD_S

CYC_E DM_DI

SPI_C

RC_FA

IL

SUPP

LY_ST

AT

WD_S

DM

BD_ST

AT

TEMP

_STAT

RES

RES RES

N

SABLE

r

rw

Field

RES

Bits

Type

Description

15:9

8

r

Reserved, always reads as 0

INTN_CYC_EN

rw

Periodical INTN generation

0_BDISABLED, no periodical INTN event generated in

case of pending interrupts

1_BENABLED, periodical INTN event generated in

case of pending interrupts

WD_SDM_DISABLE

WD_SDM

7

6

5

4

rw

Disable Watchdog in Software Development Mode

0_BENABLED, WD is enabled in Software

Development Mode

1_BDISABLED, WD is disabled in Software

Development Mode

Watchdog failure in Software Development Mode

0_BDISABLED, no INTN event generated in case of

WD trigger failure in Software Development Mode

1_BENABLED, one INTN event is generated in case of

WD trigger failure in Software Development Mode

SPI_CRC_FAIL

BD_STAT

SPI and CRC interrupt generation

0_BDISABLED, no INTN event generated in case of

SPI_FAIL or CRC_FAIL

1_BENABLED, one INTN event is generated n case of

SPI_FAIL or CRC_FAIL

Bridge Driver Interrupt generation

0_BDISABLED, no INTN event generated in case

BD_STAT (on Status Information Field) is set

1_BENABLED, one INTN event generated in case

BD_STAT (on Status Information Field) is set

RES

3

2

rw

Reserved, to be set to ‘0’

1) Every event will generate a signal on the INTN pin (when masked accordingly).

Even if the status-bit was already set in the corresponding status-register it can still trigger a signal on the INTN pin.

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Field

Bits

Type

Description

TEMP_STAT

1

rw

Temperature Interrupt generation

0_BDISABLED, no INTN event generated in case

TEMP_STAT (on Status Information Field) is set

1_BENABLED, one INTN event generated in case

TEMP_STAT (on Status Information Field) is set

SUPPLY_STAT

0

rw

SUPPLY Status Interrupt generation

0_BDISABLED, no INTN event generated in case

SUPPLY_STAT (on Status Information Field) is set

1_BENABLED, one INTN event generated in case

SUPPLY_STAT (on Status Information Field) is set

Table 45 Reset of INT_MASK

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0001 0100 0000_B

0000 000x xxxx xxxx_B

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Serial Peripheral Interface

System Status Control

SYS_STAT_CTRL

System Status Control

(000 1011_B)

Reset Value: see Table 46

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SYS_STAT

rw

Field

Bits

15:0

Type

rw

Description

System Status Control (bit0=LSB; bit15=MSB)

SYS_STAT

Dedicated bytes for system configuration, access only

by microcontroller. Cleared after power up and soft

reset.

Table 46 Reset of SYS_STAT_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR / Soft reset

Restart

0000 0000 0000 0000_B

xxxx xxxx xxxx xxxx_B

Note:

This register is intended for storing system configuration of the ECU by the microcontroller and is

only accessible in Normal Mode. The register is not accessible by the TLE9185QX and is also not

cleared after Fail-Safe or Restart Mode. It allows the microcontroller to quickly store system

configuration without loosing data.

Datasheet

141

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.5.2

Control registers bridge driver

General Bridge Control

GENCTRL

General Bridge Control

(001 0000_B)

Reset Value: see Table 47

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EN_GE

N_CH IHOLD

ECK

BDFR

EQ

CPUV FET_L CPST BDOV IPCHG

POCH AGCFI

FMOD

E

RES RES

AGC

CPEN

TH

VL

GA _REC ADT

rw rw rw

GDIS

LT

rw

r

rw

Field

Bits

Type

Description

BDFREQ

15

rw

Bridge driver synchronization frequency

0_B18MHz, typ. 18.75 MHz (default)

1_B37MHz, typ. 37.5 MHz

RES

14

13

12

r

Reserved, always reads as 0

RES

r

CPUVTH

rw

Charge pump under voltage (referred to VS)

0_BTH1, (default) CPUV threshold 1 for FET_LVL = 0,

CPUV threshold 1 for FET_LVL = 1

1_BTH2, CPUV threshold 2 for FET_LVL = 0, CPUV

threshold 2 for FET_LVL = 1

FET_LVL

CPSTGA

11

10

rw

External MOSFET normal / logic level selection

0_BLOGIC, Logic level MOSFET selected

1_BNORMAL, Normal level MOSFET selected(default)

Automatic switchover between dual and single

charge pump stage

0_BINACTIVE, Automatic switch over deactivated

(default)

1_BACTIVE, Automatic switch over activated

BDOV_REC

IPCHGADT

9

8

rw

Bridge driver recover from VS and VSINT

Overvoltage

0_BINACTIVE, Recover deactivated (default)

1_BACTIVE, Recover activated

Adaptation of the pre-charge and pre-discharge

current

0_B1STEP, 1 current step (default)

1_B2STEPS, 2 current steps

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Field

AGC

Bits

Type

Description

7:6

rw

Adaptive gate control

00_BINACTIVE1, (default) Adaptive gate control

disabled, pre-charge and pre-discharge disabled

01_BINACTIVE2, Adaptive gate control disabled,

precharge is enabled with IPRECHG = IPCHGINIT,

predischarge is enabled with IPREDCHG =

IPDCHGINIT

10_BACTIVE, Adaptive gate control enabled, IPRECHG

and IPREDCHG are self adapted

11_B, reserved. Adaptive gate control enabled,

IPRECHG and IPREDCHG are self adapted

CPEN

5

4

rw

CPEN

0_BDISABLED, Charge pump disabled (default)

1_BENABLED, Charge pump enabled

POCHGDIS

Postcharge disable bit

0_BENABLED, The postcharge phase is enabled

during PWM (default)

1_BDISABLED, The postcharge phase is disabled

during PWM

AGCFILT

3

2

1

0

rw

Filter for adaptive gate control

0_BNO_FILT, No filter applied (default)

1_BFILT_APPL, Filter applied

EN_GEN_CHECK

IHOLD

Detection of active / FW MOSFET

0_BDISABLED, Detection disabled (default)

1_BENABLED, Detection enabled

Gate driver hold current IHOLD

0_BTH1, (default) Charge: I_CHG15, discharge I_DCHG15

1_BTH2, Charge: I_CHG20, discharge: I_DCHG20

.

FMODE

Frequency modulation of the charge pump

0_BNO, No modulation

1_B15KHz, Modulation frequency 15.6 kHz (default)

Table 47 Reset of GENCTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 1000 0000 0001_B

x00x xxxx xxxx xxxx_B

Datasheet

143

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Current sense amplifier

CSA

Current sense amplifier

(001 0001_B)

Reset Value: see Table 48

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PWM_ CSO_

CSA_O

FF

RES

CSD

OCFILT

OCTH

CSAG

OCEN

NB

CAP

r

rw

Field

RES

Bits

Type

Description

15:11

10

r

Reserved, always reads as 0

PWM_NB

rw

Selection of 3 or 6 PWM inputs

0_B3PWM, 3 PWM inputs (default)

1_B6PWM, 6 PWM inputs

CSO_CAP

9

rw

Capacitance connected to the current sense

amplifier output (CCSO), see also Chapter 10.10.4

0_B400pF, CCSO < 400 pF (default)

1_B2nF, 400 pF < CCSO < 2.2 nF

CSD

8

rw

Direction of the current sense amplifier

0_BUNI, Unidirectional

1_BBI, Bidirectional (default)

OCFILT

7:6

Overcurrent filter time of CSO

00_B6us, 6 µs (default)

01_B10us, 10 µs

10_B50us, 50 µs

11_B100us, 100 µs

CSA_OFF

OCTH

5

rw

CSA OFF

0_BCSA_ON, CSA enabled

1_BCSA_OFF, CSA disabled (default)

4:3

Overcurrent detection threshold of CSO

00_BTH1, V_CSO> V_CC1/2+2 x V_CC1/20 or V_CSOx< V_CC1/2- 2x

V

_CC1/20 (default)

01_BTH2, V_CSO> V_CC1/2+ 4x V_CC1/20 or V_CSOx< V_CC1/2- 4x

_CC1/20

V

10_BTH3, V_CSO> V_CC1/2+ 5 x V_CC1/20 or V_CSOx< V_CC1/2- 5

xV_CC1/20

11_BTH4, V_CSO> V_CC1/2+ 6x V_CC1/20 or V_CSOx< V_CC1/2- 6x

V

_CC1/20

CSAG

2:1

0

rw

Gain of the current sense amplifier

00_B10VV, G_DIFF10(default)

01_B20VV, G_DIFF20

10_B40VV, G_DIFF40

11_B60VV, G_DIFF60

OCEN

Overcurrent shutdown Enable

0_BDISABLED, Disabled

1_BENABLED, Enabled (default)

Datasheet

144

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Table 48 Reset of CSA

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0001 0010 0001_B

0000 0xxx xxxx xxx1_B

Datasheet

145

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Drain-Source monitoring threshold LS1-3

LS_VDS

VDS monitoring threshold LS1-3

(001 0010_B)

Reset Value: see Table 49

15

14

13

TFVDS

rw

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

LS3VDSTH

LS2VDSTH

LS1VDSTH

r

rw

Field

RES

Bits

Type

Description

Reserved. Always read as 0

15:14

13:12

r

TFVDS

rw

Filter time of drain-source voltage monitoring

00_B500ns, 0.5 µs (default)

01_B1us, 1 µs

10_B2us, 2 µs

11_B6us, 6 µs

RES

11:9

8:6

r

Reserved, always reads as 0

LS3VDSTH

LS2VDSTH

LS1VDSTH

rw

LS3 drain-source overvoltage threshold

000_B160mV, 0.16 V

001_B200mV, 0.20 V (default)

010_B300mV, 0.30 V

011_B400mV, 0.40 V

100_B500mV, 0.50 V

101_B600mV, 0.60 V

110_B800mV, 0.80 V

111_B2V, 2.0 V

5:3

rw

LS2 drain-source overvoltage threshold

000_B160mV, 0.16V

001_B200mV, 0.20 V (default)

010_B300mV, 0.30 V

011_B400mV, 0.40 V

100_B500mV, 0.50 V

101_B600mV, 0.60 V

110_B800mV, 0.80 V

111_B2V, 2.0 V

2:0

rw

LS1 drain-source overvoltage threshold

000_B160mV, 0.16 V

001_B200mV, 0.20 V (default)

010_B300mV, 0.30 V

011_B400mV, 0.40 V

100_B500mV, 0.50 V

101_B600mV, 0.60 V

110_B800mV, 0.80 V

111_B2V, 2.0 V

Datasheet

146

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Table 49 Reset of LS_VDS

Register Reset Type Reset Values

Reset Short Name

Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0100 1001_B0000 0000 0000 0000

0000 000x xxxx xxxx_B

Datasheet

147

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Drain-Source monitoring Threshold HS1-3

HS_VDS

VDS monitoring threshold HS1-3

(001 0011_B)

Reset Value: see Table 50

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DEEP_

ADAP

RES

HS3VDSTH

HS2VDSTH

HS1VDSTH

r

rw

r

rw

Field

RES

Bits

Type

Description

Reserved. Always read as 0

15:14

13

r

rw

Reserved. This bit must be programmed to ‘0‘

DEEP_ADAP

12

Deep adaptation enable

0_BNO_DEEP_ADAP, Deep adaptation disabled

(default)

1_BDEEP_ADAP, Deep adaptation enabled

RES

11:9

8:6

r

Reserved, always reads as 0

HS3VDSTH

rw

HS3 drain-source overvoltage threshold

000_B160mV, 0.16 V

001_B200mV, 0.20 V (default)

010_B300mV, 0.30 V

011_B400mV, 0.40 V

100_B500mV, 0.50 V

101_B600mV, 0.60 V

110_B800mV, 0.80 V

111_B2V, 2.0 V

HS2VDSTH

5:3

rw

HS2 drain-source overvoltage threshold

000_B160mV, 0.16 V

001_B200mV, 0.20 V (default)

010_B300mV, 0.30 V

011_B400mV, 0.40 V

100_B500mV, 0.50 V

101_B600mV, 0.60 V

110_B800mV, 0.80 V

111_B2V, 2.0 V

HS1VDSTH

2:0

rw

HS1 drain-source overvoltage threshold

000_B160mV, 0.16 V

001_B200mV, 0.20 V (default)

010_B300mV, 0.30 V

011_B400mV, 0.40 V

100_B500mV, 0.50 V

101_B600mV, 0.60 V

110_B800mV, 0.80 V

111_B2V, 2.0 V

Datasheet

148

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Table 50 Reset of HS_VDS

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0100 1001_B

00xx 000x xxxx xxxx_B

Datasheet

149

Rev. 1.0

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

CCP and times selection

CCP_BLK

CCP and times selection

(001 0100_B)

Reset Value: see Table 51

15

14

TBLANK

rw

13

12

11

10

TCCP

rw

9

8

7

6

5

4

3

2

1

0

RES

CCP_BNK

r

rw

Field

Bits

Type

Description

Blank time

TBLANK

15:12

rw

nom. tHBxBLANK = 587 ns + 266 x T[3:0]_D

The CCP_BNK bits select the blank time for the FW or

active MOSFET and the half-bridge HBx

Reset of active and FW tHBxBLANK: 2450 ns typ.

TCCP

11:8

rw

Cross-current protection time

nom. tHBxCCP = 587 ns + 266 x TCCP[3:0]_D

The CCP_BNK bits select the cross-current protection

time for the FW or active MOSFET and the half-bridge

HBx

Reset of all active and FW tHBxCCP: 2450 ns typ.

RES

7:3

2:0

r

Reserved, always reads as 0

CCP_BNK

rw

Cross-current and time banking

000_BACT_HB1, Active blank and cross-current prot.

times for HB1 (default)

001_BACT_HB2, Active blank and cross-current prot.

times for HB2

010_BACT_HB3, Active blank and cross-current prot.

times for HB3

011_BRES, reserved

100_BFW_HB1, FW blank and cross-current prot. times

for HB1

101_BFW_HB2, FW blank and cross-current prot. times

for HB2

110_BFW_HB3, FW blank and cross-current prot. for

times for HB3

111_BRES, reserved

Table 51 Reset of CCP_BLK

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0111 0111 0000 0000_B

xxxx xxxx 0000 0000_B

Datasheet

150

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Half-Bridge MODE

HBMODE

Half-Bridge MODE

(001 0101_B)

Reset Value: see Table 52

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB3_

HB2_

HB1_

RES

HB3MODE AFW3 PWM_ HB2MODE AFW2 PWM_ HB1MODE AFW1 PWM_

EN

r

rw

Field

RES

Bits

Type

Description

15:12

11:10

r

Reserved, always reads as 0

HB3MODE

rw

Half-bridge 3 MODE selection

00_BPASSIVE_OFF, LS3 and HS3 are off by passive

discharge (default)

01_BLS3_ON, LS3 is ON

10_BHS3_ON, HS3 is ON

11_BACTIVE_OFF, LS3 and HS3 kept off by the active

discharge

AFW3

9

rw

Active freewheeling for half-bridge 3 during PWM

0_BDISABLED, active freewheeling disabled

1_BENABLED, active freewheeling enabled (default)

HB3_PWM_EN

HB2MODE

8

PWM mode for half-bridge 3

0_BINACTIVE, PWM deactivated for HB2(default)

1_BACTIVE, PWM activated for HB2

7:6

Half-bridge 2 MODE selection

00_BPASSIVE_OFF, LS2 and HS2 are off by passive

discharge (default)

01_BLS2_ON, LS2 is ON

10_BHS2_ON, HS2 is ON

11_BACTIVE_OFF, LS2 and HS2 kept off by the active

discharge

AFW2

5

rw

Active freewheeling for half-bridge 2 during PWM

0_BDISABLED, active freewheeling disabled

1_BENABLED, active freewheeling enabled (default)

HB2_PWM_EN

HB1MODE

4

PWM mode for half-bridge 2

0_BINACTIVE, PWM deactivated for HB2(default)

1_BACTIVE, PWM activated for HB2

3:2

Half-bridge 1 MODE selection

00_BPASSIVE_OFF, LS1 and HS1 are off by passive

discharge (default)

01_BLS1_ON, LS1 is ON

10_BHS1_ON, HS1 is ON

11_BACTIVE_OFF, LS1 and HS1 kept off by the active

discharge

Datasheet

151

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Field

Bits

Type

Description

AFW1

1

rw

Active freewheeling for half-bridge 1 during PWM

0_BDISABLED, active freewheeling disabled

1_BENABLED, active freewheeling enabled (default)

HB1_PWM_EN

0

rw

PWM mode for half-bridge 1

0_BINACTIVE, PWM deactivated for HB1 (default)

1_BACTIVE, PWM activated for HB1

Table 52 Reset of HBMODE

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0010 0010 0010_B

Datasheet

152

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

HB pre-charge and pre-discharge time

TPRECHG

HB pre-charge and pre-discharge time

(001 0110_B)

Reset Value: see Table 53

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TPCHG3

TPCHG2

TPCHG1

RES

TPCHG_BNK

r

rw

r

rw

Field

RES

Bits

Type

Description

Reserved, always reads as 0

15:13

12:10

r

TPCHG3

TPCHG2

TPCHG1

rw

If TPCHG_BNK=0: precharge time of HB 3, If

TPCHG_BNK=1: predischarge time of HB 3

9:7

6:4

rw

If TPCHG_BNK=0: precharge time of HB 2, If

TPCHG_BNK=1: predischarge time of HB 2

If TPCHG_BNK=0: precharge time of HB 1, If

TPCHG_BNK=1: predischarge time of HB 1

RES

3

r

Reserved, always read as 0

TPCHG_BNK

2:0

rw

Precharge/predischarge time selection

000_BPRECHARGE, Precharge time selected (default)

001_BPREDISCHARGE, Predischarge time selected

x1x_B, wrong setting of TPCHG_BNK

1xx_B, wrong setting of TPCHG_BNK

Table 53 Reset of TPRECHG

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

000x xxxx xxxx 0000_B

Datasheet

153

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Static charge/discharge current

ST_ICHG

Static charge/discharge current

(001 0111_B)

Reset Value: see Table 54

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

ICHGST3

ICHGST2

ICHGST1

r

rw

Field

RES

Bits

Type

Description

Reserved, always read as 0

15:12

11:8

r

ICHGST3

ICHGST2

ICHGST1

rw

Static charge and discharge currents of HB3

Refer to Table 17

Default: 0100_B- charge: I_CHG16,15.3 mA typ., discharge:

_DCHG16, 15.1 mA typ.

I

7:4

3:0

rw

Static charge and discharge currents of HB2

Refer to

Default: 0100_B- charge: I_CHG16,15.3 mA typ., discharge:

I_DCHG16, 15.1 mA typ.

Static charge and discharge currents of HB1

Refer to Table 17

Default: 0100_B- charge: I_CHG16,15.3 mA typ., discharge:

I_DCHG16, 15.1 mA typ.

Table 54 Reset of ST_ICHG

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0100 0100 0100_B

0000 xxxx xxxx xxxx_B

Datasheet

154

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

HB charge/discharge currents for PWM operation

HB_ICHG

HB charge/discharge currents for PWM operation

(001 1000_B)

Reset Value: see Table 55

15

14

13

IDCHG

rw

12

11

10

9

8

7

6

5

4

3

2

1

0

ICHG

RES

ICHG_BNK

rw

r

rw

Field

Bits

15:10

Type

Description

IDCHG

rw

If ICHG_BNK =0xx_B: Discharge current of HBx active

MOSFET

If ICHG_BNK=1xx_B: Reserved. Always read as ‘0’

Default value for all active MOSFETs discharge

currents: 001111_B, I_DCHG15

Refer to Table 25 for the configuration of the discharge

current

ICHG

9:4

If ICHG_BNK=0xx_B: Charge current of HBx active

MOSFET

If ICHG_BNK=1xx_B: Charge and discharge current of

HBx FW MOSFETs

Default value for all active MOSFETs charge currents

and all FW MOSFETs charge/discharge currents:

001101_B, I_CHG13

Refer to Table 24 for the configuration of the charge

current of the active and FW MOSFET

Refer to Table 25 for the configuration of the discharge

current of the FW MOSFET

RES

ICHG_BNK

3

r

Reserved, always read as 0

2:0

rw

Banking bits for charge and discharge currents of

active MOSFETs

000_BACT_HB1, Active MOSFET of HB1 is selected

(default)

001_BACT_HB2, Active MOSFET of HB2 is selected

010_BACT_HB3, Active MOSFET of HB3 is selected

011_BRES, reserved

100_BFW_HB1, FW MOSFET of HB1 is selected

101_BFW_HB2, FW MOSFET of HB2 is selected

110_BFW_HB3, FW MOSFET of HB3 is selected

111_BRES, reserved

Table 55 Reset of HB_ICHG

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

0011 1100 1101 0000_B

POR value valid for

ICHG_BNK = 0

Restart

xxxx xxxx xxxx 0000_B

Datasheet

155

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down

HB_ICHG_MAX

HB max. pre-charge/pre-discharge in PWM operation current and diagnostic pull-down

(001 1001_B)

Reset Value: see Table 56

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB3ID HB2ID HB1ID

RES

ICHGMAX3

ICHGMAX2

ICHGMAX1

IAG

r

rrw

rw

r

rw

Field

RES

Bits

Type

Description

Reserved, always read as 0

15

14

r

HB3IDIAG

rrw

Control of HB3 off-state current source and current

sink

0_BINACTIVE, Pull-down deactivated (default)

1_BACTIVE, Pull-down activated

HB2IDIAG

HB1IDIAG

13

12

rw

Control of HB2 pull-down for off-state diagnostic

0_BINACTIVE, Pull-down deactivated (default)

1_BACTIVE, Pull-down activated

Control of HB1 pull-down for off-state diagnostic

0_BINACTIVE, Pull-down deactivated (default)

1_BACTIVE, Pull-down activated

RES

11:8

7:6

r

Reserved, always read as 0

Reserved, always reads as 0

RES

r

ICHGMAX3

5:4

rw

Maximum drive current of HB3 during the pre-

charge and pre-discharge phases¹⁾

00_B31mA, charge I_CHG24: typ. 31.6 mA, discharge

I_DCHG24: typ. 30.9 mA (default)

01_B52mA, charge I_CHG32: typ. 52.5 mA, discharge

I_DCHG32: typ. 51.5 mA

10_B112mA, charge I_CHG52: typ. 112.2mA, discharge

I

_DCHG52: typ. 110.8 mA

11_B150mA, charge I_CHG63: typ. 150 mA, discharge

_DCHG63: typ. 150 mA

I

ICHGMAX2

3:2

rw

Maximum drive current of HB2 during the pre-

charge phase and pre-discharge phases¹⁾

00_B31mA, charge I_CHG24: typ. 31.6 mA, discharge

I_DCHG24: typ. 30.9 mA (default)

01_B52mA, charge I_CHG32: typ. 52.5 mA, discharge

I

_DCHG32: typ. 51.5 mA

10_B112mA, charge I_CHG52: typ. 112.2mA, discharge

_DCHG52: typ. 110.8 mA

I

11_B150mA, charge I_CHG63: typ. 150 mA, discharge

I_DCHG63: typ. 150 mA

Datasheet

156

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Field

Bits

Type

Description

ICHGMAX1

1:0

rw

Maximum drive current of HB1 during the pre-

charge and pre-discharge phases¹⁾

00_B31mA, charge I_CHG24: typ. 31.6 mA, discharge

I_DCHG24: typ. 30.9 mA (default)

01_B52mA, charge I_CHG32: typ. 52.5 mA, discharge

I

_DCHG32: typ. 51.5 mA

10_B112mA, charge I_CHG52: typ. 112.2mA, discharge

_DCHG52: typ. 110.8 mA

I

11_B150mA, charge I_CHG63: typ. 150 mA, discharge

I_DCHG63: typ. 150 mA

1) ICHGMAX is also the current applied during the post-charge of the PWM MOSFET.

Table 56 Reset of HB_ICHG_MAX

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0xxx 0000 00xx xxxx_B

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

HBx pre-charge/pre-dischage initialization configuration in PWM operation

HB_PCHG_INIT

HBx pre-charge/pre-discharge initialization configuration in PWM operation

(001 1010_B)

Reset Value: see Table 57

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PDCHGINIT

PCHGINIT

RES

INIT_BNK

rw

r

rw

Field

Bits

Type

Description

PDCHGINIT

15:10

rw

Initial predischarge current of HBx, IPDCHGINITx

The INIT_BNK bits select the addressed half-bridge

Default: 001111_B

Refer to Table 24

PCHGINIT

9:4

rw

Initial precharge current of HBx, IPCHGINITx

The INIT_BNK bits select the addressed half-bridge

Default: 001101_B

Refer to Table 24

RES

3

r

Reserved, always reads as 0

INIT_BNK

2:0

rw

Banking bits for Precharge an Predischarge Initial

Current

000_BHB1, precharge/discharge init. for HB1 selected

(default)

001_BHB2, precharge/discharge init. for HB2 selected

010_BHB3, precharge/discharge init. for HB3 selected

010_BRES, reserved

011_BRES, reserved

1xx_B, wrong setting of INIT_BANK

Table 57 Reset of HB_PCHG_INIT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0011 1100 1101 0000_B

xxxx xxxx xxxx 0000_B

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

HBx inputs TDON configuration

TDON_HB_CTRL

HBx inputs TDON configuration

(001 1011_B)

Reset Value: see Table 58

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TDON

RES

HB_TDON_BNK

r

rw

r

rw

Field

RES

Bits

Type

Description

Reserved, always read as 0

15:14

13:8

r

TDON

rw

Turn-on delay time of active MOSFET of HBx

The HB_TDON_BNK bits selects the turn-on delay time

of the active MOSFET of the half-bridge HBx

Nominal tDON = 53.3 ns x TDON[5:0]_D

Default: 00 1100_B: 640 ns typ.

RES

7:3

2:0

r

Reserved, always read as 0

HB_TDON_BNK

rw

Banking bits for turn-on delay time

000_BHB1, tDON of HB1 selected (default)

001_BHB2, tDON of HB2 selected

010_BHB3, tDON of HB3 selected

011_BRES, reserved

1xx_B, wrong setting of PWM_TDON_BNK

Table 58 Reset of TDON_HB_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 1100 0000 0000_B

00xx xxxx 0000 0000_B

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

HBx TDOFF configuration

TDOFF_HB_CTRL

HBx TDOFF configuration

(001 1100_B)

Reset Value: see Table 59

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TDOFF

RES

HB_TDOFF_BNK

r

rw

r

rw

Field

RES

Bits

Type

Description

Reserved, always read as 0

15:14

13:8

r

TDOFF

rw

Turn-off delay time of active MOSFET of HBx

The HB_TDOFF_BNK bits selects the turn-off delay

time of the active MOSFET of the half-bridge HBx

Nominal tDOFF = 53.3 ns x TDOFF[5:0]_D

Default: 0000 1100_B: 640 ns

RES

7:3

2:0

r

Reserved, always read as 0

HB_TDOFF_BNK

rw

Banking bits for turn-off delay time

000_BHB1, tDOFF of HB1 selected (default)

001_BHB2, tDOFF of HB2 selected

010_BHB3, tDOFF of HB3 selected

1xx_B, wrong setting of PWM_TDOFF_BNK

Table 59 Reset of TDOFF_HB_CTRL

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 1100 0000 0000_B

00xx xxxx 0000 0000_B

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Brake control

BRAKE

Brake control

(001 1101_B)

Reset Value: see Table 60

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SLAM SLAM SLAM

RES _LS3_ _LS2_ _LS1_ SLAM H_BR

VDST

PARK_ OV_B

BRK_E RK_E

TBLK_

BRK

RES

OV_BRK_TH

DIS

K

N

r

rw

Field

RES

Bits

Type

Description

15:14

13

r

Reserved, always read as 0

r

SLAM_LS3_DIS

SLAM_LS2_DIS

SLAM_LS1_DIS

12

rw

LS3 output disable during SLAM mode

0_BACTIVE, LS3 control active in Slam mode

(default)

1_BDISABLED, LS3 control disabled in Slam mode

11

10

rw

LS2 output disable during SLAM mode

0_BACTIVE, LS2 control active in Slam mode

(default)

1_BDISABLED, LS2 control disabled in Slam mode

LS1 output disable during SLAM mode

0_BACTIVE, LS1 control active in Slam mode

(default)

1_BDISABLED, LS1 control disabled in Slam mode

SLAM

9

rw

Slam mode

0_BINACTIVE, Slam mode deactivated (default)

1_BAVTIVE, Slam mode activated

VDSTH_BRK

TBLK_BRK

PARK_BRK_EN

OV_BRK_EN

RES

8

VDS Overvoltage for LS1-3 during braking

0_B800mV, V_{VDSMONTH0_BRAKE}, 0.8 V, typ. (default)

1_B220mV, V_{VDSMONTH1_BRAKE}, 0.22 V typ.

7

Blank time of VDS overvoltage during braking

0_B7uS, t_{BLK_BRAKE1},7 µs typ.

1_B11uS, t_{BLK_BRAKE2}, 11 µs typ. (default)

6

Parking brake enable

0_BDISABLED, Parking brake disabled (default)

1_BENABLED, Parking brake enabled

5

Overvoltage brake enable

0_BDISABLED, Overvoltage brake disabled

1_BENABLED, Overvoltage brake enabled (default)

4:3

Reserved, to be set to 0

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Field

Bits

Type

Description

OV_BRK_TH

2:0

rw

Overvoltage brake threshold

000_B27V, typ. 27V (default)

001_B28V, typ. 28V

010_B29V, typ. 29V

011_B30V, typ. 30V

100_B31V, typ. 31V

101_B32V, typ. 32V

110_B33V, typ. 33V

111_B34V, typ. 34V

Table 60 Reset of BRAKE

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 1010 0000_B

000x xxxx xxx0 0xxx_B

Note:

For min and max values of OV_BRK_TH, refer to Chapter 10.11.

Datasheet

162

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.6

SPI status information registers

READ/CLEAR Operation (see also Chapter 11.3):

•

One 32-bit SPI command consist of four bytes:

- The 7-bit address and one additional bit for the register access mode and

- following the two data bytes and the CRC.

The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to

the SPI bits 8...23 (see also figure).

•

There are two different bit types:

- ‘r’ = READ: read only bits (or reserved bits).

- ‘rc’ = READ/CLEAR: readable and clearable bits.

•

Reading a register is done word wise by setting the SPI bit 7 to “0” (= Read Only).

Clearing a register is done word wise by setting the SPI bit 7 to “1”. No single bits can be cleared. Therefore

the content of a SPI message (bit 8..23) doesn’t matter.

•

SPI status registers are in general not cleared or changed automatically (an exception are the x bits). This

must be done by the microcontroller via SPI command.

The registers are addressed wordwise.

Table 61 Register Overview

Register Short Name

Register Long Name

Offset Address Page

Number

SPI status information registers, Device Status Registers

SUP_STAT

Supply Voltage Fail Status

Thermal Protection Status

Device Information Status

Wake-up Source and Information Status

WK Input Level

1000000_B

1000001_B

1000010_B

1000100_B

1000101_B

164

THERM_STAT

DEV_STAT

166

167

169

170

WK_STAT

WK_LVL_STAT

SPI status information registers, Status registers bridge driver

GEN_STAT

TDREG

GEN Status register

1010000_B

1010001_B

1010010_B

171

173

175

177

Turn-on/off delay regulation register

Drain-source overvoltage HBVOUT

DSOV

EFF_TDON_OFF1

Effective MOSFET turn-on/off delay - PWM half- 1010011_B

bridge 1

EFF_TDON_OFF2

EFF_TDON_OFF3

Effective MOSFET turn-on/off delay - PWM half- 1010100_B

bridge 2

178

179

Effective MOSFET turn-on/off delay - PWM half- 1010101_B

bridge 3

TRISE_FALL1

TRISE_FALL2

TRISE_FALL3

MOSFET rise/fall time - PWM half-bridge 1

MOSFET rise/fall time - PWM half-bridge 2

MOSFET rise/fall time - PWM half-bridge 3

1010111_B

1011000_B

1011001_B

180

181

182

SPI status information registers, Family and product information register

FAM_PROD_STAT

Family and Product Identification Register

1110000_B

183

Datasheet

163

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.6.1

Device Status Registers

Supply Voltage Fail Status

SUP_STAT

Supply Voltage Fail Status

(100 0000_B)

Reset Value: see Table 62

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CP_O VCC1_

VSINT VSINT

_UV _OV

VCC1_ VCC1_ VCC1_ VCC1_

POR

RES

VS_UV VS_OV CP_UV

rc rc rc

T

UV_FS

SC

UV

OV WARN

rc

r

rc

rc rc

Field

POR

Bits

15

Type

Description

rc

Power-On reset detection

0_BNO_POR, No POR

1_BPOR, POR occurred

RES

14:13

12

r

Reserved, always reads as 0

CP_OT

rc

Charge pump overtemperature

0_BNO_CP_OT, No charge pump OT detected

1_BCP_OT, Charge pump OT detected

VCC1_UV_FS

11

rc

4th consecutive VCC1 UV-Detection

0_BNO_FAILSAFE, No Fail-Safe Mode entry due to

4th consecutive VCC1_UV

1_BFAILSAFE, Fail-Safe Mode entry due to 4th

consecutive VCC1_UV

RES

10:9

8

rc

Reserved

VSINT_UV

VSINT UV-Detection

0_BNO_UV, No Undervoltage

1_BUV_EVENT, VSINT Undervoltage detected

VSINT_OV

VS_UV

7

6

rc

VSINT OV-Detection

0_BNO_OV, No Overvoltage

1_BOV_EVENT, VSINT Overvoltage detected

VS Undervoltage Detection (V_S,UV

)

0_BNO_VS, No VS undervoltage detected

1_BVS_EVENT, VS undervoltage detected (detection

is only active when VCC1 is enabled)

VS_OV

5

rc

VS Overvoltage Detection (V_S,OV)

0_BNO_OV, No VS overvoltage detected

1_BOV_EVENT, VS overvoltage detected (detection is

only active when VCC1 is enabled)

CP_UV

4

3

rc

CP_UV

0_BNO_UV, No CP undervoltage detected

1_BUV_EVENT, CP undervoltage detected

VCC1_SC

VCC1 SC

0_BNO_SC, No VCC1 short to GND detected

1_BSC_EVENT, VCC1 short to GND

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Field

Bits

Type

Description

VCC1_UV

2

rc

VCC1 UV-Detection (due to Vrtx reset)

0_BNO_UV, No VCC1_UV detection

1_BUV_EVENT, VCC1 undervoltage detected

VCC1_OV

1

0

rc

VCC1 Overvoltage Detection

0_BNO_OV, No VCC1 overvoltage warning

1_BOV_EVENT, VCC1 overvoltage detected

VCC1_WARN

VCC1 Undervoltage Prewarning

0_BNO_UV, No VCC1 undervoltage prewarning

1_BUV_PREWARN, VCC1 undervoltage prewarning

detected

Table 62 Reset of SUP_STAT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

y000 0000 0000 0000_B

x00x xxxx xxxx xxxx_B

Notes

1. The VCC1 undervoltage prewarning threshold V_PW,f/ V_PW,ris a fixed threshold and independent of the VCC1

undervoltage reset thresholds.

2. VSINT undervoltage monitoring is not available in Stop Mode due to current consumption saving

requirements. Exception: VSINT undervoltage detection is also available in Stop Mode if the VCC1 load current

is above the active peak threshold (I_PEAK_TH) or if VCC1 is below the VCC1 prewarning threshold

(VCC1_WARN is set).

3. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on

reset (POR value = 1000 0000). However it will be cleared after a device Soft Reset command (Soft Reset value

= 0000 0000).

4. During Sleep Mode, the bits VCC1_SC, VCC1_OV and VCC1_UV will not be set when VCC1 is off.

5. The VCC1_UV bit is never updated in Restart Mode, in Init Mode it is only updated after RSTN was released, it

is always updated in Normal Mode and Stop Mode, and it is always updated in any device modes in a VCC1_SC

condition (after VCC1_UV = 1 for > 2 ms).

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Thermal Protection Status

THERM_STAT

Thermal Protection Status

(100 0001_B)

Reset Value: see Table 63

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TSD2_

SAFE

RES

TSD2 TSD1 TPW

rc rc rc

r

rc

Field

RES

Bits

Type

Description

Reserved, always reads as 0

15:4

3

r

TSD2_SAFE

rc

TSD2 Thermal Shut-Down Safe State Detection

0_BNO_TSD2_SF, No TSD2 safe state detected

1_BTSD2_SF, TSD2 safe state detected: >16

consecutive TSD2 events occurred, next TSD2

waiting time will be 64s

TSD2

TSD1

TPW

2

1

0

rc

TSD2 Thermal Shut-Down Detection

0_BNO_TSD2, No TSD2 event

1_BTSD2_EVENT, TSD2 OT detected - leading to Fail-

Safe Mode

TSD1 Thermal Shut-Down Detection

0_BNO_TSD1, No TSD1 fail

1_BTSD1_EVENT, TSD1 OT detected (affected

module is disabled)

Thermal Pre Warning

0_BNO_TPW, No Thermal Pre warning

1_BTPW, Thermal Pre warning detected

Table 63 Reset of THERM_STAT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0000 0000 0000 xxxx_B

Note:

Temperature warning and shutdown bits are not reset automatically, even if the temperature pre

warning or the TSD condition is not present anymore.

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Device Information Status

DEV_STAT

Device Information Status

(100 0010_B)

Reset Value: see Table 64

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CRC_S CRC_F

SW_D

EV

SPI_F FAILU

RES

DEV_STAT

RES

WD_FAIL

TAT

AIL

RE

r

rc

r

rh

rc

Field

RES

Bits

Type

Description

15:10

9

r

Reserved, always read as 0

CRC_STAT

CRC_FAIL

DEV_STAT

CRC STAT Information

0_BDISABLED, CRC disabled

1_BENABLED, CRC enabled

CRC Fail Information¹⁾

0_BNO_FAIL, No CRC Failure

8

rc

1_BFAIL, CRC Failure detected

7:6

Device Status before Restart Mode

00_BCLEARED, Cleared (Register must be actively

cleared)

01_BRESTART, Restart due to failure (WD fail, TSD2,

VCC1_UV, trial to access Sleep Mode without any

wake source activated); also after a wake from

Fail-Safe Mode

10_BSLEEP, Sleep Mode

11_B, reserved

RES

5

4

r

Reserved, always reads 0

SW_DEV

rh

Status of Operating Mode

0_BNORMAL, Normal operation

1_BSW_DEV, Software Development Mode is

enabled

WD_FAIL

3:2

rh

Number of WD-Failure Events

00_BNO_FAIL, No WD Fail

01_B1x, 1x WD Fail,

10_B2x, 2x WD Fail

11_B3x, more than 3xWD Fail

SPI_FAIL

FAILURE

1

0

rc

SPI Fail Information

0_BNO_FAIL, No SPI fail

1_BINVALID, Invalid SPI command detected

Failure detection

0_BNO_FAIL, No Failure

1_BFAIL, Failure occured

1) The CRC_FAIL bit will not be set in case the static CRC enabling / disabling sequence is sent (see Chapter 5.2).

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Table 64 Reset of DEV_STAT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0000 00xx xx0x xxxx_B

Notes

1. The bits DEV_STAT show the status of the device before exiting Restart Mode. Either the device came from

regular Sleep Mode or a failure (Restart Mode or Fail-Safe Mode) occurred. Coming from Sleep Mode will also

be shown if there was a trial to enter Sleep Mode without having cleared all wake flags before.

2. The WD_FAIL bits are implemented as a counter and are the only status bits, which are cleared automatically

by the device.

3. The SPI_FAIL bit can only be cleared via SPI command.

4. The bit CRC_STAT and CRC_FAIL can be read regardless the CRC setting. The SPI read command on

DEV_STAT ignores the CRC field.

Datasheet

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BLDC Driver

Serial Peripheral Interface

Wake-up Source and Information Status

WK_STAT

Wake-up Source and Information Status

(100 0100_B)

Reset Value: see Table 65

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

TIMER TIMER

2_WU 1_WU

WK4_

WU

RES

RES RES

RES

RES RES RES

r

rc

r

rc

r

Field

RES

Bits

Type

Description

15:11

r

Reserved, always reads as 0

10

9

r

TIMER2_WU

8

rc

Wake up via Timer2

0_BNO_WU, No Wake up

1_BWU, Wake up detected

TIMER1_WU

7

rc

Wake up via Timer1

0_BNO_WU, No Wake up

1_BWU, Wake up detected

RES

6:5

4

r

Reserved, always reads as 0

RES

r

WK4_WU

3

rc

Wake up via WK4

0_BNO_WU, No Wake up

1_BWU, Wake up detected

RES

2

1

0

r

Reserved, always reads as 0

Table 65 Reset of WK_STAT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0000 0xxx x000 00x0_B

Note:

At Fail-Safe Mode entry, the WK_STAT register is automatically cleared by the device.

Datasheet

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BLDC Driver

Serial Peripheral Interface

WK Input Level

WK_LVL_STAT

WK Input Level

(100 0101_B)

Reset Value: see Table 66

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

WK4_

LVL

RES

RES RES RES

r

Field

RES

Bits

Type

Description

15:5

4

r

Reserved, always reads as 0

WK4_LVL

3

Status of WK4

0_BLOW, Low Level (=0)

1_BHIGH, High Level (=1)

RES

2

1

0

r

Reserved, always reads as 0

Table 66 Reset of WK_LVL_STAT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 00x0_B

Note:

WK_LVL_STAT is updated in Normal Mode and Stop Mode and also in Init and Restart Mode. In cyclic

wake mode, the registers contain the sampled level, i.e. the registers are updated after every

sampling.

Datasheet

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.6.2

Status registers bridge driver

General Status register

GEN_STAT

General Status register

(101 0000_B)

Reset Value: see Table 67

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HB3V HB2V HB1V PWM6 PWM5 PWM4 PWM3 PWM2 PWM1

OUT OUT OUT STAT STAT STAT STAT STAT STAT

RES

r

Field

RES

Bits

Type

Description

15:10

r

Reserved, always reads as 0

9

8

HB3VOUT

HB2VOUT

HB1VOUT

Voltage level at VSH3 when HB3MODE[1:0] = 11 and

CPEN=1¹⁾

0_BLOW, VSH3 = Low : VS - VSH3 > V_HS3VDSTHx

1_BHIGH, VSH3 = High: VS - VSH3 ≤ V_HS3VDSTHx

7

6

r

Voltage level at VSH2 when HB2MODE[1:0] = 11 and

CPEN=1¹⁾

0_BLOW, VSH2 = Low : VS - VSH2 > V_HS2VDSTHx

1_BHIGH, VSH2 = High: VS - VSH2 ≤ V_HS2VDSTHx

Voltage level at VSH1 when HB1MODE[1:0] = 11 and

CPEN=1¹⁾

0_BLOW, VSH1 = Low : VS - VSH1 > V_HS1VDSTHx

1_BHIGH, VSH1 = High: VS - VSH1 ≤ V_HS1VDSTHx

PWM6STAT

PWM5STAT

PWM4STAT

PWM3STAT

PWM2STAT

PWM1STAT

5

4

3

2

1

0

r

PWM6 status

0_BLOW, PWM6 is Low

1_BHIGH, PWM6 is High

PWM5 status

0_BLOW, PWM5 is Low

1_BHIGH, PWM5 is High

PWM4 Status

0_BLOW, PWM4 is Low

1_BHIGH, PWM4 is High

PWM3 status

0_BLOW, PWM3 is Low

1_BHIGH, PWM3 is High

PWM2 Status

0_BLOW, PWM2 is Low

1_BHIGH, PWM2 is High

PWM1/CRC status

0_BLOW, PWM1/CRC is Low

1_BHIGH, PWM1/CRC is High

1) HBxVOUT = 0 if (CPEN=1 and HBxMODE ≠ 11) or CPEN=0.

Datasheet 171

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Table 67 Reset of GEN_STAT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0000 0000 xx00 000x_B

Datasheet

172

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Turn-on/off delay regulation register

TDREG

Turn-on/off delay regulation register

(101 0001_B)

Reset Value: see Table 68

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IPDCH IPDCH IPDCH

G3_ST G2_ST G1_ST

IPCHG IPCHG IPCHG

3_ST 2_ST 1_ST

TDRE TDRE TDRE

RES

G3

G2

G1

r

Field

RES

Bits

Type

Description

15:12

11

r

Reserved, always reads as 0

HB3 predischarge status

IPDCHG3_ST

IPDCHG2_ST

IPDCHG1_ST

10

0_BCLAMP, the predischarge current is equal to

0.5 mA typ. or ICHGMAX3 if AGC[1:0] = 10_Bor 11_B,

and HB3_PWM_EN = 1¹⁾

1_BNO_CLAMP, 0.5 mA < predischarge current <

ICHGMAX3¹⁾

9

8

r

HB2 predischarge status

0_BCLAMP, the predischarge current is equal to

0.5 mA typ. or ICHGMAX2 if AGC[1:0] = 10_Bor 11_B,

and HB2_PWM_EN = 1¹⁾

1_BNO_CLAMP, 0.5 mA < predischarge current <

ICHGMAX2¹⁾

HB1 predischarge status

0_BCLAMP, the predischarge current is equal to the

0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10_Bor 11_B,

and HBx_PWM_EN = 1¹⁾

1_BNO_CLAMP, 0.5 mA < predischarge current <

ICHGMAX1¹⁾

RES

7

6

r

Reserved, always reads as 0

IPCHG3_ST

HB3 precharge status

0_BCLAMP, the precharge current is equal to 0.5 mA

typ. or ICHGMAX3 if AGC[1:0] = 10_Bor 11_B, and

HB3_PWM_EN = 1¹⁾

1_BNO_CLAMP, 0.5 mA < precharge current <

ICHGMAX3¹⁾

IPCHG2_ST

5

r

HB2 precharge status

0_BCLAMP, the precharge current is equal to 0.5 mA

typ. or ICHGMAX2 if AGC[1:0] = 10_Bor 11_B, and

HB2_PWM_EN = 1¹⁾

1_BNO_CLAMP, 0.5 mA < precharge current <

ICHGMAX2¹⁾

Datasheet

173

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TLE9185QX

BLDC Driver

Serial Peripheral Interface

Field

Bits

Type

Description

IPCHG1_ST

4

r

HB1 precharge status

0_BCLAMP, the precharge current is equal to the

0.5 mA typ. or ICHGMAX1 if AGC[1:0] = 10_Bor 11_B,

and HB1_PWM_EN = 1¹⁾

1_BNO_CLAMP, 0.5 mA < precharge current <

ICHGMAX1¹⁾

RES

3

2

r

Reserved, always reads as 0

TDREG3

HB3 Regulation of turn-on/off delay

0_BNO_REG, tDON3 and tDOFF3 are not in regulation

1_BREG, tDON3 and/or tDOFF3 are in regulation

TDREG2

TDREG1

1

0

r

HB2 Regulation of turn-on/off delay

0_BNO_REG, tDON2 and tDOFF2 are not in regulation

1_BREG, tDON2 and/or tDOFF2 are in regulation

HB1 Regulation of turn-on/off delay

0_BNO_REG, tDON and tDOFF are not in regulation

1_BREG, tDON and/or tDOFF are in regulation

1) IPCHGx_ST = 1 otherwise (PWM disabled, HB in high impedance or AGC[1:0] = 00_Bor 01_B).

Table 68 Reset of TDREG

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0000 0000 xx00 000x_B

Datasheet

174

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Drain-source overvoltage status

DSOV

Drain-source overvoltage

(101 0010_B)

Reset Value: see Table 69

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VSINT

OVBR

AKE_S

T

VSOV

LS3DS LS2DS LS1DS

OC_C

SA

LS3DS HS3D LS2DS HS2D LS1DS HS1D

RES

BRAK RES OV_B OV_B OV_B RES RES

E_ST

OV

SOV

OV

SOV

OV

SOV

RK

r

rc

r

rc

r

rc

Field

RES

Bits

15

Type

Description

r

Reserved, always reads as 0

OC_CSA

14

rc

CSA Overcurrent detection

0_BNO_OC, No overcurrent detected

1_BOC, Overcurrent detected

VSINTOVBRAKE_ST

VSOVBRAKE_ST

13

12

rc

VSINT Brake status

0_BNOT_DETECT, VSINT overvoltage brake

condition is not detected

1_BDETECT, VSINT overvoltage brake conditions is

detected

VS Brake status

0_BNOT_DETECT, VS overvoltage brake conditions is

not detected

1_BDETECT, VS overvoltage brake conditions is

detected

RES

11

10

r

Reserved, always reads as 0

LS3DSOV_BRK

rc

Drain-source overvoltage on low-side 3 during

braking

0_BNO_OV, No drain-source overvoltage on LS3

1_BOV, Drain-source overvoltage on LS3

LS2DSOV_BRK

LS1DSOV_BRK

9

8

rc

Drain-source overvoltage on low-side 2 during

braking

0_BNO_OV, No drain-source overvoltage on LS2

1_BOV, Drain-source overvoltage on LS2

Drain-source overvoltage on low-side 1 during

braking

0_BNO_OV, No drain-source overvoltage on LS1

1_BOV, Drain-source overvoltage on LS1

RES

7

6

5

r

Reserved, always reads as 0

RES

r

LS3DSOV

rc

Drain-source overvoltage on low-side 3

0_BNO_OV, No drain-source overvoltage on LS3

1_BOV, Drain-source overvoltage on LS3

Datasheet

175

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Field

Bits

Type

Description

HS3DSOV

4

rc

Drain-source overvoltage on high-side 3

0_BNO_OV, No drain-source overvoltage on HS3

1_BOV, Drain-source overvoltage on HS3

LS2DSOV

HS2DSOV

LS1DSOV

HS1DSOV

3

2

1

0

rc

Drain-source overvoltage on low-side 2

0_BNO_OV, No drain-source overvoltage on LS2

1_BOV, Drain-source overvoltage on LS2

Drain-source overvoltage on high-side 2

0_BNO_OV, No drain-source overvoltage on HS2

1_BOV, Drain-source overvoltage on HS2

Drain-source overvoltage on low-side 1

0_BNO_OV, No drain-source overvoltage on LS1

1_BOV, Drain-source overvoltage on LS1

Drain-source overvoltage on high-side 1

0_BNO_OV, No drain-source overvoltage on HS1

1_BOV, Drain-source overvoltage on HS1

Table 69 Reset of DSOV

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

0xxx 0xxx 00xx xxxx_B

Datasheet

176

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Effective MOSFET turn.on/off delay - PWM half-bridge 1

EFF_TDON_OFF1

Effective MOSFET turn.on/off delay - HB1

(101 0011_B)

Reset Value: see Table 70

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TDOFF1EFF

RES

TDON1EFF

r

Field

RES

Bits

Type

Description

Reserved, always reads as 0

Effective active MOSFET turn-off delay HB1

15:14

13:8

r

TDOFF1EFF

Nominal effective tDOFF1 = 53.3 ns x TDOFF1EFF[13:8]_D

RES

7:6

5:0

r

Reserved, always reads as 0

TDON1EFF

Effective active MOSFET turn-on delay HB1

Nominal effective tDON1 = 53.3 ns x TDON1EFF[5:0]_D

Table 70 Reset of EFF_TDON_OFF1

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

00xx xxxx 00xx xxxx_B

Datasheet

177

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Effective MOSFET turn.on/off delay - PWM half-bridge 2

EFF_TDON_OFF2

Effective MOSFET turn.on/off delay - HB 2

(101 0100_B)

Reset Value: see Table 71

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TDOFF2EFF

RES

TDON2EFF

r

Field

RES

Bits

Type

Description

Reserved, always reads as 0

Effective active MOSFET turn-off delay HB2

15:14

13:8

r

TDOFF2EFF

Nominal effective tDOFF2 = 53.3 ns x TDOFF2EFF[13:8]_D

RES

7:6

5:0

r

Reserved, always reads as 0

TDON2EFF

Effective active MOSFET turn-on delay HB2

Nominal effective tDON2 = 53.3 ns x TDON2EFF[5:0]_D

Table 71 Reset of EFF_TDON_OFF2

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

00xx xxxx 00xx xxxx_B

Datasheet

178

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Effective MOSFET turn.on/off delay - PWM half-bridge 3

EFF_TDON_OFF3

Effective MOSFET turn.on/off delay - HB3

(101 0101_B)

Reset Value: see Table 72

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TDOFF3EFF

RES

TDON3EFF

r

Field

RES

Bits

Type

Description

Reserved, always reads as 0

Effective active MOSFET turn-off delay HB3

15:14

13:8

r

TDOFF3EFF

Nominal effective tDOFF3 = 53.3 ns x TDO3EFF[13:8]_D

RES

7:6

5:0

r

Reserved, always reads as 0

TDON3EFF

Effective active MOSFET turn-on delay HB3

Nominal effective tDON3 = 53.3 ns x TDON3EFF[5:0]_D

Table 72 Reset of EFF_TDON_OFF3

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

00xx xxxx 00xx xxxx_B

Datasheet

179

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

MOSFET rise/fall time - PWM half-bridge 1

TRISE_FALL1

MOSFET rise/fall time - HB1

(101 0111_B)

Reset Value: see Table 73

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TFALL1

RES

TRISE1

r

Field

RES

Bits

Type

Description

15:14

13:8

r

Reserved, always reads as 0

TFALL1

Active MOSFET fall time HB1

Nominal tFALL1 = 53.3 ns x TFALL1[5:0]_D

RES

7:6

5:0

r

Reserved, always reads as 0

TRISE1

Active MOSFET rise time HB1

Nominal tRISE1 = 53.3 ns x TRISE1[5:0]_D

Table 73 Reset of TRISE_FALL1

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

00xx xxxx 00xx xxxx_B

Datasheet

180

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

MOSFET rise/fall time - PWM half-bridge 2

TRISE_FALL2

MOSFET rise/fall time - HB2

(101 1000_B)

Reset Value: see Table 74

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TFALL2

RES

TRISE2

r

Field

RES

Bits

Type

Description

15:14

13:8

r

Reserved, always reads as 0

TFALL2

Active MOSFET fall time HB2

Nominal tFALL2 = 53.3 ns x TFALL2[5:0]_D

RES

7:6

5:0

r

Reserved, always reads as 0

TRISE2

Active MOSFET rise time HB2

Nominal tRISE2 = 53.3 ns x TRISE2[5:0]_D

Table 74 Reset of TRISE_FALL2

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

00xx xxxx 00xx xxxx_B

Datasheet

181

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

MOSFET rise/fall time - PWM half-bridge 3

TRISE_FALL3

MOSFET rise/fall time - HB3

(101 1001_B)

Reset Value: see Table 75

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

TFALL3

RES

TRISE3

r

Field

RES

Bits

Type

Description

15:14

13:8

r

Reserved, always reads as 0

TFALL3

Active MOSFET fall time HB3

Nominal tFALL3 = 53.3 ns x TFALL3[5:0]_D

RES

7:6

5:0

r

Reserved, always reads as 0

TRISE3

Active MOSFET rise time HB3

Nominal tRISE3 = 53.3 ns x TRISE3[5:0]_D

Table 75 Reset of TRISE_FALL3

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0000 0000 0000_B

00xx xxxx 00xx xxxx_B

Datasheet

182

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.6.3

Family and product information register

Family and Product Identification Register

FAM_PROD_STAT

Family and Product Identification Register (111 0000_B)

Reset Value: see Table 76

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RES

FAM

PROD

r

Field

RES

Bits

Type

Description

15:11

10:7

r

Reserved, always reads as 0

FAM

Device Family Identifier

1000_B, BLDC Driver

PROD

6:0

r

Device Product Identifier

000 0000_BTLE9562-3QX/QX, TLE9562-3QX/-3QXJ/QX

000 0001_BTLE9561-3QX/QX, TLE9561-3QX/-3QXJ/QX

000 0010_BTLE9563-3QX, TLE9563-3QX

000 0011_BTLE9564QX, TLE9564QX,TLE9185QX

001 0000_BTLE9562-3QX V33, TLE9562-3QX V33

001 0010_BTLE9563-3QX V33, TLE9563-3QX V33

001 0011_BTLE9564QX V33,

TLE9564QX V33,TLE9185QX V33

001 1000_BTLE9560QX, TLE9560-3QX/-3QXJ

Table 76 Reset of FAM_PROD_STAT

Register Reset Type Reset Values

Reset Short Name Reset Mode

Note

POR/Soft reset

Restart

0000 0100 0000 0011_B

Datasheet

183

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

11.7

Electrical Characteristics

Table 77 Electrical Characteristics: Power Stage

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

SPI frequency

1)

Maximum SPI frequency

f_SPI,max

–

6.0

MHz

V

> 3 V

P_14.7.1

CC1

SPI Interface; Logic Inputs SDI, CLK and CSN

H-input Voltage Threshold V_IH

L-input Voltage Threshold V_IL

Hysteresis of input Voltage V_IHY

–

0.7 ×

V_CC1

V

–

P_14.7.2

P_14.7.3

P_14.7.4

P_14.7.5

0.3 ×

V_CC1

–

V

–

1)

–

0.12 ×

V_CC1

–

V

Pull-up Resistance at pin

CSN

R_ICSN

20

–

40

10

80

–

kΩ

pF

–

Pull-down Resistance at pin R_ICLK/SDI

SDI and CLK

V_SDI/CLK= 0.2 × V_CC1P_14.7.6

1)

Input Capacitance at pin

CSN, SDI or CLK

C_I

V

, V_SDI, V_CLK

=

P_14.7.7

CSN

V_CC1

Logic Output SDO

H-output Voltage Level

V_SDOH

V_SDOL

0.8 ×

V_CC1

–

V

I_DOH= -2 mA

P_14.7.8

P_14.7.9

P_14.7.11

P_14.7.38

L-output Voltage Level

–

0.2 ×

V_CC1

V

I_DOL= 2 mA

1)

‘Tri-state Input Capacitance C_SDO

–

10

–

15

pF

µA

V

, V_SDI, V_CLK=

CSN

V_CC1

1)

Tri-state Leakage Current

I_SDOLK

–10

10

V

= V_CC1,

CSN

0V < V_SDO< V_CC1

Data Input Timing¹⁾

Clock Period

t_pCLK

t_CLKH

t_CLKL

160

70

–

ns

–

P_14.7.12

P_14.7.13

P_14.7.14

P_14.7.15

P_14.7.16

P_14.7.17

P_14.7.18

P_14.7.19

P_14.7.20

Clock HIGH Time

Clock LOW Time

70

Clock LOW before CSN LOW t_bef

70

CSN Setup Time

CLK Setup Time

t_lead

t_lag

160

70

Clock LOW after CSN HIGH t_beh

SDI Setup Time

SDI Hold Time

t_DISU

t_DIHO

60

40

Datasheet

184

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Serial Peripheral Interface

Table 77 Electrical Characteristics: Power Stage (cont’d)

V_SINT= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

–

Unit Note or

Test Condition

Number

Min.

Max.

Input Signal Rise Time at pin t_rIN

SDI, CLK and CSN

–

20

ns

µs

–

P_14.7.21

P_14.7.22

P_14.7.23

P_14.7.24

Input Signal Fall Time at pin t_fIN

SDI, CLK and CSN

–

3

–

20

5

–

3)

Delay Time for Mode

Changes²⁾

t_Del,Mode

CSN HIGH Time

t_CSN(high)

–

Data Output Timing¹⁾

SDO Rise Time

t_rSDO

t_fSDO

–

30

40

ns

C_L= 50 pF, 0.2 × V_CC1P_14.7.25

to 0.8 × V_CC1

SDO Fall Time

C_L= 50 pF, 0.8 × V_CC1P_14.7.26

to 0.2 × V_CC1

SDO Enable Time

SDO Disable Time

SDO Valid Time

t_ENSDO

t_DISSDO

t_VASDO

–

40

ns

LOW impedance

HIGH impedance

C_L= 50 pF

P_14.7.27

P_14.7.28

P_14.7.29

1) Not subject to production test; specified by design.

2) Applies to all mode changes triggered via SPI commands.

3) Guaranteed by design.

24

CSN

15

16

17

18

13

14

CLK

SDI

19

20

LSB

MSB

not defined

27

28

29

SDO

Flag

LSB

Figure 61 SPI Timing Diagram

Note:

Numbers in drawing correlate with the last 2 digits of the Number field in the Electrical

Characteristics table.

Datasheet

185

Rev. 1.0

2021-01-21

TLE9185QX

BLDC Driver

Application Information

12

Application Information

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

12.1

Application Diagrams

VCC1

D_rev1

C_VCC1

VSINT

L₁

T_rev1

SDI

R_Series

VS

VBAT

C_in1

SDO

CLK

CSN

C_CP

C_in5

CP

CPC1N

CPC1P

CPC2N

CPC2P

R_rev2

C_CP1

T_rev2

R_Series

RSTN

INTN

D_rev3

R_Series

C_CP2

GHx

WK4

R_Series

Q₁

SHx

GLx

C_HB1x

C_HB2x

TLE9185QX

Microcontroller

Q₂

to other bridges

SL

CSAP

CSAN

R_FILT1

R_Series

PWM1

PWM2

PWM3

PWM4

R_FILT2

R_Series

R_CSO

CSO

ADC IN

C_CSO

PWM5

PWM6

R_Series

GND

Figure 62 Application Diagram

Note:

This is a very simplified example of an application circuit. The function must be always verified in the

real application.

Before going to sleep mode, it is highly recommended keep the WK4 internal pull-up and pull-down

deactivated, keep WK4 to Low and enable the static wake for WK4. The 5V microcontroller wakes up

the device by pulling WK4 above V_{WKx_th,r}

.

Datasheet

186

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Application Information

Table 78 Bill of Material

Ref.

Typical Value

Purpose / Comment

Capacitances

C_in1

100 nF ±20%

ceramic

Input filter battery capacitor for optimum EMC behavior

C_in2

100 µF ±20%, 50 V

Electrolytic

Buffering capacitor to cut off battery spikes, depending on the

application

C_in2b

C_in3

470 µF ±20%, 50 V

Electrolytic

Buffering capacitor for bridges. Cut off battery spikes,

depending on the application

100 nF ±20%, 50 V

Ceramic

Input capacitor

C_in4

100 nF ±20%, 50 V

Ceramic

Input capacitor

C_in5

470 µF ±20%, 50 V

Electrolytic

Buffering capacitor for bridges. Cut off battery spikes,

depending on the application

C_CP

470 nF ±20%, 50 V

Ceramic

Charge-Pump buffering capacitor

C_CP1/ C_CP2

220 nF ±20%, 50 V

Ceramic

Charge-Pump flying capacitor to be placed as closed as possible

to the device pins, in order to minimize the length of the PCB

tracks

C_FILT1

1.5 nF ±20%, 16 V

Ceramic

Current-sense filtering

C_FILT2/ C_FILT3

C_CSO

22 nF ±20%, 16 V

Ceramic

Current-sense filtering

16 V

Ceramic

CSO buffering cap for a stable ADC voltage. Max 400 pF in case no

resistor is used. With 50 Ω resistor up to 2.2 nF. (See CSA

configuration register)

C_VCC1

C_HB1x

2.2 uF ±20%, 16 V

Blocking capacitor. Low ESR. Minimum 1 uF effective

capacitance

10 nF ±20%, 50 V

Ceramic

Half-Bridge EME (electromagnetic emission) and ESD

suppression filter to be placed close to the connector. Other

capacitance values might be needed depending on application

C_HB2x

560 pF ±20%, 50 V

Ceramic

Optional filter for EMI immunity to be placed close to the SHx pin

(PCB footprints highly recommended). Other capacitance values

might be needed depending on application

C

_WK1/ C_WK2

47 nF / OEM dependent

4 uH ... 6 uH

Spike filtering, as required by application, mandatory protection

for off-board connections

Inductances

L₁

Input filter for power stage - consider high current rating

(application dependent)

Datasheet

187

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Application Information

Table 78 Bill of Material (cont’d)

Ref.

Typical Value

Purpose / Comment

Resistances

R_REV1

100 kΩ ±5%

10 kΩ ±5%

5 mΩ ±1%

4.7 Ω ±5%

50 Ω ±5%

Other values needed depending on application

Device protection against reverse battery

R_REV2

R_REV3

R_SENSE

Current-sense resistor

Current-sense filtering

R_FILT1/ R_FILT2

R_CSO

Compensation for internal opamp.Depending on SPI

configuration

R_LED

1 k

Limit LED-current

R_WK1/ R_WK2

/

10 kΩ ±5%

R_{WK3 / RWK4}

R_SERIES

The value of the resistor depends on the voltage difference

between VCC1 and the microcontroller GPIO voltage

Active Components

D_REV1

D_REV2

D_REV3

T_REV1

T_REV2

Q₁/ Q₂

RR268MM600

Reverse polarity protection

Gate protection. Limit V_GS

BZX84C16

BAS21

IPZ40N04S5L-2R8

BC846

Reverse battery protection, N-MOS

Main power switches

IPZ40N04S5-3R1

Datasheet

188

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Application Information

12.2

ESD Tests

12.2.1

ESD according to IEC61000-4-2

Tests for ESD robustness according to IEC61000-4-2 “GUN test” (150 pF, 330 Ω) have been performed.

The results and test condition are available in a test report. The values for the test are listed below.

Table 79 ESD “GUN test”¹⁾²⁾

Performed Test

Result

Unit

Remarks

ESD at pin VS,VSINT,VS, WKx

versus GND

> 6

kV

positive pulse

ESD at pin VS,VSINT,VS, WKx

versus GND

< -6

kV

negative pulse

1) ESD susceptibility “ESD GUN” according to EMC 1.3 Test specification, Section 4.3 (IEC 61000-4-2). Tested by external

test house (IBEE Zwickau, EMC Test report Nr. 20.12.20).

2) ESD Test “Gun Test” is specified with external components for pins VS, VSINT, VS, WKx. See the application diagram

in Chapter 12.1 for more information.

Datasheet

189

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Application Information

12.3

Thermal Behavior of Package

Bottom view

cooling area

Detail solder

pads and vias

Top view

Figure 63 Board Setup

Board setup is defined according JESD 51-2, -5, -7.

Board: 76.2 × 114.3 × 1.5 mm3 with 2 inner copper layers (35 µm thick), with thermal via array under the

exposed pad contacting the first inner copper layer and 300 mm2 cooling area on the bottom layer (70 µm).

12.4

Further Application Information

•

The VS pin supplies the bridge driver and the charge pump, and is the sense pin for the high-side MOSFETs

drain voltage. It is therefore highly recommended to connect a 100 nF / 50V ceramic by-pass capacitor as

close as possible to the VS pin with a short PCB trace to GND.

•

Please contact us for information regarding the FMEA pin

For further information you may contact http://www.infineon.com/

Datasheet

190

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Package Outlines

13

Package Outlines

0ꢀ9 MAXꢀ

(0ꢀ65)

11 x 0ꢀ5 = 5ꢀ5

0ꢀ5

0ꢀ1

7

A

0ꢀ03

6ꢀ8

0ꢀ1

+0ꢀ03¹⁾

2)

37

B

36

25

24

13

48x

0ꢀ08

48

1

12

Index Marking

48x

0ꢀ1

0ꢀ4 x 45°

0ꢀ05

Index Marking

0ꢀ23

M

A B C

(0ꢀ2)

0ꢀ05 MAXꢀ

(5ꢀ2)

(6)

C

1) Vertical burr 0ꢀ03 maxꢀ, all sides

2) These four metal areas have exposed diepad potential

PG-VQFN-48-29, -31-PO V05

Figure 64 PG-VQFN-48¹⁾

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

1) Dimensions in mm

Datasheet

191

Rev.1.0

2021-01-21

TLE9185QX

BLDC Driver

Revision History

14

Revision History

Revision Date

Changes

1.0

2021-01-21

First release

Datasheet

192

Rev.1.0

2021-01-21

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2021-01-21

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

a written document signed by


型号：	TLE9185QX
厂家：	Infineon
描述：	The BLDC Driver IC provides main functions such as a 5 V low-dropout voltage regulator, three half-bridges for BDLC motor control, one current sense amplifier and one 32 bit SPI interface. The device includes diagnostic and supervision features and is intended to operate with 5.0 V microcontrollers.
文件：	总193页 (文件大小：5694K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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