TLE94104EP [INFINEON]

TLE9410EP 是受保护的四倍半桥驱动器，专为汽车运动控制应用而设计，如加热以及通风和空调 (HVAC) 活门直流电机控制。该产品是系列产品中的一款，该系列产品提供半桥驱动器，有 3 个输出到 12 个输出，具有直接接口或 SPI 接口。半桥驱动器设计用于以串联或并联方式驱动直流电机负载。通过 16 位 SPI 接口控制正向 (cw)、反向 (ccw)、制动和高阻抗工作模式。它可以提供短路、开路负载、电源故障和过温检测等诊断功能。结合极低的静态电流，该器件在汽车应用领域极具吸引力。精密小巧的散热焊盘封装 PG-TSDSO-14，提供良好的热性能，节省 PCB 板空间和成本。;


型号：	TLE94104EP
厂家：	Infineon
描述：	TLE9410EP 是受保护的四倍半桥驱动器，专为汽车运动控制应用而设计，如加热以及通风和空调 (HVAC) 活门直流电机控制。该产品是系列产品中的一款，该系列产品提供半桥驱动器，有 3 个输出到 12 个输出，具有直接接口或 SPI 接口。半桥驱动器设计用于以串联或并联方式驱动直流电机负载。通过 16 位 SPI 接口控制正向 (cw)、反向 (ccw)、制动和高阻抗工作模式。它可以提供短路、开路负载、电源故障和过温检测等诊断功能。结合极低的静态电流，该器件在汽车应用领域极具吸引力。精密小巧的散热焊盘封装 PG-TSDSO-14，提供良好的热性能，节省 PCB 板空间和成本。空调 PC 电机驱动驱动器
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中文：	中文翻译
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TLE94104EP

Features

•

Four half bridge power outputs

Very low power consumption in sleep mode

3.3V / 5V compatible inputs with hysteresis

All outputs with overload and short circuit protection

Independently diagnosable outputs (overcurrent, open load)

Open load diagnostics in ON-state for all high-side and low-side

16-bit Standard SPI interface with daisy chain and in-frame response capability for control and diagnosis

Fast diagnosis with the global error flag

Overtemperature pre-warning and protection

Over- and Undervoltage lockout

Cross-current protection

Potential applications

•

HVAC Flap DC motors

Monostable and bistable relays

Side mirror x-y adjustment

Voltage controlled bipolar stepper motors

Product validation

Qualified for Automotive Applications. Product Validation according to AEC-Q100

Description

The TLE94104EP is a protected quad half-bridge driver designed especially for automotive motion control

applications such as Heating, Ventilation and Air Conditioning (HVAC) flap DC motor control. It is part of a

larger family offering half-bridge drivers from three outputs to twelve outputs with direct interface or SPI

interface.

The half bridge drivers are designed to drive DC motor loads in sequential or parallel operation. Operation

modes forward (cw), reverse (ccw), brake and high impedance are controlled from a 16-bit SPI interface. It

offers diagnosis features such as short circuit, open load, power supply failure and overtemperature

detection. In combination with its low quiescent current, this device is attractive among others for automotive

applications. The small fine pitch exposed pad package, PG-TSDSO-14, provides good thermal performance

and reduces PCB-board space and costs.

Datasheet

www.infineon.com

1.0

2017-12-07

TLE94104EP

Type

Package

Marking

TLE94104EP

PG-TSDSO-14

TLE94104

Table 1

Product Summary

Operating Voltage

Logic Supply Voltage

V_S

5.5 ... 20 V

V_DD

3.0 ... 5.5 V

40 V

Maximum Supply Voltage for Load Dump

Protection

V_S(LD)

Minimum Overcurrent Threshold

I_SD

0.9 A

Maximum On-State Path Resistance at T_j= 150°C R_{DSON(total)_HSx+LSy}

1.8 + 1.8 Ω

0.1 µA

Typical Quiescent Current at T_j= 85°C

Maximum SPI Access Frequency

I_SQ

f_SCLK

5 MHz

Datasheet

1.0

2017-12-07

TLE94104EP

Table of Contents

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

1.2

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

3.3

3.4

Characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reset Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

5.2

5.2.1

5.2.2

5.3

5.4

6.1

6.2

Half-Bridge Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Protection & Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Short Circuit of Output to Supply or Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Cross-Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Overvoltage and undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

V_SUndervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

V_SOvervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2.1

6.2.2

6.2.3

6.2.4

6.2.4.1

6.2.4.2

6.2.4.3

6.2.5

_DDUndervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1

7.1.1

7.1.2

7.1.3

7.2

7.3

7.4

7.5

7.6

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Global Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Global Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SPI protocol error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SPI with independent slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Status register change during SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SPI Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.6.1

7.7

7.7.1

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.1

Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Datasheet

1.0

2017-12-07

TLE94104EP

8.2

8.3

Thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

EMC Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Datasheet

1.0

2017-12-07

TLE94104EP

Pin Configuration

1.1

Pin Assignment

SDI

VDD

SDO

CSN

SCLK

TEST

OUT 4

OUT 3

OUT 1

OUT 2

GND

Figure 1

Pin Configuration TLE94104EP with SPI interface

1.2

Pin Definitions and Functions

Symbol

Function

SDI

Serial data input with internal pull down

Chip select Not input with internal pull up

Serial clock input with internal pull down

CSN

SCLK

TEST

Test pin. This pin can be left open or be terminated to ground.

Main supply voltage for power half bridges.

Power half-bridge 3

OUT 3

OUT 1

GND

OUT 2

OUT 4

Power half-bridge 1

Ground

Power half-bridge 2

Power half-bridge 4

Enable with internal pull-down; Places device in standby mode by pulling the EN

line Low

TEST

SDO

VDD

Test pin. This pin must be terminated to ground

Serial data output

Logic supply voltage

EDP

Exposed Die Pad; For cooling and EMC purposes only - not usable as electrical

ground. Electrical ground must be provided by pins 8. ¹⁾

1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The

exposed pad (EP) must be either left open or connected to GND. It is recommended to connect EP to GND for best

EMC and thermal performance.

Datasheet

1.0

2017-12-07

TLE94104EP

Block Diagram

VDD

Quad Half Bridge Driver

SPI Interface

UNDERVOLTAGE

OVERVOLTAGE

MONITOR

CHARGE

PUMP

BIAS

Power stage

Power driver

short to

sshhoortrttoto

shsohrootrptoeton load

battery

shsohrotrtoto

hhigighh-s-sididee

dhdriirvgiveher-rside

ddrirviveerr

MONITOR

bbaattteteryry

babtatettreyry

detection

babtatettreyry

ddeetetecctitoionn

toction

battery

ddrirviveerr

dedteetcetciotinon

driver

dedteetcetciotinon

detection

short to ground

high-side

driver

detection

CSN

SCLK

SDI

temp

tetemmpp

overtemperature

detection

tetmempp

LOGIC CONTROL & LATCH

SPI INTERFACE

sensor

OUT 1

OUT 2

OUT 3

OUT 4

sesnetsneotsmerompr p

sesentnseotsmeormrpp

sesennsosor r

temp

sensor

sesnesnosror

open load

opoepnenlolaodad

detection

open load

dedteetcetciotinon

open load

SDO

detection

current

cucrurreroenpntetn load

low-side

loloww-s-sididee

dlorloiwvwe-s-rsididee

cucrurrernetnt

control

ccuurdrreeententcttion

ccoonntrtoroll

ccuurrerenntt

ddrirviveerr

low-side

ccoonntrtoroll

current

cocnotnrtorlol

ddrirviveerr

driver

shortctontrol

short to

short to battery

shsohrotrtoto

battery

sshhoortrttoto

batte tection

sshhoortrttoto

babtatettreyry

detecstihoonrt to

bbaattteteryry

detection

bbaattteteryry

dedteetcetciotinon

low-side

driver

drey

ERROR

DETECTION

battery

ddeetetecctitoionn

odvertempenrature

GND

Figure 2

Block Diagram TLE94104EP (SPI Interface)

Datasheet

1.0

2017-12-07

TLE94104EP

Block Diagram

2.1

Voltage and current definition

Figure 3 shows terms used in this datasheet, with associated convention for positive values.

V_S

I_S

I_DD

I_SDO

I_SDI

VDD

SDO

SDI

V_DD

V_SDO

V_SDI

V_CSN

V_SCLK

I_CSN

I_SCLK

V_DSHSx

V_DSLSx

I_OUTx

SPI INTERFACE

DRIVER

CSN

SCLK

OUT x

I_EN

V_EN

GND

I_GND

Figure 3

Voltage and Current Definition

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

3.1

Absolute Maximum Ratings

Table 2

Absolute Maximum Ratings¹⁾T_j= -40°C to +150°C

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Voltages

Supply voltage

V_S

-0.3

–

P_4.1.1

Supply Voltage Slew Rate

| dV_S/dt |

V/µs V_Sincreasing and P_4.2.2

decreasing ¹⁾

Power half-bridge output voltage

Logic supply voltage

V_OUT

V_DD

-0.3

–

0 V < V_OUT< V_S

0 V < V_S< 40 V

P_4.1.2

P_4.1.3

P_4.1.4

5.5

VDD

Logic input voltages

(SDI, SCLK, CSN, EN)

V_SDI

V_SCLK

_CSN, V_EN

0 V < V_S< 40 V

0 V < V_DD< 5.5V

Logic output voltage

(SDO)

V_SDO

-0.3

–

VDD

0 V < V_S< 40 V

0 V < V_DD< 5.5V

P_4.1.5

Test pins

V_TEST

0 V < V_S< 40 V

0 V < V_DD< 5.5V

P_4.1.19

Currents

Continuous Supply Current for V_S

Current per GND pin

Output Currents

I_S

–

2.0

–

P_4.1.20

P_4.1.14

P_4.1.15

I_GND

I_OUT

-2.0

Temperatures

Junction temperature

Storage temperature

ESD Susceptibility

T_j

-40

-50

–

150

°C

–

P_4.1.8

P_4.1.9

T_stg

ESD susceptibility OUTn and VS pins V_ESD

versus GND. All other pins

grounded.

-4

–

JEDEC HBM¹⁾²⁾

P_4.1.10

ESD susceptibility all pins

ESD susceptibility corner pins

V_ESD

-2

–

JEDEC HBM¹⁾²⁾

CDM¹⁾³⁾

P_4.1.11

P_4.1.12

P_4.1.13

-500

-750

500

750

1) Not subject to production test, specified by design

2) ESD susceptibility, “JEDEC HBM” according to ANSI/ ESDA/ JEDEC JS001 (1.5 kΩ, 100pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

3.2

Functional Range

Table 3

Functional Range

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Supply voltage range for

normal operation

V_S(nor)

V_DD

5.5

–

P_4.2.1

P_4.2.3

P_4.2.4

Logic supply voltage range for

normal operation

3.0

5.5

–

Logic input voltages

(SDI, SCLK, CSN, EN)

V_SDI

V_SCLK

_CSN, V_EN

T_j

-0.3

Junction temperature

-40

–

150

°C

P_4.2.5

Note:

Within the normal functional range the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the related electrical

characteristics table.

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

3.3

Thermal Resistance

Table 4

Thermal Resistance TLE94104EP

Symbol

Parameter

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Junction to Case, T_A= -40°C

Junction to Case, T_A= 85°C

R_{thjC_cold}

R_{thjC_hot}

–

K/W

–

1) 2)

Junction to ambient, T_A= -40°C R_{thjA_cold_}

126

(1s0p, minimal footprint)

min

1) 2)

1) 3)

1) 4)

1) 5)

Junction to ambient, T_A= 85°C R_{thjA_hot_m}

(1s0p, minimal footprint)

–

134

–

K/W

Junction to ambient, T_A= -40°C R_{thjA_cold_3}

(1s0p, 300mm2 Cu)

Junction to ambient, T_A= 85°C R_{thjA_hot_30}

(1s0p, 300mm2 Cu)

Junction to ambient, T_A= -40°C R_{thjA_cold_6}

(1s0p, 600mm2 Cu)

Junction to ambient, T_A= 85°C R_{thjA_hot_60}

(1s0p, 600mm2 Cu)

Junction to ambient, T_A= -40°C R_{thjA_cold_2}

(2s2p)

s2p

Junction to ambient, T_A= 85°C R_{thjA_hot_2s}

(2s2p)

1) Not subject to production test, specified by design.

2) Specified R_thJAvalue is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip

+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with minimal footprint copper area and 35µm thickness.

Ta = -40°C, each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.

3) Specified R_thJAvalue is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip

+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 300mm2 copper area and 35µm

thickness. Ta = -40°C, each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.

4) Specified R_thJAvalue is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip

+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 600mm2 copper area and 35µm

thickness. Ta = -40°C, each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.

5) Specified R_thJAvalue is according to JEDEC JESD51-2, -3 at natural convection on FR4 2s2p board; The product (chip

+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with two inner copper layers ( 4 x 35µm Cu). Ta = -40°C,

each channel dissipates 0.2W. Ta = 85°C, each channel dissipates 0.135W.

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

3.4

Electrical Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 20 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Current Consumption, EN = GND

Supply Quiescent current

I_SQ

–

0.1

0.6

µA

-40°C ≤ T_j≤ 85°C

P_4.4.1

P_4.4.2

P_4.4.3

Logic supply quiescent current I_{DD_Q}

Total quiescent current

I_SQ+ I_{DD_Q}

Current Consumption, EN=HIGH

Supply current

I_S

–

0.13 0.5

Power drivers and P_4.4.4

power stages are

off

Supply current

I_{S_HSON}

I_DD

I_{DD_RUN}

I_S+ I_{DD_RUN}

–

1.5

0.6

2.5

2.7

All high-sides ON¹⁾²⁾P_4.4.101

Logic supply current

Total supply current

2.5

–

SPI not active

SPI 5MHz ²⁾

P_4.4.5

P_4.4.6

P_4.4.7

–

Over- and Undervoltage Lockout

Undervoltage Switch ON

voltage threshold

V_{UV ON}

V_{UV OFF}

V_{UV HY}

4.4

4.90 5.3

4.50 4.9

V_Sincreasing

V_Sdecreasing

V_{UV ON}- V_{UV OFF}

V_Sincreasing

V_Sdecreasing

V_{OV OFF}- V_{OV ON}

P_4.4.8

Undervoltage Switch OFF

voltage threshold

P_4.4.9

Undervoltage Switch ON/OFF

hysteresis

–

0.40

–

P_4.4.10

P_4.4.11

P_4.4.12

P_4.4.13

Overvoltage Switch OFF voltage V_{OV OFF}

threshold

–

Overvoltage Switch ON voltage V_{OV ON}

threshold

Overvoltage Switch ON/OFF

hysteresis

V_{OV HY}

V_DDPower-On-Reset

V_{DD POR}

2.40

2.35

–

2.63 2.90

2.57 2.85

V_DDincreasing

V_DDdecreasing

V_{DD POR}- V_{DD POffR}

P_4.4.14

P_4.4.15

P_4.4.98

V_DDPower-Off-Reset

V_{DD POffR}

V_{DD POR HY}

V_DDPower ON/OFF hysteresis

0.06

–

Static Drain-source ON-Resistance (High-Side or Low-Side)

High-Side or Low-Side R_DSON

(all outputs)

R_{DSON_HB_25C}

–

825 1200 mΩ

I_OUT= ±0.5 A;

T_j= 25 °C

P_4.4.16

P_4.4.17

High-Side or Low-Side R_DSON

(all outputs)

R_{DSON_HB_150}

–

1350 1800 mΩ

I_OUT= ±0.5 A;

T_j= 150 °C

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 20 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified) (cont’d)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Output Protection and Diagnosis of high-side (HS) channels of half-bridge output

HS Overcurrent Shutdown

Threshold

I_{SD_HS}

-1.5

-1.2

-1.2 -0.9

See Figure 5

P_4.4.20

P_4.4.21

P_4.4.22

Difference between shutdown I_{LIM_HS}

and limit current

-0.6

²⁾|I_{LIM_HS}| ≥ |I_{SD_HS|}

See Figure 5

I_{SD_HS}

Overcurrent Shutdown filter

time

t_{dSD_HS}

µs

Open Load Detection Current

I_{OLD1_HS}

-15

-8

-3

P_4.4.23

P_4.4.24

Open Load Detection filter time t_{OLD1_HS}

2000 3000 4000 µs

Output Protection and Diagnosis of low-side (LS) channels of half-bridge output

LS Overcurrent Shutdown

Threshold

I_{SD_LS}

0.9

1.2

0.6

1.5

1.2

See Figure 6

P_4.4.27

P_4.4.28

P_4.4.29

Difference between shutdown I_{LIM_LS}

and limit current

≥ I_{SD_LS}

LIM_LS

I_{SD_LS}

Figure 6

Overcurrent Shutdown filter

time

t_{dSD_LS}

µs

Open Load Detection Current

I_{OLD_LS}

P_4.4.30

P_4.4.31

Open Load Detection filter time t_{OLD_LS}

Outputs OUT(1...n) leakage current

HS leakage current in off state I_{QLHn_NOR}

HS leakage current in off state I_{QLHn_SLE}

LS Leakage current in off state I_{QLLn_NOR}

LS Leakage current in off state I_{QLLn_SLE}

2000 3000 4000 µs

-2

–

-0.5

0.5

–

µA

V_OUTn= 0V ; EN=High P_4.4.32

V_OUTn= 0V; EN=GND P_4.4.33

V_OUTn= V_S; EN=High P_4.4.34

V_OUTn= V_S; EN=GND P_4.4.35

–

0.5

Output Switching Times. See Figure 7 and Figure 8.

Slew rate of high-side and low- d_VOUT/ dt

side outputs

0.1

0.45 0.75

V/µs Resistive load =

P_4.4.36

P_4.4.37

P_4.4.38

P_4.4.39

P_4.4.40

P_4.4.41

100Ω; V_S=13.5V

Output delay time high side

driver on

t_dONH

t_dOFFH

t_dONL

t_dOFFL

µs

Resistive load =

100Ω to GND

Output delay time high side

driver off

Resistive load =

100Ω to GND

Output delay time low side

driver on

Resistive load =

100Ω to VS

Output delay time low side

driver off

100

Resistive load =

100Ω to VS

Cross current protection time, t_DHL

high to low

130 160

Resistive load =

100Ω²⁾

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 20 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified) (cont’d)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Cross current protection time, t_DLH

low to high

100

130 160

µs

Resistive load =

P_4.4.42

100Ω²⁾

Input Interface: Logic Input EN

High-input voltage

V_ENH

V_ENL

0.7 *

V_DD

–

V_DD

–

P_4.4.43

P_4.4.44

Low-input voltage

0.3 *

V_DD

Hysteresis of input voltage

Pull down resistor

V_ENHY

–

500

–

P_4.4.45

P_4.4.46

R_{PD_EN}

kΩ

V_EN= 0.2 x V_DD

SPI frequency

2) 4)

Maximum SPI frequency

f_SPI,max

–

5.0

MHz

µs

P_4.4.47

P_4.4.48

SPI INTERFACE: Delay Time from EN rising edge to first Data in

Setup time t_set150

SPI INTERFACE: Input Interface, Logic Inputs SDI, SCLK, CSN

–

²⁾See Figure 12

H-input voltage threshold

V_IH

0.7 *

V_DD

–

V_DD

–

P_4.4.50

P_4.4.51

L-input voltage threshold

V_IL

–

0.3 *

V_DD

Hysteresis of input voltage

Pull up resistor at pin CSN

V_IHY

–

500

–

kΩ

P_4.4.52

P_4.4.53

R_{PU_CSN}

V_CSN= 0.7 x V_DD

Pull down resistor at pin SDI,

SCLK

R_{PD_SDI,}

R_{PD_SCLK}

V_SDI, V_SCLK= 0.2 x V_DDP_4.4.54

Input capacitance at pin CSN, C_I

SDI or SCLK

–

0V < V_DD< 5.25V ²⁾

P_4.4.55

P_4.4.56

Input Interface, Logic Output SDO

H-output voltage level

V_SDOH

V_DD

0.4

V_DD

0.2

V_DD

I_SDOH= -1.6 mA

I_SDOL= 1.6 mA

L-output voltage level

V_SDOL

I_SDOLK

0.2

–

0.4

P_4.4.57

P_4.4.58

Tri-state Leakage Current

-1

µA

V_CSN= V_DD;

0V < V_SDO< V_DD

Tri-state input capacitance

C_SDO

–

P_4.4.59

Data Input Timing. See Figure 13 and Figure 15.

SCLK Period

t_pCLK

200

–

P_4.4.60

P_4.4.61

SCLK High Time

t_SCLKH

0.45 *

0.55 * ns

t_pCLK

SCLK Low Time

t_SCLKL

0.45 *

–

0.55 * ns

P_4.4.62

t_pCLK

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 20 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified) (cont’d)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

SCLK Low before CSN Low

CSN Setup Time

t_BEF

125

250

125

–

P_4.4.63

P_4.4.64

P_4.4.65

P_4.4.66

P_4.4.67

P_4.4.68

P_4.4.69

t_lead

–

SCLK Setup Time

t_lag

–

SCLK Low after CSN High

SDI Setup Time

t_BEH

–

t_{SDI_setup}

t_{SDI_hold}

t_rIN

–

SDI Hold Time

–

Input Signal Rise Time at pin

SDI, SCLK, CSN

–

Input Signal Fall Time at pin SDI, t_fIN

SCLK, CSN

–

µs

P_4.4.70

P_4.4.71

P_4.4.72

Delay time from EN falling edge t_DMODE

to standby mode

Minimum CSN High Time

t_CSNH

–

Data Output Timing. See Figure 13.

SDO Rise Time

SDO Fall Time

t_rSDO

t_fSDO

–

C_load= 40pF ²⁾

Low Impedance ²⁾P_4.4.75

P_4.4.73

P_4.4.74

SDO Enable Time after CSN

falling edge

t_ENSDO

SDO Disable Time after CSN

rising edge

t_DISSDO

–

High Impedance ²⁾P_4.4.76

Duty cycle of incoming clock at duty_SCLK

SCLK

–

P_4.4.77

SDO Valid Time for V_DD= 3.3V

SDO Valid Time for V_DD= 5V

Thermal warning & Shutdown

t_VASDO3

V_SDO< 0.2 x V_DD

V_SDO> 0.8 x V_DD

C_load= 40pF ²⁾

P_4.4.78

P_4.4.79

t_VASDO5

–

V_SDO< 0.2 x V_DD

V_SDO> 0.8 V_DD

C_load= 40pF ²⁾

Thermal warning junction

temperature

T_jW

120

160

135 150

175 190

°C

See Figure 9²⁾

P_4.4.80

P_4.4.81

Thermal shutdown junction

temperature

T_jSD

Thermal comparator hysteresis T_jHYS

–

°C

P_4.4.82

Difference between T_jSD-T_jW

T_jSD-T_jW

P_4.4.120

1) I_{S_HSON}does not include the load current

2) Not subject to production test, specified by design

Datasheet

1.0

2017-12-07

TLE94104EP

General Product Characteristics

3) Measured for 20% - 80% of V_S.

4) Not applicable in daisy chain configuration

Datasheet

1.0

2017-12-07

TLE94104EP

Characterization results

Performed on 5 devices, over operating temperature and nominal/extended supply range.

Typical performance characteristics

Supply quiescent current

Supply current

P_4.4.1

P_4.4.4

2.9

0.3

0.25

0.2

2.4

1.9

1.4

0.9

0.4

0.15

0.1

0.05

-0.1

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=20

VS=22V

VS=13.5V

VS=18V

VS=20V

VS=22V

Logic supply quiescent current

Logic supply current

P_4.4.2

P_4.4.5

0.7

0.65

0.6

0.5

0.4

0.3

0.2

0.1

0.55

0.5

-0.1

-50 -30 -10 10 30 50 70 90 110 130 150

-50

100

150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=20V

VS=22V

VS=5.5V

VS=13.5V VS=18V VS=20V

VS=22V

Datasheet

1.0

2017-12-07

TLE94104EP

Characterization results

HS static Drain-source ON-resistance

LS static Drain-source ON-resistance

P_4.4.16/P_4.4.17

1500

1600

1500

1400

1300

1200

1100

1000

900

1400

1300

1200

1100

1000

900

800

700

600

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=20V

VS=22V

VS=5.5V

VS=13.5V

VS=18V

VS=20V

VS=22V

HS static drain-source ON-resistance

VS = 13.5V and VDD = 5V

LS static drain-source ON-resistance

VS = 13.5V and VDD = 5V

P_4.4.16/P_4.4.17

LS Static Drain-source ON-Resistance

P_4.4.16/P_4.4.17

1500

1400

1300

1200

1100

1000

900

1400

1300

1200

1100

1000

900

800

700

600

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

OUT1

OUT2

OUT3

OUT1

OUT2

OUT3

Datasheet

1.0

2017-12-07

TLE94104EP

Characterization results

Slew rate ON of high-side outputs

Slew rate ON of low-side outputs

P_4.4.36

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=20V

VS=22

VS=5.5V

VS=13.5V

VS=18V

VS=20V

VS=22V

Slew rate OFF of high-side outputs

Slew rate OFF of low-side outputs

P_4.4.36

0.55

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.50

0.45

0.40

0.35

0.30

0.25

0.20

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13V5

VS=18V

VS=20V

VS=22V

VS=5.5V

VS=13.5V

VS=18V

VS=20V

VS=22V

Datasheet

1.0

2017-12-07

TLE94104EP

Characterization results

HS overcurrent shutdown threshold

LS overcurrent shutdown threshold

P_4.4.20

P_4.4.27

-1120

1240

1220

1200

1180

1160

1140

1120

-1140

-1160

-1180

-1200

-1220

-1240

1100

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=20V

VS=22V

VS=5.5V

VS=13.5

VS=18V

VS=20V

VS=22V

Undervoltage switch ON voltage threshold

Undervoltage switch OFF voltage threshold

P_4.4.8

P_4.4.9

5.05

4.64

4.62

4.6

4.95

4.9

4.58

4.56

4.54

4.52

4.85

4.5

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VDD=3V

VDD=5V

VDD=5.5V

VDD=3V

VDD=5V

VDD=5.5V

Datasheet

1.0

2017-12-07

TLE94104EP

Characterization results

Overvoltage switch ON voltage threshold

Overvoltage switch OFF voltage threshold

P_4.4.12

P_4.4.11

22.8

23.6

22.7

22.6

22.5

22.4

22.3

22.2

22.1

22.0

23.5

23.4

23.3

23.2

23.1

22.9

22.8

21.9

22.7

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VDD=3V

VDD=5V

VDD=5.5V

VDD=3V

VDD=5V

VDD=5.5V

VDD Power-on-reset and VDD Power-off-reset

P_4.4.14/P_4.4.15

2.68

2.66

2.64

2.62

2.60

2.58

2.56

2.54

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VDD POR

VDD POffR

Datasheet

1.0

2017-12-07

TLE94104EP

General Description

5.1

Power Supply

The TLE94104EP has two power supply inputs, V_Sand V_DD. The half bridge outputs are supplied by V_S, which is

connected to the 12V automotive supply rail. V_DDis used to supply the I/O buffers and internal voltage

regulator of the device.

V_Sand V_DDsupplies are separated so that information stored in the logic block remains intact in the event of

voltage drop outs or disturbances on V_S. The system can therefore continue to operate once V_Shas recovered,

without having to resend commands to the device.

A rising edge on V_DDcrossing V_{DD POR}triggers an internal Power-On Reset (POR) to initialize the IC at power-on.

All data stored internally is deleted, and the outputs are switched off (high impedance).

An electrolytic and 100nF ceramic capacitors are recommended to be placed as close as possible to the V_S

supply pin of the device for improved EMC performance in the high and low frequency band. The electrolytic

capacitor must be dimensioned to prevent the VS voltage from exceeding the absolute maximum rating. In

addition, decoupling capacitors are recommended on the V_DDsupply pin.

5.2

Operation modes

5.2.1

Normal mode

The TLE94104EP enters normal mode by setting the EN input High. In normal mode, the charge pump is active

and all output transistors can be configured via SPI.

5.2.2

Sleep mode

The TLE94104EP enters sleep mode by setting the EN input Low. The EN input has an internal pull-down

resistor.

In sleep mode, all output transistors are turned off and the SPI register banks are reset. The current

consumption is reduced to I_SQ+ I_{DD_Q}

5.3

Reset Behaviour

The following reset triggers have been implemented in the TLE94104EP:

_DDUndervoltage Reset:

The SPI Interface shall not function if V_DDis below the undervoltage threshold, V_{DD POffR}. The digital block will

be deactivated, the logic contents cleared and the output stages are switched off . The digital block is

initialized once V_DDvoltage levels is above the undervoltage threshold, V_{DD POR}. Then the NPOR bit is reset

(NPOR = 0 in SYS_DIAG1 and Global Status Register).

Reset on EN pin:

If the EN pin is pulled Low, the logic content is reset and the device enters sleep mode.

The reset event is reported by the NPOR bit (NPOR = 0) once the TLE94104EP is in normal mode (EN = High;

VDD > V_{DD POR}).

Datasheet

1.0

2017-12-07

TLE94104EP

General Description

5.4

Reverse Polarity Protection

The TLE94104EP requires an external reverse polarity protection. During reverse polarity, the free-wheeling

diodes across the half bridge output will begin to conduct, causing an undesired current flow (I_RB) from ground

potential to battery and excessive power dissipation across the diodes. As such, a reverse polarity protection

diode is recommended (see Figure 4).

VBAT

GND

CS2

HSx

OUTx

LSx

VBAT

GND

Figure 4

Reverse Polarity Protection

Datasheet

1.0

2017-12-07

TLE94104EP

Half-Bridge Outputs

6.1

Functional Description

The half-bridge outputs of the TLE94104EP are intended to drive motor loads.

If the outputs are driven continuously via SPI, for example HS1 and LS2 used to drive a motor, then the

following suggested SPI commands shall be sent:

•

Activate HS1: Bit HB1_HS_EN in HB_ACT_1_CTRL register

Activate LS2: Bit HB2_LS_EN in HB_ACT_1_CTRL register

Datasheet

1.0

2017-12-07

TLE94104EP

Half-Bridge Outputs

6.2

Protection & Diagnosis

The TLE94104EP is equipped with an SPI interface to control and diagnose the state of the half-bridge drivers.

This device has embedded protective functions which are designed to prevent IC destruction under fault

conditions described in the following sections. Fault conditions are treated as “outside” normal operating

range. Protection functions are not designed for continuous repetitive operation.

The following table provides a summary of fault conditions, protection mechanisms and recovery states

embedded in the TLE94104EP device.

Table 6

Summary of diagnosis and monitoring of outputs

Fault

condition

Error Flag Error bit: Status Register

(EF)

behaviour

Output

Protection

mechanism state

Error output High-Z Half-bridgecontrol

Output Output and error

error flag (EF) recovery

Overcurrent Latch

1. Load Error bit, LE (bit 6) in

SYS_DIAG 1: Global Status 1

2. Localized error for each HS and

LS channel of half-bridge,

HBn_HS_OC and HBn_LS_OC bits

in SYS_DIAG_2 status register.

shutdown

and latched

bits remain set

despite error,

however the

output stage is

shutdown.ClearEF

to reactivate

output stage.

Open load

Latch

1. Load Error bit, LE (bit 6) in

SYS_DIAG 1: Global Status 1

2. Localized error for each HS and

LS channel of half-bridge,

HBn_HS_OL and HBn_LS_OL bits in

SYS_DIAG3 status register.

None

state

An open load

detection does not

change change the state of

the output.

EF to be cleared.

Temperature Latch

pre-warning

Global error bit 1, TPW in

SYS_DIAG_1: Global Status 1

state

change

Not applicable

Temperature Latch

shutdown

Global error bit 2, TSD in

SYS_DIAG_1: Global Status 1

All outputs

shutdown

and latched.

High-Z Half-bridgecontrol

bits remain set

despite error,

however the

output stage is

shutdown.ClearEF

to reactivate

output stage.

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TLE94104EP

Half-Bridge Outputs

Table 6

Summary of diagnosis and monitoring of outputs (cont’d)

Fault

condition

Error Flag Error bit: Status Register

(EF)

Output

Protection

Output Output and error

error flag (EF) recovery

behaviour

mechanism state

Powersupply Latch

failure due to

undervoltage

Global error bit 5, VS_UV in

SYS_DIAG_1: Global Status 1

All outputs

shutdown

and

High-Z Half-bridgecontrol

bits remain set

despite error,

automatically

recovers.

however the

output stage is

shutdown. They

will automatically

be reactivated

once the power

supplyrecovers. EF

to be cleared.

Powersupply Latch

failure due to

overvoltage

Global error bit 4, VS_OV in

SYS_DIAG_1: Global Status 1

All outputs

shutdown

and

High-Z Half-bridgecontrol

bits remain set

despite error,

automatically

recover.

however the

output stage is

shutdown. They

will automatically

be reactivated

once the power

supplyrecovers. EF

to be cleared.

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TLE94104EP

Half-Bridge Outputs

6.2.1

Short Circuit of Output to Supply or Ground

The high-side switches are protected against short to ground whereas the low-side switches are protected

against short to supply.

The high-side and low-side power switches will enter into an over-current condition if the current within the

switch exceeds the overcurrent shutdown detection threshold, I_SD. Upon detection of the I_SDthreshold, an

overcurrent shutdown filter, t_dSDis begun. As the current rises beyond the threshold I_SD, it will be limited by the

current limit threshold, I_LIM. Upon expiry of the overcurrent shutdown filter time, the affected power switch is

latched off and the corresponding error bit, HBn_HS_OC or HBn_LS_OC is set and latched. See Figure 5 and

Figure 6 for more detail. A global load error bit, LE, contained in the global status register, SYS_DIAG_1, is also

set for ease of error scanning by the application software. The power switch remains deactivated as long as

the error bit is set.

To resume normal functionality of the power switch (in the event the overcurrent condition disappears or to

verify if the failure still exists) the microcontroller shall clear the error bit in the respective status register to

reactivate the desired power switch.

| I_HS|

I I_{LIM_HS}I

I I_{LIM_HS}- I_{SD_HS}

I I_{SD_HS}

OUTn

Short to GND

t_{dSD_ HS}

Short condition on High-Side Switch

Figure 5

High-Side Switch - Short Circuit and Overcurrent Protection

I_LS

I_{LIM_ LS}

I_{LIM_ LS}- I_{SD_LS}

Short to Supply

I_{SD_LS}

OUTn

t_{dSD_LS}

Short condition on Low-Side Switch

Figure 6

Low-Side Switch - Short Circuit and Overcurrent Protection

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TLE94104EP

Half-Bridge Outputs

Table 7

Control and Status register bit state in the event of an overcurrent condition for an

activated power switch

BEFORE

DURING

AFTER

TYPE

OVERCURRENT OVERCURRENT OVERCURRENT

Bit State

Control

HB_ACT_CTRL_n HBn_HS_EN

HBn_LS_EN

1(corresponding

half-bridge

deactivated)

Status

SYS_DIAG_1:

Global Status 1

SYS_DIAG_x

where x=2

HBn_HS_OC

HBn_LS_OC

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TLE94104EP

Half-Bridge Outputs

6.2.2

Cross-Current

In bridge configurations the high-side and low-side power transistors are ensured never to be simultaneously

“ON” to avoid cross currents. This is achieved by integrating delays in the driver stage of the power outputs to

create a dead-time between switching off of one power transistor and switching on of the adjacent power

transistor within the half-bridge. The dead times, t_DHLand t_DLH, as shown in Figure 7 case 3 and Figure 8 case

3, have been specified to ensure that the switching slopes do not overlap with each other. This prevents a cross

conduction event.

CSN

Case 1: Delay TimeHigh SideDriver OFF

VOUT_HSx [V]

Previous State Æ New State

HS ON Æ HS OFF

80%

t_dOFFH

LS OFF Æ LS OFF

20%

GND ₁₎

Delay time HS OFF

Case2: Delay TimeLow SideDriver ON

VOUT_LSx [V]

Previous StateÆ New State

HS OFF Æ HS OFF

80%

t_dONL

LS OFF Æ LS ON

20%

²⁾Delay time LS ON without dead time ; HS previously OFF

GND

Case 3: Delay TimeLow SideDriver ON with t_DHLdead time

VOUT_LSx [V]

Previous State Æ New State

HS ON Æ HS OFF

80%

Low-Side

delay time

t_dONL+t_DHL

LS OFF Æ LS ON

20%

³⁾Delay time LS ON with dead time ; HS previously ON

GND

Figure 7

Half bridge outputs switching times - high-side to low-side transition

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TLE94104EP

Half-Bridge Outputs

CSN

Case 1: Delay Time High Side Driver OFF

Previous StateÆ New State

HS OFF Æ HS OFF

VOUT_LSx [V]

80%

t_dOFFL

LS ON Æ LS OFF

20%

GND

Delay time LS OFF

Case 2: Delay Time High Side Driver ON

VOUT_HSx [V]

Previous StateÆ New State

HS OFF Æ HS ON

80%

t_dONH

LS OFF Æ LS OFF

20%

²⁾Delay time HS ON without dead time ; LS previously OFF

GND

Case 3: Delay TimeHigh SideDriver ON with t_DLHdead time

VOUT _HSx [V]

Previous State Æ New State

HS OFF Æ HS ON

80%

High-Side

delay time

t_dONH+t_DLH

LS ON Æ LS OFF

20%

³⁾HS ON delay time with dead time ; LS previously ON

GND

Figure 8

Half bridge outputs switching times- low-side to high-side transition

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TLE94104EP

Half-Bridge Outputs

6.2.3

Temperature Monitoring

Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the

measured temperature to the warning and shutdown thresholds. If one or more temperature sensors reach

the warning temperature, the temperature pre-warning bit, TPW is set. This bit is latched and can only be

cleared via SPI. The outputs stages however remain activated.

If one or more temperature sensors reach the shut-down temperature threshold, all outputs are latched off.

The TSD bit in SYS_DIAG_1: Global Status 1 is set. All outputs remain deactivated until the TSD bit is cleared.

See Figure 9.

To resume normal functionality of the power switch (in the event the overtemperature condition disappears,

or to verify if the failure still exists) the microcontroller shall clear the TSD error bit in the status register to

reactivate the respective power switch.

T_j

T_jSD

T_jW

V_OUTx

Output is switched off if

T_jSDis reached, can be

reactivated if TSD bit is

cleared

High Z

no error

TPW error bit

High

TPW is latched, can

be cleared via SPI

Low

no error

TSD error bit

High

TSD is latched, can be

cleared via SPI

Low

no error

Figure 9

Overtemperature Behavior

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TLE94104EP

Half-Bridge Outputs

Table 8

Control and Status register bit state in the event of an overtemperature condition for an

activated power switch

T_j< T_jW

T_j> T_jW

T_j> T_jSD

T_j< T_jSD- T_jHYS

TYPE

Bit

Bit State

Control

HB_ACT_CTRL_n

HBn_HS_EN

HBn_LS_EN

‘1’ (outputs

(all outputs are latched off

are latched unless error is

off)

cleared)

Status

SYS_DIAG_1: Global TPW

status 1

‘0’ if error is

cleared and

T_j< T_jW, else ‘1’

(latched)

SYS_DIAG_1: Global TSD

status 1

‘0’ if error is

cleared, else

‘1’

(latched)

6.2.4

Overvoltage and undervoltage shutdown

The power supply rails V_Sand V_DDare monitored for supply fluctuations. The V_Ssupply is monitored for under-

and over-voltage conditions where as the V_DDsupply is monitored for under-voltage conditions.

6.2.4.1 V_SUndervoltage

In the event the supply voltage V_Sdrops below the switch off voltage V_{UV OFF}, all output stages are switched off,

however, the logic information remains intact and uncorrupted. The V_Sunder-voltage error bit, VS_UV,

located in SYS_DIAG_1: Global Status 1 status register, will be set and latched. If V_Srises again and reaches the

switch on voltage V_{UV ON}threshold, the power stages will automatically be activated. The VS_UV error bit

should be cleared to verify if the supply disruption is still present. See Figure 10.

6.2.4.2 V_SOvervoltage

In the event the supply voltage V_Srises above the switch off voltage V_{OV OFF}, all output stages are switched off.

The V_Sover-voltage error bit, VS_OV, located in SYS_DIAG_1: Global Status 1 status register, will be set and

latched. If V_Sfalls again and reaches the switch on voltage V_{OV ON}threshold, the power stages will automatically

be activated. The VS_OV error bit should be cleared to verify if the overvoltage condition is still present. See

Figure 10.

6.2.4.3 V_DDUndervoltage

In the event the VDD logic supply decreases below the undervoltage threshold, V_{DD POffR}, the SPI interface shall

no longer be functional and the TLE94104EP will enter reset.

The digital block will be initialized and the output stages are switched off to High impedance. The

undervoltage reset is released once V_DDvoltage levels are above the undervoltage threshold, V_{DD POR}

The reset event is reported in SYS_DIAG1 by the NPOR bit (NPOR = 0) once the TLE94104EP is in normal mode

(EN = High ; VDD > V_{DD POR}).

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TLE94104EP

Half-Bridge Outputs

V_S

V_{OV HY}

V_{OV OFF}

V_{OV ON}

V_{UV HY}

V_{UV ON}

V_{UV OFF}

Output

reactivated

V_OUTx

Output

reactivated

V_OUTx

High Z

SPI command :

Clear SYS _DIAG1

SPI command

Clear SYS_DIAG1

VS_UV error bit

VS_OV error bit

High

Low

High

Low

Figure 10 Output behavior during under- and overvoltage V_Scondition

6.2.5

Open Load

Both high-side and low-side switches of the half-bridge power outputs are capable of detecting an open load

in their activated state. If a load current lower than the open load detection threshold, I_OLDfor at least t_dOLDis

detected at the activated switch, the corresponding error bit, HBn_HS_OL or HBn_LS_OL is set and latched. A

global load error bit, LE, in the global status register, SYS_DIAG_1: Global Status 1, is also set for ease of error

scanning by the application software. The half-bridge output however, remains activated.

The microcontroller must clear the error bit in the respective status register to determine if the open load is

still present or disappeared.

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TLE94104EP

Serial Peripheral Interface (SPI)

The TLE94104EP has a 16-bit SPI interface for output control and diagnostics. This section describes the SPI

protocol, the control and status registers.

7.1

SPI Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input

SCLK provided by the microcontroller. SCLK must be Low during CSN falling edge (Clock Polarity = 0). The SPI

incorporates an in-frame response: the content of the addressed register is shifted out at SDO within the same

SPI frame (see Figure 17 and Figure 19).The transmission cycle begins when the chip is selected by the input

CSN (Chip Select Not), Low active. After the CSN input returns from Low to High, the word that has been read

is interpreted according to the content. The SDO output switches to tri-state status (High impedance) at this

point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input register with every

falling edge on SCLK. The state of SDO is shifted out of the output register at every rising edge on SCLK (Clock

Phase = 1). The SPI protocol of the TLE94104EP is compatible with independent slave configuration and with

daisy chain. Daisy chaining is applicable to SPI devices with the same protocol.

Writing, clearing and reading is done byte wise. The SPI configuration and status bits are not cleared

automatically by the device and therefore must be cleared by the microcontroller, e.g. if the TSD bit was set

due to over temperature (refer to the respective register description for detailed information).

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN

time

CSN low to high: data from shift register is transferred to output functions

SCLK

time

LSB

MSB

Actual data

New data

0 1

+ +

SDI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

time

SDI: will accept data on the falling edge of SCLK signal

Actual status

New status

GEF 0 1

+ +

SDO

GEF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

time

SDO will change state on the rising edge of SCLK signal

Figure 11 SPI Data Transfer Timing (note the reversed order of LSB and MSB as shown in this figure

compared to the register description)

SPI messages are only recognized if a minimum set time, tSET, is observed upon rising edge of the EN pin

(Figure 12).

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TLE94104EP

Serial Peripheral Interface (SPI)

t_SET

SPI

A) SPI message ignored

B) SPI message accepted

Figure 12 Setup time from EN rising edge to first SPI communication

t_lead

t_lag

t_CSNH

t_pCLK

0.8V_DD

0.2V_DD

CSN

t_SCLKH

t_SCLKL

0.8VDD

0.2V_DD

SCLK

SDI

t_{SDI_setup}

t_{SDI_hold}

0.8V_DD

0.2V_DD

t_ENSDO

t_VASDO

t_DISSDO

0.8V_DD

0.2V_DD

SDO

Figure 13 SPI Data Timing

7.1.1

Global Error Flag

A logic OR combination between Global Error Flag (GEF) and the signal present on SDI is reported on SDO

between a CSN falling edge and the first SCLK rising edge (Figure 11). GEF is set if a fault condition is detected

or if the device comes from a Power On Reset (POR).

Note:

The SDI pin of all devices in daisy chain or non daisy chain mode must be Low at the beginning of the

SPI frame (between the CSN falling edge and the first SCLK rising edge).

It is possible to check if the TLE94104EP has detected a fault by reading the GEF without SPI clock pulse

(Figure 14).

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TLE94104EP

Serial Peripheral Interface (SPI)

CSN

time

SCLK

SDI

time

High Impedance

Global Error Flag

SDO

time

Figure 14 SDO behaviour with 0-clock cycle

7.1.2

Global Status Register

The SDO shifts out during the first eight SCLK cycles the Global Status Register. This register provides an

overview of the device status. All failures conditions are reported in this byte:

•

SPI protocol error (SPI_ERR)

Load Error (LE bit): logical OR between Open Load (OL) and Overcurrent (OC) failures

VS Undervoltage (VS_UV bit)

VS Overvoltage (VS_OV bit)

Negated Power ON Reset (NPOR bit)

Temperature Shutdown (TSD bit)

Temperature Pre-Warning (TPW bit)

See Chapter 7.7.1 for details.

Note: The Global Error Flag is a logic OR combination of every bit of the Global Status Register with the

exception of NPOR: GEF = (SPI_ERR) OR (LE) OR (VS_UV) OR (VS_OV) OR (NOT(NPOR)) OR (TSD) OR

(TPW). It is possible to mask open load failures from the Global Error Flag by setting the OL_BLANK

bit (refer to Chapter 7.6).

The following table shows how failures are reported in the Global Status Register and by the Global Error Flag.

Table 9 Failure reported in the Global Status Register and Global Error Flag

Type of Error

Failure reported in the Global

Status Register

Global Error Flag

SPI protocol error

Open load or Overcurrent

VS Undervoltage

SPI_ERR = 1

LE = 1

1¹⁾

VS_UV = 1

VS_OV = 1

NPOR = 0

TSD = 1

VS Overvoltage

Power ON Reset

Thermal Shutdown

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TLE94104EP

Serial Peripheral Interface (SPI)

Table 9

Failure reported in the Global Status Register and Global Error Flag

Type of Error

Failure reported in the Global

Status Register

Global Error Flag

Thermal Warning

TPW = 1

No Error and no Power ON Reset

SPI_ERR = 0

LE = 0

VS_UV = 0

VS_OV = 0

NPOR = 1

TSD = 0

TPW = 0

1) Open load errors are reported in the Global Error Flag only if OL_BLANK bit is set to 0.

Note:

The default value (after Power ON Reset) of NPOR is 0, therefore the default value of GEF is 1.

7.1.3

SPI protocol error detection

The SPI incorporates an error flag in the Global Status Register (SPI_ERR, Bit7) to supervise and preserve the

data integrity. If an SPI protocol error is detected during a given frame, the SPI_ERR bit is set in the next SPI

communication.

The SPI_ERR bit is set in the following error conditions:

•

the number of SCLK clock pulses received when CSN is Low is not 0, or is not a multiple of 8 and at least 16

the microcontroller sends an SPI command to an unused address. In particular, SDI stuck to High is

reported in the SPI_ERR bit

•

the LSB of an address byte is not set to 1. In particular, SDI stuck to Low is reported in the SPI_ERR bit

the Last Address Bit Token (LABT, bit 1 of the address byte, see Chapter 7.2) in independent slave

configuration is not set to 1

•

the LABT bit of the last address byte in daisy chain configuration is not set to 1 (see Chapter 7.3)

a clock polarity error is detected (see Figure 15 Case 2 and Case 3): the incoming clock signal was High

during CSN rising or falling edges.

For a correct SPI communication:

•

SCLK must be Low for a minimum t_BEFbefore CSN falling edge and t_leadafter CSN falling edge

SCLK must be Low for a minimum t_lagbefore CSN rising edge and t_BEHafter CSN rising edge

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TLE94104EP

Serial Peripheral Interface (SPI)

Case 1: Correct SCLK signal

Correct incoming clock signal

Correct clock during CSN rising edge

CSN

time

t_BEF

t_lead

t_lagt_BEH

SCLK

time

Case 2: Erroneous incoming clock signal

CSN

time

SCLK is High with CSN falling edge

SCLK

Case 3: Erroneous clock signal during CSN rising edge

CSN

time

Clock is High with CSN rising edge

SCLK

Figure 15 Clock Polarity Error

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TLE94104EP

Serial Peripheral Interface (SPI)

7.2

SPI with independent slave configuration

In an independent slave configuration, the microcontroller controls the CSN of each slave individually

(Figure 16).

Microcontroller

TLE941xy_1

SPI

TLE941xy_2

SPI

TLE941xy_3

SPI

SDI1

SDO1 SDI2

SDO2 SDI3

SDO3

MCSN1

MCSN2

MCSN3

MCLK

Figure 16 SPI with independent slave configuration

Each SPI communication starts with one address byte followed by one data byte (Figure 17).The LSB of the

data byte must be set to ‘1’.The address bytes specifies:

•

the type of operation: READ ONLY (OP bit =0) or READ/ WRITE (OP bit = 1) of the configuration bits, and

READ ONLY (OP bit =0)or READ & CLEAR (OP bit = 1) of the status bits.

•

The target register address (A[6:2])

The Last Address Byte Token bit (LABT, Bit1 of the address byte) must be set to 1, as no daisy chain

configuration is used.

While the microcontroller sends the address byte on SDI, SDO shifts out GEF and the Global Status Register.

A further data byte (Bit15...8) is allocated to either configure the half-bridges or retrieve status information of

the TLE94104EP.

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TLE94104EP

Serial Peripheral Interface (SPI)

Address Byte

Data Byte

MSB

LSB

LABT

= 1

SDI

Global Status Register

Data Byte (Response)

MSB

LSB

SPI_

ERR

SD0

TPW TSD NPOR VS_OV VS_UV LE

Time

LSB is sent first in SPI message

Figure 17 SPI Operation Mode with independent slave configuration

The in-frame response characteristic enables the microcontroller to read the contents of the addressed

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TLE94104EP

Serial Peripheral Interface (SPI)

7.3

Daisy chain operation

The TLE94104EP supports daisy chain operation with devices with the same SPI protocol.This section

describes the daisy chain hardware configuration with three devices from the TLE941xy family (See

Figure 18).

The master output (noted MO) is connected to a slave SDI and the first slave SDO is connected to the next slave

SDI to form a chain. The SDO of the final slave in the chain will be connected to the master input (MI) to close

the loop of the SPI communication frame. In daisy chain configuration, a single chip select, CSN, and clock

signal, SCLK, connected in parallel to each slave device, are used by the microcontroller to control or access

the SPI devices.

In this configuration, the Master Output must send the address bytes and data bytes in the following order:

•

All address bytes must be sent first:

–

Address Byte 1 (for TLE941xy_1) is sent first, followed by Address Byte 2 (for TLE941xy_2) etc,...

The LABT bit of the last address byte must be 1, while the LABT bit of all the other address bytes must

be 0

The data bytes are sent all together once all address bytes have been transmitted: Data Byte 1 (for

TLE941xy_1) is sent first, followed by Data Byte 2 (for TLE941xy_2) etc,...

Note:

The signal on the SDI pin of the first IC in daisy chain (and in non-daisy chain mode), must be Low at

the beginning of the SPI frame (between CSN falling edge and the first SCLK rising edge). This is

because each Global Error Flag in daisy chain operation is implemented in OR logic.

The Master Input (MI), which is connected to the SDO of the last device in the daisy chain receives:

•

A logic OR combination of all Global Error Flags (GEF), at the beginning of the SPI frame, between CSN

falling edge and the first SCLK rising edge

The logic OR combination of the GEFs is followed by the Global Status Registers in reverse order. In other

words MI receives first the Global Status Register of the last device of the daisy chain

Once all Global Status Registers are received, MI receives the response bytes corresponding to the

respective address and data bytes in reverse order. For example, if the daisy chain consists of three devices

with SDO or TLE941xy_3 connected to MI, the master receives first the Response Byte 3 of TLE941xy_3

(corresponding to Address Byte 3 and Data Byte 3) followed by the Response Byte 2 of TLE941xy_2 and

finally the Response Byte 1 of TLE941xy_1.

An example of an SPI frame with three devices from the TLE941xy family is shown in Figure 19.

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TLE94104EP

Serial Peripheral Interface (SPI)

Microcontroller

TLE941xy_1

SPI

TLE941xy_2

SPI

TLE941xy_3

SPI

SDO1 SDI2

SDO2 SDI3

SDO3

SDI1

MCSN

MCLK

Figure 18 Example of daisy chain hardware configuration with devices from the TLE941xy family

8 CLOCK CYCLES

8 CLOCK CYLES

8 CLOCK CYCLES

8 CLOCK CYLES

8 CLOCK CYCLES

8 CLOCK CYLES

SCLK

CSN

LABT=0

LABT=1

ADDRESS BYTE 1

ADDRESS BYTE 2

ADDRESS BYTE 3

DATA BYTE 1

RESPONSE 1

RESPONSE 2

RESPONSE 3

DATA BYTE 2

RESPONSE1

RESPONSE2

DATA BYTE 3

RESPONSE 1

MO = SDI1

SDI2 = SDO1

GEF1

GLOBAL STATUS1 ADDRESS BYTE 2

ADDRESS BYTE 3

SDI3 = SDO2

MI =SDO3

GEF1/2

GLOBAL STATUS2 GLOBAL STATUS 1 ADDRESS BYTE 3

GLOBAL STATUS3 GLOBAL STATUS 2 GLOBAL STATUS 1

GEF1/2/3

Time

Figure 19 SPI frame with three devices of the TLE941xy family

Like in the individual slave configuration, it is possible to check if one or several TLE941xy have detected a fault

condition by reading the logic OR combination of all the Global Error Flags when CSN goes Low without any

clock cycle (Figure 20).

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TLE94104EP

Serial Peripheral Interface (SPI)

SCLK

CSN

MO = SDI1

SDI2 = SDO1

SDI3 = SDO2

MI = SDO3

HiZ

GEF1

GEF1/2

GEF1/2/3

Time

Figure 20 Global Error Flag with zero SCLK clock cycle in daisy chain consisting only of TLE941xy

devices

Note:

Some SPI protocol errors such as the LSB of an address byte is wrongly equal to 0, may be reported

in the SPI_ERR bit of another device in the daisy chain (refer to Chapter 7.1.3 and Chapter 7.7 for

more details on SPI_ERR). In this case some devices might accept wrong data during the corrupted

SPI frame. Therefore if one of the devices in the daisy chain reports an SPI error, it is recommended

to verify the content of the registers of all devices.

7.4

Status register change during SPI communication

If a new failure occurs after the transfer of the data byte(s), i.e. between the end of the last address byte and

the CSN rising edge, this failure will be reported in the next SPI frame (see example in Figure 21).

8 CLOCK CYCLES

8 CLOCK CYLES

8 CLOCK CYCLES

8 CLOCK CYLES

SCLK

CSN

End of the

address byte detection

New failure

Read status byte

corresponding to the failure

SDI

ADDRESS BYTE

DATA BYTE

ADDRESS BYTE

DATA BYTE

SDO

Failure is NOT notified in this SPI frame

Failure notified in the new SPI frame

HiZ

GEF

GLOBAL STATUS

DATA BYTE

GLOBAL STATUS

DATA BYTE

GEF

Time

Figure 21 Status register change during transfer of data byte - Example in independent slave

configuration

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TLE94104EP

Serial Peripheral Interface (SPI)

No information is lost, even if a status register is changed during a SPI frame, in particular during a Read and

Clear command. For example:

•

the microcontroller sends a Read and Clear command to a status register

the TLE94104EP detects during the transfer the data byte(s) a new fault condition, which is normally

reported in the target status register

The incoming Clear command will be ignored, so that the microcontroller can read the new failure in the

subsequent SPI frames.

Data inconsistency between the Global Status Register (see Chapter 7.7) and the data byte (status register)

within the same SPI frame is possible if:

•

an open load or overcurrent error is detected during the transfer of the data byte

the target status register corresponds to the new detected failure

In this case the new failure:

•

is not reported in the Global Status Register of the current SPI frame but in the next one

is reported in the data byte of the current SPI frame

Refer to Figure 21.

Datasheet

1.0

2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

SPI Frame 1

Overcurrent failure detected on HS of HB 1 SPI frame: Read SYS _DIAG2 (OC error of HB 1-4)

Address Byte

Data Byte

MSB

LSB

LABT

SDI

Overcurrent failure detected on HS of HB 1 during the

transfer of the address byte

Target status register : OC error of HB 1-4

Global Status Register

LSB

Response Data Byte : SYS_DIAG2

MSB

SPI_

ERR

SDO

TPW TSD NPOR VS_OV VS_UV

HB1_HS_OC reports the new

Overcurrent failure on the HS of HB 1

Load Error bit (Overcurrent or Open Load )

does not report the new Overcurrent failure

Inconsistency between Global Status Register

and target Status Register

Time

SPI frame 2 (new)

New SPI frame: e.g. Read SYS_DIAG2 (OC error of HB1-4)

Address Byte

Data Byte

MSB

LSB

LABT

Target status register : OC error of HB1-4

Global Status Register

Response Data Byte : SYS_DIAG2

MSB

LSB

SPI_

ERR

TPW TSD NPOR VS_OV VS_UV

Consistent information : Both Load Error bit and HB 1_HS_OC report

the Overcurrent failure detected during the previous SPI frame

Figure 22 Example of inconsistency between Global Error Flag and Status Register when a status bit is

changed during the transfer of an address byte

Datasheet

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2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

7.5

SPI Bit Mapping

The SPI Registers have been mapped as shown in Figure 23 and Figure 24 respectively.

The control registers are READ/ WRITE registers. To set the control register to READ, bit 7 of the address byte

(OP bit) must be programmed to ‘0’, otherwise ‘1’ for WRITE.

The status registers are READ/CLEAR registers. To CLEAR any Status Register, bit 7 of the address byte must be

set to ‘1’, otherwise ‘0’ for READ.

6 5 4 3 2

8 Address Bits [A7…0]

Access

type

8 Data Bits [D7…D0]

for Configuration & Status Information

HB_ACT_1_CTRL

read/write 0 0 0 0 0 LABT 1

read/write 0 1 1 0 0 LABT 1

read/write 1 1 0 1 0 LABT 1

FM_CLK_CTRL

OLBLK_CTRL

CONFIG_CTRL

read

1 1 0 0 1 LABT 1

SYS_DIAG_1 : Global status 1

SYS_DIAG_2 : OP ERROR_1_STAT

SYS_DIAG_3 : OP ERROR_2_STAT

read/clear 0 0 1 1 0 LABT 1

read/clear 1 0 1 1 0 LABT 1

read/clear 0 0 0 0 1 LABT 1

Figure 23 TLE94104EP SPI Register mapping

Note:

LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3.

Datasheet

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2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

R E G

R O N T C O

S T A

Figure 24 TLE94104EP Bit Mapping

Note:

LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3.

Datasheet

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2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

7.6

SPI Control Registers

The Control Registers have a READ/WRITE access (see Chapter 7.5):

•

The ‘POR’ value is defined by the register content after a POR or device Reset

–

The default value of all control registers is 0000 0000_Bwith the exception of CONFIG_CTRL and

FM_CLK_CTRL

–

The default value of the CONFIG_CTRL register is 0000 0100_B

The default value of the FM_CTLR_CTRL register is 1100 0000_B

•

One 16-bit SPI command consists of two bytes (see Figure 23 and Figure 24), i.e.

–

an address byte

followed by a data byte

The control bits are not cleared or changed automatically by the device. This must be done by the

microcontroller via SPI programming.

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= READ ONLY).

Writing to a register is done byte wise by setting the SPI bit 7 to “1”.

Datasheet

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2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

7.6.1

Control register definition

HB_ACT_1_CTRL

Half-bridge output control 1 (Address Byte [OP] 000 00[LABT]1_B)

HB4_HS_EN HB4_LS_EN HB3_HS_EN HB3_LS_EN HB2_HS_EN HB2_LS_EN HB1_HS_EN HB1_LS_EN

Field

Bits

Type

Description

HB4_HS_EN D7

HB4_LS_EN D6

HB3_HS_EN D5

HB3_LS_EN D4

HB2_HS_EN D3

HB2_LS_EN D2

HB1_HS_EN D1

HB1_LS_EN D0

Half-bridge output 4 high side switch enable

0_BHS4 OFF/ High-Z (default value)

1_BHS4 ON

Half-bridge output 4 low side switch enable

0_BLS4 OFF/ High-Z (default value)

1_BLS4 ON

Half-bridge output 3 high side switch enable

0_BHS3 OFF/ High-Z (default value)

1_BHS3 ON

Half-bridge output 3 low side switch enable

0_BLS3 OFF/ High-Z (default value)

1_BLS3 ON

Half-bridge output 2 high side switch enable

0_BHS2 OFF/ High-Z (default value)

1_BHS2 ON

Half-bridge output 2 low side switch enable

0_BLS2 OFF/ High-Z (default value)

1_BLS2 ON

Half-bridge output 1 high side switch enable

0_BHS1 OFF/ High-Z (default value)

1_BHS1 ON

Half-bridge output 1 low side switch enable

0_BLS1 OFF/ High-Z (default value)

1_BLS1 ON

Note:

The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the

digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the

logic turns off this half-bridge.

Datasheet

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2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

FM_CLK_CTRL

Frequency modulation select (Address Byte [OP]011 00[LABT]1_B)

FM_CLK_

MOD1

FM_CLK_

MOD0

Reserved

Field

Bits

Type

Description

FM Modulation Enable¹⁾

FM_MOD_EN

D7:D6

00_BNo modulation

01_BModulation frequency 15.625kHz

10_BModulation frequency 31.25kHz

11_BModulation frequency 62.5kHz (default)

reserved

D5:D4

D3:D2

D1:D0

Reserved. Always reads as ‘0’.

1) Not subject to production test, guaranteed by design. Frequency may deviate by ±10%

Datasheet

1.0

2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

OLBLK_CTRL

Open load blanking setting (Address Byte [OP]110 10[LABT]1)_B

OL_BLANK

reserved

Field

Bits

Type

Description

Internal target:

OL_BLANK

0_B(default) Open load failures are reported in the GEF

1_BOpen load failures are not reported in the GEF

reserved

To be programmed as ‘0’.

Reserved. Always reads as ‘0’.

Datasheet

1.0

2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

CONFIG_CTRL

Device Configuration control (Address Byte [OP]110 01[LABT]1_B)

reserved

DEV_ID2

DEV_ID1

DEV_ID0

Field

Bits

Type

Description

Always reads as ‘0’

Device/ derivative identifier

reserved

DEV_IDn

D7:D3

D2:D0

Note:

These bits can be used to verify the silicon

content of the device

000_BTLE94112EL chip

001_BTLE94110EL chip

010_BTLE94108EL chip

011_BTLE94106EL/ES chip

100_BTLE94104EP chip

101_BTLE94103EP chip

110_Breserved

111_Breserved

Datasheet

1.0

2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

7.7

SPI Status Registers

The Control Registers have a READ/CLEAR access (see also Chapter 7.5):

•

The ‘POR Value’ of the Status registers (content after a POR or device Reset) and is 0000 0000_B.

One 16-bit SPI command consists of two bytes (see Figure 23 and Figure 24), i.e.

–

an address byte

followed by a data byte

•

Reading a register is done byte wise by setting the SPI bit 7 of the address byte to “0” (= Read Only).

Clearing a register is done byte wise by setting the SPI bit 7 of the address byte to “1”.

SPI status registers are not cleared automatically by the device. This must be done by the microcontroller

via SPI command.

Datasheet

1.0

2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

7.7.1

Status register definition

SYS_DIAG1

Global status 1 (Address Byte [OP]001 10[LABT]1_B)

SPI_ERR

VS_UV

VS_OV

NPOR

TSD

TPW

reserved

Field

Bits

Type

Description

SPI_ERR

SPI error detection

0_BNo SPI protocol error is detected (default value).

1_BAn SPI protocol error is detected.

Load error detection (logic OR combination of Open Load and

Overcurrent)

0_BNo Open Load and no Overcurrent detected (default value)

1_BOpen Load or Overcurrent detected in at least one of the

power outputs. Error latched. Faulty output is latched off in

case of Overcurrent

VS_UV

VS_OV

VS Undervoltage error detection

0_BNo undervoltage on V_Sdetected (default value)

1_BUndervoltage on V_Sdetected. Error latched and all outputs

disabled.

VS Overvoltage error detection

0_BNo overvoltage on V_Sdetected (default value)

1_BOvervoltage on V_Sdetected. Error latched and all outputs

disabled.

NPOR

TSD

Not Power On Reset (NPOR) detection

0_BPOR on EN or VDD supply rail (default value)

1_BNo POR

Temperature shutdown error detection

0_BJunction temperature below temperature shutdown

threshold (default value)

1_BJunction temperature has reached temperature shutdown

threshold. Error latched and all outputs disabled.

TPW

Temperature pre-warning error detection

0_BJunction temperature below temperature pre-warning

threshold (default value)

1_BJunction temperature has reached temperature pre-warning

threshold.

reserved

Bit reserved. Always reads ‘0’.

Note:

The LE bit in the Global Status register is read only. It reflects an OR combination of the respective

open load and overcurrent errors of the half-bridge channels. If all OC/ OL bits of the respective high-

side and low-side channels are cleared to ‘0’, the LE bit will be automatically updated to ‘0’.

Datasheet

1.0

2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

SYS_DIAG_2 : OP_ERROR_1_STAT

Overcurrent error status of half-bridge outputs 1 - 4 (Address Byte [OP]101 10[LABT]1_B)

HB4_HS_OC HB4_LS_OC HB3_HS_OC HB3_LS_OC HB2_HS_OC HB2_LS_OC HB1_HS_OC HB1_LS_OC

Field

Bits

Type

Description

HB4_HS_OC D7

HB4_LS_OC D6

HB3_HS_OC D5

HB3_LS_OC D4

HB2_HS_OC D3

HB2_LS_OC D2

HB1_HS_OC D1

HB1_LS_OC D0

High-side (HS) switch of half-bridge 4 overcurrent detection

0_BNo error on HS4 switch (default value)

1_BOvercurrent detected on HS4 switch. Error latched and HS4

disabled.

Low-side (LS) switch of half-bridge 4 overcurrent detection

0_BNo error on LS4 switch (default value)

1_BOvercurrent detected on LS4 switch. Error latched and LS4

disabled.

High-side (HS) switch of half-bridge 3 overcurrent detection

0_BNo error on HS3 switch (default value)

1_BOvercurrent detected on HS3 switch. Error latched and HS3

disabled.

Low-side (LS) switch of half-bridge 3 overcurrent detection

0_BNo error on LS3 switch (default value)

1_BOvercurrent detected on LS3 switch. Error latched and LS3

disabled.

High-side (HS) switch of half-bridge 2 overcurrent detection

0_BNo error on HS2 switch (default value)

1_BOvercurrent detected on HS2 switch. Error latched and HS2

disabled.

Low-side (LS) switch of half-bridge 2 overcurrent detection

0_BNo error on LS2 switch (default value)

1_BOvercurrent detected on LS2 switch. Error latched and LS2

disabled.

High-side (HS) switch of half-bridge 1 overcurrent detection

0_BNo error on HS1 switch (default value)

1_BOvercurrent detected on HS1 switch. Error latched and HS1

disabled.

Low-side (LS) switch of half-bridge 1 overcurrent detection

0_BNo error on LS1 switch (default value)

1_BOvercurrent detected on LS1 switch. Error latched and LS1

disabled.

Datasheet

1.0

2017-12-07

TLE94104EP

Serial Peripheral Interface (SPI)

SYS_DIAG_3 : OP_ERROR_2_STAT

Open load error status of half-bridge outputs 1 - 4 (Address Byte [OP]000 01[LABT]1_B)

HB4_HS_OL HB4_LS_OL HB3_HS_OL HB3_LS_OL HB2_HS_OL HB2_LS_OL HB1_HS_OL HB1_LS_OL

Field

Bits

Type

Description

HB4_HS_OL D7

HB4_LS_OL D6

HB3_HS_OL D5

HB3_LS_OL D4

HB2_HS_OL D3

HB2_LS_OL D2

HB1_HS_OL D1

HB1_LS_OL D0

High-side (HS) switch of half-bridge 4 open load detection

0_BNo error on HS4 switch (default value)

1_BOpen load detected on HS4 switch. Error latched.

Low-side (LS) switch of half-bridge 4 open load detection

0_BNo error on LS4 switch (default value)

1_BOpen load detected on LS4 switch. Error latched.

High-side (HS) switch of half-bridge 3 open load detection

0_BNo error on HS3 switch (default value)

1_BOpen load detected on HS3 switch. Error latched.

Low-side (LS) switch of half-bridge 3 open load detection

0_BNo error on LS3 switch (default value)

1_BOpen load detected on LS3 switch. Error latched.

High-side (HS) switch of half-bridge 2 open load detection

0_BNo error on HS2 switch (default value)

1_BOpen load detected on HS2 switch. Error latched.

Low-side (LS) switch of half-bridge 2 open load detection

0_BNo error on LS2 switch (default value)

1_BOpen load detected on LS2 switch. Error latched.

High-side (HS) switch of half-bridge 1 open load detection

0_BNo error on HS1 switch (default value)

1_BOpen load detected on HS1 switch. Error latched.

Low-side (LS) switch of half-bridge 1 open load detection

0_BNo error on LS1 switch (default value)

1_BOpen load detected on LS1 switch. Error latched.

Datasheet

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2017-12-07

TLE94104EP

Application Information

Note:

The following simplified application examples are given as a hint for the implementation of the

device only and shall not be regarded as a description or warranty of a certain functionality,

condition or quality of the device. The function of the described circuits must be verified in the real

application.

8.1

Application Diagram

V_S

VBAT

3 motors in

cascaded

configuration

2 motors in

non-cascaded

configuration

47µF

100nF

VDD

OUT 1

TLE4678

TLE94104EP

µC

N.C.

INH

OUT 2

RADJ

VDD

SDO

SDI

Series resistors are

10kΩ

OUT 3

OUT 4

recommended if the VS of

the TLE94104 EL is protected

by an active reverse polarity

protection

CSN

SCLK

GND

Landing pads for ceramic

capacitors at OUTx

Figure 25 Application Example for DC-motor loads

Datasheet

1.0

2017-12-07

TLE94104EP

Application Information

VBAT

DRP

VReg

VCC

VDD

OUT1

OUT2

OUT3

µC

SDI

Series resistors are

recommended if the VS of

the TLE94104EP is protected

by an active reverse polarity

protection

SDO

SCLK

CSN

Landing pads for ceramic

capacitors at OUTx

OUT4

GND

Figure 26 Application Example for bipolar stepper motor in voltage mode control

Notes on the application example

1. Series resistors between the microcontroller and the signal pins of the TLE94104EP are recommended if an

active reverse polarity protection (MOSFET) is used to protect the VS pin. These resistors limit the current

between the microcontroller and the device during negative transients on VBAT (e.g. ISO/TR 7637 pulse 1)

2. Landing pads for ceramic capacitors at the outputs of the TLE94104EP as close as possible to the connectors

are recommended (the ceramic capacitors are not populated if unused). These ceramic capacitors can be

mounted if a higher performance in term of ESD capability is required.

3. The electrolytic capacitor at the VS pin should be dimensioned in order to prevent the VS voltage from

exceeding the absolute maximum rating. PWM operation with a too low capacitance can lead to a VS voltage

overshoot, which results in a VS overvoltage detection.

4. Unused outputs are recommended to be left unconnected (open) in the application. If unused output pins are

routed to an external connector which leaves the PCB, then these outputs should have provision for a zero

ohm jumper (depopulated if unused) or ESD protection. In other words, unused pins should be treated like

used pins.

5. Place bypass ceramic capacitors as close as possible to the VS pins, with shortest connections the GND pins

and GND layer, for best EMC performance

Datasheet

1.0

2017-12-07

TLE94104EP

Application Information

8.2

Thermal application information

Ta = -40°C, Ch1 to Ch4 are dissipating a total of 0.8W (0.2W each).

Ta = 85°C, Ch1 to Ch4 are dissipating a total of 0.54W (0.135W each).

Zth-ja for TLE 94104EP

150

1s0p / 600mm² / -40°C

1s0p / 600mm² / +85°C

120

1s0p / 300mm² / -40°C

1s0p / 300mm² / +85°C

1s0p / footprint / -40°C

1s0p / footprint / +85°C

2s2p / -40°C

2s2p / +85°C

0.000001 0.00001

0.0001

0.001

0.01

0.1

100

1000

10000

time [sec]

Figure 27 ZthJA Curve for different PCB setups

Zth-jc for TLE 94104EP

Tamb = -40°C

Tamb = +85°C

0.000001

0.00001

0.0001

0.001

0.01

0.1

100

1000

time [sec]

Figure 28 ZthJC Curve

Datasheet

1.0

2017-12-07

TLE94104EP

Application Information

8.3

EMC Enhancement

In the event the emissions of the device exceed the allowable limits, a modulation of the oscillator frequency

is incorporated to reduce eventual harmonics of the 8MHz base clock. The frequencies can be selected based

on the resolution bandwidth of the peak detector during EMC testing.

The selection is achieved by setting the FM_CLK_MODn bits in the FM_CLK_CTRL register as follows:

00_B: OFF

01_B: FM CLK=15.625 kHZ

10_B: FM CLK=31.25 kHz

11_B: FM CLK=62.5 kHz

Datasheet

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2017-12-07

TLE94104EP

Package Outlines

Figure 29 PG-TSDSO-14 (Plastic Green - Dual Small Outline Package)

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e lead-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Datasheet

1.0

2017-12-07

TLE94104EP

Revision History

Revision Date

Changes

1.0

2017-12-07 Initial release

Datasheet

1.0

2017-12-07

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2017-12-07

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

Document reference

Doc_Number

TLE94104EP [INFINEON]

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