TLE94112ES_技术文档

TLE94112ES

Features

•

Twelve half bridge power outputs

Very low power consumption in sleep mode

3.3V / 5V compatible inputs with hysteresis

All outputs with overload and short circuit protection

Independently diagnosable outputs (overcurrent, open load)

Open load diagnostics in ON-state for all high-side and low-side

Outputs with selectable open load thresholds (HS1, HS2)

16-bit Standard SPI interface with daisy chain and in-frame response capability for control and diagnosis

Fast diagnosis with the global error flag

PWM capable outputs for frequencies 80Hz, 100Hz and 200Hz with 8-bit duty cycle resolution

Overtemperature pre-warning and protection

Over- and Undervoltage lockout

Cross-current protection

Applications

•

HVAC Flap DC motors

Monostable and bistable Relays

Side mirror x-y adjustment and mirror fold

LEDs

Description

The TLE94112ES is a protected twelve-fold half-bridge driver designed especially for automotive motion

control applications such as Heating, Ventilation and Air Conditioning (HVAC) flap DC motor control. It is part

of a larger family offering half-bridge drivers from three outputs to twelve outputs with direct interface or SPI

interface.

The half bridge drivers are designed to drive DC motor loads in sequential or parallel operation. Operation

modes forward (cw), reverse (ccw), brake and high impedance are controlled from a 16-bit SPI interface. It

offers diagnosis features such as short circuit, open load, power supply failure and overtemperature

detection. In combination with its low quiescent current, this device is attractive among others for automotive

applications. The small fine pitch exposed pad package, PG-TSDSO-24, provides good thermal performance

and reduces PCB-board space and costs.

Data Sheet

www.infineon.com

1

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2020-09-29

TLE94112ES

Type

Package

Marking

TLE94112ES

PG-TSDSO-24

TLE94112ES

Table 1

Product Summary

Normal Operating Voltage

Extended Operating Voltage

Logic Supply Voltage

V_S

5.5 ... 18 V

18 ... 20 V

3.0 ... 5.5 V

40 V

V_S

V_DD

V_S(LD)

Maximum Supply Voltage for Load Dump

Protection

Minimum Overcurrent Threshold

I_SD

0.9 A

Maximum On-State Path Resistance at T_j= 150°C R_{DSON(total)_HSx+LSy}

1.8 + 1.8 Ω

0.1 µA

Typical Quiescent Current at T_j= 85°C

Maximum SPI Access Frequency

I_SQ

f_SCLK

5 MHz

Data Sheet

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2020-09-29

TLE94112ES

Table of Contents

1

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

1.2

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1

3.2

3.3

3.4

4

Characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reset Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1

5.2

5.2.1

5.2.2

5.3

5.4

6

6.1

Half-Bridge Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Half-bridge operation with PWM enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

LED mode (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Protection & Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Short Circuit of Output to Supply or Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Cross-Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Overvoltage and undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

V_SUndervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

V_SOvervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1.1

6.1.1.1

6.1.1.2

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.4.1

6.2.4.2

6.2.4.3

6.2.5

V

_DDUndervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Open Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7

7.1

7.1.1

7.1.2

7.1.3

7.2

7.3

7.4

7.5

7.6

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SPI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Global Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Global Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SPI protocol error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SPI with independent slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Status register change during SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Control register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

SPI Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.6.1

7.7

Data Sheet

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TLE94112ES

7.7.1

Status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Thermal application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

EMC Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.1

8.2

8.3

9

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10

Data Sheet

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TLE94112ES

Pin Configuration

1

Pin Configuration

1.1

Pin Assignment

GND

1

24

23

22

21

20

19

18

17

16

15

14

13

GND

OUT 1

OUT 5

OUT 7

SDI

2

3

4

OUT 2

OUT 8

VS2

5

6

SCLK

CSN

VDD

SDO

EN

7

8

OUT 12

OUT 11

VS1

OUT 10

OUT 3

GND

OUT 9

OUT 6

OUT 4

GND

9

10

11

12

Figure 1

Pin Configuration TLE94112ES

1.2

Pin Definitions and Functions

1

Symbol

Function

GND

OUT 1

OUT 5

OUT 7

SDI

Ground. All ground pins should be externally connected together.

Power half-bridge 1

2

3

Power half-bridge 5

4

Power half-bridge 7

5

Serial data input with internal pull down

Logic supply voltage

6

VDD

7

SDO

EN

Serial data output

8

Enable with internal pull-down; Places device in standby mode by pulling the EN

line Low

9

OUT 9

OUT 6

OUT 4

GND

Power half-bridge 9

10

11

12

Power half-bridge 6

Power half-bridge 4

Ground. All ground pins should be externally connected together.

Data Sheet

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TLE94112ES

Pin Configuration

13

14

15

16

Symbol

GND

Function

Ground. All ground pins should be externally connected together.

Power half-bridge 3

OUT 3

OUT 10

VS1

Power half-bridge 10

Main supply voltage for power half bridges. VS1 should be externally connected to

VS2.

17

18

19

20

21

OUT 11

OUT 12

CSN

Power half-bridge 11

Power half-bridge 12

Chip select Not input with internal pull up

Serial clock input with internal pull down

SCLK

VS2

Main supply voltage for power half bridges. VS1 should be externally connected to

VS2.

22

OUT 8

OUT 2

GND

-

Power half-bridge 8

23

Power half-bridge 2

24

Ground. All ground pins should be externally connected together.

EDP

Exposed Die Pad; For cooling and EMC purposes only - not usable as electrical

ground. Electrical ground must be provided by pins 1,12,13,24. ¹⁾

1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The

exposed pad (EP) must be either left open or connected to GND. It is recommended to connect EP to GND for best

EMC and thermal performance.

Data Sheet

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TLE94112ES

Block Diagram

2

Block Diagram

VDD

VS1

VS2

12-Fold Half Bridge Driver

SPI Interface

UNDERVOLTAGE

&

OVERVOLTAGE

MONITOR

CHARGE

PUMP

Power stage

BIAS

&

MONITOR

PWM

GENERATOR

OUT 1

OUT 2

OUT 3

OUT 4

OUT 5

OUT 6

OUT 7

OUT 8

OUT 9

OUT 10

OUT 11

OUT 12

EN

Power driver

short to

sshhoortrttoto

shsohrootrptoeton load

battery

hhigighh-s-sididee

dhdriirvgiveher-rside

ddrirviveerr

shsohrotrtoto

bbaattteteryry

shdoertetoction

babtatettreyry

detection

babtatettreyry

ddeetetecctitoionn

battery

ddrirviveerr

dedteetcetciotinon

driver

dedteetcetciotinon

detection

short to ground

high-side

driver

detection

CSN

SCLK

SDI

temp

tetemmpp

LOGIC CONTROL & LATCH

SPI INTERFACE

overtemperature

detection

tetmempp

sensor

sesnetsneotsmerompr p

sesentnseostmeormrpp

sesennsosorr

temp

sensor

sesnesnosror

open load

opoepnenlolaodad

detection

open load

dedteetcetciotionn

open load

SDO

detection

current

cucrurreroneptnetn load

low-side

loloww-s-sididee

dlorloiwvwe-s-rsididee

cucrurrernetnt

rerententcttion

ccoonntrtoroll

control

ccuur

d

ccuurrerenntt

ddrirviveerr

low-side

ccoonntrtoroll

current

cocnotnrtorlol

ddrirviveerr

driver

shortctontrol

short to

short to battery

shsohrotrtoto

battery

sshhoortrttoto

batte tection

sshhoortrttoto

babtatettreyry

detecstihoonrt to

bbaattteteryry

detection

bbaattteteryry

dedteetcetciotinon

low-side

driver

drey

ERROR

DETECTION

battery

ddeetetecctitoionn

oddveeeterttecectmitoiponenrature

detection

GND

GND GND

GND

Figure 2

Block Diagram TLE94112ES (SPI Interface)

Data Sheet

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TLE94112ES

Block Diagram

2.1

Voltage and current definition

Figure 3 shows terms used in this datasheet, with associated convention for positive values.

V_S

I_S1

VS1 VS2

I_S2

I_DD

I_SDO

I_SDI

VDD

SDO

SDI

V_DD

V_SDO

V_SDI

V_CSN

V_SCLK

I_CSN

I_SCLK

V_DSHSx

V_DSLSx

I_OUTx

SPI INTERFACE

DRIVER

CSN

SCLK

OUT x

I_EN

EN

V_EN

GND GND GND GND

I_GNDI_GNDI_GND

I_GND

Figure 3

Voltage and Current Definition

Data Sheet

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TLE94112ES

General Product Characteristics

3

General Product Characteristics

3.1

Absolute Maximum Ratings

Table 2

Absolute Maximum Ratings¹⁾T_j= -40°C to +150°C

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Voltages

Supply voltage

V_S

-0.3

–

40

10

V

V_S= V_S1= V_S2

P_4.1.1

Supply Voltage Slew Rate

| dV_S/dt |

V/µs V_Sincreasing and P_4.2.2

decreasing ¹⁾

Power half-bridge output voltage

Logic supply voltage

V_OUT

V_DD

-0.3

–

40

V

0 V < V_OUT< V_S

0 V < V_S< 40 V

P_4.1.2

P_4.1.3

P_4.1.4

5.5

VDD

Logic input voltages

(SDI, SCLK, CSN, EN)

V_SDI

V_SCLK

_CSN, V_EN

V_SDO

,

0 V < V_S< 40 V

0 V < V_DD< 5.5V

,

V

Logic output voltage

(SDO)

-0.3

–

VDD

V

0 V < V_S< 40 V

0 V < V_DD< 5.5V

P_4.1.5

Currents

Continuous Supply Current for V_S1I_S1

Continuous Supply Current for V_S2I_S2

0

–

3.0

2.0

A

–

P_4.1.6

P_4.1.7

P_4.1.14

P_4.1.15

0

Current per GND pin

Output Currents

I_GND

0

I_OUT

-2.0

Temperatures

Junction temperature

Storage temperature

ESD Susceptibility

T_j

-40

-50

–

150

°C

–

P_4.1.8

P_4.1.9

T_stg

ESD susceptibility OUTn and VSx

pins versus GND. All other pins

grounded.

V_ESD

-8

–

8

kV

JEDEC HBM¹⁾²⁾

P_4.1.10

ESD susceptibility all pins

ESD susceptibility corner pins

V_ESD

-2

–

2

kV

V

JEDEC HBM¹⁾²⁾

CDM¹⁾³⁾

P_4.1.11

P_4.1.12

P_4.1.13

-500

500

750

-750

V

1) Not subject to production test, specified by design

2) ESD susceptibility, “JEDEC HBM” according to ANSI/ ESDA/ JEDEC JS001 (1.5 kΩ, 100pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Data Sheet

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TLE94112ES

General Product Characteristics

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

Data Sheet

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TLE94112ES

General Product Characteristics

3.2

Functional Range

Table 3

Functional Range

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Supply voltage range for

normal operation

V_S(nor)

5.5

–

18

V

–

P_4.2.1

1)2)

Extended supply voltage range V_S(ext)

18

–

20

V

P_4.2.7

P_4.2.3

Logic supply voltage range for

normal operation

V_DD

3.0

5.5

–

Logic input voltages

(SDI, SCLK, CSN, EN)

V_SDI

,

-0.3

–

5.5

V

–

P_4.2.4

P_4.2.5

V_SCLK

_CSN, V_EN

T_j

,

V

Junction temperature

-40

150

°C

1) Not subject to production test, specified by design.

2) In the extended supply range, the device is still functional. However, deviations of the specified electrical

characteristics are possible.

Note:

Within the normal functional range the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the related electrical

characteristics table.

Data Sheet

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TLE94112ES

General Product Characteristics

3.3

Thermal Resistance

Table 4

Thermal Resistance TLE94112ESTLE94110ES

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

1)

Junction to Case, T_A= 85°C

R_{thjC_hot}

–

1.7

–

K/W

1) 2)

Junction to ambient, T_A= 85°C R_{thjA_hot_m}

77.3

(1s0p, minimal footprint)

in

1) 3)

1) 1)

1) 5)

Junction to ambient, T_A= 85°C R_{thjA_hot_30}

(1s0p, 300mm2 Cu)

–

44.9

38.2

26.9

–

K/W

0

Junction to ambient, T_A= 85°C R_{thjA_hot_60}

(1s0p, 600mm2 Cu)

0

Junction to ambient, T_A= 85°C R_{thjA_hot_2s}

(2s2p)

2p

1) Specified R_thJAvalue is according to JEDEC JESD51-2, -3 at natural convection on FR4 1s0p board; The product (chip

+ package) was simulated on a 76.2 x 114.3 x 1.5mm board with additional cooling of 600mm2 copper area and 35µm

thickness. Ta = 85°C, each channel dissipates 0.135W.

Data Sheet

12

1.0

2020-09-29

TLE94112ES

General Product Characteristics

3.4

Electrical Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 18 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

I

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Current Consumption, EN = GND

Supply Quiescent current

I_SQ

–

0.5

0.1

0.6

2

1

3

µA

-40°C ≤ T_j≤ 85°C

P_4.4.1

P_4.4.2

P_4.4.3

Logic supply quiescent current I_{DD_Q}

Total quiescent current

I_SQ+ I_{DD_Q}

Current Consumption, EN=HIGH

Supply current

I_S

–

0.5

1

mA

Power drivers and P_4.4.4

power stages are

off

Supply current

I_{S_HSON}

I_DD

I_{DD_RUN}

I_S+ I_{DD_RUN}

–

4.5

1.5

5

9

3

–

mA

All high-sides ON¹⁾P_4.4.101

Logic supply current

Total supply current

SPI not active

SPI 5MHz ³⁾

P_4.4.5

P_4.4.6

P_4.4.7

5.5

Over- and Undervoltage Lockout

Undervoltage Switch ON

voltage threshold

V_{UV ON}

V_{UV OFF}

V_{UV HY}

4.25

4

–

5.25

5.0

–

V

V_Sincreasing

V_Sdecreasing

V_{UV ON}- V_{UV OFF}

V_Sincreasing

V_Sdecreasing

V_{OV OFF}- V_{OV ON}

P_4.4.8

Undervoltage Switch OFF

voltage threshold

–

P_4.4.9

3)

Undervoltage Switch ON/OFF

hysteresis

–

0.25

P_4.4.10

P_4.4.11

P_4.4.12

P_4.4.13

Overvoltage Switch OFF voltage V_{OV OFF}

threshold

21

20

–

1

25

24

–

Overvoltage Switch ON voltage V_{OV ON}

threshold

3)

Overvoltage Switch ON/OFF

hysteresis

V_{OV HY}

V_DDPower-On-Reset

V_{DD POR}

2.40

2.35

–

2.70 2.90

2.65 2.85

V

V_DDincreasing

V_DDdecreasing

V_{DD POR}- V_{DD POffR}

P_4.4.14

P_4.4.15

P_4.4.98

V_DDPower-Off-Reset

V_{DD POffR}

V_{DD POR HY}

3)

V_DDPower ON/OFF hysteresis

0.05

–

Static Drain-source ON-Resistance (High-Side or Low-Side)

High-Side or Low-Side R_DSON

(all outputs)

R_{DSON_HB_25C}

–

850 1200 mΩ

I_OUT= ±0.5 A;

T_j= 25 °C

P_4.4.16

P_4.4.17

High-Side or Low-Side R_DSON

(all outputs)

R_{DSON_HB_150}

–

1400 1800 mΩ

I_OUT= ±0.5 A;

T_j= 150 °C

C

Data Sheet

13

1.0

2020-09-29

TLE94112ES

General Product Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 18 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

I

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified) (cont’d)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

2)

High-Side R_DSON

(HS1 and HS2 in LED mode)

R_{DSON_HI_HB_}

–

950 1300 mΩ

I

= -0.1 A;

P_4.4.18

P_4.4.19

OUT

T_j= 25 °C

25C

2)

High-Side R_DSON

R_{DSON_HI_HB_}

–

1500 2000 mΩ

I

= -0.1 A;

OUT

(HS1 and HS2 in LED mode)

T_j= 150 °C

150C

Output Protection and Diagnosis of high-side (HS) channels of half-bridge output

HS Overcurrent Shutdown

Threshold

I_{SD_HS}

-1.4

-1.2

15

-1.1 -0.9

A

See Figure 7

P_4.4.89

P_4.4.21

P_4.4.22

Difference between shutdown I_{LIM_HS}

and limit current

-

-0.6

19

0

A

³⁾|I_{LIM_HS}| ≥ |I_{SD_HS|}

See Figure 7

3)

I_{SD_HS}

Overcurrent Shutdown filter

time

t_{dSD_HS}

23

µs

Open Load Detection Current

I_{OLD1_HS}

-15

-8

-3

mA

-

3)

P_4.4.23

P_4.4.24

Open Load Detection filter time t_{OLD1_HS}

2000 3000 4000 µs

Open Load Detection Current

for LED mode

I_{OLD2_HS1,2}

-3.2

-2

-0.5

mA

Bit OL_SEL_HS1 = P_4.4.25

1, OL_SEL_HS2 = 1

(HS1 & HS2)

Open Load Detection filter time t_{OLD2_HS1,2}

for LED mode

(HS1 & HS2)

100

200 300

µs

Bit OL_SEL_HS1 = P_4.4.26

1, OL_SEL_HS2 = 1;

3)

Output Protection and Diagnosis of low-side (LS) channels of half-bridge output

LS Overcurrent Shutdown

Threshold

I_{SD_LS}

0.9

1.1

0.6

19

8

1.4

1.2

23

A

Figure 8

P_4.4.104

P_4.4.28

P_4.4.29

3)

Difference between shutdown I_{LIM_LS}

and limit current

-

0

A

I

≥ I_{SD_LS}

LIM_LS

I_{SD_LS}

Figure 8

3)

Overcurrent Shutdown filter

time

t_{dSD_LS}

15

3

µs

mA

Open Load Detection Current

I_{OLD_LS}

15

-

3)

P_4.4.30

P_4.4.31

Open Load Detection filter time t_{OLD_LS}

Outputs OUT(1...n) leakage current

HS leakage current in off state I_{QLHn_NOR}

HS leakage current in off state I_{QLHn_SLE}

LS Leakage current in off state I_{QLLn_NOR}

LS Leakage current in off state I_{QLLn_SLE}

2000 3000 4000 µs

-2

–

-0.5

0.5

–

2

µA

V_OUTn= 0V ; EN=High P_4.4.32

V_OUTn= 0V; EN=GND P_4.4.33

V_OUTn= V_S; EN=High P_4.4.34

V_OUTn= V_S; EN=GND P_4.4.35

–

0.5

Output Switching Times. See Figure 9 and Figure 10.

Slew rate of high-side and low- d_VOUT/ dt

side outputs

0.1

0.45 0.75

V/µs Resistive load =

P_4.4.36

4)

100Ω; V_S=13.5V

Data Sheet

14

1.0

2020-09-29

TLE94112ES

General Product Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 18 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

I

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified) (cont’d)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Output delay time high side

driver on

t_dONH

t_dOFFH

t_dONL

t_dOFFL

5

20

45

20

45

35

75

35

75

µs

Resistive load =

100Ω to GND

P_4.4.37

P_4.4.38

P_4.4.39

P_4.4.40

P_4.4.41

P_4.4.42

Output delay time high side

driver off

15

5

Resistive load =

100Ω to GND

Output delay time low side

driver on

Resistive load =

100Ω to VS

Output delay time low side

driver off

15

100

Resistive load =

100Ω to VS

Cross current protection time, t_DHL

high to low

130 160

Resistive load =

100Ω³⁾

Cross current protection time, t_DLH

low to high

Resistive load =

100Ω³⁾

Input Interface: Logic Input EN

High-input voltage

V_ENH

V_ENL

0.7 *

V_DD

–

V

–

P_4.4.43

P_4.4.44

Low-input voltage

–

0.3 *

V_DD

3)

Hysteresis of input voltage

Pull down resistor

V_ENHY

–

500

40

–

mV

P_4.4.45

P_4.4.46

R_{PD_EN}

20

70

kΩ

V_EN= 0.2 x V_DD

SPI frequency

3) 5)

Maximum SPI frequency

f_SPI,max

–

5.0

MHz

µs

P_4.4.47

P_4.4.48

SPI INTERFACE: Delay Time from EN rising edge to first Data in

Setup time t_set150

SPI INTERFACE: Input Interface, Logic Inputs SDI, SCLK, CSN

–

³⁾See Figure 14

H-input voltage threshold

V_IH

0.7 *

V_DD

–

V

–

P_4.4.50

P_4.4.51

L-input voltage threshold

V_IL

–

0.3 *

V_DD

3)

Hysteresis of input voltage

Pull up resistor at pin CSN

V_IHY

–

500

50

–

mV

kΩ

P_4.4.52

P_4.4.53

R_{PU_CSN}

30

20

80

70

V_CSN= 0.7 x V_DD

Pull down resistor at pin SDI,

SCLK

R_{PD_SDI,}

R_{PD_SCLK}

40

V_SDI, V_SCLK= 0.2 x V_DDP_4.4.54

Input capacitance at pin CSN, C_I

SDI or SCLK

–

10

15

–

pF

V

0V < V_DD< 5.25V ³⁾

I_SDOH= -1.6 mA

P_4.4.55

P_4.4.56

Input Interface, Logic Output SDO

H-output voltage level

V_SDOH

V_DD

-

V_DD-

0.4

0.2

Data Sheet

15

1.0

2020-09-29

TLE94112ES

General Product Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 18 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

I

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified) (cont’d)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

L-output voltage level

V_SDOL

I_SDOLK

–

0.2

–

0.4

1

V

I_SDOL= 1.6 mA

V_CSN= V_DD

P_4.4.57

P_4.4.58

Tri-state Leakage Current

-1

µA

;

0V < V_SDO< V_DD

3)

Tri-state input capacitance

C_SDO

–

10

15

–

pF

P_4.4.59

Data Input Timing. See Figure 15 and Figure 17.

3)

SCLK Period

t_pCLK

200

–

ns

P_4.4.60

P_4.4.61

SCLK High Time

t_SCLKH

0.45 *

0.55 * ns

t_pCLK

3)

SCLK Low Time

t_SCLKL

0.45 *

–

0.55 * ns

P_4.4.62

t_pCLK

3)

SCLK Low before CSN Low

CSN Setup Time

t_BEF

125

250

125

30

–

ns

P_4.4.63

P_4.4.64

P_4.4.65

P_4.4.66

P_4.4.67

P_4.4.68

P_4.4.69

t_lead

–

SCLK Setup Time

t_lag

–

SCLK Low after CSN High

SDI Setup Time

t_BEH

–

t_{SDI_setup}

t_{SDI_hold}

t_rIN

–

SDI Hold Time

30

–

Input Signal Rise Time at pin

SDI, SCLK, CSN

–

50

3)

Input Signal Fall Time at pin SDI, t_fIN

SCLK, CSN

–

5

–

50

8

ns

µs

P_4.4.70

P_4.4.71

P_4.4.72

Delay time from EN falling edge t_DMODE

to standby mode

Minimum CSN High Time

t_CSNH

–

Data Output Timing. See Figure 15.

SDO Rise Time

SDO Fall Time

t_rSDO

t_fSDO

–

30

–

80

75

ns

C_load= 40pF ³⁾

Low Impedance ³⁾P_4.4.75

P_4.4.73

P_4.4.74

SDO Enable Time after CSN

falling edge

t_ENSDO

SDO Disable Time after CSN

rising edge

t_DISSDO

–

75

55

95

ns

%

High Impedance ³⁾P_4.4.76

3)

Duty cycle of incoming clock at duty_SCLK

SCLK

45

–

P_4.4.77

SDO Valid Time for V_DD= 3.3V

t_VASDO3

70

ns

V_SDO< 0.2 x V_DD

V_SDO> 0.8 x V_DD

C_load= 40pF ³⁾

P_4.4.78

Data Sheet

16

1.0

2020-09-29

TLE94112ES

General Product Characteristics

Table 5

Electrical Characteristics, V_S=5.5 V to 18 V, V_DD= 3.0V to 5.5V, T_j= -40°C to +150°C, EN= HIGH,

_OUTn= 0 A; Typical values refer to V_DD= 5.0 V, V_S= 13.5 V and T_J= 25 °C unless otherwise

I

specified; all voltages with respect to ground, positive current flowing into pin (unless

otherwise specified) (cont’d)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

SDO Valid Time for V_DD= 5V

t_VASDO5

–

50

65

ns

V_SDO< 0.2 x V_DD

V_SDO> 0.8 V_DD

C_load= 40pF ³⁾

P_4.4.79

Thermal warning & Shutdown

Thermal warning junction

temperature

T_jW

120

150

140 170

175 200

°C

See Figure 11³⁾

P_4.4.80

P_4.4.81

Thermal shutdown junction

temperature

T_jSD

3)

Thermal comparator hysteresis T_jHYS

Ratio of SD to W temperature _jSD/ T_jW

–

5

–

°C

–

P_4.4.82

P_4.4.83

T

1.05

1.20

1) I_{S_HSON}does not include the load current

2) HS1, respectively HS2, is set to LED mode by setting OL_SEL_HS1 bit to 1, respectively OL_SEL_HS2 bit to 1

3) Not subject to production test, specified by design

4) Measured for 20% - 80% of V_S.

5) Not applicable in daisy chain configuration

Data Sheet

17

1.0

2020-09-29

TLE94112ES

Characterization results

4

Characterization results

Performed on 7 devices from 2 lots, over operating temperature and nominal/extended supply range.

Typical performance characteristics

Supply quiescent current

Supply current

P_4.4.1

P_4.4.4

5.9

300

250

200

150

100

50

4.9

3.9

2.9

1.9

0.9

-0.1

0

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

Logic supply quiescent current

Logic supply current

P_4.4.2

P_4.4.5

0.4

0.89

0.88

0.87

0.86

0.85

0.84

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

-0.05

-0.1

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

Data Sheet

18

1.0

2020-09-29

TLE94112ES

Characterization results

HS static Drain-source ON-resistance

LS static Drain-source ON-resistance

P_4.4.16 and P_4.4.17

1500

1600

1500

1400

1300

1200

1100

1000

900

1400

1300

1200

1100

1000

900

800

700

600

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

HS static drain-source ON-resistance

VS = 13.5V and VDD = 5V

LS static drain-source ON-resistance

VS = 13.5V and VDD = 5V

P_4.4.16 and P_4.4.17

1600

1500

1400

1300

1200

1100

1000

900

1500

1400

1300

1200

1100

1000

900

800

700

600

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

OUT1

OUT7

OUT2

OUT8

OUT3

OUT9

OUT4

OUT5

OUT6

OUT1

OUT7

OUT2

OUT8

OUT3

OUT9

OUT4

OUT5

OUT6

OUT10 OUT11 OUT12

Data Sheet

19

1.0

2020-09-29

TLE94112ES

Characterization results

Slew rate ON of high-side outputs

Slew rate ON of low-side outputs

P_4.4.36

0.6

0.65

0.6

0.55

0.5

0.55

0.5

0.45

0.4

0.45

0.4

0.35

0.3

0.35

0.3

0.25

0.2

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

Slew rate OFF of high-side outputs

Slew rate OFF of low-side outputs

P_4.4.36

0.65

0.6

0.55

0.5

0.6

0.55

0.5

0.45

0.4

0.45

0.4

0.35

0.3

0.35

0.3

0.25

0.2

0.25

0.2

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

Data Sheet

20

1.0

2020-09-29

TLE94112ES

Characterization results

HS overcurrent shutdown threshold

LS overcurrent shutdown threshold

P_4.4.89

P_4.4.104

-1000

1160

-1020

-1040

-1060

-1080

-1100

-1120

-1140

-1160

-1180

1140

1120

1100

1080

1060

1040

1020

-1200

1000

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

VS=5.5V

VS=13.5V

VS=18V

VS=19V

VS=21V

Undervoltage switch ON voltage threshold

Undervoltage switch OFF voltage threshold

P_4.4.8

P_4.4.9

4.95

4.79

4.9

4.85

4.8

4.74

4.69

4.64

4.59

4.75

4.7

4.65

4.54

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VDD=3V

VDD=5V

VDD=5.5V

VDD=3V

VDD=5V

VDD=5.5V

Data Sheet

21

1.0

2020-09-29

TLE94112ES

Characterization results

Overvoltage switch ON voltage threshold

Overvoltage switch OFF voltage threshold

P_4.4.12

P_4.4.11

22.8

23.6

22.7

22.6

22.5

22.4

22.3

22.2

22.1

22

23.5

23.4

23.3

23.2

23.1

23

22.9

21.9

22.8

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VDD=3V

VDD=5V

VDD=5.5V

VDD=3V

VDD=5V

VDD=5.5V

VDD Power-on-reset and VDD Power-off-reset

P_4.4.14 and P_4.4.15

2.68

2.66

2.64

2.62

2.60

2.58

2.56

-50 -30 -10 10 30 50 70 90 110 130 150

Junction Temperature [°C]

VDD POR

VDD POffR

Data Sheet

22

1.0

2020-09-29

TLE94112ES

General Description

5

General Description

5.1

Power Supply

The TLE94112ES has two power supply inputs, V_Sand V_DD. The half bridge outputs are supplied by V_S, which is

connected to the 12V automotive supply rail. V_DDis used to supply the I/O buffers and internal voltage

regulator of the device.

V_Sand V_DDsupplies are separated so that information stored in the logic block remains intact in the event of

voltage drop outs or disturbances on V_S. The system can therefore continue to operate once V_Shas recovered,

without having to resend commands to the device.

A rising edge on V_DDcrossing V_{DD POR}triggers an internal Power-On Reset (POR) to initialize the IC at power-on.

All data stored internally is deleted, and the outputs are switched off (high impedance).

An electrolytic and 100nF ceramic capacitors are recommended to be placed as close as possible to the V_S

supply pin of the device for improved EMC performance in the high and low frequency band. The electrolytic

capacitor must be dimensioned to prevent the VS voltage from exceeding the absolute maximum rating. In

addition, decoupling capacitors are recommended on the V_DDsupply pin.

5.2

Operation modes

5.2.1

Normal mode

The TLE94112ES enters normal mode by setting the EN input High. In normal mode, the charge pump is active

and all output transistors can be configured via SPI.

5.2.2

Sleep mode

The TLE94112ES enters sleep mode by setting the EN input Low. The EN input has an internal pull-down

resistor.

In sleep mode, all output transistors are turned off and the SPI register banks are reset. The current

consumption is reduced to I_SQ+ I_{DD_Q}

.

5.3

Reset Behaviour

The following reset triggers have been implemented in the TLE94112ES:

_DDUndervoltage Reset:

V

The SPI Interface shall not function if V_DDis below the undervoltage threshold, V_{DD POffR}. The digital block will

be deactivated, the logic contents cleared and the output stages are switched off . The digital block is

initialized once V_DDvoltage levels is above the undervoltage threshold, V_{DD POR}. Then the NPOR bit is reset

(NPOR = 0 in SYS_DIAG1 and Global Status Register).

Reset on EN pin:

If the EN pin is pulled Low, the logic content is reset and the device enters sleep mode.

The reset event is reported by the NPOR bit (NPOR = 0) once the TLE94112ES is in normal mode (EN = High; VDD

> V_{DD POR}).

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General Description

5.4

Reverse Polarity Protection

The TLE94112ES requires an external reverse polarity protection. During reverse polarity, the free-wheeling

diodes across the half bridge output will begin to conduct, causing an undesired current flow (I_RB) from ground

potential to battery and excessive power dissipation across the diodes. As such, a reverse polarity protection

diode is recommended (see Figure 4).

b)

VBAT

a)

GND

D

RP

CS2

C

S

HSx

OUTx

LSx

I

RB

VBAT

GND

Figure 4

Reverse Polarity Protection

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TLE94112ES

Half-Bridge Outputs

6

Half-Bridge Outputs

6.1

Functional Description

The half-bridge outputs of the TLE94112ES are intended to drive motor loads. These outputs can either be

driven continuously or PWM enabled via SPI.

If the outputs are driven continuously via SPI, for example HS1 and LS2 used to drive a motor, then the

following suggested SPI commands shall be sent:

•

Activate HS1: Bit HB1_HS_EN in HB_ACT_1_CTRL register

Activate LS2: Bit HB2_LS_EN in HB_ACT_1_CTRL register

6.1.1

Half-bridge operation with PWM enabled

All half-bridge outputs of the TLE94112ES are capable of PWM operation. They can either be used to drive an

inductive load (e.g. DC brush motor) or optionally a resistive load (e.g. LED). Each half-bridge output has been

allocated a maximum of three PWM channels with individual duty cycle settings with 8-bit resolution. Each

channel is further mapped to a maximum of three PWM frequency options, i.e. 80Hz,100Hz and 200Hz. This

feature enables a highly flexible PWM operation while driving loads with varying control profiles.

PWM frequency and duty cycle can be changed on demand during PWM operation of the desired half-bridge

output. Glitches on the PWM output waveform, which may arise as a result of on-demand changes in PWM

operation, will be prevented by the internal logic circuitry.

When operating with motor loads, active or passive free-wheeling configuration is available via SPI to select

the speed at which the inductive current can decay over the full-bridge circuit. The default setting is passive

free-wheeling.

Note:

Active free-wheeling is effectively applied if the selected duty cycle corresponds to turn-on times of

the HS and the LS, which are longer than the sum of the cross conduction times tDHL + tDLH.

Table 6

PWM capability and frequency selection per half-bridge output

Control Register:

HBx_MODEn (n=0,1) (Control Register:

PWM_CH_FREQ_CTRL)

PWM Frequency 80Hz

PWM Frequency 100Hz

(Control Register:

PWM_CH_FREQ_CTRL)

PWM Frequency 200Hz

(Control Register:

PWM_CH_FREQ_CTRL)

PWM Channel 1

PWM Channel 2

PWM Channel 3

PWM_CH1_FREQ_n (n=0,1) PWM_CH1_FREQ_n (n=0,1) PWM_CH1_FREQ_n (n=0,1)

Bit ‘01_B’ Bit ‘10_B’ Bit ‘11_B’

PWM_CH2_FREQ_n (n=0,1) PWM_CH2_FREQ_n (n=0,1) PWM_CH2_FREQ_n (n=0,1)

Bit ‘01_B’ Bit ‘10_B’ Bit ‘11_B’

PWM_CH3_FREQ_n (n=0,1) PWM_CH3_FREQ_n (n=0,1) PWM_CH3_FREQ_n (n=0,1)

Bit ‘01_B’

Bit ‘10_B’

Bit ‘11_B’

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Half-Bridge Outputs

6.1.1.1 Inductive Load

An illustration is shown in Figure 5 with OUT1 and OUT2 driving a DC brush motor. With this configuration,

HS1 is permanently driven while LS2 is driven in PWM operation. HS2 serves to actively free-wheel (FW) the

motor current load, reducing the power dissipation of the device.

VS

HBn

HS2

active FW

HS1 ON

OUT 1

t

FW

M1

OUT 1

OUT 2

CW

t

LS1

LS2 PWM

CW = motor clockwise

FW = Free-wheeling

Figure 5

PWM operation on OUT 2

Assuming HBx Mode = 00 and both HSx and LSx are considered off (tri-state). The suggested SPI control

commands for proper PWM operation are:

Option 1: The considered output is not put in parallel with another one

•

Configure the frequency to 00 (PWM is stopped and off) for selected PWM channel

Configure active or passive free-wheeling of the inductive decay current in FW_CTRL register

Assign an appropriate PWM channel for selected half-bridge output in HB_MODE_CTRL register

Configure the duty cycle of the selected half-bridge output in PWM_DC_CTRL register

Select the PWM frequency in PWM_CH_FREQ_CTRL register to begin the PWM period

Activate the channel to be driven in PWM operation: HSn or LSn in the HB_ACT_CTRL register

Option 2: Outputs controlled by different control registers are put paralleled. This sequence ensures

that corresponding HS or LS are activated simultaneously

•

Configure the frequency 00 (PWM is stopped and off) for selected PWM channel

Configure active or passive free-wheeling of the inductive decay current in FW_CTRL register

Assign an appropriate PWM channel for selected half-bridge output in HB_MODE_CTRL register

Configure the duty cycle of the selected half-bridge output in PWM_DC_CTRL register

Activate the channel to be driven in PWM operation: HSn or LSn in the HB_ACT_CTRL register

Select the PWM frequency in PWM_CH_FREQ_CTRL register to begin the PWM period

Careful attention should be paid to the free-wheeling configuration of the half-bridge required to be driven in

PWM operation. For example, in the event a high-side channel is activated and assigned a PWM channel, and

active free-wheeling is selected, but a frequency mode of ‘00’ (PWM is stopped and off) is configured in the

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Half-Bridge Outputs

PWM_CH_FREQ_CTRL register, then the respective high-side channel will be configured low and the adjacent

low-side channel within the half-bridge will be enabled. This is a result of enabling active free-wheeling.

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Half-Bridge Outputs

6.1.1.2 LED mode (optional)

Outputs, OUT1 and OUT2, are designed to optionally drive low current loads such as LEDs. The high-side

channels, HS1 and HS2 are equipped with a lower open load threshold detection current and shorter filter

time, specifically for low current loads such as LEDs. See OL_SEL_HS1 and OL_SEL_HS2 bits in FW_OL_CTRL

register. Setting HS1 or HS2 in LED mode increases the R_DSONand decreases the open load detection threshold.

An illustration is shown in Figure 6 with OUT1 driving an LED. With this configuration, HS1 is driven in PWM

operation while LS1 is deactivated.

VS

HS1 PWM

OUT 1

Figure 6

PWM operation on OUT 1

Assuming HBx Mode = 00 and both HSx and LSx are considered off (tri-state). The suggested SPI control

commands are:

•

Configure frequency 00 (PWM is stopped and off) for selected channel to ensure PWM is off.

Assign an appropriate PWM channel for selected HS1 or HS2 output in HB_MODE_CTRL register

Configure duty cycle of selected HS1 or HS2 output in PWM_DC_CTRL register

Activate channel to be driven in PWM operation: HS1 or HS2 in the HB_ACT_CTRL register

Select low current open load detection threshold for HS1 or HS2 in FW_OL_CTRL register

Select PWM frequency in PWM_CH_FREQ_CTRL register to begin the PWM period.

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TLE94112ES

Half-Bridge Outputs

6.2

Protection & Diagnosis

The TLE94112ES is equipped with an SPI interface to control and diagnose the state of the half-bridge drivers.

This device has embedded protective functions which are designed to prevent IC destruction under fault

conditions described in the following sections. Fault conditions are treated as “outside” normal operating

range. Protection functions are not designed for continuous repetitive operation.

The following table provides a summary of fault conditions, protection mechanisms and recovery states

embedded in the TLE94112ES device.

Table 7

Summary of diagnosis and monitoring of outputs

Fault

condition

Error Flag Error bit: Status Register

(EF)

behaviour

Output

Protection

mechanism state

Error output High-Z Half-bridgecontrol

Output Output and error

error flag (EF) recovery

Overcurrent Latch

1. Load Error bit, LE (bit 6) in

SYS_DIAG 1: Global Status 1

Register

2. Localized error for each HS and

LS channel of half-bridge,

HBn_HS_OC and HBn_LS_OC bits

in SYS_DIAG_2, SYS_DIAG_3,

SYS_DIAG_4 status registers.

shutdown

and latched

bits remain set

despite error,

however the

output stage is

shutdown.ClearEF

to reactivate

output stage.

Open load

Latch

1. Load Error bit, LE (bit 6) in

SYS_DIAG 1: Global Status 1

Register

2. Localized error for each HS and

LS channel of half-bridge,

HBn_HS_OL and HBn_LS_OL bits in

SYS_DIAG_5, SYS_DIAG_6,

SYS_DIAG_7 status registers.

None

No

state

An open load

detection does not

change change the state of

the output.

EF to be cleared.

Temperature Latch

pre-warning

Global error bit 1, TPW in

SYS_DIAG_1: Global Status 1

register

None

No

state

change

Not applicable

Temperature Latch

shutdown

Global error bit 2, TSD in

SYS_DIAG_1: Global Status 1

register

All outputs

shutdown

and latched.

High-Z Half-bridgecontrol

bits remain set

despite error,

however the

output stage is

shutdown.ClearEF

to reactivate

output stage.

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TLE94112ES

Half-Bridge Outputs

Table 7

Summary of diagnosis and monitoring of outputs (cont’d)

Fault

condition

Error Flag Error bit: Status Register

(EF)

Output

Protection

Output Output and error

error flag (EF) recovery

behaviour

mechanism state

Powersupply Latch

failure due to

undervoltage

Global error bit 5, VS_UV in

SYS_DIAG_1: Global Status 1

register

All outputs

shutdown

and

High-Z Half-bridgecontrol

bits remain set

despite error,

automatically

recovers.

however the

output stage is

shutdown. They

will automatically

be reactivated

once the power

supplyrecovers. EF

to be cleared.

Powersupply Latch

failure due to

overvoltage

Global error bit 4, VS_OV in

SYS_DIAG_1: Global Status 1

register

All outputs

shutdown

and

High-Z Half-bridgecontrol

bits remain set

despite error,

automatically

recover.

however the

output stage is

shutdown. They

will automatically

be reactivated

once the power

supplyrecovers. EF

to be cleared.

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TLE94112ES

Half-Bridge Outputs

6.2.1

Short Circuit of Output to Supply or Ground

The high-side switches are protected against short to ground whereas the low-side switches are protected

against short to supply.

The high-side and low-side power switches will enter into an over-current condition if the current within the

switch exceeds the overcurrent shutdown detection threshold, I_SD. Upon detection of the I_SDthreshold, an

overcurrent shutdown filter, t_dSDis begun. As the current rises beyond the threshold I_SD, it will be limited by the

current limit threshold, I_LIM. Upon expiry of the overcurrent shutdown filter time, the affected power switch is

latched off and the corresponding error bit, HBn_HS_OC or HBn_LS_OC is set and latched. See Figure 7 and

Figure 8 for more detail. A global load error bit, LE, contained in the global status register, SYS_DIAG_1, is also

set for ease of error scanning by the application software. The power switch remains deactivated as long as

the error bit is set.

To resume normal functionality of the power switch (in the event the overcurrent condition disappears or to

verify if the failure still exists) the microcontroller shall clear the error bit in the respective status register to

reactivate the desired power switch.

VS

| I_HS|

I I_{LIM_HS}I

ON

I I_{LIM_HS}- I_{SD_HS}

I

I I_{SD_HS}

I

OUTn

Short to GND

t

t_{dSD_ HS}

Short condition on High-Side Switch

Figure 7

High-Side Switch - Short Circuit and Overcurrent Protection

VS

I_LS

VS

I_{LIM_ LS}

I_{LIM_ LS}- I_{SD_LS}

Short to Supply

I_{SD_LS}

OUTn

ON

t

t_{dSD_LS}

Short condition on Low-Side Switch

Figure 8

Low-Side Switch - Short Circuit and Overcurrent Protection

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Half-Bridge Outputs

Table 8

Control and Status register bit state in the event of an overcurrent condition for an

activated power switch

BEFORE

DURING

AFTER

REGISTER

TYPE

REGISTER NAME Bit

OVERCURRENT OVERCURRENT OVERCURRENT

Bit State

Control

HB_ACT_CTRL_n HBn_HS_EN

HBn_LS_EN

1

1(corresponding

half-bridge

deactivated)

Status

SYS_DIAG_1:

Global Status 1

LE

0

1

SYS_DIAG_x

where x=2,3,4

HBn_HS_OC

HBn_LS_OC

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Half-Bridge Outputs

6.2.2

Cross-Current

In bridge configurations the high-side and low-side power transistors are ensured never to be simultaneously

“ON” to avoid cross currents. This is achieved by integrating delays in the driver stage of the power outputs to

create a dead-time between switching off of one power transistor and switching on of the adjacent power

transistor within the half-bridge. The dead times, t_DHLand t_DLH, as shown in Figure 9 case 3 and Figure 10 case

3, have been specified to ensure that the switching slopes do not overlap with each other. This prevents a cross

conduction event.

CSN

t

Case 1: Delay TimeHigh SideDriver OFF

VOUT_HSx [V]

Previous State à New State

HS ON à HS OFF

VS

80%

1)

t_dOFFH

LS OFF à LS OFF

20%

GND ₁₎

t

Delay time HS OFF

Case 2: Delay Time Low Side Driver ON

VOUT_LSx [V]

Previous Stateà New State

HS OFF à HS OFF

VS

80%

2)

t_dONL

LS OFF à LS ON

20%

²⁾Delay time LS ON without dead time ; HS previously OFF

GND

t

Case 3: Delay Time Low Side Driver ON with t_DHLdead time

VOUT_LSx [V]

Previous Stateà New State

HS ON à HS OFF

VS

80%

Low-Side

ON

delay time

3)

t_dONL+t_DHL

LS OFF à LS ON

20%

³⁾Delay time LS ON with dead time ; HS previously ON

GND

t

Figure 9

Half bridge outputs switching times - high-side to low-side transition

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Half-Bridge Outputs

CSN

t

Case 1: Delay Time High Side Driver OFF

Previous Stateà New State

HS OFF à HS OFF

VOUT_LSx [V]

VS

80%

1)

t_dOFFL

LS ON à LS OFF

20%

GND

t

1)

Delay time LS OFF

Case 2: Delay Time High Side Driver ON

VOUT_HSx [V]

Previous Stateà New State

HS OFF à HS ON

VS

80%

2)

t_dONH

LS OFF à LS OFF

20%

²⁾Delay time HS ON without dead time ; LS previously OFF

GND

t

Case 3: Delay Time High Side Driver ON with t_DLHdead time

VOUT _HSx [V]

Previous Stateà New State

HS OFF à HS ON

VS

80%

High-Side

ON

delay time

3)

t_dONH+t_DLH

LS ON à LS OFF

20%

³⁾HS ON delay time with dead time ; LS previously ON

GND

t

Figure 10 Half bridge outputs switching times- low-side to high-side transition

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Half-Bridge Outputs

6.2.3

Temperature Monitoring

Temperature sensors are integrated in the power stages. The temperature monitoring circuit compares the

measured temperature to the warning and shutdown thresholds. If one or more temperature sensors reach

the warning temperature, the temperature pre-warning bit, TPW is set. This bit is latched and can only be

cleared via SPI. The outputs stages however remain activated.

If one or more temperature sensors reach the shut-down temperature threshold, all outputs are latched off.

The TSD bit in SYS_DIAG_1: Global Status 1 is set. All outputs remain deactivated until the TSD bit is cleared.

See Figure 11.

To resume normal functionality of the power switch (in the event the overtemperature condition disappears,

or to verify if the failure still exists) the microcontroller shall clear the TSD error bit in the status register to

reactivate the respective power switch.

T_j

T_jSD

T_jW

t

V_OUTx

Output is switched off if

ON

T_jSDis reached, can be

reactivated if TSD bit is

cleared

High Z

t

no error

TPW error bit

High

TPW is latched, can

be cleared via SPI

Low

no error

TSD error bit

High

TSD is latched, can be

cleared via SPI

Low

t

no error

Figure 11 Overtemperature Behavior

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Half-Bridge Outputs

Table 9

Control and Status register bit state in the event of an overtemperature condition for an

activated power switch

T_j< T_jW

T_j> T_jW

T_j> T_jSD

T_j< T_jSD- T_jHYS

REGISTER REGISTER NAME

TYPE

Bit

Bit State

Control

HB_ACT_CTRL_n

HBn_HS_EN

HBn_LS_EN

1

‘1’ (outputs

(all outputs are latched off

are latched unless error is

off)

cleared)

Status

SYS_DIAG_1: Global TPW

status 1

0

1

‘0’ if error is

cleared and

T_j< T_jW, else ‘1’

(latched)

SYS_DIAG_1: Global TSD

status 1

0

1

‘0’ if error is

cleared, else

‘1’

(latched)

6.2.4

Overvoltage and undervoltage shutdown

The power supply rails V_Sand V_DDare monitored for supply fluctuations. The V_Ssupply is monitored for under-

and over-voltage conditions where as the V_DDsupply is monitored for under-voltage conditions.

6.2.4.1 V_SUndervoltage

In the event the supply voltage V_Sdrops below the switch off voltage V_{UV OFF}, all output stages are switched off,

however, the logic information remains intact and uncorrupted. The V_Sunder-voltage error bit, VS_UV,

located in SYS_DIAG_1: Global Status 1 status register, will be set and latched. If V_Srises again and reaches the

switch on voltage V_{UV ON}threshold, the power stages will automatically be activated. The VS_UV error bit

should be cleared to verify if the supply disruption is still present. See Figure 12.

6.2.4.2 V_SOvervoltage

In the event the supply voltage V_Srises above the switch off voltage V_{OV OFF}, all output stages are switched off.

The V_Sover-voltage error bit, VS_OV, located in SYS_DIAG_1: Global Status 1 status register, will be set and

latched. If V_Sfalls again and reaches the switch on voltage V_{OV ON}threshold, the power stages will automatically

be activated. The VS_OV error bit should be cleared to verify if the overvoltage condition is still present. See

Figure 12.

6.2.4.3 V_DDUndervoltage

In the event the VDD logic supply decreases below the undervoltage threshold, V_{DD POffR}, the SPI interface shall

no longer be functional and the TLE94112ES will enter reset.

The digital block will be initialized and the output stages are switched off to High impedance. The

undervoltage reset is released once V_DDvoltage levels are above the undervoltage threshold, V_{DD POR}

.

The reset event is reported in SYS_DIAG1 by the NPOR bit (NPOR = 0) once the TLE94112ES is in normal mode

(EN = High ; VDD > V_{DD POR}).

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Half-Bridge Outputs

V_S

V_{OV HY}

V_{OV OFF}

V_{OV ON}

V_{UV HY}

V_{UV ON}

V_{UV OFF}

t

Output

reactivated

V_OUTx

Output

reactivated

V_OUTx

ON

High Z

t

SPI command :

Clear SYS _DIAG1

SPI command

Clear SYS_DIAG1

VS_UV error bit

VS_OV error bit

High

Low

High

Low

t

Figure 12 Output behavior during under- and overvoltage V_Scondition

6.2.5

Open Load

Both high-side and low-side switches of the half-bridge power outputs are capable of detecting an open load

in their activated state. If a load current lower than the open load detection threshold, I_OLDfor at least t_dOLDis

detected at the activated switch, the corresponding error bit, HBn_HS_OL or HBn_LS_OL is set and latched. A

global load error bit, LE, in the global status register, SYS_DIAG_1: Global Status 1, is also set for ease of error

scanning by the application software. The half-bridge output however, remains activated.

The microcontroller must clear the error bit in the respective status register to determine if the open load is

still present or disappeared.

High-side outputs, HS1 and HS2, are specifically designed to detect open load thresholds for LED loads. Both

HS1 and HS2 have a unique and lower open load current threshold and filter time which are configurable via

SPI in control register, FW_OL_CTRL.

During PWM operation, the open load detection is blanked and will not be visible in the status register for

power stages used in active free-wheeling

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7

Serial Peripheral Interface (SPI)

The TLE94112ES has a 16-bit SPI interface for output control and diagnostics. This section describes the SPI

protocol, the control and status registers.

7.1

SPI Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input

SCLK provided by the microcontroller. SCLK must be Low during CSN falling edge (Clock Polarity = 0). The SPI

incorporates an in-frame response: the content of the addressed register is shifted out at SDO within the same

SPI frame (see Figure 19 and Figure 21).The transmission cycle begins when the chip is selected by the input

CSN (Chip Select Not), Low active. After the CSN input returns from Low to High, the word that has been read

is interpreted according to the content. The SDO output switches to tri-state status (High impedance) at this

point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input register with every

falling edge on SCLK. The state of SDO is shifted out of the output register at every rising edge on SCLK (Clock

Phase = 1). The SPI protocol of the TLE94112ES is compatible with independent slave configuration and with

daisy chain. Daisy chaining is applicable to SPI devices with the same protocol.

Writing, clearing and reading is done byte wise. The SPI configuration and status bits are not cleared

automatically by the device and therefore must be cleared by the microcontroller, e.g. if the TSD bit was set

due to over temperature (refer to the respective register description for detailed information).

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN

time

CSN low to high: data from shift register is transferred to output functions

SCLK

time

LSB

MSB

Actual data

New data

0 1

+ +

SDI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

time

SDI: will accept data on the falling edge of SCLK signal

Actual status

New status

GEF 0 1

+ +

SDO

GEF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

+

time

SDO will change state on the rising edge of SCLK signal

Figure 13 SPI Data Transfer Timing (note the reversed order of LSB and MSB as shown in this figure

compared to the register description)

SPI messages are only recognized if a minimum set time, tSET, is observed upon rising edge of the EN pin

(Figure 14).

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Serial Peripheral Interface (SPI)

EN

t_SET

SPI

A) SPI message ignored

B) SPI message accepted

Figure 14 Setup time from EN rising edge to first SPI communication

t_lead

t_lag

t_CSNH

t_pCLK

0.8V_DD

0.2V_DD

CSN

t_SCLKH

t_SCLKL

0.8VDD

0.2V_DD

SCLK

SDI

t_{SDI_setup}

t_{SDI_hold}

0.8V_DD

0.2V_DD

t_ENSDO

t_VASDO

t_DISSDO

0.8V_DD

0.2V_DD

SDO

Figure 15 SPI Data Timing

7.1.1

Global Error Flag

A logic OR combination between Global Error Flag (GEF) and the signal present on SDI is reported on SDO

between a CSN falling edge and the first SCLK rising edge (Figure 13). GEF is set if a fault condition is detected

or if the device comes from a Power On Reset (POR).

Note:

The SDI pin of all devices in daisy chain or non daisy chain mode must be Low at the beginning of the

SPI frame (between the CSN falling edge and the first SCLK rising edge).

It is possible to check if the TLE94112ES has detected a fault by reading the GEF without SPI clock pulse

(Figure 16).

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Serial Peripheral Interface (SPI)

CSN

time

0

SCLK

SDI

time

High Impedance

Global Error Flag

SDO

time

Figure 16 SDO behaviour with 0-clock cycle

7.1.2

Global Status Register

The SDO shifts out during the first eight SCLK cycles the Global Status Register. This register provides an

overview of the device status. All failures conditions are reported in this byte:

•

SPI protocol error (SPI_ERR)

Load Error (LE bit): logical OR between Open Load (OL) and Overcurrent (OC) failures

VS Undervoltage (VS_UV bit)

VS Overvoltage (VS_OV bit)

Negated Power ON Reset (NPOR bit)

Temperature Shutdown (TSD bit)

Temperature Pre-Warning (TPW bit)

See Chapter 7.7.1 for details.

Note: The Global Error Flag is a logic OR combination of every bit of the Global Status Register with the

exception of NPOR: GEF = (SPI_ERR) OR (LE) OR (VS_UV) OR (VS_OV) OR (NOT(NPOR)) OR (TSD) OR

(TPW).

The following table shows how failures are reported in the Global Status Register and by the Global Error Flag.

Table 10 Failure reported in the Global Status Register and Global Error Flag

Type of Error

Failure reported in the Global

Status Register

Global Error Flag

SPI protocol error

Open load or Overcurrent

VS Undervoltage

SPI_ERR = 1

LE = 1

1

VS_UV = 1

VS_OV = 1

NPOR = 0

TSD = 1

VS Overvoltage

Power ON Reset

Thermal Shutdown

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Serial Peripheral Interface (SPI)

Table 10 Failure reported in the Global Status Register and Global Error Flag

Type of Error

Failure reported in the Global

Status Register

Global Error Flag

Thermal Warning

TPW = 1

1

0

No Error and no Power ON Reset

SPI_ERR = 0

LE = 0

VS_UV = 0

VS_OV = 0

NPOR = 1

TSD = 0

TPW = 0

Note:

The default value (after Power ON Reset) of NPOR is 0, therefore the default value of GEF is 1.

7.1.3

SPI protocol error detection

The SPI incorporates an error flag in the Global Status Register (SPI_ERR, Bit7) to supervise and preserve the

data integrity. If an SPI protocol error is detected during a given frame, the SPI_ERR bit is set in the next SPI

communication.

The SPI_ERR bit is set in the following error conditions:

•

the number of SCLK clock pulses received when CSN is Low is not 0, or is not a multiple of 8 and at least 16

the microcontroller sends an SPI command to an unused address. In particular, SDI stuck to High is

reported in the SPI_ERR bit

•

the LSB of an address byte is not set to 1. In particular, SDI stuck to Low is reported in the SPI_ERR bit

the Last Address Bit Token (LABT, bit 1 of the address byte, see Chapter 7.2) in independent slave

configuration is not set to 1

•

the LABT bit of the last address byte in daisy chain configuration is not set to 1 (see Chapter 7.3)

a clock polarity error is detected (see Figure 17 Case 2 and Case 3): the incoming clock signal was High

during CSN rising or falling edges.

For a correct SPI communication:

•

SCLK must be Low for a minimum t_BEFbefore CSN falling edge and t_leadafter CSN falling edge

SCLK must be Low for a minimum t_lagbefore CSN rising edge and t_BEHafter CSN rising edge

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

Case 1: Correct SCLK signal

Correct incoming clock signal

Correct clock during CSN rising edge

CSN

time

t_BEF

t_lead

t_lagt_BEH

SCLK

time

Case 2: Erroneous incoming clock signal

CSN

time

SCLK is High with CSN falling edge

SCLK

Case 3: Erroneous clock signal during CSN rising edge

CSN

time

Clock is High with CSN rising edge

SCLK

Figure 17 Clock Polarity Error

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7.2

SPI with independent slave configuration

In an independent slave configuration, the microcontroller controls the CSN of each slave individually

(Figure 18).

Microcontroller

TLE941xy_1

SPI

TLE941xy_2

SPI

TLE941xy_3

SPI

SDI1

SDO1 SDI2

SDO2 SDI3

SDO3

MCSN1

MCSN2

MCSN3

MCLK

MO

MI

Figure 18 SPI with independent slave configuration

Each SPI communication starts with one address byte followed by one data byte (Figure 19).The LSB of the

data byte must be set to ‘1’.The address bytes specifies:

•

the type of operation: READ ONLY (OP bit =0) or READ/ WRITE (OP bit = 1) of the configuration bits, and

READ ONLY (OP bit =0)or READ & CLEAR (OP bit = 1) of the status bits.

•

The target register address (A[6:2])

The Last Address Byte Token bit (LABT, Bit1 of the address byte) must be set to 1, as no daisy chain

configuration is used.

While the microcontroller sends the address byte on SDI, SDO shifts out GEF and the Global Status Register.

A further data byte (Bit15...8) is allocated to either configure the half-bridges or retrieve status information of

the TLE94112ES.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

Address Byte

Data Byte

MSB

15

LSB

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

LABT

= 1

SDI

1

A2

A3

A4

A5

A6

OP

D0

D1

D2

D3

D4

D5

D6

D7

Register content of the selected address

Global Status Register

Data Byte (Response)

MSB

15

LSB

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SPI_

ERR

SD0

0

TPW TSD NPOR VS_OV VS_UV LE

D0

D1

D2

D3

D4

D5

D6

D7

Time

LSB is sent first in SPI message

Figure 19 SPI Operation Mode with independent slave configuration

The in-frame response characteristic enables the microcontroller to read the contents of the addressed

register within the SPI command. See Figure 19.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7.3

Daisy chain operation

The TLE94112ES supports daisy chain operation with devices with the same SPI protocol.This section

describes the daisy chain hardware configuration with three devices from the TLE941xy family (See

Figure 20).

The master output (noted MO) is connected to a slave SDI and the first slave SDO is connected to the next slave

SDI to form a chain. The SDO of the final slave in the chain will be connected to the master input (MI) to close

the loop of the SPI communication frame. In daisy chain configuration, a single chip select, CSN, and clock

signal, SCLK, connected in parallel to each slave device, are used by the microcontroller to control or access

the SPI devices.

In this configuration, the Master Output must send the address bytes and data bytes in the following order:

•

All address bytes must be sent first:

–

Address Byte 1 (for TLE941xy_1) is sent first, followed by Address Byte 2 (for TLE941xy_2) etc,...

The LABT bit of the last address byte must be 1, while the LABT bit of all the other address bytes must

be 0

The data bytes are sent all together once all address bytes have been transmitted: Data Byte 1 (for

TLE941xy_1) is sent first, followed by Data Byte 2 (for TLE941xy_2) etc,...

Note:

The signal on the SDI pin of the first IC in daisy chain (and in non-daisy chain mode), must be Low at

the beginning of the SPI frame (between CSN falling edge and the first SCLK rising edge). This is

because each Global Error Flag in daisy chain operation is implemented in OR logic.

The Master Input (MI), which is connected to the SDO of the last device in the daisy chain receives:

•

A logic OR combination of all Global Error Flags (GEF), at the beginning of the SPI frame, between CSN

falling edge and the first SCLK rising edge

The logic OR combination of the GEFs is followed by the Global Status Registers in reverse order. In other

words MI receives first the Global Status Register of the last device of the daisy chain

Once all Global Status Registers are received, MI receives the response bytes corresponding to the

respective address and data bytes in reverse order. For example, if the daisy chain consists of three devices

with SDO or TLE941xy_3 connected to MI, the master receives first the Response Byte 3 of TLE941xy_3

(corresponding to Address Byte 3 and Data Byte 3) followed by the Response Byte 2 of TLE941xy_2 and

finally the Response Byte 1 of TLE941xy_1.

An example of an SPI frame with three devices from the TLE941xy family is shown in Figure 21.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

Microcontroller

MO

TLE941xy_1

SPI

TLE941xy_2

SPI

TLE941xy_3

SPI

SDO1 SDI2

SDO2 SDI3

SDO3

SDI1

MCSN

MCLK

MI

Figure 20 Example of daisy chain hardware configuration with devices from the TLE941xy family

8 CLOCK CYCLES

8 CLOCK CYLES

8 CLOCK CYCLES

8 CLOCK CYLES

8 CLOCK CYCLES

8 CLOCK CYLES

SCLK

CSN

0

LABT=0

LABT=1

ADDRESS BYTE 1

ADDRESS BYTE 2

ADDRESS BYTE 3

DATA BYTE 1

RESPONSE 1

RESPONSE 2

RESPONSE 3

DATA BYTE 2

RESPONSE1

RESPONSE2

DATA BYTE 3

RESPONSE 1

MO = SDI1

0

SDI2 = SDO1

GEF1

GLOBAL STATUS1 ADDRESS BYTE 2

ADDRESS BYTE 3

SDI3 = SDO2

MI =SDO3

OR

GEF1/2

GLOBAL STATUS2 GLOBAL STATUS 1 ADDRESS BYTE 3

GLOBAL STATUS3 GLOBAL STATUS 2 GLOBAL STATUS 1

OR

GEF1/2/3

Time

Figure 21 SPI frame with three devices of the TLE941xy family

Like in the individual slave configuration, it is possible to check if one or several TLE941xy have detected a fault

condition by reading the logic OR combination of all the Global Error Flags when CSN goes Low without any

clock cycle (Figure 22).

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SCLK

0

CSN

MO = SDI1

SDI2 = SDO1

SDI3 = SDO2

MI = SDO3

HiZ

GEF1

OR

GEF1/2

OR

GEF1/2

OR

GEF1/2/3

OR

GEF1/2/3

Time

Figure 22 Global Error Flag with zero SCLK clock cycle in daisy chain consisting only of TLE941xy

devices

Note:

Some SPI protocol errors such as the LSB of an address byte is wrongly equal to 0, may be reported

in the SPI_ERR bit of another device in the daisy chain (refer to Chapter 7.1.3 and Chapter 7.7 for

more details on SPI_ERR). In this case some devices might accept wrong data during the corrupted

SPI frame. Therefore if one of the devices in the daisy chain reports an SPI error, it is recommended

to verify the content of the registers of all devices.

7.4

Status register change during SPI communication

If a new failure occurs after the transfer of the data byte(s), i.e. between the end of the last address byte and

the CSN rising edge, this failure will be reported in the next SPI frame (see example in Figure 23).

8 CLOCK CYCLES

8 CLOCK CYLES

8 CLOCK CYCLES

8 CLOCK CYLES

SCLK

CSN

0

End of the

address byte detection

New failure

Read status byte

corresponding to the failure

SDI

ADDRESS BYTE

DATA BYTE

ADDRESS BYTE

DATA BYTE

0

SDO

Failure is NOT notified in this SPI frame

Failure notified in the new SPI frame

HiZ

GEF

GLOBAL STATUS

DATA BYTE

GLOBAL STATUS

DATA BYTE

GEF

Time

Figure 23 Status register change during transfer of data byte - Example in independent slave

configuration

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

No information is lost, even if a status register is changed during a SPI frame, in particular during a Read and

Clear command. For example:

•

the microcontroller sends a Read and Clear command to a status register

the TLE94112ES detects during the transfer the data byte(s) a new fault condition, which is normally

reported in the target status register

The incoming Clear command will be ignored, so that the microcontroller can read the new failure in the

subsequent SPI frames.

Data inconsistency between the Global Status Register (see Chapter 7.7) and the data byte (status register)

within the same SPI frame is possible if:

•

an open load or overcurrent error is detected during the transfer of the data byte

the target status register corresponds to the new detected failure

In this case the new failure:

•

is not reported in the Global Status Register of the current SPI frame but in the next one

is reported in the data byte of the current SPI frame

Refer to Figure 23.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SPI Frame 1

Overcurrent failure detected on HS of HB 1 SPI frame: Read SYS _DIAG2 (OC error of HB 1-4)

Address Byte

Data Byte

MSB

15

LSB

0

1

2

3

4

5

6

7

8

9

10

X

11

X

12

X

13

X

14

X

LABT

=1

A2

=0

A3

=0

A4

=1

A5

=1

A6

=0

OP

=0

SDI

1

X

Overcurrent failure detected on HS of HB 1 during the

transfer of the address byte

Target status register : OC error of HB 1-4

Global Status Register

LSB

Response Data Byte : SYS_DIAG2

MSB

15

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

LE

=0

SPI_

ERR

D0

=0

D1

=1

D2

=0

D3

=0

D4

=0

D5

=0

D6

=0

D7

=0

SDO

0

TPW TSD NPOR VS_OV VS_UV

HB1_HS_OC reports the new

Overcurrent failure on the HS of HB 1

Load Error bit (Overcurrent or Open Load )

does not report the new Overcurrent failure

Inconsistency between Global Status Register

and target Status Register

Time

SPI frame 2 (new)

New SPI frame: e.g. Read SYS_DIAG2 (OC error of HB1-4)

Address Byte

Data Byte

MSB

15

LSB

0

1

2

3

4

5

6

7

8

9

10

X

11

X

12

X

13

X

14

X

LABT

=1

A2

=0

A3

=0

A4

=1

A5

=1

A6

=0

OP

=0

1

X

Target status register : OC error of HB1-4

Global Status Register

Response Data Byte : SYS_DIAG2

MSB

15

LSB

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

LE

=1

SPI_

ERR

D0

=0

D1

=1

D2

=0

D3

=0

D4

=0

D5

=0

D6

=0

D7

=0

0

TPW TSD NPOR VS_OV VS_UV

Consistent information : Both Load Error bit and HB 1_HS_OC report

the Overcurrent failure detected during the previous SPI frame

Figure 24 Example of inconsistency between Global Error Flag and Status Register when a status bit is

changed during the transfer of an address byte

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7.5

SPI Bit Mapping

The SPI Registers have been mapped as shown in Figure 25 and Figure 26 respectively.

The control registers are READ/ WRITE registers. To set the control register to READ, bit 7 of the address byte

(OP bit) must be programmed to ‘0’, otherwise ‘1’ for WRITE.

The status registers are READ/CLEAR registers. To CLEAR any Status Register, bit 7 of the address byte must be

set to ‘1’, otherwise ‘0’ for READ.

15

14

13

12

11

10

9

8

7

6 5 4 3 2

1

0

8 Address Bits [A7…A0]

8 Data Bits [D7…D0]

Access

type

for Configuration & Status Information

HB_ACT_1_CTRL

HB_ACT_2_CTRL

HB_ACT_3_CTRL

HB_MODE_1_CTRL

HB_MODE_2_CTRL

HB_MODE_3_CTRL

PWM_CH_FREQ_CTRL

PWM1_DC_CTRL

PWM2_DC_CTRL

PWM3_DC_CTRL

FW_OL_CTRL

read/write 0 0 0 0 0 LABT 1

read/write 1 0 0 0 0 LABT 1

read/write 0 1 0 0 0 LABT 1

read/write 1 1 0 0 0 LABT 1

read/write 0 0 1 0 0 LABT 1

read/write 1 0 1 0 0 LABT 1

read/write 0 1 1 0 0 LABT 1

read/write 1 1 1 0 0 LABT 1

read/write 0 0 0 1 0 LABT 1

read/write 1 0 0 1 0 LABT 1

read/write 0 1 0 1 0 LABT 1

read/write 1 1 0 1 0 LABT 1

FW_CTRL

CONFIG_CTRL

read

1 1 0 0 1 LABT 1

SYS_DIAG_1 : Global status 1

SYS_DIAG_2 : OP ERROR_1_STAT

SYS_DIAG_3 : OP ERROR_2_STAT

SYS_DIAG_4 : OP ERROR_3_STAT

SYS_DIAG_5 : OP ERROR_4_STAT

SYS_DIAG_6 : OP ERROR_5_STAT

SYS_DIAG_7 : OP ERROR_6_STAT

read/clear 0 0 1 1 0 LABT 1

read/clear 1 0 1 1 0 LABT 1

read/clear 0 1 1 1 0 LABT 1

read/clear 1 1 1 1 0 LABT 1

read/clear 0 0 0 0 1 LABT 1

read/clear 1 0 0 0 1 LABT 1

read/clear 0 1 0 0 1 LABT 1

Figure 25 TLE94112ES SPI Register mapping

Note:

LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

S T E R R S E G I

C O N T R O L

S T E R R S E

S T A T

Figure 26 TLE94112ES Bit Mapping

Note:

LABT: Last Address Bit Token, refer to Chapter 7.2 and Chapter 7.3.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7.6

SPI Control Registers

The Control Registers have a READ/WRITE access (see Chapter 7.5):

•

The ‘POR’ value is defined by the register content after a POR or device Reset

The default value of all control registers is 0000 0000_B

One 16-bit SPI command consists of two bytes (see Figure 25 and Figure 26), i.e.

–

an address byte

followed by a data byte

•

The control bits are not cleared or changed automatically by the device. This must be done by the

microcontroller via SPI programming.

•

Reading a register is done byte wise by setting the SPI bit 7 to “0” (= READ ONLY).

Writing to a register is done byte wise by setting the SPI bit 7 to “1”.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7.6.1

Control register definition

HB_ACT_1_CTRL

Half-bridge output control 1 (Address Byte [OP] 000 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB4_HS_EN HB4_LS_EN HB3_HS_EN HB3_LS_EN HB2_HS_EN HB2_LS_EN HB1_HS_EN HB1_LS_EN

r

rw

Field

Bits

Type

Description

HB4_HS_EN D7

HB4_LS_EN D6

HB3_HS_EN D5

HB3_LS_EN D4

HB2_HS_EN D3

HB2_LS_EN D2

HB1_HS_EN D1

HB1_LS_EN D0

rw

Half-bridge output 4 high side switch enable

0_BHS4 OFF/ High-Z (default value)

1_BHS4 ON

Half-bridge output 4 low side switch enable

0_BLS4 OFF/ High-Z (default value)

1_BLS4 ON

Half-bridge output 3 high side switch enable

0_BHS3 OFF/ High-Z (default value)

1_BHS3 ON

Half-bridge output 3 low side switch enable

0_BLS3 OFF/ High-Z (default value)

1_BLS3 ON

Half-bridge output 2 high side switch enable

0_BHS2 OFF/ High-Z (default value)

1_BHS2 ON

Half-bridge output 2 low side switch enable

0_BLS2 OFF/ High-Z (default value)

1_BLS2 ON

Half-bridge output 1 high side switch enable

0_BHS1 OFF/ High-Z (default value)

1_BHS1 ON

Half-bridge output 1 low side switch enable

0_BLS1 OFF/ High-Z (default value)

1_BLS1 ON

Note:

The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the

digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the

logic turns off this half-bridge.

Data Sheet

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Serial Peripheral Interface (SPI)

HB_ACT_2_CTRL

Half-bridge output control 2 (Address Byte [OP]100 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB8_HS_EN HB8_LS_EN HB7_HS_EN HB7_LS_EN HB6_HS_EN HB6_LS_EN HB5_HS_EN HB5_LS_EN

r

rw

Field

Bits

Type

Description

HB8_HS_EN D7

HB8_LS_EN D6

HB7_HS_EN D5

HB7_LS_EN D4

HB6_HS_EN D3

HB6_LS_EN D2

HB5_HS_EN D1

HB5_LS_EN D0

rw

Half-bridge output 8 high side switch enable

0_BHS8 OFF/ High-Z (default value)

1_BHS8 ON

Half-bridge output 8 low side switch enable

0_BLS8 OFF/ High-Z (default value)

1_BLS8 ON

Half-bridge output 7 high side switch enable

0_BHS7 OFF/ High-Z (default value)

1_BHS7 ON

Half-bridge output 7 low side switch enable

0_BLS7 OFF/ High-Z (default value)

1_BLS7 ON

Half-bridge output 6 high side switch enable

0_BHS6 OFF/ High-Z (default value)

1_BHS6 ON

Half-bridge output 6 low side switch enable

0_BLS6 OFF/ High-Z (default value)

1_BLS6 ON

Half-bridge output 5 high side switch enable

0_BHS5 OFF/ High-Z (default value)

1_BHS5 ON

Half-bridge output 5 low side switch enable

0_BLS5 OFF/ High-Z (default value)

1_BLS5 ON

Note:

The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the

digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the

logic turns off this half-bridge.

Data Sheet

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Serial Peripheral Interface (SPI)

HB_ACT_3_CTRL

Half-bridge output control 3 (Address Byte [OP]010 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB12_HS_EN HB12_LS_EN HB11_HS_EN HB11_LS_EN HB10_HS_EN HB10_LS_EN HB9_HS_EN HB9_LS_EN

r

rw

Field

Bits

Type

Description

HB12_HS_EN D7

HB12_LS_EN D6

HB11_HS_EN D5

HB11_LS_EN D4

HB10_HS_EN D3

HB10_LS_EN D2

HB9_HS_EN D1

rw

Half-bridge output 12 high side switch enable

0_BHS12 OFF/ High-Z (default value)

1_BHS12 ON

rw

Half-bridge output 12 low side switch enable

0_BLS12 OFF/ High-Z (default value)

1_BLS12 ON

Half-bridge output 11 high side switch enable

0_BHS11 OFF/ High-Z (default value)

1_BHS11 ON

Half-bridge output 11 low side switch enable

0_BLS11 OFF/ High-Z (default value)

1_BLS11 ON

Half-bridge output 10 high side switch enable

0_BHS10 OFF/ High-Z (default value)

1_BHS10 ON

Half-bridge output 10 low side switch enable

0_BLS10 OFF/ High-Z (default value)

1_BLS10 ON

Half-bridge output 9 high side switch enable

0_BHS9 OFF/ High-Z (default value)

1_BHS9 ON

HB9_LS_EN

D0

Half-bridge output 9 low side switch enable

0_BLS9 OFF/ High-Z (default value)

1_BLS9 ON

Note:

The simultaneous activation of both HS and LS switch within a half-bridge is prevented by the

digital block to avoid cross current. If both LS_EN and HS_EN bits of a given half-bridge are set, the

logic turns off this half-bridge.

Data Sheet

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Serial Peripheral Interface (SPI)

HB_MODE_1_CTRL

Half-bridge output mode control 1 (Address Byte [OP]110 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB4_MODE1 HB4_MODE0 HB3_MODE1 HB3_MODE0 HB2_MODE1 HB2_MODE0 HB1_MODE1 HB1_MODE0

r

rw

Field

Bits

Type

Description

HB4_MODEn D7:D6

(n = 0,1)

rw

Half-bridge output 4 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB3_MODEn D5:D4

(n = 0,1)

rw

Half-bridge output 3 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB2_MODEn D3:D2

(n = 0,1)

Half-bridge output 2 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB1_MODEn D1:D0

(n = 0,1)

Half-bridge output 1 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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Serial Peripheral Interface (SPI)

HB_MODE_2_CTRL

Half-bridge output mode control 2 (Address Byte [OP]001 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB8_MODE1 HB8_MODE0 HB7_MODE1 HB7_MODE0 HB6_MODE1 HB6_MODE0 HB5_MODE1 HB5_MODE0

r

rw

Field

Bits

Type

Description

HB8_MODEn D7:D6

(n = 0,1)

rw

Half-bridge output 8 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB7_MODEn D5:D4

(n = 0,1)

rw

Half-bridge output 7 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB6_MODEn D3:D2

(n = 0,1)

Half-bridge output 6 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB5_MODEn D1:D0

(n = 0,1)

Half-bridge output 5 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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Serial Peripheral Interface (SPI)

HB_MODE_3_CTRL

Half-bridge output mode control 3 (Address Byte [OP]101 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB12_MODE1 HB12_MODE0 HB11_MODE1 HB11_MODE0 HB10_MODE1 HB10_MODE0 HB9_MODE1 HB9_MODE0

r

rw

Field

Bits

Type

Description

HB12_MODEn D7:D6

(n = 0,1)

rw

Half-bridge output 12 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB11_MODEn D5:D4

(n = 0,1)

rw

Half-bridge output 11 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB10_MODEn D3:D2

(n = 0,1)

Half-bridge output 10 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

HB9_MODEn D1:D0

(n = 0,1)

Half-bridge output 9 mode select

00_BNo PWM (default value)

01_BPWM control with PWM Channel 1

10_BPWM control with PWM Channel 2

11_BPWM control with PWM Channel 3

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

PWM_CH_FREQ_CTRL

PWM channel frequency select (Address Byte [OP]011 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

FM_CLK_

MOD1

FM_CLK_ PWM_CH3_F PWM_CH3_F PWM_CH2_F PWM_CH2_F PWM_CH1_F PWM_CH1_F

MOD0

REQ_1

REQ_0

REQ_1

REQ_0

REQ_1

REQ_0

r

rw

Field

FM_MOD_EN

Bits

D7:D6

Type

Description

FM Modulation Enable¹⁾

00_BNo modulation (default)

01_BModulation frequency 15.625kHz

10_BModulation frequency 31.25kHz

11_BModulation frequency 62.5kHz

rw

PWM_CH3_FREQ_ D5:D4

n (n=0,1)

PWM Channel 3 frequency select

00_BPWM is stopped and off (default value)

01_BPWM frequency 1 : 80Hz

10_BPWM frequency 2 : 100Hz

11_BPWM frequency 3 : 200Hz

PWM_CH2_FREQ_ D3:D2

n (n=0,1)

PWM Channel 2 frequency select

00_BPWM is stopped and off (default value)

01_BPWM frequency 1 : 80Hz

10_BPWM frequency 2 : 100Hz

11_BPWM frequency 3 : 200Hz

PWM_CH1_FREQ_ D1:D0

n (n=0,1)

PWM Channel 1 frequency select

00_BPWM is stopped and off (default value)

01_BPWM frequency 1 : 80Hz

10_BPWM frequency 2 : 100Hz

11_BPWM frequency 3 : 200Hz

1) Not subject to production test, guaranteed by design. Frequency may deviate by ±10%

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

PWM1_DC_CTRL

PWM channel 1 duty cycle configuration (Address Byte [OP]111 00[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

PWM1_DC_ PWM1_DC_ PWM1_DC_ PWM1_DC_ PWM1_DC_ PWM1_DC_ PWM1_DC_ PWM1_DC_

CTRL_7

CTRL_6

CTRL_5

CTRL_4

CTRL_3

CTRL_2

CTRL_1

CTRL_0

r

rw

Field

Bits

Type

rw

Description

PWM1_DC_CTRLn D7:D0

PWM Channel 1 Duty Cycle configuration (bit7=MSB;

bit0)

0000 0000_B100% OFF (default value)

xxxx xxxx _Bparts of 255 ON

1111 1111_B100% ON

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

PWM2_DC_CTRL

PWM channel 2 duty cycle configuration (Address [OP]000 10[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

PWM2_DC_ PWM2_DC_ PWM2_DC_ PWM2_DC_ PWM2_DC_ PWM2_DC_ PWM2_DC_ PWM2_DC_

CTRL_7

CTRL_6

CTRL_5

CTRL_4

CTRL_3

CTRL_2

CTRL_1

CTRL_0

r

rw

Field

Bits

Type

rw

Description

PWM2_DC_CTRLn D7:D0

PWM Channel 2 Duty Cycle configuration (bit7=MSB;

bit0)

0000 0000_B100% OFF (default value)

xxxx xxxx _Bparts of 255 ON

1111 1111_B100% ON

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

PWM3_DC_CTRL

PWM channel 3 duty cycle configuration (Address Byte [OP]100 10[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

PWM3_DC_ PWM3_DC_ PWM3_DC_ PWM3_DC_ PWM3_DC_ PWM3_DC_ PWM3_DC_ PWM3_DC_

CTRL_7

CTRL_6

CTRL_5

CTRL_4

CTRL_3

CTRL_2

CTRL_1

CTRL_0

r

rw

Field

Bits

Type

rw

Description

PWM3_DC_CTRLn D7:D0

PWM Channel 3 Duty Cycle configuration (bit7=MSB;

bit0)

0000 0000_B100% OFF (default value)

xxxx xxxx _Bparts of 255 ON

1111 1111_B100% ON

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

FW_OL_CTRL

Free-wheeling configuration and Open load detection setting of HS1 and HS2 (Address Byte [OP]010

10[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

FW_HB6

FW_HB5

FW_HB4

FW_HB3

FW_HB2

FW_HB1

OL_SEL_HS2 OL_SEL_HS1

r

rw

Field

Bits

Type

Description

HB6 free-wheeling configuration

FW_HB6

D7

rw

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

FW_HB5

D6

D5

D4

D3

D2

D1

D0

HB5 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

FW_HB4

HB4 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

FW_HB3

HB3 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

FW_HB2

HB2 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

FW_HB1

HB1 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

OL_SEL_HS2

OL_SEL_HS1

HS2 open load detection current and filter time select

0_BHigh-current mode (default value)

1_BLED Mode (Low current mode)

HS1 open load detection current and filter time select

0_BHigh current mode (default value)

1_BLED Mode (Low current mode)

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

FW_CTRL

Free-wheeling configuration (Address Byte [OP]110 10[LABT]1)_B

D7

D6

D5

D4

D3

D2

D1

D0

reserved

FW_HB12

FW_HB11

FW_HB10

FW_HB9

FW_HB8

FW_HB7

r

rw

Field

Bits

Type

Description

To be programmed as ‘0’.

HB12 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

reserved

FW_HB12

D7:D6

rw

D5

D4

D3

D2

D1

D0

FW_HB11

FW_HB10

FW_HB9

FW_HB8

FW_HB7

rw

HB11 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

HB10 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

HB9 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

HB8 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

HB7 free-wheeling configuration

0_BPassive free-wheeling (default value)

1_BActive free-wheeling

Note:

Refer to Chapter 6.1.1 for more information on PWM operation

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

CONFIG_CTRL

Device Configuration control (Address Byte [OP]110 01[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

reserved

DEV_ID2

DEV_ID1

DEV_ID0

r

Field

Bits

Type

Description

Always reads as ‘0’

Device/ derivative identifier

reserved

DEV_IDn

D7:D3

D2:D0

r

Note:

These bits can be used to verify the silicon

content of the device

000_BTLE94112EL/ES chip

001_BTLE94110EL/ES chip

010_BTLE94108EL/ES chip

011_BTLE94106EL/ES chip

100_BTLE94104EP chip

101_BTLE94103EP chip

110_Breserved

111_Breserved

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7.7

SPI Status Registers

The Control Registers have a READ/CLEAR access (see also Chapter 7.5):

•

The ‘POR Value’ of the Status registers (content after a POR or device Reset) and is 0000 0000_B.

One 16-bit SPI command consists of two bytes (see Figure 25 and Figure 26), i.e.

–

an address byte

followed by a data byte

•

Reading a register is done byte wise by setting the SPI bit 7 of the address byte to “0” (= Read Only).

Clearing a register is done byte wise by setting the SPI bit 7 of the address byte to “1”.

SPI status registers are not cleared automatically by the device. This must be done by the microcontroller

via SPI command.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

7.7.1

Status register definition

SYS_DIAG1

Global status 1 (Address Byte [OP]001 10[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

SPI_ERR

LE

VS_UV

VS_OV

NPOR

TSD

TPW

reserved

r

rc

r

rc

r

Field

Bits

Type

Description

SPI_ERR

D7

rc

SPI error detection

0_BNo SPI protocol error is detected (default value).

1_BAn SPI protocol error is detected.

LE

D6

r

Load error detection (logic OR combination of Open Load and

Overcurrent)

0_BNo Open Load and no Overcurrent detected (default value)

1_BOpen Load or Overcurrent detected in at least one of the

power outputs. Error latched. Faulty output is latched off in

case of Overcurrent

VS_UV

VS_OV

D5

D4

rc

VS Undervoltage error detection

0_BNo undervoltage on V_Sdetected (default value)

1_BUndervoltage on V_Sdetected. Error latched and all outputs

disabled.

VS Overvoltage error detection

0_BNo overvoltage on V_Sdetected (default value)

1_BOvervoltage on V_Sdetected. Error latched and all outputs

disabled.

NPOR

TSD

D3

D2

rc

Not Power On Reset (NPOR) detection

0_BPOR on EN or VDD supply rail (default value)

1_BNo POR

Temperature shutdown error detection

0_BJunction temperature below temperature shutdown

threshold (default value)

1_BJunction temperature has reached temperature shutdown

threshold. Error latched and all outputs disabled.

TPW

D1

rc

Temperature pre-warning error detection

0_BJunction temperature below temperature pre-warning

threshold (default value)

1_BJunction temperature has reached temperature pre-warning

threshold.

reserved

D0

r

Bit reserved. Always reads ‘0’.

Note:

The LE bit in the Global Status register is read only. It reflects an OR combination of the respective

open load and overcurrent errors of the half-bridge channels. If all OC/ OL bits of the respective high-

side and low-side channels are cleared to ‘0’, the LE bit will be automatically updated to ‘0’.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SYS_DIAG_2 : OP_ERROR_1_STAT

Overcurrent error status of half-bridge outputs 1 - 4 (Address Byte [OP]101 10[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB4_HS_OC HB4_LS_OC HB3_HS_OC HB3_LS_OC HB2_HS_OC HB2_LS_OC HB1_HS_OC HB1_LS_OC

r

rc

Field

Bits

Type

Description

HB4_HS_OC D7

HB4_LS_OC D6

HB3_HS_OC D5

HB3_LS_OC D4

HB2_HS_OC D3

HB2_LS_OC D2

HB1_HS_OC D1

HB1_LS_OC D0

rc

High-side (HS) switch of half-bridge 4 overcurrent detection

0_BNo error on HS4 switch (default value)

1_BOvercurrent detected on HS4 switch. Error latched and HS4

disabled.

Low-side (LS) switch of half-bridge 4 overcurrent detection

0_BNo error on LS4 switch (default value)

1_BOvercurrent detected on LS4 switch. Error latched and LS4

disabled.

High-side (HS) switch of half-bridge 3 overcurrent detection

0_BNo error on HS3 switch (default value)

1_BOvercurrent detected on HS3 switch. Error latched and HS3

disabled.

Low-side (LS) switch of half-bridge 3 overcurrent detection

0_BNo error on LS3 switch (default value)

1_BOvercurrent detected on LS3 switch. Error latched and LS3

disabled.

High-side (HS) switch of half-bridge 2 overcurrent detection

0_BNo error on HS2 switch (default value)

1_BOvercurrent detected on HS2 switch. Error latched and HS2

disabled.

Low-side (LS) switch of half-bridge 2 overcurrent detection

0_BNo error on LS2 switch (default value)

1_BOvercurrent detected on LS2 switch. Error latched and LS2

disabled.

High-side (HS) switch of half-bridge 1 overcurrent detection

0_BNo error on HS1 switch (default value)

1_BOvercurrent detected on HS1 switch. Error latched and HS1

disabled.

Low-side (LS) switch of half-bridge 1 overcurrent detection

0_BNo error on LS1 switch (default value)

1_BOvercurrent detected on LS1 switch. Error latched and LS1

disabled.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SYS_DIAG_3 : OP_ERROR_2_STAT

Overcurrent error status of half-bridge outputs 5 - 8 (Address Byte [OP]011 10[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB8_HS_OC HB8_LS_OC HB7_HS_OC HB7_LS_OC HB6_HS_OC HB6_LS_OC HB5_HS_OC HB5_LS_OC

r

rc

Field

Bits

Type

Description

HB8_HS_OC D7

HB8_LS_OC D6

HB7_HS_OC D5

HB7_LS_OC D4

HB6_HS_OC D3

HB6_LS_OC D2

HB5_HS_OC D1

HB5_LS_OC D0

rc

High-side (HS) switch of half-bridge 8 overcurrent detection

0_BNo error on HS8 switch (default value)

1_BOvercurrent detected on HS8 switch. Error latched and HS8

disabled.

Low-side (LS) switch of half-bridge 8 overcurrent detection

0_BNo error on LS8 switch (default value)

1_BOvercurrent detected on LS8 switch. Error latched and LS8

disabled.

High-side (HS) switch of half-bridge 7 overcurrent detection

0_BNo error on HS7 switch (default value)

1_BOvercurrent detected on HS7 switch. Error latched and HS7

disabled.

Low-side (LS) switch of half-bridge 7 overcurrent detection

0_BNo error on LS7 switch (default value)

1_BOvercurrent detected on LS7 switch. Error latched and LS7

disabled.

High-side (HS) switch of half-bridge 6 overcurrent detection

0_BNo error on HS6 switch (default value)

1_BOvercurrent detected on HS6 switch. Error latched and HS6

disabled.

Low-side (LS) switch of half-bridge 6 overcurrent detection

0_BNo error on LS6 switch (default value)

1_BOvercurrent detected on LS6 switch. Error latched and LS6

disabled.

High-side (HS) switch of half-bridge 5 overcurrent detection

0_BNo error on HS5 switch (default value)

1_BOvercurrent detected on HS5 switch. Error latched and HS5

disabled.

Low-side (LS) switch of half-bridge 5 overcurrent detection

0_BNo error on LS5 switch (default value)

1_BOvercurrent detected on LS5 switch. Error latched and LS5

disabled.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SYS_DIAG_4 : OP_ERROR_3_STAT

Overcurrent error status of half-bridge outputs 9 - 12(Address Byte [OP]111 10[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB12_HS_OC HB12_LS_OC HB11_HS_OC HB11_LS_OC HB10_HS_OC HB10_LS_OC HB9_HS_OC HB9_LS_OC

r

rc

Field

Bits

Type

Description

HB12_HS_OC D7

HB12_LS_OC D6

HB11_HS_OC D5

HB11_LS_OC D4

HB10_HS_OC D3

HB10_LS_OC D2

HB9_HS_OC D1

rc

High-side (HS) switch of half-bridge 12 overcurrent detection

0_BNo error on HS12 switch (default value)

1_BOvercurrent detected on HS12 switch. Error latched and

HS12 disabled.

rc

Low-side (LS) switch of half-bridge 12 overcurrent detection

0_BNo error on LS12 switch (default value)

1_BOvercurrent detected on LS12 switch. Error latched and

LS12 disabled.

High-side (HS) switch of half-bridge 11 overcurrent detection

0_BNo error on HS11 switch (default value)

1_BOvercurrent detected on HS11 switch. Error latched and

HS11 disabled.

Low-side (LS) switch of half-bridge 11 overcurrent detection

0_BNo error on LS11 switch (default value)

1_BOvercurrent detected on LS11 switch. Error latched and

LS11 disabled.

High-side (HS) switch of half-bridge 10 overcurrent detection

0_BNo error on HS10 switch (default value)

1_BOvercurrent detected on HS10 switch. Error latched and

HS10 disabled.

Low-side (LS) switch of half-bridge 10 overcurrent detection

0_BNo error on LS10 switch (default value)

1_BOvercurrent detected on LS10 switch. Error latched and

LS10 disabled.

High-side (HS) switch of half-bridge 9 overcurrent detection

0_BNo error on HS9 switch (default value)

1_BOvercurrent detected on HS9 switch. Error latched and HS9

disabled.

HB9_LS_OC

D0

Low-side (LS) switch of half-bridge 9 overcurrent detection

0_BNo error on LS9 switch (default value)

1_BOvercurrent detected on LS9 switch. Error latched and LS9

disabled.

Note:

Unused or not connected outputs for lower derivatives, i.e. TLE94110ES, TLE94108ES and

TLE94106ES will be defined as ‘reserved’, always reads as ‘0’

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SYS_DIAG_5 : OP_ERROR_4_STAT

Open load error status of half-bridge outputs 1 - 4 (Address Byte [OP]000 01[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB4_HS_OL HB4_LS_OL HB3_HS_OL HB3_LS_OL HB2_HS_OL HB2_LS_OL HB1_HS_OL HB1_LS_OL

r

rc

Field

Bits

Type

Description

HB4_HS_OL D7

HB4_LS_OL D6

HB3_HS_OL D5

HB3_LS_OL D4

HB2_HS_OL D3

HB2_LS_OL D2

HB1_HS_OL D1

HB1_LS_OL D0

rc

High-side (HS) switch of half-bridge 4 open load detection

0_BNo error on HS4 switch (default value)

1_BOpen load detected on HS4 switch. Error latched.

Low-side (LS) switch of half-bridge 4 open load detection

0_BNo error on LS4 switch (default value)

1_BOpen load detected on LS4 switch. Error latched.

High-side (HS) switch of half-bridge 3 open load detection

0_BNo error on HS3 switch (default value)

1_BOpen load detected on HS3 switch. Error latched.

Low-side (LS) switch of half-bridge 3 open load detection

0_BNo error on LS3 switch (default value)

1_BOpen load detected on LS3 switch. Error latched.

High-side (HS) switch of half-bridge 2 open load detection

0_BNo error on HS2 switch (default value)

1_BOpen load detected on HS2 switch. Error latched.

Low-side (LS) switch of half-bridge 2 open load detection

0_BNo error on LS2 switch (default value)

1_BOpen load detected on LS2 switch. Error latched.

High-side (HS) switch of half-bridge 1 open load detection

0_BNo error on HS1 switch (default value)

1_BOpen load detected on HS1 switch. Error latched.

Low-side (LS) switch of half-bridge 1 open load detection

0_BNo error on LS1 switch (default value)

1_BOpen load detected on LS1 switch. Error latched.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SYS_DIAG_6 : OP_ERROR_5_STAT

Open load error status of half-bridge outputs 5 - 8 (Address Byte [OP]100 01[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB8_HS_OL HB8_LS_OL HB7_HS_OL HB7_LS_OL HB6_HS_OL HB6_LS_OL HB5_HS_OL HB5_LS_OL

r

rc

Field

Bits

Type

Description

HB8_HS_OL D7

HB8_LS_OL D6

HB7_HS_OL D5

HB7_LS_OL D4

HB6_HS_OL D3

HB6_LS_OL D2

HB5_HS_OL D1

HB5_LS_OL D0

rc

High-side (HS) switch of half-bridge 8 open load detection

0_BNo error on HS8 switch (default value)

1_BOpen load detected on HS8 switch. Error latched.

Low-side (LS) switch of half-bridge 8 open load detection

0_BNo error on LS8 switch (default value)

1_BOpen load detected on LS8 switch. Error latched.

High-side (HS) switch of half-bridge 7 open load detection

0_BNo error on HS7 switch (default value)

1_BOpen load detected on HS7 switch. Error latched.

Low-side (LS) switch of half-bridge 7 open load detection

0_BNo error on LS7 switch (default value)

1_BOpen load detected on LS7 switch. Error latched.

High-side (HS) switch of half-bridge 6 open load detection

0_BNo error on HS6 switch (default value)

1_BOpen load detected on HS6 switch. Error latched.

Low-side (LS) switch of half-bridge 6 open load detection

0_BNo error on LS6 switch (default value)

1_BOpen load detected on LS6 switch. Error latched.

High-side (HS) switch of half-bridge 5 open load detection

0_BNo error on HS5 switch (default value)

1_BOpen load detected on HS5 switch. Error latched.

Low-side (LS) switch of half-bridge 5 open load detection

0_BNo error on LS5 switch (default value)

1_BOpen load detected on LS5 switch. Error latched.

Data Sheet

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TLE94112ES

Serial Peripheral Interface (SPI)

SYS_DIAG_7 : OP_ERROR_6_STAT

Open load error status of half-bridge outputs 9 - 12 (Address Byte [OP]010 01[LABT]1_B)

D7

D6

D5

D4

D3

D2

D1

D0

HB12_HS_OL HB12_LS_OL HB11_HS_OL HB11_LS_OL HB10_HS_OL HB10_LS_OL HB9_HS_OL HB9_LS_OL

r

rc

Field

Bits

Type

Description

HB12_HS_OL D7

HB12_LS_OL D6

HB11_HS_OL D5

HB11_LS_OL D4

HB10_HS_OL D3

HB10_LS_OL D2

HB9_HS_OL D1

HB9_LS_OL D0

rc

High-side (HS) switch of half-bridge 12 open load detection

0_BNo error on HS12 switch (default value)

1_BOpen load detected on HS12 switch. Error latched.

rc

Low-side (LS) switch of half-bridge 12 open load detection

0_BNo error on LS12 switch (default value)

1_BOpen load detected on LS12 switch. Error latched.

High-side (HS) switch of half-bridge 11 open load detection

0_BNo error on HS11 switch (default value)

1_BOpen load detected on HS11 switch. Error latched.

Low-side (LS) switch of half-bridge 11 open load detection

0_BNo error on LS11 switch (default value)

1_BOpen load detected on LS11 switch. Error latched.

High-side (HS) switch of half-bridge 10 open load detection

0_BNo error on HS10 switch (default value)

1_BOpen load detected on HS10 switch. Error latched.

Low-side (LS) switch of half-bridge 10 open load detection

0_BNo error on LS10 switch (default value)

1_BOpen load detected on LS10 switch. Error latched.

High-side (HS) switch of half-bridge 9 open load detection

0_BNo error on HS9 switch (default value)

1_BOpen load detected on HS9 switch. Error latched.

Low-side (LS) switch of half-bridge 9 open load detection

0_BNo error on LS9 switch (default value)

1_BOpen load detected on LS9 switch. Error latched.

Data Sheet

72

1.0

2020-09-29

TLE94112ES

Application Information

8

Application Information

Note:

The following simplified application examples are given as a hint for the implementation of the

device only and shall not be regarded as a description or warranty of a certain functionality,

condition or quality of the device. The function of the described circuits must be verified in the real

application.

8.1

Application Diagram

V_S

VBAT

6 motors in

non-cascaded

configuration

+ 5 motors in

cascaded

configuration

3 high-current

motors in

parallel drive

VBAT

10µF

100nF

S₁

V_S

VCC1

VDD

VS2

VS1

OUT 1

WK

10kΩ

M1

M2

M3

µC

TLE9263

TLE94112ES

22nF,

50V

1kΩ

EN

OUT 2

M7

M8

M9

SDO

SDI

M1

OUT 3

10µF

SDO

SDI

/CS

VCC2

OUT 4

OUT 5

VCCHSCAN

SCLK

INT

CAN-H

SPLIT

CAN-L

CANH

CANL

CSN

60Ω

47nF

VDD

SCLK

10kΩ

OUT 6

OUT 7

60Ω

RO

M2

M4

M5

M6

Series resistors are

recommended if the VS1/2 of

the TLE94112ES are

protected by an active

reverse polarity protection

OUT 8

OUT 9

M10

M11

Landing pads for ceramic

capacitors at OUTx

OUT 10

OUT 11

M3

OUT 12

GND

GND GND GND GND

Figure 27 Application example for DC-motor loads

Data Sheet

73

1.0

2020-09-29

TLE94112ES

Application Information

V_S

VBAT

Reverse battery

protection

VBAT

100nF

VDDP

VDD

VS2

VS1

V_S

OUT 1

Embedded

TLE94112ES

Power IC

OUT 2

EN

TLE984x

LIN

OUT 3

x-adjustment

y-adjustment

M

SDO

SDI

CSN

OUT 4

SCLK

OUT 5

OUT 6

OUT 7

OUT 8

M

Mirror fold

Current < 3.6A

M

GND

OUT 9

OUT 10

OUT 11

OUT 12

VBAT

Series resistors are

recommended if the VS1/2 of

the TLE94112ES are

PROFET^TM

protected by an active

reverse polarity protection

GND GND GND GND

Landing pads for ceramic

capacitors at OUTx

Figure 28 Application example for side mirror control

Notes on the application example

1. Series resistors between the microcontroller and the signal pins of the TLE94112ES are recommended if an

active reverse polarity protection (MOSFET) is used to protect VS1 and VS2 pins. These resistors limit the

current between the microcontroller and the device during negative transients on VBAT (e.g. ISO/TR 7637

pulse 1)

2. Landing pads for ceramic capacitors at the outputs of the TLE94112ES as close as possible to the connectors

are recommended (the ceramic capacitors are not populated if unused). These ceramic capacitors can be

mounted if a higher performance in term of ESD capability is required.

3. The electrolytic capacitor at the VSx pins should be dimensioned in order to prevent the VS voltage from

exceeding the absolute maximum rating. PWM operation with a too low capacitance can lead to a VS voltage

overshoot, which results in a VS overvoltage detection.

Data Sheet

74

1.0

2020-09-29

TLE94112ES

Application Information

4. Unused outputs are recommended to be left unconnected (open) in the application. If unused output pins are

routed to an external connector which leaves the PCB, then these outputs should have provision for a zero

ohm jumper (depopulated if unused) or ESD protection. In other words, unused pins should be treated like

used pins.

5. Place bypass ceramic capacitors as close as possible to the VSx pins, with shortest connections the GND pins

and GND layer, for best EMC performance

Data Sheet

75

1.0

2020-09-29

TLE94112ES

Application Information

8.2

Thermal application information

Ta = 85°C, Ch1 to Ch12 are dissipating a total of 1.62W (0.135W each).

Zth-ja forTLE94112ES

90

80

70

60

50

40

30

20

10

0

1s0p / 600 mm² / +85 °C

1s0p / 300 mm² / +85 °C

1s0p/ footprint / +85 °C

2s2p / +85 °C

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

time [sec]

Figure 29 ZthJA Curve for different PCB setups

Zth-jc forTLE94112ES

2

1.8

1.6

1.4

1.2

1

Tamb = +85 °C

0.8

0.6

0.4

0.2

0

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

time [sec]

Figure 30 ZthJC Curve

Data Sheet

76

1.0

2020-09-29

TLE94112ES

Application Information

8.3

EMC Enhancement

In the event the emissions of the device exceed the allowable limits, a modulation of the oscillator frequency

is incorporated to reduce eventual harmonics of the 8MHz base clock. The frequencies can be selected based

on the resolution bandwidth of the peak detector during EMC testing.

The selection is achieved by setting the FM_CLK_MODn bits in the PWM_CH_FREQ_CTRL register as follows:

00_B: OFF

01_B: FM CLK=15.625 kHZ

10_B: FM CLK=31.25 kHz

11_B: FM CLK=62.5 kHz

Data Sheet

77

1.0

2020-09-29

TLE94112ES

Package Outlines

9

Package Outlines

Figure 31 PG-TSDSO-24 (Plastic/Plastic Green - Dual Small Outline Package)

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e lead-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

78

1.0

2020-09-29

TLE94112ES

Revision History

10

Revision History

Revision Date

Changes

1.0

2020-09-29 Initial release

Data Sheet

79

1.0

2020-09-29

Please read the Important Notice and Warnings at the end of this document

Trademarks of Infineon Technologies AG

µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,

DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,

HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,

OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,

SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.

Trademarks updated November 2015

Other Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2020-09-29

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.


型号：	TLE94112ES
厂家：	Infineon
描述：	It is part of a larger family offering half-bridge drivers from three outputs to twelve outputs with direct interface or SPI interface. The half bridge drivers are designed to drive DC motor loads in sequential or parallel operation. Operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a 16-bit SPI interface. It offers diagnosis features such as short circuit, open load, power supply failure and overtemperature detection. In combination with its low quiescent current, this device is attractive among others for automotive applications. The small fine pitch exposed pad package, PG-TSDSO-24, provides good thermal performance and reduces PCB-board space and costs. PC
文件：	总80页 (文件大小：2137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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