TLE9844QX [INFINEON]
TLE9844QX includes an Arm® Cortex® M0 and integrated high-side and low-side switches;
| 型号： | TLE9844QX |
| 厂家： | 
Infineon |
| 描述： | TLE9844QX includes an Arm® Cortex® M0 and integrated high-side and low-side switches |
| 文件： | 总128页 (文件大小：3290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE9844QX
Microcontroller with LIN and Power Switches for
Automotive Applications
1
Overview
Features
•
32-bit Arm® Cortex®*-M0 Core
–
–
–
up to 25 MHz clock frequency
one clock per machine cycle architecture
single cycle multiplier
VQFN-48-31
•
On-chip memory
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–
–
–
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64 KB Flash (including EEPROM)
4 KB EEPROM (emulated in Flash)
768 bytes 100 Time Programmable Memory (100TP)
4 KB RAM
Boot ROM for startup firmware and Flash routines
•
•
•
On-chip OSC
2 Low-Side Switches incl. PWM functionality, can be used e.g. as relay driver
1 High-Side Switch with cyclic sense option and PWM functionality, e.g. for supplying LEDs or switch panels
(min. 150 mA)
•
•
•
•
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4 High Voltage Monitor Input pins for wake-up and with cyclic sense with analog measurement option
10 General-purpose I/O Ports (GPIO)
6 Analog input Ports
10-Bit A/D Converter with 6 analog inputs + VBAT_SENSE + VS + 4 high voltage monitoring inputs
8-Bit A/D Converter with 7 inputs for voltage and temperature supervision
Measurement unit with 12 channels together with the onboard 10-Bit A/D converter and data post
processing
•
•
16-Bit timers - GPT12, Timer 2 and Timer 21
Capture/compare unit for PWM signal generation (CCU6)
*
Arm and Cortex are registered trademarks of Arm Limited, UK
Type
Package
Marking
TLE9844QX
VQFN-48-31
TLE9844QX
Datasheet
www.infineon.com
1
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Overview
•
•
•
•
•
•
•
•
•
•
•
2 full duplex serial interfaces (UART1, UART2), UART1 with LIN support
2 synchronous serial channels (SSC1, SSC2)
On-chip debug support via 2-wire SWD
LIN Bootstrap loader to program the Flash via LIN (LIN BSL)
1 LIN 2.2 transceiver
Single power supply from 3.0 V to 28 V
Low-dropout voltage regulators (LDO)
5 V voltage supply VDDEXT for external loads (e.g. Hall-sensor)
Core logic supply at 1.5 V
Programmable window watchdog (WDT1) with independent on-chip clock source
Power saving modes:
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–
–
–
Micro Controller Unit slow-down mode
Sleep Mode with cyclic sense option
Cyclic wake-up during Sleep Mode
Stop Mode with cyclic sense option
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•
•
•
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Power-on and undervoltage/brownout reset generator
Overtemperature protection
Short circuit protection for all voltage regulators and actuators (High Side, Low Side)
Loss of clock detection with fail safe mode for power switches
Temperature Range TJ: -40°C up to 150°C
Package VQFN-48-31 with LTI feature
Green package (RoHS compliant)
AEC Qualified
Datasheet
2
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Table of Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
Device Pinout and Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PMU Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Supply Generation (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-on Reset Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
6.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.3.2.1
6.3.2.2
6.3.3
System Control Unit - Digital Modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External Input Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External Crystal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
System Control Unit - Power Modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Description of the Power Modules System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
7.2
7.2.1
8
Arm® Cortex®-M0 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1
8.2
8.2.1
9
Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.1
10.2
10.2.1
11
11.1
11.1.1
NVM Module (Flash Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Datasheet
3
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
12
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1
12.2
12.2.1
13
13.1
13.2
Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14
14.1
14.2
GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TLE9844QX Port Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.2.1
14.2.2
14.3
14.3.1
14.3.1.1
14.3.2
14.3.2.1
14.3.3
14.3.3.1
15
15.1
General Purpose Timer Units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Features Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Features Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Block Diagram GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Block Diagram GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
15.1.1
15.1.2
15.2
15.2.1
15.2.2
16
Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Timer2 and Timer21 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
16.1
16.2
16.2.1
17
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
17.1
17.2
17.2.1
18
UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
18.1
18.2
18.2.1
18.3
19
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
19.1
19.2
19.2.1
20
High-Speed Synchronous Serial Interface SSC1/SSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
20.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Datasheet
4
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
20.2
20.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
21
Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
21.1
21.2
21.2.1
22
Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
22.1
22.2
22.2.1
23
10-Bit Analog Digital Converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
23.1
23.2
23.2.1
24
High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
24.1
24.2
24.2.1
25
High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
25.1
25.2
25.2.1
25.2.2
26
26.1
26.2
Low-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
27
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Relay Window Lift Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Connection of N.C. / N.U. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Connection of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Connection of P0.2 for SWD debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Connection of TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ESD Immunity According to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
27.1
27.2
27.3
27.4
27.5
27.6
28
28.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PMU Input Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PMU I/O Supply Parameters VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PMU Core Supply Parameters VDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VDDEXT Voltage Regulator 5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
28.1.1
28.1.2
28.1.3
28.1.4
28.1.5
28.2
28.2.1
28.2.2
28.2.3
28.2.4
Datasheet
5
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
28.2.5
28.2.5.1
28.2.6
28.3
28.3.1
28.3.2
28.4
VPRE Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Load Sharing of VPRE Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Power Down Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Electrical Characteristics Oscillators and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
External Clock Parameters XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Description of Keep and Force Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DC Parameters Port 0, Port 1, TMS, Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
DC Parameters Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Central Temperature Sensor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ADC1 Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Electrical Characteristics ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
High-Voltage Monitoring Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
High Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Low Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
28.4.1
28.5
28.5.1
28.5.2
28.5.3
28.5.4
28.6
28.6.1
28.7
28.7.1
28.8
28.8.1
28.8.2
28.8.2.1
28.9
28.9.1
28.9.2
28.10
28.10.1
28.11
28.11.1
28.12
28.12.1
29
30
31
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Datasheet
6
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Block Diagram
2
Block Diagram
TMS
P0.0
TEST / DEBUG
INTERFACE
ARM
CORTEX-M0
FLASH
slave
SRAM
slave
ROM
slave
systembus
Multilayer AHB Matrix
slave
PBA0
slave
PBA1
P2.x (ANx)
VBAT_SENSE
ADC10B
DPP1
P0.x
P1.x
P2.x
UART1
GPIO
LIN
CCU6
UART2
LS1
LS2
LS1
LIN
GNDLIN
SSC1
SSC2
GNDLS
GPT12
MU:
LS2
ADC8B
DPP2
T2
VS
T21
PMU –
Power
Management
Unit
RESET
VDDEXT
VDDP
VDDC
HS1
HS1
PLL
SCU_DM
WDT1
1- 4 MON
MON 1...4
SCU_PM
Figure 1
Block Diagram, TLE9844QX
Datasheet
7
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Device Pinout and Pin Configuration
3
Device Pinout and Pin Configuration
3.1
Device Pinout
P2.1 37
N.C. 38
P2.0 39
24 P0.4
23 P0.3
22 P0.2
21 RESET
20 P0.0/ SWD_CLK
19 GNDP
18 TMS /SWD_IO
17 P0.1
N.C. 40
N.C. 41
VDDC 42
GNDA 43
VDDP 44
VDDEXT 45
16 P1.2
N.C. 46
15 P1.1
VS 47
14 P1.0
VBAT _SENSE 48
13 GNDLS
Figure 2
Device Pinout, TLE9844QX
Datasheet
8
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Device Pinout and Pin Configuration
3.2
Pin Configuration
After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings:
•
•
•
•
Pull-up enabled only (PU)
Pull-down enabled only (PD)
Input with both pull-up and pull-down disabled (I)
Output with output stage deactivated = high impedance state (Hi-Z)
The functions and default states of the TLE9844QX external pins are provided in the following table.
Type: indicates the pin type.
•
•
•
•
I/O: Input or output
I: Input only
O: Output only
P: Power supply
Not all alternate functions listed, see Chapter 14.
Table 1
Symbol
Pin Definitions and Functions
Pin Number Type Reset Function
State
P0
Port 0
Port 0 is an 6-Bit bidirectional general purpose I/O port.
Alternate functions can be assigned and are listed in the Port
description. Main function is listed below.
P0.0
20
I/O
I/PU
SWD_CLK
GPIO
Serial Wire Debug Clock
General Purpose IO
Alternate function mapping see Table 7
P0.1
P0.2
P0.3
P0.4
P0.5
P1
17
22
23
24
25
I/O
I/O
I/O
I/O
I/O
I/PU
I/PD
I/PU
I/PU
I/PU
GPIO
GPIO
GPIO
GPIO
GPIO
Port 1
General Purpose IO
Alternate function mapping see Table 7
General Purpose IO
Alternate function mapping see Table 7
General Purpose IO
Alternate function mapping see Table 7
General Purpose IO
Alternate function mapping see Table 7
General Purpose IO
Alternate function mapping see Table 7
Port 1 is an 4-Bit bidirectional general purpose I/O port.
Alternate functions can be assigned and are listed in the Port
description. Main function is listed below.
P1.0
P1.1
P1.2
14
15
16
I/O
I/O
I/O
I
I
I
GPIO
GPIO
GPIO
General Purpose IO
Alternate function mapping see Table 8
General Purpose IO
Alternate function mapping see Table 8
General Purpose IO
Alternate function mapping see Table 8
Datasheet
9
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Device Pinout and Pin Configuration
Table 1
Symbol
Pin Definitions and Functions (cont’d)
Pin Number Type Reset Function
State
P1.4
26
I/O
I
GPIO
General Purpose IO
Alternate function mapping see Table 8
P2
Port 2
Port 2 is an 8-Bit general purpose input-only port.
Alternate functions can be assigned and are listed in the Port
description. Main function is listed below.
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
39
37
33
36
32
31
34
35
I
I
I
I
I
I
I
I
I
I
AN0
AN1
AN2
AN3
ADC1 analog input channel 12
Alternate function mapping see Table 9
ADC1 analog input channel 7
Alternate function mapping see Table 9
ADC1 analog input channel 8
Alternate function mapping see Table 9
ADC1 analog input channel 9
Alternate function mapping see Table 9
Alternate function mapping see Table 9
External oscillator input
XTAL11)
I
O
I
Alternate function mapping see Table 9
External oscillator output
Hi-Z
XTAL21)
AN6
I
I
I
I
ADC1 analog input channel 10
Alternate function mapping see Table 9
AN7
ADC1 analog input channel 11
Alternate function mapping see Table 9
Power Supply
VS
47
44
P
P
–
–
Battery supply input
VDDP
I/O port supply (5.0 V). Do not connect external loads. For
buffer and bypass capacitors
VDDC
42
P
–
Core supply (1.5 V during Active Mode,
reduced voltage during Stop Mode). Do not connect external
loads. For buffer/bypass capacitor
VDDEXT
GNDLS
GNDP
45
P
P
P
P
P
–
–
–
–
–
External voltage supply output (5.0 V, 20 mA)
Low-side ground LS1, LS2
Core supply ground
13
19, 30
43
GNDA
Analog supply ground
GNDLIN
Monitor Inputs
MON1
2
LIN ground
5
6
7
8
I
I
I
I
I
I
I
I
High Voltage Monitor Input 1
High Voltage Monitor Input 2
High Voltage Monitor Input 3
High Voltage Monitor Input 4
MON2
MON3
MON4
High-Side Switch / Low-Side Switch Outputs
Datasheet
10
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Device Pinout and Pin Configuration
Table 1
Symbol
Pin Definitions and Functions (cont’d)
Pin Number Type Reset Function
State
LS1
11
12
3
O
O
O
Hi-Z
Hi-Z
Hi-Z
Low-Side switch output 1
Low-Side Switch output 2
High-Side Switch output 1
LS2
HS1
LIN Interface
LIN
1
I/O
I
PU
LIN bus interface input/output
Others
TMS
18
21
I/PD
TMS
SWD_IO
Test mode select input
Serial Wire Debug input/output
RESET
I/O
I
I/O/PU Reset input/output, not available during Sleep Mode
VBAT_SENSE 48
I
Battery supply voltage sense input
N.C.
10, 27, 28, 29, –
–
Not connected, can be connected to GND
38, 40, 41, 46
N.U.
EP
4, 9
–
–
–
–
–
Not Used; see Chapter 27.2
Exposed Pad, connect to GND
1) configurable by user
Datasheet
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Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Modes of Operation
4
Modes of Operation
This highly integrated circuit contains analog and digital functional blocks. For system and interface control
an embedded 32-Bit Cortex®-M0 microcontroller is included. For internal and external power supply purposes,
on-chip low drop-out regulators are existent. An internal oscillator (no external components necessary)
provides a cost effective and suitable clock in particular for LIN slave nodes. As communication interface, a LIN
transceiver and several High Voltage Monitor Inputs with adjustable threshold and filters are available.
Furthermore oneHigh-Sides Switche (e.g. for driving LEDs or powering of switches), two low-side switches
(e.g. for relays) and several general purpose input/outputs (GPIO) with pulse-width modulation (PWM)
capabilities are available.
The Micro Controller Unit supervision and system protection including reset feature is controlled by a
programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated
temperature sensors are available on-chip.
All relevant modules offer power saving modes in order to support terminal 30 connected automotive
applications. A wake-up from the power saving mode is possible via a LIN bus message, via the monitoring
inputs or repetitive with a programmable time period (cyclic wake-up).
The integrated circuit is available in a package with 0.5 mm pitch and is designed to withstand the challenging
conditions of automotive applications.
The TLE9844QX has several operational modes mainly to support low power consumption requirements. The
low power modes and state transitions are depicted in Figure 3 below.
Power-up
VS > 3V
Reset
Transition by software Transition by external event
WDT1 reset
(error_wdt++)
VDDC stable &
error_supp < 5
VDDC fail
Safety Fallback Transition by internal event
(error_supp++)
Safety fallback
error_supp = 5
Cyclic wake
Active Mode
LIN wake or
Cyclic wake
MON wake or
GPIO wake
LIN wake or
MON wake
STOP command
SLEEP command
Stop Mode
Safety fallback
error_wdt = 5
Sleep Mode
Cyclic-sense
Cyclic-sense
PMU_System_Modes.vsd
Figure 3
Power Control State Diagram
Datasheet
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Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Modes of Operation
Reset Mode
The Reset Mode is a transition mode e.g. during power-up of the device after a power-on reset. In this mode
the on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is
stable, the Active Mode is entered. In case the watchdog timer WDT1 fails for more than four times, a fail-safe
transition to the Sleep Mode is done.
Active Mode
In Active Mode all modules are activated and the TLE9844QX is fully operational.
Stop Mode
The Stop Mode is one out of two major low power modes. The transition to the low power modes is done by
setting the respective Bits in the mode control register. In Stop Mode the embedded microcontroller is still
powered allowing faster wake-up reaction times, but not clocked. A wake-up from this mode is possible by LIN
bus activity, the High Voltage Monitor Input pins or the respective 5V GPIOs.
Sleep Mode
The Sleep Mode is a major low-power mode. The transition to the low-power modes is done by setting the
respective Bits in the Micro Controller Unit mode control register. The sleep time is configurable. In Sleep
Mode the embedded microcontroller power supply is deactivated, allowing the lowest system power
consumption, but the wake-up time is longer compared to the Stop Mode. In this mode a 64 bit wide buffer for
data storage is available. A wake-up from this mode is possible by LIN bus activity or the High Voltage Monitor
Input pins and cyclic wake. A wake-up from Sleep Mode behaves similar to a power-on reset. While changing
into Sleep Mode, no incoming wake-requests are lost (i.e. no dead-time). It is possible to enter sleep-mode
even with LIN dominant.
Cyclic Wake-up Mode
The cyclic wake-up mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to
the cyclic wake-up mode is done by first setting the respective Bits in the mode control register followed by
the SLEEP or STOP command. Additional to the cyclic wake-up behavior (wake-up after a programmable time
period), the wake-up sources of the normal Stop Mode and Sleep Mode are available.
Cyclic Sense Mode
The cyclic sense mode is a special operating mode of the Sleep Mode and the Stop Mode. The transition to the
cyclic sense mode is done by first setting the respective Bits in the mode control register followed by the STOP
or SLEEP command. In cyclic sense mode the High-Side Switch can be switched on periodically for biasing
some switches for example. The wake-up condition is configurable, when the sense result of defined monitor
inputs at a window of interest changed compared to the previous wake-up period or reached a defined state
respectively. In this case the Active Mode is entered immediately.
The following table shows the possible power mode configurations of each major module or function
respectively.
Table 2
Power Mode Configurations
Module/function
VPRE, VDDP, VDDC
VDDEXT
Active Mode Sleep Mode
Stop Mode
ON
Comment
ON
OFF
–
ON/OFF
ON/OFF
OFF
cyclic ON/OFF
cyclic ON/OFF
–
HSx
cyclic ON/OFF
cyclic sense
Datasheet
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Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Modes of Operation
Table 2
Power Mode Configurations (cont’d)
Module/function
LSx
Active Mode Sleep Mode
Stop Mode
Comment
ON/OFF
ON/OFF
OFF
OFF
–
–
LIN TRx
wake-up only / OFF wake-up only/
OFF
MONx (wake-up)
MONx (measurement)
VS sense
n.a.
disabled/static/
cyclic
disabled/static/ cyclic: combined with
cyclic
HS=on
ON/OFF
OFF
OFF
available on all
channels
ON/OFF
brownout
detection
brownout detection brownout
detection
brownout det. done
in PCU
VBAT_SENSE
GPIO 5V
ON/OFF
ON
OFF
OFF
OFF
OFF
ON
–
–
–
WDT1
ON
OFF
CYCLIC WAKE
n.a.
cyclic wake-up/
cyclic sense/OFF
cyclic wake-up/ cyclic sense with HS;
cyclic sense/OFF wake-up needs MC
for enter Sleep Mode
again
Measurement
ON1)
OFF
OFF
OFF
OFF
–
–
Micro Controller Unit
ON/slow-
down/STOP
CLOCK GEN (MC)
ON
ON
ON
OFF
OFF
ON
OFF
OFF
ON
–
LP_CLK (fLP_CLK
)
WDT1
LP_CLK2 (fLP_CLK2
)
for cyclic wake-up
1) May not be switched off due to safety reasons
Wake-up Source Prioritization
All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up
sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are
latched in order to provide all wake-up events to the application software. The software can clear the wake-
up source flags. It is ensured, that no wake-up event is lost.
As default wake-up sources, MON inputs and cyclic wake are activated after power-on reset, LIN is disabled as
wake-up source by default.
Wake-up Levels and Transitions
The wake-up can be triggered by rising, falling or both signal edges for each monitor input individually.
Datasheet
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Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
5
Power Management Unit (PMU)
5.1
Features
•
•
•
•
•
•
System modes control (startup, sleep, stop and active)
Power management (cyclic wake)
Control of system voltage regulators with diagnosis (overload, short, overvoltage)
Fail safe mode detection and operation in case of system errors (watchdog fail)
Wake-up sources configuration and management (LIN, MON, GPIOs)
System error logging
5.2
Introduction
The purpose of the power management unit is to ensure the fail safe behavior of the system IC. Therefore the
power management unit controls all system modes including the corresponding transitions. The power
management unit is responsible for generating all needed voltage supplies for the embedded MCU (VDDC,
VDDP) and the external supply (VDDEXT). Additionally, the PMU provides well defined sequences for the
system mode transitions and generates hierarchical reset priorities. The reset priorities control the reset
behavior of all system functionalities especially the reset behavior of the embedded MCU. All these functions
are controlled by finite state machines. The system master functionality of the PMU requires the generation of
an independent logic supply and system clock. Therefore the PMU has a module internal logic supply and
system clock which works independently of the MCU clock.
Datasheet
15
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
5.2.1
Block Diagram
The following figure shows the structure of the Power Management Unit. Table 3 describes the submodules
more detailed.
VS
Power Down Supply
VDDP
VDDC
Power Supply Generation Unit
(PGU)
I
N
T
E
R
N
A
L
e.g. for WDT1
LP_CLK
Peripherals
LDO for External Supply
VDDEXT
VDDEXT
e.g. for cyclic wake
LP_CLK2
PMU-PCU
PMU-SFR
PMU-CMU
PMU-RMU
B
U
S
MONx
LIN
PMU-WMU
PMU-Control
Power ManagementUnit
Power_Management.vsd
Figure 4
Table 3
Power Management Unit Block Diagram
Description of PMU Submodules
Mod.
Modules
Functions
Name
Power Down Independent Supply Voltage
This supply is dedicated to the PMU to ensure an
Supply
Generation for PMU
independent operation from generated power supplies
(VDDP, VDDC).
LP_CLK
(= fLP_CLK
- Clock Source for all PMU
submodules
This ultra low power oscillator generates the clock for
the PMU.
)
- Backup Clock Source for System This clock is also used as backup clock for the system in
- Clock Source for WDT1
Clock Source for PMU
Peripheral Blocks of PMU
case of PLL Clock failure and as independent clock
source for WDT1.
LP_CLK2
(= fLP_CLK2
This ultra low power oscillator generates the clock for
the PMU in Stop Mode and in the cyclic modes.
)
Peripherals
These blocks include the analog peripherals to ensure a
stable and fail safe PMU startup and operation
(bandgap, bias).
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
Table 3
Description of PMU Submodules (cont’d)
Modules Functions
Mod.
Name
Power Supply Voltage regulators for VDDP and
This block includes the voltage regulators for the pad
supply (VDDP) and the core supply (VDDC).
Generation
Unit (PGU)
VDDC
VDDEXT
Voltage regulator for VDDEXT to
supply external modules (e.g.
Sensors)
This voltage regulator is a dedicated supply for external
modules.
PMU-SFR
PMU-PCU
All PMU relevant Extended Special This module contains all PMU relevant registers, which
Function Registers
are needed to control and monitor the PMU.
Power Control Unit of the PMU
This block is responsible for controlling all power
related actions within the PGU Module.It also contains
all regulator related diagnosis like under- and
overvoltage detection, overcurrent and short circuit
diagnoses.
PMU-WMU
PMU-CMU
PMU-RMU
Wake-up Management Unit of the This block is responsible for controlling all Wake-up
PMU
related actions within the PMU Module.
Cyclic Management Unit of the
PMU
This block is responsible for controlling all actions
within cyclic mode.
Reset Management Unit of the PMU This block generates resets triggered by the PMU like
undervoltage or short circuit reset, and passes all resets
to the relevant modules and their register. A reset status
register with every reset source is available.
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
5.2.2
PMU Modes Overview
The following state diagram shows the available modes of the device.
VS > 4V and VS ramp up
or
VS
< 3V and V
S
ramp down
LIN-wake or
MON-wake or
cyclic -wake
start-up
VDDC =stable and
error_supp<5
VDDC / VDDP = fail
(short circuit)
à error_supp ++
error_sup=5
sleep
active
Sleep command (from MCU ) or
WDT1_SEQ_FAIL = 1 (à error_wdt = 5) or
VDDC / VDDP = overload
LIN-wake or
MON-wake or
GPIO-wake or
cyclic _wake or
PMU_PIN = 1 or
SUP_TMOUT = 1
PMU_PIN = 1 or
PMU_SOFT = 1 or
(PMU_Ext_WDT = 1 and
WDT1_SEQ_FAIL = 0
à error_wdt ++)
cyclic sense
Stop
command
(from MCU)
stop
cyclic sense
PMU_System _Modes _Cus_w_Stopp .vsd
Figure 5
Power Management Unit System Modes
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
5.3
Power Supply Generation (PGU)
5.3.1
Voltage Regulator 5.0V (VDDP)
This module represents the 5 V voltage regulator, which provides the pad supply for the parallel port pins and
other 5 V analog functions (e.g. LIN Transceiver).
Features
•
•
•
•
•
•
•
•
•
5 V low-drop voltage regulator
Overcurrent monitoring and shutdown with MCU signalling (Interrupt)
Overvoltage monitoring with MCU signalling (Interrupt)
Undervoltage monitoring with MCU signalling (Interrupt)
Undervoltage monitoring with Reset (Undervoltage Reset, VDDPUV
Overtemperature shutdown with MCU signalling (Interrupt)
Pre-Regulator for VDDC Regulator
)
GPIO Supply
Pull Down Current Source at the output for Sleep Mode only (typ.5 mA)
The output capacitor CVDDP is mandatory to ensure a proper regulator functionality.
VDDP Regulator
VS
VDDP
VPRE
A
CVDDP
V
GND
I
5V LDO
LDO Supervision
LDO_block_external .vsd
Figure 6
Module Block Diagram of VDDP Voltage Regulator
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
5.3.2
Voltage Regulator 1.5V (VDDC)
This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core,
digital peripherals and other chip internal analog 1.5 V functions (e.g. ADC).
Features
•
•
•
•
•
•
•
1.5 V low-drop voltage regulator
Overcurrent monitoring and Shutdown with MCU signalling (Interrupt)
Overvoltage monitoring with MCU signalling (Interrupt)
Undervoltage monitoring with MCU signalling (interrupt)
Undervoltage monitoring with reset
Overtemperature Shutdown with MCU signalling (Interrupt)
Pull Down Current Source at the output for Sleep Mode only (typ. 100 μA)
The output capacitor CVDDC is mandatory to ensure a proper regulator functionality.
VDDC Regulator
VDDP (5V)
VDDC (1.5V)
CVDDC
A
V
V
CVDDP
I
1.5V LDO
Supervision
1.5VLDOblockexternal.vsd
Figure 7
Module Block Diagram of VDDC Voltage Regulator
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
5.3.3
External Voltage Regulator 5.0V (VDDEXT)
This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used
e.g. to supply an external sensor, LEDs or potentiometers.
Features
•
•
•
•
•
•
•
•
Switchable (by software) +5 V, low-drop voltage regulator
Switch-on undervoltage blanking time in order to drive small capacitive loads
Intrinsic current limitation
Undervoltage monitoring and shutdown with MCU signalling (Interrupt)
Overtemperature Shutdown with MCU signalling (Interrupt)
Pull Down Current Source at the output for Sleep Mode only (typ. 100 μA)
Cyclic sense option together with GPIOs
Low current mode available to ensure reduced stop mode current consumption. In this mode current
capability is reduced to IVDDEXT_LCM
The output capacitor CVDDEXT is mandatory to ensure a proper regulator functionality.
VDDEXT Regulator
VS
VDDEXT (5V)
CVDDEXT
V
CVS
V
VDDEXT LDO
Supervision
HALL_LDOblockexternal.vsd
Figure 8
Module Block Diagram
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Power Management Unit (PMU)
5.3.4
Power-on Reset Concept
Vs
ca. 4V
1.5V
PMU_1V5DidPOR
LP_Clk
5V
VDDP
ca. 3.5V
3V
VDDC
1.5V
fail
stable
ok
SUPPLY_STATUS
RESET_PIN
PMU_RESET_STS
xxh
80h
Down
Start-up
Active
SYSTEM_STATE
Figure 9
Power-on Reset Concept
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
6
System Control Unit - Digital Modules (SCU-DM)
6.1
Features
•
•
•
•
•
•
Flexible clock configuration features
Reset management of all system resets
System modes control for all power modes (active, power down, sleep)
Interrupt enabling for many system peripherals
General purpose input output control
Debug mode control of system peripherals
6.2
Introduction
The System Control Unit (SCU) supports all central control tasks in the TLE9844QX. The SCU is made up of the
following sub-modules:
•
•
•
•
•
•
•
•
•
•
Clock System and Control (CGU)
Reset Control (RCU)
Power Management (PCU)
Interrupt Management (ICU)
General Port Control
Flexible Peripheral Management
Module Suspend Control
Error Detection and Correction in Data Memory
Miscellaneous Control
Register Mapping
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
6.2.1
Block Diagram
on signals to digital
peripherals;
status signalsfrom
digital peripherals
AMBA AHB
NMI
PCU
CGU
ICU
I
INTISR <9:0>
N
T
E
R
N
A
L
fpclk
fBR
fsys
LP_CLK
Baudrate Generator /
LIN Frame Detection
B
U
S
PMU_1V5DidPOR
PMU_PIN
PMU_ExtWDT
PMU_SOFT
RCU
MISC Control
MODPISELx
PMU_Wake
Reset_Type_3
Reset_Type_4
P0_POCONy.PDMx
P1_POCONy.PDMx
Port Control
System Control Unit -Digital Modules
SCU_DM_Block_Diagram_Cust.vsd
Figure 10 System Control Unit - Digital Modules Block Diagram
IO description of SCU_DM:
•
•
CGU:
–
–
f
sys; system clock
LP_CLK; low-power backup clock
RCU:
–
–
–
–
–
1V5DidPOR; Undervoltage reset of power down supply
PMU_PIN; Reset generated by reset pin
PMU_ExtWDT; WDT1 reset
PMU_SOFT; Software reset
PMU_Wake; Stop Mode exit with reset
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
–
–
Reset_Type_3; Peripheral reset (contains all resets)
Reset_Type_4; Peripheral reset (without SOFT)
•
•
Baudrate generator:
fBR; Baudrate clock for UART
Port Control:
–
–
–
P0_POCONy.PDMx; driver strength control
P1_POCONy.PDMx; driver strength control
•
MISC:
MODPISELx; Mode selection registers for UART (source selection) and Timer (trigger or count selection)
–
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
6.3
Clock Generation Unit
The Clock Generation Unit (CGU) provides a flexible clock generation for TLE9844QX. During user program
execution the frequency can be programmed for an optimal ratio between performance and power
consumption. Therefore the power consumption can be adapted to the actual application state.
The CGU in the TLE9844QX consists of one oscillator circuit (OSC_HP), a Phase-Locked Loop (PLL) module
including an internal oscillator (OSC_PLL) and a Clock Control Unit (CCU). The CGU can convert a low-
frequency input/external clock signal to a high-frequency internal clock.
The system clock fSYS is generated out of the following selectable clocks:
•
•
•
•
PLL clock output fPLL
Direct clock from oscillator OSC_HP fOSC
Direct output of internal Oscillator fINTOSC
Low precision clock fLP_CLK (HW-enabled for startup after reset and during power-down wake-up sequence)
The following sections describe the different parts of the CGU.
6.3.1
Low Precision Clock
The clock source LP_CLK is a low-precision RC oscillator (LP-OSC, see fLP_CLK) that is enabled by hardware as
an independent clock source for the TLE9844QX startup after reset and during the power-down wake-up
sequence. There is no user configuration possible on fLP_CLK
.
6.3.2
High Precision Oscillator Circuit (OSC_HP)
The high precision oscillator circuit, designed to work with both an external crystal oscillator or an external
stable clock source, consists of an inverting amplifier with XTAL1 as input, and XTAL2 as output.
Figure 11 shows the recommended external circuitries for both operating modes, External Crystal Mode and
External Input Clock Mode.
6.3.2.1 External Input Clock Mode
When supplying the clock signal directly, not using an external crystal and bypassing the oscillator, the input
frequency needs to be within the range of 4 MHz to 24 MHz if the PLL VCO part is used.
When using an external clock signal it must be connected to XTAL1. XTAL2 is left open (unconnected).
6.3.2.2 External Crystal Mode
When using an external crystal, its frequency can be within the range of 4 MHz to 6 MHz. An external oscillator
load circuitry must be used, connected to both pins, XTAL1 and XTAL2. It consists normally of the two load
capacitances C1 and C2, for some crystals a series damping resistor might be necessary. The exact values and
related operating range are dependent on the crystal and have to be determined and optimized together with
the crystal vendor using the negative resistance method. As starting point for the evaluation, the following
load cap values may be used:
Table 4
External CAP Capacitors
Fundamental Mode Crystal Frequency (approx., MHz) Load Caps C1, C2 (pF)
4
5
6
33
22
18
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
V
V
DDP
DDP
External Clock
Signal
f
XTAL1
OSC_HP
XTAL2
XTAL1
OSC_HP
f
OSC
OSC
4 - 6
MHz
XTAL2
C1
C2
Fundamental
Mode Crystal
V
V
SS
SS
External Crystal Mode
External Input Clock Mode
VSS = GND
ext_osc
Figure 11 TLE9844QX External Circuitry for the OSC_HP
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
6.3.3
Clock Control Unit
The Clock Control Unit (CCU) receives the clock from the PLL fPLL, the external input clock fOSC, the internal
input clock fINTOSC, or the low-precision input clock fLP_CLK. The system frequency is derived from one of these
clock sources.
CCU
SCU_SYSCON0.
SYSCLKSEL
fPLL
M
U
X
fOSC
f
SYS
fINTOSC
fLP_CLK
CCU_block
Figure 12 Clock Inputs to Clock Control Unit
The CCU generates all necessary clock signals within the microcontroller from the system clock. It consists of:
•
•
Clock slow down circuitry
Centralized enable/disable circuit for clock control
In normal running mode, the main module frequencies (synchronous unless otherwise stated) are as follows:
•
•
•
•
System frequency, fSYS = up to 25 MHz (measurement interface clock MI_CLK is derived from this clock)
CPU clock (CCLK, SCLK) = up to 25 MHz (divide-down of NVM access clock)
NVM access clock (NVMACCCLK) = up to 25 MHz
Peripheral clock (PCLK, PCLK2, NVMCLK) = up to 25 MHz (equals CPU clock; must be same or higher)
Some peripherals are clocked by PCLK, others clocked by PCLK2 and the NVM is clocked by both NVMCLK and
NVMACCCLK. During normal running mode, PCLK = PCLK2 = NVMCLK = CCLK. On wake-up from power-down
mode, PCLK2 is restored similarly like NVMCLK, whereas PCLK is restored only after PLL is locked.
For optimized NVM access (read/write) with reduced wait state(s) and with respect to system requirements on
CPU operational frequency, bit field NVMCLKFAC is provided for setting the frequency factor between the NVM
access clock NVMACCCLK and the CPU clock CCLK.
For the slow down mode, the operating frequency is reduced using the slow down circuitry with clock divider
setting at the bit field CLKREL. Bit field CLKREL is only effective when slow down mode is enabled via SFR bit
PMCON0.SD bit. Note that the slow down setting of bit field CLKREL correspondingly reduces the NVMACCCLK
clock. Slow down setting does not influence the erase and write cycles for the NVM.
Peripherals UART1, UART2, T2 and T21 and are not influenced by CLKREL and either not by NVMCLKFAC,
to allow functional LIN communication in slow down mode.
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
Analog Subsystem /
PBA0 / PBA1
fSYS
UART 1/2,
Timer 2/21,
Baudgen 1/2
Clock
Control Unit
APCLK2FAC
TFILT_CLK
TFILT_CLK
Analog
Peripherals
MI_CLK
PCLK2
APCLK1FAC
SFR
MI_CLK
MI_CLK
Measurement
Interface
PCLK2
PCLK
Peripherals
Peripherals
CLKREL
NVMCLKFAC
fPLL
SCLK
CCLK
fOSC
f
f
SYS
CCLK
CORE
M
U
X
fINTOSC
f
LP_CLK
NVMCLK
NVM
NVMACCCLK
PBA0CLKREL
Peripherals
Peripherals
COREL
TLEN
Toggle
Latch
CLKOUT
COUTS1
Figure 13 Clock Generation from fsys; CLKOUT Generation
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Power Modules (SCU-PM)
7
System Control Unit - Power Modules (SCU-PM)
7.1
Description of the Power Modules System Control Unit
The System Control Unit of the power modules consists of the following sub-modules:
•
•
•
•
Clock Watchdog Unit (CWU): supervision of all power modules relevant clocks with NMI signalling.
Interrupt Control Unit (ICU): all system relevant interrupt flags and status flags.
Power Control Unit (PCU): takes over control when device enters and exits Sleep and Stop Mode.
External Watchdog (WDT1): independent system watchdog to monitor system activity
7.2
Introduction
7.2.1
Block Diagram
The System Control Unit of the power modules consists of the sub-modules in the figure shown below:
on signals to analog
peripherals;
status signalsfrom
analog peripherals
AMBA AHB
I
N
T
PCU
WDT1
LP_CLK
E
R
N
A
L
fsys
MI_CLK
PREWARN_SUP_NMI
PREWARN_CLK_INT
INT<n:0>
B
U
S
CWU
ICU
TFILT_CLK
System Control Unit -Power Modules
SCU_PM_Block_Diagram_Cust.vsd
Figure 14 Block diagram of System Control Unit - Power Modules
IO description of SCU_PM:
CWU (Clock Watchdog Unit)
•
•
check of fsys = system frequency: output of PLL
check of MI_CLK = measurement interface clock (analog clock): derived out of fsys by division factors
1/2/3/4
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Power Modules (SCU-PM)
•
check of TFILT_CLK = clock used for digital filters: derived out of fsys by configurable division factors
ICU (Interrupt Control Unit)
•
•
•
PREWARN_SUP_NMI = generation of Prewarn-Supply NMI
PREWARN_CLK_INT = generation of Prewarn-Clock Watchdog NMI
INT = generation of MISC interrupts
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Arm® Cortex®-M0 Core
8
Arm® Cortex®-M0 Core
8.1
Features
The key features of the Cortex®-M0 implemented are listed below.
Processor Core. A low gate count core, with low latency interrupt processing:
•
•
•
•
•
•
Thumb® + Thumb-2® Instruction Set
Banked stack pointer (SP) only
Handler and thread modes
Thumb and debug states
Interruptible-continued instructions LDM/STM, Push/Pop for low interrupt latency
Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and
exit
•
•
•
Arm® architecture v6-M Style
ARM®v6 unaligned accesses
Systick (typ. 1ms)
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low
latency interrupt processing:
•
•
•
•
External interrupts, configurable from 1 to 24
7 interrupt priority registers for levels from 0 up to 192 in steps of 64
Dynamic repriorization of interrupts
Priority grouping. This enables selection of pre-empting interrupt levels and non pre-empting interrupt
levels
•
•
Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing
without the overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction
overhead
Bus interfaces
Advanced High-performance Bus-Lite (AHB-Lite) interfaces
•
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Arm® Cortex®-M0 Core
8.2
Introduction
The Arm® Cortex®-M0 processor is a leading 32-bit processor and provides a high-performance and cost-
optimized platform for a broad range of applications including microcontrollers, automotive body systems
and industrial control systems. Like the other Cortex®-family processors, the Cortex®-M0 processor
implements the Thumb®-2 instruction set architecture. With the optimized feature set the Cortex®-M0 delivers
32-bit performance in an application space that is usually associated with 8- and 16-bit microcontrollers.
8.2.1
Block Diagram
Figure 15 shows the functional blocks of the Cortex®-M0.
Cortex-M0 Processor
Nested Vectored
Interrupt
Breakpoint
and
watchpoint
unit
Cortex-M0
processor
core
Interrupt and
Power Control
Controller
(NVIC)
Serial-Wire
Debug Access Port
(SW-DP)
Busmatrix
Debugger interface
AHB-Lite interface
Serial-Wire Debug
Interface
Cortex_M0_Block_diagram.vsd
Figure 15 Cortex®-M0 Block Diagram
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Address Space Organization
9
Address Space Organization
The embedded Cortex®-M0 MCU offers the following address space organization:
Figure 16 Original Cortex®-M0 Memory Map
The TLE9844QX manipulates operands in the following memory spaces:
•
•
•
64 KByte of Flash memory in code space
24 KB Boot ROM memory in code space (used for boot code and IP storage)
4 KB RAM memory in code space and data space (RAM can be read/written as program memory or external
data memory)
•
Special function registers (SFRs) in peripheral linear address space, up to 0.5 GBytes
The figure below shows the detailed address alignment of TLE9844QX:
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Address Space Organization
The on-chip memory modules available in the TLE9844QX are:
FFFF.FFFFH
E010.0000H
reserved
E00F.FFFFH
Private Peripheral Bus
E000.0000H
DFFF.FFFFH
6000.0000H
reserved
5FFF.FFFFH
PBA1
4800.0000H
47FF.FFFFH
PBA0
4000.0000H
3FFF.FFFFH
1800.1000H
reserved
1800.0FFFH
SRAM
up to 4K *)
1800.0000H
17FF.FFFFH
1101.0000H
reserved
1100.FFFFH
Flash
up to 64K *)
1100.0000H
10FF.FFFFH
0000.6000H
reserved
0000.5FFFH
Boot-ROM
24K
0000.0000H
*) Product variant dependant
MemoryMapARM0_4x.vsd
Figure 17 TLE9844QX Memory Map
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Memory Control Unit
10
Memory Control Unit
10.1
Features
•
•
•
•
•
Provides Memory access to ROM, RAM, NVM, Config Sector through AHB-Lite Interface
MBIST for RAM
MBIST for ROM
NVM Configuration with Special Function Registers through AHB-Lite Interface
Hardware Memory Protection Logic
10.2
Introduction
10.2.1
Block Diagram
The Memory Control Unit is divided in the following sub-modules:
•
•
•
•
NVM Memory module (embedded Flash Memory)
RAM memory module
BootROM memory module
Memory protection Unit (MPU) module
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Memory Control Unit
NVM
S0
RAM
S1
ROM
S2
PBA0
S3
Memory Protection
Unit
Sx: BusSlave
Mx: Bus Master
M0
M1
M2
M3
Bus Matrix
MCU_Block_Diagram_overview.vsd
Figure 18 Memory Control Unit Block View
Functional Features for RAM
•
•
4 KB RAM
Error correction code (ECC) for detection of single bit and double bit errors and dynamic correction of
single bit errors
•
Single byte access
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
NVM Module (Flash Memory)
11
NVM Module (Flash Memory)
The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and
reliable storage of user code and data.
Features
•
•
In-System Programming via LIN (Flash mode) and SWD
Error Correction Code (ECC) for detection of single Bit and double Bit errors and dynamic correction of
single Bit errors on Data Block (Double words, 64 bits).
•
Interrupt and signaling of double bit error by NMI, address of double bit error readable by FW API user
routine.
•
•
•
•
•
•
•
•
•
•
•
•
Possibility of checking single bit error occurrence by ROM routines
Program width of 128 Byte (page)
Minimum erase width of 128 Byte (page)
Integrated hardware support for EEPROM emulation
8 Byte read access
Physical read access time: typ. 75 ns
Code read access acceleration integrated; read buffer
Page program time: typ. 3 ms
Programming time for 64KB via Debug Interface: < 1800 ms (typ.)
Page erase (128 bytes) and sector erase (4K bytes) time: typ. 4ms
3 separate keys for data area, program area and BSL area
Password protection for three configurable program flash areas, three separate keys for data, program
and BSL
•
•
Security option to protect read out via debug interface in application run mode. NVM protection mode
available, which can be enabled/disabled with password
Write/erase access to 100TP (e.g. option bytes) is possible via the debug interface
Note:
The user has to ensure that no flash operations which change the content of the flash get interrupted
at any time.
The clock for the NVM is supplied with the system frequency fsys. Integrated firmware routines are provided to
ease NVM, and other operations including EEPROM emulation.
The TLE9844QX NVM module provides physical implementation of the memory module as well as needed
complementary features and interface towards the core.
The module provides proper access to the memory through 2 AHB-Lite interfaces: a 8-bit data interface for
NVM internal register access and a 32-bit data interface for code/data access both multiplexed on Cortex®-M0
system bus.
The TLE9844QX NVM module consists of the memory cell array and all the control circuits and registers needed
to access the array itself. The 64 Kbyte data module is mapped in the Cortex®-M0 code address range
11000000H - 1100FFFFH while the dedicated SFRs are mapped in the Cortex®-M0 system address range
58004000H - 58007FFFH.
Access of NVM module is granted through the AMBA matrix block that forwards to the memory modules AHB-
Lite interfaces the requests generated by the masters according to the defined priority policy.
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
NVM Module (Flash Memory)
11.1
Definitions
This section defines the nomenclature and some abbreviations. The used flash memory is a non-volatile
memory (“NVM”) based on a floating gate one-transistor cell. It is called “non-volatile” because the memory
content is kept when the memory power supply is shut off.
11.1.1
General Definitions
Logical and Physical States
Erasing
The erased state of a cell is ´1´. Forcing an NVM cell to this state is called erasing. Erasing is possible with a
granularity of a page (see below).
Writing
The written state of a cell is ´0´. Forcing an NVM cell to this state is called writing. Each bit can be individually
written.
Programming
The combination of erasing and writing is called ‘programming’. Programming often means also writing a
previously erased page.
The wording ‘write’ or ‘writing’ are also used for accessing special function registers and the assembly buffer.
The meaning depends therefore on the context.
The above listed processes have certain limitations:
Retention: This is the time during which the data of a flash cell can be read reliably. The retention time is a
statistical figure that depends on the operating conditions of the flash array (temperature profile) and the
accesses to the flash array. With an increasing number of program/erase cycles (see endurance) the retention
is lowered. Drain and gate disturbs decrease data retention as well.
Endurance: As described above, the data retention is reduced with an increasing number of program/erase
cycles. A flash cell incurs one cycle whenever its page or sector is erased. This number is called “endurance”.
As said for the retention, it is a statistical figure that depend on operating conditions and the use of the flash
cells and on the required quality level.
Drain Disturb: Because of using a so called “one-transistor” flash cell each program access disturbs all pages
of the same sector slightly. Over long these “drain disturbs” make 0 and 1 values indistinguishable and thus
provoke read errors. This effect is again interrelated with the retention. A cell that incurred a high number of
drain disturbs will have a lower retention. The physical sectors of the flash array are isolated from each other.
So pages of a different sector do not incur a drain disturb. this effect must be therefore considered when the
page erase feature is used or when re-programming an ready programmed page (implicitly causing an erase
of the page before writing the new data).
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
NVM Module (Flash Memory)
Data Portions
Array(n-1)*4 kB
Spare page
sector n-1
Page 31
Page 30
Page 1
sector 1
Page 0
sector 0
1 page = 16 user data block + 1 mapping information block
Map block
Data block 0
Data block 1
Data block 14 Data block 15
1 block = 8 bytes
byte 2 byte 3
byte 0
byte 1
byte 4
byte 5
byte 6
byte 7
NVM Logical Structure
Figure 19 Logical Structure of the NVM Core
Doubleword
A doubleword consists of 64 bits. A doubleword represents the data size that is read from or written to the NVM
core module within one access cycle.
Block
A block consists of one doubleword and its associated ECC data (64 bit data and 8 bit ECC). A block represents
the smallest data portion that can be changed in the assembly buffer. Since the ECC protects 64 bits, when a
byte is written to the assembly buffer automatically an NVM internal read of the complete block is triggered,
the byte and the ECC are updated and the complete block is written back to the assembly buffer.
Mapblock
A map block consists of a module specific number of ECC -protected bits that hold the necessary information
to map a physical page to a logical page.
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
NVM Module (Flash Memory)
Page
A page consists of 16 blocks and one map block.
Spare Page
A spare page is an additional page in a sector used in each programming routine to allow tearing-safe
programming.
Sector
A sector consists of 32 logical and 33 physical pages.
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Interrupt System
12
Interrupt System
12.1
Features
•
•
•
Up to 24 interrupt nodes for on-chip peripherals
Up to 8 NMI nodes for critical system events
Maximum flexibility for all 24 interrupt nodes
12.2
Introduction
12.2.1
Overview
The TLE9844QX supports 24 interrupt vectors with 4 priority levels. 22 of these interrupt vectors are assigned
to the on-chip peripherals: GPT12, SSC1, SSC2, CCU6, Low-Side Switch, High-Side Switch and A/D Converter
are each assigned to one dedicated interrupt vector; while UART1 and Timer2 or UART2, External Interrupt 2
and Timer21 share interrupt vectors. Two vectors are dedicated for External Interrupt 0 and 1.
Table 5
Interrupt Vector Table
Service Request
GPT1
GPT2
MU
Node ID
Description
0
GPT1 Interrupt
1
GPT2 Interrupt
2
MU interrupt / ADC2, VBG interrupt
ADC10 Bit interrupt
ADC1
CCU0
CCU1
CCU2
CCU3
SSC1
3
4
CCU6 node 0 interrupt
5
CCU6 node 1 interrupt
6
CCU6 node 2 interrupt
7
CCU6 node 3 interrupt
8
SSC1 interrupt (receive, transmit, error)
SSC2 interrupt (receive, transmit, error)
UART1 (ASC-LIN) interrupt (receive, transmit), t2, linsync1, LIN
UART2 interrupt (receive, transmit), t21, External interrupt (EINT2)
External interrupt (EINT0)
SSC2
9
UART1
UART2
EXINT0
EXINT1
WAKEUP
rfu
10
11
12
13
14
15
16
17
18
19
20
External interrupt (EINT1)
Wakeup interupt (generated by a wakeup event)
Reserved for future use
rfu
Reserved for future use
LS1
Low Side 1 Interrupt
LS2
Low Side 2 Interrupt
HS1
High Side 1 Interrupt
rfu
Reserved for future use
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Interrupt System
Table 5
Interrupt Vector Table (cont’d)
Service Request
rfu
Node ID
Description
21
22
23
Reserved for future use
MONx Interrupt
Port 2.x - DPP1
MONx
Port 2.x
Table 6
NMI Interrupt Table
Service Request
Node
NMI
Description
PLL NMI
PLL Loss-of-Lock
NVM Operation Complete
NVM Operation
Complete NMI
NMI
Overtemperature NMI NMI
System Overtemperature
Oscillator Watchdog
NMI
NMI
Oscillator Watchdog and MI_CLK Watchdog Timer Overflow
NVM Map Error NMI
ECC Error NMI
NMI
NMI
NVM Map Error
RAM / NVM Uncorrectable ECC Error
Supply Prewarning
Supply Prewarning NMI NMI
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Watchdog Timer (WDT1)
13
Watchdog Timer (WDT1)
13.1
Features
In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way
to recover from software or hardware failures.
The WDT1 is always enabled in Active Mode. In Sleep Mode, Stop Mode and Debug Mode the WDT1 is disabled.
Functional Features
•
•
•
•
•
•
•
•
Watchdog Timer is operating with a from the system clock (fSYS) independent clock source (fLP_CLK)
Windowed Watchdog Timer with programmable timing (16, 32, 48, …, 1008ms period) in Active Mode
Long open window (200 ms) after power-up, reset, wake-up
Short open window (30 ms) to facilitate Flash programming
System safety shutdown to Sleep Mode after 5 missed WDT1 services
Watchdog is disabled in Debug Mode
Watchdog cannot be deactivated in Normal Mode
Watchdog reset is stored in reset status register
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Watchdog Timer (WDT1)
13.2
Introduction
The behavior of the Watchdog Timer in Active Mode is depicted in Figure 20.
Power-up
Reset
RESET
always
timeout
timeout
Maximum number
RESET
Trigger SOW
of SOW triggers
exceeded
Timeout
or
Trigger in closed window
RESET
Long
Open Window
Trigger
Trigger SOW
Trigger
Normal
„windowed“
operation
Short
open window
Trigger SOW
Trigger
Figure 20 Watchdog Timer Behavior
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
14
GPIO Ports and Peripheral I/O
The TLE9844QX has 18 port pins organized into three parallel ports: Port 0 (P0), Port 1 (P1) and Port 2 (P2). Each
port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. P0
and P1 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate
input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can
be selected. On Port 2 (P2) analog inputs are shared with general purpose input.
14.1
Features
•
•
10 GPIOs (P0.x & P1.x), 6 analog inputs (P2.x) and two additional analog inputs shared with a XTAL feature
(P2.4, P2.5).
Strong pull-up at Reset-pin and Hall-inputs (except P2.x)
Bidirectional Port Features (P0, P1)
•
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Configurable drive strength
Transfer of data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Analog Port Features (P2)
•
•
•
Configurable pull-up/pull-down devices
Transfer of data through digital inputs
Alternate inputs for on-chip peripherals
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
14.2
Introduction
14.2.1
Port 0 and Port 1
Figure 21 shows the block diagram of an TLE9844QX bidirectional port pin. Each port pin is equipped with a
number of control and data bits, thus enabling very flexible usage of the pin.
PUDSEL
Pull-up / Pull-down
Select Register
Pull-up / Pull-down
Control Logic
PUDEN
Pull-up / Pull-down
Enable Register
TCCR
Temperature Compensation
Control Register
Px_POCONy
Port Output
Driver Control Registers
I
N
T
E
R
N
A
L
OD
Open Drain
Control Register
DIR
Direction Register
ALTSEL0
Alternate Select
Register 0
B
U
S
ALTSEL1
Alternate Select
Register 1
Pull Device
AltDataOut 3
AltDataOut 2
AltDataOut 1
11
10
Output
Driver
01
00
Out
In
Data
Data Register
Input
Driver
AltDataIn
AnalogIn
Schmitt
Trigger
Pad
Port_Block_Diagram.vsd
Figure 21 General Structure of Bidirectional Port
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
14.2.2
Port 2
Figure 22 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register
P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage
level present at the port pin is translated into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the
register P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device.
Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated while register P2_PUDEN
enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt-
Trigger device for direct feed-through to the ADC input channel.
Internal
Bus
PUDSEL
Pull-up/Pull-down
Select Register
Pull-up/Pull-down
Control Logic
PUDEN
Pull-up/Pull-down
Enable Register
Pull
Device
Input
Driver
In
Data
Data Register
Schmitt
Trigger
Pad
AltDataIn
AnalogIn
Port_InputDiagram.vsd
Figure 22 General Structure of Input Port
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
14.3
TLE9844QX Port Implementation Details
Port 0
14.3.1
14.3.1.1 Port 0 Functions
Port 0 alternate function mapping according Table 7
Table 7
Port Pin
P0.0
Port 0 Input/Output Functions
Input/Output
Select
GPI
Connected Signal(s)
P0_DATA.P0
T12HR_0
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
CCU6
GPT12
Timer 2
SWD
T4INA
T2_0
SWD_CLK
EXINT2_3
P0_DATA.P0
T3OUT_0
EXF21_0
SCU
Output
Input
GPT12
Timer 21
UART2
UART2_RXDO
P0_DATA.P1
T13HR_0
P0.1
INP1
INP2
INP3
INP4
INP5
INP6
INP7
INP8
INP9
GPO
ALT1
ALT2
ALT3
CCU6
UART1_RXD
T2EX_1
UART1
Timer 2
Timer 21
SCU
T21_0
EXINT0_3
T4INC
GPT12
GPT12
SSC1/2
CCU6
CAPINA
SSC12_S_SCK
CC62_0
Output
P0_DATA.P1
T6OUT_0
CC62_0
GPT12
CCU6
SSC12_M_SCK
SSC1/2
Datasheet
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Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
Table 7
Port Pin
P0.2
Port 0 Input/Output Functions (cont’d)
Input/Output
Select
GPI
Connected Signal(s)
P0_DATA.P2
T2EUDA
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
GPT12
CCU6
CTRAP_0
SSC12_M_MRST
T21EX_0
SSC1/2
Timer 21
SCU
EXINT1_3
Output
Input
P0_DATA.P2
SSC12_S_MRST
UART1_TXD
EXF2_0
SSC1/2
UART1
Timer 2
P0.3
P0_DATA.P3
SSC1_S_SCK
T4EUDA
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
GPI
SSC1
GPT12
GPT12
SCU
CAPINB
EXINT1_2
T3EUDD
GPT12
CCU6
CCPOS0_1
P0_DATA.P3
SSC1_M_SCK
T6OFL
Output
Input
SSC1
GPT12
GPT12
T6OUT_1
P0.4
P0_DATA.P4
SSC1_S_MTSR
CC60_0
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
SSC1
CCU6
Timer 21
SCU
T21_2
EXINT2_2
T3EUDA
GPT12
CCU6
CCPOS1_1
P0_DATA.P4
SSC1_M_MTSR
CC60_0
Output
SSC1
CCU6
SCU
CLKOUT_0
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
Table 7
Port Pin
P0.5
Port 0 Input/Output Functions (cont’d)
Input/Output
Select
GPI
Connected Signal(s)
P0_DATA.P5
SSC1_M_MRST
EXINT0_0
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
SSC1
SCU
T21EX_2
Timer 21
GPT12
CCU6
T5INA
CCPOS2_1
Output
P0_DATA.P5
SSC1_S_MRST
COUT60_0
SSC1
CCU6
LIN
LIN_RXD
Datasheet
51
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
14.3.2
Port 1
14.3.2.1 Port 1 Functions
Port 1alternate function mapping according Table 8
Table 8
Port Pin
P1.0
Port 1 Input / Output Functions
Input/Output
Select
GPI
Connected Signal(s)
P1_DATA.P0
T3INC
From/to Module
Input
INP1
INP2
INP3
INP4
GPO
ALT1
ALT2
ALT3
GPI
GPT12
CCU6
SSC2
CC61_0
SSC2_S_SCK
T4EUDB
GPT12
Output
Input
P1_DATA.P0
SSC2_M_SCK
CC61_0
SSC2
CCU6
UART2
UART2_TXD
P1_DATA.P1
T6EUDA
P1.1
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
GPI
GPT12
GPT12
GPT12
SSC2
T5INB
T3EUDC
SSC2_S_MTSR
T21EX_3
Timer 21
UART2
UART2_RXD
P1_DATA.P1
SSC2_M_MTSR
COUT61_0
EXF21_1
Output
Input
SSC2
CCU6
Timer 21
P1.2
P1_DATA.P2
EXINT0_1
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
SCU
T21_1
Timer 21
GPT12
SSC2
T2INA
SSC2_M_MRST
CCPOS2_2
P1_DATA.P2
SSC2_S_MRST
COUT63_0
T3OUT_1
CCU6
Output
SSC2
CCU6
GPT12
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
Table 8
Port Pin
P1.4
Port 1 Input / Output Functions (cont’d)
Input/Output
Select
GPI
Connected Signal(s)
P1_DATA.P4
EXINT2_1
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
SCU
T21EX_1
Timer 21
GPT12
GPT12
SSC1/2
CCU6
T2INB
T5EUDA
SSC12_S_MTSR
CCPOS1_2
Output
P1_DATA.P4
CLKOUT_1
COUT62_0
SCU
CCU6
SSC1/2
SSC12_M_MTSR
Datasheet
53
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
14.3.3
Port 2
14.3.3.1 Port 2 Functions
Port 2 alternate function mapping according Table 9
Table 9
Port Pin
P2.0
Port 2 Input Functions
Input/Output
Select
Connected Signal(s)
P2_DATA.P0
EXINT1_1
CCPOS0_2
T5EUDB
From/to Module
Input
GPI
INP1
INP2
INP3
ANALOG
GPI
SCU
CCU6
GPT12
ADC
AN0
P2.1
Input
P2_DATA.P1
CCPOS0_0
EXINT1_0
T12HR_1
CC61_1
INP1
INP2
INP3
INP4
ANALOG
GPI
CCU6
SCU
CCU6
CCU6
ADC
AN1
P2.2
P2.3
Input
Input
P2_DATA.P2
T6EUDB
INP1
INP2
INP3
ANALOG
GPI
GPT12
Timer 2
CCU6
ADC
T2EX_0
T12HR_2
AN2
P2_DATA.P3
CCPOS1_0
EXINT0_2
CTRAP_1
T3IND
INP1
INP2
INP3
INP4
INP5
ANALOG
GPI
CCU6
SCU
CCU6
GPT12
CCU6
ADC
CC60_1
AN3
P2.4
Input
P2_DATA.P4
T2EUDB
INP1
INP2
INP3
INP4
INP5
IN
GPT12
Timer 2
Timer 2
CCU6
T2_2
T2EX_2
CCPOS0_3
CTRAP_2
XTAL (in)1)
CCU6
XTAL
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
GPIO Ports and Peripheral I/O
Table 9
Port Pin
P2.5
Port 2 Input Functions (cont’d)
Input/Output
Select
GPI
Connected Signal(s)
P2_DATA.P5
T3EUDB
From/to Module
Input / Output
INP1
INP2
INP3
INP4
INP5
OUT
GPT12
GPT12
Timer 2
LIN
T4EUDC
T2_1
LIN_TXD
CCPOS1_3
XTAL (out)1)
P2_DATA.P6
T4EUDD
CCU6
XTAL
P2.6
P2.7
Input
Input
GPI
INP1
INP2
INP3
INP4
ANALOG
GPI
GPT12
Timer 2
CCU6
CCU6
ADC
T2EX_3
CCPOS2_3
T13HR_2
AN6
P2_DATA.P7
CCPOS2_0
EXINT2_0
T13HR_1
CC62_1
INP1
INP2
INP3
INP4
ANALOG
CCU6
SCU
CCU6
CCU6
ADC
AN7
1) configurable by user
Datasheet
55
Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
General Purpose Timer Units (GPT12)
15
General Purpose Timer Units (GPT12)
Features
15.1
15.1.1
Features Block GPT1
The following list summarizes the supported features:
•
•
•
•
fGPT/4 maximum resolution
3 independent timers/counters
Timers/counters can be concatenated
4 operating modes:
–
–
–
–
Timer Mode
Gated Timer Mode
Counter Mode
Incremental Interface Mode
•
•
Reload and Capture functionality
Shared interrupt: Node 0
15.1.2
Features Block GPT2
The following list summarizes the supported features:
•
•
•
•
fGPT/2 maximum resolution
2 independent timers/counters
Timers/counters can be concatenated
3 operating modes:
–
–
–
Timer Mode
Gated Timer Mode
Counter Mode
•
•
Extended capture/reload functions via 16-bit capture/reload register CAPREL
Shared interrupt: Node 1
15.2
Introduction
The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures
which may be used for timing, event counting, pulse width measurement, pulse generation, frequency
multiplication, and other purposes.
They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in
each block may operate independently in a number of different modes such as Gated timer or Counter Mode,
or may be concatenated with another timer of the same block.
Each block has alternate input/output functions and specific interrupts associated with it. Input signals can
be selected from several sources by register PISEL.
The GPT module is clocked with clock fGPT. fGPT is a clock derived from fSYS
.
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
General Purpose Timer Units (GPT12)
15.2.1
Block Diagram GPT1
Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The
maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture
registers for the core timer.
T3CON.BPS1
2n : 1
Basic clock
fGPT
InterruptRequest
(T2IRQ)
Aux. Timer T2
Core Timer T3
Aux. Timer T4
U/D
T2IN
T2
Mode
Control
Capture
Reload
T2EUD
Toggle Latch
T3
Mode
Control
T3IN
T3OTL
T3OUT
U/D
T3EUD
InterruptRequest
(T3IRQ)
Capture
Reload
T4IN
T4
Mode
Control
T4EUD
InterruptRequest
(T4IRQ)
U/D
MC _GPT0101_bldiax1.vsd
Figure 23 GPT1 Block Diagram (n = 2 … 5)
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
General Purpose Timer Units (GPT12)
15.2.2
Block Diagram GPT2
Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum
resolution is fGPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation
with extended functionality.
T6CON.BPS2
fGPT
2n : 1
Basic clock
Toggle FF
T5
Mode
Control
U/D
Interrupt Request
(T5IR)
T5IN
GPT2 Timer T5
Clear
T5EUD
Capture
CAPIN
CAPREL
Mode
Control
GPT2 CAPREL
T3IN/
T3EUD
Interrupt Request
(CRIR)
Reload
Interrupt Request
(T6IR)
Clear
U/D
T6
Mode
Control
GPT2 Timer T6
T6OTL
T6OUT
T6OUF
T6IN
T6EUD
MC_GPT0108_bldiax4.vsd
Figure 24 GPT2 Block Diagram (n = 1 … 4)
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Timer2 and Timer21
16
Timer2 and Timer21
Features
16.1
•
16-bit auto-reload mode
–
selectable up or down counting
•
•
One channel 16-bit capture mode
Baud-rate generator for U(S)ART
16.2
Introduction
Two functionally identical timers are implemented: Timer 2 and 21. The description refers to Timer 2 only, but
applies to Timer 21 as well.
The timer modules are general purpose 16-bit timer. Timer 2 can function as a timer or counter in each of its
modes. As a timer, it counts with an input clock of fsys/12 (if prescaler is disabled). As a counter, Timer 2 counts
1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is fsys/24 (if prescaler
is disabled).
16.2.1
Timer2 and Timer21 Modes Overview
Table 10 Timer2 and Timer21 Modes
Mode
Description
Auto-reload
Up/Down Count Disabled
•
•
•
Count up only
Start counting from 16-Bit reload value, overflow at FFFFH
Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
•
•
Programmable reload value in register RC2
Interrupt is generated with reload events.
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Timer2 and Timer21
Table 10 Timer2 and Timer21 Modes (cont’d)
Mode
Description
Auto-reload
Up/Down Count Enabled
•
•
•
Count up or down, direction determined by level at input pin T2EX
No interrupt is generated
Count up
–
–
–
Start counting from 16-Bit reload value, overflow at FFFFH
Reload event triggered by overflow condition
Programmable reload value in register RC2
•
Count down
–
–
–
Start counting from FFFFH, underflow at value defined in register RC2
Reload event triggered by underflow condition
Reload value fixed at FFFFH
•
•
•
•
•
•
•
Count up only
Channel capture
Start counting from 0000H, overflow at FFFFH
Reload event triggered by overflow condition
Reload value fixed at 0000H
Capture event triggered by falling/rising edge at pin T2EX
Captured timer value stored in register RC2
Interrupt is generate with reload or capture event
Datasheet
60
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Capture/Compare Unit 6 (CCU6)
17
Capture/Compare Unit 6 (CCU6)
17.1
Feature Set Overview
This section gives an overview over the different building blocks and their main features.
Timer 12 Block Features
•
•
Three capture/compare channels, each channel can be used either as capture or as compare channel
Generation of a three-phase PWM supported (six outputs, individual signals for High Side and low-side
switches)
•
•
•
•
•
•
•
•
•
16-bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of T12 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Multiple interrupt request sources
Hysteresis-like control mode
Timer 13 Block Features
•
•
•
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Concurrent update of T13 registers
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Additional Specific Functions
•
•
•
•
•
•
•
•
Block commutation for Brushless DC-drives implemented
Position detection via Hall-sensor pattern
Noise filter supported for position input signals
Automatic rotational speed measurement and commutation control for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Capture/Compare Unit 6 (CCU6)
17.2
Introduction
The CCU6 unit is made up of a Timer T12 Block with three capture/compare channels and a Timer T13 Block
with one compare channel. The T12 channels can independently generate PWM signals or accept capture
triggers, or they can jointly generate control signal patterns to drive AC-motors or inverters.
A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible
generation of interrupt request signals provide means for efficient software-control.
Note:
The capture/compare module itself is named CCU6 (capture/compare unit 6). A capture/compare
channel inside this module is named CC6x.
17.2.1
Block Diagram
The Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be
combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). The
Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns which
can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
CCU6 Module Kernel
Compare
CC60
CC61
CC62
1
1
1
T12SUSP
T13SUSP
Dead-
Time
Control
Multi-
channel
Control
Debug
Suspend
Trap
Control
T12
T13
fCC6
Clock
Control
CC63
1
3
2
2
2
3
1
SR[3:0]
Interrupt
Control
Input / Output Control
Port Control
CCU6_BD.vsd
P0. x
P1.x
P2.x
Figure 25 CCU6 Block Diagram
Datasheet
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Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
UART1/UART2
18
UART1/UART2
18.1
Features
•
Full-duplex asynchronous modes
–
–
8-Bit or 9-Bit data frames, LSB first
fixed or variable baud rate
•
•
•
•
Receive buffered (1 Byte)
Multiprocessor communication
Interrupt generation on the completion of a data transmission or reception
Baud-rate generator with fractional divider for generating a wide range of baud rates, e.g. 9.6kBaud,
19.2kBaud, 115.2kBaud, 125kBaud, 250kBaud, 500kBaud
•
•
Hardware logic for break and sync byte detection
for UART1: LIN support: connected to timer channel for synchronization to LIN baud rate
In all modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is
initiated in the modes by the incoming start bit if REN = 1.
The serial interface also provides interrupt requests when transmission or reception of the frames has been
completed. The corresponding interrupt request flags are TI or RI, respectively. If the serial interrupt is not
used (i.e., serial interrupt not enabled), TI and RI can also be used for polling the serial interface.
18.2
Introduction
The UART1/UART2 provide a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive
simultaneously. They are also receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first byte still has not been
read by the time reception of the second byte is complete, the previous byte will be lost. The serial port receive
and transmit registers are both accessed at Special Function Register (SFR) SBUF. Writing to SBUF loads the
transmit register, and reading SBUF accesses a physically separate receive register.
Datasheet
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
UART1/UART2
18.2.1
Block Diagram
UART disreq from SCU _DM
RI
TXD
RXD
TXD
SCU_D
M
Interrupt
Control
RXD_0
RXD_1
TI
URIOS
SCU_DM
P0.x
P1.x
P2.x
UART
Module
PortControl
fUART2
Clock
Control
Baud Rate
Generator
f
BR
Address
Decoder
RXDO _2
SCU_DM
AHB Interface
UART
GPIOs
Figure 26 UART Block Diagram
18.3
UART Modes
The UART1/UART2 can be used in four different modes. In mode 0, it operates as an 8-Bit shift register. In mode
1, it operates as an 8-Bit serial port. In modes 2 and 3, it operates as a 9-Bit serial port. The only difference
between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable
baud rate is set by the underflow rate on the dedicated baud-rate generator.
The different modes are selected by setting bits SM0 and SM1 to their corresponding values, as shown in
Table 11.
Mode 1 example: 8 data bits, 1 start bit, 1 stop bit, no parity selection, 16 times oversampled (majority decision
of bits 6, 7, 8), receive & transmit register double buffered, Tx/Rx IRQ(s).
Table 11 UART Modes
SM0
SM1
Operating Mode
Mode 0: 8-Bit shift register
Baud Rate
0
0
1
1
0
1
0
1
f
sys/2
Variable
sys/64 or fsys/32
Variable
Mode 1: 8-Bit shift UART
Mode 2: 9-Bit shift UART
Mode 3: 9-Bit shift UART
f
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
LIN Transceiver
19
LIN Transceiver
19.1
Features
General Functional Features
•
•
Compliant to LIN2.2 Standard, backward compatible to LIN1.3, LIN2.0 and LIN 2.1
Compliant to SAE J2602 (Slew Rate, Receiver hysteresis)
Special Features
•
•
•
•
•
Measurement of LIN Master baudrate via Timer 2
LIN can be used as Input/Output with SFR bits.
TxD Timeout Feature (optional, on by default)
Overcurrent limitation and overtemperature protection
LIN module fully resettable via global enable bit
Operation Modes Features
•
•
•
•
LIN Sleep Mode (LSLM)
LIN Receive-Only Mode (LROM)
LIN Normal Mode (LNM)
High Voltage Input / Output Mode (LHVIO)
Slope Modes Features
•
•
•
•
Normal Slope Mode (20 kbit/s)
Low Slope Mode (10.4 kbit/s)
Fast Slope Mode (62.5 kbit/s)
Flash Mode (115 kbit/s, 250 kbit/s)
Wake-Up Features
•
LIN Bus wake-up. The wake-up happens on the falling edge of the LIN signal, to allow wake-up and
decoding of the same frame. It is possible to enter the sleep mode also with LIN dominant (e.g. caused by
LIN shorted to GND).
19.2
Introduction
The LIN Module is a transceiver for the Local Interconnect Network (LIN) compliant to the LIN2.2 Standard,
backward compatible to LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller
and the physical network. The LIN bus is a single wire, bi-directional bus typically used for in-vehicle networks,
using baud rates between 2.4 kBaud and 20 kBaud. Additionally baud rates up to 62.5 kBaud are
implemented.
The LIN Module offers several different operation modes, including a LIN Sleep Mode and the LIN Normal
Mode. The integrated slope control allows to use several data transmission rates with optimized EMC
performance. For data transfer at the end of line, a Flash Mode up to 115 kBaud is implemented. This Flash
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
LIN Transceiver
Mode can be used for data transfer under special conditions for up to 250 kbit/s (in production environment,
point-to-point communication with reduced wire length and limited supply voltage).
19.2.1
Block Diagram
VS
LINTransceiver
30 k
LIN_CTRL_STS
LIN-FSM
LIN
CTRL
Driver +
Curr. Limit. +
TSD
TxD_1
from UART
STATUS
GND_LIN
Transmitter
PMU_LIN_WAKE_EN.LIN_EN
Filter
RxD_1
to UART
Filter
Receiver
LIN_Wake
Sleep Comparator
LIN_Block_Diagram_Customer.vsd
GND_LIN
Figure 27 LIN Transceiver Block Diagram
Datasheet
66
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
20
High-Speed Synchronous Serial Interface SSC1/SSC2
20.1
Features
•
Master and Slave Mode operation
–
Full-duplex or half-duplex operation
•
•
Transmit and receive double buffered
Flexible data format
–
–
–
–
Programmable number of data bits: 2 to 16 bits
Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit (MSB) shift first
Programmable clock polarity: idle low or high state for the shift clock
Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
•
•
•
Variable baud rate, e.g. 250kBaud - 8MBaud
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
–
–
–
–
On a transmitter empty condition
On a receiver full condition
On an error condition (receive, phase, baud rate, transmit error)
On a transfer complete condition
•
Port direction selection, see Chapter 14
20.2
Introduction
The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial
synchronous communication. The serial clock signal can be generated by the SSC internally (master mode),
using its own 16-Bit baud-rate generator, or can be received from an external master (slave mode). Data width,
shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible
devices or devices using other synchronous serial interfaces.
Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR
(MasterTransmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line
MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally
connected to the pin SCLK. Transmission and reception of data are double-buffered.
Datasheet
67
Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
20.2.1
Block Diagram
Figure 28 shows all functional relevant interfaces associated with the SSC Kernel.
MRSTA
MRSTB
EIR
MTSR
SCU_DM
Interrupt
Control
RIR
TIR
MTSRA
MTSRB
P0.x
P1.x
P2.x
SSC
Port
Control
Module
(Kernel)
MRST
fhw_clk
Clock
Control
SCLKA
SCLKB
Address
Decoder
SCLK
AHB Interface
Module
Product Interface
SSC_interface_overview.vsd
Figure 28 SSC Interface Diagram
Datasheet
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Rev.1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Measurement Unit
21
Measurement Unit
21.1
Features
•
•
•
•
1 x 10 Bit ADC with 13 Inputs including attenuator allowing measurement of high voltage input signals
Supply Voltage Attenuators with attenuation of VBAT_SENSE, VS, MONx, P2.x.
1 x 8 Bit ADC with 7 Inputs including attenuator allowing measurement of high voltage input signals
Supply Voltage Attenuators with attenuation of VS, VDDEXT, VDDP, VBG, VDDC, TSENSE_LS,
TSENSE_CENTRAL.
•
•
•
VBG monitoring of 8 Bit ADC to support functional safety requirements.
Temperature Sensor for monitoring the chip temperature and Low Side module temperature.
Supplement Block with Reference Voltage Generation, Bias Current Generation, Voltage Buffer for NVM
Reference Voltage, Voltage Buffer for Analog Module Reference Voltage and Test Interface.
21.2
Introduction
The measurement unit is a functional unit that comprises the following associated sub-modules:
Table 12 Measurement functions and associated modules
Module
Name
Modules
Functions
Central
Functions Unit
Bandgap reference circuit +
current reference circuit
The bandgap-reference sub-module provides two
reference voltages
1. an accurate reference voltage for the 10-bit and 8-
bit ADCs. A local dedicated bandgap circuit is
implemented to avoid deterioration of the reference
voltage arising e.g. from crosstalk or ground voltage
shift.
2. the reference voltage for the NVM module
10 Bit ADC (ADC1) 10-bit ADC module with 13
multiplexed analog inputs
VBAT_SENSE, VS and MONx measurement.
Six (5V) analog inputs from Port 2.x
8 Bit ADC (ADC2) 8-bit ADC module with 7
multiplexed inputs
VS/VDDEXT/VDDP/VBG/VDDC/TSENSE_LS and
TSENSE_CENTRAL measurement.
Temperature
Sensor
Temperature sensor readout
amplifier with two multiplexed
ΔVbe-sensing elements
Generates outputs voltage which is a linear function
of the local chip (Tj) temperature.
Measurement
Core Module
Digital signal processing and ADC 1. Generates the control signal for the 8-bit ADC 2 and
control unit
the synchronous clock for the switched capacitor
circuits (temperature sensor)
2. Performs digital signal processing functions and
provides status outputs for interrupt generation.
Datasheet
69
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Measurement Unit
21.2.1
Block Diagram
The Structure of the Measurement Functions Module is shown in the following figure.
VS
VDDC
ATT
x 0.047
x 0.047
x 0.039
x 0.039
VBAT_SENSE
CH0
CH1
CH2
CH3
CH4
CH5
CH6
MON1
MON2
MON3
MON4
x 0.039
x 0.039
x 0.039
x 0.219
DPP1
ADC 1
10
/
P2.0
P2.1
SFR
MUX
A
D
CH7
CH8
CH9
P2.2
P2.3
P2.6
P2.7
N.U.
x 0.219
x 0.219
x 0.219
x 0.219
CH10
CH11
CH12
x 0.219
10 Bit ADC + DPP
ATT
x 0.039
CH0
CH1
VBG
VDDEXT
VDDP
x 0.203
x 0.203
x 0.75
CH2
CH3
DPP2
PMU Bandgap
8
/
MUX
SFR
x 0.75
x 1
CH4
CH5
CH6
CH7
A
D
VDDC
Temperature
Sensor LS
Temperature
Sensor Central
x 1
ADC 2
rfu
rfu
CH8
8 Bit ADC + DPP
Measurement-Unit
Figure 29 TLE9844QX Measurement Unit-Overview
Datasheet
70
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Measurement Core Module (incl. ADC2)
22
Measurement Core Module (incl. ADC2)
22.1
Features
•
7 individually programmable channels split into two groups of user configurable and non user
configurable
•
•
Individually programmable channel prioritization scheme for measurement unit
Two independent filter stages with programmable low-pass and time filter characteristics for each
channel
•
Two channel configurations:
–
–
Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis
Two individually programmable trigger thresholds with limit hysteresis settings
•
•
Individually programmable interrupts and status for all channel thresholds
Operation down to reset threshold of entire system
22.2
Introduction
The basic function of this block is the digital postprocessing of several analog digitized measurement signals
by means of filtering level comparison and interrupt generation. The measurement postprocessing block is
built of seven identical channel units attached to the outputs of the 7-channel 8-bit ADC (ADC2). It processes
seven channels, where the channel sequence and prioritization is programmable within a wide range.
22.2.1
Block Diagram
3
/
MUX_SEL<2:0>
Channel Controller
(Sequencer)
SOS à EOC
ADC2 - SFR
10
/
VS
CH0
Digital Signal Processing
ADC2_OUT_CHx
1st Order IIR
VDDEXT
VDDP
CH1
CH2
CH3
1
/
+
-
ADC2
UP_X_STS
+ / -
+ / -
Calibration Unit:
TH_UP_CHx
VBG
8
10
/
8
/
MUX
VDDC
CH4
CH5
CH6
CH7
CH8
A
D
/
y= a + (1+b)*x
1
/
TH_LOW_CHx
-
Temperature Sensor LS
LOW_X_STS
+
Temperature Sensor Central
rfu
rfu
Figure 30 Module Block Diagram
Datasheet
71
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
10-Bit Analog Digital Converter (ADC1)
23
10-Bit Analog Digital Converter (ADC1)
23.1
Features
The basic function of this block is the digital postprocessing of several analog digitized measurement signals
by means of filtering, level comparison and interrupt generation. The measurement postprocessing block is
built of twelve identical channel units attached to the outputs of the 13-channel 10-bit ADC. It processes
twelve channels, where the channel sequence and prioritization is programmable within a wide range.
Functional Features
•
•
•
10 Bit SAR ADC with conversion time of 17 clock cycles
Programmable clock divider for sequencer and ADC
12 individually programmable channels (ch0..ch11):
–
–
6 HV Channels: VS, VBAT_SENSE, MON1...MON4
6 LV Channels: P2.1, P2.2, P2.3, P2.6, P2.7, P2.0
•
•
•
All channels are fully calibrated and user configurable
Individually programmable channel prioritization scheme for digital postprocessing (dpp)
Two independent filter stages with programmable low-pass and time filter characteristics for each
channel
•
Two channel configurations:
–
–
Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis
Two individually programmable trigger thresholds with limit hysteresis settings
•
•
Individually programmable upper threshold and lower threshold interrupts and status for all channel
thresholds
ADC reference completely integrated
Note:
In case the MONx should be evaluated by the ADC1, it is recommended to add 6.8nF capacitors close
to the MONx pin of the device, in order to build an external RC filter to limit the bandwidth of the input
signal.
Datasheet
72
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
10-Bit Analog Digital Converter (ADC1)
23.2
Introduction
23.2.1
Block Diagram
4
/
MUX_SEL<3:0>
Channel Controller
(Sequencer)
SOS à EOC
ADC - SFR
13*12
12*12
/
/
VBAT_SENSE
CH0
VS
MON1
MON2
MON3
MON4
P2.0
CH1
CH2
CH3
ADC_OUT_CHx
ADC_OUT_CHx
1st Order IIR
1
/
+
-
10 Bit ADC
UP_X_STS
+ / -
+ / -
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
Calibration Unit:
y= a + (1+b)*x
TH_UP _CHx
13*10
/
11*12
/
12*10
/
MUX
A
D
1
/
TH_LOW_CHx
-
LOW_X_STS
P2.1
+
P2.2
P2.3
P2.6
ADC1 - Digital Post-Processing
P2.7
Figure 31 Module Block Diagram
Datasheet
73
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Voltage Monitor Input
24
High-Voltage Monitor Input
24.1
Features
Features
•
•
•
•
4 High-voltage inputs with VS/2 threshold voltage
Wake capability for system stop mode and system sleep mode
Edge sensitive wake-up feature configurable for transitions from low to high, high to low or both directions
MON inputs can also be evaluated with ADC in Active Mode, using adjustable threshold values (see also
Chapter 23).
•
Selectable pull-up and pull-down current sources available
24.2
Introduction
This module is dedicated to monitor external voltage levels above or below a specified threshold. Each MONx
pin can further be used to detect a wake-up event by detecting a level change by crossing the selected
threshold. This applies to any power mode. Further more each MONx pin can be sampled by the ADC as analog
input.
24.2.1
Block Diagram
VS
MON
+
-
Filter
MON_int
MON
Logic
SFR
MONx_Input_Circuit_ext.vsd
Figure 32 Monitoring Input Block Diagram
Datasheet
74
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Side Switch
25
High-Side Switch
25.1
Features
The high-side switch is optimized for driving resistive loads. Only small line inductance are allowed. Typical
applications are single or multiple LEDs of a dashboard, switch illumination or other loads that require a high-
side switch.
A cyclic switch activation during Sleep Mode or Stop Mode of the system is also available.
Functional Features
•
•
•
•
•
•
•
Multi-purpose high-side switch for resistive load connections (only small line inductances are allowed)
Overcurrent limitation
Overcurrent detection with thresholds: 25 mA, 50 mA, 100 mA, 150 mA and automatic shutdown
Overtemperature detection and automatic shutdown
Open load detection in on mode with open load current of max. 1.5 mA.
Interrupt signalling of overcurrent, overtemperature and open load condition
Cyclic switch activation in Sleep Mode and Stop Mode with cyclic sense support and reduced driver
capability: max. 40 mA
•
•
•
PWM capability up to 25 kHz
Internal connection to System-PWM Generator (CCU6)
Slew rate control for low EMI characteristic
Applications hints
•
The voltage at HSx must not exceed the supply voltage by more than 0.3V to prevent a reverse current from
HSx to VS.
Datasheet
75
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Side Switch
25.2
Introduction
25.2.1
Block Diagram
VS
25 mA
50 mA
100 mA
150 mA
OCTH_SEL
OC-Detection
Cyclic-
Driver
SFR
ON
Driver
OLTH
1,5 mA
HS
OL-Detection
High Side
Figure 33 High-Side Module Block Diagram (incl. subblocks)
25.2.2
General
The high-side switch can generally be controlled in three different ways:
•
In Normal mode the output stage is fully controllable through the SFR Registers HSx_CTRL. Protection
functions as overcurrent, overtemperature and open load detection are available.
•
The PWM Mode can also be enabled by a HSx_CTRL - SFR bit. The PWM configuration has to be done in the
corresponding PWM Module. All protection functions are also available in this mode. The maximum PWM
frequency must not exceed 25 kHz (disabled slew rate control only).
•
The high-side switch provides also the possibility of cyclic switch activation in all low power modes (Sleep
Mode and Stop Mode). In this configuration it has limited functionality with limited current capability.
Diagnostic functions are not available in this mode.
Datasheet
76
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Low-Side Switch
26
Low-Side Switch
26.1
Features
The general purpose low-side switch is optimized to control an on-board relay. The low-side switch provides
embedded protection functions including overcurrent and overtemperature detection. The module is
designed for on-board connections.
Measures for standard ESD (HBM) and EMC robustness are implemented.
Functional Features
•
Multi purpose low-side switch optimized for driving relays:
–
–
simple relay driver
PWM relay driver
•
•
•
•
•
•
•
•
Integrated clamping for usage as a simple relay driver
overcurrent detection and automatic shutdown
overtemperature detection and automatic shutdown
interrupt signalling of overcurrent and overtemperature condition
open load detection with interrupt signalling
PWM capability up to 25 kHz (for inductive loads with external clamping circuitry only!)
Selectable PWM source: dedicated CCU6 channels
Current drive capability up to min. 270 mA
Applications hints
It is not recommended to use the switch in PWM Mode without external free wheeling diode.
•
Datasheet
77
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Low-Side Switch
LS
Clamp
XSFR
ON
Driver
270 mA
OC-Detection
Low Side
LSGND
Figure 34 Module Block Diagram
26.2
Functional Description
The low-side switches can generally be controlled in two different ways:
•
In normal mode the output stage is fully controllable through the SFR Registers LSx_CTRL. Protection
functions as overcurrent and overtemperature are available.
•
The PWM Mode can also be enabled by a LSx_CTRL - SFR bit. The PWM configuration has to be done in the
corresponding PWM Module (CCU6). All protection functions are also available in this mode. The maximum
PWM frequency must not exceed 25 kHz (fast slew rate only).
Datasheet
78
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Application Information
27
Application Information
Note:
27.1
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Relay Window Lift Application diagram
LIN
LIN
CLIN
RMONx
GND
GND
MON 1
MON 2
MON 3
R
VBAT_SENSE
CMONx
RMONx
CMONx
RMONx
CMONx
VBAT_SENSE
CVBAT_SENSE2
C
VBAT_SENSE1
VBAT
VS
C1VS
C2VS
RMONx
MON 4
CMONx
M+
LS 1
M
R2HS
M-
HS 2*
HS 1
LS 2
C1HS
C2HS
R1HS
PWM
C1HS
C2HS
VDDC
VDDP
CVDDC
Speed
Direction
CC60
CC61
VDDEXT
Double Hall
Sensor
e.g. TLE 4966
CVDDP
CVDDEXT
ApplicationDiagram_Arkas.vsd
* onlyavailable in product variantswith HS 2
Figure 35 Simplified Application Diagram Example
Note:
This is a very simplified example of an application circuit and bill of material. The function must be
verified in the actual application.
Datasheet
79
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Application Information
Table 13 External Component (BOM)
Symbol
C1VS
Function
Component
22 µF1)
100 nF2)3)
330 nF2)
100 nF2)3) + 330 nF2)
470 nF2)3) + 470 nF2)
3.9 kΩ
Capacitor 1 at VS pin
C2VS
Capacitor 2 at VS pin
CVDDEXT
CVDDC
Capacitor at VDDEXT pin
Capacitor at VDDC pin
Capacitor at VDDP pin
Resistor at MONx pin
CVDDP
RMONx
CMONx
Capacitor at MONx connector
Resistor at VBAT_SENSE pin
Capacitor 1at VBAT_SENSE pin
Capacitor 2 at VBAT_SENSE connector
Capacitor at LIN pin
6.8 nF4)
RVBAT_SENSE
CVBAT_SENSE1
CVBAT_SENSE2
CLIN
3.9 kΩ
10 nF2)
6.8 nF4)
220 pF
R1HS
Resistor at HS pin for LED
Resistor at HS pin
e.g. 2.7kΩ
160 Ω5)
R2HS
C1HS
Capacitor at HS pin
6.8nF2)
33nF4)
C2HS
Capacitor at HS connector
1) to be dimensioned according to application requirements
2) to reduce the effect of fast voltage transients of Vs, these capacitors should be placed close to the device pin
3) ceramic capacitor
4) for ESD GUN
5) optional, for short to battery protection, calculated for 24V (jump start)
27.2
Connection of N.C. / N.U. pins
The device contains several N.C. (not connected, no bond wire) and N.U. (not used, but bonded) pins.
Table 14 Recommendation for connecting N.C. / N.U. pins
type pin number
recommendation 1 recommendation 2
comment
N.C.
N.C.
27, 28, 29, 38, 40, 41
GND
10, 46
open
GND
neighboring high-voltage
pins
N.U.
N.U.
4
9
VS
open
GND
Datasheet
80
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Application Information
27.3
Connection of unused pins
Table 15 shows recommendations how to connect pins, in case they are not needed by the application.
Table 15 Recommendation for connecting unused pins
type
pin number
recommendation 1
(if unused)
recommendation 2
(if unused)
LIN
1
open
VS
HS1
3
open
MON
LS1, LS2
GPIO
5, 6, 7, 8
11, 12
GND
GNDLS
open + configure internal PU/PD
open
14, 15, 16, 17, 20, 22, 23, GND
24, 25, 26, 33, 34, 35, 36,
37, 39
external PU/PD
or
open + configure internal PU/PD
TMS
18
21
31
32
45
48
GND
open
open
GND
open
VS
Reset
P2/XTAL out
P2/XTAL in
VDDEXT
VBAT_SENSE
27.4
Connection of P0.2 for SWD debug mode
To enter the SWD debug mode, P0.2 needs to be 0 at the rising edge of the reset signal.
P0.2 has an internal pulldown, so it just needs to be ensured that there is no external 1 at P0.2 when the debug
mode is entered.
27.5
Connection of TMS
For the debug mode, the TMS pin needs to be 1 at the rising edge of the reset signal. This is controlled by the
debugger. The TMS pin has an internal PD.
To avoid the device entering the debug mode unintendedly in the final application, adding an external pull-
down additionally is recommended.
Datasheet
81
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Application Information
27.6
ESD Immunity According to IEC61000-4-2
Note:
Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) were performed. The
results and test condition are available in a test report. The achieved values for the test are listed in
Table 16 below.
Table 16 ESD “Gun Test”
Performed Test
Result
≥6
Unit
kV
Remarks
ESD at pin LIN, versus GND
ESD at pin LIN, versus GND
1)positive pulse
1)negative pulse
1)positive pulse
≤ -6
kV
ESD at pin VS, VBAT_SENSE, MONx, ≥6
kV
HS, versus GND
ESD at pin VS, VBAT_SENSE, MONx, ≤ -6
kV
1)negative pulse
HS, versus GND
1) ESD susceptibility “ESD GUN”, tested by external test house (IBEE Zwickau, EMC Test report Nr. 11-01-16), according
to "LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008" and "Hardware Requirements for
LIN, CAN and FlexRay Interfaces in Automotive Application – AUDI, BMW, Daimler, Porsche, Volkswagen – Revision 1.3
/ 2012"
Datasheet
82
Rev.1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28
Electrical Characteristics
This chapter includes all relevant Electrical Characteristics of the product TLE9844QX.
28.1
General Characteristics
28.1.1
Absolute Maximum Ratings
Table 17
Absolute Maximum Ratings1)
Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Voltages Supply Pins
VS voltage
VS,max
-0.3
-0.3
-0.3
–
–
–
40
V
V
V
Load dump
P_1.1.1
P_1.1.2
P_1.1.3
VDDP voltage
VDDP,max
VDDEXT,max
5.5
–
–
VDDEXT voltage
VS
+0.3
VDDC voltage
VDDC,max
-0.3
–
1.6
40
V
–
P_1.1.4
Voltages High Voltage Pins
Voltage at VBAT_SENSE pin
2)
VBAT_SENSE,m -28
–
–
V
V
–
P_1.1.5
P_1.1.6
ax
Voltage at HS pin
VHS,max
-0.3
VS
–
+0.3
Voltage at LIN pin
Voltage at MON_x pins
Voltage at LS pin
VLIN,max
VMON,max
VLS,max
-28
-28
-0.3
–
–
–
40
40
40
V
V
V
–
P_1.1.7
P_1.1.8
P_1.1.9
2)
Internal clamping
structure > 40V
Voltages GPIOs
Voltage on port pin P0.x, P1.x, VIO,max
P2.x, TMS and RESET
-0.3
–
–
–
VDDP
+0.3
V
VIN < VDDPmax
P_1.1.10
P_1.1.11
Currents
Injection current in Sleep Mode Ixx
on P0.x, P1.x, P2.x, TMS and
RESET
5
mA maximum allowed
injection current on
single pin or sum of
pins in Sleep Mode
and unpowered
device
Injection current on HS
IXLO
–
–
150
mA current flowing into P_1.1.12
HS pin (back supply
in case of short to
battery)
Datasheet
83
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 17
Absolute Maximum Ratings1) (cont’d)
Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Output current on LS
ILS
-300
–
–
mA current flowing out of P_1.1.13
LS pin, e.g. reverse
polarity event
(defined in LV124) or
ISO Pulse event
(defined in ISO 7637-
2)
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_1.1.14
P_1.1.15
Tstg
ESD Susceptibility HBM
all pins
VESD1
-2
–
–
–
2
kV
kV
V
JEDEC HBM3)
JEDEC HBM3)
P_1.1.16
P_1.1.17
P_1.1.18
ESD Susceptibility HBM
pins LIN vs. LINGND
VESD3
-6
6
ESD Susceptibility CDM
VESD_CDM
–500
500
Charged device
model, acc. JEDEC
JESD22-C101
ESD Susceptibility CDM
pins 1, 12, 13, 24, 25, 36, 37, 48
(corner pins)
VESD_CDM
–750
–
750
V
Charged device
model, acc. JEDEC
JESD22-C101
P_1.1.19
1) Not subject to production test, specified by design.
2) for -28V, external 3.9kΩ resistor is required to limit output current.
3) ESD susceptibility, “JEDEC HBM” according to ANSI/ESDA/JEDEC JS001 (1.5kΩ, 100pF).
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Datasheet
84
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.1.2
Functional Range
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Table 18
Functional Range
Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ.
Max.
28
Supply voltage in Active Mode
VS_AM
5.5
–
–
V
V
–
P_1.2.1
Extended Supply voltage in Active
Mode - Range 1
VS_AM_exten 28
40
Functional with P_1.2.12
parameter
d_1
deviation1)
Extended Supply voltage in Active
Mode with reduced functionality
(Microcontroller / Flash with full
operation) - Range 2
VS_AM_exten 3.0
–
5.5
V
Functional with P_1.2.2
parameter
d_2
deviation2)
Specified Supply voltage for LIN
Transceiver - Active Mode
VS_AM_LIN 5.5
–
–
18
28
V
V
Parameter
Specification
P_1.2.3
Extended Supply voltage for LIN
Transceiver - Active Mode
VS_AM_LIN_e 4.8
Functional with P_1.2.4
parameter
xtend
deviation
Extended Supply voltage for LIN &
Monitoring Input (MON) - Stop &
Sleep Mode
VS_SSM_LIN_ 3.6
–
5.5
V
Wakeup
functionality
ensured
P_1.2.13
MON_extend
Min. Supply voltage in Stop Mode
Min. Supply voltage in Sleep Mode
VS_Stopmin 3.0
VS_Sleepmin 3.0
–
–
–
–
–
–
–
–
V
–
P_1.2.5
P_1.2.6
P_1.2.7
P_1.2.8
P_1.2.9
P_1.2.10
P_1.2.11
–
V
–
3)
Supply Voltage transients slew rate dVS/dt
Output current on any GPIO OH , IOL
-5
5
V/µs
mA
mA
MHz
°C
3)
3)
3)
I
-10
-50
5
10
50
25
150
Output sum current for all GPIO pins IGPIO,sum
4)
Operating frequency
fsys
Junction Temperature
Tj
-40
–
1) This operation voltage range is only allowed for a short duration: tmax ≤ 400 ms.
2) Hall-Supply, ADC, SPI, UART, NVM, RAM, CPU fully functional and in spec down to 3V VS. Actuators (HS, LS) in VS range
from 3V < VS < 5.5V functional but some parameters can be out of spec
3) Not subject to production test, specified by design.
4) Function not specified when limits are exceeded.
Datasheet
85
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.1.3
Current Consumption
Table 19
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Current Consumption @VS pin
Current Consumption in IVs_freduced
–
–
15
mA fsys = 10 MHz
P_1.3.1
Active Mode
Vs= 13.5V
all digital modules enabled and
functional, ADCs converting in
sequencer mode, PLL running,
no loads on GPIOs, VDDEXT off,
LIN in recessive state (no
communication), HSx & LSx
enabled but off1)
Current Consumption in IVs
–
14
18
mA fsys = 25 MHz
P_1.3.22
Active Mode
Vs= 13.5V
all digital modules enabled and
functional, ADCs converting in
sequencer mode, PLL running,
no loads on GPIOs, VDDEXT off,
LIN in recessive state (no
communication), HSx & LSx
enabled but off
Current consumption in ISleep
Sleep Mode
–
–
–
–
15
25
µA System in Sleep Mode,
microcontroller not powered,
Wake capable via LIN and MON;
GPIOs open (no loads) or
connected to GND:
P_1.3.2
P_1.3.3
TJ = -40°C to 25°C;
Vs = 13.5V
Current consumption in ISleep(T_exte
µA System in Sleep Mode,
microcontroller not powered,
Wake capable via LIN and MON;
GPIOs open (no loads) or
connected to GND:
Sleep Mode (extended
nd)
Temperature Range)
TJ = 25°C to 85°C;
Vs = 13.5V
Datasheet
86
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 19
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Current consumption in ISleep(V_T_e
–
–
30
µA System in Sleep Mode,
microcontroller not powered,
Wake capable via LIN and MON;
GPIOs open (no loads) or
connected to GND:
P_1.3.4
Sleep Mode (extended
xtend)
Voltage and
Temperature Range)
TJ = -40°C to 85°C;
Vs = 5.5V to 18V
Current consumption in ISleep(V_T_e
–
–
40
µA System in Sleep Mode,
microcontroller not powered,
Wake capable via LIN and MON;
GPIOs open (no loads) or
connected to GND:
P_1.3.7
Sleep Mode (extended
xtend2)
Voltage and
Temperature Range 2)
TJ = -40°C to 85°C;
Vs = 3V to 28V
Current consumption in ICyclic
Sleep Mode with cyclic
wake
–
–
–
–
15
30
µA TJ = -40°C to 25°C;
Vs = 13.5V
P_1.3.5
P_1.3.6
during sleep period
Current consumption in ICyclic(T_exte
µA TJ = 25°C to 85°C;
Vs = 13.5V;
Sleep Mode with cyclic
nd)
wake (extended
during sleep period
Temperature Range)
Current consumption in IStop
Stop Mode
–
65
115
µA System in Stop Mode,
microcontroller not clocked,
Wake capable via LIN and MON;
GPIOs open (no loads) or
connected to GND; TJ = -
40°C to 85°C
P_1.3.19
Datasheet
87
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 19
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Current consumption in IStop_V_exte
–
3.5
4.0
mA System in Stop Mode,
microcontroller not clocked,
Wake capable via LIN and MON;
GPIOs open (no loads) or
connected to GND; TJ = -
40°C to 85°C;
P_1.3.21
Stop Mode
nd
Vs = 3V
Current consumption in IStop_CS
Stop Mode with cyclic
sense
–
70
125
µA System in Stop Mode (during stop P_1.3.20
period), microcontroller not
clocked, Wake capable via LIN
and MON; VDDEXT off; High Side
off;
GPIOs open (no loads) or
connected to GND or VDDP; TJ = -
40°C to 85°C;
Vs = 5.5V to 28V
1) Not subject to production test, specified by design
28.1.4
Thermal Resistance
Table 20
Thermal Resistance
Parameter
Symbol
Rth(JC)
Rth(JA)
Values
Unit Note or
Test Condition
Number
Min.
Typ.
Max.
Junction to Case
–
6
–
K/W 1) measured to
Exposed Pad
P_1.4.1
P_1.4.2
2)
Junction to Ambient
–
33
–
K/W
1) Not subject to production test, specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board . Board: 76.2x114.3x1.5mm3 with 2 inner
copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and
300mm2 cooling area on the bottom layer (70µm).
Datasheet
88
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.1.5
Timing Characteristics
The transition times between the system modes are specified here. Generally the timings are defined from the
time when the corresponding Bits in register PMCON0 are set until the sequence is terminated.
Table 21
System Timing1)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Wake-up over battery
tstart
–
–
–
–
–
–
1
ms
ms
µs
Battery ramp-up till MCU
reset is released; Vs > 3V and
RESET = ’1’
P_1.5.1
Sleep-Exit
tsleep - exit
1
rising/falling edge of any
wake-up signal (LIN, MON) till
MCU software running
2)
P_1.5.2
P_1.5.3
Sleep-Entry
tsleep -
330
entry
1) Not subject to production test, specified by design.
2) Wake events during Sleep-Entry are stored and lead to wake-up after Sleep Mode is reached.
Datasheet
89
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.2
Power Management Unit (PMU)
This chapter includes all electrical characteristics of the Power Management Unit
28.2.1
PMU Input Voltage VS
Table 22
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Required decoupling
capacitance
CVS1
0.1
–
–
µF
µF
1) ESR < 1Ω
P_2.1.12
P_2.1.13
2)
Required buffer capacitance CVS2
for stability (load jumps)
10
–
–
1) only min. value is tested.
2) Not subject to production test, specified by design.
28.2.2
PMU I/O Supply Parameters VDDP
Table 23
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
2)
Specified Output Current
IVDDP
0
–
–
50
–
mA
µF
P_2.1.1
P_2.1.2
Required decoupling
capacitance
CVDDP1
0.47
3)4) ESR < 1Ω
4)5)
Required buffer capacitance CVDDP2
for stability (load jumps)
0.47
4.9
–
1
µF
V
P_2.1.3
6)
Output Voltage including line VDDPOUT
and load regulation @ Active
Mode
5.0
5.1
I
< 90mA;Vs > 5.5V P_2.1.4
is only internal;Vs P_2.1.5
= 50mA; VS = 3V; P_2.1.6
load
6)
Output Voltage including line VDDPOUTST 4.5
and load regulation @ Stop
Mode
5.0
5.25
V
I
load
> 5.5V
OP
7)
Output Drop
Vs V DDPout
–
50
–
+400 mV
I
VDDP
Load Regulation
VVDDPLOR -50
50
mV
2 ... 90mA; C =
VDDP1+CVDDP2
P_2.1.7
C
Line Regulation
VVDDPLIR
VDDPOV
-50
–
–
50
mV
V
Vs= 5.5 ... 28V
P_2.1.8
P_2.1.9
Over Voltage Detection
5.14
5.4
Vs > 5.5V; Overvoltage
leads to SUPPLY_NMI
Datasheet
90
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 23
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Under Voltage Reset
VDDPUV
IVDDPOC
2.55 2.7
90
2.8
V
–
P_2.1.10
Over Current Diagnostic
–
200 mA
current including VDDC P_2.1.11
current consumption
1) currents used in this table are positive but flowing out the pin VDDP
2) Specified output current for port supply and additional other external loads connected to VDDP, excluding on-chip
current consumption.
3) only min. value is tested.
4) the total capacitance on VDDP must not exceed 2,2 µF
5) Not subject to production test, specified by design.
6) Load current includes internal supply.
7) Output drop for IVDDP plus internal supply
Datasheet
91
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.2.3
PMU Core Supply Parameters VDDC
Table 24
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Required decoupling capacitance CVDDC1
0.1
–
–
–
1
µF
µF
1) ESR < 1Ω
2)
P_2.2.1
P_2.2.2
Required buffer capacitance for CVDDC2
0.33
stability (load jumps)
Output Voltage including line
regulation @ Active Mode/Stop
Mode
VDDCOUT 1.44 1.5
1.56
V
Iload < 40mA; with
setting of VDDC
output voltage to
1.5V in Stop Mode
P_2.2.3
Load Regulation
VDDCLOR
-50
–
50
mV 2 ... 40mA; C =
VDDC1+CVDDC2
mV Vs= 5.5 ... 28V
P_2.2.4
P_2.2.5
C
Line Regulation
VDDCLIR
VDDCOV
-25
–
–
25
Over Voltage Detection
1.58
1.68
V
Overvoltage leads to P_2.2.6
SUPPLY_NMI
Under Voltage Reset
VDDVUV
IVDDCOC
1.10
40
–
–
1.19
80
V
–
–
P_2.2.7
P_2.2.8
Over Current Diagnostic
1) only min. value is tested.
mA
2) Not subject to production test, specified by design.
Datasheet
92
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.2.4
VDDEXT Voltage Regulator 5.0V
Table 25
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
VDDEXT Regulator Active Mode
Specified Output Current
IVDDEXT
0
–
20
mA
current flowing out P_2.3.1
of pin VDDEXT
Required decoupling
capacitance
CVDDEXT1
330
100
4.9
–
1000 nF
1000 nF
2) ESR < 1 Ω
P_2.3.2
3)
Required buffer capacitance for CVDDEXT2
stability (load jumps)
–
P_2.3.3
Output Voltage including line
and load regulation
VDDEXT
5.0
50
–
5.1
V
Iload < 20mA;Vs ≥ 5.5V P_2.3.4
Output Drop
Vs-VDDEXT
VDDEXTLOR
+400 mV
Iload < 20mA;
3V < Vs < 5.0V
P_2.3.5
P_2.3.6
Load Regulation
-80
20
mV
0.01 ... 20mA; C =
C
VDDEXT1+CVDDEXT2;
Vs≥ 5.5V
Line Regulation
VVDDEXTLIR -50
–
–
50
–
mV
dB
Vs= 5.5 ... 28V
3) Vs= 13.5V; f=0 ...
P_2.3.7
P_2.3.8
Power Supply Ripple Rejection PSSRVDDEXT 50
1KHz; Vr=2Vpp; 0 ...
20mA
4)
Under Voltage Shutdown
Over Current Limitation
VVDDEXTUV
IVDDEXTOC
1.55 1.9
100
2.2
V
P_2.3.9
3)
250 380
mA
kΩ
P_2.3.10
P_2.3.11
VDDEXT output discharge
resistance
RVDDEXT_DISC 16
20
24
–
HG
VDDEXT Regulator Low Current Mode
Specified Output Current
IVDDEXT_LCM
0
–
5
mA
V
–
P_2.3.28
Output Voltage including line
and load regulation - Load 1
VDDEXT_LCM1 4.6
5.0
5.1
Iload ≤ 5mA;Vs ≥ 5.5V P_2.3.29
Output Drop - Load 1
Vs-
VDDEXT_LCM1
50
–
+300 mV
Iload ≤ 5mA;
3V < Vs ≤ 5V;
C = CVDDEXT1+CVDDEXT2
P_2.3.30
P_2.3.31
Load Regulation - Load 1
VDDEXTLOR_L -250
250
mV
0 ... 5mA; C =
C
VDDEXT1+CVDDEXT2
;
CM1
Vs≥ 5.5V
Datasheet
93
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 25
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Line Regulation - Load 1
VVDDEXTLIR_L -300
–
300
mV
Iload ≤ 5mA;
Vs= 5.5 ... 28V
3) Vs= 13.5V; f=0 ...
1KHz; Vr=2Vpp; 0 ...
5mA
P_2.3.32
P_2.3.33
CM1
Power Supply Ripple Rejection PSSRVDDEXT_L 50
–
–
dB
CM
1) currents used in this table are positive but flowing out the pin VDDEXT
2) only min. value is tested.
3) Not subject to production test, specified by design.
4) When condition is met, the Bit VDDEXT_CTRL.VDDEXT_UV_IS will be set.
Datasheet
94
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.2.5
VPRE Voltage Regulator (PMU Subblock) Parameters
The PMU VPRE Regulator acts as a supply of VDDP and VDDC voltage regulators.
Table 26
Functional Range
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
1)
Specified Output Current
IVPRE
–
–
90
mA
P_2.4.1
1) Not subject to production test, specified by design.
28.2.5.1 Load Sharing of VPRE Regulator
The figure below shows the load sharing concept of VPRE regulator.
VS
VPRE
max. 90 mA
max. 50 mA
VDDP
VDDP - 5V
max. 90 mA
CVDDP
GNDA (Pin 43)
VDDC
max. 0 mA
VDDC - 1.5V
max. 40 mA
C
VDDC
GNDA (Pin 43)
Load Sharing VPRE
Load_Sharing_VPRE.vsd
Figure 36 Load Sharing of VPRE Regulator
Datasheet
95
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.2.6
Power Down Voltage Regulator (PMU Subblock) Parameters
The PMU Power Down voltage regulator consists of two subblocks:
•
•
Power Down Pre regulator: VDD5VPD
Power Down Core regulator: VDD1V5_PD (Supply used for GPUDATAxy registers)
Both regulators are used as purely internal supplies. The following table contains all relevant parameter:
Table 27
Functional Range
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
1)
Power-On Reset Threshold
VDD1V5_PD_ 1.2
–
1.5
V
I
= internal load P_2.5.1
load
connected to
VDD1V5_PD
RSTTH
1) Not subject to production test, specified by design
Datasheet
96
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.3
System Clocks
28.3.1
Electrical Characteristics Oscillators and PLL
Table 28
Electrical Characteristics System Clocks
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min.
PMU Oscillators (Power Management Unit)
Typ. Max.
Frequency of LP_CLK fLP_CLK
17
20
23
MHz this clock is used at startup P_3.1.1
and can be used in case the
PLL fails
Frequency of LP_CLK2 fLP_CLK2
70
100
130
kHz this clock is used for cyclic P_3.1.2
wake
CGU Oscillator (Clock Generation Unit Microcontroller)
Short term frequency fTRIMST
deviation1)
-0.4%
–
+0.4% MHz within any 100 ms, e.g.
after synchronization to a
LIN frame (includes PLL
accumulated jitter
P_3.1.3
value).Assuption: Tj is
varying < 30°C.
Absolute accuracy
fTRIMABSA
-1.49%
–
–
–
+1.49% MHz Including temperature&
lifetime drift and supply
variation
P_3.1.4
P_3.1.5
CGU-OSC Start-up time tOSC
10
µs
2) startup time OSC from
Sleep Mode, power supply
stable
PLL (Clock Generation Unit Microcontroller) 2)
VCO reference
frequency range
fREF
0.8
75
4
1
–
–
1.25
160
6
MHz
MHz
–
–
P_3.1.25
P_3.1.21
VCOfrequency(tuning) fVCO
range
Input frequency range fOSC
MHz see also specified limits for P_3.1.6
fVCO and fREF resulting in
restrictions for possible N
divider settings
XTAL1 input freq. range fOSCHP
4
–
6
MHz see also specified limits for P_3.1.23
fVCO and fREF resulting in
restrictions for possible N
divider settings
Datasheet
97
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 28
Electrical Characteristics System Clocks (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min.
Typ. Max.
Output freq. range
fPLL
15
–
40
MHz see also specified limits for P_3.1.7
VCO and fREF resulting in
f
restrictions for possible N
divider settings
Free-running
frequency
fVCOfree
–
34
–
–
MHz
ns
–
P_3.1.24
P_3.1.8
P_3.1.9
Input clock high/low thigh/low
time
10
-500
–
–
Peak period jitter
tjp
–
500
ps
for K=2; this parameter
value is only valid with the
combination of an external
quartz oscillator (e.g. 5
MHz)
Accumulated jitter
with external oscillator
jacc_ext
–
–
–
–
5
ns
µs
for K=2; this parameter
value is only valid with the
combination of an external
quartz oscillator (e.g. 5
MHz).
P_3.1.10
Lock-in time
tL
260
this parameter represents P_3.1.11
the duration from module
power-on to assertion of
lock signal
1) The typical oscillator frequency is 40 MHz
2) Not subject to production test, specified by design.
28.3.2 External Clock Parameters XTAL1, XTAL2
Table 29
Functional Range
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
2)
Input voltage range limits VIX1_SR
-1.7 + VDDC
–
1.7
V
P_3.2.1
for signal on XTAL1
Input voltage (amplitude) VAX1_SR
on XTAL1
0.3 x VDDC
–
–
V
3) Peak-to-peak P_3.2.2
voltage
XTAL1 input current
Oscillator frequency
IIL
–
4
–
–
±20
6
µA 0 V < VIN < VDDI
P_3.2.3
P_3.2.4
fOSC
MHz Clock signal
Datasheet
98
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 29
Functional Range (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Oscillator frequency
fOSC
4
–
6
MHz Crystal or
Resonator
P_3.2.5
4)5)
High time
Low time
Rise time
Fall time
High time
Low time
Rise time
Fall time
t1_VCOBYP
t2_VCOBYP
t3_VCOBYP
t4_VCOBYP
t1_PLLNM
t2_PLLNM
t3_PLLNM
t4_PLLNM
6
–
–
8
8
–
–
7
7
–
–
8
8
–
–
7
7
ns
P_3.2.6
P_3.2.7
P_3.2.8
P_3.2.9
P_3.2.10
P_3.2.11
P_3.2.12
P_3.2.13
4)5)
6
ns
4)5)
–
ns
4)5)
–
ns
5)6)
12
12
–
ns
5)6)
ns
5)6)
ns
5)6)
–
ns
1) Not subject to production test, specified by design.
2) Overload conditions must not occur on pin XTAL1.
3) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation
and the resulting voltage peaks must remain within the limits defined by VIX1.
4) this performance is only valid for Prescaler Mode (VCO Bypass mode).
5) tested with rectangular signal with VIN_Low = 0V to VIN_High = VDDC
6) this performance is only valid for PLL Normal Mode.
Datasheet
99
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.4
Flash Parameters
This chapter includes the parameters for the 64 KByte embedded flash module.
28.4.1
Flash Characteristics
Table 30
Flash Characteristics1)
VS = 5.5 V to 28 V,, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Number
Test Condition
Min. Typ. Max.
Programming time per 128 Byte
page
tPR
–
32)
3.5
ms
3V < VS < 28V
P_4.1.1
Erase time per sector/page
Data retention time
tER
–
42)
–
4.5
–
ms
3V < VS < 28V
P_4.1.2
P_4.1.3
tRET
20
years
1,000 erase /
program cycles
Data retention time
tRET
50
–
–
years
1,000 erase /
program cycles
Tj = 30°C3)
P_4.1.4
Flash erase endurance for user
sectors
NER
30
10
32
–
–
–
–
–
–
kcycles Data retention P_4.1.5
time 5 years
Flash erase endurance for security NSEC
cycles Data retention P_4.1.6
pages4)
time 20 years
5)
Drain disturb limit
NDD
kcycles
P_4.1.7
1) Not subject for production test, specified by design.
2) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few
system clock cycles. The requirement is only relevant for extremely low system frequencies.
3) Derived by extrapolation of lifetime tests.
4) Temperature: 25 °C
5) This parameter limits the number of subsequent programming operations within a physical sector without a given
page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly.
For normal sector erase/program cycles this limit will not be violated. For data sectors the integrated EEPROM
emulation firmware routines handle this limit automatically, for wordline erases in code sectors (without EEPROM
emulation) it is recommended to execute a software based refresh, which may make use of the integrated random
number generator NVMBRNG to statistically start a refresh.
Datasheet
100
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.5
Parallel Ports (GPIO)
28.5.1
Description of Keep and Force Current
VDDP
keeper
current
PU Device
PUDSEL
P1.x
P0.x
\PUDSEL
keeper
current
PD Device
VSS
Pull-Up-Down.vsd
Figure 37 Pull-Up/Down Device
UGPIO
Logical „1"
7.5 KOhm (equivalent)
(1.5V / 200uA) *)
VIH - VDDP
VIL - VDDP
undefined
Logical „0"
2.33 KOhm (equivalent)
(3.5V / 1.5mA) *)
I
-IPLF
-IPLK
Current_Diag.vsd
*) value for port 0 and 1, as example
Figure 38 Pull-Up Keep and Forced Current
Datasheet
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Rev. 1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
UGPIO
Logical „1"
undefined
Logical „0"
2.33 KOhm (equivalent)
(3.5V / 1.5mA) *)
VIH
VIL
7.5 KOhm (equivalent)
(1.5V / 200uA) *)
I
IPLK
IPLF
Current_Diag-Pull_down.vsd
*) value for port 0 and 1, as example
Figure 39 Pull-Down Keep and Force Current
28.5.2
DC Parameters Port 0, Port 1, TMS, Reset
Table 31
DC Characteristics Port0, Port1
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Input low voltage
Input low voltage
Input high voltage
Input high voltage
Input Hysteresis
VIL
-0.3
–
0.3 x VDDP
V
V
V
V
V
1) 4.5V ≤ VDDP
5.5V
2) 2.6V ≤ VDDP
4.5V
1) 4.5V ≤ VDDP
5.5V
2) 2.6V ≤ VDDP
4.5V
2) 4.5V ≤ VDDP
5.5V; Series
resistance = 0 Ω
2) 2.6V ≤ VDDP
≤
<
≤
<
≤
P_5.2.1
P_5.2.14
P_5.2.2
P_5.2.15
P_5.2.3
VIL_extend -0.3
0.42 x
VDDP
–
VIH
0.7 x VDDP
–
VDDP + 0.3
VIH_extend
HYS
–
0.52 x VDDP + 0.3
VDDP
0.11 x VDDP
–
–
–
Input Hysteresis
HYSextend
–
0.09 x
V
<
P_5.2.16
VDDP
4.5V; Series
resistance = 0 Ω
3) 4)
Output low voltage
Output low voltage
Output high voltage
Output high voltage
Input leakage current
VOL
VOL
VOH
VOH
IOZ2
–
–
–
–
–
–
1.0
0.4
–
V
V
V
V
I
I
I
I
≤ IOLmax
≤ IOLnom
≥ IOHmax
≥ IOHnom
P_5.2.4
P_5.2.5
P_5.2.6
P_5.2.7
P_5.2.8
OL
OL
OH
OH
3) 5)
3) 4)
3) 5)
–
VDDP - 1.0
VDDP - 0.4
-5
–
+5
µA 6) TJ ≤ 85°C,
0.45 V < VIN
< VDDP
Datasheet
102
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 31
DC Characteristics Port0, Port1 (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Input leakage current
IOZ2
-15
–
+15
µA TJ ≤ 150°C,
P_5.2.9
0.45 V < VIN
< VDDP
8)
Pull level keep current7)
Pull level force current7)
IPLK
IPLF
CIO
–
–
–
–
±200
–
µA
mA
pF
V
≥ VIH (up)
P_5.2.10
P_5.2.11
P_5.2.12
PIN
V
PIN ≤ VIL (dn)
8)
±1.5
–
V
≥ VIL (up)
PIN
VPIN ≤ VIH (dn)
2)
9)
Pin capacitance
10
Reset Pin Timing
Reset Pin Input Filter Time Tfilt_RESET
–
5
–
µs
P_5.2.13
1) Tested at VDDP = 5V, specified for 2.55V < VDDP < 5.1V.
2) Not subject to production test, specified by design.
3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for
pin groups must be respected.
4) Tested at 2.55V < VDDP < 5.1V, IOL = 4mA, IOH = -4mA, specified for 2.7V < VDDP < 5.1V.
5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→GND, VOH→VDDP).
Tested at 2.55V < VDDP < 5.1V, IOL = 1mA, IOH = -1mA.
6) The given values are worst-case values. In production test, this leakage current is only tested at 125°C; other values
are ensured by correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [°C]):
I
OZ = 0.05 × e(1.5 + 0.028×TJ) [µA]. For example, at a temperature of 95°C the resulting leakage current is 3.2 µA.
Leakage derating depending on voltage level (DV = VDDP - VPIN [V]):
OZ = IOZtempmax - (1.6 × DV) [µA]
I
This voltage derating formula is an approximation which applies for maximum temperature.
7) Negative current is representing pullup; positive current is representing pulldown
8) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the
default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the
enabled pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down.
These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general
purpose IO pins.
9) This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK
.
Note:
Operating Conditions apply.
Keeping signal levels within the limits specified in this table ensures operation without overload
conditions. For signal levels outside these specifications, also refer to the specification of the
overload current IOV
.
Datasheet
103
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 32
Current Limits for Port Output Drivers1)
Port Output Driver Mode
Maximum Output Current Output Current (IOLnom , - Number
(IOLmax , - IOHmax) IOHnom)
VDDP ≥ 4.5V 2.55V < VDDP VDDP ≥ 4.5V 2.55V <VDDP
< 4.5V
< 4.5V
1.0 mA
0.8 mA
0.15 mA
Strong Driver
Medium Driver
Weak Driver
5 mA
3 mA
1.6 mA
1.0 mA
0.25 mA
P_5.2.20
P_5.2.21
P_5.2.22
3 mA
1.8 mA
0.3 mA
0.5 mA
1) Not subject to production test, specified by design.
28.5.3
DC Parameters Port 2
These parameters apply to the IO voltage range, 2.55 V ≤ VDDP ≤ 5.5 V.
Note:
Operating Conditions apply.
Keeping signal levels within the limits specified in this table ensures operation without overload
conditions. For signal levels outside these specifications, also refer to the specification of the
overload current IOV
.
Table 33
DC Characteristics Port 2
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Input low voltage
Input low voltage
Input high voltage
Input high voltage
Input Hysteresis
VIL_P2
-0.3
–
0.3 x VDDP
V
V
V
V
V
1) 4.5V ≤ VDDP
5.5V
2) 2.6V ≤ VDDP
4.5V
1) 4.5V ≤ VDDP
5.5V
2) 2.6V ≤ VDDP
4.5V
≤
<
≤
<
≤
P_5.3.1
P_5.3.8
P_5.3.2
P_5.3.9
P_5.3.3
VIL_P2_exte -0.3
0.42 x
VDDP
–
nd
VIH_P2
0.7 x VDDP
–
VDDP + 0.3
VIH_P2_exte
–
0.52 x VDDP + 0.3
VDDP
nd
HYSP2
0.11 x VDDP
–
–
2) 4.5V ≤ VDDP
5.5V; Series
resistance = 0 Ω
Input Hysteresis
HYSP2_ext
–
0.09 x
–
V
2) 2.6V ≤ VDDP
<
P_5.3.10
VDDP
4.5V; Series
end
resistance = 0 Ω
Input leakage current
IOZ1_P2
-400
–
–
+400
+1
nA
uA
4.5V ≤ VDDP ≤ 5.5V P_5.3.4
TJ ≤ 85°C,
0 V < VIN < VDDP
Input leakage current
(extended temperature
range)
IOZ1_P2_T_ -1
2.6V ≤ VDDP < 4.5V P_5.3.11
TJ ≤ 150°C,
0 V < VIN < VDDP
extend
Datasheet
104
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 33
DC Characteristics Port 2 (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
Pull level keep current4)
Pull level force current4)
IPLK_P2
IPLF_P2
CIO_P2
–
–
–
–
±30
µA
µA
pF
V
≥ VIH (up)
P_5.3.5
P_5.3.6
P_5.3.7
3)
PIN
V
PIN ≤ VIL (dn)
3)
±750
–
–
V
≤ VIL (up)
PIN
V
PIN ≥ VIH (dn)
2)
Pin capacitance
10
(digital inputs/outputs)
1) Tested at VDDP = 5V, specified for 4.9V < VDDP < 5.1V.
2) Not subject to production test, specified by design.
3) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the
default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the
enabled pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down.
4) Negative current is representing pullup; positive current is representing pulldown
28.5.4
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of the TLE9844QX. All
parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.
Note:
Typical parameter values refer to room temperature and nominal supply voltage,
minimum/maximum parameter values also include conditions of minimum/maximum temperature
and minimum/maximum supply voltage. Additional details are described where applicable.
Table 34
Operating Condition Parameters
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Digital core supply voltage
VDDC
1.35
2.55
0
–
1.6
5.5
0
V
V
V
Full active mode P_5.4.1
1)
Digital supply voltage for IO pads VDDP
5.0
–
P_5.4.2
Digital ground voltage
VSS
Reference
voltage
P_5.4.3
Overload current
Overload current
IOV
IOV
- 5.0
- 2.0
–
–
5.0
5.0
mA Per IO pin2)3)
P_5.4.4
mA Per analog input P_5.4.5
pin2)3)
Overload positive current coupling KOVA
–
–
1.0
1.0
–
IOV > 03)
P_5.4.6
factor for analog inputs4)
x 10-6 x 10-4
Overload negative current coupling KOVA
factor for analog inputs
2.5
1.5
–
IOV < 03)
P_5.4.7
x 10-4 x 10-3
Datasheet
105
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 34
Operating Condition Parameters (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Overload positive current coupling KOVD
factor for digital
I/O pins
–
–
–
1.0
5.0
–
IOV > 03)
P_5.4.8
x 10-4 x 10-3
Overload negative current coupling KOVD
factor for digital
I/O pins
1.0
3.0
–
IOV < 03)
P_5.4.9
x 10-2 x 10-2
3)
Absolute sum of overload currents Σ|IOV
|
–
80
mA
P_5.4.10
1) Performance of pad drivers, A/D Converter, and Flash module depends on VDDP
.
If the external supply voltage VDDP becomes lower than the specified operating range, a power reset must be
generated. Otherwise, the core supply voltage VDDI may rise above its specified operating range due to parasitic
effects.
This power reset can be generated by the on-chip SWD. If the SWD is disabled the power reset must be generated by
activating the PORST input
2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the
specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin (IOV < 0). The absolute sum of input overload currents on all pins may
not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation under overload
conditions depends on the application.
Overload conditions must not occur on pin XTAL1 (powered by VDDIM).
3) Not subject to production test, specified by design.
4) An overload current (IOV) through a pin injects an error current (IINJ) into the adjacent pins. This error current adds to
that pin’s leakage current (IOZ). The value of the error current depends on the overload current and is defined by the
overload coupling factor KOV. The polarity of the injected error current is reversed from the polarity of the overload
current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| x KOV). The additional error current may distort the input voltage
on analog inputs.
Datasheet
106
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2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.6
LIN Transceiver
28.6.1
Electrical Characteristics
Table 35
Electrical Characteristics LIN Transceiver
Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Bus Receiver Interface
Receiver threshold voltage, Vth_dom 0.4 ×VS 0.45 ×VS 0.53 x VS
V
SAE J2602
P_6.1.1
recessive to dominant edge
Receiver dominant state
VBUSdom -27
–
0.4 ×VS
V
V
LIN Spec 2.2 (Par. 17) P_6.1.2
SAE J2602 P_6.1.3
Receiver threshold voltage, Vth_rec
0.47 x 0.55 ×VS 0.6 ×VS
dominant to recessive edge
VS
Receiver recessive state
Receiver center voltage
VBUSrec 0.6 ×VS
–
1.15 ×VS
V
V
1) LIN Spec 2.2 (Par. 18) P_6.1.4
2) LIN Spec 2.2 (Par. 19) P_6.1.5
VBUS_CNT 0.475
× VS
0.5 ×VS 0.525
× VS
Receiver hysteresis
VHYS
0.07
× VS
0.12 ×VS 0.175
× VS
V
3) LIN Spec 2.2 (Par. 20) P_6.1.6
Wake-up threshold voltage VBUS,wk 0.4 ×VS 0.5 ×VS 0.6 ×VS
V
–
P_6.1.7
Dominant time for bus
wake-up
tWK,bus
30
–
150
µs
including analog and P_6.1.8
digital filter time.
Digital filter time can
be adjusted by
PMU.CNF_WAKE_FILT
ER
Bus Transmitter Interface
Bus recessive output
voltage
VBUS,ro 0.8 ×VS
IBUS,sc 40
–
VS
V
VTxD = high Level
P_6.1.9
Bus short circuit current
100
150
mA Current Limitation for P_6.1.10
driver dominant state
driver on
V
BUS = 18 V; LIN Spec
2.2 (Par. 12)
Leakage current
Leakage current
Leakage current
IBUS_NO_ -1000 -450
0
µA
µA
VS = 0 V; VBUS = -12 V;
LIN Spec 2.2 (Par. 15)
P_6.1.11
P_6.1.12
P_6.1.13
GND
IBUS_NO_
–
10
–
20
–
VS = 0 V; VBUS = 18 V;
LIN Spec 2.2 (Par. 16)
BAT
IBUS_PAS_ -1
mA VS = 18 V; VBUS = 0 V;
LIN Spec 2.2 (Par. 13)
dom
Datasheet
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Rev. 1.1
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TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 35
Electrical Characteristics LIN Transceiver (cont’d)
Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Leakage current
IBUS_PAS_
–
–
20
µA
VS = 8 V; VBUS = 18 V;
P_6.1.14
LIN Spec 2.2 (Par. 14)
rec
Bus pull-up resistance
RBUS
20
30
47
kΩ Normal mode LIN Spec P_6.1.15
2.2 (Par. 26), also
present in Sleep mode
AC Characteristics - Transceiver Normal Slope Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
1
1
–
–
6
6
2
–
µs
µs
µs
LIN Spec 2.2
(Param. 31)
P_6.1.16
P_6.1.17
P_6.1.18
P_6.1.19
Propagation delay
bus recessive to RxD HIGH
td(H),R
0.1
LIN Spec 2.2
(Param. 31)
Receiver delay symmetry tsym,R
-2
tsym,R = td(L),R - td(H),R;
LIN Spec 2.2 (Par. 32)
4) duty cycle 1
THRec(max) = 0.744 ×VS;
THDom(max) =
Duty cycle D1
Normal Slope Mode
(for worst case at 20 kbit/s)
tduty1
0.396
0.581 ×VS;
t
bit = 50 µs;
D1 = tbus_rec(min) / 2 x tbit
;
LIN Spec 2.2 (Par. 27)
Duty cycle D2
tduty2
–
–
0.581
4) duty cycle 2
P_6.1.20
Normal Slope Mode
(for worst case at 20 kbit/s)
THRec(min) = 0.422 ×VS;
THDom(min) =
0.284 ×VS;
tbit = 50 µs;
D2 = tbus_rec(max) / 2 x tbit
;
LIN Spec 2.2 (Par. 28)
AC Characteristics - Transceiver Low Slope Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
0.1
-2
1
1
–
6
6
2
µs
µs
µs
LIN Spec 2.2
(Param. 31)
P_6.1.21
P_6.1.22
P_6.1.23
Propagation delay
bus recessive to RxD HIGH
td(H),R
LIN Spec 2.2
(Param. 31)
Receiver delay symmetry tsym,R
tsym,R = td(L),R - td(H),R
;
LIN Spec 2.2 (Par. 32)
Datasheet
108
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 35
Electrical Characteristics LIN Transceiver (cont’d)
Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Duty cycle D3
(for worst case at
10,4 kbit/s)
tduty1
0.417
–
–
4) duty cycle 3
THRec(max) = 0.778 ×VS;
THDom(max) =
P_6.1.24
0.616 ×VS;
t
bit = 96 µs;
D3 = tbus_rec(min) / 2 x tbit
;
LIN Spec 2.2 (Par. 29)
Duty cycle D4
(for worst case at
10,4 kbit/s)
tduty2
–
–
0.590
4) duty cycle 4
THRec(min) = 0.389 ×VS;
THDom(min) =
0.251 ×VS;
P_6.1.25
tbit = 96 µs;
D4 = tbus_rec(max) / 2 x tbit
;
LIN Spec 2.2 (Par. 30)
AC Characteristics - Transceiver Fast Slope Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
0.1
-2.0
1
1
–
6
µs
µs
µs
–
–
P_6.1.26
P_6.1.27
P_6.1.42
Propagation delay
bus recessive to RxD HIGH
td(H),R
6
Receiver delay symmetry- tsym,R
extended supply voltage
range
2.0
tsym,R = td(L),R - td(H),R;
Duty cycle D5
tduty1
0.395
–
–
4) duty cycle 5
P_6.1.29
(used for 62,5 kbit/s)
THRec(max) = 0.744 ×VS;
THDom(max) =
0.581 ×VS;
t
bit = 16µs;
D5 = tbus_rec(min) / 2 x tbit
;
Duty cycle D6
tduty2
–
–
0.581
4) duty cycle 6
P_6.1.30
(used for 62,5 kbit/s)
THRec(min)= 0.422 ×VS;
THDom(min)= 0.284 ×VS;
tbit = 16 µs;
D6 = tbus_rec(max) / 2 x tbit
;
AC Characteristics - Flash Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
0.1
-1.0
0.5
0.5
–
6
µs
µs
µs
–
–
P_6.1.31
P_6.1.32
P_6.1.44
Propagation delay
bus recessive to RxD HIGH
td(H),R
6
Receiver delay symmetry tsym,R
2.0
tsym,R = td(L),R - td(^H),R;
Datasheet
109
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 35
Electrical Characteristics LIN Transceiver (cont’d)
Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Duty cycle D7
tduty1
0.395
–
–
5)duty cycle D7
P_6.1.34
(for worst case at
115 kbit/s)
THRec(max) = 0.744 ×VS;
THDom(max) =
for +1 µs Receiver delay
symmetry
0.581 ×VS; tbit = 8.7 µs;
D7 = tbus_rec(min) / 2 x tbit
;
(used for 250 kbit/s
programming)
Duty cycle D8
tduty2
–
–
0.578
5)duty cycle D8
P_6.1.35
(for worst case at
115 kbit/s)
THRec(min) = 0.422 ×VS;
THDom(min) =
for +1 µs Receiver delay
symmetry
0.284 ×VS; tbit = 8.7 µs;
D8 = tbus_rec(max) / 2 x tbit
;
(used for 250 kbit/s
programming)
6)
LIN input capacity
CLIN_IN
ttimeout
–
6
15
12
30
20
pF
P_6.1.36
P_6.1.37
TxD dominant time out
ms VTxD = 0 V
Thermal Shutdown (Junction Temperature)
6)
Thermal shutdown temp. TjSD
Thermal shutdown hyst. ΔT
160
–
180
10
200
–
°C
P_6.1.38
P_6.1.39
6)
K
1) Maximum limit specified by design.
2) VBUS_CNT = (Vth_dom +Vth rec)/2
3) VHYS = VBUSrec - VBUSdom
4) Bus load concerning LIN Spec 2.2:
Load 1 = 1 nF / 1 kΩ = CBUS / RBUS
Load 2 = 6.8 nF / 660 Ω = CBUS / RBUS
Load 3 = 10 nF / 500 Ω = CBUS / RBUS
5) Bus load
Load 1 = 1 nF / 500 Ω = CBUS / RBUS
6) Not subject to production test, specified by design.
Datasheet
110
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.7
High-Speed Synchronous Serial Interface
28.7.1
SSC Timing
The table below provides the SSC timing in the TLE9844QX.
Table 36 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
1) 2 * TSSC
10
Typ.
Max.
2)
2)
2)
2)
SCLK clock period
t0
t1
t2
t3
–
–
–
–
–
–
–
–
V
V
V
V
> 2.7 V
> 2.7 V
> 2.7 V
> 2.7 V
P_7.1.1
P_7.1.2
P_7.1.3
P_7.1.4
DDP
DDP
DDP
DDP
MTSR delay from SCLK
MRST setup to SCLK
MRST hold from SCLK
ns
ns
ns
10
15
1) TSSCmin = TCPU = 1/fCPU. If fCPU = 20 MHz, t0 = 100 ns. TCPU is the CPU clock period.
2) Not subject to production test, specified by design.
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
valid
MRST1)
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 40 SSC Master Mode Timing
Datasheet
111
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.8
Measurement Unit
28.8.1
Electrical Characteristics
Table 37
Supply Voltage Signal Conditioning
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
ADC1 - Battery / Supply Voltage Measurement VBAT_SENSE / VS
Input to output voltage
attenuation:
ATTVBAT_SENSE , –
ATTVS
0.047
–
–
P_8.1.10
P_8.1.11
P_8.1.12
VBAT_SENSE / VS
Nominal operating input VBAT_SENSE,
voltage range VBAT_SENSE
VS
0
–
–
25.7
7
V
2) Max. value
corresponds to typ. ADC
full scale input;
/
range, VS, range
Accuracy of VBAT_SENSE / VS ∆VBAT_SENSE_IIR, -200
after calibration - with IIR VS_IIR
filter
200 mV Vs= 5.5V to 18V,
Tj = -40..125°C,
fADCI = fsys_max
ADC1_FILTCOEFF0_11.C
Hx = 11’b.
Accuracy of VBAT_SENSE / VS ∆VBAT_SENSE, VS -300
after calibration
–
300 mV Vs= 5.5V to 18V,
Tj = -40..125°C,
P_8.1.36
fADCI = fsys_max
.
ADC1 - Monitoring Input Voltage Measurement VMONx
Input to output voltage
attenuation:
VMONx
ATTVMONx
–
0.039
–
–
P_8.1.13
P_8.1.14
P_8.1.33
Nominal operating input VMONx,range
voltage range VMONx
0
–
–
31.0
5
V
2) Max. value
corresponds to typ. ADC
full scale input;
Accuracy of VMONx sense
after calibration - with IIR
filter
ΔVMONx_IIR
-241
241 mV Vs= 5.5V to 18V,
Tj = -40..125°C,
fADCI = fsys_max
ADC1_FILTCOEFF0_11.C
Hx = 11’b.
Accuracy of VMONx sense
after calibration -
ΔVMONx_ROR_IIR -170
–
170 mV 2) Vs= 5.5V to 18V,
Tj = -40..125°C,
P_8.1.20
Reduced Operating
Range - with IIR filter
VMONx,range= 0V to 12V,
fADCI = fsys_max,
ADC1_FILTCOEFF0_11.C
Hx = 11’b.
Datasheet
112
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 37
Supply Voltage Signal Conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Accuracy of VMONx sense
after calibration
ΔVMONx
-361
–
361 mV 2) Vs= 5.5V to 18V,
Tj = -40..125°C,
P_8.1.37
fADCI = fsys_max.
ADC1 - Port 2.x Voltage Measurement V2.x
Input to output voltage
attenuation:
VPort2.x
ATT2.x
–
0.219
–
–
P_8.1.15
P_8.1.16
P_8.1.34
Nominal operating input VPort2.x,range
voltage range VPort2.x
0
–
–
5.53
V
2) Max. value
corresponds to typ. ADC
full scale input;
1)
Accuracy of VPort2.x sense ΔVPort2.x_IIR
after calibration - with IIR
filter
-43
43
mV Vs= 5.5V to 18V,
Tj = -40..125°C,
fADCI = fsys_max
ADC1_FILTCOEFF0_11.C
Hx = 11’b.
Accuracy of VPort2.x sense ΔVPort2.x
after calibration
-67
–
67
–
mV Vs= 5.5V to 18V,
Tj = -40..125°C,
ADCI = fsys_max
P_8.1.38
f
.
ADC2 - Supply Voltage Measurement VS
Input to output voltage
ATTVS_ADC2
–
3
0.039
–
–
P_8.1.1
P_8.1.2
attenuation:
VS
Nominal operating input VS,ADC2
voltage range VS
31.0
5
V
2) Max. value
corresponds to typ. ADC
full scale input; 3V < VS <
28V
Accuracy of VS after
calibration
∆VS,ADC2
-270
–
270 mV Vs= 5.5V to 18V,
Tj = -40..125°C
P_8.1.3
ADC2 - VDDEXT Voltage Measurement VDDEXT
Input to output voltage
attenuation:
VDDEXT
ATTVDDEXT
–
0.203
–
–
–
P_8.1.17
P_8.1.18
Nominal operating input VDDEXT,range
0
5.96
V
2) Max. value
voltage range VDDEXT
corresponds to typ. ADC
full scale input;
ADC2 - Pad Supply Voltage Measurement VVDDP
Input-to-output voltage ATTVDDP
–
0.203
–
–
P_8.1.4
attenuation:
VDDP
Datasheet
113
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 37
Supply Voltage Signal Conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Nominal operating input VDDP,range
0
–
5.96
V
2) Max. value
P_8.1.5
voltage range VDDP
corresponds to typ. ADC
full scale input;
ADC2 - Reference Voltage Measurement VBG
Input-to-output voltage ATTVBG
attenuation:
VBG
–
0.75
–
–
–
P_8.1.6
P_8.1.7
P_8.1.39
Nominal operating input VBG,range
voltage range VBG
0.8
VDD
C -
0.1V
V
V
2) Max. value
corresponds to typ. ADC
full scale input;
Value of ADC2-VBG
measurement after
calibration
VBG_PMU
0.90 1.0
1.1
–
ADC2 - Core supply Voltage Measurement VDDC
Input-to-output voltage ATTVDDC
attenuation:
VDDC
–
0.75
–
–
–
P_8.1.8
P_8.1.9
Nominal operating input VDDC,range
voltage range VDDC
0.6
VDD
C +
0.1V
V
2) Max. value
corresponds to typ. ADC
full scale input;
1) This typical theoretical full scale is not reached as the internal ESD Clamping Structure limits the voltage to max. 5.2V.
2) Not subject to production test, specified by design.
Datasheet
114
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.8.2
Central Temperature Sensor Module
28.8.2.1 Electrical Characteristics
Table 38
Electrical Characteristics Temperature Sensor Module
VS = 5.5 V to 28 V, , Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Output voltage VTEMP at
T0=0°C (273 K)2)
a
–
0.628
–
V
T0=0°C (273 K)
P_8.2.1
Temperature sensitivity b 2)
b
–
2.31
–
mV/K
°C
P_8.2.2
P_8.2.3
P_8.2.4
P_8.2.5
Accuracy_1
Acc_1
Acc_2
Acc_3
-10
-15
-5
–
–
–
10
15
5
1) -40°C < Tj < 85°C
125°C < Tj < 175°C
2) 85°C < Tj < 125°C
Accuracy_2
°C
Accuracy_3
°C
1) Accuracy with reference to on-chip temperature calibration measurement.
2) Not subject to production test, specified by design.
Datasheet
115
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.9
ADC1 (10-Bit)
28.9.1
ADC1 Reference Voltage
Table 39
DC Specifications
VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note or
Test Condition
Number
Min.
-1%
-1%
Max.
+1%
+1%
Reference Voltage
Temperature Drift
VBG
1.211
V
V
–
–
P_9.1.10
P_9.1.11
∆VBG
28.9.2
Electrical Characteristics ADC1 (10-Bit)
These parameters describe the conditions for optimum ADC performance.
Note:
Operating Conditions apply.
Table 40
A/D Converter Characteristics
VS = 5.5 V to 28 V, , Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
40
1)
Analog clock frequency
DNL error
fADCI
5
–
–
–
–
–
–
–
MHz
LSB
LSB
P_9.2.1
P_9.2.8
P_9.2.9
P_9.2.10
2)
EADNL
EAINL
EAGAIN
± 2
INL error
± 3
–
Gain error
± 1.2
% of 4)calibrated;
FSR Gain Error is
3)
calibrated by
implemented
calibration unit
Offset error
EAOFF
–
–
–
–
± 2.5
± 10
LSB 4)calibrated;
Offset Error is
calibrated by
P_9.2.11
P_9.2.33
implemented
calibration unit
Total unadjusted error
EATUE
LSB already
calibrated
Datasheet
116
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 40
A/D Converter Characteristics (cont’d)
VS = 5.5 V to 28 V, , Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Input referred noise
VNoise_LSB
–
–
1.5
LSB
P_9.2.34
rms 4)Tj = 25°C; this
value is
determined out
of 4 consecutive
measurements
which are
averaged.
4)
Cross-coupling
Attenuation between LV
Channels
EACCOUP
–
±1
± 2
LSB
–
P_9.2.12
4)
4)
Input capacitance of
a HV analog input
CAINT_HVI
CAINT_LVI
–
–
–
–
200
200
fF
fF
P_9.2.13
P_9.2.19
Input capacitance of
a LV analog input
1) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting.
2) this parameter is measured with disabled hardware calibration
3) this Gain error is calibrated by IFX end of line
4) Not subject to production test
Datasheet
117
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.10
High-Voltage Monitoring Input
28.10.1 Electrical Characteristics
Table 41
Electrical Characteristics Monitoring Input
VS = 5.5 V to 28 V; Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
MON Input Pin characteristics
Wake-up/monitoring VMONth
threshold voltage
0.4*Vs 0.5*Vs 0.6*Vs
V
V
without external
serial resistor Rs (with
Rs:DV = IPD/PU * Rs);
P_10.1.1
Threshold hysteresis
VMONth,hys 0.015* 0.06*Vs 0.10*Vs
in all modes; without P_10.1.2
externalserialresistor
Vs
Rs (with Rs:dV = IPD/PU
Rs); 5.5 V < VS < 18 V
*
Threshold hysteresis- VMONth,hys 0.02*Vs 0.06*Vs 0.12*Vs
V
in all modes; without P_10.1.7
externalserialresistor
extended supply
_VS_extende
voltage range
Rs (with Rs:dV = IPD/PU
Rs); 18 V < VS < 28 V
*
d
Pull-up current
IPU, MON
IPD, MON
-20
5
-10
10
–
-5
20
2
µA
µA
µA
0.6*Vs;
P_10.1.3
P_10.1.4
P_10.1.5
Pull-down current
0.4*Vs;
Input leakage current ILK,MON
-2
0 V < VMON_IN < 28 V
Timing
1)
Wake-up filter time
tFT,MON
-
20
-
µs
P_10.1.6
1) With pull-up, pull down current disabled.
Datasheet
118
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.11
High Side Switches
28.11.1 Electrical Characteristics
Table 42
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
PWM frequency of HS with fPWM_W_SR
Slew Rate Control
0
–
10
kHz 1) Frequency must be
configured in the PWM
Generator
P_11.1.1
P_11.1.2
PWM frequency of HS
fPWM_W/O_SR
0
–
252) kHz 1) Frequency must be
configured in the PWM
Generator
without Slew Rate Control
Output HS
ON-State Resistance
RON
2
10
–
18
2
Ω
5.5 V < VS < 28V,
Ids=100mA,
Tj = 25 °C
P_11.1.3
P_11.1.4
P_11.1.5
P_11.1.6
P_11.1.7
P_11.1.8
Output leakage Current
Ileakage
–
µA
Output OFF
0 V < VXLO < VS;
Tj ≤ 150 °C
Output Slew Rate (rising)
with slow Slew Rate setting
(Slew Rate 1)
SRraise_SR1
SRfall_SR1
SRraise_SR2
SRfall_SR2
tIN-HS_SR1
1
–
10
-1
V/µs 20% to 80% of VS
VS = 9 to 18V
RL =300Ω1)
Output Slew Rate (falling)
with slow Slew Rate setting
(Slew Rate 1)
-10
18.0
-43.4
–
V/µs 80% to 20% of VS
VS = 9 to 18V
RL =300Ω1)
Output Slew Rate (rising)
with fast Slew Rate setting
(Slew Rate 2)
–
55.0 V/µs 20% to 80% of VS
VS = 9 to 18V
RL =300Ω1)
Output Slew Rate (falling)
with fast Slew Rate setting
(Slew Rate 2)
–
-12.5 V/µs 80% to 20% of VS
VS = 9 to 18V
RL =300Ω1)
Turn ON Delay time (Slew
Rate 1)
–
1
–
–
4.5
15
µs
µs
ON = 1 to 20% of VS
RL =300Ω
P_11.1.9
Turn ON time (Slew Rate 1) tON_SR1
VS = 9 to 18V
HS_ON=1 to 80% of VS
RL =300Ω
P_11.1.10
Tj =25°C
Datasheet
119
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 42
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Turn OFF time (Slew Rate 1) tOFF_SR1
1
–
15
µs
VS = 9 to 18V
HS_ON= 0 to 20% of VS
RL =300Ω;
P_11.1.11
Tj =25°C
Turn ON Delay time (Slew
Rate 2)
tIN-HS_SR2
–
–
–
1
3
µs
µs
ON = 1 to 20% of VS
RL =300Ω
P_11.1.55
P_11.1.56
Turn ON time (Slew Rate 2) tON_SR2
Turn OFF time (Slew Rate 2) tOFF_SR2
Over-current detection
–
VS = 9 to 18V
HS_ON=1 to 80% of VS
RL =300Ω
Tj =25°C
–
–
3
µs
VS = 9 to 18V
HS_ON= 0 to 20% of VS
RL =300Ω;
P_11.1.57
Tj =25°C
Overcurrent threshold 0
Iocth0
26
–
42
14
60
17
60
–
mA VS = 13.5V
HSx_OC_SEL =00
mA 1) HSx_OC_SEL =00
P_11.1.12
P_11.1.13
P_11.1.14
P_11.1.15
P_11.1.16
P_11.1.17
P_11.1.18
P_11.1.19
P_11.1.20
Overcurrent threshold 0
hysteresis
Iocth0,hyst
Iocth1
Iocth1,hyst
Iocth2
Iocth2,hyst
Iocth3
Iocth3,hyst
tocft
Overcurrent threshold 1
51
–
80
–
mA VS = 13.5V
HSx_OC_SEL =01
mA 1) HSx_OC_SEL =01
Overcurrent threshold 1
hysteresis
Overcurrent threshold 2
101 123 150 mA VS = 13.5V
HSx_OC_SEL =10
mA 1) HSx_OC_SEL =10
Overcurrent threshold 2
hysteresis
–
25
–
Overcurrent threshold 3
151 176 210 mA VS = 13.5V
HSx_OC_SEL =11
mA 1) HSx_OC_SEL =11
Overcurrent threshold 3
hysteresis
–
8
30
–
–
Over-current shutdown
response time
80
µs
1) VS = 13.5V,
RL =100Ω, HS_ON to
OC_SD (including switch-
on time)
ON-state open load detection
Open load threshold
Hysteresis
IOLONth
IOLONhys
0.46 1.32 2.2
mA
–
–
P_11.1.21
P_11.1.22
35
155 300 µA
Datasheet
120
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 42
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Cyclic sense mode
Current capability
IHS max
40
–
–
mA Sleep Mode / Stop Mode P_11.1.23
sleep_pd
ON-State Resistance
RON,static
–
1
–
–
40
–
Ω
Ids = 40mA,
P_11.1.24
P_11.1.25
Output Slew Rate (rising)
SRrise_cyc
V/µs 20% to 80% of VS
VS = 9 to 18V
RL =300Ω
Output Slew Rate (falling)
SRfal_cycl
–
–
-1
V/µs 80% to 20% of VS
VS = 9 to 18V
P_11.1.26
RL =300Ω
Delay Time CYCLIC_ON-HS tIN_cyc
–
–
–
–
2
µs
µs
ON =1 to 20% of VS
RL=300Ω
P_11.1.27
P_11.1.28
Turn-ON time
Turn-OFF time
tON_cyc
15
VS = 9 to 18V
ON=1 to 80%
RL =300Ω
tOFF_cyc
–
–
15
µs
VS = 9 to 18V
ON=0 to 20% of VS
RL =300Ω;
P_11.1.29
Tj=25°C
1) Not subject to production test, specified by design.
2) this is an additional requirement which refers to a 47Ohm series resistor to charge an external power mos gate.
Datasheet
121
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
28.12
Low Side Switches
28.12.1 Electrical Characteristics
Table 43
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
PWM Frequency of LS
Overcurrent Limitation
ON-State Resistance
Leakage Current
fPWM
–
–
25
kHz 1) RL =270Ω
P_12.1.1
P_12.1.2
P_12.1.3
P_12.1.5
ILSTyp
RON
270 300 330 mA
1
–
4
–
10
2
Ω
Ids =100mA;
Ileakage
µA 0 V < VLS < VS;
Tj < 85°C
Turn ON Delay time, slow mode tdOn-LS
Turn ON Delay time, PWM mode tdOn,f-LS
–
–
–
1
50
µs
2) LS_ON=1 to 0.9*Vs
VS=13.5V, RL =270Ω
P_12.1.6
P_12.1.7
P_12.1.8
P_12.1.9
P_12.1.10
P_12.1.11
P_12.1.12
P_12.1.13
P_12.1.14
P_12.1.15
P_12.1.16
P_12.1.17
–
0.5
µs
LS_ON=1 to 0.9*Vs
VS=13.5V, RL =270Ω
Turn ON fall time, PWM mode
Turn ON fall time, slow mode
tONF,PWM
tONF,Slow
–
1.25 µs
VLS 0.9*Vs to 0.1*Vs
VS=13.5V, RL =270Ω
2)
–
100 150 µs
V 0.9*Vs to 0.1*Vs
LS
VS=13.5V, RL =270Ω
2) LS_ON=0 to 0.1*Vs
VS=13.5V, RL =270Ω
Turn OFF Delay time, slow mode tdOff-LS
Turn OFF Delay time, PWM mode tdOff,f-LS
Turn OFF Rise time, PWM mode tOFFR,PWM
Turn OFF Rise time, slow mode tOFFR,Slow
–
–
–
1
50
2
µs
µs
–
LS_ON=0 to 0.1*Vs
VS=13.5V, RL =270Ω
–
1.25 µs
VLS 0.1*Vs to 0.9*Vs;
VS=13.5V, RL =270Ω
2)
–
100 150 µs
V 0.1*Vs to 0.9*Vs;
LS
VS=13.5V, RL =270Ω
ton(dig) = 2µs1)
Minimum Duty Cycle Pulse
Width variation
tonMIN
1.5
–
2
3.5
–
µs
µs
V
Typical (systematic) Pulse Width d tonTYP
increase LS_ON to VLS
1.25
50
–
ton(dig) = 2µs1)
Zener Clamp Voltage
VAZ
–
–
values are valid at
Tj = 25°C
Clamping Energy (repetitive)
Eclamp
–
2
mJ 1)3) 1.000.000 cycles, @
max = 90mA
I
Datasheet
122
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Electrical Characteristics
Table 43
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Clamping Energy
Eclamp
Eclamp
–
–
14
mJ 1)3) 10 cycles, Tstart =
P_12.1.18
P_12.1.19
25°C, @ Imax = 230mA
mJ 1)3) 10 cycles, Tstart =
Clamping Energy (single), hot
–
–
7
85°C, @ Imax = 230mA
1) Not subject to production test, specified by design.
2) Static ON mode (no PWM)
3) valid for one low-side, not for both at the same time
Datasheet
123
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Package Outlines
29
Package Outlines
0ꢀ9 MAXꢀ
(0ꢀ65)
11 x 0ꢀ5 = 5ꢀ5
0ꢀ5
0ꢀ1
7
A
0ꢀ03
6ꢀ8
0ꢀ1
+0ꢀ031)
2)
37
B
36
25
24
48x
0ꢀ08
48
13
1
12
Index Marking
48x
0ꢀ1
0ꢀ4 x 45°
0ꢀ05
Index Marking
0ꢀ23
(0ꢀ35)
M
A B C
(0ꢀ2)
0ꢀ05 MAXꢀ
(5ꢀ2)
(6)
C
1) Vertical burr 0ꢀ03 maxꢀ, all sides
2) These four metal areas have exposed diepad potential
PG-VQFN-48-29, -31-PO V05
Figure 41 Package outline VQFN-48-31 (with LTI)
Notes
1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
2. Dimensions in mm.
Datasheet
124
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Abbreviations
30
Abbreviations
The following acronyms and terms are used within this document. List see in Table 44.
Table 44
Acronyms
AHB
CCU6
CGU
CLKMU
CMU
DPP
ECC
Acronyms
Name
Arm® Advanced High-Performance Bus
Capture Compare Unit 6
Clock Generation Unit
Clock Management Unit
Cyclic Management Unit
Data Post Processing
Error Correction Code
EEPROM
GPIO
HV
Electrically Erasable Programmable Read Only Memory
General Purpose Input Output
High Voltage
ICU
Interrupt Control Unit
LDO
LIN
Low DropOut voltage regulator
Local Interconnect Network
Least Significant Bit
LSB
LTI
Lead Tip Inspection
LV
Low Voltage
MCU
MF
Microcontroller Unit
Measurement Functions
Memory Protection Unit
Master Receive / Slave Transmit, corresponds to MISO in SPI
Most Significant Bit
MPU
MRST
MSB
MTSR
MU
Master Transmit / Slave Receive, corresponds to MOSI in SPI
Measurement Unit
NMI
Non Maskable Interrupt
Nested Vector Interrupt Controller
Oscillator
NVIC
OSC
OTP
PBA
One Time Programmable
Peripheral Bridge
PC
Program Counter
PCU
PD
Power Control Unit
Pull Down
PGU
PLL
Power supply Generation Unit
Phase Locked Loop
PMU
PPB
Power Management Unit
Private Peripheral Bus
Datasheet
125
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Abbreviations
Table 44
Acronyms
PSW
PU
Acronyms (cont’d)
Name
Program Status Word
Pull Up
PWM
RAM
Pulse Width Modulation
Random Access Memory
RCU
Reset Control Unit
rfu
reserved for future use
RMU
ROM
SCU
Reset Management Unit
Read Only Memory
System Control Unit
SOW
SPI
Short Open Window (for WDT1)
Serial Peripheral Interface
Synchronous Serial Channel
Arm® Serial Wire Debug
SSC
SWD
TCCR
TMS
Temperature Compensation Control Register
Test Mode Select
TSD
Thermal Shut Down
UART
VBG
Universal Asynchronous Receiver Transmitter
Voltage reference Band Gap
Voltage Controlled Oscillator
Watchdog timer in SCU-PM (System Control Unit - Power Modules)
Wake-up Management Unit
100 Times Programmable
VCO
WDT1
WMU
100TP
Datasheet
126
Rev. 1.1
2022-05-11
TLE9844QX
Microcontroller with LIN and Power Switches for Automotive Applications
Revision History
31
Revision History
Revision History
Page or Item
Subjects (major changes since previous revision)
Rev. 1.1, 2022-05-11
•
Table 1: For VDDC changed value 0.9 V to reduced voltage
Editorial changes:
•
Updated Arm® trademarks
•
Figure 9: Changed “PMU_RST_STS” to “PMU_RESET_STS”
Chapter 11: Added system address range “58004000H - 58007FFFH”
Table 5: Removed “wakeup” at nodes 12 and 22
Table 10: Changed table title from “Port Registers” to “Timer2 and Timer21 Modes”
Moved the “Abbreviations” to the end of the datasheet
P_1.1.10: Removed footnote
•
•
•
•
•
Rev. 1.0, 2016-03-17
Initial revision
Datasheet
127
Rev. 1.1
2022-05-11
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Important notice
Warnings
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
Edition 2022-05-11
Published by
Infineon Technologies AG
81726 Munich, Germany
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
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consequences of the use thereof can reasonably be
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