TLE9869QXA20 [INFINEON]
Microcontroller with LIN and H-Bridge MOSFET Driver for Automotive Applications;
| 型号： | TLE9869QXA20 |
| 厂家： | 
Infineon |
| 描述： | Microcontroller with LIN and H-Bridge MOSFET Driver for Automotive Applications 微控制器 |
| 文件： | 总122页 (文件大小：4649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE9869QXA20
Microcontroller with LIN and H-Bridge MOSFET Driver for Automotive Applications
BE-Step
Data Sheet
Rev. 1.0, 2015-04-30
Automotive Power
TLE9869QXA20
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.2
Device Pinout and Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PMU Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power Supply Generation Unit (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
6.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.3.2.1
6.3.2.2
System Control Unit - Digital Modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
High Precision Oscillator Circuit (OSC_HP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External Input Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External Crystal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
System Control Unit - Power Modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
7.2
7.2.1
8
ARM Cortex M3 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1
8.2
8.2.1
9
9.1
9.2
9.2.1
9.3
9.3.1
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DMA Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10
Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11
Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
NVM Module (Flash Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1
11.2
11.2.1
11.3
Data Sheet
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Table of Contents
12
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1
12.2
12.2.1
13
13.1
13.2
Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14
14.1
14.2
GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TLE9869QXA20 Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14.2.1
14.2.2
14.3
14.3.1
14.3.1.1
14.3.2
14.3.2.1
14.3.3
14.3.3.1
15
15.1
General Purpose Timer Units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Features Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Features Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Block Diagram GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Block Diagram GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
15.1.1
15.1.2
15.2
15.2.1
15.2.2
16
Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Timer2 and Timer21 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
16.1
16.2
16.2.1
17
Timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timer3 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
17.1
17.2
17.3
17.3.1
18
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
18.1
18.2
18.2.1
19
UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
19.1
19.2
19.2.1
19.3
20
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
20.1
20.2
20.2.1
Data Sheet
3
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High-Speed Synchronous Serial Interface (SSC1/SSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
21.1
21.2
21.2.1
22
Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
22.1
22.2
22.2.1
23
Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Measurement Core Module Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
23.1
23.2
23.2.1
23.2.2
24
10-Bit Analog Digital Converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
24.1
24.2
24.2.1
25
High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
25.1
25.2
25.2.1
26
Bridge Driver (incl. Charge Pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
26.1
26.2
26.2.1
26.2.2
27
Current Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
27.1
27.2
27.2.1
28
28.1
28.2
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
H-Bridge Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ESD Immunity According to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
29
29.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PMU I/O Supply (VDDP) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PMU Core Supply (VDDC) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
VDDEXT Voltage Regulator (5.0V) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
VPRE Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Load Sharing Scenarios of VPRE Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Power Down Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
29.1.1
29.1.2
29.1.3
29.1.4
29.1.5
29.2
29.2.1
29.2.2
29.2.3
29.2.4
29.2.4.1
29.2.5
29.3
Data Sheet
4
Rev. 1.0, 2015-04-30
TLE9869QXA20
Table of Contents
29.3.1
29.4
29.4.1
29.5
29.5.1
29.5.2
29.5.3
29.6
29.6.1
29.7
Oscillators and PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Description of Keep and Force Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DC Parameters of Port 0, Port 1, TMS and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DC Parameters of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SSC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
System Voltage Measurement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Central Temperature Sensor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC1 - VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Electrical Characteristics VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Electrical Characteristics ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
High-Voltage Monitoring Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
29.7.1
29.8
29.8.1
29.8.2
29.8.3
29.8.3.1
29.9
29.9.1
29.9.2
29.10
29.11
29.11.1
29.12
29.12.1
29.13
29.13.1
30
31
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Data Sheet
5
Rev. 1.0, 2015-04-30
Microcontroller with LIN and H-Bridge MOSFET Driver
for Automotive Applications
TLE9869QXA20
1
Overview
Summary of Features
•
32 bit ARM Cortex M3 Core
– up to 24 MHz clock frequency
– one clock per machine cycle architecture
On-chip memory
•
– 128 kByte Flash including
– 4 kByte EEPROM (emulated in Flash)
– 512 Byte 100 Time Programmable Memory (100TP)
– 6 kByte RAM
VQFN-48-31
– Boot ROM for startup firmware and Flash routines
On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MOSFET driver including charge pump
10 general-purpose I/O Ports (GPIO)
5 analog inputs, 10-bit A/D Converter (ADC1)
16-bit timers - GPT12, Timer 2, Timer 21 and Timer 3
Capture/compare unit for PWM signal generation (CCU6)
2 full duplex serial interfaces (UART) with LIN support (for UART1 only)
2 synchronous serial channels (SSC)
On-chip debug support via 2-wire SWD
1 LIN 2.2 transceiver
1 high voltage monitoring input
Single power supply from 5.5 V to 27 V
Extended power supply voltage range from 3 V to 28 V
Low-dropout voltage regulators (LDO)
High speed operational amplifier for motor current sensing via shunt
5 V voltage supply for external loads (e.g. Hall sensor)
Core logic supply at 1.5 V
Programmable window watchdog (WDT1) with independent on-chip clock source
Power saving modes
– MCU slow-down Mode
– Sleep Mode
– Stop Mode
– Cyclic wake-up Sleep Mode
•
Power-on and undervoltage/brownout reset generator
Type
Package
Marking
TLE9869QXA20
VQFN-48-31
Data Sheet
6
Rev. 1.0, 2015-04-30
TLE9869QXA20
Overview
•
•
•
•
•
•
•
Overtemperature protection
Short circuit protection
Loss of clock detection with fail safe mode entry for low system power consumption
Temperature Range TJ: -40 °C up to 150 °C
Package VQFN-48 with LTI feature
Green package (RoHS compliant)
AEC qualified
Data Sheet
7
Rev. 1.0, 2015-04-30
TLE9869QXA20
Overview
1.1
Abbreviations
The following acronyms and terms are used within this document. List see in Table 1.
Table 1
Acronyms
AHB
APB
Acronyms
Name
Advanced High-Performance Bus
Advanced Peripheral Bus
Capture Compare Unit 6
Clock Generation Unit
Cyclic Management Unit
Charge Pump for MOSFET driver
Current Sense Amplifier
Data Post Processing
CCU6
CGU
CMU
CP
CSA
DPP
ECC
EEPROM
EIM
Error Correction Code
Electrically Erasable Programmable Read Only Memory
Exceptional Interrupt Measurement
Finite State Machine
FSM
GPIO
H-Bridge
ICU
General Purpose Input Output
Half Bridge
Interrupt Control Unit
IEN
Interrupt Enable
IIR
Infinite Impulse Response
Load Instruction
LDM
LDO
LIN
Low DropOut voltage regulator
Local Interconnect Network
Least Significant Bit
LSB
LTI
Lead Tip Inspection
MCU
MF
Micro Controller Unit
Measurement Functions
Most Significant Bit
MSB
MPU
MRST
MTSR
MU
Memory Protection Unit
Master Receive Slave Transmit
Master Transmit Slave Receive
Measurement Unit
NMI
Non Maskable Interrupt
Nested Vector Interrupt Controller
Non-Volatile Memory
NVIC
NVM
OTP
OSC
PBA
One Time Programmable
Oscillator
Peripheral Bridge
Data Sheet
8
Rev. 1.0, 2015-04-30
TLE9869QXA20
Overview
Table 1
Acronyms
PCU
Acronyms
Name
Power Control Unit
PD
Pull Down
PGU
Power supply Generation Unit
Phase Locked Loop
PLL
PPB
Private Peripheral Bus
Pull Up
PU
PWM
RAM
RCU
Pulse Width Modulation
Random Access Memory
Reset Control Unit
RMU
ROM
SCU-DM
SCU-PM
SFR
Reset Management Unit
Read Only Memory
System Control Unit - Digital Modules
System Control Unit - Power Modules
Special Function Register
Short Open Window (for WDT)
Serial Peripheral Interface
Synchronous Serial Channel
Store Instruction
SOW
SPI
SSC
STM
SWD
TCCR
TMS
ARM Serial Wire Debug
Temperature Compensation Control Register
Test Mode Select
TSD
Thermal Shut Down
UART
VBG
Universal Asynchronous Receiver Transmitter
Voltage reference Band Gap
Voltage Controlled Oscillator
Pre Regulator
VCO
VPRE
WDT
WDT1
WMU
100TP
Watchdog Timer in SCU-DM
Watchdog Timer in SCU-PM
Wake-up Management Unit
100 Time Programmable
Data Sheet
9
Rev. 1.0, 2015-04-30
TLE9869QXA20
Block Diagram
2
Block Diagram
TMS
P0.0
TEST / DEBUG
INTERFACE
ARM
CORTEX-M3
MICRO DMA
CONTROLLER
FLASH
slave
SRAM
slave
ROM
slave
systembus
slave
Multilayer AHB Matrix
slave
PBA0
slave
PBA1
VAREF
GND_REF
SCU_DM
PLL
XTAL1
XTAL2
UART1
UART2
SSC1
SSC2
T2
MU-VAREF
P2.0, P2.2, P2.3, P2.4, P2.5
(AN0, AN2, AN3, AN4, AN5)
P0.1 – P0.4
P1.0 – P1.4
ADC 1
DPP1
GPT12
CCU6
GPIO
LIN
GND_LIN
LIN
MU
VDH
GH2
SH2
GL2
GH1
SH1
MF / ADC2
T21
MOSFET
Driver
VBAT_SENSE
DPP2
SCU_DM
WDT
OP1
OP2
OP AMP
GL1
SL
VS
SCU_PM
WDT1/
PMU –
Power
RESET
VDDEXT
VDDP
VDDC
VCP
Control
System
Functions
CLKWDT
VSD
CP2H
CP2L
CP1H
CP1L
CP
uDMA
Controller
MON
MON
T3
TLE9869_block_diagram_bus_architecture.vsd
Figure 1
Block Diagram TLE9869
Data Sheet
10
Rev. 1.0, 2015-04-30
TLE9869QXA20
Device Pinout and Pin Configuration
3
Device Pinout and Pin Configuration
3.1
Device Pinout
OP1 37
24 P0.3
23 P0.1
EP
VDDC 38
GND 39
22 RESET
21 P0.0
VDDP 40
VDDEXT 41
GND_LIN 42
20 TMS
19 GND
TLE 9869
LIN 43
18 P0. 4
17 P1.2
16 P1.1
15 P1.0
VDH 44
VS 45
VBAT _SENSE 46
VSD 47
14 MON
13 GL1
CP1H 48
Note:
= Low voltage pins
Figure 2
Device Pinout, TLE9869
Data Sheet
11
Rev. 1.0, 2015-04-30
TLE9869QXA20
Device Pinout and Pin Configuration
3.2
Pin Configuration
After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings:
•
•
•
•
Pull-up device enabled only (PU)
Pull-down device enabled only (PD)
Input with both pull-up and pull-down devices disabled (I)
Output with output stage deactivated = high impedance state (Hi-Z)
The functions and default states of the TLE9869QXA20 external pins are provided in the following table.
Type: indicates the pin type.
•
•
•
•
I/O: Input or output
I: Input only
O: Output only
P: Power supply
Not all alternate functions listed.
Table 2
Symbol
Pin Definitions and Functions
Pin Number Type
Reset Function
State1)
P0
Port 0
Port 0 is a 5-bit bidirectional general purpose I/O port. Alternate
functions can be assigned and are listed in the port description.
Main function is listed below.
P0.0
P0.1
21
23
I/O
I/O
I/PU
I/PU
SWD
GPIO
Serial Wire Debug Clock
General Purpose IO
Alternate function mapping see Table 8
P0.2
25
I/O
I/PD
GPIO
General Purpose IO
Alternate function mapping see Table 8
Note: For a functional SWD connection this
GPIO must be tied to zero!
P0.3
P0.4
P1
24
18
I/O
I/O
I/PU
I/PD
GPIO
GPIO
Port 1
General Purpose IO
Alternate function mapping see Table 8
General Purpose IO
Alternate function mapping see Table 8
Port 1 is a 5-bit bidirectional general purpose I/O port. Alternate
functions can be assigned and are listed in the Port description.
The principal functions are listed below.
P1.0
P1.1
P1.2
P1.3
P1.4
15
16
17
26
27
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
GPIO
GPIO
GPIO
GPIO
GPIO
General Purpose IO
Alternate function mapping see Table 9
General Purpose IO
Alternate function mapping see Table 9
General Purpose IO
Alternate function mapping see Table 9
General Purpose IO, used for Inrush Transistor
Alternate function mapping see Table 9
General Purpose IO
Alternate function mapping see Table 9
Data Sheet
12
Rev. 1.0, 2015-04-30
TLE9869QXA20
Device Pinout and Pin Configuration
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number Type
Reset Function
State1)
P2
Port 2
Port 2 is a 5-bit general purpose input-only port.
Alternate functions can be assigned and are listed in the Port
description. Main function is listed below.
P2.0/XTAL1
P2.2/XTAL2
P2.3
29
30
35
32
31
I/I
I
I
I
I
I
AN0
AN2
AN3
AN4
AN5
ADC analog input 0
Alternate function mapping see Table 10
I/O
ADC analog input 2
Alternate function mapping see Table 10
I
I
I
ADC analog input 3
Alternate function mapping see Table 10
P2.4
ADC analog input 4
Alternate function mapping see Table 10
P2.5
ADC analog input 5
Alternate function mapping see Table 10
Power Supply
VS
45
40
38
P
P
P
–
–
–
Battery supply input
2)I/O port supply (5.0 V). Connect external buffer capacitor.
3)Core supply (1.5 V during Active Mode).
Do not connect external loads, connect external buffer
capacitor.
VDDP
VDDC
VDDEXT
GND
41
19
28
39
P
P
P
P
–
–
–
–
External voltage supply output (5.0 V, 20 mA)
GND digital
GND digital
GND analog
GND
GND
Monitor Input
MON
14
I
–
High Voltage Monitor Input
LIN Interface
LIN
43
42
I/O
P
–
–
LIN bus interface input/output
LIN ground
GND_LIN
Charge Pump
CP1H
48
1
P
P
P
P
P
P
–
–
–
–
–
–
Charge Pump Capacity 1 High, connect external C
Charge Pump Capacity 1 Low, connect external C
Charge Pump Capacity 2 High, connect external C
Charge Pump Capacity 2 Low, connect external C
Charge Pump Capacity
CP1L
CP2H
3
CP2L
4
VCP
2
VSD
47
Battery supply input for Charge Pump
MOSFET Driver
VDH
44
6
P
P
P
–
–
–
Voltage Drain High Side MOSFET Driver
Source High Side FET 2
SH2
GH2
7
Gate High Side FET 2
Data Sheet
13
Rev. 1.0, 2015-04-30
TLE9869QXA20
Device Pinout and Pin Configuration
Table 2
Symbol
Pin Definitions and Functions (cont’d)
Pin Number Type
Reset Function
State1)
SH1
8
P
P
P
P
P
–
–
–
–
–
Source High Side FET 1
Gate High Side FET 1
Source Low Side FET
Gate Low Side FET 2
Gate Low Side FET 1
GH1
9
SL
10
12
13
GL2
GL1
Others
GND_REF
VAREF
OP1
33
34
37
36
20
P
–
GND for VAREF
I/O
–
5V ADC1 reference voltage, optional buffer or input
Negative operational amplifier input
I
I
–
OP2
–
Positive operational amplifier input
TMS
I
I/PD
TMS
Test Mode Select input
I/O
SWD
Serial Wire Debug input/output
RESET
22
I/O
I
–
–
–
Reset input, not available during Sleep Mode
Battery supply voltage sense input
Exposed Pad, connect to GND
VBAT_SENSE 46
EP
–
–
1) Only valid for digital IOs
2) Also named VDD5V.
3) Also named VDD1V5.
Data Sheet
14
Rev. 1.0, 2015-04-30
TLE9869QXA20
Modes of Operation
4
Modes of Operation
This highly integrated circuit contains analog and digital functional blocks. An embedded 32-bit microcontroller is
available for system and interface control. On-chip, low-dropout regulators are provided for internal and external
power supply. An internal oscillator provides a cost effective clock that is particularly well suited for LIN
communications. A LIN transceiver is available as a communication interface. Driver stages for an H-Bridge with
external MOSFET are integrated, featuring PWM capability, protection features and a charge pump for operation
at low supply voltage. A 10-bit SAR ADC is implemented for high precision sensor measurement. An 8-bit ADC is
used for diagnostic measurements.
The Micro Controller Unit (MCU) supervision and system protection (including a reset feature) is complemented
by a programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated
temperature sensors are available on-chip.
All relevant modules offer power saving modes in order to support automotive applications connected to terminal
30. A wake-up from power-save mode is possible via a LIN bus message, via the monitoring input or using a
programmable time period (cyclic wake-up).
Featuring LTI, the integrated circuit is available in a VQFN-48-31 package with 0.5 mm pitch, and is designed to
withstand the severe conditions of automotive applications.
The TLE9869QXA20 has several operation modes mainly to support low power consumption requirements.
Reset Mode
The Reset Mode is a transition mode used e.g. during power-up of the device after a power-on reset, or after wake-
up from Sleep Mode. In this mode, the on-chip power supplies are enabled and all other modules are initialized.
Once the core supply VDDC is stable, the device enters Active Mode. If the watchdog timer WDT1 fails more than
four times, the device performs a fail-safe transition to Sleep Mode.
Active Mode
In Active Mode, all modules are activated and the TLE9869QXA20 is fully operational.
Stop Mode
Stop Mode is one of two major low power modes. The transition to the low power modes is performed by setting
the corresponding bits in the mode control register. In Stop Mode the embedded microcontroller is still powered,
allowing faster wake-up response times. Wake-up from this mode is possible through LIN bus activity, by using
the high-voltage monitoring pin or the corresponding 5V GPIOs.
Stop Mode with Cyclic Wake-Up
The Cyclic Wake-Up Mode is a special operating mode of the Stop Mode. The transition to the Cyclic Wake-Up
Mode is done by first setting the corresponding bits in the mode control register followed by the Stop Mode
command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous
wake events via the activated sources (LIN and/or MON) are available, as in normal Stop Mode.
Sleep Mode
The Sleep Mode is a low-power mode. The transition to the low-power mode is done by setting the corresponding
bits in the MCU mode control register or in case of failure, see below. In Sleep Mode the embedded microcontroller
power supply is deactivated allowing the lowest system power consumption. A wake-up from this mode is possible
by LIN bus activity, the High Voltage Monitor Input pin or Cyclic Wake-up.
Sleep Mode in Case of Failure
Data Sheet
15
Rev. 1.0, 2015-04-30
TLE9869QXA20
Modes of Operation
Sleep Mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). In this case,
MON is enabled as the wake source and Cyclic Wake-Up is activated with 1s of wake time.
Sleep Mode with Cyclic Wake-Up
The Cyclic Wake-Up Mode is a special operating mode of the Sleep Mode. The transition to Cyclic Wake-Up Mode
is performed by first setting the corresponding bits in the mode control register followed by the Sleep and Stop
Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period),
asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Sleep Mode.
When using Sleep Mode with cyclic wake-up the voltage regulator is switched off and started again with the wake.
A limited number of registers is buffered during sleep, and can be used by SW e.g. for counting sleep/wake cycles.
MCU Slow Down Mode
In MCU Slow Down Mode the MCU frequency is reduced for saving power during operation. LIN communication
is still possible. LS MOSFET can be activated.
Wake-Up Source Prioritization
All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up sources,
the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are latched in order
to provide all wake-up events to the application software. The software can clear the wake-up source flags. This
is to ensure that no wake-up event is lost.
As default wake-up source, the MON input is activated after power-on reset only. Additionally, the device is in
Cyclic Wake-Up Mode with the max. configurable dead time setting.
The following table shows the possible power mode configurations including the Stop Mode.
Table 3
Power Mode Configurations
Module/Function
Active Mode Stop Mode
Sleep Mode
Comment
VDDEXT
ON/OFF
ON (no dynamic
OFF
–
load)/OFF
Bridge Driver
LIN TRx
ON/OFF
ON/OFF
OFF
OFF
wake-up only/
OFF
wake-up only/
OFF
–
VS sense
ON/OFF
brownout
detection
brownout detection
POR on VS
brownout det. done in
PCU
VBAT_SENSE
GPIO 5V (wake-up)
GPIO 5V (active)
WDT1
ON/OFF
n.a.
OFF
OFF
OFF
OFF
OFF
–
–
–
–
–
disabled/static
ON
ON
ON
OFF
CYCLIC WAKE
n.a.
cyclic wake-up/
cyclic sense/OFF
cyclic wake-up/
OFF
Measurement
MCU
ON1)
OFF
STOP2)
OFF
OFF
–
–
ON/slow-
down/STOP
CLOCK GEN (MC)
ON
OFF
OFF
–
Data Sheet
16
Rev. 1.0, 2015-04-30
TLE9869QXA20
Modes of Operation
Table 3
Power Mode Configurations (cont’d)
Module/Function
LP_CLK (18 MHz)
LP_CLK2 (100 kHz)
Active Mode Stop Mode
Sleep Mode
OFF
Comment
ON
OFF
WDT1
ON/OFF
ON/OFF
ON/OFF
for cyclic wake-up
1) May not be switched off due to safety reasons
2) MC PLL clock disabled, MC supply reduced to 0.9 V
Wake-Up Levels and Transitions
The wake-up can be triggered by rising, falling or both signal edges for the monitor input, by LIN or by cyclic wake-
up.
Data Sheet
17
Rev. 1.0, 2015-04-30
TLE9869QXA20
Power Management Unit (PMU)
5
Power Management Unit (PMU)
5.1
Features
•
•
•
•
•
•
System modes control (startup, sleep, stop and active)
Power management (cyclic wake-up)
Control of system voltage regulators with diagnosis (overload, short, over-voltage)
Fail safe mode detection and operation in case of system errors (watchdog fail)
Wake-up sources configuration and management (LIN, MON, GPIOs)
System error logging
5.2
Introduction
The power management unit is responsible for generating all required voltage supplies for the embedded MCU
(VDDC, VDDP) and the external supply (VDDEXT). The power management unit is designed to ensure fail-safe
behavior of the system IC by controlling all system modes including the corresponding transitions. Additionally, the
PMU provides well defined sequences for the system mode transitions and generates hierarchical reset priorities.
The reset priorities control the reset behavior of all system functionalities especially the reset behavior of the
embedded MCU. All these functions are controlled by a state machine. The system master functionality of the
PMU make use of an independent logic supply and system clock. For this reason, the PMU has an "Internal logic
supply and system clock" module which works independently of the MCU clock.
Data Sheet
18
Rev. 1.0, 2015-04-30
TLE9869QXA20
Power Management Unit (PMU)
5.2.1
Block Diagram
The following figure shows the structure of the Power Management Unit. Table 4 describes the submodules in
more detail.
VS
Power Down Supply
VDDP
VDDC
Power SupplyGeneration Unit
(PGU)
I
N
T
E
R
N
A
L
e.g. for WDT1
LP_CLK
Peripherals
LDO for External Supply
VDDEXT
VDDEXT
e.g. for cyclic
wake and sense
LP_CLK2
B
U
S
PMU-PCU
PMU-SFR
MON
LIN
P0.0...P0.4
P1.0...P1.4
PMU-CMU
PMU-RMU
PMU-WMU
PMU-Control
Power Management Unit
Power_Management_7x.vsd
Figure 3
Table 4
Power Management Unit Block Diagram
Description of PMU Submodules
Mod.
Modules
Functions
Name
Power Down
Supply
Independent supply voltage
generation for PMU
This supply is dedicated to the PMU to ensure an
independent operation from generated power supplies
(VDDP, VDDC).
LP_CLK
(= 18 MHz)
- Clock source for all PMU
submodules
This ultra low power oscillator generates the clock for the
PMU.
- Backup clock source for System
- Clock source for WDT1
This clock is also used as backup clock for the system in
case of PLL Clock failure and as an independent clock
source for WDT1.
LP_CLK2
(= 100 kHz)
Clock source for PMU
This ultra low power oscillator generates the clock for the
PMU in Stop Mode and in the cyclic modes.
Peripherals
Peripheral blocks of PMU
These blocks include the analog peripherals to ensure a
stable and fail-safe PMU startup and operation (bandgap,
bias).
Data Sheet
19
Rev. 1.0, 2015-04-30
TLE9869QXA20
Power Management Unit (PMU)
Table 4
Description of PMU Submodules (cont’d)
Modules Functions
Mod.
Name
Power Supply Voltage regulators for VDDP and
This block includes the voltage regulators for the pad
supply (VDDP) and the core supply (VDDC).
Generation
Unit (PGU)
VDDC
VDDEXT
PMU-SFR
PMU-PCU
Voltage regulator for VDDEXT to
supply external modules (e.g.
Sensors)
This voltage regulator is a dedicated supply for external
modules and can also be used for cyclic sense operations
(e.g. with hall sensor).
All Extended Special Function
registers that are relevant to the
PMU.
This module contains all registers needed to control and
monitor the PMU.
Power Control Unit of the PMU
This block is responsible for controlling all power related
actions within the PGU Module. It also contains all
regulator related diagnostics such as undervoltage and
overvoltage detection as well as overcurrent and short
circuit diagnostics.
PMU-WMU
PMU-CMU
PMU-RMU
Wake-Up Management Unit of the This block is responsible for controlling all wake-up related
PMU actions within the PMU Module.
Cyclic Management Unit of the PMU This block is responsible for controlling all actions in cyclic
mode.
Reset Management Unit of the PMU This block generates resets triggered by the PMU such as
undervoltage or short circuit reset, and passes all resets to
the relevant modules and their register.
Data Sheet
20
Rev. 1.0, 2015-04-30
TLE9869QXA20
Power Management Unit (PMU)
5.2.2
PMU Modes Overview
The following state diagram shows the available modes of the device.
VS > 4V and VS ramp up
or
VS < 3V and VS ramp down
LIN-wake or
MON-wake
or
start-up
cyclic -wake
VDDC =stable and
error_supp<5
VDDC / VDDP=
fail (short circuit)
Æ error_supp ++
error_sup=5
sleep
active
Sleep command (from MCU) or
WDT1_SEQ_FAIL = 1 (Æ error_wdt = 5)
or
VDDC / VDDP = overload
LIN-wake or
MON-wake or
GPIO-wake or
cyclic_wake or
PMU_PIN = 1 or
PMU_SOFT = 1 or
(PMU_Ext_WDT = 1 and
WDT1_SEQ_FAIL = 0
PMU_PIN = 1 or
SUP_TMOUT = 1
Æ error_wdt ++)
Stop
command
(from MCU)
stop
cyclic -sense
PMU_System_Modes _Cus _withStopp .vsd
Figure 4
Power Management Unit System Modes
Data Sheet
21
Rev. 1.0, 2015-04-30
TLE9869QXA20
Power Management Unit (PMU)
5.3
Power Supply Generation Unit (PGU)
Voltage Regulator 5.0V (VDDP)
5.3.1
This module represents the 5 V voltage regulator, which provides the pad supply for the parallel port pins and other
5 V analog functions (e.g. LIN Transceiver).
Features
•
•
•
•
•
•
•
•
5 V low-drop voltage regulator
Overcurrent monitoring and shutdown with MCU signaling (interrupt)
Overvoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with reset (Undervoltage Reset, VDDPUV
Pre-Regulator for VDDC Regulator
GPIO Supply
)
Pull Down Current Source at the output for Sleep Mode only (typ. 5 mA)
The output capacitor CVDDP is mandatory to ensure proper regulator functionality.
VDDP Regulator
VS
VDDP
VPRE
A
CVDDP
V
GND (Pin 39)
I
5V LDO
LDO Supervision
LDO_block_external .vsd
Figure 5
Module Block Diagram of VDDP Voltage Regulator
Data Sheet
22
Rev. 1.0, 2015-04-30
TLE9869QXA20
Power Management Unit (PMU)
5.3.2
Voltage Regulator 1.5V (VDDC)
This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core, the
digital peripherals and other internal analog 1.5 V functions (e.g. ADC2) of the chip. To further reduce the current
consumption of the MCU during Stop Mode the output voltage can be lowered to 0.9 V.
Features
•
•
•
•
•
•
1.5 V low-drop voltage regulator
Overcurrent monitoring and shutdown with MCU signaling (interrupt)
Overvoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with reset
Pull Down Current Source at the output for Sleep Mode only (typ. 100 μA)
The output capacitor CVDDC is mandatory to ensure a proper regulator functionality.
VDDC Regulator
VDDP (5V)
VDDC (1.5V)
A
V
CVDDP
CVDDC
I
1.5V LDO
LDO Supervision
1.5V_LDO_block_external.vsd
Figure 6
Module Block Diagram of VDDC Voltage Regulator
Data Sheet
23
Rev. 1.0, 2015-04-30
TLE9869QXA20
Power Management Unit (PMU)
5.3.3
External Voltage Regulator 5.0V (VDDEXT)
This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used
e.g. to supply an external sensor, LEDs or potentiometers.
Features
•
•
•
•
•
•
•
Switchable +5 V, low-drop voltage regulator
Switch-on overcurrent blanking time in order to drive small capacitive loads
Overcurrent monitoring and shutdown with MCU signaling (interrupt)
Overvoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with MCU signaling (interrupt)
Pull Down current source at the output for Sleep Mode only (typ. 100 μA)
Cyclic sense option together with GPIOs
The output capacitor CVDDEXT is mandatory to ensure a proper regulator functionality.
VDDEXTRegulator
VS
VDDEXT
VPRE
A
C
VDDEXT
V
GND (Pin 39)
I
5V LDO
LDO Supervision
HALL_LDO_block_external .vsd
Figure 7
Module Block Diagram of External Voltage Regulator
Data Sheet
24
Rev. 1.0, 2015-04-30
TLE9869QXA20
System Control Unit - Digital Modules (SCU-DM)
6
System Control Unit - Digital Modules (SCU-DM)
6.1
Features
•
•
•
•
•
•
Flexible clock configuration features
Reset management of all system resets
System modes control for all power modes (active, power down, sleep)
Interrupt enabling for many system peripherals
General purpose input output control
Debug mode control of system peripherals
6.2
Introduction
The System Control Unit (SCU) supports all central control tasks in the TLE9869QXA20. The SCU is made up of
the following sub-modules:
•
•
•
•
•
•
•
•
•
•
Clock System and Control
Reset Control
Power Management
Interrupt Management
General Port Control
Flexible Peripheral Management
Module Suspend Control
Watchdog Timer
Error Detection and Correction in Data Memory
Miscellaneous Control
Data Sheet
25
Rev. 1.0, 2015-04-30
TLE9869QXA20
System Control Unit - Digital Modules (SCU-DM)
6.2.1
Block Diagram
On signals to digital
peripherals;
status signals from
digital peripherals
AHB
PMCU
WDT
ICU
f
SYS
I
N
T
E
R
N
A
L
CGU
fOSC
XTAL1
OSC_HP
PLL
XTAL2
LP_CLK
NMI
f
SYS
fPLL
fPCLK
INTISR <9:0>
CG
fMI_CLK
f
TFILT _CLK
B
U
S
PMU_1V5DidPOR
PMU_PIN
PMU_ExtWDT
PMU_IntWDT
PMU_SOFT
RCU
MISC Control
MODPISELx
PMU_Wake
RESET_TYPE_3
RESET_TYPE_4
P0_POCONy.PDMx
P1_POCONy.PDMx
Port Control
System Control Unit -Digital Modules
SCU_DM_Block_Diagram_Cust.vsd
Figure 8
System Control Unit - Digital Modules Block Diagram
AMBA AHB (Advanced High-Performance Bus)
PMCU (Power Module Control Unit)
WDT (Watchdog Timer in SCU-DM)
•
f
SYS; System clock
CGU (Clock Generation Unit)
•
•
f
f
SYS; System clock
PCLK; Peripheral clock
Data Sheet
26
Rev. 1.0, 2015-04-30
TLE9869QXA20
System Control Unit - Digital Modules (SCU-DM)
•
•
•
f
f
MI_CLK; Measurement interface clock
TFILT_CLK; Analog module filter clock
LP_CLK; Clock source for all PMU submodules and WDT1
ICU (Interrupt Control Unit)
•
•
NMI (Non-Maskable Interrupt)
INTISR<15:0>; External interrupt signals
RCU (Reset Control Unit)
•
•
•
•
•
•
•
•
PMU_1V5DidPOR; Undervoltage reset of power down supply
PMU_PIN; Reset generated by reset pin
PMU_ExtWDT; WDT1 reset
PMU_IntWDT; WDT (SCU) reset
PMU_SOFT; Software reset
PMU_Wake; Sleep Mode/Stop Mode exit with reset
RESET_TYPE_3; Peripheral reset (contains all resets)
RESET_TYPE_4; Peripheral reset (without SOFT and WDT reset)
Port Control
•
•
P0_POCONy.PDMx; driver strength control
P1_POCONy.PDMx; driver strength control
MISC Control
MODPISELx; Mode selection registers for UART (source section) and Timer (trigger or count selection)
•
6.3
Clock Generation Unit
The Clock Generation Unit (CGU) enables a flexible clock generation for TLE9869QXA20. During user program
execution, the frequency can be modified to optimize the performance/power consumption ratio, allowing power
consumption to be adapted to the actual application state.
The CGU in the TLE9869QXA20 consists of one oscillator circuit (OSC_HP), a Phase-Locked Loop (PLL) module
with an internal oscillator (OSC_PLL), and a Clock Control Unit (CCU). The CGU can convert a low-frequency
input/external clock signal to a high-frequency internal clock.
The system clock fSYS is generated from of the following selectable clocks:
•
•
•
PLL clock output fPLL
Direct clock from oscillator OSC_HP fOSC
Low precision clock fLP_CLK (HW-enabled for startup after reset and during power-down wake-up sequence)
Data Sheet
27
Rev. 1.0, 2015-04-30
TLE9869QXA20
System Control Unit - Digital Modules (SCU-DM)
CGU
PLLCON
CMCON
OSC_CON
SYSCON0
XTAL1
XTAL2
PLL
OSC_HP
f
f
SYS
OSC
CCU
f
LP_CLK
LP_CLK
PMU
CGU_block
Figure 9
Clock Generation Unit Block Diagram
The following sections describe the different parts of the CGU.
6.3.1
Low Precision Clock
The clock source LP_CLK is a low-precision RC oscillator (LP-OSC) with a nominal frequency of 18 MHz that is
enabled by hardware as an independent clock source for the TLE9869QXA20 startup after reset and during the
power-down wake-up sequence. fLP_CLK is not user configurable.
6.3.2
High Precision Oscillator Circuit (OSC_HP)
The high precision oscillator circuit, designed to work with both an external crystal oscillator or an external stable
clock source, consists of an inverting amplifier with XTAL1 as the input, and XTAL2 as the output.
Figure 10 shows the recommended external circuitry for both operating modes, External Crystal Mode and
External Input Clock Mode.
6.3.2.1
External Input Clock Mode
When supplying the clock signal directly, not using an external crystal and bypassing the oscillator, the input
frequency needs to be equal to or greater than 4 MHz if the PLL VCO part is used.
When using an external clock signal, it must be connected to XTAL1. XTAL2 is left open (unconnected).
6.3.2.2
External Crystal Mode
When using an external crystal, its frequency can be within the range of 4 MHz to 25 MHz. An external oscillator
load circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists of the two load
capacitances C1 and C2. A series damping resistor could be required for some crystals. The exact values and the
corresponding operating ranges depend on the crystal and have to be determined and optimized in cooperation
with the crystal vendor using the negative resistance method. The following load cap values can be used as
starting point for the evaluation:
Data Sheet
28
Rev. 1.0, 2015-04-30
TLE9869QXA20
System Control Unit - Digital Modules (SCU-DM)
Table 5
External CAP Capacitors
Fundamental Mode Crystal Frequency (approx., MHz) Load Caps C1, C2 (pF)
4
33
18
12
10
10
8
8
12
16
20
25
External Crystal Mode
External Input Clock Mode
VDDP
VDDP
Fundamental Mode Crystal
4 - 25 MHz
External
XTAL1
Clock
XTAL1
Signal
OSC_HP
fOSC
OSC_HP
fOSC
XTAL2
XTAL2
C1
C2
VSS
VSS
VSS = GND = PIN 39
ext_Osc.vsd
Figure 10 TLE9869QXA20 External Circuitry for the OSC_HP
Data Sheet
29
Rev. 1.0, 2015-04-30
TLE9869QXA20
System Control Unit - Power Modules (SCU-PM)
7
System Control Unit - Power Modules (SCU-PM)
7.1
Features
•
•
•
•
Clock Watchdog Unit (CWU): supervision of all clocks with NMI signaling relevant to power modules
Interrupt Control Unit (ICU): all interrupt flags and status flags with system relevance
Power Control Unit (PCU): takes over control when device enters and exits Sleepand Stop Mode
External Watchdog (WDT1): independent system watchdog for monitoring system activity
7.2
Introduction
7.2.1
Block Diagram
The System Control Unit of the power modules consists of the sub-modules in the figure shown below:
On signals to analog
peripherals;
status signals from
analog peripherals
AMBA AHB
I
N
T
PCU
WDT1
LP_CLK
E
R
N
A
L
fsys
MI_CLK
PREWARN_SUP_NMI
PREWARN_SUP_INT
INT<n:0>
B
U
S
CWU
ICU
TFILT_CLK
System Control Unit -Power Modules
SCU_PM_Block_Diagram_Cust.vsd
Figure 11 Block diagram of System Control Unit - Power Modules
AMBA AHB (Advanced High-Performance Bus)
CWU (Clock Watchdog Unit)
•
•
•
fsys; system frequency: PLL output
MI_CLK; measurement interface clock (analog clock): derived from fsys using division factors 1/2/3/4
TFILT_CLK; clock used for digital filters: derived from fsys using configurable division factors
Data Sheet
30
Rev. 1.0, 2015-04-30
TLE9869QXA20
System Control Unit - Power Modules (SCU-PM)
WDT1 (System Watchdog)
LP_CLK; clock source for all PMU submodules and WDT1
•
ICU (Interrupt Control Unit)
•
•
•
PREWARN_SUP_NMI; supply prewarning NMI request
PREWARN_SUP_INT; supply prewarning interrupt
grouping of peripheral interrupts for external interupt nodes:
– grouping single peripheral interrupts for interrupt node INT<2> (Measurement Unit (MU))
– grouping single peripheral interrupts for interrupt node INT<3> (ADC1-VAREF)
– grouping single peripheral interrupts for interrupt node INT<10> (UART1-LIN Transceiver)
– grouping single peripheral interrupts for interrupt node INT<14> (Bridge Driver)
Data Sheet
31
Rev. 1.0, 2015-04-30
TLE9869QXA20
ARM Cortex M3 Core
8
ARM Cortex M3 Core
8.1
Features
The key features of the Cortex M3 implemented are listed below.
Processor Core. A low gate count core, with low latency interrupt processing:
•
•
•
•
•
•
•
•
•
A subset of the Thumb®-2 Instruction Set
Banked stack pointer (SP) only
32-bit hardware divide instructions, SDIV and UDIV (Thumb-2 instructions)
Handler and Thread Modes
Thumb and debug states
Interruptible-continued instructions LDM/STM, Push/Pop for low interrupt latency
Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit
ARM architecture v7-M Style BE8/LE support
ARMv6 unaligned accesses
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low
latency interrupt processing:
•
•
•
•
•
Interrupts, configurable from 1 to 16
Bits of priority (4)
Dynamic reprioritization of interrupts
Priority grouping. This enables selection of preemptive interrupt levels and non-preemptive interrupt levels
Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without
the overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction
overhead
•
Bus interfaces
•
•
•
Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and System bus interface
Memory access alignment
Write buffer for buffering of write data
8.2
Introduction
The ARM Cortex-M3 processor is a leading 32-bit processor and provides a high-performance and cost-optimized
platform for a broad range of applications including microcontrollers, automotive body systems and industrial
control systems. Like the other Cortex family processors, the Cortex-M3 processor implements the Thumb®-2
instruction set architecture. With the optimized feature set the Cortex-M3 delivers 32-bit performance in an
application space that is usually associated with 8- and 16-bit microcontrollers.
Data Sheet
32
Rev. 1.0, 2015-04-30
TLE9869QXA20
ARM Cortex M3 Core
8.2.1
Block Diagram
Figure 12 shows the functional blocks of the Cortex M3.
Cortex-M3 Processor
Nested Vectored
Interrupt
Cortex-M3
Processor
Core
Interrupt and
Power Control
Controller
(NVIC)
AHB
Access Port
(AHB-AP)
Serial-Wire
(SW-DP)
Bus Matrix
ICode
AHB-Lite
Instruction
Interface
DCode
AHB-Lite
Data
System Bus
ICode
Serial-Wire Debug
Interface
PBA0
PBA1
Interface
Cortex_M3_Block_diagram.vsd
Figure 12 Cortex M3 Block Diagram
Data Sheet
33
Rev. 1.0, 2015-04-30
TLE9869QXA20
DMA Controller
9
DMA Controller
Figure 13 shows the Top Level Block Diagram of the TLE9869QXA20.
The bus matrix allows the uDMA to access the PBA0, PBA1 and RAM.
9.1
Features
The principal features of the DMA Controller are that:
•
•
•
•
•
•
•
it is compatible with AHB-Lite for the DMA transfers
it is compatible with APB for programming the registers
it has a single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus
it supports 13 DMA channels
each DMA channel has dedicated handshake signals
each DMA channel has a programmable priority level
each priority level arbitrates using a fixed priority that is determined by the DMA channel number. The DMA
also supports multiple transfer types:
- memory-to-memory
- memory-to-peripheral
- peripheral-to-memory
•
•
•
•
•
it supports multiple DMA cycle types
it supports multiple DMA transfer data widths
each DMA channel can access a primary, and alternate, channel control data structure
all the channel control data is stored in system memory (RAM) in little-endian format
it performs all DMA transfers using the SINGLE AHB-Lite burst type. The destination data width is equal to the
source data width.
•
•
the number of transfers in a single DMA cycle can be programmed from 1 to 1024
the transfer address increment can be greater than the data width
Data Sheet
34
Rev. 1.0, 2015-04-30
TLE9869QXA20
DMA Controller
9.2
Introduction
Please also refer to Chapter 9.3, Functional Description.
9.2.1
Block Diagram
SSC1
GPT12
ADC1
DMA requests
DMA requests
DMA requests
DMA Controller
Bus Matrix
S
PBA1
AHB2APB
M
AHB lite
M
AHB lite
S
APB Interface
interrupts
SCU_DM
PBA0
S
AHB lite
AHB lite
M
M
RAM
S
ARM Core
interrupts
S
S
S
M
M
M
AHB lite
AHB lite
AHB lite
Figure 13
DMA Controller Top Level Block Diagram
Data Sheet
35
Rev. 1.0, 2015-04-30
TLE9869QXA20
DMA Controller
9.3
Functional Description
DMA Mode Overview
9.3.1
The DMA controller implements the following 13 hardware DMA requests:
•
ADC1 complete sequence 1 done: DMA transfer is requested on completion of the ADC1 channel conversion
sequence.
•
ADC1 exceptional sequence 2 (ESM) done: DMA transfer is requested on completion of the ADC1 conversion
sequence triggered by an exceptional measurement request.
•
•
•
SSC1/2 transmit byte: DMA transfer is requested upon the completion of data transmission via SSC1/2
SSC1/2: receive byte: DMA transfer is requested upon the completion of data reception via SSC1/2.
ADC1 channel 0 conversion done: DMA transfer is requested on completion of the ADC1 channel 0
conversion.
•
•
•
•
•
•
•
•
ADC1 channel 1 conversion done: DMA transfer is requested on completion of the ADC1 channel 1
conversion.
ADC1 channel 2 conversion done: DMA transfer is requested on completion of the ADC1 channel 2
conversion.
ADC1 channel 3 conversion done: DMA transfer is requested on completion of the ADC1 channel 3
conversion.
ADC1 channel 4 conversion done: DMA transfer is requested on completion of the ADC1 channel 4
conversion.
ADC1 channel 5 conversion done: DMA transfer is requested on completion of the ADC1 channel 5
conversion.
ADC1 channel 6 conversion done: DMA transfer is requested on completion of the ADC1 channel 6
conversion.
ADC1 channel 7 conversion done: DMA transfer is requested on completion of the ADC1 channel 7
conversion.
Timer3 ccu6_int: DMA transfer is requested following a timer trigger.
Data Sheet
36
Rev. 1.0, 2015-04-30
TLE9869QXA20
Address Space Organization
10
Address Space Organization
The TLE9869QXA20 manipulates operands in the following memory spaces:
•
•
•
128 kByte of Flash memory in code space
32 kByte Boot ROM memory in code space (used for boot code and IP storage)
6 kByte RAM memory in code space and data space (RAM can be read/written as program memory or external
data memory)
•
Special function registers (SFRs) in peripheral space
The figure below shows the detailed address alignment of TLE9869QXA20:
00000000H
Reserved (BROM)
00008000H / 10FFFFFFH
11000000H / 1101FFFFH
Flash, 128K
Reserved
11020000H / 17FFFFFFH
18000000H / 180017FFH
SRAM, 6K
Reserved
18001800H / 3FFFFFFFH
40000000H / 47FFFFFFH
PBA0
PBA1
48000000H / 5FFFFFFFH
60000000H/ DFFFFFFFH
E0000000H / E00FFFFFH
FFFFFFFFH
Reserved
Private Peripheral Bus
Reserved
Figure 14 TLE9869QXA20 Memory Map
Data Sheet
37
Rev. 1.0, 2015-04-30
TLE9869QXA20
Memory Control Unit
11
Memory Control Unit
11.1
Features
•
•
•
•
Handles all system memories and their interaction with the CPU
Memory protection functions for all system memories (D-Flash, P-Flash, RAM)
Address management with access violation detection including reporting
Linear address range for all memories (no paging)
11.2
Introduction
11.2.1
Block Diagram
The Memory Control Unit (MCU) is divided in the following sub-modules:
•
•
•
•
NVM Memory module (embedded Flash Memory)
RAM memory module
BootROM memory module
Memory Protection Unit (MPU) module
NVM
S0
RAM
S1
BROM
S2
PBA0
S3
Memory Protection
Unit
Sx: BusSlave
Mx: Bus Master
M0
M1
M2
M3
Bus Matrix
MCU_Block_Diagram_overview.vsd
Figure 15 MCU Block View
Data Sheet
38
Rev. 1.0, 2015-04-30
TLE9869QXA20
Memory Control Unit
11.3
NVM Module (Flash Memory)
The Flash Memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable
storage of user code and data.
Features
•
•
In-system programming via LIN (Flash Mode) and SWD
Error Correction Code (ECC) for detection of single-bit and double-bit errors and dynamic correction of single
Bit errors.
•
•
•
•
•
•
•
•
•
Interrupts and signals double-bit error by NMI
Program width of 128 byte (page)
Minimum erase width of 128 bytes (page)
Integrated hardware support for EEPROM emulation
8 byte read access
Physical read access time: 75 ns
Code read access acceleration integrated; read buffer and automatic pre-fetch
Page program time: 3 ms
Page erase (128 bytes) and sector erase (4K bytes) time: 4ms
Note: The user has to ensure that no flash operations which change the content of the flash get interrupted at any
time.
The clock for the NVM is supplied with the system frequency fsys. Integrated firmware routines are provided to
erase NVM, and other operations including EEPROM emulation are provided as well.
Data Sheet
39
Rev. 1.0, 2015-04-30
TLE9869QXA20
Interrupt System
12
Interrupt System
12.1
Features
•
•
•
Up to 16 interrupt nodes for on-chip peripherals
Up to 8 NMI nodes for critical system events
Maximum flexibility for all 16 interrupt nodes
12.2
Introduction
12.2.1
Overview
The TLE9869QXA20 supports 16 interrupt vectors with 16 priority levels. Fifteen of these interrupt vectors are
assigned to the on-chip peripherals: GPT12, SSC, CCU6, DMA, Bridge Driver and A/D Converter are each
assigned to one dedicated interrupt vector; while UART1 and Timer2 or UART2, External Interrupt 2 and Timer21
share interrupt vectors. Two vectors are dedicated for External Interrupt 0 and 1.
Table 6
Interrupt Vector Table
Service Request
GPT12
Node ID
Description
0/1
2
GPT interrupt (T2-T6, CAPIN)
MU- ADC8/T3
ADC1
Measurement Unit, VBG, Timer3
ADC1 interrupt / VREF5V Overload / VREF5V OV/UV, 10-bit ADC
CCU6 node 0 interrupt
3
CCU0
4
CCU1
5
CCU6 node 1 interrupt
CCU2
6
CCU6 node 2 interrupt
CCU3
7
CCU6 node 3 interrupt
SSC1
8
SSC1 interrupt (receive, transmit, error)
SSC2 interrupt (receive, transmit, error)
UART1 (ASC-LIN) interrupt (receive, transmit), Timer2, linsync1, LIN
SSC2
9
UART1
UART2
10
11
UART2 interrupt (receive, transmit), Timer21, External interrupt
(EINT2)
EXINT0
EXINT1
BDRV/CP
DMA
12
13
14
15
External interrupt (EINT0), MON
External interrupt (EINT1)
Bridge Driver / Charge Pump
DMA Controller
Table 7
NMI Interrupt Table
Service Request
Watchdog Timer NMI
PLL NMI
Node
NMI
NMI
NMI
Description
Watchdog Timer overflow
PLL Loss-of-Lock
NVM Operation
Complete NMI
NVM Operation Complete
Overtemperature NMI
NMI
System Overtemperature
Data Sheet
40
Rev. 1.0, 2015-04-30
TLE9869QXA20
Interrupt System
Table 7
NMI Interrupt Table
Service Request
Node
Description
Oscillator Watchdog
NMI
NMI
Oscillator Watchdog / MI_CLK Watchdog Timer Overflow
NVM Map Error NMI
ECC Error NMI
NMI
NMI
NVM Map Error
RAM / NVM Uncorrectable ECC Error
Supply Prewarning
Supply Prewarning NMI NMI
Data Sheet
41
Rev. 1.0, 2015-04-30
TLE9869QXA20
Watchdog Timer (WDT1)
13
Watchdog Timer (WDT1)
13.1
Features
There are two watchdog timers in the system. The Watchdog Timer (WDT) within the System Control Unit - Digital
Modules (see SCU_DM) and the Watchdog Timer (WDT1) located within the System Control Unit - Power
Modules (see SCU_PM). The Watchdog Timer WDT1 is described in this section.
In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way to
recover from software or hardware failures.
The WDT1 is always enabled in Active Mode. In Sleep Mode, Low Power Mode and SWD Mode the WDT1 is
automatically disabled.
Functional Features
•
•
•
•
•
Windowed Watchdog Timer with programmable timing in Active Mode
Long open window (typ. 80ms) after power-up, reset, wake-up
Short open window (typ. 30ms) to facilitate Flash programming
Disabled during debugging
Safety shutdown to Sleep Mode after 5 missed WDT1 services
Data Sheet
42
Rev. 1.0, 2015-04-30
TLE9869QXA20
Watchdog Timer (WDT1)
13.2
Introduction
The behavior of the Watchdog Timer in Active Mode is illustrated in Figure 16.
Power-up
Reset
RESET
Timeout
always
Timeout
RESET
Trigger SOW
Maximum number
of count_SOW
Timeout
or
Trigger in closed window
RESET
Long
Open Window
Trigger&
count_SOW = 0
Trigger SOW&
count_SOW++
Normal
„windowed“
operation
Short
open window
& SOW
Trigger &
count_SOW = 0
Trigger SOW &
count_SOW++
Trigger&
count_SOW = 0
Figure 16 Watchdog Timer Behavior
Data Sheet
43
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
14
GPIO Ports and Peripheral I/O
The TLE9869QXA20 has 15 port pins organized into three parallel ports: Port 0 (P0), Port 1 (P1) and Port 2 (P2).
Each port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. P0
and P1 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate
input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be
selected. On Port 2 (P2) analog inputs are shared with general purpose input.
14.1
Features
Bidirectional Port Features (P0, P1)
•
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Configurable drive strength
Transfer of data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Analog Port Features (P2)
•
•
•
Configurable pull-up/pull-down devices
Transfer of data through digital inputs
Alternate inputs for on-chip peripherals
14.2
Introduction
14.2.1
Port 0 and Port 1
Figure 17 shows the block diagram of an TLE9869QXA20 bidirectional port pin. Each port pin is equipped with a
number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the control
register, each individual pin can be configured as an input or an output. The user can also configure each pin as
an open drain pin with or without internal pull-up/pull-down device.
Each bidirectional port pin can be configured for input or output operation. Switching between input and output
mode is accomplished through the register Px_DIR (x = 0 or 1), which enables or disables the output and input
drivers. A port pin can only be configured as either input or output mode at any one time.
In input mode (default after reset), the output driver is switched off (high-impedance). The actual voltage level
present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via the register
Px_DATA.
In output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin.
In the output driver, each port line can be switched to open drain mode or normal mode (push-pull mode) via the
register Px_OD.
The output multiplexer in front of the output driver enables the port output function to be used for different
purposes. If the pin is used for general purpose output, the multiplexer is switched by software to the data register
Px_DATA. Software can set or clear the bit in Px_DATA and therefore directly influence the state of the port pin.
If an on-chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be switched via the
multiplexer to the output driver circuitry. Selection of the alternate output function is defined in registers
Data Sheet
44
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
Px_ALTSEL0 and Px_ALTSEL1. When a port pin is used as an alternate function, its direction must be set
accordingly in the register Px_DIR.
Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register Px_PUDSEL
selects whether a pull-up or the pull-down device is activated while register Px_PUDEN enables or disables the
pull device.
PUDSEL
Pull-up / Pull-down
Select Register
Pull-up / Pull-down
Control Logic
PUDEN
Pull-up / Pull-down
Enable Register
TCCR
Temperature Compensation
Control Register
Px_POCONy
Port Output
Driver Control Registers
I
N
T
E
R
N
A
L
OD
Open Drain
Control Register
DIR
Direction Register
ALTSEL0
Alternate Select
Register 0
B
U
S
ALTSEL1
Alternate Select
Register 1
Pull Device
AltDataOut 3
AltDataOut 2
AltDataOut 1
11
10
Output
Driver
01
00
Out
In
Data
Data Register
Input
Driver
AltDataIn
Schmitt
Trigger
Pad
Port_Block_Diagram.vsd
Figure 17 General Structure of Bidirectional Port (P0, P1)
Data Sheet
45
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
14.2.2
Port 2
Figure 18 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register
P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage level
present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via register
P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register
P2_PUDSEL selects whether a pull-up or the pull-down device is activated while register P2_PUDEN enables or
disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt trigger device for
direct feed-through to the ADC input channels.
PUDSEL
Pull-up / Pull-down
Select Register
Pull-up / Pull-down
Control Logic
I
N
T
E
R
N
A
L
PUDEN
Pull-up / Pull-down
Enable Register
Pull Device
B
U
S
Input
Driver
In
Data
Data Register
Schmitt
Trigger
Pad
AltDataIn
AnalogIn
Port_Input_Diagram.vsd
Figure 18 General Structure of Input Port (P2)
Data Sheet
46
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
14.3
TLE9869QXA20 Port Module
Port 0
14.3.1
14.3.1.1 Port 0 Functions
Table 8
Port Pin
P0.0
Port 0 Input/Output Functions
Input/Output
Select
GPI
Connected Signal(s)
P0_DATA.P0
SWCLK / TCK_0
T12HR_0
T4INA
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
GPI
SW
CCU6
GPT12T4
Timer 2
–
T2_0
–
EXINT2_3
P0_DATA.P0
T3OUT
SCU
Output
Input
GPT12T3
Timer 21
UART2
EXF21_0
RXDO_2
P0_DATA.P1
T13HR_0
TxD1
P0.1
INP2
INP3
INP4
INP5
INP6
INP7
INP8
GPO
ALT1
ALT2
ALT3
CCU6
LIN_TxD
GPT12CAP
Timer 21
GPT12T4
SSC1
CAPINA
T21_0
T4INC
MRST_1_2
EXINT0_2
P0_DATA.P1
TxD1
SCU
Output
UART1 / LIN_TxD
–
–
T6OUT
GPT12T6
Data Sheet
47
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
Table 8
Port Pin
P0.2
Port 0 Input/Output Functions (cont’d)
Input/Output
Select
GPI
Connected Signal(s)
P0_DATA.P2
CCPOS2_1
T2EUDA
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
CCU6
GPT12T2
SSC1
MTSR_1
T21EX_0
Timer 21
GPT12T6
–
T6INA
Output
Input
P0_DATA.P2
COUT60_0
MTSR_1
CCU6
SSC1
EXF2_0
Timer 2
P0.3
P0_DATA.P3
SCK_1
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
SSC1
CAPINB
GPT12
GPT12T5
GPT12T4
CCU6
T5INA
T4EUDA
CCPOS0_1
P0_DATA.P3
SCK_1
Output
Input
SSC1
EXF21_2
T6OUT
Timer 21
GPT12T6
P0.4
P0_DATA.P4
MRST_1_0
CC60_0
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
SSC1
CCU6
T21_2
Timer 21
SCU
EXINT2_2
T3EUDA
GPT12T3
CCU6
CCPOS1_1
P0_DATA.P4
MRST_1_0
CC60_0
Output
SSC1
CCU6
SCU
CLKOUT_0
Data Sheet
48
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
14.3.2
Port 1
14.3.2.1 Port 1 Functions
Table 9
Port Pin
P1.0
Port 1 Input / Output Functions
Input/Output
Select
GPI
Connected Signal(s)
P1_DATA.P0
T3INC
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
GPT12T3
GPT12T4
CCU6
T4EUDB
CC61_0
SCK_2
SSC2
EXINT1_2
P1_DATA.P0
SCK_2
SCU
Output
Input
SSC2
CC61_0
CCU6
EXF21_3
P1_DATA.P1
–
Timer 21
P1.1
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
GPI
–
T6EUDA
–
GPT12T6
-
MTSR_2
T21_1
SSC2
Timer 21
SCU
–
EXINT1_0
P1_DATA.P1
MTSR_2
COUT61_0
TXD2_0
Output
Input
SSC2
CCU6
UART2
P1.2
P1_DATA.P2
T2INA
INP1
INP2
INP3
INP4
INP5
INP6
INP7
GPO
ALT1
ALT2
ALT3
GPT12T2
Timer 2
Timer 21
SSC2
T2EX_1
T21EX_3
MRST_2_0
RXD2_0
UART2
CCU6
CCPOS2_2
EXINT0_1
P1_DATA.P2
MRST_2_0
COUT63_0
T3OUT
SCU
Output
SSC2
CCU6
GPT12T3
Data Sheet
49
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
Table 9
Port Pin
P1.3
Port 1 Input / Output Functions (cont’d)
Input/Output
Select
GPI
Connected Signal(s)
P1_DATA.P3
T6INB
From/to Module
Input
INP1
INP2
INP3
INP4
INP5
INP6
INP7
GPO
ALT1
ALT2
ALT3
GPI
GPT12T6
–
CC62_0
CCU6
T6EUDB
–
GPT12T6
CCPOS0_2
EXINT1_1
P1_DATA.P3
EXF21_1
CC62_0
CCU6
SCU
Output
Input
Timer 21
CCU6
TXD2_1
UART2
P1.4
P1_DATA.P4
EXINT2_1
T21EX_1
T5EUDA
RxD1
INP1
INP2
INP3
INP4
INP5
INP6
INP7
GPO
ALT1
ALT2
ALT3
SCU
Timer 21
GPT12T5
UART1
GPT12T2
CCU6
T2INB
CCPOS1_2
MRST_1_3
P1_DATA.P4
CLKOUT_1
COUT62_0
RxD1
SSC1
Output
SCU
CCU6
UART1 / LIN_RxD
Data Sheet
50
Rev. 1.0, 2015-04-30
TLE9869QXA20
GPIO Ports and Peripheral I/O
14.3.3
Port 2
14.3.3.1 Port 2 Functions
Table 10
Port Pin
P2.0
Port 2 Input Functions
Input/Output
Select
Connected Signal(s)
P2_DATA.P0
CCPOS0_3
-
From/to Module
Input
GPI
INP1
INP2
INP3
INP4
INP5
ANALOG
CCU6
-
T12HR_2
EXINT0_0
CC61_2
CCU6
SCU
CCU6
ADC
XTAL
AN0
XTAL (in)
P2_DATA.P2
CCPOS2_3
T13HR_2
–
P2.2
Input
GPI
INP1
INP2
INP3
INP4
ANALOG
OUT
CCU6
CCU6
CC62_2
CCU6
ADC
AN2
XTAL (out)
P2_DATA.P3
CCPOS1_0
T3IND
XTAL
P2.3
Input
GPI
INP1
INP2
INP3
INP4
INP5
INP6
ANALOG
GPI
CCU6
GPT12T3
CCU6
Timer 21
CCU6
SCU
CTRAP#_1
T21EX_2
CC60_1
EXINT0_3
AN3
ADC
P2.4
P2.5
Input
Input
P2_DATA.P4
CTRAP#_0
T2EUDB
MRST_1_1
EXINT1_3
AN4
INP1
INP2
INP3
INP4
ANALOG
GPI
CCU6
GPT12T2
SSC1
SCU
ADC
P2_DATA.P5
RXD2_1
T3EUDB
MRST_2_1
T2_1
INP1
INP2
INP3
INP4
ANALOG
UART2
GPT12T3
SSC2
Timer 2
ADC
AN5
Data Sheet
51
Rev. 1.0, 2015-04-30
TLE9869QXA20
General Purpose Timer Units (GPT12)
15
General Purpose Timer Units (GPT12)
15.1
Features
15.1.1
Features Block GPT1
The following list summarizes the supported features:
•
•
•
•
fGPT/4 maximum resolution
3 independent timers/counters
Timers/counters can be concatenated
4 operating modes:
– Timer Mode
– Gated Timer Mode
– Counter Mode
– Incremental Interface Mode
Reload and Capture functionality
Shared interrupt: Node 0
•
•
15.1.2
Features Block GPT2
The following list summarizes the supported features:
•
•
•
•
fGPT/2 maximum resolution
2 independent timers/counters
Timers/counters can be concatenated
3 operating modes:
– Timer Mode
– Gated Timer Mode
– Counter Mode
•
•
Extended capture/reload functions via 16-bit capture/reload register CAPREL
Shared interrupt: Node 1
15.2
Introduction
The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures which
may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and
other purposes.
They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each
block may operate independently in a number of different modes such as Gated timer or Counter Mode, or may
be concatenated with another timer of the same block.
Each block has alternate input/output functions and specific interrupts associated with it. Input signals can be
selected from several sources by register PISEL.
The GPT module is clocked with clock fGPT. fGPT is a clock derived from fSYS
.
Data Sheet
52
Rev. 1.0, 2015-04-30
TLE9869QXA20
General Purpose Timer Units (GPT12)
15.2.1
Block Diagram GPT1
Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The
maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture
registers for the core timer.
T3CON.BPS1
2n : 1
Basic clock
fGPT
Interrupt Request
(T2IRQ)
Aux. Timer T2
Core Timer T3
Aux. Timer T4
U/D
T2IN
T2
Mode
Control
Capture
Reload
T2EUD
Toggle Latch
T3
Mode
Control
T3IN
T3OTL
T3OUT
U/D
T3EUD
Interrupt Request
(T3IRQ)
Capture
Reload
T4IN
T4
Mode
Control
T4EUD
Interrupt Request
(T4IRQ)
U/D
MC _GPT0101_bldiax1.vsd
Figure 19 GPT1 Block Diagram (n = 2 … 5)
Data Sheet
53
Rev. 1.0, 2015-04-30
TLE9869QXA20
General Purpose Timer Units (GPT12)
15.2.2
Block Diagram GPT2
Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum resolution
is fGPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation with extended
functionality.
T6CON.BPS2
fGPT
2n : 1
Basic clock
Toggle FF
T5
Mode
Control
U/D
InterruptRequest
(T5IR)
T5IN
GPT2 Timer T5
Clear
T5EUD
Capture
CAPIN
CAPREL
Mode
Control
GPT2 CAPREL
T3IN/
T3EUD
InterruptRequest
(CRIR)
Reload
InterruptRequest
(T6IR)
Clear
U/D
T6
Mode
Control
GPT2 Timer T6
T6OTL
T6OUT
T6OUF
T6IN
T6EUD
MC_GPT0108_bldiax4.vsd
Figure 20 GPT2 Block Diagram
Data Sheet
54
Rev. 1.0, 2015-04-30
TLE9869QXA20
Timer2 and Timer21
16
Timer2 and Timer21
16.1
Features
•
•
16-bit auto-reload mode
– selectable up or down counting
One channel 16-bit capture mode
16.2
Introduction
The timer modules are general-purpose 16-bit timers. Timer 2/21 can function as a timer or counter in each of its
modes. As a timer, it counts with an input clock of fPCLK/12 (if prescaler is disabled). As a counter, Timer 2 counts
1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is fPCLK/24 (if prescaler is
disabled).
16.2.1
Timer2 and Timer21 Modes Overview
Table 11
Mode
Timer2 and Timer21 Modes
Description
Auto-reload
Up/Down Count Disabled
•
•
•
Count up only
Start counting from 16-bit reload value, overflow at FFFFH
Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
Programmable reload value in register RC2
Interrupt is generated with reload events.
•
•
Auto-reload
Up/Down Count Enabled
•
•
•
Count up or down, direction determined by level at input pin T2EX
No interrupt is generated
Count up
– Start counting from 16-bit reload value, overflow at FFFFH
– Reload event triggered by overflow condition
– Programmable reload value in register RC2
Count down
•
– Start counting from FFFFH, underflow at value defined in register RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFFH
Channel capture
•
•
•
•
•
•
•
Count up only
Start counting from 0000H, overflow at FFFFH
Reload event triggered by overflow condition
Reload value fixed at 0000H
Capture event triggered by falling/rising edge at pin T2EX
Captured timer value stored in register RC2
Interrupt is generated by reload or capture events
Data Sheet
55
Rev. 1.0, 2015-04-30
TLE9869QXA20
Timer3
17
Timer3
17.1
Features
•
•
•
•
•
•
16-bit incremental timer/counter (counting up)
Counting frequency up to fsys
Selectable clock prescaler
6 modes of operation
Interrupt up on overflow
Interrupt on compare
17.2
Introduction
The possible applications for the timer include measuring the time interval between events, counting events and
generating a signal at regular intervals.
Timer3 can function as timer or counter. When functioning as a timer, Timer3 is incremented in periods based on
the MI_CLK or LP_CLK clock. When functioning as a counter, Timer3 is incremented in response to a 1-to-0
transition (falling edge) at its respective input. Timer3 can be configured in four different operating modes to use
in a variety of applications, see Table 12.
Several operating modes can be used for different tasks such as the following:
•
•
•
simple time measurement between two events
triggering of the measuring unit upon PWM/CCU6 unit
measurement of the 100kHz LP_CLK2
17.3
Functional Description
Six modes of operation are provided to fulfill various tasks using this timer. In every mode the clocking source can
be selected between MI_CLK and LP_CLK. A prescaler provides in addition capability to divide the selected clock
source by 2, 4 or 8. The timer counts upwards, starting with the value in the timer count registers, until the
maximum count value which depends on the selected mode of operation. Timer 3 provides two individual
interrupts upon counter overflow, one for the low-byte and one for the high-byte counter register.
17.3.1
Timer3 Modes Overview
The following table provides an overview of the timer modes together with the reasonable configuration options in
Table 12.
Table 12
Mode
Timer3 Modes
Sub- Operation
Mode
No Sub- 13-bit Timer
0
1
1
Mode
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
a
16-bit Timer
The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter.
b
16-bit Timer triggered by an event
The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter, which is
triggered by an event to enable a single shot measurement on a preset channel with the
measurement unit.
Data Sheet
56
Rev. 1.0, 2015-04-30
TLE9869QXA20
Timer3
Table 12
Mode
Timer3 Modes (cont’d)
Sub- Operation
Mode
No Sub- 8-bit Timer with auto-reload
2
3
3
Mode
The timer register TL3 is reloaded with a user-defined 8-bit value in TH3 upon overflow.
a
Timer3 operates as two 8-bit timers
The timer registers TL3 and TH3, operate as two separate 8-bit counters.
b
Timer3 operates as Two 8-bit timers for clock measurement
The timer registers, TL3 and TH3 operate as two separate 8-bit counters. In this mode the
LP_CLK2 Low Power Clock can be measured. TL3 acts as an edge counter for the clock
edges and TH3 as a counter which counts the time between the edges.
Data Sheet
57
Rev. 1.0, 2015-04-30
TLE9869QXA20
Capture/Compare Unit 6 (CCU6)
18
Capture/Compare Unit 6 (CCU6)
18.1
Feature Set Overview
This section gives an overview over the different building blocks and their main features.
Timer 12 Block Features
•
•
Three capture/compare channels, each channel can be used either as capture or as compare channel
Generation of a three-phase PWM supported (six outputs, individual signals for high-side and low-side
switches)
•
•
•
•
•
•
•
•
•
16-bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of T12 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Multiple interrupt request sources
Hysteresis-like control mode
Timer 13 Block Features
•
•
•
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Concurrent update of T13 registers
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Additional Specific Functions
•
•
•
•
•
•
•
•
Block commutation for brushless DC-drives implemented
Position detection via hall-sensor pattern
Noise filter supported for position input signals
Automatic rotational speed measurement and commutation control for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
18.2
Introduction
The CCU6 unit is made up of a Timer T12 block with three capture/compare channels and a Timer T13 block with
one compare channel. The T12 channels can independently generate PWM signals or accept capture triggers, or
they can jointly generate control signal patterns to drive DC-motors or inverters.
A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible generation
of interrupt request signals provide efficient software-control.
Data Sheet
58
Rev. 1.0, 2015-04-30
TLE9869QXA20
Capture/Compare Unit 6 (CCU6)
Note:The capture/compare module itself is referred to as CCU6 (capture/compare unit 6). A capture/compare
channel inside this module is referred to as CC6x.
The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined
(e.g. a channel works in compare mode, whereas another channel works in capture mode). The timer T13 can
work in compare mode only. The multi-channel control unit generates output patterns which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal modulation.
18.2.1
Block Diagram
CCU6 Module Kernel
Compare
CC60
CC61
CC62
1
T12SUSP
Dead-
Time
Control
Multi-
channel
Control
Debug
Suspend
Trap
Control
T12
T13
1
1
T13SUSP
fCC 6
Clock
Control
CC63
1
3
2
2
2
3
1
SR[3:0]
Interrupt
Control
Input / Output Control
PortControl
CCU6_MCB05506.vsd
P0.x
P1.x
P2.x
Figure 21 CCU6 Block Diagram
Data Sheet
59
Rev. 1.0, 2015-04-30
TLE9869QXA20
UART1/UART2
19
UART1/UART2
19.1
Features
•
Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– fixed or variable baud rate
•
•
•
•
•
Receive buffered
Multiprocessor communication
Interrupt generation on the completion of a data transmission or reception
Baud-rate generator with fractional divider for generating a wide range of baud rates
Hardware logic for break and synch byte detection
19.2
Introduction
The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive
simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously
received byte has been read from the receive register. However, if the first byte still has not been read by the time
reception of the second byte is complete, one of the bytes will be lost. The serial port receive and transmit registers
are both accessed at Special Function Register (SFR) SBUF. Writing to SBUF loads the transmit register, and
reading SBUF accesses a physically separate receive register.
19.2.1
Block Diagram
UART disreq from SCU_DM
RI
TXD
RXD
TXD
SCU_D
M
Interrupt
Control
RXD_0
RXD_1
TI
URIOS
SCU_DM
P0.x
P1.x
P2.x
UART
Module
(Kernel)
PortControl
fUART2
Clock
Control
Baud Rate
Generator
f
BR
Address
Decoder
RXDO _2
SCU_DM
AHB Interface
SSC Module
GPIOs
Figure 22 UART Block Diagram
Data Sheet
60
Rev. 1.0, 2015-04-30
TLE9869QXA20
UART1/UART2
19.3
UART Modes
The UART can be used in four different modes. In mode 0, it operates as an 8-bit shift register. In mode 1, it
operates as an 8-bit serial port. In modes 2 and 3, it operates as a 9-bit serial port. The only difference between
mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is
set by the underflow rate on the dedicated baud-rate generator.
The different modes are selected by setting bits SM0 and SM1 to their corresponding values, as shown in
Table 13.
Table 13
UART Modes
SM1
SM0
Operating Mode
Mode 0: 8-bit shift register
Baud Rate
0
0
1
1
0
1
0
1
f
PCLK/2
Variable
PCLK/64
Variable
Mode 1: 8-bit shift UART
Mode 2: 9-bit shift UART
Mode 3: 9-bit shift UART
f
The UART1 is connected to the integrated LIN transceiver, and to GPIO for test purpose. The UART2 is connected
to GPIO only.
Data Sheet
61
Rev. 1.0, 2015-04-30
TLE9869QXA20
LIN Transceiver
20
LIN Transceiver
20.1
Features
General Functional Features
•
•
Compliant to LIN2.2 standard, backward compatible to LIN1.3, LIN2.0 and LIN 2.1
Compliant to SAE J2602 (slew rate, receiver hysteresis)
Special Features
•
•
•
Measurement of LIN master baudrate via Timer 2
LIN can be used as input/output with SFR bits.
TxD timeout feature (optional, on by default)
Operation Mode Features
•
•
•
•
LIN Sleep Mode (LSLM)
LIN Receive-Only Mode (LROM)
LIN Normal Mode (LNM)
High Voltage Input / Output Mode (LHVIO)
Supported Baud Rates
•
•
•
•
Mode for a transmission up to 10.4 kBaud
Mode for a transmission up to 20 kBaud
Mode for a transmission up to 40 kBaud
Mode for a transmission up to 115.2 kBaud
Slope Mode Features
•
•
•
Normal Slope Mode (20 kbit/s)
Low Slope Mode (10.4 kbit/s)
Flash Mode (115.2 kbit/s)
Wake-Up Features
LIN bus wake-up
•
Data Sheet
62
Rev. 1.0, 2015-04-30
TLE9869QXA20
LIN Transceiver
20.2
Introduction
The LIN Module is a transceiver for the Local Interconnect Network (LIN) compliant to the LIN2.2 standard,
backward compatible to LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller and
the physical network. The LIN bus is a single wire, bi-directional bus typically used for in-vehicle networks, using
baud rates between 2.4 kBaud and 20 kBaud. Additionally baud rates up to 115.2 kBaud are implemented.
The LIN Module offers several different operation modes, including a LIN Sleep Mode and the LIN Normal Mode.
The integrated slope control allows to use several data transmission rates with optimized EMC performance. For
data transfer at the end of line, a Flash Mode up to 115.2 kBaud is implemented. This Flash Mode can be used
for data transfer under special conditions for up to 250 kbit/s (in production environment, point-to-point
communication with reduced wire length and limited supply voltage).
20.2.1
Block Diagram
VS
LIN Transceiver
30 k
LIN_CTRL_STS
LIN-FSM
LIN
CTRL
Driver +
Curr. Limit. +
TSD
TxD_1
from UART
STATUS
GND_LIN
Transmitter
Filter
RxD_1
to UART
Receiver
Filter
LIN_Wake
Sleep Comparator
LIN_Block_Diagram_Customer.vsd
GND_LIN
Figure 23 LIN Transceiver Block Diagram
Data Sheet
63
Rev. 1.0, 2015-04-30
TLE9869QXA20
High-Speed Synchronous Serial Interface (SSC1/SSC2)
21
High-Speed Synchronous Serial Interface (SSC1/SSC2)
21.1
Features
•
Master and Slave Mode operation
– Full-duplex or half-duplex operation
•
•
Transmit and receive buffered
Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit (MSB) shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
Variable baud rate
•
•
•
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
– On a transmitter empty condition
– On a “receiver full” condition
– On an error condition (receive, phase, baud rate, transmission error)
Data Sheet
64
Rev. 1.0, 2015-04-30
TLE9869QXA20
High-Speed Synchronous Serial Interface (SSC1/SSC2)
21.2
Introduction
The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial synchronous
communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-
bit baud rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock
polarity, and phase are programmable. This allows communication with SPI-compatible devices or devices using
other synchronous serial interfaces.
Data is transmitted or received on TXD and RXD lines, which are normally connected to the MTSR
(MasterTransmit/Slave Receive) and MRST (Master Receive/Slave Transmit) pins. The clock signal is output via
line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are
normally connected to the pin SCLK. Transmission and reception of data are double-buffered.
21.2.1
Block Diagram
Figure 24 shows all functional relevant interfaces associated with the SSC Kernel.
MRSTA
MRSTB
EIR
MTSR
SCU_DM
Interrupt
Control
RIR
TIR
MTSRA
MTSRB
P0.x
P1.x
P2.x
SSC
Port
Control
Module
(Kernel)
MRST
fhw_clk
Clock
Control
SCLKA
SCLKB
Address
Decoder
SCLK
AHB Interface
Module
ProductInterface
SSC_interface_overview.vsd
Figure 24 SSC Interface Diagram
Data Sheet
65
Rev. 1.0, 2015-04-30
TLE9869QXA20
Measurement Unit
22
Measurement Unit
22.1
Features
•
•
•
•
•
•
1 x 8-bit ADC with 10 Inputs including attenuator allowing measurement of high voltage input signals
Supply Voltage Attenuators with attenuation of VBAT_SENSE, VS, VDDP and VDDC.
VBG monitoring of 8-bit ADC to guarantee functional safety requirements.
Bridge Driver Diagnosis Measurement (VDH, VCP).
Temperature Sensor for monitoring the chip temperature and PMU Regulator temperature.
Supplement Block with Reference Voltage Generation, Bias Current Generation, Voltage Buffer for NVM
Reference Voltage, Voltage Buffer for Analog Module Reference Voltage and Test Interface.
22.2
Introduction
The measurement unit is a functional unit that comprises the following associated sub-modules:
Table 14
Measurement Functions and Associated Modules
Module
Name
Modules
Functions
Central Functions Bandgap reference circuit
Unit
The bandgap-reference sub-module provides two
reference voltages
1. a trimmable reference voltage for the 8-bit ADCs. A
local dedicated bandgap circuit is implemented to avoid
deterioration of the reference voltage arising e.g. from
crosstalk or ground voltage shift.
2. the reference voltage for the NVM module
8-bit ADC (ADC2) 8-bit ADC module with 10
multiplexed inputs, including HV
input attenuator
5 high voltage full supply range capable inputs
(2.5V...30,7V(FS))
2 medium voltage inputs (0..5V/7V FS).
3 low voltage inputs (0..1.2V/1.6V FS)
(allocation see following overview figure)
10-bit ADC
(ADC1)
10-bit ADC module with 8
multiplexed inputs
Five (5V) analog inputs from Port 2.x
VDH Input
Voltage
VDH input voltage attenuator
Scales down V(VDH) to the input voltage range of
ADC1.CH6
Attenuator
Temperature
Sensor
Temperature sensor with two
multiplexed sensing elements:
Generates output voltage which is a linear function of
the local chip (junction) temperature.
•
•
PMU located sensor
Central chip located sensor
Measurement
Core Module
Digital signal processing and ADC2 1. Generates the control signal for the 8-bit ADC2 and
control unit
the synchronous clock for the switched capacitor
circuits,
2. Performs digital signal processing functions and
provides status outputs for interrupt generation.
Data Sheet
66
Rev. 1.0, 2015-04-30
TLE9869QXA20
Measurement Unit
22.2.1
Block Diagram
VAGND
VS
VAREF
P2.0
OP1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
5
V
GND_SENSE
OP
OP2
P2.2
G = 10/20/40/60
ADC 1
10
/
MUX
SFR
A
D
Channel sequencer
P2.3
P2.4
P2.5
VDH
x 0.226
x 0.166
rfu
10 Bit ADC + DPP1
Programmable
range setting
x 0.055
x 0.039
x 0.055
x 0.039
VBAT_SENSE
CH0
CH1
CH2
CH3
CH4
CH5
1.23
V
VSD
VCP
x 0.039
x 0.023
x 0.039
x 0.164
x 0.219
calibration & filter unit
with
upper / lower
threshold
MON
VDDP
8
/
SFR
MUX
A
D
detection / interrupt
VAREF
CH6
CH7
ADC 2
PMU-VBG
CH8
CH9
VDDC
x 0.75
Temperature
Sensor
8 Bit ADC + DPP2
Measurement-Unit
Measurement_Unit_Overview_TLE9869_B15.vsd
Figure 25
Measurement Unit-Overview (with opamp)
Data Sheet
67
Rev. 1.0, 2015-04-30
TLE9869QXA20
Measurement Core Module (incl. ADC2)
23
Measurement Core Module (incl. ADC2)
23.1
Features
•
•
•
•
8 individually programmable channels split into two groups of user configurable and non user configurable
Individually programmable channel prioritization scheme for measurement unit
Two independent filter stages with programmable low-pass and time filter characteristics for each channel
Two channel configurations:
– Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis
– Two individually programmable trigger thresholds with limit hysteresis settings
Individually programmable interrupts and statuses for all channel thresholds
•
23.2
Introduction
The basic function of this block is the digital postprocessing of several analog digitized measurement signals by
means of filtering, level comparison and interrupt generation. The measurement postprocessing block consists of
ten identical channel units attached to the outputs of the 10-channel 8-bit ADC (ADC2). It processes ten channels,
where the channel sequence and prioritization is programmable within a wide range.
23.2.1
Block Diagram
4
/
MUX_SEL<3:0>
Channel Controller
(Sequencer)
ADC2 - SFR
VBAT_SENSE
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
VS
VSD
1st Order IIR
1
/
+
-
8 Bit ADC
UP_X_STS
VCP
+ / -
+ / -
THy_z_UPPER.
CHx
Calibration Unit:
y= a + (1+b)*x
8
/
10
/
8
/
MON
MUX
A
D
VDDP
1
/
THy_z_LOWER.
CHx
-
VAREF
LOW_X_STS
+
PMU-VBG
VDDC
Digital Signal Processing
Temperature Sensor
TSENSE
Measurement Core Module
Figure 26 Module Block Diagram
Data Sheet
68
Rev. 1.0, 2015-04-30
TLE9869QXA20
Measurement Core Module (incl. ADC2)
23.2.2
Measurement Core Module Modes Overview
The basic function of this unit, is the digital signal processing of several analog digitized measurement signals by
means of filtering, level comparison and interrupt generation. The Measurement Core module processes ten
channels in a quasi parallel process.
As shown in the figure above, the ADC2 postprocessing unit consists of a channel controller (Sequencer), an 10-
channel demultiplexer and the signal processing block, which filters and compares the sampled ADC2 values for
each channel individually. The channel control block controls the multiplexer sequencing on the analog side before
the ADC2 and on the digital domain after the ADC2. As described in the following section, the channel sequence
can be controlled in a flexible way, which allows a certain degree of channel prioritization.
This capability can be used e.g. to set a higher priority to supply voltage channels compared to the other channel
measurements. The Measurement Core Module offers additionally two different post-processing measurement
modes for over-/undervoltage detection and for two-level threshold detection.
The channel controller (sequencer) runs in one of the following modes:
“Normal Sequencer Mode” – channels are selected according to the 10 sequence registers which contain
individual enablers for each of the 10 channels.
“Exceptional Interrupt Measurement” – following a hardware event, a high priority channel is inserted into the
current sequence. The current actual measurement is not destroyed.
“Exceptional Sequence Measurement” – following a hardware event, a complete sequence is inserted after the
current measurement is finished. The current sequence is interrupted by the exception sequence.
Data Sheet
69
Rev. 1.0, 2015-04-30
TLE9869QXA20
10-Bit Analog Digital Converter (ADC1)
24
10-Bit Analog Digital Converter (ADC1)
24.1
Features
The principal features of the ADC1 are:
•
•
Up to 8 analog input channels (channel 7 reserved for future use)
Flexible results handling
- 8-bit and 10-bit resolution
•
Flexible source selection due to sequencer
- insert one exceptional sequence (ESM)
- insert one interrupt measurement into the current sequence (EIM), single or up to 128 times
- software mode
•
•
•
•
•
•
•
Conversion sample time (separate for each channel) adjustable to adapt to sensors and reference
Standard external reference (VAREF) to support ratiometric measurements and different signal scales
DMA support, transfer ADC conversion results via DMA into RAM
Support of suspend and power saving modes
Result data protection for slow CPU access (wait-for-read mode)
Programmable clock divider
Integrated sample and hold circuitry
24.2
Introduction
The TLE9869QXA20 includes a high-performance 10-bit Analog-to-Digital Converter (ADC1) with eight
multiplexed analog input channels. The ADC1 uses a successive approximation technique to convert the analog
voltage levels from up to eight different sources. The analog input channels of the ADC1 are available at AN0,
AN2 - AN5.
Data Sheet
70
Rev. 1.0, 2015-04-30
TLE9869QXA20
10-Bit Analog Digital Converter (ADC1)
24.2.1
Block Diagram
3
3
/
/
MUX_SEL <2:0>
Channel Controller
(Sequencer)
ADC1 - SFR
10
10
10
10
10
10
10
10
10
/
/
/
/
/
/
/
/
/
ADC1_OUT_CH0
ADC1_OUT_CH1
ADC1_OUT_CH2
ADC1_OUT_CH3
ADC1_OUT_CH4
ADC1_OUT_CH5
ADC1_OUT_CH6
ADC1_OUT_CH7
ADC1_RES_OUT_EIM
P2.0
CH0
CH1
CH2
CH3
ADC1
P2.2
P2.3
P2.4
P2.5
VDH
rfu
10
MUX
A
D
/
MUX
CH4
CH5
CH6
CH7
OP1
OP2
OPA
ADC10B_Signal_Conditioning_TLE9869_B15.vsd
Figure 27
ADC1 Top Level Block Diagram
As shown in the figure above, the ADC1 postprocessing consists of a channel controller (Sequencer) and an 8-
channel demultiplexer. The channel control block controls the multiplexer sequencing on the analog side before
the ADC1 and on the digital domain after the ADC1. As described in the following section, the channel sequence
can be controlled in a flexible way, which allows a certain degree of channel prioritization.
This capability can be used e.g. to give a higher priority to some channels compared to the other channel
measurements.
Data Sheet
71
Rev. 1.0, 2015-04-30
TLE9869QXA20
High-Voltage Monitor Input
25
High-Voltage Monitor Input
25.1
Features
•
•
•
•
High-voltage input with VS/2 threshold voltage
Integrated selectable pull-up and pull-down current sources
Wake capability for power saving modes
Level change sensitivity configurable for transitions from low to high, high to low or both directions
25.2
Introduction
This module is dedicated to monitor external voltage levels above or below a specified threshold or it can be used
to detect a wake-up event at the high-voltage MON pin in low-power mode. The input is sensitive to a input level
monitoring, this is available when the module is switched to active mode with the SFR bit EN.
To use the Wake function during low power mode of the IC, the monitoring pin is switched to Sleep Mode via the
SFR bit EN.
25.2.1
Block Diagram
VS
MON
+
-
Filter
to internal
circuitry
MON
Logic
SFR
MONx_Input_Circuit_ext.vsd
Figure 28 Monitoring Input Block Diagram
Data Sheet
72
Rev. 1.0, 2015-04-30
TLE9869QXA20
Bridge Driver (incl. Charge Pump)
26
Bridge Driver (incl. Charge Pump)
26.1
Features
The MOSFET Driver is intended to drive external normal level NFET transistors in bridge configuration. The driver
provides many diagnostic possibilities to detect faults.
Functional Features
•
External Power NFET Transistor Driver Stage with driver capability for max. 100 nC gate charge @ 25 kHz
switching frequency.
•
•
Implemented adjustable cross conduction protection.
Supply voltage (VSD) monitoring incl. adjustable over- and undervoltage shutdown with configurable interrupt
signalling.
•
•
•
VSD operating range down to 5.4 V
VDS comparators for short circuit detection in on- and off-state
Open-Load detection in off-state
26.2
Introduction
The MOSFET Driver Stage can be used for controlling external Power NFET Transistors (normal level). The
module output is controlled by SFR or System PWM Machine (CCU6).
Data Sheet
73
Rev. 1.0, 2015-04-30
TLE9869QXA20
Bridge Driver (incl. Charge Pump)
26.2.1
Block Diagram
VDH
VCP
PWM-Unit
CCU6
(not part of the module )
Pre-Driver
+
VDS
-
>1
>1
GHx
VREF
SFR
SHx
+
VDS
GLx
-
VREF
SL
Block_Diagram_PreDriver_Cus.vsd
Figure 29 Driver Module Block Diagram (incl. system connections)
26.2.2
General
The Driver can be controlled in two different ways:
•
In Normal Mode the output stage is fully controllable through the SFR registers CTRLx (x = 1,2,3). Protection
functions such as overcurrent and open-load detection are available.
•
The PWM Mode can also be enabled by the corresponding bit in CTRL1 and CTRL2. The PWM must be
configured in the System PWM Module (CCU6). All protection functions are available in PWM mode as well.
Protection Functions
•
•
•
Overcurrent detection and shutdown feature for external MOSFET by Drain Source measurement
Programmable minimum cross current protection time
Open-load detection feature in Off-state for external MOSFET.
Data Sheet
74
Rev. 1.0, 2015-04-30
TLE9869QXA20
Current Sense Amplifier
27
Current Sense Amplifier
27.1
Features
Main Features
•
•
•
•
Programmable gain settings: G = 10, 20, 40, 60
Differential input voltage: ± 1.5V / G
Wide common mode input range ± 2 V
Low setting time < 1.4 µs
27.2
Introduction
The current sense amplifier in Figure 30 can be used to measure near ground differential voltages via the 10-bit
ADC. Its gain is digitally programmable through internal control registers.
Linear calibration has to be applied to achieve high gain accuracy, e.g. end-of-line calibration including the shunt
resistor.
Figure 30 shows how the current sense amplifier can be used as a low-side current sense amplifier where the
motor current is converted to a voltage by means of a shunt resistor RSH. A differential amplifier input is used in
order to eliminate measurement errors due to voltage drop across the stray resistance RStray and differences
between the external and internal ground. If the voltage at one or both inputs is out of the operating range, the
input circuit is overloaded and requires a certain specified recovery time.
In general, the external low pass filter should provide suppression of EMI.
27.2.1
Block Diagram
VBAT
M
V
5V
AREF
VZERO
Motor
Current
Amplifier
configurable
LP Filter
OP2
OP1
ROPAFILT
Gain: 10, 20, 40, 60
VP
Vzero + (VOP2 -VOP1) * G
10
/
10-bit ADC
RSH
COPAFILT
ROPAFILT
ADC1_OUT_CH1
VN
CSA_CTRL
RStray
Ext. GND
Current_Sense_Amplifier.vsd
Figure 30 Simplified Application Diagram
Data Sheet
75
Rev. 1.0, 2015-04-30
TLE9869QXA20
Application Information
28
Application Information
28.1
H-Bridge Driver
Figure 31 shows the TLE9869QXA20 in an electric drive application setup controlling an H-Bridge motor.
Note:The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Rev . Polarity Protection
LPFILT
VBAT
CPFILT
CPFILT
1
1
TRP
CVD DP 2
CVDD P1
CVDDC1
CVDDC2
EMC Filter
DRP
RRP1
DVS
VDDP VDDC
RRP2
VS
TRPG
CP1H
CP1L
CP2H
CCPS1
CVS2
CVS 1
Switch
CCPS2
CP2L
VCP
RVBAT
_SEN SE
VBAT_SENSE
RVSD
CVCP
CVBAT
_SEN SE
VSD
CVSD
RVDH
CVDH
VDH
LIN
LIN
CLIN
GND_LIN
VAREF
CVAREF
D
S
D
S
GND_REF
RGATE
G
G
GH1
TH1
CPH
TH2
1
CPH2
VDD_EXT
P0.3
RGS
CGS
RGS
CGS
CVDD _EXT
CVDD_EXT
2
1
RVDDPU
TLE4946 -2K
Hall
RGATE
GH2
SH2
RAD C
CADC
CEMC
M
RMON
MON
SH1
GL1
CMON
TLE9869
CEMC
D
S
D
S
RGATE
G
G
RSWITCH
TL1
TL2
RGS
CGS
Temp Sensor
RGS
CGS
P2.2
P1.2
RGATE
GL2
SL
ROPAFILT
P1.0
OP2
OP1
RShunt
COPAFILT
ROPAFILT
TMS
P0.0
Debug Connector
P0.1
P0.4
P2.5
P1.3
GND
RTMS
GND
H-Bridge System
Figure 31 Simplified Application Diagram Example
Note:This is a very simplified example of an application circuit and bill of materials. The function must be verified
in the actual application.
Data Sheet
76
Rev. 1.0, 2015-04-30
TLE9869QXA20
Application Information
Table 15
Symbol
CVS1
External Components (BOM)
Function
Component
Blocking capacitor at VS pin
Blocking capacitor at VS pin
Blocking capacitor at VDDP pin
Blocking capacitor at VDDEXT pin
Blocking capacitor at VDDC pin
Blocking capacitor at VAREF pin
Standard C for LIN slave
≥ 100 nF Ceramic, ESR < 1Ω
> 2.2 µF Elco1)
CVS2
CVDDP
CVDD_EXT
CVDDC
CVAREF
CLIN
470 nF + 100 nF Ceramic, ESR < 1Ω
100nF, Ceramic ESR < 1Ω
470 nF + 100 nF Ceramic, ESR < 1Ω
100 nF, Ceramic ESR < 1Ω
220 pF
CVSD
Filter C for charge pump end driver 1 µF
CCPS1
CCP2S
CVCP
Charge pump capacitor
Charge pump capacitor
Charge pump capacitor
Filter C for ISO pulses
Capacitor
220 nF
220 nF
470 nF
10nF
1 nF
CMON1
CVDH
CPH1
Capacitor
220 µF
220 µF
100 nF
1 nF
CPH2
Capacitor
COPAFILT
CEMCP1
CEMCP2
Capacitor
Capacitor
Capacitor
1 nF
C
PFILT1, CPFILT2
CVBAT_SENSE
RMON1
Capacitor
10 µF
10 nF
1kΩ
Capacitor
Resistor at MON pin
RVSD
Limitation of reverse current due to
transient (-2V, 8ms)
2Ω
RVDH
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
1kΩ
2Ω
RGATE
ROPAFILT
RVBAR_SENSE
RSH1
12Ω
optional
optional
RSH2
LPFILT
DVS
Reverse-polarity protection diode
–
1) The capacitor must be dimensioned so as to ensure that flash operations modifying the content of the flash are never
interrupted (e.g. in case of power loss).
Data Sheet
77
Rev. 1.0, 2015-04-30
TLE9869QXA20
Application Information
28.2
ESD Immunity According to IEC61000-4-2
Note:Tests for ESD immunity according to IEC61000-4-2 “Gun test” (150pF, 330Ω) has been performed. The
results and test condition will be available in a test report.
Table 16
ESD “Gun Test”
Performed Test
Result
Unit
Remarks
ESD at pin LIN, versus
GND1)
> 6
kV
2)positive pulse
ESD at pin LIN, versus
GND1)
< -6
kV
2)negative pulse
1) ESD test “ESD GUN” is specified with external components; see application diagram:
MON = 100nF, RMON = 1kΩ, CLIN = 220pF, CVS = >20µF ELCO + 100nF ESR < 1Ω, CVSD = 1µF, RVSD = 2Ω.
C
2) ESD susceptibility “ESD GUN” according to LIN EMC Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external
test house (IBEE Zwickau, EMC Test report Nr. 09-07-14)
Data Sheet
78
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29
Electrical Characteristics
This chapter includes all relevant electrical characteristics of the product TLE9869QXA20.
29.1
General Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings1)
29.1.1
Table 17
Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min. Typ. Max.
Voltages – Supply Pins
Supply voltage – VS
Supply voltage – VSD
Supply voltage – VSD
VS
-0.3
-0.3
–
–
–
40
48
48
V
V
V
Load dump
–
P_1.1.1
P_1.1.2
VSD
VSD_max_exten -2.8
Series resistor RVSD = P_1.1.32
2.2 Ω, t = 8 ms 2)
d
Voltage range – VDDP
Voltage range – VDDP
VDDP
-0.3
–
–
5.5
7
V
V
–
P_1.1.3
VDDP_max_ext -0.3
In case of voltage
transients on VS with
dVS/dt ≤ 1V/µs;
P_1.1.41
end
duration: t ≤ 150µs;
CVDDP ≤ 570 nF
Voltage range – VDDEXT
Voltage range – VDDEXT
VDDEXT
-0.3
–
–
5.5
7
V
V
–
P_1.1.4
VDDEXT_max_ -0.3
In case of voltage
transients on VS with
dVS/dt ≤ 1V/µs;
P_1.1.42
extend
duration: t ≤ 150µs;
CVDDEXT ≤ 570 nF
Voltage range – VDDC
Voltages – High Voltage Pins
Battery voltage VBAT_SENSE
Input voltage at LIN
VDDC
-0.3
–
1.6
V
–
P_1.1.5
3)
VBAT_SENSE -28
VLIN -28
–
40
40
40
40
48
19
48
48
19
V
V
V
V
V
V
V
V
V
P_1.1.6
P_1.1.7
P_1.1.8
P_1.1.38
P_1.1.9
P_1.1.44
P_1.1.11
P_1.1.13
P_1.1.45
–
–
4)
Input voltage at MON
VMON_maxrate -28
VVDH_maxrate -2.8
–
5)
6)
Input voltage at VDH
–
Voltage range at GHx
VGH
-6.0
14
–
Voltage range at GHx vs. SHx
Voltage range at SHx
VGHvsSH
VSH
16
–
–
-6.0
-6.0
14
–
7)
Voltage range at GLx
VGL
–
–
Voltage range at GLx vs. SL
VGLvsSL
16
–
Data Sheet
79
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 17
Absolute Maximum Ratings1) (cont’d)
Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min. Typ. Max.
8)
Voltage range at charge pump
pins CP1H, CP1L, CP2H, CP2L,
VCP
VCPx
-0.3
–
48
V
P_1.1.15
Voltages – GPIOs
9)
Voltage on any port pin
Vin
-0.3
–
–
VDDP
+0.3
V
VIN < VDDPmax
P_1.1.16
P_1.1.35
Current at VCP Pin
Max. current at VCP pin
Injection Current at GPIOs
IVCP
-15
-5
–
mA
–
10)
10)
Injection current on any port pin IGPIONM
–
–
5
mA
mA
P_1.1.34
P_1.1.30
Sum of all injected currents in
Normal Mode
IGPIOAM_sum -50
50
10)
10)
Sum of all injected currents in
Power Down Mode (Stop Mode)
IGPIOPD_sum -5000 –
50
5
µA
P_1.1.36
P_1.1.37
Sum of all injected currents in
Sleep Mode
IGPIOSleep_su -5
–
mA
m
Other Voltages
Input voltage VAREF
VAREF
VOAI
-0.3
–
–
VDDP
+0.3
V
V
–
–
P_1.1.17
P_1.1.23
Input voltage
OP1, OP2
-7
7
Temperatures
Junction temperature
Storage temperature
ESD Susceptibility
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_1.1.18
P_1.1.19
Tstg
ESD susceptibility
all pins
VESD1
VESD2
-2
-4
–
–
2
4
kV
kV
HBM 11)
HBM 12)
P_1.1.20
P_1.1.21
ESD susceptibility
pins MON, VS, VSD,
VBAT_SENSE vs.GND
ESD susceptibility
pins LIN vs. GND_LIN
VESD3
-6
–
–
–
6
kV
V
HBM 11)
P_1.1.22
P_1.1.28
P_1.1.43
13)
ESD susceptibility CDM
all pins vs. GND
VESD_CDM1
VESD_CDM2
-500
-750
500
750
13)
ESD susceptibility CDM
pins 1, 12, 13, 24, 25, 36, 37, 48
(corner pins) vs. GND
V
1) Not subject to production test, specified by design.
2) Conditions and min. value is derived from application condition for reverse polarity event.
Data Sheet
80
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
3) Min voltage -28V with external 3.9kΩ series resistor only.
4) Min voltage -28V with external 3.9kΩ series resistor only.
5) Min voltage -2.8V with external 1kΩ series resistor only.
6) To achieve max. ratings on this pin, Parameter P_1.1.44 has to be taken into account resulting in the following dependency:
VGH < VSH + VGHvsSH and additionally VSH < VGH + 0.3V.
7) To achieve max. ratings on this pin, Parameter P_1.1.45 has to be taken into account resulting in the following dependency:
VGL < VSL + VGLvsSL and additionally VSL < VGL + 0.3V.
8) These limits can be kept if max current drawn out of pin does not exceed limit of 200 µA.
9) Includes TMS and RESET.
10) Maximum rating for injection current of GPIO with VIN respected.
11) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001 (1.5kΩ, 100pF)
12) MON with external circuitry of a series resistor of 3.9kΩ and 10nF (at connector); VS with an external ceramic capacitor of
100nF; VSD with an external capacitor of 470nF; VDH with external circuitry of a series resistor of 1kΩ and 3.3nF (at pin).
13) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JESD22-C101F
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
81
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.1.2
Functional Range
Table 18
Functional Range
Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
Typ.
Max.
28
Supply voltage in Active Mode
VS_AM
5.5
–
–
V
V
–
P_1.2.1
Extended supply voltage in Active
Mode
VS_AM_exte 28
40
1) Functionalwith P_1.2.16
parameter
nd
deviation
Supply voltage in Active Mode for
MOSFET Driver Supply
VSD_AM
5.4
–
–
28
32
V
V
P_1.2.18
Extended supply voltage in Active
Mode for MOSFET Driver Supply
VSD_AM_ext 28
1)Functional with P_1.2.17
parameter
end
deviation
Specified supply voltage for LIN
Transceiver
VS_AM_LIN 5.5
VS_AM_LIN 4.8
–
–
18
28
V
V
Parameter
Specification
P_1.2.2
Extended supply voltage for LIN
Transceiver
Functional with P_1.2.14
parameter
deviation
2)
Supply voltage in Active Mode with
reduced functionality (Microcontroller /
Flash with full operation)
VS_AMmin 3.0
–
5.5
V
P_1.2.3
Supply voltage in Sleep Mode
VS_Sleep
3.0
-1
–
–
–
–
–
28
1
V
–
3)
P_1.2.4
P_1.2.5
P_1.2.7
P_1.2.15
P_1.2.9
Supply voltage transients slew rate
dVS/dt
V/µs
mA
MHz
°C
Output sum current for all GPIO pins IGPIO,sum
-50
5
50
24
150
–
4)
Operating frequency
Junction temperature
fsys
Tj
-40
–
1) This operation voltage range is only allowed for a short duration: tmax ≤ 400 ms, fsys = 24 MHz, IVDDP = 10 mA, IVDDEXT = 5 mA.
2) Reduced functionality (e.g. cranking pulse) - Parameter deviation possible.
3) Not subject to production test, specified by design.
4) Function not specified when limits are exceeded.
Data Sheet
82
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.1.3
Current Consumption
Table 19
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Current Consumption @VS pin
Current consumption in IVs
Active Mode at pin VS
–
30
35
mA
f
sys = 20 MHz
P_1.3.1
P_1.3.8
no loads on pins, LIN in recessive
state1)
Current consumption in IVSD
Active Mode at pin VSD
–
–
–
–
40
30
mA 20 kHz
PWM on Bridge Driver
sys = 5 MHz; LIN communication P_1.3.6
Current consumption in ISDM
mA
f
Slow Down Mode
running; charge pump on (reverse
polarity FET on), external Low
Side FET static on (motor break
mode); VDDEXT on; all other
module set to power down;VS =
13.5V
Current consumption in ISleep
Sleep Mode
–
–
–
30
90
–
35
µA
System in Sleep Mode,
microcontrollernotpowered, Wake
capable via LIN and MON; MON
connected to VS or GND;
GPIOs open (no loads) or
connected to GND:
P_1.3.3
P_1.3.15
P_1.3.9
TJ = -40°C to 85°C;
VS = 5.5 V to 18V;2)
Current consumption in ISleep_exten
200
µA
System in Sleep Mode,
microcontrollernotpowered, Wake
capable via LIN and MON; MON
connected to VS or GND;
GPIOs open (no loads) or
connected to GND:
Sleep Mode extended
d
range
TJ = -40°C to 150°C;
VS = 5.5 V to 18V;2)
Current consumption in ISleep
Sleep Mode
33
µA
System in Sleep Mode,
microcontrollernotpowered, Wake
capable via LIN and MON; MON
connected to VS or GND;
GPIOs open (no loads) or
connected to GND:
TJ = -40°C to 40°C;
VS = 5.5 V to 18V;2)
Data Sheet
83
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 19
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Current consumption in ICyclic
Sleep Mode with cyclic
wake
–
–
110
µA
TJ = -40°C to 85°C;
VS = 5.5 V to 18V;
P_1.3.4
t
t
Cyclic_ON = 4ms;
Cyclic_OFF = 2048 ms;2)
Current consumption in IStop
–
100
150
µA
System in Stop Mode,
P_1.3.10
Stop Mode
microcontroller not clocked, Wake
capable via LIN and MON; MON
connected to VS or GND;
GPIOs open (no loads) or
connected to GND; TJ = -
40°C to 85°C;
VS = 5.5V to 18V
1) Current on VS, ADC1/2 active, timer running, LIN active (recessive).
2) Incl. leakage currents form VBAT_SENSE, VDH, VSD and MON
Note:Within the functional range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
84
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.1.4
Thermal Resistance
Table 20
Thermal Resistance
Parameter
Symbol
Values
Typ.
6
Unit Note /
Test Condition
Number
Min.
Max.
Junction to Soldering Point
Junction to Ambient
RthJSP
RthJA
–
–
K/W
1) measured to
P_1.4.1
P_1.4.2
Exposed Pad
2)
–
33
–
K/W
1) Not subject to production test, specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board. Board: 76.2x114.3x1.5mm³ with 2 inner
copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and
300mm2 cooling area on the bottom layer (70µm).
29.1.5
Timing Characteristics
The transition times between the system modes are specified here. Generally the timings are defined from the
time when the corresponding bits in register PMCON0 are set until the sequence is terminated.
Table 21
System Timing1)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min. Typ.
Unit Note / Test Condition
Number
Max.
Wake-up over battery
Wake-up over battery
tstart
–
–
3
ms
ms
Battery ramp-up time to code P_1.5.6
execution
tstartSW
–
–
–
–
1.5
1.5
330
Battery ramp-up time to till
MCU reset is released; VS > 3
V and RESET = 1
P_1.5.1
P_1.5.2
P_1.5.3
Sleep-Exit
tsleep - exit
–
–
ms
µs
Rising/falling edge of any
wake-up signal (LIN, MON) till
MCU reset is released;
2)
Sleep-Entry
tsleep -
entry
1) Not subject to production test, specified by design.
2) Wake events during Sleep-Entry are stored and lead to wake-up after Sleep Mode is reached.
Data Sheet
85
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.2
Power Management Unit (PMU)
This chapter includes all electrical characteristics of the Power Management Unit
29.2.1
PMU I/O Supply (VDDP) Parameters
This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the pad-
supply VDDP and the transition times between the system modes are specified here.
Table 22
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
1)
Specified output current
Specified output current
IVDDP
0
–
–
–
50
30
2.2
mA
P_2.1.1
P_2.1.22
P_2.1.2
1)2)
IVDDP
0
mA
Required decoupling
capacitance
CVDDP1
0.47
µF
µF
V
3)4) ESR < 1Ω; the
specified capacitor value
is a typical value.
3)4) The specified
capacitor value is a
typical value.
Required buffer capacitance for CVDDP2
stability (load jumps)
1
–
2.2
5.1
5.1
5.5
400
P_2.1.20
Output voltage including line
and load regulation @ Active
Mode
VDDPOUT 4.9
5.0
5.0
5.0
50
5) Iload < 90mA; VS > 5.5V P_2.1.3
Output voltage including line
and load regulation @ Active
Mode
VDDPOUT 4.9
V
2)5) Iload < 70mA; VS >
5.5V
P_2.1.23
P_2.1.21
P_2.1.4
Output voltage including line
and load regulation @ Stop
Mode
VDDPOUTS 4.5
V
5) Iload is only internal;
VS > 5.5V
TOP
Output drop @ Active Mode
VSVDDPout
–
mV
I
VDDP = 30mA6);
3.5V < VS < 5.0V
2 ... 90mA; C = 570nF
VS = 5.5 ... 28V
Load regulation @ Active Mode VVDDPLOR -50
Line regulation @ Active Mode VVDDPLIR -50
–
–
–
50
50
5.4
mV
mV
V
P_2.1.5
P_2.1.6
Overvoltage detection
VDDPOV
5.14
VS > 5.5V; Overvoltage P_2.1.7
leads to SUPPLY_NMI
3)7)
Overvoltage detection filter time tFILT_VDDP
–
735
–
–
µs
V
P_2.1.24
OV
3)
Voltage OK detection
VDDPOK
–
3
P_2.1.25
3)
Voltage stable detection range8) ∆VDDPSTB - 220
–
+ 220 mV
P_2.1.26
Undervoltage reset
VDDPUV
IVDDPOC
2.5
91
2.6
–
2.7
V
–
–
P_2.1.8
P_2.1.9
Overcurrent diagnostic
220
mA
Data Sheet
86
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 22
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
3)7)
Overcurrent diagnostic filter
time
tFILT_VDDP
–
27
–
µs
P_2.1.27
P_2.1.28
OC
3)7)9)
Overcurrent diagnostic
shutdown time
tFILT_VDDP
–
290
–
µs
OC_SD
1) Specified output current for port supply and additional other external loads already excluding VDDC current.
2) This use case applies to cases where output current on VDDEXT is max. 40 mA.
3) Not subject to production test, specified by design.
4) Ceramic capacitor.
5) Load current includes internal supply.
6) Output drop for IVDDP without internal supply current.
7) This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK
8) The absolute voltage value is the sum of parameters VDDP + VDDPSTB
9) After tFILT_VDDCOC_SD is passed and the overcurrent condition is still present the device will enter sleep mode.
.
.
Data Sheet
87
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.2.2
PMU Core Supply (VDDC) Parameters
This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the core-
supply VDDC and the transition times between the system modes are specified here.
Table 23
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min. Typ.
Unit Note /
Test Condition
Number
Max.
Required decoupling capacitance CVDDC1
0.1
–
1
µF
1)2) ESR < 1Ω; the
specified capacitor
value is a typical
value.
P_2.2.1
Required buffer capacitance for
stability (load jumps)
CVDDC2
0.33
–
1
µF
V
2)the specified
capacitor value is a
typical value.
P_2.2.17
P_2.2.2
Output voltage including line
regulation @ Active Mode/Stop
Mode
VDDCOUT 1.44 1.5
1.56
Iload < 40mA
Load Regulation @ Active Mode
Line regulation @ Active Mode
Overvoltage detection
VDDCLOR -50
VDDCLIR -25
VDDCOV
–
–
50
mV
mV
V
2 ... 40mA; C =430nF P_2.2.3
DDP = 2.5 ... 5.5V P_2.2.4
25
V
1.59 1.62
1.68
Overvoltage leads to P_2.2.5
SUPPLY_NMI
1)3)
Overvoltage detection filter time
tFILT_VDDC
–
735
–
µs
P_2.2.18
OV
1)
Voltage OK detection range4)
Voltage stable detection range5)
Undervoltage reset
∆VDDCOK - 280
∆VDDCSTB - 110
–
–
+ 280 mV
+ 110 mV
P_2.2.19
1)
P_2.2.20
VDDVUV
1.136 1.20
1.264
100
–
V
–
P_2.2.6
P_2.2.7
P_2.2.21
Overcurrent diagnostic
IVDDCOC 45
–
mA
µs
–
1)3)
Overcurrent diagnostic filter time tFILT_VDDC
–
–
27
OC
1)3)6)
Overcurrent diagnostic shutdown tFILT_VDDC
290
–
µs
P_2.2.22
time
OC_SD
1) Not subject to production test, specified by design.
2) Ceramic capacitor.
3) This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK
4) The absolute voltage value is the sum of parameters VDDC + VDDCSTB
5) The absolute voltage value is the sum of parameters VDDC + VDDCOK
6) After tFILT_VDDCOC_SD is passed and the overcurrent condition is still present the device will enter sleep mode.
.
.
.
Data Sheet
88
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.2.3
VDDEXT Voltage Regulator (5.0V) Parameters
Table 24
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note /
Test Condition
Number
Min.
0
Typ. Max.
Specified output current
Specified output current
IVDDEXT
IVDDEXT
–
–
–
20
40
2.2
mA
mA
µF
–
1)
P_2.3.1
0
P_2.3.21
P_2.3.22
Required decoupling capacitance CVDDEXT1
0.1
3) 2)ESR < 1 Ω; the
specified capacitor
value is a typical
value.
Required buffer capacitance for
stability (load jumps)
CVDDEXT2
1
–
2.2
µF
3)2)the specified
capacitor value is a
typical value.
P_2.3.20
Output voltage including line and VDDEXT
load regulation
4.9
4.8
5.0
5.0
50
–
5.1
5.2
V
V
3) Iload<20mA; VS >
5.5V
P_2.3.3
P_2.3.23
P_2.3.4
P_2.3.14
Output voltage including line and VDDEXT
load regulation
Iload<40mA; VS >
5.5V
3) Iload < 20mA;
3V < VS < 5.0V
Output drop @ Active Mode
Output drop @ Active Mode
VS-VDDEXT
VS-VDDEXT
+300 mV
+400 mV
I
load < 40mA;
3V < VS < 5.0V
2 ... 40mA; C =200nF P_2.3.5
VS = 5.5 ... 28V P_2.3.6
Load regulation @ Active Mode
Line regulation @ Active Mode
VDDEXTLOR -50
VVDDEXTLIR -50
–
–
–
50
50
–
mV
mV
dB
Power supply ripple rejection @ PSSRVDDEXT 50
3) VS = 13.5V; f =0 ... P_2.3.7
Active Mode
1KHz; Vr=2Vpp
Overvoltage detection
VVDDEXTOV 5.18
–
5.4
–
V
VS > 5.5V
3)4)
P_2.3.8
Overvoltage detection filter time tFILT_VDDEXT
–
735
µs
P_2.3.24
OV
3)
3)
Voltage OK detection range
Voltage stable detection range5) ∆VVDDEXTST - 220
VVDDEXTOK
–
3
–
–
V
P_2.3.25
P_2.3.26
+ 220 mV
B
6)
Undervoltage trigger
VVDDEXTUV 2.6
IVDDEXTOC 50
2.8
–
3.0
160
–
V
P_2.3.9
Overcurrent diagnostic
mA
µs
µs
–
3)4)
P_2.3.10
P_2.3.27
P_2.3.28
Overcurrent diagnostic filter time tFILT_VDDCOC
Overcurrent diagnostic shutdown tFILT_VDDCOC
–
–
27
290
3)4)
–
time
_SD
1) This use case requires the reduced utilization of VDDP output current by 20 mA, see P_2.1.22.
2) Ceramic capacitor.
3) Not subject to production test, specified by design.
4) This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK
.
Data Sheet
89
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
5) The absolute voltage value is the sum of parameters VDDEXT + VDDEXTSTB
.
6) When the condition is met, the Bit VDDEXT_CTRL.bit.SHORT will be set.
Data Sheet
90
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.2.4
VPRE Voltage Regulator (PMU Subblock) Parameters
The PMU VPRE Regulator acts as a supply of VDDP and VDDEXT voltage regulators.
Table 25
Functional Range
Parameter
Symbol
Values
Unit Note / Test Condition Number
Min.
Typ. Max.
1)
Specified output current
IVPRE
–
–
110
mA
P_2.4.1
1) Not subject to production test, specified by design.
29.2.4.1 Load Sharing Scenarios of VPRE Regulator
The figure below shows the possible load sharing scenarios of VPRE regulator.
VS
VPRE
max. 110 mA
VDDEXT - 5V
1: max. 20 mA
2: max. 40 mA
VDDP - 5V
1: max. 90 mA
2: max. 70 mA
VDDEXT
VDDP
VDDC
CVDDEXT
CVDDP
GND (Pin 39)
GND (Pin 39)
VDDC - 1.5V
max. 40 mA
CVDDC
GND (Pin 39)
Load Sharing VPRE – Scenarios 1 & 2
Load_Sharing_VPRE.vsd
Figure 32 Load Sharing Scenarios of VPRE Regulator
29.2.5
Power Down Voltage Regulator (PMU Subblock) Parameters
The PMU Power Down voltage regulator consists of two subblocks:
•
•
Power Down Pre regulator: VDD5VPD
Power Down Core regulator: VDD1V5_PD (Supply used for GPUDATAxy registers)
Both regulators are used as purely internal supplies. The following table contains all relevant parameters:
Data Sheet
91
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 26
Functional Range
Parameter
Symbol
Values
Unit Note / Test Condition Number
Min.
Typ. Max.
VDD1V5_PD
1)
Power-On Reset Threshold
VDD1V5_PD_ 1.2
–
1.5
V
P_2.5.1
RSTTH
1) Not subject to production test, specified by design
Data Sheet
92
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.3
System Clocks
29.3.1
Oscillators and PLL Parameters
Table 27
Electrical Characteristics System Clocks
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Number
Min.
PMU Oscillators (Power Management Unit)
Max.
Frequency of LP_CLK fLP_CLK
14
18
22
MHz This clock is used at startup P_3.1.1
and can be used in case the
PLL fails
Frequency of LP_CLK2 fLP_CLK2
70
100
130
kHz This clock is used for cyclic P_3.1.2
wake
CGU Oscillator (Clock Generation Unit Microcontroller)
Short term frequency
deviation1)
fTRIMST
-0.4
–
+0.4
%
2)3) Within any 10 ms, e.g.
after synchronization to a
LIN frame (PLL settings
untouched within 10 ms)
P_3.1.3
Absolute accuracy
fTRIMABSA -1.5
tOSC
–
–
+1.5
10
%
Including temperature and P_3.1.4
lifetime deviation
CGU-OSC Start-up
time
–
µs
3) Startup time OSC from
Sleep Mode, power supply
stable
P_3.1.5
PLL (Clock Generation Unit Microcontroller) 3)
VCO frequency range fVCO-0
Mode 0
48
–
112
160
MHz VCOSEL =”0”
MHz VCOSEL =”1”
P_3.1.6
P_3.1.7
VCO frequency range fVCO-1
96
–
Mode 1
Input frequency range fOSC
XTAL1 input freq. range fOSC
4
4
–
–
16
16
80
38
MHz
MHz
MHz
–
–
–
P_3.1.8
P_3.1.9
P_3.1.10
P_3.1.11
Output freq. range
fPLL
0.04687 –
Free-running frequency fVCOfree_0
Mode 0
–
–
–
–
MHz VCOSEL =”0”
Free-running frequency fVCOfree_1
Mode 1
–
76
–
MHz VCOSEL =”1”
P_3.1.12
P_3.1.13
Input clock high/low
time
thigh/low
10
ns
–
Peak period jitter
Accumulated jitter
Lock-in time
tjp
-500
–
–
–
500
5
ps
ns
µs
4) for K=1
4) for K=1
–
P_3.1.14
P_3.1.15
P_3.1.16
jacc
tL
–
–
200
Data Sheet
93
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
1) The typical oscillator frequency is 5 MHz
2) VDDC = 1.5 V, Tj = 25°C
3) Not subject to production test, specified by design.
4) This parameter is valid for PLL operation with an external clock source and thus reflects the real PLL performance.
29.4
Flash Memory
This chapter includes the parameters for the 128 kByte embedded flash module.
29.4.1
Flash Parameters
Table 28
Flash Characteristics1)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Number
Test Condition
Min.
–
Typ. Max.
Programming time per 128 byte page tPR
32)
42)
–
3.5
4.5
–
ms
3V < VS < 28V P_4.1.1
3V < VS < 28V P_4.1.2
Erase time per sector/page
Data retention time
tER
–
ms
tRET
20
years
1,000 erase /
P_4.1.3
program cycles
Data retention time
tRET
50
–
–
years
1,000 erase /
program cycles
Tj = 30°C3)
P_4.1.9
Flash erase endurance for user sectors NER
30
10
32
–
–
–
–
–
–
kcycles Data retention P_4.1.4
time 5 years
cycles 4)Data retention P_4.1.5
Flash erase endurance for security
pages
NSEC
NDD
time 20 years
5)
Drain disturb limit
kcycles
P_4.1.6
1) Not subject for production test, specified by design.
2) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system
clock cycles. The requirement is only relevant for extremely low system frequencies.
3) Derived by extrapolation of lifetime tests.
4) Temperature: 25 °C
5) This parameter limits the number of subsequent programming operations within a physical sector without a given page in
this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly. For normal
sector erase/program cycles this limit will not be violated. For data sectors the integrated EEPROM emulation firmware
routines handle this limit automatically, for wordline erases in code sectors (without EEPROM emulation) it is
recommended to execute a software based refresh, which may make use of the integrated random number generator
NVMBRNG to statistically start a refresh.
Data Sheet
94
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.5
Parallel Ports (GPIO)
29.5.1
Description of Keep and Force Current
VDDP
keeper
current
PU Device
PUDSEL
P1.x
P0.x
\PUDSEL
keeper
current
PD Device
VSS
Pull-Up-Down.vsd
Figure 33 Pull-Up/Down Device
UGPIO
Logical "1"
Undefined
Logical "0"
7.5 kOhm (equivalent)
(1.5V / 200uA)
VIH - VDDP
VIL - VDDP
2.33 kOhm (equivalent)
(3.5V / 1.5mA)
I
-IPLF
-IPLK
Current_Diag.vsd
Figure 34 Pull-Up Keep and Forced Current
Data Sheet
95
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
UGPIO
Logical "1"
Undefined
Logical "0"
2.33 kOhm (equivalent)
(3.5V / 1.5mA)
VIH
VIL
7.5 kOhm (equivalent)
(1.5V / 200uA)
I
IPLK
IPLF
Current_Diag-Pull_down.vsd
Figure 35 Pull-Down Keep and Force Current
29.5.2
DC Parameters of Port 0, Port 1, TMS and Reset
Note:Operating Conditions apply.
Keeping signal levels within the limits specified in this table ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the maximum allowed ocurrent
which can be taken out of VDDP.
Table 29
Port Output Driver Mode
Current Limits for Port Output Drivers1)
Maximum Output Current
(IOLmax , - IOHmax)
DDP ≥ 4.5V
Maximum Output Current
(IOLnom , - IOHnom)
Number
V
2.6V < VDDP < VDDP ≥ 4.5V 2.6V < VDDP <
4.5V
4.5V
Strong driver2)
Medium driver3)
Weak driver3)
5 mA
3 mA
1.6 mA
1.0 mA
0.25 mA
1.0 mA
0.8 mA
0.15 mA
P_5.1.15
P_5.1.1
P_5.1.2
3 mA
1.8 mA
0.3 mA
0.5 mA
1) Not subject to production test, specified by design.
2) Not available for port pins P0.4, P1.0, P1.1 and P1.2
3) All P0.x and P1.x
Table 30
DC Characteristics Port0, Port1
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Number
Min.
HYSP0_P1 0.11 x VDDP
Max.
Input hysteresis
–
V
1) Series
P_5.1.5
resistance = 0 Ω;
4.5V ≤ VDDP
≤
5.5V
Input hysteresis
Data Sheet
HYSP0_P1
–
0.09 x
VDDP
–
V
1) Series
resistance = 0 Ω;
2.6V ≤ VDDP
4.5V
P_5.1.16
_exend
≤
96
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 30
DC Characteristics Port0, Port1 (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Number
Min.
Max.
Input low voltage
Input low voltage
Input high voltage
Input high voltage
VIL
-0.3
0.3 x VDDP
V
2)4.5V ≤ VDDP
≤
≤
≤
≤
P_5.1.3
P_5.1.17
P_5.1.4
P_5.1.18
5.5V
VIL_extend -0.3
0.42 x
VDDP
–
V
1)2.6V ≤ VDDP
4.5V
VIH
0.7 x VDDP
–
V
DDP + 0.3 V
2)4.5V ≤ VDDP
5.5V
VIH_extend
–
0.52 x VDDP + 0.3 V
1)2.6V ≤ VDDP
VDDP
4.5V
Output low voltage
Output low voltage
Output high voltage
Output high voltage
Input leakage current
VOL
VOL
VOH
VOH
IOZ2
–
–
–
–
–
–
1.0
0.4
–
V
V
V
V
3) 4) IOL ≤ IOLmax P_5.1.6
3) 5) IOL ≤ IOLnom P_5.1.7
3) 4) IOH ≥ IOHmax P_5.1.8
3) 5) IOH ≥ IOHnom P_5.1.9
–
V
V
DDP - 1.0
DDP - 0.4
–
-5
+5
µA 6) TJ ≤ 85°C,
0.45 V < VIN
< VDDP
P_5.1.10
Input leakage current
IOZ2
-15
–
+15
µA TJ ≤ 150°C,
0.45 V < VIN
< VDDP
P_5.1.11
Pull level keep current
Pull level force current
IPLK
IPLF
CIO
-200
-1.5
–
–
–
–
+200
+1.5
10
µA 7) VPIN ≥ VIH (up) P_5.1.12
PIN ≤ VIL (dn)
mA 7) VPIN ≤ VIL (up) P_5.1.13
V
VPIN ≥ VIH (dn)
1)
Pin capacitance
pF
µs
P_5.1.14
P_5.1.19
Reset Pin Timing
1)
Reset Pin Input Filter Time Tfilt_RESET
–
5
–
1) Not subject to production test, specified by design.
2) Tested at VDDP = 5V, specified for 4.5V < VDDP < 5.5V.
3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for pin
groups must be respected.
4) Tested at 4.9V < VDDP < 5.1V, IOL = 4mA, IOH = -4mA, specified for 4.5V < VDDP < 5.5V.
5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→GND, VOH→VDDP).
Tested at 4.9V < VDDP < 5.1V, IOL = 1mA, IOH = -1mA.
6) The given values are worst-case values. In production tests, this leakage current is only tested at 150°C; other values are
ensured by correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [°C]):
I
OZ = 0.05 × e(1.5 + 0.028×TJ) [µA]. For example, at a temperature of 95°C the resulting leakage current is 3.2 µA.
Leakage derating depending on voltage level (DV = VDDP - VPIN [V]):
OZ = IOZtempmax - (1.6 × DV) [µA]
This voltage derating formula is an approximation which applies for maximum temperature.
I
Data Sheet
97
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled
pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down.
These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose
IO pins.
29.5.3
DC Parameters of Port 2
These parameters apply to the IO voltage range, 4.5 V ≤ VDDP ≤ 5.5 V.
Note:Operating Conditions apply.
Keeping signal levels within the limits specified in this table ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV
.
Table 31 DC Characteristics Port 2
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note /
Test Condition
Number
Min.
Max.
Input low voltage
Input low voltage
Input high voltage
Input high voltage
Input hysteresis
VIL
-0.3
0.3 x VDDP
V
1)4.5V ≤ VDDP
5.5V
2)2.6V ≤ VDDP
4.5V
1)4.5V ≤ VDDP
5.5V
2)2.6V ≤ VDDP
≤
≤
≤
≤
P_5.2.1
P_5.2.10
P_5.2.2
P_5.2.11
P_5.2.3
VIL_extend -0.3
0.42 x
VDDP
–
V
VIH
0.7 x VDDP
–
V
DDP + 0.3 V
VIH_extend
HYSP2
–
0.52 x VDDP + 0.3 V
VDDP
4.5V
0.11 x VDDP
–
–
V
2)Series
resistance = 0 Ω;
4.5V ≤ VDDP
≤
5.5V
Input hysteresis
HYSP2_ext
–
0.09 x
–
V
2)Series
P_5.2.12
VDDP
resistance = 0 Ω;
2.6V ≤ VDDP <
4.5V
end
Input leakage current
Pull level keep current
Pull level force current
IOZ1
IPLK
IPLF
CIO
-400
-30
-750
–
–
–
–
–
+400
+30
+750
10
nA TJ ≤ 85°C,
0 V < VIN < VDDP
µA 3) VPIN ≥ VIH (up) P_5.2.5
PIN ≤ VIL (dn)
µA 3) VPIN ≤ VIL (up) P_5.2.6
P_5.2.4
V
VPIN ≥ VIH (dn)
2)
Pin capacitance
pF
P_5.2.7
(digital inputs/outputs)
1) Tested at VDDP = 5V, specified for 4.5V < VDDP < 5.5V.
2) Not subject to production test, specified by design.
3) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled
pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down.
Data Sheet
98
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.6
LIN Transceiver
29.6.1
Electrical Characteristics
Table 32
Electrical Characteristics LIN Transceiver
Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition Number
Min.
Max.
Bus Receiver Interface
Receiver threshold voltage, Vth_dom 0.4 ×VS 0.45 ×VS 0.53 x VS
V
SAE J2602
P_6.1.1
recessive to dominant edge
Receiver dominant state
VBUSdom -27
–
0.4 ×VS
V
V
LIN Spec 2.2 (Par. 17) P_6.1.2
SAE J2602 P_6.1.3
Receiver threshold voltage, Vth_rec
0.47 x 0.55 ×VS 0.6 ×VS
dominant to recessive edge
VS
Receiver recessive state
Receiver center voltage
VBUSrec 0.6 ×VS
–
1.15 ×VS
V
V
1) LIN Spec 2.2 (Par. 18) P_6.1.4
2) LIN Spec 2.2 (Par. 19) P_6.1.5
VBUS_CN 0.475
0.5 ×VS 0.525
× VS
× VS
T
Receiver hysteresis
VHYS
0.07 VS 0.12 ×VS 0.175
× VS
V
3) LIN Spec 2.2 (Par. 20) P_6.1.6
Wake-up threshold voltage VBUS,wk 0.4 ×VS 0.5 ×VS 0.6 ×VS
V
–
P_6.1.7
P_6.1.8
Dominant time for bus wake- tWK,bus
up (internal analog filter
delay)
3
–
15
µs
The overall dominant
time for bus wake-up is
a sum of tWK,bus
+
adjustable digital filter
time. The digital filter
time can be adjusted by
PMU.CNF_WAKE_FIL
TER.CNF_LIN_FT;
Bus Transmitter Interface
Bus recessive output
voltage
VBUS,ro 0.8 ×VS
–
VS
V
V
TxD = high Level
P_6.1.9
Bus short circuit current
IBUS,sc
40
100
150
mA Current Limitation for
driver dominant state
driver on
P_6.1.10
V
BUS = 18 V; LIN Spec
2.2 (Par. 12)
Bus short circuit filter time
tBUS,sc
–
1
–
µs
The overall bus short
circuit filter time is a sum
of tBUS,sc + digital filter
time. The digital filter
time is 4 µs (typ.)
P_6.1.71
Data Sheet
99
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 32
Electrical Characteristics LIN Transceiver (cont’d)
Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition Number
Min.
Max.
Leakage current (loss of
ground)
IBUS_NO_ -1000
-450
1000
µA VS = 12 V; 0 < VBUS
<
P_6.1.11
18 V; LIN Spec 2.2 (Par.
15)
GND
Leakage current
Leakage current
Leakage current
Bus pull-up resistance
IBUS_NO_
–
10
–
20
–
µA VS = 0 V; VBUS = 18 V; P_6.1.12
LIN Spec 2.2 (Par. 16)
BAT
IBUS_PAS -1
mA VS = 18 V; VBUS = 0 V; P_6.1.13
LIN Spec 2.2 (Par. 13)
_dom
IBUS_PAS
–
–
20
47
µA VS = 8 V; VBUS = 18 V; P_6.1.14
LIN Spec 2.2 (Par. 14)
_rec
RBUS
20
30
kΩ Normal mode LIN Spec P_6.1.15
2.2 (Par. 26)
AC Characteristics - Transceiver Normal Slope Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
td(H),R
tsym,R
tduty1
0.1
–
–
–
–
6
6
2
–
µs
µs
µs
LIN Spec 2.2
(Param. 31)
P_6.1.16
P_6.1.17
P_6.1.18
P_6.1.19
Propagation delay
bus recessive to RxD HIGH
0.1
LIN Spec 2.2
(Param. 31)
Receiver delay symmetry
-2
tsym,R = td(L),R - td(H),R;
LIN Spec 2.2 (Par. 32)
4) duty cycle 1
THRec(max) =
0.744 ×VS;
Duty cycle D1
Normal Slope Mode
(for worst case at 20 kbit/s)
0.396
THDom(max) =
0.581 ×VS; VS = 5.5 …
18 V;
tbit = 50 µs;
D1 = tbus_rec(min)/2 tbit;
LIN Spec 2.2 (Par. 27)
Duty cycle D2
tduty2
–
–
0.581
4) duty cycle 2
P_6.1.20
Normal Slope Mode
(for worst case at 20 kbit/s)
THRec(min) = 0.422 ×VS;
THDom(min) =
0.284 ×VS;
VS = 5.5 … 18 V;
tbit = 50 µs;
D2 = tbus_rec(max)/2 tbit;
LIN Spec 2.2 (Par. 28)
AC Characteristics - Transceiver Low Slope Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
–
6
6
µs
µs
LIN Spec 2.2
(Param. 31)
P_6.1.21
P_6.1.22
Propagation delay
bus recessive to RxD HIGH
td(H),R
0.1
–
LIN Spec 2.2
(Param. 31)
Data Sheet
100
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 32
Electrical Characteristics LIN Transceiver (cont’d)
Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition Number
Min.
Max.
Receiver delay symmetry
tsym,R
tduty1
-2
–
2
µs
t
sym,R = td(L),R - td(H),R
;
P_6.1.23
P_6.1.24
LIN Spec 2.2 (Par. 32)
Duty cycle D3
(for worst case at
10,4 kbit/s)
0.417
–
–
4) duty cycle 3
THRec(max) =
0.778 ×VS;
THDom(max) =
0.616 ×VS; VS = 5.5 …
18 V;
tbit = 96 µs;
D3 = tbus_rec(min)/2 tbit;
LIN Spec 2.2 (Par. 29)
Duty cycle D4
(for worst case at
10,4 kbit/s)
tduty2
–
–
0.590
4) duty cycle 4
THRec(min) = 0.389 ×VS;
THDom(min) =
P_6.1.25
0.251 ×VS;
VS = 5.5 … 18 V;
tbit = 96 µs;
D4 = tbus_rec(max)/2 tbit;
LIN Spec 2.2 (Par. 30)
AC Characteristics - Transceiver Fast Slope Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
td(H),R
tsym,R
0.1
0.1
-1.5
–
–
–
6
µs
µs
µs
–
–
P_6.1.26
P_6.1.27
P_6.1.28
Propagation delay
bus recessive to RxD HIGH
6
Receiver delay symmetry
1.5
t
sym,R = td(L),R - td(H),R
;
AC Characteristics - Flash Mode
Propagation delay
bus dominant to RxD LOW
td(L),R
td(H),R
tsym,R
0.1
0.1
-1.0
–
–
–
6
µs
µs
µs
–
–
P_6.1.31
P_6.1.32
P_6.1.33
Propagation delay
bus recessive to RxD HIGH
6
Receiver delay symmetry
1.5
tsym,R = td(L),R - td(H),R
;
Data Sheet
101
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 32
Electrical Characteristics LIN Transceiver (cont’d)
Vs = 5.5V to 18V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition Number
Min.
Max.
Duty cycle D7 (for worst
case at 115 kbit/s)
for +1 µs Receiver delay
symmetry
tduty1
0.399
–
–
5) duty cycle D7
THRec(max) =
0.744 ×VS;
P_6.1.34
THDom(max) =
0.581 ×VS; VS = 13.5 V;
tbit = 8.7 µs;
D7 = tbus_rec(min)/2 tbit;
Duty cycle D8 (for worst
case at 115 kbit/s)
for +1 µs Receiver delay
symmetry
tduty2
–
–
0.578
5) duty cycle 8
THRec(min) = 0.422 ×VS;
THDom(min) =
0.284 ×VS;VS = 13.5 V;
tbit = 8.7 µs;
P_6.1.35
D8 = tbus_rec(max)/2 tbit;
6)
LIN input capacity
CLIN_IN
ttimeout
–
6
15
12
30
20
pF
P_6.1.69
P_6.1.36
TxD dominant time out
ms
V
TxD = 0 V
Thermal Shutdown (Junction Temperature)
6)
6)
Thermal shutdown temp.
Thermal shutdown hyst.
TjSD
160
–
180
10
200
–
°C
K
P_6.1.65
P_6.1.66
∆T
1) Maximum limit specified by design.
2) VBUS_CNT = (Vth_dom +Vth rec)/2
3) VHYS = VBUSrec - VBUSdom
4) Bus load concerning LIN Spec 2.2:
Load 1 = 1 nF / 1 kΩ = CBUS / RBUS
Load 2 = 6.8 nF / 660 Ω = CBUS / RBUS
Load 3 = 10 nF / 500 Ω = CBUS / RBUS
5) Bus load
Load 1 = 1 nF / 500 Ω = CBUS / RBUS
6) Not subject to production test, specified by design.
Data Sheet
102
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.7
High-Speed Synchronous Serial Interface
SSC Timing Parameters
29.7.1
The table below provides the SSC timing in the TLE9869QXA20.
Table 33 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Number
Test Condition
Min.
Typ.
Max.
SCLK clock period
t0
t1
t2
t3
1) 2 * TSSC
–
–
–
–
–
–
–
–
2) VDDP > 2.7 V P_7.1.1
2) VDDP > 2.7 V P_7.1.2
2) VDDP > 2.7 V P_7.1.3
2) VDDP > 2.7 V P_7.1.4
MTSR delay from SCLK
MRST setup to SCLK
MRST hold from SCLK
10
10
15
ns
ns
ns
1) TSSCmin = TCPU = 1/fCPU. If fCPU = 20 MHz, t0 = 100 ns. TCPU is the CPU clock period.
2) Not subject to production test, specified by design.
t0
SCLK1)
t1
t1
1)
MTSR
t2
t3
Data
valid
MRST1)
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 36 SSC Master Mode Timing
Data Sheet
103
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.8
Measurement Unit
29.8.1
System Voltage Measurement Parameters
Table 34
Supply Voltage Signal Conditioning
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min. Typ.
Unit Note / Test Condition
Number
Max.
Measurement output
voltage range @ VAREF5
VA5
0
–
5
V
V
–
–
P_8.1.15
P_8.1.16
Measurement output
voltage range @
VAREF1V2
VA1V2
0
–
1.23
Battery / Supply Voltage Measurement VBAT_SENSE / VS
Input to output voltage
attenuation:
VS
ATTVS_1
–
–
3
0.055
0.055
–
–
SFR setting 1
SFR setting 1
P_8.1.41
P_8.1.60
P_8.1.1
Input to output voltage
attenuation:
VBAT_SENSE
ATTVBAT_SENSE
–
_1
Nominal operating input
voltage rangeVBAT_SENSE
and VS
VBAT_SENSE
,range1 , VS,range1
22
V
1)SFR setting 1;
Max. value corresponds
to typ. ADC full scale
input; 3V < VBAT_SENSE/ VS
< 28V
Accuracy of VBAT_SENSE/ VS ΔVBAT_SENSE
-220
–
220 mV SFR setting 1, VS = 5.5 V P_8.1.70
after calibration
,range1 , VS,range1
to 18V,
Tj = -40..85°C
Input to output voltage
attenuation:
VS
ATTVS_2
–
–
3
0.039
0.039
–
–
SFR setting 2
SFR setting 2
P_8.1.42
P_8.1.61
P_8.1.40
Input to output voltage
attenuation:
VBAT_SENSE
ATTVBAT_SENSE
–
_2
Nominal operating input
VBAT_SENSE
31
V
1)SFR setting 2;
voltage range VBAT_SENSE ,range2 ,VS,range2
and VS
Max. value corresponds
to typ. ADC full scale input
3V < VBAT_SENSE/ VS <
28V
Data Sheet
104
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 34
Supply Voltage Signal Conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min. Typ.
Unit Note / Test Condition
Number
Max.
Accuracy of VBAT_SENSE
VS after calibration
/
ΔVBAT_SENSE
,range2 , VS,range2
-370
–
370 mV SFR setting 2, VS = 5.5V P_8.1.44
to 18V,
Tj = -40..85°C
Measurement input
leakage current for
VBAT_SENSE
Ileak_VBAT_SENSE
0
–
4.0
µA PD_N=0 (off-state),
P_8.1.72
P_8.1.21
V
BAT_SENSE = 13.5V
, measure
Driver Supply Voltage Measurement VSD
Input to output voltage
attenuation:
VSD
ATTVSD
–
0.039
–
–
1)
Nominal operating input
voltage range VSD
VSD,range
2.5
–
–
31
V
P_8.1.2
Accuracy of VSD sense
after calibration
∆VSD
-440
440 mV VS = 5.5V to 18V,
Tj = -40..85°C
P_8.1.47
Charge Pump Voltage Measurement VCP
Input to output voltage
attenuation:
VCP
ATTVCP
–
0.023
–
–
P_8.1.56
1)
Nominal operating input
voltage range VCP
VCP,range
2.5
–
–
52
V
P_8.1.7
Accuracy of VCP sense
after calibration
∆VCP
-747
747 mV VS = 5.5V to 18V,
Tj = -40..85°C
P_8.1.62
Monitoring Input Voltage Measurement VMON
Input to output voltage
attenuation:
ATTVMON
–
0.039
–
–
P_8.1.49
VMON
1)
Nominal operating input
voltage range VMON
VMON,range
2.5
–
–
31
V
P_8.1.8
Accuracy of VMON sense
after calibration
∆VMON
-440
440 mV VS = 5.5V to 18V,
Tj = -40..85°C
P_8.1.68
Pad Supply Voltage Measurement VVDDP
Input-to-output voltage
attenuation:
VDDP
ATTVDDP
–
0
0.164
–
–
–
P_8.1.33
P_8.1.50
1)
Nominal operating input
VDDP,range
7.50
V
voltage range VDDP
Data Sheet
105
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 34
Supply Voltage Signal Conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min. Typ.
-105
Unit Note / Test Condition
Number
Max.
Accuracy of VDDP sense
after calibration
∆VDDP_SENSE
–
105 mV 2)VS = 5.5 to 18V,
Tj = -40..85°C
P_8.1.5
10-Bit ADC Reference Voltage Measurement VAREF
Input to output voltage
attenuation:
ATTVAREF
–
0.219
–
–
P_8.1.22
VAREF
1)
Nominal operating input
voltage range VAREF
VAREF,range
0
–
–
5.62
79
V
P_8.1.51
P_8.1.48
Accuracy of VAREF sense ∆VAREF
after calibration
-79
mV VS = 5.5V to 18V,
Tj = -40..85°C
8-Bit ADC Reference Voltage Measurement VBG
Input-to-output voltage
attenuation:
VBG
ATTVBG
–
0.75
–
–
P_8.1.57
P_8.1.52
1)
Nominal operating input
VBG,range
0.8
–
1.64
V
voltage range VBG
Core supply Voltage Measurement VDDC
Input-to-output voltage
attenuation:
ATTVDDC
–
0.75
–
–
P_8.1.34
VDDC
1)
Nominal operating input
voltage range VDDC
VDDC,range
0.8
-22
–
–
1.64
22
V
P_8.1.53
P_8.1.6
Accuracy of VDDC sense
after calibration
∆VDDC_SENSE
mV VS = 5.5 to 18V,
Tj = -40..85°C
VDH Input Voltage Measurement VVDH10BITADC
VDH Input to output
voltage attenuation:
ATTVDH_1
ATTVDH_2
VVDH,range1
–
–
–
0.1666 –
667
SFR setting 1
SFR setting 2
SFR setting 1
P_8.1.64
P_8.1.65
P_8.1.66
VDH Input to output
voltage attenuation:
0.2260 –
0
Nominal operating input
–
30
voltage range VVDH, Range
1
Nominal operating input
VVDH,range2
–
–
20
SFR setting 2
P_8.1.67
voltage range VVDH, Range
2
V
VDH 10-bit ADC, Range 1 ∆VVDHADC10B
VDH 10-bit ADC, Range 2 ∆VVDHADC10B
-300
-200
–
–
300 mV VS= 5.5 to 18V,
Tj = -40..85°C
P_8.1.39
P_8.1.71
V
200 mV VS= 5.5V to 18V,
Tj = -40..85°C
Data Sheet
106
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 34
Supply Voltage Signal Conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ.
Max.
470 kΩ PD_N=1 (on-state)
10-Bit ADC measurement Rin_VDH,measure 200
390
P_8.1.3
input resistance for VDH
Measurement input
leakage current for VVDH
Ileak_VDH, measure
0
–
2.0
µA PD_N=0 (off-state),
MON = 13.5V
P_8.1.10
V
1) Not subject to production test, specified by design.
2) Accuracy is valid for a calibrated device.
Data Sheet
107
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.8.2
Central Temperature Sensor Parameters
Table 35
Electrical Characteristics Temperature Sensor Module
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition Number
Min.
Max.
1)
Output voltage VTEMP at
T0=273 K (0°C)
a
–
0.666
–
V
P_8.2.2
T0=273 K (0°C)
1)
Temperature sensitivity b
Accuracy_1
b
–
2.31
–
mV/K
°C
P_8.2.4
Acc_1
Acc_2
Acc_3
-10
-10
-5
–
–
–
10
10
5
2)1) -40°C < Tj < 85°C
2)1) 125°C < Tj < 150°C P_8.2.6
2)1) 85°C < Tj < 125°C
P_8.2.7
P_8.2.5
Accuracy_2
°C
Accuracy_3
°C
1) Not subject to production test, specified by design
2) Accuracy with reference to on-chip temperature calibration measurement, valid for Mode1
29.8.3
ADC2
29.8.3.1 ADC2 Specifications
Table 36
DC Specifications
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
8
Unit
Note /
Test Condition
Number
Min.
–
Max.
–
Resolution
RES
Bits
Full
P_8.3.18
P_8.3.19
P_8.3.20
P_8.3.21
Guaranteed offset error
Gain error
–
–
–
-2.0
-2.0
-0.8
±0.3
±0.5
±0
2.0
2.0
0.8
LSB
not calibrated
not calibrated
Full
%FSR
LSB
Differential non-linearity
(DNL)
Integral non-linearity (INL) –
Input referred noise
-1.2
–
±0
1.2
1.5
LSB
–
P_8.3.22
P_8.3.23
–
0.5
LSBrms 1)@ TJ = 27°C
1) Not subject to production test, specified by design.
Data Sheet
108
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.9
ADC1 - VAREF
29.9.1
Electrical Characteristics VAREF
Table 37
Electrical Characteristics VAREF
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Required buffer
capacitance
CVAREF
0.1
–
1
µF
ESR < 1Ω
VS > 5.5V
P_9.1.1
Reference output voltage VAREF
4.95
5
–
5.05
–
V
P_9.1.2
P_9.1.3
1)
DC supply voltage
rejection
DCPSRVAREF 30
dB
–
1)
Supply voltage ripple
rejection
ACPSRVAREF 26
–
–
dB
µs
VS = 13.5V; f = 0 ... 1KHz; P_9.1.4
Vr = 2Vpp
Turn ON time
tso
–
–
–
200
–
1) Cext = 100nF
PD_N to 99.9% of final value
1)input impedance in case of P_9.1.20
VAREF is applied from
external
P_9.1.5
Input resistance at VAREF RIN,VAREF
Pin
100
kΩ
1) Not subject to production test, specified by design.
Data Sheet
109
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.9.2
Electrical Characteristics ADC1 (10-Bit)
These parameters describe the conditions for optimum ADC performance.
Note:Operating Conditions apply.
Table 38
A/D Converter Characteristics
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Number
Min.
Max.
1)
Analog reference supply VAREF
Analog reference ground VAGND
VAGND
+ 1.0
–
–
–
–
VDDPA
+ 0.05
V
P_9.2.1
P_9.2.2
P_9.2.3
VSS
- 0.05
1.5
V
–
2)
Analog input voltage
range
VAIN
VAGND
VAREF
24
V
3)
4)
Analog clock frequency fADCI
5
MHz
P_9.2.4
P_9.2.5
Conversion time for 10- tC10
bit result
(13 + STC) (13 + STC (13 + STC –
× tADCI ) × tADCI ) × tADCI
+ 2 x tSYS + 2 x tSYS + 2 x tSYS
Conversion time for 8-bit tC8
result
(11 + STC) (11 + STC (11 + STC –
–
P_9.2.6
P_9.2.7
P_9.2.8
× tADCI
) × tADCI
) × tADCI
+ 2 × tSYS + 2 × tSYS + 2 × tSYS
1)
Wakeup time from
analog powerdown, fast
mode
tWAF
–
–
–
–
4
µs
µs
5)
Wakeup time from
analog powerdown, slow
mode
tWAS
15
Total unadjusted error (8 TUE8B
bit)
–
–
±1
±6
±2
counts 6)7)VAREF = 5.0 V P_9.2.9
counts 7)8)VAREF = 5.0 V P_9.2.22
Total unadjusted error
(10 bit)
TUE10B
±12
DNL error
EADNL
–
–
±0.8
±0.8
±3
±5
counts –
counts –
P_9.2.10
P_9.2.11
INL error with internal 5V EAINL_int_V
reference VAREF
AREF
Gain error with internal
5V reference VAREF
EAGAIN_int_
–
±0.4
±10
counts –
counts –
P_9.2.12
VAREF
Offset error
EAOFF
–
–
±0.5
–
±2
10
P_9.2.13
P_9.2.14
5)9)
Total capacitance
of an analog input
CAINT
CAINS
RAIN
pF
pF
kΩ
5)9)
5)9)
Switched capacitance
of an analog input
–
–
–
–
4
2
P_9.2.15
P_9.2.16
Resistance of
the analog input path
Data Sheet
110
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 38
A/D Converter Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Number
Min.
Max.
5)9)
5)9)
5)9)
Total capacitance
of the reference input
CAREFT
CAREFS
RAREF
–
–
–
–
15
pF
pF
kΩ
P_9.2.17
P_9.2.18
P_9.2.19
Switched capacitance
of the reference input
–
–
7
2
Resistance of
the reference input path
1) Not subject to production test, specified by design.
2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion result in these cases will
be 0000H or 03FFH, respectively.
3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting.
4) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine the
digital result and the time to load the result register with the conversion result.
5) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate of not more than 500 µs.
6) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual
errors.
All error specifications are based on measurement methods standardized by IEEE 1241.2000.
7) The specified TUE is valid only if the absolute sum of input overload currents (see IOV specification) does not exceed
10 mA, and if VAREF and VAGND remain stable during the measurement time.
8) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual
errors.
All error specifications are based on measurement methods standardized by IEEE 1241.2000.
9) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply
voltage) typical values can be used for calculation. At room temperature and nominal supply voltage the following typical
values can be used:
CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kꢀ, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kꢀ.
29.10
Reserved
Data Sheet
111
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.11
High-Voltage Monitoring Input
29.11.1 Electrical Characteristics
Table 39
Electrical Characteristics Monitoring Input
Tj = -40 °C to +150 °C; VS = 5.5 V to 28 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Number
Min.
Max.
MON Input Pin characteristics
Wake-up/monitoring
threshold voltage
VMONth
0.4*VS 0.5*VS 0.6*VS
V
Without external serial
resistor Rs (with Rs:DV =
P_11.1.1
I
PD/PU * Rs); VS = 5.5V to
18V;
TJ = -40°C to 85°C
Wake-up/monitoring
threshold voltage
extended range
VMONth_ext 0.44*VS 0.53*V 0.64*VS
V
V
Without external serial
resistor Rs (with Rs:DV =
P_11.1.11
P_11.1.12
end
S
I
PD/PU * Rs)
Threshold hysteresis
VMONth,hys 0.015* 0.05*
VS VS
0.1*VS
In all modes; without
external serial resistor Rs
(with Rs:dV = IPD/PU * Rs);
VS = 5.5V to 18V;
Threshold hysteresis
VMONth,hys 0.02*VS 0.06*
0.12*VS
V
In all modes; without
external serial resistor Rs
(with Rs:dV = IPD/PU * Rs);
VS = 18V to 28V;
P_11.1.2
VS
Pull-up current
Pull-down current
Input leakage current
Timing
IPU, MON -20
-10
10
–
-1
µA
µA
µA
0.6*VS
P_11.1.3
P_11.1.4
P_11.1.5
IPD, MON
ILK,MON
3
20
2.5
0.4*VS
1) 0 V < VMON_IN < 28 V
-2.5
Wake-up filter time
(internal analog filter
delay)
tFT,MON
–
500
–
ns
2) The overall filter time for P_11.1.6
MON wake-up is a sum of
t
FT,MON + adjustable digital
filter time. The digital filter
time can be adjusted by
PMU.CNF_WAKE_FILTE
R.CNF_MON_FT;
1) Input leakage is valid for disabled state.
2) With pull-up, pull down current disabled.
Data Sheet
112
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.12
MOSFET Driver
29.12.1 Electrical Characteristics
Table 40
Electrical Characteristics MOSFET Driver
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
MOSFET Driver Output
Source current - Charge
current (low gate voltage)
ISoumax
200
250 420
250 420
mA
mA
V
I
SD > 8 V, CLoad = 10 nF, P_12.1.44
SOU = CLoad * slew rate, ( =
(20%-50%) / tSLEW),
CHARGE = IDISCHG
31(max)
SD > 8 V, CLoad = 10 nF, P_12.1.45
SOU = CLoad * slew rate, ( =
(50%-20%) / tSLEW),
CHARGE = IDISCHG
31(max)
I
=
Sink current - Discharge
current
ISinkmax
200
V
I
I
=
High level output voltage
Gxx vs. Sxx
VGxx1
VGxx2
VGxx3
VGxx6
VGxx7
trise3_3nf
10
8
–
14
–
V
V
V
V
V
ns
V
V
SD > 8V1), CLoad = 10 nF P_12.1.3
High level output voltage
GHx vs. SHx
–
SD = 6.4 V1)2), CLoad = 10 P_12.1.4
nF
High level output voltage
GHx vs. SHx
7
–
–
V
nF
SD = 5.4 V1), CLoad = 10
P_12.1.5
High level output voltage
GLx vs. GND
8
–
–
V
SD = 6.4 V1)2), CLoad = 10 P_12.1.6
nF
High level output voltage
GLx vs. GND
7
–
–
V
nF
SD = 5.4 V1), CLoad = 10
P_12.1.7
Rise time
Fall time
Rise time
–
200
–
2)CLoad = 3.3 nF,
V
25-75%, ICHARGE = IDISCHG
= 31(max)
2)CLoad = 3.3 nF,
V
75-25%, ICHARGE = IDISCHG
= 31(max)
P_12.1.8
SD > 8 V,
tfall3_3nf
–
200
–
ns
ns
P_12.1.9
SD > 8 V,
trisemax
100
250 450
C
Load = 10 nF,
P_12.1.57
V
SD > 8 V,
25-75%, ICHARGE = IDISCHG
= 31(max)
Data Sheet
113
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 40
Electrical Characteristics MOSFET Driver (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Fall time
tfallmax
100
250 450
ns
µs
µs
ns
ns
C
Load = 10 nF,
P_12.1.58
V
SD > 8 V,
75-25%, ICHARGE = IDISCHG
= 31(max)
2)CLoad = 10 nF,
Rise time
Fall time
trisemin
1.25 2.5
1.25 2.5
5
P_12.1.14
P_12.1.15
P_12.1.35
P_12.1.36
P_12.1.11
V
SD > 8 V,
25-75%,
CHARGE = IDISCHG = 3(min)
2)CLoad = 10 nF,
SD > 8 V,
75-25%,
CHARGE = IDISCHG = 3(min)
Load = 10 nF,
SD > 8 V,
I
tfallmin
5
V
I
Absolute rise - fall time
difference for all LSx
tr_f(diff)LSx
–
–
–
–
100
100
C
V
25-75%, ICHARGE = IDISCHG
= 31(max)
Absolute rise - fall time
difference for all HSx
tr_f(diff)HSx
CLoad = 10 nF,
V
SD > 8 V,
25-75%, ICHARGE = IDISCHG
= 31(max)
2)
Resistor between GHx/GLx RGGND
and GND
30
30
40
40
50
50
kꢀ
kꢀ
–
Resistor between SHx and
GND
RSHGN
2)3) This resistance is the P_12.1.10
resistance between GHx
and GND connected
through a diode to SHx. As
a consequence, the
voltage at SHx can rise up
to 0,6V typ. before it is
discharged through the
resistor.
Low RDSON mode
(boosted discharge mode)
RONCCP
–
9
12
ꢀ
V
V
VSD = 13.5 V,
VCP = VVSD + 14.0 V;
P_12.1.50
I
CHARGE = IDISCHG =
31(max); 50mA forced into
Gx, Sx grounded
2)
Resistance between VDH
and VSD
IBSH
–
–
4
–
3
kꢀ
P_12.1.24
P_12.1.37
Input propagation time (LS
on)
tP(ILN)min
1.5
µs
C = 10 nF, (25%) /
tSLEWon
2)4)
Data Sheet
114
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 40
Electrical Characteristics MOSFET Driver (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Input propagation time (LS
off)
tP(ILF)min
tP(IHN)min
tP(IHF)min
tP(ILN)max
tP(ILF)max
tP(IHN)max
tP(IHF)max
tPon(diff)LSx
–
–
–
–
–
–
–
–
1.5
1.5
1.5
3
3
3
µs
µs
µs
ns
ns
ns
ns
ns
C = 10 nF, (75%) /
tSLEWoff
P_12.1.38
P_12.1.39
P_12.1.40
P_12.1.26
P_12.1.27
P_12.1.28
P_12.1.29
P_12.1.30
2)4)
Input propagation time (HS
on)
C = 10 nF, (25%) /
2)4)
tSLEWon
Input propagation time (HS
off)
C = 10 nF, (75%) /
2)4)
tSLEWoff
Input propagation time (LS
on)
200 350
200 300
200 350
200 300
C = 10 nF, (25%) /
5)
tSLEWon
Input propagation time (LS
off)
C = 10 nF, (75%) /
5)
tSLEWoff
Input propagation time (HS
on)
C = 10 nF, (25%) /
5)
tSLEWon
Input propagation time (HS
off)
C = 10 nF, (75%) /
5)
tSLEWoff
Absolute input propagation
time difference between
propagation times for all LSx
(LSx on)
–
–
–
–
100
100
100
100
C = 10 nF, (25%) /
5)
tSLEWon
Absolute input propagation
time difference between
propagation times for all LSx
(LSx off)
tPoff(diff)LSx
tPon(diff)HSx
tPoff(diff)HSx
–
–
–
ns
ns
ns
C = 10 nF, (75%) /
P_12.1.41
P_12.1.42
P_12.1.43
5)
tSLEWoff
Absolute input propagation
time difference between
propagation times for all HSx
(HSx on)
C = 10 nF, (25%) /
5)
tSLEWon
Absolute input propagation
time difference between
propagation times for all HSx
(HSx off)
C = 10 nF, (75%) /
5)
tSLEWoff
Drain source monitoring
Drain source monitoring
threshold
VDSMONVTH
–
–
–
V
DRV_CTRL3.DSMONVT P_12.1.46
H<2:0>
000
001
010
011
100
101
0.25
0.50
0.75
1.00
1.25
1.5
1.75
2.00
110
111
Data Sheet
115
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 40
Electrical Characteristics MOSFET Driver (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
Open load diagnosis currents
Pull-up diagnosis current
Pull-down diagnosis current IPDDiag
Charge pump
IPUDiag
-220 -370 -520 µA
I
I
DISCHG = 1; VSHx = 5.0 V
DISCHG = 1; VSHx = 5.0 V
P_12.1.47
P_12.1.48
650
900 1100 µA
Output voltage
VCP vs. VSD
VCPmin1
8.5
12
80
–
–
V
V
VSD = 5.4V, ICP=5 mA,
P_12.1.53
P_12.1.49
P_12.1.59
Bridge Driver enabled
Regulated output voltage
VCP vs. VSD
VCP
14
88
16
120
V
8 V < VVSD < 28,
ICP=10mA, @250kHz fCP
Turn ON Time
tON_VCP
us
8 V < VVSD < 28,
(25%)2)6)
,
C
CP1, CCP2 = 220 nF,
CP = 250kHz
8 V < VVSD < 28,
(25-75%)2)7)
CP1, CCP2 = 220 nF,
CP = 250kHz
f
Rise time
trise_VCP
60
72
88
us
P_12.1.60
,
C
f
1) Specification for H-Bridge Drive, 6 MOSFET switching with 25 KHz. Test condition: IGx = - 100 µA, ICHARGE =
IDISCHARGE = 31(max), IDISCHARGEDIV2_N = 1 and ICHARGEDIV2_N = 1.
2) Not subject to production test.
3) This resistance is connected through a diode between SHx and GHx to ground.
4) ICHARGE = IDISCHARGE = 3(min).
5) ICHARGE = IDISCHARGE = 31(max).
6) This time applies when Bit DRV_CP_CTRL_STS.bit.CP_EN is set
7) This time applies when Bit DRV_CP_CLK_CTRL.bit.CPCLK_EN is set
Data Sheet
116
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
29.13
Operational Amplifier
29.13.1 Electrical Characteristics
Table 41
Electrical Characteristics Operational Amplifier
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note / Test Condition
Number
Min.
Max.
Differential gain
(uncalibrated)
G
Gain settings GAIN<1:0>: P_13.1.6
9.5
19
38
57
10
20
40
60
10.5
21
42
00
01
10
11
63
Differential input operating VIX
voltage range OP2 - OP1
-1.5 / G –
1.5 / G
2.0
V
V
G is the Gain specified
below
P_13.1.1
Operating. common mode VCM
inputvoltage range (referred
to GND (OP2 - GND) or
(OP1 - GND)
-2.0
-7.0
–
–
Input common mode has P_13.1.2
to be checked in
evaluation if it fits the
required range
Max. input voltage range
(referred to GND (OP_2 -
GND) or (OP1 - GND)
VIX
7.0
V
Max. rating of operational P_13.1.3
amplifier inputs, where
measurement is not done
Single ended output voltage VOUT
range (linear range)
VZERO
- 1.5
–
–
VZERO
+ 1.5
V
1)2) Offset output voltage 2 P_13.1.4
V ± 1.5V
Linearity error
Linearity error
Gain drift
EPWM
-15
15
1.0
1
mV
Maximum deviation from P_13.1.5
best fit straight line
divided by max. value of
differential output voltage
range (0.5V - 3.5V); this
parameter is determined
at G = 10.
EPWM_% -1.0
–
–
%
%
Maximum deviation from P_13.1.24
best fit straight line
divided by max. value of
differential output voltage
range (0.5V - 3.5V); this
parameter is determined
at G = 10.
-1
Gain drift after calibration P_13.1.7
at G = 10.
Data Sheet
117
Rev. 1.0, 2015-04-30
TLE9869QXA20
Electrical Characteristics
Table 41
Electrical Characteristics Operational Amplifier (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
80
Unit Note / Test Condition
Number
Min.
Max.
DC input voltage common
mode rejection ratio
DC-
CMRR
58
–
dB
ns
CMRR (in dB)=-20*log
(differential mode gain/
common mode gain)
P_13.1.8
V
V
CMI= -2V... 2V,
AIP-VAIN=0V
Settling time to 98%
TSET
–
1
800
1400
1.5
Derived from 80 - 20 %
rise fall times for ± 2V
overload condition (3 Tau
value of settling time
constant)2)
P_13.1.9
2)
Current Sense Amplifier
Input Resistance @ OP1,
OP2
Rin_OP1_
1.25
kꢀ
–
P_13.1.25
OP2
1) Typical VZERO = 0,4 * VAREF.
2) This parameter is not subject to production test.
Data Sheet
118
Rev. 1.0, 2015-04-30
TLE9869QXA20
Package Outlines
30
Package Outlines
0ꢀ9 MAXꢀ
(0ꢀ65)
11 x 0ꢀ5 = 5ꢀ5
0ꢀ5
0ꢀ1
7
A
0ꢀ03
6ꢀ8
0ꢀ1
+0ꢀ031)
2)
37
B
36
25
24
48x
0ꢀ08
48
13
1
12
Index Marking
48x
0ꢀ1
0ꢀ4 x 45°
0ꢀ05
Index Marking
0ꢀ23
(0ꢀ35)
M
A B C
(0ꢀ2)
0ꢀ05 MAXꢀ
(5ꢀ2)
(6)
C
1) Vertical burr 0ꢀ03 maxꢀ, all sides
2) These four metal areas have exposed diepad potential
PG-VQFN-48-29, -31-PO V05
Figure 37 Package outline VQFN-48-31 (with LTI)
Notes
1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/products.
2. Dimensions in mm.
Data Sheet
119
Rev. 1.0, 2015-04-30
TLE9869QXA20
Revision History
31
Revision History
Revision History
Page or Item
Rev. 1.0, 2015-04-30
all
Subjects (major changes since previous revision)
Initial Release.
Data Sheet
120
Rev. 1.0, 2015-04-30
Edition 2015-04-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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