TLE9872QTW40 [INFINEON]
The TLE9872QTW40 is part of the MOTIX™ TLE987x product family. The TLE9872QTW40 is a single chip;
| 型号： | TLE9872QTW40 |
| 厂家： | 
Infineon |
| 描述： | The TLE9872QTW40 is part of the MOTIX™ TLE987x product family. The TLE9872QTW40 is a single chip |
| 文件： | 总129页 (文件大小：3388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLE9872QTW40
Microcontroller with LIN and BLDC MOSFET Driver for Automotive
Applications
A-Step
Extended operating temperature range (grade 0)
Features
•
•
•
•
•
•
•
•
•
32-bit Arm®* Cortex®-M3 core
256 KB flash
8 KB RAM
On-chip OSC and PLL for clock generation
MOSFET driver including charge pump
1 LIN 2.2 transceiver
High-speed operational amplifier for motor current sensing via shunt
Single power supply from 5.5 V to 27 V
Temperature range Tj = -40°C to +175°C
Potential applications
•
•
•
•
•
•
Wiper
Aux. pumps
Fans
Window lift
Sunroof
Tailgate
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
Type
Package
Marking
TLE9872QTW40
TQFP-48-10
*
Arm and Cortex are registered trademarks of Arm Limited, UK
Datasheet
www.infineon.com
Rev. 1.0
2020-07-23
1
TLE9872QTW40
Table of contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.2
Device pinout and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PMU modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power supply generation unit (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage regulator 5.0 V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage regulator 1.5 V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
External voltage regulator 5.0 V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
6.1
6.2
6.2.1
6.3
System control unit – digital modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Low-precision clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3.1
7
System control unit – power modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
7.2
7.2.1
8
Arm® Cortex®-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1
8.2
8.2.1
9
9.1
9.2
9.2.1
9.3
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DMA mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3.1
10
Address space organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Memory control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
NVM module (flash memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1
11.2
11.2.1
11.3
Datasheet
2
Rev. 1.0
2020-07-23
TLE9872QTW40
12
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1
12.2
12.2.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13
13.1
13.2
Watchdog timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14
14.1
14.2
GPIO ports and peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port 0 and port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TLE9872QTW40 port module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port 1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Port 2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14.2.1
14.2.2
14.3
14.3.1
14.3.1.1
14.3.2
14.3.2.1
14.3.3
14.3.3.1
15
15.1
General-purpose timer units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Features of block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Features of block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Block diagram of GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Block diagram of GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
15.1.1
15.1.2
15.2
15.2.1
15.2.2
16
Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timer2 and Timer21 mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
16.1
16.2
16.2.1
17
Timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Timer3 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17.1
17.2
17.3
17.3.1
18
Capture/compare unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Feature set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
18.1
18.2
18.2.1
19
UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
UART modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
19.1
19.2
19.2.1
19.3
20
LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Datasheet
3
Rev. 1.0
2020-07-23
TLE9872QTW40
20.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
20.2
20.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
21
High-speed synchronous serial interface (SSC1/SSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
21.1
21.2
21.2.1
22
22.1
22.2
22.2.1
22.2.1.1
Measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
BEMF comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
23
Core measurement module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Core measurement module mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
23.1
23.2
23.2.1
23.2.2
24
10-bit analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
24.1
24.2
24.2.1
25
High-voltage monitor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
25.1
25.2
25.2.1
26
Bridge driver (incl. charge pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
26.1
26.2
26.2.1
26.2.2
27
Current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
27.1
27.2
27.2.1
28
28.1
28.2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
BLDC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ESD immunity according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
29
29.1
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
29.1.1
29.1.2
29.1.3
29.1.4
29.1.5
Datasheet
4
Rev. 1.0
2020-07-23
TLE9872QTW40
29.2
Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
29.2.1
29.2.2
29.2.3
29.2.4
29.2.4.1
29.2.5
29.3
29.3.1
29.3.2
29.4
29.4.1
29.5
29.5.1
29.5.2
29.5.3
29.6
PMU I/O supply (VDDP) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PMU core supply (VDDC) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VDDEXT voltage regulator (5.0 V) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
VPRE voltage regulator (PMU subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Load-sharing scenario for the VPRE regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Power-down voltage regulator (PMU subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
System clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Parameters of oscillators and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
External clock parameters XTAL1, XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Parallel ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Description of the keep and force currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DC parameters of port 0, port 1, TMS, and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DC parameters of port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
High-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SSC timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
System voltage measurement parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Central temperature sensor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ADC2 VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC2 reference voltage VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC1 reference voltage - VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Electrical characteristics of VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Electrical characteristics of the ADC1 (10-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
High-voltage monitoring input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MOSFET driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
29.6.1
29.7
29.7.1
29.8
29.8.1
29.8.2
29.8.3
29.8.3.1
29.8.3.2
29.9
29.9.1
29.9.2
29.10
29.11
29.11.1
29.12
29.12.1
29.13
29.13.1
30
31
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Datasheet
5
Rev. 1.0
2020-07-23
TLE9872QTW40
Overview
1
Overview
Summary of Features
•
32-bit Arm® Cortex®-M3 core
–
–
Up to 40 MHz clock frequency
One clock per machine cycle architecture
•
On-chip memory
–
–
–
–
–
256 KB flash including
4 KB EEPROM (emulated in flash)
512 byte 100-time programmable memory (100TP)
8 KB RAM
Boot ROM for startup firmware and flash routines
•
On-chip OSC and PLL for clock generation
PLL loss-of-lock detection
–
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MOSFET driver including charge pump
10 general-purpose I/O Ports (GPIO)
5 analog inputs, 10-bit A/D Converter (ADC1)
16-bit timers - GPT12, Timer2, Timer21, and Timer3
Capture/compare unit for PWM signal generation (CCU6)
2 full-duplex serial interfaces (UART) with LIN support (for UART1 only)
2 synchronous serial channels (SSC)
On-chip debug support via 2-wire SWD
1 LIN 2.2 transceiver
1 high-voltage monitoring input
Single power supply from 5.5 V to 27 V
Extended power supply voltage range from 3 V to 28 V
Low-dropout voltage regulators (LDO)
High-speed operational amplifier for motor current sensing via shunt
5 V voltage supply for external loads (e.g., Hall sensor)
Core logic supply at 1.5 V
Programmable window watchdog (WDT1) with independent on-chip clock source
Power-saving modes
–
–
–
–
MCU slow-down mode
Sleep mode
Stop mode
Cyclic wake-up sleep mode
•
•
•
•
•
Power-on and undervoltage/brownout reset generator
Overtemperature protection
Short-circuit protection
Loss of clock detection with fail-safe mode entry for low system power consumption
Temperature range Tj = -40°C to +175°C
Datasheet
6
Rev. 1.0
2020-07-23
TLE9872QTW40
Overview
•
•
•
Package TQFP-48
Green package (RoHS compliant)
AEC-qualified
Datasheet
7
Rev. 1.0
2020-07-23
TLE9872QTW40
Overview
1.1
Abbreviations
The following acronyms and terms are used within this document. List see in Table 1.
Table 1
Acronyms
AHB
APB
Acronyms
Name
Advanced High-performance Bus
Advanced Peripheral Bus
Capture compare unit 6
Clock generation unit
CCU6
CGU
CMU
CP
Cyclic management unit
Charge pump for MOSFET driver
Current-sense amplifier
Data post-processing
CSA
DPP
ECC
Error correction code
EEPROM
EIM
Electrically erasable programmable read only memory
Exceptional interrupt measurement
Finite state machine
FSM
GPIO
H-Bridge
ICU
General-purpose input/output
Half-bridge
Interrupt control unit
IEN
Interrupt enable
IIR
Infinite impulse response
Load instruction
LDM
LDO
LIN
Low-dropout voltage regulator
Local interconnect network
Least significant bit
LSB
LTI
Lead tip inspection
MCU
MF
Microcontroller unit
Measurement functions
Most significant bit
MSB
MPU
MRST
MTSR
MU
Memory protection unit
Master receive, slave transmit
Master transmit, slave receive
Measurement unit
NMI
Non-maskable interrupt
Nested vector interrupt controller
Non-volatile memory
NVIC
NVM
OTP
OSC
PBA
One-time programmable
Oscillator
Peripheral bridge
Datasheet
8
Rev. 1.0
2020-07-23
TLE9872QTW40
Overview
Table 1
Acronyms
PCU
Acronyms (cont’d)
Name
Power control unit
PD
Pull-down
PGU
Power supply generation unit
Phase-locked loop
PLL
PPB
Private Peripheral Bus
Pull-up
PU
PWM
RAM
Pulse-width modulation
Random-access memory
Reset control unit
RCU
RMU
ROM
SCU-DM
SCU-PM
SFR
Reset management unit
Read-only memory
System control unit – digital modules
System control unit – power modules
Special function register
Short open window (for WDT)
Serial Peripheral Interface
Synchronous serial channel
Store instruction
SOW
SPI
SSC
STM
SWD
TCCR
TMS
Arm® Serial Wire Debug
Temperature compensation control register
Test mode select
TSD
Thermal shut-down
UART
VBG
Universal asynchronous receiver-transmitter
Voltage reference bandgap
Voltage-controlled oscillator
Preregulator
VCO
VPRE
WDT
WDT1
WMU
100TP
Watchdog timer in SCU-DM
Watchdog timer in SCU-PM
Wake-up management unit
100-time programmable
Datasheet
9
Rev. 1.0
2020-07-23
TLE9872QTW40
Block diagram
2
Block diagram
TMS
P0.0
TEST / DEBUG
INTERFACE
Arm®
µDMA
CONTROLLER
FLASH
slave
SRAM
slave
ROM
slave
Cortex®-M3
system bus
slave
Multilayer AHB matrix
slave
PBA0
slave
PBA1
VAREF
GND_REF
MU-VAREF
SCU_DM
PLL
P2.0, P2.2, P2.3, P2.4, P2.5
(AN0, AN2, AN3, AN4, AN5)
ADC 1
DPP1
GPT12
CCU6
XTAL1
XTAL2
UART1
UART2
SSC1
SSC2
T2
P0.1 – P0.4
P1.0 – P1.4
VDH
GH3
SH3
GL3
GH2
SH2
GL2
GH1
SH1
GPIO
LIN
LIN
GND_LIN
MOSFET
driver
MU
MF / ADC2
T21
DPP2
SCU_DM
WDT
OP1
OP2
OP AMP
GL1
SL
VS
SCU_PM
WDT1/
CLKWDT
PMU –
power
control
system
functions
RESET
VDDEXT
VDDP
VDDC
VCP
VSD
CP2H
CP2L
CP1H
CP1L
CP
µ
DMA
controller
MON
MON
T3
Figure 1
Block diagram
Datasheet
10
Rev. 1.0
2020-07-23
TLE9872QTW40
Device pinout and pin configuration
3
Device pinout and pin configuration
3.1
Device pinout
OP1 37
24 P0.3
EP
VDDC 38
23 P0.1
22 RESET
GND 39
VDDP 40
VDDEXT 41
GND_LIN 42
LIN 43
21 P0.0
20 TMS
19 GND
18 P0.4
17 P1. 2
16 P1.1
15 P1.0
TLE 987x
VDH 44
VS 45
SH3 46
VSD 47
14 MON
13 GL1
CP1H 48
Note:
= Low voltage pins
Figure 2
Device pinout
Datasheet
11
Rev. 1.0
2020-07-23
TLE9872QTW40
Device pinout and pin configuration
3.2
Pin configuration
After a reset, all pins are configured as input (except supply and LIN pins) with one of the following settings:
•
•
•
•
Pull-up device enabled only (PU)
Pull-down device enabled only (PD)
Input with both pull-up and pull-down devices disabled (I)
Output with output stage deactivated = high-impedance state (Hi-Z)
The functions and default states of the TLE9872QTW40 external pins are provided in the following table.
Type: indicates the pin type.
•
•
•
•
I/O: Input or output
I: Input only
O: Output only
P: Power supply
Not all alternate functions are listed.
Table 2
Symbol
Pin definitions and functions
Pin
Type Reset Function
number
state1)
P0
Port 0
Port 0 is a 5-bit bidirectional general-purpose I/O port.
Alternate functions can be assigned and are listed in the port
description. The main functions are listed below.
P0.0
P0.1
21
23
I/O
I/O
I/PU
I/PU
SWD
GPIO
Serial wire debug clock
General-purpose I/O
Alternate function mapping see Table 7.
P0.2
25
I/O
I/PD
GPIO
General-purpose I/O
Alternate function mapping see Table 7.
Note:
For a functional SWD connection,
this GPIO must be tied to zero.
P0.3
P0.4
P1
24
18
I/O
I/O
I/PU
I/PD
GPIO
GPIO
Port 1
General-purpose I/O
Alternate function mapping see Table 7.
General-purpose I/O
Alternate function mapping see Table 7.
Port 1 is a 5-bit bidirectional general-purpose I/O port.
Alternate functions can be assigned and are listed in the port
description. The main functions are listed below.
P1.0
P1.1
P1.2
15
16
17
I/O
I/O
I/O
I
I
I
GPIO
GPIO
GPIO
General-purpose I/O
Alternate function mapping see Table 7.
General-purpose I/O
Alternate function mapping see Table 8.
General-purpose I/O
Alternate function mapping see Table 8.
Datasheet
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TLE9872QTW40
Device pinout and pin configuration
Table 2
Symbol
Pin definitions and functions (cont’d)
Pin
Type Reset Function
state1)
number
P1.3
P1.4
P2
26
I/O
I
GPIO
GPIO
Port 2
General-purpose I/O, used for inrush transistor
Alternate function mapping see Table 8.
27
I/O
I
General-purpose I/O
Alternate function mapping see Table 8.
Port 2 is a 5-bit general-purpose input-only port.
Alternate functions can be assigned and are listed in the port
description. The main functions are listed below.
P2.0/XTAL1
P2.2/XTAL2
P2.3
29
30
35
32
31
I/I
I
I
I
I
I
AN0
AN2
AN3
AN4
AN5
ADC analog input 0
Alternate function mapping see Table 9.
I/O
ADC analog input 2
Alternate function mapping see Table 9.
I
I
I
ADC analog input 3
Alternate function mapping see Table 9.
P2.4
ADC analog input 4
Alternate function mapping see Table 9.
P2.5
ADC analog input 5
Alternate function mapping see Table 9.
Power supply
VS
45
40
38
P
P
P
–
–
–
Battery supply input
2)I/O port supply (5.0 V). Connect external buffer capacitor.
3)Core supply (1.5 V in Active mode).
Do not connect external loads, but connect an external buffer
capacitor.
VDDP
VDDC
VDDEXT
GND
41
19
28
39
P
P
P
P
–
–
–
–
External voltage supply output (5.0 V, 20 mA)
GND digital
GND digital
GND analog
GND
GND
Monitor input
MON
14
I
–
High voltage monitor input
LIN interface
LIN
43
42
I/O
P
–
–
LIN bus interface input/output
LIN ground
GND_LIN
Charge pump
CP1H
48
1
P
P
P
P
P
–
–
–
–
–
Charge pump capacity 1 high, connect external C
Charge pump capacity 1 low, connect external C
Charge pump capacity 2 high, connect external C
Charge pump capacity 2 low, connect external C
Charge pump capacity
CP1L
CP2H
3
CP2L
4
VCP
2
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TLE9872QTW40
Device pinout and pin configuration
Table 2
Symbol
Pin definitions and functions (cont’d)
Pin
Type Reset Function
state1)
number
VSD
47
P
–
Battery supply input for charge pump
MOSFET driver
VDH
44
46
6
P
P
P
P
P
P
P
P
P
P
P
–
–
–
–
–
–
–
–
–
–
–
Voltage drain high-side MOSFET driver
Source high-side FET 3
Source high-side FET 2
Gate high-side FET 2
Source high-side FET 1
Gate high-side FET 1
Source low-side FET
SH3
SH2
GH2
7
SH1
8
GH1
9
SL
10
12
13
5
GL2
Gate low-side FET 2
GL1
Gate low-side FET 1
GH3
Gate high-side FET 3
Gate low-side FET 3
GL3
11
Others
GND_REF
VAREF
OP1
33
34
37
36
20
P
–
GND for VAREF
I/O
–
5V ADC1 reference voltage, optional buffer or input
Negative operational amplifier input
Positive operational amplifier input
I
I
–
OP2
–
TMS
I
I/PD
TMS
SWD
Test mode select input
Serial Wire Debug input/output
I/O
RESET
EP
22
–
I/O
–
–
–
Reset input, not available during sleep mode
Exposed pad, connect to GND
1) Only valid for digital IO.
2) Also named VDD5V.
3) Also named VDD1V5.
Datasheet
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Rev. 1.0
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TLE9872QTW40
Modes of operation
4
Modes of operation
The TLE9872QTW40 highly integrated circuit contains analog and digital functional blocks. An embedded 32-
bit microcontroller is available for system and interface control. On-chip, low-dropout regulators are provided
for internal and external power supply. An internal oscillator provides a cost-effective clock that is particularly
well suited for LIN communications. A LIN transceiver is available as a communication interface. Driver stages
for a motor bridge or BLDC motor bridge with external MOSFET are integrated, featuring PWM capability,
protection features, and a charge pump for operation at low supply voltage. A 10-bit SAR ADC implemented
for high-precision sensor measurement. An 8-bit ADC is used for diagnostic measurements.
The Micro controller unit supervision and system protection (including a reset feature) is complemented by a
programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated
temperature sensors are available on-chip.
All relevant modules offer power saving modes in order to support automotive applications connected to
terminal 30. A wake-up from power-save mode is possible via a LIN bus message, via the monitoring input, or
using a programmable time period (cyclic wake-up).
The TLE9872QTW40 has several operation modes mainly to support low power consumption requirements.
Reset mode
The Reset mode is a transition mode used, e.g., during power-up of the device after a power-on reset, or after
wake-up from Sleep mode. In this mode, the on-chip power supplies are enabled and all other modules are
initialized. Once the core supply VDDC is stable, the device enters Active mode. If the watchdog timer WDT1
fails more than four times, the device performs a fail-safe transition to Sleep mode.
Active mode
In Active mode, all modules are activated and the TLE9872QTW40 is fully operational.
Stop mode
Stop mode is one of two major low-power modes. The transition to the low-power modes is performed by
setting the corresponding bits in the mode control register. In Stop mode, the embedded microcontroller is
still powered, allowing for shorter wake-up response times. Wake-up from this mode is possible through LIN
bus activity, by using the high-voltage monitoring pin, or through the corresponding 5 V GPIOs.
Stop mode with cyclic wake-up
The Cyclic Wake-Up mode is a special operating mode of the Stop mode. The transition to the Cyclic Wake-Up
mode is performed by first setting the corresponding bits in the mode control register, followed by the Stop
Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period),
asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Stop mode.
Sleep mode
The Sleep mode is a low-power mode. The transition to the low-power mode is performed by setting the
corresponding bits in the MCU mode control register or in case of failure (see below). In Sleep mode the
embedded microcontroller power supply is deactivated, allowing for the lowest system power consumption.
A wake-up from this mode is possible by LIN bus activity, the High Voltage Monitor Input pin, or through cyclic
wake-up.
Sleep mode in case of failure
Sleep mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). In this case,
MON is enabled as the wake source and cyclic wake-up is activated with 1 s of dead time.
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TLE9872QTW40
Modes of operation
Sleep Mode with cyclic wake-up
The Cyclic Wake-Up mode is a special operating mode of the Sleep mode. The transition to Cyclic Wake-Up
mode is performed by first setting the corresponding bits in the mode control register followed by the Sleep
Mode and Stop Mode commands. In addition to the cyclic wake-up behavior (wake-up after a programmable
time period), asynchronous wake events via the activated sources (LIN and/or MON) are available, as in
normal Sleep mode.
When using Sleep mode with cyclic wake-up, the voltage regulator is switched off and started again with the
wake. A limited number of registers is buffered during sleep, and can be used by software, e.g., for counting
sleep/wake cycles.
MCU Slow Down mode
In MCU Slow Down mode the MCU frequency is reduced to save power during operation. LIN communication
is still possible. LS MOSFET can be activated.
Wake-up source prioritization
All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up
sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless, all wake-up sources are
latched in order to provide all wake-up events to the application software. The software can clear the wake-
up source flags. This is to ensure that no wake-up event is lost.
As the default wake-up source, the MON input is activated after power-on reset only. Additionally, the device
is in Cyclic Wake-Up mode with the configurable dead time setting.
The following table shows the possible power mode configurations including the Stop mode.
Table 3
Power mode configurations
Module/function
Active mode
Stop mode
Sleep mode
Comment
VDDEXT
ON/OFF
ON (no dynamic
load)/OFF
OFF
–
Bridge Driver
LIN TRx
ON/OFF
ON/OFF
OFF
OFF
Wake-up only/OFF Wake-up only/OFF
Brownout detection POR on VS
–
VS sense
ON/OFF
Brownoutdetection
performed in PCU
Brownout detection
GPIO 5V (wake-up) n.a.
Disabled/static
OFF
OFF
OFF
–
–
–
GPIO 5V (active)
WDT1
ON
ON
n.a.
ON
OFF
CYCLIC WAKE
Cyclic wake-up/
cyclic sense/OFF
Cyclic wake-up/OFF –
Measurement
MCU
ON1)
OFF
OFF
–
ON/slow-down/STOP STOP2)
OFF
–
CLOCK GEN (MC)
LP_CLK (18 MHz)
ON
ON
OFF
OFF
–
OFF
OFF
WDT1
LP_CLK2 (100 kHz) ON/OFF
ON/OFF
ON/OFF
For cyclic wake-up
1) May not be switched off due to safety reasons.
2) MC PLL clock disabled, MC supply reduced to VDDCOUT_Stop_Red
.
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TLE9872QTW40
Modes of operation
Wake-up levels and transitions
The wake-up can be triggered by rising, falling, or both signal edges for the monitor input, GPIOs, by LIN, or by
cyclic wake-up.
Datasheet
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TLE9872QTW40
Power management unit (PMU)
5
Power management unit (PMU)
5.1
Features
•
•
•
•
•
•
System mode control (startup, sleep, stop and active)
Power management (cyclic wake-up)
Control of system voltage regulators with diagnosis (overload, short, overvoltage)
Fail-safe mode detection and operation in case of system errors (watchdog fail)
Wake-up sources configuration and management (LIN, MON, GPIOs)
System error logging
5.2
Introduction
The power management unit is responsible for generating all required voltage supplies for the embedded
MCU (VDDC, VDDP) and the external supply (VDDEXT). The power management unit is designed to ensure fail-
safe behavior of the system IC by controlling all system modes, including the corresponding transitions.
Additionally, the PMU provides well-defined sequences for the system mode transitions and generates
hierarchical reset priorities. The reset priorities control the reset behavior of all system functions, especially
the reset behavior of the embedded MCU. All these functions are controlled by a state machine. The system
master function of the PMU uses an independent logic supply and system clock. For this reason, the PMU has
an "Internal logic supply and system clock" module which works independently of the MCU clock.
Datasheet
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TLE9872QTW40
Power management unit (PMU)
5.2.1
Block diagram
The following figure shows the structure of the power management unit. Table 4 describes the submodules in
more detail.
VS
Power-down supply
VDDP
VDDC
Power supply generation unit
(PGU)
I
N
T
E
R
N
A
L
e.g. for WDT1
LP_CLK
Peripherals
LDO for external supply
VDDEXT
VDDEXT
e.g. for cyclic
wake and sense
LP_CLK2
B
U
S
PMU-PCU
PMU-SFR
MON
LIN
PMU-CMU
PMU-RMU
PMU-WMU
P0.0...P0.4
P1.0...P1.4
PMU control
Power management unit
Figure 3
Table 4
Power management unit block diagram
Description of PMU submodules
Module name Modules
Functions
Power-down Independent supply voltage
This supply is dedicated to the PMU to ensure an
operation independently of generated power
supplies (VDDP, VDDC).
supply
generation for PMU.
•
•
•
Clock source for all PMU
submodules.
LP_CLK
(18 MHz)
This ultra-low-power oscillator generates the clock
for the PMU.
This clock is also used as the backup clock for the
system in case of PLL clock failures and as an
independent clock source for WDT1.
Backup clock source for the
system.
Clock source for WDT1.
LP_CLK2
(100 kHz)
Clock source for PMU.
This ultra-low-power oscillator generates the clock
for the PMU in Stop mode and in the cyclic modes.
Peripherals
Peripheral blocks of PMU.
These blocks include the analog peripherals to
ensure a stable and fail-safe PMU startup and
operation (bandgap, bias).
Datasheet
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TLE9872QTW40
Power management unit (PMU)
Table 4
Description of PMU submodules (cont’d)
Module name Modules
Power supply Voltage regulators for VDDP and
Functions
This block includes the voltage regulators for the pad
supply (VDDP) and the core supply (VDDC).
generation
unit (PGU)
VDDC.
VDDEXT
Voltage regulator for VDDEXT to
supply external modules (e.g.,
sensors).
This voltage regulator is a dedicated supply for
external modules and can also be used for cyclic
sense operations (e.g., with hall sensor).
PMU-SFR
PMU-PCU
All extended special function registers This module contains all registers needed to control
that are relevant to the PMU.
and monitor the PMU.
Power control unit of the PMU.
This block is responsible for controlling all power-
related actions within the PGU module. It also
contains all regulator-related diagnostics such as
undervoltage and overvoltage detection as well as
overcurrent and short-circuit diagnostics.
PMU-WMU
PMU-CMU
PMU-RMU
Wake-up management unit of the
PMU.
This block is responsible for controlling all actions
related to wake-up within the PMU module.
Cyclic management unit of the PMU. This block is responsible for controlling all actions in
cyclic mode.
Reset management unit of the PMU. This block generates resets triggered by the PMU,
such as undervoltage or short-circuit reset, and
passes all resets to the relevant modules and their
registers.
Datasheet
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TLE9872QTW40
Power management unit (PMU)
5.2.2
PMU modes overview
The following state diagram shows the available modes of the device.
VS > 4 V and VS ramp-up
or
VS < 3 V and VS ramp-down
LIN-wake or
MON-wake or
cyclic-wake
start-up
VDDC = stable and
error_supp < 5
VDDC / VDDP =
fail (short-circuit)
error_supp ++
error_supp=5
sleep
active
Sleep command (from MCU) or
WDT1_SEQ_FAIL = 1 ( error_wdt = 5) or
VDDC / VDDP = overload or
system overtemperature
LIN-wake or
MON-wake or
GPIO-wake or
cyclic_wake or
PMU_PIN = 1 or
SUP_TMOUT = 1
PMU_PIN = 1 or
PMU_SOFT = 1 or
(PMU_Ext_WDT = 1 and
WDT1_SEQ_FAIL = 0
error_wdt ++)
Stop
command
(from MCU)
stop
cyclic-sense
Figure 4
Power management unit system modes
Datasheet
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TLE9872QTW40
Power management unit (PMU)
5.3
Power supply generation unit (PGU)
5.3.1
Voltage regulator 5.0 V (VDDP)
This module represents the 5 V voltage regulator, which provides the pad supply for the parallel port pins and
other 5 V analog functions (e.g. LIN transceiver).
Features
•
•
•
•
•
•
•
•
5 V low-drop voltage regulator
Overcurrent monitoring and shutdown with MCU signaling (interrupt)
Overvoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with reset (undervoltage reset, VDDPUV
Preregulator for the VDDC regulator
GPIO supply
)
Pull-down current source at the output for Sleep mode only (typ. 5 mA)
The output capacitor CVDDP is mandatory to ensure proper regulator functionality.
VDDP regulator
VS
VDDP
CVDDP
VPRE
A
V
GND (pin 39)
I
5 V LDO
LDO supervision
Figure 5
Module block diagram of the VDDP voltage regulator
Datasheet
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TLE9872QTW40
Power management unit (PMU)
5.3.2
Voltage regulator 1.5 V (VDDC)
This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core, the
digital peripherals, and other internal analog 1.5 V functions (e.g., ADC2) of the chip. To further reduce the
current consumption of the MCU during Stop mode the output voltage can be lowered to VDDCOUT_Stop_Red
.
Features
•
•
•
•
•
•
1.5 V low-drop voltage regulator
Overcurrent monitoring and shutdown with MCU signaling (interrupt)
Overvoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with reset
Pull-down current source at the output for Sleep mode only (typ. 100 μA)
The output capacitor CVDDC is mandatory to ensure a proper regulator functionality.
VDDC regulator
VDDP (5 V)
VDDC (1.5 V)
A
V
CVDDP
CVDDC
GND (pin 39)
I
1.5 V LDO
LDO supervision
Figure 6
Module block diagram of the VDDC voltage regulator
Datasheet
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TLE9872QTW40
Power management unit (PMU)
5.3.3
External voltage regulator 5.0 V (VDDEXT)
This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used,
e.g., to supply an external sensor, LEDs, or potentiometers.
Features
•
•
•
•
•
•
•
Switchable +5 V, low-drop voltage regulator
Switch-on overcurrent blanking time in order to drive small capacitive loads
Overcurrent monitoring and shutdown with MCU signaling (interrupt)
Overvoltage monitoring with MCU signaling (interrupt)
Undervoltage monitoring with MCU signaling (interrupt)
Pull-down current source at the output for Sleep mode only (typ. 100 μA)
Cyclic sense option together with GPIOs
The output capacitor CVDDEXT is mandatory to ensure a proper regulator functionality.
VDDEXT regulator
VS
VDDEXT
CVDDEXT
VPRE
A
V
GND (pin 39)
I
5 V LDO
LDO supervision
Figure 7
Module block diagram of the external voltage regulator
Datasheet
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TLE9872QTW40
System control unit – digital modules (SCU-DM)
6
System control unit – digital modules (SCU-DM)
6.1
Features
•
•
•
•
•
•
Flexible clock configuration features
Reset management of all system resets
System modes control for all power modes (Active mode, Stop mode, Sleep mode)
Enabling interrupts for many system peripherals
General-purpose input/output control
Debug mode control of system peripherals
6.2
Introduction
The system control unit (SCU) supports all central control tasks in the TLE9872QTW40. The SCU is made up of
the following submodules:
•
•
•
•
•
•
•
•
•
•
Clock system and control
Reset control
Power management
Interrupt management
General port control
Flexible peripheral management
Module suspension control
Watchdog timer
Error detection and correction in data memory
Miscellaneous control
Datasheet
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TLE9872QTW40
System control unit – digital modules (SCU-DM)
6.2.1
Block diagram
"On" signals to digital
peripherals;
status signalsfrom
digital peripherals
AHB
PMCU
WDT
fSYS
I
N
T
E
R
N
A
L
CGU
fOSC
XTAL1
XTAL2
OSC_HP
PLL
NMI
ICU
fPLL
LP_CLK
fSYS
INTISR<15:0>
CG
fPCLK
fMI_CLK
B
U
S
fTF ILT_CLK
PMU_1V5DidPOR
PMU_PIN
PMU_ExtWDT
PMU_IntWDT
PMU_SOFT
Misc. control
MODPISELx
RCU
PMU_Wake
RESET_TYPE_3
RESET_TYPE_4
P0_POCONy.PDMx
P1_POCONy.PDMx
Portcontrol
System control unit – digital modules
Figure 8
System control unit – digital modules block diagram
AHB (Advanced High-Performance Bus)
PMCU (power module control unit)
WDT (watchdog timer in SCU-DM)
•
fSYS: System clock
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TLE9872QTW40
System control unit – digital modules (SCU-DM)
CGU (clock generation unit)
•
•
•
•
•
f
SYS: System clock
fPCLK: Peripheral clock
f
f
MI_CLK: Measurement interface clock
TFILT_CLK: Analog module filter clock
LP_CLK Clock source for all PMU submodules and WDT1
ICU (interrupt control unit)
•
•
NMI (non-maskable interrupt)
INTISR<15,13:4,1,0> External interrupt signals
RCU (reset control unit)
•
•
•
•
•
•
•
•
PMU_1V5DidPOR Undervoltage reset of power-down supply
PMU_PIN Reset generated by reset pin
PMU_ExtWDT WDT1 reset
PMU_IntWDT WDT (SCU) reset
PMU_SOFT Software reset
PMU_Wake Sleep mode/Stop mode exit with reset
RESET_TYPE_3 Peripheral reset (contains all resets)
RESET_TYPE_4 Peripheral reset (without SOFT and WDT reset)
Port control
•
•
P0_POCONy.PDMx Driver strength control
P1_POCONy.PDMx Driver strength control
Miscellaneous control
MODPISELx mode selection registers for UART (source section) and timer (trigger or count selection)
•
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TLE9872QTW40
System control unit – digital modules (SCU-DM)
6.3
Clock generation unit
The clock generation unit (CGU) enables a flexible clock generation for the TLE9872QTW40. During user
program execution, the frequency can be modified to optimize the performance/power consumption ratio,
allowing power consumption to be adapted to the actual application state.
The CGU in the TLE9872QTW40 consists of one oscillator circuit (OSC_HP), a phase-locked loop (PLL) module
with an internal oscillator (OSC_PLL), and a clock control unit (CCU). The CGU can convert a low-frequency
input/external clock signal to a high-frequency internal clock.
The system clock fSYS is generated from one of the following selectable clocks:
•
•
•
PLL clock output fPLL
Direct clock from oscillator OSC_HP fOSC
Low-precision clock fLP_CLK (hardware-enabled for startup after reset and during power-down wake-up
sequence)
CGU
PLL_CON
CMCON1
OSC_CON
SYSCON0
XTAL1
XTAL2
PLL
f
PLL
OSC_HP
0
1
f
OSC_int
f
SYS
f
LP_CLK
2
3
LP_CLK
f
LP_CLK
PMU
Figure 9
Clock generation unit block diagram
The following sections describe the different parts of the CGU.
6.3.1
Low-precision clock
The clock source LP_CLK is a low-precision RC oscillator (LP-OSC) with a nominal frequency of 18 MHz that is
enabled by hardware as an independent clock source for the TLE9872QTW40 startup after reset and during the
power-down wake-up sequence. fLP_CLK is not user-configurable.
Datasheet
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TLE9872QTW40
System control unit – power modules (SCU-PM)
7
System control unit – power modules (SCU-PM)
7.1
Features
•
•
•
•
Clock watchdog unit (CWU): Supervises all clocks with NMI signaling relevant to power modules.
Interrupt control unit (ICU): All interrupt flags and status flags with system relevance.
Power control unit (PCU): Takes over control when device enters and exits Sleep and Stop mode.
External watchdog (WDT1): Independent system watchdog for monitoring system activity.
7.2
Introduction
7.2.1
Block diagram
The system control unit of the power modules consists of the submodules in the figure shown below:
"On" signals to analog
peripherals;
status signalsfrom
analog peripherals
AHB
I
N
T
PCU
WDT1
LP_CLK
E
R
N
A
L
fSYS
MI_CLK
PREWARN_SUP_NMI
PREWARN_SUP_INT
INT<n:0>
B
U
S
CWU
ICU
TFILT_CLK
System control unit – power modules
Figure 10 Block diagram of system control unit – power modules
AHB (Advanced High-performance Bus)
CWU (clock watchdog unit)
•
•
•
fsys: System frequency
MI_CLK: Measurement interface clock (analog clock), derived from fsys using division factors 1/2/3/4
TFILT_CLK: Clock used for digital filters, derived from fsys using configurable division factors
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System control unit – power modules (SCU-PM)
WDT1 (system watchdog)
•
LP_CLK Clock source for all PMU submodules and WDT1
ICU (interrupt control unit)
•
•
•
PREWARN_SUP_NMI Supply prewarning NMI request
PREWARN_SUP_INT Supply prewarning interrupt
Grouping of peripheral interrupts for external interupt nodes:
–
–
–
–
Grouping single peripheral interrupts for interrupt node INT<2> (measurement unit (MU))
Grouping single peripheral interrupts for interrupt node INT<3> (ADC1-VAREF)
Grouping single peripheral interrupts for interrupt node INT<10> (UART1-LIN transceiver)
Grouping single peripheral interrupts for interrupt node INT<14> (bridge driver)
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Arm® Cortex®-M3 core
8
Arm® Cortex®-M3 core
8.1
Features
The key features of the Arm® Cortex®-M3 implemented are listed below.
Processor core: a low-gate-count core, with low-latency interrupt processing
•
•
•
•
•
•
•
A subset of the Thumb®-2 instruction set
Banked stack pointer (SP) only
32-bit hardware divide instructions, SDIV and UDIV (Thumb-2 instructions)
Handler and thread modes
Thumb and debug states
Interruptible-continued instructions LDM/STM, push/pop for low interrupt latency
Automatic processor state saving and restoration for low-latency interrupt service routine (ISR) entry and
exit
•
•
Arm® architecture v7-M Style BE8/LE support
Arm®v6 unaligned accesses
Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low
latency interrupt processing
•
•
•
•
Interrupts, configurable from 1 to 16
Bits of priority (4)
Dynamic reprioritization of interrupts
Priority grouping. This enables selection of preemptive interrupt levels and non-preemptive interrupt
levels.
•
•
Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing
without the overhead of state-saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction
overhead.
Bus interfaces
•
•
•
Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and system bus interface
Memory access alignment
Write buffer for buffering of write data
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Arm® Cortex®-M3 core
8.2
Introduction
The Arm® Cortex®-M3 processor is a leading 32-bit processor and provides a high-performance and cost-
optimized platform for a broad range of applications including microcontrollers, automotive body systems
and industrial control systems. Like the other Arm® Cortex® family processors, the Arm® Cortex®-M3 processor
implements the Thumb®-2 instruction set architecture. With the optimized feature set the Arm® Cortex®-M3
delivers 32-bit performance in an application space that is usually associated with 8- and 16-bit
microcontrollers.
8.2.1
Block diagram
Figure 11 shows the functional blocks of the Arm® Cortex®-M3.
Arm® Cortex®-M3 processor
Nested vectored
interrupt
Arm® Cortex®-M3
processor
core
Interrupt and
power control
controller
(NVIC)
AHB
access port
(AHB-AP)
Serial-wire
(SW-DP)
Bus matrix
ICode
DCode
AHB-Lite
data
System bus
ICode
Serial-wire debug
interface
AHB-Lite
instruction
interface
PBA0
PBA1
interface
Figure 11 Arm® Cortex®-M3 block diagram
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DMA controller
9
DMA controller
Figure 12 shows the top level block diagram of the TLE9872QTW40.
The bus matrix allows the μDMA to access the PBA0, PBA1, and RAM.
9.1
Features
The principal features of the DMA Controller are:
•
•
•
•
•
•
•
It is compatible with AHB-Lite for DMA transfers.
It is compatible with APB for register programming.
It has a single AHB-Lite master for transferring data using a 32-bit address bus and a 32-bit data bus.
It supports 13 DMA channels.
Each DMA channel has dedicated handshake signals.
Each DMA channel has a programmable priority level.
Each priority level arbitrates using a fixed priority that is determined by the DMA channel number. The DMA
also supports multiple transfer types:
- Memory-to-memory
- Memory-to-peripheral
- Peripheral-to-memory
•
•
•
•
•
It supports multiple DMA cycle types.
It supports multiple DMA transfer data widths.
Each DMA channel can access a primary and an alternate channel control data structure.
All the channel control data is stored in system memory (RAM) in little-endian format.
It performs all DMA transfers using the single AHB-Lite burst type. The destination data width is equal to
the source data width.
•
•
The number of transfers in a single DMA cycle can be programmed from 1 to 1024.
The transfer address increment can be greater than the data width.
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DMA controller
9.2
Introduction
Please also refer to Chapter 9.3, Functional description.
9.2.1
Block diagram
SSC1
ADC1
Timer3
DMA requests
DMA requests
DMA requests
DMA controller
Bus matrix
S
PBA1
S
AHB2APB
AHB-Lite
M
M
AHB-Lite
APB interface
interrupts
SCU_DM
PBA0
S
AHB-Lite
AHB-Lite
M
M
RAM
S
Arm® core
interrupts
S
S
S
M
M
M
AHB-Lite
AHB-Lite
Figure 12
DMA controller top level block diagram
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DMA controller
9.3
Functional description
9.3.1
DMA mode overview
The DMA controller implements the following 13 hardware DMA requests:
•
ADC1 complete sequence 1 done: DMA transfer is requested on completion of the ADC1 channel conversion
sequence.
•
ADC1 exceptional sequence 2 (ESM) done: DMA transfer is requested on completion of the ADC1 conversion
sequence triggered by an exceptional measurement request.
•
•
•
SSC1/2 transmit byte: DMA transfer is requested upon the completion of data transmission via SSC1/2.
SSC1/2: receive byte: DMA transfer is requested upon the completion of data reception via SSC1/2.
ADC1 channel 0 conversion done: DMA transfer is requested on completion of the ADC1 channel 0
conversion.
•
•
•
•
•
•
•
•
ADC1 channel 1 conversion done: DMA transfer is requested on completion of the ADC1 channel 1
conversion.
ADC1 channel 2 conversion done: DMA transfer is requested on completion of the ADC1 channel 2
conversion.
ADC1 channel 3 conversion done: DMA transfer is requested on completion of the ADC1 channel 3
conversion.
ADC1 channel 4 conversion done: DMA transfer is requested on completion of the ADC1 channel 4
conversion.
ADC1 channel 5 conversion done: DMA transfer is requested on completion of the ADC1 channel 5
conversion.
ADC1 channel 6 conversion done: DMA transfer is requested on completion of the ADC1 channel 6
conversion.
ADC1 channel 7 conversion done: DMA transfer is requested on completion of the ADC1 channel 7
conversion.
Timer3 ccu6_int: DMA transfer is requested following a timer trigger.
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Address space organization
10
Address space organization
The TLE9872QTW40 manipulates operands in the following memory spaces:
•
•
•
256 KB (incl. 4 KByte emulated EEPROM) of flash memory in code space
32 KB Boot ROM memory in code space (used for boot code and IP storage)
8 KB RAM memory in code space and data space (RAM can be read/written as program memory or external
data memory)
•
Special function registers (SFRs) in peripheral space
The figure below shows the detailed address alignment of the TLE9872QTW40:
00000000H
Reserved (boot ROM)
00007FFFH
10FFFFFFH
00008000H
Reserved
11000000H
Flash, 256 KB
1103FFFFH
11040000H
Reserved
17FFFFFFH
18001FFFH
18000000H
SRAM, 8 KB
18002000H
Reserved
3FFFFFFFH
47FFFFFFH
40000000H
PBA0
48000000H
PBA1
5FFFFFFFH
DFFFFFFFH
60000000H
Reserved
E0000000H
Private Peripheral Bus
E00FFFFFH
FFFFFFFFH
E0100000H
Reserved
Figure 13 Memory map
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Memory control unit
11
Memory control unit
11.1
Features
•
•
•
•
Handles all system memory types and their interaction with the CPU
Memory protection functions for all system memory types (D-flash, P-flash, RAM)
Address management with access violation detection including reporting
Linear address range for all memory types (no paging)
11.2
Introduction
11.2.1
Block diagram
The memory control unit is divided into the following submodules:
•
•
•
•
•
NVM memory module (embedded flash memory)
RAM memory module
BootROM memory module
Memory protection unit (MPU) module
Peripheral bridge PBA0
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Memory control unit
NVM
S0
RAM
S1
BROM
S2
PBA0
S3
Memory protection
unit
Sx: Bus slave
Mx: Bus master
M0
M1
M2
M3
Bus matrix
Figure 14 Block diagram of the memory control unit
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Memory control unit
11.3
NVM module (flash memory)
The flash memory provides embedded user-programmable non-volatile memory, allowing fast and reliable
storage of user code and data.
Features
•
•
In-system programming via LIN (flash mode) and SWD.
Error correction code (ECC) for detection of single-bit and double-bit errors and dynamic correction of
single-bit errors.
•
•
•
•
•
•
•
•
•
•
•
Interrupts and signals double-bit errors by the NMI.
Program width of 128 byte (page).
Minimum erase width of 128 bytes (page).
Integrated hardware support for EEPROM emulation.
8-byte read access.
Physical read access time: 75 ns.
Code-read access acceleration integrated; read buffer and automatic pre-fetch.
Page-program time: tPR
.
Page-erase (128 bytes) and sector-erase (4 KB) time: tER.
Erased bit (cell) is read as ‘1’, for code flash and 100TP.
Erased bit (cell) is read as ‘0’ plus NMIMAP request, for data flash.
Note:
The user has to ensure that no flash operations which change the content of the flash get interrupted
at any time.
The clock for the NVM is supplied with the system frequency fsys. Integrated firmware routines for erasing NVM,
EEPROM emulation, and other operations are provided.
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Interrupt system
12
Interrupt system
12.1
Features
•
•
•
Up to 16 interrupt nodes for on-chip peripherals
Up to 8 NMI nodes for critical system events
Maximum flexibility for all 16 interrupt nodes
12.2
Introduction
Before enabling an interrupt, all corresponding interrupt status flags must be cleared.
12.2.1
Overview
The TLE9872QTW40 supports 16 interrupt vectors with 16 priority levels. Fifteen of these interrupt vectors are
assigned to the on-chip peripherals: GPT12, SSC, CCU6, DMA, bridge driver and A/D converter are each
assigned to one dedicated interrupt vector; while UART1 and Timer2, as well as UART2, external interrupt 2
and Timer21 share interrupt vectors. Two vectors are dedicated for external interrupt 0 and 1.
Table 5
Interrupt vector table
Service request Node ID Description
GPT12
MU-ADC2/T3
ADC1
0/1
2
GPT interrupt (T2-T6, CAPIN)
Measurement unit, VBG, Timer3, BEMF
ADC1 interrupt / VREF5V overload / VREF5V OV/UV
CCU6 node 0 interrupt
3
CCU0
4
CCU1
5
CCU6 node 1 interrupt
CCU2
6
CCU6 node 2 interrupt
CCU3
7
CCU6 node 3 interrupt
SSC1
8
SSC1 interrupt (receive, transmit, error)
SSC2 interrupt (receive, transmit, error)
UART1 (ASC-LIN) interrupt (receive, transmit), Timer2, linsync1, LIN
UART2 interrupt (receive, transmit), Timer21, external interrupt (EINT2)
External interrupt (EINT0), MON
SSC2
9
UART1
UART2
EXINT0
EXINT1
BDRV/CP
DMA
10
11
12
13
14
15
External interrupt (EINT1)
Bridge driver / charge pump
DMA controller
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Interrupt system
Table 6
NMI interrupt table
Service request
Node
NMI
NMI
NMI
NMI
NMI
NMI
NMI
NMI
Description
Watchdog timer NMI
PLL NMI
Watchdog timer overflow
PLL loss-of-lock
NVM operation complete NMI
Overtemperature NMI
Oscillator watchdog NMI
NVM map error NMI
ECC error NMI
NVM operation complete
System overtemperature
Oscillator watchdog / MI_CLK watchdog timer overflow
NVM map error
RAM/NVM uncorrectable ECC error
Supply prewarning
Supply prewarning NMI
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Watchdog timer (WDT1)
13
Watchdog timer (WDT1)
13.1
Features
There are two watchdog timers in the system. The watchdog timer (WDT) within the system control unit –
digital modules (see SCU_DM) and the Watchdog Timer (WDT1) located within the system control unit – power
modules (see SCU_PM). The watchdog timer WDT1 is described in this section.
In Active mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way
to recover from software or hardware failures.
The WDT1 is always enabled in Active mode. In Sleep mode, Stop Mode and SWD mode (Debug mode), the
WDT1 is automatically disabled.
Functional Features
•
•
•
•
•
Windowed watchdog timer with programmable timing in Active mode.
Long-open window (typ. 80 ms) after power-up, reset, wake-up.
Short-open window (typ. 30 ms) to facilitate flash programming.
Disabled during debugging.
Safety shutdown to Sleep mode after 5 missed WDT1 services.
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Watchdog timer (WDT1)
13.2
Introduction
The behavior of the watchdog timer in Active mode is illustrated in Figure 15.
Reset
Always
Long
Open Window
Trigger and
count_SOW = 0
Normal
Short
"windowed"
operation
open window
and SOW
Trigger and
count_SOW = 0
Trigger SOW and
count_SOW++
Trigger and
count_SOW = 0
Figure 15 Watchdog timer behavior
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GPIO ports and peripheral I/O
14
GPIO ports and peripheral I/O
The TLE9872QTW40 has 15 port pins organized into three parallel ports: Port 0 (P0), port 1 (P1) and port 2 (P2).
Each port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled.
P0 and P1 are bidirectional and can be used as general-purpose input/output (GPIO) or to perform alternate
input/output functions for the on-chip peripherals. For ports configured as an output, the open drain mode
can be selected. On port 2 (P2), analog inputs are shared with general-purpose inputs.
14.1
Features
Features of bidirectional ports (P0, P1)
•
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open-drain mode
Configurable drive strength
Transfer of data through digital inputs and outputs (general-purpose I/O)
Alternate input/output for on-chip peripherals
Features of the analog port (P2)
•
•
•
Configurable pull-up/pull-down devices
Transfer of data through digital inputs
Alternate inputs for on-chip peripherals
14.2
Introduction
14.2.1
Port 0 and port 1
Figure 16 shows the block diagram of a TLE9872QTW40 bidirectional port pin. Each port pin is equipped with
a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents of the
control register, each individual pin can be configured as an input or an output. The user can also configure
each pin as an open-drain pin with or without an internal pull-up/pull-down.
Each bidirectional port pin can be configured for input or output operation. Switching between input and
output mode is accomplished through the register Px_DIR (x = 0 or 1), which enables or disables the output
and input drivers. A port pin can only be configured as either input or output at any one time.
In input mode (default after reset), the output driver is switched off (high-impedance). The voltage level
present at the port pin is translated into a logical 0 or 1 via a Schmitt trigger device and can be read via the
register Px_DATA.
In output mode, the output driver is activated and drives the value supplied through the multiplexer to the
port pin. In the output driver, each port line can be switched to open-drain mode or normal mode (push-pull
mode) via the register Px_OD.
The output multiplexer in front of the output driver enables the port output function to be used for different
purposes. If the pin is used for general-purpose output, the multiplexer is switched by software to the data
register Px_DATA. Software can set or clear the bit in Px_DATA and therefore directly influence the state of the
port pin. If an on-chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be
switched via the multiplexer to the output driver circuitry. Selection of the alternate output function is defined
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GPIO ports and peripheral I/O
in registers Px_ALTSEL0 and Px_ALTSEL1. When a port pin is used in an alternate function, its direction must
be set accordingly in the register Px_DIR.
Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register
Px_PUDSEL selects whether a pull-up or pull-down device is activated, while register Px_PUDEN enables or
disables the pull device.
PUDSEL
Pull-up / pull-down
select register
Pull-up / pull-down
control logic
PUDEN
Pull-up / pull-down
enable register
TCCR
Temperature compensation
control register
Px_POCONy
Port output
driver control registers
I
N
T
E
R
N
A
L
OD
Open-drain
control register
DIR
Direction register
ALTSEL0
Alternate select
register 0
B
U
S
ALTSEL1
Alternate select
register 1
Pull device
AltDataOut 3
AltDataOut 2
AltDataOut 1
11
10
Output
driver
01
00
Out
In
Px_DATA
Data register
Input
driver
AltDataIn
Schmitt trigger
Pad
Figure 16 General structure of a bidirectional port (P0, P1)
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GPIO ports and peripheral I/O
14.2.2
Port 2
Figure 17 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register
P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage
level present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via
register P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device.
Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated, while register P2_PUDEN
enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt
trigger device for direct feed-through to the ADC input channels.
PUDSEL
Pull-up / pull-down
select register
Pull-up / pull-down
control logic
I
N
T
E
R
N
A
L
PUDEN
Pull-up / pull-down
enable register
DIR
Direction register
Pull device
B
U
S
Input
driver
In
DATA
Data register
Schmitt
trigger
Pad
AltDataIn
AnalogIn
Figure 17 General structure of input port (P2)
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GPIO ports and peripheral I/O
14.3
TLE9872QTW40 port module
14.3.1
Port 0
14.3.1.1 Port 0 functions
Table 7
Port pin
P0.0
Port 0 input/output functions
Input/output
Select
GPI
Connected signals
P0_DATA.P0
SWCLK / TCK_0
T12HR_0
T4INA
From/to module
Input
–
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
GPI
SW
CCU6
GPT12T4
Timer2
–
T2_0
–
EXINT2_3
P0_DATA.P0
T3OUT
SCU
Output
Input
–
GPT12T3
Timer 21
UART2
–
EXF21_0
RXDO_2
P0_DATA.P1
T13HR_0
TxD1
P0.1
INP1
INP2
INP3
INP4
INP5
INP6
INP7
GPO
ALT1
ALT2
ALT3
CCU6
LIN_TxD
GPT12CAP
Timer21
GPT12T4
SSC1
CAPINA
T21_0
T4INC
MRST_1_2
EXINT0_2
P0_DATA.P1
TxD1
SCU
Output
–
UART1 / LIN_TxD
–
–
T6OUT
GPT12T6
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GPIO ports and peripheral I/O
Table 7
Port pin
P0.2
Port 0 input/output functions (cont’d)
Input/output
Select
GPI
Connected signals
P0_DATA.P2
CCPOS2_1
T2EUDA
From/to module
–
Input
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
CCU6
GPT12T2
SSC1
MTSR_1
T21EX_0
Timer21
GPT12T6
–
T6INA
Output
Input
P0_DATA.P2
COUT60_0
MTSR_1
CCU6
SSC1
EXF2_0
Timer2
–
P0.3
P0_DATA.P3
SCK_1
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
SSC1
CAPINB
GPT12
GPT12T5
GPT12T4
CCU6
–
T5INA
T4EUDA
CCPOS0_1
P0_DATA.P3
SCK_1
Output
Input
SSC1
EXF21_2
Timer21
GPT12T6
–
T6OUT
P0.4
P0_DATA.P4
MRST_1_0
CC60_0
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
SSC1
CCU6
Timer21
SCU
T21_2
EXINT2_2
T3EUDA
GPT12T3
CCU6
–
CCPOS1_1
P0_DATA.P4
MRST_1_0
CC60_0
Output
SSC1
CCU6
SCU
CLKOUT_0
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GPIO ports and peripheral I/O
14.3.2
Port 1
14.3.2.1 Port 1 functions
Table 8
Port pin
P1.0
Port 1 input/output functions
Input/output
Select
GPI
Connected signals
P1_DATA.P0
T3INC
From/to module
–
Input
INP1
INP2
INP3
INP4
INP5
GPO
ALT1
ALT2
ALT3
GPI
GPT12T3
GPT12T4
CCU6
SSC2
SCU
T4EUDB
CC61_0
SCK_2
EXINT1_2
P1_DATA.P0
SCK_2
Output
Input
–
SSC2
CCU6
Timer21
–
CC61_0
EXF21_3
P1_DATA.P1
–
P1.1
INP1
INP2
INP3
INP4
INP5
INP6
GPO
ALT1
ALT2
ALT3
GPI
–
T6EUDA
–
GPT12T6
–
MTSR_2
T21_1
SSC2
Timer21
SCU
EXINT1_0
P1_DATA.P1
MTSR_2
COUT61_0
TXD2_0
Output
Input
–
SSC2
CCU6
UART2
–
P1.2
P1_DATA.P2
T2INA
INP1
INP2
INP3
INP4
INP5
INP6
INP7
GPO
ALT1
ALT2
ALT3
GPT12T2
Timer2
Timer21
SSC2
UART2
CCU6
SCU
T2EX_1
T21EX_3
MRST_2_0
RXD2_0
CCPOS2_2
EXINT0_1
P1_DATA.P2
MRST_2_0
COUT63_0
T3OUT
Output
–
SSC2
CCU6
GPT12T3
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GPIO ports and peripheral I/O
Table 8
Port pin
P1.3
Port 1 input/output functions (cont’d)
Input/output
Select
GPI
Connected signals
P1_DATA.P3
T6INB
From/to module
Input
–
INP1
INP2
INP3
INP4
INP5
INP6
INP7
GPO
ALT1
ALT2
ALT3
GPI
GPT12T6
–
–
CC62_0
CCU6
GPT12T6
–
T6EUDB
–
CCPOS0_2
EXINT1_1
P1_DATA.P3
EXF21_1
CC62_0
CCU6
SCU
Output
Input
–
Timer21
CCU6
UART2
–
TXD2_1
P1.4
P1_DATA.P4
EXINT2_1
T21EX_1
T5EUDA
RxD1
INP1
INP2
INP3
INP4
INP5
INP6
INP7
GPO
ALT1
ALT2
ALT3
SCU
Timer21
GPT12T5
UART1
GPT12T2
CCU6
SSC1
–
T2INB
CCPOS1_2
MRST_1_3
P1_DATA.P4
CLKOUT_1
COUT62_0
RxD1
Output
SCU
CCU6
UART1 / LIN_RxD
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GPIO ports and peripheral I/O
14.3.3
Port 2
14.3.3.1 Port 2 functions
Table 9
Port pin
P2.0
Port 2 input functions
Input/output
Select
Connected signals
P2_DATA.P0
CCPOS0_3
-
From/to module
–
Input
GPI
INP1
INP2
INP3
INP4
INP5
ANALOG
GPI
CCU6
–
T12HR_2
EXINT0_0
CC61_2
CCU6
SCU
CCU6
ADC1
–
AN0
P2.2
P2.3
Input
Input
P2_DATA.P2
CCPOS2_3
T13HR_2
–
INP1
INP2
INP3
INP4
ANALOG
GPI
CCU6
CCU6
–
CC62_2
CCU6
ADC1
–
AN2
P2_DATA.P3
CCPOS1_0
CTRAP#_1
T21EX_2
CC60_1
INP1
INP2
INP3
INP4
INP5
ANALOG
GPI
CCU6
CCU6
Timer21
CCU6
SCU
EXINT0_3
AN3
ADC1
–
P2.4
P2.5
Input
Input
P2_DATA.P4
CTRAP#_0
T2EUDB
MRST_1_1
EXINT1_3
AN4
INP1
INP2
INP3
INP4
ANALOG
GPI
CCU6
GPT12T2
SSC1
SCU
ADC1
–
P2_DATA.P5
RXD2_1
INP1
INP2
INP3
INP4
ANALOG
UART2
GPT12T3
SSC2
Timer 2
ADC1
T3EUDB
MRST_2_1
T2_1
AN5
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General-purpose timer units (GPT12)
15
General-purpose timer units (GPT12)
15.1
Features
15.1.1
Features of block GPT1
The following list summarizes the supported features:
•
•
•
•
•
fGPT is derived from PCLK
fGPT/4 maximum resolution
3 independent timers/counters
Timers/counters can be concatenated
4 Operating modes:
–
–
–
–
Timer mode
Gated Timer mode
Counter mode
Incremental Interface mode
•
•
Reload and capture functionality
Shared interrupt: node 0
15.1.2
Features of block GPT2
The following list summarizes the supported features:
•
•
•
•
•
f
f
GPT is derived from PCLK
GPT/2 maximum resolution
2 independent timers/counters
Timers/counters can be concatenated
3 Operating modes:
–
–
–
Timer mode
Gated Timer mode
Counter mode
•
•
Extended capture/reload functions via 16-bit capture/reload register CAPREL
Shared interrupt: node 1
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General-purpose timer units (GPT12)
15.2
Introduction
The general-purpose timer unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures
which may be used for timing, event counting, pulse-width measurement, pulse generation, frequency
multiplication, and other purposes.
They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in
each block may operate independently in a number of different modes such as Gated Timer or Counter mode,
or may be concatenated with another timer of the same block.
Each block has alternate input/output functions and specific interrupts associated with it. Input signals can
be selected from several sources through the PISEL register.
The GPT module is clocked with clock fGPT. fGPT is a clock derived from PCLK.
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General-purpose timer units (GPT12)
15.2.1
Block diagram of GPT1
The GPT1 block contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The
maximum resolution is fGPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture
registers for the core timer.
T3CON.BPS1
2n : 1
Basic clock
fGPT
Interrupt request
(T2IRQ)
Aux. timer T2
Core timer T3
Aux. timer T4
U/D
T2IN
T2
mode
control
Capture
Reload
T2EUD
Toggle Latch
T3
mode
control
T3IN
T3OTL
T3OUT
U/D
T3EUD
Interrupt request
(T3IRQ)
Capture
Reload
T4IN
T4
mode
control
T4EUD
Interrupt request
(T4IRQ)
U/D
Figure 18 GPT1 block diagram (n = 2 … 5)
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General-purpose timer units (GPT12)
15.2.2
Block diagram of GPT2
The GPT2 block contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum
resolution is fGPT/2. An additional capture/reload register (CAPREL) supports capture and reload operation
with extended functionality.
T6CON.BPS2
2n : 1
Basic clock
fGPT
Toggle FF
T2
mode
control
U/D
Interrupt request
(T5IRQ)
GPT2 timer T5
T5IN
Clear
T5EUD
Capture
CAPIN
CAPREL
mode
control
GPT2 CAPREL
T3IN/
T3EUD
Interrupt request
(CRIRQ)
Reload
Interrupt request
(T6IRQ)
Clear
U/D
T6
mode
control
GPT2 timer T6
T6OTL
T6OUT
T6OUF
T6IN
T6EUD
Figure 19 GPT2 block diagram (n = 1 … 4)
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Timer2 and Timer21
16
Timer2 and Timer21
16.1
Features
•
•
16-bit auto-reload mode
Selectable up- or down-counting
One-channel 16-bit capture mode
–
16.2
Introduction
The timer modules are general-purpose 16-bit timers. Timer 2 and Timer 21 can function as timers or counters
in each of their modes. As timers, they count with an input clock of fPCLK/12 (if the prescaler is disabled). As a
counter, Timer2 counts 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for
counting is fPCLK/24 (if the prescaler is disabled).
16.2.1
Timer2 and Timer21 mode overview
Table 10
Mode
Timer2 and Timer21 modes
Description
Auto-reload
Up/down-count-disabled
•
•
•
Counting up only.
Counting starts from the 16-bit reload value, overflow at FFFFH.
The reload event can be configured to be triggered only by the overflow condition
or by a negative or positive edge at the input pin T2EX as well.
•
•
Programmable reload value in register RC2.
Interrupt is generated with reload events.
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Timer2 and Timer21
Table 10
Mode
Timer2 and Timer21 modes (cont’d)
Description
Auto-reload
Up/down-count-enabled
•
•
•
Counting up or down, direction determined by level at input pin T2EX.
No interrupt is generated.
Counting up
–
–
–
Counting starts from the 16-bit reload value, overflow at FFFFH.
Reload event triggered by overflow condition.
Programmable reload value in register RC2.
•
Counting down
–
–
–
Counting starts from FFFFH, underflow at value defined in register RC2.
Reload event triggered by underflow condition.
Reload value fixed at FFFFH.
•
•
•
•
•
•
•
Counting up only.
Channel capture
Counting starts from 0000H, overflow at FFFFH.
Reload event triggered by overflow condition.
Reload value fixed at 0000H.
Capture event triggered by falling/rising edge at pin T2EX.
Captured timer value stored in register RC2.
Reload or capture events generate interrupts.
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Timer3
17
Timer3
17.1
Features
•
•
•
•
•
•
16-bit incremental timer/counter (counting up)
Counting frequency up to fsys
Selectable clock prescaler
Six operating modes
Interrupt on overflow
Interrupt on compare
17.2
Introduction
The possible applications for this timer include measuring the time interval between events, counting events,
and generating a signal at regular intervals.
Timer3 can function as a timer or a counter. When functioning as a timer, Timer3 is incremented in periods
based on the MI_CLK or LP_CLK clocks. When functioning as a counter, Timer3 is incremented in response to
a 1-to-0 transition (falling edge) at its configured input. Timer3 can be configured in four different operating
modes for a variety of applications (see Table 11).
The different operating modes allow the timer to be used for tasks such as:
•
•
•
Simple measurements of the times between two events.
Triggering the measuring unit upon PWM/CCU6 unit
Measurement of the 100 kHz LP_CLK2
17.3
Functional description
Six modes of operation are provided to enable using this timer for various tasks. In every mode, the clocking
source can be selected from MI_CLK and LP_CLK. In addition, a prescaler provides the capability to divide the
selected clock source by 2, 4, or 8. The timer counts upwards, starting with the value in the timer count
registers, up to the maximum count value, which depends on the selected mode of operation. Timer 3
provides two individual interrupts on counter overflow, one for the low-byte and one for the high-byte counter
register.
17.3.1
Timer3 modes overview
The following table provides an overview of the timer modes together with the reasonable configuration
options in Table 11.
Table 11
Timer3 modes
Mode Submode Operation
0
1
No
13-bit timer
submode The timer essentially operates an 8-bit counter with a divide-by-32 prescaler.
a
16-bit timer
The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter.
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Timer3
Table 11
Timer3 modes (cont’d)
Mode Submode Operation
1
b
16-bit timer triggered by an event
The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter, which is
triggered by an event to enable a single-shot measurement on a preset channel with the
measurement unit.
2
3
3
No
8-bit timer with auto-reload
submode The timer register TL3 is reloaded with a user-defined 8-bit value in TH3 on overflow.
a
b
Timer3 operating as two 8-bit timers
The timer registers TL3 and TH3, operate as two separate 8-bit counters.
Timer3 operating as two 8-bit timers for clock measurement
The timer registers, TL3 and TH3, operate as two separate 8-bit counters. In this mode, the
LP_CLK2 low power clock can be measured. TL3 acts as an edge counter for the clock
edges and TH3 measures the interval between the edges.
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Capture/compare unit 6 (CCU6)
18
Capture/compare unit 6 (CCU6)
18.1
Feature set overview
This section gives an overview over the different building blocks and their main features.
Timer 12 block features
•
•
•
•
•
•
•
•
•
•
•
Three capture/compare channels. Each channel can be used either as capture or as compare channel.
Supports three-phase PWM (six outputs with separate signals for high-side and low-side switches).
16-bit resolution, maximum count frequency = peripheral clock.
Dead-time control for each channel to avoid short-circuits in the power stage.
Concurrent update of the T12 registers.
Center-aligned and edge-aligned PWM can be generated.
Single-shot mode is supported.
Start can be controlled by external events.
External events can be counted.
Multiple interrupt request sources.
Hysteresis-like control mode.
Timer 13 block features
•
•
•
•
•
•
•
•
One independent compare channel with one output.
16-bit resolution, maximum count frequency = peripheral clock.
Concurrent update of T13 registers.
Can be synchronized to T12.
Interrupt generation at period-match and compare-match.
Single-shot mode is supported.
Start can be controlled by external events.
Capability of counting external events.
Additional specific functions
•
•
•
•
•
•
•
•
Block commutation for brushless DC-drives implemented.
Position detection via hall-sensor pattern.
Noise filter for position input signals supported.
Automatic rotational speed measurement and commutation control for block commutation.
Integrated error handling.
Fast emergency stop without CPU load via external signal (CTRAP).
Control modes for multi-channel AC drives.
Output levels can be selected and adapted to the power stage.
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Capture/compare unit 6 (CCU6)
18.2
Introduction
The CCU6 unit is made up of the T12 timer block with three capture/compare channels and the T13 timer block
with one compare channel. The T12 channels can independently generate PWM signals or accept capture
triggers, or they can jointly generate control signal patterns to drive DC motors or inverters.
A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible
generation of interrupt request signals provide efficient software control.
Note:
The capture/compare module itself is referred to as CCU6 (capture/compare unit 6). A
capture/compare channel inside this module is referred to as CC6x.
The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be
combined (e.g., a channel works in compare mode, whereas another channel works in capture mode). The
timer T13 can work only in compare mode. The multi-channel control unit generates output patterns which
can be modulated by T12 and/or T13. The modulation sources can be selected and combined for modulating
signals.
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Capture/compare unit 6 (CCU6)
18.2.1
Block diagram
CCU6 Module Kernel
Compare
CC60
CC61
CC62
1
T12SUSP
Dead-
Multi-
channel
control
Debug
suspend
Trap
control
T12
T13
time
1
1
T13SUSP
control
fCC6
Clock
control
CC63
1
3
2
2
2
3
1
SR[3:0]
Interrupt
control
Input/output control
Port control
P0.x
P1.x
P2.x
Figure 20 CCU6 block diagram
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UART1/UART2
19
UART1/UART2
The description in this chapter applies to both UART1 and UART2.
19.1
Features
•
Full-duplex asynchronous modes
–
–
8-bit or 9-bit data frames, LSB first.
Fixed or variable baud rate.
•
•
•
•
•
Receive-buffered.
Multiprocessor communication.
Interrupt are generated when data transmission or receptions are complete.
Baud-rate generator with fractional divider for generating a wide range of baud rates.
Hardware logic for break and synch byte detection.
19.2
Introduction
The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive
simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first byte still has not been
read by the time when the reception of the second byte is complete, one of the bytes will be lost. The serial
port receive and transmit registers are both accessed through the special function register (SFR) SBUF. Writing
to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.
19.2.1
Block diagram
UART disreq from SCU_DM
TXD
RXD
RI
TI
TXD
SCU_DM
Interrupt
control
RXD_0
RXD_1
URIOS
SCU_DM
P0.x
UART
module
Portcontrol
P1.x
P2.x
fUART2
Clock
control
Baud rate
generator
f
BR
Address
decoder
RXDO_2
SCU_DM
AHB interface
UART
GPIOs
Figure 21 UART block diagram
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UART1/UART2
19.3
UART modes
The UART can be used in four different modes. In mode 0, it operates as an 8-bit shift register. In mode 1, it
operates as an 8-bit serial port. In modes 2 and 3, it operates as a 9-bit serial port. The only difference between
mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is
set by the underflow rate on the dedicated baud-rate generator.
The different modes are selected by setting bits SM0 and SM1 to the appropriate values, as shown in Table 12.
Table 12
UART modes
SM0
SM1
Operating mode
Baud rate
PCLK/2
Variable
PCLK/64
Variable
0
0
1
1
0
1
0
1
Mode 0: 8-bit shift register
Mode 1: 8-bit shift UART
Mode 2: 9-bit shift UART
Mode 3: 9-bit shift UART
f
f
UART1 is connected to the integrated LIN transceiver, and to GPIO for test purposes. UART2 is connected to
GPIO only.
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LIN transceiver
20
LIN transceiver
20.1
Features
General functional features
•
•
Compliant with the LIN2.2 standard, backward-compatible with LIN1.3, LIN2.0, and LIN 2.1
Compliant with SAE J2602 (slew rate, receiver hysteresis)
Special features
•
•
•
Measurement of the LIN master baudrate via Timer2
LIN can be used as input/output with SFR bits
TxD timeout feature (optional, on by default)
Operation mode features
•
•
•
•
LIN Sleep mode (LSLM)
LIN Receive-Only mode (LROM)
LIN Normal mode (LNM)
High voltage input/output mode (LHVIO)
Supported baud rates
•
•
•
•
Mode for transmission with up to 10.4 kilobaud
Mode for transmission with up to 20 kilobaud
Mode for transmission with up to 40 kilobaud
Mode for transmission with up to 115.2 kilobaud
Slope mode features
•
•
•
Normal Slope mode (20 kbit/s)
Low Slope mode (10.4 kbit/s)
Flash mode (115.2 kbit/s)
Wake-up features
LIN bus wake-up
•
20.2
Introduction
The LIN module is a transceiver for the Local Interconnect Network (LIN), compliant with the LIN2.2 standard
and backward-compatible with LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol
controller and the physical network. The LIN bus is a single-wire, bidirectional bus typically used for in-vehicle
networks, using baud rates between 2.4 kilobaud and 20 kilobaud. Additionally, baud rates up to
115.2 kilobaud are implemented.
The LIN module offers several different operation modes, including a LIN Sleep mode and the LIN Normal
mode. The integrated slope control allows using several data transmission rates with optimized EMC
performance. For data transfer at the end of line, a Flash mode up to 115.2 kilobaud is implemented. In
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LIN transceiver
specific conditions, this Flash mode supports data rates of up to 250 kbit/s. (In production environments, in
point-to-point communications with reduced wire lengths and limited supply voltages.).
20.2.1
Block diagram
VS
LIN transceiver
RBUS
LIN.CTRL_STS
LIN-FSM
LIN
CTRL
TxD_1
from UART
Driver, current
limiter, and TSD
STATUS
GND_LIN
Transmitter
RxD_1 to UART
and TIMER2,
pin T2EX
Filter
(T2EXCON=0,
T2EXIS=0)
Receiver
Filter
LIN_Wake
Sleep comparator
GND_LIN
Figure 22 LIN transceiver block diagram
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High-speed synchronous serial interface (SSC1/SSC2)
21
High-speed synchronous serial interface (SSC1/SSC2)
21.1
Features
•
Master and Slave mode operation
–
Full-duplex or half-duplex operation
•
•
Transmit- and receive-buffered
Flexible data format
–
–
–
–
Programmable number of data bits: 2 to 16 bits
Programmable shift direction: least significant bit (LSB) or most significant bit (MSB) shift first
Programmable clock polarity: idle low or high state for the shift clock
Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
•
•
•
Variable baud rate
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
–
–
–
On a “transmitter empty” condition
On a “receiver full” condition
On an error condition (receive, phase, baud rate, or transmission error)
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High-speed synchronous serial interface (SSC1/SSC2)
21.2
Introduction
The high-speed synchronous serial interface (SSC) supports both full-duplex and half-duplex serial
synchronous communication. The serial clock signal can be generated by the SSC internally (Master mode),
using its own 16-bit baud rate generator, or can be received from an external master (Slave mode). Data width,
shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible
devices as well as devices using other synchronous serial interfaces.
Data is transmitted or received on the TXD and RXD lines, which are normally connected to the MTSR (Master
Transmit, Slave Receive) and MRST (Master Receive, Slave Transmit) pins. The clock signal is output via the
MS_CLK (Master Serial Shift Clock) line or input via the SS_CLK (Slave Serial Shift Clock) line. Both lines are
normally connected to the SCLK pin. Transmission and reception of data are double-buffered.
21.2.1
Block diagram
Figure 23 shows all functionally relevant interfaces associated with the SSC kernel.
MRSTA
MRSTB
EIR
MTSR
SCU_DM
interrupt
control
RIR
TIR
MTSRA
MTSRB
P0.x
P1.x
P2.x
SSC
module
Port
control
MRST
fhw_clk
Clock
control
SCLKA
SCLKB
Address
decoder
SCLK
AHB interface
Module
Product interface
Figure 23 SSC interface diagram
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Measurement unit
22
Measurement unit
22.1
Features
•
•
•
•
•
•
•
1 x 8-bit ADC with 10 inputs. Attenuators allow measuring high-voltage input signals.
Supply voltage attenuators for attenuating VS, VDDP and VDDC.
VBG monitoring of the 8-bit ADC to guarantee functional safety requirements.
Bridge driver diagnosis measurement (VDH, VCP).
Temperature sensor for monitoring the chip temperature and PMU regulator temperature.
BEMF comparators for triggering commutation in BLDC applications.
Supplement block with reference voltage generation, bias current generation, voltage buffer for NVM
reference voltage, voltage buffer for analog module reference voltage, and a test interface.
22.2
Introduction
The measurement unit is a functional unit that comprises the following submodules:
Table 13
Measurement functions and associated modules
Module name
Module
Functions
Central function Bandgap reference circuit
unit
The bandgap reference submodule provides two
reference voltages:
1. A trimmable reference voltage for the 8-bit ADC. A
local dedicated bandgap circuit ensures that the
reference voltage does not drop, e.g., because of
crosstalk or ground voltage shift.
2. The reference voltage for the NVM module.
•
5 high-voltage inputs supporting the full supply
range (2.5 V...30.7 V(FS))
8-bit ADC (ADC2) 8-bit ADC module with 10
multiplexed inputs and including
high-voltage input attenuators
•
•
2 medium-voltage inputs (0..5 V/7 V FS).
3 low-voltage inputs (0..1.2 V/1.6 V FS)
(See the following figure for the allocation of the
inputs).
10-bit ADC (ADC1) 10-bit ADC module with 8
multiplexed inputs
Five (5 V) analog inputs from port 2.x.
VDH input
voltage
VDH input voltage attenuator
Scales down (VDH) to the input voltage range of
ADC1.CH6.
attenuator
Temperature
sensor
Temperature sensor with two
multiplexed sensing elements:
Generates an output voltage that is a linear function
of the local chip (junction) temperature.
•
•
Sensor located on the PMU
Sensor located on the central
chip
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Measurement unit
Table 13
Measurement functions and associated modules (cont’d)
Module name
Module
Functions
BEMF
comparators
Back electromotive force
comparators
Comparators are used to detect the back
electromotive force (zero-crossing event), which can
be used as a commutation trigger for BLDC
applications.
1. Generates the control signal for the 8-bit ADC2
and the synchronous clock for the switched
capacitor circuits.
Core
measurement
module
Digital signal processing and ADC2
control unit
2. Performs digital signal processing functions and
provides status outputs for interrupt generation.
22.2.1
Block diagram
GND_REF
VS
VAREF
P2.0
OP1
CH0
CH1
CH2
CH3
VARE F
GND_SENSE
CSA
OP2
P2.2
10
/
MUX
SFR
A
D
Channel sequencer
P2.3
P2.4
P2.5
CH4
CH5
CH6
CH7
ADC 1
ATTVDH_1
ATTVDH_2
ATTVDH_3
VDH
rfu
10 Bit ADC + DPP1
Programmable
range setting
CH0
CH1
CH2
CH3
CH4
CH5
rfu
ATTVS_1
ATTVS_2
VBG
VSD
ATTVSD
ATTVCP
VCP
MON
VDDP
Calibration and filter
unit with
upper and lower
threshold
ATTMON
ATTVDDP
ATTVAREF
8
/
SFR
MUX
A
D
detection and interrupt
CH6
CH7
CH8
CH9
VAREF
ADC 2
ATTVBG
PMU-VBG
ATTVDDC
VDDC
Temperature
sensor
8 Bit ADC + DPP2
Measurement unit
Figure 24 Measurement unit, overview (with opamp)
Datasheet
70
Rev. 1.0
2020-07-23
TLE9872QTW40
Measurement unit
22.2.1.1 BEMF comparator block diagram
V phase U
W
V
U
VS/2
SH3
SH2
R
R
R
R
Blank filter
BEMF comparator
Spike filter
BEMF OUT
SH1
BEMF IN
t
Measurement unit, BEMF comparators
Figure 25 BEMF comparator (applies to each of the three comparators)
Datasheet
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Rev. 1.0
2020-07-23
TLE9872QTW40
Core measurement module (incl. ADC2)
23
Core measurement module (incl. ADC2)
23.1
Features
•
10 individually programmable channels, split into two groups of user-configurable and non-configurable
channels, respectively.
•
•
Individually programmable channel prioritization scheme for the measurement unit.
Two independent filter stages with programmable low-pass and time filter characteristics for each
channel.
•
Two channel configurations:
–
–
Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis.
Two individually programmable trigger thresholds with limit hysteresis settings.
•
Individually programmable interrupts and statuses for all channel thresholds.
23.2
Introduction
The basic function of this block is the digital postprocessing of several digitized analog measurement signals
by filtering, level comparison, and interrupt generation. The measurement postprocessing block consists of
ten identical channel units attached to the outputs of the 10-channel 8-bit ADC (ADC2). It processes ten
channels, where the channel sequence and prioritization is programmable within a wide range.
23.2.1
Block diagram
4
/
Core measurement module
MUX_SEL<3:0>
Channel controller
(sequencer)
ADC2 - SFR
rfu
VS
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
VSD
VCP
First-order IIR
1
/
+
-
8-bit ADC
ADC2_CHx_UPPER_STS
ADC2_CHx_LOWER_STS
+ / -
+ / -
Calibration unit:
y= a + (1+b)*x
THy_z_UPPER.
CHx
8
/
10
/
8
/
MON
MUX
A
D
VDDP
1
/
THy_z_LOWER.
CHx
-
VAREF
+
PMU-VBG
VDDC
Digital signal processing
Temperature sensor
TSENSE
Figure 26 Module block diagram
Datasheet
72
Rev. 1.0
2020-07-23
TLE9872QTW40
Core measurement module (incl. ADC2)
23.2.2
Core measurement module mode overview
The basic function of this unit is the digital signal processing of several digitized analog measurement signals
by filtering, level comparison, and interrupt generation. The core measurement module processes ten
channels in a quasi-parallel process.
As shown in the figure above, the ADC2 postprocessing unit consists of a channel controller (sequencer), a 10-
channel demultiplexer, and the signal-processing block, which filters and compares the sampled ADC2 values
for each channel individually. The channel control block controls the multiplexer sequencing on the analog
side, before the ADC2, and in the digital domain, behind the ADC2. The channel sequence can be controlled in
a flexible way, which allows a certain degree of channel prioritization.
This capability can be used, e.g., to give supply voltage channels a higher priority than the other channel
measurements. In addition, the core measurement module offers two different postprocessing measurement
modes for over- and undervoltage detection and for two-level threshold detection.
The channel controller (sequencer) runs in one of the following modes:
•
•
•
Normal Sequencer: Channels are selected according to the 10 sequence registers which contain individual
enablers for each of the 10 channels.
Exceptional Interrupt Measurement: Following a hardware event, a high-priority channel is inserted into
the current sequence. The current actual measurement is not destroyed.
Exceptional Sequence Measurement: Following a hardware event, a complete sequence is inserted after
the current measurement is finished. The current sequence is interrupted by the exception sequence.
Datasheet
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Rev. 1.0
2020-07-23
TLE9872QTW40
10-bit analog-to-digital converter (ADC1)
24
10-bit analog-to-digital converter (ADC1)
24.1
Features
The principal features of the ADC1 are:
•
•
Up to 8 analog input channels (channel 7 reserved for future use).
Flexible results handling
–
10-bit resolution.
•
Flexible source selection due to sequencer:
–
–
–
Insert one exceptional sequence (ESM).
Insert one interrupt measurement into the current sequence (EIM), single or up to 128 times.
Software mode.
•
•
•
•
•
•
•
Conversion sample time (separate for each channel) adjustable to adapt to sensors and reference.
Standard external reference (VAREF) to support ratiometric measurements and different signal scales.
DMA support, transfer ADC conversion results via DMA into RAM.
Support of suspended and power-saving modes.
Result data protection for slow CPU access (Wait-for-Read mode).
Programmable clock divider.
Integrated sample and hold circuitry.
24.2
Introduction
The TLE9872QTW40 includes a high-performance 10-bit analog-to-digital converter (ADC1) with eight
multiplexed analog input channels. The ADC1 uses a successive approximation technique to convert the
analog voltage levels from up to eight different sources. The analog input channels of the ADC1 are available
at AN0 and AN2 to AN5.
Datasheet
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Rev. 1.0
2020-07-23
TLE9872QTW40
10-bit analog-to-digital converter (ADC1)
24.2.1
Block diagram
3
/
3
/
MUX_SEL <2:0>
Channel controller
(sequencer)
ADC1 - SFR
10
10
10
10
10
10
10
10
10
/
/
/
/
/
/
/
/
/
ADC1_OUT_CH0
ADC1_OUT_CH1
ADC1_OUT_CH2
ADC1_OUT_CH3
ADC1_OUT_CH4
ADC1_OUT_CH5
ADC1_OUT_CH6
ADC1_OUT_CH7
ADC1_RES_OUT_EIM
P2.0
CH0
CH1
CH2
CH3
ADC1
P2.2
P2.3
P2.4
P2.5
VDH
rfu
10
MUX
A
D
/
MUX
CH4
CH5
CH6
CH7
OP1
OP2
OPA
Figure 27
ADC1 top-level block diagram
As shown in the figure above, the ADC1 postprocessing block consists of a channel controller (Sequencer) and
an 8-channel demultiplexer. The channel control block controls the multiplexer sequencing on the analog
side, before the ADC1, and in the digital domain, behind the ADC1. The channel sequence can be controlled in
a flexible way, which allows a certain degree of channel prioritization.
This capability can be used, e.g., to give supply voltage channels a higher priority than the other channel
measurements.
Datasheet
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Rev. 1.0
2020-07-23
TLE9872QTW40
High-voltage monitor input
25
High-voltage monitor input
25.1
Features
•
•
•
•
High-voltage input with VMONth threshold voltage
Integrated selectable pull-up and pull-down current sources
Wake capability for power-saving modes
Level change sensitivity configurable for transitions from low to high, high to low, or both directions
25.2
Introduction
This module is dedicated to monitor external voltage levels above or below a specified threshold or it can be
used to detect a wake-up event at the high-voltage MON pin in low-power mode. The input level can be
monitored if the module is enabled (PMU_MON_CNF).
To use the Wake function when the IC is in a low-power mode, the monitoring pin is switched to Sleep mode
via the SFR bit EN.
25.2.1
Block diagram
VS
MON
+
-
Filter
to internal
circuitry
MON
Logic
SFR
Figure 28 High-voltage monitor input block diagram
Datasheet
76
Rev. 1.0
2020-07-23
TLE9872QTW40
Bridge driver (incl. charge pump)
26
Bridge driver (incl. charge pump)
26.1
Features
The MOSFET driver is intended to drive external normal-level NFET transistors in bridge configurations. The
driver provides many diagnostic functions for detecting faults.
Functional features
•
•
•
External power NFET transistor driver stage with driver capability of Qtot_max.
Adjustable cross-conduction protection.
Supply voltage (VSD) monitoring incl. adjustable over- and undervoltage shutdown with configurable
interrupt signalling.
•
•
•
•
VSD operating range: VSD_AM.
VDS comparators for short-circuit-detection in both on- and off-states.
Open-load detection in the off-state.
Flexible PWM frequency range. Rates above 25 kHz require power dissipation and duty-cycle resolution
analysis.
26.2
Introduction
The MOSFET driver stage can be used for controlling external power NFET transistors (normal level). The
module output is controlled by the SFR or the System PWM Machine (CCU6).
Datasheet
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Rev. 1.0
2020-07-23
TLE9872QTW40
Bridge driver (incl. charge pump)
26.2.1
Block diagram
VDH
VCP
PWM unit
CCU6
(not part of the module)
Predriver
BDRV.TRIM_DRVx.
LSDRV_DS_TFILT_SEL LS_HS_BT_TFILT_SEL
BDRV.TRIM_DRVx.
BDRV.CTRL3.
DSMONVTH
+
Spike
filter
Blank
filter
VDS
High-side
-
driver 1)
1
0
GHx
VREF
RGG ND
BDRV.CTRL1.HSx_PWM
SFR
SHx
1
IPDDiag
0
Low-side
driver 1)
BDRV.CTRL1.LSx_PWM
+
Blank
filter
Spike
filter
VDS
GLx
SL
-
RGG ND
BDRV.TRIM_DRVx.
BDRV.TRIM_DRVx.
LSDRV_DS_TFILT_SEL LS_HS_BT_TFILT_SEL
BDRV.CTRL3.
DSMONVTH
VREF
1) The VGSx limiter and fast discharge functions are implemented in this block.
Figure 29 Bridge driver module block diagram (incl. system connections)
26.2.2
General
The bridge driver can be controlled in two different ways:
•
In Normal mode, the output stage is fully controllable through the SFR registers CTRLx (x = 1,2,3).
Protection functions such as overcurrent and open-load detection are available.
•
The PWM mode can be enabled by setting the corresponding bit in CTRL1 and CTRL2. The PWM must be
configured in the System PWM Module (CCU6). All protection functions are available in PWM mode as well.
Protection functions
•
•
•
Overcurrent detection and shutdown feature for external MOSFET based on drain-source measurements.
Programmable minimum cross-current protection time.
Open-load detection feature in the off-state for external MOSFET.
Datasheet
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Rev. 1.0
2020-07-23
TLE9872QTW40
Current sense amplifier
27
Current sense amplifier
27.1
Features
Main features
•
•
•
•
Programmable gain settings: G
Differential input voltage: VIX
Wide common-mode input range: VCM
Low setting time: TSET
27.2
Introduction
The current sense amplifier in the following figure can be used to measure near-ground differential voltages
via the 10-bit ADC. Its gain is digitally programmable through internal control registers.
Linear calibration has to be applied to achieve high gain accuracy, e.g., end-of-line calibration using the shunt
resistor.
The following figure shows how the current sense amplifier can be used as a low-side current sense amplifier
where the motor current is converted to a voltage by means of a shunt resistor RSH. A differential amplifier
input is used to eliminate measurement errors caused by a voltage drop across the stray resistance RStray and
differences between the external and internal grounds. If the voltage at one or both inputs is outside the
operating range, the input circuit is overloaded and requires a certain specified recovery time.
In general, an external low-pass filter should suppress of EMI.
Datasheet
79
Rev. 1.0
2020-07-23
TLE9872QTW40
Current sense amplifier
27.2.1
Block diagram
VDH
VAREF or
VREF5V
VZERO
CSAb CTRL.VZERO
MOSFET
bridge
Low-pass filter
Input
offset
ROPAFILT
G = 10/20/40/60
OP2
Vzero
+
Rin_OP2
+
G
-
(VOP2 -VOP1)*G
10-bit ADC
COPAFILT
ROPAFILT
RSH
+
Rin_OP1
OP1
CSA_CTRL
RStray
AHB
CSA
GND
Figure 30 Current sense amplifier block diagram
Datasheet
80
Rev. 1.0
2020-07-23
TLE9872QTW40
Application information
28
Application information
28.1
BLDC driver
The following figure shows the TLE9872QTW40 in an electric drive application setup controlling a BLDC motor.
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition, or quality of the
device.
Rev. polarity protection
LPF
ILT
VBAT
CPF
CPF
ILT1
ILT1
CVDDP2
CVD DP1
CVDDC1
CVDDC2
EMC filter
DVS
VDDP VDDC
VS
CP1H
CP1L
CP2H
CCPS1
CVS 2
CVS1
CCPS2
CP2L
VCP
RMON
IGN
LIN
MON
LIN
RVS D
CVC P
CMON
VSD
CVS D
RVDH
VDH
CVDH
RGATE
CLIN
D
S
GND_LIN
G
GH1
SH1
TH1
CPH 1
VAREF
GND_REF 1)
RGS
CGS
CVA REF
D
S
G
CEM
CEM
CEM
CP1
CP2
CP3
TH2
CPH 2
RGATE
VDDEXT
P0.3
RGS
CGS
GH2
SH2
CVDD_EXT2
CVDD_EXT1
RVDDPU
D
S
TLE4946-2K
Hall
G
RADC
CADC
RGATE
TH3
CPH3
RVDDPU
RGS
CGS
GH3
SH3
TLE4946-2K
Hall
P1.4
P0.2
RADC
U
V
CADC
RVDDPU
D
S
RGATE
TLE4946-2K
Hall
G
W
GL1
GL2
GL3
RADC
TL1
TLE987x
CADC
RGS
CGS
D
S
M
RGATE
G
TL2
Temperature
sensor
RGS
CGS
P2.2
P1.2
D
S
RGATE
G
TL3
RGS
CGS
SL
ROPAFIL
T
OP2
RShunt
COPAFILT
OP1
P1.0
ROPAFIL
T
P1.1
Input protection
circuit
P2.0
P2.3
P2.4
RESET
Input protection
circuit
Input protection
circuit
TMS
P0.0
Debug connector
P0.1
P0.4
P2.5
P1.3
GND
RTM
S
GND
BLDC system
1) Note: Not connected to board GND.
Figure 31 Simplified sample application diagram
Note:
This is a very simplified example of an application circuit and bill of materials. The function must be
verified in the actual application.
Datasheet
81
Rev. 1.0
2020-07-23
TLE9872QTW40
Application information
Table 14
Symbol
CVS1
External components (BOM)
Function
Component
Blocking capacitor at VS pin
Blocking capacitor at VS pin
Blocking capacitor at VDDP pin
Blocking capacitor at VDDEXT pin
Blocking capacitor at VDDC pin
Blocking capacitor at VAREF pin
Standard C for LIN slave
Filter C for charge pump end driver
Charge pump capacitor
Charge pump capacitor
Charge pump capacitor
Filter C for ISO pulses
Capacitor
≥ 100 nF ceramic, ESR < 1 Ω
> 2.2 µF Elco1)
CVS2
CVDDP
CVDD_EXT
CVDDC
CVAREF
CLIN
See P_2.1.2 and P_2.1.20
See P_2.3.22 and P_2.3.20
See P_2.2.1 and P_2.2.17
See P_9.1.1
220 pF
1 µF
CVSD
CCPS1
CCP2S
CVCP
220 nF
220 nF
470 nF
10 nF
CMON
CVDH
3.3 nF
220 µF
220 µF
220 µF
1 nF
CPH1
Capacitor
CPH2
Capacitor
CPH3
Capacitor
COPAFILT
CEMCP1
CEMCP2
CEMCP3
Capacitor
Capacitor
1 nF
Capacitor
1 nF
Capacitor
1 nF
CPFILT1, CPFILT2
Capacitor
RMON
RVSD
Resistor at MON pin
3.9 kΩ
2 Ω
Limitation of reverse current due to
transient (-2 V, 8 ms).
Max. ratings of the VSD pin has to be
met, alternatively the resistor shall be
replaced by a diode
RVDH
RGATE
ROPAFILT
RSH1
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
1 kΩ
2 Ω
12 Ω
Optional
Optional
Optional
–
RSH2
RSH3
LPFILT
DVS
Reverse-polarity protection diode
–
1) The capacitor must be dimensioned so as to ensure that operations which modify the content of the flash are never
interrupted (e.g., in case of power loss).
Datasheet
82
Rev. 1.0
2020-07-23
TLE9872QTW40
Application information
28.2
ESD immunity according to IEC61000-4-2
Note:
Tests for ESD immunity according to IEC61000-4-2 “gun test” (150 pF, 330 Ω) have been performed.
The results and test conditions will be available in a test report.
Table 15
ESD “gun test”
Performed test
Result
> 6
Unit
kV
Remarks
ESD at pin LIN, versus GND1)
ESD at pin LIN, versus GND1)
Positive pulse
Negative pulse
< -6
kV
1) ESD test “ESD GUN” is specified with external components; see application diagram:
MON = 100 nF, RMON = 1 kΩ, CLIN = 220 pF, CVS = > 20 µF ELCO + 100 nF ESR < 1 Ω, CVSD = 1 µF, RVSD = 2 Ω.
C
Datasheet
83
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29
Electrical characteristics
This chapter includes all relevant electrical characteristics of the product TLE9872QTW40.
29.1
General characteristics
29.1.1
Absolute maximum ratings
Table 16
Absolute maximum ratings1)
Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Voltages – supply pins
Supply voltage VS
VS
-0.3
-0.3
-2.8
–
–
–
40
48
48
V
V
V
Load dump
–
P_1.1.1
P_1.1.2
P_1.1.32
Supply voltage VSD
Supply voltage VSD
VSD
VSD_max_extend
Series resistor
R
VSD = 2.2 Ω, t = 8 ms 2)
Voltage range VDDP
Voltage range VDDP
VDDP
-0.3
–
–
5.5
7
V
V
–
P_1.1.3
VDDP_max_extend -0.3
In case of voltage
transients on VS with
∆VS/∆t ≥ 1 V/µs;
P_1.1.41
duration: t ≤ 150 µs;
C
VDDP ≤ 570 nF
Voltage range VDDEXT
Voltage range VDDEXT
VDDEXT
-0.3
–
–
5.5
7
V
V
–
P_1.1.4
VDDEXT_max_extend -0.3
In case of voltage
transients on VS with
∆VS/∆t ≥ 1 V/µs;
P_1.1.42
duration: t ≤ 150 µs;
C
VDDEXT ≤ 570 nF
Voltage range VDDC
VDDC
-0.3
–
1.6
V
–
P_1.1.5
Voltages – high-voltage pins
Input voltage at LIN
VLIN
-28
–
–
–
–
–
–
–
–
–
40
40
40
48
14
48
48
48
14
V
V
V
V
V
V
V
V
V
–
P_1.1.7
3)
Input voltage at MON
Input voltage at VDH
Voltage range at GHx
VMON_maxrate
VVDH_maxrate
VGH
-28
P_1.1.8
4)
5)
-2.8
-8.0
-0.3
-8.0
-8.0
-8.0
-0.3
P_1.1.38
P_1.1.9
Voltage range at GHx vs. SHx VGHvsSH
–
–
P_1.1.44
P_1.1.11
P_1.1.48
P_1.1.13
P_1.1.45
Voltage range at SHx
Voltage range at SLx
Voltage range at GLx
Voltage range at GLx vs. SL
VSH
VSL
–
6)
VGL
VGLvsSL
–
Datasheet
84
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 16
Absolute maximum ratings1) (cont’d)
Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
7)
Voltage range at charge pump VCPx
pins CP1H, CP1L, CP2H, CP2L,
VCP
-0.3
–
48
V
P_1.1.15
Voltages – GPIOs
Voltage on any port pin8)
9)
Vin
-0.3
-15
–
–
VDDP
+0.3
V
V
< VDDPmax
P_1.1.16
P_1.1.35
IN
Current at VCP pin
Max. current at VCP pin
Injection current at GPIOs
IVCP
–
mA
–
10)
10)
10)
Injection current on any port IGPIONM
pin
-5
–
–
5
mA
mA
µA
P_1.1.34
P_1.1.30
P_1.1.36
Sum of all injected currents in IGPIOAM_sum
Normal mode
-50
50
50
Sum of all injected currents in IGPIOPD_sum
Power-down mode (Stop
mode)
-5000 –
10)
Sum of all injected currents in IGPIOSleep_sum
-5
–
5
mA
P_1.1.37
Sleep mode
Other voltages
Input voltage VAREF
VAREF
VOAI
-0.3
-7
–
–
VDDP
+0.3
V
V
–
–
P_1.1.17
P_1.1.23
Input voltage
OP1, OP2
7
Temperatures
Junction temperature
Storage temperature
ESD susceptibility
Tj
-40
-55
–
–
175
150
°C
°C
–
–
P_1.1.18
P_1.1.19
Tstg
ESD susceptibility
all pins
VESD1
-2
–
–
–
–
–
2
kV
kV
kV
V
HBM 11)
HBM 12)
P_1.1.20
P_1.1.21
P_1.1.22
P_1.1.28
P_1.1.43
ESD susceptibility
pins MON, VS, VSD vs.GND
VESD2
-4
4
ESD susceptibility
pins LIN vs. GND_LIN
VESD3
-6
6
HBM 11)
13)
ESD susceptibility CDM
all pins vs. GND
VESD_CDM1
VESD_CDM2
-500
-750
500
750
13)
ESD susceptibility CDM
pins 1, 12, 13, 24, 25, 36, 37, 48
(corner pins) vs. GND
V
Datasheet
85
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
1) Not subject to production test, specified by design.
2) Conditions and minimum values are derived from application conditions for reverse polarity events.
3) The minimum voltage of -28 V applies only with an external 3.9 kΩ series resistor.
4) The minimum voltage of -2.8 V applies only with an external 1 kΩ series resistor.
5) To achieve the maximum ratings on this pin, the following relationships with parameter P_1.1.44 have to be
observed: VGH < VSH + VGHvsSH_min and VSH < VGH + 0.3 V.
6) To achieve the maximum ratings on this pin, the following relationships with parameter P_1.1.45 have to be
observed: VGL < VSL + VGLvsSL_min and VSL < VGL + 0.3 V.
7) These limits can be kept if the maximum current drawn out of the pin does not exceed the limit of 200 µA.
8) See the XTAL parameter specification, when GPIOs (Port pins P2.0 and P2.2) are used as XTAL.
9) Includes TMS and RESET.
10) P_1.1.16 must not been exceeded in the injection current.
11) ESD susceptibility based on the HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).
12) MON with external circuitry of a series resistor with 3.9 kΩ and 10 nF (at connector); VS with an external ceramic
capacitor with 100 nF; VSD with an external capacitor with 470 nF; VDH with external circuitry of a series resistor with
1 kΩ and 3.3 nF (at pin).
13) ESD susceptibility based on the HBM according to ANSI/ESDA/JEDEC JESD22-C101F.
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect the reliability of the device.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered to be outside the normal operating range. Protection functions
are not designed for continuous repetitive operation.
Datasheet
86
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.1.2
Functional range
Table 17
Functional range
Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply voltage in Active mode
VS_AM
5.5
–
–
28
40
V
V
–
P_1.2.1
Extended supply voltage in Active VS_AM_extend 28
mode
1)2) Extended supply P_1.2.16
range leads to
parameter deviation.
Supply voltage in Active mode for VSD_AM
MOSFET driver supply
5.4
–
–
28
32
V
V
–
P_1.2.18
Extended supply voltage in Active VSD_AM_extend 28
mode for MOSFET driver supply
1)2)5) Extended supply P_1.2.17
range leads to
parameter deviation.
Specified supply voltage for LIN
transceiver
VS_AM_LIN
VS_AM_LIN
5.5
4.8
–
–
18
28
V
V
Parameter
specification.
3) Extended supply
range leads to
parameter deviation.
4)
P_1.2.2
Extended supply voltage for LIN
transceiver
P_1.2.14
Supply voltage in Active mode with VS_AMmin
reduced functionality (retaining full
operation for microcontroller and
flash)
3.0
–
5.5
V
P_1.2.3
Supply voltage in Sleep mode
VS_Sleep
3.0
-1
–
–
–
28
1
V
–
P_1.2.4
P_1.2.5
P_1.2.7
5)
Supply voltage transients slew rate ∆VS/∆t
V/µs
mA
5)
Output sum current for all GPIO
pins
IGPIO,sum
-50
50
Junction temperature range 1
Junction temperature range 2
Tj_extend_1
Tj_extend_2
-40
-40
–
–
150
165
°C
°C
–
P_1.2.22
P_1.2.23
5) Incl. flash
read/write/erase
Junction temperature range 3
Tj_extend_3
165
–
175
°C
5) Incl. flash read
P_1.2.24
1) This operation voltage range is only allowed for a short duration: tmax ≤ 400 ms (continuous operation at this voltage
is not allowed), fsys = 24 MHz, IVDDP = 10 mA, IVDDEXT = 5 mA. In addition, the power dissipation caused by the charge
pump and the MOSFET driver has to be considered. Charge pump and MOSFET driver operation above the specified
voltage range is not allowed.
2) Parameter deviations mean that the electrical parameters of the device may present values outside the range
specified within the minimum and maximum values.
3) Parameter deviations mean that the electrical parameters of the device may present values outside the range
specified within the minimum and maximum values.
4) Functionality is reduced (for example, cranking pulse); parameter deviations are possible: The electrical parameters
of the device may present values outside the range specified within the minimum and maximum values.
5) Not subject to production test, specified by design.
Datasheet
87
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.1.3
Current consumption
Table 18
Electrical characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Current consumption at VS pin
Currentconsumptionin IVs
Active mode at VS pin
–
30
35
mA fsys = 20 MHz
No loads on pins,
P_1.3.1
LIN in recessive state 1)
Currentconsumptionin IVSD
Active mode at VSD pin
–
–
–
–
40
35
mA 20 kHz
P_1.3.8
PWM on bridge driver
Currentconsumptionin ISDM_3P
mA fsys = 5 MHz;
P_1.3.19
Slow-down mode
LIN communication running;
charge pump on (reverse polarity
FET on), external low-side FET
static on (Motor Break mode);
VDDEXT on; all other modules set
to power down;
VS = 13.5 V
Currentconsumptionin ISleep
Sleep mode
–
–
–
30
90
35
µA System in Sleep mode,
microcontroller not powered,
wake-capable via LIN and MON;
MON connected to VS or GND;
GPIOs open (no loads) or
connected to GND:
P_1.3.3
-40°C ≤ Tj ≤ 85°C;
VS = 5.5 V to 18 V 2)
Currentconsumptionin ISleep_extend_1
Sleep mode, extended
temperature 1
200 µA System in Sleep mode,
microcontroller not powered,
wake-capable via LIN and MON;
MON connected to VS or GND;
GPIOs open (no loads) or
connected to GND:
P_1.3.15
P_1.3.16
-40°C ≤ Tj ≤ 150°C;
VS = 5.5 V to 18 V 2)
Currentconsumptionin ISleep_extend_2
Sleep mode, extended
temperature 2
300 500 µA System in Sleep mode,
microcontroller not powered,
wake-capable via LIN and MON;
MON connected to VS or GND;
GPIOs open (no loads) or
connected to GND:
150°C ≤ Tj ≤ 175°C;
VS = 5.5 V to 18 V 2)
Datasheet
88
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 18
Electrical characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Currentconsumptionin ISleep
Sleep mode
–
–
33
µA System in Sleep mode,
microcontroller not powered,
wake-capable via LIN and MON;
MON connected to VS or GND;
GPIOs open (no loads) or
connected to GND:
P_1.3.9
-40°C ≤ Tj ≤ 40°C;
VS = 5.5 V to 18 V 2)
Currentconsumptionin ICyclic
Sleep mode with cyclic
wake
–
–
–
–
–
110 µA -40°C ≤ Tj ≤ 85°C;
VS = 5.5 V to 18 V;
P_1.3.4
t
Cyclic_ON = 4 ms;
tCyclic_OFF = 2048 ms 2)
Currentconsumptionin ICyclic_extend
Sleep mode with cyclic
wake, extended
600 µA -40°C ≤ Tj ≤ 175°C;
VS = 5.5 V to 18 V;
P_1.3.18
P_1.3.10
t
t
Cyclic_ON = 4 ms;
temperature range
Cyclic_OFF = 2048 ms 2)
Currentconsumptionin IStop
Stop mode
110 160 µA System in Stop mode,
microcontroller not clocked,
wake-capable via LIN and MON;
MON connected to VS or GND;
GPIOs open (no loads) or
connected to GND;
-40°C ≤ Tj ≤ 85°C;
VS = 5.5 V to 18 V
Currentconsumptionin IStop_extend
Stop mode, extended
temperature range 1
–
600 1800 µA System in Stop mode,
microcontroller not clocked,
wake-capable via LIN and MON;
MON connected to VS or GND;
GPIOs open (no loads) or
connected to GND;
P_1.3.20
-40°C ≤ Tj ≤ 150°C;
VS = 5.5 V to 18 V
1) Current on VS, ADC1/2 active, timer running, LIN active (recessive).
2) Incl. leakage currents from VDH, VSD and MON.
Note:
Within the functional range, the IC operates as described in the circuit description. The electrical
characteristics are specified under the conditions noted in the related electrical characteristics
table.
Datasheet
89
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.1.4
Thermal resistance
Table 19
Thermal resistance
Parameter
Symbol
Values
Typ.
6
Unit Note or
Test Condition
Number
Min.
Max.
Junction to soldering point
RthJSP
–
–
K/W 1) Measured to
exposed pad
P_1.4.1
1)2)
Junction to ambient
Junction to top
RthJA
–
–
33
8
–
–
K/W
P_1.4.2
P_1.4.3
1)2)
ΨJTOP 2s2p
K/W
1) Not subject to production test, specified by design.
2) According to Jedec JESD51-2,-5,-7 with natural convection on an FR4 2s2p board. Board: 76.2 × 114.3 × 1.5 mm3 with
two inner copper layers (35 µm strong), with thermal dissipation via array under the exposed pad contacting the first
inner copper layer and 300 mm2 of cooling area on the bottom layer (70 µm).
29.1.5
Timing characteristics
The transition times between the system modes are specified here. Generally, the timings are defined from the
time when the corresponding bits in register PMCON0 are set until the sequence is terminated.
Table 20
System timing1)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Wake-up time when
running on battery
tstart
–
–
3
ms
ms
Battery ramp-up time until
the start of code execution
P_1.5.6
P_1.5.1
Wake-up time when
running on battery
tstartSW
–
–
1.5
Battery ramp-up time until
the MCU reset is released;
VS > 3 V and RESET = 1
Time to exit sleep
tsleep - exit
–
–
–
–
1.5
ms
Rising/falling edge of any
wake-up signal (LIN, MON)
until the MCU reset is
released
P_1.5.2
P_1.5.3
2)
Time to enter sleep
tsleep -
330
µs
entry
1) Not subject to production test, specified by design.
2) Wake events during sleep entry are stored and lead to wake-up after Sleep mode is reached.
Datasheet
90
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.2
Power management unit (PMU)
This chapter includes all electrical characteristics of the power management unit.
29.2.1
PMU I/O supply (VDDP) parameters
This chapter describes electrical parameters which are observable on the SoC level. The pad-supply VDDP and
the transition times between the system modes are specified in the following table.
Table 21
Electrical characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
1)
Specified output current
Specified output current
IVDDP
0
–
–
–
50
30
2.2
mA
mA
P_2.1.1
P_2.1.22
P_2.1.2
1)2)
IVDDP
0
Required decoupling
capacitance
CVDDP1
0.47
µF 3)4)5) ESR < 1 Ω
3)4)5)
Required buffer capacitance CVDDP2
for stability (load jumps)
1
–
2.2
5.1
µF
P_2.1.20
P_2.1.3
6)
Output voltage including line VDDPOUT
and load regulation in Active
mode
4.9
5.0
V
V
V
V
I
< 90 mA;
load
VS > 5.5 V
2)6)
Output voltage including line VDDPOUT
and load regulation in Active
mode
4.9
4.5
5.0
5.0
5.0
5.1
5.5
5.8
I
< 70 mA;
P_2.1.23
P_2.1.21
P_2.1.29
load
VS > 5.5 V
6)
Output voltage including line VDDPOUTSTOP
and load regulation in Stop
mode
I
is only internal;
load
VS > 5.5 V;
-40°C ≤ Tj ≤ -150°C
6)
Output voltage including line VDDPOUTSTOP_HT 3.5
and load regulation in Stop
mode, extended temperature
range
I
is only internal;
load
VS > 5.5 V;
150°C < Tj ≤ 175°C
Output drop in Active mode
VSVDDPout
–
50
–
400 mV IVDDP = 30 mA7);
3.5 V < VS < 5.0 V
P_2.1.4
P_2.1.5
Load regulation in Active
mode
VVDDPLOR
-50
50
mV 2 mA … 90 mA;
C = 570 nF;
-40°C < Tj ≤ 150°C
Load regulation in Active
mode, extended temperature
range
VVDDPLOR_HT
-70
–
70
mV 2 mA … 90 mA;
C = 570 nF;
P_2.1.30
150°C < Tj ≤ 175°C
Line regulation in Active mode VVDDPLIR
-50
–
–
50
mV VS = 5.5 V … 28 V
P_2.1.6
P_2.1.7
Overvoltage detection
VDDPOV
5.14
5.4
V
VS > 5.5 V;
Overvoltage leads to
SUPPLY_NMI
Datasheet
91
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 21
Electrical characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
3)8)
Overvoltage detection filter
time
tFILT_VDDPOV
VDDPOK
–
735
–
µs
V
P_2.1.24
P_2.1.25
P_2.1.26
3)
3)
Voltage OK detection
threshold
–
3
–
Voltage stable detection
range9)
∆VDDPSTB
-220
–
220 mV
Undervoltage reset
VDDPUV
IVDDPOC
2.5
91
–
2.6
–
2.7
V
–
P_2.1.8
P_2.1.9
P_2.1.27
Overcurrent diagnostic
220 mA
–
3)8)
Overcurrent diagnostic filter tFILT_VDDPOC
time
27
–
–
µs
µs
3)8)10)
Overcurrent diagnostic
shutdown time
tFILT_VDDPOC_SD
–
100
P_2.1.28
1) Specified output current for port supply and additional other external loads, already excluding VDDC current.
2) This use case applies when the output current on VDDEXT does not exceed 40 mA.
3) Not subject to production test, specified by design.
4) Ceramic capacitor.
5) Ranges of P_2.1.2 and P_2.1.20 can be added to one ceramic capacitor with ESR < 1 Ω.
6) Load current includes internal supply.
7) Output drop for IVDDP without internal supply current.
8) This filter time is derived from the time base tLP_CLK = 1 / fLP_CLK
9) The absolute voltage value is the sum of parameters VDDP + ∆VDDPSTB
10) When tFILT_VDDCOC_SD is passed and the overcurrent condition is still present, the device will enter Sleep mode.
.
.
Datasheet
92
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.2.2
PMU core supply (VDDC) parameters
This chapter describes electrical parameters which are observable on the SoC level. The core-supply VDDC
and the transition times between the system modes are specified in the following table.
Table 22
Electrical characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Required decoupling capacitance CVDDC1
0.1
–
–
1
1
µF
µF
1)2)3) ESR < 1 Ω
2)3)
P_2.2.1
Required buffer capacitance for CVDDC2
0.33
P_2.2.17
stability (load jumps)
Output voltage including line
regulation in Active mode
VDDCOUT
1.44 1.5 1.56
V
V
Iload < 40 mA
P_2.2.2
Reduced output voltage
including line regulation in Stop
mode
VDDCOUT_Stop_Red 0.95 1.1 1.3
With internal VDDC P_2.2.23
load only:
Iload_internal < 1.5 mA
Load regulation in Active mode VDDCLOR
-50
-25
–
–
50
25
mV 2 mA … 40 mA;
P_2.2.3
C = 430 nF
Line regulation in Active mode
Overvoltage detection
VDDCLIR
VDDCOV
mV VDDP = 2.5 V … 5.5 V P_2.2.4
1.59 1.62 1.68
V
Overvoltageleadsto P_2.2.5
SUPPLY_NMI
1)4)
Overvoltage detection filter time tFILT_VDDCOV
Voltage OK detection range5)
∆VDDCOK
Voltage stable detection range6) ∆VDDCSTB
–
735
–
–
µs
P_2.2.18
1)
-280
-110
280 mV
110 mV
P_2.2.19
1)
–
P_2.2.20
Undervoltage reset
VDDVUV
IVDDCOC
1.136 1.20 1.264 V
–
P_2.2.6
P_2.2.7
P_2.2.21
P_2.2.22
Overcurrent diagnostic
45
–
–
100 mA
–
1)4)
Overcurrent diagnostic filter time tFILT_VDDCOC
27
290
–
–
µs
µs
1)4)7)
Overcurrent diagnostic
shutdown time
tFILT_VDDCOC_SD
–
1) Not subject to production test, specified by design.
2) Ceramic capacitor.
3) Ranges of P_2.2.1 and P_2.2.17 can be added to one ceramic capacitor with ESR < 1 Ω.
4) This filter time is derived from the time base tLP_CLK = 1 / fLP_CLK
5) This absolute voltage value is the sum of parameters VDDC + ∆VDDCSTB
6) This absolute voltage value is the sum of parameters VDDC + ∆VDDCOK
7) When tFILT_VDDCOC_SD is passed and the overcurrent condition is still present the device will enter Sleep mode.
.
.
.
Datasheet
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Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.2.3
VDDEXT voltage regulator (5.0 V) parameters
Table 23
Electrical characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Specified output current
Specified output current
IVDDEXT
IVDDEXT
CVDDEXT1
0
–
–
–
20
40
2.2
mA
mA
µF
–
P_2.3.1
1)
0
P_2.3.21
P_2.3.22
Required decoupling
capacitance
0.1
2)3)4) ESR < 1 Ω
2)3)4)
Required buffer capacitance for CVDDEXT2
stability (load jumps)
1
–
2.2
5.1
5.2
µF
V
P_2.3.20
P_2.3.3
P_2.3.23
P_2.3.4
P_2.3.14
P_2.3.5
4)
Output voltage including line
and load regulation
VDDEXT
4.9 5.0
I
< 20 mA;
load
VS > 5.5 V
Output voltage including line
and load regulation
VDDEXT
4.8 5.0
V
Iload < 40 mA;
VS > 5.5 V
4)
Output drop in Active mode
VS-VDDEXT
VS-VDDEXT
50
–
300 mV
I
< 20 mA;
load
3 V < VS < 5.0 V
Output drop in Active mode
400 mV Iload < 40 mA;
3 V < VS < 5.0 V
Load regulation in Active mode VDDEXTLOR
Line regulation in Active mode VVDDEXTLIR
-50
–
50
mV 2 mA … 40 mA;
C = 200 nF
-50
50
–
–
50
–
mV VS = 5.5 V … 28 V
P_2.3.6
P_2.3.7
Power supply ripple rejection in PSSRVDDEXT
Active mode
dB
4) VS = 13.5 V;
f = 0 kHz … 1 kHz;
Vr = 2 Vpp
Overvoltage detection
VVDDEXTOV
5.18
–
–
5.4
–
V
VS > 5.5 V
P_2.3.8
4)5)
Overvoltage detection filter time tFILT_VDDEXTOV
Voltage OK detection threshold VVDDEXTOK
Voltage stable detection range6) ∆VVDDEXTSTB
735
3
µs
V
P_2.3.24
P_2.3.25
P_2.3.26
P_2.3.9
4)
4)
7)
–
–
-220
–
220 mV
3.0
160 mA
Undervoltage trigger
VVDDEXTUV
2.6 2.8
V
Overcurrent diagnostic
IVDDEXTOC
50
–
–
–
4)5)
P_2.3.10
P_2.3.27
Overcurrent diagnostic filter
time
tFILT_VDDEXTOC
27
–
µs
4)5)
Overcurrent diagnostic
shutdown time
tFILT_VDDEXTOC_SD
–
100
–
µs
P_2.3.28
1) This use case requires the reduced utilization of VDDP output current by 20 mA, see P_2.1.22.
2) Ceramic capacitor.
3) Ranges of P_2.3.22 and P_2.3.20 can be added to one ceramic capacitor with ESR < 1 Ω.
4) Not subject to production test, specified by design.
5) This filter time is derived from the time base tLP_CLK = 1 / fLP_CLK
6) The absolute voltage value is the sum of parameters VDDEXT + ∆VDDEXTSTB
7) When the undervoltage condition is met, the VDDEXT_CTRL.bit.SHORT bit is set.
.
.
Datasheet
94
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.2.4
VPRE voltage regulator (PMU subblock) parameters
The PMU VPRE regulator acts as a supply for the VDDP and VDDEXT voltage regulators.
Table 24
Functional range
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
1)
Specified output current
IVPRE
–
–
110
mA
P_2.4.1
1) Not subject to production test, specified by design.
29.2.4.1 Load-sharing scenario for the VPRE regulator
The figure below shows the load-sharing scenario for VPRE regulator.
VS
VPRE
VDDEXT
VDDP
VDDC
VDDEXT
5 V
VDDP
5 V
CVDDEXT
CVDDP
GND (pin 39)
GND (pin 39)
VDDC
1.5 V
CVDDC
GND (pin 39)
Figure 32 Load-sharing scenario for the VPRE regulator
Datasheet
95
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.2.5
Power-down voltage regulator (PMU subblock) parameters
The PMU power-down voltage regulator consists of two subblocks:
•
•
Power-down preregulator: VDD5VPD
Power-down core regulator: VDD1V5_PD (Supply used for the GPUDATAxy registers)
Both regulators are used as purely internal supplies. The following table contains all relevant parameters.
Table 25
Functional range
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
VDD1V5_PD
1)
Power-on reset threshold
VDD1V5_PD_RSTTH 1.2
–
1.5
V
P_2.5.1
1) Not subject to production test, specified by design.
Datasheet
96
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.3
System clocks
29.3.1
Parameters of oscillators and PLLs
Table 26
Electrical characteristics of the system clocks
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min.
PMU oscillators (power management unit)
Typ. Max.
Frequency of LP_CLK fLP_CLK
14
18
22
MHz This clock is used during
startup and can be used
when the PLL fails.
P_3.1.1
Frequency of LP_CLK2 fLP_CLK2
70
100
130
kHz This clock is used for cyclic P_3.1.2
wakes.
CGU oscillator (clock generation unit microcontroller)
Short-term frequency fTRIMST
-0.4
–
0.4
%
2)3) Within any 10 ms, e.g., P_3.1.3
after synchronization to a
LIN frame. (The PLL
deviation1)
settings must not change
in these 10 ms.)
Absolute accuracy
fTRIMABSA
-1.5
–
–
–
1.5
2.0
10
%
%
µs
Including temperature and P_3.1.4
lifetime deviation;
-40°C ≤ Tj ≤ 150°C
Absolute accuracy,
extended temperature
range
fTRIMABSA_HT -2.0
Including temperature and P_3.1.18
lifetime deviation;
150°C ≤ Tj ≤ 175°C
3) Start-up time OSC from P_3.1.5
Sleep mode, power supply
stable
CGU-OSC start-up time tOSC
–
PLL (clock generation unit microcontroller) 3)
VCO frequency range fVCO-0
mode 0
48
–
112
160
MHz VCOSEL = ”0”
MHz VCOSEL = ”1”
P_3.1.6
P_3.1.7
VCO frequency range fVCO-1
96
–
mode 1
Input frequency range fOSC
4
4
–
–
16
16
MHz
MHz
–
–
P_3.1.8
P_3.1.9
XTAL1 input frequency fOSC
range
Output frequency
range
fPLL
0.04687 –
80
38
MHz
–
P_3.1.10
P_3.1.11
Free-running
fVCOfree_0
–
–
MHz VCOSEL = ”0”
frequency mode 0
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TLE9872QTW40
Electrical characteristics
Table 26
Electrical characteristics of the system clocks (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min.
Typ. Max.
Free-running
frequency mode 1
fVCOfree_1
thigh/low
–
–
76
MHz VCOSEL = ”1”
P_3.1.12
P_3.1.13
Input clock high/low
time
10
–
–
ns
–
Peak period jitter
Accumulated jitter
Lock-in time
tjp
-500
–
–
–
500
5
ps
ns
µs
4) for K = 1
4) for K = 1
–
P_3.1.14
P_3.1.15
P_3.1.16
jacc
–
tL
–
200
1) The typical oscillator frequency is 5 MHz.
2) VDDC = 1.5 V, Tj = 25°C.
3) Not subject to production test, specified by design.
4) This parameter is valid for PLL operation with an external clock source and thus reflects the real PLL performance.
29.3.2
External clock parameters XTAL1, XTAL2
Table 27
Functional range
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ. Max.
2)
Input voltage range limits VIX1_SR
-1.7 + VDDC
–
1.7
V
P_3.2.1
for signal on XTAL1
Input voltage (amplitude) VAX1_SR
on XTAL1
0.3 × VDDC
–
–
V
3) Peak-to-peak P_3.2.2
voltage
XTAL1 input current
Oscillator frequency
Oscillator frequency
IIL
–
4
4
–
–
–
±20
24
µA 0 V < VIN < VDDI
P_3.2.3
P_3.2.4
P_3.2.5
fOSC
fOSC
MHz Clock signal
16
MHz Crystal or
resonator
High time
Low time
Rise time
Fall time
t1
t2
t3
t4
6
6
–
–
–
–
8
8
–
–
8
8
ns
ns
ns
ns
–
–
–
–
P_3.2.6
P_3.2.7
P_3.2.8
P_3.2.9
1) This parameter table is not subject to production test, specified by design.
2) Overload conditions must not occur on pin XTAL1.
3) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the operation
and the resulting voltage peaks must remain within the limits defined by VIX1
.
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Electrical characteristics
29.4
Flash memory
This chapter includes the parameters for the 256 kByte embedded flash module.
29.4.1
Flash parameters
Table 28
Flash characteristics1)
VS = 3.0 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit
Note or
Number
Test Condition
Min. Typ. Max.
Programming time per 128 byte tPR
page
–
32)
3.5
ms
3) 3 V ≤ VS ≤ 28 V
P_4.1.1
P_4.1.2
Erase time per sector or page
Data retention time
tER
–
42)
–
4.5
–
ms
3) 3 V ≤ VS ≤ 28 V
tRET
20
year
1,000 erase/program P_4.1.3
cycles
Data retention time
tRET
50
–
–
year
1,000 erase/program P_4.1.9
cycles
Tj = 30°C 4)
Flash erase endurance for pages NER
in user sectors
30
10
32
–
–
–
–
–
kilocycles Data retention time P_4.1.4
5 years
Flash erase endurance for
security pages
NSEC
NDD
cycles
5) Data retention time P_4.1.5
20 years
6)
Drain disturb limit
–
–
–
kilocycles
P_4.1.6
Junction temperature range 1
Junction temperature range 2
Tj_extend_1 -40
Tj_extend_2 -40
150 °C
165 °C
–
P_4.1.10
P_4.1.11
1) Incl. flash
erase/write/read
Junction temperature range 3
Tj_extend_3 165
–
175 °C
1) Incl. flash read
P_4.1.12
1) Not subject to production test, specified by design.
2) Programming and erase times depend on the internal flash clock source. The control state machine needs a few
system clock cycles. The requirement is only relevant for extremely low system frequencies.
3) While the flash memory is being programmed or erased, flash read operation is not possible to be performed.
4) Determined by extrapolating of lifetime tests.
5) Tj = 25°C.
6) This parameter limits the number of subsequent programming operations within a physical sector without a given
page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly.
For normal sector erase/program cycles, this limit will not be violated. For data sectors, the integrated EEPROM
emulation firmware routines handle this limit automatically. For wordline erases in code sectors (without EEPROM
emulation), it is recommended to execute a software-based refresh, which use of the integrated NVMBRNG random
number generator to statistically start a refresh.
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Electrical characteristics
29.5
Parallel ports (GPIO)
29.5.1
Description of the keep and force currents
VDDP
keeper
current
PU device
PUDSEL
P1.x
P0.x
\PUDSEL
keeper
current
PD device
VSS
Figure 33 Pull-up/down device
U
GPIO
Logical 1
Undefined
Logical 0
7.5 kΩ (equivalent)
(1.5 V / 200 μA)
VIH - VDDP
VIL - VDDP
2.33 kΩ (equivalent)
(3.5 V / 1.5 mA)
I
-IPLF
-IPLK
Figure 34 Pull-up keep and force currents
U
GPIO
Logical 1
Undefined
Logical 0
2.33 kΩ (equivalent)
VIH
VIL
(3.5 V / 1.5 mA)
7.5 kΩ (equivalent)
(1.5 V / 200 μA)
I
IPLK
IPLF
Figure 35 Pull-down keep and force currents
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Electrical characteristics
29.5.2
DC parameters of port 0, port 1, TMS, and reset
Note:
Operating conditions apply.
Keeping signal levels within the limits specified in this table ensures operation without overload
conditions. For signal levels outside these specifications, also refer to the specification of the
maximum allowed current that can be taken out of VDDP.
Table 29
Current limits for port output drivers1)
Port output driver mode Maximum output current
Maximum output current
Number
(IOLmax, - IOHmax)
(IOLnom, - IOHnom)
VDDP ≥ 4.5 V 2.6 V < VDDP < 4.5 V VDDP ≥ 4.5 V 2.6 V < VDDP < 4.5 V
Strong driver2)
Medium driver3)
Weak driver3)
5 mA
3 mA
1.6 mA
1.0 mA
0.25 mA
1.0 mA
0.8 mA
0.15 mA
P_5.1.15
P_5.1.1
P_5.1.2
3 mA
1.8 mA
0.3 mA
0.5 mA
1) Not subject to production test, specified by design.
2) Not available for port pins P0.4, P1.0, P1.1, and P1.2.
3) All P0.x and P1.x pins.
Table 30
DC characteristics of port0 and port1
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Input hysteresis
HYSP0_P1
0.11 × VDDP
–
–
V
1) Series
P_5.1.5
resistance = 0 Ω;
4.5 V ≤ VDDP ≤ 5.5 V
Input hysteresis
HYSP0_P1_exend
–
0.09 × VDDP
–
V
1) Series
P_5.1.16
resistance = 0 Ω;
2.6 V ≤ VDDP ≤ 4.5 V
Input low voltage
Input low voltage
Input high voltage
Input high voltage
Output low voltage
Output low voltage
VIL
-0.3
–
0.3 × VDDP
V
V
2) 4.5 V ≤ VDDP ≤ 5.5 V P_5.1.3
1) 2.6 V ≤ VDDP ≤ 4.5 V P_5.1.17
2) 4.5 V ≤ VDDP ≤ 5.5 V P_5.1.4
VIL_extend
VIH
VIH_extend
VOL
-0.3
0.42 × VDDP
–
0.7 × VDDP
–
VDDP + 0.3 V
–
0.52 × VDDP VDDP + 0.3 V
1) 2.6 V ≤ VDDP ≤ 4.5 V P_5.1.18
3)4)
–
–
–
–
–
–
1.0
0.4
–
V
V
V
V
I
I
I
I
≤ IOLmax
≤ IOLnom
≥ IOHmax
≥ IOHnom
P_5.1.6
P_5.1.7
P_5.1.8
P_5.1.9
P_5.1.20
OL
OL
OH
OH
3)5)
3)4)
3)5)
VOL
–
Output high voltage VOH
Output high voltage VOH
Input leakage current IOZ_extend1
VDDP - 1.0
VDDP - 0.4
-500
–
500
nA -40°C ≤ Tj ≤ 25°C,
0.45 V < VIN < VDDP
Input leakage current IOZ1
-5
–
–
5
µA 6) 25°C < TJ ≤ 85°C, P_5.1.10
0.45 V < VIN < VDDP
Input leakage current IOZ_extend2
-15
15
µA 85°C < TJ ≤ 150°C, P_5.1.21
0.45 V < VIN < VDDP
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Electrical characteristics
Table 30
DC characteristics of port0 and port1 (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Input leakage current IOZ_extend3
-20
–
–
–
–
20
µA 85°C < TJ ≤ 175°C, P_5.1.11
0.45 V < VIN < VDDP
7)
Pull level keep
current
IPLK
IPLF
CIO
-200
-1.5
–
200
1.5
10
µA
mA
pF
V
≥ VIH (up)
P_5.1.12
P_5.1.13
P_5.1.14
PIN
V
PIN ≤ VIL (down)
7)
Pull level force
current
V
≤ VIL (up)
PIN
VPIN ≥ VIH (down)
1)
1)
Pin capacitance
Reset pin timing
Reset pin input filter tfilt_RESET
–
5
–
µs
P_5.1.19
time
1) Not subject to production test, specified by design.
2) Tested at VDDP = 5 V, specified for 4.5 V < VDDP < 5.5 V.
3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for
pin groups must be respected.
4) Tested at 4.9 V < VDDP < 5.1 V, IOL = 4 mA, IOH = -4 mA, specified for 4.5 V < VDDP < 5.5 V.
5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→GND, VOH→VDDP).
Tested at 4.9 V < VDDP < 5.1 V, IOL = 1 mA, IOH = -1 mA.
6) The given values are worst-case values. In production tests, this leakage current is only tested at 150°C; other values
are ensured by correlation. For derating, please refer to the following descriptions:
Leakage derating depending on temperature (TJ = junction temperature [°C]):
I
OZ = 0.05 × e(1.5 + 0.028×Tj) [µA]. For example, at a temperature of 95°C, the resulting leakage current is 3.2 µA.
Leakage derating depending on the voltage level (DV = VDDP - VPIN [V]):
OZ = IOZtempmax - (1.6 × DV) [µA]
I
This voltage derating formula is an approximation which applies for the maximum temperature.
7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the
default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the
enabled pull device: VPIN ≤ VIL for a pull-up; VPIN ≥ VIH for a pull-down.
These values apply to the fixed pull devices in dedicated pins and to the user-selectable pull devices in general-
purpose IO pins.
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Electrical characteristics
29.5.3
DC parameters of port 2
These parameters apply to the IO voltage range 4.5 V ≤ VDDP ≤ 5.5 V.
Note:
Operating conditions apply.
Keeping signal levels within the limits specified in this table ensures operation without overload
conditions. For signal levels outside these specifications, also refer to the specification of the
overload current IOV
.
Table 31
DC characteristics of port 2
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ.
Max.
0.3 × VDDP
–
Input low voltage
Input low voltage
Input high voltage
Input high voltage
Input hysteresis
VIL
-0.3
–
V
V
1) 4.5 V ≤ VDDP ≤ 5.5 V P_5.2.1
2) 2.6 V ≤ VDDP ≤ 4.5 V P_5.2.10
1) 4.5 V ≤ VDDP ≤ 5.5 V P_5.2.2
2) 2.6 V ≤ VDDP ≤ 4.5 V P_5.2.11
VIL_extend
VIH
-0.3
0.42 × VDDP
0.7 × VDDP
–
–
VDDP + 0.3 V
VIH_extend
HYSP2
0.52 × VDDP VDDP + 0.3 V
0.11 × VDDP
–
–
V
2) Series
P_5.2.3
P_5.2.12
P_5.2.4
resistance = 0 Ω;
4.5 V ≤ VDDP ≤ 5.5 V
Input hysteresis
HYSP2_extend
–
0.09 × VDDP
–
V
2) Series
resistance = 0 Ω;
2.6 V ≤ VDDP < 4.5 V
nA 3) TJ ≤ 85°C,
0 V < VIN < VDDP
nA 3) 85°C < Tj ≤ 175°C, P_5.2.14
0 V < VIN < VDDP
Input leakage current IOZ2
-400
–
–
400
Input leakage current, IOZ2_HT_P2_0 -2500
extended temperature
2500
range for port pin P2.0
Input leakage current, IOZ2_HT_P2_x -1500
extended temperature
range for all other P2.x
–
–
–
1500
30
nA 3) 85°C < Tj ≤ 175°C, P_5.2.13
0 V < VIN < VDDP
Pull-level keep current IPLK
-30
-27
µA 4) -40°C < Tj ≤ 150°C, P_5.2.5
V
PIN ≥ VIH (up)
VPIN ≤ VIL (down)
Pull-level keep current, IPLK_HT_P2
extended temperature
range
27
µA 4) 150°C<Tj ≤ 175°C, P_5.2.15
VPIN ≥ VIH (up)
V
4)
PIN ≤ VIL (down)
Pull-level force current IPLF
-750
–
–
–
750
10
µA
pF
V
≤ VIL (up)
P_5.2.6
P_5.2.7
PIN
VPIN ≥ VIH (down)
2)
Pin capacitance(digital CIO
inputs/outputs)
1) Tested at VDDP = 5 V, specified for 4.5 V < VDDP < 5.5 V.
2) Not subject to production test, specified by design.
3) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
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Electrical characteristics
4) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the
default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down.
Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the
enabled pull device: VPIN ≤ VIL for a pull-up; VPIN ≥ VIH for a pull-down.
Datasheet
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Electrical characteristics
29.6
LIN transceiver
29.6.1
Electrical characteristics
Table 32
Electrical characteristics of the LIN transceiver
Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Max.
Bus receiver interface
Receiver threshold
voltage, recessive to
dominant edge
Vth_dom 0.4 × VS 0.45 × VS 0.53 × VS
V
SAE J2602
P_6.1.1
Receiver dominant state VBUSdom -27
–
0.4 × VS
V
V
LIN spec 2.2 (par. 17)
SAE J2602
P_6.1.2
P_6.1.3
Receiver threshold
voltage, dominant to
recessive edge
Vth_rec
0.47 × VS 0.55 × VS 0.6 × VS
Receiver recessive state
Receiver center voltage
VBUSrec 0.6 × VS
–
1.15 × VS
V
V
1) LIN spec 2.2 (par. 18) P_6.1.4
2) LIN spec 2.2 (par. 19) P_6.1.5
VBUS_CNT 0.475
× VS
0.5 × VS 0.525
× VS
Receiver hysteresis
VHYS
0.07 × VS 0.12 × VS 0.175
× VS
V
V
3) LIN spec 2.2 (par. 20) P_6.1.6
Wake-up threshold
voltage
VBUS,wk 0.4 × VS 0.5 × VS 0.6 × VS
–
P_6.1.7
P_6.1.8
Dominant time for bus
wake-up (internal analog
filter delay)
tWK,bus
3
–
15
µs The overall dominant
time for bus wake-up is
the sum of tWK,bus and
the adjustable digital
filter time. The digital
filter time can be
adjusted by setting the
PMU.CNF_WAKE_FILTE
R.CNF_LIN_FT register
Bus transmitter interface
Bus recessive output
voltage
VBUS,ro 0.8 × VS
VBUS,do
–
–
VS
V
V
VTxD = high level
P_6.1.9
Bus dominant output
voltage
–
0.22 × VS
Driverdominantvoltage P_6.1.78
RL = 500 Ω
Datasheet
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Rev. 1.0
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TLE9872QTW40
Electrical characteristics
Table 32
Electrical characteristics of the LIN transceiver (cont’d)
Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Max.
Bus short circuit current
IBUS,sc
40
100
150
mA Current limitation for
driver-dominant state
driver on VBUS = 18 V;
P_6.1.10
LIN spec 2.2 (par. 12)
Bus short circuit filter time tBUS,sc
–
5
–
µs 6) The overall bus short P_6.1.71
circuit filter time is the
sum of tBUS,sc and the
digital filter time. The
digital filter time is 4 µs
(typ.)
Leakage current (loss of
ground)
IBUS_NO_ -1000
-450
1000
µA VS = 12 V;
0 V < VBUS < 18 V;
P_6.1.11
GND
LIN spec 2.2 (par. 15)
Leakage current
Leakage current
Leakage current
Bus pull-up resistance
IBUS_NO_
–
10
–
20
–
µA VS = 0 V; VBUS = 18 V;
P_6.1.12
P_6.1.13
P_6.1.14
P_6.1.15
LIN spec 2.2 (par. 16)
BAT
IBUS_PAS_ -1
mA VS = 18 V; VBUS = 0 V;
LIN spec 2.2 (par. 13)
dom
IBUS_PAS_
–
–
20
47
µA VS = 8 V; VBUS = 18 V;
LIN spec 2.2 (par. 14)
rec
RBUS
20
30
kΩ Normal mode,
LIN spec 2.2 (par. 26)
AC characteristics - transceiver Normal Slope mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
–
–
–
–
6
6
2
–
µs LIN spec 2.2 (par. 31)
µs LIN spec 2.2 (par. 31)
P_6.1.16
P_6.1.17
P_6.1.18
P_6.1.19
Propagation delay
bus recessive to RxD HIGH
td(H),R
0.1
Receiver delay symmetry tsym,R
-2
µs tsym,R = td(L),R - td(H),R;
LIN spec 2.2 (par. 32)
4) Duty cycle D1
Duty cycle D1
tduty1
0.396
Normal Slope mode
(for worst case at 20 kbit/s)
THRec(max) = 0.744 × VS;
THDom(max) = 0.581 × VS;
VS = 5.5 V … 18 V;
t
bit = 50 µs;
D1 = tbus_rec(min) / 2 tbit
;
LIN spec 2.2 (par. 27)
Datasheet
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TLE9872QTW40
Electrical characteristics
Table 32
Electrical characteristics of the LIN transceiver (cont’d)
Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Max.
Duty cycle D2
tduty2
–
–
0.581
4) Duty cycle D2
P_6.1.20
Normal Slope mode
(for worst case at 20 kbit/s)
THRec(min) = 0.422 × VS;
THDom(min) = 0.284 × VS;
VS = 5.5 V … 18 V;
t
bit = 50 µs;
D2 = tbus_rec(max) / 2 tbit
;
LIN spec 2.2 (par. 28)
AC characteristics - transceiver Low Slope mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
–
–
–
–
6
6
2
–
µs LIN spec 2.2 (par. 31)
µs LIN spec 2.2 (par. 31)
P_6.1.21
P_6.1.22
P_6.1.23
P_6.1.24
Propagation delay
bus recessive to RxD HIGH
td(H),R
0.1
Receiver delay symmetry tsym,R
-2
µs tsym,R = td(L),R - td(H),R;
LIN spec 2.2 (par. 32)
4) Duty cycle D3
THRec(max) = 0.778 × VS;
THDom(max) = 0.616 × VS;
VS = 5.5 V … 18 V;
Duty cycle D3
(for worst case at
10.4 kbit/s)
tduty1
0.417
t
bit = 96 µs;
D3 = tbus_rec(min) / 2 tbit
;
LIN spec 2.2 (par. 29)
Duty cycle D4
(for worst case at
10.4 kbit/s)
tduty2
–
–
0.590
4) Duty cycle D4
THRec(min) = 0.389 × VS;
THDom(min) = 0.251 × VS;
VS = 5.5 V … 18 V;
P_6.1.25
t
bit = 96 µs;
D4 = tbus_rec(max) / 2 tbit
;
LIN spec 2.2 (par. 30)
AC characteristics - transceiver Fast Slope mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
0.1
-1.5
–
–
–
–
6
µs
µs
–
–
P_6.1.26
P_6.1.27
P_6.1.28
P_6.1.74
Propagation delay
bus recessive to RxD HIGH
td(H),R
6
Receiver delay symmetry tsym,R
1.5
2.0
µs tsym,R = td(L),R - td(H),R
;
;
-40°C ≤ Tj ≤ 150°C
Receiver delay symmetry- tsym,R_HT -2.0
Extended temperature
range
µs tsym,R = td(L),R - td(H),R
150°C < Tj ≤ 175°C
Datasheet
107
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 32
Electrical characteristics of the LIN transceiver (cont’d)
Vs = 5.5 V to 18 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Max.
AC characteristics - Flash mode
Propagation delay
bus dominant to RxD LOW
td(L),R
0.1
0.1
–
–
6
6
µs
µs
–
–
P_6.1.31
P_6.1.32
Propagation delay
td(H),R
bus recessive to RxD HIGH
Receiver delay symmetry tsym,R
-1.0
–
–
1.5
–
µs tsym,R = td(L),R - td(H),R
P_6.1.33
P_6.1.34
Duty cycle D7 (for worst
case at 115 kbit/s)
for +1 µs receiver delay
symmetry
tduty1
0.399
5) Duty cycle D7
THRec(max) = 0.744 × VS;
THDom(max) = 0.581 × VS;
VS = 13.5 V;
t
bit = 8.7 µs;
D7 = tbus_rec(min) / 2 tbit
Duty cycle D8 (for worst
case at 115 kbit/s)
for +1 µs receiver delay
symmetry
tduty2
–
–
0.578
5) Duty cycle D8
THRec(min) = 0.422 × VS;
THDom(min) = 0.284 × VS;
VS = 13.5 V;
P_6.1.35
tbit = 8.7 µs;
D8 = tbus_rec(max) / 2 tbit
6)
LIN input capacity
CLIN_IN
ttimeout
–
6
15
12
30
20
pF
P_6.1.69
P_6.1.36
TxD dominant time out
ms VTxD = 0 V
Thermal shutdown (junction temperature)
6)
Thermal shutdown
temperature
TjSD
190
200
10
215
–
°C
P_6.1.65
P_6.1.66
6)
Thermal shutdown
hysteresis
∆T
–
K
1) Maximum limit specified by design.
2) VBUS_CNT = (Vth_dom + Vth rec)/ 2.
3) VHYS = VBUSrec - VBUSdom
.
4) Bus load concerning LIN spec 2.2:
Load 1 = 1 nF / 1 kΩ = CBUS / RBUS
Load 2 = 6.8 nF / 660 Ω = CBUS / RBUS
Load 3 = 10 nF / 500 Ω = CBUS / RBUS
5) Bus load
Load 1 = 1 nF / 500 Ω = CBUS / RBUS
.
6) Not subject to production test, specified by design.
Datasheet
108
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.7
High-speed synchronous serial interface
29.7.1
SSC timing parameters
The table below provides the SSC timing in the TLE9872QTW40.
Table 33 SSC master mode timing (operating conditions apply; CL = 50 pF)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
1) 2 × TSSC
10
Typ.
Max.
2)
2)
2)
2)
SCLK clock period
t0
t1
t2
t3
–
–
–
–
–
–
–
–
V
V
V
V
> 2.7 V
> 2.7 V
> 2.7 V
> 2.7 V
P_7.1.1
P_7.1.2
P_7.1.3
P_7.1.4
DDP
DDP
DDP
DDP
MTSR delay from SCLK
MRST setup to SCLK
MRST hold from SCLK
ns
ns
ns
10
15
1) TSSCmin = TCPU = 1/fCPU. If fCPU = 20 MHz, t0 = 100 ns. TCPU is the CPU clock period.
2) Not subject to production test, specified by design.
t0
SCLK 1)
t1
t1
MTSR 1)
MRST1)
t2
t3
Data
valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
Figure 36 SSC master mode timing
Datasheet
109
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.8
Measurement unit
29.8.1
System voltage measurement parameters
Table 34
Supply voltage signal conditioning
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Measurement output
voltage range at VAREF5
VA5
0
–
5
V
V
–
–
P_8.1.15
P_8.1.16
Measurement output
voltage range at
VAREF1V2
VA1V2
0
–
1.23
Battery/supply voltage measurement
Input-to-output voltage ATTVS_1
attenuation: VS
–
3
0.055
–
–
SFR setting 1
P_8.1.41
P_8.1.1
Nominal operating input VS,range1
voltage range VS
22
V
1) SFR setting 1;
max. value corresponds
to typ. ADC full scale
input;
3 V < VS < 28 V
Accuracy of VS after
calibration
∆VS,range1
-312
312 mV SFR setting 1,
P_8.1.83
P_8.1.42
P_8.1.40
VS = 5.5 V to 18 V
Input-to-output voltage ATTVS_2
attenuation: VS
–
3
0.039
–
–
SFR setting 2
Nominal operating input VS,range2
voltage range VS
31
V
1) SFR setting 2;
max. value corresponds
to typ. ADC full scale
input
3 V < VS < 28 V
Accuracy of VS after
∆VS,range2
-440
440 mV SFR setting 2,
P_8.1.84
calibration
VS = 5.5 V to 18 V
Drivers supply voltage measurement VSD
Input-to-output voltage ATTVSD
attenuation: VSD
–
0.039
–
–
P_8.1.21
P_8.1.2
1)
Nominal operating input VSD,range
voltage range VSD
2.5
-440
–
–
31
V
Accuracy of VSD sense
∆VSD
440 mV VS = 5.5 V to 18 V
P_8.1.47
after calibration
Charge pump voltage measurement VCP
Input-to-output voltage ATTVCP
attenuation: VCP
–
0.023
–
–
P_8.1.56
Datasheet
110
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 34
Supply voltage signal conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
1)
Nominal operating input VCP,range
voltage range VCP
2.5
–
52
V
P_8.1.7
AccuracyofVCP sense after ∆VCP
-747
–
747 mV VS = 5.5 V to 18 V
P_8.1.62
calibration
Monitoring input voltage measurement VMON
Input-to-output voltage ATTVMON
attenuation: VMON
–
0.039
–
–
P_8.1.49
P_8.1.8
1)
Nominal operating input VMON,range
voltage range VMON
2.5
-440
–
–
31
V
Accuracy of VMON sense
∆VMON
440 mV VS = 5.5 V to 18 V
P_8.1.68
after calibration
Pad supply voltage measurement VVDDP
Input-to-output voltage ATTVDDP
attenuation: VDDP
–
0.164
–
–
P_8.1.33
P_8.1.50
P_8.1.5
1)
Nominal operating input VDDP,range
voltage range VDDP
0
–
–
7.50 V
Accuracy of VDDP sense
∆VDDP_SENSE
-105
105 mV 2) VS = 5.5 V to 18 V
after calibration
10-bit ADC reference voltage measurement VAREF
Input-to-output voltage ATTVAREF
attenuation: VAREF
–
0.219
–
–
P_8.1.22
P_8.1.51
P_8.1.48
1)
Nominal operating input VAREF,range
voltage range VAREF
0
–
–
5.62
79
V
Accuracy of VAREF sense
∆VAREF
-79
mV VS = 5.5 V to 18 V
after calibration
8-bit ADC reference voltage measurement VBG
Input-to-output voltage ATTVBG
attenuation: VBG
–
0.75
–
–
–
P_8.1.57
P_8.1.52
P_8.1.73
1)
Nominal operating input VBG,range
voltage range VBG
0.8
1.64
1.18
V
Value of ADC2-VBG
measurement after
calibration
VBG_PMU
1.01 1.07
1.01 1.07
V
V
-40°C ≤ Tj ≤ 150°C
150°C < Tj ≤ 175°C
Value of ADC2-VBG
measurement after
calibration, extended
temperature range
VBG_PMU_HT
1.44
P_8.1.75
Datasheet
111
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 34
Supply voltage signal conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Core supply voltage measurement VDDC
Input-to-output voltage ATTVDDC
attenuation: VDDC
–
0.75
–
–
P_8.1.34
P_8.1.53
P_8.1.6
1)
Nominal operating input VDDC,range
voltage range VDDC
0.8
-22
–
–
1.64
22
V
Accuracy of VDDC sense
∆VDDC_SENSE
mV VS = 5.5 V to 18 V
after calibration
VDH input voltage measurement VVDH10BITADC
VDH input-to-output
voltage attenuation
ATTVDH_1
ATTVDH_2
ATTVDH_3
–
–
–
–
0.166
0.224
0.226
–
–
SFR setting 1
SFR setting 2
P_8.1.64
P_8.1.65
P_8.1.81
P_8.1.66
VDH input-to-output
voltage attenuation
–
VDH input-to-output
voltage attenuation
–
1) SFR setting 2,
-40°C ≤ Tj ≤ 85°C
Nominal operating input VVDH,range1
voltage range VVDH
30
V
V
SFR setting 1
,
attenuation range 1
Nominal operating input VVDH,range2
–
–
20
SFR setting 2
P_8.1.67
voltage range VVDH
attenuation range 2
VDH 10-bit ADC, range 1
,
V
∆VVDHADC10B
∆VVDHADC10B
-300
-800
–
–
300 mV VVDH = 5.5 V to 17.5 V,
-40°C ≤ Tj ≤ 150°C
P_8.1.39
P_8.1.77
Accuracy of VVDH-10-bit
ADC, ATTVDH_1, extended
temperature range
800 mV VVDH = 5.5 V to 17.5 V,
-40°C ≤ Tj ≤ 175°C
1)
Accuracy of VVDH 10-bit
ADC, ATTVDH_3
∆VVDHADC10B
-200
–
200 mV
V
= 5.5 V to 17.5 V,
P_8.1.80
VDH
-40°C ≤ Tj ≤ 85°C
ATTVDH_3
Accuracy of VVDH 10-bit
ADC, ATTVDH_2
∆VVDHADC10B
∆VVDHADC10B
-400
-1.5
–
–
400 mV VVDH = 5.5 V to 17.5 V,
-40°C ≤ Tj ≤ 150°C
P_8.1.71
P_8.1.78
Accuracy of VVDH 10-bit
ADC, ATTVDH_2, extended
temperature range
1.5
V
VVDH = 5.5 V to 17.5 V,
-40°C ≤ Tj ≤ 175°C
10-bit ADC measurement- Rin_VDH,measure 200 390
470 kΩ PD_N = 1 (on-state)
P_8.1.3
input resistance for VDH
Datasheet
112
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 34
Supply voltage signal conditioning (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Measurement input
leakage current for VVDH
Ileak_VDH, measure -0.05
–
2.0 µA PD_N = 0 (off-state),
P_8.1.10
P_8.1.79
-40°C ≤ Tj ≤ 150°C
Measurement input
leakage current for VVDH
extended temperature
range
Ileak_VDH,
-0.05
–
4.0 µA PD_N = 0 (off-state),
,
150°C ≤ Tj ≤ 175°C
measure_HT
1) Not subject to production test, specified by design.
2) Accuracy is valid for a calibrated device.
Datasheet
113
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.8.2
Central temperature sensor parameters
Table 35
Electrical characteristics of the temperature sensor module
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Output voltage VTEMP at
T0 = 273 K (0°C)
a
–
0.666
–
V
1) T0 = 273 K (0°C)
P_8.2.2
1)
Temperature sensitivity b
Accuracy_1
b
–
2.31
–
mV/K
°C
P_8.2.4
P_8.2.5
P_8.2.6
P_8.2.7
Acc_1
Acc_2
Acc_3
-10
-10
-5
–
–
–
10
10
5
1)2) -40°C ≤ Tj ≤ 85°C
1)2) 125°C < Tj ≤ 175°C
1)2) 85°C < Tj ≤ 125°C
Accuracy_2
°C
Accuracy_3
°C
1) Not subject to production test, specified by design.
2) Accuracy with reference to on-chip temperature calibration measurement, valid for Mode1.
Datasheet
114
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.8.3
ADC2 VBG
29.8.3.1 ADC2 reference voltage VBG
Table 36
DC specifications
VS = 3.0 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
1)
Reference voltage
VBG
1.199
1.211
1.223
V
P_8.3.1
1) Not subject to production test, specified by design.
29.8.3.2 ADC2 specifications
Table 37
DC specifications
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
8
Unit
Note or
Test Condition
Number
Min.
–
Max.
–
Resolution
RES
bit
Full
P_8.3.18
P_8.3.19
P_8.3.20
P_8.3.21
Guaranteed offset error EAOFF_8Bit
Gain error EAGain_8Bit
-2.0
-2.0
-0.8
±0.3
±0.5
±0
2.0
2.0
0.8
LSB
%FSR
LSB
Not calibrated
Not calibrated
Differential non-linearity EADNL_8Bit
Full;
(DNL)
-40°C ≤ Tj ≤ 150°C
Differential non-linearity EADNL_8Bit_HT -1.2
(DNL), extended
±0
1.2
LSB
Full;
P_8.3.28
150°C < Tj ≤ 175°C
temperature range
Integral non-linearity
(INL)
EAINL_8Bit
-1.2
±0
±0
1.2
LSB
LSB
Full;
-40°C ≤ Tj ≤ 150°C
P_8.3.22
P_8.3.29
Integral non-linearity
(INL), extended
EAINL_8Bit_HT -1.50
1.50
Full;
150°C < Tj ≤ 175°C
temperature range
Datasheet
115
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.9
ADC1 reference voltage - VAREF
29.9.1
Electrical characteristics of VAREF
Table 38
Electrical characteristics of VAREF
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Required buffer capacitance CVAREF
Reference output voltage VAREF
0.1
–
5
–
–
1
µF
V
ESR < 1 Ω
P_9.1.1
P_9.1.2
P_9.1.3
P_9.1.4
4.95
5.05
VS > 5.5 V
1)
DC supply voltage rejection DCPSRVAREF 30
–
–
dB
dB
Supply voltage ripple
rejection
ACPSRVAREF 26
1) VS = 13.5 V;
f = 0 kHz … 1 kHz;
Vr = 2 Vpp
1)
Turn-on time
tso
–
–
–
200 µs
C
= 100 nF
P_9.1.5
ext
PD_N to 99.9% of final
value
1) Input impedance in case P_9.1.20
of VAREF is applied from
external input
Input resistance at VAREF pin RIN,VAREF
100
–
kΩ
1) Not subject to production test, specified by design.
Datasheet
116
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.9.2
Electrical characteristics of the ADC1 (10-bit)
These parameters describe the conditions for optimum ADC performance.
Note:
Operating conditions apply.
Table 39
A/D converter characteristics
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit
Note or
Test Condition
Number
Min.
Max.
1)
Analog reference supply VAREF
VAGND
+ 1.0
–
–
–
–
VDDPA
+ 0.05
V
V
V
P_9.2.1
P_9.2.2
P_9.2.3
Analog reference
ground
VAGND
VAIN
VSS
- 0.05
1.5
–
2)
Analog input voltage
range
VAGND
VAREF
3)
Analog clock frequency fADCI
5
24
MHz
–
P_9.2.4
P_9.2.5
1)4)
Conversion time for
10-bit result
tC10
(13 + STC) (13 + STC) (13 + STC)
× tADCI
× tADCI
× tADCI
+ 2 × tSYS
+ 2 × tSYS + 2 × tSYS
1)
Conversion time for
8-bit result
tC8
(11 + STC) (11 + STC) (11 + STC)
–
P_9.2.6
P_9.2.7
P_9.2.8
× tADCI
+ 2 × tSYS
× tADCI
+ 2 × tSYS + 2 × tSYS
× tADCI
1)
Wake-up time from
analog power-down,
fast mode
tWAF
–
–
–
4
µs
µs
1)5)
Wake-up time from
analog power-down,
slow mode
tWAS
–
15
Total unadjusted error TUE8B
(8 bit)
-2
±1
±6
2
counts 6)7) Reference is P_9.2.9
internal VAREF
counts 8)9) Reference is P_9.2.22
Total unadjusted error TUE10B
-12
12
(10 bit)
internal VAREF
DNL error
INL error
EADNL
-3
±0.8
±0.8
3
5
counts –
P_9.2.10
P_9.2.11
EAINL_int_V -5
counts Reference is
internal VAREF
AREF
Gain error
EAGAIN_int_ -10
±0.4
10
counts Reference is
P_9.2.12
internal VAREF
VAREF
Offset error
EAOFF
CAINT
-2
–
±0.5
–
2
counts –
P_9.2.13
P_9.2.14
1)5)10)
Total capacitance
of an analog input
10
pF
1)5)10)
Switched capacitance
of an analog input
CAINS
–
–
4
pF
P_9.2.15
Datasheet
117
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 39
A/D converter characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit
Note or
Test Condition
Number
Min.
Max.
1)5)10)
1)5)10)
1)5)10)
1)5)10)
Resistance of
the analog input path
RAIN
–
–
–
–
–
2
kΩ
pF
pF
kΩ
P_9.2.16
P_9.2.17
P_9.2.18
P_9.2.19
Total capacitance
of the reference input
CAREFT
CAREFS
RAREF
–
–
–
15
7
Switched capacitance
of the reference input
Resistance of
2
the reference input path
1) Not subject to production test, specified by design.
2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion results in these cases
will be 0000H or 03FFH, respectively.
3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting.
4) This parameter includes the sample time (and the additional sample time specified by STC), the time to determine
the digital results and the time to load the result register with the conversion result.
5) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 µs.
6) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual
errors.
All error specifications are based on measurement methods standardized by IEEE 1241.2000.
7) The specified TUE is valid only if the absolute sum of input overload currents (see IOV specification) does not exceed
10 mA, and if VAREF and VAGND remain stable during the measurement time.
8) The specified TUE is valid only if the absolute sum of input overload currents (see IOV specification) does not exceed
10 mA, and if VAREF and VAGND remain stable during the measurement time.
9) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual
errors.
All error specifications are based on measurement methods standardized by IEEE 1241.2000.
10) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature,
supply voltage), typical values can be used for the calculation. At room temperature and nominal supply voltage, the
following typical values can be used:
C
AINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kΩ.
29.10
Reserved
Datasheet
118
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.11
High-voltage monitoring input
29.11.1 Electrical characteristics
Table 40
Electrical characteristics of the monitoring input
Tj = -40°C to +175°C; VS = 5.5 V to 28 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Max.
MON input pin characteristics
Wake-up/monitoring
threshold voltage
VMONth
0.4 × VS 0.5 × VS 0.675 ×
V
V
Without external serial P_11.1.1
resistor Rs
(with Rs: DV = IPD/PU × Rs)
VS
Threshold hysteresis
VMONth,hys 0.015 × 0.05 × 0.1 × VS
VS VS
In all modes; without
external serial resistor Rs
(with Rs: dV = IPD/PU × Rs);
VS = 5.5 V to 18 V
P_11.1.12
Threshold hysteresis
VMONth,hys 0.02 × 0.06 × 0.12 ×
V
In all modes; without
external serial resistor Rs
(with Rs: dV = IPD/PU × Rs);
VS = 18 V to 28 V
P_11.1.2
VS
VS
VS
Pull-up current
Pull-down current
Input leakage current
Timing
IPU, MON
IPD, MON
ILK,MON
-20
3
-10
10
–
-1
µA
µA
µA
0.6 × VS
P_11.1.3
P_11.1.4
P_11.1.5
20
2.5
0.4 × VS
1) 0 V < VMON_IN < 28 V
-2.5
Wake-up filter time
(internal analog filter
delay)
tFT,MON
–
500
–
ns
2) The overall filter time P_11.1.6
for MON wake-up is the
sum of tFT,MON and the
adjustable digital filter
time. The digital filter
time can be adjusted by
setting the
PMU.CNF_WAKE_FILTER
.CNF_MON_FT register
1) Input leakage is valid for the disabled state.
2) With pull-up, pull-down current disabled.
Datasheet
119
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.12
MOSFET driver
29.12.1 Electrical characteristics
Table 41
Electrical characteristics of the MOSFET driver
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
MOSFET driver output
Maximum total charge
driver capability
Qtot_max
–
–
–
–
100 nC
1) Due to charge pump
current capability, six
MOSFETs and additional
external capacitors with a
total charge of maximal
100 nC can be driven
P_12.1.20
simultaneously at a PWM
frequency of 25 kHz
Maximum total charge
driver capability (three-
phase PWM)
Qtot_max,20kHz
150 nC
1) Due to charge pump
current capability, six
MOSFETs and additional
external capacitors with a
total charge of maximal
150 nC can be driven
P_12.1.120
simultaneously at a PWM
frequency of 20 kHz.
V
V
SD,min ≥ 6.5 V for
GS,min ≥ 7 V
Source current - charge
current (low gate voltage)
high-side driver
ISoumax_HS
ISinkmax_HS
ISoumax_LS
ISinkmax_LS
230 345 450 mA VSD ≥ 8 V, CLoad = 10 nF,
Sou = CLoad × slew rate
(= 20% to 50% of VGHx1),
CHARGE = IDISCHG = 31(max)
230 330 450 mA VSD ≥ 8 V, CLoad = 10 nF,
Sink = CLoad × slew rate
(from 80% to 50% of VGHx1),
CHARGE = IDISCHG = 31(max)
200 295 375 mA VSD ≥ 8 V, CLoad = 10 nF,
Sou = CLoad × slew rate
P_12.1.78
P_12.1.79
P_12.1.80
P_12.1.81
I
I
Sink current - discharge
current - high-side driver
I
I
Source current - charge
current (low gate voltage)
low-side driver
I
(= 20% to 50% of VGLx1),
ICHARGE = IDISCHG = 31(max)
Sink current - discharge
current - low-side driver
200 314 375 mA VSD ≥ 8 V, CLoad = 10 nF,
ISink = CLoad × slew rate
(from 80% to 50% of VGLx1),
ICHARGE = IDISCHG = 31(max)
Datasheet
120
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 41
Electrical characteristics of the MOSFET driver (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
High-level output voltage
Gxx vs. Sxx
VGxx1
VGxx2
VGxx3
VGxx6
VGxx7
trise3_3nf
10
–
14
14
14
14
14
–
V
VSD ≥ 8 V, CLoad = 10 nF,
CP = 2.5 mA2)
P_12.1.3
I
High-level output voltage
GHx vs. SHx
8
–
V
VSD = 6.4 V1), CLoad = 10 nF, P_12.1.4
CP = 2.5 mA2)
VSD = 5.4 V, CLoad = 10 nF,
CP = 2.5 mA2)
VSD = 6.4 V1), CLoad = 10 nF, P_12.1.6
CP = 2.5 mA2)
VSD = 5.4 V, CLoad = 10 nF,
CP = 2.5 mA2)
I
High-level output voltage
GHx vs. SHx
7
–
V
P_12.1.5
I
High-level output voltage
GLx vs. GND
8
–
V
I
High-level output voltage
GLx vs. GND
7
–
V
P_12.1.7
P_12.1.8
I
1)
Rise time
Fall time
Rise time
Fall time
Rise time
Fall time
–
200
ns
C
= 3.3 nF,
Load
V
SD ≥ 8 V,
25% to 75% of VGxx1
ICHARGE = IDISCHG = 31(max)
1)
,
tfall3_3nf
trisemax
tfallmax
–
200
–
ns
C
= 3.3 nF,
P_12.1.9
Load
VSD ≥ 8 V,
75% to 25% of VGxx1
,
ICHARGE = IDISCHG = 31(max)
100 250 450 ns
100 250 450 ns
CLoad = 10 nF,
SD ≥ 8 V,
25% to 75% of VGxx1
P_12.1.57
P_12.1.58
P_12.1.14
P_12.1.15
P_12.1.35
V
,
I
CHARGE = IDISCHG = 31(max)
CLoad = 10 nF,
SD ≥ 8 V,
75% to 25% of VGxx1
V
,
ICHARGE = IDISCHG = 31(max)
1)
trisemin
1.25 2.5
1.25 2.5
5
5
µs
µs
C
= 10 nF,
Load
VSD ≥ 8 V,
25% to 75% of VGxx1
ICHARGE = IDISCHG = 3(min)
1)
,
tfallmin
C
= 10 nF,
Load
VSD ≥ 8 V,
75% to 25% of VGxx1
,
ICHARGE = IDISCHG = 3(min)
Absolute difference
between rise and fall for all
LSx
tr_f(diff)LSx
–
–
100 ns
CLoad = 10 nF,
SD ≥ 8 V,
25% to 75% of VGxx1
V
,
ICHARGE = IDISCHG = 31(max)
Datasheet
121
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 41
Electrical characteristics of the MOSFET driver (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Absolute difference
between rise and fall for all
HSx
tr_f(diff)HSx
–
–
100 ns
CLoad = 10 nF,
SD ≥ 8 V,
25% to 75% of VGxx1
P_12.1.36
V
,
ICHARGE = IDISCHG = 31(max)
1)
Resistor between GHx/GLx RGGND
and GND
30
30
40
40
50
50
kΩ
P_12.1.11
P_12.1.10
Resistor between SHx and RSHGN
GND
kΩ 1)3) This resistance is the
resistance between GHx
and GND connected
through a diode to SHx. As
a consequence, the
voltage at SHx can rise up
to 0.6 V typ. before it is
discharged through the
resistor
Low-RDSON mode
(boosted discharge mode)
RONCCP
–
–
9
9
12
Ω
Ω
VVSD = 13.5 V,
VCP = VVSD + 14.0 V;
CHARGE = IDISCHG = 31(max);
50 mA forced into Gx, Sx
grounded
P_12.1.50
P_12.1.84
V
I
-40°C ≤ Tj ≤ 150°C
Low-RDSON mode
(boosted discharge mode),
extended temperature
range
RONCCP_HT
14.5
VVSD = 13.5 V,
V
VCP = VVSD + 14.0 V;
ICHARGE = IDISCHG = 31(max);
50 mA forced into Gx, Sx
grounded
150°C < Tj ≤ 175°C
1)
Resistance between VDH
and VSD
IBSH
–
–
4
–
3
kΩ
P_12.1.24
P_12.1.37
1)
Input propagation time
(LS on)
tP(ILN)min
1.5
µs
C
= 10 nF,
Load
ICharge = 3(min),
25% of VGxx1
1)
Input propagation time
(LS off)
tP(ILF)min
tP(IHN)min
tP(IHF)min
–
–
–
1.5
1.5
1.5
3
3
3
µs
µs
µs
C
= 10 nF,
P_12.1.38
P_12.1.39
P_12.1.40
Load
IDischarge = 3(min),
75% of VGxx1
1)
Input propagation time
(HS on)
C
= 10 nF,
Load
ICharge = 3(min),
25% of VGxx1
1)
Input propagation time
(HS off)
C
= 10 nF,
Load
IDischarge = 3(min),
75% of VGxx1
Datasheet
122
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 41
Electrical characteristics of the MOSFET driver (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Input propagation time
(LS on)
tP(ILN)max
–
–
–
–
–
200 350 ns
CLoad = 10 nF,
P_12.1.26
ICharge = 31(max),
25% of VGxx1
Input propagation time
(LS off)
tP(ILF)max
tP(IHN)max
tP(IHF)max
200 300 ns
200 350 ns
200 300 ns
CLoad = 10 nF,
P_12.1.27
P_12.1.28
P_12.1.29
P_12.1.30
IDischarge = 31(max),
75% of VGxx1
Input propagation time
(HS on)
CLoad = 10 nF,
ICharge = 31(max),
25% of VGxx1
Input propagation time
(HS off)
CLoad = 10 nF,
IDischarge = 31(max),
75% of VGxx1
Absolute input propagation tPon(diff)LSx
time difference between
propagation times for all
LSx (LSx on)
–
–
–
–
100 ns
100 ns
100 ns
100 ns
CLoad = 10 nF,
ICharge = 31(max),
25% of VGxx1
Absolute input propagation tPoff(diff)LSx
time difference between
propagation times for all
LSx (LSx off)
–
–
–
CLoad = 10 nF,
P_12.1.41
P_12.1.42
P_12.1.43
IDischarge = 31(max),
75% of VGxx1
Absolute input propagation tPon(diff)HSx
time difference between
propagation times for all
HSx (HSx on)
CLoad = 10 nF,
ICharge = 31(max),
25% of VGxx1
Absolute input propagation tPoff(diff)HSx
time difference between
propagation times for all
HSx (HSx off)
CLoad = 10 nF,
IDischarge = 31(max),
75% of VGxx1
Drain source monitoring
Drain source monitoring
threshold
VDSMONVTH
–
–
–
V
DRV_CTRL3.DSMONVTH<2 P_12.1.46
:0> xxx
000
001
010
011
100
101
110
111
0.07 0.25 0.40
0.35 0.50 0.650
0.55 0.75 0.90
0.65 1.00 1.25
0.90 1.25 1.45
1.00 1.5 1.80
1.20 1.75 2.10
1.40 2.00 2.40
Datasheet
123
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 41
Electrical characteristics of the MOSFET driver (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Open load diagnostic currents
Pull-up diagnostic current IPUDiag
-220 -370 -520 µA
650 900 1100 µA
IDISCHG = 1; VSHx = 5.0 V
IDISCHG = 1; VSHx = 5.0 V
P_12.1.47
P_12.1.48
Pull-down diagnostic
current
IPDDiag
Charge pump
Output voltage
VCP vs. VSD
VCPmin1
8.5
8.4
–
–
–
–
V
V
VVSD = 5.4 V,
P_12.1.53
P_12.1.85
ICP = 5 mA,
C
CP1, CCP2 = 220 nF,
bridge driver enabled,
-40°C ≤ Tj ≤ 150°C
Output voltage
VCPmin1_HT
VVSD = 5.4 V,
VCP vs. VSD, extended
temperature range
I
C
CP = 5 mA,
CP1, CCP2 = 220 nF,
bridge driver enabled,
150°C < Tj ≤ 175°C
Regulated output voltage
VCP vs. VSD
VCP
12
10
20
14
24
60
16
40
88
V
8 V ≤ VVSD ≤ 28 V,
P_12.1.49
P_12.1.59
P_12.1.60
ICP = 10 mA,
C
CP1, CCP2 = 220 nF,
fCP = 250 kHz
Turn-on time
Rise time
tON_VCP
us
us
8 V ≤ VVSD ≤ 28 V,
1)4)
(25%) of VCP
,
C
CP1, CCP2 = 220 nF,
f
CP = 250 kHz
trise_VCP
8 V ≤ VVSD ≤ 28 V,
(25% to 75%) of VCP
CCP1, CCP2 = 220 nF,
1)5)
,
f
CP = 250 kHz
1) Not subject to production test.
2) The condition ICP = 2.5 mA emulates a BLDC Driver with 6 MOSFETs switching at 20 kHz with a CLoad = 3.3 nF. Test
condition: IGx = - 100 µA, ICHARGE = IDISCHARGE = 31(max), IDISCHARGEDIV2_N = 1 and ICHARGEDIV2_N = 1.
3) This resistance is connected through a diode between SHx and GHx to ground.
4) This time applies when the DRV_CP_CTRL_STS.bit.CP_EN bit is set.
5) This time applies when the DRV_CP_CLK_CTRL.bit.CPCLK_EN bit is set.
Datasheet
124
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
29.13
Operational amplifier
29.13.1 Electrical characteristics
Table 42
Electrical characteristics of the operational amplifier
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition Number
Min.
Max.
Differential gain
(uncalibrated)
G
Gain settings GAIN<1:0>: P_13.1.6
9.5
19
38
57
10
20
40
60
10.5
21
42
00
01
10
11
63
Differentialinputoperating VIX
voltage range OP2 - OP1
-1.5 / G –
1.5 / G
V
V
G is the gain specified
below
P_13.1.1
Operating: common mode VCM
input voltage range
(referred to GND: OP2 -
GND or OP1 - GND
-2.0
–
–
2.0
Inputcommonmodehas P_13.1.2
to be checked in
evaluation if it fits the
required range
Max. input voltage range
(referred to GND: OP_2 -
GND or OP1 - GND
VIX_max -7.0
7.0
V
Max. rating of
P_13.1.3
operational amplifier
inputs when no
measurement is
performed
Single-ended output
voltage range (linear
range)
VOUT
VZERO
- 1.5
–
–
VZERO
+ 1.5
V
1)2) Offset output voltage P_13.1.4
2 V ±1.5 V
Linearity error
EPWM
-15
15
mV
Maximum deviation
from best-fit straight line
divided by the maximum
value of the differential
output voltage range
(0.5 V - 3.5 V); this
P_13.1.5
parameter is determined
with G = 10
Linearity error
EPWM_% -1.0
–
1.0
%
Maximum deviation
from best fit straight line
divided by the maximum
value of the differential
output voltage range
(0.5 V - 3.5 V); this
P_13.1.24
parameter is determined
with G = 10
Datasheet
125
Rev. 1.0
2020-07-23
TLE9872QTW40
Electrical characteristics
Table 42
Electrical characteristics of the operational amplifier (cont’d)
VS = 5.5 V to 28 V, Tj = -40°C to +175°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified).
Parameter
Symbol
Values
Typ.
–
Unit Note or Test Condition Number
Min.
Max.
Gain drift
-1
1
%
Gain drift after
P_13.1.7
calibration with G = 10
Adjusted output offset
voltage
VOOS
-40
10
10
80
40
50
–
mV
VAIP= VAIN = 0 V and
G = 40,
-40°C < Tj ≤ 150°C
P_13.1.17
Adjusted output offset
voltage, extended
temperature range
VOOS_HT -50
mV
dB
VAIP= VAIN = 0 V and
G = 40,
150°C < Tj ≤ 175°C
P_13.1.28
P_13.1.8
DC input voltage common DC-
mode rejection ratio
58
CMRR (in dB) = -20*log
(differential mode gain /
common mode gain)
CMRR
V
CMI = -2 V … 2 V,
VAIP - VAIN= 0 V,
-40°C ≤ Tj ≤ 150°C
DC input voltage common DC-
57
80
–
dB
CMRR (in dB) = -20*log
(differential mode gain /
common mode gain)
VCMI = -2 V … 2 V,
P_13.1.27
mode rejection ratio,
extended temperature
range
CMRR_
HT
V
AIP - VAIN = 0 V,
150°C ≤ Tj ≤ 175°C
Settling time to 98%
TSET
–
1
800
1400
1.5
ns
2) Derived from 80% -
20% rise fall times for
±2 V overload condition
(3 Tau value of settling
time constant)
P_13.1.9
2)
Current sense amplifier
input resistance at OP1,
OP2
Rin_OP1_
1.25
kΩ
P_13.1.25
OP2
1) Typical VZERO = 0,4 × VAREF
.
2) Not subject to production test, specified by design.
Datasheet
126
Rev. 1.0
2020-07-23
TLE9872QTW40
Package information
30
Package information
12°
H
+0.075
-0.035
0.5
0.08
48x
C
C
12°
0.125
Seating Plane
Coplanarity
11 x 0.5 = 5.5
0.2 MIN.
0.15
0.05
0.6
0.22
M
0.08
A-B D C 48x
(1)
9
0.2 A-B D 48x
0.2 A-B D H 4x
1)
7
5
42)
D
Exposed Diepad
A
B
48
48
1
1
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Exposed pad for soldering purpose
Figure 37 Package outline TQFP-48-10 1)
Green product (RoHS-compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations, the device is available as a green product. Green products are RoHS-compliant
(i.e., Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
1) Dimensions in mm
Datasheet
127
Rev. 1.0
2020-07-23
TLE9872QTW40
Revision history
31
Revision history
Revision Date
Changes
Rev. 1.0 2020-07-23 Datasheet initial release.
Datasheet
128
Rev. 1.0
2020-07-23
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
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Edition 2020-07-23
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
Infineon Technologies Office (www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
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subject to customer's compliance with its obligations
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Microcontroller with LIN and BLDC MOSFET Driver for Automotive ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INFINEON
TLE9877QXW40
TLE9877QXW40 是TLE987x产品系列的组成部分。TLE9877QXW40是一款单芯片三相电机驱动器，集成了行业标准的Arm®Cortex®-M3内核，可实现先进的电机控制算法，如磁场定向控等制。它包括6个完全集成的NFET驱动器，经过优化，可通过6个外部电源NFET驱动3相电机，其电压泵可实现低电压操作和可编程电流以及电流斜坡控制，从而优化EMC性能。其外设集包括电流传感器、用于实现PWM控制的采集和比较单元同步的逐次逼近ADC以及16位定时器。还集成了LIN收发器，以实现与器件的通信，同时还具有大量通用I/O。它包括一个片上线性稳压器，为外部负载供电。Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INFINEON
TLE9879-2QXA40
TLE9879-2QXA40 属于 MOTIX™ TLE987x 产品系列。TLE9879-2QXA40 是单芯片三相电机驱动器，集成工业标准 Arm® Cortex™ M3 核心，支持实施磁场定向控制等高级电机控制算法。该器件包括 6 个经过优化的全集成 NFET 驱动器，通过 6 个外部功率 NFET 驱动三相电机，其电荷泵支持低电压运行，可编程电流以及电流斜率控制实现优化 EMC 行为。外设包括电流传感器、同步逐次逼近 ADC、用于 PWM 控制的捕捉和比较单元以及 16 位定时器。除 TLE987x 产品系列其他产品外，TLE9879-2QXA40 还集成两个 14 位 Sigma-Delta ADC，为外部 GMR/TMR 构建传感器接口。此外还集成 LIN 收发器，通过多个通用 I/O 支持器件通信。该器件还配备片上线性电压调节器，为外部负载供电。Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INFINEON
TLE9879QTW40
The TLE9879QTW40 is part of the TLE987x product family. The TLE9879QTW40 is a single chip 3-PhaseWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INFINEON
TLE9879QXA20
Microcontroller with LIN and BLDC MOSFET Driver for Automotive ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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INFINEON
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