TLE9879-2QXA40_技术文档

TLE9879-2QXA40

Microcontroller with LIN and BLDC MOSFET Driver

for Automotive Applications

BF-Step

Features

•

32-bit ARM Cortex M3 Core

128 KByte Flash

6 KByte RAM

On-chip OSC and PLL for clock generation

MOSFET driver including charge pump for B6-Bridge Motor Application

1 LIN 2.2 transceiver

2 differential Sigma Delta 14-bit ADC

High speed operational amplifier for motor current sensing via shunt

Single power supply from 5.5 V to 27 V

Temperature Range T_j= -40°C to +150°C

Potential applications

KL30

Computation

Reverse

Polarity

TMS

SWD

ARM®

Cortex™-M3

DMA

FLASH

SRAM

ROM

VCP

Debug

NVIC

VS

System

Timer

Motor Control

CAPCOM6

VDH/VSD

Internal

Supply

VDDP

VDDC

VDDEXT

SYSTICK

T2/T21

Diagnostic

ADC

8 Bit

B6-Bridge

External

Supply

2x WDT

T3

3~ Bridge Driver

GHx

SHx

GLx

GPT12

PLL

Fail Safe

M

N-FET

Stage

Charge

Pump

Communication

Sensor Interface

UART1

UART2

VDDEXT

Meas-ADC

Sigma Delta

ADC 14 Bit

SL

OP2

SSC1

LIN

10 Bit

LIN TRX

SSC2

Comparator

Amplifier

OP1

Input/Output

BEMF

Comparator

KL15

MON

GPIO

GPI / Analog In

5x Analog In*

RESET

10x

GPIO

ADC3_p/_n

ADC4_p/_n

*) four inputs shared with SDADC

Figure 1

TLE9879-2QXA40 simplified application diagram

Data Sheet

www.infineon.com

Rev. 1.0

2018-01-16

1

TLE9879-2QXA40

Product validation

Qualified for Automotive Applications. Product Validation according to AEC-Q100/101.

Description

Type

Package

Marking

TLE9879-2QXA40

VQFN-48-31

Data Sheet

2

Rev.1.0

2018-01-16

TLE9879-2QXA40

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3

3.1

3.2

Device Pinout and Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5

5.1

5.2

5.2.1

5.2.2

5.3

5.3.1

5.3.2

5.3.3

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PMU Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power Supply Generation Unit (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6

6.1

6.2

6.2.1

6.3

System Control Unit - Digital Modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.1

7

System Control Unit - Power Modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1

7.2

7.2.1

8

ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.1

8.2

8.2.1

9

9.1

9.2

9.2.1

9.3

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DMA Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.3.1

10

Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11

Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

NVM Module (Flash Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.1

11.2

11.2.1

11.3

Data Sheet

3

Rev. 1.0

2018-01-16

TLE9879-2QXA40

12

Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12.1

12.2

12.2.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

13

13.1

13.2

Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

14

14.1

14.2

GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TLE9879-2QXA40 Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

14.2.1

14.2.2

14.3

14.3.1

14.3.1.1

14.3.2

14.3.2.1

14.3.3

14.3.3.1

15

15.1

General Purpose Timer Units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Features Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Features Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Block Diagram GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Block Diagram GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15.1.1

15.1.2

15.2

15.2.1

15.2.2

16

Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Timer2 and Timer21 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

16.1

16.2

16.2.1

17

Timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Timer3 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

17.1

17.2

17.3

17.3.1

18

Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

18.1

18.2

18.2.1

19

UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

19.1

19.2

19.2.1

19.3

20

LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Data Sheet

4

Rev. 1.0

2018-01-16

TLE9879-2QXA40

20.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

20.2

20.2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

21

High-Speed Synchronous Serial Interface (SSC1/SSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

21.1

21.2

21.2.1

22

22.1

22.2

22.2.1

22.2.1.1

Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Block Diagram BEMF Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

23

Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Measurement Core Module Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

23.1

23.2

23.2.1

23.2.2

24

10-Bit Analog Digital Converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

24.1

24.2

24.2.1

25

14-Bit Sigma Delta ADC (ADC3 / ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Input Voltage Range of SD ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Interpretation of ADC output code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

25.1

25.2

25.2.1

25.2.2

26

High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

26.1

26.2

26.2.1

27

Bridge Driver (incl. Charge Pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

27.1

27.2

27.2.1

27.2.2

28

Current Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

28.1

28.2

28.2.1

29

29.1

29.2

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

BLDC Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

ESD Immunity According to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

30

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

30.1

General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Data Sheet

5

Rev. 1.0

2018-01-16

TLE9879-2QXA40

30.1.1

30.1.2

30.1.3

30.1.4

30.1.5

30.2

30.2.1

30.2.2

30.2.3

30.2.4

30.2.4.1

30.2.5

30.3

30.3.1

30.4

30.4.1

30.5

30.5.1

30.5.2

30.5.3

30.6

30.6.1

30.7

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

PMU I/O Supply (VDDP) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

PMU Core Supply (VDDC) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

VDDEXT Voltage Regulator (5.0V) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

VPRE Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Load Sharing Scenarios of VPRE Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Power Down Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Oscillators and PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Description of Keep and Force Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

DC Parameters of Port 0, Port 1, TMS and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

DC Parameters of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

SSC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

System Voltage Measurement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Central Temperature Sensor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

ADC2-VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

ADC2 Reference Voltage VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

ADC2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

ADC1 Reference Voltage - VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Electrical Characteristics VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Electrical Characteristics ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14-Bit Sigma Delta ADC (ADC3 / ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

High-Voltage Monitoring Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

30.7.1

30.8

30.8.1

30.8.2

30.8.3

30.8.3.1

30.8.3.2

30.9

30.9.1

30.9.2

30.10

30.10.1

30.11

30.11.1

30.12

30.12.1

30.13

30.13.1

31

32

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Data Sheet

6

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Overview

1

Overview

Summary of Features

•

32-bit ARM Cortex M3 Core

–

up to 40 MHz clock frequency

one clock per machine cycle architecture

•

On-chip memory

–

128 KByte Flash including

4 KByte EEPROM (emulated in Flash)

512 Byte 100 Time Programmable Memory (100TP)

6 KByte RAM

Boot ROM for startup firmware and Flash routines

•

On-chip OSC and PLL for clock generation

PLL loss-of-lock detection

–

•

MOSFET driver including charge pump

10 general-purpose I/O Ports (GPIO)

5 analog inputs, 10-bit A/D Converter (ADC1)

2 differential Sigma Delta 14-bit ADC (ADC3/4)

16-bit timers - GPT12, Timer 2, Timer 21 and Timer 3

Capture/compare unit for PWM signal generation (CCU6)

2 full duplex serial interfaces (UART) with LIN support (for UART1 only)

2 synchronous serial channels (SSC)

On-chip debug support via 2-wire SWD

1 LIN 2.2 transceiver

1 high voltage monitoring input

Single power supply from 5.5 V to 27 V

Extended power supply voltage range from 3 V to 28 V

Low-dropout voltage regulators (LDO)

High speed operational amplifier for motor current sensing via shunt

5 V voltage supply for external loads (e.g. Hall sensor)

Core logic supply at 1.5 V

Programmable window watchdog (WDT1) with independent on-chip clock source

Power saving modes

–

MCU slow-down Mode

Sleep Mode

Stop Mode

Cyclic wake-up Sleep Mode

•

Power-on and undervoltage/brownout reset generator

Overtemperature protection

Short circuit protection

Data Sheet

7

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Overview

•

Loss of clock detection with fail safe mode entry for low system power consumption

Temperature Range T_j= -40°C to +150°C

Package VQFN-48 with LTI feature

Green package (RoHS compliant)

AEC qualified

Data Sheet

8

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Overview

1.1

Abbreviations

The following acronyms and terms are used within this document. List see in Table 1.

Table 1

Acronyms

AHB

APB

Acronyms

Name

Advanced High-Performance Bus

Advanced Peripheral Bus

Capture Compare Unit 6

Clock Generation Unit

Cyclic Management Unit

Charge Pump for MOSFET driver

Current Sense Amplifier

Data Post Processing

CCU6

CGU

CMU

CP

CSA

DPP

ECC

Error Correction Code

EEPROM

EIM

Electrically Erasable Programmable Read Only Memory

Exceptional Interrupt Measurement

Finite State Machine

FSM

GPIO

H-Bridge

ICU

General Purpose Input Output

Half Bridge

Interrupt Control Unit

IEN

Interrupt Enable

IIR

Infinite Impulse Response

Load Instruction

LDM

LDO

LIN

Low DropOut voltage regulator

Local Interconnect Network

Least Significant Bit

LSB

LTI

Lead Tip Inspection

MCU

MF

Memory Control Unit

Measurement Functions

Most Significant Bit

MSB

MPU

MRST

MTSR

MU

Memory Protection Unit

Master Receive Slave Transmit

Master Transmit Slave Receive

Measurement Unit

NMI

Non Maskable Interrupt

Nested Vector Interrupt Controller

Non-Volatile Memory

NVIC

NVM

OTP

One Time Programmable

Oscillator

OSC

Data Sheet

9

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Overview

Table 1

Acronyms

PBA

Acronyms

Name

Peripheral Bridge

PCU

Power Control Unit

PD

Pull Down

PGU

Power supply Generation Unit

Phase Locked Loop

PLL

PPB

Private Peripheral Bus

Pull Up

PU

PWM

RAM

Pulse Width Modulation

Random Access Memory

Reset Control Unit

RCU

RMU

ROM

SCU-DM

SCU-PM

SFR

Reset Management Unit

Read Only Memory

System Control Unit - Digital Modules

System Control Unit - Power Modules

Special Function Register

Short Open Window (for WDT)

Serial Peripheral Interface

Synchronous Serial Channel

Store Instruction

SOW

SPI

SSC

STM

SWD

TCCR

TMS

ARM Serial Wire Debug

Temperature Compensation Control Register

Test Mode Select

TSD

Thermal Shut Down

UART

VBG

Universal Asynchronous Receiver Transmitter

Voltage reference Band Gap

Voltage Controlled Oscillator

Pre Regulator

VCO

VPRE

WDT

WDT1

WMU

100TP

Watchdog Timer in SCU-DM

Watchdog Timer in SCU-PM

Wake-up Management Unit

100 Time Programmable

Data Sheet

10

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Block Diagram

2

Block Diagram

TMS

P0.0

TEST / DEBUG

INTERFACE

ARM

CORTEX-M3

µDMA

CONTROLLER

FLASH

slave

SRAM

slave

ROM

slave

systembus

slave

Multilayer AHB Matrix

slave

PBA0

slave

PBA1

VAREF

GND_REF

MU-VAREF

ADC 3/4

SCU_DM

PLL

UART1

UART2

SSC1

SSC2

T2

P2.0, P2.2, P2.3, P2.4, P2.5

(AN0, AN2, AN3, AN4, AN5)

ADC 1

DPP1

GPT12

CCU6

P0.1 – P0.4

P1.0 – P1.4

GPIO

LIN

VDH

GH3

SH3

GL3

GH2

SH2

GL2

GH1

SH1

LIN

GND_LIN

MU

MF / ADC2

MOSFET

Driver

T21

DPP2

SCU_DM

WDT

OP1

OP2

OP AMP

VS

GL1

SL

SCU_PM

WDT1/

CLKWDT

PMU –

Power

Control

System

Functions

RESET

VDDEXT

VDDP

VDDC

VCP

VSD

CP2H

CP2L

CP1H

CP1L

µ

DMA

CP

Controller

MON

T3

Figure 2

Block Diagram

Data Sheet

11

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Device Pinout and Pin Configuration

3

Device Pinout and Pin Configuration

3.1

Device Pinout

OP1 37

24 P0.3

EP

VDDC 38

23 P0.1

22 RESET

GND 39

VDDP 40

VDDEXT 41

GND_LIN 42

LIN 43

21 P0.0

20 TMS

19 GND

18 P0.4

17 P1.2

16 P1.1

15 P1.0

TLE 9879-2

VDH 44

VS 45

SH3 46

VSD 47

14 MON

13 GL1

CP1H 48

Note:

= Low voltage pins

Figure 3

Device Pinout

Data Sheet

12

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Device Pinout and Pin Configuration

3.2

Pin Configuration

After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings:

•

Pull-up device enabled only (PU)

Pull-down device enabled only (PD)

Input with both pull-up and pull-down devices disabled (I)

Output with output stage deactivated = high impedance state (Hi-Z)

The functions and default states of the TLE9879-2QXA40 external pins are provided in the following table.

Type: indicates the pin type.

•

I/O: Input or output

I: Input only

O: Output only

P: Power supply

Not all alternate functions listed.

Table 2

Symbol

Pin Definitions and Functions

Type Reset Function

State¹⁾

Number

P0

Port 0

Port 0 is a 5-bit bidirectional general purpose I/O port.

Alternate functions can be assigned and are listed in the port

description. Main function is listed below.

P0.0

P0.1

21

23

I/O

I/PU

SWD

GPIO

Serial Wire Debug Clock

General Purpose IO

Alternate function mapping see Table 7

P0.2

25

I/O

I/PD

GPIO

General Purpose IO

Alternate function mapping see Table 7

Note:

For a functional SWD connection

this GPIO must be tied to zero!

P0.3

P0.4

P1

24

18

I/O

I/PU

I/PD

GPIO

Port 1

General Purpose IO

Alternate function mapping see Table 7

General Purpose IO

Alternate function mapping see Table 7

Port 1 is a 5-bit bidirectional general purpose I/O port.

Alternate functions can be assigned and are listed in the Port

description. The principal functions are listed below.

P1.0

P1.1

P1.2

15

16

17

I/O

I

GPIO

General Purpose IO

Alternate function mapping see Table 8

General Purpose IO

Alternate function mapping see Table 8

General Purpose IO

Alternate function mapping see Table 8

Data Sheet

13

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Device Pinout and Pin Configuration

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Type Reset Function

State¹⁾

Number

P1.3

P1.4

P2

26

I/O

I

GPIO

Port 2

General Purpose IO, used for Inrush Transistor

Alternate function mapping see Table 8

27

I/O

I

General Purpose IO

Alternate function mapping see Table 8

Port 2 is a 5-bit general purpose input-only port.

Alternate functions can be assigned and are listed in the Port

description. Main function is listed below.

P2.0/ADC3.P

P2.2/ADC3.N

P2.3

29

30

35

32

31

I/I

I

AN0

AN2

AN3

AN4

AN5

ADC analog input 0 (Sensor), ADC3+

Alternate function mapping see Table 9

I/O

ADC analog input 2 (Sensor), ADC3-

Alternate function mapping see Table 9

I

ADC analog input 3 (Sensor),

Alternate function mapping see Table 9

P2.4/ADC4.P

P2.5/ADC4.N

ADC analog input 4 (Sensor), ADC4+

Alternate function mapping see Table 9

ADC analog input 5 (Sensor), ADC4-

Alternate function mapping see Table 9

Power Supply

VS

45

40

38

P

–

Battery supply input

²⁾I/O port supply (5.0 V). Connect external buffer capacitor.

³⁾Core supply (1.5 V during Active Mode).

Do not connect external loads, connect external buffer

capacitor.

VDDP

VDDC

VDDEXT

GND

41

19

28

39

P

–

External voltage supply output (5.0 V, 20 mA)

GND digital

GND analog

GND

Monitor Input

MON

14

I

–

High Voltage Monitor Input

LIN Interface

LIN

43

42

I/O

P

–

LIN bus interface input/output

LIN ground

GND_LIN

Charge Pump

CP1H

48

1

P

–

Charge Pump Capacity 1 High, connect external C

Charge Pump Capacity 1 Low, connect external C

Charge Pump Capacity 2 High, connect external C

Charge Pump Capacity 2 Low, connect external C

Charge Pump Capacity

CP1L

CP2H

3

CP2L

4

VCP

2

Data Sheet

14

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Device Pinout and Pin Configuration

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Type Reset Function

State¹⁾

Number

VSD

47

P

–

Battery supply input for Charge Pump

MOSFET Driver

VDH

44

46

6

P

–

Voltage Drain High Side MOSFET Driver

Source High Side FET 3

Source High Side FET 2

Gate High Side FET 2

SH3

SH2

GH2

7

SH1

8

Source High Side FET 1

Gate High Side FET 1

GH1

9

SL

10

12

13

5

Source Low Side FET

Gate Low Side FET 2

GL2

GL1

Gate Low Side FET 1

GH3

Gate High Side FET 3

GL3

11

Gate Low Side FET 3

Others

GND_REF

VAREF

OP1

33

34

37

36

20

P

–

GND for VAREF

I/O

–

5V ADC1 reference voltage, optional buffer or input

Negative operational amplifier input

Positive operational amplifier input

I

–

OP2

–

TMS

I

I/PD

TMS

SWD

Test Mode Select input

Serial Wire Debug input/output

I/O

RESET

EP

22

–

I/O

–

Reset input, not available during Sleep Mode

Exposed Pad, connect to GND

1) Only valid for digital IOs

2) Also named VDD5V.

3) Also named VDD1V5.

Data Sheet

15

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Modes of Operation

4

Modes of Operation

This highly integrated circuit contains analog and digital functional blocks. An embedded 32-bit

microcontroller is available for system and interface control. On-chip, low-dropout regulators are provided for

internal and external power supply. An internal oscillator provides a cost effective clock that is particularly

well suited for LIN communications. A LIN transceiver is available as a communication interface. Driver stages

for a Motor Bridge or BLDC Motor Bridge with external MOSFET are integrated, featuring PWM capability,

protection features and a charge pump for operation at low supply voltage. A 10-bit SAR ADC and two

differential 14-bit Sigma Delta ADCs are implemented for high precision sensor measurement. An 8-bit ADC is

used for diagnostic measurements.

The Micro Controller Unit supervision and system protection (including a reset feature) is complemented by a

programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated

temperature sensors are available on-chip.

All relevant modules offer power saving modes in order to support automotive applications connected to

terminal 30. A wake-up from power-save mode is possible via a LIN bus message, via the monitoring input or

using a programmable time period (cyclic wake-up).

Featuring LTI, the integrated circuit is available in a VQFN-48-31 package with 0.5 mm pitch, and is designed

to withstand the severe conditions of automotive applications.

The TLE9879-2QXA40 has several operation modes mainly to support low power consumption requirements.

Reset Mode

The Reset Mode is a transition mode used e.g. during power-up of the device after a power-on reset, or after

wake-up from Sleep Mode. In this mode, the on-chip power supplies are enabled and all other modules are

initialized. Once the core supply VDDC is stable, the device enters Active Mode. If the watchdog timer WDT1

fails more than four times, the device performs a fail-safe transition to Sleep Mode.

Active Mode

In Active Mode, all modules are activated and the TLE9879-2QXA40 is fully operational.

Stop Mode

Stop Mode is one of two major low power modes. The transition to the low power modes is performed by

setting the corresponding bits in the mode control register. In Stop Mode the embedded microcontroller is still

powered, allowing faster wake-up response times. Wake-up from this mode is possible through LIN bus

activity, by using the high-voltage monitoring pin or the corresponding 5V GPIOs.

Stop Mode with Cyclic Wake-Up

The Cyclic Wake-Up Mode is a special operating mode of the Stop Mode. The transition to the Cyclic Wake-Up

Mode is done by first setting the corresponding bits in the mode control register followed by the Stop Mode

command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period),

asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Stop Mode.

Sleep Mode

The Sleep Mode is a low-power mode. The transition to the low-power mode is done by setting the

corresponding bits in the MCU mode control register or in case of failure, see below. In Sleep Mode the

embedded microcontroller power supply is deactivated allowing the lowest system power consumption. A

wake-up from this mode is possible by LIN bus activity, the High Voltage Monitor Input pin or Cyclic Wake-up.

Data Sheet

16

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Modes of Operation

Sleep Mode in Case of Failure

Sleep Mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). In this case,

MON is enabled as the wake source and Cyclic Wake-Up is activated with 1s of wake time.

Sleep Mode with Cyclic Wake-Up

The Cyclic Wake-Up Mode is a special operating mode of the Sleep Mode. The transition to Cyclic Wake-Up

Mode is performed by first setting the corresponding bits in the mode control register followed by the Sleep

and Stop Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time

period), asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal

Sleep Mode.

When using Sleep Mode with cyclic wake-up the voltage regulator is switched off and started again with the

wake. A limited number of registers is buffered during sleep, and can be used by SW e.g. for counting

sleep/wake cycles.

MCU Slow Down Mode

In MCU Slow Down Mode the MCU frequency is reduced for saving power during operation. LIN

communication is still possible. LS MOSFET can be activated.

Wake-Up Source Prioritization

All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up

sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are

latched in order to provide all wake-up events to the application software. The software can clear the wake-

up source flags. This is to ensure that no wake-up event is lost.

As default wake-up source, the MON input is activated after power-on reset only. Additionally, the device is in

Cyclic Wake-Up Mode with the max. configurable dead time setting.

The following table shows the possible power mode configurations including the Stop Mode.

Table 3

Power Mode Configurations

Module/Function

Active Mode Stop Mode

Sleep Mode

Comment

VDDEXT

ON/OFF

ON (no dynamic

OFF

–

load)/OFF

Bridge Driver

LIN TRx

ON/OFF

OFF

wake-up only/

OFF

wake-up only/

OFF

–

VS sense

ON/OFF

brownout

detection

brownout detection POR on VS

brownout det. done

in PCU

GPIO 5V (wake-up)

GPIO 5V (active)

WDT1

n.a.

ON

n.a.

disabled/static

OFF

–

ON

OFF

CYCLIC WAKE

cyclic wake-up/

cyclic sense/OFF

cyclic wake-up/

OFF

Measurement

MCU

ON¹⁾

OFF

STOP²⁾

OFF

–

ON/slow-

down/STOP

Data Sheet

17

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Modes of Operation

Table 3

Power Mode Configurations (cont’d)

Module/Function

CLOCK GEN (MC)

LP_CLK (18 MHz)

LP_CLK2 (100 kHz)

Active Mode Stop Mode

Sleep Mode

OFF

Comment

ON

OFF

–

ON

OFF

WDT1

ON/OFF

for cyclic wake-up

1) May not be switched off due to safety reasons

2) MC PLL clock disabled, MC supply reduced to 1.1 V

Wake-Up Levels and Transitions

The wake-up can be triggered by rising, falling or both signal edges for the monitor input, by LIN or by cyclic

wake-up.

Data Sheet

18

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Power Management Unit (PMU)

5

Power Management Unit (PMU)

5.1

Features

•

System modes control (startup, sleep, stop and active)

Power management (cyclic wake-up)

Control of system voltage regulators with diagnosis (overload, short, overvoltage)

Fail safe mode detection and operation in case of system errors (watchdog fail)

Wake-up sources configuration and management (LIN, MON, GPIOs)

System error logging

5.2

Introduction

The power management unit is responsible for generating all required voltage supplies for the embedded

MCU (VDDC, VDDP) and the external supply (VDDEXT). The power management unit is designed to ensure fail-

safe behavior of the system IC by controlling all system modes including the corresponding transitions.

Additionally, the PMU provides well defined sequences for the system mode transitions and generates

hierarchical reset priorities. The reset priorities control the reset behavior of all system functionalities

especially the reset behavior of the embedded MCU. All these functions are controlled by a state machine. The

system master functionality of the PMU make use of an independent logic supply and system clock. For this

reason, the PMU has an "Internal logic supply and system clock" module which works independently of the

MCU clock.

Data Sheet

19

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Power Management Unit (PMU)

5.2.1

Block Diagram

The following figure shows the structure of the Power Management Unit. Table 4 describes the submodules

in more detail.

VS

Power Down Supply

VDDP

VDDC

Power SupplyGeneration Unit

(PGU)

I

N

T

E

R

N

A

L

e.g. for WDT1

LP_CLK

Peripherals

LDO for External Supply

VDDEXT

e.g. for cyclic

wake and sense

LP_CLK2

B

U

S

PMU-PCU

PMU-SFR

MON

LIN

P0.0...P0.4

P1.0...P1.4

PMU-CMU

PMU-RMU

PMU-WMU

PMU-Control

Power Management Unit

Power_Management_7x.vsd

Figure 4

Table 4

Power Management Unit Block Diagram

Description of PMU Submodules

Mod.

Modules

Functions

Name

Power Down Independent supply voltage

This supply is dedicated to the PMU to ensure an

independent operation from generated power supplies

(VDDP, VDDC).

Supply

generation for PMU

LP_CLK

(= 18 MHz)

- Clock source for all PMU

submodules

This ultra low power oscillator generates the clock for

the PMU.

- Backup clock source for System This clock is also used as backup clock for the system in

- Clock source for WDT1

Clock source for PMU

Peripheral blocks of PMU

case of PLL Clock failure and as an independent clock

source for WDT1.

LP_CLK2

(= 100 kHz)

This ultra low power oscillator generates the clock for

the PMU in Stop Mode and in the cyclic modes.

Peripherals

These blocks include the analog peripherals to ensure a

stable and fail-safe PMU startup and operation

(bandgap, bias).

Data Sheet

20

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Power Management Unit (PMU)

Table 4

Description of PMU Submodules (cont’d)

Mod.

Modules

Functions

Name

Power Supply Voltage regulators for VDDP and

This block includes the voltage regulators for the pad

supply (VDDP) and the core supply (VDDC).

Generation

Unit (PGU)

VDDC

VDDEXT

Voltage regulator for VDDEXT to

supply external modules (e.g.

sensors)

This voltage regulator is a dedicated supply for external

modules and can also be used for cyclic sense

operations (e.g. with hall sensor).

PMU-SFR

PMU-PCU

All Extended Special Function

registers that are relevant to the

PMU.

This module contains all registers needed to control and

monitor the PMU.

Power Control Unit of the PMU

This block is responsible for controlling all power

related actions within the PGU Module. It also contains

all regulator related diagnostics such as undervoltage

and overvoltage detection as well as overcurrent and

short circuit diagnostics.

PMU-WMU

PMU-CMU

PMU-RMU

Wake-Up Management Unit of the This block is responsible for controlling all wake-up

PMU

related actions within the PMU Module.

Cyclic Management Unit of the

PMU

This block is responsible for controlling all actions in

cyclic mode.

Reset Management Unit of the PMU This block generates resets triggered by the PMU such as

undervoltage or short circuit reset, and passes all resets

to the relevant modules and their register.

Data Sheet

21

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Power Management Unit (PMU)

5.2.2

PMU Modes Overview

The following state diagram shows the available modes of the device.

V_S> 4V and V_Sramp up

or

V_S< 3V and V_Sramp down

LIN-wake or

MON-wake

or

cyclic -wake

start-up

VDDC =stable and

error_supp<5

VDDC / VDDP =

fail (short circuit)

Æ error_supp ++

error_supp=5

sleep

active

Sleep command (from MCU) or

WDT1_SEQ_FAIL = 1 (Æ error_wdt = 5)

or

VDDC / VDDP = overload

LIN-wake or

MON-wake or

GPIO-wake or

cyclic _wake or

PMU_PIN = 1 or

PMU_SOFT = 1 or

(PMU_Ext_WDT = 1 and

WDT1_SEQ_FAIL = 0

Æ error_wdt ++)

SUP_TMOUT = 1

Stop

command

(from MCU)

stop

cyclic -sense

Figure 5

Power Management Unit System Modes

Data Sheet

22

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Power Management Unit (PMU)

5.3

Power Supply Generation Unit (PGU)

5.3.1

Voltage Regulator 5.0V (VDDP)

This module represents the 5 V voltage regulator, which provides the pad supply for the parallel port pins and

other 5 V analog functions (e.g. LIN Transceiver).

Features

•

5 V low-drop voltage regulator

Overcurrent monitoring and shutdown with MCU signaling (interrupt)

Overvoltage monitoring with MCU signaling (interrupt)

Undervoltage monitoring with MCU signaling (interrupt)

Undervoltage monitoring with reset (Undervoltage Reset, V_DDPUV

Pre-Regulator for VDDC Regulator

GPIO Supply

)

Pull Down Current Source at the output for Sleep Mode only (typ. 5 mA)

The output capacitor C_VDDPis mandatory to ensure proper regulator functionality.

VDDP Regulator

VS

VDDP

VPRE

A

CVDDP

V

GND (Pin 39)

I

5V LDO

LDO Supervision

Figure 6

Module Block Diagram of VDDP Voltage Regulator

Data Sheet

23

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Power Management Unit (PMU)

5.3.2

Voltage Regulator 1.5V (VDDC)

This module represents the 1.5 V voltage regulator, which provides the supply for the microcontroller core, the

digital peripherals and other internal analog 1.5 V functions (e.g. ADC2) of the chip. To further reduce the

current consumption of the MCU during Stop Mode the output voltage can be lowered to 1.1 V.

Features

•

1.5 V low-drop voltage regulator

Overcurrent monitoring and shutdown with MCU signaling (interrupt)

Overvoltage monitoring with MCU signaling (interrupt)

Undervoltage monitoring with MCU signaling (interrupt)

Undervoltage monitoring with reset

Pull Down Current Source at the output for Sleep Mode only (typ. 100 μA)

The output capacitor C_VDDCis mandatory to ensure a proper regulator functionality.

VDDC Regulator

VDDP (5V)

VDDC (1.5V)

A

V

C_VDDP

C_VDDC

GND (Pin 39)

I

1.5V LDO

LDO Supervision

Figure 7

Module Block Diagram of VDDC Voltage Regulator

Data Sheet

24

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Power Management Unit (PMU)

5.3.3

External Voltage Regulator 5.0V (VDDEXT)

This module represents the 5 V voltage regulator, which serves as a supply for external circuits. It can be used

e.g. to supply an external sensor, LEDs or potentiometers. VDDEXT can be used as reference for ADC3/4.

Features

•

Switchable +5 V, low-drop voltage regulator

Switch-on overcurrent blanking time in order to drive small capacitive loads

Overcurrent monitoring and shutdown with MCU signaling (interrupt)

Overvoltage monitoring with MCU signaling (interrupt)

Undervoltage monitoring with MCU signaling (interrupt)

Pull Down current source at the output for Sleep Mode only (typ. 100 μA)

Cyclic sense option together with GPIOs

The output capacitor C_VDDEXTis mandatory to ensure a proper regulator functionality.

VDDEXT Regulator

VS

VDDEXT

C_VDDEXT

VPRE

A

V

GND (Pin 39)

I

5V LDO

LDO Supervision

Figure 8

Module Block Diagram of External Voltage Regulator

Data Sheet

25

Rev. 1.0

2018-01-16

TLE9879-2QXA40

System Control Unit - Digital Modules (SCU-DM)

6

System Control Unit - Digital Modules (SCU-DM)

6.1

Features

•

Flexible clock configuration features

Reset management of all system resets

System modes control for all power modes (active, power down, sleep)

Interrupt enabling for many system peripherals

General purpose input output control

Debug mode control of system peripherals

6.2

Introduction

The System Control Unit (SCU) supports all central control tasks in the TLE9879-2QXA40. The SCU is made up

of the following sub-modules:

•

Clock System and Control

Reset Control

Power Management

Interrupt Management

General Port Control

Flexible Peripheral Management

Module Suspend Control

Watchdog Timer

Error Detection and Correction in Data Memory

Miscellaneous Control

Data Sheet

26

Rev. 1.0

2018-01-16

TLE9879-2QXA40

System Control Unit - Digital Modules (SCU-DM)

6.2.1

Block Diagram

On signals to digital

peripherals;

status signals from

digital peripherals

AHB

PMCU

WDT

ICU

f

SYS

I

N

T

E

R

N

A

L

CGU

f_OSC

OSC

PLL

NMI

LP_CLK

f_PLL

f

SYS

INTISR <9:0>

CG

f_PCLK

f_{MI_CLK}

B

U

S

f_{TFILT _CLK}

PMU_1V5DidPOR

PMU_PIN

PMU_ExtWDT

PMU_IntWDT

PMU_SOFT

MISCControl

MODPISELx

RCU

PMU_Wake

RESET_TYPE_3

RESET_TYPE_4

P0_POCONy.PDMx

P1_POCONy.PDMx

Port Control

System Control Unit -Digital Modules

Figure 9

System Control Unit - Digital Modules Block Diagram

AHB (Advanced High-Performance Bus)

PMCU (Power Module Control Unit)

WDT (Watchdog Timer in SCU-DM)

•

f

_SYSSystem clock

CGU (Clock Generation Unit)

•

f

_SYSSystem clock

_PCLKPeripheral clock

Data Sheet

27

Rev. 1.0

2018-01-16

TLE9879-2QXA40

System Control Unit - Digital Modules (SCU-DM)

•

f_{MI_CLK}Measurement interface clock

f_{TFILT_CLK}Analog module filter clock

LP_CLK Clock source for all PMU submodules and WDT1

ICU (Interrupt Control Unit)

•

NMI (Non-Maskable Interrupt)

INTISR<15,13:4,1,0> External interrupt signals

RCU (Reset Control Unit)

•

PMU_1V5DidPOR Undervoltage reset of power down supply

PMU_PIN Reset generated by reset pin

PMU_ExtWDT WDT1 reset

PMU_IntWDT WDT (SCU) reset

PMU_SOFT Software reset

PMU_Wake Sleep Mode/Stop Mode exit with reset

RESET_TYPE_3 Peripheral reset (contains all resets)

RESET_TYPE_4 Peripheral reset (without SOFT and WDT reset)

Port Control

•

P0_POCONy.PDMx driver strength control

P1_POCONy.PDMx driver strength control

MISC Control

MODPISELx Mode selection registers for UART (source section) and Timer (trigger or count selection)

•

6.3

Clock Generation Unit

The Clock Generation Unit (CGU) enables a flexible clock generation for TLE9879-2QXA40. During user

program execution, the frequency can be modified to optimize the performance/power consumption ratio,

allowing power consumption to be adapted to the actual application state.

The CGU in the TLE9879-2QXA40 consists of one oscillator circuit (OSC_HP), a Phase-Locked Loop (PLL)

module with an internal oscillator (OSC_PLL), and a Clock Control Unit (CCU). The CGU can convert a low-

frequency input/external clock signal to a high-frequency internal clock.

The system clock f_SYSis generated from of the following selectable clocks:

•

PLL clock output f_PLL

Direct clock from oscillator OSC_HP

Low precision clock f_{LP_CLK}(HW-enabled for startup after reset and during power-down wake-up sequence)

Data Sheet

28

Rev. 1.0

2018-01-16

TLE9879-2QXA40

System Control Unit - Digital Modules (SCU-DM)

CGU

PLLCON

CMCON

OSC_CON

HPOSCCON

SYSCON0

PLL

OSC_HP

f

SYS

OSC

CCU

f

LP_CLK

PMU

CGU_block

Figure 10 Clock Generation Unit Block Diagram

The following sections describe the different parts of the CGU.

6.3.1

Low Precision Clock

The clock source LP_CLK is a low-precision RC oscillator (LP-OSC) with a nominal frequency of 18 MHz that is

enabled by hardware as an independent clock source for the TLE9879-2QXA40 startup after reset and during

the power-down wake-up sequence. f_{LP_CLK}is not user configurable.

Data Sheet

29

Rev. 1.0

2018-01-16

TLE9879-2QXA40

System Control Unit - Power Modules (SCU-PM)

7

System Control Unit - Power Modules (SCU-PM)

7.1

Features

•

Clock Watchdog Unit (CWU): supervision of all clocks with NMI signaling relevant to power modules

Interrupt Control Unit (ICU): all interrupt flags and status flags with system relevance

Power Control Unit (PCU): takes over control when device enters and exits Sleep and Stop Mode

External Watchdog (WDT1): independent system watchdog for monitoring system activity

7.2

Introduction

7.2.1

Block Diagram

The System Control Unit of the power modules consists of the sub-modules in the figure shown below:

On signals to analog

peripherals;

status signals from

analog peripherals

AHB

I

N

T

PCU

WDT1

LP_CLK

E

R

N

A

L

fsys

MI_CLK

PREWARN_SUP_NMI

PREWARN_SUP_INT

INT<n:0>

B

U

S

CWU

ICU

TFILT_CLK

System Control Unit -Power Modules

Figure 11 Block diagram of System Control Unit - Power Modules

AHB (Advanced High-Performance Bus)

CWU (Clock Watchdog Unit)

•

f_syssystem frequency: PLL output

MI_CLK measurement interface clock (analog clock): derived from fsys using division factors 1/2/3/4

TFILT_CLK clock used for digital filters: derived from fsys using configurable division factors

Data Sheet

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TLE9879-2QXA40

System Control Unit - Power Modules (SCU-PM)

WDT1 (System Watchdog)

•

LP_CLK clock source for all PMU submodules and WDT1

ICU (Interrupt Control Unit)

•

PREWARN_SUP_NMI supply prewarning NMI request

PREWARN_SUP_INT supply prewarning interrupt

grouping of peripheral interrupts for external interupt nodes:

–

grouping single peripheral interrupts for interrupt node INT<2> (Measurement Unit (MU))

grouping single peripheral interrupts for interrupt node INT<3> (ADC1-VAREF)

grouping single peripheral interrupts for interrupt node INT<10> (UART1-LIN Transceiver)

grouping single peripheral interrupts for interrupt node INT<14> (Bridge Driver)

Data Sheet

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TLE9879-2QXA40

ARM Cortex-M3 Core

8

ARM Cortex-M3 Core

8.1

Features

The key features of the Cortex-M3 implemented are listed below.

Processor Core; a low gate count core, with low latency interrupt processing:

•

A subset of the Thumb^®-2 Instruction Set

Banked stack pointer (SP) only

32-bit hardware divide instructions, SDIV and UDIV (Thumb-2 instructions)

Handler and Thread Modes

Thumb and debug states

Interruptible-continued instructions LDM/STM, Push/Pop for low interrupt latency

Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and

exit

•

ARM architecture v7-M Style BE8/LE support

ARMv6 unaligned accesses

Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low

latency interrupt processing:

•

Interrupts, configurable from 1 to 16

Bits of priority (4)

Dynamic reprioritization of interrupts

Priority grouping. This enables selection of preemptive interrupt levels and non-preemptive interrupt

levels

•

Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing

without the overhead of state saving and restoration between interrupts.

Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction

overhead

Bus interfaces

•

Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and System bus interface

Memory access alignment

Write buffer for buffering of write data

Data Sheet

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TLE9879-2QXA40

ARM Cortex-M3 Core

8.2

Introduction

The ARM Cortex-M3 processor is a leading 32-bit processor and provides a high-performance and cost-

optimized platform for a broad range of applications including microcontrollers, automotive body systems

and industrial control systems. Like the other Cortex family processors, the Cortex-M3 processor implements

the Thumb^®-2 instruction set architecture. With the optimized feature set the Cortex-M3 delivers 32-bit

performance in an application space that is usually associated with 8- and 16-bit microcontrollers.

8.2.1

Block Diagram

Figure 12 shows the functional blocks of the Cortex-M3.

Cortex-M3 Processor

Nested Vectored

Interrupt

Cortex-M3

Processor

Core

Interrupt and

Power Control

Controller

(NVIC)

AHB

Access Port

(AHB-AP)

Serial-Wire

(SW-DP)

Bus Matrix

ICode

AHB-Lite

Instruction

Interface

DCode

AHB-Lite

Data

System Bus

ICode

Serial-Wire Debug

Interface

PBA0

PBA1

Interface

Cortex_M3_Block_diagram.vsd

Figure 12 Cortex-M3 Block Diagram

Data Sheet

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TLE9879-2QXA40

DMA Controller

9

DMA Controller

Figure 13 shows the Top Level Block Diagram of the TLE9879-2QXA40.

The bus matrix allows the μDMA to access the PBA0, PBA1 and RAM.

9.1

Features

The principal features of the DMA Controller are that:

•

it is compatible with AHB-Lite for the DMA transfers

it is compatible with APB for programming the registers

it has a single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus

it supports 14 DMA channels

each DMA channel has dedicated handshake signals

each DMA channel has a programmable priority level

each priority level arbitrates using a fixed priority that is determined by the DMA channel number. The DMA

also supports multiple transfer types:

- memory-to-memory

- memory-to-peripheral

- peripheral-to-memory

•

it supports multiple DMA cycle types

it supports multiple DMA transfer data widths

each DMA channel can access a primary, and alternate, channel control data structure

all the channel control data is stored in system memory (RAM) in little-endian format

it performs all DMA transfers using the single AHB-Lite burst type. The destination data width is equal to

the source data width.

•

the number of transfers in a single DMA cycle can be programmed from 1 to 1024

the transfer address increment can be greater than the data width

Data Sheet

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TLE9879-2QXA40

DMA Controller

9.2

Introduction

Please also refer to Chapter 9.3, Functional Description.

9.2.1

Block Diagram

SSC1

Timer3

ADC1

DMA requests

DMA Controller

Bus Matrix

S

PBA1

S

AHB2APB

M

AHB lite

M

AHB lite

APB Interface

interrupts

SCU_DM

PBA0

S

AHB lite

M

RAM

S

ARM Core

interrupts

S

M

AHB lite

Figure 13

DMA Controller Top Level Block Diagram

Data Sheet

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TLE9879-2QXA40

DMA Controller

9.3

Functional Description

9.3.1

DMA Mode Overview

The DMA controller implements the following 14 hardware DMA requests:

•

ADC1 complete sequence 1 done: DMA transfer is requested on completion of the ADC1 channel conversion

sequence.

•

ADC1 exceptional sequence 2 (ESM) done: DMA transfer is requested on completion of the ADC1 conversion

sequence triggered by an exceptional measurement request.

•

SSC1/2 transmit byte: DMA transfer is requested upon the completion of data transmission via SSC1/2

SSC1/2: receive byte: DMA transfer is requested upon the completion of data reception via SSC1/2.

ADC1 channel 0 conversion done: DMA transfer is requested on completion of the ADC1 channel 0

conversion.

•

ADC1 channel 1 conversion done: DMA transfer is requested on completion of the ADC1 channel 1

conversion.

ADC1 channel 2 conversion done: DMA transfer is requested on completion of the ADC1 channel 2

conversion.

ADC1 channel 3 conversion done: DMA transfer is requested on completion of the ADC1 channel 3

conversion.

ADC1 channel 4 conversion done: DMA transfer is requested on completion of the ADC1 channel 4

conversion.

ADC1 channel 5 conversion done: DMA transfer is requested on completion of the ADC1 channel 5

conversion.

ADC1 channel 6 conversion done: DMA transfer is requested on completion of the ADC1 channel 6

conversion.

ADC1 channel 7 conversion done: DMA transfer is requested on completion of the ADC1 channel 7

conversion.

•

Timer3 ccu6_int: DMA transfer is requested following a timer trigger.

SDADC, conversion done: DMA transfer is requested on completion of the SDADC (ADC3/4) conversion.

Data Sheet

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TLE9879-2QXA40

Address Space Organization

10

Address Space Organization

The TLE9879-2QXA40 manipulates operands in the following memory spaces:

•

128 KByte of Flash memory in code space

32 KByte Boot ROM memory in code space (used for boot code and IP storage)

6 KByte RAM memory in code space and data space (RAM can be read/written as program memory or

external data memory)

•

Special function registers (SFRs) in peripheral space

The figure below shows the detailed address alignment of TLE9879-2QXA40:

00000000_H

Reserved (BootROM)

00008000_H/ 10FFFFFF_H

11000000_H/ 1101FFFF_H

Flash, 128K

Reserved

11020000_H/ 17FFFFFF_H

18000000_H/ 180017FF_H

SRAM, 6K

Reserved

18001800_H/ 3FFFFFFF_H

40000000_H/ 47FFFFFF_H

PBA0

PBA1

48000000_H/ 5FFFFFFF_H

60000000_H/ DFFFFFFF_H

E0000000_H/ E00FFFFF_H

FFFFFFFF_H

Reserved

Private Peripheral Bus

Reserved

Figure 14 TLE9879-2QXA40 Memory Map

Data Sheet

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TLE9879-2QXA40

Memory Control Unit

11

Memory Control Unit

11.1

Features

•

Handles all system memories and their interaction with the CPU

Memory protection functions for all system memories (D-Flash, P-Flash, RAM)

Address management with access violation detection including reporting

Linear address range for all memories (no paging)

11.2

Introduction

11.2.1

Block Diagram

The Memory Control Unit (MCU) is divided in the following sub-modules:

•

NVM memory module (embedded Flash Memory)

RAM memory module

BootROM memory module

Memory Protection Unit (MPU) module

Peripheral Bridge PBA0

Data Sheet

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TLE9879-2QXA40

Memory Control Unit

NVM

S0

RAM

S1

BROM

S2

PBA0

S3

Memory Protection

Unit

Sx: BusSlave

Mx: Bus Master

M0

M1

M2

M3

Bus Matrix

MCU_Block_Diagram_overview.vsd

Figure 15 MCU Block View

Data Sheet

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TLE9879-2QXA40

Memory Control Unit

11.3

NVM Module (Flash Memory)

The Flash Memory provides an embedded user-programmable non-volatile memory, allowing fast and

reliable storage of user code and data.

Features

•

In-system programming via LIN (Flash Mode) and SWD

Error Correction Code (ECC) for detection of single-bit and double-bit errors and dynamic correction of

single Bit errors.

•

Interrupts and signals double-bit error by NMI

Program width of 128 byte (page)

Minimum erase width of 128 bytes (page)

Integrated hardware support for EEPROM emulation

8 byte read access

Physical read access time: 75 ns

Code read access acceleration integrated; read buffer and automatic pre-fetch

Page program time: 3 ms

Page erase (128 bytes) and sector erase (4K bytes) time: 4ms

Note:

The user has to ensure that no flash operations which change the content of the flash get

interrupted at any time.

The clock for the NVM is supplied with the system frequency fsys. Integrated firmware routines are provided

to erase NVM, and other operations including EEPROM emulation are provided as well.

Data Sheet

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TLE9879-2QXA40

Interrupt System

12

Interrupt System

12.1

Features

•

Up to 16 interrupt nodes for on-chip peripherals

Up to 8 NMI nodes for critical system events

Maximum flexibility for all 16 interrupt nodes

12.2

Introduction

Before enabling an interrupt, all corresponding interrupt status flags should be cleared.

12.2.1

Overview

The TLE9879-2QXA40 supports 16 interrupt vectors with 16 priority levels. Fifteen of these interrupt vectors

are assigned to the on-chip peripherals: GPT12, SSC, CCU6, DMA, Bridge Driver and A/D Converter are each

assigned to one dedicated interrupt vector; while UART1 and Timer2 or UART2, External Interrupt 2 and

Timer21 share interrupt vectors. Two vectors are dedicated for External Interrupt 0 and 1.

Table 5

Interrupt Vector Table

Service Request

GPT12

Node ID

Description

0/1

2

GPT interrupt (T2-T6, CAPIN)

Measurement Unit, VBG, SD-ADC, Timer3, BEMF

ADC1 interrupt / VREF5V Overload / VREF5V OV/UV

CCU6 node 0 interrupt

MU- ADC8/T3

ADC1

3

CCU0

4

CCU1

5

CCU6 node 1 interrupt

CCU2

6

CCU6 node 2 interrupt

CCU3

7

CCU6 node 3 interrupt

SSC1

8

SSC1 interrupt (receive, transmit, error)

SSC2 interrupt (receive, transmit, error)

SSC2

9

UART1

10

UART1 (ASC-LIN) interrupt (receive, transmit), Timer2, linsync1,

LIN

UART2

11

UART2 interrupt (receive, transmit), Timer21, External interrupt

(EINT2)

EXINT0

EXINT1

BDRV/CP

DMA

12

13

14

15

External interrupt (EINT0), MON

External interrupt (EINT1)

Bridge Driver / Charge Pump

DMA Controller

Data Sheet

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TLE9879-2QXA40

Interrupt System

Table 6

NMI Interrupt Table

Service Request

Watchdog Timer NMI

PLL NMI

Node

NMI

Description

Watchdog Timer overflow

PLL Loss-of-Lock

NMI

NVM Operation

Complete NMI

NMI

NVM Operation Complete

Overtemperature NMI NMI

System Overtemperature

Oscillator Watchdog

NMI

Oscillator Watchdog / MI_CLK Watchdog Timer Overflow

NVM Map Error NMI

ECC Error NMI

NMI

NVM Map Error

RAM / NVM Uncorrectable ECC Error

Supply Prewarning

Supply Prewarning NMI NMI

Data Sheet

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TLE9879-2QXA40

Watchdog Timer (WDT1)

13

Watchdog Timer (WDT1)

13.1

Features

There are two watchdog timers in the system. The Watchdog Timer (WDT) within the System Control Unit -

Digital Modules (see SCU_DM) and the Watchdog Timer (WDT1) located within the System Control Unit - Power

Modules (see SCU_PM). The Watchdog Timer WDT1 is described in this section.

In Active Mode, the WDT1 acts as a windowed watchdog timer, which provides a highly reliable and safe way

to recover from software or hardware failures.

The WDT1 is always enabled in Active Mode. In Sleep Mode, Low Power Mode and SWD Mode the WDT1 is

automatically disabled.

Functional Features

•

Windowed Watchdog Timer with programmable timing in Active Mode

Long open window (typ. 80ms) after power-up, reset, wake-up

Short open window (typ. 30ms) to facilitate Flash programming

Disabled during debugging

Safety shutdown to Sleep Mode after 5 missed WDT1 services

Data Sheet

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TLE9879-2QXA40

Watchdog Timer (WDT1)

13.2

Introduction

The behavior of the Watchdog Timer in Active Mode is illustrated in Figure 16.

Power-up

Reset

RESET

always

Timeout

RESET

Trigger SOW

Maximum number

of count_SOW

Timeout

or

Trigger in closed window

RESET

Long

Open Window

Trigger&

count_SOW = 0

Trigger SOW&

count_SOW++

Normal

„windowed“

operation

Short

open window

& SOW

Trigger &

count_SOW = 0

Trigger SOW &

count_SOW++

Trigger&

count_SOW = 0

Figure 16 Watchdog Timer Behavior

Data Sheet

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TLE9879-2QXA40

GPIO Ports and Peripheral I/O

14

GPIO Ports and Peripheral I/O

The TLE9879-2QXA40 has 15 port pins organized into three parallel ports: Port 0 (P0), Port 1 (P1) and Port 2

(P2). Each port pin has a pair of internal pull-up and pull-down devices that can be individually enabled or

disabled. P0 and P1 are bidirectional and can be used as general purpose input/output (GPIO) or to perform

alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain

mode can be selected. On Port 2 (P2) analog inputs are shared with general purpose input.

14.1

Features

Bidirectional Port Features (P0, P1)

•

Configurable pin direction

Configurable pull-up/pull-down devices

Configurable open drain mode

Configurable drive strength

Transfer of data through digital inputs and outputs (general purpose I/O)

Alternate input/output for on-chip peripherals

Analog Port Features (P2)

•

Configurable pull-up/pull-down devices

Transfer of data through digital inputs

Alternate inputs for on-chip peripherals

14.2

Introduction

14.2.1

Port 0 and Port 1

Figure 17 shows the block diagram of an TLE9879-2QXA40 bidirectional port pin. Each port pin is equipped

with a number of control and data bits, thus enabling very flexible usage of the pin. By defining the contents

of the control register, each individual pin can be configured as an input or an output. The user can also

configure each pin as an open drain pin with or without internal pull-up/pull-down device.

Each bidirectional port pin can be configured for input or output operation. Switching between input and

output mode is accomplished through the register Px_DIR (x = 0 or 1), which enables or disables the output

and input drivers. A port pin can only be configured as either input or output mode at any one time.

In input mode (default after reset), the output driver is switched off (high-impedance). The voltage level

present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via the

register Px_DATA.

In output mode, the output driver is activated and drives the value supplied through the multiplexer to the

port pin. In the output driver, each port line can be switched to open drain mode or normal mode (push-pull

mode) via the register Px_OD.

The output multiplexer in front of the output driver enables the port output function to be used for different

purposes. If the pin is used for general purpose output, the multiplexer is switched by software to the data

register Px_DATA. Software can set or clear the bit in Px_DATA and therefore directly influence the state of the

Data Sheet

45

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TLE9879-2QXA40

GPIO Ports and Peripheral I/O

port pin. If an on-chip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be

switched via the multiplexer to the output driver circuitry. Selection of the alternate output function is defined

in registers Px_ALTSEL0 and Px_ALTSEL1. When a port pin is used as an alternate function, its direction must

be set accordingly in the register Px_DIR.

Each pin can also be programmed to activate an internal weak pull-up or pull-down device. Register

Px_PUDSEL selects whether a pull-up or the pull-down device is activated while register Px_PUDEN enables

or disables the pull device.

PUDSEL

Pull-up / Pull-down

Select Register

Pull-up / Pull-down

Control Logic

PUDEN

Pull-up / Pull-down

Enable Register

TCCR

Temperature Compensation

Control Register

Px_POCONy

Port Output

Driver Control Registers

I

N

T

E

R

N

A

L

OD

Open Drain

Control Register

DIR

Direction Register

ALTSEL0

Alternate Select

Register 0

B

U

S

ALTSEL1

Alternate Select

Register 1

Pull Device

AltDataOut 3

AltDataOut 2

AltDataOut 1

11

10

Output

Driver

01

00

Out

In

Px_DATA

Data Register

Input

Driver

AltDataIn

Schmitt

Trigger

Pad

Figure 17 General Structure of Bidirectional Port (P0, P1)

Data Sheet

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TLE9879-2QXA40

GPIO Ports and Peripheral I/O

14.2.2

Port 2

Figure 18 shows the structure of an input-only port pin. Each P2 pin can only function in input mode. Register

P2_DIR is provided to enable or disable the input driver. When the input driver is enabled, the actual voltage

level present at the port pin is translated into a logic 0 or 1 via a Schmitt trigger device and can be read via

register P2_DATA. Each pin can also be programmed to activate an internal weak pull-up or pull-down device.

Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated while register P2_PUDEN

enables or disables the pull device. The analog input (AnalogIn) bypasses the digital circuitry and Schmitt

trigger device for direct feed-through to the ADC input channels.

PUDSEL

Pull-up / Pull-down

SelectRegister

Pull-up / Pull-down

Control Logic

I

N

T

E

R

N

A

L

PUDEN

Pull-up / Pull-down

Enable Register

Pull Device

B

U

S

Input

Driver

In

DATA

Data Register

Schmitt

Trigger

Pad

AltDataIn

AnalogIn

Figure 18 General Structure of Input Port (P2)

Data Sheet

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TLE9879-2QXA40

GPIO Ports and Peripheral I/O

14.3

TLE9879-2QXA40 Port Module

14.3.1

Port 0

14.3.1.1 Port 0 Functions

Table 7

Port Pin

P0.0

Port 0 Input/Output Functions

Input/Output

Select

GPI

Connected Signal(s)

P0_DATA.P0

SWCLK / TCK_0

T12HR_0

T4INA

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

INP6

GPO

ALT1

ALT2

ALT3

GPI

SW

CCU6

GPT12T4

Timer 2

–

T2_0

–

EXINT2_3

P0_DATA.P0

T3OUT

SCU

Output

Input

GPT12T3

Timer 21

UART2

EXF21_0

RXDO_2

P0_DATA.P1

T13HR_0

TxD1

P0.1

INP1

INP2

INP3

INP4

INP5

INP6

INP7

GPO

ALT1

ALT2

ALT3

CCU6

LIN_TxD

GPT12CAP

Timer 21

GPT12T4

SSC1

CAPINA

T21_0

T4INC

MRST_1_2

EXINT0_2

P0_DATA.P1

TxD1

SCU

Output

UART1 / LIN_TxD

–

T6OUT

GPT12T6

Data Sheet

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TLE9879-2QXA40

GPIO Ports and Peripheral I/O

Table 7

Port Pin

P0.2

Port 0 Input/Output Functions (cont’d)

Input/Output

Select

GPI

Connected Signal(s)

P0_DATA.P2

CCPOS2_1

T2EUDA

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

GPO

ALT1

ALT2

ALT3

GPI

CCU6

GPT12T2

SSC1

MTSR_1

T21EX_0

Timer 21

GPT12T6

–

T6INA

Output

Input

P0_DATA.P2

COUT60_0

MTSR_1

CCU6

SSC1

EXF2_0

Timer 2

P0.3

P0_DATA.P3

SCK_1

INP1

INP2

INP3

INP4

INP5

GPO

ALT1

ALT2

ALT3

GPI

SSC1

CAPINB

GPT12

GPT12T5

GPT12T4

CCU6

T5INA

T4EUDA

CCPOS0_1

P0_DATA.P3

SCK_1

Output

Input

SSC1

EXF21_2

Timer 21

GPT12T6

T6OUT

P0.4

P0_DATA.P4

MRST_1_0

CC60_0

INP1

INP2

INP3

INP4

INP5

INP6

GPO

ALT1

ALT2

ALT3

SSC1

CCU6

T21_2

Timer 21

SCU

EXINT2_2

T3EUDA

GPT12T3

CCU6

CCPOS1_1

P0_DATA.P4

MRST_1_0

CC60_0

Output

SSC1

CCU6

SCU

CLKOUT_0

Data Sheet

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TLE9879-2QXA40

GPIO Ports and Peripheral I/O

14.3.2

Port 1

14.3.2.1 Port 1 Functions

Table 8

Port Pin

P1.0

Port 1 Input / Output Functions

Input/Output

Select

GPI

Connected Signal(s)

P1_DATA.P0

T3INC

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

GPO

ALT1

ALT2

ALT3

GPI

GPT12T3

GPT12T4

CCU6

T4EUDB

CC61_0

SCK_2

SSC2

EXINT1_2

P1_DATA.P0

SCK_2

SCU

Output

Input

SSC2

CC61_0

CCU6

EXF21_3

P1_DATA.P1

–

Timer 21

P1.1

INP1

INP2

INP3

INP4

INP5

INP6

GPO

ALT1

ALT2

ALT3

GPI

–

T6EUDA

GPT12T6

-

–

MTSR_2

SSC2

Timer 21

SCU

T21_1

EXINT1_0

P1_DATA.P1

MTSR_2

Output

Input

–

SSC2

CCU6

UART2

COUT61_0

TXD2_0

P1.2

P1_DATA.P2

T2INA

INP1

INP2

INP3

INP4

INP5

INP6

INP7

GPO

ALT1

ALT2

ALT3

GPT12T2

Timer 2

Timer 21

SSC2

T2EX_1

T21EX_3

MRST_2_0

RXD2_0

UART2

CCU6

CCPOS2_2

EXINT0_1

P1_DATA.P2

MRST_2_0

COUT63_0

T3OUT

SCU

Output

SSC2

CCU6

GPT12T3

Data Sheet

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TLE9879-2QXA40

GPIO Ports and Peripheral I/O

Table 8

Port Pin

P1.3

Port 1 Input / Output Functions (cont’d)

Input/Output

Select

GPI

Connected Signal(s)

P1_DATA.P3

T6INB

From/to Module

Input

INP1

INP2

INP3

INP4

INP5

INP6

INP7

GPO

ALT1

ALT2

ALT3

GPI

GPT12T6

–

CC62_0

CCU6

T6EUDB

–

GPT12T6

CCPOS0_2

EXINT1_1

P1_DATA.P3

EXF21_1

CC62_0

CCU6

SCU

Output

Input

Timer 21

CCU6

TXD2_1

UART2

P1.4

P1_DATA.P4

EXINT2_1

T21EX_1

T5EUDA

INP1

INP2

INP3

INP4

INP5

INP6

INP7

GPO

ALT1

ALT2

ALT3

SCU

Timer 21

GPT12T5

UART1

GPT12T2

CCU6

RxD1

T2INB

CCPOS1_2

MRST_1_3

P1_DATA.P4

CLKOUT_1

COUT62_0

RxD1

SSC1

Output

SCU

CCU6

UART1 / LIN_RxD

Data Sheet

51

Rev. 1.0

2018-01-16

TLE9879-2QXA40

GPIO Ports and Peripheral I/O

14.3.3

Port 2

14.3.3.1 Port 2 Functions

Table 9

Port Pin

P2.0

Port 2 Input Functions

Input/Output

Select

Connected Signal(s)

P2_DATA.P0

CCPOS0_3

-

From/to Module

Input

GPI

INP1

INP2

INP3

INP4

INP5

ANALOG

IN

CCU6

-

T12HR_2

EXINT0_0

CC61_2

CCU6

SCU

CCU6

ADC1

SD-ADC

AN0

ADC3.P

P2.2

P2.3

P2.4

Input

GPI

P2_DATA.P2

CCPOS2_3

T13HR_2

–

INP1

INP2

INP3

INP4

ANALOG

IN

CCU6

CC62_2

CCU6

AN2

ADC1

ADC3.N

SD-ADC

GPI

P2_DATA.P3

CCPOS1_0

CTRAP#_1

T21EX_2

CC60_1

INP1

INP2

INP3

INP4

INP5

ANALOG

GPI

CCU6

Timer 21

CCU6

SCU

EXINT0_3

AN3

ADC1

P2_DATA.P4

CTRAP#_0

T2EUDB

MRST_1_1

EXINT1_3

AN4

INP1

INP2

INP3

INP4

ANALOG

IN

CCU6

GPT12T2

SSC1

SCU

ADC1

ADC4.P

SD-ADC

Data Sheet

52

Rev. 1.0

2018-01-16

TLE9879-2QXA40

GPIO Ports and Peripheral I/O

Table 9

Port Pin

P2.5

Port 2 Input Functions (cont’d)

Input/Output

Select

GPI

Connected Signal(s)

P2_DATA.P5

RXD2_1

From/to Module

Input

INP1

INP2

INP3

INP4

ANALOG

IN

UART2

GPT12T3

SSC2

T3EUDB

MRST_2_1

T2_1

Timer 2

ADC1

AN5

ADC4.N

SD-ADC

Data Sheet

53

Rev. 1.0

2018-01-16

TLE9879-2QXA40

General Purpose Timer Units (GPT12)

15

General Purpose Timer Units (GPT12)

15.1

Features

15.1.1

Features Block GPT1

The following list summarizes the supported features:

•

f_GPTis derived from PCLK

f_GPT/4 maximum resolution

3 independent timers/counters

Timers/counters can be concatenated

4 operating modes:

–

Timer Mode

Gated Timer Mode

Counter Mode

Incremental Interface Mode

•

Reload and Capture functionality

Shared interrupt: Node 0

15.1.2

Features Block GPT2

The following list summarizes the supported features:

•

f

_GPTis derived from PCLK

_GPT/2 maximum resolution

2 independent timers/counters

Timers/counters can be concatenated

3 operating modes:

–

Timer Mode

Gated Timer Mode

Counter Mode

•

Extended capture/reload functions via 16-bit capture/reload register CAPREL

Shared interrupt: Node 1

15.2

Introduction

The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible multifunctional timer structures

which may be used for timing, event counting, pulse width measurement, pulse generation, frequency

multiplication, and other purposes.

They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in

each block may operate independently in a number of different modes such as Gated timer or Counter Mode,

or may be concatenated with another timer of the same block.

Each block has alternate input/output functions and specific interrupts associated with it. Input signals can

be selected from several sources by register PISEL.

Data Sheet

54

Rev. 1.0

2018-01-16

TLE9879-2QXA40

General Purpose Timer Units (GPT12)

The GPT module is clocked with clock f_GPT. f_GPTis a clock derived from PCLK.

15.2.1

Block Diagram GPT1

Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary timers T2 and T4. The

maximum resolution is f_GPT/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture

registers for the core timer.

T3CON.BPS1

2ⁿ: 1

Basic clock

f_GPT

Interrupt Request

(T2IRQ)

Aux. Timer T2

Core Timer T3

Aux. Timer T4

U/D

T2IN

T2

Mode

Control

Capture

Reload

T2EUD

Toggle Latch

T3

Mode

Control

T3IN

T3OTL

T3OUT

U/D

T3EUD

Interrupt Request

(T3IRQ)

Capture

Reload

T4IN

T4

Mode

Control

T4EUD

Interrupt Request

(T4IRQ)

U/D

MC _GPT0101_bldiax1.vsd

Figure 19 GPT1 Block Diagram (n = 2 … 5)

Data Sheet

55

Rev. 1.0

2018-01-16

TLE9879-2QXA40

General Purpose Timer Units (GPT12)

15.2.2

Block Diagram GPT2

Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5. The maximum

resolution is f_GPT/2. An additional Capture/Reload register (CAPREL) supports capture and reload operation

with extended functionality.

T6CON.BPS2

f_GPT

2ⁿ: 1

Basic clock

Toggle FF

T2

Mode

Control

U/D

InterruptRequest

(T5IRQ)

T5IN

GPT2 Timer T5

Clear

T5EUD

Capture

CAPIN

CAPREL

Mode

Control

GPT2 CAPREL

T3IN/

T3EUD

InterruptRequest

(CRIRQ)

Reload

InterruptRequest

(T6IRQ)

Clear

U/D

T6

Mode

Control

GPT2 Timer T6

T6OTL

T6OUT

T6OUF

T6IN

T6EUD

Figure 20 GPT2 Block Diagram (n = 1 … 4)

Data Sheet

56

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Timer2 and Timer21

16

Timer2 and Timer21

16.1

Features

•

16-bit auto-reload mode

selectable up or down counting

One channel 16-bit capture mode

–

16.2

Introduction

The timer modules are general-purpose 16-bit timers. Timer 2/21 can function as a timer or counter in each of

its modes. As a timer, it counts with an input clock of f_PCLK/12 (if prescaler is disabled). As a counter, Timer 2

counts 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is f_PCLK/24 (if

prescaler is disabled).

16.2.1

Timer2 and Timer21 Modes Overview

Table 10

Mode

Timer2 and Timer21 Modes

Description

Auto-reload

Up/Down Count Disabled

•

Count up only

Start counting from 16-bit reload value, overflow at FFFF_H

Reload event configurable for trigger by overflow condition only, or by

negative/positive edge at input pin T2EX as well

•

Programmable reload value in register RC2

Interrupt is generated with reload events.

Data Sheet

57

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Timer2 and Timer21

Table 10

Mode

Timer2 and Timer21 Modes (cont’d)

Description

Auto-reload

Up/Down Count Enabled

•

Count up or down, direction determined by level at input pin T2EX

No interrupt is generated

Count up

–

Start counting from 16-bit reload value, overflow at FFFF_H

Reload event triggered by overflow condition

Programmable reload value in register RC2

•

Count down

–

Start counting from FFFF_H, underflow at value defined in register RC2

Reload event triggered by underflow condition

Reload value fixed at FFFF_H

•

Count up only

Channel capture

Start counting from 0000_H, overflow at FFFF_H

Reload event triggered by overflow condition

Reload value fixed at 0000_H

Capture event triggered by falling/rising edge at pin T2EX

Captured timer value stored in register RC2

Interrupt is generated by reload or capture events

Data Sheet

58

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Timer3

17

Timer3

17.1

Features

•

16-bit incremental timer/counter (counting up)

Counting frequency up to f_sys

Selectable clock prescaler

6 modes of operation

Interrupt up on overflow

Interrupt on compare

17.2

Introduction

The possible applications for the timer include measuring the time interval between events, counting events

and generating a signal at regular intervals.

Timer3 can function as timer or counter. When functioning as a timer, Timer3 is incremented in periods based

on the MI_CLK or LP_CLK clock. When functioning as a counter, Timer3 is incremented in response to a 1-to-0

transition (falling edge) at its respective input. Timer3 can be configured in four different operating modes to

use in a variety of applications, see Table 11.

Several operating modes can be used for different tasks such as the following:

•

simple time measurement between two events

triggering of the measuring unit upon PWM/CCU6 unit

measurement of the 100kHz LP_CLK2

17.3

Functional Description

Six modes of operation are provided to fulfill various tasks using this timer. In every mode the clocking source

can be selected between MI_CLK and LP_CLK. A prescaler provides in addition capability to divide the selected

clock source by 2, 4 or 8. The timer counts upwards, starting with the value in the timer count registers, until

the maximum count value which depends on the selected mode of operation. Timer 3 provides two individual

interrupts upon counter overflow, one for the low-byte and one for the high-byte counter register.

17.3.1

Timer3 Modes Overview

The following table provides an overview of the timer modes together with the reasonable configuration

options in Table 11.

Table 11

Mode

Timer3 Modes

Sub- Operation

Mode

No Sub- 13-bit Timer

0

1

Mode

The timer is essentially an 8-bit counter with a divide-by-32 prescaler.

a

16-bit Timer

The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter.

Data Sheet

59

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Timer3

Table 11

Mode

Timer3 Modes (cont’d)

Sub-

Operation

Mode

1

b

16-bit Timer triggered by an event

The timer registers, TL3 and TH3, are concatenated to form a 16-bit counter, which is

triggered by an event to enable a single shot measurement on a preset channel with the

measurement unit.

2

3

No Sub- 8-bit Timer with auto-reload

Mode

The timer register TL3 is reloaded with a user-defined 8-bit value in TH3 upon overflow.

a

Timer3 operates as two 8-bit timers

The timer registers TL3 and TH3, operate as two separate 8-bit counters.

b

Timer3 operates as Two 8-bit timers for clock measurement

The timer registers, TL3 and TH3 operate as two separate 8-bit counters. In this mode

the LP_CLK2 Low Power Clock can be measured. TL3 acts as an edge counter for the

clock edges and TH3 as a counter which counts the time between the edges.

Data Sheet

60

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Capture/Compare Unit 6 (CCU6)

18

Capture/Compare Unit 6 (CCU6)

18.1

Feature Set Overview

This section gives an overview over the different building blocks and their main features.

Timer 12 Block Features

•

Three capture/compare channels, each channel can be used either as capture or as compare channel

Generation of a three-phase PWM supported (six outputs, individual signals for high-side and low-side

switches)

•

16-bit resolution, maximum count frequency = peripheral clock

Dead-time control for each channel to avoid short-circuits in the power stage

Concurrent update of T12 registers

Center-aligned and edge-aligned PWM can be generated

Single-shot mode supported

Start can be controlled by external events

Capability of counting external events

Multiple interrupt request sources

Hysteresis-like control mode

Timer 13 Block Features

•

One independent compare channel with one output

16-bit resolution, maximum count frequency = peripheral clock

Concurrent update of T13 registers

Can be synchronized to T12

Interrupt generation at period-match and compare-match

Single-shot mode supported

Start can be controlled by external events

Capability of counting external events

Additional Specific Functions

•

Block commutation for brushless DC-drives implemented

Position detection via hall-sensor pattern

Noise filter supported for position input signals

Automatic rotational speed measurement and commutation control for block commutation

Integrated error handling

Fast emergency stop without CPU load via external signal (CTRAP)

Control modes for multi-channel AC-drives

Output levels can be selected and adapted to the power stage

Data Sheet

61

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Capture/Compare Unit 6 (CCU6)

18.2

Introduction

The CCU6 unit is made up of a Timer T12 block with three capture/compare channels and a Timer T13 block

with one compare channel. The T12 channels can independently generate PWM signals or accept capture

triggers, or they can jointly generate control signal patterns to drive DC-motors or inverters.

A rich set of status bits, synchronized updating of parameter values via shadow registers, and flexible

generation of interrupt request signals provide efficient software-control.

Note:

The capture/compare module itself is referred to as CCU6 (capture/compare unit 6). A

capture/compare channel inside this module is referred to as CC6x.

The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be

combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). The

timer T13 can work in compare mode only. The multi-channel control unit generates output patterns which

can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal

modulation.

Data Sheet

62

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Capture/Compare Unit 6 (CCU6)

18.2.1

Block Diagram

CCU6 Module Kernel

Compare

CC60

CC61

CC62

1

T12SUSP

Dead-

Time

Control

Multi-

channel

Control

Debug

Suspend

Trap

Control

T12

T13

1

T13SUSP

f_{CC 6}

Clock

Control

CC63

1

3

2

3

1

SR[3:0]

Interrupt

Control

Input / Output Control

PortControl

CCU6_MCB05506.vsd

P0.x

P1.x

P2.x

Figure 21 CCU6 Block Diagram

Data Sheet

63

Rev. 1.0

2018-01-16

TLE9879-2QXA40

UART1/UART2

19

UART1/UART2

19.1

Features

•

Full-duplex asynchronous modes

–

8-bit or 9-bit data frames, LSB first

fixed or variable baud rate

•

Receive buffered

Multiprocessor communication

Interrupt generation on the completion of a data transmission or reception

Baud-rate generator with fractional divider for generating a wide range of baud rates

Hardware logic for break and synch byte detection

19.2

Introduction

The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive

simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a

previously received byte has been read from the receive register. However, if the first byte still has not been

read by the time reception of the second byte is complete, one of the bytes will be lost. The serial port receive

and transmit registers are both accessed at Special Function Register (SFR) SBUF. Writing to SBUF loads the

transmit register, and reading SBUF accesses a physically separate receive register.

19.2.1

Block Diagram

UART disreq from SCU_DM

RI

TXD

RXD

TXD

SCU_D

M

Interrupt

Control

RXD_0

RXD_1

TI

URIOS

SCU_DM

P0.x

P1.x

P2.x

UART

Module

PortControl

f_UART2

Clock

Control

Baud Rate

Generator

f

BR

Address

Decoder

RXDO_2

SCU_DM

AHB Interface

UART

GPIOs

Figure 22 UART Block Diagram

Data Sheet

64

Rev. 1.0

2018-01-16

TLE9879-2QXA40

UART1/UART2

19.3

UART Modes

The UART can be used in four different modes. In mode 0, it operates as an 8-bit shift register. In mode 1, it

operates as an 8-bit serial port. In modes 2 and 3, it operates as a 9-bit serial port. The only difference between

mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. The variable baud rate is

set by the underflow rate on the dedicated baud-rate generator.

The different modes are selected by setting bits SM0 and SM1 to their corresponding values, as shown in

Table 12.

Table 12

UART Modes

SM1

SM0

Operating Mode

Mode 0: 8-bit shift register

Baud Rate

0

1

0

1

0

1

f_PCLK/2

Mode 1: 8-bit shift UART

Mode 2: 9-bit shift UART

Mode 3: 9-bit shift UART

Variable

f_PCLK/64

Variable

The UART1 is connected to the integrated LIN transceiver, and to GPIO for test purpose. The UART2 is

connected to GPIO only.

Data Sheet

65

Rev. 1.0

2018-01-16

TLE9879-2QXA40

LIN Transceiver

20

LIN Transceiver

20.1

Features

General Functional Features

•

Compliant to LIN2.2 standard, backward compatible to LIN1.3, LIN2.0 and LIN 2.1

Compliant to SAE J2602 (slew rate, receiver hysteresis)

Special Features

•

Measurement of LIN master baudrate via Timer 2

LIN can be used as input/output with SFR bits.

TxD timeout feature (optional, on by default)

Operation Mode Features

•

LIN Sleep Mode (LSLM)

LIN Receive-Only Mode (LROM)

LIN Normal Mode (LNM)

High Voltage Input / Output Mode (LHVIO)

Supported Baud Rates

•

Mode for a transmission up to 10.4 kBaud

Mode for a transmission up to 20 kBaud

Mode for a transmission up to 40 kBaud

Mode for a transmission up to 115.2 kBaud

Slope Mode Features

•

Normal Slope Mode (20 kbit/s)

Low Slope Mode (10.4 kbit/s)

Flash Mode (115.2 kbit/s)

Wake-Up Features

LIN bus wake-up

•

Data Sheet

66

Rev. 1.0

2018-01-16

TLE9879-2QXA40

LIN Transceiver

20.2

Introduction

The LIN Module is a transceiver for the Local Interconnect Network (LIN) compliant to the LIN2.2 standard,

backward compatible to LIN1.3, LIN2.0 and LIN2.1. It operates as a bus driver between the protocol controller

and the physical network. The LIN bus is a single wire, bi-directional bus typically used for in-vehicle networks,

using baud rates between 2.4 kBaud and 20 kBaud. Additionally baud rates up to 115.2 kBaud are

implemented.

The LIN Module offers several different operation modes, including a LIN Sleep Mode and the LIN Normal

Mode. The integrated slope control allows to use several data transmission rates with optimized EMC

performance. For data transfer at the end of line, a Flash Mode up to 115.2 kBaud is implemented. This Flash

Mode can be used for data transfer under special conditions for up to 250 kbit/s (in production environment,

point-to-point communication with reduced wire length and limited supply voltage).

20.2.1

Block Diagram

VS

LIN Transceiver

30 k

LIN_CTRL_STS

LIN-FSM

LIN

CTRL

Driver +

Curr. Limit. +

TSD

TxD_1

from UART

STATUS

GND_LIN

Transmitter

Filter

RxD_1

to UART

Receiver

Filter

LIN_Wake

Sleep Comparator

LIN_Block_Diagram_Customer.vsd

GND_LIN

Figure 23 LIN Transceiver Block Diagram

Data Sheet

67

Rev. 1.0

2018-01-16

TLE9879-2QXA40

High-Speed Synchronous Serial Interface (SSC1/SSC2)

21

High-Speed Synchronous Serial Interface (SSC1/SSC2)

21.1

Features

•

Master and Slave Mode operation

–

Full-duplex or half-duplex operation

•

Transmit and receive buffered

Flexible data format

–

Programmable number of data bits: 2 to 16 bits

Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit (MSB) shift first

Programmable clock polarity: idle low or high state for the shift clock

Programmable clock/data phase: data shift with leading or trailing edge of the shift clock

•

Variable baud rate

Compatible with Serial Peripheral Interface (SPI)

Interrupt generation

–

On a transmitter empty condition

On a “receiver full” condition

On an error condition (receive, phase, baud rate, transmission error)

Data Sheet

68

Rev. 1.0

2018-01-16

TLE9879-2QXA40

High-Speed Synchronous Serial Interface (SSC1/SSC2)

21.2

Introduction

The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and half-duplex serial

synchronous communication. The serial clock signal can be generated by the SSC internally (master mode),

using its own 16-bit baud rate generator, or can be received from an external master (slave mode). Data width,

shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible

devices or devices using other synchronous serial interfaces.

Data is transmitted or received on TXD and RXD lines, which are normally connected to the MTSR

(MasterTransmit/Slave Receive) and MRST (Master Receive/Slave Transmit) pins. The clock signal is output via

line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are

normally connected to the pin SCLK. Transmission and reception of data are double-buffered.

21.2.1

Block Diagram

Figure 24 shows all functional relevant interfaces associated with the SSC Kernel.

MRSTA

MRSTB

EIR

MTSR

SCU_DM

Interrupt

Control

RIR

TIR

MTSRA

MTSRB

P0.x

P1.x

P2.x

SSC

Module

Port

Control

MRST

f_{hw_clk}

Clock

Control

SCLKA

SCLKB

Address

Decoder

SCLK

AHB Interface

Module

ProductInterface

SSC_interface_overview.vsd

Figure 24 SSC Interface Diagram

Data Sheet

69

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Measurement Unit

22

Measurement Unit

22.1

Features

•

1 x 8-bit ADC with 10 Inputs including attenuator allowing measurement of high voltage input signals

Supply Voltage Attenuators with attenuation of VS, VDDP and VDDC.

VBG monitoring of 8-bit ADC to guarantee functional safety requirements.

Bridge Driver Diagnosis Measurement (VDH, VCP).

Temperature Sensor for monitoring the chip temperature and PMU Regulator temperature.

BEMF Comparators for commutation triggering inside BLDC Applications.

Supplement Block with Reference Voltage Generation, Bias Current Generation, Voltage Buffer for NVM

Reference Voltage, Voltage Buffer for Analog Module Reference Voltage and Test Interface.

22.2

Introduction

The measurement unit is a functional unit that comprises the following associated sub-modules:

Table 13

Measurement Functions and Associated Modules

Module

Name

Modules

Functions

Central

Functions Unit

Bandgap reference circuit

The bandgap-reference sub-module provides two

reference voltages

1. a trimmable reference voltage for the 8-bit ADCs. A

local dedicated bandgap circuit is implemented to

avoid deterioration of the reference voltage arising

e.g. from crosstalk or ground voltage shift.

2. the reference voltage for the NVM module

8-bit ADC (ADC2) 8-bit ADC module with 10

input attenuator

5 high voltage full supply range capable inputs

multiplexed inputs, including HV (2.5V...30,7V(FS))

2 medium voltage inputs (0..5V/7V FS).

3 low voltage inputs (0..1.2V/1.6V FS)

(allocation see following overview figure)

10-bit ADC (ADC1) 10-bit ADC module with 8

multiplexed inputs

Five (5V) analog inputs from Port 2.x

14 Bit ADCs

14 Bit Sigma Delta ADC module

Two diffential analog inputs from Port 2.x

(ADC3, ADC4)

VDH Input

Voltage

VDH input voltage attenuator

Scales down V(VDH) to the input voltage range of

ADC1.CH6

Attenuator

Temperature

Sensor

Temperature sensor with two

multiplexed sensing elements:

Generates output voltage which is a linear function of

the local chip (junction) temperature.

•

PMU located sensor

Central chip located sensor

Data Sheet

70

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Measurement Unit

Table 13

Measurement Functions and Associated Modules

Module

Name

Modules

Functions

BEMF -

Comparators

Back Electromotive Force

Comparators

Comparators are used to detect the Back

Electromotive Force (Zero Crossing Event), which can

be used as a commutation trigger for BLDC

applications.

Measurement

Core Module

Digital signal processing and ADC2 1. Generates the control signal for the 8-bit ADC2 and

control unit

the synchronous clock for the switched capacitor

circuits,

2. Performs digital signal processing functions and

provides status outputs for interrupt generation.

22.2.1

Block Diagram

VAGND

VS

GND_VDDEXT VDDEXT

VAREF

P2.0

P2.0_ADC_SEL

0

1

CH0

CH1

CH2

CH3

5

V

OP1

OP2

GND_SENSE

OP

P2.2_ADC_SEL

G = 10/20/40/60

0

1

VREF

10

/

P2.2

P2.3

P2.4

MUX

SFR

A

D

Channel sequencer

CH4

P2.4_ADC_SEL

CH5

CH6

CH7

0

1

ADC 1

P2.5_ADC_SEL

0

1

P2.5

VDH

x 0.226

x 0.166

10 Bit ADC + DPP1

REF- REF+

3rd Order Comb Filter

incl.Decimation

ADC 3

P2.0

P2.2

fully differential

ΣΔ-ADC

1

/

SFR

REF- REF+

3rd Order Comb Filter

incl.Decimation

ADC 4

P2.4

P2.5

fully differential

ΣΔ-ADC

1

/

Sensor-Interface

Programmable

range setting

CH0

1.21

x 0.055

x 0.039

CH1

V

VSD

VCP

x 0.039

x 0.023

x 0.039

x 0.164

x 0.219

CH2

CH3

calibration

with

upper lower

& filter unit

MON

CH4

MUX

CH5

8

/

SFR

A

D

threshold

VDDP

VAREF

detection / interrupt

CH6

CH7

CH8

CH9

ADC 2

PMU-VBG

x 0.75

VDDC

Temperature

Sensor

8 Bit ADC + DPP2

Measurement-Unit

Measurement_Unit_Overview_TLE9879-2_B17.vsd

Figure 25

Measurement Unit-Overview TLE9879-2QXA40

Data Sheet

71

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Measurement Unit

22.2.1.1 Block Diagram BEMF Comparator

V Phase U

W

V

U

VS/2

SH3

SH2

R

Blank Filter

BEMF-Comp

Spike Filter

BEMF OUT

SH1

BEMF IN

t

Measurement-Unit / BEMF Comparators

Figure 26

3 Times BEMF Comparator

Data Sheet

72

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Measurement Core Module (incl. ADC2)

23

Measurement Core Module (incl. ADC2)

23.1

Features

•

8 individually programmable channels split into two groups of user configurable and non user

configurable

•

Individually programmable channel prioritization scheme for measurement unit

Two independent filter stages with programmable low-pass and time filter characteristics for each

channel

•

Two channel configurations:

–

Programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis

Two individually programmable trigger thresholds with limit hysteresis settings

•

Individually programmable interrupts and statuses for all channel thresholds

23.2

Introduction

The basic function of this block is the digital postprocessing of several analog digitized measurement signals

by means of filtering, level comparison and interrupt generation. The measurement postprocessing block

consists of ten identical channel units attached to the outputs of the 10-channel 8-bit ADC (ADC2). It processes

ten channels, where the channel sequence and prioritization is programmable within a wide range.

Data Sheet

73

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Measurement Core Module (incl. ADC2)

23.2.1

Block Diagram

4

/

Measurement Core Module

MUX_SEL<3:0>

Channel Controller

(Sequencer)

ADC2 - SFR

rfu

VS

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

VSD

VCP

1st Order IIR

1

/

+

-

8 Bit ADC

VREF

ADC2_CHx_UPPER_STS

ADC2_CHx_LOWER_STS

+ / -

Calibration Unit:

y= a + (1+b)*x

THy_z_UPPER.

CHx

8

/

10

/

8

/

MON

MUX

A

D

VDDP

1

/

THy_z_LOWER.

CHx

-

VAREF

+

PMU-VBG

VDDC

Digital Signal Processing

Temperature Sensor

TSENSE

Figure 27 Module Block Diagram

23.2.2

Measurement Core Module Modes Overview

The basic function of this unit, is the digital signal processing of several analog digitized measurement signals

by means of filtering, level comparison and interrupt generation. The Measurement Core module processes

ten channels in a quasi parallel process.

As shown in the figure above, the ADC2 postprocessing unit consists of a channel controller (Sequencer), an

10-channel demultiplexer and the signal processing block, which filters and compares the sampled ADC2

values for each channel individually. The channel control block controls the multiplexer sequencing on the

analog side before the ADC2 and on the digital domain after the ADC2. As described in the following section,

the channel sequence can be controlled in a flexible way, which allows a certain degree of channel

prioritization.

This capability can be used e.g. to set a higher priority to supply voltage channels compared to the other

channel measurements. The Measurement Core Module offers additionally two different post-processing

measurement modes for over-/undervoltage detection and for two-level threshold detection.

The channel controller (sequencer) runs in one of the following modes:

“Normal Sequencer Mode” – channels are selected according to the 10 sequence registers which contain

individual enablers for each of the 10 channels.

“Exceptional Interrupt Measurement” – following a hardware event, a high priority channel is inserted into the

current sequence. The current actual measurement is not destroyed.

“Exceptional Sequence Measurement” – following a hardware event, a complete sequence is inserted after

the current measurement is finished. The current sequence is interrupted by the exception sequence.

Data Sheet

74

Rev. 1.0

2018-01-16

TLE9879-2QXA40

10-Bit Analog Digital Converter (ADC1)

24

10-Bit Analog Digital Converter (ADC1)

24.1

Features

The principal features of the ADC1 are:

•

Up to 8 analog input channels (channel 7 reserved for future use)

Flexible results handling

- 8-bit and 10-bit resolution

•

Flexible source selection due to sequencer

- insert one exceptional sequence (ESM)

- insert one interrupt measurement into the current sequence (EIM), single or up to 128 times

- software mode

•

Conversion sample time (separate for each channel) adjustable to adapt to sensors and reference

Standard external reference (VAREF) to support ratiometric measurements and different signal scales

DMA support, transfer ADC conversion results via DMA into RAM

Support of suspend and power saving modes

Result data protection for slow CPU access (wait-for-read mode)

Programmable clock divider

Integrated sample and hold circuitry

Data Sheet

75

Rev. 1.0

2018-01-16

TLE9879-2QXA40

10-Bit Analog Digital Converter (ADC1)

24.2

Introduction

The TLE9879-2QXA40 includes a high-performance 10-bit Analog-to-Digital Converter (ADC1) with eight

multiplexed analog input channels. The ADC1 uses a successive approximation technique to convert the

analog voltage levels from up to eight different sources. The analog input channels of the ADC1 are available

at AN0, AN2 - AN5.

24.2.1

Block Diagram

3

/

MUX_SEL <2:0>

Channel Controller

(Sequencer)

ADC1 - SFR

10

/

ADC1_OUT_CH0

ADC1_OUT_CH1

ADC1_OUT_CH2

ADC1_OUT_CH3

ADC1_OUT_CH4

ADC1_OUT_CH5

ADC1_OUT_CH6

ADC1_OUT_CH7

ADC1_RES_OUT_EIM

P2.0

CH0

CH1

CH2

CH3

ADC1

P2.2

P2.3

P2.4

P2.5

VDH

rfu

10

MUX

A

D

/

MUX

CH4

CH5

CH6

CH7

OP1

OP2

OPA

Figure 28

ADC1 Top Level Block Diagram

As shown in the figure above, the ADC1 postprocessing consists of a channel controller (Sequencer) and an 8-

channel demultiplexer. The channel control block controls the multiplexer sequencing on the analog side

before the ADC1 and on the digital domain after the ADC1. As described in the following section, the channel

sequence can be controlled in a flexible way, which allows a certain degree of channel prioritization.

This capability can be used e.g. to give a higher priority to some channels compared to the other channel

measurements.

Data Sheet

76

Rev. 1.0

2018-01-16

TLE9879-2QXA40

14-Bit Sigma Delta ADC (ADC3 / ADC4)

25

14-Bit Sigma Delta ADC (ADC3 / ADC4)

25.1

Features

Module Features:

•

full differential capacitive input.

14 Bit resolution.

full differential scale: V_diff,lin

extended differential input range with reduced accuracy: V_diff,nonlin

sampling frequency: f_ADC3/4

programmable oversampling ratio: OSR

high supply rejection ratio

internal clock jittering

25.2

Functional Description

The 2 integrated 14 Bit Sigma Delta ADCs are building a Sensor Interface for an external AMR / GMR Sensor. The

application configuration is shown below.

ADC3

VDDEXT

Rfilp

3rd Order Comb Filter

Cfilp

Cfiln

2nd Order

SD-ADC

MR-

sin ᵩ

with programmable

Decimation up to

2048

SFR

Rfiln

C_SMP

Dynamic input impedance due to switch cap architecture : Zi = 1/(2*f_ADC*C_SMP

)

ADC 4

VDDEXT

Rfilp

Rfiln

3rd Order Comb Filter

with programmable

Decimation up to

2048

2nd Order

SD-ADC

Cfilp

Cfiln

MR-

cos ᵩ

SFR

C_SMP

Figure 29 Application of Integrated Sigma Delta ADCs

Data Sheet

77

Rev. 1.0

2018-01-16

TLE9879-2QXA40

14-Bit Sigma Delta ADC (ADC3 / ADC4)

25.2.1

Input Voltage Range of SD ADC

V_in

V_IH,max

V_REF

V_in,com

+2V

Non linear area

V_in,com

+1.875V

linear area

V_diff,lin

max.

V_diff,nonlin

ADCx.P

ADCx.N

Max.

V_in,com

V_diff= |V_ADCx.P-V_ADCx.N

|

V_in,com

–

1.875V

V_in,com

Non linear area

–2V

t

V_IL,min

0V

ADC34_VoltRangeDiff.vsdx

x={3,4}

Figure 30 Input Voltage Range

25.2.2

Interpretation of ADC output code

0x4xxx

0x3FFF

Linear

range

0

0xC001

0x8xxx

V_in

0

V_REF

V

in,com

–2V

in,com

in,

com

in,com

+2V

–1.875V

+1.875V

Differential Analog Input

ADC34_TransferCharDiff.vsdx

Figure 31 ADC output code over input voltage

Data Sheet

78

Rev. 1.0

2018-01-16

TLE9879-2QXA40

High-Voltage Monitor Input

26

High-Voltage Monitor Input

26.1

Features

•

High-voltage input with V_S/2 threshold voltage

Integrated selectable pull-up and pull-down current sources

Wake capability for power saving modes

Level change sensitivity configurable for transitions from low to high, high to low or both directions

26.2

Introduction

This module is dedicated to monitor external voltage levels above or below a specified threshold or it can be

used to detect a wake-up event at the high-voltage MON pin in low-power mode. The input is sensitive to a

input level monitoring, this is available when the module is switched to active mode with the SFR bit EN.

To use the Wake function during low power mode of the IC, the monitoring pin is switched to Sleep Mode via

the SFR bit EN.

26.2.1

Block Diagram

VS

MON

+

-

Filter

to internal

circuitry

MON

Logic

SFR

MONx_Input_Circuit_ext.vsd

Figure 32 Monitoring Input Block Diagram

Data Sheet

79

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Bridge Driver (incl. Charge Pump)

27

Bridge Driver (incl. Charge Pump)

27.1

Features

The MOSFET Driver is intended to drive external normal level NFET transistors in bridge configuration. The

driver provides many diagnostic possibilities to detect faults.

Functional Features

•

External Power NFET Transistor Driver Stage with driver capability for max. 100 nC gate charge @ 25 kHz

switching frequency.

•

Implemented adjustable cross conduction protection.

Supply voltage (VSD) monitoring incl. adjustable over- and undervoltage shutdown with configurable

interrupt signalling.

•

VSD operating range down to 5.4 V

VDS comparators for short circuit detection in on- and off-state

Open-Load detection in off-state

Flexible PWM frequency range, rates above 25 kHz require power dissipation and duty cycle resolution

analysis

27.2

Introduction

The MOSFET Driver Stage can be used for controlling external Power NFET Transistors (normal level). The

module output is controlled by SFR or System PWM Machine (CCU6).

Data Sheet

80

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Bridge Driver (incl. Charge Pump)

27.2.1

Block Diagram

VDH

VCP

PWM-Unit

CCU6

(not part of the module )

Pre-Driver

DRV.TRIM_DRVx.

LSDRV_DS_TFILT_SEL LS_HS_BT_TFILT_SEL

DRV.TRIM_DRVx.

DRV.CTRL3.

DSMONVTH

+

Spike

Filter

Blank

Filter

VDS

-

High Side

Driver

1

0

GHx

R_GGND

VREF

DRV.CTRL1.HSx_PWM

SFR

SHx

1

0

Low Side

Driver

DRV.CTRL1.LSx_PWM

+

Blank

Filter

Spike

Filter

VDS

GLx

SL

-

R

GGND

VREF

DRV.TRIM_DRVx.

LSDRV_DS_TFILT_SEL LS_HS_BT _TFILT_SEL

DRV.CTRL3.

DSMONVTH

PreDriver_Customer.vsd

Figure 33 Driver Module Block Diagram (incl. system connections)

27.2.2

General

The Driver can be controlled in two different ways:

•

In Normal Mode the output stage is fully controllable through the SFR registers CTRLx (x = 1,2,3). Protection

functions such as overcurrent and open-load detection are available.

•

The PWM Mode can also be enabled by the corresponding bit in CTRL1 and CTRL2. The PWM must be

configured in the System PWM Module (CCU6). All protection functions are available in PWM mode as well.

Protection Functions

•

Overcurrent detection and shutdown feature for external MOSFET by Drain Source measurement

Programmable minimum cross current protection time

Open-load detection feature in Off-state for external MOSFET.

Data Sheet

81

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Current Sense Amplifier

28

Current Sense Amplifier

28.1

Features

Main Features

•

Programmable gain settings: G = 10, 20, 40, 60

Differential input voltage: ± 1.5V / G

Wide common mode input range ± 2 V

Low setting time < 1.4 µs

28.2

Introduction

The current sense amplifier in the following figure can be used to measure near ground differential voltages

via the 10-bit ADC. Its gain is digitally programmable through internal control registers.

Linear calibration has to be applied to achieve high gain accuracy, e.g. end-of-line calibration including the

shunt resistor.

The following figure shows how the current sense amplifier can be used as a low-side current sense amplifier

where the motor current is converted to a voltage by means of a shunt resistor R_SH. A differential amplifier

input is used in order to eliminate measurement errors due to voltage drop across the stray resistance R_Stray

and differences between the external and internal ground. If the voltage at one or both inputs is out of the

operating range, the input circuit is overloaded and requires a certain specified recovery time.

In general, the external low pass filter should provide suppression of EMI.

28.2.1

Block Diagram

VBAT

M

V

5V

AREF

VZERO

Motor

Current

Amplifier

configurable

LP Filter

OP2

OP1

R_OPAFILT

Gain: 10, 20, 40, 60

VP

Vzero + (VOP2 -VOP1) * G

10

/

10-bit ADC

R_SH

C_OPAFILT

R_OPAFILT

ADC1_OUT_CH1

VN

CSA_CTRL

R_Stray

Ext. GND

Current_Sense_Amplifier.vsd

Figure 34 Simplified Application Diagram

Data Sheet

82

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Application Information

29

Application Information

29.1

BLDC Driver

The following figure shows the TLE9879-2QXA40 in an electric drive application setup controlling a BLDC

motor.

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Rev. Polarity Protection

L_PF

ILT

VBAT

C_PF

ILT1

C_VDDP2

C_VDDP1

C_VDDC1

C_VDDC2

EMC Filter

D_VS

VDDP VDDC

VS

CP1H

CP1L

CP2H

C_CPS1

C_{VS 2}

C_{VS 1}

C_CPS2

CP2L

VCP

R_MON

IGN

LIN

MON

LIN

R_{VS D}

C_VCP

C_MON

VSD

C_{VS D}

R_VDH

VDH

C_{VD H}

R_GATE

C_LIN

D

S

GND_LIN

G

GH1

SH1

T_H1

C_{PH 1}

VAREF

R_GS

C_GS

C_{VA REF}

D

S

GND_REF

G

C_{EM C P1}

C_{EM CP2}

C_{EM CP3}

T_H2

C_{PH 2}

R_GATE

VDDEXT

R_GS

C_GS

GH2

SH2

C_{VDD_EXT2}

C_{VDD_EXT1}

D

S

G

R_{SI N_P}

R_{SI N_N}

R_{COS_P}

R_{COS_N}

R_GATE

T_H3

VDD

C_PH3

SIN_P

SIN_N

P2.0/ADC3.P

P2.2/ADC3.N

P2.4/ADC4.P

P2.5/ADC4.N

R_GS

C_GS

GH3

SH3

U

V

TLE5009

GND GND

COS_P

COS_N

D

S

R_GATE

G

VGMR

W

P2.3

GL1

GL2

GL3

T_L1

TLE9879-2QXA40

R_GS

C_GS

D

S

M

R_GATE

G

T_L2

R_GS

C_GS

D

S

R_GATE

P0.3

G

T_L3

P0.2

P0.1

R_GS

C_GS

P0.4

P1.4

P1.3

P1.2

P1.1

SL

R_OPAFILT

R_GATE

OP2

R_Shunt

C_OPAFILT

R_GATE

OP1

R_OPAFILT

P1.0

RESET

TMS

P0.0

Debug Connector

GND

R_{TM S}

GND

BLDC System

Figure 35 Simplified Application Diagram Example

Note:

This is a very simplified example of an application circuit and bill of materials. The function must be

verified in the actual application.

Data Sheet

83

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Application Information

Table 14

Symbol

C_VS1

External Components (BOM)

Function

Component

Blocking capacitor at VS pin

Blocking capacitor at VDDP pin

Blocking capacitor at VDDEXT pin

Blocking capacitor at VDDC pin

Blocking capacitor at VAREF pin

Standard C for LIN slave

≥ 100 nF Ceramic, ESR < 1 Ω

> 2.2 µF Elco¹⁾

C_VS2

C_VDDP

C_{VDD_EXT}

C_VDDC

C_VAREF

C_LIN

470 nF + 100 nF Ceramic, ESR < 1 Ω

100nF, Ceramic ESR < 1 Ω

470 nF + 100 nF Ceramic, ESR < 1 Ω

100 nF, Ceramic ESR < 1 Ω

220 pF

C_VSD

Filter C for charge pump end driver 1 µF

C_CPS1

C_CP2S

C_VCP

Charge pump capacitor

Filter C for ISO pulses

Capacitor

220 nF

470 nF

10 nF

3.3 nF

220 µF

100 nF

1 nF

C_MON

C_VDH

C_PH1

Capacitor

C_PH2

Capacitor

C_PH3

Capacitor

C_OPAFILT

C_EMCP1

C_EMCP2

C_EMCP3

Capacitor

1 nF

Capacitor

1 nF

C_PFILT1, C_PFILT2

Capacitor

R_MON

R_VSD

Resistor at MON pin

3.9 kΩ

Limitation of reverse current due to 2 Ω

transient (-2V, 8ms)

max. ratings of the VSD pin has to be

met, alternatively the resistor shall

be replaced by a diode

R_VDH

R_GATE

R_OPAFILT

R_SH1

Resistor

1 kΩ

2 Ω

12 Ω

optional

–

R_SH2

R_SH3

L_PFILT

D_VS

Reverse-polarity protection diode

–

1) The capacitor must be dimensioned so as to ensure that flash operations modifying the content of the flash are never

interrupted (e.g. in case of power loss).

Data Sheet

84

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Application Information

29.2

ESD Immunity According to IEC61000-4-2

Note:

Tests for ESD immunity according to IEC61000-4-2 “Gun test” (150pF, 330Ω) has been performed. The

results and test condition will be available in a test report.

Table 15

ESD “Gun Test”

Performed Test

Result

Unit

Remarks

²⁾positive pulse

ESD at pin LIN, versus

GND¹⁾

> 6

kV

ESD at pin LIN, versus

< -6

kV

²⁾negative pulse

GND¹⁾

1) ESD test “ESD GUN” is specified with external components; see application diagram:

_MON= 100 nF, R_MON= 1 kΩ, C_LIN= 220 pF, C_VS= >20 µF ELCO + 100 nF ESR < 1 Ω, C_VSD= 1 µF, R_VSD= 2 Ω.

C

2) ESD susceptibility “ESD GUN” according to LIN EMC Test Specification, Section 4.3 (IEC 61000-4-2). To be tested by

external test house (IBEE Zwickau)

Data Sheet

85

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30

Electrical Characteristics

This chapter includes all relevant electrical characteristics of the product TLE9879-2QXA40.

30.1

General Characteristics

30.1.1

Absolute Maximum Ratings

Table 16

Absolute Maximum Ratings¹⁾

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Voltages – Supply Pins

Supply voltage – VS

Supply voltage – VSD

V_S

-0.3

–

40

48

V

Load dump

–

P_1.1.1

P_1.1.2

P_1.1.32

V_SD

V_{SD_max_exten}-2.8

Series resistor R_VSD

2.2 Ω, t = 8 ms ²⁾

=

d

Voltage range – VDDP

V_DDP

-0.3

–

5.5

7

V

–

P_1.1.3

V_{DDP_max_exte}-0.3

In case of voltage

P_1.1.41

transients on V_Swith

dV_S/dt ≥ 1V/µs;

nd

duration: t ≤ 150µs;

C

_VDDP≤ 570 nF

Voltage range – VDDEXT

V_DDEXT

-0.3

–

5.5

7

V

–

P_1.1.4

V_{DDEXT_max_e}-0.3

In case of voltage

transients on V_Swith

dV_S/dt ≥ 1V/µs;

P_1.1.42

xtend

duration: t ≤ 150µs;

C

_VDDEXT≤ 570 nF

Voltage range – VDDC

Voltages – High Voltage Pins

Input voltage at LIN

V_DDC

V_LIN

-0.3

-28

–

1.6

V

–

P_1.1.5

–

40

48

–

V

–

3)

P_1.1.7

Input voltage at MON

Input voltage at VDH

V_{MON_maxrate}-28

V_{VDH_maxrate}-2.8

P_1.1.8

4)

5)

P_1.1.38

P_1.1.9

Voltage range at GHx

Voltage range at GHx vs. SHx

Voltage range at SHx

V_GH

-8.0

14

V_GHvsSH

V_SH

–

P_1.1.44

P_1.1.11

P_1.1.13

P_1.1.45

-8.0

14

48

–

6)

Voltage range at GLx

V_GL

–

Voltage range at GLx vs. SL

V_GLvsSL

–

Data Sheet

86

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 16

Absolute Maximum Ratings¹⁾(cont’d)

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

7)

Voltage range at charge pump V_CPx

pins CP1H, CP1L, CP2H, CP2L,

VCP

-0.3

–

48

V

P_1.1.15

Voltages – GPIOs

8)

Voltage on any port pin

V_in

-0.3

–

V_DDP

+0.3

V

V_IN< V_DDPmax

P_1.1.16

P_1.1.35

Current at VCP Pin

Max. current at VCP pin

Injection Current at GPIOs

I_VCP

-15

-5

–

mA

–

9)

Injection current on any port

I_GPIONM

–

5

mA

µA

P_1.1.34

P_1.1.30

P_1.1.36

P_1.1.37

Sum of all injected currents in I_{GPIOAM_sum}-50

Normal Mode

50

5

Sum of all injected currents in I_{GPIOPD_sum}-5000 –

Power Down Mode (Stop Mode)

Sum of all injected currents in I_{GPIOSleep_sum}-5

–

mA

Sleep Mode

Other Voltages

Input voltage VAREF

V_AREF

V_OAI

-0.3

-7

–

V_DDP

+0.3

V

–

P_1.1.17

P_1.1.23

Input voltage

OP1, OP2

7

Temperatures

Junction temperature

Storage temperature

ESD Susceptibility

T_j

-40

-55

–

150

°C

–

P_1.1.18

P_1.1.19

T_stg

ESD susceptibility

all pins

V_ESD1

-2

–

2

kV

V

HBM ¹⁰⁾

HBM ¹¹⁾

P_1.1.20

P_1.1.21

P_1.1.22

P_1.1.28

P_1.1.43

ESD susceptibility

pins MON, VS, VSD vs.GND

V_ESD2

-4

4

ESD susceptibility

pins LIN vs. GND_LIN

V_ESD3

-6

6

HBM ¹⁰⁾

12)

ESD susceptibility CDM

all pins vs. GND

V_{ESD_CDM1}

V_{ESD_CDM2}

-500

-750

500

750

12)

ESD susceptibility CDM

pins 1, 12, 13, 24, 25, 36, 37, 48

(corner pins) vs. GND

V

1) Not subject to production test, specified by design.

Data Sheet

87

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

2) Conditions and min. value is derived from application condition for reverse polarity event.

3) Min voltage -28V with external 3.9kΩ series resistor only.

4) Min voltage -2.8V with external 1kΩ series resistor only.

5) To achieve max. ratings on this pin, Parameter P_1.1.44 has to be taken into account resulting in the following

dependency: V_GH< V_SH+ V_{GHvsSH_min}and additionally V_SH< V_GH+ 0.3V.

6) To achieve max. ratings on this pin, Parameter P_1.1.45 has to be taken into account resulting in the following

dependency: V_GL< V_SL+ V_{GLvsSL_min}and additionally V_SL< V_GL+ 0.3V.

7) These limits can be kept if max current drawn out of pin does not exceed limit of 200 µA.

8) Includes TMS and RESET.

9) Maximum rating for injection current of GPIO with V_INrespected.

10) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001 (1.5kΩ, 100pF)

11) MON with external circuitry of a series resistor of 3.9kΩand 10nF (at connector); VS with an external ceramic capacitor

of 100nF; VSD with an external capacitor of 470nF; VDH with external circuitry of a series resistor of 1kΩ and 3.3nF (at

pin).

12) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JESD22-C101F

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

Data Sheet

88

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.1.2

Functional Range

Table 17

Functional Range

T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ.

Max.

28

Supply voltage in Active Mode

V_{S_AM}

5.5

–

V

–

P_1.2.1

Extended supply voltage in Active

Mode

V_{S_AM_exten}28

40

¹⁾Functional

with parameter

deviation

P_1.2.16

d

Supply voltage in Active Mode for

MOSFET Driver Supply

V_{SD_AM}

5.4

–

28

32

V

P_1.2.18

P_1.2.17

Extended supply voltage in Active

Mode for MOSFET Driver Supply

V_{SD_AM_exte}28

¹⁾³⁾Functional

with parameter

deviation

nd

Specified supply voltage for LIN

Transceiver

V_{S_AM_LIN}5.5

V_{S_AM_LIN}4.8

–

18

28

V

Parameter

Specification

P_1.2.2

Extended supply voltage for LIN

Transceiver

Functional with P_1.2.14

parameter

deviation

2)

Supply voltage in Active Mode with V_{S_AMmin}

reduced functionality

3.0

–

5.5

V

P_1.2.3

(Microcontroller / Flash with full

operation)

Supply voltage in Sleep Mode

V_{S_Sleep}

3.0

-1

–

28

1

V

–

P_1.2.4

P_1.2.5

P_1.2.7

P_1.2.15

P_1.2.9

3)

Supply voltage transients slew rate dV_S/dt

Output sum current for all GPIO pins I_GPIO,sum

V/µs

mA

MHz

°C

3)

4)

-50

5

50

40

150

Operating frequency

Junction temperature

f_sys

T_j

-40

–

1) This operation voltage range is only allowed for a short duration: t_max≤ 400 ms (continuous operation at this voltage

is not allowed), f_sys= 24 MHz, I_VDDP= 10 mA, I_VDDEXT= 5 mA. In addition, the power dissipation caused by the Charge

Pump + MOSFET driver have to be considered.

2) Reduced functionality (e.g. cranking pulse) - Parameter deviation possible.

3) Not subject to production test, specified by design.

4) Function not specified when limits are exceeded.

Data Sheet

89

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.1.3

Current Consumption

Table 18

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Current Consumption @VS pin

Current consumption in I_Vs

Active Mode at pin VS

–

30

35

mA f_sys= 20 MHz

no loads on pins, LIN in recessive

state¹⁾

P_1.3.1

P_1.3.8

Current consumption in I_VSD

Active Mode at pin VSD

–

40

35

mA 20 kHz

PWM on Bridge Driver

Current consumption in I_{SDM_3P}

Slow Down Mode

mA f_sys= 5 MHz; LIN communication P_1.3.19

running; charge pump on

(reverse polarity FET on), external

Low Side FET static on (motor

break mode); VDDEXT on; Sensor

input read via SD ADC and

calculate angle (f_ADC3/4= 5 MHz) all

other module set to power

down;V_S= 13.5V

Current consumption in I_Sleep

Sleep Mode

–

30

90

–

35

µA System in Sleep Mode,

microcontroller not powered,

Wake capable via LIN and MON;

MON connected to VS or GND;

GPIOs open (no loads) or

connected to GND:

P_1.3.3

P_1.3.15

P_1.3.9

T_J= -40°C to 85°C;

V_S= 5.5 V to 18V;²⁾

Current consumption in I_{Sleep_exten}

200

µA System in Sleep Mode,

microcontroller not powered,

Wake capable via LIN and MON;

MON connected to VS or GND;

GPIOs open (no loads) or

connected to GND:

Sleep Mode extended

d

range

T_J= -40°C to 150°C;

V_S= 5.5 V to 18V;²⁾

Current consumption in I_Sleep

Sleep Mode

33

µA System in Sleep Mode,

microcontroller not powered,

Wake capable via LIN and MON;

MON connected to VS or GND;

GPIOs open (no loads) or

connected to GND:

T_J= -40°C to 40°C;

V_S= 5.5 V to 18V;²⁾

Data Sheet

90

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 18

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Current consumption in I_Cyclic

Sleep Mode with cyclic

wake

–

110

µA T_J= -40°C to 85°C;

V_S= 5.5 V to 18V;

P_1.3.4

t

_{Cyclic_ON}= 4ms;

t_{Cyclic_OFF}= 2048 ms;²⁾

Current consumption in I_Stop

Stop Mode

–

110

160

µA System in Stop Mode,

microcontroller not clocked,

Wake capable via LIN and MON;

MON connected to VS or GND;

GPIOs open (no loads) or

connected to GND; T_J= -

40°C to 85°C;

P_1.3.10

P_1.3.20

V_S= 5.5 V to 18V

Current consumption in I_{Stop_extend}

Stop Mode-Extended

temperature range 1

–

600

1800 µA System in Stop Mode,

microcontroller not clocked,

Wake capable via LIN and MON;

MON connected to VS or GND;

GPIOs open (no loads) or

connected to GND;

T_J= -40 °C to 150 °C;

V_S= 5.5 V to 18 V

1) Current on V_S, ADC1/2 active, timer running, LIN active (recessive).

2) Incl. leakage currents form VDH, VSD and MON

Note:

Within the functional range, the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics

table.

Data Sheet

91

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.1.4

Thermal Resistance

Table 19

Thermal Resistance

Parameter

Symbol

Values

Typ.

6

Unit Note or

Test Condition

Number

Min.

Max.

Junction to Soldering Point

Junction to Ambient

R_thJSP

R_thJA

–

K/W ¹⁾measured to

Exposed Pad

P_1.4.1

P_1.4.2

2)

–

33

–

K/W

1) Not subject to production test, specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board. Board: 76.2x114.3x1.5mm3 with 2 inner

copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and

300mm²cooling area on the bottom layer (70µm).

30.1.5

Timing Characteristics

The transition times between the system modes are specified here. Generally the timings are defined from the

time when the corresponding bits in register PMCON0 are set until the sequence is terminated.

Table 20

System Timing¹⁾

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Wake-up over battery

t_start

–

3

ms

Battery ramp-up time to code P_1.5.6

execution

t_startSW

–

1.5

Battery ramp-up time to till P_1.5.1

MCU reset is released; V_S> 3 V

and RESET = 1

Sleep-Exit

t_{sleep - exit}

–

1.5

ms

µs

Rising/falling edge of any

wake-up signal (LIN, MON) till

MCU reset is released;

2)

P_1.5.2

Sleep-Entry

t_{sleep -}

330

P_1.5.3

entry

1) Not subject to production test, specified by design.

2) Wake events during Sleep-Entry are stored and lead to wake-up after Sleep Mode is reached.

Data Sheet

92

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.2

Power Management Unit (PMU)

This chapter includes all electrical characteristics of the Power Management Unit

30.2.1

PMU I/O Supply (VDDP) Parameters

This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the

pad-supply VDDP and the transition times between the system modes are specified here.

Table 21

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

1)

Specified output current

I_VDDP

0

–

50

30

2.2

mA

µF

P_2.1.1

P_2.1.22

P_2.1.2

1)2)

I_VDDP

0

Required decoupling

capacitance

C_VDDP1

0.47

³⁾⁴⁾ESR < 1Ω; the

specified capacitor

value is a typical value.

Required buffer capacitance C_VDDP2

for stability (load jumps)

1

–

2.2

5.1

5.5

µF

V

³⁾⁴⁾The specified

capacitor value is a

typical value.

5)

P_2.1.20

Output voltage including line V_DDPOUT

and load regulation @ Active

Mode

4.9

5.0

50

I

< 90mA; V_S> 5.5V P_2.1.3

I < 70mA; V_S> 5.5V P_2.1.23

load

2)5)

Output voltage including line V_DDPOUT

and load regulation @ Active

Mode

V

5)

Output voltage including line V_DDPOUTST4.5

V

I

is only internal;

P_2.1.21

P_2.1.4

load

and load regulation @ Stop

V_S> 5.5V

OP

Mode

Output drop @ Active Mode

V_SVDDPout

–

400 mV

I_VDDP= 30mA⁶⁾;

3.5V < V_S< 5.0V

Load regulation @ Active Mode V_VDDPLOR-50

–

50

5.4

mV

V

2 ... 90mA; C = 570nF

V_S= 5.5 ... 28V

P_2.1.5

P_2.1.6

P_2.1.7

Line regulation @ Active Mode V_VDDPLIR

-50

Overvoltage detection

V_DDPOV

5.14

V_S> 5.5V; Overvoltage

leads to SUPPLY_NMI

3)7)

Overvoltage detection filter

time

t_{FILT_VDDPO}

–

735

–

µs

P_2.1.24

V

3)

Voltage OK detection

V_DDPOK

–

3

–

V

P_2.1.25

P_2.1.26

Voltage stable detection

range⁸⁾

∆V_DDPSTB- 220

+ 220 mV

Undervoltage reset

V_DDPUV

I_VDDPOC

2.5

91

2.6

–

2.7

V

–

P_2.1.8

P_2.1.9

Overcurrent diagnostic

220 mA

Data Sheet

93

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 21

Electrical Characteristics (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

3)7)

Overcurrent diagnostic filter

time

t_{FILT_VDDPO}

–

27

–

µs

P_2.1.27

P_2.1.28

C

3)7)9)

Overcurrent diagnostic

shutdown time

t_{FILT_VDDPO}

–

290

–

C_SD

1) Specified output current for port supply and additional other external loads already excluding VDDC current.

2) This use case applies to cases where output current on VDDEXT is max. 40 mA.

3) Not subject to production test, specified by design.

4) Ceramic capacitor.

5) Load current includes internal supply.

6) Output drop for IVDDP without internal supply current.

7) This filter time and its variation is derived from the time base t_{LP_CLK}= 1 / f_{LP_CLK}

8) The absolute voltage value is the sum of parameters V_DDP+ ∆V_DDPSTB

9) After t_{FILT_VDDCOC_SD}is passed and the overcurrent condition is still present, the device will enter sleep mode.

.

Data Sheet

94

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.2.2

PMU Core Supply (VDDC) Parameters

This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the

core-supply VDDC and the transition times between the system modes are specified here.

Table 22

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Required decoupling capacitance C_VDDC1

0.1

–

1

µF

¹⁾²⁾ESR < 1Ω; the

specified capacitor

value is a typical

value.

P_2.2.1

Required buffer capacitance for C_VDDC2

stability (load jumps)

0.33

–

1

µF

²⁾the specified

capacitor value is a

typical value.

P_2.2.17

P_2.2.2

Output voltage including line

regulation @ Active Mode

V_DDCOUT1.44 1.5

1.56

1.3

V

I_load< 40mA

Reduced output voltage

including line regulation @ Stop

Mode

V_{DDCOUT_S}0.95 1.1

with internal VDDC P_2.2.23

load only: I_{load_internal}

< 1.5mA

top_Red

Load Regulation @ Active Mode V_DDCLOR

-50

-25

–

50

mV 2 ... 40mA; C =430nF P_2.2.3

mV V_DDP= 2.5 ... 5.5V P_2.2.4

Line regulation @ Active Mode

Overvoltage detection

V_DDCLIR

V_DDCOV

25

1.59 1.62

1.68

V

Overvoltage leads to P_2.2.5

SUPPLY_NMI

1)3)

Overvoltage detection filter time t_{FILT_VDDC}

–

735

–

µs

P_2.2.18

OV

1)

Voltage OK detection range⁴⁾

Voltage stable detection range⁵⁾∆V_DDCSTB- 110

∆V_DDCOK- 280

–

+ 280 mV

+ 110 mV

P_2.2.19

1)

P_2.2.20

Undervoltage reset

V_DDVUV

I_VDDCOC

1.136 1.20

1.264

100

–

V

–

P_2.2.6

P_2.2.7

P_2.2.21

Overcurrent diagnostic

45

–

mA

µs

–

1)3)

Overcurrent diagnostic filter time t_{FILT_VDDC}

27

OC

1)3)6)

Overcurrent diagnostic shutdown t_{FILT_VDDC}

–

290

–

µs

P_2.2.22

time

OC_SD

1) Not subject to production test, specified by design.

2) Ceramic capacitor.

3) This filter time and its variation is derived from the time base t_{LP_CLK}= 1 / f_{LP_CLK}

4) The absolute voltage value is the sum of parameters V_DDC+ ∆V_DDCSTB

5) The absolute voltage value is the sum of parameters V_DDC+ ∆V_DDCOK

6) After t_{FILT_VDDCOC_SD}is passed and the overcurrent condition is still present the device will enter sleep mode.

.

Data Sheet

95

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.2.3

VDDEXT Voltage Regulator (5.0V) Parameters

Table 23

Electrical Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Specified output current

I_VDDEXT

C_VDDEXT1

0

–

20

40

2.2

mA

µF

–

P_2.3.1

1)

0

P_2.3.21

P_2.3.22

Required decoupling

capacitance

0.1

^{3) 2)}ESR < 1 Ω; the

specified capacitor

value is a typical

value.

Required buffer capacitance for C_VDDEXT2

stability (load jumps)

1

–

2.2

µF

³⁾²⁾the specified

capacitor value is a

typical value.

3)

P_2.3.20

P_2.3.3

Output voltage including line

and load regulation

V_DDEXT

4.9

4.8

5.0

50

–

5.1

5.2

V

I

<20mA; V_S>

load

5.5V

Output voltage including line

and load regulation

V_DDEXT

I_load<40mA; V_S> 5.5V P_2.3.23

3)

Output drop @ Active Mode

V_S-V_DDEXT

+300 mV

+400 mV

I

< 20mA;

P_2.3.4

load

3V < V_S< 5.0V

Output drop @ Active Mode

I_load< 40mA;

3V < V_S< 5.0V

P_2.3.14

Load regulation @ Active Mode V_DDEXTLOR

Line regulation @ Active Mode

-50

–

50

–

mV

dB

2 ... 40mA; C =200nF P_2.3.5

V_S= 5.5 ... 28V P_2.3.6

³⁾V_S= 13.5V; f =0 ... P_2.3.7

V_VDDEXTLIR-50

Power supply ripple rejection @ P_SSRVDDEXT50

Active Mode

1KHz; Vr=2Vpp

Overvoltage detection

V_VDDEXTOV

5.18

–

5.4

–

V

V_S> 5.5V

3)4)

P_2.3.8

Overvoltage detection filter time t_{FILT_VDDEXTO}

735

µs

P_2.3.24

V

3)

6)

Voltage OK detection range

Voltage stable detection range⁵⁾∆V_VDDEXTSTB- 220

V_VDDEXTOK

–

3

–

V

P_2.3.25

P_2.3.26

P_2.3.9

–

+ 220 mV

Undervoltage trigger

V_VDDEXTUV

I_VDDEXTOC

2.6

50

–

2.8

–

3.0

160

–

V

Overcurrent diagnostic

mA

µs

–

3)4)

P_2.3.10

P_2.3.27

Overcurrent diagnostic filter

time

t_{FILT_VDDCOC}

27

3)4)

Overcurrent diagnostic

shutdown time

t_{FILT_VDDCOC}

–

290

–

µs

P_2.3.28

_SD

1) This use case requires the reduced utilization of VDDP output current by 20 mA, see P_2.1.22.

2) Ceramic capacitor.

3) Not subject to production test, specified by design.

Data Sheet

96

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

4) This filter time and its variation is derived from the time base t_{LP_CLK}= 1 / f_{LP_CLK}

.

5) The absolute voltage value is the sum of parameters V_DDEXT+ ∆V_DDEXTSTB

.

6) When the condition is met, the Bit VDDEXT_CTRL.bit.SHORT will be set.

Data Sheet

97

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.2.4

VPRE Voltage Regulator (PMU Subblock) Parameters

The PMU VPRE Regulator acts as a supply of VDDP and VDDEXT voltage regulators.

Table 24

Functional Range

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

1)

Specified output current

I_VPRE

–

110

mA

P_2.4.1

1) Not subject to production test, specified by design.

30.2.4.1 Load Sharing Scenarios of VPRE Regulator

The figure below shows the possible load sharing scenarios of VPRE regulator.

VS

VPRE

max. 110 mA

VDDEXT - 5V

1: max. 20 mA

2: max. 40 mA

VDDP - 5V

1: max. 90 mA

2: max. 70 mA

VDDEXT

VDDP

VDDC

C_VDDEXT

C_VDDP

GND (Pin 39)

VDDC - 1.5V

max. 40 mA

CVDDC

GND (Pin 39)

Load Sharing VPRE – Scenarios 1 & 2

Load_Sharing_VPRE.vsd

Figure 36 Load Sharing Scenarios of VPRE Regulator

Data Sheet

98

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.2.5

Power Down Voltage Regulator (PMU Subblock) Parameters

The PMU Power Down voltage regulator consists of two subblocks:

•

Power Down Pre regulator: VDD5VPD

Power Down Core regulator: VDD1V5_PD (Supply used for GPUDATAxy registers)

Both regulators are used as purely internal supplies. The following table contains all relevant parameters:

Table 25

Functional Range

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

VDD1V5_PD

1)

Power-On Reset Threshold

V_{DD1V5_PD_}1.2

–

1.5

V

P_2.5.1

RSTTH

1) Not subject to production test, specified by design

Data Sheet

99

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.3

System Clocks

30.3.1

Oscillators and PLL Parameters

Table 26

Electrical Characteristics System Clocks

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min.

PMU Oscillators (Power Management Unit)

Typ. Max.

Frequency of LP_CLK f_{LP_CLK}

14

18

22

MHz This clock is used at

startup and can be used in

case the PLL fails

P_3.1.1

Frequency of LP_CLK2 f_{LP_CLK2}

70

100

130

kHz This clock is used for cyclic P_3.1.2

wake

CGU Oscillator (Clock Generation Unit Microcontroller)

Short term frequency f_TRIMST

-0.4

–

+0.4

%

²⁾³⁾Within any 10 ms, e.g. P_3.1.3

after synchronization to a

LIN frame (PLL settings

deviation¹⁾

untouched within 10 ms)

Absolute accuracy

f_TRIMABSA

-1.5

–

+1.5

10

%

Including temperature and P_3.1.4

lifetime deviation

CGU-OSC Start-up time t_OSC

µs

³⁾Startup time OSC from

Sleep Mode, power supply

stable

P_3.1.5

PLL (Clock Generation Unit Microcontroller) ³⁾

VCO frequency range f_VCO-0

Mode 0

48

96

4

–

112

160

MHz VCOSEL =”0”

MHz VCOSEL =”1”

P_3.1.6

P_3.1.7

VCO frequency range f_VCO-1

Mode 1

Input frequency range f_OSC

16

80

38

MHz

–

P_3.1.8

Output freq. range

f_PLL

0.04687 –

P_3.1.10

P_3.1.11

Free-running

f_{VCOfree_0}

–

MHz VCOSEL =”0”

frequency Mode 0

Free-running

frequency Mode 1

f_{VCOfree_1}

t_high/low

–

76

–

MHz VCOSEL =”1”

P_3.1.12

P_3.1.13

Input clock high/low

time

10

ns

–

Peak period jitter

Accumulated jitter

Lock-in time

t_jp

-500

–

500

5

ps

ns

µs

⁴⁾for K=1

–

P_3.1.14

P_3.1.15

P_3.1.16

jacc

t_L

–

200

Data Sheet

100

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

1) The typical oscillator frequency is 5 MHz

2) V_DDC= 1.5 V, T_j= 25°C

3) Not subject to production test, specified by design.

4) This parameter is valid for PLL operation with an external clock source and thus reflects the real PLL performance.

Data Sheet

101

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.4

Flash Memory

This chapter includes the parameters for the 128 kByte embedded flash module.

30.4.1

Flash Parameters

Table 27

Flash Characteristics¹⁾

V_S= 3.0 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit

Note or

Number

Test Condition

Min. Typ. Max.

Programming time per 128 byte t_PR

–

3²⁾

3.5

ms

3V < V_S< 28V

P_4.1.1

page

Erase time per sector/page

Data retention time

t_ER

–

4²⁾

–

4.5

–

ms

3V < V_S< 28V

P_4.1.2

P_4.1.3

t_RET

20

years

1,000 erase /

program cycles

Data retention time

t_RET

50

–

years

1,000 erase /

program cycles

T_j= 30°C³⁾

P_4.1.9

Flash erase endurance for user

sectors

N_ER

30

10

32

–

kcycles Data retention

time 5 years

cycles ⁴⁾Data retention P_4.1.5

P_4.1.4

Flash erase endurance for

security pages

N_SEC

N_DD

time 20 years

5)

Drain disturb limit

kcycles

P_4.1.6

1) Not subject for production test, specified by design.

2) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few

system clock cycles. The requirement is only relevant for extremely low system frequencies.

3) Derived by extrapolation of lifetime tests.

4) T_j= 25 °C.

5) This parameter limits the number of subsequent programming operations within a physical sector without a given

page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly.

For normal sector erase/program cycles this limit will not be violated. For data sectors the integrated EEPROM

emulation firmware routines handle this limit automatically, for wordline erases in code sectors (without EEPROM

emulation) it is recommended to execute a software based refresh, which may make use of the integrated random

number generator NVMBRNG to statistically start a refresh.

Data Sheet

102

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.5

Parallel Ports (GPIO)

30.5.1

Description of Keep and Force Current

V_DDP

keeper

current

PU Device

PUDSEL

P1.x

P0.x

\PUDSEL

keeper

current

PD Device

V_SS

Pull-Up-Down.vsd

Figure 37 Pull-Up/Down Device

UGPIO

Logical "1"

7.5 kOhm (equivalent)

(1.5V / 200uA)

V_IH- V_DDP

V_IL- V_DDP

Undefined

Logical "0"

2.33 kOhm (equivalent)

(3.5V / 1.5mA)

I

-I_PLF

-I_PLK

Current_Diag.vsd

Figure 38 Pull-Up Keep and Forced Current

Data Sheet

103

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

UGPIO

Logical "1"

Undefined

Logical "0"

2.33 kOhm (equivalent)

(3.5V / 1.5mA)

V_IH

V_IL

7.5 kOhm (equivalent)

(1.5V / 200uA)

I

I_PLK

I_PLF

Current_Diag-Pull_down.vsd

Figure 39 Pull-Down Keep and Force Current

30.5.2

DC Parameters of Port 0, Port 1, TMS and Reset

Note:

Operating Conditions apply.

Keeping signal levels within the limits specified in this table ensures operation without overload

conditions. For signal levels outside these specifications, also refer to the specification of the

maximum allowed ocurrent which can be taken out of VDDP.

Table 28

Current Limits for Port Output Drivers¹⁾

Port Output Driver Mode

Maximum Output Current Maximum Output Current Number

(I_OLmax, - I_OHmax)(I_OLnom, - I_OHnom)

V_DDP≥ 4.5V 2.6V < V_DDP< V_DDP≥ 4.5V 2.6V < V_DDP

<

4.5V

Strong driver²⁾

Medium driver³⁾

Weak driver³⁾

5 mA

3 mA

1.6 mA

1.0 mA

0.25 mA

1.0 mA

0.8 mA

0.15 mA

P_5.1.15

P_5.1.1

P_5.1.2

3 mA

1.8 mA

0.3 mA

0.5 mA

1) Not subject to production test, specified by design.

2) Not available for port pins P0.4, P1.0, P1.1 and P1.2

3) All P0.x and P1.x

Table 29

DC Characteristics Port0, Port1

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

HYS_{P0_P1}0.11 x V_DDP

Typ. Max.

Input hysteresis

–

V

¹⁾Series

P_5.1.5

resistance = 0 Ω;

4.5V ≤ V_DDP≤ 5.5V

Input hysteresis

HYS_{P0_P1_}

–

0.09 x

–

V

¹⁾Series

P_5.1.16

V_DDP

resistance = 0 Ω;

2.6V ≤ V_DDP≤ 4.5V

exend

Data Sheet

104

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 29

DC Characteristics Port0, Port1 (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Input low voltage

Input high voltage

V_IL

-0.3

–

0.3 x V_DDP

V

²⁾4.5V ≤ V_DDP

5.5V

¹⁾2.6V ≤ V_DDP

4.5V

²⁾4.5V ≤ V_DDP

5.5V

¹⁾2.6V ≤ V_DDP

4.5V

≤

P_5.1.3

P_5.1.17

P_5.1.4

P_5.1.18

V_{IL_extend}-0.3

0.42 x

V_DDP

–

V_IH

0.7 x V_DDP

–

V_DDP+ 0.3

V_{IH_extend}

–

0.52 x V_DDP+ 0.3

V_DDP

3) 4)

Output low voltage

Output high voltage

Input leakage current

V_OL

V_OH

–

1.0

0.4

–

V

I

≤ I_OLmax

≤ I_OLnom

≥ I_OHmax

≥ I_OHnom

P_5.1.6

P_5.1.7

P_5.1.8

P_5.1.9

OL

OH

3) 5)

3) 4)

3) 5)

–

V_DDP- 1.0

V_DDP- 0.4

–

I_{OZ_extend1}-500

+500

nA -40°C ≤ T_J≤ 25°C, P_5.1.20

0.45 V < V_IN

< V_DDP

Input leakage current

I_OZ1

-5

–

+5

µA ⁶⁾25°C < T_J≤ 85°C, P_5.1.10

0.45 V < V_IN

< V_DDP

I_{OZ_extend2}-15

+15

µA 85°C < T_J

≤ 150°C,

0.45 V < V_IN

< V_DDP

P_5.1.11

7)

Pull level keep current

Pull level force current

I_PLK

I_PLF

C_IO

-200

–

+200

+1.5

10

µA

mA

pF

V

≥ V_IH(up)

P_5.1.12

P_5.1.13

P_5.1.14

V

_PIN≤ V_IL(dn)

7)

-1.5

–

V

≤ V_IL(up)

V

_PIN≥ V_IH(dn)

1)

Pin capacitance

Reset Pin Timing

Reset Pin Input Filter Time t_{filt_RESET}

–

5

–

µs

P_5.1.19

1) Not subject to production test, specified by design.

2) Tested at V_DDP= 5V, specified for 4.5V < V_DDP< 5.5V.

3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for

pin groups must be respected.

4) Tested at 4.9V < V_DDP< 5.1V, I_OL= 4mA, I_OH= -4mA, specified for 4.5V < V_DDP< 5.5V.

5) As a rule, with decreasing output current the output levels approach the respective supply level (V_OL→GND, V_OH→V_DDP).

Tested at 4.9V < V_DDP< 5.1V, I_OL= 1mA, I_OH= -1mA.

Data Sheet

105

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

6) The given values are worst-case values. In production tests, this leakage current is only tested at 150°C; other values

are ensured by correlation. For derating, please refer to the following descriptions:

Leakage derating depending on temperature (T_J= junction temperature [°C]):

I

_OZ= 0.05 × e^{(1.5 + 0.028×TJ)}[µA]. For example, at a temperature of 95°C the resulting leakage current is 3.2 µA.

Leakage derating depending on voltage level (DV = V_DDP- V_PIN[V]):

_OZ= I_OZtempmax- (1.6 × DV) [µA]

I

This voltage derating formula is an approximation which applies for maximum temperature.

7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the

default pin level: V_PIN≥ V_IHfor a pull-up; V_PIN≤ V_ILfor a pull-down.

Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the

enabled pull device: V_PIN≤ V_ILfor a pull-up; V_PIN≥ V_IHfor a pull-down.

These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general

purpose IO pins.

Data Sheet

106

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.5.3

DC Parameters of Port 2

These parameters apply to the IO voltage range, 4.5 V ≤ V_DDP≤ 5.5 V.

Note:

Operating Conditions apply.

Keeping signal levels within the limits specified in this table ensures operation without overload

conditions. For signal levels outside these specifications, also refer to the specification of the

overload current I_OV

.

Table 30

DC Characteristics Port 2

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ. Max.

Input low voltage

Input high voltage

Input hysteresis

V_IL

-0.3

–

0.3 x V_DDP

V

¹⁾4.5V ≤ V_DDP

5.5V

²⁾2.6V ≤ V_DDP

4.5V

¹⁾4.5V ≤ V_DDP

5.5V

²⁾2.6V ≤ V_DDP

4.5V

≤

P_5.2.1

P_5.2.10

P_5.2.2

P_5.2.11

P_5.2.3

V_{IL_extend}-0.3

0.42 x

V_DDP

–

V_IH

0.7 x V_DDP

–

V_DDP+ 0.3

V_{IH_extend}

HYS_P2

–

0.52 x V_DDP+ 0.3

V_DDP

0.11 x V_DDP

–

²⁾Series

resistance = 0 Ω;

4.5V ≤ V_DDP≤ 5.5V

Input hysteresis

HYS_{P2_ext}

–

0.09 x

V

²⁾Series

P_5.2.12

V_DDP

resistance = 0 Ω;

2.6V ≤ V_DDP< 4.5V

end

Input leakage current

Pull level keep current

Pull level force current

I_OZ2

I_PLK

I_PLF

C_IO

-400

-30

-750

–

+400

+30

+750

10

nA T_J≤ 85°C,

0 V < V_IN< V_DDP

P_5.2.4

P_5.2.5

P_5.2.6

P_5.2.7

3)

µA

pF

V

≥ V_IH(up)

V_PIN≤ V_IL(dn)

3)

V

≤ V_IL(up)

V_PIN≥ V_IH(dn)

2)

Pin capacitance

(digital inputs/outputs)

1) Tested at V_DDP= 5V, specified for 4.5V < V_DDP< 5.5V.

2) Not subject to production test, specified by design.

3) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the

default pin level: V_PIN≥ V_IHfor a pull-up; V_PIN≤ V_ILfor a pull-down.

Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the

enabled pull device: V_PIN≤ V_ILfor a pull-up; V_PIN≥ V_IHfor a pull-down.

Data Sheet

107

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.6

LIN Transceiver

30.6.1

Electrical Characteristics

Table 31

Electrical Characteristics LIN Transceiver

V_s= 5.5V to 18V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Bus Receiver Interface

Receiver threshold

voltage, recessive to

dominant edge

V_{th_dom}0.4 ×V_S0.45 ×V_S0.53 x V_S

V

SAE J2602

P_6.1.1

Receiver dominant state V_BUSdom-27

–

0.4 ×V_S

V

LIN Spec 2.2 (Par. 17) P_6.1.2

SAE J2602 P_6.1.3

Receiver threshold

voltage, dominant to

recessive edge

V_{th_rec}

0.47 x V 0.55 ×V_S0.6 ×V_S

S

Receiver recessive state

Receiver center voltage

V_BUSrec0.6 ×V_S

–

1.15 ×V_S

V

¹⁾LIN Spec 2.2 (Par. 18) P_6.1.4

²⁾LIN Spec 2.2 (Par. 19) P_6.1.5

V_{BUS_CNT}0.475

× V_S

0.5 ×V_S0.525

× V_S

Receiver hysteresis

V_HYS

0.07 V_S0.12 ×V_S0.175

× V_S

V

³⁾LIN Spec 2.2 (Par. 20) P_6.1.6

Wake-up threshold

voltage

V_BUS,wk0.4 ×V_S0.5 ×V_S0.6 ×V_S

V

–

P_6.1.7

Dominant time for bus

wake-up (internal analog

filter delay)

t_WK,bus

3

–

15

µs

The overall dominant P_6.1.8

time for bus wake-up is

a sum of t_WK,bus

+

adjustable digital filter

time. The digital filter

time can be adjusted

by

PMU.CNF_WAKE_FILTE

R.CNF_LIN_FT;

Bus Transmitter Interface

Bus recessive output

voltage

V_BUS,ro0.8 ×V_S

V_BUS,do

–

V_S

V

V_TxD= high Level

P_6.1.9

Bus dominant output

voltage

–

0.22 ×V_S

Driver Dominant

Voltage

P_6.1.78

R_L= 500 Ohm

Data Sheet

108

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 31

Electrical Characteristics LIN Transceiver (cont’d)

V_s= 5.5V to 18V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Bus short circuit current

I_BUS,sc

40

100

150

mA Current Limitation for P_6.1.10

driver dominant state

driver on

V

_BUS= 18 V; LIN Spec 2.2

(Par. 12)

Bus short circuit filter time t_BUS,sc

–

5

–

µs

⁶⁾The overall bus short P_6.1.71

circuit filter time is a

sum of t_BUS,sc+ digital

filter time. The digital

filter time is 4 µs (typ.)

Leakage current (loss of

ground)

I_{BUS_NO_}-1000 -450

1000

20

–

µA V_S= 12 V; 0 < V_BUS< 18 V; P_6.1.11

LIN Spec 2.2 (Par. 15)

GND

Leakage current

Bus pull-up resistance

I_{BUS_NO_}

–

10

–

µA V_S= 0 V; V_BUS= 18 V;

P_6.1.12

P_6.1.13

P_6.1.14

LIN Spec 2.2 (Par. 16)

BAT

I_{BUS_PAS_}-1

mA V_S= 18 V; V_BUS= 0 V;

LIN Spec 2.2 (Par. 13)

dom

I_{BUS_PAS_}

–

20

47

µA V_S= 8 V; V_BUS= 18 V;

LIN Spec 2.2 (Par. 14)

rec

R_BUS

20

30

kΩ Normal mode LIN Spec P_6.1.15

2.2 (Par. 26)

AC Characteristics - Transceiver Normal Slope Mode

Propagation delay

bus dominant to RxD LOW

t_d(L),R

0.1

–

6

2

–

µs

LIN Spec 2.2

(Param. 31)

P_6.1.16

P_6.1.17

P_6.1.18

P_6.1.19

Propagation delay

bus recessive to RxD HIGH

t_d(H),R

0.1

LIN Spec 2.2

(Param. 31)

Receiver delay symmetry t_sym,R

-2

t_sym,R= t_d(L),R- t_d(H),R;

LIN Spec 2.2 (Par. 32)

⁴⁾duty cycle 1

TH_Rec(max) = 0.744 ×V_S;

TH_Dom(max) =

Duty cycle D1

Normal Slope Mode

(for worst case at 20 kbit/s)

t_duty1

0.396

0.581 ×V_S; V_S= 5.5 …

18 V;

t

_bit= 50 µs;

D1 = t_{bus_rec(min)}/2 t_bit

LIN Spec 2.2 (Par. 27)

;

Data Sheet

109

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 31

Electrical Characteristics LIN Transceiver (cont’d)

V_s= 5.5V to 18V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Duty cycle D2

t_duty2

–

0.581

⁴⁾duty cycle 2

P_6.1.20

Normal Slope Mode

(for worst case at 20 kbit/s)

TH_Rec(min) = 0.422 ×V_S;

TH_Dom(min) = 0.284 ×V_S;

V_S= 5.5 … 18 V;

t_bit= 50 µs;

D2 = t_{bus_rec(max)}/2 t_bit

;

LIN Spec 2.2 (Par. 28)

AC Characteristics - Transceiver Low Slope Mode

Propagation delay

bus dominant to RxD LOW

t_d(L),R

0.1

–

6

2

–

µs

LIN Spec 2.2

(Param. 31)

P_6.1.21

P_6.1.22

P_6.1.23

P_6.1.24

Propagation delay

bus recessive to RxD HIGH

t_d(H),R

0.1

LIN Spec 2.2

(Param. 31)

Receiver delay symmetry t_sym,R

-2

t_sym,R= t_d(L),R- t_d(H),R;

LIN Spec 2.2 (Par. 32)

⁴⁾duty cycle 3

TH_Rec(max) = 0.778 ×V_S;

TH_Dom(max) =

Duty cycle D3

(for worst case at

10.4 kbit/s)

t_duty1

0.417

0.616 ×V_S; V_S= 5.5 …

18 V;

t_bit= 96 µs;

D3 = t_{bus_rec(min)}/2 t_bit

;

LIN Spec 2.2 (Par. 29)

Duty cycle D4

(for worst case at

10.4 kbit/s)

t_duty2

–

0.590

⁴⁾duty cycle 4

TH_Rec(min) = 0.389 ×V_S;

TH_Dom(min) = 0.251 ×V_S;

V_S= 5.5 … 18 V;

P_6.1.25

t_bit= 96 µs;

D4 = t_{bus_rec(max)}/2 t_bit

;

LIN Spec 2.2 (Par. 30)

AC Characteristics - Transceiver Fast Slope Mode

Propagation delay

bus dominant to RxD LOW

t_d(L),R

0.1

-1.5

–

6

µs

–

P_6.1.26

P_6.1.27

P_6.1.28

Propagation delay

bus recessive to RxD HIGH

t_d(H),R

6

Receiver delay symmetry t_sym,R

1.5

t_sym,R= t_d(L),R- t_d(H),R;

AC Characteristics - Flash Mode

Propagation delay

bus dominant to RxD LOW

t_d(L),R

0.1

–

6

µs

–

P_6.1.31

P_6.1.32

Propagation delay

t_d(H),R

bus recessive to RxD HIGH

Data Sheet

110

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 31

Electrical Characteristics LIN Transceiver (cont’d)

V_s= 5.5V to 18V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

-1.0

Max.

1.5

–

Receiver delay symmetry t_sym,R

–

µs

t_sym,R= t_d(L),R- t_d(H),R

⁵⁾duty cycle D7

;

P_6.1.33

P_6.1.34

Duty cycle D7 (for worst

case at 115 kbit/s)

for +1 µs Receiver delay

symmetry

t_duty1

0.399

TH_Rec(max) = 0.744 ×V_S;

TH_Dom(max) =

0.581 ×V_S; V_S= 13.5 V;

t_bit= 8.7 µs;

D7 = t_{bus_rec(min)}/2 t_bit

;

Duty cycle D8 (for worst

case at 115 kbit/s)

for +1 µs Receiver delay

symmetry

t_duty2

–

0.578

⁵⁾duty cycle 8

TH_Rec(min) = 0.422 ×V_S;

TH_Dom(min) =

P_6.1.35

0.284 ×V_S;V_S= 13.5 V;

t_bit= 8.7 µs;

D8 = t_{bus_rec(max)}/2 t_bit

;

6)

LIN input capacity

C_{LIN_IN}

t_timeout

–

6

15

12

30

20

pF

P_6.1.69

P_6.1.36

TxD dominant time out

ms V_TxD= 0 V

Thermal Shutdown (Junction Temperature)

6)

Thermal shutdown temp. T_jSD

Thermal shutdown hyst. ∆T

190

–

200

10

215

–

°C

P_6.1.65

P_6.1.66

6)

K

1) Maximum limit specified by design.

2) V_{BUS_CNT}= (V_{th_dom}+V_{th rec})/2

3) V_HYS= V_BUSrec- V_BUSdom

4) Bus load concerning LIN Spec 2.2:

Load 1 = 1 nF / 1 kΩ = C_BUS/ R_BUS

Load 2 = 6.8 nF / 660 Ω = C_BUS/ R_BUS

Load 3 = 10 nF / 500 Ω = C_BUS/ R_BUS

5) Bus load

Load 1 = 1 nF / 500 Ω = C_BUS/ R_BUS

6) Not subject to production test, specified by design.

Data Sheet

111

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.7

High-Speed Synchronous Serial Interface

30.7.1

SSC Timing Parameters

The table below provides the SSC timing in the TLE9879-2QXA40.

Table 32 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

¹⁾2 * T_SSC

10

Typ.

Max.

2)

SCLK clock period

t₀

t₁

t₂

t₃

–

V

> 2.7 V

P_7.1.1

P_7.1.2

P_7.1.3

P_7.1.4

DDP

MTSR delay from SCLK

MRST setup to SCLK

MRST hold from SCLK

ns

10

15

1) T_SSCmin= T_CPU= 1/f_CPU. If f_CPU= 20 MHz, t₀= 100 ns. T_CPUis the CPU clock period.

2) Not subject to production test, specified by design.

t₀

SCLK¹⁾

t₁

1)

MTSR

t₂

t₃

Data

valid

MRST¹⁾

t₁

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_Tmg1

Figure 40 SSC Master Mode Timing

Data Sheet

112

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.8

Measurement Unit

30.8.1

System Voltage Measurement Parameters

Table 33

Supply Voltage Signal Conditioning

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Measurement output

voltage range @ VAREF5

V_A5

0

–

5

V

–

P_8.1.15

P_8.1.16

Measurement output

voltage range @

VAREF1V2

V_A1V2

0

–

1.23

Battery / Supply Voltage Measurement

Input to output voltage ATT_{VS_1}

attenuation:

V_S

–

3

0.055

–

SFR setting 1

P_8.1.41

P_8.1.1

Nominal operating input V_S,range1

voltage range V_S

22

V

¹⁾SFR setting 1;

Max. value corresponds

to typ. ADC full scale

input; 3V < V_S< 28V

Accuracy of V_Safter

calibration

V_S,range1

-220

–

220 mV SFR setting 1, V_S= 5.5 V P_8.1.70

to 18V

Input to output voltage ATT_{VS_2}

attenuation:

V_S

0.039

–

SFR setting 2

P_8.1.42

P_8.1.40

Nominal operating input V_S,range2

voltage range V_S

3

–

31

V

¹⁾SFR setting 2;

Max. value corresponds

to typ. ADC full scale

input 3V < V_S< 28V

Accuracy of V_Safter

V_S,range2

-370

–

370 mV SFR setting 2, V_S= 5.5V to P_8.1.44

calibration

18V

Driver Supply Voltage Measurement V_SD

Input to output voltage ATT_VSD

–

0.039

–

P_8.1.21

attenuation:

V_SD

1)

Nominal operating input V_SD,range

voltage range V_SD

2.5

–

31

V

P_8.1.2

Accuracy of V_SDsense

∆V_SD

-440

440 mV V_S= 5.5V to 18V

P_8.1.47

after calibration

Charge Pump Voltage Measurement V_CP

Data Sheet

113

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 33

Supply Voltage Signal Conditioning (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Input to output voltage ATT_VCP

–

0.023

–

P_8.1.56

attenuation:

V_CP

1)

Nominal operating input V_CP,range

voltage range V_CP

2.5

–

52

V

P_8.1.7

Accuracy of V_CPsense

∆V_CP

-747

747 mV V_S= 5.5V to 18V

P_8.1.62

after calibration

Monitoring Input Voltage Measurement V_MON

Input to output voltage ATT_VMON

–

0.039

–

P_8.1.49

attenuation:

V_MON

1)

Nominal operating input V_MON,range

voltage range V_MON

2.5

–

31

V

P_8.1.8

Accuracy of V_MONsense

∆V_MON

-440

440 mV V_S= 5.5V to 18V

P_8.1.68

after calibration

Pad Supply Voltage Measurement V_VDDP

Input-to-output voltage ATT_VDDP

–

0.164

–

P_8.1.33

attenuation:

V_DDP

1)

Nominal operating input V_DDP,range

voltage range V_DDP

0

–

7.50

V

P_8.1.50

P_8.1.5

Accuracy of V_DDPsense

∆V_{DDP_SENSE}

-105

105 mV ²⁾V_S= 5.5 to 18V

after calibration

10-Bit ADC Reference Voltage Measurement V_AREF

Input to output voltage ATT_VAREF

–

0.219

–

P_8.1.22

attenuation:

V_AREF

1)

Nominal operating input V_AREF,range

voltage range V_AREF

0

–

5.62

79

V

P_8.1.51

P_8.1.48

Accuracy of V_AREFsense

∆V_AREF

-79

mV V_S= 5.5V to 18V

after calibration

8-Bit ADC Reference Voltage Measurement V_BG

Input-to-output voltage ATT_VBG

attenuation:

V_BG

–

0.75

–

P_8.1.57

P_8.1.52

1)

Nominal operating input V_BG,range

voltage range V_BG

0.8

–

1.64

V

Data Sheet

114

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 33

Supply Voltage Signal Conditioning (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Value of ADC2-V_BG

measurement after

calibration

V_{BG_PMU}

1.01 1.07

1.18

V

P_8.1.73

Core supply Voltage Measurement V_DDC

Input-to-output voltage ATT_VDDC

–

0.75

–

P_8.1.34

attenuation:

V_DDC

1)

Nominal operating input V_DDC,range

voltage range V_DDC

0.8

-22

–

1.64

22

V

P_8.1.53

P_8.1.6

Accuracy of V_DDCsense

∆V_{DDC_SENSE}

mV V_S= 5.5 to 18V

after calibration

VDH Input Voltage Measurement V_VDH10BITADC

VDH Input to output

voltage attenuation:

ATT_{VDH_1}

ATT_{VDH_2}

ATT_{VDH_3}

–

-

0.166

0.224

0.226

–

SFR setting 1

SFR setting 2

P_8.1.64

P_8.1.65

P_8.1.75

P_8.1.66

VDH Input to output

voltage attenuation:

–

VDH Input to output

voltage attenuation:

-

¹⁾SFR setting 2

T_j= -40..85°C

Nominal operating input V_VDH,range1

–

30

SFR setting 1

voltage range V_VDH, Range

1

Nominal operating input V_VDH,range2

–

20

SFR setting 2

P_8.1.67

voltage range V_VDH, Range

2

V_VDH10-bit ADC, Range 1 ∆V_VDHADC10B

-300

-200

–

300 mV V_DH= 5.5 to 17.5V,

P_8.1.39

P_8.1.71

T_j= -40..150°C

1)

V_VDH10-bit ADC, Range 3 ∆V_VDHADC10B

200 mV

V = 5.5V to 17.5V,

DH

T_j= -40..85°C

ATT_{VDH_3}

V_VDH10-bit ADC, Range 2 ∆V_{VDHADC10B_ext}-400

–

400 mV V_DH= 5.5V to 17.5V,

T_j= -40..150°C

P_8.1.74

P_8.1.3

end_T

10-Bit ADC measurement R_{in_VDH,measure}200 390

470 kΩ PD_N=1 (on-state)

input resistance for VDH

Measurement input

I_{leak_VDH, measure}-0.05

–

2.0 µA PD_N=0 (off-state),

P_8.1.10

leakage current for V_VDH

1) Not subject to production test, specified by design.

2) Accuracy is valid for a calibrated device.

Data Sheet

115

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.8.2

Central Temperature Sensor Parameters

Table 34

Electrical Characteristics Temperature Sensor Module

V_S= 3.0 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Output voltage V_TEMPat

T₀=273 K (0°C)

a

–

0.666

–

V

¹⁾T₀=273 K (0°C)

P_8.2.2

1)

Temperature sensitivity b

Accuracy_1

b

–

2.31

–

mV/K

°C

P_8.2.4

P_8.2.5

P_8.2.6

P_8.2.7

Acc_1

Acc_2

Acc_3

-10

-5

–

10

5

²⁾¹⁾-40°C < T_j< 85°C

²⁾¹⁾125°C < T_j< 150°C

²⁾¹⁾85°C < T_j< 125°C

Accuracy_2

°C

Accuracy_3

°C

1) Not subject to production test, specified by design

2) Accuracy with reference to on-chip temperature calibration measurement, valid for Mode1

Data Sheet

116

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.8.3

ADC2-VBG

30.8.3.1 ADC2 Reference Voltage VBG

Table 35

DC Specifications

V_S= 3.0 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

1)

Reference Voltage

V_BG

1.199

1.211

1.223

V

P_8.3.1

1) Not subject to production test, specified by design

30.8.3.2 ADC2 Specifications

Table 36

DC Specifications

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

8

Unit

Note or

Test Condition

Number

Min.

Max.

–

Resolution

RES

–

Bits

LSB

Full

P_8.3.18

P_8.3.19

Guaranteed offset error EA_{OFF_8Bi}-2.0

±0.3

2.0

not calibrated

t

Gain error

EA_{Gain_8B}-2.0

±0.5

±0

2.0

0.8

1.2

%FSR

LSB

not calibrated

P_8.3.20

P_8.3.21

P_8.3.22

it

Differential non-linearity EA_{DNL_8Bi}-0.8

(DNL)

Full

–

t

Integral non-linearity

(INL)

EA_{INL_8Bit}-1.2

±0

LSB

Data Sheet

117

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.9

ADC1 Reference Voltage - VAREF

30.9.1

Electrical Characteristics VAREF

Table 37

Electrical Characteristics VAREF

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Required buffer

capacitance

C_VAREF

0.1

–

1

µF

ESR < 1Ω

V_S> 5.5V

P_9.1.1

Reference output voltage V_AREF

4.95

5

–

5.05

–

V

P_9.1.2

P_9.1.3

1)

DC supply voltage

rejection

DC_PSRVAREF30

dB

–

1)

Supply voltage ripple

rejection

AC_PSRVAREF26

–

dB

µs

V_S= 13.5V; f = 0 ... 1KHz; P_9.1.4

V_r= 2Vpp

1)

Turn ON time

t_so

–

200

C

= 100nF

P_9.1.5

ext

PD_N to 99.9% of final

value

¹⁾input impedance in case P_9.1.20

of VAREF is applied from

external

Input resistance at VAREF R_IN,VAREF

100

–

kΩ

1) Not subject to production test, specified by design.

Data Sheet

118

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.9.2

Electrical Characteristics ADC1 (10-Bit)

These parameters describe the conditions for optimum ADC performance.

Note:

Operating Conditions apply.

Table 38

A/D Converter Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or

Test Condition

Number

Min.

Max.

1)

Analog reference supply V_AREF

V_AGND

+ 1.0

–

V_DDPA

+ 0.05

V

P_9.2.1

P_9.2.2

P_9.2.3

Analog reference

ground

V_AGND

V_AIN

V_SS

- 0.05

1.5

–

2)

Analog input voltage

range

V_AGND

V_AREF

24

3)

Analog clock frequency f_ADCI

5

MHz

–

P_9.2.4

P_9.2.5

1)4)

Conversion time for 10- t_C10

(13 + STC) (13 + STC) (13 + STC)

bit result

× t_ADCI

+ 2 x t_SYS

1)

Conversion time for 8- t_C8

bit result

(11 + STC) (11 + STC) (11 + STC)

–

P_9.2.6

P_9.2.7

P_9.2.8

× t_ADCI

+ 2 × t_SYS

× t_ADCI

+ 2 × t_SYS+ 2 × t_SYS

× t_ADCI

1)

Wakeup time from

analog powerdown, fast

mode

t_WAF

–

4

µs

1)5)

Wakeup time from

analog powerdown,

slow mode

t_WAS

15

Total unadjusted error TUE_8B

(8 bit)

-2

±1

±6

+2

counts ⁶⁾⁷⁾Reference is P_9.2.9

internal V_AREF

counts ⁷⁾⁸⁾Reference is P_9.2.22

Total unadjusted error TUE_10B

(10 bit)

-12

+12

internal V_AREF

DNL error

INL error

EA_DNL

-3

±0.8

+3

+5

counts –

P_9.2.10

P_9.2.11

EA_{INL_int_V}-5

counts Reference is

internal V_AREF

AREF

Gain error

EA_{GAIN_int_}-10

±0.4

+10

counts Reference is

P_9.2.12

internal V_AREF

VAREF

Offset error

EA_OFF

-2

–

±0.5

–

+2

10

counts –

P_9.2.13

P_9.2.14

1)5)9)

Total capacitance

of an analog input

C_AINT

pF

1)5)9)

Switched capacitance

of an analog input

C_AINS

–

4

pF

P_9.2.15

Data Sheet

119

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 38

A/D Converter Characteristics (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or

Test Condition

Number

Min.

Max.

1)5)9)

Resistance of

the analog input path

R_AIN

–

2

kΩ

pF

kΩ

P_9.2.16

P_9.2.17

P_9.2.18

P_9.2.19

Total capacitance

of the reference input

C_AREFT

C_AREFS

R_AREF

–

15

7

Switched capacitance

of the reference input

Resistance of

2

the reference input path

1) Not subject to production test, specified by design.

2) V_AINmay exceed V_AGNDor V_AREFxup to the absolute maximum ratings. However, the conversion result in these cases will

be 0000_Hor 03FF_H, respectively.

3) The limit values for f_ADCImust not be exceeded when selecting the peripheral frequency and the prescaler setting.

4) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine

the digital result and the time to load the result register with the conversion result.

5) The broken wire detection delay against V_AGNDis measured in numbers of consecutive precharge cycles at a

conversion rate of not more than 500 µs.

6) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual

errors.

All error specifications are based on measurement methods standardized by IEEE 1241.2000.

7) The specified TUE is valid only if the absolute sum of input overload currents (see I_OVspecification) does not exceed

10 mA, and if V_AREFand V_AGNDremain stable during the measurement time.

8) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual

errors.

All error specifications are based on measurement methods standardized by IEEE 1241.2000.

9) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature,

supply voltage) typical values can be used for calculation. At room temperature and nominal supply voltage the

following typical values can be used:

C

_AINTtyp= 12 pF, C_AINStyp= 5 pF, R_AINtyp= 1.0 kΩ, C_AREFTtyp= 15 pF, C_AREFStyp= 10 pF, R_AREFtyp= 1.0 kΩ.

Data Sheet

120

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.10

14-Bit Sigma Delta ADC (ADC3 / ADC4)

30.10.1 Analog/Digital Converter Parameters

These parameters describe the conditions for optimum ADC performance.

Note:

Operating Conditions apply.

Table 39

A/D Converter ADC3/4 Characteristics

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ.

Max.

20

Analog clock frequency

f_ADC3/4

C_in1

5

–

2

MHz

pF

P_10.1.20

P_10.1.1

1)

Single ended input

capacitance

–

Oversampling ratio

OSR

V_Fs

128

–

2048

–

²⁾decimation factor P_10.1.2

ADC full scale voltage

(differential)

3.75

V

²⁾at V_DIFF= ±V_FS,

DD.max resp. DD.min

is reached

P_10.1.3

Input voltage

V_in

0

–

V_REF

input voltage on

ADCx.P or ADCx.N

P_10.1.21

V_REFcan be VAREF or

VREF5V

x={3,4}

2)

Differential non-linear

input voltage

V_diff,nonlin-4.0

–

4.0

V

= V_ADCx.P-V_ADCx.NP_10.1.4

diff

V_ADCx.P, V_ADCx.Pwithin

V_inrange

x={3,4}

2)

Differential linear input

voltage

V_diff,lin

-3.75

3.75

V

= V_ADCx.P-V_ADCx.NP_10.1.6

diff

V_ADCx.P, V_ADCx.Pwithin

V_inrange

x={3,4}

Input common mode

range

V_in,com

0.48 ×

0.52 ×

V_REF

V

V_REFcan be VAREF or P_10.1.7

VREF5V

V_REF

2)

Input frequency

RMS noise

f_in

0

–

1

kHz

P_10.1.8

V_rms

0.69

1.15

mV tested with OSR=128 P_10.1.22

and V_REF= VREF5V

Effective resolution

RES_eff

ENOB

11.7

12.4

11.7

bit calculated,

RES_eff= ld(V_Fs/ V_RMS

bit ²⁾ENOB=(SNDR-

1.76dB)/6.02dB

P_10.1.23

)

Effective number of bits

P_10.1.24

Data Sheet

121

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 39

A/D Converter ADC3/4 Characteristics (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

72

Unit Note or

Test Condition

Number

Min.

Max.

2)

SNDR with a fully

differential sinus -6dBFS

SNDR

–

dB

P_10.1.10

P_10.1.13

Digital filtered data of raw DD

ADC values

-16384

–

16383

LSB ²⁾represented in

two's complement

DD = (V_diff/V_REF) *

ATT_adc34* (2¹⁴- 1)

ADC34 input attenuator

ATT_adc34

–

4/3

250

1

–

P_10.1.25

P_10.1.15

P_10.1.17

2)

Dynamic input impedance Z_IN

–

kΩ

ADC Gain Ratio

G_ADC3

G_ADC4

OFF_ADC3/4

/

0.990

1.010

–

ADC Offset Drift

–

5.4

–

mV

–

P_10.1.18

1) In addition to pin capacitance C_IO, see P_5.2.7.

2) Not subject to production test, specified by design.

Data Sheet

122

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.11

High-Voltage Monitoring Input

30.11.1 Electrical Characteristics

Table 40

Electrical Characteristics Monitoring Input

T_j= -40°C to +150°C; V_S= 5.5 V to 28 V, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or Test Condition Number

Min.

Max.

MON Input Pin characteristics

Wake-up/monitoring

threshold voltage

V_MONth

0.4*V_S0.5*V_S0.6*V_S

V

Without external serial P_11.1.1

resistor R_s(with R_s:DV =

I_PD/PU* R_s); V_S= 5.5V to

18V

Wake-up/monitoring

threshold voltage

extended range

V_{MONth_ext}0.44*V_S0.53*V_S0.64*V_S

V

Without external serial P_11.1.11

resistor R_s(with R_s:DV =

I_PD/PU* R_s)

end

Threshold hysteresis

V_MONth,hys0.015* 0.05* 0.1*V_S

In all modes; without

external serial resistor R_s

(with R_s:dV = I_PD/PU* R_s);

V_S= 5.5V to 18V;

P_11.1.12

V_S

Threshold hysteresis

V_MONth,hys0.02*V_S0.06* 0.12*V_S

V

In all modes; without

external serial resistor R_s

(with R_s:dV = I_PD/PU* R_s);

V_S= 18V to 28V;

P_11.1.2

V_S

Pull-up current

Pull-down current

Input leakage current

Timing

I_{PU, MON}

I_{PD, MON}

I_LK,MON

-20

3

-10

10

–

-1

µA

0.6*V_S

P_11.1.3

P_11.1.4

P_11.1.5

20

2.5

0.4*V_S

¹⁾0 V < V_{MON_IN}< 28 V

-2.5

Wake-up filter time

(internal analog filter

delay)

t_FT,MON

–

500

–

ns

²⁾The overall filter time P_11.1.6

for MON wake-up is a

sum of t_FT,MON

+

adjustable digital filter

time. The digital filter

time can be adjusted by

PMU.CNF_WAKE_FILTER

.CNF_MON_FT;

1) Input leakage is valid for disabled state.

2) With pull-up, pull down current disabled.

Data Sheet

123

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.12

MOSFET Driver

30.12.1 Electrical Characteristics

Table 41

Electrical Characteristics MOSFET Driver

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

MOSFET Driver Output

Maximumtotalchargedriver Q_{tot_max}

capability

–

100 nC

¹⁾Due to Charge Pump

currrent capability only 3

x MOSFETs + additional

external capacitors with a

total charge of max.

P_12.1.20

100nC can be driven

simultaneous at a PWM

frequency of 25 kHz.

Source current - Charge

current - High Side Driver

I_{Soumax_HS}

I_{Sinkmax_HS}

I_{Soumax_LS}

I_{Sinkmax_LS}

230 345 450 mA V_SD≥ 8 V, C_Load= 10 nF, I_SouP_12.1.78

= C_Load* slew rate ( = 20%-

50% of V_GHx1),

I_CHARGE= I_DISCHG= 31(max)

Sink current - Discharge

current-High Side Driver

230 330 450 mA V_SD≥ 8 V, C_Load= 10 nF, I_SinkP_12.1.79

= C_Load* slew rate ( = 50%-

20% of V_GHx1),

I_CHARGE= I_DISCHG= 31(max)

Source current - Charge

current - Low Side Driver

200 295 375 mA V_SD≥ 8 V, C_Load= 10 nF, I_SouP_12.1.80

= C_Load* slew rate ( = 20%-

50% of V_GLx1),

I_CHARGE= I_DISCHG= 31(max)

Sink current - Discharge

current-Low Side Driver

200 314 375 mA V_SD≥ 8 V, C_Load= 10 nF, I_SinkP_12.1.81

= C_Load* slew rate ( = 50%-

20% of V_GHx1),

I_CHARGE= I_DISCHG= 31(max)

High level output voltage

Gxx vs. Sxx

V_Gxx1

V_Gxx2

V_Gxx3

V_Gxx6

10

8

–

14

–

V

V_SD≥ 8V, C_Load= 10 nF,

P_12.1.3

I_CP=2.5 mA²⁾.

High level output voltage

GHx vs. SHx

V_SD= 6.4 V¹⁾, C_Load= 10 nF, P_12.1.4

I_CP=2.5 mA²⁾

High level output voltage

GHx vs. SHx

7

–

V_SD= 5.4 V, C_Load= 10 nF, P_12.1.5

I_CP=2.5 mA²⁾

High level output voltage

GLx vs. GND

8

–

V_SD= 6.4 V¹⁾, C_Load= 10 nF, P_12.1.6

I_CP=2.5 mA²⁾

Data Sheet

124

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 41

Electrical Characteristics MOSFET Driver (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

High level output voltage

GLx vs. GND

V_Gxx7

7

–

V

V_SD= 5.4 V, C_Load= 10 nF, P_12.1.7

_CP=2.5 mA²⁾

I

1)

Rise time

Fall time

Rise time

Fall time

Rise time

Fall time

t_{rise3_3nf}

–

200

–

ns

C

= 3.3 nF,

P_12.1.8

Load

V

_SD≥ 8 V,

25-75% of V_Gxx1, I_CHARGE

I_DISCHG= 31(max)

1)

=

t_{fall3_3nf}

t_risemax

t_fallmax

–

200

–

ns

C

= 3.3 nF,

P_12.1.9

Load

V_SD≥ 8 V,

75-25% of V_Gxx1, I_CHARGE

I

_DISCHG= 31(max)

C_Load= 10 nF,

_SD≥ 8 V,

25-75% of V_Gxx1, I_CHARGE

_DISCHG= 31(max)

C_Load= 10 nF,

_SD≥ 8 V,

100 250 450 ns

P_12.1.57

P_12.1.58

P_12.1.14

P_12.1.15

P_12.1.35

P_12.1.36

P_12.1.11

V

I

V

75-25% of V_Gxx1, I_CHARGE

I_DISCHG= 31(max)

1)

t_risemin

1.25 2.5

5

µs

C

= 10 nF,

Load

V_SD≥ 8 V,

25-75% of V_Gxx1

,

I

_CHARGE= I_DISCHG= 3(min)

1)

t_fallmin

C

= 10 nF,

Load

V

_SD≥ 8 V,

75-25% of V_Gxx1

,

I

_CHARGE= I_DISCHG= 3(min)

C_Load= 10 nF,

_SD≥ 8 V,

25-75% of V_Gxx1, I_CHARGE

_DISCHG= 31(max)

C_Load= 10 nF,

_SD≥ 8 V,

Absolute rise - fall time

difference for all LSx

t_{r_f(diff)LSx}

–

100 ns

V

=

I

Absolute rise - fall time

difference for all HSx

t_{r_f(diff)HSx}

–

V

25-75% of V_Gxx1, I_CHARGE

I_DISCHG= 31(max)

1)

Resistor between GHx/GLx R_GGND

30

40

50

kΩ

–

and GND

Data Sheet

125

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 41

Electrical Characteristics MOSFET Driver (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Resistor between SHx and

GND

R_SHGN

30

40

50

kΩ ¹⁾³⁾This resistance is the P_12.1.10

resistance between GHx

and GND connected

through a diode to SHx.

As a consequence, the

voltage at SHx can rise up

to 0,6V typ. before it is

discharged through the

resistor.

Low RDSON mode

(boosted discharge mode)

R_ONCCP

–

9

12

Ω

V_VSD= 13.5 V,

_VCP= V_VSD+ 14.0 V; I_CHARGE

P_12.1.50

V

= I_DISCHG= 31(max); 50mA

forced into Gx, Sx

grounded

1)

Resistance between VDH

and VSD

I_BSH

–

4

–

3

kΩ

P_12.1.24

P_12.1.37

1)

Input propagation time (LS t_P(ILN)min

1.5

µs

C

= 10 nF,

Load

on)

I_Charge=3(min),

25% of V_Gxx1

1)

Input propagation time (LS t_P(ILF)min

off)

–

1.5

3

µs

C

= 10 nF,

P_12.1.38

P_12.1.39

P_12.1.40

P_12.1.26

P_12.1.27

P_12.1.28

P_12.1.29

Load

I_Discharge=3(min),

75% of V_Gxx1

1)

Input propagation time (HS t_P(IHN)min

on)

C

= 10 nF,

Load

I_Charge=3(min)

25% of V_Gxx1

1)

Input propagation time (HS t_P(IHF)min

off)

C

= 10 nF,

Load

I_Disharge=3(min),

75% of V_Gxx1

Input propagation time (LS t_P(ILN)max

on)

200 350 ns

200 300 ns

200 350 ns

200 300 ns

C_Load= 10 nF,

I_Charge=31(max),

25% of V_Gxx1

Input propagation time (LS t_P(ILF)max

off)

C_Load= 10 nF,

I_Discharge=31(max),

75% of V_Gxx1

Input propagation time (HS t_P(IHN)max

on)

C_Load= 10 nF,

I_Charge=31(max),

25% of V_Gxx1

Input propagation time (HS t_P(IHF)max

C_Load= 10 nF,

off)

I_Discharge=31(max),

75% of V_Gxx1

Data Sheet

126

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 41

Electrical Characteristics MOSFET Driver (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Absolute input propagation t_Pon(diff)LSx

time difference between

propagation times for all LSx

(LSx on)

–

100 ns

C_Load= 10 nF,

_Charge=31(max),

25% of V_Gxx1

P_12.1.30

P_12.1.41

P_12.1.42

P_12.1.43

I

Absolute input propagation t_{Poff(diff)LSx}

time difference between

propagation times for all LSx

(LSx off)

C_Load= 10 nF,

I_Discharge=31(max),

75% of V_Gxx1

Absolute input propagation t_Pon(diff)HSx

time difference between

propagation times for all

HSx (HSx on)

C_Load= 10 nF,

I_Charge=31(max),

25% of V_Gxx1

Absolute input propagation t_{Poff(diff)HSx}

time difference between

propagation times for all

HSx (HSx off)

C_Load= 10 nF,

I_Discharge=31(max),

75% of V_Gxx1

Drain source monitoring

threshold

V_DSMONVTH

–

V

DRV_CTRL3.DSMONVTH< P_12.1.46

2:0> xxx

000

001

010

011

100

101

110

0.07 0.25 0.40

0.35 0.50 0.650

0.55 0.75 0.90

0.65 1.00 1.25

0.90 1.25 1.45

1.00 1.5 1.80

1.20 1.75 2.10

1.40 2.00 2.40

111

Open load diagnosis currents

Pull-up diagnosis current

Pull-down diagnosis current I_PDDiag

Charge pump

I_PUDiag

-220 -370 -520 µA

650 900 1100 µA

I_DISCHG= 1; V_SHx= 5.0 V

P_12.1.47

P_12.1.48

Output voltage

VCP vs. VSD

V_CPmin1

8.5

–

V

V_VSD= 5.4V,

P_12.1.53

I_CP=5 mA,

C

_CP1, C_CP2= 220 nF,

Bridge Driver enabled

Regulated output voltage

VCP vs. VSD

V_CP

12

14

16

V

8 V ≤ V_VSD≤ 28,

I_CP=10mA,

P_12.1.49

C

_CP1, C_CP2=220 nF,

f

_CP=250kHz

Data Sheet

127

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 41

Electrical Characteristics MOSFET Driver (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Turn ON Time

t_{ON_VCP}

10

24

40

us

8 V ≤ V_VSD≤ 28,

_CP=2.5mA,

P_12.1.59

P_12.1.60

I

1)4)

(25%) of V_CP

C_CP1, C_CP2=220 nF,

_CP=250kHz

8 V ≤ V_VSD≤ 28,

_CP=2.5mA,

(25-75%) of V_CP

C_CP1, C_CP2=220 nF,

_CP=250kHz

,

f

Rise time

t_{rise_VCP}

20

60

88

I

1)5)

,

f

1) Not subject to production test.

2) The condition I_CP= 2,5 mA emulates an BLDC Driver with 6 MOSFET switching at 20 KHz with a C_Load=3.3nF. Test

condition: I_Gx= - 100 µA, ICHARGE = IDISCHARGE = 31(max), IDISCHARGEDIV2_N = 1 and ICHARGEDIV2_N = 1.

3) This resistance is connected through a diode between SHx and GHx to ground.

4) This time applies when Bit DRV_CP_CTRL_STS.bit.CP_EN is set

5) This time applies when Bit DRV_CP_CLK_CTRL.bit.CPCLK_EN is set

Data Sheet

128

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

30.13

Operational Amplifier

30.13.1 Electrical Characteristics

Table 42

Electrical Characteristics Operational Amplifier

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit Note or Test Condition Number

Min.

Max.

Differential gain

(uncalibrated)

G

Gain settings GAIN<1:0>: P_13.1.6

9.5

19

38

57

10

20

40

60

10.5

21

42

00

01

10

11

63

Differentialinputoperating V_IX

voltage range OP2 - OP1

-1.5 / G –

1.5 / G

V

G is the Gain specified

below

P_13.1.1

Operating. common mode V_CM

input voltage range

(referred to GND (OP2 -

GND) or (OP1 - GND)

-2.0

–

2.0

Inputcommonmodehas P_13.1.2

to be checked in

evaluation if it fits the

required range

Max. input voltage range

(referred to GND (OP_2 -

GND) or (OP1 - GND)

V_{IX_max}-7.0

7.0

V

Max. rating of

operational amplifier

inputs, where

measurement is not

done

P_13.1.3

Single ended output

voltage range (linear

range)

V_OUT

V_ZERO

- 1.5

–

V_ZERO

+ 1.5

V

¹⁾²⁾typ. output offset

voltage 2 V ± 1.5V

P_13.1.4

P_13.1.5

Linearity error

E_PWM

-15

15

1.0

1

mV

Maximum deviation

from best fit straight line

divided by max. value of

differential output

voltage range (0.5V -

3.5V); this parameter is

determined at G = 10.

Linearity error

E_{PWM_%}-1.0

–

%

Maximum deviation

from best fit straight line

divided by max. value of

differential output

voltage range (0.5V -

3.5V); this parameter is

determined at G = 10.

P_13.1.24

P_13.1.7

Gain drift

-1

Gain drift after

calibration at G = 10.

Data Sheet

129

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Electrical Characteristics

Table 42

Electrical Characteristics Operational Amplifier (cont’d)

V_S= 5.5 V to 28 V, T_j= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min.

Typ. Max.

Adjusted output offset

voltage

V_OOS

-40

10

40

mV V_AIP= V_AIN= 0 V and

P_13.1.17

P_13.1.8

G = 40.

DC input voltage common DC-

mode rejection ratio

58

80

–

dB

ns

CMRR (in dB)=-20*log

(differential mode gain/

common mode gain)

V_CMI= -2V... 2V,

CMRR

V

_AIP-V_AIN=0V

Settling time to 98%

T_SET

–

800

1400

1.5

Derived from 80 - 20 % P_13.1.9

rise fall times for ± 2V

overload condition (3

Tau value of settling time

constant)²⁾

2)

Current Sense Amplifier

Input Resistance @ OP1,

OP2

R_{in_OP1_}

1

1.25

kΩ

–

P_13.1.25

OP2

1) Typical V_ZERO= 0,4 * VAREF.

2) This parameter is not subject to production test.

Data Sheet

130

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Package Outlines

31

Package Outlines

0ꢀ9 MAXꢀ

(0ꢀ65)

11 x 0ꢀ5 = 5ꢀ5

0ꢀ5

0ꢀ1

7

A

0ꢀ03

6ꢀ8

0ꢀ1

+0ꢀ03¹⁾

2)

37

B

36

25

24

48x

0ꢀ08

48

13

1

12

Index Marking

48x

0ꢀ1

0ꢀ4 x 45°

0ꢀ05

Index Marking

0ꢀ23

(0ꢀ35)

M

A B C

(0ꢀ2)

0ꢀ05 MAXꢀ

(5ꢀ2)

(6)

C

1) Vertical burr 0ꢀ03 maxꢀ, all sides

2) These four metal areas have exposed diepad potential

PG-VQFN-48-29, -31-PO V05

Figure 41 Package outline VQFN-48-31 (with LTI)

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

131

Rev. 1.0

2018-01-16

TLE9879-2QXA40

Revision History

32

Revision History

Page or Item

Rev. 1.0, 2018-01-16

all

Subjects (major changes since previous revision)

Initial Release.

Data Sheet

132

Rev. 1.0

2018-01-16

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2018-01-16

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

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a written document signed by

Document reference


型号：	TLE9879-2QXA40
厂家：	Infineon
描述：	TLE9879-2QXA40 属于 MOTIX™ TLE987x 产品系列。TLE9879-2QXA40 是单芯片三相电机驱动器，集成工业标准 Arm® Cortex™ M3 核心，支持实施磁场定向控制等高级电机控制算法。该器件包括 6 个经过优化的全集成 NFET 驱动器，通过 6 个外部功率 NFET 驱动三相电机，其电荷泵支持低电压运行，可编程电流以及电流斜率控制实现优化 EMC 行为。外设包括电流传感器、同步逐次逼近 ADC、用于 PWM 控制的捕捉和比较单元以及 16 位定时器。除 TLE987x 产品系列其他产品外，TLE9879-2QXA40 还集成两个 14 位 Sigma-Delta ADC，为外部 GMR/TMR 构建传感器接口。此外还集成 LIN 收发器，通过多个通用 I/O 支持器件通信。该器件还配备片上线性电压调节器，为外部负载供电。通信电机驱动泵传感器驱动器调节器
文件：	总133页 (文件大小：3766K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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