TLS805B1 [INFINEON]
Ultra Low Quiescent Current Linear Voltage Regulator;型号: | TLS805B1 |
厂家: | Infineon |
描述: | Ultra Low Quiescent Current Linear Voltage Regulator |
文件: | 总26页 (文件大小:1247K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ultra Low Quiescent Current Linear
Voltage Regulator
TLS805B1
TLS805B1SJV
TLS805B1LDV
Linear Voltage Regulator
Data Sheet
Rev. 1.2, 2016-01-11
Automotive Power
TLS805B1
TLS805B1SJ/LDV
1
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Ultra Low Quiescent Current of 5 µA
Wide Input Voltage Range of 2.75 V to 42 V
Output Current Capacity up to 50 mA
Off Mode Current Less than 1 µA
Low Drop Out Voltage of typ. 100 mV @ 50 mA
Output Current Limit Protection
Overtemperature Shutdown
Enable
Figure 1
PG-DSO-8
Available in PG-DSO-8 Package
Available in PG-TSON-10 Package
Wide Temperature Range
Green Product (RoHS Compliant)
AEC Qualified
Figure 2
PG-TSON-10
Type
Package
Marking
TLS805B1SJV
TLS805B1LDV
PG-DSO-8
PG-TSON-10
805B1V
805B1V
Data Sheet
2
Rev. 1.2, 2016-01-11
TLS805B1SJ/LDV
Overview
Description
The TLS805B1 is a linear voltage regulator featuring wide input voltage range, low drop out voltage and ultra
low quiescent current.
With an input voltage range of 2.75 V to 42 V and ultra low quiescent of only 5 µA, the regulator is perfectly
suitable for automotive or any other supply systems connected permanently to the battery.
The TLS805B1SJ/LDV is the adjustable output version with an accuracy of 2 % and output current capability
up to 50 mA.
The new regulation concept implemented in TLS805B1 combines fast regulation and very good stability while
requiring only a small ceramic capacitor of 1 μF at the output.
The tracking region starts already at input voltages of 2.75 V (extended operating range). This makes the
TLS805B1 also suitable to supply automotive systems that need to operate during cranking condition.
Internal protection features like output current limitation and overtemperature shutdown are implemented
to protect the device against immediate damage due to failures like output short circuit to GND, over-current
and over-temperature.
The device can be switched on and off by the Enable feature. When the device is switched off, the current
consumption is typically less than 1 µA.
Choosing External Components
An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for
the stability of the regulating circuit. Stability is guaranteed at values CQ≥ 1 µF and an ESR ≤ 100 Ω within the
whole operating range.
Data Sheet
3
Rev. 1.2, 2016-01-11
TLS805B1SJ/LDV
Block Diagram
2
Block Diagram
I
Q
Current
Limitation
EN
ADJ
Enable
Bandgap
Reference
Temperature
Shutdown
GND
Figure 3
Block Diagram TLS805B1
Data Sheet
4
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment in PG-DSO-8 Package
1
2
8
7
I
Q
N.C.
ADJ
3
4
6
5
EN
N.C.
N.C.
GND
Figure 4
Pin Configuration TLS805B1 in PG-DSO-8 package
3.2
Pin Definitions and Functions in PG-DSO-8 Package
Pin
Symbol
Function
1
I
Input
It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close
to the IC terminals, in order to compensate line influences.
2
3
N.C.
EN
Not connected
Enable
Integrated pull-down resistor.
Enable the IC with high level input signal.
Disable the IC with low level input signal.
4
5
6
7
GND
N.C.
N.C.
ADJ
Ground
Not connected
Not connected
Voltage Adjustment
Connect an external voltage divider to determine the output voltage.
8
Q
Output
Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the
values specified for its capacitance and ESR in Table 2 “Functional Range” on
Page 9.
Data Sheet
5
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Pin Configuration
3.3
Pin Assignment in PG-TSON-10 Package
TSON-10
I
N.C.
EN
1
2
3
4
5
10
9
N.C.
Q
8
ADJ
N.C.
N.C.
7
GND
N.C.
6
Figure 5
Pin Configuration TLS805B1 in PG-TSON-10 package
3.4
Pin Definitions and Functions in PG-TSON-10 Package
Pin
Symbol
Function
1
I
Input
It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close
to the IC terminals, in order to compensate line influences.
2
3
N.C.
EN
Not connected
Enable
Integrated pull-down resistor.
Enable the IC with high level input signal.
Disable the IC with low level input signal.
4
5
6
7
8
N.C.
GND
N.C.
N.C.
ADJ
Not connected
Ground
Not connected
Not connected
Voltage Adjustment
Connect an external voltage devider to determine the output voltage.
The pin is left not connected for fixed output voltage version.
9
Q
Output
Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the
values specified for its capacitance and ESR in Table 2 “Functional Range” on
Page 9.
Data Sheet
6
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Pin Configuration
Pin
10
Symbol
N.C.
–
Function
Not connected
Pad
Exposed Pad
Connect to heatsink area.
Connect to GND.
Data Sheet
7
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit
Note or
Test Condition
Number
Min.
-0.3
-0.3
-0.3
Max.
45
Voltage Input I, Enable EN
Voltage
VI, VEN
VQ
–
–
–
V
V
V
–
–
–
P_4.1.1
P_4.1.2
P_4.1.3
Voltage Output Q
Voltage
45
Voltage Adjustment ADJ
Voltage
VADJ
7
Temperatures
Junction Temperature
Storage Temperature
ESD Absorption
Tj
-40
-55
–
–
150
150
°C
°C
–
–
P_4.1.4
P_4.1.5
Tstg
ESD Susceptibility to GND
VESD,HBM -2
–
–
2
kV
V
HBM2)
P_4.1.6
ESD Susceptibility to GND
VESD,CDM -750
750
CDM3) at all pins P_4.1.7
1) Not subject to production testing, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
8
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min.
Typ.
Max.
42
1)
Input Voltage Range
VI
VQ,nom+Vdr
2.75
–
–
V
V
–
–
P_4.2.1
P_4.2.2
2)
Extended Input Voltage
Range
VI,ext
42
3)4)
4)
Output Capacitor
CQ
1
–
–
–
–
µF
Ω
–
–
–
P_4.2.3
P_4.2.4
P_4.2.5
Output Capacitor’s ESR
ESR(CQ)
–
100
Junction temperature
Tj
-40
150
°C
1) Output current is limited internally and depends on the input voltage, see Electrical Characteristics for more details.
2) When VI is between VI,ext.min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V.
3) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.
4) Not subject to production testing, specified by design.
Note: Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics table.
Data Sheet
9
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3
Thermal Resistance TLS805B1 in PG-DSO-8 Package
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Package Version PG-DSO-8
Junction to Case1)
Junction to Ambient1)
Junction to Ambient1)
RthJC
RthJA
RthJA
–
–
–
40
–
–
–
K/W
–
P_4.3.1
P_4.3.2
114
172
K/W 2s2p board2)
K/W 1s0p board, footprint P_4.3.3
only3)
Junction to Ambient1)
Junction to Ambient1)
RthJA
RthJA
–
–
139
133
–
–
K/W 1s0p board, 300 mm2 P_4.3.4
heatsink area on PCB3)
K/W 1s0p board, 600 mm2 P_4.3.5
heatsink area on PCB3)
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Table 4
Thermal Resistance TLS805B1 in PG-TSON-10 Package
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Package Version PG-DSO-8
Junction to Case1)
Junction to Ambient1)
Junction to Ambient1)
RthJC
RthJA
RthJA
–
–
–
13
–
–
–
K/W
–
P_4.3.6
P_4.3.7
60
K/W 2s2p board2)
188
K/W 1s0p board, footprint P_4.3.8
only3)
Junction to Ambient1)
Junction to Ambient1)
RthJA
RthJA
–
–
77
65
–
–
K/W 1s0p board, 300 mm2 P_4.3.9
heatsink area on PCB3)
K/W 1s0p board, 600 mm2 P_4.3.10
heatsink area on PCB3)
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
10
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
5
Block Description and Electrical Characteristics
5.1
Voltage Regulation
The output voltage VQ is divided by a resistor network. This fractional voltage is compared to an internal
voltage reference and the pass transistor is driven accordingly.
The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the
internal circuit structure. To ensure stable operation, the output capacitor’s capacitance and its equivalent
series resistor ESR requirements given in “Functional Range” on Page 9 have to be maintained. For details
see the typical performance graph Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ.
Since the output capacitor is used to buffer load steps, it should be sized according to the application’s needs.
An input capacitor CI is not required for stability, but is recommended to compensate line fluctuations. An
additional reverse polarity protection diode and a combination of several capacitors for filtering should be
used, in case the input is connected directly to the battery line. Connect the capacitors close to the regulator
terminals.
In order to prevent overshoots during start-up, a smooth ramping up function is implemented. This ensures
almost no overshoots during start-up, mostly independent from load and output capacitance.
Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is
limited and the output voltage decreases.
The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions
(e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the
regulator restarts. This oscillatory thermal behaviour causes the junction temperature to exceed the
maximum rating of 150°C and can significantly reduce the IC’s lifetime.
Regulated
Output Voltage
Supply
IQ
I
I
I
Q
Current
Limitation
R1
C
ADJ
ESR
LOAD
VI
VQ
CI
Bandgap
CQ
Reference
Temperature
Shutdown
R2
GND
Figure 6
Block Diagram Voltage Regulation
Data Sheet
11
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
Table 5
Electrical Characteristics
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified).
Typical values are given at Tj = 25 °C, VI = 13.5 V.
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Output Voltage Precision1) ΔVQ
-2
–
2
%
%
50 µA ≤ IQ ≤ 50 mA,
VQ+ Vdr ≤ VI ≤ 28 V, VI ≥ 3 V, R2
≤ 250 kΩ
P_5.1.1
Output Voltage Precision
ΔVQ
-2
–
2
50 µA ≤ IQ ≤ 25 mA,
VQ+ Vdr ≤ VI ≤ 42 V, VI ≥ 3 V, R2
≤ 250 kΩ
P_5.1.2
Output Current Limitation IQ,lim
51
–
85
1
120
20
mA
mV
0 V ≤ VQ ≤ VQ,nom - 0.1 V
IQ = 1 mA, 6 V ≤ VI ≤ 32 V
P_5.1.3
P_5.1.4
Line Regulation
steady-state
ΔVQ,line
Load Regulation
steady-state
Dropout Voltage2)
ΔVQ,load -20
-1
–
mV
mV
VI = 6 V,
50 µA ≤ IQ ≤ 50 mA
P_5.1.5
P_5.1.6
Vdr
–
100
300
IQ = 50 mA, VI = 5.4 V
Vdr = VI - VQ
Reference voltage
Vref
1.17
1.2
–
1.23
V
V
–
P_5.1.7
P_5.1.8
Output Voltage Adjustable VQ,Range 1.2
VI - Vdr
VI < 42 V
Range
Ripple Rejection3)
PSRR
–
60
–
dB
IQ = 50 mA, VQ = 1.2 V,
P_5.1.9
fripple = 100 Hz,
V
ripple = 0.5 Vp-p
Overtemperature
Tj,sd
151
–
175
10
–
–
°C
K
Tj increasing
Tj decreasing
P_5.1.10
P_5.1.11
Shutdown Threshold3)
Overtemperature
Shutdown Threshold
Hysteresis3)
Tj,sdh
1) Referring to the device tolerance only, the tolerance of the resistor divider can cause additional deviation. Parameter
is tested with the ADJ pin directly connected to the output pin Q.
2) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V
3) Not subject to production test, specified by design
Data Sheet
12
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
5.2
Typical Performance Characteristics Voltage Regulation
Typical Performance Characteristics
Output Voltage VQ versus
Junction Temperature Tj
Output Current IQ versus
Input Voltage VI
120
100
80
60
40
20
0
T = −40 °C
j
1.24
1.23
1.22
1.21
1.2
T = 25 °C
j
T = 150 °C
j
1.19
1.18
1.17
V = 13.5 V
I
I
= 25 mA
1.16
1.15
Q
V
= 1.2 V
Q,nom
0
50
100
150
0
10
20
V [V]
30
40
T [°C]
j
I
Dropout Voltage Vdr versus
Junction Temperature Tj
Dropout Voltage Vdr versus
Output Current IQ
200
200
I
= 10 mA
= 25 mA
= 50 mA
Tj = −40 °C
Q
180
160
140
120
100
80
180
I
Tj = 25 °C
Q
I
Q
Tj = 150 °C
160
140
120
100
80
60
60
40
40
20
20
0
0
0
50
100
150
0
10
20
30
40
50
T [°C]
IQ [mA]
j
Data Sheet
13
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
Load Regulation ΔVQ,load versus
Output Current IQ
Line Regulation ΔVQ,line versus
Input Voltage VI
10
5
Tj = −40 °C
Tj = −40 °C
8
4
Tj = 25 °C
Tj = 25 °C
Tj = 150 °C
Tj = 150 °C
6
3
4
2
2
1
0
0
−2
−4
−6
−8
−10
−1
−2
−3
−4
−5
IQ = 1 mA
VQ,nom = 1.2 V
0
10
20
30
40
50
10
15
20
25
VI [V]
30
35
40
IQ [mA]
Output Voltage VQ versus
Input Voltage VI
Power Supply Ripple Rejection PSRR versus
Ripple Frequency fr
6
5
4
3
2
1
0
80
70
60
50
40
30
IQ = 10 mA
CQ = 1 μF
VI = 13.5 V
VQ,nom = 1.2 V
Vripple = 0.5 Vpp
Tj = 25 °C
20
10
0
V
I
= 5 V
= 50 mA
Q,nom
Q
T = 25 °C
j
10−2
10−1
100
101
102
103
0
1
2
3
4
5
6
V [V]
f [kHz]
I
Data Sheet
14
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
103
Unstable Region
102
101
Stable Region
100
10−1
C
= 1 μF
Q
V = 3...28 V
I
10−2
0
10
20
30
40
50
I
[mA]
Q
Data Sheet
15
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
5.3
Current Consumption
Table 6
Electrical Characteristics Current Consumption
Tj = -40 °C to +150 °C, VI = 13.5 V (unless otherwise specified).
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Current Consumption
Iq = II
Iq,off
Iq
–
–
–
–
–
–
1
µA
µA
µA
µA
µA
VEN ≤ 0.4 V, Tj < 105 °C
IQ = 50 µA, Tj = 25 °C
IQ = 50 µA, Tj < 105 °C
IQ = 50 µA, Tj < 125 °C
IQ= 50 mA, Tj < 125 °C
P_5.3.1
P_5.3.2
P_5.3.3
P_5.3.4
P_5.3.5
Current Consumption
Iq = II - IQ
5
7.5
10
11
11
Current Consumption
Iq = II - IQ
Iq
6
Current Consumption
Iq = II - IQ
Iq
6.5
6.5
Current Consumption
Iq
Iq = II - IQ
Data Sheet
16
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
5.4
Typical Performance Characteristics Current Consumption
Typical Performance Characteristics
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Input Voltage VI
40
16
Tj = −40 °C
T = −40 °C
j
Tj = 25 °C
T = 25 °C
35
14
12
10
8
j
Tj = 105 °C
T = 105 °C
j
Tj = 125 °C
T = 125 °C
30
j
25
20
15
10
5
6
4
2
V = 13.5 V
I
IQ = 50 μA
35 40
0
0
10
15
20
25
30
0
10
20
30
40
50
VI [V]
I
[mA]
Q
Current Consumption Iq versus
Junction Temperature Tj
Current Consumption in OFF mode Iq,off versus
Junction Temperature Tj
16
14
12
10
8
4
V = 13.5 V
I
V
≤ 0.4 V
EN
3.5
3
2.5
2
6
1.5
1
4
2
0.5
0
VI = 13.5 V
IQ = 50 μA
0
0
50
100
150
0
50
100
150
Tj [°C]
T [°C]
j
Data Sheet
17
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
5.5
Enable
The device can be switched on and off by the Enable feature. Connect a HIGH level as specified below (e.g. the
battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to switch it
off. The Enable function has a build-in hysteresis to avoid toggling between ON/OFF state, if signals with slow
slopes are appiled to the EN input.
Table 7
Electrical Characteristics Enable
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified).
Typical values are given at Tj = 25 °C, VI = 13.5 V.
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Enable High Level Input
Voltage
VEN,H
VEN,L
IEN,H
2
–
–
–
2
–
V
VQ settled
VQ ≤ 0.1 V
VEN = 5 V
–
P_5.5.1
P_5.5.2
P_5.5.3
P_5.5.4
Enable Low Level Input
Voltage
–
0.8
4
V
Enable High Level Input
Current
–
µA
MΩ
Enable Internal Pull-down REN
Resistor
1.25
3.5
Data Sheet
18
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Block Description and Electrical Characteristics
5.6
Typical Performance Characteristics Enable
Typical Performance Characteristics
Enable Input Current IEN versus
Enable Input Voltage VEN
40
Tj = −40 °C
Tj = 25 °C
35
Tj = 150 °C
30
25
20
15
10
5
0
0
10
20
30
40
VEN [V]
Data Sheet
19
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Application Information
6
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
6.1
Application Diagram
Regulated
Output Voltage
DI1
IQ
Supply
II
I
Q
R1
e.g. Ignition
EN
Load
(e.g.
ADJ
TLS805B1
Micro
Controller)
CQ
DI2
CI2
CI1
1μF
<45V
10μF 100nF
R2
GND
GND
Figure 7
Application Diagram
6.2
Selection of External Components
Input Pin
6.2.1
The typical input circuitry for a linear voltage regulator is shown in the application diagram above.
A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high
frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to
the input pin of the linear voltage regulator on the PCB.
An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to
smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of
the linear voltage regulator on the PCB.
An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum
rating of the linear voltage regulator and protect the device against any damage due to over-voltage.
The external components at the input are not mandatory for the operation of the voltage regulator, but they
are recommended in case of possible external disturbances.
Data Sheet
20
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Application Information
6.2.2
Output Pin
An output capacitor is mandatory for the stability of linear voltage regulators.
The requirement to the output capacitor is given in “Functional Range” on Page 9. The graph “Output
Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15 shows the stable operation range
of the device.
TLS805B1 is designed to be stable with extremely low ESR capacitors. According to the automotive
environment, ceramic capacitors with X5R or X7R dielectrics are recommended.
The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the
same side of the PCB as the regulator itself.
In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in
accordance and verified in the real application that the output stability requirements are fulfilled.
6.3
Output Voltage Adjust
The output voltage of TLS805B1SJ/LDV can be adjusted between 1.2 V and VI - Vdr by an external resistor
divider, connected to the adjust pin ADJ, as shown in Figure 7.
The pin ADJ is connected to the error amplifier comparing the voltage at this pin with the internal reference
voltage of typically 1.2 V.
The output voltage can be easily calculated, neglecting the current flowing into the ADJ pin:
R1 + R2
------------------
VQ
=
× Vref
(6.1)
R2
with
•
•
•
Vref: internal reference voltage, typically 1.2V
R1: resistor between regulator output Q and adjust pin ADJ
R2: resistor between adjust pin ADJ and GND
The bigger the resistors R1 and R2, the less the current flowing through the resistor divider. However, using too
big resistors makes the current flowing into the ADJ pin non-negligible. In oder to neglect the current flowing
into the ADJ pin, the values of R1 and R2 should be selected fulfilling the criteria R2 ≤ 250 kΩ.
To set the output voltage to 1.2 V, the adjust pin ADJ should be directly connected to the output pin Q.
Take into consideration that an additional error to the output voltage tolerance may be introduced by the
accuracy of the resistors R1 and R2.
6.4
Thermal Considerations
Knowing the input voltage, the output voltage and the load profile of the application, the total power
dissipation can be calculated:
PD = (VI – VQ) × IQ + VI × Iq
(6.2)
with
•
•
•
PD: continuous power dissipation
VI: input voltage
VQ: output voltage
Data Sheet
21
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Application Information
•
•
IQ: output current
Iq: quiescent current
The maximum acceptable thermal resistance RthJA can then be calculated:
Tj, max – Ta
RthJA, max = ---------------------------
PD
(6.3)
with
•
•
T
j,max: maximum allowed junction temperature
Ta: ambient temperature
Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with
reference to the specification in “Thermal Resistance” on Page 10.
Example
Application conditions:
VI = 13.5 V
VQ = 5 V
IQ = 35 mA
Ta = 105 °C
Calculation of RthJA,max
:
PD = (VI – VQ) x IQ + VI x Iq
= (13.5V – 5V) x 35 mA + 13.5 V x 0.0115 mA
= 0.2975 W
R
thJA,max= (Tj,max – Ta) / PD
= (150 °C – 105 °C) / 0.2975 W
= 151.2 K/W
As a result, the PCB design must ensure a thermal resistance RthJA lower than 151.2 K/W. According to
“Thermal Resistance” on Page 10, for both TLS805B1SJV and TLS805B1LDV at least 300 mm² heatsink area
is needed on the FR4 1s0p PCB, or the FR4 2s2p board can be used.
6.5
Reverse Polarity Protection
TLS805B1 is not self protected against reverse polarity faults. To protect the device against negative supply
voltage, an external reverse polarity diode is needed, as shown in Figure 7. The absolute maximum ratings of
the device as specified in “Absolute Maximum Ratings” on Page 8 must be kept.
6.6
Further Application Information
•
For further information you may contact http://www.infineon.com/
Data Sheet
22
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Package Outlines
7
Package Outlines
0.35 x 45°
1)
4-0.2
C
1.27
B
0.1
SEATING PLANE
±0.25
0.64
+0.1 2)
-0.06
0.41
±0.2
6
M
M
0.2
A
A B 8x
0.2
C 8x
8
5
1
4
1)
5-0.2
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
PG-DSO-8-16, -24, -25, -28, -31, -33, -36, -44, -49-PO V06
Figure 8
PG-DSO-8
Data Sheet
23
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Package Outlines
±0.1
2.58
±0.1
0.1
±0.1
±0.1
±0.1
3.3
0.36
0.53
0.05
Z
Pin 1 Marking
±0.1
0.5
Pin 1 Marking
±0.1
0.25
PG-TSON-10-2-PO V02
Z (4:1)
0.07 MIN.
Figure 9
PG-TSON-10
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Data Sheet
24
Rev. 1.2 2016-01-11
TLS805B1SJ/LDV
Revision History
8
Revision History
Revision
1.2
Date
Changes
2016-01-11 New variant TLS805B1LDV in PG-TSON-10 package added.
1.1
2015-11-02 - Functional range of the Enable input voltage defined.
- Document style updated.
- Typical performance graph Load Regulation updated.
- Editorial changes.
1.0
2015-02-05 Datasheet - Initial Version
Data Sheet
25
Rev. 1.2 2016-01-11
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, LITIX™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,
UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of
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Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association
Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave
Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of
Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
www.infineon.com
Edition 2016-01-11
Published by
Infineon Technologies AG
81726 Munich, Germany
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no event be regarded as
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may contain dangerous substances. For
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contact the nearest Infineon Technologies
Office. Infineon Technologies components may
be used in life-support devices or systems only
with the express written approval of Infineon
Technologies, if a failure of such components
can reasonably be expected to cause the failure
of that life-support device or system or to affect
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to support and/or maintain and sustain and/or
protect human life. If they fail, it is reasonable to
assume that the health of the user or other
persons may be endangered.
a guarantee of
conditions or characteristics. With respect to any
examples or hints given herein, any typical
values stated herein and/or any information
regarding the application of the device, Infineon
Technologies hereby disclaims any and all
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