TLS810D1LD V50 [INFINEON]

TLS810D1LDV50 是一个线性稳压器，具有较宽的输入电压范围，低电压差和超低静态电流的特点。此产品可采用3.3mm * 3.3mm 新型无铅汽车用封装(TSON10) ，具有经过改善的光学检测特性。稳压器的输入电压范围为 2.75V 至 42V，静态电流极低，仅 9μA，非常适合汽车或任何永久连接电池的其他电源系统。TLS810D1LDV50 有精度为 2% 的 5.0V 输出电压版本可选，输出电流能力可达100mA。它只配有一个小型的陶瓷电容器，输出电流为1μF，十分稳定。此装置可通过启用功能打开或关断，电流损耗低于 1μA。TLS810D1LDV50 的操作范围扩展至2.75V，也适用于启动情况下的汽车系统操作的供电。TLS810D1LDV50 包括内部保护功能，例如输出电流限制和过温保护。输出电压由复位功能控制，包括欠压复位和启动时的延迟复位释放。 ;


型号：	TLS810D1LD V50
厂家：	Infineon
描述：	TLS810D1LDV50 是一个线性稳压器，具有较宽的输入电压范围，低电压差和超低静态电流的特点。此产品可采用3.3mm * 3.3mm 新型无铅汽车用封装(TSON10) ，具有经过改善的光学检测特性。稳压器的输入电压范围为 2.75V 至 42V，静态电流极低，仅 9μA，非常适合汽车或任何永久连接电池的其他电源系统。TLS810D1LDV50 有精度为 2% 的 5.0V 输出电压版本可选，输出电流能力可达100mA。它只配有一个小型的陶瓷电容器，输出电流为1μF，十分稳定。此装置可通过启用功能打开或关断，电流损耗低于 1μA。TLS810D1LDV50 的操作范围扩展至2.75V，也适用于启动情况下的汽车系统操作的供电。TLS810D1LDV50 包括内部保护功能，例如输出电流限制和过温保护。输出电压由复位功能控制，包括欠压复位和启动时的延迟复位释放。电池电容器陶瓷电容器装置稳压器
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Ultra Low Quiescent Current Linear

Voltage Regulator

TLS810D1

TLS810D1EJV50

TLS810D1LDV50

Linear Voltage Regulator

Data Sheet

Rev. 1.1, 2015-11-02

Automotive Power

TLS810D1

TLS810D1EJ/LDV50

Overview

Features

•

Ultra Low Quiescent Current of 9 µA

Wide Input Voltage Range of 2.75 V to 42 V

Output Current Capacity up to 100 mA

Off Mode Current Less than 1 µA

Low Drop Out Voltage of typ. 200 mV @ 100 mA

Output Current Limit Protection

Overtemperature Shutdown

Enable

Figure 1

PG-DSO-8 EP

Reset

Available in PG-DSO-8 EP Package

Available in PG-TSON-10 Package

Wide Temperature Range

Green Product (RoHS Compliant)

AEC Qualified

Figure 2

PG-TSON-10

Type

Package

Marking

TLS810D1EJV50

TLS810D1LDV50

PG-DSO-8 EP

PG-TSON-10

810D1V50

Data Sheet

Rev. 1.1, 2015-11-02

TLS810D1EJ/LDV50

Overview

Description

The TLS810D1 is a linear voltage regulator featuring wide input voltage range, low drop out voltage and ultra

low quiescent current.

With an input voltage range of 2.75 V to 42 V and ultra low quiescent of only 9 µA, the regulator is perfectly

suitable for automotive or any other supply systems connected permanently to the battery.

The TLS810D1EJ/LDV50 is the fixed 5 V output version with an accuracy of 2 % and output current capability

up to 100 mA.

The new regulation concept implemented in TLS810D1 combines fast regulation and very good stability while

requiring only a small ceramic capacitor of 1 μF at the output.

The tracking region starts already at input voltages of 2.75 V (extended operating range). This makes the

TLS810D1 also suitable to supply automotive systems that need to operate during cranking condition.

Internal protection features like output current limitation and overtemperature shutdown are implemented

to protect the device against immediate damage due to failures like output short circuit to GND, over-current

and over-temperature.

The device can be switched on and off by the Enable feature. When the device is switched off, the current

consumption is typically less than 1 µA.

The output voltage is supervised by the Reset feature, including undervoltage reset and delayed reset release

at power-on.

Choosing External Components

An input capacitor C_Iis recommended to compensate line influences. The output capacitor C_Qis necessary for

the stability of the regulating circuit. Stability is guaranteed at values C_Q≥ 1 µF and an ESR ≤ 100 Ω within the

whole operating range.

Data Sheet

Rev. 1.1, 2015-11-02

TLS810D1EJ/LDV50

Block Diagram

Current

Limitation

Reset

Enable

Bandgap

Reference

Temperature

Shutdown

GND

Figure 3

Block Diagram TLS810D1

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Pin Configuration

3.1

Pin Assignment in PG-DSO-8 EP Package

N.C.

GND

Figure 4

Pin Configuration TLS810D1 in PG-DSO-8 EP package

3.2

Pin Definitions and Functions in PG-DSO-8 EP Package

Symbol

Function

Input

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close

to the IC terminals, in order to compensate line influences.

N.C.

Not connected

Enable

Integrated pull-down resistor.

Enable the IC with high level input signal.

Disable the IC with low level input signal.

GND

Ground

Reset Delay Timing

Connect a ceramic capacitor to GND for adjusting the reset delay time.

Leave open if the reset function is not needed.

Reset Output

Integrated pull-up resistor.

Open collector output.

Leave open if the reset function is not needed.

N.C.

Not connected

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Pin Configuration

Symbol

Function

Output

Connect an output capacitor C_Qto GND close to the IC’s terminals, respecting the

values specified for its capacitance and ESR in Table 2 “Functional Range” on

Page 9.

Pad

–

Exposed Pad

Connect to heatsink area.

Connect to GND.

3.3

Pin Assignment in PG-TSON-10 Package

TSON-10

N.C.

GND

Figure 5

Pin Configuration TLS810D1 in PG-TSON-10 package

3.4

Pin Definitions and Functions in PG-TSON-10 Package

Symbol

Function

Input

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close

to the IC terminals, in order to compensate line influences.

N.C.

Not connected

Enable

Integrated pull-down resistor.

Enable the IC with high level input signal.

Disable the IC with low level input signal.

N.C.

GND

Not connected

Ground

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Pin Configuration

Symbol

Function

Reset Delay Timing

Connect a ceramic capacitor to GND for adjusting the reset delay time.

Leave open if the reset function is not needed.

Reset Output

Integrated pull-up resistor.

Open collector output.

Leave open if the reset function is not needed.

N.C.

Not connected

Output

Connect an output capacitor C_Qto GND close to the IC’s terminals, respecting the

values specified for its capacitance and ESR in Table 2 “Functional Range” on

Page 9.

N.C.

–

Not connected

Pad

Exposed Pad

Connect to heatsink area.

Connect to GND.

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

General Product Characteristics

4.1

Absolute Maximum Ratings

Table 1

Absolute Maximum Ratings¹⁾

T_j= -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Typ.

Unit

Note or

Test Condition

Number

Min.

-0.3

Max.

Voltage Input I, Enable EN

Voltage

V_I, V_EN

–

P_4.1.1

P_4.1.2

P_4.1.3

Voltage Output Q

Voltage

V_Q

Reset Output RO, Reset Delay D

Voltage

V_RO, V_D

Temperatures

Junction Temperature

Storage Temperature

ESD Absorption

T_j

-40

-55

–

150

°C

–

P_4.1.4

P_4.1.5

T_stg

ESD Susceptibility to GND

V_ESD,HBM-2

–

HBM²⁾

P_4.1.6

ESD Susceptibility to GND

V_ESD,CDM-750

750

CDM³⁾at all pins P_4.1.7

1) Not subject to production testing, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Notes

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

General Product Characteristics

4.2

Functional Range

Table 2

Functional Range

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ.

Max.

Input Voltage Range

V_I

V_Q,nom+V_dr

–

P_4.2.1

P_4.2.2

P_4.2.3

P_4.2.4

P_4.2.5

Extended Input Voltage Range V_I,ext

2.75

3)4)

Output Capacitor

C_Q

–

µF

Ω

°C

Output Capacitor’s ESR

ESR(C_Q)

–

100

Junction temperature

T_j

-40

150

1) Output current is limited internally and depends on the input voltage, see Electrical Characteristics for more details.

2) When V_Iis between V_I,ext.minand V_Q,nom+ V_dr, V_Q= V_I- V_dr. When V_Iis below V_I,ext,min, V_Qcan drop down to 0 V.

3) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.

4) Not subject to production testing, specified by design.

Note: Within the functional or operating range, the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the Electrical Characteristics table.

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

General Product Characteristics

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance TLS810D1 in PG-DSO-8 EP Package

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Package Version

Junction to Case¹⁾

Junction to Ambient

R_thJC

R_thJA

–

K/W

–

P_4.3.1

P_4.3.2

2s2p board²⁾

167

1s0p board, footprint P_4.3.3

only³⁾

Junction to Ambient

R_thJA

–

K/W

1s0p board, 300 mm²P_4.3.4

heatsink area on PCB³⁾

1s0p board, 600 mm²P_4.3.5

heatsink area on PCB³⁾

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70µm Cu).

Table 4

Thermal Resistance TLS810D1 in PG-TSON-10 Package

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

Max.

Package Version

Junction to Case¹⁾

Junction to Ambient

R_thJC

R_thJA

–

K/W

–

P_4.3.6

P_4.3.7

K/W 2s2p board²⁾

184

K/W 1s0p board, footprint P_4.3.8

only³⁾

Junction to Ambient

R_thJA

–

K/W 1s0p board, 300 mm²P_4.3.9

heatsink area on PCB³⁾

K/W 1s0p board, 600 mm²P_4.3.10

heatsink area on PCB³⁾

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70µm Cu).

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.1

Voltage Regulation

The output voltage V_Qis divided by a resistor network. This fractional voltage is compared to an internal

voltage reference and the pass transistor is driven accordingly.

The control loop stability depends on the output capacitor C_Q, the load current, the chip temperature and the

internal circuit structure. To ensure stable operation, the output capacitor’s capacitance and its equivalent

series resistor ESR requirements given in “Functional Range” on Page 9 have to be maintained. For details

see the typical performance graph Output Capacitor Series Resistor ESR(C_Q) versus Output Current I_Q.

Since the output capacitor is used to buffer load steps, it should be sized according to the application’s needs.

An input capacitor C_Iis not required for stability, but is recommended to compensate line fluctuations. An

additional reverse polarity protection diode and a combination of several capacitors for filtering should be

used, in case the input is connected directly to the battery line. Connect the capacitors close to the regulator

terminals.

In order to prevent overshoots during start-up, a smooth ramping up function is implemented. This ensures

almost no overshoots during start-up, mostly independent from load and output capacitance.

Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is

limited and the output voltage decreases.

The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions

(e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the

regulator restarts. This oscillatory thermal behaviour causes the junction temperature to exceed the

maximum rating of 150°C and can significantly reduce the IC’s lifetime.

Regulated

Output Voltage

Supply

I_Q

Current

Limitation

ESR

LOAD

V_I

V_Q

C_I

Bandgap

C_Q

Reference

Temperature

Shutdown

GND

Figure 6

Block Diagram Voltage Regulation

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

Table 5

Electrical Characteristics

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified).

Typical values are given at T_j= 25 °C, V_I= 13.5 V.

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Output Voltage Precision

V_Q

4.90

5.00

5.10

50 µA ≤ I_Q≤ 100 mA,

5.7 V ≤ V_I≤ 28 V

P_5.1.1

Output Voltage Precision

V_Q

4.90

5.00

5.10

50 µA ≤ I_Q≤ 50 mA,

5.7 V ≤ V_I≤ 42 V

P_5.1.2

Output Current Limitation I_Q,lim

110

–

190

260

mA 0 V ≤ V_Q≤ V_Q,nom- 0.1 V

P_5.1.3

P_5.1.4

Line Regulation

steady-state

ΔV_Q,line

I_Q= 1 mA, 6 V ≤ V_I≤ 32 V

Load Regulation

steady-state

ΔV_Q,load-20

-1

–

V_I= 6 V,

50 µA ≤ I_Q≤ 100 mA

P_5.1.5

P_5.1.6

P_5.1.7

Dropout Voltage¹⁾

V_dr

–

200

550

–

I_Q= 100 mA

V_dr= V_I- V_Q

Ripple Rejection²⁾

PSRR

I_Q= 50 mA,

f_ripple= 100 Hz,

_ripple= 0.5 V_p-p

Overtemperature

Shutdown Threshold

T_j,sd

151

–

175

–

°C

T_jincreasing

T_jdecreasing

P_5.1.8

P_5.1.9

Overtemperature

Shutdown Threshold

Hysteresis

T_j,sdh

1) Measured when the output voltage V_Qhas dropped 100 mV from the nominal value obtained at V_I= 13.5V

2) Not subject to production test, specified by design

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.2

Typical Performance Characteristics Voltage Regulation

Typical Performance Characteristics

Output Voltage V_Qversus

Junction Temperature T_j

Output Current I_Qversus

Input Voltage V_I

300

250

200

150

100

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

5.15

5.1

5.05

4.95

4.9

4.85

V_I= 13.5 V

I_Q= 50 mA

4.8

V_I[V]

T_j[°C]

100

150

Dropout Voltage V_drversus

Junction Temperature T_j

Dropout Voltage V_drversus

Output Current I_Q

400

I_Q= 10 mA

T_j= −40 °C

I_Q= 50 mA

T_j= 25 °C

350

I_Q= 100 mA

T_j= 150 °C

300

250

200

150

100

250

200

150

100

150

100

T_j[°C]

I_Q[mA]

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

Load Regulation ΔV_Q,loadversus

Output Current I_Q

Line Regulation ΔV_Q,lineversus

Input Voltage V_I

T_j= −40 °C

T = −40 °C

T_j= 25 °C

T = 25 °C

T_j= 150 °C

T = 150 °C

−2

−4

−6

−8

−10

−2

−4

−6

−8

V = 6 V

I_Q= 1 mA

35 40

−10

100

V_I[V]

[mA]

Output Voltage V_Qversus

Input Voltage V_I

Power Supply Ripple Rejection PSRR versus

Ripple Frequency f_r

I_Q= 10 mA

C_Q= 1 μF

V_I= 13.5 V

V_ripple= 0.5 Vpp

I_Q= 50 mA

T_j= 25 °C

10⁻²

10⁻¹

10⁰

10¹

10²

10³

V_I[V]

f [kHz]

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

Output Capacitor Series Resistor ESR(C_Q) versus

Output Current I_Q

10³

Unstable Region

10²

10¹

Stable Region

10⁰

10⁻¹

= 1 μF

V = 3...28 V

10⁻²

100

[mA]

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.3

Current Consumption

Table 6

Electrical Characteristics Current Consumption

T_j= -40 °C to +150 °C, V_I= 13.5 V (unless otherwise specified).

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min.

Typ. Max.

Current Consumption

I_q= I_I

I_q,off

I_q

–

µA

V_EN≤ 0.4 V, T_j< 105 °C

I_Q= 50 µA, T_j= 25 °C

I_Q= 50 µA, T_j< 105 °C

I_Q= 50 µA, T_j< 125 °C

I_Q= 100 mA, T_j< 125 °C

P_5.3.1

P_5.3.2

P_5.3.3

P_5.3.4

P_5.3.5

Current Consumption

I_q= I_I- I_Q

–

11.5

Current Consumption

I_q= I_I- I_Q

I_q

11.5 14.5

Current Consumption

I_q= I_I- I_Q

I_q

Current Consumption

I_q

I_q= I_I- I_Q

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.4

Typical Performance Characteristics Current Consumption

Typical Performance Characteristics

Current Consumption I_qversus

Output Current I_Q

Current Consumption I_qversus

Input Voltage V_I

T_j= −40 °C

T_j= 25 °C

T_j= 105 °C

T_j= 125 °C

V_I= 13.5 V

I_Q= 50 μA

35 40

100

V_I[V]

I_Q[mA]

Current Consumption I_qversus

Junction Temperature T_j

Current Consumption in OFF mode I_q,offversus

Junction Temperature T_j

V_I= 13.5 V

V_EN≤ 0.4 V

3.5

2.5

1.5

V_I= 13.5 V

0.5

I_Q= 50 μA

100

150

100

150

T_j[°C]

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.5

Enable

The device can be switched on and off by the Enable feature. Connect a HIGH level as specified below (e.g. the

battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to switch it

off. The Enable function has a build-in hysteresis to avoid toggling between ON/OFF state, if signals with slow

slopes are appiled to the EN input.

Table 7

Electrical Characteristics Enable

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified).

Typical values are given at T_j= 25 °C, V_I= 13.5 V.

Parameter

Symbol

Values

Unit Note or Test Condition

Number

Min. Typ. Max.

Enable High Level Input

Voltage

V_EN,H

V_EN,L

I_EN,H

–

V_Qsettled

V_Q≤ 0.1 V

V_EN= 5 V

–

P_5.5.1

P_5.5.2

P_5.5.3

P_5.5.4

Enable Low Level Input

Voltage

–

0.8

Enable High Level Input

Current

–

µA

MΩ

Enable Internal Pull-down R_EN

Resistor

1.25

3.5

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.6

Typical Performance Characteristics Enable

Typical Performance Characteristics

Enable Input Current I_ENversus

Enable Input Voltage V_EN

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

V_EN[V]

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.7

Reset Function

The reset function provides several features:

Output Undervoltage Reset

An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal may be

used to reset a microcontroller during low supply voltage.

Power-On Reset Delay Time

The power-on reset delay time t_rdallows microcontoller and oscillator to start up. This delay time is the time

frame from exceeding the reset switching threshold V_RTuntil the reset is released by switching the reset output

“RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor C_D

connected to pin D charged by the delay capacitor charge current I_D,chstarting from V_D= 0 V.

If the application needs a power-on reset delay time t_rddifferent from the value given in Table 8, the delay

capacitor’s value can be derived from the specified value and the desired power-on delay time:

t_rd,new

•

100 nF

C_D

t_rd

(5.1)

with

•

C_D: capacitance of the delay capacitor to be chosen

_rd,new: desired power-on reset delay time

t_rd: power-on reset delay time specified in this datasheet

For a precise calculation also take the delay capacitor’s tolerance into consideration.

Reset Reaction Time

The reset reaction rime t_rrconsiders the internal reaction time t_rr,intand the discharge time t_rr,ddefined by the

external delay capacitor C_D(see typical performance graph for details). Hence, the total reset reaction time

becomes:

t_rr

t_rr,int

rr,d

(5.2)

with

•

t_rr: reset reaction time

_rr,int: internal reset reaction time

_rr,d: reset discharge

Optional Reset Output Pull-Up Resistor R_RO,ext

The Reset Output RO is an open collector output with an integrated pull-up resistor. If needed, an external

pull-up resistor to the output Q can be added. In Table 8 a minimum value for the external resistor R_RO,extis

given.

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

Supply

VDD

Int.

Supply

R_RO

C_Q

R_{RO ,ext}

Control

I_D,ch

Reset

I_RO

V_DST

V_{RADJ ,th}

Micro-

Controller

I_D,dch

GND

C_D

Figure 7

Block Diagram Reset Function

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

V_I

t < t_rr,total

V_Q

V_RT,high

V_RT,low

1 V

t_rd

V_D

V_DU

V_DRL

t_rd

t_rr,total

t_rd

t_rr,total

t_rd

t_rr,total

V_RO

V_RO,low

Thermal

Shutdown

Input

Voltage Dip

Under-

voltage

Spike at Over-

output load

TimingDiagram_Reset.vsd

Figure 8

Table 8

Timing Diagram Reset

Electrical Characteristics Reset

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified).

Typical values are given at T_j= 25 °C, V_I= 13.5 V.

Parameter

Symbol

Values

Typ.

Unit Note or

Test Condition

Number

Min.

V_RT,high4.6

V_RT,low4.5

Max.

Output Undervoltage Reset

Upper Switching Threshold

4.7

4.6

4.8

4.7

V_Qincreasing,

_EN≥ 2.0 V

V_Qdecreasing,

_EN≥ 2.0 V

P_5.7.1

P_5.7.2

Output Undervoltage Reset

Lower Switching Threshold

Reset Output RO

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

Table 8

Electrical Characteristics Reset (cont’d)

T_j= -40 °C to +150 °C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified).

Typical values are given at T_j= 25 °C, V_I= 13.5 V.

Parameter

Symbol

Values

Typ.

0.2

Unit Note or

Test Condition

Number

Min.

Max.

Reset Output Low Voltage

V_RO,low

0.4

1 V ≤ V_Q≤ V_RT;

_RO> 4.7 kΩ

P_5.7.3

Reset Output

Internal Pull-Up Resistor

R_RO,int

R_RO,ext

–

kΩ

Internally connected P_5.7.4

to Q

Reset Output External

Pull-up Resistor to V_Q

4.7

1 V ≤ V_Q≤ V_RT;

V_RO≤ 0.4 V

P_5.7.5

Reset Delay Timing

Power On Reset Delay Time

t_rd

C_D= 100 nF

P_5.7.6

Calculated vaule

Upper Delay Switching

Threshold

V_DU

V_DL

–

0.9

0.6

–

P_5.7.7

P_5.7.8

Lower Delay Switching

Threshold

–

Delay Capacitor Charge Current I_D,ch

–

3.6

–

µA

V_D= 1 V

P_5.7.9

Delay Capacitor Discharge

Current

I_D,dch

250

mA V_D= 1 V

P_5.7.10

Delay Capacitor Discharge Time t_rr,d

–

µs

C_D= 100 nF

P_5.7.11

Calculated value

Internal Reset Reaction Time¹⁾

Reset Reaction Time

t_rr,int

–

µs

C_D= 0 nF

P_5.7.12

P_5.7.13

t_rr,total

C_D= 100 nF

Calculated value

1) Parameter not subject to production test; specified by design.

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Block Description and Electrical Characteristics

5.8

Typical Performance Characteristics Reset

Typical Performance Characteristics

Undervoltage Reset Threshold V_RTversus

Junction Temperature T_j

Power On Reset Delay Time t_rdversus

Junction Temperature T_j

V_{RT high}

4.95

V_{RT low}

4.9

4.85

4.8

4.75

4.7

4.65

4.6

4.55

4.5

= 100 nF

100

150

100

150

T [°C]

T_j[°C]

Internal Reset Reaction Time t_rr,intversus

Junction Temperature T_j

100

150

T [°C]

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

6.1

Application Diagram

Regulated

Output Voltage

D_I1

I_Q

Supply

I_I

R_RO

e.g. Ignition

Load

(e.g.

TLS810D1

Micro

Controller)

C_Q

D_I2

C_I2

C_I1

1μF

<45V

10μF 100nF

C_D

GND

100nF

Figure 9

Application Diagram

6.2

Selection of External Components

Input Pin

6.2.1

The typical input circuitry for a linear voltage regulator is shown in the application diagram above.

A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high

frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to

the input pin of the linear voltage regulator on the PCB.

An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to

smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of

the linear voltage regulator on the PCB.

An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum

rating of the linear voltage regulator and protect the device against any damage due to over-voltage.

The external components at the input are not mandatory for the operation of the voltage regulator, but they

are recommended in case of possible external disturbances.

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Application Information

6.2.2

Output Pin

An output capacitor is mandatory for the stability of linear voltage regulators.

The requirement to the output capacitor is given in “Functional Range” on Page 9. The graph “Output

Capacitor Series Resistor ESR(C_Q) versus Output Current I_Q” on Page 15 shows the stable operation range

of the device.

TLS810D1 is designed to be stable with extremely low ESR capacitors. According to the automotive

environment, ceramic capacitors with X5R or X7R dielectrics are recommended.

The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the

same side of the PCB as the regulator itself.

In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in

accordance and verified in the real application that the output stability requirements are fulfilled.

6.3

Thermal Considerations

Knowing the input voltage, the output voltage and the load profile of the application, the total power

dissipation can be calculated:

P_D= (V_I– V_Q) × I_Q+ V_I× I_q

(6.1)

with

•

P_D: continuous power dissipation

V_I: input voltage

V_Q: output voltage

I_Q: output current

I_q: quiescent current

The maximum acceptable thermal resistance R_thJAcan then be calculated:

T_{j, max}– T_a

R_{thJA, max}= ---------------------------

P_D

(6.2)

with

•

T_j,max: maximum allowed junction temperature

T_a: ambient temperature

Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with

reference to the specification in “Thermal Resistance” on Page 10.

Example

Application conditions:

V_I= 13.5 V

V_Q= 5 V

I_Q= 80 mA

T_a= 105 °C

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Application Information

Calculation of R_thJA,max

P_D= (V_I– V_Q) x I_Q+ V_Ix I_q

= (13.5V – 5V) x 80 mA + 13.5 V x 0.016 mA

= 0.68 W

_thJA,max= (T_j,max– T_a) / P_D

= (150 °C – 105 °C) / 0.68 W

= 66.2 K/W

As a result, the PCB design must ensure a thermal resistance R_thJAlower than 66.2 K/W. According to “Thermal

Resistance” on Page 10, for both TLS810D1EJV50 and TLS810D1LDV50 at least 600 mm² heatsink area is

needed on the FR4 1s0p PCB, or the FR4 2s2p board can be used.

6.4

Reverse Polarity Protection

TLS810D1 is not self protected against reverse polarity faults. To protect the device against negative supply

voltage, an external reverse polarity diode is needed, as shown in Figure 9. The absolute maximum ratings of

the device as specified in “Absolute Maximum Ratings” on Page 8 must be kept.

6.5

Further Application Information

•

For further information you may contact http://www.infineon.com/

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Package Outlines

0.35 x 45°

±0.1

3.9

0.1 C D 2x

+0.06

0.19

0.08

Seating Plane

0.64_±0.25

±0.2

0.2

1.27

0.2

±0.09

0.41

D 8x

C A-B D 8x

Bottom View

±0.2

0.1 C A-B 2x

±0.1

4.9

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width

3) JEDEC reference MS-012 variation BA

Figure 10 PG-DSO-8 EP

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Package Outlines

±0.1

2.58

±0.1

0.1

±0.1

3.3

0.36

0.53

0.05

Pin 1 Marking

±0.1

0.5

Pin 1 Marking

±0.1

0.25

PG-TSON-10-2-PO V02

Z (4:1)

0.07 MIN.

Figure 11 PG-TSON-10

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Data Sheet

Rev. 1.1 2015-11-02

TLS810D1EJ/LDV50

Revision History

Revision

Date

Changes

1.1

2015-11-02 - New variant TLS810D1LDV50 in PG-TSON-10 package added.

- Document style updated.

- Typical performance graph Load Regulation updated.

- Editorial changes.

1.0

2015-01-27 Datasheet - Initial Version

Data Sheet

Rev. 1.1 2015-11-02

Trademarks of Infineon Technologies AG

AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™,

EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, LITIX™, MIPAQ™,

ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,

ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,

UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of

Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay

Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association

Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.

MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA

MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave

Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of

Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.

TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas

Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.

Last Trademarks Update 2011-11-11

www.infineon.com

Edition 2015-11-02

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in

no event be regarded as

Warnings

Due to technical requirements, components

may contain dangerous substances. For

information on the types in question, please

contact the nearest Infineon Technologies

Office. Infineon Technologies components may

be used in life-support devices or systems only

with the express written approval of Infineon

Technologies, if a failure of such components

can reasonably be expected to cause the failure

of that life-support device or system or to affect

the safety or effectiveness of that device or

system. Life support devices or systems are

intended to be implanted in the human body or

to support and/or maintain and sustain and/or

protect human life. If they fail, it is reasonable to

assume that the health of the user or other

persons may be endangered.

a guarantee of

conditions or characteristics. With respect to any

examples or hints given herein, any typical

values stated herein and/or any information

regarding the application of the device, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation, warranties of non-

infringement of intellectual property rights of

any third party.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Information

For further information on technology, delivery

terms and conditions and prices, please contact

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(www.infineon.com).

TLS810D1LD V50 [INFINEON]

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