TLS820F0EL V33_技术文档

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Features

•

Wide input voltage range from 3.0 V to 40 V

Fixed output voltage 5 V or 3.3 V

Output voltage precision ≤ ±2 %

Output current capability up to 200 mA

Ultra low current consumption typ. 40 µA

Very low dropout voltage typ. 70 mV @100 mA

Stable with ceramic output capacitor of 1 µF

Delayed reset at power-on with 2 Programmable delay times 8.5 ms / 16.5 ms

Adjustable reset threshold down to 2.50 V

Watchdog with flexible timings and current dependent deactivation: 16 ms / 32 ms / 48 ms / 96 ms,

Activated at I_Q> 5.5 mA

•

Enable, undervoltage reset, overtemperature shutdown

Output current limitation

Wide temperature range

Green product (RoHS compliant)

Potential applications

•

Automotive general ECUs

Dashboard and cluster supplies

Powertrain and EPS applications

Microcontroller supply for safety applications

Product validation

Qualified for automotive applications. Product validation according to AEC-Q100/101.

Description

The OPTIREG™ linear TLS820F0ELVxx is a high performance very low dropout linear voltage regulator for 5 V

(TLS820F0ELV50) or 3.3 V (TLS820F0ELV33) supply in a PG-SSOP-14 package.

With an input voltage range of 3 V to 40 V and very low quiescent of only 40 µA, these regulators are perfectly

suitable for automotive or any other supply systems connected to the battery permanently. The TLS820F0

provides an output voltage accuracy of 2 % and a maximum output current up to 200 mA.

Datasheet

Rev. 1.2

2021-04-08

www.infineon.com/OPTIREG-linear

1

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

The new loop concept combines fast regulation and very good stability while requiring only one small ceramic

capacitor of 1 µF at the output. At currents below 100 mA the device will have a very low typical dropout

voltage of only 70 mV (for 5 V device) and 80 mV (for 3.3 V device). The operating range starts already at input

voltages of only 3 V (extended operating range). This makes the TLS820F0 also suitable to supply automotive

systems that need to operate during cranking condition.

The device can be switched on and off by the enable feature as described in Chapter 4.5.

The output voltage is supervised by the reset feature, including undervoltage reset, delayed reset at power-on

and an adjustable lower reset threshold. More details can be found in Chapter 4.7.

In addition, a watchdog circuit with flexible timings is integrated to monitor the microcontroller‘s operation.

Internal protection features like output current limitation and overtemperature shutdown are implemented

to protect the device against immediate damage due to failures like output short circuit to GND, over-current

and over-temperatures.

External components

An input capacitor C_Iis recommended to compensate line influences. The output capacitor C_Qis necessary for

the stability of the regulating circuit. TLS820F0 is designed to be also stable with low ESR ceramic capacitors.

Type

Package

Marking

820F0V50

820F0V33

TLS820F0ELV50

TLS820F0ELV33

PG-SSOP-14

Datasheet

2

Rev.1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Table of contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2

2.1

2.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin assignment TLS820F0ELV50 and TLS820F0ELV33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin definitions and functions TLS820F0ELV50 and TLS820F0ELV33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1

3.2

3.3

4

Block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Typical performance characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typical performance characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Typical performance characteristics enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Typical performance characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Standard watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Typical performance characteristics standard watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

5

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Selection of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1

5.2

5.2.1

5.2.2

5.3

5.4

5.5

6

7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Datasheet

3

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block diagram

1

Block diagram

I

Q

RO

Current

Limitation

Reset

EN

RADJ

Enable

Bandgap

Reference

DT1

DT2

WI

Temperature

Shutdown

WO

Watchdog

GND

Figure 1

Block diagram TLS820F0ELV50 and TLS820F0ELV33

Datasheet

4

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Pin configuration

2

Pin configuration

2.1

Pin assignment TLS820F0ELV50 and TLS820F0ELV33

SSOP-14

I

1

2

3

4

5

6

7

14

13

12

11

10

9

Q

n.c.

WO

EN

n.c.

RO

DT2

GND

n.c.

DT1

RADJ

8

WI

Figure 2

Pin configuration

2.2

Pin definitions and functions TLS820F0ELV50 and TLS820F0ELV33

Symbol

Function

1

I

Input

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close

to the IC terminals, in order to compensate line influences. See also

Chapter 5.2.1

2, 4, 6 n.c.

Not connected

Leave open or connect to GND

3

EN

Enable (integrated pull-down resistor)

Enable the IC with high level input signal;

Disable the IC with low level input signal;

5

7

GND

WI

Ground

Watchdog input (integrated pull-down resistor)

Serve Watchdog with trigger input signal (usable for microcontroller monitoring)

8

9

RADJ

DT1

Reset threshold adjustment

Connect to GND to use standard value;

Connect an external voltage divider to adjust reset threshold

Delay timing 1 (integrated pull-down resistor)

Connect to GND or Q to select Reset timing acc. to Table 8

Connect to GND or Q to select Watchdog timing acc. to Table 11

10

11

DT2

RO

Delay timing 2 (integrated pull-down resistor)

Connect to GND or Q to select Watchdog timing acc. to Table 11

Reset output (integrated pull-up resistor to Q)

Open collector output;

Leave open if the reset function is not needed

Datasheet

5

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Pin configuration

Symbol

Function

12

WO

Watchdog output (integrated pull-up resistor to Q)

Open collector output;

Leave open if the watchdog function is not needed

13

14

n.c.

Q

Not connected

Leave open or connect to GND

Output voltage

Connect output capacitor C_Qto GND close to the IC’s terminals, respecting the

values specified for its capacitance and ESR in “Functional range” on Page 8

Pad

–

Exposed pad

Connect to heatsink area;

Connect to GND

Datasheet

6

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

General product characteristics

3

General product characteristics

3.1

Absolute maximum ratings

Table 1

Absolute maximum ratings¹⁾

T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Input I, Enable EN

Voltage

V_I, V_EN

-0.3

–

45

7

V

–

P_4.1.1

P_4.1.3

P_4.1.5

Output Q, Watchdog output WO

Voltage

V_Q, V_RO, V_WO-0.3

–

Watchdog input WI, Delay timing DT1 and DT2, Reset threshold adjustment RADJ

Voltage

V_WI,V_DT1

,

-0.3

–

7

V

–

V

_DT2, V_RADJ

Temperatures

Junction temperature

Storage temperature

ESD absorption

T_j

-40

-55

–

150

°C

–

P_4.1.7

P_4.1.8

T_stg

ESD susceptibility to GND

V_ESD

-2

–

2

kV

V

²⁾HBM

³⁾CDM

P_4.1.9

-500

500

750

P_4.1.10

P_4.1.11

ESD susceptibility pin 1, 7, 8, 14 (corner V_ESD1,7,8,14-750

pins) to GND

V

1) Not subject to production test, specified by design.

2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)

3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101

Note:

1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are

not designed for continuous repetitive operation.

Datasheet

7

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

General product characteristics

3.2

Functional range

Table 2

Functional range

T_j= -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min.

Typ.

Max.

40

1)

Input voltage range

V_I

V_Q,nom+ V_dr

–

V

–

P_4.2.1

P_4.2.3

P_4.2.5

P_4.2.6

2)

Extended input voltage range

Enable voltage range

V_I,ext

V_EN

C_Q

3.0

0

40

V

40

V

–

3)4)

Output capacitor’s

1

–

µF

–

requirements for stability

3)

ESR

ESR(C_Q)

T_j

–

100

150

Ω

–

P_4.2.7

P_4.2.9

Junction temperature

-40

°C

–

1) Output current is limited internally and depends on the input voltage, see Electrical Characteristics for more details.

2) When V_Iis between V_I,ext,minand V_Q,nom+ V_dr, V_Q= V_I- V_dr. When V_Iis below V_I,ext,min, V_Qcan drop down to 0 V.

3) Not subject to production test, specified by design.

4) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%

Note:

Within the functional or operating range, the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the Electrical Characteristics

table.

Datasheet

8

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

General product characteristics

3.3

Thermal resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 3

Thermal resistance

Parameter

Symbol

Values

Min. Typ.

Unit Note or

Test Condition

Number

Max.

Package version PG-SSOP-14

Junction to case

1)

R_thJC

R_thJA

–

9

–

K/W

–

P_4.3.1

P_4.3.2

P_4.3.3

Junction to ambient

43

¹⁾²⁾2s2p board

¹⁾³⁾1s0p board,

footprint only

128

Junction to ambient

R_thJA

–

58

50

–

K/W

¹⁾³⁾1s0p board,

300 mm²heatsink

area on PCB

¹⁾³⁾1s0p board,

600 mm²heatsink

area on PCB

P_4.3.4

P_4.3.5

R_thJA

1) Not subject to production test, specified by design

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Specified R_thJAvalue is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³board with 1 copper layer (1 x 70µm Cu).

Datasheet

9

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4

Block description and electrical characteristics

4.1

Voltage regulation

The output voltage V_Qis divided by a resistor network. This fractional voltage is compared to an internal

voltage reference and the pass transistor is driven accordingly.

The control loop stability depends on the output capacitor C_Q, the load current, the chip temperature and the

internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent

series resistor (ESR) requirements given in “Functional range” on Page 8 have to be maintained. For details,

also see the typical performance graph “Output capacitor series resistor ESR(CQ) versus output current

IQ” on Page 15. As the output capacitor also has to buffer load steps, it should be sized according to the

application’s needs.

An input capacitor C_Iis recommended to compensate line influences. In order to block influences like pulses

and HF distortion at input side, an additional reverse polarity protection diode and a combination of several

capacitors for filtering should be used. Connect the capacitors close to the component’s terminals.

In order to prevent overshoots during start-up, a smooth ramp up function is implemented. This ensures

almost no output voltage overshoots during start-up, mostly independent from load and output capacitance.

Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is

limited and the output voltage decreases.

The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions

(e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the

regulator restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed.

However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly

reduce the IC’s lifetime.

Regulated

Output Voltage

Supply

I_Q

I_I

I

Q

RO

Current

Limitation

Reset

EN

RADJ

C

Enable

C_I

V_I

V_Q

Bandgap

Reference

LOAD

ESR

DT1

DT2

Temperature

Shutdown

C_Q

WI

WO

Watchdog

GND

Figure 3

Voltage regulation

V

V_I

V_dr

V_Q,nom

V_I,ext,min

V_Q

t

Figure 4

Output voltage vs. input voltage

Datasheet

10

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Table 4

Electrical characteristics voltage regulator 5 V version

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Output voltage precision

Output Voltage Precision

V_Q

4.9

5.0

7.5

5.1

18

V

0.05 mA < I_Q< 200 mA

5.44 V < V_I< 28 V

P_5.1.1

P_5.1.2

P_5.1.7

4.9

0.05 mA < I_Q< 100 mA

5.27 V < V_I< 40 V

Output voltage start-up

slew rate

dV_Q/dt 3.0

V/ms V_I> 18 V/ms

C_Q= 1 µF

0.5 V < V_Q< 4.5 V

Output current limitation

I_Q,max

201

350 550 mA 0 V < V_Q< 4.8 V

P_5.1.8

Load regulation

steady-state

ΔV_Q,load-15

-1.5

0

5

mV I_Q= 0.05 mA to 200 mA

V_I= 6 V

P_5.1.10

Line regulation

steady-state

ΔV_Q,line-25

25

mV V_I= 8 V to 32 V

I_Q= 1 mA

P_5.1.12

P_5.1.14

P_5.1.15

P_5.1.18

P_5.1.19

P_5.1.20

Dropout voltage

V_dr= V_I- V_Q

V_dr

–

140 340 mV ¹⁾I_Q= 200 mA

Dropout voltage

V_dr= V_I- V_Q

V_dr

–

70

59

–

170 mV ¹⁾I_Q= 100 mA

2)

Power supply ripple rejection

PSRR

T_j,sd

T_j,sdh

–

dB

f

= 100 Hz

ripple

V

_ripple= 0.5 Vpp

Overtemperature shutdown

threshold

151

–

200 °C

²⁾T_jincreasing

Overtemperature shutdown

threshold hysteresis

15

–

K

²⁾T_jdecreasing

1) Measured when the output voltage V_Qhas dropped 100 mV from the nominal value obtained at V_I= 13.5V

2) Not subject to production test, specified by design

Datasheet

11

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Table 5

Electrical characteristics voltage regulator 3.3 V version

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Output voltage precision

V_Q

3.23 3.3

3.37

18

V

0.05 mA < I_Q< 200 mA

3.72 V < V_I< 28 V

P_5.1.21

P_5.1.22

P_5.1.27

3.23 3.3

0.05 mA < I_Q< 100 mA

3.55 V < V_I< 40 V

Output voltage start-up

slew rate

dV_Q/dt 3.0

7.5

V/ms V_I> 18 V/ms

C_Q= 1 µF

0.33 V < V_Q< 2.97 V

Output current limitation

I_Q,max

201

350 550 mA 0 V < V_Q< 3.1 V

P_5.1.28

P_5.1.30

Load regulation

steady-state

ΔV_Q,load-15

-1.5

0

5

mV I_Q= 0.05 mA to 200 mA

V_I= 6 V

Line regulation

steady-state

ΔV_Q,line-20

20

mV V_I= 8 V to 32 V

I_Q= 1 mA

P_5.1.32

P_5.1.34

P_5.1.35

P_5.1.38

P_5.1.39

P_5.1.40

Dropout voltage

V_dr= V_I- V_Q

V_dr

–

160 350 mV ¹⁾I_Q= 200 mA

Dropout voltage

V_dr= V_I- V_Q

V_dr

–

80

63

–

175 mV ¹⁾I_Q= 100 mA

2)

Power supply ripple rejection

PSRR

T_j,sd

T_j,sdh

–

dB

f

= 100 Hz

ripple

V

_ripple= 0.5 Vpp

Overtemperature shutdown

threshold

151

–

200 °C

²⁾T_jincreasing

Overtemperature shutdown

threshold hysteresis

15

–

K

²⁾T_jdecreasing

1) Measured when the output voltage V_Qhas dropped 100 mV from the nominal value obtained at V_I= 13.5V

2) Not subject to production test, specified by design

Datasheet

12

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.2

Typical performance characteristics voltage regulator

Typical performance characteristics

Output voltage V_Qversus

junction temperature T_j(3.3 V version)

junction temperature T_j(5 V version)

3.5

I_Q= 100mA

3.45

3.4

5.15

5.1

3.35

3.3

5.05

5

3.25

3.2

4.95

4.9

3.15

3.1

4.85

4.8

0

50

100

150

0

50

100

150

T_j[°C]

Dropout voltage V_drversus

junction temperature T_j(3.3 V version)

junction temperature T_j(5 V version)

300

I_Q= 100 mA

I_Q= 200 mA

250

200

150

100

50

250

200

150

100

50

V_Q= 3.3 V

V_Q= 5 V

0

50

100

150

0

50

100

150

T_j[°C]

Datasheet

13

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Load regulation ΔV_Q,loadversus

output current change I_Q

Line regulation ΔV_Q,lineversus

input voltage V_I

0

−0.5

−1

8

6

4

−1.5

−2

2

−2.5

−3

0

−2

−4

−6

−8

−3.5

V_I= 6 V

I_Q= 1 mA

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

−4

T_j= −40 °C

T_j= 25 °C

−4.5

T_j= 150 °C

−5

0

50

100

150

200

10

15

20

25

30

I_Q[mA]

V_I[V]

Output voltage V_Qversus

Input voltage V_I(3.3 V version)

Input voltage V_I(5 V version)

4

6

T_j= −40 °C

T_j= 25 °C

3.5

5

T_j= 150 °C

I_Q= 100 mA

3

I_Q= 100 mA

4

2.5

2

3

2

1

0

1.5

1

0.5

0

1

2

3

4

5

6

0

1

2

3

4

5

6

V_I[V]

Datasheet

14

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Power supply ripple rejection PSRR versus

ripple frequency f

Output capacitor series resistor ESR(C_Q) versus

output current I_Q

10³

80

V_Q= 3.3 V

V_Q= 5 V

70

Unstable Region

10²

60

50

40

30

10¹

Stable Region

10⁰

20

10

0

I_Q= 10 mA

_Q= 1 μF

_ripple= 0.5 V_PP

10⁻¹

C

V

T_j= 25 °C

C_Q= 1 μF

T_j= 25 °C

10⁻²

10⁻¹

10⁰

10¹

10²

10³

0.05

1

10

200

I_Q[mA]

f [kHz]

Maximum output current I_Qversus

input voltage V_I

Dropout voltage V_drversus

output current I_Q

800

300

V_Q= 3.3 V

T_j= −40 °C

V_Q= 5 V

700

600

500

400

300

200

100

0

T_j= 25 °C

T_j= 150 °C

V_Q= 0 V

250

T_j= 25 °C

200

150

100

50

0

10

20

30

40

0

50

100

150

200

V_I[V]

I_Q[mA]

Datasheet

15

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.3

Current consumption

Table 6

Electrical characteristics current consumption

T_j= -40°C to 150°C, V_I= 13.5 V (unless otherwise specified)

Typical values are given at T_j= 25 °C

Conditions of other pins: DT1 = DT2 = WI = GND

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Current consumption

I_q= I_I

I_q,off

I_q

–

1.3

5

µA

V_EN= 0 V; T_j< 105 °C

V_EN= 0.4 V; T_j< 125 °C

P_5.3.1

P_5.3.3

P_5.3.4

P_5.3.7

P_5.3.9

Current consumption

I_q= I_I

–

8

Current consumption

I_q= I_I- I_Q

40

62

52

77

80

I_Q= 0.05 mA

T_j= 25 °C

Current consumption

I_q= I_I- I_Q

I_q

I_Q= 0.05 mA

T_j< 125 °C

¹⁾I_Q= 200 mA

T_j< 125 °C

Current consumption

I_q= I_I- I_Q

I_q

1) Not subject to production test, specified by design

Datasheet

16

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.4

Typical performance characteristics current consumption

Typical performance characteristics

Current consumption I_qversus

output current I_Q

Current consumption I_qversus

input voltage V_I

100

200

180

160

140

120

100

80

T_j= 25 °C

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

90

80

70

60

50

40

30

20

10

0

V_EN= 5 V

I_Q= 50 uA

60

40

20

0

50

100

150

200

5

10

15

20

V_I[V]

25

30

35

40

I_Q[mA]

Datasheet

17

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.5

Enable

The TLS820F0 can be switched on and off by the enable feature: connect a HIGH level as specified below (e.g.

the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to shut

it down. The enable has a built in hysteresis to avoid toggling between ON/OFF state, if signals with slow

slopes are applied to the EN input.

Table 7

Electrical characteristics enable

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

High level input voltage

Low level input voltage

Enable threshold hysteresis

High level input current

V_EN,H

V_EN,L

V_EN,Hy

I_EN,H

R_EN

2

–

V

V_Qsettled

V_Q≤ 0.1 V

–

P_5.5.1

P_5.5.2

P_5.5.3

P_5.5.4

P_5.5.6

P_5.5.7

–

0.8

–

V

100

–

mV

µA

MΩ

3.5

22

2.6

V_EN= 3.3 V

V_EN≤ 18 V

–

Enable internal pull-down

resistor

0.95 1.5

Datasheet

18

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.6

Typical performance characteristics enable

Typical performance characteristics

Input current I_INversus

input voltage V_IN(condition: V_EN= 0 V)

Enable input current I_ENversus

enable input voltage V_EN

30

50

T_j= −40 °C

45

T_j= 25 °C

25

T_j= 150 °C

40

35

30

25

20

15

10

5

V_EN= 0V

20

15

10

5

0

10

20

30

40

0

10

20

30

40

V_IN[V]

V_EN[V]

Output voltage V_Qversus

time (EN switched ON, 5 V version)

time (EN switched ON, 3.3 V version)

6

5

4

3

2

5

4

3

2

I_Q= 100 mA

T_j= −40 °C

I_Q= 100 mA

T_j= −40 °C

T_j= 25 °C

T_j= 150 °C

V_EN

T_j= 25 °C

T_j= 150 °C

V_EN

1

0

1

0

500

1000

t [us]

1500

2000

0

500

1000

t [us]

1500

2000

Datasheet

19

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.7

Reset

The TLS820F0’s output voltage is supervised by the reset feature, including undervoltage reset, delayed reset

at power-on and an adjustable reset threshold.

The undervoltage reset function sets the pin RO to LOW, in case V_Qis falling for any reason below the reset

threshold V_RT,low

.

When the regulator is powered on, the pin RO is held at LOW for the duration of the power-on reset delay time

t_rd.

Supply

I

Q

VDD

C_Q

R_RO,int

Control

RO

Reset

S

R

I_RO

Reference

OR

Q

OR

Micro-

Controller

R_{ADJ ,1}

Timer

RADJ

I_RADJ

GND

DT1

GND

R_{ADJ ,2}

Figure 5

Block diagram reset circuit

Reset delay time

The pin DT1 is used to set the desired reset delay time t_rd. Connect this pin either to GND or Q to select the

timing according to Table 8.

Table 8

Reset delay time selection

DT1 connected to

t_rd

GND

Q

16.5 ms

8.5 ms

Power-on reset delay time

The power-on reset delay time is defined by the parameter t_rdand allows a microcontroller and oscillator to

start up. This delay time is the time period from exceeding the upper reset switching threshold V_RT,highuntil the

reset is released by switching the reset output “RO” from “LOW” to “HIGH”.

Undervoltage reset delay time

The undervoltage reset delay time is defined by the parameter t_rd. It is the time interval from exceeding the

reset switching threshold V_RT,highuntil the reset is released by switching the reset output from low to high.

Reset blanking time

The reset blanking time t_rr,blankavoids that short undervoltage spikes trigger an unwanted reset “low” signal.

Datasheet

20

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Reset reaction time

In case the output voltage of the regulator drops below the output undervoltage lower reset threshold V_RT,low

,

the reset output “RO” is set to low, after the delay of the internal reset reaction time t_rr,int. The reset blanking

time t_rr,blankis part of the reset reaction time t_rr,int

.

Reset output “RO”

The reset output “RO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic

“RO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the maximum

“RO” sink current is limited, the minimum value of the optional external resistor “R_RO,ext” is given in Table

“Reset output RO” on Page 23.

Reset output “RO” low for VQ ≥ 1 V

In case of an undervoltage reset condition reset output “RO” is held “low” for V_Q≥ 1 V, even if the input “I” is

not supplied and the voltage V_Idrops below 1 V. This is achieved by supplying the reset circuit from the output

capacitor.

Reset adjust function

The undervoltage reset switching threshold can be adjusted according to the application’s needs by

connecting an external voltage divider (R_ADJ1, R_ADJ2) at pin “RADJ”. For selecting the default threshold connect

pin “RADJ” to GND. The reset adjustment range for the TLS820F0ELV50 is given in Reset threshold

adjustment range. The reset adjustment range for the TLS820F0ELV33 is given in Reset threshold

adjustment range.

When dimensioning the voltage divider, take into consideration that there will be an additional current

constantly flowing through the resistors.

With a voltage divider connected, the reset switching threshold V_RT,newis calculated as follows

(neglecting the Reset adjust pin current I_RADJ):

V_RT,lo,new= V_RADJ,th× (R_ADJ,1+ R_ADJ,2) / R_ADJ,2

(4.1)

with

•

V

_RT,lo,new: Desired undervoltage reset switching threshold.

_ADJ,1, R_ADJ,2: Resistors of the external voltage divider, see Figure 5.

_RADJ,th: Reset adjust switching threshold given in Reset adjustment switching threshold.

R

V

Datasheet

21

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

V_I

t

t < t_rr,blank

V_Q

V_RH

V_RT,high

V_RT,low

1 V

t_rd

t_rr,int

t_rd

t_rr,int

t_rd

t_rr,int

V_RO

t_rd

1V

V_RO,low

Thermal

Shutdown

Input

Voltage Dip

Under-

voltage

Spike at Over-

output load

Figure 6

Typical timing diagram reset

Datasheet

22

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Table 9

Electrical characteristics reset

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Output undervoltage reset 5V version only

Output undervoltage reset upper V_RT,high

switching threshold

4.6

4.5

60

4.7

4.6

100

4.8

4.7

–

V

V_Qincreasing

P_5.7.1

P_5.7.2

Output undervoltage reset lower V_RT,low

switching threshold - default

V_Qdecreasing

RADJ = GND

Output undervoltage reset

switching hysteresis

V_RT,hy

V_RH

mV RADJ connected to GND P_5.7.3

Output undervoltage reset

200 400

–

mV RADJ = GND

P_5.7.4

headroom V_Q- V_RT

Output undervoltage reset 3V3 version only

Output undervoltage reset upper V_RT,high

switching threshold

3.08 3.15 3.22

V

V_Qincreasing

P_5.7.5

P_5.7.6

Output undervoltage reset lower V_RT,low

switching threshold - default

3.0

60

3.05 3.13

V_Qdecreasing

RADJ = GND

Output undervoltage reset

switching hysteresis

V_RT,hy

V_RH

100

–

mV RADJ connected to GND P_5.7.7

Output undervoltage reset

100 250

mV RADJ = GND

P_5.7.8

P_5.7.9

headroom V_Q- V_RT

Reset threshold adjustment

Reset adjustment switching

threshold

V_RADJ,th

1.15 1.20 1.25

V

–

Reset threshold adjustment range V_RT,range

Reset output RO

2.5

–

4.4

2.9

V

for V_Q,nom= 5 V

P_5.7.10

P_5.7.11

for V_Q,nom= 3.3 V

Reset output low voltage

V_RO,low

R_RO,int

R_RO,ext

–

0.2

20

–

0.4

36

–

V

1 V ≤ V_Q≤ V_RT;

P_5.7.12

R

_RO≥ 5.1 kΩ

Reset output

internal pull-up resistor

13

5.1

kΩ internally connected to P_5.7.13

Q

Reset output external

pull-up resistor to V_Q

kΩ 1 V ≤ V_Q≤ V_RT

_RO≤ 0.4 V

;

P_5.7.14

V

Reset delay timing

Reset delay time

t_rd,slow

t_rd,fast

t_rr,blank

t_rr,int

13.2 16.5 19.8 ms DT1 connected to GND P_5.7.20

Reset delay time

6.8

–

8.5

6

10.2 ms DT1 connected to Q

P_5.7.21

P_5.7.22

P_5.7.46

P_5.7.23

P_5.7.36

Reset blanking time

Internal reset reaction time

–

µs

¹⁾for V_Q,nom= 3.3 V

²⁾for V_Q,nom= 5 V

for V_Q,nom= 3.3 V

for V_Q,nom= 5 V

–

7

–

7

20

33

t_rr,int

–

10

Datasheet

23

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Table 9

Electrical characteristics reset (cont’d)

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Reset delay input DT1

Delay input DT1

high signal valid

V_DT1,H

2.0

–

V

–

P_5.7.24

P_5.7.25

P_5.7.34

Delay input DT1

low signal valid

V_DT1,L

0.80

–

Delay input DT1

signal slew rate

dV_DT1/dt

1

V/µs V_DT1,L< V_DT1< V_DT1,H

High level input current

I_DT1,H

R_DT1

–

3.5

2.6

µA

V_DT1= 3.3 V

P_5.7.27

P_5.7.28

Delay input DT1

0.9

1.5

MΩ

–

internal pull-down resistor

1) Not subject to production test, specified by design.

2) Not subject to production test, specified by design.

Datasheet

24

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.8

Typical performance characteristics reset

Typical performance characteristics

Undervoltage reset threshold V_RTversus

junction temperature T_j(3.3 V version)

Undervoltage reset threshold V_RTversus

junction temperature T_j(5 V version)

3.5

3.4

3.3

3.2

3.1

3

5

4.9

4.8

4.7

4.6

4.5

4.4

2.9

2.8

4.3

I_Q= 1 mA

V_Q= 5 V

RADJ set to GND

V_Q= 3.3 V

2.7

2.6

2.5

4.2

4.1

4

RADJ set to GND

V_{RT, high}

V_{RT, low}

0

50

100

150

0

50

100

150

T_j[°C]

Power-on reset delay time t_rdversus

junction temperature T_j

Internal reset reaction time t_rr,intversus

junction temperature T_j

25

20

V_Q= 3.3 V

fast

slow

I_Q= 1 mA

18

V_Q= 5 V

16

14

12

10

8

20

15

10

5

6

4

2

0

50

100

150

0

50

100

150

T_j[°C]

Datasheet

25

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.9

Standard watchdog

The TLS820F0 features a load dependent watchdog function with a programmable watchdog timing. The

watchdog function monitors a microcontroller, including time base failures. In case of a missing falling edge

within a certain pulse repetition time, the watchdog output “WO” is set to “low”.

The watchdog uses an internal oscillator as timebase. The effective trigger window is derived from the

watchdog timebase and can be adjusted by using the pins DT1 and DT2.

The watchdog output “WO” is separated from the reset output “RO”. Hence, the watchdog output might be

used as an interrupt signal for the microcontroller independent from the reset signal. It is possible to

interconnect pin “WO” and pin “RO” in order to establish a wire-or function with a dominant low signal.

Supply

I

Q

VDD

C_Q

R_WO,int

WO

Reset

I_WO

Reference

Control

WD core

Micro-

Controller

Control

GND

WI

I_WI

GND

DT1 DT2

Figure 7

Block diagram watchdog circuit

Watchdog timing

By changing the condition on the “DT” pins, the new timing is valid from the beginning of next period. From

this time on, the frequency of the WI signal must be adapted (see also “Typical watchdog timing diagram,

watchdog and reset modes” on Page 27).

Figure 8 shows the state diagram of the watchdog (WD) and the mode selection. After power-on, the reset

output signal at the “RO” pin (microcontroller reset) is kept LOW for the reset delay time t_rd. With the LOW to

HIGH transition of the signal at “WO” the device starts the watchdog ignore time t_WI.i. Next, the WD starts the

watchdog trigger time (time frame within a trigger at WI must occur).

From now on, the timing of the signal on WI from the microcontroller must fit to the WD-trigger time t_WI,tr

,

based on the setting of the “DT” pins. A re-trigger of the WD-trigger time is done with a HIGH-to-LOW transient

at the WI-pin within the active t_WI,tr

.

Watchdog output “WO”

The watchdog output “WO” is an open collector output with an integrated pull-up resistor. In case a lower-

ohmic “WO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the

maximum “WO” sink current is limited, the minimum value of the optional external resistor “R_WO,ext” is given

in Table “Watchdog output WO” on Page 30. A HIGH to LOW transition of the watchdog trigger signal on pin

WI is taken as a trigger. A watchdog signal is generated (“WO” goes LOW), if there is no trigger pulse during the

watchdog trigger time.

Datasheet

26

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

V_I

t

V_RT,high

V_RT,low

V_Q

t

I_Q

I_Q,W,act

I_Q,W,deact

Capture DT1

Capture DT2

Capture DT1

Capture DT2

Capture DT1

Capture DT2

DT1

DT2

Capture DT1

Capture DT2

Capture DT1

Capture DT2

t

Setup t_{rd (slow)}

Capture DT2

Current Controlled

WD-turn off

Trigger

WI

t_rd

(WD-trigger time t_WI,tr

)

Ignore Time

t_WI,i

48ms *)

16ms *)

96ms *)

32ms *)

96ms *)

32ms

16.5ms typ.

t

WD Trigger

NO WD Trigger

WD Trigger

Don’t care WI

during t _WO,lowand

ignore time

Don’t care WI

during WD-off

and ignore time

Don’t care WI

during t_rdand ignore time

V_WO

t_rd

t_WO,low

No WO assertion during

Current shut down

Normal operation

Power

Fail

V_RO

t_rd

t_rr,int

t

*) watchdog trigger time interrupted by correct WI signal serving the watchdog

Figure 8

Typical watchdog timing diagram, watchdog and reset modes

Watchdog input “WI”

The watchdog is triggered by a falling edge at the watchdog input pin “WI”. The amplitude and slope of this

signal has to comply with the specification (Table “Watchdog input WI” on Page 29). For details regarding

test pulses, see Figure 9 “Test pulses watchdog input WI” on Page 27.

V_WI

t_WI,ph

V_WI,high

t_WI,pl

V_WI,low

dV_WI/ dt

t

Figure 9

Test pulses watchdog input WI

Datasheet

27

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Table 10

Electrical characteristics watchdog

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Watchdog timing

Watchdog ignore time

Watchdog trigger time

t_WI,i

12.8 16

76.8 96

19.2 ms

–

P_5.9.1

P_5.9.2

t_WI,tr,1

115.2 ms DT1 connected to GND;

DT2 connected to GND

Watchdog trigger time

Watchdog output low time

t_WI,tr,2

t_WI,tr,3

t_WI,tr,4

t_WO,low

38.4 48

25.6 32

12.8 16

57.6 ms DT1 connected to Q;

DT2 connected to GND

P_5.9.3

P_5.9.4

P_5.9.5

P_5.9.6

38.4 ms DT1 connected to GND;

DT2 connected to Q

19.2 ms DT1 connected to Q;

DT2 connected to Q

6.4

–

8

–

9.6

ms

–

Load dependent watchdog activation

Watchdog activation current

threshold

I_Q,W,act

5.5

mA for V_Q,nom= 5 V:

V_I> 5.44 V;

P_5.9.11

high current condition

must be applied at least

for the time of t_W,filter,max

Watchdog deactivation current I_Q,W,deact

1

–

mA for V_Q,nom= 5 V:

P_5.9.12

threshold

V_I> 5.44 V;

low current condition

must be applied at least

for the time of t_W,filter,max

Watchdog deactivation current I_Q,W,hy

hysteresis

0.35

–

mA for V_Q,nom= 5 V:

P_5.9.13

P_5.9.39

V_I> 5.44 V;

Watchdog activation current

threshold

I_Q,W,act

5.5

mA for V_Q,nom= 3.3 V:

V_I> 3.72 V;

high current condition

must be applied at least

for the time of t_W,filter,max

Watchdog deactivation current I_Q,W,deact

1

–

mA for V_Q,nom= 3.3 V:

P_5.9.40

threshold

V_I> 3.72 V;

low current condition

must be applied at least

for the time of t_W,filter,max

Watchdog deactivation current I_Q,W,hy

hysteresis

0.35

–

mA for V_Q,nom= 3.3 V:

P_5.9.41

P_5.9.14

V_I> 3.72 V;

Watchdog minimum filter time t_W,IQ,filter,100

µs

¹⁾– see Page 30

state transition by current

min

Datasheet

28

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Table 10

Electrical characteristics watchdog (cont’d)

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Watchdog maximum filter time t_W,IQ,filter,

–

500 µs

¹⁾– see Page 30

P_5.9.15

state transition by current

max

Watchdog input WI

2)

Watchdog input

low signal valid

V_WI,low

V_WI,high

t_WI,ph

–

0.8

–

V

–

P_5.9.16

P_5.9.17

P_5.9.19

P_5.9.20

P_5.9.21

2)

Watchdog input

high signal valid

2.0

1

V

–

2)

Watchdog input

high signal pulse length

–

µs

V/µs

V ≥ V_WI,high

WI

2)

Watchdog input

low signal pulse length

t_WI,pl

1

–

V ≤ V_WI,low

WI

2)

Watchdog input

signal slew rate

dV_WI/dt

1

–

V

< V_WI< V_WI,high

WI,low

High level input current

I_WI,H

R_WI

–

3.5

µA V_WI= 3.3 V

P_5.9.22

P_5.9.23

Watchdog input internal pull-

down resistor

0.9 1.5 2.6

MΩ

–

Watchdog disable threshold

WI signal value

V_WI,dis

1.15

–

1.40

–

V

for V_Q,nom= 5 V:

V_I> 5.44 V;

signal must be applied for

> t_W,filter,maxto deactivate

and activate the

watchdog

P_5.9.31

P_5.9.24

Watchdog disable threshold

WI signal value

V_WI,dis

–

V

for V_Q,nom= 3.3 V:

V_I> 4.6 V;

signal must be applied for

> t_W,filter,maxto deactivate

and activate the

watchdog

Watchdog minimum filter time t_WI,filter,

state transition by WI

100

–

µs

³⁾– see Page 32

P_5.9.25

P_5.9.26

min

Watchdog maximum filter time t_WI,filter,

500 µs

³⁾– see Page 32

state transition by WI

max

Watchdog delay input DT2 (DT1 is defined in chapter Reset delay input DT1)

Delay input DT2

low signal valid

V_DT2,L

–

0.8

V

–

P_5.9.27

P_5.9.28

Delay input DT2

high signal valid

V_DT2,H

2.0

–

V

–

Datasheet

29

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Table 10

Electrical characteristics watchdog (cont’d)

T_j= -40°C to 150°C, V_I= 13.5 V, all voltages with respect to ground (unless otherwise specified)

Typical values are given at T_j= 25 °C

Parameter

Symbol

Values

Unit Note or Test Condition Number

Min. Typ. Max.

Delay input DT2

Signal Slew Rate

dV_DT2/dt

1

–

V/µs V_DTx,L< V_DTx< V_DTx,H

µA V_DTx= 3.3 V

P_5.9.38

High level input current DT2

I_DT2,H

R_DT2

–

3.5

P_5.9.30

P_5.9.32

Delay input DT2 internal pull-

down resistor

0.9 1.5 2.6

MΩ

–

Watchdog setup and hold time t_setup,hold,150

–

µs

³⁾Within the setup and

hold time phase, a DTx

transition will not be

recognized

P_5.9.33

(DT1, DT2)

DT

Watchdog output WO

Watchdog output low voltage

V_WO,low

R_WO,int

–

0.2 0.4

V

R_WO> 5.1 kΩ

P_5.9.34

P_5.9.35

Watchdog output

13

20

36

kΩ internally connected to

internal pull-up resistor

pin Q

Watchdog output external

R_WO,ext

5.1

–

kΩ V_WO≤ 0.4 V;

P_5.9.36

pull-up resistor to V_Q

1) Not subject to production test, specified by design.

2) For details on applied test pulse, see Figure 9

3) Not subject to production test, specified by design.

Watchdog trigger time

Two pins, DT1 and DT2, are used to set the desired watchdog trigger time t_WI,tr. Connect these pins either to

GND or to high level (e.g. Q) to select the timing according to Table 11.

Table 11

Watchdog trigger time selection

DT1 connected to

DT2 connected to

t_WI,tr,typ

96 ms

48 ms

32 ms

16 ms

GND

Q

GND

Q

GND

Q

Watchdog deactivation by current control

The watchdog is load dependent inactive. This ensures, that if the microcontroller is in a power save mode

(I_Q≤ I_Q,W,deact) and not able to provide a correct watchdog trigger signal at pin “WI”, no watchdog signal

“WO = low” is generated. The transition from an active to an inactive state will be performed after a dead time

of t_{W,IQ,filter,max}, when output current keeps below the deactivation threshold. This protects against an

unintended entering of the watchdog deactivation state caused by short dynamic current drops. In case of

very short current drops up to the time of t_{W,IQ,filter,min}, the activation state will definitely be kept. These

scenarios are also valid for the transition from deactivation to activation state. For details see also Figure 10

Datasheet

30

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

I_Q

Scenario „D“

>t_WO,low

<t_WO,low

I_Q,W,act

I_Q,W,deact

t

V_WO

WD disabled

Scenario „A“

WD-trigger time t_WI,tr*)

WD disabled

ignore time t_WI,i

WD-trigger time t_WI,tr

t_WO,low

ignore time t_WI,i

WD-trigger time t_WI,tr

V_WO

*) interrupted by entering in „Watchdog deactivation by current control“

Watchdog filter time t_W,IQ,filter

Scenario „B“

WD-trigger time t_WI,tr

t_WO,low

WD-trigger time t_WI,tr

V_WO

Scenario „C“

WD-trigger time t_WI,tr

t_WO,low

WD disabled

*)

WD-trigger time t_WI,tr

Figure 10 Watchdog output behavior for watchdog deactivation by current control

Scenario “A”

In scenario “A” the watchdog logic expects a next trigger at WI pin within the WD-trigger time t_WI,tr. This state

is interrupted by the low current load state (I_Q≤ I_Q,W,deact). During this state, the watchdog is disabled. The

watchdog output signal “WO” will stay high while the watchdog is disabled. After leaving the low current load

state (I_Q≥ I_Q,W,act), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts based on the

setting of the DT pins. This behavior is defined for cases with a low current load time greater than t_WO,low

.

Scenario “B”

In scenario “B” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a

result the “WO” is set to low. This state is interrupted by the low current load state (I_Q≤ I_Q,W,deact). During this

state, the watchdog is disabled. The watchdog output signal “WO” is kept in low state for t_WO,lowand then the

“WO” is set to high. After leaving the low current load state (I_Q≥ I_Q,W,act), an ignore window t_WI,ifollows. After

this, the watchdog trigger time t_WI,trstarts based on the setting of the DT pins. This behavior is defined for cases

with a low current load time greater than t_WO,low

.

Scenario “C”

In scenario “C” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a

result the “WO” is set to low. After this an ignore window follows. This state is interrupted by the low current

load state (I_Q≤ I_Q,W,deact). During this state, the watchdog is disabled. The watchdog output signal “WO” will

stay high while the watchdog is disabled. After leaving the low current load state (I_Q≥ I_Q,W,act), an ignore

window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts based on the setting of the DT pins. This

behavior is defined for cases with a low current load time greater than t_WO,low

.

Scenario “D”

In scenario “D” the watchdog is not served within WD-trigger time t_WI,trwith a trigger event at WI pin. As a result

the “WO” is set to low. This state is interrupted by the low current load state (I_Q≤ I_Q,W,deact). During this state,

the watchdog is disabled. The watchdog output signal “WO” is kept in low state for the time of low current load

state. After leaving the low current load state (I_Q≥ I_Q,W,act), an ignore window t_WI,ifollows. After this, the

watchdog trigger time t_WI,trstarts based on the setting of the DT pins. This behavior is defined for cases with a

low current load time less than t_WO,low

.

Datasheet

31

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

Watchdog deactivation by external signal (pin “WI”)

Note:

Disabling the watchdog should only considered when the application is not running in the normal

operating conditions as the safe operation is not ensured any more. Example would be the flashing

process of the microcontroller.

The Watchdog can be disabled by connecting a voltage level between the range of 1.15 V to 1.40 V to WI. By

entering the watchdog deactivation, the “WO” signal behaves like it is described in Figure 11. The transition

from active to an inactive state will be performed after a dead time of t_{WI,filter,max}, when correct level to WI pin

is applied. This protects against the unintended entering of watchdog deactivation state. After leaving the

deactivation voltage range 1.15 V to 1.40 V, the watchdog is again active and starts with an ignore window.

This scenario is also valid for the transition from deactivation to activation state.

V_WI

Scenario D

>t_WO,low

<t_WO,low

V_WI,dis.high

V_WI,dis,low

V_WI,dis.high

V_WI,dis,low

t

V_WO

WD disabled

Scenario A

WD-trigger time t_WI,tr*)

WD disabled

ignore time t_WI,i

WD-trigger time t_WI,tr

t_WO,low

ignore time t_WI,i

WD-trigger time t_WI,tr

*) interrupted by entering in Watchdog deactivation by WI pin

Watchdog filter time t_WI,filter

Scenario B

WD-trigger time t_WI,tr

t_WO,low

Scenario C

WD-trigger time t_WI,tr

t_WO,low

WD disabled

*)

Figure 11 Watchdog output behavior for watchdog deactivation by WI pin

Scenario “A”

In scenario “A” the watchdog logic expects a next trigger at WI pin within the WD-trigger time t_WI,tr. This state

is interrupted by setting V_WIto the disable condition (V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog

is disabled. The watchdog output signal “WO” will stay high while the watchdog is disabled. After leaving the

disable condition (V_WI≥ V_WI,dis,highor V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog

trigger time t_WI,trstarts based on the setting of the DT pins. This behavior is defined for cases with a watchdog

disabled duration greater than t_WO,low

.

Scenario “B”

In scenario “B” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a

result the “WO” is set to low. This state is interrupted by setting V_WIto the disable condition

(V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog is disabled. The watchdog output signal “WO” is

kept in low state for t_WO,lowand then the “WO” is set to high. After leaving the disable condition (V_WI≥ V_WI,dis,high

or V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts based on the

setting of the DT pins. This behavior is defined for cases with a watchdog disabled duration greater than

t_WO,low

.

Scenario “C”

In scenario “C” the watchdog is not served within WD-trigger time t_WI,trwith an trigger event at WI pin. As a

result the “WO” is set to low. After this an ignore window follows. This state is interrupted by setting V_WIto the

Datasheet

32

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

disable condition (V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog is disabled. The watchdog output

signal “WO” will stay high while the watchdog is disabled. After leaving the disable condition (V_WI≥ V_WI,dis,high

or V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts based on the

setting of the DT pins. This behavior is defined for cases with a watchdog disabled duration greater than

t_WO,low

.

Scenario “D”

In scenario “D” the watchdog is not served within WD-trigger time t_WI,trwith a trigger event at WI pin. As a result

the “WO” is set to low. This state is interrupted by setting V_WIto the disable condition

(V_WI,dis,low≤ V_WI≤ V_WI,dis,high). During this state, the watchdog is disabled. The watchdog output signal “WO” is

kept in low state as long the watchdog is disabled. After leaving the disable condition (V_WI≥ V_WI,dis,highor

V_WI≤ V_WI,dis,low), an ignore window t_WI,ifollows. After this, the watchdog trigger time t_WI,trstarts based on the

setting of the DT pins. This behavior is defined for cases with a watchdog disabled duration less than t_WO,low

.

Datasheet

33

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Block description and electrical characteristics

4.10

Typical performance characteristics standard watchdog

Typical performance characteristics

Watchdog trigger time t_{WI,tr,1,2,3,4}versus

junction temperature T_j

Watchdog output low time t_WO,lowversus

junction temperature T_j

15

I_Q= 10 mA

x = 1

x = 2

x = 3

x = 4

I_Q= 10 mA

120

100

80

60

40

20

0

10

5

0

50

100

150

0

50

100

150

T_j[°C]

Watchdog activation/deactivation current I_Q,W,act

,

Watchdog disable V_WI,disthreshold versus

junction temperature T_j

I_Q,W,deactversus junction temperature T_j

3

2.5

2

7

6

5

4

3

2

1

1.5

1

0.5

I_Q= 10 mA

I_Q,W,deact

I_Q,W,act

low

high

0

50

T_j[°C]

100

150

0

50

T_j[°C]

100

150

Datasheet

34

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Application information

5

Application information

5.1

Application diagram

Note:

The following information is given as a hint for the implementation of the device only and shall not

be regarded as a description or warranty of a certain functionality, condition or quality of the device.

Supply

Regulated Output Voltage

I

Q

RO

Load

e. g.

Micro

D_I1

Current

Limitation

Controller

XC22xx

Reset

EN

D_I2

<45V

C_I2

C_I1

C_Q

R₁

1µF

100nF

47µF

RADJ

Enable

Bandgap

Reference

DT1

DT2

WI

Temperature

Shutdown

R₂

WO

Watchdog

GND

e.g. Ignition

Figure 12 Application diagram

Note:

This is a very simplified example of an application circuit. The function must be verified in the real

application.

5.2

Selection of external components

5.2.1

Input pin

The typical input circuitry for a linear voltage regulator is shown in the application diagram above.

A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high

frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to

the input pin of the linear voltage regulator on the PCB.

An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to

smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of

the linear voltage regulator on the PCB.

An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum

rating of the linear voltage regulator and protect the device against any damage due to over-voltage.

The external components at the input are not mandatory for the operation of the voltage regulator, but they

are recommended in case of possible external disturbances.

5.2.2

Output pin

An output capacitor is mandatory for the stability of linear voltage regulators.

Datasheet

35

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Application information

The requirement to the output capacitor is given in “Functional range” on Page 8. The graph “Output

capacitor series resistor ESR(CQ) versus output current IQ” on Page 15 shows the stable operation range

of the device.

TLS820F0 is designed to be also stable with low ESR capacitors. According to the automotive requirements,

ceramic capacitors with X5R or X7R dielectrics are recommended.

The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the

same side of the PCB as the regulator itself.

In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in

accordance and verified in the real application that the output stability requirements are fulfilled.

5.3

Thermal considerations

Knowing the input voltage, the output voltage and the load profile of the application, the total power

dissipation can be calculated:

P_D= (V_I- V_Q) × I_Q+ V_I× I_q

(5.1)

with

•

P_D: continuous power dissipation

V_I: input voltage

V_Q: output voltage

I_Q: output current

I_q: quiescent current

The maximum acceptable thermal resistance R_thJAcan then be calculated:

R_thJA,max= ( T_j,max- T_a) / P_D

(5.2)

with

•

T

_j,max: maximum allowed junction temperature

T_a: ambient temperature

Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with

reference to the specification in “Thermal resistance” on Page 9.

Example

Application conditions:

V_I= 13.5 V

V_Q= 5 V

I_Q= 150 mA

T_a= 85 °C

Calculation of R_thJA,max

:

P_D= (V_I– V_Q) × I_Q+ V_I× I_q

(V_I× I_qcan be neglected because of very low I_q)

= (13.5 V – 5 V) × 150 mA = 1.275 W

_thJA,max= (T_j,max– T_a) / P_D

R

= (150 °C – 85 °C) / 1.275 W = 50.98 K/W

Datasheet

36

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Application information

As a result, the PCB design must ensure a thermal resistance R_thJAlower than 50.98 K/W. According to

“Thermal resistance” on Page 9, at least 600 mm²heatsink area is needed on the FR4 1s0p PCB, or the FR4

2s2p board can be used to ensure a proper cooling for the TLS820F0 in PG-SSOP-14 package.

5.4

Reverse polarity protection

TLS820F0 is not self protected against reverse polarity faults and must be protected by external components

against negative supply voltage. An external reverse polarity diode is needed. The absolute maximum ratings

of the device as specified in “Absolute maximum ratings” on Page 7 must be kept.

5.5

Further application information

•

For further information you may contact http://www.infineon.com/

Datasheet

37

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Package information

6

Package information

0.35 x 45°

1)

0.1 H D 2x

±0.1

3.9

+0.06

H

0.19

0.08

SEATING

PLANE

C

0.64_±0.25

0.2 C 14x

0.65

6 x 0.65 = 3.9

D

±0.2

6

2)

±0.05

0.25

M

0.15

C A-B D 14x

Bottom View

±0.2

3

A

8

1

7

14

1

7

14

8

Exposed

Diepad

B

0.1 H A-B 2x

Index

Marking 4.9

1)

±0.1

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Lead width can be 0.61 max. in dambar area

PG-SSOP-14

Figure 13 PG-SSOP-14¹⁾

Green product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations the device is available as a green product. Green products are RoHS-Compliant

(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

1) Dimensions in mm

Datasheet

38

Rev. 1.2

2021-04-08

OPTIREG™ linear TLS820F0ELVxx

Low dropout linear voltage regulator

Revision history

7

Revision history

Revision

Date

Changes

1.2

2021-04-08 Update layout and structure

Parameter P_5.1.12 updated

Parameter P_5.1.32 updated

Editorial changes applied

1.1

1.0

2015-07-24 Additional description added for function “Watchdog deactivation by WI pin”

Parameter P_5.7.22 updated

New parameter P_5.7.46 added

Editorial changes applied

2015-03-20 Data Sheet - Initial version

Datasheet

39

Rev. 1.2

2021-04-08

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2021-04-08

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

Document reference

Z8F53875111


型号：	TLS820F0EL V33
厂家：	Infineon
描述：	TLS820F0 V33 是高性能极低压降线性稳压器，采用 PG-SSOP-14 封装，适用于 3.3 V 电源。稳压器
文件：	总40页 (文件大小：1227K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLS820F0EL V33 [INFINEON]

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