XMC1302-T028X0016 AB [INFINEON]
32 位微控制器,带 ARM® Cortex®-M0,重点用于低成本嵌入式控制应用。对于将传统 32 位设计带入一个新的水平,涵盖从典型 32 位应用到数字功率换算,甚至是磁场定向电动机控制的广泛应用领域,当首选 XMC1000。XMC1300 系列可集成无传感器现场定向控制(FOC)电机、无刷(BLDC)电机、有刷直流电机以及永磁同步电机所需的所有控制和模拟接口功能。;型号: | XMC1302-T028X0016 AB |
厂家: | Infineon |
描述: | 32 位微控制器,带 ARM® Cortex®-M0,重点用于低成本嵌入式控制应用。对于将传统 32 位设计带入一个新的水平,涵盖从典型 32 位应用到数字功率换算,甚至是磁场定向电动机控制的广泛应用领域,当首选 XMC1000。XMC1300 系列可集成无传感器现场定向控制(FOC)电机、无刷(BLDC)电机、有刷直流电机以及永磁同步电机所需的所有控制和模拟接口功能。 电动机控制 电机 控制器 微控制器 传感器 |
文件: | 总78页 (文件大小:2710K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
XMC1300 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet
V2.0 2017-10
Microcontrollers
Edition 2017-10
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
XMC1300 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet
V2.0 2017-10
Microcontrollers
XMC1300 AB-Step
XMC1000 Family
XMC1300 Data Sheet
Revision History: V2.0 2017-10
Previous Version: V1.9 2017-03
Page
Subjects
Page 10, Add marking option for XMC1302-T28X0032, XMC1302-T28X0064,
Page 13
XMC1302-T28X0128, XMC1302-T28X0200.
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.
Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace
Buffer™ are trademarks of ARM, Limited.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1
1.2
1.3
1.4
2
2.1
2.2
2.2.1
2.2.2
2.2.3
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 27
3
3.1
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . . 46
Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power-Up and Supply Monitoring Characteristics . . . . . . . . . . . . . . . . 57
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . 61
SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 63
Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 68
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.6.3
4
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.1
4.1.1
4.2
Data Sheet
5
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Table of Contents
5
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data Sheet
6
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
About this Document
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC1300 series devices.
The document describes the characteristics of a superset of the XMC1300 series
devices. For simplicity, the various device types are referred to by the collective term
XMC1300 throughout this document.
XMC1000 Family User Documentation
The set of user documentation includes:
•
Reference Manual
– decribes the functionality of the superset of devices.
Data Sheets
•
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•
Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions
of those documents.
Data Sheet
7
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
1
Summary of Features
The XMC1300 devices are members of the XMC1000 Family of microcontrollers based
on the ARM Cortex-M0 processor core. The XMC1300 series addresses the real-time
control needs of motor control, digital power conversion. It also features peripherals for
LED Lighting applications.
SWD
Cortex-M0
Analog system
Debug
system
CPU
SPD
EVR
2 x DCO
NVIC
Temperature sensor
ANACTRL SFRs
PRNG
AHB to APB
Bridge
PAU
AHB-Lite Bus
Flash SFRs
200k + 0.5k1)
Flash
ACMP &
ORC
MATH
CCU40
16k
SRAM
USIC0
VADC
ERU0
PORTS
WDT
BCCU0
CCU80
POSIF0
8k ROM
Memories
SCU
RTC
1) 0.5kbytes of sector 0 (readable only).
Figure 1
System Block Diagram
CPU Subsystem
CPU Core
– High-performance 32-bit ARM Cortex-M0 CPU
•
– Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set
– Single cycle 32-bit hardware multiplier
– System timer (SysTick) for Operating System support
Data Sheet
8
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
– Ultra low power consumption
•
•
•
Nested Vectored Interrupt Controller (NVIC)
Event Request Unit (ERU) for processing of external and internal service requests
MATH Co-processor (MATH)
– CORDIC unit for trigonometric calculation
– division unit
On-Chip Memories
•
•
•
8 kbytes on-chip ROM
16 kbytes on-chip high-speed SRAM
up to 200 kbytes on-chip Flash program and data memory
Communication Peripherals
•
Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI,
quad-SPI, IIC, IIS and LIN interfaces
Analog Frontend Peripherals
•
A/D Converters
– up to 12 analog input pins
– 2 sample and hold stages with 8 analog input channels each
– fast 12-bit analog to digital converter with adjustable gain
Up to 8 channels of out of range comparators (ORC)
Up to 3 fast analog comparators (ACMP)
Temperature Sensor (TSE)
•
•
•
Industrial Control Peripherals
•
•
•
•
Capture/Compare Units 4 (CCU4) as general purpose timers
Capture/Compare Units 8 (CCU8) for motor control and power conversion
Position Interfaces (POSIF) for hall and quadrature encoders and motor positioning
Brightness and Colour Control Unit (BCCU), for LED color and dimming application
System Control
•
•
•
•
Window Watchdog Timer (WDT) for safety sensitive applications
Real Time Clock module with alarm support (RTC)
System Control Unit (SCU) for system configuration and control
Pseudo random number generator (PRNG) for fast random data generation
Input/Output Lines
•
•
Tri-stated in input mode
Push/pull or open drain output mode
Data Sheet
9
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
•
Configurable pad hysteresis
On-Chip Debug Support
•
•
Support for debug features: 4 breakpoints, 2 watchpoints
Various interfaces: ARM serial wire debug (SWD), single pin debug (SPD)
1.1
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:
•
•
<DDD> the derivatives function set
<Z> the package variant
– T: TSSOP
– Q: VQFN
•
•
<PPP> package pin count
<T> the temperature range:
– F: -40°C to 85°C
– X: -40°C to 105°C
•
<FFFF> the Flash memory size.
For ordering codes for the XMC1300 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC1300 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC1300 is used for all derivatives throughout this document.
1.2
Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XMC1300 Device Types
Package
Derivative
Flash
SRAM
Kbytes
Kbytes
XMC1301-T016F0008
XMC1301-T016F0016
XMC1301-T016F0032
XMC1301-T016X0008
XMC1301-T016X0016
XMC1302-T016X0008
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-16-8
8
16
16
16
16
16
16
16
32
8
16
8
Data Sheet
10
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
Table 1
Synopsis of XMC1300 Device Types (cont’d)
Derivative
Package
Flash
Kbytes
SRAM
Kbytes
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
XMC1302-T016X0016
XMC1302-T016X0032
XMC1302-T028X0016
XMC1302-T028X0032
XMC1302-T028X0064
XMC1302-T028X0128
XMC1302-T028X0200
XMC1301-T038F0008
XMC1301-T038F0016
XMC1301-T038F0032
XMC1301-T038X0032
XMC1301-T038F0064
XMC1302-T038X0016
XMC1302-T038X0032
XMC1302-T038X0064
XMC1302-T038X0128
XMC1302-T038X0200
XMC1301-Q024F0008
XMC1301-Q024F0016
XMC1302-Q024F0016
XMC1302-Q024F0032
XMC1302-Q024F0064
XMC1302-Q024X0016
XMC1302-Q024X0032
XMC1302-Q024X0064
XMC1301-Q040F0008
XMC1301-Q040F0016
XMC1301-Q040F0032
XMC1302-Q040X0016
XMC1302-Q040X0032
PG-TSSOP-16-8
PG-TSSOP-16-8
PG-TSSOP-28-8
PG-TSSOP-28-8
PG-TSSOP-28-8
PG-TSSOP-28-8
PG-TSSOP-28-8
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-TSSOP-38-9
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-24-19
PG-VQFN-40-13
PG-VQFN-40-13
PG-VQFN-40-13
PG-VQFN-40-13
PG-VQFN-40-13
16
32
16
32
64
128
200
8
16
32
32
64
16
32
64
128
200
8
16
16
32
64
16
32
64
8
16
32
16
32
Data Sheet
11
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
Table 1
Synopsis of XMC1300 Device Types (cont’d)
Derivative
Package
Flash
Kbytes
SRAM
Kbytes
16
XMC1302-Q040X0064
XMC1302-Q040X0128
XMC1302-Q040X0200
PG-VQFN-40-13
PG-VQFN-40-13
PG-VQFN-40-13
64
128
200
16
16
1.3
Device Type Features
The following table lists the available features per device type.
Table 2
Features of XMC1300 Device Types1)
Derivative
ADC channel
ACMP
BCCU
MATH
XMC1301-T016
XMC1302-T016
XMC1302-T028
XMC1301-T038
XMC1302-T038
XMC1301-Q024
XMC1302-Q024
XMC1301-Q040
XMC1302-Q040
11
11
14
16
16
13
13
16
16
2
2
3
3
3
3
3
3
3
-
-
1
1
-
1
1
-
1
-
1
-
1
-
1
-
1
1
1) Features that are not included in this table are available in all the derivatives
Table 3
ADC Channels 1)
VADC0 G0
Package
VADC0 G1
PG-TSSOP-16
PG-TSSOP-28
PG-TSSOP-38
PG-VQFN-24
PG-VQFN-40
CH0..CH5
CH0..CH7
CH0..CH7
CH0..CH7
CH0..CH7
CH0..CH4
CH0 .. CH4, CH7
CH0..CH7
CH0..CH4
CH0..CH7
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port
I/O Function table.
Data Sheet
12
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
1.4
Chip Identification Number
The Chip Identification Number allows software to identify the marking. It is a 8 words
value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at
address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and
most significant word of the Chip Identification Number are the value of registers
DBGROMID and IDCHIP, respectively.
Table 4
XMC1300 Chip Identification Number
Value
Derivative
Marking
XMC1301-T016F0008
XMC1301-T016F0016
XMC1301-T016F0032
XMC1301-T016X0008
XMC1301-T016X0016
XMC1302-T016X0008
XMC1302-T016X0016
XMC1302-T016X0032
XMC1302-T028X0016
XMC1302-T028X0032
XMC1302-T028X0064
XMC1302-T028X0128
XMC1302-T028X0200
XMC1301-T038F0008
00013032 01CF00FF 00001FF7 0000100F
00000C00 00001000 00003000 201ED083H
AB
00013032 01CF00FF 00001FF7 0000100F
00000C00 00001000 00005000 201ED083H
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
00013032 01CF00FF 00001FF7 0000100F
00000C00 00001000 00009000 201ED083H
00013033 01CF00FF 00001FF7 0000100F
00000C00 00001000 00003000 201ED083H
00013033 01CF00FF 00001FF7 0000100F
00000C00 00001000 00005000 201ED083H
00013033 01FF00FF 00001FF7 0000900F
00000C00 00001000 00003000 201ED083H
00013033 01FF00FF 00001FF7 0000900F
00000C00 00001000 00005000 201ED083H
00013033 01FF00FF 00001FF7 0000900F
00000C00 00001000 00009000 201ED083H
00013023 01FF00FF 00001FF7 0000900F
00000C00 00001000 00005000 201ED083H
00013023 01FF00FF 00001FF7 0000900F
00000C00 00001000 00009000 201ED083H
00013023 01FF00FF 00001FF7 0000900F
00000C00 00001000 00011000 201ED083H
00013023 01FF00FF 00001FF7 0000900F
00000C00 00001000 00021000 201ED083H
00013023 01FF00FF 00001FF7 0000900F
00000C00 00001000 00033000 201ED083H
00013012 01CF00FF 00001FF7 0000100F
00000C00 00001000 00003000 201ED083H
Data Sheet
13
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
Table 4
XMC1300 Chip Identification Number (cont’d)
Derivative
Value
Marking
XMC1301-T038F0016
XMC1301-T038F0032
XMC1301-T038X0032
XMC1301-T038F0064
XMC1302-T038X0016
XMC1302-T038X0032
XMC1302-T038X0064
XMC1302-T038X0128
XMC1302-T038X0200
XMC1301-Q024F0008
XMC1301-Q024F0016
XMC1302-Q024F0016
XMC1302-Q024F0032
XMC1302-Q024F0064
XMC1302-Q024X0016
XMC1302-Q024X0032
XMC1302-Q024X0064
00013012 01CF00FF 00001FF7 0000100F
00000C00 00001000 00005000 201ED083H
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
00013012 01CF00FF 00001FF7 0000100F
00000C00 00001000 00009000 201ED083H
00013013 01CF00FF 00001FF7 0000100F
00000C00 00001000 00009000 201ED083H
00013012 01CF00FF 00001FF7 0000100F
00000C00 00001000 00011000 201ED083H
00013013 01FF00FF 00001FF7 0000900F
00000C00 00001000 00005000 201ED083H
00013013 01FF00FF 00001FF7 0000900F
00000C00 00001000 00009000 201ED083H
00013013 01FF00FF 00001FF7 0000900F
00000C00 00001000 00011000 201ED083H
00013013 01FF00FF 00001FF7 0000900F
00000C00 00001000 00021000 201ED083H
00013013 01FF00FF 00001FF7 0000900F
00000C00 00001000 00033000 201ED083H
00013062 01CF00FF 00001FF7 0000100F
00000C00 00001000 00003000 201ED083H
00013062 01CF00FF 00001FF7 0000100F
00000C00 00001000 00005000 201ED083H
00013062 01FF00FF 00001FF7 0000900F
00000C00 00001000 00005000 201ED083H
00013062 01FF00FF 00001FF7 0000900F
00000C00 00001000 00009000 201ED083H
00013062 01FF00FF 00001FF7 0000900F
00000C00 00001000 00011000 201ED083H
00013063 01FF00FF 00001FF7 0000900F
00000C00 00001000 00005000 201ED083H
00013063 01FF00FF 00001FF7 0000900F
00000C00 00001000 00009000 201ED083H
00013063 01FF00FF 00001FF7 0000900F
00000C00 00001000 00011000 201ED083H
Data Sheet
14
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Summary of Features
Table 4
XMC1300 Chip Identification Number (cont’d)
Derivative
Value
Marking
XMC1301-Q040F0008
XMC1301-Q040F0016
XMC1301-Q040F0032
XMC1302-Q040X0016
XMC1302-Q040X0032
XMC1302-Q040X0064
XMC1302-Q040X0128
XMC1302-Q040X0200
00013042 01CF00FF 00001FF7 0000100F
00000C00 00001000 00003000 201ED083H
AB
AB
AB
AB
AB
AB
AB
AB
00013042 01CF00FF 00001FF7 0000100F
00000C00 00001000 00005000 201ED083H
00013042 01CF00FF 00001FF7 0000100F
00000C00 00001000 00009000 201ED083H
00013043 01FF00FF 00001FF7 0000900F
00000C00 00001000 00005000 201ED083H
00013043 01FF00FF 00001FF7 0000900F
00000C00 00001000 00009000 201ED083H
00013043 01FF00FF 00001FF7 0000900F
00000C00 00001000 00011000 201ED083H
00013043 01FF00FF 00001FF7 0000900F
00000C00 00001000 00021000 201ED083H
00013043 01FF00FF 00001FF7 0000900F
00000C00 00001000 00033000 201ED083H
Data Sheet
15
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
2
General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1
Logic Symbols
VDDP
VSSP
(2)
VDDP
(1)
VSSP
(1)
(2)
Port 0
16 bit
Port 0
12 bit
Port 1
6 bit
Port 1
4 bit
XMC13XX
TSSOP-38
XMC13XX
TSSOP-28
Port 2
4 bit
Port 2
4 bit
Port 2
8 bit
Port 2
6 bit
VDDP
VSSP
(1)
(1)
Port 0
8 bit
XMC13XX
TSSOP-16
Port 2
3 bit
Port 2
3 bit
Figure 2
XMC1300 Logic Symbol for TSSOP-38, TSSOP-28 and TSSOP-16
Data Sheet
16
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
VDDP
VSSP
(1)
VDD VSS VDDP VSSP
(1) (1) (2) (1)
(1)
Port 0
10 bit
Port 0
16 bit
Port 1
4 bit
Port 1
7 bit
XMC1300
VQFN-24
XMC1300
VQFN-40
Port 2
4 bit
Port 2
4 bit
Port 2
4 bit
Port 2
8 bit
Figure 3
XMC1300 Logic Symbol for VQFN-24 and VQFN-40
Data Sheet
17
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
2.2
Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
P2.4
P2.5
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P2.3
Top View
2
P2.2
P2.6
3
P2.1
P2.7
4
P2.0
P2.8
5
P0.15
P0.14
P0.13
P2.9
6
P2.10
P2.11
SSP/VSS
7
8
P0.12
P0.11
P0.10
V
9
VDDP/VDD
10
11
12
13
14
15
16
17
18
19
P1.5
P1.4
P1.3
P0.9
P0.8
VDDP
P1.2
P1.1
P1.0
VSSP
P0.7
P0.6
P0.5
P0.4
P0.3
P0.0
P0.1
P0.2
Figure 4
XMC1300 PG-TSSOP-38 Pin Configuration (top view)
Data Sheet
18
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
P2.6
P2.7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P2.5
Top View
2
P2.2
P2.8
3
P2.1
P2.9
4
P2.0
P2.10
P2.11
SSP/VSS
5
P0.15
P0.14
P0.13
6
V
7
VDDP/VDD
P1.3
8
P0.12
P0.10
9
P1.2
10
11
12
13
14
P0.9
P1.1
P0.8
P0.7
P1.0
P0.0
P0.6
P0.5
P0.4
Figure 5
XMC1300 PG-TSSOP-28 Pin Configuration (top view)
P2.7/P2.8
P2.9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P2.6
P2.0
P0.15
P0.14
P0.9
P0.8
P0.7
P0.6
Top View
P2.10
P2.11
V
SSP/VSS
VDDP/VDD
P0.0
P0.5
Figure 6
XMC1300 PG-TSSOP-16 Pin Configuration (top view)
Data Sheet
19
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
18 17 16 15 14 13
P0.8
P0.9
12
P1.2
P1.3
19
20
11
10
9
21
22
V
P0.12
P0.13
P0.14
P0.15
DDP/V DD
SSP /V SS
V
8
23
24
P2.11
P2.10
7
1
2
3
4
5
6
Figure 7
XMC1300 PG-VQFN-24 Pin Configuration (top view)
Data Sheet
20
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
30 29 28 27 26 25 24 23 22 21
VSSP
VDDP
P1.2
P1.3
P1.4
P1.5
31
32
33
20
19
18
17
16
15
14
P0.8
P0.9
34
35
36
P1.6
VDDP
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
37
38
39
40
VDD
VSS
13
12
11
P2.11
P2.10
1
2
3
4
5
6
7
8
9
10
Figure 8
XMC1300 PG-VQFN-40 Pin Configuration (top view)
Data Sheet
21
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
2.2.1
Package Pin Summary
The following general building block is used to describe each pin:
Table 5
Function
Px.y
Package Pin Mapping Description
Package A
Package B
...
Pad Type
N
N
Pad Class
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type:
•
•
•
•
•
STD_INOUT(standard bi-directional pads)
STD_INOUT/AN (standard bi-directional pads with analog input)
High Current (high current bi-directional pads)
STD_IN/AN (standard input pads with analog input)
Power (power supply)
Details about the pad properties are defined in the Electrical Parameters.
Table 6
Package Pin Mapping
Function VQFN TSSOP TSSOP VQFN TSSOP Pad
Notes
40
38
28
24
16
Type
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
23
17
13
15
7
STD_IN
OUT
24
25
26
27
28
29
18
19
20
21
22
23
-
-
-
STD_IN
OUT
-
-
-
STD_IN
OUT
-
-
-
STD_IN
OUT
14
15
16
-
-
STD_IN
OUT
16
17
8
9
STD_IN
OUT
STD_IN
OUT
Data Sheet
22
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN TSSOP TSSOP VQFN TSSOP Pad
Notes
40
38
28
24
16
Type
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
30
24
17
18
10
STD_IN
OUT
33
34
35
36
37
38
39
40
22
21
20
19
18
17
16
1
27
28
29
30
31
32
33
34
16
15
14
13
12
11
-
18
19
20
-
19
20
-
11
12
-
STD_IN
OUT
STD_IN
OUT
STD_IN
OUT
-
-
STD_IN
OUT
21
22
23
24
12
11
10
9
21
22
23
24
14
13
12
11
-
-
STD_IN
OUT
-
STD_IN
OUT
13
14
-
STD_IN
OUT
STD_IN
OUT
High
Current
-
High
Current
-
High
Current
-
High
Current
-
-
High
Current
-
-
-
High
Current
-
-
-
STD_IN
OUT
35
25
1
15
STD_IN
OUT/AN
Data Sheet
23
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN TSSOP TSSOP VQFN TSSOP Pad
Notes
40
38
28
24
16
Type
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
VSS
2
36
26
2
-
STD_IN
OUT/AN
3
37
38
1
27
-
3
-
-
STD_IN/
AN
4
-
STD_IN/
AN
5
-
-
-
STD_IN/
AN
6
2
28
1
-
-
STD_IN/
AN
7
3
4
5
5
6
7
8
9
16
1
1
2
3
4
5
STD_IN/
AN
8
4
2
STD_IN/
AN
9
5
3
STD_IN/
AN
10
11
12
13
6
4
STD_IN/
AN
7
5
STD_IN
OUT/AN
8
6
STD_IN
OUT/AN
9
7
Power
Supply GND,
ADC reference
GND
VDD
14
15
10
10
8
8
10
10
6
6
Power
Supply VDD,
ADC reference
voltage/ ORC
reference voltage
VDDP
Power
When VDD is
supplied, VDDP
has to be
supplied with the
same voltage.
Data Sheet
24
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN TSSOP TSSOP VQFN TSSOP Pad
Notes
40
31
32
38
25
26
-
28
-
24
-
16
-
Type
VSSP
VDDP
VSSP
Power
Power
Power
I/O port ground
I/O port supply
-
-
-
Exp.
Pad
-
Exp.
Pad
-
Exposed Die
Pad
The exposed die
pad is connected
internally to
VSSP. For proper
operation, it is
mandatory to
connect the
exposed pad to
the board ground.
For thermal
aspects, please
refer to the
Package and
Reliability
chapter.
2.2.2
Port I/O Function Description
The following general building block is used to describe the I/O functions of each PORT
pin:
Table 7
Port I/O Function Description
Outputs
Function
Inputs
ALT1
ALTn
Input
Input
P0.0
Pn.y
MODA.OUT
MODC.INA
MODA.INA
MODA.OUT
MODC.INB
Data Sheet
25
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
Pn.y
XMC1000
Control Logic
PAD
VDDP
Input 0
...
MODA.INA
Input n
HWI0
MODA
MODB
Pn.y
HWI1
SW
ALT1
MODB.OUT
...
ALTn
HWO0
HWO1
GND
Figure 9
Simplified Port Structure
Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port
pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective
module, with the pin characteristics controlled by the port registers (within the limits of
the connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
Please refer to the Port I/O Functions table for the complete Port I/O function mapping.
Data Sheet
26
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
General Device Information
2.2.3
Hardware Controlled I/O Function Description
The following general building block is used to describe the hardware I/O and pull control
functions of each PORT pin:
Table 8
Hardware Controlled I/O Function Description
Function
Outputs
HWO0
Inputs
Pull Control
HW0_PD
HWI0
HW0_PU
P0.0
Pn.y
MODB.OUT
MODB.INA
MODC.OUT
MODC.OUT
By Pn_HWSEL, it is possible to select between different hardware “masters”
(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).
Hardware control overrules settings in the respective port pin registers. Additional
hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the
peripherals can be used to control the pull devices of the pin.
Please refer to the Hardware Controlled I/O Functions table for the complete hardware
I/O and pull control function mapping.
Data Sheet
27
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Data Sheet
Ports, V2.3
2-28
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Data Sheet
Ports, V2.3
2-29
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Data Sheet
Ports, V2.3
2-30
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Data Sheet
Ports, V3.1
2-31
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Data Sheet
Ports, V3.1
2-32
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3
Electrical Parameters
This section provides the electrical parameters which are implementation-specific for the
XMC1300.
3.1
General Parameters
3.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XMC1300
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•
CC
Such parameters indicate Controller Characteristics, which are distinctive feature of
the XMC1300 and must be regarded for a system design.
SR
•
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC1300 is designed in.
Data Sheet
33
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.1.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 9
Absolute Maximum Rating Parameters
Symbol Values
Parameter
Unit Note /
Test Cond
Min Typ. Max.
.
ition
Junction temperature
Storage temperature
TJ
SR -40
SR -40
–
–
–
115
125
6
°C
°C
V
–
–
–
TST
Voltage on power supply pin VDDP SR -0.3
with respect to VSSP
Voltage on digital pins with
respect to VSSP
VIN
SR -0.5
–
–
–
–
–
V
DDP + 0.5
V
whichever
is lower
1)
or max. 6
Voltage on P2 pins with
VINP2 SR -0.3
VDDP + 0.3
V
–
2)
respect to VSSP
Voltage on analog input pins VAIN
with respect to VSSP
-0.5
VDDP + 0.5
V
whichever
is lower
VAREF SR
or max. 6
10
Input current on any pin
during overload condition
IIN
SR -10
mA
mA
–
Absolute maximum sum of all ΣIIN SR -50
inputcurrentsduringoverload
condition
+50
–
1) Excluding port pins P2.[1,2,6,7,8,9,11].
2) Applicable to port pins P2.[1,2,6,7,8,9,11].
Data Sheet
34
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.1.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 10 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time is not exceeded
Operating Conditions are met for
– pad supply levels (VDDP
)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery.
Table 10
Overload Parameters
Symbol
Parameter
Values
Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin IOV SR -5
during overload condition
–
5
mA
mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR
–
–
25
Figure 10 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Data Sheet
35
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
VDDP
VDDP
Pn.y
IOVx
GND
ESD
GND
Pad
Figure 10
Input Overload Current via ESD structures
Table 11 and Table 12 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as defined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 11
PN-Junction Characterisitics for positive Overload
OV = 5 mA
Pad Type
I
Standard, High-current,
AN/DIG_IN
V
V
V
IN = VDDP + 0.5 V
AIN = VDDP + 0.5 V
AREF = VDDP + 0.5 V
P2.[1,2,6:9,11]
V
INP2 = VDDP + 0.3 V
Table 12
PN-Junction Characterisitics for negative Overload
OV = 5 mA
Pad Type
I
Standard, High-current,
AN/DIG_IN
V
V
V
IN = VSS - 0.5 V
AIN = VSS - 0.5 V
AREF = VSS - 0.5 V
P2.[1,2,6:9,11]
V
INP2 = VSS - 0.3 V
Data Sheet
36
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.1.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC1300. All parameters specified in the following tables
refer to these operating conditions, unless noted otherwise.
Table 13
Operating Conditions Parameters
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
SR -40
-40
Digital supply voltage1) VDDP SR 1.8
Typ.
Max.
85
Ambient Temperature TA
−
−
−
−
−
°C
°C
V
Temp. Range F
Temp. Range X
105
5.5
MCLK Frequency
PCLK Frequency
fMCLK CC
fPCLK CC
−
−
33.2
66.4
MHz CPU clock
MHz Peripherals
clock
Short circuit current of ISC
digital outputs
SR -5
−
−
5
mA
Absolute sum of short ΣISC_D SR
circuit currents of the
device
−
25
mA
1) See also the Supply Monitoring thresholds, Chapter 3.3.2.
Data Sheet
37
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.2
DC Parameters
3.2.1
Input/Output Characteristics
Table 14 provides the characteristics of the input/output pins of the XMC1300.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Unless otherwise stated, input DC and AC characteristics, including peripheral
timings, assume that the input pads operate with the standard hysteresis.
Table 14
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
Max.
Output low voltage on
port pins
(with standard pads)
VOLP CC
–
1.0
V
V
V
I
I
OL = 11 mA (5 V)
OL = 7 mA (3.3 V)
–
–
0.4
1.0
I
I
OL = 5 mA (5 V)
OL = 3.5 mA (3.3 V)
Output low voltage on
high current pads
VOLP1 CC
I
I
OL = 50 mA (5 V)
OL = 25 mA (3.3 V)
–
–
0.32
0.4
–
V
V
V
I
I
OL = 10 mA (5 V)
OL = 5 mA (3.3 V)
Output high voltage on VOHP CC VDDP
-
-
-
-
-
I
I
OH = -10 mA (5 V)
OH = -7 mA (3.3 V)
port pins
(with standard pads)
1.0
VDDP
0.4
–
–
–
–
V
V
V
V
I
I
OH = -4.5 mA (5 V)
OH = -2.5 mA (3.3 V)
Output high voltage on VOHP1 CC VDDP
I
I
I
OH = -6 mA (5 V)
OH = -8 mA (3.3 V)
OH = -4 mA (3.3 V)
high current pads
0.32
VDDP
1.0
VDDP
0.4
Input low voltage on port VILPS SR
pins
–
0.19 × V
VDDP
CMOS Mode
(5 V, 3.3 V & 2.2 V)
(Standard Hysteresis)
Data Sheet
38
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 14
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
Max.
Input high voltage on
port pins
VIHPS SR 0.7 ×
–
V
CMOS Mode
(5 V, 3.3 V & 2.2 V)
VDDP
(Standard Hysteresis)
Input low voltage on port VILPL SR
pins
–
0.08 × V
VDDP
CMOS Mode
(5 V, 3.3 V & 2.2 V)18)
(Large Hysteresis)
Input high voltage on
port pins
VIHPL SR 0.85 ×
–
V
CMOS Mode
VDDP
(5 V, 3.3 V & 2.2 V)18)
(Large Hysteresis)
Rise time on High
Current Pad1)
tHCPR CC
–
–
–
9
ns
ns
ns
50 pF @ 5 V2)
50 pF @ 3.3 V3)
50 pF @ 1.8 V4)
12
25
Fall time on High
Current Pad1)
tHCPF CC
–
–
–
9
ns
ns
ns
50 pF @ 5 V2)
50 pF @ 3.3 V3)
50 pF @ 1.8 V4)
12
25
Rise time on Standard tR
CC
CC
–
–
–
12
15
31
ns
ns
ns
50 pF @ 5 V5)
50 pF @ 3.3 V6)
50 pF @ 1.8 V7)
Pad1)
Fall time on Standard
Pad1)
tF
–
–
–
12
15
31
ns
ns
ns
50 pF @ 5 V5)
50 pF @ 3.3 V6)
50 pF @ 1.8 V7)
Data Sheet
39
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 14
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
Max.
Input Hysteresis8)
HYS CC 0.08 ×
–
V
V
V
CMOS Mode (5 V),
Standard Hysteresis
VDDP
0.03 ×
VDDP
–
–
CMOS Mode (3.3 V),
Standard Hysteresis
0.02 ×
VDDP
CMOS Mode (2.2 V),
Standard Hysteresis
0.5 ×
VDDP VDDP
0.75 × V
0.75 × V
CMOS Mode(5 V),
Large Hysteresis
0.4 ×
VDDP VDDP
CMOS Mode(3.3 V),
Large Hysteresis
0.2 ×
VDDP VDDP
0.65 × V
CMOS Mode(2.2 V),
Large Hysteresis
Pin capacitance (digital CIO
inputs/outputs)
CC
–
10
50
50
1
pF
Pull-up resistor on port RPUP CC 20
pins
kohm VIN = VSSP
kohm VIN = VDDP
Pull-down resistor on
port pins
Input leakage current9) IOZP
RPDP CC 20
CC -1
SR
SR -10
μA
V
0 < VIN < VDDP
TA ≤ 105 °C
,
10)
Voltage on any pin
during VDDP power off
VPO
IMP
–
0.3
11
Maximum current per
pin (excluding P1, VDDP
and VSS)
mA
–
Maximum current per
high currrent pins
IMP1A SR -10
50
mA
mA
–
18)
Maximum current into
IMVDD1 SR
–
–
130
V
DDP (TSSOP16,
VQFN24)
18)
Maximum current into
IMVDD2 SR
260
mA
V
DDP (TSSOP38,
VQFN40)
Data Sheet
40
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 14
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values Unit Test Conditions
Min.
Max.
18)
18)
Maximum current out of IMVSS1 SR
SS (TSSOP16,
VQFN24)
–
130
mA
mA
V
Maximum current out of IMVSS2 SR
–
260
V
SS (TSSOP38,
VQFN40)
1) Rise/Fall time parameters are taken with 10% - 90% of supply.
2) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage.
3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.
4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.
5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage.
6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.
7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.
8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot
be guaranteed that it suppresses switching due to external system noise.
9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
10) However, for applications with strict low power-down current requirements, it is mandatory that no active
voltage source is supplied at any GPIO pin when VDDP is powered off.
Data Sheet
41
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.2.2
Analog to Digital Converters (ADC)
Table 15 shows the Analog to Digital Converter (ADC) characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 15
ADC Characteristics (Operating Conditions apply)1)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
DD_int SR 2.0
Typ. Max.
Supply voltage range
(internal reference)
V
–
3.0
V
SHSCFG.AREF = 11B
CALCTR.CALGNSTC
= 0CH
3.0
3.0
–
–
5.5
5.5
V
V
SHSCFG.AREF = 10B
SHSCFG.AREF = 00B
Supply voltage range VDD_ext
(external reference)
SR
Analog input voltage
range
VAIN SR
VSSP
- 0.05
–
VDDP
+
V
0.05
Auxiliary analog
reference ground
VREFGND
SR
VSSP
- 0.05
–
–
1.0
0.2
V
V
V
G0CH0
G1CH0
VSSP
- 0.05
Internal reference
voltage (full scale
value)
VREFINT
CC
5
Switched capacitance CAINS CC
of an analog input
–
–
–
–
–
–
1.2
1.2
4.5
4.5
–
2
pF
pF
pF
pF
pF
pF
GNCTRxz.GAINy=00B
(unity gain)
2
GNCTRxz.GAINy=01B
(gain g1)
6
GNCTRxz.GAINy=10B
(gain g2)
6
GNCTRxz.GAINy=11B
(gain g3)
Total capacitance of
an analog input
CAINT CC
10
10
Total capacitance of
the reference input
CAREFT
CC
–
Data Sheet
42
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 15
ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Gain settings
GIN CC
1
–
–
–
–
GNCTRxz.GAINy=00B
(unity gain)
3
GNCTRxz.GAINy=01B
(gain g1)
6
GNCTRxz.GAINy=10B
(gain g2)
12
GNCTRxz.GAINy=11B
(gain g3)
Sample Time
t
sample CC 3
3
–
–
–
–
–
–
–
–
1 /
fADC
V
V
V
DD = 5.0 V
DD = 3.3 V
DD = 2.0 V
1 /
fADC
30
20
1 /
fADC
Sigma delta loop hold tSD_hold
time
μs
Residual charge stored
in an active sigma delta
loop remains available
2)
CC
Conversion time
in fast compare mode
t
t
CF CC
9
1 /
fADC
2)
Conversion time
in 12-bit mode
C12 CC
20
–
1 /
fADC
Maximum sample rate fC12 CC
–
–
fADC / –
1 sample
pending
in 12-bit mode 3)
42.5
–
fADC / –
2 samples
pending
2)
62.5
Conversion time
in 10-bit mode
t
C10 CC
18
–
1 /
fADC
Maximum sample rate fC10 CC
–
–
f
ADC / –
40.5
ADC / –
58.5
1 sample
pending
in 10-bit mode 3)
–
f
2 samples
pending
2)
Conversion time
in 8-bit mode
t
C8 CC
16
1 /
fADC
Data Sheet
43
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 15
ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Maximum sample rate fC8 CC
–
–
f
ADC / –
1 sample
pending
in 8-bit mode 3)
38.5
–
–
–
f
ADC / –
2 samples
pending
54.5
RMS noise 4)
ENRMS
1.5
–
LSB DC input,
CC
12
VDD = 5.0 V,
VAIN = 2.5 V
,
25°C
DNL error
INL error
EADNL CC –
±2.0 –
±4.0 –
±0.5 –
±3.6 –
LSB
12
EAINL CC
–
–
–
LSB
12
Gain error with
external reference
EAGAIN
CC
%
SHSCFG.AREF = 00B
(calibrated)
Gain error with internal EAGAIN
%
SHSCFG.AREF = 1XB
(calibrated),
-40°C - 105°C
reference 5)
CC
–
±2.0 –
±8.0 –
%
SHSCFG.AREF = 1XB
(calibrated),
0°C - 85°C
Offset error
EAOFF CC –
mV Calibrated,
DD = 5.0 V
V
1) The parameters are defined for ADC clock frequency fSH = 32MHz, SHSCFG.DIVS = 0000B. Usage of any
other frequencies may affect the ADC performance.
2) No pending samples assumed, excluding sampling time and calibration.
3) Includes synchronization and calibration (average of gain and offset calibration).
4) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(AMAXeff / NRMS).
With AMAXeff = 2N / 2, SNR[dB] = 20 × log ( 2048 / NRMS) [N = 12].
NRMS = 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.
5) Includes error from the reference voltage.
Data Sheet
44
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
CH7
VAIN
.
.
SAR
Converter
:
CH0
VREF
VREFGND
VREFINT
VAREF
VSS
VDD
Internal
Reference
VDDint
VDDext
/
CHNR
REFSEL
AREF
MC_VADC_AREFPATHS
Figure 11
ADC Voltage Supply
Data Sheet
45
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.2.3
Out of Range Comparator (ORC) Characteristics
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
VDDP on selected input pins (ORCx.AIN) and generates a service request trigger
(ORCx.OUT).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 16
Out of Range Comparator (ORC) Characteristics (Operating
Conditions apply; VDDP = 3.0 V - 5.5 V; CL = 0.25 pF)
Parameter
Symbol
Values
Unit Note / Test Condition
Min. Typ. Max.
DC Switching Level VODC CC 54
−
−
−
−
−
−
−
−
183 mV VAIN ≥ VDDP + VODC
Hysteresis
VOHYS CC 15
tOPDD CC 103
88
54
-
mV
ns
ns
ns
ns
Always detected
Overvoltage Pulse
VAIN ≥ VDDP + 150 mV
VAIN ≥ VDDP + 350 mV
VAIN ≥ VDDP + 150 mV
VAIN ≥ VDDP + 350 mV
VAIN ≥ VDDP + 150 mV
VAIN ≥ VDDP + 350 mV
-
Never detected
Overvoltage Pulse
tOPDN CC
−
−
21
11
Detection Delay of a tODD CC 39
132 ns
121 ns
persistent
Overvoltage
31
Release Delay
tORD CC 44
57
−
−
−
240 ns
340 ns
300 ns
VAIN ≤ VDDP; VDDP = 5 V
VAIN ≤ VDDP; VDDP = 3.3 V
ORCCTRL.ENORCx = 1
Enable Delay
tOED CC −
VDDP
ORCx.AIN
VSS
ORCx.OUT
tODD
tORD
Figure 12
ORCx.OUT Trigger Generation
Data Sheet
46
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
VAIN(V)
T > tOPDD
tOPDN < T < tOPDD
T < tOPDN
VDDP + 350 mV
VDDP + 150 mV
tOPDN < T < tOPDD
T > tOPDD
T < tOPDN
T > tOPDD
VDDP + 60 mV
VDDP
Never
detected
Overvoltage
Pulse
Never
detected
Overvoltage
Pulse
Overvoltage
may be
detected
Never
detected
Overvoltage
Pulse
Overvoltage
may be
detected
Always detected
Overvoltage Pulse
Always detected
Overvoltage Pulse
Overvoltage
may be
detected
(long enough,
level uncertain
(Too low)
(Too short)
(Too short)
)
VSSA
Figure 13
ORC Detection Ranges
Data Sheet
47
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.2.4
Analog Comparator Characteristics
Table 17 below shows the Analog Comparator characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 17
Analog Comparator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Notes/
Test Conditions
Min. Typ. Max.
Input Voltage
Input Offset
VCMP
SR -0.05
–
VDDP
0.05
+
V
VCMPOFF CC
–
–
–
–
–
–
–
+/-3
–
mV High power mode
Δ VCMP < 200 mV
+/-20 –
mV Low power mode
Δ VCMP < 200 mV
Propagation
Delay1)
tPDELAY
CC
25
–
–
–
–
–
ns
ns
ns
ns
μA
High power mode,
Δ VCMP = 100 mV
80
High power mode,
Δ VCMP = 25 mV
250
700
100
Low power mode,
Δ VCMP = 100 mV
Low power mode,
Δ VCMP = 25 mV
Current
Consumption
IACMP
CC
First active ACMP in
high power mode,
ΔVCMP > 30 mV
–
66
–
μA
Each additional
ACMP in high power
mode, ΔVCMP > 30 mV
–
–
10
6
–
–
μA
μA
First active ACMP in
low power mode
Each additional
ACMP in low power
mode
Input Hysteresis VHYS
Filter Delay1)
tFDELAY
CC
CC
–
–
+/-15 –
mV
ns
5
–
1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay.
Data Sheet
48
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.2.5
Temperature Sensor Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 18
Temperature Sensor Characteristics
Parameter
Symbol
Values
Unit Note /
Test Condition
Min. Typ. Max.
Measurement time
tM CC
−
−
10
ms
Temperature sensor range
Sensor Accuracy1)
T
T
SR SR
-40
−
115 °C
TSAL CC -6
-10
–
6
°C
°C
°C
TJ > 20°C
–
10
–
0°C ≤ TJ ≤ 20°C
TJ < 0°C
−
-/+8
Start-up time after enabling
t
TSSTE SR −
−
15
μs
1) The temperature sensor accuracy is independent of the supply voltage.
Data Sheet
49
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.2.6
Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19
Power Supply Parameters; VDDP = 5V
Parameter
Symbol
Values
Unit
Note /
Min Typ.1) Max.
.
Test Condition
Active mode current
Peripherals enabled
fMCLK / fPCLK in MHz2)
I
I
I
I
DDPAE CC −
9.2
8.1
6.6
5.5
4
12
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
−
−
-
−
-
−
-
Active mode current
Peripherals disabled
fMCLK / fPCLK in MHz3)
DDPAD CC −
4.8
4.1
3.3
2.7
1.5
7.3
6.3
5.2
4.2
3.3
6.6
5.8
5.1
4.4
3.7
-
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
−
-
−
-
−
-
−
-
Active mode current
DDPAR CC −
-
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
Code execution from RAM
Flash is powered down
fMCLK / fPCLK in MHz
−
-
−
-
−
−
-
-
Sleep mode current
DDPSE CC −
-
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
Peripherals clock enabled
-
fMCLK / fPCLK in MHz4)
-
-
-
Data Sheet
50
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 19
Power Supply Parameters; VDDP = 5V
Parameter
Symbol
Values
Unit
Note /
Min Typ.1) Max.
.
Test Condition
Sleep mode current
Peripherals clock disabled
Flash active
I
I
I
DDPSD CC −
DDPSR CC −
DDPDS CC −
1.8
1.7
1.6
1.5
1.4
1.2
1.1
1.0
0.8
0.7
0.24
6
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
cycles
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
fMCLK / fPCLK in MHz5)
Sleep mode current
32 / 64
24 / 48
16 / 32
8 / 16
1 / 1
Peripherals clock disabled
Flash powered down
fMCLK / fPCLK in MHz6)
Deep Sleep mode current7)
Wake-up time from Sleep to tSSA CC
−
Active mode8)
Wake-up time from Deep
Sleep to Active mode9)
t
DSA CC
−
280
-
μsec
1) The typical values are measured at TA = + 25 °C and VDDP = 5 V.
2) CPU and all peripherals clock enabled, Flash is in active mode.
3) CPU enabled, all peripherals clock disabled, Flash is in active mode.
4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.
5) CPU in sleep, Flash is in active mode.
6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.
7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.
8) CPU in sleep, Flash is in active mode during sleep mode.
9) CPU in sleep, Flash is in powered down mode during deep sleep mode.
Data Sheet
51
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Figure 14 shows typical graphs for active mode supply current for VDDP = 5V, VDDP
=
3.3V, VDDP = 1.8V across different clock frequencies.
10
9
8
7
6
IDDPA E 5V/3.3V
IDDPA E 1.8V
5
4
3
2
1
0
I (mA)
IDDPA D 5V/3.3V/1.8V
1/1
8/16
16/32 24/48 32/64
MCLK / PCLK (MHz)
Condition:
1. TA = +25° C
Figure 14
Active mode, a) peripherals clocks enabled, b) peripherals clocks
disabled: Supply current IDDPA over supply voltage VDDP for different clock
frequencies
Data Sheet
52
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Figure 15 shows typical graphs for sleep mode current for VDDP = 5V, VDDP = 3.3V, VDDP
= 1.8V across different clock frequencies.
1 .4
1 .2
1
0 .8
I (m A)
0 .6
ID DPS R
5 V/3.3V/1.8V
0 .4
0 .2
0
1 /1
8 /1 6 1 6 /32 2 4 /48 3 2 /64
M CLK / P CL K (M Hz)
C o n d itio n :
1 . T A = + 2 5 ° C
Figure 15
Sleep mode, peripherals clocks disabled, Flash powered down:
Supply current IDDPSR over supply voltage VDDP for different clock frequencies
Data Sheet
53
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 20 provides the active current consumption of some modules operating at 5 V
power supply at 25° C. The typical values shown are used as a reference guide on the
current consumption when these modules are enabled.
Table 20
Typical Active Current Consumption
Active Current
Consumption
Symbol
Limit
Values
Unit
Test Condition
Typ.
Baseload current ICPUDDC
5.04
mA
Modules including Core, SCU,
PORT, memories, ANATOP1)
VADC and SHS
USIC0
IADCDDC
3.4
mA
mA
mA
mA
mA
mA
mA
mA
mA
Set CGATCLR0.VADC to 12)
Set CGATCLR0.USIC0 to 13)
Set CGATCLR0.CCU40 to 14)
Set CGATCLR0.CCU80 to 15)
Set CGATCLR0.POSIF0 to 16)
Set CGATCLR0.BCCU0 to 17)
Set CGATCLR0.MATH to 18)
Set CGATCLR0.WDT to 19)
Set CGATCLR0.RTC to 110)
IUSIC0DDC 0.87
ICCU40DDC 0.94
ICCU80DDC 0.42
CCU40
CCU80
POSIF0
BCCU0
MATH
IPIF0DDC
0.26
IBCCU0DDC 0.24
IMATHDDC 0.35
WDT
IWDTDDC
IRTCDDC
0.03
0.01
RTC
1) Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop
in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.
2) Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode
3) Active current is measured with: module enabled, alternating messages sent to PC at 57.6kbaud every 200ms
4) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching
from 1500Hz and 1000Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle
5) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU8 slice with PWM frequency
at 1500Hz and a period match interrupt used to toggle duty cycle between 10% and 90%
6) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, hall sensor mode
7) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, FCLK=0.8MHz, Normal
mode (BCCU Clk = FCLK/4), 3 BCCU Channels and 1 Dimming Engine, change color or dim every 1s
8) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, tangent calculation in while
loop; CORDIC circular rotation, no keep, autostart; 32-by-32 bit signed DIV, autostart, DVS right shift by 11
9) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB =
0x00008000; WDT serviced every 1s
10) Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled
Data Sheet
54
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.2.7
Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 21
Flash Memory Parameters
Symbol
Parameter
Values
Unit
Note /
Test Condition
Min. Typ. Max.
Erase Time per
page / sector
t
t
t
ERASE CC
PSER CC
WU CC
6.8 7.1 7.6
ms
Program time per
block
102 152 204
μs
Wake-Up time
−
32.2
50
−
−
−
−
μs
Read time per word
Data Retention Time
ta CC
RET CC
−
ns
t
10
years Max. 100 erase /
program cycles
Flash Wait States 1)
N
WSFLASH CC 0
0
0
1
2
1
fMCLK = 8 MHz
fMCLK = 16 MHz
fMCLK = 32 MHz
0
1
0
1
1.3
0
Fixed Flash Wait
States configured in
bit
NFWSFLASH
SR
NVM_CONFIG1.FI
XWS = 1B,
fMCLK ≤ 16 MHz
NVM_NVMCONF.WS
1
1
1
NVM_CONFIG1.FI
XWS = 1B,
16 MHz < fMCLK
≤
32 MHz
Erase Cycles
N
ECYC CC
−
−
−
−
5*104 cycles Sum of page and
sector erase cycles
2*106 cycles
Total Erase Cycles
NTECYC CC
1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical
values are calculated from the execution of the Dhrystone benchmark program.
Data Sheet
55
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.3
AC Parameters
3.3.1
Testing Waveforms
VDDP
90%
90%
10%
10%
VSS
tR
tF
Figure 16
Rise/Fall Time Parameters
VDDP
VDDP / 2
VDDP / 2
Test Points
VSS
Figure 17
Testing Waveform, Output Delay
VLOAD + 0.1V
VOH - 0.1V
VOL + 0.1V
Timing
Reference
Points
VLOAD - 0.1V
Figure 18
Testing Waveform, Output High Impedance
Data Sheet
56
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.3.2
Power-Up and Supply Monitoring Characteristics
Table 22 provides the characteristics of the power-up and supply monitoring in
XMC1300.
The guard band between the lowest valid operating voltage and the brownout reset
threshold provides a margin for noise immunity and hysteresis. The electrical
parameters may be violated while VDDP is outside its operating range.
The brownout detection triggers a reset within the defined range. The prewarning
detection can be used to trigger an early warning and issue corrective and/or fail-safe
actions in case of a critical supply voltage drop.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 22
Power-Up and Supply Monitoring Parameters (Operating Conditions
apply)
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Condition
Min.
V
V
DDP ramp-up time
DDP slew rate
t
RAMPUP SR VDDP
/
−
−
−
107
0.1
10
μs
SVDDPrise
S
VDDPOP SR
0
V/μs Slope during
normal operation
SVDDP10 SR
0
0
V/μs Slope during fast
transient within +/-
10% of VDDP
S
VDDPrise SR
−
−
10
V/μs Slope during
power-on or
restart after
brownout event
SVDDPfall1) SR 0
0.25 V/μs Slope during
supply falling out
of the +/-10%
limits2)
V
DDP prewarning
V
DDPPW CC 2.1
2.85
4.2
2.25 2.4
V
V
V
ANAVDEL.VDEL_
SELECT = 00B
voltage
3
3.15
4.6
ANAVDEL.VDEL_
SELECT = 01B
4.4
ANAVDEL.VDEL_
SELECT = 10B
Data Sheet
57
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 22
Power-Up and Supply Monitoring Parameters (Operating Conditions
apply) (cont’d)
Parameter
Symbol
Values
Typ. Max.
1.62 1.75
Unit Note /
Test Condition
Min.
DDPBO CC 1.55
V
DDP brownout reset
V
V
V
calibrated, before
user code starts
running
voltage
V
DDP voltage to
DDPPA CC
−
−
−
1.0
−
–
–
V
ensure defined pad
states
Start-up time from
power-on reset
t
t
SSW SR
320
8.25
μs
ms
Time to the first
user code
instruction3)
BMI program time
BMI SR
Time taken from a
user-triggered
system reset after
BMI installation is
is requested
1) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated
for this parameter.
2) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to
the chip. A larger capacitor value has to be chosen if the power source sink a current.
3) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHz
and the clocks to peripheral as specified in register CGATSTAT0 are gated.
5.0V
VDDPPW
}
VDDP
VDDPBO
Figure 19
Supply Threshold Parameters
Data Sheet
58
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.3.3
On-Chip Oscillator Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 23 provides the characteristics of the 64 MHz clock output from the digital
controlled oscillator, DCO1 in XMC1300.
Table 23
64 MHz DCO1 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min. Typ. Max.
Nominal frequency fNOM CC
–
64
–
MHz under nominal
conditions1) after
trimming
Accuracy2)
ΔfLT CC -1.7
–
3.4
4.0
%
with respect to fNOM(typ),
over temperature
(TA = 0 °C to 85 °C)
-3.9
–
%
with respect to fNOM(typ),
over temperature
(TA = -40 °C to 105 °C)
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
2) The accuracy can be further improved through alternative methods, refer to XMC1000 Oscillator Handling
Application Note.
Data Sheet
59
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Figure 20 shows the typical curves for the accuracy of DCO1, with and without
calibration based on temperature sensor, respectively.
4.00
3.00
2.00
Without calibration based
on temperature sensor
1.00
With calibration based on
temperature sensor
0.00
-1.00
-2.00
-3.00
-4.00
-50 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100 110 120
°
Temperature [ C]
Figure 20
Typical DCO1 accuracy over temperature
Table 24 provides the characteristics of the 32 kHz clock output from digital controlled
oscillators, DCO2 in XMC1300.
Table 24
32 kHz DCO2 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
Min. Typ. Max.
Nominal frequency
Accuracy
fNOM CC –
32.75 –
kHz under nominal
conditions1) after trimming
ΔfLT CC -1.7
–
–
3.4
%
%
with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9
4.0
with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
Data Sheet
60
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.3.4
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 25
SWD Interface Timing Parameters(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
50
Typ. Max.
SWDCLK high time
SWDCLK low time
t1 SR
t2 SR
t3 SR
–
–
–
500000 ns
500000 ns
–
–
–
50
SWDIO input setup
10
–
ns
to SWDCLK rising edge
SWDIO input hold
t4 SR
10
–
–
ns
–
after SWDCLK rising edge
SWDIO output valid time t5 CC
after SWDCLK rising edge
–
–
4
–
–
–
68
62
–
ns
ns
ns
CL = 50 pF
CL = 30 pF
SWDIO output hold time t6 CC
from SWDCLK rising edge
t1
t2
SWDCLK
t6
SWDIO
(Output)
t5
t3
t4
SWDIO
(Input )
Figure 21
SWD Timing
Data Sheet
61
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.3.5
SPD Timing Requirements
The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints for the sample clock. For instance for a oversampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
Table 26
Optimum Number of Sample Clocks for SPD
Sample Effective Remark
Sample Sampling Sample
Freq.
Factor
Clocks 0B Clocks 1B Decision
Time1)
8 MHz
4
1 to 5
6 to 12
0.69 µs
The other closest option
(0.81 µs) for the effective
decision time is less robust.
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks)
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
•
•
Frequency deviation of the sample clock is +/- 5%
Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Data Sheet
62
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.3.6
Peripheral Timings
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 27
USIC SSC Master Mode Timing
Symbol Values
Typ. Max.
Parameter
Unit Note /
Test Condition
Min.
CLK CC 62.5
SCLKOUT master clock
period
t
−
−
ns
ns
Slave select output SELO t1 CC 80
active to first SCLKOUT
transmit edge
−
−
Slave select output SELO t2 CC
inactive after last
0
−
−
ns
SCLKOUT receive edge
Data output DOUT[3:0]
valid time
t3 CC -10
t4 SR 80
−
−
10
ns
ns
Receive data input
−
DX0/DX[5:3] setup time to
SCLKOUT receive edge
Data input DX0/DX[5:3]
hold time from SCLKOUT
receive edge
t5 SR
0
−
−
ns
Data Sheet
63
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 28
USIC SSC Slave Mode Timing
Parameter
Symbol
Min.
Values
Unit Note /
Test Condition
Typ. Max.
DX1 slave clock period
tCLK SR 125
t10 SR 10
−
−
−
−
ns
ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
Select input DX2 hold after t11 SR 10
last clock input DX1 receive
edge1)
−
−
−
−
−
ns
ns
ns
ns
Receive data input
t12 SR 10
−
DX0/DX[5:3] setup time to
shift clock receive edge1)
Data input DX0/DX[5:3] hold t13 SR 10
time from clock input DX1
receive edge1)
−
Data output DOUT[3:0] valid t14 CC -
80
time
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
64
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Master Mode Timing
t1
t2
Select Output
SELOx
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
Last Receive
Edge
First Transmit
Edge
Transmit
Edge
t3
t3
Data Output
DOUT[3:0]
t4
t4
t5
t5
Data Input
DX0/DX[5:3]
Data
valid
Data
valid
Slave Mode Timing
t10
t11
Select Input
DX2
Inactive
Active
Inactive
Clock Input
DX1
Receive
Edge
Last Receive
Edge
First Transmit
Edge
Transmit
Edge
t12
t12
t13
t13
Data Input
DX0/DX[5:3]
Data
valid
Data
valid
t14
t14
Data Output
DOUT[3:0]
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched.
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
Figure 22
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
Data Sheet
65
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
3.3.6.2 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 29
USIC IIC Standard Mode Timing1)
Symbol Values
Parameter
Unit Note /
Test Condition
Min.
Typ.
Max.
Fall time of both SDA and t1
-
-
300
ns
ns
µs
ns
µs
µs
µs
µs
µs
µs
SCL
CC/SR
Rise time of both SDA and t2
-
-
-
-
-
-
-
-
-
-
1000
SCL
CC/SR
Data hold time
t3
0
-
-
-
-
-
-
-
-
CC/SR
Data set-up time
t4
250
4.7
4.0
4.0
4.7
4.0
4.7
CC/SR
LOW period of SCL clock t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
CC/SR
Hold time for (repeated)
START condition
Set-up time for repeated t8
START condition
CC/SR
Set-up time for STOP
condition
t9
CC/SR
Bus free time between a t10
STOP and START
CC/SR
condition
Capacitive load for each
bus line
Cb SR
-
-
400
pF
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Data Sheet
66
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
Table 30
USIC IIC Fast Mode Timing1)
Parameter
Symbol
Min.
Values
Typ.
-
Unit Note /
Test Condition
Max.
Fall time of both SDA and t1
20 +
300
ns
SCL CC/SR 0.1*Cb
2)
Rise time of both SDA and t2
20 +
-
-
-
-
-
-
-
-
-
300
ns
µs
ns
µs
µs
µs
µs
µs
µs
SCL
CC/SR 0.1*Cb
Data hold time
t3
0
-
-
-
-
-
-
-
-
CC/SR
Data set-up time
t4
100
1.3
0.6
0.6
0.6
0.6
1.3
CC/SR
LOW period of SCL clock t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
CC/SR
Hold time for (repeated)
START condition
Set-up time for repeated t8
START condition
CC/SR
Set-up time for STOP
condition
t9
CC/SR
Bus free time between a t10
STOP and START
CC/SR
condition
Capacitive load for each
bus line
Cb SR
-
-
400
pF
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet
67
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
t1
t2
t4
70%
30%
SDA
SCL
t1
t3
t2
t6
9th
clock
t7
t5
t10
S
SDA
SCL
t8
t7
t9
9th
clock
Sr
P
S
Figure 23
USIC IIC Stand and Fast Mode Timing
3.3.6.3 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 31
USIC IIS Master Transmitter Timing
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
Clock period
t1 CC
2/fMCLK
4/fMCLK
-
-
-
-
-
-
ns
ns
ns
VDDP ≥ 3 V
VDDP < 3 V
Clock HIGH
Clock Low
t2 CC
t3 CC
0.35 x
t1min
0.35 x
t1min
-
-
-
ns
Hold time
t4 CC
t5 CC
0
-
-
-
ns
Clock rise time
0.15 x ns
t1min
Data Sheet
68
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Electrical Parameters
t1
t2
t5
t4
t3
SCK
WA/
DOUT
Figure 24
USIC IIS Master Transmitter Timing
USIC IIS Slave Receiver Timing
Table 32
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
Clock period
Clock HIGH
t6 SR
t7 SR
4/fMCLK
-
-
-
-
ns
ns
0.35 x
t6min
Clock Low
Set-up time
Hold time
t8 SR
t9 SR
0.35 x
t6min
-
-
-
-
-
-
ns
ns
ns
0.2 x
t6min
t10 SR 10
t6
t7
t8
t9
SCK
t10
WA/
DIN
Figure 25
USIC IIS Slave Receiver Timing
Data Sheet
69
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Package and Reliability
4
Package and Reliability
The XMC1300 is a member of the XMC1000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the exposed die pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1
Package Parameters
Table 33 provides the thermal characteristics of the packages used in XMC1300.
Table 33
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Min. Max.
Unit
Package Types
Exposed Die Pad
Dimensions
Ex × Ey
CC
-
-
2.7 × 2.7 mm
3.7 × 3.7 mm
PG-VQFN-24-19
PG-VQFN-40-13
PG-TSSOP-16-81)
PG-TSSOP-28-161)
PG-TSSOP-38-91)
PG-VQFN-24-191)
PG-VQFN-40-131)
Thermal resistance
Junction-Ambient
RΘJA CC -
104.6
83.2
70.3
46.0
38.4
K/W
K/W
K/W
K/W
K/W
-
-
-
-
1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSSP, independent of EMC and thermal requirements.
4.1.1
Thermal Considerations
When operating the XMC1300 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 115 °C.
Data Sheet
70
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Package and Reliability
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
P
INT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
IOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
P
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
71
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Package and Reliability
4.2
Package Outlines
Figure 26
PG-TSSOP-38-9
Data Sheet
72
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Package and Reliability
Figure 27
PG-TSSOP-28-16
Data Sheet
73
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Package and Reliability
Figure 28
PG-TSSOP-16-8
Data Sheet
74
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Package and Reliability
Figure 29
PG-VQFN-24-19
Data Sheet
75
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Package and Reliability
Figure 30
PG-VQFN-40-13
All dimensions in mm.
Data Sheet
76
V2.0, 2017-10
XMC1300 AB-Step
XMC1000 Family
Quality Declaration
5
Quality Declaration
Table 34 shows the characteristics of the quality parameters in the XMC1300.
Table 34
Quality Parameters
Symbol Limit Values
Parameter
Unit Notes
Min.
Max.
ESD susceptibility
according to Human Body SR
Model (HBM)
VHBM
-
2000
V
V
Conforming to
EIA/JESD22-
A114-B
ESD susceptibility
VCDM
-
500
Conforming to
according to Charged
Device Model (CDM) pins
SR
JESD22-C101-C
Moisture sensitivity level
MSL
CC
-
-
3
-
JEDEC
J-STD-020D
Soldering temperature
TSDR
SR
260
°C
Profile according
to JEDEC
J-STD-020D
Data Sheet
77
V2.0, 2017-10
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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