XMC7100-F176K4160AA [INFINEON]
The XMC7100/7200 series belongs to the XMC7000 family of 32-bit industrial microcontrollers based on -up to two- ARM Cortex-M7 processor cores.;型号: | XMC7100-F176K4160AA |
厂家: | Infineon |
描述: | The XMC7100/7200 series belongs to the XMC7000 family of 32-bit industrial microcontrollers based on -up to two- ARM Cortex-M7 processor cores. |
文件: | 总196页 (文件大小:2104K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
XMC7100
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
General description
XMC7100 is a family of XMC7000 microcontrollers targeted at industrial applications. XMC7100 has one or two
Arm® Cortex®-M7 CPUs for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and security
processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data
rate (CAN FD) and Ethernet. XMC7000 devices are manufactured on an advanced 40-nm process. XMC7100
incorporates Infineon's low-power flash memory, multiple high-performance analog and digital peripherals, and
enables the creation of a secure computing platform.
Features
• CPU subsystem
- One or two[1] 250-MHz 32-bit Arm® Cortex®-M7 CPUs, each with
• Single-cycle multiply
• Single/double-precision floating point unit (FPU)
• 16-KB data cache, 16-KB instruction cache
• Memory Protection Unit (MPU)
• 16-KB instruction and 16-KB data Tightly-Coupled Memories (TCM)
- 100-MHz 32-bit Arm® Cortex® M0+ CPU with
• Single-cycle multiply
• MPU
- Inter-processor communication in hardware
- Three DMA controllers
• Peripheral DMA controller #0 (P-DMA0, DW0) with 100 channels
• Peripheral DMA controller #1 (P-DMA1, DW1) with 58 channels
• Memory DMA controller (M-DMA0, DMAC0) with 8 channels
• Integrated memories
- Up to 4160 KB of code-flash with an additional up to 256 KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
- Up to 768 KB of SRAM with selectable retention granularity
• Cryptography engine
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
• Using digital signature verification
• Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve
(ECC)
- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)
Note
1. For more information, refer to Ordering information.
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features
• Safety for application
- Memory Protection Unit (MPU)
- Shared Memory Protection Unit (SMPU)
- Peripheral Protection Unit (PPU)
- Watchdog Timer (WDT)
- Multi-Counter Watchdog Timer (MCWDT)
- Low-Voltage Detector (LVD)
- Brown-Out Detection (BOD)
- Overvoltage Detection (OVD)
- Clock Supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)
• Low-power 2.7-V to 5.5-V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power
management
- Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup
- Up to two pins to wake from Hibernate mode
- Up to 220 GPIO pins to wake from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
• Clocks
- Internal Main Oscillator (IMO)
- Internal Low-Speed Oscillator (ILO)
- External Crystal Oscillator (ECO)
- Watch Crystal Oscillator (WCO)
- Phase-Locked Loop (PLL)
- Frequency-Locked Loop (FLL)
• Communication interfaces
- Up to eight CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers
• Compliant with ISO 11898-1:2015
• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
• ISO 16845:2015 certificate available
- Up to 11 runtime-reconfigurable serial communication block (SCB) channels, each configurable as I2C, SPI,
or UART
- One 10/100 Mbps Ethernet MAC interface conforming to IEEE-802.3bw
• Supports the following PHY interfaces:
Media-independent interface (MII)
Reduced media-independent interface (RMII)
• Compliant with IEEE-802.1BA Audio Video Bridging (AVB)
• Compliant with IEEE-1588 Precision Time Protocol (PTP)
• External memory interface
- One SPI (Single, Dual, Quad, or Octal) or HYPERBUS™ interface
- On-the-fly encryption and decryption
- Execute-In-Place (XIP) from external memory
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features
• SDHC interface
- One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure
Digital (SD), or Secure Digital Input Output (SDIO)
• Compliant with eMMC 5.1, SD 6.0, and SDIO 4.10 specifications
- Data rates up to SD High Speed 50 MHz, or eMMC 52-MHz DDR
• Audio interface
- Three Inter-IC Sound (I2S) Interface for connecting digital audio devices
- I2S, left justified, or Time Division Multiplexed (TDM) audio formats
- Independent transmit or receive operation, each in master or slave mode
• Timers
- Up to 75 16-bit and eight 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks
• Up to 12 16-bit counters for motor control
• Up to 63 16-bit counters and eight 32-bit counters for regular operations
• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time
(PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep
• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,
and so on)
• Real time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
• I/O
- Up to 220 programmable I/Os
- Three I/O types
• GPIO Standard (GPIO_STD)
• GPIO Enhanced (GPIO_ENH)
• High-Speed I/O Standard (HSIO_STD)
• Regulators
- Generate a 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Three regulators:
• DeepSleep
• Core internal
• Core external
• Programmable analog
- Three SAR A/D converters with up to 75 external channels (72 I/Os + 3 I/Os for motor control)
• ADC0 supports 32 logical channels, with 32 + 1 physical connections
• ADC1 supports 32 logical channels, with 32 + 1 physical connections
• ADC2 supports 8 logical channels, with 8 + 1 physical connections
• Any external channel can be connected to any logical channel in the respective SAR
- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps
- Each ADC also supports six internal analog inputs like
• Bandgap reference to establish absolute voltage levels
• Calibrated diode for junction temperature calculations
• Two AMUXBUS inputs and two direct connections to monitor supply levels
- Each ADC supports addressing of external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features
• Smart I/O
- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36 I/Os (GPIO_STD) supported
• Debug interface
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® Serial Wire Debug (SWD) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
• Data trace using SWD
• Instruction and data trace using JTAG
• Industry advanced development tools
- Infineon IDE ModusToolbox™ software for code development and debugging
• Packages
- 100-TEQFP, 14 × 14 × 1.6 mm (max), 0.5-mm lead pitch
- 144-TEQFP, 20 × 20 × 1.6 mm (max), 0.5-mm lead pitch
- 176-TEQFP, 24 × 24 × 1.6 mm (max), 0.5-mm lead pitch
- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents...............................................................................................................................5
Features list..................................................................................................................................... 6
Communication peripheral instance list.................................................................................................................... 8
Blocks and functionality ................................................................................................................... 9
Architecture block diagram......................................................................................................................................... 9
Functional description.................................................................................................................... 10
CPU subsystem .......................................................................................................................................................... 10
System resources....................................................................................................................................................... 11
Peripherals................................................................................................................................................................. 15
I/Os ............................................................................................................................................................................. 18
XMC7100 address map .................................................................................................................... 21
Flash base address map .................................................................................................................. 23
Peripheral I/O map ......................................................................................................................... 25
XMC7100 clock diagram .................................................................................................................. 27
XMC7100 CPU start-up sequence ..................................................................................................... 28
Pin assignment .............................................................................................................................. 29
High-speed I/O matrix connections .................................................................................................. 36
Package pin list and alternate functions........................................................................................... 37
Power pin assignments................................................................................................................... 45
Alternate function pin assignments ................................................................................................. 46
Pin function description............................................................................................................................................ 54
Interrupts and wake-up assignments............................................................................................... 57
Core interrupt types ....................................................................................................................... 67
Trigger multiplexer ........................................................................................................................ 68
Triggers group inputs ..................................................................................................................... 70
Triggers group outputs ................................................................................................................... 74
Triggers one-to-one........................................................................................................................ 75
Peripheral clocks............................................................................................................................ 79
Faults............................................................................................................................................ 82
Peripheral protection unit fixed structure pairs................................................................................ 85
Bus masters ................................................................................................................................... 98
Miscellaneous configuration ........................................................................................................... 99
Development support................................................................................................................... 101
Documentation........................................................................................................................................................ 101
Tools......................................................................................................................................................................... 101
Electrical specifications ................................................................................................................ 102
Absolute maximum ratings ..................................................................................................................................... 102
Device-level specifications...................................................................................................................................... 108
Smoothing capacitor recommendations ............................................................................................................... 109
DC specifications ..................................................................................................................................................... 110
Reset specifications................................................................................................................................................. 115
I/O ............................................................................................................................................................................. 116
Analog peripherals................................................................................................................................................... 122
26.8 AC specifications...............................................................................................................................................128
Digital peripherals ................................................................................................................................................... 129
Memory .................................................................................................................................................................... 139
System resources..................................................................................................................................................... 141
Clock specifications................................................................................................................................................. 154
Clock timing diagrams........................................................................................................................................... 160
Datasheet
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32-bit Arm® Cortex®-M7
Table of contents
Ethernet specifications............................................................................................................................................ 162
SDHC specifications................................................................................................................................................. 165
Audio subsystem specifications.............................................................................................................................. 170
Serial memory interface specifications.................................................................................................................. 175
Ordering information ................................................................................................................... 182
Part number nomenclature .................................................................................................................................... 182
Packaging.................................................................................................................................... 183
Appendix ..................................................................................................................................... 188
Bootloading or end-of-line (EoL) programming .................................................................................................... 188
External IP revisions ................................................................................................................................................ 189
Acronyms .................................................................................................................................... 190
Errata.......................................................................................................................................... 192
Revision History ............................................................................................................................ 195
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features list
1
Features list
Table 1-1
XMC7100 feature list for all packages
Packages
144-TEQFP 176-TEQFP
Features
100-TEQFP
272-BGA
CPU
Core
One or two 32-bit Arm® Cortex®-M7 CPUs and a 32-bit Arm® Cortex® M0+ CPU
2.7 V to 5.5 V
Operating voltage
Operating voltage for HSIO_STD
Core voltage
Not supported
1.05 V to 1.15 V
2.7 V to 3.6 V
Arm® Cortex®-M7 250 MHz (max for each) and Arm® Cortex®-M0+ 100 MHz
Operating frequency
(max)
MPU, PPU
FPU
DSP-MUL/DIV/MAC
TCM
Supported
Supports both single (32-bit) and double (64-bit) precision
Supported by Arm® Cortex®-M7 CPUs
16-KB instruction and 16-KB data for each Cortex®-M7 CPU
Memory
1088 KB (960 KB + 128 KB) / 2112 KB (1984 KB + 128 KB) / 4160 KB (4032 KB +
128 KB)[2]
Code-flash
Work-flash
SRAM (configurable for retention)
ROM
128 KB (96 KB + 32 KB) / 256 KB (192 KB + 64 KB)[2]
192 KB / 384 KB / 768 KB[2]
64 KB
Communication Interfaces
CAN0 (CAN-FD: Up to 8 Mbps)
CAN1 (CAN-FD: Up to 8 Mbps)
CAN RAM
4 ch
4[3]/3[4] ch
4 ch
32 KB per instance (CAN0/1), 64 KB in total
Serial Communication Block
9 ch
9[5]/8[6] ch
8 ch
10 ch
10 ch
11 ch
11 ch
11 ch
(SCB/UART)
Serial Communication Block
(SCB/I2C)
Serial Communication Block
10 ch
(SCB/SPI)
Ethernet MAC
1 ch × 10/100 (ETH0, MII/RMII on GPIO_STD)
Memory Interfaces
1 ch
(HSIO_STD at
50 MHz,
1 ch (GPIO_STD at 32 MHz)
1 ch (GPIO_STD at 32 MHz)
eMMC/SD
GPIO_STD at
32 MHz)
1 ch
(HSIO_STD at
100 MHz,
Single SPI / Dual SPI / Quad SPI /
Octal SPI / HYPERBUS™
GPIO_STD at
32 MHz)
Timers
RTC
1 ch
12 ch
63 ch
8 ch
TCPWM (16-bit) (Motor Control)
TCPWM (16-bit)
TCPWM (32-bit)
External Interrupts
72
116
148
220
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features list
Table 1-1
Analog
XMC7100 feature list for all packages (continued)
Packages
144-TEQFP 176-TEQFP
Features
100-TEQFP
272-BGA
3 Units (SAR0/32, SAR1/32, SAR2/8 logical channels)
37 external
52 external
64 external
72 external
channels(SAR0/14 channels(SAR0/21 channels(SAR0/24
channels
12-bit, 1 Msps SAR ADC
ch,
ch,
ch,
(SAR0/32 ch,
SAR1/32 ch,
SAR2/8 ch)
SAR1/15 ch,
SAR2/8 ch)
SAR1/23 ch,
SAR1/32 ch,
SAR2/8 ch)
SAR2/8 ch)
18 ch (6 per ADC) Internal sampling
Motor control input
Security
3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Supported
Flash Security (program/work
read protection)
Flash chip erase enable
eSHE / HSM
Audio
Configurable
By separate firmware[7]
I2S / TDM
Tx 2 ch, Rx 2 ch
Tx 3 ch, Rx 3 ch
System
P-DMA0 with 100 channels (16 general-purpose), P-DMA1 with 58 channels
(8 general-purpose), and M-DMA0 with 8 channels
DMA Controller
Internal main oscillator
8 MHz
Internal low speed oscillator
32.768 kHz (nominal)
PLL
FLL
Input: 3.988 to 33.34 MHz, PLL output: up to 250 MHz
Input: 0.25 to 80 MHz, FLL output: up to 100 MHz
Watchdog Timer and
Supported
Multi-counter Watchdog Timer
Clock Supervisor
Cyclic wakeup from DeepSleep
GPIO_STD
GPIO_ENH
HSIO_STD
Supported
Supported
68
112
144
203
13
4
Not supported
3 blocks, mapped 5 blocks, mapped
Smart I/O (Blocks)
5 blocks, mapped through 36 I/Os
through 15 I/Os through 27 I/Os
Low-voltage detect
Maximum Ambient Temperature
Debug Interface
Two, 26 selectable levels
125 °C
SWD/JTAG
Debug Trace
Arm® Cortex®-M7 ETB size of 8 KB, Arm® Cortex® M0+ MTB size of 4 KB
Notes
2. For more information, refer to Ordering Information.
3. Function EXT_PS_CTL0 on P22.1 is not used.
4. Function EXT_PS_CTL0 on P22.1 is used.
5. Functions EXT_PS_CTL0 on P21.1 and EXT_PS_CTL1 on P21.2 are not used.
6. Function EXT_PS_CTL0 on P21.1 or EXT_PS_CTL1 on P21.2 is used.
7. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Features list
1.1
Communication peripheral instance list
The following table lists the instances supported under each package for communication peripherals, based on
the minimum pins needed for the functionality.
Table 1-2
Communication peripheral instance list
Module
CAN0
CAN1
100-TEQFP
144-TEQFP
0/1/2/3
0/1/2/3
176-TEQFP
0/1/2/3
0/1/2/3
272-BGA
0/1/2/3
0/1/2/3
Minimum pin functions
TX, RX
TX, RX
0/1/2/3
0/1/2/3[3] or
0/2/3[4]
SCB/UAR
T
SCB/I2C
0 to 8
0 to 9
0 to 9
0 to 9
0 to 9
0 to 9
0 to 9
0 to 10
0 to 10
0 to 10
TX, RX
0 to 8[5] or
SCL, SDA
0/1/2/3/4/5/7/8[6]
SCB/SPI
0/1/2/3/4/5/7/8
MISO, MOSI, SCK, SELECT0
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Blocks and functionality
2
Blocks and functionality
2.1
Architecture block diagram
ITCM
16 KB
DTCM
16 KB
DTCM
CPU Subsystem
ITCM
16 KB
SWJ/ETM/ITM/CTI
XMC7100
MXS40-HT
16 KB
SWJ/MTB/CTI
SRAM0
Up to
512KB
SRAM1
Up to
256KB
eCT Flash
Crypto
Arm Cortex M7
ROM
64KB
Arm
Cortex M0+
100 MHz
Up to 4160 KB Code-Flash
+ Up to 256 KB Work-Flash
AES,SHA,CRC,
TRNG,RSA,ECC
250 MHz
B
BS
16KB
D$I$
16KB
FPU
(SP/DP)
SRAM
Controller
SRAM
Controller
8 KB $
Flash Controller
System Resources
Initiator/MMIO
ROM Controller
NVIC, MPU, AXI
AHBP
AHBS
MUL, NVIC, MPU
Power
Sleep Control
POR
OVD
BOD
LVD
System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU)
Peripheral Interconnect (MMIO,PPU)
REF
PWRSYS-HT
LDO
PCLK
Clock
Clock Control
3x MCWDT
Prog.
Analog
2xILO
IMO
WDT
ECO
CSV
FLL
SAR
ADC
(12-bit)
4xPLL
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
x3
Analog DFT
SARMUX
72 ch
WCO
RTC
Power Modes
High Speed I/O Matrix, Smart I/O, Boundary Scan
5x Smart I/O
Active/Sleep
LowePowerActive/Sleep
Up to 203x GPIO_STD, 4x GPIO_ENH, Up to 13x HSIO_STD
DeepSleep
Hibernate
IO Subsystem
The Architecture block diagram shows a simplified view of the interconnection between subsystems and
blocks. XMC7100 has four major subsystems: CPU, system resources, peripherals, and I/O[8, 9, 10]. The
color-coding shows the lowest power mode where the particular block is still functional.
XMC7100 provides extensive support for programming, testing, debugging, and tracing of both hardware and
firmware.
Debug-on-chip functionality enables in-system debugging using the production device. It does not require
special interfaces, debugging pods, simulators, or emulators.
The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet and J-Link.
The debug circuits are enabled by default.
XMC7100 provides a high level of security with robust flash protection and the ability to disable features such as
debug.
Additionally, each device interface can be permanently disabled for applications concerned with phishing
attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash
programming sequences. All programming, debug, and test interfaces are disabled when maximum device
security is enabled.
Notes
8. GPIO_STD supports 2.7 V to 5.5 V VDDIO range.
9. GPIO_ENH supports 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages.
10.HSIO_STD supports 2.7 V to 3.6 V VDDIO range with high-speed signalling and programmable drive strength.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3
Functional description
3.1
CPU subsystem
3.1.1
CPU
The XMC7100 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and one or two 32-bit
Arm® Cortex®-M7 CPUs, each with MPU, single/double-precision FPU, and 16-KB data and instruction caches. This
subsystem also includes P-/M-DMA controllers, a cryptographic accelerator, up to 4160 KB of code-flash, up to
256 KB of work-flash, up to 768 KB of SRAM, and 64 KB of ROM.
The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following
completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,
SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by
an inter-processor communication (IPC) mechanism using hardware semaphores.
Each Cortex-M7 CPU has 16 KB of instruction and 16 KB of data TCM with programmable read wait states. Each
TCM is clocked by the associated Cortex-M7 CPU clock.
3.1.2
DMA controllers
XMC7100 has three DMA controllers: P-DMA0 with 16 general-purpose and 84 dedicated channels, P-DMA1 with 8
general-purpose and 50 dedicated channels, and M-DMA0 with eight channels. P-DMA is used for
peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of
channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.
General-purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables
demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)
to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high
memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each
channel. They support independent accesses to peripherals using the AHB multi-layer bus.
3.1.3
Flash
XMC7100 has 1088 KB (960 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size), 2112 KB (1984 KB
with a 32-KB sector size, and 128 KB with an 8-KB sector size) or 4160 KB (4032 KB with a 32-KB sector size, and
128 KB with an 8-KB sector size) of code-flash with an additional work-flash of 128 KB (96 KB with a 2-KB sector
size, and 32 KB with a 128-B sector size) or 256 KB (192 KB with a 2-KB sector size, and 64 KB with a 128-B sector
size). Work-flash is optimized for reprogramming many more times than code-flash. Code-flash supports
Read-While-Write (RWW) operation allowing flash to be updated while the CPU is active. Both the code-flash and
work-flash areas support dual-bank operation for over-the-air (OTA) programming.
3.1.4
SRAM
XMC7100 has up to 768 KB of SRAM with two independent controllers. SRAM0 provides DeepSleep retention in
32-KB increments while SRAM1 is selectable between fully retained and not retained.
3.1.5
ROM
XMC7100 has 64 KB of ROM that contains boot and configuration routines. This ROM enables secure boot and
authentication of user flash to guarantee a secure system.
3.1.6
Cryptography accelerator for security
The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy
check, pseudo random number generation, true random number generation, galois/counter mode, and a vector
unit to support asymmetric key cryptography such as RSA and ECC.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.2
System resources
Power system
3.2.1
The power system ensures that the supply voltage levels meet the requirements of each power mode, and
provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip
reset during the initial power ramp.
Three BOD circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD is initially
enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the
external supplies VDDD and VDDA, BOD circuits are software-configurable with two settings; a 2.7-V minimum
voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which is also robust for all I/O
specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a
robust detector.
Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and
overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and
VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage.
Two voltage detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising
levels, each configurable for one of the 26 selectable levels.
All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.
The BOD and OVD circuits on VDDA can be configured to generate either a reset, or a fault.
3.2.2
Regulators
XMC7100 contains three regulators that provide power to the low-voltage core transistors: DeepSleep, core
internal, and core external. These regulators accept a 2.7-V to 5.5-V VDDD supply and provide a low-noise 1.1-V
supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and
firmware when switching between power modes. The core internal and core external regulators operate in Active
mode, and provide power to the CPU subsystem and associated peripherals.
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.2.2.1
DeepSleep
The DeepSleep regulator is used to maintain power in a small number of blocks when in DeepSleep mode.
These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other
configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal
regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is
disabled.
3.2.2.2
Core internal
The core internal regulator supports load currents up to 280 mA, and is operational during device start-up
(boot process), and in Active/Sleep modes.
3.2.2.3
Core external[11]
To support worst-case loading, with both M7 CPUs and the M0+ CPU at their maximum clock frequency and all
integrated peripherals operating, a core external regulator is required, capable of load currents up to 600 mA.
While the control and monitor circuits for the core external regulator are internal to XMC7100, the power
regulating element (NPN pass transistor, PMIC, or LDO) is external. This reduces the overall power dissipation
within the XMC7100 package, while maintaining a well-regulated core supply.
The core external regulator may be implemented with either an external NPN pass transistor, PMIC, or linear
regulator (LDO). Each implementation requires different external components on the PCB, and different
connections to XMC7100 for both regulation and control.
Vpwr
(2.7-5.5V)
10 uF
XMC7000
VDDD
NPN transistor
Emitter Follower
ZXT849K
etc
DRV_VOUT
EXT_PS_CTL0
0.1Ω
1/4W
1%
EXT_PS_CTL1
Core supply rail
VCCD
CS1
Figure 3-4
Sample core external regulator with NPN transistor
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
2.7V – 5.5V Power rail
VDDD
Vin
Core supply rail
Switching node
VCCD
XMC7000
External
PMIC
CS1
R1
R2
Enable
(EN)
Feedback
(FB)
DRV_VOUT
VDDD or
EXT_PS_CTL1
Power Good
Power Good
(PG)
EXT_PS_CTL0
EXT_PS_CTL1
- PMIC EN pin polarity is HIGH for enable. PMIC PG pin polarity is HIGH for power good.
- If EN pin of PMIC does not have the internal pull-down resistor, an external pull-down resistor must be placed to keep the PMIC disabled during power-on reset.
- See the Traveo II device datasheet for CS1
.
- Output voltage setting resistors (R1, R2) are needed according to the selected PMIC.
Figure 3-5
Sample core external regulator with PMIC/LDO
Both the core internal and core external regulators require an external bulk storage capacitor connected to the
VCCD pin. This capacitor provides charge under the dynamic loads of the low-voltage core transistors.
3.2.3
Clock system
The XMC7100 clock system provides clocks to all subsystems that require them, and glitch-free switching
between different clock sources. In addition, the clock system ensures that no metastable conditions occur.
The clock system for XMC7100 consists of the 8-MHz IMO, two ILOs, four watchdog timers, four PLLs, an FLL, five
clock supervisors (CSV), a 8- to 33.34-MHz ECO, and a 32.768-kHz WCO.
The clock system supports three main clock domains: CLK_HF, CLK_SLOW, and CLK_LF.
• CLK_HFx are the Active mode clocks. Each can use any of the high-frequency clock sources including IMO,
EXT_CLK, ECO, FLL, or PLL
• CLK_SLOW provides a reference clock for the Cortex-CM0+ CPU, Crypto, P-/M-DMA, and other slow infrastructure
blocks of CPU subsystem
• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The
reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO.
Note
11.When XMC7100 is in Hibernate mode, the GPIO used to control the core external regulator are High-Z. This may
require an external pull-up or pull-down resistor to disable the external regulator and configure it for minimum
operating current.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
Table 3-1
CLK_HF destinations
Description
CPUSS (Memories, CLK_SLOW, Peripherals)
CPUSS (Cortex-M7 CPU 0, 1)
CAN FD, TCPWM, SCB, SAR
Event Generator
Ethernet
Audio Subsystem (I2S)
SDHC Interface, SMIF
Name
CLK_HF0
CLK_HF1
CLK_HF2
CLK_HF3
CLK_HF4
CLK_HF5
CLK_HF6
3.2.3.6
IMO clock source
The IMO is the frequency reference in XMC7100 when no external reference is available or enabled. The IMO
operates at a frequency of around 8 MHz.
3.2.3.7
ILO clock source
An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in
DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven
counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-
vision.
3.2.3.8
PLL and FLL
A PLL (one of the two 200 MHz and two 400 MHz) or FLL may be used to generate high-speed clocks from the IMO,
ECO, or an EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 45 µs) in exchange for a
small amount (±2%) of frequency error[12]. A 400-MHz PLL supports spread spectrum clock generation (SSCG)
with down spreading.
3.2.3.9
Clock supervisor
Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).
Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the
frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the
frequency-range comparator detects a stopped clock or a clock outside the specified frequency range, an
abnormal state is signaled and either a reset or an interrupt is generated.
3.2.3.10
EXT_CLK
One of the three GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be
used as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.
3.2.3.11
ECO
The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.
It supports fundamental mode (non-overtone) quartz crystals, in the range of 8 to 33.34 MHz. When used in
conjunction with the PLL, it generates CPU and peripheral clocks up to the device’s maximum frequency. ECO
accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the
available I/O functions.
Note
12.Operation of reference-timed peripherals (such as a UART) with an FLL-based reference is not recommended
due the allowed frequency error.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.2.3.12
WCO
The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external
32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock
reference for CLK_LF, which is the clock source for the MCWDT and RTC.
3.2.4
Reset
XMC7100 can be reset from a variety of sources, including software. Most reset events are asynchronous and
guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT,
software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and
allows software to determine the cause of the reset. An XRES_L pin is available for external reset.
3.2.5
Watchdog timer
XMC7100 has one watchdog timer (WDT) and three multi-counter watchdog timers (MCWDT).
The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from
Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT
timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause
register.
An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are
only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used
separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.
3.2.6
Power modes
XMC7100 has six power modes.
• Active – all peripherals are available
• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are
available, but with limited capability
• Sleep – all peripherals except the CPUs are available
• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are
available, but with limited capability
• DeepSleep – only peripherals which work with CLK_LF are available
• Hibernate – the device and I/Os are frozen, the device resets on wakeup
3.3
Peripherals
3.3.1
Peripheral clock dividers
Integer and fractional clock dividers are provided for peripheral and timing purposes.
Table 3-1 Clock Dividers - CPUSS Group (Nr. 0)
Divider Type
Instances
Description
div_8
div_16
3
1
Integer divider, 8 bits
Integer divider, 16 bits
Table 3-2
Clock Dividers - COMM Group (Nr. 1)
Divider Type
Instances
Description
div_8
div_16
div_24_5
16
17
16
Integer divider, 8 bits
Integer divider, 16 bits
Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.3.2
Peripheral protection unit
The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,
P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the
bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address
range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).
3.3.3
12-bit SAR ADC
XMC7100 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit
result in 26 clock cycles. The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and
VREFL[13]
.
XMC7100 supports up to 93 logical ADC channels, and external inputs from up to 75 I/Os. Each ADC also supports
six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC and
package type) are listed in Table 1-1.
Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with
zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1
Msps whether it is for a single channel or distributed over several channels). The sequencer switching is
controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the
appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates
subsequent conversions for repetitive or group conversions without CPU intervention.
Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32
GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal
signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports
synchronous sampling of one motor-sense channel on each of the three ADCs.
XMC7100 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be
sampled by one ADC at a time. Software post-processing is required to convert the temperature sensor reading
into kelvin or Celsius values.
To accommodate signals with varying source impedances and frequencies, it is possible to have different sample
times programmed for each channel. Each ADC also supports range comparison, which allows fast detection of
out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate
the measurement for out-of-range values. The ADCs are not usable in DeepSleep and Hibernate modes as they
require a high-speed clock. The ADC input reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA
.
3.3.4
Timer/counter/PWM block (TCPWM)
The TCPWM block consists of 16-bit (75 channels) and 32-bit (8 channels) counters with user-programmable
period. Twelve of the 16-bit counters are optimized for motor-control operations. Each TCPWM counter contains
a capture register to record the count at the time of an event, a period register (used to either stop or auto-reload
the counter when its count is equal to the period register), and compare registers to generate signals that are
used as PWM duty-cycle outputs.
Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,
PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.
In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with
features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead
times for PWM output signals.
The TCPWM block also provides true and complement outputs, with programmable offset between them, to
allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the
PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems
when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time
for software intervention).
Note
13.VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when
properly connected, reduces or removes the impact of IR drops in the VSSIO and VSSA paths from measure-
ments.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.3.5
Serial communication blocks (SCB)
XMC7100 contains up to 11 serial communication blocks, each configurable to support I2C, UART, or SPI.
3.3.5.1
I2C interface
An SCB can be configured to implement a full I2C master (capable of multi-master arbitration) or slave
interface. Each SCB configured for I2C can operate at speeds of up to 1 Mbps (Fast-mode Plus) and has flexible
buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO
buffering for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the
need for clock stretching. The I2C interface is compatible with Standard, Fast-mode, and Fast-mode Plus
devices as specified in the NXP I2C-bus specification and user manual (UM10204). The I2C-bus I/O is
implemented with GPIO in open-drain modes[14, 15]
.
3.3.5.2
UART interface
When configured as a UART, each SCB provides a full-featured UART with maximum signalling rate determined
by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and
SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit
multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines.
Common UART functions such as parity, number of stop bits, break detect, and frame error are supported.
FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.
3.3.5.3
SPI interface
The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start
pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The
SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports
EZSPI[16] mode.
SCB0 supports the following additional features:
• Operable as a slave in DeepSleep mode
• I2C slave EZ (EZI2C[17]) mode with up to 256-B data buffer for multi-byte communication without CPU
intervention
• I2C slave externally-clocked operations
• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention
3.3.6
CAN FD
XMC7100 contains two CAN FD controller blocks, each supporting four CAN FD channel. All CAN FD controllers are
compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the
time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in
hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx
handler manages message acceptance filtering, transfer of received messages from the CAN core to a message
RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages
from the message RAM to the CAN core, and provides transmit-message status.
3.3.7
Ethernet MAC
XMC7100 supports one Ethernet channel with transfer rates of 10, or 100 Mbps. The input/output frames and flow
control are complaint to the Ethernet/IEEE 802.3bw standard and also IEEE-1588 precision-time protocol (PTP).
XMC7100 supports half/full-duplex data transport using external PHY devices. The MAC supports glue-free
connection to PHYs through IEEE standard MII, and RMII interfaces. The device also supports Audio-Video
Bridging (AVB). The MAC supports standard 6-byte programmable addresses.
Notes
14.This is not 100% compliant with the I2C-bus specification; I/Os are not over-voltage tolerant, do not support the 20-mA sink requirement
of Fast-mode Plus, and violate the leakage specification when no power is applied.
15.Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.
16.The Easy SPI (EZSPI) protocol is based on the Motorola SPI protocol operating in any mode (0, 1, 2, or 3). It allows communication
between master and slave while reducing the need for CPU intervention.
17.The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Infineon. It uses a meta protocol
around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This reduces the need for CPU
intervention.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.3.8
External memory interface
In addition to the internal flash memory, XMC7100 supports direct connection to as much as 128 MB of external
flash or RAM memory. This connection is made through either a HYPERBUS™ or serial peripheral interface (SPI).
HYPERBUS™ allows connection to HYPERFLASH™ and HYPERRAM™ devices, while SPI (single, dual, quad, or octal
SPI at up to 90 MHz) can connect with serial flash memory. Code stored in memory connected through this
interface allows execute-in-place (XIP) operation, which does not require the instructions to be first copied to
internal memory, and on-the-fly encryption and decryption for environments requiring secure external data and
code.
3.3.9
SDHC interface
XMC7100 supports one Secure Digital High Capacity (SDHC) interface, which conforms to Secure Digital (SD) 6.0,
Secure Digital Input Output (SDIO) 4.10, and Embedded Multimedia Card (eMMC) 5.1 specifications, along with
Host Control Interface (HCI) 4.2 specification. The interface supports System DMA (SDMA), Advance DMA (ADMA2,
ADMA3), and command queuing (CQ) features. This interface supports data rates of SD DS (Default Speed, 4-bits
at 25 MHz), SD HS (High Speed, 4-bits at 50 MHz, and eMMC 52-MHz DDR (8-bits at 52-MHz card clock).
3.3.10
Audio interface
XMC7100 supports three instances of Inter-IC Sound Bus (I2S) interface to connect to digital audio devices:
Supports I2S, Left Justified (LJ), and eight-channel Time Division Multiplexed (TDM) digital audio interface
formats in both master and slave modes with independent operations in receive and transmit directions.
3.3.11
One-time-programmable (OTP) eFuse
XMC7100 contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable
identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing,
programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available
for user purposes.
3.3.12
Event generator
The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep
mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a
SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide
CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing
overall power consumption and processing overhead.
3.3.13
Trigger multiplexer
XMC7100 supports connection of various peripherals using trigger signals. Triggers are used to inform a
peripheral of the occurrence of an event or change of state. These triggers are used to affect or initiate some
action in other peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a
destination. Triggers provide active logic functionality and are typically supported in Active mode.
3.4
I/Os
XMC7100 has up to 220 programmable I/Os.
The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on and
reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.
Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service
routine (ISR) associated with it.
I/O port power source mapping is listed in Table 3-1. The associated supply determines the VOH, VOL, VIH, and VIL
levels when configured for CMOS and Industrial thresholds.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
Table 3-1
I/O port power source
Supply pins
Ports
VDDD
P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23, P28, P29, P30, P31
VDDIO_1
VDDIO_2
VDDIO_3
P6, P7, P8, P9, P32
P10, P11, P12, P13, P14, P15, P26, P27
P24, P25
3.4.1
Port nomenclature
Px.y describes a particular bit “y” available within an I/O port “x.”
For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
• Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down
XMC7100 has three types of programmable I/Os: GPIO Standard, GPIO Enhanced, and HSIO Standard.
3.4.2
GPIO Standard (GPIO_STD)
Supports standard industrial signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multiple
configurable drive levels, drive modes, and selectable input levels.
3.4.3
GPIO Enhanced (GPIO_ENH)
Supports extended functionality industrial signalling across the 2.7-V to 5.5-V VDDIO range with higher currents at
lower voltages (full I2C timing support, slew-rate control).
Both GPIO_STD and GPIO_ENH implement the following:
• Configurable input threshold (CMOS, TTL, or industrial)
• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
• Analog input mode (input and output buffers disabled)
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Functional description
3.4.4
HSIO Standard (HSIO_STD)
These I/Os are optimized exclusively for high-speed signaling and do not support slew-rate control, DeepSleep
operation, POR mode control, analog connections, or non-CMOS signaling levels. HSIO_STD supports high-speed
peripherals such as QSPI, HYPERBUS™, Ethernet, and SDHC controller. HSIO_STD also supports programmable
drive strength. These I/Os are available only in Active mode and retain state in DeepSleep mode.
3.4.5
Smart I/O
Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals
coming into the chip. XMC7100 has five Smart I/O blocks. Operation can be synchronous or asynchronous and
the blocks operate in all device power modes except for Hibernate.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7100 address map
4
XMC7100 address map
The XMC7100 microcontroller supports the memory spaces shown in Figure 4-1.
• 1088 KB (960 KB + 128 KB), 2112 KB (1984 KB + 128 KB), or 4160 KB (4032 KB + 128 KB) of code-flash, used in
the single- or dual-bank mode based on the associated bit in the flash control register
- Single-bank mode: 1088 KB, 2112 KB, or 4160 KB
- Dual-bank mode: 544 KB, 1056 KB, or 2080 KB per bank
• 128 KB (96 KB + 32 KB) or 256 KB (192 KB + 64 KB) of work-flash, used in the single- or dual-bank mode based
on the associated bit in the flash control register
- Single-bank mode: 128 KB or 256 KB
- Dual-bank mode: 64 KB or 128 KB per bank
• 64 KB of secure ROM
• 192 KB, 384 KB, or 768 KB of SRAM (First 2 KB is reserved for internal usage)
• 16 KB of Instruction TCM for each Cortex-M7 CPU
• 16 KB of Data TCM for each Cortex-M7 CPU
• 128 MB SMIF XIP
0xFFFF FFFF
Arm System
CPU & Debug Registers
Space
0xE000 0000
Reserved
0xA011 3FFF
16 KB
Reserved
16 KB
Reserved
16 KB
Reserved
16 KB
Core CM7_1 Data TCM
CM7_1 DTCM
CM7_1 ITCM
0xA011 0000
0xA010 3FFF
0xA010 0000
Core CM7_1 Instruction TCM
0xA001 3FFF
0xA001 0000
CM7_0 DTCM
CM7_0 ITCM
Core CM7_0 Data TCM
0xA000 3FFF
0xA000 0000
Core CM7_0 Instruction TCM
Reserved
0x67FF FFFF
Serial Memory Interface XIP
128 MB
SMIF_XIP
0x6000 0000
0x43FF FFFF
Reserved
Peripheral
Mainly used for on-chip peripherals;
e.g., AHB or APB peripherals
Interconnect or
Memory map
0x4000 0000
Reserved
General purpose RAM,
mainly used for data
See “XMC7100 Address
Map 2” for the memory
size details
SRAM
0x2800 0800
0x2800 0000
2
KB
Reserved
16 KB
Reserved
32 KB
Reserved
32 KB
CM7 internal address map for its
Data TCM
0x2000 3FFF
0x2000 0000
CM7 DTCM
0x1780 7FFF
0x1780 0000
Alternate Flash
Supervisory
Used to store manufacture specific
data like flash protection settings, trim
settings, device addresses, serial numbers,
calibration data, etc.
0x1700 7FFF
0x1700 0000
Flash Supervisory
Work flash
Reserved
See “XMC7100 Address
Map 2” for the memory
size details
Work flash used for long
term data retention
0x1400 0000
Reserved
See “XMC7100 Address
Map 2” for the memory
size details
Mainly used for user program code
Code flash
ROM Mirror
0x1000 0000
Reserved
Secured Boot ROM to set user specified
protection levels, trim and configuration
data, code authentication, jump to user mode, etc.
0x0100 FFFF
0x0100 0000
64 KB
Reserved
64 KB
0x0000 FFFF
ROM
0x0000 0000
CM7 internal address map for its instruction TCM.
The address overlaps with portion of ROM region.
0x0000 3FFF
16 KB
CM7 ITCM
0x0000 0000
Figure 4-1
XMC7100 address map 1[18, 19]
Datasheet
22
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7100 address map
XMC7100/XMC7100D-
F100K/F144K/F176K/E272K
XMC7100/XMC7100D-
F100K/F144K
2112
XMC7100-
F100K
1088
4160
0x4000 0000
0x4000 0000
0x4000 0000
Reserved
Reserved
Reserved
0x280B FFFF
SRAM1 256 KB
0x2808 0000
0x2807 FFFF
0x2805 FFFF
SRAM
768 KB
SRAM1 128 KB
SRAM0 256 KB
0x2802 FFFF
0x2804 0000
0x2803 FFFF
SRAM1 64 KB
SRAM0 128 KB
SRAM
384 KB
SRAM0 512 KB
SRAM
192 KB
0x2802 0000
0x2802 FFFF
0x2800 0000
0x2800 0000
0x2800 0000
Reserved
Reserved
Reserved
0x1403 FFFF
64 KB
(128 B Small Sectors)
Work
Flash
0x1403 0000
0x1402 FFFF
0x1401 FFFF
0x1401 FFFF
32 KB
(128 B Small Sectors)
32 KB
(128 B Small Sectors)
Work
Flash
128 KB
Work
Flash
128 KB
256 KB
192 KB
(2 KB Large Sectors)
0x1401 8000
0x1401 7FFF
0x1401 8000
0x1401 7FFF
96 KB
(2 KB Large Sectors)
96 KB
(2 KB Large Sectors)
0x1400 0000
0x1400 0000
0x1400 0000
Reserved
0x1040 FFFF
128 KB
Reserved
(8 KB Small Sectors)
0x103F 0000
0x103E FFFF
Reserved
Code
Flash
4160 KB
0x1020 FFFF
128 KB
(8 KB Small Sectors)
4032 KB
(32 KB Large Sectors)
0x101F 0000
0x101E FFFF
Code
Flash
2112 KB
0x1010 FFFF
128 KB
(8 KB Small Sectors)
1984 KB
(32 KB Large Sectors)
0x100F 0000
0x100E FFFF
Code
Flash
1088 KB
960 KB
(32 KB Large Sectors)
0x1000 0000
0x1000 0000
0x1000 0000
Figure 4-2
XMC7100 address map 2[18]
Notes
18.The size representation is not up to scale.
19.First 2KB of SRAM is reserved, not available for users. User must keep the power of first 32KB block of SRAM0 in enabled or retained
in all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.
Datasheet
23
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Flash base address map
5
Flash base address map
Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions
along with their respective base addresses.
Table 5-1
Code-flash address mapping in single-bank mode
Code-flash Size
Large Sectors Small Sectors
Large Sector Base Address Small Sector Base Address
(KB)
(LS)
(SS)
4160
2112
1088
32 KB × 126
32 KB x 62
32 KB x 30
8 KB × 16
8 KB x 16
8 KB x 16
0x1000 0000
0x1000 0000
0x1000 0000
0x103F 0000
0x101F 0000
0x100F 0000
Table 5-2
Work-flash address mapping in single-bank mode
Work-flash Size
(KB)
Large Sectors Small Sectors Large Sector Base Address Small Sector Base Address
256
128
2 KB × 96
2 KB x 48
128 B × 512
128 B x 256
0x1400 0000
0x1400 0000
0x1403 0000
0x1401 8000
Table 5-3
Code-flas
Code-flash address mapping in dual-bank mode (Mapping A)
Second
Second
Half SS
Base
First Half First Half
First
First
Second
Half LS
Second
Half SS
Half
LS Base
Address
SS Base
Address
h Size (KB) Half LS
Half SS
LS Base
Address
Address
4160
2112
1088
32 KB × 63 8 KB × 8 32 KB × 63 8 KB × 8
32 KB x 31 8 KB x 8 32 KB x 31 8 KB x 8
32 KB x 15 8 KB x 8 32 KB x 15 8 KB x 8
0x1000
0000
0x1000
0000
0x1000
0000
0x101F
8000
0x100F
8000
0x1007
8000
0x1200
0000
0x1200
0000
0x1200
0000
0x121F
8000
0x120F
8000
0x1207
8000
Table 5-4
Code-flas
Code-flash address mapping in dual-bank mode (Mapping B)
First Half First Half
Second
Half
Second
Half SS
Base
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
h Size (KB) Half LS
Half SS
LS Base
Address
Address
4160
2112
1088
32 KB × 63 8 KB × 8 32 KB × 63 8 KB × 8
32 KB x 31 8 KB x 8 32 KB x 31 8 KB x 8
32 KB x 15 8 KB x 8 32 KB x 15 8 KB x 8
0x1200
0000
0x1200
0000
0x1200
0000
0x121F
8000
0x120F
8000
0x1207
8000
0x1000
0000
0x1000
0000
0x1000
0000
0x101F
8000
0x100F
8000
0x1007
8000
Datasheet
24
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Flash base address map
Table 5-5
Work-flas
Work-flash address mapping in dual-bank mode (Mapping A)
Second
Half
Second
Half SS
Base
First Half First Half
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
h Size (KB) Half LS
Half SS
LS Base
Address
Address
256
128
2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1400 0x1401 8000 0x1500 0x1501 8000
0000
0000
2 KB x 24 128 B x 128 2 KB x 24 128 B x 128 0x1400
0000
0x1400
C000
0x1500 0x1500 C000
0000
Table 5-6
Work-flas
Work-flash address mapping in dual-bank mode (Mapping B)
Second
Half
Second
Half SS
Base
First Half First Half
First
First
Second
Half LS
Second
Half SS
LS Base
Address
SS Base
Address
h Size (KB) Half LS
Half SS
LS Base
Address
Address
256
128
2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1500
0000
2 KB x 24 128 B x 128 2 KB x 24 128 B x 128 0x1500
0000
0x1501
8000
0x1500
C000
0x1400
0000
0x1400
0000
0x1401
8000
0x1400
C000
Datasheet
25
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral I/O map
6
Peripheral I/O map
Table 6-1
XMC7100 peripheral I/O map
Instanc-
es
Instance
Size
Section
Description
Base Address
Group Slave
Peripheral interconnect
Peripheral group (0, 1, 2, 3, 4, 5, 6, 8, 9)
Peripheral trigger group
Peripheral 1:1 trigger group
Peripheral interconnect, master interface
PERI Programmable PPU
0x4000 0000
0x4000 4000
0x4000 8000
0x4000 C000
0x4002 0000
0x4002 0000
0x4002 0800
0x4004 0000
0x4010 0000
0x4020 0000
0x4021 0000
0x4021 0000
0x4022 0000
0x4022 0000
0x4022 1000
0x4023 0000
9
11
11
0x40
0x400
0x400
PERI
0
0
PERI_MS
10[20]
700
2
0x40
0x40
0x2000
0
1
PERI Fixed PPU
PERI_PCLK Peripheral Clock Groups
0
1
2
2
0
0
CRYPTO
CPUSS
Cryptography component
CPU subsystem (CPUSS)
Fault structure subsystem
Fault structures
Inter process communication
IPC structures
FAULT
2
1
4
0x100
IPC
8
8
0x20
0x20
2
2
IPC interrupt structures
Protection
PROT
Shared memory protection unit structures 0x4023 2000
16
16
0x40
0x400
2
2
3
4
Memory protection unit structures
Flash controller
0x4023 4000
0x4024 0000
FLASHC
System Resources Sub-System Core
Registers
0x4026 0000
Clock Supervision High Frequency
Clock Supervision Reference Frequency
Clock Supervision Low Frequency
0x4026 1400
0x4026 1710
0x4026 1720
8
1
1
1
2
3
1
0x10
SRSS
2
5
Clock Supervision Internal Low Frequency 0x4026 1730
Clock PLL 400 MHz
Multi Counter WDT
Free Running WDT
SRSS Backup Domain/RTC
Backup Register
P-DMA0 Controller
P-DMA0 channel structures
P-DMA1 Controller
0x4026 1900
0x4026 8000
0x4026 C000
0x4027 0000
0x4027 1000
0x4028 0000
0x4028 8000
0x4029 0000
0x4029 8000
0x402A 0000
0x402A 1000
0x10
0x100
BACKUP
P-DMA
2
2
2
2
6
7
8
9
4
100
58
8
0x04
0x40
0x40
0x100
P-DMA1 channel structures
M-DMA0 Controller
M-DMA0 channels
M-DMA
Note
20.These Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the
device-specific TRM to know more about the configuration of these programmable PPUs.
Datasheet
26
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral I/O map
Table 6-1
Section
XMC7100 peripheral I/O map (continued)
Instanc-
es
Instance
Size
Description
Base Address
Group Slave
eFUSE
HSIOM
GPIO
eFUSE Customer Data (192 bits)
High-Speed I/O Matrix (HSIOM)
GPIO port control/configuration
Programmable I/O configuration
SMARTIO port configuration
Event generator 0 (EVTGEN0)
Event generator 0 comparator structures
Serial Memory Interface 0 (SMIF0)
SMIF0 Devices
Secure Digital High Capacity 0 (SDHC0)
SDHC0 Wrap
SDHC0 Core
Ethernet 0 (ETH0)
CAN0 controller
Message RAM CAN0
CAN1 controller
Message RAM CAN1
Timer/Counter/PWM 0 (TCPWM0)
TCPWM0 Group #0 (16-bit)
TCPWM0 Group #1 (16-bit, Motor control)
TCPWM0 Group #2 (32-bit)
0x402C 0868
0x4030 0000
0x4031 0000
0x4032 0000
0x4032 0C00
0x403F 0000
0x403F 0800
0x4042 0000
0x4042 0800
0x4046 0000
0x4046 0000
0x4046 1000
0x4048 0000
0x4052 0000
0x4053 0000
0x4054 0000
0x4055 0000
0x4038 0000
0x4038 0000
0x4038 8000
0x4039 0000
6
33
33
0x04
0x10
0x80
2
3
3
10
0
1
SMARTIO
EVTGEN
SMIF
3
3
4
2
3
0
5
16
1
0x100
0x20
0x80
SDHC
ETH
4
1
1
4
0x10000
0x200
0x7FFF
0x200
4
5
2
1
TTCANFD
TCPWM
4
5
5
2
3
0x7FFF
63
12
8
0x80
0x80
0x80
Serial Communications Block
SCB
I2S
0x4060 0000
0x4080 0000
11
3
0x10000
0x1000
6
8
0-10
0-2
(SPI/UART/I2C)
I2S Audio Subsystem
Programmable Analog Subsystem (PASS0) 0x4090 0000
SAR0 channel controller
SAR1 channel controller
SAR PASS SAR2 channel controller
SAR0 channel structures
0x4090 0000
0x4090 1000
0x4090 2000
0x4090 0800
0x4090 1800
0x4090 2800
9
0
32
32
8
0x40
0x40
0x40
SAR1 channel structures
SAR2 channel structures
Datasheet
27
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7100 clock diagram
7
XMC7100 clock diagram
IMO
EXT_CLK
ECO
WCO
LS
ILO0
LS
ILO1
LS
ECO
Prescaler
LS
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
FLL
MUX
PLL400#0
MUX
PLL400#1
CLK_
MUX
PLL#2
MUX
PLL#3
MUX
MUX
LS
CLK_ILO0
CLK_
PATH0
CLK_
PATH1
CLK_
PATH3
CLK_
PATH4
CLK_
PATH5
CLK_REF_HF
PATH2
WDT
MUX
CLK_BAK
CLK_LF
RTC
CSV
CLK_ILO0
MCWDT
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
CLK_HF0
CLK_HF1
CLK_HF2
CLK_HF3
CLK_HF4
CLK_HF5
CLK_HF6
CLK_HF7
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CLK_ILO0
CLK_LF
CLK_REF_HF
SDHC
AUDIOSS
I2S External Clock
Ethernet
Tx _CLK,Rx_CLK and REF_CLK to Ethernet PHY
Event Generator
CAN FD
CLK_GR
5
Divider
(1- 256)
TCPWM[0]
CLK_GR
6
Divider
(1- 256)
SCB[*]
SCB[0]
Serial Interface Clock
CLK_GR
9
Divider
(1- 256)
SAR ADC
PCLK_CANFD [x] _CLOCK_CAN[y]
PCLK_TCPWM0 _CLOCKS[x]
PCLK_SCB [x] _CLOCK
Peripheral
Clock Dividers #1
PCLK_PASS_CLOCK_SAR[x]
CLK_FAST_0
CLK_FAST_1
Divider
(1-256)
CM7_0
CM7_1
Divider
(1-256)
SMIF
CLK_MEM
Divider
(1- 256)
ROM/SRAM/FLASH
CPUSS FastI nfrastructure
CLK_SLOW
Divider
(1-256)
CM0+
LEGEND 1:
LEGEND 2:
Active Domain
CPUSSSlow I nfrastructure
DeepSleep Domain
Hibernate Domain
P- DMA / M-DMA
CRYPTO
PERI
CLK_PERI
CLK_GR3
CLK_GR4
CLK_GR8
Divider
(1-256)
Divider
(1- 256)
Relationship of Monitored Clock and
Reference Clock
Monitored Clock
Divider
(1- 256)
SRSS
Reference Clock
CSV
Divider
(1- 256)
EFUSE
LEGEND 3:
One Clock Line
MultipleC lockL ines
IOSS
Peripheral
Clock Dividers #0
CPUSS(DEBUG)
TCK/SWDCLK from a Debugger
CLK_ TRC_DBG
Divider
(1-256)
PCLK_SMARTIO[x] _CLOCK
PCLK_CPUSS_CLOCK_TRACE_IN
Figure 7-1
XMC7100 clock diagram
Datasheet
28
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
XMC7100 CPU start-up sequence
8
XMC7100 CPU start-up sequence
The start-up sequence is described in the following steps:
1. System Reset (@0x0000 0000)
2. CM0+ executes ROM boot (@0x0000 0004)
i. Applies trims
ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory
flash
iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
i. Debug pins are configured based on the SWD/JTAG spec[21]
ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash
(@0x1000 0000)
iii.CM0+ branches to its Reset handler
4. CM0+ starts execution of application
i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
i. Sets clocks for CM7_0 (CLK_HF1) and CM7_1 (CLK_HF2)
ii. Sets CM7_0 (CM7_0_VECTOR_TABLE_BASE @0x4020 0200) and CM7_1 (CM7_1_VECTOR_TABLE_BASE
@0x4020 0600) vector tables to the respective locations, also and mentioned in flash (specified in the linker
definition file)
iii.Enables the power for both the CPU cores CM7_0 and CM7_1
iv.Disables CPU_WAIT to allow accesses from the debugger
v. Releases CM7_0 and/or CM7_1 from reset
vi.Continues execution of CM0+ user application
5. CM7_0 and/or CM7_1 executes directly from either code-flash or SRAM
i. CM7_0/CM7_1 branches to its Reset handler
ii. Continues execution of the user application
Note
21.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer
to Table 11-1 for pin assignments.
Datasheet
29
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
9
Pin assignment
Note: For all TEQFP packages, the thermal pad needs to be connected to VSSD.
VSSD
P0.0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
VSSD
VCCD
VCCD
VCCD
VDDD
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
P0.1
3
P0.2
4
P0.3
5
P2.0
6
P2.1
7
P2.2
8
P2.3
9
P3.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P3.1
VDDD
VSSD
P5.0
100-TEQFP
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
VDDD
VDDIO_1
Figure 9-1
100-TEQFP pin assignment
Datasheet
30
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
VSSD
1
2
3
4
P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/ETH0_TXD_3/PWM_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_7
P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/ETH0_TXD_2/PWM_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_6
P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/ETH0_TXD_1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5
P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/ETH0_TXD_0/PWM_H_2/SCB1_SEL1/SCB3_SEL0/TRACE_DATA_0/ADC[2]_4
P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/ETH0_TX_CLK/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/SCB3_CLK/TRACE_CLOCK/ADC[2]_3
P18.2 PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/ETH0_TX_ER/PWM_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/SCB3_MOSI/ADC[2]_2
P18.1 PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/ETH0_TX_CTL/PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/SCB3_MISO/FAULT_OUT_1/ADC[2]_1
P18.0 PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/ETH0_REF_CLK/PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0
VSSD
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO P0.0
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI P0.1
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/CAN0_1_TX P0.2
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX P0.3
PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/TC_H_4_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/TC_H_5_TR0/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/CAN0_0_RX/TRIG_IN[3] P2.1
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/ETH0_RX_ER/TC_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/TRIG_IN[4] P2.2
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL/TC_H_7_TR0/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3
PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/ETH0_MDIO/PWM_H_6_N/SCB6_RX/SCB6_MISO/CAN0_3_TX/TRIG_DBG[0] P3.0
PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/ETH0_MDC/PWM_H_7_N/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN0_3_RX/TRIG_DBG[1] P3.1
VDDD
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCCD
VCCD
VCCD
VSSD
100-TEQFP
VDDD
PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2 P5.0
P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/AUDIOSS2_TX_SCK/PWM_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_0_RX/ADC[1]_21
P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/AUDIOSS2_MCLK/PWM_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20
P13.7 PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/AUDIOSS1_RX_SDI/PWM_H_5_N/TRIG_IN[23]/ADC[1]_19
P13.6 PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/AUDIOSS1_RX_WS/PWM_H_5/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18
P13.5 PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/AUDIOSS1_RX_SCK/PWM_H_4_N/SCB3_SEL2/ADC[1]_17
P13.4 PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/AUDIOSS1_CLK_I2S_IF/PWM_H_4/SCB3_SEL1/ADC[1]_16
P13.3 PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15
P13.2 PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14
P13.1 PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13
P13.0 PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12
VSSD
PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/SCB9_SEL3 P5.1
PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1 P5.2
PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3
PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/ADC[0]_0 P6.0
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/ADC[0]_1 P6.1
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SDHC_CARD_MECH_WRITE_PROT/SCB4_RTS/SCB4_SCL/SCB4_CLK/CAN0_2_TX/ADC[0]_2 P6.2
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SPIHB_CLK/SDHC_CARD_CMD/SCB4_CTS/SCB4_SEL0/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SPIHB_RWDS/SDHC_CLK_CARD/SCB4_SEL1/ADC[0]_4 P6.4
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SPIHB_SEL0/SDHC_CARD_DETECT_N/SCB4_SEL2/ADC[0]_5 P6.5
VDDD
VDDIO_1
Figure 9-2
100-TEQFP pin assignment with alternate functions
Datasheet
31
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
VSSD
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P2.0
P2.1
P2.2
P2.3
P2.4
P3.0
P3.1
P3.2
P3.3
P3.4
VDDD
VSSD
P4.0
P4.1
P5.0
P5.1
P5.2
P5.3
P5.4
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
VDDD
VDDIO_1
1
108
107
106
105
104
103
102
101
100
99
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.4
P17.3
P17.2
P17.1
P17.0
VSSD
VCCD
VCCD
VCCD
VDDD
P15.3
P15.2
P15.1
P15.0
P14.5
P14.4
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
93
92
91
144-TEQFP
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Figure 9-3
144-TEQFP pin assignment
Datasheet
32
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
108
107
106
105
104
103
102
101
100
99
VDDD
VSSD
1
P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/ETH0_TXD_3/PWM_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_7
P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/ETH0_TXD_2/PWM_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_6
P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/ETH0_TXD_1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5
P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/ETH0_TXD_0/PWM_H_2/SCB1_SEL1/SCB3_SEL0/TRACE_DATA_0/ADC[2]_4
P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/ETH0_TX_CLK/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/SCB3_CLK/TRACE_CLOCK/ADC[2]_3
P18.2 PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/ETH0_TX_ER/PWM_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/SCB3_MOSI/ADC[2]_2
P18.1 PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/ETH0_TX_CTL/PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/SCB3_MISO/FAULT_OUT_1/ADC[2]_1
P18.0 PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/ETH0_REF_CLK/PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0
P17.4 PWM_57/PWM_58_N/TC_57_TR0/TC_58_TR1/PWM_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]
P17.3 PWM_58/PWM_59_N/TC_58_TR0/TC_59_TR1/PWM_H_3/SCB3_RTS/SCB3_SCL/SCB3_CLK/TRIG_IN[26]
P17.2 PWM_59/PWM_60_N/TC_59_TR0/TC_60_TR1/SCB3_TX/SCB3_SDA
2
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO P0.0
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI P0.1
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/CAN0_1_TX P0.2
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX P0.3
PWM_12/PWM_13_N/TC_12_TR0/TC_13_TR1/PWM_H_4/SCB0_SCL/SCB0_MISO/SCB4_CLK P1.0
PWM_11/PWM_12_N/TC_11_TR0/TC_12_TR1/PWM_H_5/SCB0_SDA/SCB0_MOSI/SCB4_SEL0 P1.1
PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/TC_H_4_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/TC_H_5_TR0/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/CAN0_0_RX/TRIG_IN[3] P2.1
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/ETH0_RX_ER/TC_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/TRIG_IN[4] P2.2
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL/TC_H_7_TR0/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3
PWM_3/PWM_4_N/TC_3_TR0/TC_4_TR1/PWM_H_4_N/SCB7_SEL1/TRIG_IN[6] P2.4
PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/ETH0_MDIO/PWM_H_6_N/SCB6_RX/SCB6_MISO/CAN0_3_TX/TRIG_DBG[0] P3.0
PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/ETH0_MDC/PWM_H_7_N/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN0_3_RX/TRIG_DBG[1] P3.1
PWM_M_3/PWM_0_N/TC_M_3_TR0/TC_0_TR1/TC_H_4_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK P3.2
PWM_M_2/PWM_M_3_N/TC_M_2_TR0/TC_M_3_TR1/TC_H_5_TR1/SCB6_CTS/SCB6_SEL0 P3.3
PWM_M_1/PWM_M_2_N/TC_M_1_TR0/TC_M_2_TR1/TC_H_6_TR1/SCB6_SEL1 P3.4
VDDD
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
P17.1 PWM_60/PWM_61_N/TC_60_TR0/TC_61_TR1/SCB3_RX/CAN1_1_RX
95
P17.0 PWM_61/PWM_62_N/TC_61_TR0/TC_62_TR1/CAN1_1_TX
94
VSSD
93
VCCD
92
VCCD
91
VCCD
144-TEQFP
90
VDDD
VSSD
89
P15.3 PWM_59/PWM_58_N/TC_59_TR0/TC_58_TR1/AUDIOSS2_RX_SDI/TC_H_7_TR1/SCB9_CTS/SCB9_SEL0/ADC[1]_31
P15.2 PWM_58/PWM_57_N/TC_58_TR0/TC_57_TR1/AUDIOSS2_RX_WS/TC_H_7_TR0/SCB9_RTS/SCB9_SCL/SCB9_CLK/ADC[1]_30
P15.1 PWM_57/PWM_56_N/TC_57_TR0/TC_56_TR1/AUDIOSS2_RX_SCK/TC_H_6_TR1/SCB9_TX/SCB9_SDA/SCB9_MOSI/CAN1_3_RX/ADC[1]_29
P15.0 PWM_56/PWM_55_N/TC_56_TR0/TC_55_TR1/AUDIOSS2_CLK_I2S_IF/TC_H_6_TR0/SCB9_RX/SCB9_MISO/CAN1_3_TX/ADC[1]_28
P14.5 PWM_53/PWM_52_N/TC_53_TR0/TC_52_TR1/AUDIOSS2_TX_SDO/TC_H_4_TR1/SCB2_SEL2/ADC[1]_25
P14.4 PWM_52/PWM_51_N/TC_52_TR0/TC_51_TR1/AUDIOSS2_TX_WS/TC_H_4_TR0/SCB2_SEL1/ADC[1]_24
P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/AUDIOSS2_TX_SCK/PWM_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_0_RX/ADC[1]_21
P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/AUDIOSS2_MCLK/PWM_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20
P13.7 PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/AUDIOSS1_RX_SDI/PWM_H_5_N/TRIG_IN[23]/ADC[1]_19
P13.6 PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/AUDIOSS1_RX_WS/PWM_H_5/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18
P13.5 PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/AUDIOSS1_RX_SCK/PWM_H_4_N/SCB3_SEL2/ADC[1]_17
P13.4 PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/AUDIOSS1_CLK_I2S_IF/PWM_H_4/SCB3_SEL1/ADC[1]_16
P13.3 PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15
P13.2 PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14
P13.1 PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13
P13.0 PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12
VSSD
PWM_4/PWM_M_0_N/TC_4_TR0/TC_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/SCB5_MISO/TRIG_IN[10] P4.0
PWM_5/PWM_4_N/TC_5_TR0/TC_4_TR1/EXT_MUX[0]_1/SCB5_TX/SCB5_SDA/SCB5_MOSI/TRIG_IN[11] P4.1
PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2 P5.0
88
87
PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/SCB9_SEL3 P5.1
86
PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1 P5.2
85
PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3
84
PWM_13/PWM_12_N/TC_13_TR0/TC_12_TR1 P5.4
83
82
PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/ADC[0]_0 P6.0
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/ADC[0]_1 P6.1
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SDHC_CARD_MECH_WRITE_PROT/SCB4_RTS/SCB4_SCL/SCB4_CLK/CAN0_2_TX/ADC[0]_2 P6.2
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SPIHB_CLK/SDHC_CARD_CMD/SCB4_CTS/SCB4_SEL0/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SPIHB_RWDS/SDHC_CLK_CARD/SCB4_SEL1/ADC[0]_4 P6.4
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SPIHB_SEL0/SDHC_CARD_DETECT_N/SCB4_SEL2/ADC[0]_5 P6.5
PWM_M_3/PWM_2_N/TC_M_3_TR0/TC_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6 P6.6
PWM_3/PWM_M_3_N/TC_3_TR0/TC_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7
81
80
79
78
77
76
75
74
VDDD
73
VDDIO_1
Figure 9-4
144-TEQFP pin assignment with alternate functions
Datasheet
33
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
VSSD
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
VDDD
VSSD
P4.0
P4.1
P4.2
P4.3
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
VDDD
VDDIO_1
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.7
P17.6
P17.5
P17.4
P17.3
P17.2
P17.1
P17.0
P16.3
VSSD
VCCD
VCCD
VCCD
VDDD
P15.3
P15.2
P15.1
P15.0
P14.7
P14.6
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-TEQFP
98
97
96
95
94
93
92
91
90
89
Figure 9-5
176-TEQFP pin assignment
Datasheet
34
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
VSSD
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
2
P18.7 PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/ETH0_TXD_3/PWM_H_3_N/CAN1_2_RX/TRACE_DATA_3/ADC[2]_7
P18.6 PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/ETH0_TXD_2/PWM_H_3/SCB1_SEL3/CAN1_2_TX/TRACE_DATA_2/ADC[2]_6
P18.5 PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/ETH0_TXD_1/PWM_H_2_N/SCB1_SEL2/TRACE_DATA_1/ADC[2]_5
P18.4 PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/ETH0_TXD_0/PWM_H_2/SCB1_SEL1/SCB3_SEL0/TRACE_DATA_0/ADC[2]_4
P18.3 PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/ETH0_TX_CLK/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/SCB3_CLK/TRACE_CLOCK/ADC[2]_3
P18.2 PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/ETH0_TX_ER/PWM_H_1/SCB1_RTS/SCB1_SCL/SCB1_CLK/SCB3_MOSI/ADC[2]_2
P18.1 PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/ETH0_TX_CTL/PWM_H_0_N/SCB1_TX/SCB1_SDA/SCB1_MOSI/SCB3_MISO/FAULT_OUT_1/ADC[2]_1
P18.0 PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/ETH0_REF_CLK/PWM_H_0/SCB1_RX/SCB1_MISO/FAULT_OUT_0/ADC[2]_0
P17.7 PWM_M_5/PWM_M_4_N/TC_M_5_TR0/TC_M_4_TR1
PWM_18/PWM_22_N/TC_18_TR0/TC_22_TR1/SCB0_RX/SCB7_SDA/SCB0_MISO P0.0
PWM_17/PWM_18_N/TC_17_TR0/TC_18_TR1/SCB0_TX/SCB7_SCL/SCB0_MOSI P0.1
PWM_14/PWM_17_N/TC_14_TR0/TC_17_TR1/SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/CAN0_1_TX P0.2
PWM_13/PWM_14_N/TC_13_TR0/TC_14_TR1/SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX P0.3
PWM_12/PWM_13_N/TC_12_TR0/TC_13_TR1/PWM_H_4/SCB0_SCL/SCB0_MISO/SCB4_CLK P1.0
PWM_11/PWM_12_N/TC_11_TR0/TC_12_TR1/PWM_H_5/SCB0_SDA/SCB0_MOSI/SCB4_SEL0 P1.1
PWM_10/PWM_11_N/TC_10_TR0/TC_11_TR1/PWM_H_6/SCB0_CLK/TRIG_IN[0] P1.2
PWM_8/PWM_10_N/TC_8_TR0/TC_10_TR1/PWM_H_7/SCB0_SEL0/TRIG_IN[1] P1.3
PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/TC_H_4_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/TC_H_5_TR0/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/CAN0_0_RX/TRIG_IN[3] P2.1
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/ETH0_RX_ER/TC_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/TRIG_IN[4] P2.2
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL/TC_H_7_TR0/SCB7_CTS/SCB7_SEL0/TRIG_IN[5] P2.3
PWM_3/PWM_4_N/TC_3_TR0/TC_4_TR1/PWM_H_4_N/SCB7_SEL1/TRIG_IN[6] P2.4
PWM_2/PWM_3_N/TC_2_TR0/TC_3_TR1/PWM_H_5_N/SCB7_SEL2/TRIG_IN[7] P2.5
PWM_1/PWM_2_N/TC_1_TR0/TC_2_TR1/ETH0_MDIO/PWM_H_6_N/SCB6_RX/SCB6_MISO/CAN0_3_TX/TRIG_DBG[0] P3.0
PWM_0/PWM_1_N/TC_0_TR0/TC_1_TR1/ETH0_MDC/PWM_H_7_N/SCB6_TX/SCB6_SDA/SCB6_MOSI/CAN0_3_RX/TRIG_DBG[1] P3.1
PWM_M_3/PWM_0_N/TC_M_3_TR0/TC_0_TR1/TC_H_4_TR1/SCB6_RTS/SCB6_SCL/SCB6_CLK P3.2
PWM_M_2/PWM_M_3_N/TC_M_2_TR0/TC_M_3_TR1/TC_H_5_TR1/SCB6_CTS/SCB6_SEL0 P3.3
PWM_M_1/PWM_M_2_N/TC_M_1_TR0/TC_M_2_TR1/TC_H_6_TR1/SCB6_SEL1 P3.4
PWM_M_0/PWM_M_1_N/TC_M_0_TR0/TC_M_1_TR1/TC_H_7_TR1/SCB6_SEL2 P3.5
VDDD
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P17.6 PWM_M_4/PWM_56_N/TC_M_4_TR0/TC_56_TR1/PWM_H_2_N/SCB3_SEL2
P17.5 PWM_56/PWM_57_N/TC_56_TR0/TC_57_TR1/PWM_H_2/SCB3_SEL1
P17.4 PWM_57/PWM_58_N/TC_57_TR0/TC_58_TR1/PWM_H_3_N/SCB3_CTS/SCB3_SEL0/TRIG_IN[27]
P17.3 PWM_58/PWM_59_N/TC_58_TR0/TC_59_TR1/PWM_H_3/SCB3_RTS/SCB3_SCL/SCB3_CLK/TRIG_IN[26]
P17.2 PWM_59/PWM_60_N/TC_59_TR0/TC_60_TR1/SCB3_TX/SCB3_SDA
P17.1 PWM_60/PWM_61_N/TC_60_TR0/TC_61_TR1/SCB3_RX/CAN1_1_RX
P17.0 PWM_61/PWM_62_N/TC_61_TR0/TC_62_TR1/CAN1_1_TX
P16.3 PWM_62/PWM_62_N/TC_62_TR0/TC_62_TR1/PWM_H_1_N
VSSD
VCCD
VCCD
VCCD
176-TEQFP
VSSD
VDDD
PWM_4/PWM_M_0_N/TC_4_TR0/TC_M_0_TR1/EXT_MUX[0]_0/SCB5_RX/SCB5_MISO/TRIG_IN[10] P4.0
PWM_5/PWM_4_N/TC_5_TR0/TC_4_TR1/EXT_MUX[0]_1/SCB5_TX/SCB5_SDA/SCB5_MOSI/TRIG_IN[11] P4.1
PWM_6/PWM_5_N/TC_6_TR0/TC_5_TR1/EXT_MUX[0]_2/SCB5_RTS/SCB5_SCL/SCB5_CLK/TRIG_IN[12] P4.2
PWM_7/PWM_6_N/TC_7_TR0/TC_6_TR1/EXT_MUX[0]_EN/SCB5_CTS/SCB5_SEL0/CAN0_1_TX/TRIG_IN[13] P4.3
PWM_8/PWM_7_N/TC_8_TR0/TC_7_TR1/SCB5_SEL1/CAN0_1_RX P4.4
P15.3 PWM_59/PWM_58_N/TC_59_TR0/TC_58_TR1/AUDIOSS2_RX_SDI/TC_H_7_TR1/SCB9_CTS/SCB9_SEL0/ADC[1]_31
P15.2 PWM_58/PWM_57_N/TC_58_TR0/TC_57_TR1/AUDIOSS2_RX_WS/TC_H_7_TR0/SCB9_RTS/SCB9_SCL/SCB9_CLK/ADC[1]_30
P15.1 PWM_57/PWM_56_N/TC_57_TR0/TC_56_TR1/AUDIOSS2_RX_SCK/TC_H_6_TR1/SCB9_TX/SCB9_SDA/SCB9_MOSI/CAN1_3_RX/ADC[1]_29
P15.0 PWM_56/PWM_55_N/TC_56_TR0/TC_55_TR1/AUDIOSS2_CLK_I2S_IF/TC_H_6_TR0/SCB9_RX/SCB9_MISO/CAN1_3_TX/ADC[1]_28
P14.7 PWM_55/PWM_54_N/TC_55_TR0/TC_54_TR1/TC_H_5_TR1/TRIG_IN[25]/ADC[1]_27
P14.6 PWM_54/PWM_53_N/TC_54_TR0/TC_53_TR1/TC_H_5_TR0/TRIG_IN[24]/ADC[1]_26
P14.5 PWM_53/PWM_52_N/TC_53_TR0/TC_52_TR1/AUDIOSS2_TX_SDO/TC_H_4_TR1/SCB2_SEL2/ADC[1]_25
P14.4 PWM_52/PWM_51_N/TC_52_TR0/TC_51_TR1/AUDIOSS2_TX_WS/TC_H_4_TR0/SCB2_SEL1/ADC[1]_24
P14.3 PWM_51/PWM_50_N/TC_51_TR0/TC_50_TR1/PWM_H_7_N/SCB2_SEL0/SCB2_CTS/ADC[1]_23
P14.2 PWM_50/PWM_49_N/TC_50_TR0/TC_49_TR1/PWM_H_7/SCB2_CLK/SCB2_SCL/SCB2_RTS/ADC[1]_22
P14.1 PWM_49/PWM_48_N/TC_49_TR0/TC_48_TR1/AUDIOSS2_TX_SCK/PWM_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_0_RX/ADC[1]_21
P14.0 PWM_48/PWM_47_N/TC_48_TR0/TC_47_TR1/AUDIOSS2_MCLK/PWM_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20
P13.7 PWM_47/PWM_M_11_N/TC_47_TR0/TC_M_11_TR1/AUDIOSS1_RX_SDI/PWM_H_5_N/TRIG_IN[23]/ADC[1]_19
P13.6 PWM_M_11/PWM_46_N/TC_M_11_TR0/TC_46_TR1/AUDIOSS1_RX_WS/PWM_H_5/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18
P13.5 PWM_46/PWM_M_10_N/TC_46_TR0/TC_M_10_TR1/AUDIOSS1_RX_SCK/PWM_H_4_N/SCB3_SEL2/ADC[1]_17
P13.4 PWM_M_10/PWM_45_N/TC_M_10_TR0/TC_45_TR1/AUDIOSS1_CLK_I2S_IF/PWM_H_4/SCB3_SEL1/ADC[1]_16
P13.3 PWM_45/PWM_M_9_N/TC_45_TR0/TC_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/SCB3_SEL0/ADC[1]_15
P13.2 PWM_M_9/PWM_44_N/TC_M_9_TR0/TC_44_TR1/AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/SCB3_CLK/ADC[1]_14
P13.1 PWM_44/PWM_M_8_N/TC_44_TR0/TC_M_8_TR1/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/SCB3_MOSI/ADC[1]_13
P13.0 PWM_M_8/PWM_43_N/TC_M_8_TR0/TC_43_TR1/AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX/SCB3_MISO/ADC[1]_12
VSSD
PWM_9/PWM_8_N/TC_9_TR0/TC_8_TR1/SCB5_SEL2 P5.0
PWM_10/PWM_9_N/TC_10_TR0/TC_9_TR1/SCB9_SEL3 P5.1
PWM_11/PWM_10_N/TC_11_TR0/TC_10_TR1 P5.2
PWM_12/PWM_11_N/TC_12_TR0/TC_11_TR1 P5.3
PWM_13/PWM_12_N/TC_13_TR0/TC_12_TR1 P5.4
PWM_14/PWM_13_N/TC_14_TR0/TC_13_TR1 P5.5
PWM_M_0/PWM_14_N/TC_M_0_TR0/TC_14_TR1/SCB4_RX/SCB4_MISO/ADC[0]_0 P6.0
PWM_0/PWM_M_0_N/TC_0_TR0/TC_M_0_TR1/SCB4_TX/SCB4_SDA/SCB4_MOSI/ADC[0]_1 P6.1
PWM_M_1/PWM_0_N/TC_M_1_TR0/TC_0_TR1/SDHC_CARD_MECH_WRITE_PROT/SCB4_RTS/SCB4_SCL/SCB4_CLK/CAN0_2_TX/ADC[0]_2 P6.2
PWM_1/PWM_M_1_N/TC_1_TR0/TC_M_1_TR1/SPIHB_CLK/SDHC_CARD_CMD/SCB4_CTS/SCB4_SEL0/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM_M_2/PWM_1_N/TC_M_2_TR0/TC_1_TR1/SPIHB_RWDS/SDHC_CLK_CARD/SCB4_SEL1/ADC[0]_4 P6.4
PWM_2/PWM_M_2_N/TC_2_TR0/TC_M_2_TR1/SPIHB_SEL0/SDHC_CARD_DETECT_N/SCB4_SEL2/ADC[0]_5 P6.5
PWM_M_3/PWM_2_N/TC_M_3_TR0/TC_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6 P6.6
PWM_3/PWM_M_3_N/TC_3_TR0/TC_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7
98
97
96
95
94
93
92
91
VDDD
90
VDDIO_1
89
Figure 9-6
176-TEQFP pin assignment with alternate functions
Datasheet
35
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Pin assignment
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VSSD
P6.5
P6.2
P31.2 P31.0
P5.0
P4.4
P4.0
P29.5 P29.1 P29.0
P3.1
P3.2
P3.3
P3.4
P3.0
P2.4
P2.5
P2.6
P2.0
P2.1
P2.2
P2.3
P1.1
P1.2
P1.3
P1.4
P1.0
P0.2
VSSD
A
B
C
D
E
F
P6.7
P6.6
P6.3
P6.4
P6.0
P6.1
P31.1
P5.4
P5.5
P5.1
P5.2
P5.3
P30.0
P30.1
P30.2
P4.1
P4.2
P4.3
P29.6 P29.2
P29.7 P29.3
VSSD P29.4
P3.5
P3.6
P3.7
P0.3
P0.1
P0.0
P32.0 P32.1
P28.7 P28.6 P28.5
P28.4 P28.3 P28.2
P32.2 P32.3 P32.4 P32.5
P7.0
P7.2
P7.6
P9.0
P9.2
P7.1
P7.3
P7.7
P9.1
P9.3
P32.6 P32.7
P28.1 P28.0 P23.7 P23.6
P23.5 P23.4 P23.3 P22.3
P23.1 P23.0 P22.7 P22.2
P22.6 P22.5 P22.4 P22.1
VDDIO
_1
VDDIO VDDIO
P7.4
P8.0
P8.3
P7.5
P8.1
P8.4
VCCD P30.3 VDDD
P2.7
VCCD
_1
_1
P8.2
VSSD
VSSD P23.2
VDDD
G
H
J
VDDIO
_3
VSSIO
_3
VSSD VSSD VSSD
VSSD VSSD VSSD
DRV_
VSSD P21.7 P21.6
VOUT
VDDIO
_3
VSSIO
_3
VDDD
P24.0 P24.1
XRES_
P24.2 P24.3 P24.4 P25.0
P25.1 P25.2 P25.3 P25.4
P10.0 P25.5 P25.6 P25.7
P10.1 P10.2 P10.3 P10.4
P10.5 P10.6 P10.7 P11.1
VREFH
VDDA
VREFL VSSD VSSD VSSD
VDDD
P20.7 P20.6 P21.5
L
K
L
VSSD
_1
VSSD
_2
VDDD
VSSA VSSD VSSD
P20.5 P20.4 P21.4
P11.0 VSSD
VCCD P14.5
VSSD P20.3
VDDD P16.7 VCCD
P20.2 P20.1 P21.2 P21.3
M
N
P
R
T
VDDIO
_2
VDDIO VDDIO
_2 _2
P19.4 P20.0 P21.0 P21.1
VSSD
_2
P18.7 P19.3 P19.2
P12.0 P12.1 P12.2 P11.2 VSSD P14.4 P14.7 P26.1 P26.5 P27.1 P27.5 P27.7 P16.5 VSSD P18.6 P18.5 P19.1 P19.0
P12.3 P12.4 P12.5 P13.5 P13.7 P14.3 P14.6 P26.0 P26.4 P27.0 P27.4 P27.6 P16.4 P16.6 P17.4 P18.4 P18.3 P18.2
P12.6 P12.7 P13.2 P13.4 P13.6 P14.2 P15.1 P15.3 P26.3 P26.7 P27.3 P16.1 P16.3 P17.1 P17.3 P17.6 P18.1 P18.0
VSSD P13.0 P13.1 P13.3 P14.0 P14.1 P15.0 P15.2 P26.2 P26.6 P27.2 P16.0 P16.2 P17.0 P17.2 P17.5 P17.7 VSSD
U
V
Figure 9-7
272-BGA ball map
Datasheet
36
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
High-speed I/O matrix connections
10
High-speed I/O matrix connections
Table 10-1
HSIOM connections reference
Name
Number
0
Description
HSIOM_SEL_GPIO
HSIOM_SEL_GPIO_DSI
HSIOM_SEL_DSI_DSI
HSIOM_SEL_DSI_GPIO
HSIOM_SEL_AMUXA
HSIOM_SEL_AMUXB
HSIOM_SEL_AMUXA_DSI
HSIOM_SEL_AMUXB_DSI
HSIOM_SEL_ACT_0
HSIOM_SEL_ACT_1
HSIOM_SEL_ACT_2
HSIOM_SEL_ACT_3
HSIOM_SEL_DS_0
HSIOM_SEL_DS_1
HSIOM_SEL_DS_2
HSIOM_SEL_DS_3
HSIOM_SEL_ACT_4
HSIOM_SEL_ACT_5
HSIOM_SEL_ACT_6
HSIOM_SEL_ACT_7
HSIOM_SEL_ACT_8
HSIOM_SEL_ACT_9
HSIOM_SEL_ACT_10
HSIOM_SEL_ACT_11
HSIOM_SEL_ACT_12
HSIOM_SEL_ACT_13
HSIOM_SEL_ACT_14
HSIOM_SEL_ACT_15
HSIOM_SEL_DS_4
HSIOM_SEL_DS_5
HSIOM_SEL_DS_6
HSIOM_SEL_DS_7
GPIO controls 'out'
Reserved
1
2
3
4
5
6
7
8
Active functionality 0
Active functionality 1
Active functionality 2
Active functionality 3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DeepSleep functionality 0
DeepSleep functionality 1
DeepSleep functionality 2
DeepSleep functionality 3
Active functionality 4
Active functionality 5
Active functionality 6
Active functionality 7
Active functionality 8
Active functionality 9
Active functionality 10
Active functionality 11
Active functionality 12
Active functionality 13
Active functionality 14
Active functionality 15
DeepSleep functionality 4
DeepSleep functionality 5
DeepSleep functionality 6
DeepSleep functionality 7
Datasheet
37
002-33896 Rev. *A
2022-10-20
11
Package pin list and alternate functions
Most pins have alternate functionality, as specified in Table 11-1.
Port 11 has the following additional features,
• Ability to pass full-level analog signals to the SAR without clipping to VDDIO in cases where VDDIO < VDDA
• Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M)
• Lower noise, for the most sensitive sensors
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary)
I/O Type
HCon#0[22]
Package
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
176-TEQFP
144-TEQFP
100-TEQFP
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
2
Pin
2
Pin
2
DS #1
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P1.4
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
B18
B17
A17
B16
A16
A15
B15
C15
D15
A14
B14
C14
D14
B13
C13
D13
F12
SCB0_MISO
SCB0_MOSI
SCB0_CLK
SCB0_SEL0
SCB0_MISO
SCB0_MOSI
SCB0_CLK
SCB0_SEL0
3
3
3
4
4
4
SCB0_SCL
SCB0_SDA
SCB0_SCL
SCB0_SDA
5
5
5
6
6
NA
NA
NA
NA
NA
6
7
7
8
NA
NA
NA
8
9
NA
10
11
12
13
14
15
NA
NA
16
17
18
19
SWJ_TRSTN
SCB0_SEL1
SCB0_SEL2
SCB0_SEL3
9
7
10
11
12
NA
NA
NA
13
14
15
16
8
9
NA
NA
NA
NA
10
11
NA
NA
A13
A12
B12
C12
Notes
22.HCon refers to High Speed I/O matrix connection reference as per Table 10-1.
23.DeepSleep ordering (DS #0, DS #1, DS #2) does not have any impact on choosing any alternate functions; the HSIOM module handles the individual alternate function assignment.
24.All port pin functions available in DeepSleep mode are also available in Active mode.
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary) (continued)
I/O Type
HCon#0[22]
Package
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
D12
B11
C11
D11
A8
176-TEQFP
144-TEQFP
Pin
17
100-TEQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
14
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
20
21
NA
NA
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
48
49
50
51
52
53
54
55
DS #1
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
NA
NA
NA
20
B8
21
C8
NA
NA
NA
22
D8
A7
A6
B6
23
15
C6
24
16
D6
C5
25
17
26
NA
NA
18
D5
B4
NA
27
ADC[0]_0
ADC[0]_1
ADC[0]_2
ADC[0]_3
ADC[0]_4
ADC[0]_5
ADC[0]_6
ADC[0]_7
ADC[0]_16
ADC[0]_17
ADC[0]_18
ADC[0]_19
ADC[0]_20
ADC[0]_21
ADC[0]_22
ADC[0]_23
C4
28
19
A3
29
20
B3
30
21
C3
31
22
A2
32
23
B2
33
NA
NA
29
B1
34
E1
40
E2
41
30
F1
42
31
F2
43
32
F3
44
33
F4
45
34
G1
G2
46
NA
NA
47
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary) (continued)
I/O Type
HCon#0[22]
Package
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
G3
G4
G6
H3
H4
H1
H2
J1
176-TEQFP
144-TEQFP
Pin
48
100-TEQFP
Pin
35
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
80
81
82
83
84
85
86
87
90
91
92
DS #1
P8.0
P8.1
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
49
36
ADC[0]_24
ADC[0]_25
ADC[0]_26
ADC[0]_27
ADC[0]_28
ADC[0]_29
ADC[0]_30
ADC[0]_31
P8.2
50
37
P8.3
51
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
38
P8.4
NA
52
P9.0
P9.1
53
P9.2
NA
NA
54
P9.3
J2
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
P13.1
P13.2
M1
N1
N2
N3
N4
P1
55
56
57
58
ADC[1]_0
ADC[1]_1
ADC[1]_2
ADC[1]_3
ADC[0]_M
ADC[1]_M
ADC[2]_M
ADC[1]_4
ADC[1]_5
ADC[1]_6
ADC[1]_7
ADC[1]_8
ADC[1]_9
ADC[1]_10
ADC[1]_11
ADC[1]_12
ADC[1]_13
ADC[1]_14
NA
NA
NA
59
P2
P3
M6
P4
60
39
R4
61
40
R1
66
45
SMARTIO12_0
SMARTIO12_1
SMARTIO12_2
SMARTIO12_3
SMARTIO12_4
SMARTIO12_5
SMARTIO12_6
SMARTIO12_7
SMARTIO13_0
SMARTIO13_1
SMARTIO13_2
R2
67
46
R3
68
47
T1
69
48
T2
70
49
T3
71
NA
NA
NA
52
U1
U2
V2
NA
NA
74
V3
75
53
U3
76
54
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary) (continued)
I/O Type
HCon#0[22]
Package
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
V4
176-TEQFP
144-TEQFP
Pin
77
100-TEQFP
Pin
55
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
93
DS #1
P13.3
P13.4
P13.5
P13.6
P13.7
P14.0
P14.1
P14.2
P14.3
P14.4
P14.5
P14.6
P14.7
P15.0
P15.1
P15.2
P15.3
P16.0
P16.1
P16.2
P16.3
P16.4
P16.5
P16.6
P16.7
P17.0
P17.1
P17.2
P17.3
P17.4
P17.5
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
ADC[1]_15
ADC[1]_16
ADC[1]_17
ADC[1]_18
ADC[1]_19
ADC[1]_20
ADC[1]_21
ADC[1]_22
ADC[1]_23
ADC[1]_24
ADC[1]_25
ADC[1]_26
ADC[1]_27
ADC[1]_28
ADC[1]_29
ADC[1]_30
ADC[1]_31
SMARTIO13_3
SMARTIO13_4
SMARTIO13_5
SMARTIO13_6
SMARTIO13_7
SMARTIO14_0
SMARTIO14_1
SMARTIO14_2
SMARTIO14_3
SMARTIO14_4
SMARTIO14_5
SMARTIO14_6
SMARTIO14_7
SMARTIO15_0
SMARTIO15_1
SMARTIO15_2
SMARTIO15_3
U4
94
78
56
T4
95
79
57
U5
96
80
58
T5
97
81
59
V5
98
82
60
V6
99
83
61
U6
100
101
102
103
104
105
106
107
108
109
NA
NA
NA
84
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
T6
R6
N7
85
T7
NA
NA
86
R7
V7
U7
87
V8
88
U8
89
V12
U12
V13
U13
T13
R13
T14
N12
V14
U14
V15
U15
T15
V16
NA
NA
NA
NA
NA
NA
NA
NA
95
NA
NA
115
NA
NA
NA
NA
116
117
118
119
120
121
SMARTIO17_0
SMARTIO17_1
SMARTIO17_2
SMARTIO17_3
SMARTIO17_4
SMARTIO17_5
96
97
98
99
NA
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary) (continued)
I/O Type
HCon#0[22]
Package
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
176-TEQFP
144-TEQFP
Pin
NA
100-TEQFP
Pin
NA
NA
67
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
122
123
124
125
126
127
128
129
130
131
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
DS #1
P17.6
P17.7
P18.0
P18.1
P18.2
P18.3
P18.4
P18.5
P18.6
P18.7
P19.0
P19.1
P19.2
P19.3
P19.4
P20.0
P20.1
P20.2
P20.3
P20.4
P20.5
P20.6
P20.7
P21.0
P21.1
P21.2
P21.3
P21.4
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
U16
V17
U18
U17
T18
T17
T16
R16
R15
P15
R18
R17
P17
P16
N15
N16
M16
M15
M13
L16
SMARTIO17_6
SMARTIO17_7
NA
100
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
118
NA
ADC[2]_0
ADC[2]_1
ADC[2]_2
ADC[2]_3
ADC[2]_4
ADC[2]_5
ADC[2]_6
ADC[2]_7
68
69
70
71
72
73
74
77
78
79
80
NA
NA
NA
NA
NA
NA
NA
NA
NA
81
L15
NA
K16
K15
N17
N18
M17
M18
L17
NA
NA
119
120
121
122
NA
WCO_IN[25]
WCO_OUT[25]
ECO_IN[25]
82
83
84
ECO_OUT[25]
HIBERNATE_WAKEUP[0][26]
NA
Notes
25.I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled.
26.This I/O has increased leakage to ground when the VDDD supply is below the POR threshold.
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary) (continued)
I/O Type
HCon#0[22]
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
K18
K17
J17
J16
J18
H18
G18
F18
H17
H16
H15
G17
G16
G15
G13
F17
F16
F15
E18
E17
J3
144-TEQFP
Pin
123
128
129
NA
100-TEQFP
Pin
85
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
152
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
NA
DS #1
XRES
P21.5
P21.6
P21.7
DRV_VOUT
P22.1
P22.2
P22.3
P22.4
P22.5
P22.6
P22.7
P23.0
P23.1
P23.2
P23.3
P23.4
P23.5
P23.6
P23.7
P24.0
P24.1
P24.2
P24.3
P24.4
P25.0
P25.1
P25.2
P25.3
P25.4
P25.5
GPIO_STD
GPIO_STD
GPIO_STD
90
NA
NA
91
RTC_CAL
130
131
132
133
134
135
136
NA
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
92
EXT_PS_CTL0
EXT_PS_CTL1
EXT_PS_CTL2
93
94
NA
NA
NA
NA
NA
NA
NA
95
137
138
NA
139
140
141
142
143
NA
96
SWJ_SWO_TDO
SWJ_SWCLK_TCLK
SWJ_SWDIO_TMS
SWJ_SWDOE_TDI
97
98
99
HIBERNATE_WAKEUP[1][26]
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
J4
NA
NA
K1
NA
NA
K2
NA
NA
K3
NA
NA
K4
NA
NA
L1
NA
NA
L2
NA
NA
L3
NA
NA
L4
NA
NA
M2
NA
NA
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary) (continued)
I/O Type
HCon#0[22]
Package
176-TEQFP
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
M3
144-TEQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
100-TEQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
DS #1
P25.6
P25.7
P26.0
P26.1
P26.2
P26.3
P26.4
P26.5
P26.6
P26.7
P27.0
P27.1
P27.2
P27.3
P27.4
P27.5
P27.6
P27.7
P28.0
P28.1
P28.2
P28.3
P28.4
P28.5
P28.6
P28.7
P29.0
P29.1
P29.2
P29.3
P29.4
HSIO_STD
HSIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
M4
T8
R8
V9
U9
T9
R9
V10
U10
T10
R10
V11
U11
T11
R11
T12
R12
E16
E15
D18
D17
D16
C18
C17
C16
A11
A10
B10
C10
D10
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O (Preliminary) (continued)
I/O Type
HCon#0[22]
Package
DeepSleep Mapping
HCon#29
Name
272-BGA
Pin
A9
176-TEQFP
144-TEQFP
Pin
NA
100-TEQFP
Pin
NA
HCon#14
DS #0[23, 24]
HCon#30
DS #2
Analog
SMART I/O
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
DS #1
P29.5
P29.6
P29.7
P30.0
P30.1
P30.2
P30.3
P31.0
P31.1
P31.2
P32.0
P32.1
P32.2
P32.3
P32.4
P32.5
P32.6
P32.7
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
B9
NA
NA
C9
NA
NA
B7
NA
NA
C7
NA
NA
D7
F7
NA
NA
NA
NA
A5
NA
NA
B5
NA
NA
A4
NA
NA
C1
NA
NA
ADC[0]_8
ADC[0]_9
C2
NA
NA
D1
D2
D3
D4
E3
NA
NA
ADC[0]_10
ADC[0]_11
ADC[0]_12
ADC[0]_13
ADC[0]_14
ADC[0]_15
NA
NA
NA
NA
NA
NA
NA
NA
E4
NA
NA
12
Power pin assignments
Table 12-1
Power pin assignments
Package
176-TEQFP
22, 43, 110, 132, 153, 176
Power pin
name
Remarks
272-BGA
144-TEQFP
100-TEQFP
VDDD
VSSD
F8, H13, J13, K13, L13, N11
18, 35, 90, 108, 124, 144
12, 24, 62, 75, 86, 100
Main digital supply
A1, A18, D9, G7, G12, H9, H10, H11, J9, J10, 1, 23, 45, 89, 114, 133, 154, 155 1, 19, 37, 73, 94, 109, 125, 126 1, 13, 26, 51, 66, 76, 87, 88 Main digital ground
J11, J15, K9, K10, K11, M7, M12, R5, R14, V1,
V18, L9, L10
VSSD_1
VSSD_2
VDDIO_1
VDDIO_2
VDDIO_3
VSSIO_3
VCCD[27]
L11
NA
NA
NA
Digital Ground
L18, P18
F9, F10, F11
N8, N9, N10
H6, J6
NA
NA
NA
Noise guard for ECO inputs
44
36
25
I/O supply (except analog I/Os on VDDA)
I/O supply (except analog I/Os on VDDA)
I/O supply for high speed domain#0 (HSIO_STD), P24, P25
HSIO ground
88
72
50
NA
NA
NA
H8, J8
NA
NA
NA
F6, F13, N6, N13
46, 47, 111, 112, 113, 156
38, 39, 91, 92, 93, 127
27, 28, 63, 64, 65, 89
Main regulated supply. Driven by LDO regulator (either
internal LDO or external LDO/PMIC)
VREFH
VREFL
K6
79
65
44
41
43
42
85
91
High-reference voltage for SAR ADCs
Low-reference voltage for SAR ADCs
Main analog supply for SAR ADCs
Main analog ground
K8
76
62
VDDA
L6
78
64
VSSA
L8
77
63
XRES_L
DRV_VOUT
K18
J18
152
160
123
130
Active LOW external reset input
Dedicated external supply control pin
Note
27.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure )
13
Table 13-1
Alternate function pin assignments
Alternate pin functions in Active Mode (Preliminary) [24, 30]
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
HCon#18
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[29]
ACT #0
ACT #1
ACT #2
ACT #3
ACT #5
ACT #6
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P1.4
P2.0
P2.1
P2.2
P2.3
PWM_18
PWM_17
PWM_14
PWM_13
PWM_12
PWM_11
PWM_10
PWM_8
PWM_22_N
TC_18_TR0
TC_22_TR1
SCB0_RX
SCB7_SDA
PWM_18_N
PWM_17_N
PWM_14_N
PWM_13_N
PWM_12_N
PWM_11_N
PWM_10_N
TC_17_TR0
TC_14_TR0
TC_13_TR0
TC_12_TR0
TC_11_TR0
TC_10_TR0
TC_8_TR0
TC_18_TR1
TC_17_TR1
TC_14_TR1
TC_13_TR1
TC_12_TR1
TC_11_TR1
TC_10_TR1
SCB0_TX
SCB0_RTS
SCB0_CTS
SCB7_SCL
SCB4_MISO
SCB4_MOSI
SCB4_CLK
SCB4_SEL0
CAN0_1_TX
CAN0_1_RX
PWM_H_4
PWM_H_5
PWM_H_6
PWM_H_7
TRIG_IN[0]
TRIG_IN[1]
PWM_7
PWM_6
PWM_5
PWM_4
PWM_8_N
PWM_7_N
PWM_6_N
PWM_5_N
TC_7_TR0
TC_6_TR0
TC_5_TR0
TC_4_TR0
TC_8_TR1
TC_7_TR1
TC_6_TR1
TC_5_TR1
TC_H_4_TR0
TC_H_5_TR0
TC_H_6_TR0
TC_H_7_TR0
SCB7_RX
SCB7_TX
SCB7_RTS
SCB7_CTS
SCB7_MISO
SCB7_MOSI
SCB7_CLK
SCB7_SEL0
CAN0_0_TX
CAN0_0_RX
TRIG_IN[2]
TRIG_IN[3]
TRIG_IN[4]
TRIG_IN[5]
SCB7_SDA
SCB7_SCL
ETH0_RX_ER
ETH0_ETH_TSU_TIMER_C-
MP_VAL
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
PWM_3
PWM_2
PWM_4_N
PWM_3_N
TC_3_TR0
TC_2_TR0
TC_4_TR1
TC_3_TR1
PWM_H_4_N
PWM_H_5_N
SCB7_SEL1
SCB7_SEL2
TRIG_IN[6]
TRIG_IN[7]
PWM_1
PWM_0
PWM_2_N
PWM_1_N
PWM_0_N
TC_1_TR0
TC_0_TR0
TC_2_TR1
TC_1_TR1
TC_0_TR1
PWM_H_6_N
PWM_H_7_N
TC_H_4_TR1
SCB6_RX
SCB6_TX
SCB6_RTS
SCB6_CTS
SCB6_MISO
SCB6_MOSI
SCB6_CLK
SCB6_SEL0
CAN0_3_TX
CAN0_3_RX
ETH0_MDIO
ETH0_MDC
TRIG_DBG[0]
TRIG_DBG[1]
SCB6_SDA
SCB6_SCL
PWM_M_3
TC_M_3_TR0
PWM_M_2 PWM_M_3_
N
TC_M_2_TR0 TC_M_3_TR1 TC_H_5_TR1
TC_M_1_TR0 TC_M_2_TR1 TC_H_6_TR1
TC_M_0_TR0 TC_M_1_TR1 TC_H_7_TR1
P3.4
P3.5
PWM_M_1 PWM_M_2_
N
SCB6_SEL1
SCB6_SEL2
SCB8_SEL2
PWM_M_0 PWM_M_1_
N
P3.6
P3.7
CAN1_2_TX
CAN1_2_RX
Notes
28.High Speed I/O matrix connection (HCon) reference as per Table 10-1.
29.Active Mode ordering (ACT #0, ACT #1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments.
30.Refer to Table 13-2 for more information on pin multiplexer abbreviations used.
[24, 30]
Table 13-1
Alternate pin functions in Active Mode (Preliminary) (continued)
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
ACT #1
HCon#10
HCon#11
ACT #3
HCon#16
ACT #4
HCon#17
HCon#18
ACT #6
HCon#19
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
HCon#27
ACT #15
[29]
ACT #0
ACT #2
ACT #5
ACT #7
ACT #9
ACT #14
P4.0
P4.1
P4.2
P4.3
PWM_4
PWM_5
PWM_6
PWM_7
PWM_M_0_
N
TC_4_TR0
TC_M_0_TR1 EXT_MUX[0]_
0
SCB5_RX
SCB5_MISO
TRIG_IN[10]
PWM_4_N
PWM_5_N
PWM_6_N
TC_5_TR0
TC_6_TR0
TC_7_TR0
TC_4_TR1
TC_5_TR1
TC_6_TR1
EXT_MUX[0]_
1
SCB5_TX
SCB5_RTS
SCB5_CTS
SCB5_SDA
SCB5_SCL
SCB5_MOSI
SCB5_CLK
SCB5_SEL0
TRIG_IN[11]
TRIG_IN[12]
TRIG_IN[13]
EXT_MUX[0]_
2
EXT_MUX[0]_
EN
CAN0_1_TX
CAN0_1_RX
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
PWM_8
PWM_9
PWM_7_N
PWM_8_N
PWM_9_N
PWM_10_N
PWM_11_N
PWM_12_N
PWM_13_N
PWM_14_N
TC_8_TR0
TC_9_TR0
TC_7_TR1
TC_8_TR1
SCB5_SEL1
SCB5_SEL2
SCB9_SEL3
PWM_10
PWM_11
PWM_12
PWM_13
PWM_14
PWM_M_0
PWM_0
TC_10_TR0
TC_11_TR0
TC_12_TR0
TC_13_TR0
TC_14_TR0
TC_M_0_TR0
TC_0_TR0
TC_9_TR1
TC_10_TR1
TC_11_TR1
TC_12_TR1
TC_13_TR1
TC_14_TR1
TC_M_0_TR1
SCB4_RX
SCB4_TX
SCB4_MISO
SCB4_MOSI
PWM_M_0_
N
SCB4_SDA
SCB4_SCL
P6.2
P6.3
P6.4
P6.5
PWM_M_1
PWM_1
PWM_0_N
TC_M_1_TR0
TC_1_TR0
TC_0_TR1
TC_M_1_TR1
TC_1_TR1
SCB4_RTS
SCB4_CTS
SCB4_CLK
SCB4_SEL0
SCB4_SEL1
SCB4_SEL2
SCB4_SEL3
CAN0_2_TX
CAN0_2_RX
SDHC_CARD_-
MECH_WRITE_PROT
PWM_M_1_
N
SPIHB_CLK
SDHC_CARD_CMD
CAL_SUP_NZ
PWM_M_2
PWM_2
PWM_1_N
TC_M_2_TR0
TC_2_TR0
SPIHB_RWD
S
SDHC_CLK_CARD
PWM_M_2_
N
TC_M_2_TR1
SPIHB_SEL
0
SDHC_CARD_DE-
TECT_N
P6.6
P6.7
PWM_M_3
PWM_3
PWM_2_N
TC_M_3_TR0
TC_3_TR0
TC_2_TR1
TRIG_IN[8]
TRIG_IN[9]
PWM_M_3_
N
TC_M_3_TR1
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
PWM_M_4
PWM_15
PWM_3_N
TC_M_4_TR0
TC_15_TR0
TC_M_5_TR0
TC_16_TR0
TC_M_6_TR0
TC_17_TR0
TC_3_TR1
TC_M_4_TR1
TC_15_TR1
TC_M_5_TR1
TC_16_TR1
TC_M_6_TR1
SCB5_RX
SCB5_TX
SCB5_RTS
SCB5_CTS
SCB5_MISO
SCB5_MOSI
SCB5_CLK
SCB5_SEL0
SCB5_SEL1
SCB5_SEL2
SPIHB_SEL
1
SDHC_CARD_IF_P-
WR_EN
PWM_M_4_
N
SCB5_SDA
SCB5_SCL
SPIHB_-
DATA0
SDHC_CARD_DAT_3-
TO0_0
PWM_M_5
PWM_16
PWM_15_N
SPIHB_-
DATA1
SDHC_CARD_DAT_3-
TO0_1
PWM_M_5_
N
SPIHB_-
DATA2
SDHC_CARD_DAT_3-
TO0_2
PWM_M_6
PWM_17
PWM_16_N
SPIHB_-
DATA3
SDHC_CARD_DAT_3-
TO0_3
PWM_M_6_
N
SPIHB_-
DATA4
SDHC_CARD_DAT_7-
TO4_0
P7.6
P7.7
PWM_M_7
PWM_18
PWM_17_N
TC_M_7_TR0
TC_18_TR0
TC_17_TR1
TRIG_IN[16]
TRIG_IN[17]
PWM_M_7_
N
TC_M_7_TR1
[24, 30]
Table 13-1
Alternate pin functions in Active Mode (Preliminary) (continued)
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[29]
ACT #0
ACT #1
ACT #2
ACT #3
ACT #9
P8.0
P8.1
P8.2
PWM_19
PWM_20
PWM_21
PWM_18_N
TC_19_TR0
TC_18_TR1
CAN0_0_TX
SPIHB_-
DATA5
SDHC_CARD_DAT_7-
TO4_1
PWM_19_N
PWM_20_N
TC_20_TR0
TC_21_TR0
TC_19_TR1
TC_20_TR1
CAN0_0_RX
SPIHB_-
DATA6
SDHC_CARD_DAT_7-
TO4_2
TRIG_IN[14]
TRIG_IN[15]
SPIHB_-
DATA7
SDHC_CARD_DAT_7-
TO4_3
P8.3
P8.4
PWM_22
PWM_23
PWM_24
PWM_25
PWM_26
PWM_27
PWM_28
PWM_29
PWM_30
PWM_31
PWM_32
PWM_33
PWM_21_N
PWM_22_N
PWM_23_N
PWM_24_N
PWM_25_N
PWM_26_N
PWM_27_N
PWM_28_N
PWM_29_N
PWM_30_N
PWM_31_N
PWM_32_N
PWM_33_N
PWM_34_N
PWM_62_N
PWM_61_N
PWM_60_N
TC_22_TR0
TC_23_TR0
TC_24_TR0
TC_25_TR0
TC_26_TR0
TC_27_TR0
TC_28_TR0
TC_29_TR0
TC_30_TR0
TC_31_TR0
TC_32_TR0
TC_33_TR0
TC_21_TR1
TC_22_TR1
TC_23_TR1
TC_24_TR1
TC_25_TR1
TC_26_TR1
TC_27_TR1
TC_28_TR1
TC_29_TR1
TC_30_TR1
TC_31_TR1
TC_32_TR1
TC_33_TR1
TC_34_TR1
TC_62_TR1
TC_61_TR1
TC_60_TR1
TRIG_DBG[0]
TRIG_DBG[1]
P9.0
P9.1
P9.2
P9.3
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P12.0
P12.1
SCB4_RX
SCB4_TX
SCB4_RTS
SCB4_CTS
SCB4_MISO
SCB4_MOSI
SCB4_CLK
SCB4_SEL0
SCB4_SEL1
SCB4_SEL2
TRIG_IN[18]
TRIG_IN[19]
SCB4_SDA
SCB4_SCL
PWM_34
PWM_35
PWM_61
PWM_60
PWM_59
PWM_36
PWM_37
TC_35_TR0
TC_61_TR0
TC_60_TR0
TC_59_TR0
TC_36_TR0
TC_37_TR0
AUDIOSS0_MCLK
AUDIOSS0_TX_SCK
AUDIOSS0_TX_WS
AUDIOSS0_TX_SDO
SCB8_RX
SCB8_TX
SCB8_MISO
SCB8_MOSI
CAN0_2_TX
CAN0_2_RX
PWM_35_N
TRIG_IN[20]
TRIG_IN[21]
PWM_36_N
PWM_37_N
PWM_38_N
PWM_39_N
PWM_40_N
TC_36_TR1
TC_37_TR1
TC_38_TR1
TC_39_TR1
TC_40_TR1
SCB8_SDA
SCB8_SCL
AUDIOSS0_-
CLK_I2S_IF
P12.2
P12.3
P12.4
P12.5
PWM_38
PWM_39
PWM_40
PWM_41
TC_38_TR0
TC_39_TR0
TC_40_TR0
TC_41_TR0
EXT_MUX[1]_
EN
SCB8_RTS
SCB8_CTS
SCB8_CLK
SCB8_SEL0
SCB8_SEL1
AUDIOSS0_RX_SCK
AUDIOSS0_RX_WS
AUDIOSS0_RX_SDI
EXT_MUX[1]_
0
EXT_MUX[1]_
1
CAN1_1_TX
CAN1_1_RX
EXT_MUX[1]_
2
P12.6
P12.7
PWM_42
PWM_43
PWM_41_N
PWM_42_N
PWM_43_N
TC_42_TR0
TC_43_TR0
TC_M_8_TR0
TC_41_TR1
TC_42_TR1
TC_43_TR1
P13.0 PWM_M_8
EXT_MUX[2]_
0
SCB3_RX
SCB3_MISO
AUDIOSS1_MCLK
[24, 30]
Table 13-1
Alternate pin functions in Active Mode (Preliminary) (continued)
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
ACT #1
HCon#10
HCon#11
ACT #3
HCon#16
ACT #4
HCon#17
HCon#18
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
HCon#26
ACT #14
HCon#27
ACT #15
[29]
ACT #0
PWM_44
ACT #2
ACT #5
ACT #6
ACT #9
ACT #13
P13.1
PWM_M_8_
N
TC_44_TR0
TC_M_8_TR1 EXT_MUX[2]_
1
SCB3_TX
SCB3_SDA
SCB3_MOSI
AUDIOSS1_TX_SCK
P13.2 PWM_M_9
P13.3 PWM_45
PWM_44_N
TC_M_9_TR0
TC_45_TR0
TC_44_TR1
EXT_MUX[2]_
2
SCB3_RTS
SCB3_CTS
SCB3_SCL
SCB3_CLK
SCB3_SEL0
SCB3_SEL1
SCB3_SEL2
SCB3_SEL3
AUDIOSS1_TX_WS
AUDIOSS1_TX_SDO
PWM_M_9_
N
TC_M_9_TR1 EXT_MUX[2]_
EN
P13.4 PWM_M_10 PWM_45_N TC_M_10_TR0
TC_45_TR1
PWM_H_4
AUDIOSS1_-
CLK_I2S_IF
P13.5
PWM_46
PWM_M_10
_N
TC_46_TR0
TC_M_10_TR PWM_H_4_N
1
AUDIOSS1_RX_SCK
P13.6 PWM_M_11 PWM_46_N TC_M_11_TR0
TC_46_TR1
PWM_H_5
AUDIOSS1_RX_WS
AUDIOSS1_RX_SDI
TRIG_IN[22]
TRIG_IN[23]
P13.7
PWM_47
PWM_M_11
_N
TC_47_TR0
TC_M_11_TR PWM_H_5_N
1
P14.0
P14.1
P14.2
P14.3
P14.4
P14.5
P14.6
P14.7
P15.0
PWM_48
PWM_49
PWM_50
PWM_51
PWM_52
PWM_53
PWM_54
PWM_55
PWM_56
PWM_47_N
PWM_48_N
PWM_49_N
PWM_50_N
PWM_51_N
PWM_52_N
PWM_53_N
PWM_54_N
PWM_55_N
TC_48_TR0
TC_49_TR0
TC_50_TR0
TC_51_TR0
TC_52_TR0
TC_53_TR0
TC_54_TR0
TC_55_TR0
TC_56_TR0
TC_47_TR1
TC_48_TR1
TC_49_TR1
TC_50_TR1
TC_51_TR1
TC_52_TR1
TC_53_TR1
TC_54_TR1
TC_55_TR1
PWM_H_6
PWM_H_6_N
PWM_H_7
SCB2_MISO
SCB2_MOSI
SCB2_CLK
SCB2_SEL0
SCB2_SEL1
SCB2_SEL2
SCB2_RX
SCB2_TX
SCB2_RTS
SCB2_CTS
CAN1_0_TX
CAN1_0_RX
AUDIOSS2_MCLK
SCB2_SDA
SCB2_SCL
AUDIOSS2_TX_SCK
PWM_H_7_N
TC_H_4_TR0
TC_H_4_TR1
TC_H_5_TR0
TC_H_5_TR1
TC_H_6_TR0
AUDIOSS2_TX_WS
AUDIOSS2_TX_SDO
TRIG_IN[24]
TRIG_IN[25]
SCB9_RX
SCB9_MISO
CAN1_3_TX
CAN1_3_RX
AUDIOSS2_-
CLK_I2S_IF
P15.1
P15.2
P15.3
P16.0
P16.1
P16.2
P16.3
P16.4
P16.5
P16.6
P16.7
P17.0
P17.1
PWM_57
PWM_58
PWM_59
PWM_60
PWM_61
PWM_62
PWM_62
PWM_56_N
PWM_57_N
PWM_58_N
PWM_59_N
PWM_60_N
PWM_61_N
PWM_62_N
TC_57_TR0
TC_58_TR0
TC_59_TR0
TC_60_TR0
TC_61_TR0
TC_62_TR0
TC_62_TR0
TC_56_TR1
TC_57_TR1
TC_58_TR1
TC_59_TR1
TC_60_TR1
TC_61_TR1
TC_62_TR1
TC_H_6_TR1
TC_H_7_TR0
TC_H_7_TR1
PWM_H_0
SCB9_TX
SCB9_RTS
SCB9_CTS
SCB9_SDA
SCB9_SCL
SCB9_MOSI
SCB9_CLK
SCB9_SEL0
SCB9_SEL1
SCB9_SEL2
SCB9_SEL3
AUDIOSS2_RX_SCK
AUDIOSS2_RX_WS
AUDIOSS2_RX_SDI
PWM_H_0_N
PWM_H_1
PWM_H_1_N
PWM_61
PWM_60
PWM_62_N
PWM_61_N
TC_61_TR0
TC_60_TR0
TC_62_TR1
TC_61_TR1
CAN1_1_TX
CAN1_1_RX
SCB3_RX
[24, 30]
Table 13-1
Alternate pin functions in Active Mode (Preliminary) (continued)
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
HCon#18
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[29]
ACT #0
ACT #1
ACT #2
ACT #3
ACT #5
ACT #6
ACT #9
P17.2
P17.3
P17.4
P17.5
PWM_59
PWM_58
PWM_57
PWM_56
PWM_60_N
TC_59_TR0
TC_60_TR1
SCB3_TX
SCB3_SDA
PWM_59_N
PWM_58_N
PWM_57_N
PWM_56_N
TC_58_TR0
TC_57_TR0
TC_56_TR0
TC_M_4_TR0
TC_59_TR1
TC_58_TR1
TC_57_TR1
TC_56_TR1
PWM_H_3
PWM_H_3_N
PWM_H_2
SCB3_RTS
SCB3_CTS
SCB3_SCL
SCB3_CLK
SCB3_SEL0
SCB3_SEL1
SCB3_SEL2
TRIG_IN[26]
TRIG_IN[27]
P17.6 PWM_M_4
PWM_H_2_N
P17.7 PWM_M_5 PWM_M_4_
N
TC_M_5_TR0 TC_M_4_TR1
TC_M_6_TR0 TC_M_5_TR1
P18.0 PWM_M_6 PWM_M_5_
N
PWM_H_0
SCB1_RX
SCB1_TX
SCB1_RTS
SCB1_CTS
SCB1_MISO
SCB1_MOSI
SCB1_CLK
ETH0_REF_CLK
ETH0_TX_CTL
ETH0_TX_ER
FAULT_OUT_0
FAULT_OUT_1
P18.1 PWM_M_7 PWM_M_6_
N
TC_M_7_TR0 TC_M_6_TR1 PWM_H_0_N
SCB1_SDA
SCB1_SCL
SCB3_MISO
SCB3_MOSI
P18.2
PWM_55
PWM_M_7_
N
TC_55_TR0
TC_M_7_TR1
PWM_H_1
P18.3
P18.4
P18.5
P18.6
P18.7
PWM_54
PWM_53
PWM_52
PWM_51
PWM_50
PWM_55_N
PWM_54_N
PWM_53_N
PWM_52_N
PWM_51_N
PWM_50_N
TC_54_TR0
TC_53_TR0
TC_52_TR0
TC_51_TR0
TC_50_TR0
TC_M_3_TR0
TC_26_TR0
TC_55_TR1
TC_54_TR1
TC_53_TR1
TC_52_TR1
TC_51_TR1
TC_50_TR1
PWM_H_1_N
PWM_H_2
SCB1_SEL0
SCB1_SEL1
SCB1_SEL2
SCB1_SEL3
SCB3_CLK
SCB3_SEL0
ETH0_TX_CLK
ETH0_TXD_0
ETH0_TXD_1
ETH0_TXD_2
ETH0_TXD_3
ETH0_RXD_0
ETH0_RXD_1
TRACE_CLOCK
TRACE_DATA_0
TRACE_DATA_1
TRACE_DATA_2
TRACE_DATA_3
FAULT_OUT_2
FAULT_OUT_3
PWM_H_2_N
PWM_H_3
CAN1_2_TX
CAN1_2_RX
CAN1_3_TX
CAN1_3_RX
PWM_H_3_N
TC_H_0_TR0
P19.0 PWM_M_3
SCB2_MISO
SCB2_MOSI
SCB2_RX
SCB2_TX
P19.1
PWM_26
PWM_M_3_
N
TC_M_3_TR1 TC_H_0_TR1
SCB2_SDA
SCB2_SCL
P19.2
P19.3
P19.4
P20.0
P20.1
P20.2
P20.3
P20.4
P20.5
P20.6
P20.7
P21.0
P21.1
P21.2
PWM_27
PWM_28
PWM_29
PWM_30
PWM_49
PWM_48
PWM_47
PWM_46
PWM_45
PWM_44
PWM_43
PWM_42
PWM_41
PWM_40
PWM_26_N
PWM_27_N
PWM_28_N
PWM_29_N
PWM_30_N
PWM_49_N
PWM_48_N
PWM_47_N
PWM_46_N
PWM_45_N
PWM_44_N
PWM_43_N
PWM_42_N
PWM_41_N
TC_27_TR0
TC_28_TR0
TC_29_TR0
TC_30_TR0
TC_49_TR0
TC_48_TR0
TC_47_TR0
TC_46_TR0
TC_45_TR0
TC_44_TR0
TC_43_TR0
TC_42_TR0
TC_41_TR0
TC_40_TR0
TC_26_TR1
TC_27_TR1
TC_28_TR1
TC_29_TR1
TC_30_TR1
TC_49_TR1
TC_48_TR1
TC_47_TR1
TC_46_TR1
TC_45_TR1
TC_44_TR1
TC_43_TR1
TC_42_TR1
TC_41_TR1
TC_H_1_TR0
TC_H_1_TR1
TC_H_2_TR0
TC_H_2_TR1
TC_H_3_TR0
TC_H_3_TR1
SCB2_CLK
SCB2_SEL0
SCB2_SEL1
SCB2_SEL2
SCB2_RTS
SCB2_CTS
ETH0_RXD_2
ETH0_RXD_3
TRIG_IN[28]
TRIG_IN[29]
SCB1_RX
SCB1_TX
SCB1_RTS
SCB1_CTS
SCB1_MISO
SCB1_MOSI
SCB1_CLK
SCB1_SEL0
SCB1_SEL1
SCB1_SEL2
CAN1_2_TX
CAN1_2_RX
SCB1_SDA
SCB1_SCL
EXT_CLK
TRIG_DBG[1]
[24, 30]
Table 13-1
Alternate pin functions in Active Mode (Preliminary) (continued)
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[29]
ACT #0
ACT #1
ACT #2
ACT #3
ACT #9
P21.3
P21.4
P21.5
P21.6
P21.7
P22.1
P22.2
P22.3
P22.4
P22.5
P22.6
P22.7
PWM_39
PWM_38
PWM_37
PWM_36
PWM_35
PWM_33
PWM_32
PWM_31
PWM_30
PWM_29
PWM_28
PWM_27
PWM_40_N
TC_39_TR0
TC_40_TR1
PWM_39_N
PWM_38_N
PWM_37_N
PWM_36_N
PWM_34_N
PWM_33_N
PWM_32_N
PWM_31_N
PWM_30_N
PWM_29_N
PWM_28_N
PWM_27_N
TC_38_TR0
TC_37_TR0
TC_36_TR0
TC_35_TR0
TC_33_TR0
TC_32_TR0
TC_31_TR0
TC_30_TR0
TC_29_TR0
TC_28_TR0
TC_27_TR0
TC_M_8_TR0
TC_39_TR1
TC_38_TR1
TC_37_TR1
TC_36_TR1
TC_34_TR1
TC_33_TR1
TC_32_TR1
TC_31_TR1
TC_30_TR1
TC_29_TR1
TC_28_TR1
TC_27_TR1
CAN1_1_TX
PWM_34 PWM_35_N
ETH0_RX_CTL
TRACE_DATA_0
SCB6_RX
SCB6_TX
SCB6_RTS
SCB6_CTS
SCB6_MISO
SCB6_MOSI
SCB6_CLK
SCB6_SEL0
SCB6_SEL1
SCB6_SEL2
CAL_SUP_NZ
TRACE_DATA_1
TRACE_DATA_2
TRACE_DATA_3
TRACE_CLOCK
SCB6_SDA
SCB6_SCL
CAN1_1_RX
P23.0 PWM_M_8
SCB7_RX
SCB7_TX
SCB7_MISO
SCB7_MOSI
CAN1_0_TX
CAN1_0_RX
FAULT_OUT_0
FAULT_OUT_1
P23.1 PWM_M_9 PWM_M_8_
N
TC_M_9_TR0 TC_M_8_TR1
SCB7_SDA
SCB7_SCL
P23.2 PWM_M_10 PWM_M_9_ TC_M_10_TR0 TC_M_9_TR1
N
SCB7_RTS
SCB7_CTS
SCB2_MISO
SCB7_CLK
SCB7_SEL0
SCB7_SEL1
SCB7_SEL2
FAULT_OUT_2
FAULT_OUT_3
TRIG_DBG[0]
P23.3 PWM_M_11 PWM_M_10 TC_M_11_TR0 TC_M_10_TR
ETH0_RX_CLK
TRIG_IN[30]
TRIG_IN[31]
_N
1
P23.4
PWM_25
PWM_M_11
_N
TC_25_TR0
TC_M_11_TR
1
P23.5
P23.6
P23.7
P24.0
PWM_24
PWM_23
PWM_22
PWM_25_N
PWM_24_N
PWM_23_N
TC_24_TR0
TC_23_TR0
TC_22_TR0
TC_25_TR1
TC_24_TR1
TC_23_TR1
SCB2_MOSI
SCB2_CLK
SCB2_SEL0
EXT_CLK
EXT_CLK
CAL_SUP_NZ
SDHC_CARD_DE-
TECT_N
P24.1
P24.2
P24.3
P24.4
P25.0
P25.1
P25.2
SPIHB_CLK
SDHC_CARD_-
MECH_WRITE_PROT
SPIHB_RWD
S
SDHC_CLK_CARD
SDHC_CARD_CMD
SPIHB_SEL
0
SPIHB_SEL
1
SDHC_CARD_IF_P-
WR_EN
SPIHB_-
DATA0
SDHC_CARD_DAT_3-
TO0_0
SPIHB_-
DATA1
SDHC_CARD_DAT_3-
TO0_1
SPIHB_-
DATA2
SDHC_CARD_DAT_3-
TO0_2
[24, 30]
Table 13-1
Alternate pin functions in Active Mode (Preliminary) (continued)
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
ACT #1
HCon#10
ACT #2
HCon#11
ACT #3
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[29]
ACT #0
P25.3
P25.4
P25.5
P25.6
P25.7
SPIHB_-
DATA3
SDHC_CARD_DAT_3-
TO0_3
SPIHB_-
DATA4
SDHC_CARD_DAT_7-
TO4_0
SPIHB_-
DATA5
SDHC_CARD_DAT_7-
TO4_1
SPIHB_-
DATA6
SDHC_CARD_DAT_7-
TO4_2
SPIHB_-
DATA7
SDHC_CARD_DAT_7-
TO4_3
P26.0
P26.1
P26.2
P26.3
P26.4
P26.5
P26.6
P26.7
P27.0
P27.1
P27.2
P27.3
P27.4
P27.5
P27.6
P27.7
P28.0
P28.1
P28.2
P28.3
P28.4
P28.5
P28.6
P28.7
P29.0
SCB10_RX
SCB10_TX
SCB10_MISO
SCB10_SDA SCB10_MOSI
SCB10_RTS SCB10_SCL SCB10_CLK
SCB10_CTS
SCB10_SEL0
SCB10_SEL1
SCB10_SEL2
SCB10_SEL3
[24, 30]
Table 13-1
Alternate pin functions in Active Mode (Preliminary) (continued)
Active Mapping
Port
Pin
[28]
HCon#8
HCon#9
ACT #1
HCon#10
ACT #2
HCon#11
ACT #3
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[29]
ACT #0
ACT #9
P29.1
P29.2
P29.3
P29.4
P29.5
P29.6
P29.7
P30.0
P30.1
P30.2
P30.3
P31.0
P31.1
P31.2
P32.0
P32.1
P32.2
P32.3
P32.4
P32.5
P32.6
P32.7
SCB9_RTS
SCB9_CTS
SCB9_CLK
SCB9_SEL0
SCB9_SEL1
SCB9_SEL2
CAN1_3_TX
CAN1_3_RX
SCB10_RX
SCB10_TX
SCB10_MISO
SCB10_SDA SCB10_MOSI
SCB10_RTS SCB10_SCL SCB10_CLK
SCB10_CTS
SCB10_SEL0
SCB10_SEL1
SCB10_SEL2
SCB10_SEL3
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Alternate function pin assignments
13.1
Pin function description
Table 13-2
Pin function description
Sl.
Pin
Module
TCPWM
Description
No.
1
2
PWMx_y
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR line out, x-TCPWM block,
y-counter number
PWMx_y_N
TCPWM
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR complementary line out (N),
x-TCPWM block, y-counter number
3
4
PWMx_M_y
TCPWM
TCPWM
TCPWM 16-bit PWM with motor control line out, x-TCPWM block, y-counter number
PWMx_M_y_N
TCPWM 16-bit PWM with motor control complementary line out (N), x-TCPWM block,
y-counter number
5
6
PWMx_H_y
TCPWM
TCPWM
TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM block, y-counter number
PWMx_H_y_N
TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary line out (N), x-TCPWM block,
y-counter number
7
8
9
TCx_y_TRz
TCPWM
TCPWM
TCPWM
TCPWM 16-bit dedicated counter input triggers, x-TCPWM block, y-counter number, z-trigger
number
TCx_M_y_TRz
TCx_H_y_TRz
TCPWM 16-bit dedicated counter input triggers with motor control, x-TCPWM block,
y-counter number, z-trigger number
TCPWM 32-bit dedicated counter input triggers, x-TCPWM block, y-counter number, z-trigger
number
10 SCBx_RX
SCB
UART Receive, x-SCB block
11 SCBx_TX
SCB
UART Transmit, x-SCB block
12 SCBx_RTS
13 SCBx_CTS
14 SCBx_SDA
15 SCBx_SCL
16 SCBx_MISO
17 SCBx_MOSI
18 SCBx_CLK
19 SCBx_SELy
23 CANx_y_TX
24 CANx_y_RX
25 SPIHB_CLK
26 SPIHB_RWDS
27 SPIHB_SELx
28 SPIHB_DATAx
29 ETHx_RX_ER
SCB
UART Request to Send (Handshake), x-SCB block
UART Clear to Send (Handshake), x-SCB block
I2C Data line, x-SCB block
SCB
SCB
SCB
I2C Clock line, x-SCB block
SCB
SPI Master Input Slave Output, x-SCB block
SPI Master Output Slave Input, x-SCB block
SPI Serial Clock, x-SCB block
SCB
SCB
SCB
SPI Slave Select, x-SCB block, y-select line
CAN Transmit line, x-CAN block, y-channel number
CAN Receive line, x-CAN block, y-channel number
SMIF interface clock
CANFD
CANFD
SMIF
SMIF
SMIF
SMIF
Ethernet
Ethernet
SMIF (SPI/HYPERBUS™) read-write-data-strobe line
SMIF (SPI/HYPERBUS™) memory select line, x-select line number
SMIF (SPI/HYPERBUS™) memory data read and write line, x-0 to 7 data lines
Ethernet receive error indication line, x-ETH module number
Ethernet time stamp unit timer compare indication line, x-ETH module number
30 ETHx_ETH_TSU_TIMER_C-
MP_VAL
31 ETHx_MDIO
32 ETHx_MDC
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
SDHC
Ethernet management data input/output (MDIO) interface to PHY, x-ETH module number
Ethernet management data clock (MDC) line, x-ETH module number
Ethernet reference clock line, x-ETH module number
33 ETHx_REF_CLK
34 ETHx_TX_CTL
35 ETHx_TX_ER
36 ETHx_TX_CLK
37 ETHx_TXD_y
38 ETHx_RXD_y
39 ETHx_RX_CTL
40 ETHx_RX_CLK
Ethernet transmit control line, x-ETH module number
Ethernet transmit error indication line, x-ETH module number
Ethernet transmit clock line, x-ETH module number
Ethernet transmit data line, , x-ETH module number, y-transmit channel number
Ethernet receive data line, , x-ETH module number, y-receive channel number
Ethernet receive control line, x-ETH module number
Ethernet receive clock line, x-ETH module number
41 SDHC_CARD_-
MECH_WRITE_PROT
SDHC mechanical write protect
42 SDHC_CARD_CMD
SDHC
SDHC command line
Datasheet
55
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Alternate function pin assignments
Table 13-2
Pin function description (continued)
Sl.
Pin
Module
SDHC
Description
No.
43 SDHC_CLK_CARD
44 SDHC_CARD_DETECT_N
45 SDHC_CARD_IF_PWR_EN
46 SDHC_CARD_DAT_3TO0_x
47 SDHC_CARD_DAT_7TO4_x
48 AUDIOSSx_MCLK
49 AUDIOSSx_TX_SCK
50 AUDIOSSx_TX_WS
51 AUDIOSSx_TX_SDO
52 AUDIOSSx_CLK_I2S_IF
53 AUDIOSSx_RX_SCK
54 AUDIOSSx_RX_WS
55 AUDIOSSx_RX_SDI
56 CAL_SUP_NZ
SDHC clock line
SDHC
SDHC interface insertion or removal detection line
SDHC interface power cycle line
SDHC
SDHC
SDHC lower 4-bits of the data
SDHC
SDHC upper 4-bits of the data in 8-bit mode
AudioSS master clock out, x-AudioSS block
I2S serial clock for transmitter, x-AudioSS block
I2S word select for transmitter, x-AudioSS block
I2S serial data output for transmitter, x-AudioSS block
I2S clock supplied from external I2S bus host, x-AudioSS block
I2S serial clock for receiver, x-AudioSS block
I2S word select for receiver, x-AudioSS block
I2S serial data input for receiver, x-AudioSS block
ETAS Calibration support line
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
System
SRSS
57 FAULT_OUT_x
Fault output line x-0 to 3
58 TRACE_DATA_x
SRSS
Trace dataout line x-0 to 3
59 TRACE_CLOCK
SRSS
Trace clock line
60 RTC_CAL
SRSS RTC
SRSS
RTC calibration clock input
61 SWJ_TRSTN
JTAG Test reset line (Active low)
62 SWJ_SWO_TDO
SRSS
JTAG Test data output/SWO (Serial Wire Output)
JTAG Test clock/SWD clock (Serial Wire Clock)
JTAG Test mode select/SWD data (Serial Wire Data Input/Output)
JTAG Test data input
63 SWJ_SWCLK_TCLK
64 SWJ_SWDIO_TMS
65 SWJ_SWDOE_TDI
66 HIBERNATE_WAKEUP[x]
67 EXT_CLK
SRSS
SRSS
SRSS
SRSS
Hibernate wakeup line x-0 to 1
SRSS
External clock input
68 EXT_PS_CTL0
SRSS REGHC
REGHC control line, Transistor mode/Positive terminal of the current sense resistor, PMIC
mode/Power good input from PMIC
69 EXT_PS_CTL1
70 EXT_PS_CTL2
SRSS REGHC
SRSS REGHC
REGHC control line, Transistor mode/Negative terminal of the current sense resistor, PMIC
mode/Enable output for PMIC
REGHC control line, Transistor mode/unused, PMIC mode/Reset threshold adjustment for
some PMICs
71 ADC[x]_y
PASS SAR
PASS SAR
PASS SAR
PASS SAR
SAR, channel, x-SAR number, y-channel number
SAR motor control input, x-SAR number
72 ADC[x]_M
73 EXT_MUX[x]_y
74 EXT_MUX[x]_EN
External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
External SAR MUX enable line
Datasheet
56
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
14
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary)
Interrupt
0
Source
Power Mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Description
CPUSS Inter Process Communication Interrupt #0
CPUSS Inter Process Communication Interrupt #1
CPUSS Inter Process Communication Interrupt #2
CPUSS Inter Process Communication Interrupt #3
CPUSS Inter Process Communication Interrupt #4
CPUSS Inter Process Communication Interrupt #5
CPUSS Inter Process Communication Interrupt #6
CPUSS Inter Process Communication Interrupt #7
CPUSS Fault Structure #0 Interrupt
CPUSS Fault Structure #1 Interrupt
CPUSS Fault Structure #2 Interrupt
CPUSS Fault Structure #3 Interrupt
BACKUP domain Interrupt
cpuss_interrupts_ipc_0_IRQn
1
cpuss_interrupts_ipc_1_IRQn
2
cpuss_interrupts_ipc_2_IRQn
3
cpuss_interrupts_ipc_3_IRQn
4
cpuss_interrupts_ipc_4_IRQn
5
cpuss_interrupts_ipc_5_IRQn
6
cpuss_interrupts_ipc_6_IRQn
7
cpuss_interrupts_ipc_7_IRQn
8
cpuss_interrupts_fault_0_IRQn
cpuss_interrupts_fault_1_IRQn
cpuss_interrupts_fault_2_IRQn
cpuss_interrupts_fault_3_IRQn
srss_interrupt_backup_IRQn
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
srss_interrupt_mcwdt_0_IRQn
srss_interrupt_mcwdt_1_IRQn
srss_interrupt_mcwdt_2_IRQn
srss_interrupt_wdt_IRQn
Multi Counter Watchdog Timer #0 interrupt
Multi Counter Watchdog Timer #1 interrupt
Multi Counter Watchdog Timer #2 interrupt
Hardware Watchdog Timer interrupt
Other combined Interrupts for SRSS (LVD, CLKCAL)
SCB0 interrupt (DeepSleep capable)
Event gen DeepSleep domain interrupt
I/O Supply (VDDIO, VDDA, VDDD) state change Interrupt
Consolidated Interrupt for GPIO_STD and GPIO_ENH, All Ports
GPIO_ENH Port #0 Interrupt
srss_interrupt_IRQn
scb_0_interrupt_IRQn
evtgen_0_interrupt_dpslp_IRQn
ioss_interrupt_vdd_IRQn
ioss_interrupt_gpio_dpslp_IRQn
ioss_interrupts_gpio_dpslp_0_IRQn
ioss_interrupts_gpio_dpslp_1_IRQn
ioss_interrupts_gpio_dpslp_2_IRQn
ioss_interrupts_gpio_dpslp_3_IRQn
ioss_interrupts_gpio_dpslp_4_IRQn
ioss_interrupts_gpio_dpslp_5_IRQn
ioss_interrupts_gpio_dpslp_6_IRQn
ioss_interrupts_gpio_dpslp_7_IRQn
ioss_interrupts_gpio_dpslp_8_IRQn
ioss_interrupts_gpio_dpslp_9_IRQn
ioss_interrupts_gpio_dpslp_10_IRQn
ioss_interrupts_gpio_dpslp_11_IRQn
ioss_interrupts_gpio_dpslp_12_IRQn
ioss_interrupts_gpio_dpslp_13_IRQn
ioss_interrupts_gpio_dpslp_14_IRQn
ioss_interrupts_gpio_dpslp_15_IRQn
ioss_interrupts_gpio_dpslp_16_IRQn
ioss_interrupts_gpio_dpslp_17_IRQn
ioss_interrupts_gpio_dpslp_18_IRQn
ioss_interrupts_gpio_dpslp_19_IRQn
ioss_interrupts_gpio_dpslp_20_IRQn
GPIO_STD Port #1 Interrupt
GPIO_STD Port #2 Interrupt
GPIO_STD Port #3 Interrupt
GPIO_STD Port #4 Interrupt
GPIO_STD Port #5 Interrupt
GPIO_STD Port #6 Interrupt
GPIO_STD Port #7 Interrupt
GPIO_STD Port #8 Interrupt
GPIO_STD Port #9 Interrupt
GPIO_STD Port #10 Interrupt
GPIO_STD Port #11 Interrupt
GPIO_STD Port #12 Interrupt
GPIO_STD Port #13 Interrupt
GPIO_STD Port #14 Interrupt
GPIO_STD Port #15 Interrupt
GPIO_STD Port #16 Interrupt
GPIO_STD Port #17 Interrupt
GPIO_STD Port #18 Interrupt
GPIO_STD Port #19 Interrupt
GPIO_STD Port #20 Interrupt
Datasheet
57
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
43
Source
Power Mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Active
Description
ioss_interrupts_gpio_dpslp_21_IRQn
ioss_interrupts_gpio_dpslp_22_IRQn
ioss_interrupts_gpio_dpslp_23_IRQn
ioss_interrupts_gpio_dpslp_28_IRQn
ioss_interrupts_gpio_dpslp_29_IRQn
ioss_interrupts_gpio_dpslp_30_IRQn
ioss_interrupts_gpio_dpslp_31_IRQn
ioss_interrupts_gpio_dpslp_32_IRQn
ioss_interrupts_gpio_act_IRQn
ioss_interrupts_gpio_act_24_IRQn
ioss_interrupts_gpio_act_25_IRQn
ioss_interrupts_gpio_act_26_IRQn
ioss_interrupts_gpio_act_27_IRQn
cpuss_interrupt_crypto_IRQn
cpuss_interrupt_fm_IRQn
GPIO_STD Port #21 Interrupt
GPIO_STD Port #22 Interrupt
GPIO_STD Port #23 Interrupt
GPIO_STD Port #28 Interrupt
GPIO_STD Port #29 Interrupt
GPIO_STD Port #30 Interrupt
GPIO_STD Port #31 Interrupt
GPIO_STD Port #32 Interrupt
44
45
46
47
48
49
50
51
Consolidated Interrupt for HSIO_STD, All Ports
HSIO_STD Port #24 Interrupt
HSIO_STD Port #25 Interrupt
HSIO_STD Port #26 Interrupt
HSIO_STD Port #27 Interrupt
CRYPTO Accelerator Interrupt
Flash Macro Interrupt
52
Active
53
Active
54
Active
55
Active
56
Active
57
Active
58
cpuss_interrupts_cm7_0_fp_IRQn
cpuss_interrupts_cm7_1_fp_IRQn
cpuss_interrupts_cm0_cti_0_IRQn
cpuss_interrupts_cm0_cti_1_IRQn
cpuss_interrupts_cm7_0_cti_0_IRQn
cpuss_interrupts_cm7_0_cti_1_IRQn
cpuss_interrupts_cm7_1_cti_0_IRQn
cpuss_interrupts_cm7_1_cti_1_IRQn
evtgen_0_interrupt_IRQn
Active
CM7_0 Floating Point operation fault
CM7_1 Floating Point operation fault
CM0+ CTI (Cross Trigger Interface) #0
CM0+ CTI #1
59
Active
60
Active
61
Active
62
Active
CM7_0 CTI #0
63
Active
CM7_0 CTI #1
64
Active
CM7_1 CTI #0
65
Active
CM7_1 CTI #1
66
Active
Event gen Active domain Interrupt
CAN0, Consolidated Interrupt #0 for all four channels
CAN0, Consolidated Interrupt #1 for all four channels
CAN1, Consolidated Interrupt #0 for all four channels
CAN1, Consolidated Interrupt #1 for all four channels
CAN0, Interrupt #0, Channel #0
CAN0, Interrupt #0, Channel #1
CAN0, Interrupt #0, Channel #2
CAN0, Interrupt #0, Channel #3
CAN0, Interrupt #1, Channel #0
CAN0, Interrupt #1, Channel #1
CAN0, Interrupt #1, Channel #2
CAN0, Interrupt #1, Channel #3
CAN1, Interrupt #0, Channel #0
CAN1, Interrupt #0, Channel #1
CAN1, Interrupt #0, Channel #2
CAN1, Interrupt #0, Channel #3
CAN1, Interrupt #1, Channel #0
CAN1, Interrupt #1, Channel #1
CAN1, Interrupt #1, Channel #2
CAN1, Interrupt #1, Channel #3
Reserved for future use
67
canfd_0_interrupt0_IRQn
Active
68
canfd_0_interrupt1_IRQn
Active
69
canfd_1_interrupt0_IRQn
Active
70
canfd_1_interrupt1_IRQn
Active
71
canfd_0_interrupts0_0_IRQn
canfd_0_interrupts0_1_IRQn
canfd_0_interrupts0_2_IRQn
canfd_0_interrupts0_3_IRQn
canfd_0_interrupts1_0_IRQn
canfd_0_interrupts1_1_IRQn
canfd_0_interrupts1_2_IRQn
canfd_0_interrupts1_3_IRQn
canfd_1_interrupts0_0_IRQn
canfd_1_interrupts0_1_IRQn
canfd_1_interrupts0_2_IRQn
canfd_1_interrupts0_3_IRQn
canfd_1_interrupts1_0_IRQn
canfd_1_interrupts1_1_IRQn
canfd_1_interrupts1_2_IRQn
canfd_1_interrupts1_3_IRQn
Reserved
Active
72
Active
73
Active
74
Active
75
Active
76
Active
77
Active
78
Active
79
Active
80
Active
81
Active
82
Active
83
Active
84
Active
85
Active
86
Active
87 - 102
Active
Datasheet
58
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Source
scb_1_interrupt_IRQn
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
SCB1 Interrupt
SCB2 Interrupt
SCB3 Interrupt
SCB4 Interrupt
SCB5 Interrupt
SCB6 Interrupt
SCB7 Interrupt
SCB8 Interrupt
SCB9 Interrupt
SCB10 Interrupt
scb_2_interrupt_IRQn
scb_3_interrupt_IRQn
scb_4_interrupt_IRQn
scb_5_interrupt_IRQn
scb_6_interrupt_IRQn
scb_7_interrupt_IRQn
scb_8_interrupt_IRQn
scb_9_interrupt_IRQn
scb_10_interrupt_IRQn
pass_0_interrupts_sar_0_IRQn
pass_0_interrupts_sar_1_IRQn
pass_0_interrupts_sar_2_IRQn
pass_0_interrupts_sar_3_IRQn
pass_0_interrupts_sar_4_IRQn
pass_0_interrupts_sar_5_IRQn
pass_0_interrupts_sar_6_IRQn
pass_0_interrupts_sar_7_IRQn
pass_0_interrupts_sar_8_IRQn
pass_0_interrupts_sar_9_IRQn
pass_0_interrupts_sar_10_IRQn
pass_0_interrupts_sar_11_IRQn
pass_0_interrupts_sar_12_IRQn
pass_0_interrupts_sar_13_IRQn
pass_0_interrupts_sar_14_IRQn
pass_0_interrupts_sar_15_IRQn
pass_0_interrupts_sar_16_IRQn
pass_0_interrupts_sar_17_IRQn
pass_0_interrupts_sar_18_IRQn
pass_0_interrupts_sar_19_IRQn
pass_0_interrupts_sar_20_IRQn
pass_0_interrupts_sar_21_IRQn
pass_0_interrupts_sar_22_IRQn
pass_0_interrupts_sar_23_IRQn
pass_0_interrupts_sar_24_IRQn
pass_0_interrupts_sar_25_IRQn
pass_0_interrupts_sar_26_IRQn
pass_0_interrupts_sar_27_IRQn
pass_0_interrupts_sar_28_IRQn
pass_0_interrupts_sar_29_IRQn
pass_0_interrupts_sar_30_IRQn
pass_0_interrupts_sar_31_IRQn
pass_0_interrupts_sar_32_IRQn
pass_0_interrupts_sar_33_IRQn
pass_0_interrupts_sar_34_IRQn
SAR0, Logical Channel #0 Interrupt
SAR0, Logical Channel #1 Interrupt
SAR0, Logical Channel #2 Interrupt
SAR0, Logical Channel #3 Interrupt
SAR0, Logical Channel #4 Interrupt
SAR0, Logical Channel #5 Interrupt
SAR0, Logical Channel #6 Interrupt
SAR0, Logical Channel #7 Interrupt
SAR0, Logical Channel #8 Interrupt
SAR0, Logical Channel #9 Interrupt
SAR0, Logical Channel #10 Interrupt
SAR0, Logical Channel #11 Interrupt
SAR0, Logical Channel #12 Interrupt
SAR0, Logical Channel #13 Interrupt
SAR0, Logical Channel #14 Interrupt
SAR0, Logical Channel #15 Interrupt
SAR0, Logical Channel #16 Interrupt
SAR0, Logical Channel #17 Interrupt
SAR0, Logical Channel #18 Interrupt
SAR0, Logical Channel #19 Interrupt
SAR0, Logical Channel #20 Interrupt
SAR0, Logical Channel #21 Interrupt
SAR0, Logical Channel #22 Interrupt
SAR0, Logical Channel #23 Interrupt
SAR0, Logical Channel #24 Interrupt
SAR0, Logical Channel #25 Interrupt
SAR0, Logical Channel #26 Interrupt
SAR0, Logical Channel #27 Interrupt
SAR0, Logical Channel #28 Interrupt
SAR0, Logical Channel #29 Interrupt
SAR0, Logical Channel #30 Interrupt
SAR0, Logical Channel #31 Interrupt
SAR1, Logical Channel #0 Interrupt
SAR1, Logical Channel #1 Interrupt
SAR1, Logical Channel #2 Interrupt
Datasheet
59
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
SAR1, Logical Channel #3 Interrupt
pass_0_interrupts_sar_35_IRQn
pass_0_interrupts_sar_36_IRQn
pass_0_interrupts_sar_37_IRQn
pass_0_interrupts_sar_38_IRQn
pass_0_interrupts_sar_39_IRQn
pass_0_interrupts_sar_40_IRQn
pass_0_interrupts_sar_41_IRQn
pass_0_interrupts_sar_42_IRQn
pass_0_interrupts_sar_43_IRQn
pass_0_interrupts_sar_44_IRQn
pass_0_interrupts_sar_45_IRQn
pass_0_interrupts_sar_46_IRQn
pass_0_interrupts_sar_47_IRQn
pass_0_interrupts_sar_48_IRQn
pass_0_interrupts_sar_49_IRQn
pass_0_interrupts_sar_50_IRQn
pass_0_interrupts_sar_51_IRQn
pass_0_interrupts_sar_52_IRQn
pass_0_interrupts_sar_53_IRQn
pass_0_interrupts_sar_54_IRQn
pass_0_interrupts_sar_55_IRQn
pass_0_interrupts_sar_56_IRQn
pass_0_interrupts_sar_57_IRQn
pass_0_interrupts_sar_58_IRQn
pass_0_interrupts_sar_59_IRQn
pass_0_interrupts_sar_60_IRQn
pass_0_interrupts_sar_61_IRQn
pass_0_interrupts_sar_62_IRQn
pass_0_interrupts_sar_63_IRQn
pass_0_interrupts_sar_64_IRQn
pass_0_interrupts_sar_65_IRQn
pass_0_interrupts_sar_66_IRQn
pass_0_interrupts_sar_67_IRQn
pass_0_interrupts_sar_68_IRQn
pass_0_interrupts_sar_69_IRQn
pass_0_interrupts_sar_70_IRQn
pass_0_interrupts_sar_71_IRQn
cpuss_interrupts_dmac_0_IRQn
cpuss_interrupts_dmac_1_IRQn
cpuss_interrupts_dmac_2_IRQn
cpuss_interrupts_dmac_3_IRQn
cpuss_interrupts_dmac_4_IRQn
cpuss_interrupts_dmac_5_IRQn
cpuss_interrupts_dmac_6_IRQn
cpuss_interrupts_dmac_7_IRQn
SAR1, Logical Channel #4 Interrupt
SAR1, Logical Channel #5 Interrupt
SAR1, Logical Channel #6 Interrupt
SAR1, Logical Channel #7 Interrupt
SAR1, Logical Channel #8 Interrupt
SAR1, Logical Channel #9 Interrupt
SAR1, Logical Channel #10 Interrupt
SAR1, Logical Channel #11 Interrupt
SAR1, Logical Channel #12 Interrupt
SAR1, Logical Channel #13 Interrupt
SAR1, Logical Channel #14 Interrupt
SAR1, Logical Channel #15 Interrupt
SAR1, Logical Channel #16 Interrupt
SAR1, Logical Channel #17 Interrupt
SAR1, Logical Channel #18 Interrupt
SAR1, Logical Channel #19 Interrupt
SAR1, Logical Channel #20 Interrupt
SAR1, Logical Channel #21 Interrupt
SAR1, Logical Channel #22 Interrupt
SAR1, Logical Channel #23 Interrupt
SAR1, Logical Channel #24 Interrupt
SAR1, Logical Channel #25 Interrupt
SAR1, Logical Channel #26 Interrupt
SAR1, Logical Channel #27 Interrupt
SAR1, Logical Channel #28 Interrupt
SAR1, Logical Channel #29 Interrupt
SAR1, Logical Channel #30 Interrupt
SAR1, Logical Channel #31 Interrupt
SAR2, Logical Channel #0 Interrupt
SAR2, Logical Channel #1 Interrupt
SAR2, Logical Channel #2 Interrupt
SAR2, Logical Channel #3 Interrupt
SAR2, Logical Channel #4 Interrupt
SAR2, Logical Channel #5 Interrupt
SAR2, Logical Channel #6 Interrupt
SAR2, Logical Channel #7 Interrupt
CPUSS M-DMA0, Channel #0 Interrupt
CPUSS M-DMA0, Channel #1 Interrupt
CPUSS M-DMA0, Channel #2 Interrupt
CPUSS M-DMA0, Channel #3 Interrupt
CPUSS M-DMA0, Channel #4 Interrupt
CPUSS M-DMA0, Channel #5 Interrupt
CPUSS M-DMA0, Channel #6 Interrupt
CPUSS M-DMA0, Channel #7 Interrupt
Datasheet
60
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA0, Channel #0 Interrupt
cpuss_interrupts_dw0_0_IRQn
cpuss_interrupts_dw0_1_IRQn
cpuss_interrupts_dw0_2_IRQn
cpuss_interrupts_dw0_3_IRQn
cpuss_interrupts_dw0_4_IRQn
cpuss_interrupts_dw0_5_IRQn
cpuss_interrupts_dw0_6_IRQn
cpuss_interrupts_dw0_7_IRQn
cpuss_interrupts_dw0_8_IRQn
cpuss_interrupts_dw0_9_IRQn
cpuss_interrupts_dw0_10_IRQn
cpuss_interrupts_dw0_11_IRQn
cpuss_interrupts_dw0_12_IRQn
cpuss_interrupts_dw0_13_IRQn
cpuss_interrupts_dw0_14_IRQn
cpuss_interrupts_dw0_15_IRQn
cpuss_interrupts_dw0_16_IRQn
cpuss_interrupts_dw0_17_IRQn
cpuss_interrupts_dw0_18_IRQn
cpuss_interrupts_dw0_19_IRQn
cpuss_interrupts_dw0_20_IRQn
cpuss_interrupts_dw0_21_IRQn
cpuss_interrupts_dw0_22_IRQn
cpuss_interrupts_dw0_23_IRQn
cpuss_interrupts_dw0_24_IRQn
cpuss_interrupts_dw0_25_IRQn
cpuss_interrupts_dw0_26_IRQn
cpuss_interrupts_dw0_27_IRQn
cpuss_interrupts_dw0_28_IRQn
cpuss_interrupts_dw0_29_IRQn
cpuss_interrupts_dw0_30_IRQn
cpuss_interrupts_dw0_31_IRQn
cpuss_interrupts_dw0_32_IRQn
cpuss_interrupts_dw0_33_IRQn
cpuss_interrupts_dw0_34_IRQn
cpuss_interrupts_dw0_35_IRQn
cpuss_interrupts_dw0_36_IRQn
cpuss_interrupts_dw0_37_IRQn
cpuss_interrupts_dw0_38_IRQn
cpuss_interrupts_dw0_39_IRQn
cpuss_interrupts_dw0_40_IRQn
cpuss_interrupts_dw0_41_IRQn
cpuss_interrupts_dw0_42_IRQn
cpuss_interrupts_dw0_43_IRQn
cpuss_interrupts_dw0_44_IRQn
CPUSS P-DMA0, Channel #1 Interrupt
CPUSS P-DMA0, Channel #2 Interrupt
CPUSS P-DMA0, Channel #3 Interrupt
CPUSS P-DMA0, Channel #4 Interrupt
CPUSS P-DMA0, Channel #5 Interrupt
CPUSS P-DMA0, Channel #6 Interrupt
CPUSS P-DMA0, Channel #7 Interrupt
CPUSS P-DMA0, Channel #8 Interrupt
CPUSS P-DMA0, Channel #9 Interrupt
CPUSS P-DMA0, Channel #10 Interrupt
CPUSS P-DMA0, Channel #11 Interrupt
CPUSS P-DMA0, Channel #12 Interrupt
CPUSS P-DMA0, Channel #13 Interrupt
CPUSS P-DMA0, Channel #14 Interrupt
CPUSS P-DMA0, Channel #15 Interrupt
CPUSS P-DMA0, Channel #16 Interrupt
CPUSS P-DMA0, Channel #17 Interrupt
CPUSS P-DMA0, Channel #18 Interrupt
CPUSS P-DMA0, Channel #19 Interrupt
CPUSS P-DMA0, Channel #20 Interrupt
CPUSS P-DMA0, Channel #21 Interrupt
CPUSS P-DMA0, Channel #22 Interrupt
CPUSS P-DMA0, Channel #23 Interrupt
CPUSS P-DMA0, Channel #24 Interrupt
CPUSS P-DMA0, Channel #25 Interrupt
CPUSS P-DMA0, Channel #26 Interrupt
CPUSS P-DMA0, Channel #27 Interrupt
CPUSS P-DMA0, Channel #28 Interrupt
CPUSS P-DMA0, Channel #29 Interrupt
CPUSS P-DMA0, Channel #30 Interrupt
CPUSS P-DMA0, Channel #31 Interrupt
CPUSS P-DMA0, Channel #32 Interrupt
CPUSS P-DMA0, Channel #33 Interrupt
CPUSS P-DMA0, Channel #34 Interrupt
CPUSS P-DMA0, Channel #35 Interrupt
CPUSS P-DMA0, Channel #36 Interrupt
CPUSS P-DMA0, Channel #37 Interrupt
CPUSS P-DMA0, Channel #38 Interrupt
CPUSS P-DMA0, Channel #39 Interrupt
CPUSS P-DMA0, Channel #40 Interrupt
CPUSS P-DMA0, Channel #41 Interrupt
CPUSS P-DMA0, Channel #42 Interrupt
CPUSS P-DMA0, Channel #43 Interrupt
CPUSS P-DMA0, Channel #44 Interrupt
Datasheet
61
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA0, Channel #45 Interrupt
CPUSS P-DMA0, Channel #46 Interrupt
CPUSS P-DMA0, Channel #47 Interrupt
CPUSS P-DMA0, Channel #48 Interrupt
CPUSS P-DMA0, Channel #49 Interrupt
CPUSS P-DMA0, Channel #50 Interrupt
CPUSS P-DMA0, Channel #51 Interrupt
CPUSS P-DMA0, Channel #52 Interrupt
CPUSS P-DMA0, Channel #53 Interrupt
CPUSS P-DMA0, Channel #54 Interrupt
CPUSS P-DMA0, Channel #55 Interrupt
CPUSS P-DMA0, Channel #56 Interrupt
CPUSS P-DMA0, Channel #57 Interrupt
CPUSS P-DMA0, Channel #58 Interrupt
CPUSS P-DMA0, Channel #59 Interrupt
CPUSS P-DMA0, Channel #60 Interrupt
CPUSS P-DMA0, Channel #61 Interrupt
CPUSS P-DMA0, Channel #62 Interrupt
CPUSS P-DMA0, Channel #63 Interrupt
CPUSS P-DMA0, Channel #64 Interrupt
CPUSS P-DMA0, Channel #65 Interrupt
CPUSS P-DMA0, Channel #66 Interrupt
CPUSS P-DMA0, Channel #67 Interrupt
CPUSS P-DMA0, Channel #68 Interrupt
CPUSS P-DMA0, Channel #69 Interrupt
CPUSS P-DMA0, Channel #70 Interrupt
CPUSS P-DMA0, Channel #71 Interrupt
CPUSS P-DMA0, Channel #72 Interrupt
CPUSS P-DMA0, Channel #73 Interrupt
CPUSS P-DMA0, Channel #74 Interrupt
CPUSS P-DMA0, Channel #75 Interrupt
CPUSS P-DMA0, Channel #76 Interrupt
CPUSS P-DMA0, Channel #77 Interrupt
CPUSS P-DMA0, Channel #78 Interrupt
CPUSS P-DMA0, Channel #79 Interrupt
CPUSS P-DMA0, Channel #80 Interrupt
CPUSS P-DMA0, Channel #81 Interrupt
CPUSS P-DMA0, Channel #82 Interrupt
CPUSS P-DMA0, Channel #83 Interrupt
CPUSS P-DMA0, Channel #84 Interrupt
CPUSS P-DMA0, Channel #85 Interrupt
CPUSS P-DMA0, Channel #86 Interrupt
CPUSS P-DMA0, Channel #87 Interrupt
CPUSS P-DMA0, Channel #88 Interrupt
CPUSS P-DMA0, Channel #89 Interrupt
cpuss_interrupts_dw0_45_IRQn
cpuss_interrupts_dw0_46_IRQn
cpuss_interrupts_dw0_47_IRQn
cpuss_interrupts_dw0_48_IRQn
cpuss_interrupts_dw0_49_IRQn
cpuss_interrupts_dw0_50_IRQn
cpuss_interrupts_dw0_51_IRQn
cpuss_interrupts_dw0_52_IRQn
cpuss_interrupts_dw0_53_IRQn
cpuss_interrupts_dw0_54_IRQn
cpuss_interrupts_dw0_55_IRQn
cpuss_interrupts_dw0_56_IRQn
cpuss_interrupts_dw0_57_IRQn
cpuss_interrupts_dw0_58_IRQn
cpuss_interrupts_dw0_59_IRQn
cpuss_interrupts_dw0_60_IRQn
cpuss_interrupts_dw0_61_IRQn
cpuss_interrupts_dw0_62_IRQn
cpuss_interrupts_dw0_63_IRQn
cpuss_interrupts_dw0_64_IRQn
cpuss_interrupts_dw0_65_IRQn
cpuss_interrupts_dw0_66_IRQn
cpuss_interrupts_dw0_67_IRQn
cpuss_interrupts_dw0_68_IRQn
cpuss_interrupts_dw0_69_IRQn
cpuss_interrupts_dw0_70_IRQn
cpuss_interrupts_dw0_71_IRQn
cpuss_interrupts_dw0_72_IRQn
cpuss_interrupts_dw0_73_IRQn
cpuss_interrupts_dw0_74_IRQn
cpuss_interrupts_dw0_75_IRQn
cpuss_interrupts_dw0_76_IRQn
cpuss_interrupts_dw0_77_IRQn
cpuss_interrupts_dw0_78_IRQn
cpuss_interrupts_dw0_79_IRQn
cpuss_interrupts_dw0_80_IRQn
cpuss_interrupts_dw0_81_IRQn
cpuss_interrupts_dw0_82_IRQn
cpuss_interrupts_dw0_83_IRQn
cpuss_interrupts_dw0_84_IRQn
cpuss_interrupts_dw0_85_IRQn
cpuss_interrupts_dw0_86_IRQn
cpuss_interrupts_dw0_87_IRQn
cpuss_interrupts_dw0_88_IRQn
cpuss_interrupts_dw0_89_IRQn
Datasheet
62
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA0, Channel #90 Interrupt
CPUSS P-DMA0, Channel #91 Interrupt
CPUSS P-DMA0, Channel #92 Interrupt
CPUSS P-DMA0, Channel #93 Interrupt
CPUSS P-DMA0, Channel #94 Interrupt
CPUSS P-DMA0, Channel #95 Interrupt
CPUSS P-DMA0, Channel #96 Interrupt
CPUSS P-DMA0, Channel #97 Interrupt
CPUSS P-DMA0, Channel #98 Interrupt
CPUSS P-DMA0, Channel #99 Interrupt
CPUSS P-DMA1, Channel #0 Interrupt
CPUSS P-DMA1, Channel #1 Interrupt
CPUSS P-DMA1, Channel #2 Interrupt
CPUSS P-DMA1, Channel #3 Interrupt
CPUSS P-DMA1, Channel #4 Interrupt
CPUSS P-DMA1, Channel #5 Interrupt
CPUSS P-DMA1, Channel #6 Interrupt
CPUSS P-DMA1, Channel #7 Interrupt
CPUSS P-DMA1, Channel #8 Interrupt
CPUSS P-DMA1, Channel #9 Interrupt
CPUSS P-DMA1, Channel #10 Interrupt
CPUSS P-DMA1, Channel #11 Interrupt
CPUSS P-DMA1, Channel #12 Interrupt
CPUSS P-DMA1, Channel #13 Interrupt
CPUSS P-DMA1, Channel #14 Interrupt
CPUSS P-DMA1, Channel #15 Interrupt
CPUSS P-DMA1, Channel #16 Interrupt
CPUSS P-DMA1, Channel #17 Interrupt
CPUSS P-DMA1, Channel #18 Interrupt
CPUSS P-DMA1, Channel #19 Interrupt
CPUSS P-DMA1, Channel #20 Interrupt
CPUSS P-DMA1, Channel #21 Interrupt
CPUSS P-DMA1, Channel #22 Interrupt
CPUSS P-DMA1, Channel #23 Interrupt
CPUSS P-DMA1, Channel #24 Interrupt
CPUSS P-DMA1, Channel #25 Interrupt
CPUSS P-DMA1, Channel #26 Interrupt
CPUSS P-DMA1, Channel #27 Interrupt
CPUSS P-DMA1, Channel #28 Interrupt
CPUSS P-DMA1, Channel #29 Interrupt
CPUSS P-DMA1, Channel #30 Interrupt
CPUSS P-DMA1, Channel #31 Interrupt
CPUSS P-DMA1, Channel #32 Interrupt
CPUSS P-DMA1, Channel #33 Interrupt
CPUSS P-DMA1, Channel #34 Interrupt
cpuss_interrupts_dw0_90_IRQn
cpuss_interrupts_dw0_91_IRQn
cpuss_interrupts_dw0_92_IRQn
cpuss_interrupts_dw0_93_IRQn
cpuss_interrupts_dw0_94_IRQn
cpuss_interrupts_dw0_95_IRQn
cpuss_interrupts_dw0_96_IRQn
cpuss_interrupts_dw0_97_IRQn
cpuss_interrupts_dw0_98_IRQn
cpuss_interrupts_dw0_99_IRQn
cpuss_interrupts_dw1_0_IRQn
cpuss_interrupts_dw1_1_IRQn
cpuss_interrupts_dw1_2_IRQn
cpuss_interrupts_dw1_3_IRQn
cpuss_interrupts_dw1_4_IRQn
cpuss_interrupts_dw1_5_IRQn
cpuss_interrupts_dw1_6_IRQn
cpuss_interrupts_dw1_7_IRQn
cpuss_interrupts_dw1_8_IRQn
cpuss_interrupts_dw1_9_IRQn
cpuss_interrupts_dw1_10_IRQn
cpuss_interrupts_dw1_11_IRQn
cpuss_interrupts_dw1_12_IRQn
cpuss_interrupts_dw1_13_IRQn
cpuss_interrupts_dw1_14_IRQn
cpuss_interrupts_dw1_15_IRQn
cpuss_interrupts_dw1_16_IRQn
cpuss_interrupts_dw1_17_IRQn
cpuss_interrupts_dw1_18_IRQn
cpuss_interrupts_dw1_19_IRQn
cpuss_interrupts_dw1_20_IRQn
cpuss_interrupts_dw1_21_IRQn
cpuss_interrupts_dw1_22_IRQn
cpuss_interrupts_dw1_23_IRQn
cpuss_interrupts_dw1_24_IRQn
cpuss_interrupts_dw1_25_IRQn
cpuss_interrupts_dw1_26_IRQn
cpuss_interrupts_dw1_27_IRQn
cpuss_interrupts_dw1_28_IRQn
cpuss_interrupts_dw1_29_IRQn
cpuss_interrupts_dw1_30_IRQn
cpuss_interrupts_dw1_31_IRQn
cpuss_interrupts_dw1_32_IRQn
cpuss_interrupts_dw1_33_IRQn
cpuss_interrupts_dw1_34_IRQn
Datasheet
63
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA1, Channel #35 Interrupt
CPUSS P-DMA1, Channel #36 Interrupt
CPUSS P-DMA1, Channel #37 Interrupt
CPUSS P-DMA1, Channel #38 Interrupt
CPUSS P-DMA1, Channel #39 Interrupt
CPUSS P-DMA1, Channel #40 Interrupt
CPUSS P-DMA1, Channel #41 Interrupt
CPUSS P-DMA1, Channel #42 Interrupt
CPUSS P-DMA1, Channel #43 Interrupt
CPUSS P-DMA1, Channel #44 Interrupt
CPUSS P-DMA1, Channel #45 Interrupt
CPUSS P-DMA1, Channel #46 Interrupt
CPUSS P-DMA1, Channel #47 Interrupt
CPUSS P-DMA1, Channel #48 Interrupt
CPUSS P-DMA1, Channel #49 Interrupt
CPUSS P-DMA1, Channel #50 Interrupt
CPUSS P-DMA1, Channel #51 Interrupt
CPUSS P-DMA1, Channel #52 Interrupt
CPUSS P-DMA1, Channel #53 Interrupt
CPUSS P-DMA1, Channel #54 Interrupt
CPUSS P-DMA1, Channel #55 Interrupt
CPUSS P-DMA1, Channel #56 Interrupt
CPUSS P-DMA1, Channel #57 Interrupt
TCPWM0 Group #0, Counter #0 Interrupt
TCPWM0 Group #0, Counter #1 Interrupt
TCPWM0 Group #0, Counter #2 Interrupt
TCPWM0 Group #0, Counter #3 Interrupt
TCPWM0 Group #0, Counter #4 Interrupt
TCPWM0 Group #0, Counter #5 Interrupt
TCPWM0 Group #0, Counter #6 Interrupt
TCPWM0 Group #0, Counter #7 Interrupt
TCPWM0 Group #0, Counter #8 Interrupt
TCPWM0 Group #0, Counter #9 Interrupt
TCPWM0 Group #0, Counter #10 Interrupt
TCPWM0 Group #0, Counter #11 Interrupt
TCPWM0 Group #0, Counter #12 Interrupt
TCPWM0 Group #0, Counter #13 Interrupt
TCPWM0 Group #0, Counter #14 Interrupt
TCPWM0 Group #0, Counter #15 Interrupt
TCPWM0 Group #0, Counter #16 Interrupt
TCPWM0 Group #0, Counter #17 Interrupt
TCPWM0 Group #0, Counter #18 Interrupt
TCPWM0 Group #0, Counter #19 Interrupt
TCPWM0 Group #0, Counter #20 Interrupt
TCPWM0 Group #0, Counter #21 Interrupt
cpuss_interrupts_dw1_35_IRQn
cpuss_interrupts_dw1_36_IRQn
cpuss_interrupts_dw1_37_IRQn
cpuss_interrupts_dw1_38_IRQn
cpuss_interrupts_dw1_39_IRQn
cpuss_interrupts_dw1_40_IRQn
cpuss_interrupts_dw1_41_IRQn
cpuss_interrupts_dw1_42_IRQn
cpuss_interrupts_dw1_43_IRQn
cpuss_interrupts_dw1_44_IRQn
cpuss_interrupts_dw1_45_IRQn
cpuss_interrupts_dw1_46_IRQn
cpuss_interrupts_dw1_47_IRQn
cpuss_interrupts_dw1_48_IRQn
cpuss_interrupts_dw1_49_IRQn
cpuss_interrupts_dw1_50_IRQn
cpuss_interrupts_dw1_51_IRQn
cpuss_interrupts_dw1_52_IRQn
cpuss_interrupts_dw1_53_IRQn
cpuss_interrupts_dw1_54_IRQn
cpuss_interrupts_dw1_55_IRQn
cpuss_interrupts_dw1_56_IRQn
cpuss_interrupts_dw1_57_IRQn
tcpwm_0_interrupts_0_IRQn
tcpwm_0_interrupts_1_IRQn
tcpwm_0_interrupts_2_IRQn
tcpwm_0_interrupts_3_IRQn
tcpwm_0_interrupts_4_IRQn
tcpwm_0_interrupts_5_IRQn
tcpwm_0_interrupts_6_IRQn
tcpwm_0_interrupts_7_IRQn
tcpwm_0_interrupts_8_IRQn
tcpwm_0_interrupts_9_IRQn
tcpwm_0_interrupts_10_IRQn
tcpwm_0_interrupts_11_IRQn
tcpwm_0_interrupts_12_IRQn
tcpwm_0_interrupts_13_IRQn
tcpwm_0_interrupts_14_IRQn
tcpwm_0_interrupts_15_IRQn
tcpwm_0_interrupts_16_IRQn
tcpwm_0_interrupts_17_IRQn
tcpwm_0_interrupts_18_IRQn
tcpwm_0_interrupts_19_IRQn
tcpwm_0_interrupts_20_IRQn
tcpwm_0_interrupts_21_IRQn
Datasheet
64
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
TCPWM0 Group #0, Counter #22 Interrupt
TCPWM0 Group #0, Counter #23 Interrupt
TCPWM0 Group #0, Counter #24 Interrupt
TCPWM0 Group #0, Counter #25 Interrupt
TCPWM0 Group #0, Counter #26 Interrupt
TCPWM0 Group #0, Counter #27 Interrupt
TCPWM0 Group #0, Counter #28 Interrupt
TCPWM0 Group #0, Counter #29 Interrupt
TCPWM0 Group #0, Counter #30 Interrupt
TCPWM0 Group #0, Counter #31 Interrupt
TCPWM0 Group #0, Counter #32 Interrupt
TCPWM0 Group #0, Counter #33 Interrupt
TCPWM0 Group #0, Counter #34 Interrupt
TCPWM0 Group #0, Counter #35 Interrupt
TCPWM0 Group #0, Counter #36 Interrupt
TCPWM0 Group #0, Counter #37 Interrupt
TCPWM0 Group #0, Counter #38 Interrupt
TCPWM0 Group #0, Counter #39 Interrupt
TCPWM0 Group #0, Counter #40 Interrupt
TCPWM0 Group #0, Counter #41 Interrupt
TCPWM0 Group #0, Counter #42 Interrupt
TCPWM0 Group #0, Counter #43 Interrupt
TCPWM0 Group #0, Counter #44 Interrupt
TCPWM0 Group #0, Counter #45 Interrupt
TCPWM0 Group #0, Counter #46 Interrupt
TCPWM0 Group #0, Counter #47 Interrupt
TCPWM0 Group #0, Counter #48 Interrupt
TCPWM0 Group #0, Counter #49 Interrupt
TCPWM0 Group #0, Counter #50 Interrupt
TCPWM0 Group #0, Counter #51 Interrupt
TCPWM0 Group #0, Counter #52 Interrupt
TCPWM0 Group #0, Counter #53 Interrupt
TCPWM0 Group #0, Counter #54 Interrupt
TCPWM0 Group #0, Counter #55 Interrupt
TCPWM0 Group #0, Counter #56 Interrupt
TCPWM0 Group #0, Counter #57 Interrupt
TCPWM0 Group #0, Counter #58 Interrupt
TCPWM0 Group #0, Counter #59 Interrupt
TCPWM0 Group #0, Counter #60 Interrupt
TCPWM0 Group #0, Counter #61 Interrupt
TCPWM0 Group #0, Counter #62 Interrupt
TCPWM0 Group #1, Counter #0 Interrupt
TCPWM0 Group #1, Counter #1 Interrupt
TCPWM0 Group #1, Counter #2 Interrupt
TCPWM0 Group #1, Counter #3 Interrupt
tcpwm_0_interrupts_22_IRQn
tcpwm_0_interrupts_23_IRQn
tcpwm_0_interrupts_24_IRQn
tcpwm_0_interrupts_25_IRQn
tcpwm_0_interrupts_26_IRQn
tcpwm_0_interrupts_27_IRQn
tcpwm_0_interrupts_28_IRQn
tcpwm_0_interrupts_29_IRQn
tcpwm_0_interrupts_30_IRQn
tcpwm_0_interrupts_31_IRQn
tcpwm_0_interrupts_32_IRQn
tcpwm_0_interrupts_33_IRQn
tcpwm_0_interrupts_34_IRQn
tcpwm_0_interrupts_35_IRQn
tcpwm_0_interrupts_36_IRQn
tcpwm_0_interrupts_37_IRQn
tcpwm_0_interrupts_38_IRQn
tcpwm_0_interrupts_39_IRQn
tcpwm_0_interrupts_40_IRQn
tcpwm_0_interrupts_41_IRQn
tcpwm_0_interrupts_42_IRQn
tcpwm_0_interrupts_43_IRQn
tcpwm_0_interrupts_44_IRQn
tcpwm_0_interrupts_45_IRQn
tcpwm_0_interrupts_46_IRQn
tcpwm_0_interrupts_47_IRQn
tcpwm_0_interrupts_48_IRQn
tcpwm_0_interrupts_49_IRQn
tcpwm_0_interrupts_50_IRQn
tcpwm_0_interrupts_51_IRQn
tcpwm_0_interrupts_52_IRQn
tcpwm_0_interrupts_53_IRQn
tcpwm_0_interrupts_54_IRQn
tcpwm_0_interrupts_55_IRQn
tcpwm_0_interrupts_56_IRQn
tcpwm_0_interrupts_57_IRQn
tcpwm_0_interrupts_58_IRQn
tcpwm_0_interrupts_59_IRQn
tcpwm_0_interrupts_60_IRQn
tcpwm_0_interrupts_61_IRQn
tcpwm_0_interrupts_62_IRQn
tcpwm_0_interrupts_256_IRQn
tcpwm_0_interrupts_257_IRQn
tcpwm_0_interrupts_258_IRQn
tcpwm_0_interrupts_259_IRQn
Datasheet
65
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (Preliminary) (continued)
Interrupt
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
TCPWM0 Group #1, Counter #4 Interrupt
TCPWM0 Group #1, Counter #5 Interrupt
TCPWM0 Group #1, Counter #6 Interrupt
TCPWM0 Group #1, Counter #7 Interrupt
TCPWM0 Group #1, Counter #8 Interrupt
TCPWM0 Group #1, Counter #9 Interrupt
TCPWM0 Group #1, Counter #10 Interrupt
TCPWM0 Group #1, Counter #11 Interrupt
TCPWM0 Group #2, Counter #0 Interrupt
TCPWM0 Group #2, Counter #1 Interrupt
TCPWM0 Group #2, Counter #2 Interrupt
TCPWM0 Group #2, Counter #3 Interrupt
TCPWM0 Group #2, Counter #4 Interrupt
TCPWM0 Group #2, Counter #5 Interrupt
TCPWM0 Group #2, Counter #6 Interrupt
TCPWM0 Group #2, Counter #7 Interrupt
SMIF0 (QSPI) interrupt
tcpwm_0_interrupts_260_IRQn
tcpwm_0_interrupts_261_IRQn
tcpwm_0_interrupts_262_IRQn
tcpwm_0_interrupts_263_IRQn
tcpwm_0_interrupts_264_IRQn
tcpwm_0_interrupts_265_IRQn
tcpwm_0_interrupts_266_IRQn
tcpwm_0_interrupts_267_IRQn
tcpwm_0_interrupts_512_IRQn
tcpwm_0_interrupts_513_IRQn
tcpwm_0_interrupts_514_IRQn
tcpwm_0_interrupts_515_IRQn
tcpwm_0_interrupts_516_IRQn
tcpwm_0_interrupts_517_IRQn
tcpwm_0_interrupts_518_IRQn
tcpwm_0_interrupts_519_IRQn
smif_0_interrupt_IRQn
eth_0_interrupt_eth_0_IRQn
eth_0_interrupt_eth_2_IRQn
eth_0_interrupt_eth_1_IRQn
sdhc_0_interrupt_general_IRQn
sdhc_0_interrupt_wakeup_IRQn
audioss_0_interrupt_i2s_IRQn
audioss_1_interrupt_i2s_IRQn
audioss_2_interrupt_i2s_IRQn
Ethernet0 interrupt for dma_priority_queue0
Ethernet0 interrupt for dma_priority_queue2
Ethernet0 interrupt for dma_priority_queue1
SDHC0 general interrupt
SDHC0 wakeup interrupt
AUDIOSS I2S0 interrupt
AUDIOSS I2S1 interrupt
AUDIOSS I2S2 interrupt
Datasheet
66
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Core interrupt types
15
Core interrupt types
Table 15-1
Core interrupt types
Interrupt
Source
CPUIntIdx0_IRQn[31]
CPUIntIdx1_IRQn[31]
CPUIntIdx2_IRQn
CPUIntIdx3_IRQn
CPUIntIdx4_IRQn
CPUIntIdx5_IRQn
CPUIntIdx6_IRQn
CPUIntIdx7_IRQn
Internal0_IRQn
Internal1_IRQn
Internal2_IRQn
Internal3_IRQn
Internal4_IRQn
Internal5_IRQn
Internal6_IRQn
Internal7_IRQn
Power mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Active
Description
CPU User Interrupt #0
CPU User Interrupt #1
CPU User Interrupt #2
CPU User Interrupt #3
CPU User Interrupt #4
CPU User Interrupt #5
CPU User Interrupt #6
CPU User Interrupt #7
Internal Software Interrupt #0
Internal Software Interrupt #1
Internal Software Interrupt #2
Internal Software Interrupt #3
Internal Software Interrupt #4
Internal Software Interrupt #5
Internal Software Interrupt #6
Internal Software Interrupt #7
0
1
2
3
4
5
6
7
8
9
Active
Active
Active
Active
Active
Active
Active
10
11
12
13
14
15
Note
31.User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM7 application.
Datasheet
67
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Trigger multiplexer
16
Trigger multiplexer
Green number in mux means Mux TriggerGroupNr.
[0:15]
[0:15]
[0:7]
[1:16]
[17:32]
[33:40]
[41:44]
[45:48]
[49:64]
[65:68]
PDMA0_TR_OUT[0:15]
PDMA1_TR_OUT[0:15]
MDMA_TR_OUT[0:7]
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
HSIOM_IO_INPUT[0:15]
FAULT_TR_OUT[0:3]
P-DMA0: PDMA0_TR_OUT[0:99]
P-DMA1: PDMA1_TR_OUT[0:57]
M-DMA: MDMA_TR_OUT[0:7]
CAN[0]: CAN0_TT_TR_OUT[0:3]
CAN[1]: CAN1_TT_TR_OUT[0:3]
HSIO: HSIOM_IO_INPUT[0:31]
CPUSS: FAULT_TR_OUT[0:3]
[0:3]
[0:7]
P-DMA0: PDMA0_TR_IN[0:7]
0
[0:3]
[0:15]
[0:3]
[0:29]
[0:11]
[0:7]
[0:5]
[0:1]
[0:3]
[1:30]
[31:42]
[43:50]
[51:56]
[57:58]
[59:62]
TCPWM_16_TR_OUT0[0:29]
TCPWM_16M_TR_OUT0[0:11]
TCPWM_32_TR_OUT0[0:7]
PASS_GEN_TR_OUT[0:5]
CTI_TR_OUT[0:1]
TCPWM[0]16: TCPWM_16_TR_OUT0[0:62]
TCPWM[0]16M: TCPWM_16M_TR_OUT0[0:11]
TCPWM[0]32: TCPWM_32_TR_OUT0[0:7]
PASS: PASS_GEN_TR_OUT[0:5]
[0:7]
P-DMA0: PDMA0_TR_IN[8:15]
1
CPUSS: CTI_TR_OUT[0:1]
EVTGEN_TR_OUT[0:3]
EVTGEN: EVTGEN_TR_OUT[0:15]
[0:15]
[0:15]
[1:16]
[17:32]
[33:65]
[66:81]
PDMA1_TR_OUT[0:15]
PDMA0_TR_OUT[0:15]
TCPWM_16_TR_OUT0[30:62]
HSIOM_IO_INPUT[16:31]
PDMA1_TR_OUT[0:15]
PDMA0_TR_OUT[0:15]
TCPWM_16_TR_OUT0[30:62]
HSIOM_IO_INPUT[16:31]
P-DMA1: PDMA1_TR_OUT[0:15]
P-DMA0: PDMA0_TR_OUT[0:15]
[0:15]
[0:7]
P-DMA1: PDMA1_TR_IN[0:15]
M-DMA: MDMA_TR_IN[0:7]
[30:62]
[16:31]
2
3
TCPWM[0]16: TCPWM_16_TR_OUT0[30:62]
HSIOM_IO_INPUT[16:31]
[0:2]
[0:2]
[1:3]
[4:6]
TCPWM_16_TR_OUT1[0:2]
TCPWM_16M_TR_OUT1[0:2]
TCPWM[0]16: TCPWM_16_TR_OUT1[0:62]
TCPWM[0]16M: TCPWM_16M_TR_OUT1[0:11]
[0:62]
[0:11]
[0:7]
[0:3]
[0:3]
[0:3]
[0:3]
[1:63]
[64:75]
[76:83]
[84:87]
[88:91]
[92:95]
[96:99]
TCPWM_16_TR_OUT0[0:62]
TCPWM_16M_TR_OUT0[0:11]
TCPWM_32_TR_OUT0[0:7]
CAN0_DBG_TR_OUT[0:3]
CAN0_FIFO0_TR_OUT[0:3]
CAN0_FIFO1_TR_OUT[0:3]
CAN1_DBG_TR_OUT[0:3]
CAN1_FIFO0_TR_OUT[0:3]
CAN1_FIFO1_TR_OUT[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
EVTGEN_TR_OUT[4:11]
PDMA0_TR_OUT[0:15]
PDMA1_TR_OUT[0:15]
MDMA_TR_OUT[0:7]
TCPWM_16_TR_OUT0[0:62]
TCPWM_16M_TR_OUT0[0:11]
TCPWM_32_TR_OUT0[0:7]
CAN0_DBG_TR_OUT[0:3]
CAN0_FIFO0_TR_OUT[0:3]
CAN0_FIFO1_TR_OUT[0:3]
CAN1_DBG_TR_OUT[0:3]
CAN1_FIFO0_TR_OUT[0:3]
CAN1_FIFO1_TR_OUT[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
EVTGEN_TR_OUT[4:11]
PDMA0_TR_OUT[0:15]
PDMA0_TR_OUT[0:15]
MDMA_TR_OUT[0:7]
TCPWM[0]16: TCPWM_16_TR_OUT0[0:62]
TCPWM[0]16: TCPWM_16M_TR_OUT0[0:11]
TCPWM[0]32: TCPWM_32_TR_OUT0[0:7]
CAN[0]: CAN0_DBG_TR_OUT[0:3]
CAN[0]: CAN0_FIFO0_TR_OUT[0:3]
CAN[0]: CAN0_FIFO1_TR_OUT[0:3]
CAN[1]: CAN1_DBG_TR_OUT[0:3]
CAN[1]: CAN1_FIFO0_TR_OUT[0:3]
CAN[1]: CAN1_FIFO1_TR_OUT[0:3]
CAN[0]: CAN0_TT_TR_OUT[0:3]
CAN[1]: CAN1_TT_TR_OUT[0:3]
EVTGEN: EVTGEN_TR_OUT[4:11]
P-DMA0: PDMA0_TR_OUT[0:15]
P-DMA1: PDMA1_TR_OUT[0:15]
MDMA0: MDMA_TR_OUT[0:7]
[0:3] [100:103]
[0:3] [104:107]
[0:3] [108:111]
[0:3] [112:115]
[4:11] [116:123]
[0:15] [124:139]
[0:15] [140:155]
[0:7] [156:163]
[0:11]
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[0:11]
5
1
1
[164]
[165]
SMIF_TX_TR_OUT
SMIF_TX_TR_OUT
SIMF: SMIF_TX_TR_OUT
SMIF_RX_TR_OUT
SMIF_RX_TR_OUT
SIMF: SMIF_RX_TR_OUT
1
1
1
1
1
1
[166]
[167]
[168]
[169]
[170]
[171]
I2S0_TX_TR_OUT
I2S0_RX_TR_OUT
I2S1_TX_TR_OUT
I2S1_RX_TR_OUT
I2S2_TX_TR_OUT
I2S2_RX_TR_OUT
I2S0_TX_TR_OUT
I2S0_RX_TR_OUT
I2S1_TX_TR_OUT
I2S1_RX_TR_OUT
I2S2_TX_TR_OUT
I2S2_RX_TR_OUT
AUDIOSS[0]: I2S0_TX_TR_OUT
AUDIOSS[0]: I2S0_RX_TR_OUT
AUDIOSS[1]: I2S1_TX_TR_OUT
AUDIOSS[1]: I2S1_RX_TR_OUT
AUDIOSS[2]: I2S2_TX_TR_OUT
AUDIOSS[2]: I2S2_RX_TR_OUT
[0:15]
[1:16]
[17]
TCPWM_16_TR_OUT1[0:15]
SCB_TX_TR_OUT[0]
TCPWM[0]16: TCPWM_16_TR_OUT1[0:15]
SCB[0]: SCB_TX_TR_OUT[0]
1
1
[18]
SCB_RX_TR_OUT[0]
SCB[0]: SCB_RX_TR_OUT[0]
1
[19]
SCB_I2C_SCL_TR_OUT[0]
(repeat from [1] to [9])
SCB[0]: SCB_I2C_SCL_TR_OUT[0]
(repeat from [1] to [9])
27
1
[20:46]
[47]
SCB_TX_TR_OUT[10]
SCB_RX_TR_OUT[10]
SCB_I2C_SCL_TR_OUT[10]
SCB[10]: SCB_TX_TR_OUT[10]
SCB[10]: SCB_RX_TR_OUT[10]
SCB[10]: SCB_I2C_SCL_TR_OUT[10]
1
[48]
[0:14]
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[12:26]
6
1
[49]
[0:5]
[0:31]
[0:1]
[50:55]
[56:87]
[88:89]
[90:93]
PASS_GEN_TR_OUT[0:5]
HSIOM_IO_INPUT[0:31]
CTI_TR_IN[0:1]
PASS_GEN_TR_OUT[0:5]
HSIOM_IO_INPUT[0:31]
CTI_TR_IN[0:1]
[0:3]
FAULT_TR_OUT[0:3]
FAULT_TR_OUT[0:3]
[0:15]
[0:11]
[0:7]
[1:16]
[17:28]
[29:36]
[37:38]
[39:46]
[47:49]
PDMA0_TR_OUT[0:15]
PDMA0_TR_OUT[0:15]
TCPWM[0]16M: TCPWM_16M_TR_OUT0[0:11]
TCPWM[0]32M: TCPWM_32_TR_OUT0[0:7]
TCPWM[0]16: TCPWM_16_TR_OUT1[60:61]
HSIOM_IO_INPUT[0:7]
TCPWM_16M_TR_OUT0[0:11]
TCPWM_32_TR_OUT0[0:7]
TCPWM_16_TR_OUT1[60:61]
HSIOM_IO_INPUT[0:7]
[0:11]
PASS: PASS_GEN_TR_IN[0:11]
[60:61]
[0:7]
7
8
[12:14]
EVTGEN_TR_OUT[12:14]
EVTGEN_TR_OUT[12:14]
[0:3]
[0:3]
[1:4]
[5:8]
[0:3]
[4:7]
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
CAN[0]: CAN0_TT_TR_IN[0:3]
CAN[1]: CAN1_TT_TR_IN[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
[0]
[1]
HSIOM: HSIOM_IO_OUTPUT[0]
HSIOM: HSIOM_IO_OUTPUT[1]
[2:3]
[4]
CPUSS: CTI_TR_IN[0:1]
PERI: PERI_DEBUG_FREEZE_TR_IN
PASS: PASS_DEBUG_FREEZE_TR_IN
SRSS: SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[2]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[1]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0]
TCPWM[0]: TCPWM_DEBUG_FREEZE_TR_IN
[1:5]
[6:10]
[5]
TR_GROUP10_OUTPUT[0:4]
TR_GROUP11_OUTPUT[0:4]
TR_GROUP12_OUTPUT[0:4]
TR_GROUP10_OUTPUT[0:4]
9
[6]
[11:15]
[7]
[8]
[9]
TR_GROUP11_OUTPUT[0:4]
[10]
TR_GROUP12_OUTPUT[0:4]
[0:99]
[1:100]
[0:10] [101:111]
[0:10] [112:122]
[0:10] [123:133]
[0:3] [134:137]
[0:3] [138:141]
[0:3] [142:145]
[0:3] [146:149]
[0:3] [150:153]
[0:3] [154:157]
[0:3] [158:161]
[0:3] [162:165]
[0:1] [166:167]
[0:3] [168:171]
[0:15] [172:187]
PDMA0_TR_OUT[0:99]
SCB_TX_TR_OUT[0:10]
SCB_RX_TR_OUT[0:10]
SCB_I2C_SCL_TR_OUT[0:10]
CAN0_DBG_TR_OUT[0:3]
CAN0_FIFO0_TR_OUT[0:3]
CAN0_FIFO1_TR_OUT[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_DBG_TR_OUT[0:3]
CAN1_FIFO0_TR_OUT[0:3]
CAN1_FIFO1_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
PDMA0_TR_OUT[0:99]
SCB_TX_TR_OUT[0:10]
SCB_RX_TR_OUT[0:10]
SCB_I2C_SCL_TR_OUT[0:10]
CAN0_DBG_TR_OUT[0:3]
CAN0_FIFO0_TR_OUT[0:3]
CAN0_FIFO1_TR_OUT[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_DBG_TR_OUT[0:3]
CAN1_FIFO0_TR_OUT[0:3]
CAN1_FIFO1_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
PDMA0_TR_OUT[0:99]
SCB_TX_TR_OUT[0:10]
SCB_RX_TR_OUT[0:10]
SCB_I2C_SCL_TR_OUT[0:10]
CAN0_DBG_TR_OUT[0:3]
CAN0_FIFO0_TR_OUT[0:3]
CAN0_FIFO1_TR_OUT[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_DBG_TR_OUT[0:3]
CAN1_FIFO0_TR_OUT[0:3]
CAN1_FIFO1_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
[0:4]
TR_GROUP9_INPUT[1:5]
10
FAULT_TR_OU[0:3]
FAULT_TR_OU[0:3]
FAULT_TR_OU[0:3]
EVTGEN_TR_OUT[0:15]
EVTGEN_TR_OUT[0:15]
EVTGEN_TR_OUT[0:15]
[0:7]
[1:8]
[9:20]
[21:83]
[84]
TCPWM_32_TR_OUT0[0:7]
TCPWM_16M_TR_OUT0[0:11]
TCPWM_16_TR_OUT0[0:62]
TCPWM_32_TR_OUT0[0:7]
TCPWM_16M_TR_OUT0[0:11]
TCPWM_16_TR_OUT0[0:62]
SMIF_TX_TR_OUT
TCPWM[0]32: TCPWM_32_TR_OUT0[0:7]
TCPWM[0]16M: TCPWM_16M_TR_OUT0[0:11]
TCPWM[0]16: TCPWM_16_TR_OUT0[0:62]
SMIF_TX_TR_OUT
[0:11]
[0:62]
1
1
1
1
1
1
1
1
[85]
SMIF_RX_TR_OUT
SMIF_RX_TR_OUT
[86]
I2S0_TX_TR_OUT
I2S0_TX_TR_OUT
[87] 11
[88]
[0:4]
I2S0_RX_TR_OUT
TR_GROUP9_INPUT[6:10]
I2S0_RX_TR_OUT
I2S1_TX_TR_OUT
I2S1_TX_TR_OUT
[89]
I2S1_RX_TR_OUT
I2S1_RX_TR_OUT
[90]
I2S2_TX_TR_OUT
I2S2_TX_TR_OUT
[91]
I2S2_RX_TR_OUT
I2S2_RX_TR_OUT
[0:31] [92:123]
HSIOM_IO_INPUT[0:31]
HSIOM_IO_INPUT[0:31]
HSIOM_IO_INPUT[0:31]
[0:57]
[0:7]
[1:58]
PDMA1_TR_OUT[0:57]
PDMA1_TR_OUT[0:57]
PDMA1_TR_OUT[0:57]
MDMA_TR_OUT[0:7]
[59:66]
MDMA_TR_OUT[0:7]
MDMA_TR_OUT[0:7]
[0:62] [67:129]
[0:11] [130:141] 12
[0:7] [142:149]
TCPWM_16_TR_OUT1[0:62]
TCPWM_16M_TR_OUT1[0:11]
TCPWM_32_TR_OUT1[0:7]
PASS_GEN_TR_OUT[0:5]
TCPWM_16_TR_OUT1[0:62]
TCPWM_16M_TR_OUT1[0:11]
TCPWM_32_TR_OUT1[0:7]
PASS_GEN_TR_OUT[0:5]
TCPWM[0]16: TCPWM_16_TR_OUT1[0:62]
TCPWM[0]16M: TCPWM_16M_TR_OUT1[0:11]
TCPWM[0]32: TCPWM_32_TR_OUT1[0:7]
PASS_GEN_TR_OUT[0:5]
[0:4]
TR_GROUP9_INPUT[11:15]
[0:5] [150:155]
Figure 16-1
Trigger multiplexer group [32]
Note
32.This diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula
TRIG_{PREFIX(IN/OUT)}_{MUX_x}_{TRIG_LABEL} and the information provided in Table 17-1 on page 70 and Table 18-1 on
page 74.
Datasheet
68
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Trigger multiplexer
One-To-One TriggerGroupNr = 0
CAN[0]: CAN0_DBG_TR_OUT[0]
CAN[0]: CAN0_FIFO0_TR_OUT[0]
CAN[0]: CAN0_FIFO1_TR_OUT[0]
CAN[0]: CAN0_DBG_TR_OUT[1]
CAN[0]: CAN0_FIFO0_TR_OUT[1]
CAN[0]: CAN0_FIFO1_TR_OUT[1]
CAN[0]: CAN0_DBG_TR_OUT[2]
CAN[0]: CAN0_FIFO0_TR_OUT[2]
CAN[0]: CAN0_FIFO1_TR_OUT[2]
CAN[0]: CAN0_DBG_TR_OUT[3]
CAN[0]: CAN0_FIFO0_TR_OUT[3]
CAN[0]: CAN0_FIFO1_TR_OUT[3]
P-DMA0: PDMA0_TR_IN[16]
P-DMA0: PDMA0_TR_IN[17]
P-DMA0: PDMA0_TR_IN[18]
P-DMA0: PDMA0_TR_IN[19]
P-DMA0: PDMA0_TR_IN[20]
P-DMA0: PDMA0_TR_IN[21]
P-DMA0: PDMA0_TR_IN[22]
P-DMA0: PDMA0_TR_IN[23]
P-DMA0: PDMA0_TR_IN[24]
P-DMA0: PDMA0_TR_IN[25]
P-DMA0: PDMA0_TR_IN[26]
P-DMA0: PDMA0_TR_IN[27]
One-To-One TriggerGroupNr = 1
PASS0: PASS0_CH_DONE_TR_OUT[0:31]
PASS0: PASS0_CH_DONE_TR_OUT[32:63]
PASS0: PASS0_CH_DONE_TR_OUT[64:71]
P-DMA0: PDMA0_TR_IN[28:59]
P-DMA0: PDMA0_TR_IN[60:91]
P-DMA0: PDMA0_TR_IN[92:99]
One-To-One TriggerGroupNr = 2
SCB[0]: SCB0_TX_TR_OUT
SCB[0]: SCB0_RX_TR_OUT
…
P-DMA1: PDMA1_TR_IN[16]
P-DMA1: PDMA1_TR_IN[17]
…
…
…
SCB[10]: SCB10_TX_TR_OUT
SCB[10]: SCB10_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[36]
P-DMA1: PDMA1_TR_IN[37]
One-To-One TriggerGroupNr = 3
SMIF: SMIF_TX_TR_OUT
SMIF: SMIF_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[50]
P-DMA1: PDMA1_TR_IN[51]
One-To-One TriggerGroupNr = 4
CAN[1]: CAN1_DBG_TR_OUT[0]
CAN[1]: CAN1_FIFO0_TR_OUT[0]
CAN[1]: CAN1_FIFO1_TR_OUT[0]
CAN[1]: CAN1_DBG_TR_OUT[1]
CAN[1]: CAN1_FIFO0_TR_OUT[1]
CAN[1]: CAN1_FIFO1_TR_OUT[1]
CAN[1]: CAN1_DBG_TR_OUT[2]
CAN[1]: CAN1_FIFO0_TR_OUT[2]
CAN[1]: CAN1_FIFO1_TR_OUT[2]
CAN[1]: CAN1_DBG_TR_OUT[3]
CAN[1]: CAN1_FIFO0_TR_OUT[3]
CAN[1]: CAN1_FIFO1_TR_OUT[3]
P-DMA1: PDMA1_TR_IN[38]
P-DMA1: PDMA1_TR_IN[39]
P-DMA1: PDMA1_TR_IN[40]
P-DMA1: PDMA1_TR_IN[41]
P-DMA1: PDMA1_TR_IN[42]
P-DMA1: PDMA1_TR_IN[43]
P-DMA1: PDMA1_TR_IN[44]
P-DMA1: PDMA1_TR_IN[45]
P-DMA1: PDMA1_TR_IN[46]
P-DMA1: PDMA1_TR_IN[47]
P-DMA1: PDMA1_TR_IN[48]
P-DMA1: PDMA1_TR_IN[49]
One-To-One TriggerGroupNr = 5
AUDIO: AUDIO0_TX_TR_OUT
AUDIO: AUDIO0_RX_TR_OUT
AUDIO: AUDIO1_TX_TR_OUT
AUDIO: AUDIO1_RX_TR_OUT
AUDIO: AUDIO2_TX_TR_OUT
AUDIO: AUDIO2_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[52]
P-DMA1: PDMA1_TR_IN[53]
P-DMA1: PDMA1_TR_IN[54]
P-DMA1: PDMA1_TR_IN[55]
P-DMA1: PDMA1_TR_IN[56]
P-DMA1: PDMA1_TR_IN[57]
One-To-One TriggerGroupNr = 6
PASS: PASS0_CH_RANGEVIO_TR_OUT[0]
PASS: PASS0_CH_RANGEVIO_TR_OUT[1]
PASS: PASS0_CH_RANGEVIO_TR_OUT[2]
PASS: PASS0_CH_RANGEVIO_TR_OUT[3]
PASS: PASS0_CH_RANGEVIO_TR_OUT[4:31]
PASS: PASS0_CH_RANGEVIO_TR_OUT[32]
PASS: PASS0_CH_RANGEVIO_TR_OUT[33]
PASS: PASS0_CH_RANGEVIO_TR_OUT[34]
PASS: PASS0_CH_RANGEVIO_TR_OUT[35]
PASS: PASS0_CH_RANGEVIO_TR_OUT[36:63]
PASS: PASS0_CH_RANGEVIO_TR_OUT[64]
PASS: PASS0_CH_RANGEVIO_TR_OUT[65]
PASS: PASS0_CH_RANGEVIO_TR_OUT[66]
PASS: PASS0_CH_RANGEVIO_TR_OUT[67]
PASS: PASS0_CH_RANGEVIO_TR_OUT[68:71]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[0]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[3]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[6]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[9]
TCPWM[0]16: TCPWM0_16_ONE_CNT_TR_IN[0:27]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[1]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[4]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[7]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[10]
TCPWM[0]16: TCPWM0_16_ONE_CNT_TR_IN[28:55]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[2]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[5]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[8]
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[11]
TCPWM[0]16: TCPWM0_16_ONE_CNT_TR_IN[56:59]
One-To-One TriggerGroupNr = 7
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[0]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[3]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[6]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[9]
TCPWM[0]16: TCPWM0_16_TR_OUT1[0:27]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[1]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[4]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[7]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[10]
TCPWM[0]16: TCPWM0_16_TR_OUT1[28:55]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[2]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[5]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[8]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[11]
TCPWM[0]16: TCPWM0_16_TR_OUT1[56:59]
PASS: PASS0_CH_TR_IN[0]
PASS: PASS0_CH_TR_IN[1]
PASS: PASS0_CH_TR_IN[2]
PASS: PASS0_CH_TR_IN[3]
PASS: PASS0_CH_TR_IN[4:31]
PASS: PASS0_CH_TR_IN[32]
PASS: PASS0_CH_TR_IN[33]
PASS: PASS0_CH_TR_IN[34]
PASS: PASS0_CH_TR_IN[35]
PASS: PASS0_CH_TR_IN[36:63]
PASS: PASS0_CH_TR_IN[64]
PASS: PASS0_CH_TR_IN[65]
PASS: PASS0_CH_TR_IN[66]
PASS: PASS0_CH_TR_IN[67]
PASS: PASS0_CH_TR_IN[68:71]
One-To-One TriggerGroupNr = 8
P-DMA1: PDMA1_TR_OUT[38]
P-DMA1: PDMA1_TR_OUT[41]
P-DMA1: PDMA1_TR_OUT[44]
P-DMA1: PDMA1_TR_OUT[47]
CAN[1]: CAN1_DBG_TR_ACK[0]
CAN[1]: CAN1_DBG_TR_ACK[1]
CAN[1]: CAN1_DBG_TR_ACK[2]
CAN[1]: CAN1_DBG_TR_ACK[3]
One-To-One TriggerGroupNr = 9
P-DMA0: PDMA0_TR_OUT[16]
P-DMA0: PDMA0_TR_OUT[19]
P-DMA0: PDMA0_TR_OUT[22]
P-DMA0: PDMA0_TR_OUT[25]
CAN[0]: CAN0_DBG_TR_ACK[0]
CAN[0]: CAN0_DBG_TR_ACK[1]
CAN[0]: CAN0_DBG_TR_ACK[2]
CAN[0]: CAN0_DBG_TR_ACK[3]
Figure 16-2
Triggers one-to-one[33]
Note
33.The diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula TRIG_{PREFIX(IN_1TO1/OUT_1-
TO1)}_{x}_{TRIG_LABEL} and the information provided in Table 19-1 on page 75.
Datasheet
69
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
17
Triggers group inputs
Table 17-1
Trigger inputs
Input
Trigger
Description
MUX Group 0: P-DMA0 trigger multiplexer
1:16[34]
17:32
33:40
41:44
45:48
49:64
65:68
PDMA0_TR_OUT[0:15]
PDMA1_TR_OUT[0:15]
MDMA_TR_OUT[0:7]
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
HSIOM_IO_INPUT[0:15]
FAULT_TR_OUT[0:3]
Allow P-DMA0 to chain to itself. Channels 0 - 15 are dedicated for chaining
Cross connections from P-DMA1 to P-DMA0, Channels 0-15 are used
Cross connections from M-DMA0 to P-DMA0
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
I/O Inputs
Fault events
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
1:30
TCPWM_16_TR_OUT0[0:29]
16-bit TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
32-bit TCPWM0 counters
PASS SAR events
31:42
43:50
51:56
57:58
59:62
TCPWM_16M_TR_OUT0[0:11]
TCPWM_32_TR_OUT0[0:7]
PASS_GEN_TR_OUT[0:5]
CTI_TR_OUT[0:1]
Trace events
EVTGEN_TR_OUT[0:3]
Event generator triggers
MUX Group 2: P-DMA1 trigger multiplexer
1:16
17:32
33:65
66:81
PDMA1_TR_OUT[0:15]
Allow P-DMA1 to chain to itself. Channels 0–15 are dedicated for chaining
Cross connections from P-DMA0 to P-DMA1, channels 0–15 are used
16-bit TCPWM0 counters
PDMA0_TR_OUT[0:15]
TCPWM_16_TR_OUT0[30:62]
HSIOM_IO_INPUT[16:31]
I/O Inputs
MUX Group 3: M-DMA0 trigger multiplexer
1:3
4:6
TCPWM_16_TR_OUT1[0:2]
TCPWM_16M_TR_OUT1[0:2]
16-bit TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
MUX Group 5: TCPWM0 Loop back trigger multiplexer
1:63
64:75
TCPWM_16_TR_OUT0[0:62]
TCPWM_16M_TR_OUT0[0:11]
TCPWM_32_TR_OUT0[0:7]
CAN0_DBG_TR_OUT[0:3]
CAN0_FIFO0_TR_OUT[0:3]
CAN0_FIFO1_TR_OUT[0:3]
CAN1_DBG_TR_OUT[0:3]
CAN1_FIFO0_TR_OUT[0:3]
CAN1_FIFO1_TR_OUT[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
EVTGEN_TR_OUT[4:11]
PDMA0_TR_OUT[0:15]
PDMA1_TR_OUT[0:15]
MDMA_TR_OUT[0:7]
16-bit TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
32-bit TCPWM0 counters
CAN0 M-DMA0 events
CAN0 FIFO0 events
76:83
84:87
88:91
92:95
CAN0 FIFO1 events
96:99
CAN1 M-DMA0 events
CAN1 FIFO0 events
100:103
104:107
108:111
112:115
116:123
124:139
140:155
156:163
164
CAN1 FIFO1 events
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
Event generator triggers
P-DMA0 general-purpose triggers
P-DMA1 general-purpose triggers
M-DMA0 events
SMIF_TX_TR_OUT
SMIF0 TX trigger
165
SMIF_RX_TR_OUT
SMIF0 RX trigger
166
I2S0_TX_TR_OUT
I2S0 TX trigger
167
I2S0_RX_TR_OUT
I2S0 RX trigger
Note
34.“x:y” depicts a range starting from ‘x’ through ‘y’.
Datasheet
70
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
Table 17-1
Trigger inputs (continued)
Input
Trigger
I2S1_TX_TR_OUT
Description
168
169
170
171
I2S1 TX trigger
I2S1 RX trigger
I2S2 TX trigger
I2S2 RX trigger
I2S1_RX_TR_OUT
I2S2_TX_TR_OUT
I2S2_RX_TR_OUT
MUX Group 6: TCPWM0 trigger Multiplexer
1:16
17
TCPWM_16_TR_OUT1[0:15]
16-bit TCPWM0 counters
SCB0 TX trigger
SCB0 RX trigger
SCB0 I2C trigger
SCB1 TX trigger
SCB1 RX trigger
SCB1 I2C trigger
SCB2 TX trigger
SCB2 RX trigger
SCB2 I2C trigger
SCB3 TX trigger
SCB3 RX trigger
SCB3 I2C trigger
SCB4 TX trigger
SCB4 RX trigger
SCB4 I2C trigger
SCB5 TX trigger
SCB5 RX trigger
SCB5 I2C trigger
SCB6 TX trigger
SCB6 RX trigger
SCB6 I2C trigger
SCB7 TX trigger
SCB7 RX trigger
SCB7 I2C trigger
SCB8 TX trigger
SCB8 RX trigger
SCB8 I2C trigger
SCB9 TX trigger
SCB9 RX trigger
SCB9 I2C trigger
SCB10 TX trigger
SCB10 RX trigger
SCB10 I2C trigger
PASS SAR events
I/O Inputs
SCB_TX_TR_OUT[0]
SCB_RX_TR_OUT[0]
SCB_I2C_SCL_TR_OUT[0]
SCB_TX_TR_OUT[1]
SCB_RX_TR_OUT[1]
SCB_I2C_SCL_TR_OUT[1]
SCB_TX_TR_OUT[2]
SCB_RX_TR_OUT[2]
SCB_I2C_SCL_TR_OUT[2]
SCB_TX_TR_OUT[3]
SCB_RX_TR_OUT[3]
SCB_I2C_SCL_TR_OUT[3]
SCB_TX_TR_OUT[4]
SCB_RX_TR_OUT[4]
SCB_I2C_SCL_TR_OUT[4]
SCB_TX_TR_OUT[5]
SCB_RX_TR_OUT[5]
SCB_I2C_SCL_TR_OUT[5]
SCB_TX_TR_OUT[6]
SCB_RX_TR_OUT[6]
SCB_I2C_SCL_TR_OUT[6]
SCB_TX_TR_OUT[7]
SCB_RX_TR_OUT[7]
SCB_I2C_SCL_TR_OUT[7]
SCB_TX_TR_OUT[8]
SCB_RX_TR_OUT[8]
SCB_I2C_SCL_TR_OUT[8]
SCB_TX_TR_OUT[9]
SCB_RX_TR_OUT[9]
SCB_I2C_SCL_TR_OUT[9]
SCB_TX_TR_OUT[10]
SCB_RX_TR_OUT[10]
SCB_I2C_SCL_TR_OUT[10]
PASS_GEN_TR_OUT[0:5]
HSIOM_IO_INPUT[0:31]
CTI_TR_IN[0:1]
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50:55
56:87
88:89
90:93
Trace events
FAULT_TR_OUT[0:3]
Fault events
MUX Group 7: PASS trigger multiplexer
1:16 PDMA0_TR_OUT[0:15]
General-purpose P-DMA0 triggers
Datasheet
71
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
Table 17-1
Trigger inputs (continued)
Input
Trigger
Description
16-bit Motor enhanced TCPWM0 counters
17:28
TCPWM_16M_TR_OUT0[0:11]
TCPWM_32_TR_OUT0[0:7]
TCPWM_16_TR_OUT1[60:61]
HSIOM_IO_INPUT[0:7]
29:36
32-bit TCPWM0 counters
16-bit TCPWM0 counters
I/O Inputs
37:38
39:46
47:49
EVTGEN_TR_OUT[12:14]
Event generator triggers
MUX Group 8: CAN TT Sync
1:4
CAN0_TT_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
5:8
MUX Group 9: Debug multiplexer
1:5
6:10
11:15
TR_GROUP10_OUTPUT[0:4]
TR_GROUP11_OUTPUT[0:4]
TR_GROUP12_OUTPUT[0:4]
Output from debug reduction multiplexer #1
Output from debug reduction multiplexer #2
Output from debug reduction multiplexer #3
MUX Group 10: Debug Reduction #1
1:100
PDMA0_TR_OUT[0:99]
General-purpose P-DMA0 triggers
SCB TX triggers
SCB RX triggers
SCB I2C triggers
CAN0 DMA
101:111
112:122
123:133
134:137
138:141
142:145
146:149
150:153
154:157
158:161
162:165
166:167
168:171
172:187
SCB_TX_TR_OUT[0:10]
SCB_RX_TR_OUT[0:10]
SCB_I2C_SCL_TR_OUT[0:10]
CAN0_DBG_TR_OUT[0:3]
CAN0_FIFO0_TR_OUT[0:3]
CAN0_FIFO1_TR_OUT[0:3]
CAN0_TT_TR_OUT[0:3]
CAN1_DBG_TR_OUT[0:3]
CAN1_FIFO0_TR_OUT[0:3]
CAN1_FIFO1_TR_OUT[0:3]
CAN1_TT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
CAN0 FIFO0
CAN0 FIFO1
CAN0 TT Sync Outputs
CAN1 DMA
CAN1 FIFO0
CAN1 FIFO1
CAN1 TT Sync Outputs
Trace events
FAULT_TR_OU[0:3]
Fault events
EVTGEN_TR_OUT[0:15]
EVTGEN Triggers
MUX Group 11: Debug Reduction #2
1:8
9:20
21:83
84
TCPWM_32_TR_OUT0[0:7]
32-bit TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
16-bit TCPWM0 counters
SMIF TX trigger
TCPWM_16M_TR_OUT0[0:11]
TCPWM_16_TR_OUT0[0:62]
SMIF_TX_TR_OUT
85
SMIF_RX_TR_OUT
SMIF RX trigger
86
I2S0_TX_TR_OUT
I2S0 TX trigger
87
I2S0_RX_TR_OUT
I2S0 RX trigger
88
I2S1_TX_TR_OUT
I2S1 TX trigger
89
I2S1_RX_TR_OUT
I2S1 RX trigger
90
I2S2_TX_TR_OUT
I2S2 TX trigger
91
I2S2_RX_TR_OUT
I2S2 RX trigger
92:123
HSIOM_IO_INPUT[0:31]
I/O inputs
MUX Group 12: Debug Reduction #3
1:58
59:66
67:129
PDMA1_TR_OUT[0:57]
General-purpose P-DMA1 triggers
M-DMA0 triggers
MDMA_TR_OUT[0:7]
TCPWM_16_TR_OUT1[0:62]
16-bit TCPWM0 counters
Datasheet
72
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group inputs
Table 17-1
Trigger inputs (continued)
Input
Trigger
Description
16-bit Motor enhanced TCPWM0 counters
130:141
142:149
150:155
TCPWM_16M_TR_OUT1[0:11]
TCPWM_32_TR_OUT1[0:7]
PASS_GEN_TR_OUT[0:5]
32-bit TCPWM0 counters
PASS SAR events
Datasheet
73
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers group outputs
18
Triggers group outputs
Table 18-1
Trigger outputs
Output
MUX Group 0: P-DMA0 trigger multiplexer
Trigger
Description
0:7
PDMA0_TR_IN[0:7]
Triggers to P-DMA0[0:7]
Triggers to P-DMA0[8:15]
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
0:7
PDMA0_TR_IN[8:15]
MUX Group 2: P-DMA1 trigger multiplexer
0:15
PDMA1_TR_IN[0:15]
Triggers to P-DMA1
Triggers to M-DMA0
Triggers to TCPWM0
Triggers to TCPWM0
Triggers to SAR ADCs
MUX Group 3: M-DMA0 trigger multiplexer
0:7
MDMA_TR_IN[0:7]
MUX Group 5: TCPWM0 loop-back multiplexer
0:11
TCPWM_ALL_CNT_TR_IN[0:11]
MUX Group 6: TCPWM0 Trigger Multiplexer
0:14
TCPWM_ALL_CNT_TR_IN[12:26]
MUX Group 7: PASS trigger multiplexer
0:11
PASS_GEN_TR_IN[0:11]
MUX Group 8: CAN TT Sync
0:3
4:7
CAN0_TT_TR_IN[0:3]
CAN1_TT_TR_IN[0:3]
CAN0 TT Sync Inputs
CAN1 TT Sync Inputs
MUX Group 9: Debug multiplexer
0
1
HSIOM_IO_OUTPUT[0]
To HSIOM as an output
To HSIOM as an output
HSIOM_IO_OUTPUT[1]
2:3
4
CTI_TR_IN[0:1]
To the Cross Trigger system
PERI_DEBUG_FREEZE_TR_IN
PASS_DEBUG_FREEZE_TR_IN
SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS_MCWDT_DEBUG_FREEZE_TR_IN[2]
SRSS_MCWDT_DEBUG_FREEZE_TR_IN[1]
SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0]
TCPWM_DEBUG_FREEZE_TR_IN
Signal to Freeze PERI operation
Signal to Freeze PASS operation
Signal to Freeze WDT operation
Signal to Freeze MCWDT2 operation
Signal to Freeze MCWDT1 operation
Signal to Freeze MCWDT0 operation
Signal to Freeze TCPWM0 operation
5
6
7
8
9
10
MUX Group 10: Debug Reduction #1
0:4
TR_GROUP9_INPUT[1:5]
To main debug multiplexer
To main debug multiplexer
To main debug multiplexer
MUX Group 11: Debug Reduction #2
0:4
TR_GROUP9_INPUT[6:10]
MUX Group 12: Debug Reduction #3
0:4
TR_GROUP9_INPUT[11:15]
Datasheet
74
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
19
Triggers one-to-one
Table 19-1
One-to-one triggers
Input
Trigger In
Trigger Out
Description
MUX Group 0: CAN0 to P-DMA0 Triggers
0
1
CAN0_DBG_TR_OUT[0]
PDMA0_TR_IN[16]
CAN0, Channel #0 P-DMA0 trigger
CAN0_FIFO0_TR_OUT[0]
CAN0_FIFO1_TR_OUT[0]
CAN0_DBG_TR_OUT[1]
CAN0_FIFO0_TR_OUT[1]
CAN0_FIFO1_TR_OUT[1]
CAN0_DBG_TR_OUT[2]
CAN0_FIFO0_TR_OUT[2]
CAN0_FIFO1_TR_OUT[2]
CAN0_DBG_TR_OUT[3]
CAN0_FIFO0_TR_OUT[3]
CAN0_FIFO1_TR_OUT[3]
PDMA0_TR_IN[17]
PDMA0_TR_IN[18]
PDMA0_TR_IN[19]
PDMA0_TR_IN[20]
PDMA0_TR_IN[21]
PDMA0_TR_IN[22]
PDMA0_TR_IN[23]
PDMA0_TR_IN[24]
PDMA0_TR_IN[25]
PDMA0_TR_IN[26]
PDMA0_TR_IN[27]
CAN0, Channel #0 FIFO0 trigger
CAN0, Channel #0 FIFO1 trigger
CAN0, Channel #1 P-DMA0 trigger
CAN0, Channel #1 FIFO0 trigger
CAN0, Channel #1 FIFO1 trigger
CAN0, Channel #2 P-DMA0 trigger
CAN0, Channel #2 FIFO0 trigger
CAN0, Channel #2 FIFO1 trigger
CAN0, Channel #3 P-DMA0 trigger
CAN0, Channel #3 FIFO0 trigger
CAN0, Channel #3 FIFO1 trigger
2
3
4
5
6
7
8
9
10
11
MUX Group 1: PASS SARx to P-DMA0 direct connect
0:31
32:63
64:71
PASS0_CH_DONE_TR_OUT[0:31]
PASS0_CH_DONE_TR_OUT[32:63]
PASS0_CH_DONE_TR_OUT[64:71]
PDMA0_TR_IN[28:59]
PDMA0_TR_IN[60:91]
PDMA0_TR_IN[92:99]
PASS SAR0 [0:31] to P-DMA0 direct connect
PASS SAR1 [0:31] to P-DMA0 direct connect
PASS SAR2 [0:7] to P-DMA0 direct connect
MUX Group 2: SCBx to P-DMA1 Triggers
0
1
SCB0_TX_TR_OUT
SCB0_RX_TR_OUT
SCB1_TX_TR_OUT
SCB1_RX_TR_OUT
SCB2_TX_TR_OUT
SCB2_RX_TR_OUT
SCB3_TX_TR_OUT
SCB3_RX_TR_OUT
SCB4_TX_TR_OUT
SCB4_RX_TR_OUT
SCB5_TX_TR_OUT
SCB5_RX_TR_OUT
SCB6_TX_TR_OUT
SCB6_RX_TR_OUT
SCB7_TX_TR_OUT
SCB7_RX_TR_OUT
SCB8_TX_TR_OUT
SCB8_RX_TR_OUT
SCB9_TX_TR_OUT
SCB9_RX_TR_OUT
SCB10_TX_TR_OUT
SCB10_RX_TR_OUT
PDMA1_TR_IN[16]
PDMA1_TR_IN[17]
PDMA1_TR_IN[18]
PDMA1_TR_IN[19]
PDMA1_TR_IN[20]
PDMA1_TR_IN[21]
PDMA1_TR_IN[22]
PDMA1_TR_IN[23]
PDMA1_TR_IN[24]
PDMA1_TR_IN[25]
PDMA1_TR_IN[26]
PDMA1_TR_IN[27]
PDMA1_TR_IN[28]
PDMA1_TR_IN[29]
PDMA1_TR_IN[30]
PDMA1_TR_IN[31]
PDMA1_TR_IN[32]
PDMA1_TR_IN[33]
PDMA1_TR_IN[34]
PDMA1_TR_IN[35]
PDMA1_TR_IN[36]
PDMA1_TR_IN[37]
SCB0 to P-DMA1 Trigger
SCB0 to P-DMA1 Trigger
SCB1 to P-DMA1 Trigger
SCB1 to P-DMA1 Trigger
SCB2 to P-DMA1 Trigger
SCB2 to P-DMA1 Trigger
SCB3 to P-DMA1 Trigger
SCB3 to P-DMA1 Trigger
SCB4 to P-DMA1 Trigger
SCB4 to P-DMA1 Trigger
SCB5 to P-DMA1 Trigger
SCB5 to P-DMA1 Trigger
SCB6 to P-DMA1 Trigger
SCB6 to P-DMA1 Trigger
SCB7 to P-DMA1 Trigger
SCB7 to P-DMA1 Trigger
SCB8 to P-DMA1 Trigger
SCB8 to P-DMA1 Trigger
SCB9 to P-DMA1 Trigger
SCB9 to P-DMA1 Trigger
SCB10 to P-DMA1 Trigger
SCB10 to P-DMA1 Trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MUX Group 3: SMIF0 to P-DMA1 Triggers
0
1
SMIF_TX_TR_OUT
SMIF_RX_TR_OUT
PDMA1_TR_IN[50]
PDMA1_TR_IN[51]
SMIF0 to P-DMA1 Trigger
SMIF0 to P-DMA1 Trigger
MUX Group 4: CAN1 to P-DMA1 triggers
0
1
2
3
CAN1_DBG_TR_OUT[0]
PDMA1_TR_IN[38]
PDMA1_TR_IN[39]
PDMA1_TR_IN[40]
PDMA1_TR_IN[41]
CAN1 Channel #0 P-DMA1 trigger
CAN1 Channel #0 FIFO0 trigger
CAN1 Channel #0 FIFO1 trigger
CAN1 Channel #1 P-DMA1 trigger
CAN1_FIFO0_TR_OUT[0]
CAN1_FIFO1_TR_OUT[0]
CAN1_DBG_TR_OUT[1]
Datasheet
75
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
Table 19-1
One-to-one triggers (continued)
Input
Trigger In
CAN1_FIFO0_TR_OUT[1]
CAN1_FIFO1_TR_OUT[1]
CAN1_DBG_TR_OUT[2]
CAN1_FIFO0_TR_OUT[2]
CAN1_FIFO1_TR_OUT[2]
CAN1_DBG_TR_OUT[3]
CAN1_FIFO0_TR_OUT[3]
CAN1_FIFO1_TR_OUT[3]
Trigger Out
Description
CAN1 Channel #1 FIFO0 trigger
4
5
PDMA1_TR_IN[42]
PDMA1_TR_IN[43]
PDMA1_TR_IN[44]
PDMA1_TR_IN[45]
PDMA1_TR_IN[46]
PDMA1_TR_IN[47]
PDMA1_TR_IN[48]
PDMA1_TR_IN[49]
CAN1 Channel #1 FIFO1 trigger
CAN1 Channel #2 P-DMA1 trigger
CAN1 Channel #2 FIFO0 trigger
CAN1 Channel #2 FIFO1 trigger
CAN1 Channel #3 P-DMA1 trigger
CAN1 Channel #3 FIFO0 trigger
CAN1 Channel #3 FIFO1 trigger
6
7
8
9
10
11
2
MUX Group 5: I Sx to P-DMA1 Triggers
2
0
1
2
3
4
5
AUDIO0_TX_TR_OUT
PDMA1_TR_IN[52]
PDMA1_TR_IN[53]
PDMA1_TR_IN[54]
PDMA1_TR_IN[55]
PDMA1_TR_IN[56]
PDMA1_TR_IN[57]
I S0 TX to P-DMA1 trigger
2
AUDIO0_RX_TR_OUT
AUDIO1_TX_TR_OUT
AUDIO1_RX_TR_OUT
AUDIO2_TX_TR_OUT
AUDIO2_RX_TR_OUT
I S0 RX to P-DMA1 trigger
2
I S1 TX to P-DMA1 trigger
2
I S1 RX to P-DMA1 trigger
2
I S2 TX to P-DMA1 trigger
2
I S2 RX to P-DMA1 trigger
MUX Group 6: PASS SARx to TCPWM0 direct connect
[35]
0
PASS0_CH_RANGEVIO_TR_OUT[0]
PASS0_CH_RANGEVIO_TR_OUT[1]
PASS0_CH_RANGEVIO_TR_OUT[2]
PASS0_CH_RANGEVIO_TR_OUT[3]
PASS0_CH_RANGEVIO_TR_OUT[4]
PASS0_CH_RANGEVIO_TR_OUT[5]
PASS0_CH_RANGEVIO_TR_OUT[6]
PASS0_CH_RANGEVIO_TR_OUT[7]
PASS0_CH_RANGEVIO_TR_OUT[8]
PASS0_CH_RANGEVIO_TR_OUT[9]
PASS0_CH_RANGEVIO_TR_OUT[10]
PASS0_CH_RANGEVIO_TR_OUT[11]
PASS0_CH_RANGEVIO_TR_OUT[12]
PASS0_CH_RANGEVIO_TR_OUT[13]
PASS0_CH_RANGEVIO_TR_OUT[14]
PASS0_CH_RANGEVIO_TR_OUT[15]
PASS0_CH_RANGEVIO_TR_OUT[16]
PASS0_CH_RANGEVIO_TR_OUT[17]
PASS0_CH_RANGEVIO_TR_OUT[18]
PASS0_CH_RANGEVIO_TR_OUT[19]
PASS0_CH_RANGEVIO_TR_OUT[20]
PASS0_CH_RANGEVIO_TR_OUT[21]
TCPWM0_16M_ONE_CNT_TR_IN[0]
TCPWM0_16M_ONE_CNT_TR_IN[3]
TCPWM0_16M_ONE_CNT_TR_IN[6]
TCPWM0_16M_ONE_CNT_TR_IN[9]
TCPWM0_16_ONE_CNT_TR_IN[0]
TCPWM0_16_ONE_CNT_TR_IN[1]
TCPWM0_16_ONE_CNT_TR_IN[2]
TCPWM0_16_ONE_CNT_TR_IN[3]
TCPWM0_16_ONE_CNT_TR_IN[4]
TCPWM0_16_ONE_CNT_TR_IN[5]
TCPWM0_16_ONE_CNT_TR_IN[6]
TCPWM0_16_ONE_CNT_TR_IN[7]
TCPWM0_16_ONE_CNT_TR_IN[8]
TCPWM0_16_ONE_CNT_TR_IN[9]
TCPWM0_16_ONE_CNT_TR_IN[10]
TCPWM0_16_ONE_CNT_TR_IN[11]
TCPWM0_16_ONE_CNT_TR_IN[12]
TCPWM0_16_ONE_CNT_TR_IN[13]
TCPWM0_16_ONE_CNT_TR_IN[14]
TCPWM0_16_ONE_CNT_TR_IN[15]
TCPWM0_16_ONE_CNT_TR_IN[16]
TCPWM0_16_ONE_CNT_TR_IN[17]
SAR0 ch#0 , range violation to TCPWM0 Group #1 Counter #00
trig = 2
1
SAR0 ch#1, range violation to TCPWM0 Group #1 Counter #03 trig
= 2
2
SAR0 ch#2, range violation to TCPWM0 Group #1 Counter #06 trig
= 2
3
SAR0 ch#3, range violation to TCPWM0 Group #1 Counter #09 trig
= 2
4
SAR0 ch#4, range violation to TCPWM0 Group #0 Counter #00 trig
= 2
5
SAR0 ch#5, range violation to TCPWM0 Group #0 Counter #01 trig
= 2
6
SAR0 ch#6, range violation to TCPWM0 Group #0 Counter #02 trig
= 2
7
SAR0 ch#7, range violation to TCPWM0 Group #0 Counter #03 trig
= 2
8
SAR0 ch#8, range violation to TCPWM0 Group #0 Counter #04 trig
= 2
9
SAR0 ch#9, range violation to TCPWM0 Group #0 Counter #05 trig
= 2
10
11
12
13
14
15
16
17
18
19
20
21
SAR0 ch#10, range violation to TCPWM0 Group #0 Counter #06
trig = 2
SAR0 ch#11, range violation to TCPWM0 Group #0 Counter #07
trig = 2
SAR0 ch#12, range violation to TCPWM0 Group #0 Counter #08
trig = 2
SAR0 ch#13, range violation to TCPWM0 Group #0 Counter #09
trig = 2
SAR0 ch#14, range violation to TCPWM0 Group #0 Counter #10
trig = 2
SAR0 ch#15, range violation to TCPWM0 Group #0 Counter #11
trig = 2
SAR0 ch#16, range violation to TCPWM0 Group #0 Counter #12
trig = 2
SAR0 ch#17, range violation to TCPWM0 Group #0 Counter #13
trig = 2
SAR0 ch#18, range violation to TCPWM0 Group #0 Counter #14
trig = 2
SAR0 ch#19, range violation to TCPWM0 Group #0 Counter #15
trig = 2
SAR0 ch#20, range violation to TCPWM0 Group #0 Counter #16
trig = 2
SAR0 ch#21, range violation to TCPWM0 Group #0 Counter #17
trig = 2
Note
35.Each logical channel of SAR ADC[x] can be connected to any of the SAR ADC[x]_y external pin. (x = 0, or 1, or, 2 and y=0 to 31).
Datasheet
76
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
Table 19-1
One-to-one triggers (continued)
Input
Trigger In
Trigger Out
Description
22
PASS0_CH_RANGEVIO_TR_OUT[22]
TCPWM0_16_ONE_CNT_TR_IN[18]
SAR0 ch#22, range violation to TCPWM0 Group #0 Counter #18
trig = 2
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
PASS0_CH_RANGEVIO_TR_OUT[23]
PASS0_CH_RANGEVIO_TR_OUT[24]
PASS0_CH_RANGEVIO_TR_OUT[25]
PASS0_CH_RANGEVIO_TR_OUT[26]
PASS0_CH_RANGEVIO_TR_OUT[27]
PASS0_CH_RANGEVIO_TR_OUT[28]
PASS0_CH_RANGEVIO_TR_OUT[29]
PASS0_CH_RANGEVIO_TR_OUT[30]
PASS0_CH_RANGEVIO_TR_OUT[31]
PASS0_CH_RANGEVIO_TR_OUT[32]
PASS0_CH_RANGEVIO_TR_OUT[33]
PASS0_CH_RANGEVIO_TR_OUT[34]
PASS0_CH_RANGEVIO_TR_OUT[35]
PASS0_CH_RANGEVIO_TR_OUT[36]
PASS0_CH_RANGEVIO_TR_OUT[37]
PASS0_CH_RANGEVIO_TR_OUT[38]
PASS0_CH_RANGEVIO_TR_OUT[39]
PASS0_CH_RANGEVIO_TR_OUT[40]
PASS0_CH_RANGEVIO_TR_OUT[41]
PASS0_CH_RANGEVIO_TR_OUT[42]
PASS0_CH_RANGEVIO_TR_OUT[43]
PASS0_CH_RANGEVIO_TR_OUT[44]
PASS0_CH_RANGEVIO_TR_OUT[45]
PASS0_CH_RANGEVIO_TR_OUT[46]
PASS0_CH_RANGEVIO_TR_OUT[47]
PASS0_CH_RANGEVIO_TR_OUT[48]
PASS0_CH_RANGEVIO_TR_OUT[49]
PASS0_CH_RANGEVIO_TR_OUT[50]
PASS0_CH_RANGEVIO_TR_OUT[51]
PASS0_CH_RANGEVIO_TR_OUT[52]
PASS0_CH_RANGEVIO_TR_OUT[53]
PASS0_CH_RANGEVIO_TR_OUT[54]
PASS0_CH_RANGEVIO_TR_OUT[55]
TCPWM0_16_ONE_CNT_TR_IN[19]
TCPWM0_16_ONE_CNT_TR_IN[20]
TCPWM0_16_ONE_CNT_TR_IN[21]
TCPWM0_16_ONE_CNT_TR_IN[22]
TCPWM0_16_ONE_CNT_TR_IN[23]
TCPWM0_16_ONE_CNT_TR_IN[24]
TCPWM0_16_ONE_CNT_TR_IN[25]
TCPWM0_16_ONE_CNT_TR_IN[26]
TCPWM0_16_ONE_CNT_TR_IN[27]
TCPWM0_16M_ONE_CNT_TR_IN[1]
TCPWM0_16M_ONE_CNT_TR_IN[4]
TCPWM0_16M_ONE_CNT_TR_IN[7]
TCPWM0_16M_ONE_CNT_TR_IN[10]
TCPWM0_16_ONE_CNT_TR_IN[28]
TCPWM0_16_ONE_CNT_TR_IN[29]
TCPWM0_16_ONE_CNT_TR_IN[30]
TCPWM0_16_ONE_CNT_TR_IN[31]
TCPWM0_16_ONE_CNT_TR_IN[32]
TCPWM0_16_ONE_CNT_TR_IN[33]
TCPWM0_16_ONE_CNT_TR_IN[34]
TCPWM0_16_ONE_CNT_TR_IN[35]
TCPWM0_16_ONE_CNT_TR_IN[36]
TCPWM0_16_ONE_CNT_TR_IN[37]
TCPWM0_16_ONE_CNT_TR_IN[38]
TCPWM0_16_ONE_CNT_TR_IN[39]
TCPWM0_16_ONE_CNT_TR_IN[40]
TCPWM0_16_ONE_CNT_TR_IN[41]
TCPWM0_16_ONE_CNT_TR_IN[42]
TCPWM0_16_ONE_CNT_TR_IN[43]
TCPWM0_16_ONE_CNT_TR_IN[44]
TCPWM0_16_ONE_CNT_TR_IN[45]
TCPWM0_16_ONE_CNT_TR_IN[46]
TCPWM0_16_ONE_CNT_TR_IN[47]
SAR0 ch#23, range violation to TCPWM0 Group #0 Counter #19
trig = 2
SAR0 ch#24, range violation to TCPWM0 Group #0 Counter #20
trig = 2
SAR0 ch#25, range violation to TCPWM0 Group #0 Counter #21
trig = 2
SAR0 ch#26, range violation to TCPWM0 Group #0 Counter #22
trig = 2
SAR0 ch#27, range violation to TCPWM0 Group #0 Counter #23
trig = 2
SAR0 ch#28, range violation to TCPWM0 Group #0 Counter #24
trig = 2
SAR0 ch#29, range violation to TCPWM0 Group #0 Counter #25
trig = 2
SAR0 ch#30, range violation to TCPWM0 Group #0 Counter #26
trig = 2
SAR0 ch#31, range violation to TCPWM0 Group #0 Counter #27
trig = 2
SAR1 ch#0, range violation to TCPWM0 Group #1 Counter #01 trig
= 2
SAR1 ch#1, range violation to TCPWM0 Group #1 Counter #04 trig
= 2
SAR1 ch#2, range violation to TCPWM0 Group #1 Counter #07 trig
= 2
SAR1 ch#3, range violation to TCPWM0 Group #1 Counter #10 trig
= 2
SAR1 ch#4, range violation to TCPWM0 Group #0 Counter #28 trig
= 2
SAR1 ch#5, range violation to TCPWM0 Group #0 Counter #29 trig
= 2
SAR1 ch#6, range violation to TCPWM0 Group #0 Counter #30 trig
= 2
SAR1 ch#7, range violation to TCPWM0 Group #0 Counter #31 trig
= 2
SAR1 ch#8, range violation to TCPWM0 Group #0 Counter #32 trig
= 2
SAR1 ch#9, range violation to TCPWM0 Group #0 Counter #33 trig
= 2
SAR1 ch#10, range violation to TCPWM0 Group #0 Counter #34
trig = 2
SAR1 ch#11, range violation to TCPWM0 Group #0 Counter #35
trig = 2
SAR1 ch#12, range violation to TCPWM0 Group #0 Counter #36
trig = 2
SAR1 ch#13, range violation to TCPWM0 Group #0 Counter #37
trig = 2
SAR1 ch#14, range violation to TCPWM0 Group #0 Counter #38
trig = 2
SAR1 ch#15, range violation to TCPWM0 Group #0 Counter #39
trig = 2
SAR1 ch#16, range violation to TCPWM0 Group #0 Counter #40
trig = 2
SAR1 ch#17, range violation to TCPWM0 Group #0 Counter #41
trig = 2
SAR1 ch#18, range violation to TCPWM0 Group #0 Counter #42
trig = 2
SAR1 ch#19, range violation to TCPWM0 Group #0 Counter #43
trig = 2
SAR1 ch#20, range violation to TCPWM0 Group #0 Counter #44
trig = 2
SAR1 ch#21, range violation to TCPWM0 Group #0 Counter #45
trig = 2
SAR1 ch#22, range violation to TCPWM0 Group #0 Counter #46
trig = 2
SAR1 ch#23, range violation to TCPWM0 Group #0 Counter #47
trig = 2
Datasheet
77
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Triggers one-to-one
Table 19-1
One-to-one triggers (continued)
Input
Trigger In
Trigger Out
Description
56
PASS0_CH_RANGEVIO_TR_OUT[56]
TCPWM0_16_ONE_CNT_TR_IN[48]
SAR1 ch#24, range violation to TCPWM0 Group #0 Counter #48
trig = 2
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
PASS0_CH_RANGEVIO_TR_OUT[57]
PASS0_CH_RANGEVIO_TR_OUT[58]
PASS0_CH_RANGEVIO_TR_OUT[59]
PASS0_CH_RANGEVIO_TR_OUT[60]
PASS0_CH_RANGEVIO_TR_OUT[61]
PASS0_CH_RANGEVIO_TR_OUT[62]
PASS0_CH_RANGEVIO_TR_OUT[63]
PASS0_CH_RANGEVIO_TR_OUT[64]
PASS0_CH_RANGEVIO_TR_OUT[65]
PASS0_CH_RANGEVIO_TR_OUT[66]
PASS0_CH_RANGEVIO_TR_OUT[67]
PASS0_CH_RANGEVIO_TR_OUT[68]
PASS0_CH_RANGEVIO_TR_OUT[69]
PASS0_CH_RANGEVIO_TR_OUT[70]
PASS0_CH_RANGEVIO_TR_OUT[71]
TCPWM0_16_ONE_CNT_TR_IN[49]
TCPWM0_16_ONE_CNT_TR_IN[50]
TCPWM0_16_ONE_CNT_TR_IN[51]
TCPWM0_16_ONE_CNT_TR_IN[52]
TCPWM0_16_ONE_CNT_TR_IN[53]
TCPWM0_16_ONE_CNT_TR_IN[54]
TCPWM0_16_ONE_CNT_TR_IN[55]
TCPWM0_16M_ONE_CNT_TR_IN[2]
TCPWM0_16M_ONE_CNT_TR_IN[5]
TCPWM0_16M_ONE_CNT_TR_IN[8]
TCPWM0_16M_ONE_CNT_TR_IN[11]
TCPWM0_16_ONE_CNT_TR_IN[56]
TCPWM0_16_ONE_CNT_TR_IN[57]
TCPWM0_16_ONE_CNT_TR_IN[58]
TCPWM0_16_ONE_CNT_TR_IN[59]
SAR1 ch#25, range violation to TCPWM0 Group #0 Counter #49
trig = 2
SAR1 ch#26, range violation to TCPWM0 Group #0 Counter #50
trig = 2
SAR1 ch#27, range violation to TCPWM0 Group #0 Counter #51
trig = 2
SAR1 ch#28, range violation to TCPWM0 Group #0 Counter #52
trig = 2
SAR1 ch#29, range violation to TCPWM0 Group #0 Counter #53
trig = 2
SAR1 ch#30, range violation to TCPWM0 Group #0 Counter #54
trig = 2
SAR1 ch#31, range violation to TCPWM0 Group #0 Counter #55
trig = 2
SAR2 ch#0, range violation to TCPWM0 Group #1 Counter #02 trig
= 2
SAR2 ch#1, range violation to TCPWM0 Group #1 Counter #05 trig
= 2
SAR2 ch#2, range violation to TCPWM0 Group #1 Counter #08 trig
= 2
SAR2 ch#3, range violation to TCPWM0 Group #1 Counter #11 trig
= 2
SAR2 ch#4, range violation to TCPWM0 Group #0 Counter #56 trig
= 2
SAR2 ch#5, range violation to TCPWM0 Group #0 Counter #57 trig
= 2
SAR2 ch#6, range violation to TCPWM0 Group #0 Counter #58 trig
= 2
SAR2 ch#7, range violation to TCPWM0 Group #0 Counter #59 trig
= 2
MUX Group 7: TCPWM0 to PASS SARx
0
1
TCPWM0_16M_TR_OUT1[0]
PASS0_CH_TR_IN[0]
PASS0_CH_TR_IN[1]
PASS0_CH_TR_IN[2]
PASS0_CH_TR_IN[3]
PASS0_CH_TR_IN[4:31]
TCPWM0 Group #1 Counter #00 (PWM0_M_0) to SAR0 ch#0
TCPWM0 Group #1 Counter #03 (PWM0_M_3) to SAR0 ch#1
TCPWM0 Group #1 Counter #06 (PWM0_M_6) to SAR0 ch#2
TCPWM0 Group #1 Counter #09 (PWM0_M_9) to SAR0 ch#3
TCPWM0_16M_TR_OUT1[3]
TCPWM0_16M_TR_OUT1[6]
TCPWM0_16M_TR_OUT1[9]
TCPWM0_16_TR_OUT1[0:27]
2
3
4:31
TCPWM0 Group #0 Counter #00 through 27 (PWM0_0 to
PWM0_27) to SAR0 ch#4 through SAR0 ch#31
32
33
TCPWM0_16M_TR_OUT1[1]
TCPWM0_16M_TR_OUT1[4]
TCPWM0_16M_TR_OUT1[7]
TCPWM0_16M_TR_OUT1[10]
TCPWM0_16_TR_OUT1[28:55]
PASS0_CH_TR_IN[32]
PASS0_CH_TR_IN[33]
PASS0_CH_TR_IN[34]
PASS0_CH_TR_IN[35]
PASS0_CH_TR_IN[36:63]
TCPWM0 Group #1 Counter #01 (PWM0_M_1) to SAR1 ch#0
TCPWM0 Group #1 Counter #04 (PWM0_M_4) to SAR1 ch#1
TCPWM0 Group #1 Counter #07 (PWM0_M_7) to SAR1 ch#2
TCPWM0 Group #1 Counter #10 (PWM0_M_10) to SAR1 ch#3
34
35
36:63
TCPWM0 Group #0 Counter #28 through 55 (PWM0_28 to
PWM0_55) to SAR1 ch#4 through SAR1 ch#31
64
65
TCPWM0_16M_TR_OUT1[2]
TCPWM0_16M_TR_OUT1[5]
TCPWM0_16M_TR_OUT1[8]
TCPWM0_16M_TR_OUT1[11]
TCPWM0_16_TR_OUT1[56:59]
PASS0_CH_TR_IN[64]
PASS0_CH_TR_IN[65]
PASS0_CH_TR_IN[66]
PASS0_CH_TR_IN[67]
PASS0_CH_TR_IN[68:71]
TCPWM0 Group #1 Counter #02 (PWM0_M_2) to SAR2 ch#0
TCPWM0 Group #1 Counter #05 (PWM0_M_5) to SAR2 ch#1
TCPWM0 Group #1 Counter #08 (PWM0_M_8) to SAR2 ch#2
TCPWM0 Group #1 Counter #11 (PWM0_M_11) to SAR2 ch#3
66
67
68:71
TCPWM0 Group #1 Counter #56 through 59 (PWM0_56 to
PWM0_59) to SAR2 ch#4 through SAR2 ch#7
MUX Group 8: Acknowledge triggers from P-DMA1 to CAN1
0
1
2
3
PDMA1_TR_OUT[38]
PDMA1_TR_OUT[41]
PDMA1_TR_OUT[44]
PDMA1_TR_OUT[47]
CAN1_DBG_TR_ACK[0]
CAN1_DBG_TR_ACK[1]
CAN1_DBG_TR_ACK[2]
CAN1_DBG_TR_ACK[3]
CAN1 Channel#0 P-DMA1 acknowledge
CAN1 Channel#1 P-DMA1 acknowledge
CAN1 Channel#2 P-DMA1 acknowledge
CAN1 Channel#3 P-DMA1 acknowledge
MUX Group 9: Acknowledge triggers from P-DMA0 to CAN0
0
1
2
3
PDMA0_TR_OUT[32]
PDMA0_TR_OUT[35]
PDMA0_TR_OUT[38]
PDMA0_TR_OUT[41]
CAN0_DBG_TR_ACK[0]
CAN0_DBG_TR_ACK[1]
CAN0_DBG_TR_ACK[2]
CAN0_DBG_TR_ACK[3]
CAN0 Channel#0 P-DMA0 acknowledge
CAN0 Channel#1 P-DMA0 acknowledge
CAN0 Channel#2 P-DMA0 acknowledge
CAN0 Channel#3 P-DMA0 acknowledge
Datasheet
78
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral clocks
20
Peripheral clocks
Table 20-1
Peripheral clock assignments
Output
Destination
Description
CPUSS Root Clocks (Group 0)
0
1
2
3
4
5
PCLK_CPUSS_CLOCK_TRACE_IN
Trace clock
PCLK_SMARTIO12_CLOCK
PCLK_SMARTIO13_CLOCK
PCLK_SMARTIO14_CLOCK
PCLK_SMARTIO15_CLOCK
PCLK_SMARTIO17_CLOCK
Smart I/O #12
Smart I/O #13
Smart I/O #14
Smart I/O #15
Smart I/O #17
COMM Root Clocks (Group 1)
0
1
PCLK_CANFD0_CLOCK_CAN0
CAN0, Channel #0
CAN0, Channel #1
CAN0, Channel #2
CAN0, Channel #3
CAN1, Channel #0
CAN1, Channel #1
CAN1, Channel #2
CAN1, Channel #3
Reserved for future use
SCB0
PCLK_CANFD0_CLOCK_CAN1
PCLK_CANFD0_CLOCK_CAN2
PCLK_CANFD0_CLOCK_CAN3
PCLK_CANFD1_CLOCK_CAN0
PCLK_CANFD1_CLOCK_CAN1
PCLK_CANFD1_CLOCK_CAN2
PCLK_CANFD1_CLOCK_CAN3
Reserve
2
3
4
5
6
7
8 - 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
PCLK_SCB0_CLOCK
PCLK_SCB1_CLOCK
SCB1
PCLK_SCB2_CLOCK
SCB2
PCLK_SCB3_CLOCK
SCB3
PCLK_SCB4_CLOCK
SCB4
PCLK_SCB5_CLOCK
SCB5
PCLK_SCB6_CLOCK
SCB6
PCLK_SCB7_CLOCK
SCB7
PCLK_SCB8_CLOCK
SCB8
PCLK_SCB9_CLOCK
SCB9
PCLK_SCB10_CLOCK
SCB10
PCLK_PASS0_CLOCK_SAR0
PCLK_PASS0_CLOCK_SAR1
PCLK_PASS0_CLOCK_SAR2
PCLK_TCPWM0_CLOCKS0
PCLK_TCPWM0_CLOCKS1
PCLK_TCPWM0_CLOCKS2
PCLK_TCPWM0_CLOCKS3
PCLK_TCPWM0_CLOCKS4
PCLK_TCPWM0_CLOCKS5
PCLK_TCPWM0_CLOCKS6
PCLK_TCPWM0_CLOCKS7
PCLK_TCPWM0_CLOCKS8
PCLK_TCPWM0_CLOCKS9
PCLK_TCPWM0_CLOCKS10
PCLK_TCPWM0_CLOCKS11
SAR0
SAR1
SAR2
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #3
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
TCPWM0 Group #0, Counter #8
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
Datasheet
79
002-33896 Rev. *A
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral clocks
Table 20-1
Peripheral clock assignments (continued)
Output
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Destination
PCLK_TCPWM0_CLOCKS12
Description
TCPWM0 Group #0, Counter #12
PCLK_TCPWM0_CLOCKS13
PCLK_TCPWM0_CLOCKS14
PCLK_TCPWM0_CLOCKS15
PCLK_TCPWM0_CLOCKS16
PCLK_TCPWM0_CLOCKS17
PCLK_TCPWM0_CLOCKS18
PCLK_TCPWM0_CLOCKS19
PCLK_TCPWM0_CLOCKS20
PCLK_TCPWM0_CLOCKS21
PCLK_TCPWM0_CLOCKS22
PCLK_TCPWM0_CLOCKS23
PCLK_TCPWM0_CLOCKS24
PCLK_TCPWM0_CLOCKS25
PCLK_TCPWM0_CLOCKS26
PCLK_TCPWM0_CLOCKS27
PCLK_TCPWM0_CLOCKS28
PCLK_TCPWM0_CLOCKS29
PCLK_TCPWM0_CLOCKS30
PCLK_TCPWM0_CLOCKS31
PCLK_TCPWM0_CLOCKS32
PCLK_TCPWM0_CLOCKS33
PCLK_TCPWM0_CLOCKS34
PCLK_TCPWM0_CLOCKS35
PCLK_TCPWM0_CLOCKS36
PCLK_TCPWM0_CLOCKS37
PCLK_TCPWM0_CLOCKS38
PCLK_TCPWM0_CLOCKS39
PCLK_TCPWM0_CLOCKS40
PCLK_TCPWM0_CLOCKS41
PCLK_TCPWM0_CLOCKS42
PCLK_TCPWM0_CLOCKS43
PCLK_TCPWM0_CLOCKS44
PCLK_TCPWM0_CLOCKS45
PCLK_TCPWM0_CLOCKS46
PCLK_TCPWM0_CLOCKS47
PCLK_TCPWM0_CLOCKS48
PCLK_TCPWM0_CLOCKS49
PCLK_TCPWM0_CLOCKS50
PCLK_TCPWM0_CLOCKS51
PCLK_TCPWM0_CLOCKS52
PCLK_TCPWM0_CLOCKS53
PCLK_TCPWM0_CLOCKS54
PCLK_TCPWM0_CLOCKS55
PCLK_TCPWM0_CLOCKS56
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #27
TCPWM0 Group #0, Counter #28
TCPWM0 Group #0, Counter #29
TCPWM0 Group #0, Counter #30
TCPWM0 Group #0, Counter #31
TCPWM0 Group #0, Counter #32
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #35
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #43
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
TCPWM0 Group #0, Counter #56
Datasheet
80
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral clocks
Table 20-1
Peripheral clock assignments (continued)
Output
95
Destination
PCLK_TCPWM0_CLOCKS57
Description
TCPWM0 Group #0, Counter #57
96
PCLK_TCPWM0_CLOCKS58
PCLK_TCPWM0_CLOCKS59
PCLK_TCPWM0_CLOCKS60
PCLK_TCPWM0_CLOCKS61
PCLK_TCPWM0_CLOCKS62
PCLK_TCPWM0_CLOCKS256
PCLK_TCPWM0_CLOCKS257
PCLK_TCPWM0_CLOCKS258
PCLK_TCPWM0_CLOCKS259
PCLK_TCPWM0_CLOCKS260
PCLK_TCPWM0_CLOCKS261
PCLK_TCPWM0_CLOCKS262
PCLK_TCPWM0_CLOCKS263
PCLK_TCPWM0_CLOCKS264
PCLK_TCPWM0_CLOCKS265
PCLK_TCPWM0_CLOCKS266
PCLK_TCPWM0_CLOCKS267
PCLK_TCPWM0_CLOCKS512
PCLK_TCPWM0_CLOCKS513
PCLK_TCPWM0_CLOCKS514
PCLK_TCPWM0_CLOCKS515
PCLK_TCPWM0_CLOCKS516
PCLK_TCPWM0_CLOCKS517
PCLK_TCPWM0_CLOCKS518
PCLK_TCPWM0_CLOCKS519
TCPWM0 Group #0, Counter #58
TCPWM0 Group #0, Counter #59
TCPWM0 Group #0, Counter #60
TCPWM0 Group #0, Counter #61
TCPWM0 Group #0, Counter #62
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #1, Counter #3
TCPWM0 Group #1, Counter #4
TCPWM0 Group #1, Counter #5
TCPWM0 Group #1, Counter #6
TCPWM0 Group #1, Counter #7
TCPWM0 Group #1, Counter #8
TCPWM0 Group #1, Counter #9
TCPWM0 Group #1, Counter #10
TCPWM0 Group #1, Counter #11
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #1
TCPWM0 Group #2, Counter #2
TCPWM0 Group #2, Counter #3
TCPWM0 Group #2, Counter #4
TCPWM0 Group #2, Counter #5
TCPWM0 Group #2, Counter #6
TCPWM0 Group #2, Counter #7
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Datasheet
81
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Faults
21
Faults
Table 21-1
Fault assignments (Preliminary)
Fault
Source
Description
CM0+ SMPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
0
CPUSS_MPU_VIO_0
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1
2
CPUSS_MPU_VIO_1
CPUSS_MPU_VIO_2
CPUSS_MPU_VIO_3
CPUSS_MPU_VIO_4
CPUSS_MPU_VIO_5
CPUSS_MPU_VIO_6
CPUSS_MPU_VIO_13
CPUSS_MPU_VIO_14
CPUSS_MPU_VIO_15
CRYPTO SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
SDHC MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Ethernet0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM7_1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM7_0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
3
4
5
9
13
14
15
Correctable ECC error in CM7_1 TCM memory
DATA0[23:2]: Violating address.
16
17
18
CPUSS_CM7_1_TCM_C_ECC
CPUSS_CM7_1_TCM_NC_ECC
CPUSS_CM7_0_CACHE_C_ECC
DATA1[7:0]: Syndrome of code word (at address offset 0x0).
DATA1[31:30]: 0= ITCM, 2=D0TCM, 3=D1TCM
Non Correctable ECC error in CM7_1 TCM memory.
See CPUSS_CM7_1_TCM_C_ECC description.
Correctable ECC error in CM7_0 Cache memories
DATA0[16:2]: location information: Tag/Data SRAM, Way, Index and line Offset, see CM7 UGRM
IEBR0/DEBR0 description for details.
DATA0[31]: 0=Instruction cache, 1= Data cache
Non Correctable ECC error in CM7_0 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
19
20
21
25
CPUSS_CM7_0_CACHE_NC_ECC
CPUSS_CM7_1_CACHE_C_ECC
CPUSS_CM7_1_CACHE_NC_ECC
PERI_MS_VIO_4
Correctable ECC error in CM7_1 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
Non Correctable ECC error in CM7_1 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
P-DMA1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
Peripheral protection SRAM correctable ECC violation
DATA0[10:0]: Violating address.
26
27
PERI_PERI_C_ECC
PERI_PERI_NC_ECC
DATA1[7:0]: Syndrome of SRAM word.
Peripheral protection SRAM non-correctable ECC violation
CM0+ Peripheral Master Interface PPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
28
PERI_MS_VIO_0
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error, other:
undefined.
CM7_0 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
29
30
31
PERI_MS_VIO_1
PERI_MS_VIO_2
PERI_MS_VIO_3
CM7_1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
P-DMA0 Peripheral Master Interface PPU_3 violation.
See PERI_MS_VIO_0 description.
Datasheet
82
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Faults
Table 21-1
Fault assignments (Preliminary) (continued)
Fault
Source
Description
Peripheral Group #0 violation.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
32
PERI_GROUP_VIO_0
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.
Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #4 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #8 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.
33
34
35
36
37
38
40
41
PERI_GROUP_VIO_1
PERI_GROUP_VIO_2
PERI_GROUP_VIO_3
PERI_GROUP_VIO_4
PERI_GROUP_VIO_5
PERI_GROUP_VIO_6
PERI_GROUP_VIO_8
PERI_GROUP_VIO_9
Flash controller main flash bus error
FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit
system address.
48
CPUSS_FLASHC_MAIN_BUS_ERR
FAULT_DATA1[11:8]: Master identifier.
Flash controller main flash correctable ECC violation
DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00).
DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08).
DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10).
DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).
49
CPUSS_FLASHC_MAIN_C_ECC
Flash controller main flash non-correctable ECC violation.
See CPUSS_FLASHC_MAIN_C_ECC description.
50
51
CPUSS_FLASHC_MAIN_NC_ECC
CPUSS_FLASHC_WORK_BUS_ERR
Flash controller work-flash bus error.
See CPUSS_FLASHC_MAIN_BUS_ERR description.
Flash controller work flash correctable ECC violation.
DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
52
53
CPUSS_FLASHC_WORK_C_ECC
CPUSS_FLASHC_WORK_NC_ECC
DATA1[6:0]: Syndrome of 32-bit word.
Flash controller work-flash non-correctable ECC violation.
See CPUSS_FLASHC_WORK_C_ECC description.
Flash controller CM0+ cache correctable ECC violation.
DATA0[26:0]: Violating address.
DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0).
DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).
DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8).
DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).
54
CPUSS_FLASHC_CM0_CA_C_ECC
Flash controller CM0+ cache non-correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
55
56
57
CPUSS_FLASHC_CM0_CA_NC_ECC
CPUSS_CM7_0_TCM_C_ECC
CPUSS_CM7_0_TCM_NC_ECC
CPU CM7_0 TCM memory correctable ECC violation.
See CPUSS_CM7_1_TCM_C_ECC description.
CPU CM7_0 TCM memory non-correctable ECC violation.
See CPUSS_CM7_1_TCM_C_ECC description.
System memory controller 0 correctable ECC violation:
DATA0[31:0]: Violating address.
58
CPUSS_RAMC0_C_ECC
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
System memory controller 0 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
59
60
61
CPUSS_RAMC0_NC_ECC
CPUSS_RAMC1_C_ECC
CPUSS_RAMC1_NC_ECC
System memory controller 1 correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
System memory controller 1 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
Crypto memory correctable ECC violation.
DATA0[31:0]: Violating address.
DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM.
DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM.
64
CPUSS_CRYPTO_C_ECC
Datasheet
83
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Faults
Table 21-1
Fault assignments (Preliminary) (continued)
Fault
Source
Description
CRYPTO memory non-correctable ECC violation.
65
70
CPUSS_CRYPTO_NC_ECC
CPUSS_DW0_C_ECC
See CPUSS_CRYPTO_C_ECC description.
P-DMA0 memory correctable ECC violation:
DATA0[11:0]: Violating DW SRAM address
(word address, assuming byte addressable).
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
P-DMA0 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
71
72
73
CPUSS_DW0_NC_ECC
CPUSS_DW1_C_ECC
CPUSS_DW1_NC_ECC
P-DMA1 memory correctable ECC violation.
See CPUSS_DW0_C_ECC description.
P-DMA1 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
Flash code storage SRAM memory correctable ECC violation:
DATA0[15:0]: Address location in the eCT Flash SRAM.
DATA1[6:0]: Syndrome of 32-bit SRAM word.
74
75
CPUSS_FM_SRAM_C_ECC
CPUSS_FM_SRAM_NC_ECC
Flash code storage SRAM memory non-correctable ECC violation:
See CPUSS_FM_SRAMC_C_ECC description.
CAN0 message buffer correctable ECC violation:
DATA0[15:0]: Violating address.
80
81
CANFD_0__CAN_C_ECC
CANFD_0__CAN_NC_ECC
DATA0[22:16]: ECC violating data[38:32] from MRAM.
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA1[31:0]: ECC violating data[31:0] from MRAM.
CAN0 message buffer non-correctable ECC violation:
DATA0[15:0]: Violating address.
DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error).
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA0[30]: Write access, only possible for Address Error
DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE
DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error).
CAN1 message buffer correctable ECC violation.
See CANFD_0_CAN_C_ECC description.
82
83
CANFD_1__CAN_C_ECC
CANFD_1__CAN_NC_ECC
CAN1 message buffer non-correctable ECC violation.
See CANFD_0_CAN_NC_ECC description.
Consolidated fault output for clock supervisors. Multiple CSV can detect a violation at the same time.
DATA0[15:0]: CLK_HF* root CSV violation flags.
90
91
92
SRSS_FAULT_CSV
SRSS_FAULT_SSV
SRSS_FAULT_MCWDT0
DATA0[24]: CLK_REF CSV violation flag (reference clock for CLK_HF CSVs)
DATA0[25]: CLK_LF CSV violation flag
DATA0[26]: CLK_HVILO CSV violation flag
Consolidated fault output for supply supervisors. Multiple CSV can detect a violation at the same
time.
DATA0[0]: BOD on VDDA
DATA[1]: OVD on VDDA
DATA[16]: LVD/HVD #1
DATA0[17]: LVD/HVD #2
Fault output for MCWDT0 (all sub-counters) Multiple counters can detect a violation at the same time.
DATA0[0]: MCWDT sub counter 0 LOWER_LIMIT
DATA0[1]: MCWDT sub counter 0 UPPER_LIMIT
DATA0[2]: MCWDT sub counter 1 LOWER_LIMIT
DATA0[3]: MCWDT sub counter 1 UPPER_LIMIT
Fault output for MCWDT1 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
93
94
SRSS_FAULT_MCWDT1
SRSS_FAULT_MCWDT2
Fault output for MCWDT2 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
Datasheet
84
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
22
Peripheral protection unit fixed structure pairs
Protection pair is a pair PPU structures, a master, and a slave structure. The master structure protects the slave
structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself.
Table 22-1
PPU fixed structure pairs
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_PERI_MAIN
PERI_MS_PPU_FX_PERI_SECURE
0x40000200
0x00000040
Peripheral Interconnect main
0
0x40002000
0x40004010
0x40004050
0x40004090
0x400040C0
0x40004100
0x40004140
0x40004180
0x40004200
0x40004240
0x40004020
0x40004060
0x400040A0
0x400040E0
0x40004120
0x40004160
0x400041A0
0x40004220
0x40004260
0x40008000
0x40030000
0x40040000
0x40100000
0x40101000
0x40102000
0x40102100
0x40102120
0x40108000
0x40200000
0x40200400
0x40201000
0x40202000
0x40208000
0x4020A000
0x4020C000
0x40210000
0x40210100
0x40210200
0x00000004
0x00000004
0x00000004
0x00000004
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00008000
0x00001000
0x00004000
0x00000400
0x00000800
0x00000100
0x00000004
0x00000004
0x00002000
0x00000400
0x00000400
0x00001000
0x00000200
0x00001000
0x00001000
0x00001000
0x00000100
0x00000100
0x00000100
Peripheral interconnect secure
Peripheral Group #0 main
Peripheral Group #1 main
Peripheral Group #2 main
Peripheral Group #3 main
Peripheral Group #4 main
Peripheral Group #5 main
Peripheral Group #6 main
Peripheral Group #8 main
Peripheral Group #9 main
Peripheral Group #0 boot
Peripheral Group #1 boot
Peripheral Group #2 boot
Peripheral Group #3 boot
Peripheral Group #4 boot
Peripheral Group #5 boot
Peripheral Group #6 boot
Peripheral Group #8 boot
Peripheral Group #9 boot
Peripheral trigger multiplexer
Peripheral master slave boot
Peripheral clock main
Crypto main
1
PERI_MS_PPU_FX_PERI_GR0_GROUP
PERI_MS_PPU_FX_PERI_GR1_GROUP
PERI_MS_PPU_FX_PERI_GR2_GROUP
PERI_MS_PPU_FX_PERI_GR3_GROUP
PERI_MS_PPU_FX_PERI_GR4_GROUP
PERI_MS_PPU_FX_PERI_GR5_GROUP
PERI_MS_PPU_FX_PERI_GR6_GROUP
PERI_MS_PPU_FX_PERI_GR8_GROUP
PERI_MS_PPU_FX_PERI_GR9_GROUP
PERI_MS_PPU_FX_PERI_GR0_BOOT
PERI_MS_PPU_FX_PERI_GR1_BOOT
PERI_MS_PPU_FX_PERI_GR2_BOOT
PERI_MS_PPU_FX_PERI_GR3_BOOT
PERI_MS_PPU_FX_PERI_GR4_BOOT
PERI_MS_PPU_FX_PERI_GR5_BOOT
PERI_MS_PPU_FX_PERI_GR6_BOOT
PERI_MS_PPU_FX_PERI_GR8_BOOT
PERI_MS_PPU_FX_PERI_GR9_BOOT
PERI_MS_PPU_FX_PERI_TR
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PERI_MS_PPU_FX_PERI_MS_BOOT
PERI_MS_PPU_FX_PERI_PCLK_MAIN
PERI_MS_PPU_FX_CRYPTO_MAIN
PERI_MS_PPU_FX_CRYPTO_CRYPTO
PERI_MS_PPU_FX_CRYPTO_BOOT
PERI_MS_PPU_FX_CRYPTO_KEY0
PERI_MS_PPU_FX_CRYPTO_KEY1
PERI_MS_PPU_FX_CRYPTO_BUF
PERI_MS_PPU_FX_CPUSS_CM7_0
PERI_MS_PPU_FX_CPUSS_CM7_1
PERI_MS_PPU_FX_CPUSS_CM0
Crypto MMIO (Memory Mapped I/O)
Crypto boot
Crypto Key #0
Crypto Key #1
Crypto buffer
CM7_0 CPU core
CM7_1 CPU core
CM0+ CPU core
[40]
PERI_MS_PPU_FX_CPUSS_BOOT
CPUSS boot
PERI_MS_PPU_FX_CPUSS_CM0_INT
CPUSS CM0+ interrupts
CPUSS CM7_0 interrupts
CPUSS CM7_1 interrupts
CPUSS Fault Structure #0 main
CPUSS Fault Structure #1 main
CPUSS Fault Structure #2 main
PERI_MS_PPU_FX_CPUSS_CM7_0_INT
PERI_MS_PPU_FX_CPUSS_CM7_1_INT
PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN
Note
40.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.
Datasheet
85
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN
PERI_MS_PPU_FX_IPC_STRUCT0_IPC
0x40210300
0x00000100
CPUSS Fault Structure #3 main
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
0x40220000
0x40220020
0x40220040
0x40220060
0x40220080
0x402200A0
0x402200C0
0x402200E0
0x40221000
0x40221020
0x40221040
0x40221060
0x40221080
0x402210A0
0x402210C0
0x402210E0
0x40230000
0x40234000
0x40235400
0x40235800
0x40237400
0x40237800
0x40237C00
0x40240000
0x40240008
0x40240200
0x40240400
0x402404E0
0x40240560
0x40240580
0x40240600
0x40240680
0x40240700
0x40240780
0x4024F000
0x4024F400
0x4024F500
0x4024F000
0x40260000
0x40261000
0x40262000
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000040
0x00000004
0x00000400
0x00000400
0x00000004
0x00000004
0x00000400
0x00000008
0x00000004
0x00000100
0x00000080
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00000004
0x00000080
0x00000008
0x00000004
0x00001000
0x00000400
0x00001000
0x00002000
CPUSS IPC Structure #0
PERI_MS_PPU_FX_IPC_STRUCT1_IPC
PERI_MS_PPU_FX_IPC_STRUCT2_IPC
PERI_MS_PPU_FX_IPC_STRUCT3_IPC
PERI_MS_PPU_FX_IPC_STRUCT4_IPC
PERI_MS_PPU_FX_IPC_STRUCT5_IPC
PERI_MS_PPU_FX_IPC_STRUCT6_IPC
PERI_MS_PPU_FX_IPC_STRUCT7_IPC
PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR
PERI_MS_PPU_FX_PROT_SMPU_MAIN
PERI_MS_PPU_FX_PROT_MPU0_MAIN
PERI_MS_PPU_FX_PROT_MPU5_MAIN
PERI_MS_PPU_FX_PROT_MPU6_MAIN
PERI_MS_PPU_FX_PROT_MPU13_MAIN
PERI_MS_PPU_FX_PROT_MPU14_MAIN
PERI_MS_PPU_FX_PROT_MPU15_MAIN
PERI_MS_PPU_FX_FLASHC_MAIN
CPUSS IPC Structure #1
CPUSS IPC Structure #2
CPUSS IPC Structure #3
CPUSS IPC Structure #4
CPUSS IPC Structure #5
CPUSS IPC Structure #6
CPUSS IPC Structure #7
CPUSS IPC Interrupt Structure #0
CPUSS IPC Interrupt Structure #1
CPUSS IPC Interrupt Structure #2
CPUSS IPC Interrupt Structure #3
CPUSS IPC Interrupt Structure #4
CPUSS IPC Interrupt Structure #5
CPUSS IPC Interrupt Structure #6
CPUSS IPC Interrupt Structure #7
Peripheral protection SMPU main
Peripheral protection MPU #0 main
Peripheral protection MPU #5 main
Peripheral protection MPU #6 main
Peripheral protection MPU #13 main
Peripheral protection MPU #14 main
Peripheral protection MPU #15 main
Flash controller main
PERI_MS_PPU_FX_FLASHC_CMD
Flash controller command
Flash controller tests
PERI_MS_PPU_FX_FLASHC_DFT
PERI_MS_PPU_FX_FLASHC_CM0
Flash controller CM0+
PERI_MS_PPU_FX_FLASHC_CM7_0
PERI_MS_PPU_FX_FLASHC_CM7_1
PERI_MS_PPU_FX_FLASHC_CRYPTO
PERI_MS_PPU_FX_FLASHC_DW0
Flash controller CM7_0
Flash controller CM7_1
Flash controller Crypto
Flash controller P-DMA0
PERI_MS_PPU_FX_FLASHC_DW1
Flash controller P-DMA1
PERI_MS_PPU_FX_FLASHC_DMAC
Flash controller M-DMA0
PERI_MS_PPU_FX_FLASHC_SLOW0
Flash External AHB-Lite Master 0
Flash management
[41]
PERI_MS_PPU_FX_FLASHC_FlashMgmt
PERI_MS_PPU_FX_FLASHC_MainSafety
PERI_MS_PPU_FX_FLASHC_WorkSafety
PERI_MS_PPU_FX_FLASHC_FM
Flash controller code-flash safety
Flash controller work-flash safety
Flash management
PERI_MS_PPU_FX_SRSS_GENERAL
PERI_MS_PPU_FX_SRSS_MAIN
SRSS General
SRSS main
PERI_MS_PPU_FX_SRSS_SECURE
SRSS secure
Note
41.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.
Datasheet
86
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
MCWDT #0 configuration
PERI_MS_PPU_FX_MCWDT0_CONFIG
PERI_MS_PPU_FX_MCWDT1_CONFIG
0x40268000
0x00000080
81
82
0x40268100
0x40268200
0x40268080
0x40268180
0x40268280
0x4026C000
0x4026C040
0x40270000
0x40280000
0x40290000
0x40280100
0x40290100
0x40288000
0x40288040
0x40288080
0x402880C0
0x40288100
0x40288140
0x40288180
0x402881C0
0x40288200
0x40288240
0x40288280
0x402882C0
0x40288300
0x40288340
0x40288380
0x402883C0
0x40288400
0x40288440
0x40288480
0x402884C0
0x40288500
0x40288540
0x40288580
0x402885C0
0x40288600
0x40288640
0x40288680
0x402886C0
0x40288700
0x40288740
0x40288780
0x402887C0
0x00000080
0x00000080
0x00000040
0x00000040
0x00000040
0x00000020
0x00000020
0x00010000
0x00000100
0x00000100
0x00000080
0x00000080
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
MCWDT #1 configuration
MCWDT #2 configuration
MCWDT #0 main
PERI_MS_PPU_FX_MCWDT2_CONFIG
PERI_MS_PPU_FX_MCWDT0_MAIN
83
84
PERI_MS_PPU_FX_MCWDT1_MAIN
MCWDT #1 main
85
PERI_MS_PPU_FX_MCWDT2_MAIN
MCWDT #2 main
86
PERI_MS_PPU_FX_WDT_CONFIG
System WDT configuration
System WDT main
SRSS backup
87
PERI_MS_PPU_FX_WDT_MAIN
88
PERI_MS_PPU_FX_BACKUP_BACKUP
PERI_MS_PPU_FX_DW0_DW
89
P-DMA0 main
90
PERI_MS_PPU_FX_DW1_DW
P-DMA1 main
91
PERI_MS_PPU_FX_DW0_DW_CRC
P-DMA0 CRC
92
PERI_MS_PPU_FX_DW1_DW_CRC
P-DMA1 CRC
93
PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT31_CH
P-DMA0 Channel #0
P-DMA0 Channel #1
P-DMA0 Channel #2
P-DMA0 Channel #3
P-DMA0 Channel #4
P-DMA0 Channel #5
P-DMA0 Channel #6
P-DMA0 Channel #7
P-DMA0 Channel #8
P-DMA0 Channel #9
P-DMA0 Channel #10
P-DMA0 Channel #11
P-DMA0 Channel #12
P-DMA0 Channel #13
P-DMA0 Channel #14
P-DMA0 Channel #15
P-DMA0 Channel #16
P-DMA0 Channel #17
P-DMA0 Channel #18
P-DMA0 Channel #19
P-DMA0 Channel #20
P-DMA0 Channel #21
P-DMA0 Channel #22
P-DMA0 Channel #23
P-DMA0 Channel #24
P-DMA0 Channel #25
P-DMA0 Channel #26
P-DMA0 Channel #27
P-DMA0 Channel #28
P-DMA0 Channel #29
P-DMA0 Channel #30
P-DMA0 Channel #31
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
Datasheet
87
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
P-DMA0 Channel #32
PERI_MS_PPU_FX_DW0_CH_STRUCT32_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH
0x40288800
0x00000040
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
0x40288840
0x40288880
0x402888C0
0x40288900
0x40288940
0x40288980
0x402889C0
0x40288A00
0x40288A40
0x40288A80
0x40288AC0
0x40288B00
0x40288B40
0x40288B80
0x40288BC0
0x40288C00
0x40288C40
0x40288C80
0x40288CC0
0x40288D00
0x40288D40
0x40288D80
0x40288DC0
0x40288E00
0x40288E40
0x40288E80
0x40288EC0
0x40288F00
0x40288F40
0x40288F80
0x40288FC0
0x40289000
0x40289040
0x40289080
0x402890C0
0x40289100
0x40289140
0x40289180
0x402891C0
0x40289200
0x40289240
0x40289280
0x402892C0
0x40289300
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
P-DMA0 Channel #33
P-DMA0 Channel #34
P-DMA0 Channel #35
P-DMA0 Channel #36
P-DMA0 Channel #37
P-DMA0 Channel #38
P-DMA0 Channel #39
P-DMA0 Channel #40
P-DMA0 Channel #41
P-DMA0 Channel #42
P-DMA0 Channel #43
P-DMA0 Channel #44
P-DMA0 Channel #45
P-DMA0 Channel #46
P-DMA0 Channel #47
P-DMA0 Channel #48
P-DMA0 Channel #49
P-DMA0 Channel #50
P-DMA0 Channel #51
P-DMA0 Channel #52
P-DMA0 Channel #53
P-DMA0 Channel #54
P-DMA0 Channel #55
P-DMA0 Channel #56
P-DMA0 Channel #57
P-DMA0 Channel #58
P-DMA0 Channel #59
P-DMA0 Channel #60
P-DMA0 Channel #61
P-DMA0 Channel #62
P-DMA0 Channel #63
P-DMA0 Channel #64
P-DMA0 Channel #65
P-DMA0 Channel #66
P-DMA0 Channel #67
P-DMA0 Channel #68
P-DMA0 Channel #69
P-DMA0 Channel #70
P-DMA0 Channel #71
P-DMA0 Channel #72
P-DMA0 Channel #73
P-DMA0 Channel #74
P-DMA0 Channel #75
P-DMA0 Channel #76
PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT35_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT38_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT39_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT40_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT41_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT43_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT44_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT45_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT46_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT47_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT48_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT49_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT50_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT51_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT52_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT58_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT59_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT60_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT67_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT68_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT69_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT70_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT73_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT74_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT75_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT76_CH
Datasheet
88
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
P-DMA0 Channel #77
PERI_MS_PPU_FX_DW0_CH_STRUCT77_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT78_CH
0x40289340
0x00000040
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
0x40289380
0x402893C0
0x40289400
0x40289440
0x40289480
0x402894C0
0x40289500
0x40289540
0x40289580
0x402895C0
0x40289600
0x40289640
0x40289680
0x402896C0
0x40289700
0x40289740
0x40289780
0x402897C0
0x40289800
0x40289840
0x40289880
0x402898C0
0x40298000
0x40298040
0x40298080
0x402980C0
0x40298100
0x40298140
0x40298180
0x402981C0
0x40298200
0x40298240
0x40298280
0x402982C0
0x40298300
0x40298340
0x40298380
0x402983C0
0x40298400
0x40298440
0x40298480
0x402984C0
0x40298500
0x40298540
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
P-DMA0 Channel #78
P-DMA0 Channel #79
P-DMA0 Channel #80
P-DMA0 Channel #81
P-DMA0 Channel #82
P-DMA0 Channel #83
P-DMA0 Channel #84
P-DMA0 Channel #85
P-DMA0 Channel #86
P-DMA0 Channel #87
P-DMA0 Channel #88
P-DMA0 Channel #89
P-DMA0 Channel #90
P-DMA0 Channel #91
P-DMA0 Channel #92
P-DMA0 Channel #93
P-DMA0 Channel #94
P-DMA0 Channel #95
P-DMA0 Channel #96
P-DMA0 Channel #97
P-DMA0 Channel #98
P-DMA0 Channel #99
P-DMA1 Channel #0
P-DMA1 Channel #1
P-DMA1 Channel #2
P-DMA1 Channel #3
P-DMA1 Channel #4
P-DMA1 Channel #5
P-DMA1 Channel #6
P-DMA1 Channel #7
P-DMA1 Channel #8
P-DMA1 Channel #9
P-DMA1 Channel #10
P-DMA1 Channel #11
P-DMA1 Channel #12
P-DMA1 Channel #13
P-DMA1 Channel #14
P-DMA1 Channel #15
P-DMA1 Channel #16
P-DMA1 Channel #17
P-DMA1 Channel #18
P-DMA1 Channel #19
P-DMA1 Channel #20
P-DMA1 Channel #21
PERI_MS_PPU_FX_DW0_CH_STRUCT79_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT80_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT89_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT90_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT91_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT92_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT93_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT94_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT95_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT96_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT97_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT98_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT99_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH
Datasheet
89
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
P-DMA1 Channel #22
PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH
0x40298580
0x00000040
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
0x402985C0
0x40298600
0x40298640
0x40298680
0x402986C0
0x40298700
0x40298740
0x40298780
0x402987C0
0x40298800
0x40298840
0x40298880
0x402988C0
0x40298900
0x40298940
0x40298980
0x402989C0
0x40298A00
0x40298A40
0x40298A80
0x40298AC0
0x40298B00
0x40298B40
0x40298B80
0x40298BC0
0x40298C00
0x40298C40
0x40298C80
0x40298CC0
0x40298D00
0x40298D40
0x40298D80
0x40298DC0
0x40298E00
0x40298E40
0x402A0000
0x402A1000
0x402A1100
0x402A1200
0x402A1300
0x402A1400
0x402A1500
0x402A1600
0x402A1700
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000010
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
P-DMA1 Channel #23
P-DMA1 Channel #24
P-DMA1 Channel #25
P-DMA1 Channel #26
P-DMA1 Channel #27
P-DMA1 Channel #28
P-DMA1 Channel #29
P-DMA1 Channel #30
P-DMA1 Channel #31
P-DMA1 Channel #32
P-DMA1 Channel #33
P-DMA1 Channel #34
P-DMA1 Channel #35
P-DMA1 Channel #36
P-DMA1 Channel #37
P-DMA1 Channel #38
P-DMA1 Channel #39
P-DMA1 Channel #40
P-DMA1 Channel #41
P-DMA1 Channel #42
P-DMA1 Channel #43
P-DMA1 Channel #44
P-DMA1 Channel #45
P-DMA1 Channel #46
P-DMA1 Channel #47
P-DMA1 Channel #48
P-DMA1 Channel #49
P-DMA1 Channel #50
P-DMA1 Channel #51
P-DMA1 Channel #52
P-DMA1 Channel #53
P-DMA1 Channel #54
P-DMA1 Channel #55
P-DMA1 Channel #56
P-DMA1 Channel #57
M-DMA0 main
PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT32_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT33_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT34_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT35_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT38_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT39_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT40_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT41_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT43_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT44_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT45_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT46_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT47_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT48_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT49_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT50_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT51_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT52_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT57_CH
PERI_MS_PPU_FX_DMAC_TOP
PERI_MS_PPU_FX_DMAC_CH0_CH
M-DMA0 Channel #0
M-DMA0 Channel #1
M-DMA0 Channel #2
M-DMA0 Channel #3
M-DMA0 Channel #4
M-DMA0 Channel #5
M-DMA0 Channel #6
M-DMA0 Channel #7
PERI_MS_PPU_FX_DMAC_CH1_CH
PERI_MS_PPU_FX_DMAC_CH2_CH
PERI_MS_PPU_FX_DMAC_CH3_CH
PERI_MS_PPU_FX_DMAC_CH4_CH
PERI_MS_PPU_FX_DMAC_CH5_CH
PERI_MS_PPU_FX_DMAC_CH6_CH
PERI_MS_PPU_FX_DMAC_CH7_CH
Datasheet
90
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_EFUSE_CTL
PERI_MS_PPU_FX_EFUSE_DATA
0x402C0000
0x00000200
EFUSE control
EFUSE data
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
0x402C0800
0x402F0000
0x40300000
0x40300010
0x40300020
0x40300030
0x40300040
0x40300050
0x40300060
0x40300070
0x40300080
0x40300090
0x403000A0
0x403000B0
0x403000C0
0x403000D0
0x403000E0
0x403000F0
0x40300100
0x40300110
0x40300120
0x40300130
0x40300140
0x40300150
0x40300160
0x40300170
0x40300180
0x40300190
0x403001A0
0x403001B0
0x403001C0
0x403001D0
0x403001E0
0x403001F0
0x40300200
0x40302000
0x40302200
0x40302240
0x40310000
0x40310080
0x40310100
0x40310180
0x40310200
0x40310280
0x00000200
0x00001000
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000010
0x00000010
0x00000004
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
PERI_MS_PPU_FX_BIST
Built-in self test
HSIOm Port #0
HSIOm Port #1
HSIOm Port #2
HSIOm Port #3
HSIOm Port #4
HSIOm Port #5
HSIOm Port #6
HSIOm Port #7
HSIOm Port #8
HSIOm Port #9
HSIOm Port #10
HSIOm Port #11
HSIOm Port #12
HSIOm Port #13
HSIOm Port #14
HSIOm Port #15
HSIOm Port #16
HSIOm Port #17
HSIOm Port #18
HSIOm Port #19
HSIOm Port #20
HSIOm Port #21
HSIOm Port #22
HSIOm Port #23
HSIOm Port #24
HSIOm Port #25
HSIOm Port #26
HSIOm Port #27
HSIOm Port #28
HSIOm Port #29
HSIOm Port #30
HSIOm Port #31
HSIOm Port #32
PERI_MS_PPU_FX_HSIOM_PRT0_PRT
PERI_MS_PPU_FX_HSIOM_PRT1_PRT
PERI_MS_PPU_FX_HSIOM_PRT2_PRT
PERI_MS_PPU_FX_HSIOM_PRT3_PRT
PERI_MS_PPU_FX_HSIOM_PRT4_PRT
PERI_MS_PPU_FX_HSIOM_PRT5_PRT
PERI_MS_PPU_FX_HSIOM_PRT6_PRT
PERI_MS_PPU_FX_HSIOM_PRT7_PRT
PERI_MS_PPU_FX_HSIOM_PRT8_PRT
PERI_MS_PPU_FX_HSIOM_PRT9_PRT
PERI_MS_PPU_FX_HSIOM_PRT10_PRT
PERI_MS_PPU_FX_HSIOM_PRT11_PRT
PERI_MS_PPU_FX_HSIOM_PRT12_PRT
PERI_MS_PPU_FX_HSIOM_PRT13_PRT
PERI_MS_PPU_FX_HSIOM_PRT14_PRT
PERI_MS_PPU_FX_HSIOM_PRT15_PRT
PERI_MS_PPU_FX_HSIOM_PRT16_PRT
PERI_MS_PPU_FX_HSIOM_PRT17_PRT
PERI_MS_PPU_FX_HSIOM_PRT18_PRT
PERI_MS_PPU_FX_HSIOM_PRT19_PRT
PERI_MS_PPU_FX_HSIOM_PRT20_PRT
PERI_MS_PPU_FX_HSIOM_PRT21_PRT
PERI_MS_PPU_FX_HSIOM_PRT22_PRT
PERI_MS_PPU_FX_HSIOM_PRT23_PRT
PERI_MS_PPU_FX_HSIOM_PRT24_PRT
PERI_MS_PPU_FX_HSIOM_PRT25_PRT
PERI_MS_PPU_FX_HSIOM_PRT26_PRT
PERI_MS_PPU_FX_HSIOM_PRT27_PRT
PERI_MS_PPU_FX_HSIOM_PRT28_PRT
PERI_MS_PPU_FX_HSIOM_PRT29_PRT
PERI_MS_PPU_FX_HSIOM_PRT30_PRT
PERI_MS_PPU_FX_HSIOM_PRT31_PRT
PERI_MS_PPU_FX_HSIOM_PRT32_PRT
PERI_MS_PPU_FX_HSIOM_AMUX
HSIOm Analog multiplexer
HSIOm monitor
PERI_MS_PPU_FX_HSIOM_MON
PERI_MS_PPU_FX_HSIOM_ALTJTAG
PERI_MS_PPU_FX_GPIO_PRT0_PRT
PERI_MS_PPU_FX_GPIO_PRT1_PRT
PERI_MS_PPU_FX_GPIO_PRT2_PRT
PERI_MS_PPU_FX_GPIO_PRT3_PRT
PERI_MS_PPU_FX_GPIO_PRT4_PRT
PERI_MS_PPU_FX_GPIO_PRT5_PRT
HSIOm Alternate JTAG
GPIO_ENH Port #0
GPIO_STD Port #1
GPIO_STD Port #2
GPIO_STD Port #3
GPIO_STD Port #4
GPIO_STD Port #5
Datasheet
91
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_GPIO_PRT6_PRT
PERI_MS_PPU_FX_GPIO_PRT7_PRT
0x40310300
0x00000040
GPIO_STD Port #6
GPIO_STD Port #7
GPIO_STD Port #8
GPIO_STD Port #9
GPIO_STD Port #10
GPIO_STD Port #11
GPIO_STD Port #12
GPIO_STD Port #13
GPIO_STD Port #14
GPIO_STD Port #15
GPIO_STD Port #16
GPIO_STD Port #17
GPIO_STD Port #18
GPIO_STD Port #19
GPIO_STD Port #20
GPIO_STD Port #21
GPIO_STD Port #22
GPIO_STD Port #23
HSIO_STD Port #24
HSIO_STD Port #25
HSIO_STD Port #26
HSIO_STD Port #27
GPIO_STD Port #28
GPIO_STD Port #29
GPIO_STD Port #30
GPIO_STD Port #31
GPIO_STD Port #32
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
0x40310380
0x40310400
0x40310480
0x40310500
0x40310580
0x40310600
0x40310680
0x40310700
0x40310780
0x40310800
0x40310880
0x40310900
0x40310980
0x40310A00
0x40310A80
0x40310B00
0x40310B80
0x40310C00
0x40310C80
0x40310D00
0x40310D80
0x40310E00
0x40310E80
0x40310F00
0x40310F80
0x40311000
0x40310040
0x403100C0
0x40310140
0x403101C0
0x40310240
0x403102C0
0x40310340
0x403103C0
0x40310440
0x403104C0
0x40310540
0x403105C0
0x40310640
0x403106C0
0x40310740
0x403107C0
0x40310840
0x403108C0
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
PERI_MS_PPU_FX_GPIO_PRT8_PRT
PERI_MS_PPU_FX_GPIO_PRT9_PRT
PERI_MS_PPU_FX_GPIO_PRT10_PRT
PERI_MS_PPU_FX_GPIO_PRT11_PRT
PERI_MS_PPU_FX_GPIO_PRT12_PRT
PERI_MS_PPU_FX_GPIO_PRT13_PRT
PERI_MS_PPU_FX_GPIO_PRT14_PRT
PERI_MS_PPU_FX_GPIO_PRT15_PRT
PERI_MS_PPU_FX_GPIO_PRT16_PRT
PERI_MS_PPU_FX_GPIO_PRT17_PRT
PERI_MS_PPU_FX_GPIO_PRT18_PRT
PERI_MS_PPU_FX_GPIO_PRT19_PRT
PERI_MS_PPU_FX_GPIO_PRT20_PRT
PERI_MS_PPU_FX_GPIO_PRT21_PRT
PERI_MS_PPU_FX_GPIO_PRT22_PRT
PERI_MS_PPU_FX_GPIO_PRT23_PRT
PERI_MS_PPU_FX_GPIO_PRT24_PRT
PERI_MS_PPU_FX_GPIO_PRT25_PRT
PERI_MS_PPU_FX_GPIO_PRT26_PRT
PERI_MS_PPU_FX_GPIO_PRT27_PRT
PERI_MS_PPU_FX_GPIO_PRT28_PRT
PERI_MS_PPU_FX_GPIO_PRT29_PRT
PERI_MS_PPU_FX_GPIO_PRT30_PRT
PERI_MS_PPU_FX_GPIO_PRT31_PRT
PERI_MS_PPU_FX_GPIO_PRT32_PRT
PERI_MS_PPU_FX_GPIO_PRT0_CFG
PERI_MS_PPU_FX_GPIO_PRT1_CFG
PERI_MS_PPU_FX_GPIO_PRT2_CFG
PERI_MS_PPU_FX_GPIO_PRT3_CFG
PERI_MS_PPU_FX_GPIO_PRT4_CFG
PERI_MS_PPU_FX_GPIO_PRT5_CFG
PERI_MS_PPU_FX_GPIO_PRT6_CFG
PERI_MS_PPU_FX_GPIO_PRT7_CFG
PERI_MS_PPU_FX_GPIO_PRT8_CFG
PERI_MS_PPU_FX_GPIO_PRT9_CFG
PERI_MS_PPU_FX_GPIO_PRT10_CFG
PERI_MS_PPU_FX_GPIO_PRT11_CFG
PERI_MS_PPU_FX_GPIO_PRT12_CFG
PERI_MS_PPU_FX_GPIO_PRT13_CFG
PERI_MS_PPU_FX_GPIO_PRT14_CFG
PERI_MS_PPU_FX_GPIO_PRT15_CFG
PERI_MS_PPU_FX_GPIO_PRT16_CFG
PERI_MS_PPU_FX_GPIO_PRT17_CFG
GPIO_ENH Port #0 configuration
GPIO_STD Port #1 configuration
GPIO_STD Port #2 configuration
GPIO_STD Port #3 configuration
GPIO_STD Port #4 configuration
GPIO_STD Port #5 configuration
GPIO_STD Port #6 configuration
GPIO_STD Port #7 configuration
GPIO_STD Port #8 configuration
GPIO_STD Port #9 configuration
GPIO_STD Port #10 configuration
GPIO_STD Port #11 configuration
GPIO_STD Port #12 configuration
GPIO_STD Port #13 configuration
GPIO_STD Port #14 configuration
GPIO_STD Port #15 configuration
GPIO_STD Port #16 configuration
GPIO_STD Port #17 configuration
Datasheet
92
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_GPIO_PRT18_CFG
PERI_MS_PPU_FX_GPIO_PRT19_CFG
0x40310940
0x00000020
GPIO_STD Port #18 configuration
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
0x403109C0
0x40310A40
0x40310AC0
0x40310B40
0x40310BC0
0x40310C40
0x40310CC0
0x40310D40
0x40310DC0
0x40310E40
0x40310EC0
0x40310F40
0x40310FC0
0x40311040
0x40314000
0x40315000
0x40320C00
0x40320D00
0x40320E00
0x40320F00
0x40321100
0x403F0000
0x40420000
0x40460000
0x40480000
-
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000040
0x00000008
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00001000
0x00010000
0x00010000
0x00010000
-
GPIO_STD Port #19 configuration
GPIO_STD Port #20 configuration
GPIO_STD Port #21 configuration
GPIO_STD Port #22 configuration
GPIO_STD Port #23 configuration
HSIO_STD Port #24 configuration
HSIO_STD Port #25 configuration
HSIO_STD Port #26 configuration
HSIO_STD Port #27 configuration
GPIO_STD Port #28 configuration
GPIO_STD Port #29 configuration
GPIO_STD Port #30 configuration
GPIO_STD Port #31 configuration
GPIO_STD Port #32 configuration
GPIO main
PERI_MS_PPU_FX_GPIO_PRT20_CFG
PERI_MS_PPU_FX_GPIO_PRT21_CFG
PERI_MS_PPU_FX_GPIO_PRT22_CFG
PERI_MS_PPU_FX_GPIO_PRT23_CFG
PERI_MS_PPU_FX_GPIO_PRT24_CFG
PERI_MS_PPU_FX_GPIO_PRT25_CFG
PERI_MS_PPU_FX_GPIO_PRT26_CFG
PERI_MS_PPU_FX_GPIO_PRT27_CFG
PERI_MS_PPU_FX_GPIO_PRT28_CFG
PERI_MS_PPU_FX_GPIO_PRT29_CFG
PERI_MS_PPU_FX_GPIO_PRT30_CFG
PERI_MS_PPU_FX_GPIO_PRT31_CFG
PERI_MS_PPU_FX_GPIO_PRT32_CFG
PERI_MS_PPU_FX_GPIO_GPIO
PERI_MS_PPU_FX_GPIO_TEST
GPIO test
PERI_MS_PPU_FX_SMARTIO_PRT12_PRT
PERI_MS_PPU_FX_SMARTIO_PRT13_PRT
PERI_MS_PPU_FX_SMARTIO_PRT14_PRT
PERI_MS_PPU_FX_SMARTIO_PRT15_PRT
PERI_MS_PPU_FX_SMARTIO_PRT17_PRT
PERI_MS_PPU_FX_EVTGEN0
SMART I/O #12
SMART I/O #13
SMART I/O #14
SMART I/O #15
SMART I/O #17
Event generator #0
PERI_MS_PPU_FX_SMIF0
Serial Memory Interface #0
Secure Digital High Capacity #0
Ethernet0
PERI_MS_PPU_FX_SDHC0
PERI_MS_PPU_FX_ETH0
Reserved for future use
CAN0, Channel #0
377 - 393 Reserve
PERI_MS_PPU_FX_CANFD0_CH0_CH
0x40520000
0x40520200
0x40520400
0x40520600
0x40540000
0x40540200
0x40540400
0x40540600
0x40521000
0x40541000
0x40530000
0x40550000
0x40580000
0x40580080
0x40580100
0x40580180
0x40580200
0x40580280
0x00000200
0x00000200
0x00000200
0x00000200
0x00000200
0x00000200
0x00000200
0x00000200
0x00000100
0x00000100
0x00010000
0x00010000
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
PERI_MS_PPU_FX_CANFD0_CH1_CH
PERI_MS_PPU_FX_CANFD0_CH2_CH
PERI_MS_PPU_FX_CANFD0_CH3_CH
PERI_MS_PPU_FX_CANFD1_CH0_CH
PERI_MS_PPU_FX_CANFD1_CH1_CH
PERI_MS_PPU_FX_CANFD1_CH2_CH
PERI_MS_PPU_FX_CANFD1_CH3_CH
PERI_MS_PPU_FX_CANFD0_MAIN
CAN0, Channel #1
CAN0, Channel #2
CAN0, Channel #3
CAN1, Channel #0
CAN1, Channel #1
CAN1, Channel #2
CAN1, Channel #3
CAN0 main
PERI_MS_PPU_FX_CANFD1_MAIN
CAN1 main
PERI_MS_PPU_FX_CANFD0_BUF
CAN0 buffer
PERI_MS_PPU_FX_CANFD1_BUF
CAN1 buffer
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT4_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT5_CNT
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #3
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
Datasheet
93
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT6_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT7_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT8_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT9_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT10_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT11_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT12_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT13_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT14_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT15_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT16_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT17_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT18_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT19_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT20_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT21_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT22_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT23_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT24_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT25_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT26_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT27_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT28_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT29_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT30_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT31_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT32_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT33_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT34_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT35_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT36_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT37_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT38_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT39_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT40_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT41_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT42_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT43_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT44_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT45_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT46_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT47_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT48_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT49_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT50_CNT
0x40580300
0x00000080
TCPWM0 Group #0, Counter #6
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
0x40580380
0x40580400
0x40580480
0x40580500
0x40580580
0x40580600
0x40580680
0x40580700
0x40580780
0x40580800
0x40580880
0x40580900
0x40580980
0x40580A00
0x40580A80
0x40580B00
0x40580B80
0x40580C00
0x40580C80
0x40580D00
0x40580D80
0x40580E00
0x40580E80
0x40580F00
0x40580F80
0x40581000
0x40581080
0x40581100
0x40581180
0x40581200
0x40581280
0x40581300
0x40581380
0x40581400
0x40581480
0x40581500
0x40581580
0x40581600
0x40581680
0x40581700
0x40581780
0x40581800
0x40581880
0x40581900
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
TCPWM0 Group #0, Counter #7
TCPWM0 Group #0, Counter #8
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #27
TCPWM0 Group #0, Counter #28
TCPWM0 Group #0, Counter #29
TCPWM0 Group #0, Counter #30
TCPWM0 Group #0, Counter #31
TCPWM0 Group #0, Counter #32
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #35
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #43
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
Datasheet
94
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT51_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT52_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT53_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT54_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT55_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT56_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT57_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT58_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT59_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT60_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT61_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT62_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT8_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT9_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT10_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT11_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT3_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT4_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT5_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT6_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT7_CNT
PERI_MS_PPU_FX_SCB0
0x40581980
0x00000080
TCPWM0 Group #0, Counter #51
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
0x40581A00
0x40581A80
0x40581B00
0x40581B80
0x40581C00
0x40581C80
0x40581D00
0x40581D80
0x40581E00
0x40581E80
0x40581F00
0x40588000
0x40588080
0x40588100
0x40588180
0x40588200
0x40588280
0x40588300
0x40588380
0x40588400
0x40588480
0x40588500
0x40588580
0x40590000
0x40590080
0x40590100
0x40590180
0x40590200
0x40590280
0x40590300
0x40590380
0x40600000
0x40610000
0x40620000
0x40630000
0x40640000
0x40650000
0x40660000
0x40670000
0x40680000
0x40690000
0x406A0000
0x40800000
0x40801000
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00001000
0x00001000
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
TCPWM0 Group #0, Counter #56
TCPWM0 Group #0, Counter #57
TCPWM0 Group #0, Counter #58
TCPWM0 Group #0, Counter #59
TCPWM0 Group #0, Counter #60
TCPWM0 Group #0, Counter #61
TCPWM0 Group #0, Counter #62
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #1, Counter #3
TCPWM0 Group #1, Counter #4
TCPWM0 Group #1, Counter #5
TCPWM0 Group #1, Counter #6
TCPWM0 Group #1, Counter #7
TCPWM0 Group #1, Counter #8
TCPWM0 Group #1, Counter #9
TCPWM0 Group #1, Counter #10
TCPWM0 Group #1, Counter #11
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #1
TCPWM0 Group #2, Counter #2
TCPWM0 Group #2, Counter #3
TCPWM0 Group #2, Counter #4
TCPWM0 Group #2, Counter #5
TCPWM0 Group #2, Counter #6
TCPWM0 Group #2, Counter #7
SCB0
PERI_MS_PPU_FX_SCB1
SCB1
PERI_MS_PPU_FX_SCB2
SCB2
PERI_MS_PPU_FX_SCB3
SCB3
PERI_MS_PPU_FX_SCB4
SCB4
PERI_MS_PPU_FX_SCB5
SCB5
PERI_MS_PPU_FX_SCB6
SCB6
PERI_MS_PPU_FX_SCB7
SCB7
PERI_MS_PPU_FX_SCB8
SCB8
PERI_MS_PPU_FX_SCB9
SCB9
PERI_MS_PPU_FX_SCB10
SCB10
PERI_MS_PPU_FX_I2S0
AUDIOSS I2S0
PERI_MS_PPU_FX_I2S1
AUDIOSS I2S1
Datasheet
95
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_I2S2
PERI_MS_PPU_FX_PASS0_SAR0_SAR
0x40802000
0x00001000
AUDIOSS I2S2
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
0x40900000
0x40901000
0x40902000
0x40900800
0x40900840
0x40900880
0x409008C0
0x40900900
0x40900940
0x40900980
0x409009C0
0x40900A00
0x40900A40
0x40900A80
0x40900AC0
0x40900B00
0x40900B40
0x40900B80
0x40900BC0
0x40900C00
0x40900C40
0x40900C80
0x40900CC0
0x40900D00
0x40900D40
0x40900D80
0x40900DC0
0x40900E00
0x40900E40
0x40900E80
0x40900EC0
0x40900F00
0x40900F40
0x40900F80
0x40900FC0
0x40901800
0x40901840
0x40901880
0x409018C0
0x40901900
0x40901940
0x40901980
0x409019C0
0x40901A00
0x00000400
0x00000400
0x00000400
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
PASS SAR0
PERI_MS_PPU_FX_PASS0_SAR1_SAR
PASS SAR1
PERI_MS_PPU_FX_PASS0_SAR2_SAR
PASS SAR2
PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH31_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH
SAR0, Channel #0
SAR0, Channel #1
SAR0, Channel #2
SAR0, Channel #3
SAR0, Channel #4
SAR0, Channel #5
SAR0, Channel #6
SAR0, Channel #7
SAR0, Channel #8
SAR0, Channel #9
SAR0, Channel #10
SAR0, Channel #11
SAR0, Channel #12
SAR0, Channel #13
SAR0, Channel #14
SAR0, Channel #15
SAR0, Channel #16
SAR0, Channel #17
SAR0, Channel #18
SAR0, Channel #19
SAR0, Channel #20
SAR0, Channel #21
SAR0, Channel #22
SAR0, Channel #23
SAR0, Channel #24
SAR0, Channel #25
SAR0, Channel #26
SAR0, Channel #27
SAR0, Channel #28
SAR0, Channel #29
SAR0, Channel #30
SAR0, Channel #31
SAR1, Channel #0
SAR1, Channel #1
SAR1, Channel #2
SAR1, Channel #3
SAR1, Channel #4
SAR1, Channel #5
SAR1, Channel #6
SAR1, Channel #7
SAR1, Channel #8
Datasheet
96
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Peripheral protection unit fixed structure pairs
Table 22-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_PASS0_SAR1_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH10_CH
0x40901A40
0x00000040
SAR1, Channel #9
SAR1, Channel #10
SAR1, Channel #11
SAR1, Channel #12
SAR1, Channel #13
SAR1, Channel #14
SAR1, Channel #15
SAR1, Channel #16
SAR1, Channel #17
SAR1, Channel #18
SAR1, Channel #19
SAR1, Channel #20
SAR1, Channel #21
SAR1, Channel #22
SAR1, Channel #23
SAR1, Channel #24
SAR1, Channel #25
SAR1, Channel #26
SAR1, Channel #27
SAR1, Channel #28
SAR1, Channel #29
SAR1, Channel #30
SAR1, Channel #31
SAR2, Channel #0
SAR2, Channel #1
SAR2, Channel #2
SAR2, Channel #3
SAR2, Channel #4
SAR2, Channel #5
SAR2, Channel #6
SAR2, Channel #7
PASS0 SAR main
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
0x40901A80
0x40901AC0
0x40901B00
0x40901B40
0x40901B80
0x40901BC0
0x40901C00
0x40901C40
0x40901C80
0x40901CC0
0x40901D00
0x40901D40
0x40901D80
0x40901DC0
0x40901E00
0x40901E40
0x40901E80
0x40901EC0
0x40901F00
0x40901F40
0x40901F80
0x40901FC0
0x40902800
0x40902840
0x40902880
0x409028C0
0x40902900
0x40902940
0x40902980
0x409029C0
0x409F0000
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00001000
PERI_MS_PPU_FX_PASS0_SAR1_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH31_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH
PERI_MS_PPU_FX_PASS0_TOP
Datasheet
97
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Bus masters
23
Bus masters
The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus
master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC function-
ality.
Table 23-1
Bus masters for access and protection control
ID No.
Master ID
Description
Master ID for CM0+
0
1
CPUSS_MS_ID_CM0
Master ID for Crypto
Master ID for P-DMA0
Master ID for P-DMA1
Master ID for M-DMA0
CPUSS_MS_ID_CRYPTO
CPUSS_MS_ID_DW0
CPUSS_MS_ID_DW1
CPUSS_MS_ID_DMAC
CPUSS_MS_ID_SLOW0
CPUSS_MS_ID_SLOW1
CPUSS_MS_ID_CM7_1
CPUSS_MS_ID_CM7_0
CPUSS_MS_ID_TC
2
3
4
Master ID for External AHB-Lite Master 0 (SDHC)
Master ID for External AHB-Lite Master 1 (ETH0)
Master ID for CM7_1
5
6
13
14
15
Master ID for CM7_0
Master ID for DAP Tap Controller
Datasheet
98
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Miscellaneous configuration
24
Miscellaneous configuration
Table 24-1
Miscellaneous configuration for XMC7100 devices
Sl. No.
Configuration
Number/Instances
Description
Number of clock paths. One for each of FLL, PLL, Direct and CSV
Number of CLK_HFs present
0
1
SRSS_NUM_CLKPATH
7
8
SRSS_NUM_HFROOT
PERI_PC_NR
Number of protection contexts
2
8
Number of asynchronous PCLK groups
3
PERI_PERI_PCLK_PCLK_GROUP_NR
2
Group 0, Number of divide-by-8 clock dividers
Group 0, Number of divide-by-16 clock dividers
Group 0, Number of programmable clocks [1, 256]
Group 1, Number of divide-by-8 clock dividers
Group 1, Number of divide-by-16 clock dividers
Group 1, Number of divide-by-24.5 clock dividers
Group 1, Number of programmable clocks [1, 256]
Number of MPU regions in CM0+
4
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT
CPUSS_CM0P_MPU_NR
3
5
1
7
6
8
16
17
16
121
8
9
10
11
12
CM7_0 Floating point unit configuration.
0 - No FPU
13
CPUSS_CM7_0_FPU_LVL
2
1 - Single precision FPU
2 - Single and Double precision FPU
Number of MPU regions in CM7_0
14
15
16
17
18
CPUSS_CM7_0_MPU_NR
16
16
16
16
16
CM7_0 Instruction cache (ICACHE) size in KB
CM7_0 Data cache size (DCACHE) in KB
CM7_0 Instruction TCM (ITCM) size in KB
CM7_0 Data TCM (DTCM) size in KB
CPUSS_CM7_0_ICACHE_SIZE
CPUSS_CM7_0_DCACHE_SIZE
CPUSS_CM7_0_ITCM_SIZE
CPUSS_CM7_0_DTCM_SIZE
CM7_1 Floating point unit configuration.
0 - No FPU
19
CPUSS_CM7_1_FPU_LVL
2
1 - Single precision FPU
2 - Single and Double precision FPU
Number of MPU regions in CM7_1
CM7_1 Instruction cache (ICACHE) size in KB
CM7_1 Data cache size (DCACHE) in KB
CM7_1 Instruction TCM (ITCM) size in KB
CM7_1 Data TCM (DTCM) size in KB
Number of P-DMA0 channels
20
21
22
23
24
25
26
27
CPUSS_CM7_1_MPU_NR
CPUSS_CM7_1_ICACHE_SIZE
CPUSS_CM7_1_DCACHE_SIZE
CPUSS_CM7_1_ITCM_SIZE
CPUSS_CM7_1_DTCM_SIZE
CPUSS_DW0_CH_NR
16
16
16
16
16
100
58
8
Number of P-DMA1 channels
CPUSS_DW1_CH_NR
Number of M-DMA0 controller channels
CPUSS_DMAC_CH_NR
Number of 32-bit words in the IP internal memory buffer (to allow for a
256-B, 512-B, 1-KB, 2-KB, 4-KB, 8-KB, 16-KB, and 32-KB memory buffer)
28
29
CPUSS_CRYPTO_BUFF_SIZE
CPUSS_FAULT_FAULT_NR
2048
4
Number of fault structures
Number of IPC structures
0 - Reserved for CM0+ access
1 - Reserved for CM7_0 access
2 - Reserved for CM7_1 access
3 - Reserved for DAP access
Remaining for user purposes
30
CPUSS_IPC_IPC_NR
8
Number of SMPU protection structures
31
32
CPUSS_PROT_SMPU_STRUCT_NR
SCB0_EZ_DATA_NR
16
Number of EZ memory bytes. This memory is used in EZ mode,
CMD_RESP mode and FIFO mode.
Note: Only SCB0 supports EZ mode
256
Number of input triggers per counter, routed to one counter
Number of input triggers routed to all counters, based on the pin package
Number of TCPWM0 counter groups
33
34
35
36
TCPWM0_TR_ONE_CNT_NR
TCPWM0_TR_ALL_CNT_NR
TCPWM0_GRP_NR
3
27
3
Number of counters per TCPWM0 Group #0
TCPWM0_GRP_NR0_GRP_GRP_CNT_NR
63
Counter width in number of bits per TCPWM0
Group #0
37
TCPWM0_GRP_NR0_CNT_GRP_CNT_WIDTH
16
Datasheet
99
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Miscellaneous configuration
Table 24-1
Miscellaneous configuration for XMC7100 devices (continued)
Sl. No.
Configuration
Number/Instances
Description
Number of counters per TCPWM0 Group #1
38
39
40
41
TCPWM0_GRP_NR1_GRP_GRP_CNT_NR
TCPWM0_GRP_NR1_CNT_GRP_CNT_WIDTH
TCPWM0_GRP_NR2_GRP_GRP_CNT_NR
TCPWM0_GRP_NR2_CNT_GRP_CNT_WIDTH
12
Counter width in number of bits per TCPWM0
Group #1
16
8
Number of counters per TCPWM0 Group #2
Counter width in number of bits per TCPWM0
Group #2
32
Message RAM size in KB shared by all the channels
Number of Event Generator comparator structures
42
43
CANFD0_MRAM_SIZE / CANFD1_MRAM_SIZE
EVTGEN_COMP_STRUCT_NR
32
16
Datasheet
100
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Development support
25
Development support
XMC7100 has a rich set of documentation, programming tools, and online resources to assist during the devel-
opment process. Visit www.infineon.com to find out more.
25.1
Documentation
A suite of documentation supports XMC7100 to ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
25.1.1
Software user guide
A step-by-step guide for using the sample driver library along with Infineon IDE ModusToolbox™ software.
25.1.2
Technical reference manual
The Technical Reference Manual (TRM) contains all the technical detail needed to use a XMC7100 device,
including a complete description of all registers. The TRM is available in the documentation section at
www.infineon.com.
25.2
Tools
XMC7100 is supported on Infineon IDE ModusToolbox™ software that gives user experience with either a local or
GitHub-hosted set of software repos. XMC7100 is also supported by Infineon programming utilities for
programming, erasing, or reading using Infineon’s MiniProg4 or KitProg3. More details are available in the
documentation section at www.infineon.com.
Datasheet
101
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26
Electrical specifications
26.1
Absolute maximum ratings
Use of this device under conditions outside the Min and Max limits listed in Table 26-1 may cause permanent
damage to the device. Exposure to conditions within the limits of Table 26-1 but beyond those of normal
operation for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C
in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When operated under condi-
tions within the limits of Table 26-1 but beyond those of normal operation, the device may not operate to speci-
fication.
Power considerations
The average chip-junction temperature, TJ, in °C, may be calculated using Equation 1:
TJ = TA + PD JA
Equation. 1
Where:
TA is the ambient temperature in °C.
JA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PIO (PD = PINT + PIO).
θ
PINT is the chip internal power. (PINT = VDDD × IDD + VDDA × IA)
PIO represents the power dissipation on input and output pins; user determined.
For most applications, PIO < PINT and may be neglected.
On the other hand, PIO may be significant if the device is configured to continuously drive external modules
and/or memories.
WARNING:
• The recommended operating conditions are required to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are guaranteed when the device is operated under these
conditions.
• Operation under any conditions other than those mentioned in the respective “Details/Conditions” may
adversely affect reliability of the device and can result in device failure.
• No guarantee is made with respect to any use, operating conditions, or combinations not represented in this
datasheet. If you want to operate the device under any condition other than those listed herein, contact the
sales representatives.
Datasheet
102
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
For ports 0, 1, 2, 3,
4, 5, 16, 17, 18, 19,
20, 21, 22, 23, 28,
29, 30, 31
SID10
VDDD_ABS
VDDD power supply voltage[42] VSSD – 0.3
–
VSSD + 6.0
V
VDDIO_1 power supply
VSSD – 0.3
For ports 6, 7, 8, 9,
32
For ports 10, 11, 12,
13, 14, 15, 26, 27
SID10B VDDIO_1_ABS
SID10C VDDIO_2_ABS
SID10D VDDIO_3_ABS
–
–
–
–
–
VSSD + 6.0
VSSD + 6.0
V
V
V
V
V
voltage[42]
VDDIO_2 power supply
VSSD – 0.3
voltage[42]
VDDIO_3 power supply
VSSIO_3
0.3
–
VSSIO_3
4.0
+
For ports 24, 25
VDDIO_2 = VDDA
voltage[42]
VDDA analog power supply
voltage[42]
SID11
SID12
VDDA_ABS
VSSA – 0.3
VSSA – 0.3
VSSA – 0.3
VSSA + 6.0
VSSA + 6.0
Analog reference voltage,
VREFH
VREFH_ABS
HIGH[42]
(VDDA + 0.3 V)
Analog reference voltage,
LOW[42]
VCCD Power supply voltage[42] VSSD – 0.3
SID12A VREFL_ABS
SID13 VCCD_ABS
–
–
VSSA + 0.3
V
V
VSSD + 1.21
For ports 0, 1, 2, 3,
4, 5, 16, 17, 18, 19,
20, 21, 22, 23, 28,
29, 30, 31
SID15A VI0_ABS
Input voltage[42]
VSSD – 0.5
–
VDDD + 0.5
V
VDDIO_1
0.5
VDDIO_2
0.5
VDDIO_3
0.5
+
+
+
For ports 6, 7, 8, 9,
32
For ports 10, 11, 12,
13, 14, 15, 26, 27
SID15B VI1_ABS
SID15C1 VI2_ABS
SID15D VI3_ABS
Input voltage[42]
Input voltage[42]
Input voltage[42]
VSSD – 0.5
VSSD – 0.5
–
–
–
V
V
V
VSSIO_3
0.5
–
For ports 24, 25
For EXT_PS_CTL0
in external
PMIC/transistor
mode,
SID15F VI5_ABS
Input voltage[42]
VSSD – 0.5
–
VDDD + 0.5
V
EXT_PS_CTL1 in
external transistor
mode.
SID16
VIA_ABS
Analog input voltage[42]
Output voltage[42]
VSSA – 0.3
VSSD – 0.3
–
–
VDDA + 0.3
VDDD + 0.3
V
V
For ports 0, 1, 2, 3,
4, 5, 16, 17, 18, 19,
20, 21, 22, 23, 28,
29, 30, 31
SID17A VO0_ABS
VDDIO_1
0.3
VDDIO_2
0.3
VDDIO_3
0.3
+
+
+
For ports 6, 7, 8, 9,
32
For ports 10, 11, 12,
13, 14, 15, 26, 27
SID17B VO1_ABS
SID17C1 VO2_ABS
SID17D VO3_ABS
Output voltage[42]
Output voltage[42]
Output voltage[42]
VSSD – 0.3
VSSD – 0.3
–
–
–
V
V
V
VSSIO_3
0.3
–
For ports 24, 25
Note
42.These parameters are based on the condition that VSSD = VSSA = VSSIO_3 = 0.0 V.
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
For
EXT_PS_CTL1/2 in
external PMIC
SID17F VO4_ABS
Output voltage[42]
VSSD – 0.3
–
VDDD + 0.3
V
mode, DRV_VOUT
in external
transistor mode
Maximum clamp current[43,
SID18
|ICLAMP_ABS
|
–5
–
–
–
5
mA
mA
44, 45]
Maximum positive clamp
current per I/O supply pin.
Limit applies to I/O supply pin
closest to the B+ injected
current[46]
+B injected DC
current is not
allowed for Ports
11 and 21.
ICLAMP_SUP-
PLY_POS_ABS
SID18A
10
Maximum negative clamp
current per I/O ground pin.
Limit applies to I/O supply pin
closest to the B+ injected
current[46]
+B injected DC
current is not
allowed for Ports
11 and 21.
ICLAMP_SUP-
PLY_NEG_ABS
SID18B
–
–
10
mA
Maximum positive clamp
current per I/O supply, if not
limited by the per supply pin
(based on SID18A).
Maximum negative clamp
current per I/O ground, if not
limited by the per supply pin
(based on SID18B).
ICLAMP_TO-
TAL_POS_ABS
SID18C
SID18D
–
–
–
–
–
–
–
–
–
–
–
–
50
50
6
mA
mA
mA
mA
mA
mA
ICLAMP_TO-
TAL_NEG_ABS
GPIO_STD,
configured for
drive_sel<1:0>=
0b0X
GPIO_STD,
configured for
drive_sel<1:0>=
0b10
GPIO_STD,
configured for
drive_sel<1:0>=
0b11
GPIO_ENH,
configured for
drive_sel<1:0>=
0b0X
LOW-level maximum output
current[47]
SID20A IOL1A_ABS
SID20B IOL1B_ABS
SID20C IOL1C_ABS
LOW-level maximum output
current[47]
2
LOW-level maximum output
current[47]
1
LOW-level maximum output
current[47]
SID21A IOL2A_ABS
6
Notes
43.A current-limiting resistor must be provided such that the current at the I/O pin does not exceed rated values at any time, including
during power transients. Refer to Figure 26-1 for more information on the recommended circuit.
44.VDDD and VDDIO must be sufficiently loaded or protected to prevent them from being pulled out of the recommended operating range
by the clamp current.
45.When the conditions of [42], [44] and SID18A/B/C/D are met, |ICLAMP_ABS| supersedes VIA_ABS and VI_ABS.
46.The definition of “closer” depends on the package. In TEQFP packaging, “closest” is determined by counting pins. For example, in a
176-TEQFP package, P17.4 (pin 120) is closer to the VDDD on pin 110 than on pin 132. Ports 11 and 21 should not be used for injection
currents. The impact of injection currents is only defined for GPIO_STD/GPIO_ENH type I/Os. In BGA packaging, the following IO port
groups are treated as having separate supply pins: Ports 0, 1, 2, 22, 23, and 28; Ports 3, 4, 5, 29, 30, and 31; Ports 6, 7, 8, 9, and 32; Ports
10, 12, 13, 14, 15, 26, and 27; Ports 16 and 17; Ports 18, 19, and 20.
47.The maximum output current is the peak current flowing through any one I/O.
Datasheet
104
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
GPIO_ENH,
LOW-level maximum output
current[47]
configured for
drive_sel<1:0>=
0b10
SID21B IOL2B_ABS
–
–
2
mA
GPIO_ENH,
configured for
drive_sel<1:0>=
0b11
LOW-level maximum output
current[47]
SID21C IOL2C_ABS
–
–
1
mA
HSIO, configured
LOW-level maximum output
current[47]
SID22A IOL3A_ABS
SID22B IOL3B_ABS
SID22C IOL3C_ABS
SID22D IOL3D_ABS
–
–
–
–
–
–
–
–
10
2
mA for drive_sel<1:0>=
0b00
HSIO, configured
mA for drive_sel<1:0>=
0b01
HSIO, configured
mA for drive_sel<1:0>=
0b10
HSIO, configured
mA for drive_sel<1:0>=
0b11
LOW-level maximum output
current[47]
LOW-level maximum output
current[47]
1
LOW-level maximum output
current[48]
0.5
For pin
EXT_PS_CTL1 in
external PMIC
mode and internal
mA regulator mode
and pin
SID23A IOL4A_ABS
Sink maximum current[48]
–
–
4
EXT_PS_CTL2 in
external PMIC
mode
For pin
EXT_PS_CTL1 in
external PMIC
mode and internal
mA regulator mode
and pin
SID23B IOL4B_ABS
Sink average current[50]
Sink maximum current[47]
–
–
–
–
1
EXT_PS_CTL2 in
external PMIC
mode
For pin DRV_VOUT
mA in external
SID23C IOL4C_ABS
25
transistor mode
LOW-level total output
current[49]
SID26A ∑IOL_ABS_GPIO
SID26B ∑IOL_ABS_HSIO
–
–
–
–
50
85
mA
LOW-level total output
mA
current[52]
GPIO_STD,
HIGH-level maximum output
current[48]
configured for
SID27A IOH1A_ABS
–
–
–5
mA
drive_sel<1:0>=
0b0X
Notes
48.The maximum output current is the peak current flowing through any one I/O.
49.The total output current is the maximum current flowing through all GPIO_STD and GPIO_ENH I/Os.
Datasheet
105
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
GPIO_STD,
HIGH-level maximum output
current[48]
configured for
drive_sel<1:0>=
0b10
SID27B IOH1B_ABS
SID27C IOH1C_ABS
SID28A IOH2A_ABS
SID28B IOH2B_ABS
SID28C IOH2C_ABS
–
–
–2
mA
GPIO_STD,
configured for
drive_sel<1:0>=
0b11
GPIO_ENH,
configured for
drive_sel<1:0>=
0b0X
GPIO_ENH,
configured for
drive_sel<1:0>=
0b10
GPIO_ENH,
configured for
drive_sel<1:0>=
0b11
HIGH-level maximum output
current[48]
–
–
–
–
–
–
–
–
–1
–5
–2
–1
mA
mA
mA
mA
HIGH-level maximum output
current[48]
HIGH-level maximum output
current[48]
HIGH-level maximum output
current[48]
HSIO, configured
HIGH-level maximum output
current[48]
SID29A IOH3A_ABS
SID29B IOH3B_ABS
SID29C IOH3C_ABS
SID29D IOH3D_ABS
–
–
–
–
–
–
–
–
–10
–2
mA for drive_sel<1:0>=
0b00
HSIO, configured
mA for drive_sel<1:0>=
0b01
HSIO, configured
mA for drive_sel<1:0>=
0b10
HSIO, configured
mA for drive_sel<1:0>=
0b11
HIGH-level maximum output
current[48]
HIGH-level maximum output
current[48]
–1
HIGH-level maximum output
current[48]
–0.5
For pin
EXT_PS_CTL1 in
external PMIC
mode and internal
mA regulator mode
and pin
SID30A IOH4A_ABS
SID30B IOH4B_ABS
SID30C IOH4C_ABS
Source maximum current[48]
Source maximum current[48]
Source average current[50]
–
–
–
–
–
–
–4
–25
–1
EXT_PS_CTL2 in
external PMIC
mode.
For pin DRV_VOUT
mA in external
transistor mode.
For pin
EXT_PS_CTL1 in
external PMIC
mode and internal
mA regulator mode
and pin
EXT_PS_CTL2 in
external PMIC
mode.
Datasheet
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-1
Absolute maximum ratings (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
For pin DRV_VOUT
SID30D IOH4D_ABS
Source average current[50]
–
–
–12
mA in external
transistor mode.
HIGH-level total output
current[51]
SID33A ∑IOH_ABS_GPIO
SID33B ∑IOH_ABS_HSIO
SID33D PIO
–
–
–
–
–
–
–
–
–
–
–50
–85
mA
mA
HIGH-level total output
current[52]
Total output power
dissipation[53]
Power dissipation for external
PMIC/transistor mode
Power dissipation for internal
regulator mode
307
mW
mW
mW
TJ should not
exceed 150 °C
TJ should not
exceed 150 °C
SID34
PD
1000
2000
SID34A PD
SID36
SID37
TA
TSTG
Ambient temperature
Storage temperature
–40
–55
–
–
125
150
°C
°C
Operating junction
temperature
Electrostatic discharge
human body model
Electrostatic discharge
charged device model for
corner pins
Electrostatic discharge
charged device model for all
other pins
SID38
TJ
–40
–
–
150
–
°C
V
SID39A VESD_HBM
SID39B1 VESD_CDM1
2000
750
500
–
–
–
–
–
V
V
SID39B2 VESD_CDM2
SID39C ILU
The maximum pin current the
device can tolerate before
triggering a latch-up
–100
100
mA
Notes
50.The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a
10 ms period. The average value is the operation current × the operation ratio. The operation current period over the average current
spec should be less than 100 ns.
51.The total output current is the maximum current flowing through all GPIO_STD and GPIO_ENH I/Os.
52.The total output current is the maximum current flowing through all HSIO_STD I/Os.
53.The total output power dissipation is the maximum power dissipation flowing through all I/Os. PIO = (VDDD,VDDIO_1,VDDIO_2) ×
(|∑IOH_ABS_GPIO| + |∑IOL_ABS_GPIO|) + VDDIO_3 × (|∑IOH_ABS_HSIO| + |∑IOL_ABS_HSIO|)
Datasheet
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VDDD or VDDIO
Current
limiting
resistor
Protection
Diode
+B input
Protection
Diode
VSSD
Example of a recommended circuit[54]
Figure 26-1
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current, or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
26.2
Device-level specifications
Table 26-2
Recommended operating conditions
Unit
s
Spec ID Parameter
Description
Min
Typ
Max
Details/Conditions
V
DDD, VDDA
,
SID40
VDDIO_1
VDDIO_2
,
,
Power supply voltage[55]
2.7[56]
–
5.5[57]
V
Power supply voltage for
eFuse programming[58]
Power supply voltage
SID40A
VDDIO_1_EFP
3
–
–
5.5
3.6
V
V
SID40B VDDIO_3
2.7
External VCCD power
supply range when
externally
SID40C VCCD
External VCCD power supply
Smoothing capacitor[59, 60]
1.10
6.79
1.15
–
1.20
22
V
supplying VCCD
SID41
CS1
µF
Notes
54.+B is the positive battery voltage around 45 V.
55.VDDD, VDDIO_1, VDDIO_2, VDDIO_3, and VDDA do not have any sequencing limitation and can establish in any order. These supplies (except
VDDA and VDDIO_2) are independent in voltage level. See 12-Bit SAR ADC DC Specifications when using ADC units.
56.3.0 V ±10% is supported with a lower BOD setting option for VDDD and VDDA. This setting provides robust protection for internal timing
but BOD reset occurs at a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with
down to 3.0 V) and guarantees that all operating conditions are met.
57.5.0 V ±10% is supported with a higher OVD setting option for VDDD and VDDA. This setting provides robust protection for internal and
interface timing, but OVD reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available
(consistent with up to 5.0 V) and guarantees that all operating conditions are met.
58.eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single CAN
channel on VDDD domain, no activity on VDDIO_1).
59.Smoothing capacitor, CS1 is required per chip (not per VCCD pin). The VCCD pins must be connected together to ensure a low-impedance
connection (see the requirement in Figure 26-2).
60.Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC
power across them provide less than their target capacitance, and their capacitance is not constant across their working voltage range.
When selecting capacitors for use with this device, ensure that the selected components provide the required capacitance under the
specific operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally found
within a part’s catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component datasheet
or direct from the manufacturer. Use of components that do not provide the required capacitance under the actual operating condi-
tions may cause the device to operate to less than datasheet specifications.
Datasheet
108
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VCCD
VSSD
VREF_L
CS1
VSSA
Single-point connection
between analog and
digital grounds
Figure 26-2
Smoothing capacitor
Smoothing capacitor should be placed as close as possible to the VCCD pin.
26.3
Smoothing capacitor recommendations
Table 26-3
Smoothing capacitor connections
Package
100-TEQFP
144-TEQFP
176-TEQFP
272-BGA
CS1 @ pin pair
VCCD: 89, VSSD: 88
VCCD: 127, VSSD: 126
VCCD: 156, VSSD: 155
VCCD: F13, VSSD: G12
Datasheet
109
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.4
DC specifications
Table 26-4
DC specifications, CPU current, and transition time specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Active/Sleep mode
CM0+ and CM7_0 clocked at 8
MHz with IMO. CM7_1 powered
off.
All peripherals are disabled. No
IO toggling. CM0+ and CM7_0
executing Dhrystone from flash
with cache enabled.
V
current in internal regulator
DDD
I
mode, LPACTIVE mode
DD_VDDD_CM07_8_
SID49C14
–
9
13
mA
(CM0+ and CM7_0 at 8 MHz, all periph-
erals are disabled)
1_4M
TYP: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
MAX: T = 25 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
CM0+ and CM7_0 clocked at 8
MHz with IMO. CM7_1 powered
off. All peripherals are enabled.
No IO toggling.
CM0+ and CM7_0 executing
Dhrystone from flash with cache
enabled. M-DMA transferring
data from code + work flash,
P-DMA chains with maximum
trigger activity.
V
current in internal regulator
DDD
I
4M
mode, LPACTIVE mode
DD_VDDD_CM07_8_
SID49C4
–
10
141
mA
(CM0+ and CM7_0 at 8 MHz, all periph-
erals are enabled)
TYP: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
MAX: T = 105 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
PLL enabled at
250 MHz with ECO reference.
All peripherals are enabled. No
IO toggling. CM7_1 powered off.
CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
V
current in external
CCD
PMIC/transistor mode, Active mode
(CM7_0 at
I
DD1_VC-
CD_CM7_250
SID49G1
–
82
240
mA
250 MHz, CM0+ at 80 MHz, all periph-
erals are enabled)
TYP: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
MAX: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
Datasheet
110
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-4
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
PLL enabled at
250 MHz with ECO reference.
All peripherals are enabled. No
IO toggling. CM7_1 powered off.
CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
V
current in external
DDD
PMIC/transistor mode, Active mode
(CM7_0 at
I
DD1_-
VDDD_CM7_250
SID49G2
–
7
9
mA
250 MHz, CM0+ at 80 MHz, all periph-
erals are enabled)
TYP: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
MAX: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
PLL enabled at
250 MHz with ECO reference.
All peripherals are enabled. No
IO toggling.
CM7 CPUs and CM0+ executing
Dhrystone from flash with cache
enabled.
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
V
current in external
CCD
PMIC/transistor mode, Active mode
(CM7 CPUs at 250 MHz, CM0+ at 80
MHz, all peripherals are enabled)
SID50G1
I
–
124
287
mA
DD1_VCCD_F250
TYP: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
MAX: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
PLL enabled at
250 MHz with ECO reference.
All peripherals are enabled. No
IO toggling.
CM7 CPUs and CM0+ executing
Dhrystone from flash with cache
enabled.
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
V
current in external
DDD
PMIC/transistor mode, Active mode
(CM7 CPUs at 250 MHz, CM0+ at 80
MHz, all peripherals are enabled)
SID50G2
I
–
7
9.3
mA
DD1_VDDD_F250
TYP: T = 25 °C,
A
V
= 5.0 V,
DDD
process typ (TT)
MAX: T = 125 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
IMO clocked at 8 MHz.
All peripherals, PLL, FLL,
peripheral clocks, interrupts,
CSV, DMA are disabled. No IO
toggling.
V
current in internal regulator
DDD
SID53A4
I
mode. CM7_1=OFF, Other CPUs in
Sleep
–
7
140
mA
TYP: T = 25 °C,
DD2_8_VDDD_4M
A
V
= 5.0 V,
DDD
process typ (TT)
MAX: T = 105 °C,
A
V
= 5.5 V,
DDD
process worst (FF)
Datasheet
111
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-4
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
T = 25 °C, 64-KB SRAM retention,
A
Event generator operates with
ILO0 in DeepSleep and LP Active,
Smart I/O operates with ILO0,
CM0+, CM7_0: Retain, CM7_1:
OFF.
TYP: V
MAX: V
(FF)
= 5.0 V, process typ (TT)
DDD
= 5.5 V, process worst
DDD
This average current is achieved
under the following conditions.
1. MCU repetitively goes from
DeepSleep to LP Active with a
period of 32 ms.
2. One of the I/Os is toggled using
Smart I/O to activate an external
sensor connected to an analog
input of A/D in DeepSleep
3. After 200 µs delay, the CM7_0
wakes up by Event generator
trigger to LP Active mode with
IMO and A/D conversion is
triggered by software.
Average current for cyclic wake-up
operation. This is the average current
for the specified LPACTIVE mode and
DeepSleep mode (RTC, WDT, and
Event Generator operating).
SID58A
I
–
60
198
µA
DD_CWU2
4. Group A/D conversion is
performed on 5 channels with
the sampling time of 1 µs each.
5. Once the group A/D conversion
is finished, and the results fit in
the window of the range
comparator, the I/O is toggled
back by software to de-activate
the sensor and the CM7_0 goes
back to DeepSleep.
DeepSleep mode
DeepSleep Mode (RTC, WDT and
event generator operating, all
other peripherals are off except
for retention registers)
SID64A
SID64C
I
64-KB SRAM retention, ILO0 operation
64 KB SRAM retention, ILO0 operation
–
–
50
138
5.5
µA
CM0+, CM7_0: Retained
DD_DS64A
T = 25 °C
A
TYP: V
= 5.0 V, process typ (TT)
DDD
MAX: V
(FF)
= 5.5 V, process worst
DDD
DeepSleep Mode steady state at
T = 125 °C (RTC, WDT, and event
A
generator operating, all other
peripherals are off except for
retention registers),
I
1.4
mA
DD_DS64C
CM0+, CM7_0: Retained
Typ: V
= 5.0 V
DDD
process worst (TT)
Max: V
process worst (FF)
= 5.5 V
DDD
Hibernate mode
ILO0/WDT operating. All other
peripherals, and CPUs are off.
SID66
I
Hibernate Mode
Hibernate Mode
–
–
8
–
–
µA
µA
DD_HIB1
DD_HIB2
T = 25°C, V
= 5.0 V, Process
DDD
A
typ (TT)
ILO0/WDT operating. All other
peripherals, and CPUs are off.
SID66A
I
180
T = 125°C, V
= 5.5 V, Process
DDD
A
worst (FF)
Datasheet
112
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-4
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Power mode transition times
When the IMO is already running
and all HFCLK roots are at least 8
MHz. HFCLK roots that are slower
than this will require additional
time to turn off.
Power down time from Active to
DeepSleep
SID69
t
–
–
2.5
µs
ACT_DS
When using the 8-MHz IMO.
Measured from wakeup
interrupt during DeepSleep until
wakeup.
DeepSleep to Active transition time
(IMO clock)
[61]
SID67
t
t
–
–
–
–
10
µs
µs
DS_ACT
When using the 8-MHz IMO.
Measured from wakeup
interrupt during DeepSleep until
flash execution.
DeepSleep to Active transition time
(IMO clock, flash execution)
[61]
SID67C
26
DS_ACT1
When using the FLL to generate
96 MHz from the 8-MHz IMO.
Measured from wakeup
interrupt during DeepSleep until
the FLL locks.
DeepSleep to Active transition time
(FLL clock)
[61]
SID67A
SID67D
SID67B
t
t
t
–
–
–
–
–
–
15
µs
µs
µs
DS_ACT_FLL
DS_ACT_FLL1
DS_ACT_PLL
When using the FLL to generate
96 MHz from the 8-MHz IMO.
Measured from wakeup
interrupt
DeepSleep to Active transition time
(FLL clock, flash execution)
[61]
26
during DeepSleep until flash
execution.
When using the PLL to generate
96 MHz from the 8-MHz IMO.
Measured from wakeup
DeepSleep to Active transition time
(PLL clock)
[61]
60
interrupt during DeepSleep until
the PLL locks.
ReleasetimefromHVreset(POR, BOD,
OVD, OCD, WDT, Hibernate wakeup, or
XRES_L) release until CM0+ begins
executing ROM boot
Without boot runtime,
guaranteed by design
SID68
t
t
–
–
–
–
265
10
µs
µs
HVR_ACT
LVR_ACT
Release time from LV reset (Fault,
Internal system reset, MCWDT, or CSV)
during Active/Sleep until CM0+ begins
executing ROM boot
Without boot runtime.
Guaranteed by design
SID68A
Release time from LV reset (Fault, or
MCWDT) during DeepSleep until CM0+
begins executing ROM boot
Without boot runtime.
Guaranteed by design
SID68B
SID80A
t
t
–
–
–
–
15
µs
µs
LVR_DS
RB_N
ROM boot startup time or wakeup
time from hibernate in NORMAL
protection state
Guaranteed by Design, CM0+
clocked at 100 MHz (Flash boot
version 3.1.0.554 and later)
1640
Guaranteed by Design, TOC2_-
FLAGS = 0x2CF, CM0+ clocked at
100 MHz (Flash boot version
3.1.0.554 and later)
ROM boot startup time or wakeup
time from hibernate in SECURE
protection state
SID80B
SID81A
t
t
–
–
–
–
2330
80
µs
µs
RB_S
FB
Guaranteed by Design, TOC2_-
FLAGS = 0x2CF, CM0+ clocked at
100 MHz, (Flash boot version
3.1.0.554 and later), Listen
window = 0 ms
Flash boot startup time or wakeup
time from hibernate in
NORMAL/SECURE protection state
ROM boot startup time or wakeup
time from hibernate in NORMAL
protection state
Guaranteed by Design, CM0+
clocked at 50 MHz (Flash boot
version earlier than 3.1.0.554)
SID80A_2
SID80B_2
t
t
–
–
–
–
2640
3890
µs
µs
RB_N_2
RB_S_2
ROM boot startup time or wakeup
time from hibernate in SECURE
protection state
Guaranteed by Design, CM0+
clocked at 50 MHz (Flash boot
version earlier than 3.1.0.554)
Note
61.At cold temperature -5°C to -40°C, the DeepSleep to Active transition time can be higher than the max time indicated by as much as
20 us.
Datasheet
113
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-4
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Guaranteed by Design, TOC2_-
FLAGS=0x2CF, CM0+ clocked at
50 MHz (Flash boot version
earlier than 3.1.0.554), Listen
window = 0 ms
Flash boot startup time or wakeup
time from hibernate in
SID81A_2
t
t
–
–
200
µs
FB_2
NORMAL/SECURE protection state
Guaranteed by Design, TOC2_-
FLAGS=0x24F, CM0+ clocked at
50 MHz (Flash boot version
earlier than 3.1.0.554), Listen
window = 0 ms, Public key
exponent e = 0x010001, App size
is 64 KB with the last 256 bytes
being a digital signature in
RSASSA-PKCS1-v1.5. Valid for
RSA2K.
Flash boot with app authentication
time in NORMAL/SECURE protection
state
SID81B_2
–
–
–
–
10000
µs
µs
FB_A_2
Guaranteed by Design,
TOC2_-FLAGS=0x24F, CM0+
clocked at 100 MHz (Flash boot
version 3.1.0.554 and later),
Listen window = 0 ms, Public key
exponent e = 0x010001, App size
is 64 KB with the last 256 bytes
being a digital signature in
RSASSA-PKCS1-v1.5. Valid for
RSA2K.
Flash boot with app authentication
time in NORMAL/SECURE protection
state
SID81B
t
5000
FB_A
Regulator specifications
SID600
V
V
Core supply voltage (transient range)
1.05
1.1
1.1
1.15
V
V
CCD
Core supply voltage (static range, no
load)
SID600A
1.075
1.125
Guaranteed by design
Guaranteed by design
Guaranteed by design
CCD_S
Regulator operating current in
Active/Sleep mode
SID601
SID602
I
I
–
–
900
1.5
1500
20
µA
µA
DDD_ACT
Regulator operating current in
DeepSleep mode
DDD_DPSLP
Average V
current until C
s1
CCD
DDD
(connected to V
pin) is
SID603
I
In-rush current
–
–
850
mA
RUSH
charged after Active regulator is
turned on
Internal regulator output current for
operation
SID604
SID605
SID606
SID606A
I
I
–
–
–
–
–
–
–
300
600
0.5
–
mA
mA
V
ILDOUT
High current regulator output current
for operation
Using an external pass transistor
HCROUT
Output voltage LOW level for external
PMIC enable output (EXT_PS_CTL1)
V
V
I
I
= 1 mA
OL_HCR
OH_HCR
OL
Output voltage HIGH level for external
PMIC enable output (EXT_PS_CTL1)
V
–
DDD
V
= –1 mA
OH
0.5
Input voltage HIGH threshold for
external PMIC power OK input
(EXT_PS_CTL0)
0.7 ×
DDD
SID607
V
–
–
–
V
V
IH_HCR
IL_HCR
V
Input voltage LOW threshold for
external PMIC power OK input
(EXT_PS_CTL0)
SID607A
V
V
–
0.3 × V
DDD
Hysteresis for external PMIC power OK 0.05 ×
SID607B
SID608
–
–
–
9
V
HYS_HCR
DRV_OUT
input (EXT_PS_CTL0)
V
DDD
DRV_VOUT pin output current to
external NPN base current
See Architecture TRM for
external NPN transistor selection
I
–
mA
Datasheet
114
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.5
Reset specifications
Table 26-5
XRES_L reset
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
XRES_L DC specifications
MAX: TA = 125 °C,
VDDD = 5.5 V,
SID73
IIDD_XRES
IDD when XRES_L asserted
–
–
2.5
mA
VCCD = 1.15 V,
process worst (FF)
SID74
SID75
SID76
SID77
SID78
VIH
VIL
RPULLUP
CIN
VHYSXRES
Input voltage HIGH threshold 0.7 × VDDD
–
–
–
–
–
–
V
V
kΩ
pF
V
CMOS Input
CMOS Input
Input voltage LOW threshold
Pull-up resistor
–
7
0.3 × VDDD
20
5
–
Input capacitance
–
Input voltage hysteresis
0.05 × VDDD
XRES_L AC specifications
XRES_L deasserted to Active
transition time
Without boot runtime
Guaranteed by design
SID70
tXRES_ACT
–
–
265
µs
SID71
SID72
tXRES_PW
tXRES_FT
XRES_L pulse width
Pulse suppression width
5
100
–
–
–
–
µs
ns
release
HV/LV reset
System clock
System reset
release
RESET
ACTIVE
MODES
1
2
3
4
1:
2:
3:
4:
SID68/68A/68B: Time from HV/LV reset release until CM0+ begins executing ROM boot
SID80A/80B: ROM boot code operation
SID81A/81B: Flash boot code operation
User code operation
Figure 26-3
Reset sequence
Datasheet
115
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.6
I/O
Table 26-6
I/O specifications
Spec ID
Parameter
Description
Min
–
Typ
–
Max
0.6
0.4
0.4
0.4
0.4
0.4
0.4
–
Units
Details/Conditions
GPIO_STD Specifications for ports P1 through P23, P26 to P32
IOL = 6 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
SID650
SID650C
SID651
SID652
SID652C
SID653
SID653C
SID654
SID655
SID656
SID656C
SID657
SID657C
VOL1_GPIO_STD
VOL1C_GPIO_STD
VOL2_GPIO_STD
VOL3_GPIO_STD
VOL3C_GPIO_STD
VOL4_GPIO_STD
VOL4C_GPIO_STD
VOH1_GPIO_STD
VOH2_GPIO_STD
VOH3_GPIO_STD
VOH3C_GPIO_STD
VOH4_GPIO_STD
VOH4C_GPIO_STD
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
V
V
V
V
V
V
V
V
V
V
V
V
V
IOL = 5 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD or VDDIO_1 or
–
–
V
DDIO_2 ≤ 5.5 V
IOL = 2 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD or VDDIO_1 or
–
–
V
DDIO_2 < 4.5 V
IOL = 1 mA
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
–
–
IOL = 2 mA
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
–
–
IOL = 0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD or VDDIO_1 or
–
–
V
DDIO_2 < 4.5 V
IOL = 1 mA
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
–
–
IOH = –2 mA
(VDDD, VDDIO_1, or
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
–
V
DDIO_2) – 0.5
IOH = –5 mA
(VDDD, VDDIO_1, or
VDDIO_2) – 0.5
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD or VDDIO_1 or
–
–
V
DDIO_2 ≤ 5.5 V
IOH = –1 mA
(VDDD, VDDIO_1, or
VDDIO_2) – 0.5
drive_sel<1:0> = 0b10,
2.7 V ≤ (VDDD, VDDIO_1, or
VDDIO_2) < 4.5 V
–
–
IOH = –2 mA
(VDDD, VDDIO_1, or
drive_sel<1:0> = 0b10,
4.5 V ≤ (VDDD, VDDIO_1, or
VDDIO_2) ≤ 5.5 V
–
–
V
DDIO_2) – 0.5
IOH = –0.5 mA
(VDDD, VDDIO_1, or
VDDIO_2) – 0.5
drive_sel<1:0> = 0b11,
2.7 V ≤ (VDDD, VDDIO_1, or
–
–
V
DDIO_2) < 4.5 V
IOH = –1 mA
(VDDD, VDDIO_1, or
VDDIO_2) – 0.5
drive_sel<1:0> = 0b11,
4.5 V ≤ (VDDD, VDDIO_1, or
VDDIO_2) ≤ 5.5 V
–
–
SID658
SID659
RPD_GPIO_STD
RPU_GPIO_STD
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
0.7 × (VDDD
,
Input voltage HIGH threshold in
CMOS mode
SID660
SID661
SID662
VIH_CMOS_GPIO_STD
VIH_TTL_GPIO_STD
VIH_AUTO_GPIO_STD
V
DDIO_1, or
–
–
–
–
–
V
V
V
VDDIO_2
2.0
)
Input voltage HIGH threshold in
TTL mode
0.8 × (VDDD
,
Input voltage HIGH threshold in
AUTO mode
VDDIO_1, or
VDDIO_2
–
)
0.3 × (VDDD
,
Input voltage LOW threshold in
CMOS mode
SID663
VIL_CMOS_GPIO_STD
–
–
V
DDIO_1, or
V
VDDIO_2
)
Datasheet
116
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-6
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
0.8
Units
Details/Conditions
Input voltage LOW threshold in
TTL mode
SID664
VIL_TTL_GPIO_STD
–
–
V
0.5 × (VDDD
,
Input voltage LOW threshold in
AUTO mode
SID665
SID666
VIL_AUTO_GPIO_STD
–
–
–
VDDIO_1, or
V
V
VDDIO_2
)
0.05 × (VDDD
,
,
VHYST_CMOS_GPIO_STD Hysteresis in CMOS mode
VHYST_AUTO_GPIO_STD Hysteresis in AUTO mode
VDDIO_1, or
–
VDDIO_2
)
0.05 × (VDDD
VDDIO_1, or
VDDIO_2
SID668
SID669
–
–
–
5
V
)
Cin_GPIO_STD
Input pin capacitance
–
pF
For 10 MHz and 100 MHz
For GPIO_STD except
P21.0, P21.1, P21.2,
P21.3, P21.4, P22.1,
P22.2, P22.3, P23.3,
P23.4.
V
V
V
V
= V
= 5.5 V,
= V
=
,
DDIO_1
DDIO_2
DDD
SID670
I
Input leakage current
–250
0.02
250
nA
IL_GPIO_STD
DDA
< V < V , V
SSD
I
DDD DDIO_1
DDIO_2
–40 °C T 125 °C
A
Typ: T = 25 °C, V
=
A
DDIO_1
V
V
=V
=V
=5.0
DDA
DDIO_2
DDD
Only for P21.0, P21.1,
P21.2, P21.3, P21.4,
P22.1, P22.2, P22.3,
P23.3, P23.4.
V
V
V
V
= V
= 5.5 V,
= V
=
,
DDIO_1
DDIO_2
DDD
DDA
SID670C
I
Input leakage current
–700
0.02
700
nA
IL_GPIO_STD_B
< V < V , V
SSD
I
DDD DDIO_1
DDIO_2
–40 °C T 125 °C
A
Typ: T = 25 °C, V
=
A
DDIO_1
V
V
=V
=V
=5.0
DDA
DDIO_2
DDD
20-pF load, drive_sel<1:0>
= 0b00
tR or tF (fast)_20_0_GPI- Rise time or fall time (10% to
90% of VDDIO
SID671
SID672
SID673
SID674
SID675
1
1
1
1
1
–
–
–
–
–
10
20
20
20
20
ns
ns
ns
ns
ns
)
O_STD
50-pF load, drive_sel<1:0>
= 0b00
t
R or tF (fast)_50_0_GPI- Rise time or fall time (10% to
90% of VDDIO
)
)
O_STD
20-pF load, drive_sel<1:0>
= 0b01
t
R or tF (fast)_20_1_GPI- Rise time or fall time (10% to
90% of VDDIO
O_STD
10-pF load, drive_sel<1:0>
= 0b10
tR or tF (fast)_10_2_GPI- Rise time or fall time (10% to
90% of VDDIO
)
O_STD
6-pF load, drive_sel<1:0> =
0b11
t
R or tF (fast)_6_3_GPI- Rise time or fall time (10% to
90% of VDDIO
)
O_STD
10-pF to 400-pF load, RPU=
767 Ω, drive_sel<1:0>=
0b00,
SID676
tF (fast)_100_GPIO_STD Fall time (30% to 70% of VDDIO
tF (fast)_400_GPIO_STD Fall time (30% to 70% of VDDIO
)
)
0.35
–
250
ns
Freq = 100 kHz
10-pF to 400-pF load, RPU=
350 Ω, drive_sel<1:0>=
0b00,
SID677
SID678
SID679
0.35
–
–
–
250
100
50
ns
Freq = 400 kHz
fIN_GPIO_STD
Input frequency
–
–
MHz
MHz
20-pF load,
drive_sel<1:0>= 00,
4.5 V ≤ VDDD or VDDIO_1 or
fOUT_GPIO_STD0H
Output frequency
V
DDIO_2 ≤ 5.5 V
Datasheet
117
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-6
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
20-pF load,
drive_sel<1:0>= 00,
2.7 V ≤ VDDD or VDDIO_1 or
SID680
SID681
SID682
SID683
SID684
SID685
SID686
fOUT_GPIO_STD0L
Output frequency
–
–
32
MHz
V
DDIO_2 < 4.5 V
20-pF load,
drive_sel<1:0>= 01,
4.5 V ≤ VDDD or VDDIO_1 or
fOUT_GPIO_STD1H
fOUT_GPIO_STD1L
fOUT_GPIO_STD2H
fOUT_GPIO_STD2L
fOUT_GPIO_STD3H
fOUT_GPIO_STD3L
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
–
–
25
15
25
15
15
10
MHz
MHz
MHz
MHz
MHz
MHz
V
DDIO_2 ≤ 5.5 V
20-pF load,
drive_sel<1:0>= 01,
2.7 V ≤ VDDD or VDDIO_1 or
V
DDIO_2 < 4.5 V
10-pF load,
drive_sel<1:0>= 10,
4.5 V ≤ VDDD or VDDIO_1 or
V
DDIO_2 ≤ 5.5 V
10-pF load,
drive_sel<1:0>= 10,
2.7 V ≤ VDDD or VDDIO_1 or
V
DDIO_2 < 4.5 V
6-pF load,
drive_sel<1:0>= 11,
4.5 V ≤ VDDD or VDDIO_1 or
V
DDIO_2 ≤ 5.5 V
6-pF load,
drive_sel<1:0>= 11,
2.7 V ≤ VDDD or VDDIO_1 or
V
DDIO_2 < 4.5 V
GPIO_ENH specifications for P0
IOL = 6 mA
SID650A
SID650D
SID651A
SID652A
SID652D
SID653A
SID653D
SID654A
SID655A
SID656A
SID656D
SID657A
VOL1_GPIO_ENH
VOL1D_GPIO_ENH
VOL2_GPIO_ENH
VOL3_GPIO_ENH
VOL3D_GPIO_ENH
VOL4_GPIO_ENH
VOL4D_GPIO_ENH
VOH1_GPIO_ENH
VOH2_GPIO_ENH
VOH3_GPIO_ENH
VOH3D_GPIO_ENH
VOH4_GPIO_ENH
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
–
–
–
–
–
–
–
–
–
–
–
–
–
0.6
0.4
0.4
0.4
0.4
0.4
0.4
–
V
V
V
V
V
V
V
V
V
V
V
V
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD ≤ 5.5 V
IOL = 5 mA
–
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
IOL = 2 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
–
IOL = 1 mA
–
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
IOL = 2 mA
–
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
IOL = 0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V
–
IOL = 1 mA
–
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
I
= –2 mA
OH
VDDD – 0.5
VDDD – 0.5
VDDD – 0.5
VDDD – 0.5
VDDD – 0.5
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
I
= –5 mA
OH
–
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
I
= –1 mA
OH
–
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
I
= –2 mA
OH
–
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
I
= –0.5 mA
OH
–
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V
Datasheet
118
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-6
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
I
= –1 mA
OH
SID657D
VOH4D_GPIO_ENH
Output voltage HIGH level
VDDD – 0.5
–
–
V
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
SID658A
SID659A
RPD_GPIO_ENH
RPU_GPIO_ENH
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
Input voltage HIGH threshold in
CMOS mode
SID660A
SID661A
SID662A
SID663A
SID664A
SID665A
VIH_CMOS_GPIO_ENH
VIH_TTL_GPIO_ENH
VIH_AUTO_GPIO_ENH
VIL_CMOS_GPIO_ENH
VIL_TTL_GPIO_ENH
VIL_AUTO_GPIO_ENH
0.7 × VDDD
–
–
–
–
–
–
–
V
V
V
V
V
V
Input voltage HIGH threshold in
TTL mode
2.0
–
–
Input voltage HIGH threshold in
AUTO mode
0.8 × VDDD
Input voltage LOW threshold in
CMOS mode
–
–
–
0.3 × VDDD
0.8
Input voltage LOW threshold in
TTL mode
Input voltage LOW threshold in
AUTO mode
0.5 × VDDD
SID666A
SID668A
SID669A
VHYST_CMOS_GPIO_ENH Hysteresis in CMOS mode
VHYST_AUTO_GPIO_ENH Hysteresis in AUTO mode
0.05 × VDDD
0.05 × VDDD
–
–
–
–
–
–
5
V
V
Cin_GPIO_ENH
Input pin capacitance
pF
For 10 MHz and 100 MHz
VDDD = VDDA = 5.5 V,
V
SSD < VI < VDDD
SID670A
IIL_GPIO_ENH
Input leakage current
–350
0.055
350
nA
–40 °C TA 125 °C
TYP: TA = 25 °C,
V
DDD = VDDA = 5.0 V
20-pF load, drive_sel<1:0>
= 0b00, slow = 0
t
R or tF (fast)_20_0_GPI- Rise time or fall time (10% to
90% of VDDIO
SID671A
SID672A
SID673A
SID674A
SID675A
1
1
1
1
1
–
–
–
–
–
10
20
20
20
20
ns
ns
ns
ns
ns
)
O_ENH
50-pF load, drive_sel<1:0>
= 0b00, slow = 0
t
R or tF (fast)_50_0_GPI- Rise time or fall time (10% to
90% of VDDIO
)
O_ENH
20-pF load, drive_sel<1:0>
= 0b01, slow = 0
tR or tF (fast)_20_1_GPI- Rise time or fall time (10% to
90% of VDDIO
)
O_ENH
10-pF load, drive_sel<1:0>
= 0b10, slow = 0
t
R or tF (fast)_10_2_GPI- Rise time or fall time (10% to
90% of VDDIO
)
)
O_ENH
6-pF load, drive_sel<1:0> =
0b11, slow = 0
t
R or tF (fast)_6_3_GPI- Rise time or fall time (10% to
90% of VDDIO
O_ENH
10-pF to 400-pF load,
drive_sel<1:0> = 0b00,
slow = 1,
tF_I2C
SID676A
SID677A
SID678A
Fall time (30% to 70% of VDDIO
)
20 × (VDDD / 5.5)
20 × (VDDD / 5.5)
20 × (VDDD / 5.5)
–
–
–
250
160
250
ns
ns
(slow)_GPIO_ENH
minimum RPU = 400 Ω
20-pF load, drive_sel<1:0>
= 0b00, slow = 1,
output frequency = 1 MHz
tR or tF (slow)_20_GPI- Rise time or fall time (10% to
90% of VDDIO
)
O_ENH
400-pF load,
drive_sel<1:0>=0b00,slow
= 1, output frequency = 400
kHz
t
R or tF (slow)_400_GPI- Rise time or fall time (10% to
ns
90% of VDDIO
)
O_ENH
SID679A
SID680A
fIN_GPIO_ENH
Input frequency
–
–
–
–
100
50
MHz
20-pF load,
fOUT_GPIO_ENH0H
Output frequency
MHz drive_sel<1:0>= 0b00,
4.5 V ≤ VDDD ≤ 5.5 V
20-pF load,
MHz drive_sel<1:0>= 0b00,
SID681A
SID682A
SID683A
fOUT_GPIO_ENH0L
fOUT_GPIO_ENH1H
fOUT_GPIO_ENH1L
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
32
25
15
2.7 V ≤ VDDD < 4.5 V
20-pF load,
MHz drive_sel<1:0>= 0b01,
4.5 V ≤ VDDD ≤ 5.5 V
20-pF load,
MHz drive_sel<1:0>= 0b01,
2.7 V ≤ VDDD < 4.5 V
Datasheet
119
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-6
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
10-pF load,
SID684A
SID685A
SID686A
SID687A
fOUT_GPIO_ENH2H
Output frequency
–
–
25
MHz drive_sel<1:0>= 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
10-pF load,
MHz drive_sel<1:0>= 0b10,
fOUT_GPIO_ENH2L
fOUT_GPIO_ENH3H
fOUT_GPIO_ENH3L
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
15
15
10
2.7 V ≤ VDDD < 4.5 V
6-pF load,
MHz drive_sel<1:0>= 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
6-pF load,
MHz drive_sel<1:0>= 0b11,
2.7 V ≤ VDDD < 4.5 V
HSIO specifications for ports P24, P25
IOL = 0.1 mA,
drive_sel<1:0> = 0b00
SID651B
SID652B
SID653B
VOL_HB_HSSPI
VOL_eMMC
VOL_SD
Output LOW voltage
Output LOW voltage
Output LOW voltage
–
–
–
–
–
–
0.2
V
IOL = 0.1 mA,
drive_sel<1:0> = 0b00
0.125 × VDDIO_3
0.125 × VDDIO_3
V
IOL = 2 mA,
drive_sel<1:0> = 0b00
V
IOL = 10 mA,
drive_sel<1:0> = 0b00,
SID654B
SID655B
SID656B
SID656E
VOL1
VOL2
VOL3
VOL4
Output LOW voltage
Output LOW voltage
Output LOW voltage
Output LOW voltage
–
–
–
–
–
–
–
–
0.4
0.4
0.4
0.4
V
V
V
V
V
DDIO_3 = 2.7 V
IOL = 2 mA,
drive_sel<1:0> = 0b01,
V
DDIO_3 = 2.7 V
IOL = 1 mA,
drive_sel<1:0> = 0b10,
V
DDIO_3 = 2.7 V
IOL = 0.5 mA,
drive_sel<1:0> = 0b11,
V
DDIO_3 = 2.7 V
I
= –0.1 mA
drive_sel<1:0> = 0b00
OH
SID658B
SID659B
SID660B
VOH_HB_HSSPI
VOH_eMMC
VOH_SD
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
VDDIO_3 – 0.2
–
–
–
–
–
–
V
V
V
I
= –0.1 mA
V
V
DDIO_3 – (0.25 ×
OH
VDDIO_3
)
drive_sel<1:0> = 0b00
I
= –2 mA
DDIO_3 – (0.25 ×
VDDIO_3
OH
)
drive_sel<1:0> = 0b00
I
= –10 mA
OH
SID661B
SID662B
SID663B
SID663E
VOH1
VOH2
VOH3
VOH4
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
VDDIO_3 – 0.5
VDDIO_3 – 0.5
VDDIO_3 – 0.5
VDDIO_3 – 0.5
–
–
–
–
–
–
–
–
V
V
V
V
drive_sel<1:0> = 0b00,
DDIO_3 = 2.7 V
= –2 mA
V
I
OH
drive_sel<1:0> = 0b01,
DDIO_3 = 2.7 V
= –1 mA
V
I
OH
drive_sel<1:0> = 0b10,
DDIO_3 = 2.7 V
= –0.5 mA
V
I
OH
drive_sel<1:0> = 0b11,
V
DDIO_3 = 2.7 V
SID664B
SID665B
RPD
RPU
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
Input HIGH voltage for
HYPERBUS™ and HSSPI in
CMOS mode
SID666B
VIH_CMOS
0.7 × VDDIO_3
2
0.625 × VDDIO_3
–
–
V
vtrip_sel<1:0> = 0b00
Input Voltage HIGH threshold
for TTL mode
SID668E
SID669B
VIH_TTL
–
–
–
–
V
V
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b00
Input HIGH voltage for SD and
eMMC in CMOS mode
VIH_SD_eMMC
Datasheet
120
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-6
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Input Voltage HIGH threshold in
AUTO mode
SID669E
VIH_AUTO
0.8 × VDDIO_3
–
–
V
vtrip_sel<1:0> = 0b00
Input LOW voltage for
HYPERBUS™ and HSSPI in
CMOS mode
SID670B
VIL_CMOS
–
–
0.3 × VDDIO_3
V
vtrip_sel<1:0> = 0b00
Input Voltage LOW threshold for
TTL mode
SID672E
SID673B
SID673E
VIL_TTL
–
–
–
–
–
–
0.8
V
V
V
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b00
Input LOW voltage for SD and
eMMC in CMOS mode
VIL_SD_eMMC
VIL_AUTO
0.25 × VDDIO_3
0.5 × VDDIO_3
Input Voltage LOW threshold in
AUTO mode
SID674B
SID674F
SID675B
VHYST_CMOS
VHYST_AUTO
CIN
Hysteresis in CMOS mode
Hysteresis in AUTO mode
Input pin capacitance
0.05 × VDDIO_3
0.05 × VDDIO_3
–
–
–
–
–
–
5
V
V
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b00
For 10 MHz and 100 MHz
VDDIO_3 = 3.6 V,
pF
V
SSIO_3 < VI < VDDIO_3
SID676B
IIL
Input leakage current
–450
1.02
450
nA
–40 °C TA 125 °C
TYP: TA = 25 °C,
V
DDIO_3 = 3.3 V
SID679B
SID680B
SID681B
SID683B
SID684B
SID685B
fIN_HB_HSSPI
fIN_eMMC
Input frequency
Input frequency
Input frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
–
–
100
52
MHz
MHz
MHz
MHz
MHz
MHz
fIN_SD
50
fOUT_HB_HSSPI
fOUT_eMMC
fOUT_SD
100
52
50
GPIO input specifications
Analog glitch filter (pulse
suppression width)
SID98
SID99
tFT
–
–
–
50[62]
–
ns
ns
One filter per port
Minimum pulse width for GPIO
interrupt
tINT
160
Note
62.If a longer pulse suppression width is necessary, use Smart I/O.
Datasheet
121
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.7
Analog peripherals
SAR ADC
26.7.1
0xFFF
Actual conversion
characteristics
1.5 LSb
0xFFE
0xFFD
1 LSb (N - 1) + 0.5 LSb
VNT
0x003
0x002
0x001
Actual conversion
characteristics
Ideal
characteristics
0.5 LSb
VREFH
VREFL
Analog input
[LSb]
[V]
Total error of digital output N = ( VNT {1 LSb × (N – 1) + 0.5 LSb} ) / 1 LSb
1 LSb (Ideal value) = (VREFH – VREFL) / 4096
N: A/D converter digital output value
VZT (Ideal value): VREFL + 0.5 LSb [V]
V
FST (Ideal value): VREFH – 1.5 LSb [V]
VNT: Voltage at which the digital output changes from N – 1 to N
Figure 26-4
ADC characteristics and error descriptions
Datasheet
122
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-7
12-Bit SAR ADC DC specifications
Spec ID Parameter
SID100 A_RES
Description
SAR ADC resolution
Input voltage range
VDDA voltage range
Min
–
VREFL
2.7
Typ
–
–
Max
12
VREFH
5.5
Units Details/Conditions
bits
V
V
SID101 A_VINS
[63]
SID102A A_VDDA
–
ADC performance
degrades when high
SID102 A_VREFH
VREFH voltage range
VREFL voltage range
2.7
–
VDDA
V
reference is higher
than supply (VDDA
)
ADC performance
degrades when low
reference is lower
than ground
SID103 A_VREFL
SID103A Vband_gap
VSSA
–
VSSA
V
V
Internal band gap
reference voltage
0.882
0.9
0.918
Ratio of current collected
on a pin to the positive
current injected into a
neighboring pin
CLAMP_COU-
SID19A PLING_RA-
TIO_POS
–
–
0.1
%
Ratio of current collected
on a pin to the negative
current injected into a
neighboring pin
Internal pin resistance to
current collection point
CLAMP_COU-
SID19B PLING_RA-
TIO_NEG
–
–
–
–
1.2
50
%
RCLAMP_IN-
SID19C
Ω
TERNAL
Datasheet
123
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.7.2
Calculating the impact of neighboring pins
The three ADC specifications based on SID19A, SID19B, and SID19C, can be used to calculate the pin leakage and
resulting ADC offset caused by injection current using the below formula:
LEAK = IINJECTED × CLAMP_COUPLING_RATIO
V
ERROR = ILEAK × (RCLAMP_INTERNAL + RSOURCE
)
Code Error = VERROR × 212 / VREF
Where:
INJECTED is the injected current in mA.
ILEAK is the calculated leakage current in mA.
I
V
V
ERROR is the voltage error calculated due to leakage currents in V.
REF is the ADC reference voltage in V.
Differential linearity error
Integral linearity error
0xFFF
Ideal
characteristics
Actual conversion
characteristics
N + 1
0xFFE
0xFFD
VFST
Actual conversion
characteristics
(Measured value)
(1 LSb [N - 1] + VZT)
N
VNT
(Measured value)
0x004
0x003
0x002
0x001
N - 1
Actual conversion
characteristics
V(N +
1)T
(Measured value)
VNT
(Measured value)
Ideal
characteristics
Actual conversion
characteristics
N -2
VZT
(Measured value)
VREFL
Analog input
VREFL
Analog input
VREFH
VREFH
Integral linearity error of digital output N = (VNT
–
{1 LSb × (N
–
1) + VZT}) / 1 LSb
[LSb]
[LSb]
[V]
Differential linearity error of digital output N = (V(N + 1)T – VNT
1 LSb = (VFST – VZT ) / 4094
– 1 LSb ) / 1 LSb
VZT: Voltage for which digital output changes from 0x000 to 0x001
VFST: Voltage for which digital output changes from 0xFFE to 0xFFF.
Figure 26-5
Integral and differential linearity errors
Note
63.VDDD must be greater than 0.8 × VDDA when ADC[2] is enabled. VDDIO_1 must be greater than 0.8 × VDDA when ADC[0] is enabled.
Datasheet
124
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
EXTERNAL CIRCUIT
INTERNAL EQUIVALENT CIRCUIT
VDDIO
Channel selection MUX and ADC
REXT
RVIN
CVIN
CEXT
CIN
ESD Protection
R
C
C
R
C
EXT: Source impedance
EXT: On-PCB capacitance
IN: I/O pad or Input capacitance
VIN: ADC equivalent input resistance
VIN: ADC equivalent input capacitance
K: Constant for sampling accuracy, K = ln(abs(4096/LSbSAMPLE))
Sampling Time (tSAMPLE) requirement is shown in the following equation
tSAMPLE > K x { CVIN x ( RVIN + REXT ) + ( CIN + CEXT ) x (REXT) } [seconds]
K = value of 9.0 is recommended to get ±0.5 LSb sampling accuracy at 12-bit (LSbSAMPLE = ±0.5)
Figure 26-6
ADC equivalent circuit for analog input
Datasheet
125
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-8
SAR ADC AC specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
SID104 VZT
SID105 VFST
Zero transition voltage
–20
–
20
mV
before offset
adjustment
VDDA = 2.7 V to 5.5 V,
Full-scale transition
voltage
–40 °C ≤ TA ≤ 125 °C
–20
–
20
mV
before offset
adjustment
SID114 fADC_4P5
SID114A fADC_2P7
ADC operating frequency
ADC operating frequency
2
2
–
–
26.67
13.34
MHz 4.5 V ≤ VDDA ≤ 5.5 V
MHz 2.7 V ≤ VDDA ≤ 4.5 V
4.5 V ≤ VDDA ≤ 5.5 V,
ns guaranteed by
design
2.7 V ≤ VDDA ≤ 4.5 V,
ns guaranteed by
design
Analog input sample time
SID113 tS_4P5
SID113A tS_2P7
412
600
–
–
–
–
(4.5 V ≤ VDDA
)
Analog input sample time
(2.7 V ≤ VDDA
)
Analog input sample time
when input is from
4.5 V ≤ VDDA ≤ 5.5 V,
µs guaranteed by
design
SID113B tS_DR_4P5
2
–
–
diagnostic reference (4.5
V ≤ VDDA
)
Analog input sample time
when input is from
2.7 V ≤ VDDA ≤ 4.5 V,
µs guaranteed by
design
SID113C tS_DR_2P7
SID113D tS_TS
2.5
7
–
–
–
–
diagnostic reference (2.7
V ≤ VDDA
)
2.7 V ≤ VDDA ≤ 5.5 V,
µs Guaranteed by
design
Analog input sample time
for temperature sensor
4.5 V ≤ VDDA ≤ 5.5 V,
80 MHz / 3 = 26.67
Msps MHz,
Max Throughput
SID106 tST_4P5
SID106A tST_2P7
–
–
–
–
1
(samples per second)
11 sampling cycles,
15 conversion cycles
2.7 V ≤ VDDA < 4.5 V
Max Throughput
80 MHz /6 = 13.3 MHz,
0.5
Msps
(samples per second)
11 sampling cycles,
15 conversion cycles
ADC input sampling
capacitance
Input path ON resistance
(4.5 V to 5.5 V)
Input path ON resistance
(2.7 V to 4.5 V)
Diagnostic path ON resis-
tance (4.5 V to 5.5 V)
Guaranteed by
SID107 CVIN
–
–
–
–
–
–
–
–
4.8
9.4
13.9
40
pF
design
Guaranteed by
SID108 RVIN1
SID108A RVIN2
SID108B RDREF1
SID108C RDREF2
SID119 ACC_RLAD
kΩ
design
Guaranteed by
–
kΩ
design
Guaranteed by
–
kΩ
design
Diagnostic path ON resis-
tance (2.7 V to 4.5 V)
Guaranteed by
–
50
kΩ
design
Diagnostic reference
–4
4
%
resistor ladder accuracy
Datasheet
126
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-8
SAR ADC AC specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
LSb Total Error after
offset and gain
SID109 A_TE
SID109A A_TEB
Total error
–5
–
5
adjustment at 12-bit
resolution mode
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
LSb Total error before
offset and gain
Total error
–12
–
12
adjustment at 12 bit
resolution mode
VDDA = 2.7 V to 5.5 V,
SID110 A_INL
SID111 A_DNL
Integral nonlinearity
–2.5
–
–
2.5
1.9
LSb
–40 °C ≤ TA ≤ 125 °C
VDDA = 2.7 V to 5.5 V,
Differential nonlinearity –0.99
Channel to channel
LSb
–40 °C ≤ TA ≤ 125 °C
VDDA = 2.7 V to 5.5 V,
LSb
SID112 A_CE
variation (for channels
connected to same ADC)
–1
–
1
–40 °C ≤ TA ≤ 125 °C
When input pad is
nA selected for
conversion
Analog input leakage
current
SID115 IAIC
–350
70
–
350
70
Diagnostic reference
current
Analog power supply
current while ADC is
operating
SID116 IDIAGREF
SID117 IVDDA
–
–
µA
360
550
µA Per enabled ADC
Analog power supply
current while ADC is not
operating
Analog reference voltage
current while ADC is
operating
SID117A IVDDA_DS
SID118 IVREF
–
–
–
1
21
550
5
µA Per enabled ADC
µA Per enabled ADC
µA Per enabled ADC
360
1.8
Analog reference voltage
SID118A IVREF_LEAK current while ADC is not
operating
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-9
Temperature sensor specifications
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TJ = 150 °C
SID200 TSENSACC1
Temperature sensor
accuracy 1
–2
–
2
°C
This spec is valid when using ADC[0]
(VDDIO_1), ADC[1] (VDDIO_2) or ADC[2]
(VDDD) with the following conditions:
a. 3.0 V ≤ VDDD, VDDIO_1 or VDDIO_2
VDDA = VREFH ≤ 3.6 V
=
or
b. 4.5 V ≤ VDDD, VDDIO_1 or VDDIO_2
VDDA = VREFH ≤ 5.5 V
=
–40 °C ≤ TJ < 150 °C
SID201 TSENSACC2
Temperature sensor
accuracy 2
–5
–
–
5
°C
°C
This spec is valid when using ADC[0]
(VDDIO_1), ADC[1] (VDDIO_2) or ADC[2]
(VDDD) with the following conditions:
a. 3.0 V ≤ VDDD, VDDIO_1 or VDDIO_2
VDDA = VREFH ≤ 3.6 V
=
or
b. 4.5 V ≤ VDDD, VDDIO_1 or VDDIO_2
VDDA = VREFH ≤ 5.5 V
=
–40 °C ≤ TJ ≤ 150 °C
SID201A TSENSACC3
Temperature sensor
accuracy 3
–10
10
This spec is valid when using ADC[0]
(VDDIO_1) or ADC[2] (VDDD) with the
following condition:
2.7 V ≤ VDDD or VDDIO_1 ≤ 5.5 V and
2.7 V ≤ VDDA = VREFH ≤ 5.5 V and
0.8 × VDDA < VDDD or VDDIO_1
26.7.3
Voltage divider accuracy
Table 26-10 Voltage divider accuracy
Spec ID Parameter
Description
Min
–20
Typ
Max
20
Units Details/Conditions
Uncorrected monitor
voltage divider accuracy
(measured by ADC),
Any HV supply pad
SID202 VMONDIV
2
%
within 2.7 V–5.5 V
operating range
compared to ideal supply/2
26.8
AC specifications
Unless otherwise noted, the timings are defined with the guidelines mentioned in the Figure 26-7.
Definition of rise / fall times
VDDD or VDDIO_x
80 %
80 %
20 %
20 %
VSSD or VSSD_x or VSSIO_x
tR
tF
Time Reference Point Definition
VDDD or VDDIO_x
0.5 x VDDD or VDDIO_x
VSSD or VSSD_x or VSSIO_x
Timing Reference Points
Figure 26-7
AC timings specifications
Datasheet
128
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.9
Digital peripherals
Table 26-11 Timer/counter/PWM (TCPWM) specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID120 fC
TCPWM operating frequency
–
–
100
MHz fC = peripheral clock
Trigger Events can be
Stop, Start, Reload,
Input trigger pulse width for
all trigger events
Count, Capture, or Kill
SID121 tPWMENEXT
2 / fC
–
–
–
–
ns
depending on which
mode of operation is
selected.
Minimum possible
width of Overflow,
Underflow, and
SID122 tPWMEXT
Output trigger pulse widths
2 / fC
ns
Counter = Compare
(CC) value trigger
outputs
Minimumtimebetween
SID123 tCRES
Resolution of counter
PWM resolution
1 / fC
1 / fC
–
–
–
–
ns
successive counts
Minimum pulse width
SID124 tPWMRES
ns
of PWM output
Minimum pulse width
ns between Quadrature
phase inputs.
SID125 tQRES
Quadrature inputs resolution
2 / fC
–
–
TCPWM Timing Diagrams
VIH
VIL
Input Signal
1
1
2
VOH
VOL
Output Signal
2
1: tPWMENEXT, tQRES
2: tPWMEXT
Figure 26-8
TCPWM timing diagrams
Datasheet
129
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-12 Serial communication block (SCB) specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
–
–
100
MHz
SID129 fSCB
SCB operating frequency
I2C Interface-Standard-mode
SID130 fSCL
SCL clock frequency
Hold time, START condition
Low period of SCL
High period of SCL
Setup time for a repeated START 4700
Data hold time, for receiver
Data setup time
Fall time of SCL and SDA
Setup time for STOP
–
–
–
–
–
–
–
–
–
–
100
–
–
–
–
–
–
300
–
kHz
ns
ns
ns
ns
ns
ns
SID131 tHD;STA
SID132 tLOW
SID133 tHIGH
SID134 tSU;STA
SID135 tHD;DAT
SID136 tSU;DAT
SID138 tF
4000
4700
4000
0
250
–
ns Input and output
ns
SID139 tSU;STO
4000
Bus-free time between START
and STOP
Capacitive load for each bus line
Time for data signal from SCL
LOW to SDA output
SID140 tBUF
SID141 CB
4700
–
–
–
–
–
–
–
ns
pF
ns
ns
–
–
–
0
3
400
3450
3450
0.4
SID142 tVD;DAT
SID143 tVD;ACK
SID144 VOL
Data valid acknowledge time
LOW level output voltage
LOW level output current
Open drain at 3-mA
V
sink current
SID145 IOL
–
mA VOL = 0.4 V
I2C Interface-Fast-mode
SID150 fSCL_F
SCL clock frequency
–
–
–
–
–
–
–
–
400
–
–
–
–
kHz
ns
ns
ns
ns
ns
ns
SID151 tHD;STA_F
SID152 tLOW_F
SID153 tHIGH_F
SID154 tSU;STA_F
SID155 tHD;DAT_F
SID156 tSU;DAT_F
Hold time, START condition
Low period of SCL
High period of SCL
Setup time for a repeated START
Data hold time, for receiver
Data setup time
600
1300
600
600
0
–
–
100
20 ×
Input and output,
ns GPIO_ENH: slow
mode, 400 pF load
(VDDD
/
SID158 tF_F
Fall time of SCL and SDA
–
300
300
5.5)
Input and output
GPIO_STD:
drive_sel<1:0>= 0b00
ns MIN: 10 pF load,
RPU = 35.41 kΩ
SID158A tFA_F
Fall time of SCL and SDA
Setup time for STOP
Bus free time between START
and STOP
Capacitive load for each bus line
0.35
–
MAX: 400 pF load,
RPU = 350 Ω
SID159 tSU;STO_F
SID160 tBUF_F
SID161 CB_F
600
1300
–
–
–
–
–
–
ns Input and output
–
ns
pF
ns
400
900
Time for data signal from SCL
LOW to SDA output
SID162 tVD;DAT_F
–
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-12 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SID163 tVD;ACK_F
Data valid acknowledge time
–
–
900
ns
Pulse width of spikes that must
be suppressed by the input filter
SID164 tSP_F
–
–
50
ns
Open-drain at 3 mA
sink current
SID165 VOL_F
SID165 IOL_F
SID167 IOL2_F
LOW level output voltage
LOW level output current
LOW level output current
0
3
6
–
–
–
0.4
–
V
mA VOL = 0.4 V
–
mA VOL = 0.6 V[64]
I2C Interface-Fast-Plus mode
SID170 fSCL_FP
SCL clock frequency
Hold time, START condition
Low period of SCL
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
MHz
ns
ns
ns
ns
SID171 tHD;STA_FP
SID172 tLOW_FP
SID173 tHIGH_FP
SID174 tSU;STA_FP
SID175 tHD;DAT_FP
SID176 tSU;DAT_FP
260
500
260
260
0
High period of SCL
Setup time for a repeated START
Data hold time, for receiver
Data setup time
ns
ns
50
20 ×
Input and output
ns 20-pF load
(VDDD
/
SID178 tF_FP
Fall time of SCL and SDA
Setup time for STOP
Bus free time between START
and STOP
Capacitive load for each bus line
Time for data signal from SCL
LOW to SDA output
–
160
GPIO_ENH: slow mode
5.5)
260
SID179 tSU;STO_FP
SID180 tBUF_FP
SID181 CB_FP
–
–
–
–
–
–
–
–
ns Input and output
500
–
ns
pF
ns
ns
ns
20
450
450
50
SID182 tVD;DAT_FP
SID183 tVD;ACK_FP
SID184 tSP_FP
–
Data valid acknowledge time
Pulse width of spikes that must
be suppressed by the input filter
–
–
Open-drain at 3 mA
SID186 VOL_FP
SID187 IOL_FP
LOW level output voltage
LOW level output current
0
–
–
0.4
–
V
sink current
3[65]
mA VOL = 0.4 V[65]
SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1) [Conditions: drive_sel<1:0>= 0x]
Do not use half-clock
mode:
SID190 fSPI
SPI operating frequency
–
–
12.5
MHz
LATE_MISO_SAMPLE =
0
SPI Master: MOSI valid after
SCLK driving edge
SPI Master: MISO valid before
SCLK capturing edge
SPI Master: Previous MOSI data
hold time
SID191 tDMO
SID192 tDSI
SID193 tHMO
–
40
0
–
–
–
15
–
ns
ns
ns
–
Notes
64.In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL
.
65.In order to drive full bus load at 1 MHz, 20 mA IOL is required at 0.4 V VOL. However, this device does not support it.
Datasheet
131
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-12 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
0.4 ×
(1 /
SPI SCLK pulse width HIGH or
LOW
SID194 tW_SCLK_H_L
–
–
ns
fSPI
)
SPI Master: MISO hold time after
SCLK capturing edge
SSEL valid, before the first SCK
capturing edge
SID196 tDHI
0
–
–
–
ns
0.5 ×
SID198 tEN_SETUP
–
ns Min is half clock period
(1/fSPI
)
SSEL hold, after the last SCK
capturing edge
SPI capacitive load
0.5 ×
SID199 tEN_SHOLD
SID195 CSPIM_MS
–
–
–
ns Min is half clock period
pF
(1/fSPI
)
–
10
SPI Interface Slave (internally clocked) [Conditions: drive_sel<1:0>= 0x]
SID205 fSPI_INT
SPI operating frequency
SPI Slave: MOSI Valid before
Sclock capturing edge
–
–
10
–
MHz
ns
SID206 tDMI_INT
5
–
SPI Slave: MISO Valid after
Sclock driving edge, in the
internal-clocked mode
SID207 tDSO_INT
–
–
62
ns
SPI Slave: Previous MISO data
hold time
SPI Slave: SSEL valid to first SCK
valid edge
SPI Slave Select active (LOW)
from last SCLK hold
SID208 tHSP
3
–
–
–
–
–
–
ns
ns
ns
SID209 tEN_SETUP_INT
SID210 tEN_HOLD_INT
33
33
SPI Slave: from SSEL valid, to
SCK falling edge before the first
data bit
tEN_SET-
SID211
20
20
20
20
–
–
–
–
–
–
–
–
ns
ns
ns
ns
UP_PRE
SPI Slave: from SCK falling edge
SID212 tEN_HOLD_PRE before the first data bit, to SSEL
invalid
SPI Slave: from SSEL valid, to
SID213 tEN_SETUP_CO SCK falling edge in the first data
bit
SPI Slave: from SCK falling edge
SID214 tEN_HOLD_CO in the first data bit, to SSEL
invalid
SID215 tW_DIS_INT
SID216 tW_SCLKH_INT SPI SCLK pulse width HIGH
SID217 tW_SCLKL_INT SPI SCLK pulse width LOW
SID218 tSIH_INT
SID219 CSPIS_INT
SPI Slave Select inactive time
40
20
20
12
–
–
–
–
–
–
–
–
–
–
10
ns
ns
ns
ns
pF
SPI MOSI hold from SCLK
SPI Capacitive Load
SPI Interface Slave (externally clocked) [Conditions: drive_sel<1:0>= 0x]
SID220 fSPI_EXT
SPI operating frequency
SPI Slave: MOSI Valid before
Sclock capturing edge
–
–
12.5
–
MHz
ns
SID221 tDMI_EXT
5
–
SPI Slave: MISO Valid after
Sclock driving edge, in the
external-clocked mode
SID222 tDSO_EXT
–
–
32
ns
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-12 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SPI Slave: Previous MISO data
hold time
SPI Slave: SSEL valid to first SCK
valid edge
SPI Slave Select active (LOW)
from last SCLK hold
SID223 tHSO_EXT
3
–
–
–
–
ns
ns
ns
tEN_SET-
SID224
40
40
–
–
UP_EXT
SID225 tEN_HOLD_EXT
SID226 tW_DIS_EXT
SID227 tW_SCLKH_EXT SPI SCLK pulse width HIGH
SID228 tW_SCLKL_EXT SPI SCLK pulse width LOW
SID229 tSIH_EXT
SID230 CSPIS_EXT
SPI Slave Select inactive time
80
34
34
20
–
–
–
–
–
–
–
–
–
–
10
ns
ns
ns
ns
pF
SPI MOSI hold from SCLK
SPI Capacitive Load
SPI Slave: MISO valid after SSEL
falling edge (CPHA = 0)
SID231 tVSS_EXT
–
–
33
10
ns
UART interface
SID240 fBPS
Data rate
–
–
Mbps
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
8
9
7
70%
30%
70%
70%
70%
30%
6
SDA
SCL
30%
30%
12
8
9
4
70%
70%
70%
70%
30%
70%
30%
30%
30%
30%
30%
30%
2
1
3
START condition
11
70%
30%
70%
30%
70%
70%
SDA
SCL
30%
70%
2
14
10
13
70%
70%
30%
9th clock
5
Repeated START
condition
STOP condition
START condition
1: SCL clock period = 1/fSCL
2: Hold time, START condition = tHD;STA
3: LOW period of SCL = tLOW
4: HIGH period of SCL = tHIGH
5: Setup time for a repeated START = tSU;STA
6: Data hold time, for receiver = tHD;DAT
7: Data setup time = tSU;DAT
8: Fall time of SCL and SDA = tF
9: Rise time of SCL and SDA = tR
10: Setup time for STOP = tSU;STO
11: Bus-free time between START and STOP = tBUF
12: Time for data signal from SCL LOW to SDA output = tVD;DAT
13: Data valid acknowledge time = tVD;ACK
14: Pulse width of spikes that must be suppressed by the input filter = tSP
Figure 26-9
I2C timing diagrams
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=0
9
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tDHI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 26-10 SPI master timing diagrams with LOW clock phase
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tHDI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 26-11 SPI master timing diagrams with HIGH clock phase
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI Slave Timing Diagrams
CPHA=0
10
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
8
7
9
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data valid after SSEL falling edge (CPHA=0) = tVSS_EXT
9: output data hold time = tHSO
10: SSEL high pulse width = tDIS_EXT
Figure 26-12 SPI slave timing diagrams with LOW clock phase
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
SPI slave Timing Diagrams
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
SCLK
(CPOL=1)
7
8
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data hold time = tHSO
9: SSEL high pulse width = tDIS_EXT
Figure 26-13 SPI slave timing diagrams with HIGH clock phase
Table 26-13 CAN FD specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
fCCLK ≤ fHCLK,
,
SID630
SID631
fHCLK
fCCLK
System clock frequency
–
–
100
MHz
MHz
guaranteed by design
fCCLK ≤ fHCLK,
,
CAN clock frequency
–
–
100
guaranteed by design
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.10
Memory
Table 26-14 Flash DC specifications
Spec ID
SID260
Parameter
VPE
Description
Erase and program voltage 2.7
Min
Typ Max Units
5.5
Details/Conditions
Details/Conditions
–
V
Table 26-15 Flash AC specifications
Spec ID Parameter Description
Min Typ Max Units
Zero wait access to
code-flash memory up to
Maximum flash memory
operation frequency
SID257
fFO
–
–
100 MHz 100 MHz
Zero wait access with
cache hit up to 250 MHz
Maximum time from erase
suspend command till erase
is indeed suspend
SID254
SID255
SID258
tERS_SUS
–
250
–
–
–
–
37.5
–
µs
Minimum time allowed from
tERS_RES_SUS erase resume to erase
suspend
µs Guaranteed by design
At 100 MHz, N ≥ 4 and
µs multiple of 4, excludes
system overhead time
Blank check time for N-bytes
10+0.3
× N
tBC_WF
of work-flash
tSECTORE-
RASE1
tSECTORE-
RASE2
tSECTORE-
RASE3
tSECTORE-
RASE4
Sector erase time
(code-flash: 32 KB)
Sector erase time
(code-flash: 8 KB)
Sector erase time
(work-flash, 2 KB)
Sector erase time
(work-flash, 128 B)
Includes internal
SID259
SID259A
SID261
SID262
SID263
SID264
SID265
SID266
SID267
SID268
SID269
–
–
45
15
80
5
90
30
ms
preprogramming time
Includes internal
ms
preprogramming time
Includes internal
–
160
15
ms
preprogramming time
Includes internal
–
ms
preprogramming time
Excludes system overhead
tWRITE1
tWRITE2
tWRITE3
tWRITE4
tFRET1
64-bit write time (code-flash)
–
30
40
60
µs
time
256-bit write time
(code-flash)
Excludes system overhead
–
70
µs
time
4096-bit write time
Excludes system overhead
–
320 1200
µs
(code-flash)[66]
time
Excludes system overhead
32-bit write time (work-flash)
–
30
–
60
–
µs
time
Code-flash retention.
TA (power on and off) ≤ 85
20
20
10
years
1000 program/erase cycles
°C average
Work-flash retention.
TA (power on and off) ≤ 85
tFRET3
–
–
years
125,000 program/erase cycles
°C average
Work-flash retention.
TA (power on and off) ≤ 85
tFRET4
–
–
years
250,000 program/erase cycles
°C average
Note
66.The code-flash includes a 'Write Buffer' of 4096-bit. If the application software writes this buffer multiple times, to get the overall write
time multiply one sector write time with the corresponding factor (say for factor 64, example, 64 x 512 B = 32 KB [one sector]).
Datasheet
139
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-15 Flash AC specifications (continued)
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
TYP: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Program operating VCCD
SID612
SID613
ICC_ACT2
–
–
–
–
7
7
8
8
58
52
10
16
mA MAX: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
current (code or work-flash)
Guaranteed by design
TYP: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Erase operating VCCD current
(code- or work-flash)
ICC_ACT3
mA MAX: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
TYP: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Program operating VDDD
SID612A ICC_ACT2A
mA MAX: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
current (code or work-flash)
Guaranteed by design
TYP: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Erase operating VDDD current
(code- or work-flash)
SID613A ICC_ACT3A
mA MAX: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Datasheet
140
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.11
System resources
Table 26-16 System resources
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Power-on reset specifications
SID270
SID276
SID271
V
V
V
V
V
rising voltage to de assert POR
falling voltage to assert POR
1.5
1.45
20
–
–
–
2.35
2.1
V
V
Guaranteed by design
POR_D
POR_A
POR_H
DDD
DDD
Level detection hysteresis
300
mV
Delay between V
rising through
DDD
SID272
t
t
2.3 V and internal deassertion of
POR
–
–
3
µs
Guaranteed by design
DLY_POR
SID273
SID274
V
V
Power off time
100
–
–
–
–
µs
V
< 1.45 V
DDD
POFF
DDD
power ramp rate with robust
This ramp supports robust
BOD
DDD
POR_RR1
100
mV/µs
BOD (BOD operation is guaranteed)
This ramp does not support
V
power ramp rate without
DDD
SID275
POR_RR2
–
–
1000
mV/µs robust BOD
robust BOD
t
must be satisfied.
POFF
High-voltage BOD (HV BOD) Specifications
HV BOD 2.7 V rising detection point
for V and V (default)
SID500
SID501
SID502
SID503
SID505
SID506
V
V
V
V
2.474
2.449
2.765
2.74
–
2.55
2.525
2.85
2.825
–
2.627
2.601
2.936
2.91
100
V
TR_2P7_R
TR_2P7_F
TR_3P0_R
TR_3P0_F
DDD
DDA
HV BOD 2.7 V falling detection point
for V and V (default)
V
V
DDD
DDA
HV BOD 3.0 V rising detection point
for V and V
DDD
DDA
HV BOD 3.0 V falling detection point
for V and V
V
DDD
DDA
Power ramp rate: V
(Active)
and V
DDD
DDA
HVBOD_RR_A
mV/µs
mV/µs
Power ramp rate: V
(DeepSleep)
and V
DDD
DDA
HVBOD_RR_DS
–
–
10
Active mode delay between V
DDD
falling/rising through V
or
TR_2P7_F/R
SID507
t
t
t
–
–
–
–
–
–
0.5
1
µs
µs
µs
Guaranteed by design
Guaranteed by design
Guaranteed by design
DLY_ACT_HVBOD
DLY_ACT_HVBOD
DLY_DS_HVBOD
V
and an internal HV BOD
TR_3P0_F/R
signal transitioning
Active mode delay between V
DDA
falling/rising through V
or
TR_2P7_F/R
SID507A
SID507B
V
and internal HV BOD
TR_3P0_F/R
signal transitioning
DeepSleep mode delay between
V
V
/V
falling/rising through
DDD DDA
4
or V
and an
TR_2P7_F/R
TR_3P0_F/R
internal HV BOD signal transitioning
Response time of HV BOD,
V
/V
supply. (For
DDD DDA
SID508
t
falling-then-rising supply at max
ramp rate; threshold is V
100
–
–
ns
Guaranteed by design
RES_HVBOD
or
TR_2P7_F
V
)
TR_3P0_F
Low-voltage BOD (LV BOD) Specifications
LV BOD rising detection point for
CCD
SID510
SID511
V
V
0.917
0.892
0.945
0.920
0.973
0.948
V
V
TR_R_LVBOD
TR_F_LVBOD
V
LV BOD falling detection point for
V
CCD
Active delay between V
falling/rising through V
CCD
TR_R/F_LVBOD
SID515
t
–
–
1
µs
Guaranteed by design
DLY_ACT_LVBOD
and an internal LV BOD signal transi-
tioning
DeepSleep mode delay between
V
V
falling/rising through
CCD
SID515A
SID516
t
t
–
–
–
12
–
µs
ns
Guaranteed by design
Guaranteed by design
DLY_DS_LVBOD
RES_LVBOD
and an internal LV
TR_R/F_LVBOD
BOD signal transitioning
Response time of LV BOD (for
falling-then-rising supply at max
100
ramp rate; threshold is V
)
TR_F_LVBOD
Datasheet
141
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-16 System resources (continued)
Spec ID
Low-voltage detector (LVD) DC specifications
LVD 2.8 V falling detection point for
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID520
SID521
SID522
SID523
SID524
SID525
SID526
SID527
SID528
SID529
SID530
SID531
SID532
SID533
SID534
SID535
SID536
SID537
SID538
SID539
SID540
SID541
SID542
SID543
SID544
SID545
SID546
SID547
SID548
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Typ – 4% 2800 Typ + 4%
Typ – 4% 2900 Typ + 4%
Typ – 4% 3000 Typ + 4%
Typ – 4% 3100 Typ + 4%
Typ – 4% 3200 Typ + 4%
Typ – 4% 3300 Typ + 4%
Typ – 4% 3400 Typ + 4%
Typ – 4% 3500 Typ + 4%
Typ – 4% 3600 Typ + 4%
Typ – 4% 3700 Typ + 4%
Typ – 4% 3800 Typ + 4%
Typ – 4% 3900 Typ + 4%
Typ – 4% 4000 Typ + 4%
Typ – 4% 4100 Typ + 4%
Typ – 4% 4200 Typ + 4%
Typ – 4% 4300 Typ + 4%
Typ – 4% 4400 Typ + 4%
Typ – 4% 4500 Typ + 4%
Typ – 4% 4600 Typ + 4%
Typ – 4% 4700 Typ + 4%
Typ – 4% 4800 Typ + 4%
Typ – 4% 4900 Typ + 4%
Typ – 4% 5000 Typ + 4%
Typ – 4% 5100 Typ + 4%
Typ – 4% 5200 Typ + 4%
Typ – 4% 5300 Typ + 4%
Typ – 4% 2825 Typ + 4%
Typ – 4% 2925 Typ + 4%
Typ – 4% 3025 Typ + 4%
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
TR_2P8_F
TR_2P9_F
TR_3P0_F
TR_3P1_F
TR_3P2_F
TR_3P3_F
TR_3P4_F
TR_3P5_F
TR_3P6_F
TR_3P7_F
TR_3P8_F
TR_3P9_F
TR_4P0_F
TR_4P1_F
TR_4P2_F
TR_4P3_F
TR_4P4_F
TR_4P5_F
TR_4P6_F
TR_4P7_F
TR_4P8_F
TR_4P9_F
TR_5P0_F
TR_5P1_F
TR_5P2_F
TR_5P3_F
TR_2P8_R
TR_2P9_R
TR_3P0_R
V
DDD
LVD 2.9 V falling detection point for
DDD
V
LVD 3.0 V falling detection point for
DDD
V
LVD 3.1 V falling detection point for
DDD
V
LVD 3.2 V falling detection point for
DDD
V
LVD 3.3 V falling detection point for
DDD
V
LVD 3.4 V falling detection point for
DDD
V
LVD 3.5 V falling detection point for
DDD
V
LVD 3.6 V falling detection point for
DDD
V
LVD 3.7 V falling detection point for
DDD
V
LVD 3.8 V falling detection point for
DDD
V
LVD 3.9 V falling detection point for
DDD
V
LVD 4.0 V falling detection point for
DDD
V
LVD 4.1 V falling detection point for
DDD
V
LVD 4.2 V falling detection point for
DDD
V
LVD 4.3 V falling detection point for
DDD
V
LVD 4.4 V falling detection point for
DDD
V
LVD 4.5 V falling detection point for
DDD
V
LVD 4.6 V falling detection point for
DDD
V
LVD 4.7 V falling detection point for
DDD
V
LVD 4.8 V falling detection point for
DDD
V
LVD 4.9 V falling detection point for
DDD
V
LVD 5.0 V falling detection point for
DDD
V
LVD 5.1 V falling detection point for
DDD
V
LVD 5.2 V falling detection point for
DDD
V
LVD 5.3 V falling detection point for
DDD
V
LVD 2.8 V rising detection point for
DDD
mV Same as V
mV Same as V
mV Same as V
+ 25 mV
+ 25 mV
+ 25 mV
TR_2P8_F
TR_2P9_F
TR_3P0_F
V
LVD 2.9 V rising detection point for
DDD
V
LVD 3.0 V rising detection point for
DDD
V
Datasheet
142
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-16 System resources (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
LVD 3.1 V rising detection point for
DDD
SID549
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Typ – 4% 3125 Typ + 4%
Typ – 4% 3225 Typ + 4%
Typ – 4% 3325 Typ + 4%
Typ – 4% 3425 Typ + 4%
Typ – 4% 3525 Typ + 4%
Typ – 4% 3625 Typ + 4%
Typ – 4% 3725 Typ + 4%
Typ – 4% 3825 Typ + 4%
Typ – 4% 3925 Typ + 4%
Typ – 4% 4025 Typ + 4%
Typ – 4% 4125 Typ + 4%
Typ – 4% 4225 Typ + 4%
Typ – 4% 4325 Typ + 4%
Typ – 4% 4425 Typ + 4%
Typ – 4% 4525 Typ + 4%
Typ – 4% 4625 Typ + 4%
Typ – 4% 4725 Typ + 4%
Typ – 4% 4825 Typ + 4%
Typ – 4% 4925 Typ + 4%
Typ – 4% 5025 Typ + 4%
Typ – 4% 5125 Typ + 4%
Typ – 4% 5225 Typ + 4%
Typ – 4% 5325 Typ + 4%
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
mV Same as V
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
+ 25 mV
TR_3P1_R
TR_3P1_F
TR_3P2_F
TR_3P3_F
TR_3P4_F
TR_3P5_F
TR_3P6_F
TR_3P7_F
TR_3P8_F
TR_3P9_F
TR_4P0_F
TR_4P1_F
TR_4P2_F
TR_4P3_F
TR_4P4_F
TR_4P5_F
TR_4P6_F
TR_4P7_F
TR_4P8_F
TR_4P9_F
TR_5P0_F
TR_5P1_F
TR_5P2_F
TR_5P3_F
V
LVD 3.2 V rising detection point for
SID550
SID551
SID552
SID553
SID554
SID555
SID556
SID557
SID558
SID559
SID560
SID561
SID562
SID563
SID564
SID565
SID566
SID567
SID568
SID569
SID570
SID571
TR_3P2_R
TR_3P3_R
TR_3P4_R
TR_3P5_R
TR_3P6_R
TR_3P7_R
TR_3P8_R
TR_3P9_R
TR_4P0_R
TR_4P1_R
TR_4P2_R
TR_4P3_R
TR_4P4_R
TR_4P5_R
TR_4P6_R
TR_4P7_R
TR_4P8_R
TR_4P9_R
TR_5P0_R
TR_5P1_R
TR_5P2_R
TR_5P3_R
V
DDD
LVD 3.3 V rising detection point for
V
DDD
LVD 3.4 V rising detection point for
V
DDD
LVD 3.5 V rising detection point for
V
DDD
LVD 3.6 V rising detection point for
V
DDD
LVD 3.7 V rising detection point for
V
DDD
LVD 3.8 V rising detection point for
V
DDD
LVD 3.9 V rising detection point for
V
DDD
LVD 4.0 V rising detection point for
V
DDD
LVD 4.1 V rising detection point for
V
DDD
LVD 4.2 V rising detection point for
V
DDD
LVD 4.3 V rising detection point for
V
DDD
LVD 4.4 V rising detection point for
V
DDD
LVD 4.5 V rising detection point for
V
DDD
LVD 4.6 V rising detection point for
V
DDD
LVD 4.7 V rising detection point for
V
DDD
LVD 4.8 V rising detection point for
V
DDD
LVD 4.9 V rising detection point for
V
DDD
LVD 5.0 V rising detection point for
V
DDD
LVD 5.1 V rising detection point for
V
DDD
LVD 5.2 V rising detection point for
V
DDD
LVD 5.3 V rising detection point for
V
DDD
SID573
SID574
LVD_RR_A
Power ramp rate: V
Power ramp rate: V
(Active)
–
–
–
–
100
10
mV/µs
mV/µs
DDD
LVD_RR_DS
(DeepSleep)
DDD
Active mode delay between V
falling/rising through LVD
DDD
SID575
SID575A
SID576
t
t
t
–
–
–
–
–
1
4
–
µs
µs
ns
Guaranteed by design
Guaranteed by design
Guaranteed by design
DLY_ACT_LVD
DLY_DS_LVD
RES_LVD
rising/falling point and an internal
LVD signal transitioning
DeepSleep mode delay between
V
falling/rising through LVD
DDD
rising/falling point and an internal
LVD signal transitioning
Response time of LVD, V
supply.
DDD
(For falling-then-rising supply at
max ramp rate; threshold is LVD
falling point)
100
Datasheet
143
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-16 System resources (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
High-voltage OVD specifications
HV OVD 5.0-V rising detection point
SID580
SID581
SID582
SID583
SID585
SID586
V
V
V
V
5.049
5.025
5.548
5.524
–
5.205
5.18
5.72
5.695
–
5.361
5.335
5.892
5.866
100
V
TR_5P0_R
TR_5P0_F
TR_5P5_R
TR_5P5_F
for V
and V
DDA
DDD
HV OVD 5.0-V falling detection point
for V and V
V
V
DDD
DDA
HV OVD 5.5-V rising detection point
for V and V (default)
DDD
DDA
HV OVD 5.5-V falling detection point
for V and V (default)
V
DDD
DDA
Power ramp rate: V
(Active)
and V
DDD
DDA
HVOVD_RR_A
mV/µs
mV/µs
Power ramp rate: V
(DeepSleep)
and V
DDD
DDA
HVOVD_RR_DS
–
–
10
Active mode delay between V
DDD
falling/rising through V
or
TR_5P0_F/R
SID587
t
t
–
–
–
–
1
µs
µs
Guaranteed by design
Guaranteed by design
DLY_ACT_HVOVD
V
and an internal HV OVD
TR_5P5_F/R
signal transitioning
Active mode delay between V
DDA
falling/rising through V
or
TR_5P0_F/R
SID587A
1.5
DLY_ACT_HVOVD_A
V
and an internal HV OVD
TR_5P5_F/R
signal transitioning
DeepSleep mode delay between
V
V
/V
falling/rising through
DDD DDA
SID587B
SID588
t
t
–
–
–
4
–
µs
ns
Guaranteed by design
Guaranteed by design
DLY_DS_HVOVD
RES_HVOVD
or V
and an
TR_5P0_F/R
internal HV OVD signal transitioning
TR_5P5_F/R
Response time of HV OVD (for
rising-then-falling supply at max
100
ramp rate; threshold is V
or
TR_5P0_R
V
)
TR_5P5_R
Low-voltage OVD specifications
LV OVD rising detection point for
CCD
SID590
SID591
V
V
1.261
1.237
1.3
1.339
1.313
V
V
TR_R_LVOVD
TR_F_LVOVD
V
LV OVD falling detection point for
1.275
V
CCD
Active mode delay between V
CCD
TR_F/R_LVOVD
falling/rising through V
SID595
t
–
–
1
µs
Guaranteed by design
DLY_ACT_LVOVD
and an internal LV OVD signal transi-
tioning
DeepSleep mode delay between
V
V
falling/rising through
CCD
SID595A
SID596
t
t
–
–
–
12
–
µs
ns
Guaranteed by design
Guaranteed by design
DLY_DS_LVOVD
RES_LVOVD
and an internal LV
TR_F/R_LVOVD
OVD signal transitioning
Response time of LV OVD. (For
rising-then-falling supply at max
ramp rate; threshold is V
100
)
TR_R_LVOVD
Over current detection (OCD) specifications
Over current detection range for
internal Active regulator
SID598A
SID598B
SID599
I
I
I
312
675
18
–
–
–
630
825
72
mA Guaranteed by design
OCD_LDO
Over current detection range for
external transistor mode
mA
mA
OCD_EXT
Over current detection range for
internal DeepSleep regulator
OCD_DPSLP
Datasheet
144
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VDDD
CPU and
CPU and
Peripherals
Regulators
I/O
Peripherals
Regulators
I/O
6.0 V
Reset
By OVD
High-Z
OVD rising trip
(Default: 5.548 V to
5.892 V)
Normal
Operation
Normal
Operation
Enable
Reset
By
XRES_L
Disable
High-Z
BOD rising trip
(Default: 2.474 V to
2.627 V)
Reset
By BOD
POR rising trip
(1.5 V to 2.35 V)
Reset
High-Z
By POR
CMOS threshold
(0.7 V)
Disable
OFF
OFF
-0.3 V
VDDD
XRES_L
HIGH Level
LOW Level
Figure 26-14 Device operations supply range
Datasheet
145
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
2.3 V
VDDD
tDLY_POR
Internal reset by POR
VDDD
tPOFF
1.45 V
Figure 26-15 POR specifications
Datasheet
146
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VDDD, VDDA
VTR_2P7_R or VTR_3P0_R
VTR_2P7_F or VTR_3P0_F
Internal HV BOD signal
tDLY_ACT/DS_HVBOD
tDLY_ACT/DS_HVBOD
VDDD, VDDA
tRES_HVBOD
VTR_2P7_F or VTR_3P0_F
Figure 26-16 High-voltage BOD specifications
Datasheet
147
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VCCD
VTR_R_LVBOD
VTR_F_LVBOD
Internal LV BOD signal
tDLY_ACT/DS_LVBOD
tDLY_ACT/DS_LVBOD
VCCD
tRES_LVBOD
VTR_F_LVBOD
Figure 26-17 Low-voltage BOD specifications
Datasheet
148
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VTR_5P0_R or VTR_5P5_R
VTR_5P0_F or VTR_5P5_F
VDDD/VDDA
Internal HV OVD signal
tDLY_ACT/DS_HVOVD
tDLY_ACT/DS_HVOVD
VTR_5P0_R or VTR_5P5_R
tRES_HVOVD
VDDD/VDDA
Figure 26-18 High-voltage OVD specifications
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VTR_R_LVOVD
VTR_F_LVOVD
VCCD
Internal LV OVD signal
tDLY_ACT/DS_LVOVD
tDLY_ACT/DS_LVOVD
VTR_R_LVOVD
tRES_LVOVD
VCCD
Figure 26-19 Low-voltage OVD specifications
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
VDDD
LVD rising detection point
LVD falling detection point
Internal LVD signal
tDLY_ACT/DS_LVD
tDLY_ACT/DS_LVD
VDDD
tRES_LVD
LVD falling detection point
Figure 26-20 LVD specifications
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.11.1
SWD interface
Table 26-17 SWD interface specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID300
Parameter
fSWDCLK
Description
SWD clock input frequency
Min
–
Typ
–
Max Units Details/Conditions
10
MHz 2.7 V ≤ VDDD ≤ 5.5 V
0.25 ×
T
0.25 ×
T
SID301
SID302
tSWDI_SETUP
SWDI setup time
SWDI hold time
–
–
–
ns T = 1 / fSWDCLK
tSWDI_HOLD
tSWDO_VALID
tSWDO_HOLD
–
ns T = 1 / fSWDCLK
SID303
SID304
SWDO valid time
SWDO hold time
–
1
–
–
0.5 × T
–
ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
Table 26-18 JTAG AC Specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID620
SID621
SID622
SID623
SID624
SID625
SID626
SID627
Parameter
tJCKH
tJCKL
tJCP
tJSU
tJH
tJZX
tJXZ
tJCO
Description
TCK HIGH time
TCK LOW time
Min
30
30
66.7
12
12
–
Typ
–
–
–
–
–
–
–
–
Max Units Details/Conditions
–
–
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
TCK clock period
–
–
–
TDI/TMS setup time
TDI/TMS hold time
TDO High-Z to active
TDO active to High-Z
TDO clock to output
30
30
30
–
–
tJCKH
tJCKL
tJCP
TCK
tJH
tJSU
TDI/TMS
tJCO
tJXZ
tJZX
TDO
Figure 26-21 JTAG specifications
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-19 Trace specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
SID1412A CTRACE
Trace capacitive load
–
–
30
pF
Trace clock cycle time
for 25 MHz
SID1412 tTRACE_CYC
Trace clock period
40
–
–
ns
SID1413 tTRACE_CLKL
SID1414 tTRACE_CLKH
SID1415A tTRACE_SETUP
SID1416A tTRACE_HOLD
Trace clock LOW pulse width
Trace clock HIGH pulse width
Trace data setup time
2
2
3
2
–
–
–
–
–
–
–
–
ns Clock low pulse width
ns Clock high pulse width
ns Trace data setup time
ns Trace data hold time
Trace data hold time
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.12
Clock specifications
Table 26-20 Root and intermediate clocks[67]
Maxfrequency
Clock
Source
Description
(MHz)
160
CLK_HF0
CLK_HF1
CLK_HF2
PLL200#0 Root clock for CPUSS, PERI
250
100
PLL400#0 CM7 CPU Core#0, CM7 CPU Core#1 clock
PLL200#1 Peripheral clock root other than CLK_PERI
Event generator (CLK_REF), clock output on EXT_CLK pins (when
CLK_HF3
CLK_HF4
CLK_HF5
100
50
PLL200#1
used as output)
PLL200#1 Ethernet Channel#0, Ethernet Channel#1 internal clock
I2S channel#0, I2S channel#1, I2S channel#2 interface clock,
196.608
PLL400#1
Ethernet Channel#0 TSU
CLK_HF6
CLK_HF7
200
8
PLL200#1 Root clock for SDHC, SMIF interface clock
ILO
CSV
CLK_FAST_
0
CLK_FAST_
1
250
250
160
100
100
NA
CM7 CPU Core#0, intermediate clock
NA
NA
NA
NA
CM7 CPU Core#1, intermediate clock
Generated by clock gating CLK_HF0, intermediate clock for SMIF,
Flash, Ethernet
Generated by clock gating CLK_MEM, intermediate clock for CM0+,
P-DMA, M-DMA, Crypto, SMIF, SDHC
Generated by clock gating CLK_HF0, intermediate clock for IOSS,
TCPWM0, CPU trace, SMIF
CLK_MEM
CLK_SLOW
CLK_PERI
Table 26-21 Relation between CLK_HF0 and CLK_SLOW (Example)[68]
CLK_HF0 (MHz)
CLK_SLOW (MHz)
160
120
100
80
80
60
100
80
Table 26-22 IMO AC specifications
Spec ID
SID310
Parameter
fIMOTOL
Description
IMO operating frequency 7.68
Min
Typ
8
Max Units Details/Conditions
8.32
7.5
22
MHz
Start-up time to 90% of
final frequency
SID311
SID312
tSTARTIMO
IIMO_ACT
IMO start-up time
IMO current
–
–
–
µs
13.5
µA
Notes
67.Intermediate clocks that are not listed have the same limitations as that of their parent clock.
68.CLOCK_SLOW and CLK_HF0 are related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on).
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-23 ILO AC specifications
Spec ID
Parameter
fILOTRIM
Description
Min
30.4742
4
Typ
Max
35.0617
6
Units Details/Conditions
ILO operating
SID320
32.768
kHz
frequency
Start-up time to 90% of
SID321
SID323
tSTARTILO
IILO
ILO start-up time
ILO current
–
–
8
12
µs
final frequency
500
2800
nA
Table 26-24 ECO specifications
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
SID330
SID332
fECO
RFDBK
Crystal frequency range
8
100
–
–
33.34 MHz
Feedback resistor value.
Min: RTRIM = 3; Max: RTRIM =
0 with 100-kΩ step size on
RTRIM
400
2000
10
kΩ Guaranteed by design
Maximum operation
µA current with a 33-MHz
crystal, 18-pF load
SID333
SID334
IECO3
ECO current at TJ = 150 °C
–
–
–
–
Time from set
CLK_ECO_-CONFIG.ECO
_EN to 1 until
tSTART_8M
8-MHz ECO start-up time[69]
ms CLK_ECO_STATUS.ECO
_READY is set to 1 (See
Clock timing
diagrams)
Time from set
CLK_ECO_-CONFIG.ECO
_EN to 1 until
SID335
tSTART_33M
33-MHz ECO start-up time[69]
–
–
1
ms CLK_ECO_STATUS.ECO
_READY is set to 1 (See
Clock timing
diagrams)
VDDD
MCU
ITrim
Rf
RTrim
ECO_IN: External crystal oscillator input pin
ECO_OUT: External crystal oscillator output pin
C1, C2: Load Capacitors
ECO_IN
C3*, C4*: Stray Capacitance of the PCB
C1
C2
C3*
C4*
GTrim
VSSD
VSSD
ECO_OUT
Rd
0R
Rd
FTrim
Figure 26-22 ECO connection scheme[70]
Notes
69.Mainly depends on the external crystal.
70.Refer to the family-specific Architecture TRM for more information on crystal requirements (32-bit Arm® Cortex® -M7 Industrial Micro
controller XMC7000 family Architecture Technical Reference Manual).
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-25 PLL specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
PLL (without SSCG and fractional divider) specifications for 200 MHz
Time from stable
reference clock until PLL
µs frequency is within 0.1%
of final value and lock
indicator is set
SID340
SID341
tPLL200_LOCK
Time to achieve PLL lock
–
–
–
35
Output frequency from
PLL block
fPLL_OUT
11
200 MHz
For 125 ns
Guaranteed by design
fPLL_VCO: 320 MHz or
SID342
SID343
SID344
PLL_LJIT1
PLL_LJIT2
PLL_LJIT3
Long term jitter
Long term jitter
Long term jitter
–0.25
–0.5
–
–
–
–
0.25
0.5
ns 400 MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 500 ns
Guaranteed by design
fPLL_VCO: 320 MHz or
ns 400 MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 1000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or
–0.5
0.5
ns 400 MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 10000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or
SID345A1 PLL_LJIT5
Long term jitter
–0.75
0.75
ns 400 MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
SID346
SID347
fPLL_IN
PLL input frequency
PLL operating current
(fOUT = 200 MHz)
3.988
–
–
33.34 MHz
IPLL_200M
0.87
1.8
mA fOUT = 200 MHz
SID348C
SID349C
fPLL_VCO
fPLL_PFD
VCO frequency
PFD frequency
170
3.988
–
–
400 MHz
8
MHz
PLL (with SSCG and fractional divider) specifications for 400 MHz
Time from stable
reference clock until PLL
SID340A
tPLL400_LOCK
Time to achieve PLL lock
–
–
–
50
µs frequency is within 0.1%
of final value and lock
indicator is set
Programmed output
frequency from PLL
Block (spreading off)
SID341A4 fOUT0_4M
25
250 MHz Spreading off
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-25 PLL specifications (continued)
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
Programmed output
frequency from PLL
Block (spreading on)
SID341B4 fOUT1_4M
25
–
240 MHz Spreading on
Spread spectrum
modulation depth
Spread spectrum
modulation rate
Downspread only,
SID343A
SID343B
SPREAD_D
fSPREAD_MR
0.5
–
–
–
3
%
triangle modulation
Selected by modulation
divider from fPFD
32
kHz
For 125 ns
Guaranteed by design
fVCO: 800 MHz or 500 MHz
SID342D14 PLL400_LJIT14 Long term jitter
SID343D14 PLL400_LJIT24 Long term jitter
SID344D14 PLL400_LJIT34 Long term jitter
SID345E14 PLL400_LJIT54 Long term jitter
–0.25
–0.5
–1
–
–
–
–
0.25
0.5
1
ns (spreading is off)
fIN: ECO
fPFD: 4 MHz
f
OUT: 100 MHz to 250 MHz
For 500 ns
Guaranteed by design
f
VCO: 800 MHz or 500 MHz
ns (spreading is off)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 250 MHz
For 1000 ns
Guaranteed by design
fVCO: 800 MHz or 500 MHz
ns (spreading is off)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 250 MHz
For 10000 ns
Guaranteed by design
fVCO: 800 MHz or 500 MHz
ns (spreading is off)
fIN: ECO
–1.5
1.5
fPFD: 4 MHz
fOUT: 100 MHz to 250 MHz
SID345A
SID346A
fVCO
fIN
VCO frequency
PLL input frequency
400
3.988
–
–
800 MHz
33.34 MHz
PLL operating current
(fOUT = 400 MHz)
PFD Frequency (fIN /
Reference divider)
PFD Frequency (fIN /
Reference divider)
SID347A
SID348A
SID349A
IPLL_400M
fPFD_S
–
3.988
8
1.4
–
2.2
20
20
mA fOUT = 400 MHz
MHz Spreading off/on
fPFD_F
–
MHz Fractional operation
fPFD = 8 MHz,
fVCO = 400 MHz,
fOUT = 100 MHz,
Output frequency from
PLL Block (spreading on)
SID341C
fOUT_400_8S1
93
–
105 MHz
Modulation frequency:
fPFD / 512,
Modulation depth: 3%
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-25 PLL specifications (continued)
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
fPFD = 8 MHz,
fVCO = 400 MHz,
fOUT = 100 MHz,
Modulation frequency:
fPFD / 512,
Cycle-to-cycle jitter
(spreading on)
SID342C
tPLL_CJIT400_8S1
–710
93
–
–
–
710
ps
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
fOUT = 100 MHz,
Modulation frequency:
fPFD / 256,
Output frequency from
PLL Block (spreading on)
SID341D
SID342D
fOUT_400_8S2
105 MHz
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
Cycle-to-cycle jitter
(spreading on)
fOUT = 100 MHz,
tPLL_CJIT400_8S2
–710
710
ps
Modulation frequency:
fPFD / 256,
Modulation depth: 3%
Table 26-26 FLL specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
Wakeup with < 10 °C
temperature change
while in DeepSleep.
fFLL_IN = 8 MHz,
SID350
tFLL_WAKE
FLL wake up time
–
–
5
µs
fFLL_OUT = 100 MHz, Time
from stable reference
clock until FLL frequency
is within 5% of final value
Output frequency from
FLL block
Output range of FLL
divided-by-2 output
SID351
fFLL_OUT
24
–
100 MHz
This is added to the error
of the source
SID352
SID353
FLL_CJIT
fFLL_IN
FLL frequency accuracy
Input frequency
–1
–
–
1
%
0.25
80
MHz
Reference clock: IMO,
CCO frequency: 200 MHz,
FLL frequency: 100 MHz,
guaranteed by design
SID354
IFLL
FLL operating current
–
250
360
µA
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-27 WCO specifications
Spec ID
SID360
SID361
Parameter
fWCO
WCO_DC
Description
Min
Typ
Max Units Details/Conditions
Maximum drive level:
Crystal frequency
–
32.768
–
kHz
0.5 µW
WCO duty cycle
WCO start-up time[71]
10
–
–
–
90
%
SID362E tSTART_WCOE
1400
ms Time from set
CTL.WCO_EN to 1 until
STATUS.WCO_OK is
set to 1. (See Clock
timing diagrams)
SID363
IWCO
WCO current
–
1.4
–
µA
VDDD
MCU
Rf
WCO_IN: Watch crystal oscillator input pin
WCO_OUT: Watch crystal oscillator output pin
C1, C2: Load Capacitors
WCO_IN
VSSD
C3*, C4*: Stray Capacitance of the PCB
C1
C2
C3*
C4*
VSSD
WCO_OUT
Rd
0R
Figure 26-23 WCO connection scheme[72]
Table 26-28 External clock input specifications
Spec ID
SID366
SID367
Parameter
fEXT
EXT_DC
Description
Min
Typ
–
Max Units Details/Conditions
For EXT_CLK pin (all
input level settings:
External clock input
frequency
0.25
45
80
55
MHz
%
CMOS, TTL, Indus-
trial)
External clock duty cycle
–
Table 26-29 MCWDT timeout specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID410
tMCWDT1
Minimum MCWDT timeout
Maximum MCWDT timeout
57
–
–
µs
s
16-bit MCWDT counter
Guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
16-bit MCWDT counter
Guaranteed by design
SID411
tMCWDT2
–
–
2.15
Notes
71.Mainly depends on the external crystal.
72.Refer to the family-specific Architecture TRM for more information on crystal requirements (32-bit Arm® Cortex® -M7 Industrial Microcon-
troller XMC7000 family Architecture Technical Reference Manual).
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-30 WDT timeout specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID412
SID413
tWDT1
Minimum WDT timeout
57
–
–
µs
h
16-bit WDT counter,
guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
16-bit WDT counter,
guaranteed by design
tWDT2
Maximum WDT timeout
Default WDT timeout
–
–
–
39.15
When using the ILO
and 32-bit WDT
SID414
tWDT3
1000
–
ms counter at 0x8000
(default value),
guaranteed by design
26.13
Clock timing diagrams
ECO: 8 MHz
PLL: 160 MHz
FLL: 100 MHz
Active
CLK_ECO_CONFIG.ECO_EN
ECO_OUT
8 MHz
CLK_ECO_STATUS.ECO_READY
10 ms
CLK_PLL_CONFIG.ENABLE
CLK_PLL_STATUS.LOCKED
160 MHz
35 µs
PLL_OUTPUT
CLK_FLL_CONFIG.FLL_ENABLE
CCO is already up-and-running
CLK_FLL_STATUS.LOCKED
5 µs
100 MHz
FLL_OUTPUT
Figure 26-24 ECO to PLL or FLL diagram
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
WCO: 32.768 kHz
FLL: 100 MHz
Active
CTL.WCO_EN
WCO_OUT
32.768 kHz
STATUS.WCO_OK
1000 ms
CLK_FLL_CONFIG.FLL_ENABLE
CLK_FLL_STATUS.LOCKED
CCO is already up-and-running
5 µs
100 MHz
FLL_OUTPUT
Figure 26-25 WCO to FLL diagram
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.14
Ethernet specifications
Table 26-31 Ethernet specifications [Conditions: drive_sel<1:0>= 00]
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
Ethernet general specifications
SID368
SID369
SID399
fSYS
fAXI
VETH
System clock max frequency
AXI clock max frequency
Ethernet MAC I/O supply voltage 3.0
–
–
–
–
–
100
200
3.6
MHz Guaranteed by design
MHz Guaranteed by design
V
For VDDD
For MDIO all signals
SID364A CL_MD
SID364A2 CL_MG
SID365A tRF
Load capacitance
Load capacitance
Rise / fall time
–
–
–
–
–
–
25
15
2
pF betweenMACandPHY
using GPIO_STD
For MII and RMII all
signals between MAC
pF
and PHY using
GPIO_STD
20% to 80%, for MII,
ns RMII, and MDIO using
GPIO_STD
Ethernet MII specifications for GPIO_STD
MII TX/RX_CLK Clock frequency -100
100
SID375
SDI376
fTXRX_CLK
25
–
MHz
%
at 100 Mbps
ppm
35
ppm
DUTY_REF
Duty cycle of reference clock
65
25
MII Transmit data
(TXD,TX_CTL,TX_ER) valid after
TX_CLK
SID372
tSKEWT
0.5
–
ns
MII Receive data setup to
RX_CLK rising edge
MII Receive data hold to RX_CLK
rising edge
SID373
SID374
tSUR
10
10
–
–
–
–
ns
ns
tHOLDR
Ethernet RMII specifications for GPIO_STD
-50
50
SID375A fREF_CLK
RMII reference Clock frequency
50
–
MHz External clock
ppm
ppm
SID376A DUTY_REF
Duty cycle of reference clock
35
65
%
RXD[1:0], RX_CTL, RX_ER Data
Setup to REF_CLK rising edge
RXD[1:0], RX_CTL, RX_ER, Data
hold from REF_CLK rising edge
SID377
SID378
SID393
tSU
4
–
–
ns
tHOLD
tTXOUT
2
2
–
–
–
ns
ns
TX_EN,TXD[1:0], Data output
14
delay from REF_CLK rising edge
Ethernet MDIO Specifications for GPIO_STD
SID395
tMDCYC
MDC clock cycle
The minimum HIGH and LOW
times for MDC
400
160
–
–
–
–
ns
ns
SID395A tHL_MDCYC
MDIO input setup time to MDC
rising edge
MDIO input hold time to MDC
rising edge
MDIO output skew from MDC
rising edge
SID396
SID397
SID398
tMDIS
tMDIH
tMDIO
100
0
–
–
–
–
–
ns
ns
ns
10
390
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
1
2.0 V
RX_CLK
0.8 V
2
3
RXD, RX_CTL,
RX_ER
2.0 V
0.8 V
2.0 V
0.8 V
TX_CLK
4
2.0 V
0.8 V
TXD, TX_CTL,
TX_ER
1: RX_CLK or TX_CLK cycle = 1/fTXRX_CLK
2: MII receive data setup time to RX_CLK rising edge = tSUR
3: MII receive data hold time to RX_CLK rising edge = tHOLDR
4: MII transmit data valid after TX_CLK rising edge = tSKEWT
Figure 26-26 MII timing diagram
1
2.0 V
MDC
0.8 V
2
3
MDIO
2.0 V
0.8 V
2.0 V
0.8 V
MDC
4
2.0 V
0.8 V
MDIO
1: MDC clock cycle = tMDCCYC
2: MDIO input setup time to MDC rising edge = tMDIS
3: MDIO input hold time tp MDC rising edge = tMDIH
4: MDIO output skew from MDC rising edge = tMDIO
Figure 26-27 MDIO timing diagram
Datasheet
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XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
1
REF_CLK
1.4 V
2
3
2.0 V
0.8 V
RXD, RX_CTL,
RX_ER
4
2.0 V
0.8 V
TXD, TX_CTL
1: RMII reference clock cycle = 1/fREF_CLK
2: Data setup to REF_CLK rising edge = tSU
3: Data hold from REF_CLK rising edge = tHOLD
4: Data output delay from REF_CLK_rising edge = tTXOUT
Figure 26-28 RMII timing diagram
Datasheet
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.15
SDHC specifications
Table 26-32 SDHC specifications
Spec ID Parameter
Description
Min Typ Max Units Details/Conditions
SDHC and eMMC specifications (the source clock must be divided by 2 or more in DDR modes)
SID801
SID802
SID803
VSDHC
IODS
tIT
SDHC IO supply voltage
I/O drive select
2.7
8
–
–
–
3.6
8
V
For VDDIO_1 or VDDIO_3
drive_sel<1:0>= 0b00
for all modes
mA
ns
Input transition time
0.7
3
SD: DS timing specifications for GPIO_STD/HSIO_STD
SID810
SID812
SID813
fLP
CD
CC
Interface clock period
I/O loading at DATA/CMD pins
I/O loading at CLK pins
–
40
40
–
–
–
25
40
40
MHz 40-ns period
pF
pF
Output setup time of
CMD/DAT prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID814
SID815
SID816
SID818
tOS
5.5
5.5
24
0
–
–
–
–
–
–
–
–
ns
ns
tOH
tIS_LP
tIH
Clock period - Output
delay
ns
ns
SD: HS timing specifications for GPIO_STD/HSIO_STD
SID820
SID822
SID823
fLP_SD_HS
CD_SD_HS
CC_SD_HS
Interface clock period
I/O loading at DATA/CMD pins
I/O loading at CLK pins
–
40
40
–
–
–
50
40
40
MHz 20-ns period
pF
pF
Output setup time of
CMD/DAT prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID824
SID825
SID826
SID828
tOS_SD_HS
tOH_SD_HS
tIS_LP_SD_HS
tIH_SD_HS
6.5
2.5
4
–
–
–
–
–
–
–
–
ns
ns
Clock period less
output delay
ns
ns
2.5
eMMC: BWC timing specifications for GPIO_STD/HSIO_STD
fLP_eM-
MC_BWC
SID870
Interface clock period
–
–
26
MHz 38.4-ns period
SID872
SID873
CD_eMMC_BWC I/O loading at DATA/CMD pins
CC_eMMC_BWC I/O loading at CLK pins
30
30
–
–
30
30
pF
pF
tOS_eM-
MC_BWC
tOH_eM-
MC_BWC
tIS_LP_eM-
MC_BWC
Output setup time of
CMD/DAT prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID874
SID875
SID876
SID878
3.5
3.5
9.7
8.3
–
–
–
–
–
–
–
–
ns
ns
Clock period less
ns
output delay
tIH_eMMC_BWC
ns
eMMC: SDR timing specifications for HSIO_STD
SID880
fLP_eMMC_SDR Interface clock period
–
–
52
MHz 19.2-ns period
Datasheet
165
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-32 SDHC specifications (continued)
Spec ID Parameter
Description
Min Typ Max Units Details/Conditions
SID882
SID883
CD_eMMC_SDR I/O loading at DATA/CMD pins
CC_eMMC_SDR I/O loading at CLK pins
30
30
–
–
30
30
pF
pF
tOS_eM-
MC_SDR
tOH_eM-
MC_SDR
tIS_LP_eM-
MC_SDR
Output setup time of
CMD/DAT prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID884
SID885
SID886
SID888
3.5
3.5
3.5
2.5
–
–
–
–
–
–
–
–
ns
ns
ns
ns
Clock period less
output delay
tIH_eMMC_SDR
eMMC: DDR timing specifications for HSIO_STD
SID890
fLP_eMMC_DDR Interface clock period
DUTY_-
–
–
–
52
55
MHz 19.2-ns period
%
SID892
CLK_eM-
Duty cycle of output CLK
45
MC_DDR
SID893
SID894
CD_eMMC_DDR I/O loading at DATA/CMD pins
CC_eMMC_DDR I/O loading at CLK pins
20
20
–
–
20
20
pF
pF
tOS_eM-
MC_DDR
tOH_eM-
MC_DDR
tIS_LP_eM-
MC_DDR
Output setup time of
CMD/DAT prior to CLK
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Input hold time of CMD/DAT
after CLK
SID895
SID896
SID897
SID899
2.6
2.6
2.4
1.5
–
–
–
–
–
–
–
–
ns
ns
Clock period less
ns
output delay
tIH_eMMC_DDR
ns
Input Timing for SD: DS
1
VDDIO_1
or VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
3
2
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
1: Clock period = 1/fLP
2: Input setup time = tIS_LP
3: Input hold time = tIH
Figure 26-29 SD default speed input timing
Datasheet
166
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Output Timing for SD: DS
1
VDDIO_1
or
VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
2
3
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
Invalid
1: Clock period = 1/fLP
2: Output setup time = tOS
3: Output hold time = tOH
Figure 26-30 SD default speed output timing
Input Timing for SD: HS and eMMC: BWC/SDR
1
VDDIO_1
or VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
3
2
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
1: Clock period = 1/fLP_SD_HS or 1/fLP_eMMC_BWC or 1/fLP_eMMC_SDR
2: Input setup time = tIS_LP_SD_HS or tIS_LP_eMMC_BWC or tIS_LP_eMMC_SDR
3: Input hold time = tIH_SD_HS or tIH_eMMC_BWC or tIH_eMMC_SDR
Figure 26-31 SD high-speed and eMMC BWC/SDR input timing
Datasheet
167
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Output Timing for SD: HS and eMMC: BWC/SDR
1
VDDIO_1
or
VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
2
3
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
Invalid
1: Clock period = 1/fLP_SD_HS or 1/fLP_eMMC_BWC or 1/fLP_eMMC_SDR
2: Output setup time = tOS_SD_HS or tOS_eMMC_BWC or tOS_eMMC_SDR
3: Output hold time = tOH_SD_HS or tOH_eMMC_BWC or tOH_eMMC_SDR
Figure 26-32 SD high-speed and eMMC BWC/SDR output timing
Input Timing for eMMC: DDR
1
VDDIO_3
CLK
0.5 x VDDIO_3
VSSIO_3
2
3
2
3
CMD/DAT
Valid
Valid
0.5 x VDDIO_3
1: Clock period = 1/fLP_eMMC_DDR
2: Input setup time = tIS_LP_eMMC_DDR
3: Input hold time = tIH_eMMC_DDR
Figure 26-33 eMMC DDR input timing
Datasheet
168
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Output Timing for eMMC: DDR
1
VDDIO_3
0.5 x VDDIO_3
CLK
VSSIO_3
2
3
2
3
CMD/DAT
0.5 x VDDIO_3
Valid
Valid
1: Clock period = 1/fLP_eMMC_DDR
2: Output setup time = tOS_LP_eMMC_DDR
3: Output hold time = tOH_eMMC_DDR
Figure 26-34 eMMC DDR output timing
Datasheet
169
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.16
Audio subsystem specifications
Table 26-33 Audio subsystem specifications
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
SID770
fAUDIO
Audio subsystem frequency
–
–
200
MHz Guaranteed by design
Audio subsystem I/O supply
voltage
SID772
SID773
SID774
SID775
SID776
VAUDIO
3.0
–
–
–
–
–
–
3.6
V
V
V
V
V
For VDDIO_2
drive_sel<1:0>= 0b0X,
Pull-up, pull-down: off
drive_sel<1:0>= 0b0X,
Pull-up, pull-down: off
VOL_A
Output voltage LOW level
Output voltage HIGH level
0.4
–
VDDIO_2
– 0.5
VOH_A
Input voltage HIGH threshold
in CMOS mode
Input Voltage LOW threshold
in CMOS mode
0.7 ×
VIH_CMOS_A
–
VDDIO_2
0.3 ×
VIL_CMOS_A
–
VDDIO_2
I2S/TDM word clock frequency
SID796
SID797
SID798
fWS_I2S
fWS_TDM
Word
WS Clock Rate in I2S mode
WS Clock Rate in TDM mode
Length of I2S Word
8
–
8
–
–
–
192
96
32
kHz Guaranteed by design
kHz Guaranteed by design
bit Guaranteed by design
I2S/TDM Master mode
Except TDM 96 kHz
mode, TX/RX_WS output
ns and TX/RX_SCK output
with drive_sel<1:0> = 0b
01,guaranteed by design
Delay Time of TX/RX_WS
Output Transition from
Falling Edge of TX/RX_SCK
Output
SID740
tD_WS
–8
–8
–
–
9
TDM 96 kHz mode,
TX/RX_WS output with
drive_sel<1:0> = 0b01
ns and TX/RX_SCK output
with drive_sel<1:0> =
0b00,
Delay Time of TX/RX_WS
output Transition from
Falling Edge of TX/RX_SCK
output
SID740A tD_WS_TDM96A
11
guaranteed by design
TX_SDO and TX_SCK
output with
Delay Time of TX_SDO
Transition from Falling Edge
of TX_SCK Output
drive_sel<1:0> = 0b01 for
SID741
tD_SDO
–8
–
–
8
8
ns
except TDM 96 kHz
mode,
guaranteed by design
TX_SDO with
drive_sel<1:0> = 0b01
and TX_SCK output with
ns drive_sel<1:0> = 0b00 for
TDM
Delay Time of TX_SDO
SID741A tD_SDO_TDM96 Transition from Falling Edge
of TX_SCK Output
–8
11
96 kHz mode,
guaranteed by design
RX_SDI Setup Time to the
Following Rising Edge of
RX_SCK output with
ns drive_sel<1:0> = 0b00,
guaranteed by design
SID742
SID743
SID744
tS_SDI
tH_SDI
tS_SDI1
–
–
–
–
–
–
RX_SCK Output
(RX_CTL.B_CLOCK_INV = 0)
RX_SDI Hold Time to the
RX_SCK output with
ns drive_sel<1:0> = 0b00,
guaranteed by design
tMCLK_S
OC – 0.9
Rising Edge of RX_SCK Output
(RX_CTL.B_CLOCK_INV = 0)
RX_SDI Setup Time to the
Following Falling Edge of
RX_SCK Output
RX_SCK output with
ns drive_sel<1:0> = 0b00,
guaranteed by design
11
(RX_CTL.B_CLOCK_INV = 1)
Datasheet
170
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-33 Audio subsystem specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
RX_SDI Hold Time to the
Falling Edge of RX_SCK
Output
RX_SCK output with
tMCLK_S
OC – 0.9
SID745
tH_SDI1
–
–
ns drive_sel<1:0> = 0b00,
guaranteed by design
(RX_CTL.B_CLOCK_INV = 1)
TX/RX_SCK Output Bit Clock
SID746
SID748
tSCKCY
45
–
55
%
Guaranteed by design
Duty Cycle
196.60
8
Internal Fractional PLL,
guaranteed by design
fMCLK_SOC
MCLK input clock frequency
1.024
1.024
5.086
–
–
–
MHz
SID748A fMCLK_SOC_E MCLK input clock frequency
98.304 MHz External clock
976.56
SID749
SID750
tMCLK_SOC
tJITTER
MCLK input clock period
ns Guaranteed by design
3
MCLK Input clock jitter
tolerance
–200
–
–
200
ps Guaranteed by design
MCLK output with
MHz drive_sel<1:0> = 0b00
Guaranteed by design
MCLK output with
MHz drive_sel<1:0> = 0b01
Guaranteed by design
SID748B fMCLK
SID748C fMCLK1
MCLK output clock frequency
1.024
25
MCLK output clock frequency
MCLK output clock duty
1.024
45
–
–
15
55
SID749B fMCLK_DT
I2S/TDM Slave mode
%
Guaranteed by design
TX/RX_WS Input Alignment
Clock Setup Time to the
following Rising Edge of
TX/RX_SCK Input
TX/RX_WS Input Alignment
Clock Hold Time to the Rising
Edge of TX/RX_SCK Input
SID751
SID752
SID753
tS_WS
tH_WS
tD_SDO
5
–
–
–
–
–
ns Guaranteed by design
ns Guaranteed by design
tMCLK_S
OC + 5.0
Delay Time of TX_SDO
Transition from Falling Edge
of TX_SCK Input
–
TX_SDO with
tMCLK_S
OC + 15
tMCLK_S
OC + 5.0
ns drive_sel<1:0>= 0b00,
guaranteed by design
(TX_CTL.B_CLOCK_INV = 0)
Delay Time of TX_SDO
Transition from Rising Edge of
TX_SCK Input
–
TX_SDO with
tMCLK_S
OC + 15
SID754
SID755
tD_SDO1
tMCLK_S
OC + 5.0
–
–
ns drive_sel<1:0>= 0b00,
guaranteed by design
(TX_CTL.B_CLOCK_INV = 1)
RX_SDI Setup Time to the
Following Rising Edge of
RX_SCK Input
tS_SDI
tH_SDI
tSCKCY
5
–
ns Guaranteed by design
ns Guaranteed by design
RX_SDI Hold Time to the
tMCLK_S
OC + 5.0
SID756
SID757
–
–
–
Rising Edge of RX_SCK Input
TX/RX_SCK Input Bit Clock
Duty Cycle
45
55
%
Guaranteed by design
Datasheet
171
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
I2S/TDM Master Mode: Output Delay Timing
VDDIO_2
TX/RX_SCK
or TX_SCK
output
0.5 x VDDIO_2
VSSD
1
VDDIO_2
TX/RX_WS
or TX_SDO
output
0.5 x VDDIO_2
VSSD
1: Delay time = tD_WS or tD_WS_TDM96A or tD_SDO or tD_SDO_TDM96
Figure 26-35 Master output delay
I2S/TDM Master Mode: Setup Timing
(RX_CTL.B_CLOCK_INV = 0)
VDDIO_2
RX_SCK
output
0.5 x VDDIO_2
VSSD
1
2
VDDIO_2
RX_SDI
input
0.5 x VDDIO_2
VSSD
1: Setup time = tS_SDI
2: Hold time = tH_SDI
Figure 26-36 Master setup without clock inversion
Datasheet
172
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
I2S/TDM Master Mode: Setup Timing
(RX_CTL.B_CLOCK_INV = 1)
VDDIO_2
RX_SCK
output
0.5 x VDDIO_2
VSSD
1
2
VDDIO_2
RX_SDI
input
0.5 x VDDIO_2
VSSD
1: Setup time = tS_SDI1
2: Hold time = tH_SDI1
Figure 26-37 Master setup with clock inversion
I2S/TDM Slave Mode: Output Delay Timing
VDDIO_2
TX_SCK input
(TX_CTL.B_CLOCK_INV = 0)
0.5 x VDDIO_2
VSSD
VDDIO_2
TX_SCK input
0.5 x VDDIO_2
(TX_CTL.B_CLOCK_INV = 1)
VSSD
1
VDDIO_2
TX_SDO output
0.5 x VDDIO_2
VSSD
1: Delay time = tD_SDO or tD_SDO1
Figure 26-38 Slave output delay
Datasheet
173
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
I2S/TDM Slave Mode: Setup Timing
VDDIO_2
TX/RX_SCK
or RX_SCK
input
0.5 x VDDIO_2
VSSD
1
2
VDDIO_2
TX/RX_WS
or RX_SDI
input
0.5 x VDDIO_2
VSSD
1: Setup time = tS_WS or tS_SDI
2: Hold time = tH_WS or tH_SDI
Figure 26-39 Slave setup
Datasheet
174
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
26.17
Serial memory interface specifications
Table 26-34 SMIF specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
SMIF DC specification
For VDDIO_1 or
VDDIO_3
SID785 VSMIF
SMIF I/O supply voltage
2.7
–
3.6
V
SMIF HSSPI(SDR) specification for HSIO_STD
SID760
SID761
SID762
SID763
SID764
SID765
SID766
SID767
CL_SDR_HSIO
SR_SDR_HSIO
fCK_SDR_HSIO
tCK_SDR_HSIO
Load capacitance
Input rise and fall slew rates
Clock frequency
–
1.5
-
–
–
–
–
–
–
–
–
30
–
pF
V/ns
MHz
ns
Guaranteed by
design
100
–
1 / f
CK_S-
Clock period
DR_HSIO
DCK_SDR_HSIO Clock duty
45
55
–
%
Clock rise and fall slew
rates
Chip select HIGH time
Chip select active setup
time
CSR_SDR_HSIO
tCS_SDR_HSIO
tCSS_SDR_HSIO
1.5
10
3
V/ns
ns
–
–
ns
SID768
SID769
SID780
SID781
SID782
SID783
tCSH_SDR_HSIO Chip select active hold time
5
1.5
2
1.5
2
–
–
–
–
–
–
–
–
–
7.65
–
7.5
ns
ns
ns
ns
ns
ns
tSU_SDR_HSIO
tHD_SDR_HSIO
tV_SDR_HSIO
tHO_SDR_HSIO
tDIS_SDR_HSIO
tIO_SKEW_S-
DR_HSIO
Data setup time
Data hold time
Clock LOW output valid
Input hold time
Input disable time
0
Data skew (first data bit to
last data bit)
Guaranteed by
design
SID784
–
–
0.6
ns
SMIF HSSPI(SDR) specification for GPIO_STD
SID760A CL_SDR_GPIO
SID761A SR_SDR_GPIO
SID762A fCK_SDR_GPIO
SID763A tCK_SDR_GPIO
Load capacitance
Input rise and fall slew rates
Clock frequency
–
1
–
–
–
–
–
–
–
–
–
30
–
pF
V/ns
MHz
ns
Guaranteed by
design
32
–
1 / f
CK_S-
Clock period
DR_GPIO
SID764A DCK_SDR_GPIO Clock duty
45
55
–
%
Clock rise and fall slew
rates
Chip select HIGH time
Chip select active setup
time
SID765A CSR_SDR_GPIO
SID766A tCS_SDR_GPIO
SID767A tCSS_SDR_GPIO
1
30
9
V/ns
ns
–
–
ns
SID768A tCSH_SDR_GPIO Chip select active hold time
15
4.5
6
4.5
2
–
–
–
–
–
–
–
–
9
–
ns
ns
ns
ns
ns
SID769A tSU_SDR_GPIO
SID780A tHD_SDR_GPIO
SID781A tV_SDR_GPIO
SID782A tHO_SDR_GPIO
Data setup time
Data hold time
Clock LOW output valid
Input hold time
Datasheet
175
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-34 SMIF specifications [Conditions: drive_sel<1:0>= 00] (continued)
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
SID783A tDIS_SDR_GPIO
Input disable time
0
–
22.5
ns
tIO_SKEW_S-
DR_GPIO
Data skew (first data bit to
last data bit)
Guaranteed by
design
SID784A
–
–
1.8
ns
SMIF HSSPI(DDR) specification for HSIO_STD
SID760B CL_DDR_HSIO
SID761B SR_DDR_HSIO
SID762B2 fCK_DDR_HSIO
SID763B tCK_DDR_HSIO
Load capacitance
Input rise and fall slew rates
Clock frequency
–
1.5
-
–
–
–
–
–
–
–
–
15
-
pF
V/ns
MHz
ns
Guaranteed by
design
90
–
1 / fCK_D-
DR_HSIO
45
Clock period
SID764B DCK_DDR_HSIO Clock duty
55
–
%
Clock rise and fall slew
rates
Chip select HIGH time
Chip select active setup
time
SID765B CSR_DDR_HSIO
SID766B tCS_DDR_HSIO
SID767B tCSS_DDR_HSIO
1.5
10
4
V/ns
ns
–
–
ns
SID768B tCSH_DDR_HSIO Chip select active hold time
4
2
1.2
0
1
–
–
–
–
–
–
–
–
–
–
6.5
–
7.5
ns
ns
ns
ns
ns
ns
SID769B tSU_DDR_HSIO
SID780B tHD_DDR_HSIO
SID781B tV_DDR_HSIO
SID782B tHO_DDR_HSIO
SID783B tDIS_DDR_HSIO
Data setup time
Data hold time
Clock LOW output valid
Input hold time
Input disable time
tIO_SKEW_D-
DR_HSIO
Data skew (first data bit to
last data bit)
Guaranteed by
design
SID784B
–
–
0.6
ns
SMIF HSSPI(DDR) specification for GPIO_STD
SID760C CL_DDR_GPIO
SID761C SR_DDR_GPIO
SID762C fCK_DDR_GPIO
SID763C tCK_DDR_GPIO
Load capacitance
Input rise and fall slew rates
Clock frequency
–
1
–
–
–
–
–
–
–
–
–
15
–
pF
V/ns
MHz
ns
Guaranteed by
design
32
-
1 / fCK_D-
DR_GPIO
45
Clock period
SID764C DCK_DDR_GPIO Clock duty
55
–
%
Clock rise and fall slew
rates
Chip select HIGH time
Chip select active setup
time
SID765C CSR_DDR_GPIO
SID766C tCS_DDR_GPIO
SID767C tCSS_DDR_GPIO
1
30
5
V/ns
ns
–
–
ns
SID768C tCSH_DDR_GPIO Chip select active hold time
4
5
4.5
0
3
–
–
–
–
–
–
–
–
–
–
9
–
ns
ns
ns
ns
ns
ns
SID769C tSU_DDR_GPIO
SID780C tHD_DDR_GPIO
SID781C tV_DDR_GPIO
SID782C tHO_DDR_GPIO
SID783C tDIS_DDR_GPIO
Data setup time
Data hold time
Clock LOW output valid
Input hold time
Input disable time
22.5
Datasheet
176
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-34 SMIF specifications [Conditions: drive_sel<1:0>= 00] (continued)
Spec ID
Parameter
tIO_SKEW_D-
DR_GPIO
Description
Data skew (first data bit to
last data bit)
Min
Typ Max Units Details/Conditions
Guaranteed by
SID784C
–
–
1.8
ns
design
SMIF HYPERBUS™ specification for HSIO_STD
SID785
CL_HB_HSIO
Load capacitance
–
1
–
–
20
–
pF
For all signals,
SID786
SRI_HB_HSIO
Input rise and fall slew rates
V/ns Guaranteed by
design
Output rise and fall slew
rates
SID787
SRO_HB_HSIO
1
–
–
V/ns For all signals
Clock characteristics
SID700
SID701
SID702
fCK_HB_HSIO
tCK_HB_HSIO
DCK_HB_HSIO
Clock frequency
Clock period
Clock duty
–
–
–
–
100
–
MHz
ns
1 / fCK_H-
B_HSIO
45
55
%
AC parameters
Chip select HIGH between
transactions
Chip select setup to next CK
rising edge
Guaranteed by
design
SID706
SID708
tCSHI_HB_HSIO
10
3
–
–
–
–
ns
tCSS_HB_HSIO
ns
SID709
SID710
SID711
SID715
SID718
SID719
tDSV_HB_HSIO
tOSU_HB_HSIO
tOH_HB_HSIO
tCKD_HB_HSIO
tCKDS_HB_HSIO CK transition to RWDS valid
tDSS_HB_HSIO
Data strobe valid
DQ output setup
DQ output hold
–
1
1
1
1
–
–
–
–
–
–
12
–
–
5.5
5.5
0.8
ns
ns
ns
ns
ns
ns
CK transition to DQ valid
RWDS transition to DQ valid
–0.8
RWDS transition to DQ
invalid
Chip select hold after CK
falling edge
SID720
SID721
tDSH_HB_HSIO
–0.8
0
–
–
0.8
-
ns
ns
tCSH_HB_HSIO
SMIF HYPERBUS™ specification for GPIO_STD
SID785A CL_HB_GPIO
Load capacitance
–
–
–
20
–
pF
For all signals,
V/ns guaranteed by
design
SID786A SRI_HB_GPIO
Input rise and fall slew rates
0.45
Output rise and fall slew
rates
SID787A SRO_HB_GPIO
0.45
–
–
V/ns For all signals
Clock characteristics
SID700A fCK_HB_GPIO
Clock frequency
Clock period
Clock duty
-
–
–
–
32
–
MHz
ns
1 / fCK_H-
B_GPIO
SID701A tCK_HB_GPIO
SID702A DCK_HB_GPIO
45
55
%
AC parameters
Chip select HIGH between
transactions
Guaranteed by
design
SID706A tCSHI_HB_GPIO
30
–
–
ns
Datasheet
177
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
Table 26-34 SMIF specifications [Conditions: drive_sel<1:0>= 00] (continued)
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
Chip select setup to next CK
rising edge
SID708A tCSS_HB_GPIO
SID709A tDSV_HB_GPIO
9
–
–
–
ns
ns
Guaranteed by
design
Data strobe valid
–
36
SID710A tOSU_HB_GPIO
SID711A tOH_HB_GPIO
SID715A tCKD_HB_GPIO
SID718A tCKDS_HB_GPIO CK transition to RWDS valid
SID719A tDSS_HB_GPIO
DQ output setup
DQ output hold
CK transition to DQ valid
3
3
3
3
–2.4
–
–
–
–
–
–
–
16.5
16.5
2.4
ns
ns
ns
ns
ns
RWDS transition to DQ valid
RWDS transition to DQ
invalid
Chip select hold after CK
falling edge
SID720A tDSH_HB_GPIO
–2.4
0
–
–
2.4
–
ns
ns
SID721A tCSH_HB_GPIO
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tSU
tHD
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 26-40 SDR Write timing reference level
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tV
tV
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 26-41 SDR Read timing reference level
Datasheet
178
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
tCK
VDD IO_1
or
VDD IO_3
CK
VSSD
or
VSSIO_3
tSU
tHD
tSU
tHD
0.5 x VDDIO_1
or VDD IO_3
Data
Timing Reference Level
Figure 26-42 DDR Write timing reference level
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
tV
VSSIO_3
Timing
0.5 x VDDIO_1
or VDDIO_3
Data
Reference Level
Figure 26-43 DDR Read timing reference level
CK
1
6
Chip
select
2
3
8
4
5
LSB IN
LSB OUT
MSB IN
MSB OUT
Data
1: Chip select active setup time = tCSS
2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW output valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS
Figure 26-44 SDR Write and Read timing diagram
Datasheet
179
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2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
CK
7
1
Chip
select
4
5
4
8
2
3
2
3
MSB OUT
LSB OUT
MSB IN
LSB IN
Data
1: Chip select active setup time = tCSS
2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW output valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS
Figure 26-45 DDR Write and Read timing diagram
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tIS
tIH
tIS
tIH
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 26-46 HYPERBUS™ timing reference level
Datasheet
180
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Electrical specifications
9
Chip
select
10
1
CK
2
5
RWDS
3
4
3
4
DQ[7:0]
(output)
Command Address
Host drives DQ[7:0] and RWDS
6
7
8
DQ[7:0]
(input)
Memory drives DQ[7:0] and RWDS
1: Chip select setup to next CK rising edge = tCSS
2: Data strobe valid = tDSV
3: DQ output setup = tOSU
4: DQ output hold = tOH
5: CK transition to RWDS valid = tCKDS
6: CK transition to DQ valid = tCKD
7: RWDS transition to DQ valid = tDSS
8: RWDS transition to DQ invalid = tDSH
9: Chip select hold after CK falling edge = tCSH
10: Chip select HIGH between transactions = tCSHI
Figure 26-47 HYPERBUS™ timing diagram
Datasheet
181
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Ordering information
27
Ordering information
The XMC7100 microcontroller part numbers and features are listed in Table 27-1.
Table 27-1
XMC7100 ordering information
XMC7100-F100K1088
100-TEQFP
100-TEQFP
100-TEQFP
100-TEQFP
100-TEQFP
144-TEQFP
144-TEQFP
144-TEQFP
144-TEQFP
176-TEQFP
176-TEQFP
272-BGA
1
1
1
2
2
1
1
2
2
1
2
1
2
1088
2112
4160
2112
4160
2112
4160
2112
4160
4160
4160
4160
4160
128
128
256
128
256
128
256
128
256
256
256
256
256
192
384
768
384
768
384
768
384
768
768
768
768
768
37
37
37
37
37
52
52
52
52
64
64
72
72
9
9
1
1
1
1
1
1
1
1
1
1
1
1
1
125°C
125°C
125°C
125°C
125°C
125°C
125°C
125°C
125°C
125°C
125°C
125°C
125°C
0x1E944069
0x1E945069
0x1E946069
0x1E947069
0x1E948069
0x1E949069
0x1E94A069
0x1E94B069
0x1E94C069
0x1E94D069
0x1E94E069
0x1E94F069
0x1E950069
XMC7100-F100K2112
XMC7100-F100K4160
XMC7100D-F100K2112
XMC7100D-F100K4160
XMC7100-F144K2112
XMC7100-F144K4160
XMC7100D-F144K2112
XMC7100D-F144K4160
XMC7100-F176K4160
XMC7100D-F176K4160
XMC7100-E272K4160
XMC7100D-E272K4160
9
9
9
10
10
10
10
10
10
11
11
272-BGA
27.1
Part number nomenclature
Table 27-2
Ordering code nomenclature
Description
XMC prefix
Series Name
Values
XMC
7100
D
Meaning
Comment
XMC prefix- industrial microcontroller
Entry level XMC7000 series
Dual-core option based on both dies
Fixed
Dual-Core option
Optional. Omitting “D”
in part number means
single core version
Code-Flash/
Work-Flash/RAM
Density
1088
2112
4160
100
144
176
272
F
1088 KB / 128 KB / 192 KB
2112 KB / 128 KB / 384 KB
4160 KB / 256 KB / 768 KB
PKG Pin Count
100-pin
144-pin
176-pin
272-pin
TEQFP
BGA
PKG pin count options
Package option
Available package
options
E
Datasheet
182
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
28
Packaging
The XMC7100 microcontroller is offered in the packages listed in the Table 28-1.
Table 28-1
Package
Package Information
Dimensions[73]
Contact/lead pitch Coefficient of thermal expansion
I/O pins
a1[74] = 6 ppm/°C,
272-BGA 16 × 16 × 1.70 mm (max)
0.8-mm
220
a2[75] = 25 ppm/°C
176-TEQFP 24 × 24 × 1.60 mm (max)
144-TEQFP 20 × 20 × 1.60 mm (max)
100-TEQFP 14 × 14 × 1.60 mm (max)
0.5-mm
0.5-mm
0.5-mm
a1 = 9.5 ppm/°C, a2 = 37 ppm/°C
a1 = 9.5 ppm/°C, a2 = 36.7 ppm/°C
a1 = 9.4 ppm/°C, a2 = 36 ppm/°C
148
116
72
Table 28-2
Parameter
Package characteristics
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient
temperature
-
–40
–
125
°C
TJ
Operating junction
temperature
–
–
–
150
°C
272-BGA
176-TEQFP
144-TEQFP
100-TEQFP
272-BGA
176-TEQFP
144-TEQFP
100-TEQFP
272-BGA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
21.6
17.8
17.4
18.3
12.8
13.0
12.3
10.4
10.4
8.0
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Package thermal resistance,
RθJA
RθJB
RθJC
[76, 77]
junction to ambient θJA
Package θJB
176-TEQFP
144-TEQFP
100-TEQFP
Package thermal resistance,
junction to case θJC
8.1
8.5
Table 28-3
Package
Solder reflow peak temperature, Package moisture sensitivity level (MSL), IPC/JEDEC
J-STD-2
Maximum peak temperature
(°C)
Maximum time at peak temperature
(seconds)
MSL
272-BGA
176-TEQFP
144-TEQFP
100-TEQFP
260
260
260
260
30
30
30
30
3
3
3
3
Notes
73.The dimensions (column 2) are valid for room temperature.
74.a1 = CTE (Coefficient of Thermal Expansion) value below Tg (ppm/°C) (Tg is glass transition temperature which is 131°C).
75.a2 = CTE value above Tg (ppm/°C).
76.Maximum value °C/Watt shown is for TA = 125 °C.
77.Board condition complies to JESD51-7(4 Layers).
Datasheet
183
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
4
5
7
8
BOTTOM VIEW
TOP VIEW
2
DETAIL A
11
10
DETAIL A
SIDE VIEW
DIMENSION
SYMBOL
MIN. NOM. MAX.
1.60
A
0.15
0.05
A1
D
16.00 BSC
14.00 BSC
6.10 REF
D
D
D
E
E
E
E
R
1
2
3
5.30 REF
16.00 BSC
14.00 BSC
6.10 REF
5.30 REF
1
2
3
1
0.08
0.08
0°
0.20
8°
R
θ
2
0.09
0.15
0.45
0.127 0.20
0.27
c
b
L
L
L
e
0.60
0.75
1.00 REF
0.25 REF
0.50 BSC
1
2
002-28239 *B
Figure 28-1
Package outline – 100-TEQFP
Datasheet
184
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
4
5
7
BOTTOM VIEW
8
TOP VIEW
2
DETAIL A
11
10
DETAIL A
SIDE VIEW
DIMENSION
SYMBOL
MIN. NOM. MAX.
1.60
A
0.15
0.05
A1
D
22.00 BSC
20.00 BSC
6.10 REF
D
D
D
E
E
E
E
R
1
2
3
5.30 REF
22.00 BSC
20.00 BSC
6.10 REF
5.30 REF
1
2
3
1
0.08
0.08
0°
0.20
8°
R
θ
2
0.09
0.17
0.45
0.127 0.20
c
b
L
L
L
e
0.20
0.60
0.27
0.75
1.00 REF
0.25 REF
0.50 BSC
1
2
002-28240 *B
Figure 28-2
Package outline – 144-TEQFP
Datasheet
185
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
4
5
7
BOTTOM VIEW
8
TOP VIEW
2
DETAIL A
11
10
DETAIL A
SIDE VIEW
DIMENSION
SYMBOL
MIN. NOM. MAX.
1.60
A
0.15
0.05
A1
D
26.00 BSC
24.00 BSC
6.10 REF
D
D
D
E
E
E
E
R
1
2
3
5.30 REF
26.00 BSC
24.00 BSC
6.10 REF
5.30 REF
1
2
3
1
0.08
0.08
0°
0.20
8°
R
θ
2
0.09
0.17
0.45
0.127 0.20
c
b
L
L
L
e
0.20
0.60
0.27
0.75
1.00 REF
0.25 REF
0.50 BSC
1
2
002-28241 *B
Figure 28-3
Package outline – 176-TEQFP
Datasheet
186
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Packaging
002-24865 *A
Figure 28-4
Package Outline – 272-BGA
Datasheet
187
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Appendix
29
Appendix
29.1
Bootloading or end-of-line (EoL) programming
• Triggered at device startup, if a trigger condition is applied
• CAN communication may be used
• Bootloader polls for the communication on CAN at separate time frames, until the overall 300-second timeout
is reached
• If a bootloader command is received on either communication interface, the polling stops and bootloader starts
using this interface
150 ms
10 ms
10 ms
CAN,
100 Kbps
Polling
CAN,
500 Kbps
Polling
CAN,
100 Kbps
Polling
Bootloader
Stopped
Reserved
….
Overall bootloading time, if no communication ( 300 s)
Figure 29-1
Bootloading sequence
CAN interface details
Table 29-1
Sl. No.
CAN interface
Configuration
1
2
3
4
5
6
7
8
9
CAN Mode
CAN Instance
CAN TX
CAN RX
CAN Transceiver NSTB / EN (Low)
CAN Transceiver EN / EN (High)
CAN RX Message ID
Classic CAN
CAN0, Channel#1
P0.2 / CAN0_1_TX
P0.3 / CAN0_1_RX
P23.3 (optional)
P2.1 (optional)
0x1A1
CAN TX Message ID
Baud
0x1B1
100 or 500 kbps alternating
VSS
CAN
Transceiver
XMC7100
EN (Low)
NSTB
EN
EN (High)
TX
TX
RX
RX
Figure 29-2
MCU to CAN transceiver connections
Datasheet
188
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Appendix
29.2
External IP revisions
Table 29-2
IP revisions
Module
IP
mxsdhc
mxttcanfd
armcm0p
armcm7
Revision
Vendor
Synopsys
Bosch
Arm®
Arm®
SDHC
CANFD
version 1.70a
M_TTCAN IP revision: Rev.3.2.3
Cortex®-M0+ AT590-r0p1-00rel0
CORTEX-M7-r1p1-00rel0
Arm® Cortex®-M0+
Arm® Cortex®-M7
Arm® Coresight
Ethernet
armcoresighttk CoreSight-SoC-TM100-r3p2-00rel0
mxeth
Arm®
Cadence
GEM_GXL r1p09
Datasheet
189
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Acronyms
30
Acronyms
Table 30-1
Acronyms used in the document
Acronym
A/D
Description
Analog to digital
ABS
Absolute
ADC
AES
Analog to Digital converter
Advanced encryption standard
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus,
Arm® data transfer bus
Arm®
BOD
CAN FD
CMOS
CPU
CRC
CSV
Advanced RISC machine, a CPU architecture
Brown-out detection
Controller Area Network with Flexible Data rate
Complementary metal-oxide-semiconductor
Central Processing Unit
Cyclic redundancy check, an error-checking protocol
Clock supervisor
CTI
Cross Trigger Interface
DES
ECC
Data encryption standard
Error correcting code
ECO
ETM
FLL
External crystal oscillator
Embedded Trace Macrocell
Frequency Locked Loop
FPU
GPIO
HSM
I/O
Floating point unit
General-purpose input/output
Hardware security module
Input/output
Inter-Integrated Circuit, a communications protocol
Inter-Integrated Circuit Sound
Internal low-speed oscillator
Internal main oscillator
I2C
I2S
ILO
IMO
IPC
IrDA
IRQ
Inter-processor communication
Infrared interface
Interrupt request
JTAG
LVD
Joint test action group
Low voltage detection
MCU
MCWDT
M-DMA
MISO
MMIO
MOSI
MPU
Microcontroller Unit
Multi-counter watchdog timer
Memory-Direct Memory Access
Master-in slave-out
Memory mapped I/O
Master-out slave-in
Memory protection unit
Datasheet
190
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Acronyms
Table 30-1
Acronyms used in the document
Description
Over-the-air programming
One-time programmable
Overvoltage detection
Acronym
OTA
OTP
OVD
PASS
P-DMA
PLL
Programmable Analog Subsystem
Peripheral-Direct Memory Access
Phase Locked Loop
POR
Power-on reset
PPU
Peripheral protection unit
Pseudorandom number generator
Programmable system on chip
Pulse-width modulation
Random access memory
Reduced-instruction-set computing
Read only memory
PRNG
PSoC
PWM
RAM
RISC
ROM
RTC
Real-time clock
SAR
SCB
SCL
SDA
Successive approximation register
Serial communication block
I2C serial clock
I2C serial data
SHA
Secure hash algorithm
SHE
SMPU
SPI
SRAM
SWD
TCM
Secure hardware extension
Shared memory protection unit
Serial peripheral interface, a communications protocol
Static random access memory
Single wire debug
Tightly Coupled Memory
TCPWM
TTL
Timer/Counter Pulse-width modulator
Transistor-transistor logic
True random number generator
Universal Asynchronous Transmitter Receiver, a communications protocol
Watch crystal oscillator
TRNG
UART
WCO
WDT
XIP
Watchdog timer reset
eXecute In Place
XTAL
Crystal
Datasheet
191
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Errata
31
Errata
This section describes the errata for the XMC7100 product family. Details include trigger conditions, scope of
impact, available workaround, and silicon revision applicability. Contact your local Infineon Sales Represen-
tative if you have further questions.
Part numbers affected
Part numbers
All XMC7100 parts
XMC7100 qualification status
Production samples
XMC7100 errata summary
The following table defines the errata applicability to available XMC7100 family devices.
Errata
ID
Silicon
Rev.
Items
XMC7100
Fix Status
[1] CAN FD RX FIFO top pointer feature
does not function as expected
96
All parts
No silicon fix planned.
Use workaround.
[2] CAN FD debug message handling
state machine is not reset to Idle state
when CANFD_CH_CCCR.INIT is set
97
No silicon fix planned.
Use workaround.
B
[3] Limitation of the memory hole in SCB
124
128
No silicon fix planned.
Use workaround.
register space
[4] Limitation of the memory hole in
Ethernet (ETH) register space
No silicon fix planned.
Use workaround.
1. CAN FD RX FIFO top pointer feature does not function as expected
Problem Definition
RX FIFO top pointer function calculates the address for received messages in Message
RAM by hardware. This address should restart back from the start address after reading
all messages of RX FIFO n size (n: 0 or 1). However, the address does not restart back
from the start address when RX FIFO n size is set to 1(CANFD_CH_RXFnC.FnS = 0x01).
This results in CPU/DMA reading messages from the wrong address in Message RAM.
Parameters Affected NA
Trigger Condition(s) The RX FIFO top pointer function is used when RX FIFO n size is set to 1 element
(CANFD_CH_RXFnC.FnS = 0x01).
Scope of Impact
Workaround
Received message cannot be correctly read by using the RX FIFO top pointer function,
when RX FIFO n size is set to 1 element.
Any of the following can be used as a workaround:
1) Set RX FIFO n size to 2 or more when using RX FIFO top pointer function.
2) Do not use the RX FIFO top pointer function when RX FIFO n size is set to 1 element.
Instead of RX FIFO top pointer, read received messages from the Message RAM directly.
Fix Status
No silicon fix planned. Use workaround.
Datasheet
192
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Errata
2.CAN FD debug message handling state machine is not reset to Idle state when CANFD_CH_CCCR.INIT
is set
Problem Definition
If either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN
module enters BusOff state, the debug message handling state machine stays in its
current state instead of being reset to Idle state. Configuring the bit
CANFD_CH_CCCR.CCE does not change CANFD_CH_RXF1S.DMS.
Parameters Affected NA
Trigger Condition(s) Either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN
module enters BusOff state.
Scope of Impact
The errata is limited to the use case when the debug on CAN functionality is active.
Normal operation of the CAN module is not affected, in which case the debug message
handling state machine always remains in Idle state. In the described use case, the
debug message handling state machine is stopped and remains in the current state
signaled by the CANFD_CH_RXF1S.DMS bit. In case CANFD_CH_RXF1S.DMS is set to
0b11, the DMA request remains active.
Bosch classifies this as a non-critical error with low severity, there is no fix for the IP.
Bosch recommends the workaround listed here.
Workaround
Fix Status
In case the debug message handling state machine has stopped while
CANFD_CH_RXF1S.DMS is 0b01 or 0b10, it can be reset to Idle state by hardware reset
or by reception of debug messages after CANFD_CH_CCCR.INIT is reset to zero.
No silicon fix planned. Use workaround.
3.Limitation of the memory hole in SCB register space
Problem Definition The memory hole [offset address: 0x1000 to 0xFFFF] inside SCB register space is not
aligned to the below defined spec. The offset address bits [15:12] are ignored and
treated as 4’b0000, so write/read access to offset address [0x1000 to 0xFFFF], will
actually happen to [0x0000 to 0x0FFF].
- Access to address gaps in memory mapped space: writes are ignored and any read
returns a zero.
Parameters Affected NA
Trigger Condition(s) Access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
Scope of Impact
Workaround
Fix Status
The memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space is not
aligned to other IP registers.
Do not access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register
space.
No silicon fix planned.
Datasheet
193
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Errata
4.Limitation of the memory hole in Ethernet (ETH) register space
Problem Definition
The memory hole [offset address: 0x2000 to 0xFFFF] in ETH register space has the
below mentioned original spec. However, when accessing to address gaps within
[0x1000 to 0x1FFF], the offset address bits [15:13] are ignored and treated as 3’b000,
so write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to
0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will
actually happen to [0x1000 to 0x1FFF].
- Access to address gaps within [0x0000 to 0x0FFF]: writes are ignored and any read
returns a zero.
- Access to address gaps within [0x1000 to 0x1FFF]: returns AHB ERROR.
Parameters Affected NA
Trigger Condition(s) Access to the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF,
0x7000 to 0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to
0xFFFF] in ETH register space.
Scope of Impact
Workaround
Fix Status
Write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to
0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will
actually happen to [0x1000 to 0x1FFF].
Do not access to the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF,
0x7000 to 0x7FFF, 0x9000 to 0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to
0xFFFF] in ETH register space.
No silicon fix planned.
Datasheet
194
002-33896 Rev. *A
2022-10-20
XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Revision History
Revision History
Document
Date of release
version
Description of changes
**
2021-12-17
New datasheet.
Updated Features and Architecture block diagram.
Updated 100-TQFP, 144 TQFP, and 176 TQFP package diagrams.
*A
2022-10-20
Datasheet
195
002-33896 Rev. *A
2022-10-20
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