概述
规格参数
数据手册IN74HC165N 概述
Logic Circuit 其他逻辑集成电路
IN74HC165N 规格参数
| 生命周期： | Contact Manufacturer | 包装说明： | , |
| Reach Compliance Code： | unknown | 风险等级： | 5.7 |
| Base Number Matches： | 1 |
IN74HC165N 数据手册
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PDF下载TECHNICAL DATA
IN74HC165
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The IN74HC165 is identical in pinout to the LS/ALS165. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the
rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
ORDERING INFORMATION
IN74HC165N Plastic
IN74HC165D SOIC
TA = -55° to 125° C for all packages
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Clock
Internal Stages
Output
QH
Operation
Serial Shift/
Parallel Load
Clock SA A-H
Inhibit
QA
QB-QG
L
H
H
H
X
L
L
X
L
a...h
X
a
b-g
h
Asynchronous Parallel Load
Serial Shift via Clock
L
H
QAn-QFn
QAn-QFn
QGn
QGn
H
X
H
H
L
L
L
X
X
L
QAn-QFn
QAn-QFn
QGn
QGn
Serial Shift via Clock
Inhibit
H
H
H
H
X
H
L
H
X
L
X
X
X
X
X
X
no change
Inhibited Clock
H
no change
No Clock
X = Don’t Care
QAn-QFn = Data shifted from the preceding stage
228
IN74HC165
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
VIN, VOUT
TA
VCC
+125
V
-55
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
0
0
0
1000
500
400
V
V
CC =4.5 V
CC =6.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
229
IN74HC165
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85
°C
≤125
°C
-55°C
Minimum High-Level VOUT=0.1 V or VCC-0.1 V
Input Voltage
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
IOUT ≤ 20 µA
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-Level VIN=VIH or VIL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Output Voltage
IOUT ≤ 20 µA
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-Level VIN= VIL or VIH
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Output Voltage
IOUT ≤ 20 µA
VIN= VIL or VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
8.0
80
160
230
IN74HC165
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
fmax
Parameter
Unit
MHz
ns
25 °C
to
≤85°C ≤125°C
-55°C
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
tPLH, tPHL Maximum Propagation Delay, Clock (or Clock
Inhibit) to QH or QH (Figures 1 and 8)
2.0
4.5
6.0
150
30
190
38
225
45
26
33
38
tPLH, tPHL Maximum Propagation Delay ,
SerialShift./.Parallel Load to QH or QH
(Figures 2 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH, tPHL Maximum Propagation Delay, Input H to QH or
QH (Figures 3 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
85
pF
PD=CPDVCC2f+ICCVCC
231
IN74HC165
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tSU
Parameter
V
Unit
ns
25 °C to
-55°C
≤85°C
≤125°C
Minimum Setup Time, Parallel
Data Inputs to Serial
Shift/Parallel Load (Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
tSU
tSU
tSU
th
Minimum Setup Time, Input
SA to Clock (or Clock Inhibit)
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Minimum Setup Time, Serial
Shift/Parallel Load to Clock
(or Clock Inhibit) (Figure 6)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
Minimum Setup Time, Clock
to Clock Inhibit (Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
Minimum Hold Time, Serial
Shift/Parallel Load to Parallel
Data Inputs (Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
th
Minimum Hold Time, Clock
(or Clock Inhibit) to Input SA
(Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
th
Minimum Hold Time, Clock
(or Clock Inhibit) to Serial
Shift/Parallel Load (Figure 6)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
trec
Minimum Recovery Time,
Clock to Clock Inhibit
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
tw
Minimum Pulse Width, Clock
(or Clock Inhibit) (Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tw
Minimum Pulse Width, Serial
Shift/Parallel Load (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
232
IN74HC165
SWITCHING WAVEFORMS
233
IN74HC165
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
234
IN74HC165N 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| IN74HC166 | INTEGRAL | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC166A | IKSEMICON | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC166AD | IKSEMICON | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC166AN | IKSEMICON | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC166D | INTEGRAL | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC166N | INTEGRAL | 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC174A | INTEGRAL | Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC174A | IKSEMICON | Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC174AD | INTEGRAL | Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS | 获取价格 |
|
| IN74HC174AN | INTEGRAL | Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS | 获取价格 |
|
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