IN74LV164D [INTEGRAL]

8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER; 8位串行输入/并行输出移位寄存器


型号：	IN74LV164D
厂家：	INTEGRAL CORP.
描述：	8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER 8位串行输入/并行输出移位寄存器移位寄存器
文件：	总6页 (文件大小：49K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TECHNICAL DATA

IN74LV164

8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER

The IN74LV164 is a low-voltage Si-gate CMOS device and is pin

and function compatible with the IN74HC/HCT164.

N SUFFIX

PLASTIC DIP

The IN74LV164 is an 8-bit edge-triggered shift register with serial

data entry and an output from each of the eight stages. Data is entered

serially through one of two inputs (DSA or DSB); either input can be

used as an active HIGH enable for data entry through the other input.

Both inputs must be connected together or an unused input must be tied

HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition

of the clock (CP) input and enters into Q₀, which is the logical AND of

the two data inputs (DSA, DSB ) that existed one set-up time prior to the

rising clock edge.

D SUFFIX

ORDERING INFORMATION

IN74LV164N

IN74LV164D

IZ74LV164

Plastic DIP

SOIC

chip

A LOW on the master reset (MR) input overrides all other inputs

and clears the register asynchronously, forcing all outputs LOW.

T_A= -40° to 125° C for all packages

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 1.2 to 5.5 V

Low Input Current: 1.0 mA, 0.1 mÀ at Ò = 25 °Ñ

Output Current: 6 mA at V_CC= 3.0 V; 12 mA at V_CC= 4.5 V

High Noise Immunity Characteristic of CMOS Devices

PIN ASSIGNMENT

DSA

DSB

14 V_CC

13 Q7

12 Q6

LOGIC DIAGRAM

10 Q4

SERIAL

DATA

INPUTS DSB

DSA

DATA

GND

PARALLEL

DATA

OUTPUTS

FUNCTION TABLE

Inputs

Outputs

DSA DSB Q0 Q1 ... Q7

L … L

Q0 ... Q6

PIN 14=V_CC

PIN 7 = GND

H = high voltage level

L = low voltage level

X = don’t care

INTEGRAL

IN74LV164

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to + 7.0

±20

Unit

V_CC

DC supply voltage

I_IK

DC Input diode current

DC Output diode current

I_OK

±50

I_O*³

DC Output source or sink current

V_CCcurrent

±25

I_CC

±50

I_GND

P_D

GND current

±50

Power dissipation per package: *⁴

Plastic DIP

750

500

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO

Package) from Case for 4 Seconds

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

*¹V < -0.5 V or V > V_CC+ 0.5 V.

*²V_O< -0.5 V or V_O> V_CC+ 0.5 V.

*³-0.5 V < V_O< V_CC+ 0.5 V.

*⁴Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SO Package: : - 8 mW/°C from 70° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

1.2

Max

5.5

Unit

V_CC

DC Supply Voltage

Input Voltage

V_CC

V_O

T_A

Output Voltage

V_CC

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

-40

+125

°C

t_r, t_f

1.0 V £ V_CC< 2.0 V

2.0 V £ V_CC< 2.7 V

2.7 V £ V_CC< 3.6 V

3.6 V £ V_CC£ 5.5 V

500

200

100

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages

to this high-impedance circuit. For proper operation, V and V_OUTshould be constrained to the range GND£(V or

V_OUT)£V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused

outputs must be left open.

INTEGRAL

IN74LV164

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Test

V_CC

Guaranteed Limit

Symbol

Parameter

conditions

25°C to -40°C

85°C

125°C

Unit

min

max min max

min

max

HIGH level input

voltage

1.2

2.0

2.7

3.0

3.6

4.5

5.5

0.9

1.4

2.0

0.9

1.4

2.0

0.9

1.4

2.0

3.15

3.85

3.15

3.85

3.15

3.85

LOW level input

voltage

1.2

2.0

2.7

3.0

3.6

4.5

5.5

0.3

0.6

0.8

0.3

0.6

0.8

0.3

0.6

0.8

1.35

1.65

1.35

1.65

1.35

1.65

V_OH

HIGH level output V = V or V

voltage

1.2

2.0

2.7

3.0

3.6

4.5

5.5

1.05

1.85

2.55

2.85

3.45

4.35

5.35

1.0

1.8

2.5

2.8

3.4

4.3

5.3

1.0

1.8

2.5

2.8

3.4

4.3

5.3

I_O= -100 mÀ

V = V or V

3.0

2.48

2.40

2.20

I_O= -6.0 mÀ

V = V or V

4.5

3.70

3.60

3.50

I_O= -12.0 mÀ

LOW level output V = V or V

V_OL

1.2

2.0

2.7

3.0

3.6

4.5

5.5

0.15

0.2

voltage

I_O= 100 mÀ

V = V or V

3.0

0.33

0.4

0.5

I_O= 6.0 mÀ

V = V or V

4.5

0.40

0.55

0.65

I_O= 12.0 mÀ

I_I

Input current

V = V_CCor 0 V

5.5

±0.1

±1.0

mÀ

I_CC

Supply current

V =V_CCor 0 V

8.0

160

I_O= 0 mÀ

I_CC1

Supply current

V =V_CC– 0.6 V

2.7

3.6

0.2

0.5

0.85

mÀ

INTEGRAL

IN74LV164

AC ELECTRICAL CHARACTERISTICS (C_L=50 pF, t_r=t_f= 2.5 ns, R_L= 1 kW)

Test

V_CC

Guaranteed Limit

25°C to -40°C 85°C

max min max min

Symbol

Parameter

conditions

125°C

Unit

min

max

t_PHL,t_PLHPropagation delay , CP to V = 0 V or V

1.2

2.0

2.7

3.0

4.5

150

180

210

Figure 1 and 4

t_PHL

Propagation delay , MR to V = 0 V or V

1.2

2.0

2.7

3.0

4.5

150

180

210

Figure 1 and 4

t_w

Pulse Width, CP or MR

V = 0 V or V

1.2

2.0

2.7

3.0

4.5

100

130

160

Figure 1

t_su

Setup Time, DSA or DSB V = 0 V or V

1.2

2.0

2.7

3.0

4.5

100

to CP

Figure 3

t_h

Hold Time, DSA or DSB to V = 0 V or V

1.2

2.0

2.7

3.0

4.5

Figure 3

t_rec

Recovery Time, MR to CP V = 0 V or V

1.2

2.0

2.7

3.0

4.5

100

130

Figure 2

f_max

Clock Frequency

Input capacitance

V = 0 V or V

Figure 1 and 4

1.2

2.0

2.7

3.0

4.5

MHz

C_I

5.0

5.5

7.0

C_PD

Power dissipation

capacitance

V = 0 V or V_CC

INTEGRAL

IN74LV164

t_w

(2)

V₁

(2)

(1)

V₁

V_M

90%

(1 )

V_M

GND

10%

GND

t_PHL

t _w

V_OH

V_OL

( 1)

V_M

1/f

max

t_PLH

t_PHL

V_OH

t _rec

(1 )

V_M

(2)

V₁

V_OL

(1)

V_M

GND

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

TEST POINT

VALID

(2)

(1 )

OUTPUT

V_M

DEVICE

UNDER

TEST

DSA or DSB

GND

(2)

( 1)

V_M

GND

* Includes all probe and jig capacitance

Figure 3. Switching Waveforms

(1)

Figure 4. Test Circuit

Note:

V_M= 1.5 V at V_CC= 2.7 V

V_M= 0.5 ×V_CCat V_CC=1.2 V, 2.0 V, 3.0 V, 4.5 V

(2)

V = V_CCat V_CC=1.2 V, 2.0 V, 2.7 V, 4.5 V

V = 2.7 V at V_CC= 3.0 V

TIMING DIAGRAM

DSA

DSB

INTEGRAL

IN74LV164

CHIP PAD DIAGRAM

Chip marking

(0,0)

LV164

1.71 + 0.03

Location of marking (mm): left lower corner x= 0.960, y= 0.130.

Chip thickness: 0.46 ± 0.02 (0.35 ± 0.02) mm.

PAD LOCATION

Location (left lower corner), mm

Pad No

Symbol

Pad size, mm

1.172

1.486

0.978

0.440

0.127

0.635

DSA

DSB

0.131

0.100 õ 0.100

0.131

0.363

0.531

0.689

0.885

0.653

0.485

0.326

0.131

GND

V_CC

Note: Pad location is given as per passivation layer

INTEGRAL

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