IN74LV244DW [INTEGRAL]
OCTAL BUFFER/LINE DRIVER 3-STATE; 八路缓冲器/线路驱动器3 -STATE
| 型号： | IN74LV244DW |
| 厂家： | 
INTEGRAL CORP. |
| 描述： | OCTAL BUFFER/LINE DRIVER 3-STATE |
| 文件： | 总4页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IN74LV244
OCTAL BUFFER/LINE DRIVER 3-STATE
The IN74LV244 is a low-voltage Si-gate CMOS device and is pin and function compatible with
IN74HC/HCT244.
The IN74LV244 is an octal non-inverting buffer/line
driver with 3-state outputs. The 3-state outputs are controlled
N SUFFIX
PLASTIC DIP
by the output enable inputs
and
. A HIGH on
2OE nOE
1OE
causes the outputs to assume a high impedance OFF-state.
The IN74LV244 is identical to the IN74LV240 but has non-
inverting outputs.
20
1
DW SUFFIX
SO
20
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 1.2 to 3.6 V
1
• Low Input Current: 1.0 µA, 0.1 µА at Т = 25 °С
• Output Current: 8 mA at VCC = 3.0 V
ORDERING INFORMATION
• High Noise Immunity Characteristic of CMOS Devices
IN74LV244N Plastic DIP
IN74LV244DW
IZ74LV244
SOIC
chip
TA = -40° to 125° C for all
packages
LOGIC DIAGRAM
2
18
16
14
12
9
PIN ASSIGNMENT
1Y
1Y
1A
1A
0
1
0
1
1OE
1A0
2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0
GND
1
20
19
18
17
VCC
2OE
1Y0
2A3
4
2
6
1Y
1A
1A
2A
2A
2
2
3
3
8
1Y
4
3
NONINVERTING
OUTPUTS
DATA
INPUTS
5
16 1Y1
15 2A2
11
13
15
17
2Y
0
0
1
6
7
2Y
1
7
14 1Y2
13 2A1
12 1Y3
5
2Y
2Y
2A
2A
0
1
0
1
8
3
9
10
11
2A0
1
1OE
2OE
OUTPUT
19
ENABLES
FUNCTION TABLE
Input
OUTPUT
nOE
L
nAn
L
nYn
L
PIN 20=VCC
PIN 10 = GND
L
H
H
Z
H
X
H= high level
L = low level
X = don’t care
Z = high impedance
1
IN74LV244
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +5.0
±20
Unit
V
VCC
DC supply voltage
DC Input diode current
DC Output diode current
IIK *1
mA
mA
mA
mA
mA
mW
2
IOK
*
±50
IO *3
ICC
IGND
PD
DC Output source or sink current
DC VCC current
±35
±70
DC GND current
±70
4
Power
Plastic
SO
dissipation
per
package:
*
DIP
750
500
Tstg
TL
Storage Temperature
-65 to +150
°C
°C
Lead Temperature, 1.5 mm (Plastic DIP
Package), 0.3 mm (SO Package) from Case for
4 Seconds
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*1 VI < -0.5 V or VI > VCC + 0.5 V.
*2 VO < -0.5 V or VO > VCC + 0.5 V.
*3 -0.5 V < VO < VCC + 0.5 V.
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: : - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Min
1.2
0
Max
3.6
Unit
DC Supply Voltage
Input Voltage
V
V
VCC
VO
TA
Output Voltage
0
VCC
+125
1000
700
500
400
V
°C
ns
Operating Temperature, All Package Types
-40
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =1.2 V
0
0
0
0
VCC =2.0 V
VCC =3.0 V
VCC =3.6 V
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
V
OUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74LV244
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Test
VCC
V
Guaranteed Limit
-40°C to
Symbo
l
Parameter
conditions
Unit
25°C
125°C
85°C
min max min max min max
VIH
HIGH level input
voltage
1.2 0.9
2.0 1.4
3.0 2.1
3.6 2.5
1.2
2.0
3.0
3.6
-
0.9
1.4
2.1
2.5
-
-
0.9
1.4
2.1
2.5
-
-
V
-
-
-
-
-
-
-
-
-
VIL
LOW level input
voltage
-
-
-
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
-
0.3
0.6
0.9
1.1
-
V
V
-
-
-
-
-
-
VOH HIGH
level VI = VIH or VIL 1.2 1.1
1.0
1.9
2.9
3.5
2.34
1.0
1.9
2.9
3.5
2.20
output voltage
2.0 1.92
3.0 2.92
3.6 3.52
-
-
-
IO = -50 µА
-
-
-
-
-
-
VI = VIH or VIL 3.0 2.48
-
-
-
V
V
IO = -8 mА
VOL
LOW
level VI = VIH or VIL 1.2
-
-
-
-
-
0.09
0.09
0.09
0.09
0.33
-
-
-
-
-
0.1
0.1
0.1
0.1
0.4
-
-
-
-
-
0.1
0.1
0.1
0.1
0.5
output voltage
2.0
3.0
3.6
IO = 50 µА
VI = VIH or VIL 3.0
V
IO = 8 mА
II
IOZ
Input current
Three
VI = VCC or 0 V
*
1.2
*
-
-
-
-
-
-
±0.1
±0.5
±1.0
±5
±1.0
±10
µА
µА
state 3-state
leakage current outputs
VI (01,19) =
VIH
VO =VCC or 0 V
ICC
Supply current VI =VCC or 0 V
IO = 0 µА
*
-
8.0
-
80
-
160
µА
* VCC = 3.3 ± 0.3 V
3
IN74LV244
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=6.0 ns)
Test
VCC
V
Guaranteed Limit
-40°C to
Symbol
Parameter
conditions
Unit
25°C
125°C
85°C
min ma min max min max
x
tPHL, tPLH Propagation delay , VI = 0 V or 1.2
1An to 1Yn, 2An to VCC Figure 1 2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
24
-
-
-
-
-
-
125
30
-
-
-
-
-
-
150
36
ns
ns
2Yn
and 3
*
15
19
23
tPHZ tPLZ Propagation
delay, VI = 0 V or 1.2
VCC Figure 2 2.0
140
30
175
35
210
41
to 1Yn,
to
1OE
2OE
and 4
*
20
24
28
2Yn
tPZH tPZL Propagation
delay, VI = 0 V or 1.2
140
-
-
-
175
-
-
-
210
ns
ns
VCC Figure 2 2.0
to
32
40
48
to 1Yn,
1OE
2Yn
2OE
and 4
*
20
25
30
tTHL, tTLH Output
Transition VI = 0 V or 1.2
60
16
10
7.0
50
-
-
-
-
-
75
20
13
7.0
-
-
-
-
-
-
90
24
15
7.0
-
Time, Any Output
VCC Figure 1 2.0
and 3
*
3.0
CI
CPD
Input capacitance
pF
pF
Power
dissipation VI = 0 V or
capacitance (per one VCC
channel)
* VCC = 3.3 ± 0.3 V
VCC
t
t
f
50%
r
1OE or 2OE
GND
VCC
90%
50%
1An or 2An
1Yn or 2Yn
tPZL
tPLZ
10%
GND
VCC
VOL
tPLH
tPHL
50%
50%
1Yn or 2Yn
1Yn or 2Yn
90%
tPHZ
tPZH
50%
10%
VOH
GND
tTLH
tTHL
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
TEST POINT
TEST POINT
Connect to V when
CC
1 k
DEVICE
UNDER
TEST
OUTPUT
testing t
and t
OUTPUT
PLZ
PZL
DEVICE
UNDER
TEST
Connect to GND when
*
L
testing t and t
*
L
PHZ
PZH
C
C
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
4
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