IN74LV273 [INTEGRAL]

Octal D Flip-Flop with Common Clock and Reset; 八路D触发器与普通时钟和复位


型号：	IN74LV273
厂家：	INTEGRAL CORP.
描述：	Octal D Flip-Flop with Common Clock and Reset 八路D触发器与普通时钟和复位触发器时钟
文件：	总7页 (文件大小：135K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TECHNICAL DATA

IN74LV273

Octal D Flip-Flop with Common Clock and Reset

The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and

function compatible with the 74HC/HCT273.

The IN74LV273 has eight edge-triggered, D-type flip-flops with

individual D inputs and Q outputs. The common clock (CP) and master

reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The

N SUFFIX

PLASTIC DIP

state of each D input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding output (Qn) of the flip-

DW SUFFIX

flop. All outputs will be forced LOW independently of clock or data

inputs by a LOW voltage level on the MR input. The device is useful for

applications where the true output only is required and the clock and

master reset are common to all storage elements.

Output voltage levels are compatible with input levels of CMOS,

NMOS and TTL IC_S

Supply voltage range: 1.2 to 5.5 V

Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ

High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

IN74LV273N

IN74LV273DW

IZ74LV273

Plastic DIP

SOIC

chip

T_A= -40° to 125° C for all packages

PIN ASSIGNMENT

RESET

LOGIC DIAGRAM

18 D7

17 D6

16 Q6

15 Q5

14 D5

13 D4

12 Q4

11 CLOCK

GND

FUNCTION TABLE

Inputs

Clock

Output

Reset

no change

PIN 20=V_CC

PIN 10 = GND

H= high level

L = low level

X = don’t care

Z = high impedance

INTEGRAL

IN74LV273

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to +7.0

±20

Unit

V_CC

DC supply voltage

Input diode current

Output diode current

I_IK

I_OK

±50

I_O*³

Output source or sink current

V_CCcurrent

±25

I_CC

±50

I_GND

P_D

GND current

±50

Power dissipation per package:

Plastic DIP *⁴

750

500

SO *⁴

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO

Package) from Case for 4 Seconds

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

V < -0.5 V or V > V_CC+ 0.5 V.

I I

V_O< -0.5 V or V_O> V_CC+ 0.5 V.

*³-0.5 V < V_O< V_CC+ 0.5 V.

*⁴Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SO Package: - 8 mW/°C from 70° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

1.2

Max

5.5

Unit

V_CC

DC Supply Voltage

DC Input Voltage

DC Output Voltage

V_CC

V_O

T_A

V_CC

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

-40

+125

°C

0 V £ V_CC£ 2.0 V

2.0 V £ V_CC£ 2.7 V

2.7 V £ V_CC£ 3.6 V

t_r, t_f

500

200

100

3.6 V £ V_CC£ 5.5 V

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages

to this high-impedance circuit. For proper operation, V and V_OUTshould be constrained to the range GND£(V or

V_OUT)£V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused

outputs must be left open.

INTEGRAL

IN74LV273

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Test

V_CC

Guaranteed Limit

-40°C 85°C

max min max

Symbol Parameter

conditions

25°C

min

125°C

Unit

min

max min max

HIGH level

input

voltage

1.2

2.0

2.7

3.0

3.6

4.5

5.5

0.9

1.4

2.0

0.9

1.4

2.0

0.9

1.4

2.0

0.9

1.4

2.0

3.15

3.85

3.15

3.85

3.15

3.85

3.15

3.85

LOW level

output

voltage

1.2

2.0

2.7

3.0

3.6

4.5

5.5

0.3

0.6

0.8

0.3

0.6

0.8

0.3

0.6

0.8

0.3

0.6

0.8

1.35

1.65

1.35

1.65

1.35

1.65

1.35

1.65

V_OH

HIGH level V = V or V

output

voltage

1.2

2.0

2.7

3.0

3.6

4.5

5.5

1.05

1.85

2.55

2.85

3.45

4.35

5.35

1.05

1.85

2.55

2.85

3.45

4.35

5.35

1.0

1.8

2.5

2.8

3.4

4.3

5.3

1.0

1.8

2.5

2.8

3.4

4.3

5.3

I_O= -100 mÀ

V = V or V

3.0

2.48

2.40

2.20

I_O= -6 mÀ

V = V or V

4.5

3.70

3.60

3.50

I_O= -12 mÀ

LOW level V = V or V

V_OL

1.2

2.0

2.7

3.0

3.6

4.5

5.5

0.15

0.2

output

voltage

I_O= 100 mÀ

V = V or V

3.0

4.5

5.5

0.33

0.40

±0.1

8.0

0.33

0.40

±0.1

8.0

0.40

0.55

±1.0

0.50

I_O= 6 mÀ

V = V or V

0.65

I_O= 12 mÀ

I_I

Input

current

V = V_CCor 0 V

±1.0 mÀ

160 mÀ

0.85 mA

I_CC

I_CC1

Supply

current

V =V_CCor 0 V

I_O= 0 mÀ

Additional V = V_CC– 0.6V 2.7

0.2

0.5

supply

3.6

current per

input

INTEGRAL

IN74LV273

AC ELECTRICAL CHARACTERISTICS (C_L=50 pF, t_r=t_f=2.5 ns)

Test

V_CC

Guaranteed Limit

Symbol

Parameter

conditions

-40°C to

25°C

85°C

125°C

max

Unit

min max

min

max min

t_PHL,t_PLHPropagation delay , Clock V = 0 V or V

1.2

2.0

2.7

3.0

4.5

150

to Q

Figures 1,4

t_PHL

Propagation delay , Reset V = 0 V or V

1.2

2.0

2.7

3.0

4.5

160

to Q

Figures 2,4

C_I

Input capacitance

5.0

5.5

6.0*

40*

C_PD

Power dissipation

V = 0 V or V_CC

capacitance (per flip-flop)

* T = 25^oC

TIMING REQUIREMENTS(C_L=50 pF, t_r=t_f=2.5 ns)

Test

V_CC

Guaranteed Limit

Symbol

Parameter

conditions

-40°C to

25°C

85°C

125°C

Unit

min max

min

max min

max

Pulse Width, Clock (low or

high), Reset (low)

t_w

V = 0 V or V

Figures 1,2,4

1.2

2.0

2.7

3.0

4.5

Setup Time, Data to Clock

t_su

t_rem

t_h

V = 0 V or V

Figures 3,4

1.2

2.0

2.7

3.0

4.5

Removal Time, Reset to

Clock

V = 0 V or V

1.2

2.0

2.7

3.0

4.5

Figures 2,4

Hold Time, Clock to Data

V = 0 V or V

1.2

2.0

2.7

3.0

4.5

Figures 3,4

INTEGRAL

IN74LV273

Clock Frequency

f_c

V = 0 V or V

Figures 1,4

1.2

2.0

2.7

3.0

4.5

MHz

V_OLand V_OHare the typical output voltage drop that occur with the output load.

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

INTEGRAL

IN74LV273

Figure 3. Switching Waveforms

Level of a signal, V

Symbol

1,2

0,6

2,0

1,0

2,7

1,5

3,0

2,7

1,5

4,5

V_CC

2,25

V_M

TEST POINT

DEVICE

OUTPUT

UNDER

TEST

* Includes all probe and jig capacitance

Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

INTEGRAL

IN74LV273

CHIP PAD DIAGRAM

Chip marking

25LV273

(0,0)

1.48 + 0.03

Location of marking (mm): left lower corner x=0.119, y=0.082.

Chip thickness: 0.46 ± 0.02 mm, (0.35 ± 0.02 mm – for SOIC).

PAD LOCATION

Location (left lower corner), mm

Pad No

Symbol

Pad size, mm

0.1415

0.1375

0.4535

0.6245

0.7800

0.9520

1.2685

1.2480

1.2650

1.2425

1.2465

0.9520

0.7800

0.6245

0.4535

0.1160

0.1440

0.1190

Reset

Q 0

D 0

D 1

Q 1

Q 2

D 2

D 3

Q 3

GND

Clock

Q 4

D 4

D 5

Q 5

Q 6

D 6

D 7

Q 7

V_CC

0.6270

0.3880

0.1515

0.1190

0.1180

0.1185

0.2960

0.5160

0.8430

1.0820

1.3165

1.3120

1.3110

1.3115

1.1350

0.9140

0.100 x0.100

Note: Pad location is given as per passivation layer.

INTEGRAL

相关型号：