IZ74LV08 [INTEGRAL]
Quad 2-Input AND Gate; 四2输入与门
| 型号： | IZ74LV08 |
| 厂家： | 
INTEGRAL CORP. |
| 描述： | Quad 2-Input AND Gate |
| 文件： | 总5页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
IN74LV08
Quad 2-Input AND Gate
The IN74LV08 is low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT08A.
The IN74LV08 provides the 2-input AND function.
·
·
·
Optimized for Low Voltage applications: 1.2 to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Low Input Current
ORDERING INFORMATION
IN74LV08N
IN74LV08D
IZ74LV08
Plastic
SOIC
Chip
TA = -40° ? 125°C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
A1
Y1
B1
A2
Y2
B2
A3
Y3
B3
A4
FUNCTION TABLE
Y4
Input
Output
B4
A
L
B
L
Y = A*B
L
L
L
H
L
H
L
PIN 14 =VCC
PIN 7 = GND
H
H
H
H - high level
L - low level
INTEGRAL
1
IN74LV08
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC supply voltage (Referenced to GND)
DC input diode current
-0.5 ¸ +5.0
±20
V
1
IIK
*
mA
mA
mA
2
IOK
*
DC output diode current
±50
IO *3
ICC
IGND
PD
DC output source or sink current
-bus driver outputs
±25
DC VCC current for types with
- bus driver outputs
±50
±50
mA
mA
mW
DC GND current for types with
- bus driver outputs
Power dissipation per package, plastic DIP+
SOIC package+
750
500
Tstg
TL
Storage temperature
-65 ¸ +150
°C
°C
Lead temperature, 1.5 mm from Case for 10 seconds
(Plastic DIP ), 0.3 mm (SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SOIC Package: : - 8 mW/°C from 70° to 125°C
*1: V < -0.5V or V > VCC+0.5V
I
I
*2: Vo < -0.5V or Vo > VCC+0.5V
*3: -0.5V < Vo < VCC+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
1.2
0
Max
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
3.6
VCC
V , VOUT
IN
V
TA
-40
+125
°C
ns
tr, tf
Input Rise and Fall Time
VCC =1.2 V
VCC =2.0 V
VCC =3.0 V
VCC =3.6 V
0
0
0
0
1000
700
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range GND£(V or
IN
IN
VOUT)£VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
INTEGRAL
2
IN74LV08
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
Guaranteed Limit
Unit
VCC,
V
25°C
-40°C ¸ 85°C
-40°C ¸
125°C
min max min max min max
V
High-Level Input
Voltage
1.2
2.0
3.0
3.6
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
0.9
1.4
2.1
2.5
-
-
-
-
V
V
V
IH
V
IL
Low -Level Input
Voltage
1.2
2.0
3.0
3.6
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.3
0.6
0.9
1.1
VOH
High-Level Output V = V or V
IH
Voltage
1.2
2.0
3.0
3.6
1.1
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
I
IL
IO = -50 mÀ
1.92
2.92
3.52
V = V or V
IH
3.0
2.48
-
2.34
-
2.20
-
V
V
I
IL
IO = -6.0 mÀ
Low-Level Output V = V or V
IH
VOL
1.2
2.0
3.0
3.6
-
-
-
-
0.09
0.09
0.09
0.09
-
-
-
-
0.1
0.1
0.1
0.1
-
-
-
-
0.1
0.1
0.1
0.1
I
IL
Voltage
IO = 50 mÀ
V = V or V
IH
IO = 6.0 mÀ
3.0
3.6
3.6
3.6
-
-
-
-
0.33
-0.1
0.1
-
-
-
-
0.4
-1.0
1.0
20
-
-
-
-
0.5
-1.0
1.0
40
V
I
IL
mA
IIL
IIÍ
Low-Level Input V = 0 V
I
Leakage Current
mA
mA
High-Level Input V = VCC
I
Leakage Current
IÑÑ
Quiescent Supply V = 0 Â or VCC
2.0
I
Current
(per Package)
IO = 0 mÀ
INTEGRAL
3
IN74LV08
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns, V =0V, V =VCC, RL=1k? )
IL
IH
Symbol
Parameter
Guaranteed Limit
Unit
VCC
V
25°C
-40°C ? 85°C
-40°C ? 125°C
min
max
min
max
min
max
tTHL, (tTLH
)
)
Output Transition
Time, Any Output
(Figure 1)
1.2
2.0
*
-
-
60
16
10
-
-
-
75
20
13
-
-
-
90
24
15
ns
tPHL, (tPLH
Propagation Delay,
Input A to Output Y
(Figure 1)
1.2
2.0
*
-
-
-
135
23
14
-
-
-
405
28
18
-
-
-
405
34
21
CI
Input Capacitance
3.0
-
7.0
-
-
-
-
pF
pF
CPD
Power Dissipation Capacitance (Per Gate)
ÒÀ=25°Ñ, V =0V?V
I CC
44
* - VCC= (3.3±0.3) V
Used to determine the no-load dynamic power consumption:
PD = CPDVCC2fI+ ?(CLVCC2fo), fI-input frequency, fo- output frequency (MHz)
?(CLVCC2fo) – sum of the outputs
tHL
tLH
VCC
0.9
0.9
V1
V1
Input À, B
0.1
0.1
GND
tPLH
tPHL
VOH
VOL
0.9
0.9
V1
Output Y
V1
0.1
0.1
tTHL
tTLH
V1 = 0.5 VCC
Figure 1. Switching Waveforms
VCC
VI
VO
DEVICE
UNDER
TEST
PULSE
GENERATOR
Termination resistance RT -
should be equal to ZOUT pulse
generators
RT
RL
CL
Figure 2. Test Circuit
INTEGRAL
4
IN74LV08
CHIP PAD DIAG RAM IZ74LV08
Chip marking
25LV08
(x=1.009; y=0.727)
10
12 11
09
08
13
14
07
06
05
01
02
04
03
1.23
±0.03
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)
Thickness of chip 0.46 ± 0,02 mm
PAD LOCATION
Pad No
Symbol
X
Y
01
02
03
04
05
06
07
08
09
10
11
12
13
14
A1
B1
0.111
0.111
0.504
0.672
1.009
1.009
1.009
1.009
1.009
0.672
0.504
0.336
0.111
0.111
0.287
0.119
0.111
0.111
0.111
0.277
0.447
0.806
0.974
0.974
0.974
0.974
0.772
0.618
Y1
A2
B2
Y2
GND
Y3
A3
B3
Y4
A4
B4
Vcc
INTEGRAL
5
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