10M08SFE144C7G_技术文档

MAX 10 FPGA Device Datasheet

2015.05.04

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This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for MAX^®10 devices.

Table 1: MAX 10 Device Grades and Speed Grades Supported

Device Grade

Speed Grade Supported

Commercial

Industrial

•

–C7

–C8 (slowest)

•

–I6 (fastest)

–I7

Automotive

–A7

Note: The –I6 speed grade MAX 10 FPGA device option is not available by default in the Quartus^®II software. Contact your local Altera sales

representatives for support.

Related Information

Device Ordering Information, MAX 10 FPGA Device Overview

Provides more information about the densities and packages of devices in the MAX 10.

Electrical Characteristics

The following sections describe the operating conditions and power consumption of MAX 10 devices.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent

and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera

warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without

notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are

advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

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2

Operating Conditions

MAX 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the MAX 10

devices, you must consider the operating requirements described in this section.

Absolute Maximum Ratings

This section defines the maximum operating conditions for MAX 10 devices. The values are based on experiments conducted with the devices and

theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

Caution: Conditions outside the range listed in the absolute maximum ratings tables may cause permanent damage to the device. Additionally,

device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Single Supply Devices Absolute Maximum Ratings

Table 2: Absolute Maximum Ratings for MAX 10 Single Supply Devices—Preliminary

Symbol

Parameter

Min

Max

Unit

V_{CC_ONE}

Supply voltage for core and periphery through on-

die voltage regulator

–0.5

3.9

V

V_CCIO

V_CCA

Supply voltage for input and output buffers

–0.5

3.9

V

Supply voltage for phase-locked loop (PLL)

regulator and analog-to-digital converter (ADC)

block (analog)

Dual Supply Devices Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings for MAX 10 Dual Supply Devices—Preliminary

Symbol

Parameter

Min

–0.5

Max

1.63

3.9

Unit

V

V_CC

Supply voltage for core and periphery

Supply voltage for input and output buffers

Supply voltage for PLL regulator (analog)

Supply voltage for PLL regulator (digital)

V_CCIO

V_CCA

V

3.41

1.63

V

V_{CCD_PLL}

V

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Absolute Maximum Ratings

Symbol

Parameter

Min

–0.5

Max

3.41

1.63

Unit

V

V_{CCA_ADC}

V_CCINT

Supply voltage for ADC analog block

Supply voltage for ADC digital block

V

Absolute Maximum Ratings

Table 4: Absolute Maximum Ratings for MAX 10 Devices—Preliminary

Symbol

Parameter

Min

–0.5

–25

–65

–40

Max

4.12

25

Unit

V

V_I

DC input voltage

I_OUT

T_STG

T_J

DC output current per pin

Storage temperature

mA

°C

150

125

Operating junction temperature

°C

Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame

Table 5: Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame for MAX 10 Devices

Condition (V)

4.12

Overshoot Duration as % of High Time

Unit

%

100.0

11.7

7.1

4.17

%

4.22

%

4.27

4.3

%

4.32

2.6

%

4.37

1.6

%

4.42

1.0

%

4.47

0.6

%

4.52

0.3

%

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Recommended Operating Conditions

Condition (V)

Overshoot Duration as % of High Time

Unit

4.57

0.2

%

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for MAX 10 devices. The tables list the steady-state voltage values

expected from MAX 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.

Single Supply Devices Power Supplies Recommended Operating Conditions

Table 6: Power Supplies Recommended Operating Conditions for MAX 10 Single Supply Devices—Preliminary

Symbol

Parameter

Condition

Min

Typ

Max

Unit

(1)

V_{CC_ONE}

Supply voltage for core and periphery

through on-die voltage regulator

—

2.85/3.135

3.0/3.3

3.15/3.465

V

3.3 V

3.0 V

2.5 V

1.8 V

1.5 V

1.35 V

1.2 V

—

3.135

2.85

3.3

3

3.465

3.15

V

2.375

2.5

2.625

Supply voltage for input and output

buffers

(2)

V_CCIO

1.71

1.8

1.89

1.425

1.5

1.575

1.2825

1.14

1.35

1.2

1.4175

1.26

(1)

V_CCA

Supply voltage for PLL regulator and

ADC block (analog)

2.85/3.135

3.0/3.3

3.15/3.465

(1)

(2)

V_CCAmust be connected to V_{CC_ONE}through a filter.

V_CCIOfor all I/O banks must be powered up during user mode because V_CCIOI/O banks are used for the ADC and I/O functionalities.

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Dual Supply Devices Power Supplies Recommended Operating Conditions

Table 7: Power Supplies Recommended Operating Conditions for MAX 10 Dual Supply Devices—Preliminary

Symbol

Parameter

Condition

—

Min

1.15

Typ

1.2

3.3

3

Max

1.25

Unit

V

V_CC

Supply voltage for core and periphery

3.3 V

3.0 V

2.5 V

1.8 V

1.5 V

1.35 V

1.2 V

—

3.135

2.85

3.465

3.15

V

2.375

1.71

2.5

1.8

1.5

1.35

1.2

2.5

2.625

1.89

V

Supply voltage for input and output

buffers

(3)

V_CCIO

V

1.425

1.2825

1.14

1.575

1.4175

1.26

V

(4)

V_CCA

Supply voltage for PLL regulator

(analog)

2.375

2.625

V

(5)

V_{CCD_PLL}

Supply voltage for PLL regulator

(digital)

—

1.15

1.2

1.25

V

V_{CCA_ADC}

V_CCINT

Supply voltage for ADC analog block

Supply voltage for ADC digital block

—

2.375

1.15

2.5

1.2

2.625

1.25

V

Recommended Operating Conditions

Table 8: Recommended Operating Conditions for MAX 10 Devices—Preliminary

Symbol

Parameter

Condition

Min

Max

Unit

V_I

DC input voltage

—

–0.5

3.6

V

(3)

(4)

(5)

V_CCIOfor all I/O banks must be powered up during user mode because V_CCIOI/O banks are used for the ADC and I/O functionalities.

All V_CCApins must be powered to 2.5 V (even when PLLs are not used), and must be powered up and powered down at the same time.

V_{CCD_PLL}must always be connected to V_CCthrough a decoupling capacitor and ferrite bead.

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Programming/Erasure Specifications

Symbol

Parameter

Condition

—

Min

0

Max

V_CCIO

85

Unit

V

V_O

T_J

Output voltage for I/O pins

Commercial

Industrial

Automotive

Standard POR⁽⁶⁾

Fast POR ⁽⁷⁾

Instant-on

—

0

°C

—

Operating junction temperature

–40

200 μs

—

100

125

50 ms

3 ms

10

t_RAMP

Power supply ramp time

—

I_Diode

Magnitude of DC current across PCI clamp

diode when enabled

mA

Programming/Erasure Specifications

Table 9: Programming/Erasure Specifications for MAX 10 Devices—Preliminary

This table shows the programming cycles and data retention duration of the user flash memory (UFM) and configuration flash memory (CFM) blocks.

Erase and reprogram cycles (E/P) ⁽⁸⁾(Cycles/page)

Temperature (°C)

Data retention duration (Years)

10,000

85

20

10

100

DC Characteristics

I/O Pin Leakage Current

The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all V_CCIOsettings (3.3,

3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).

(6)

(7)

(8)

Each individual power supply should reach the recommended operating range within 50 ms.

Each individual power supply should reach the recommended operating range within 3 ms.

The number of E/P cycles applies to the smallest possible flash block that can be erased or programmed in each MAX 10 device. Each MAX 10 device

has multiple flash pages per device.

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Bus Hold Parameters

10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on.

Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is

enabled or disabled. This is applicable to all MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50

devices. The ADC I/O pins are in Bank 1A.

Table 10: I/O Pin Leakage Current for MAX 10 Devices—Preliminary

Symbol

Parameter

Input pin leakage current

Condition

V_I= 0 V to V_CCIOMAX

V_O= 0 V to V_CCIOMAX

Min

–10

Max

10

Unit

µA

I_I

I_OZ

Tristated I/O pin leakage current

10

µA

Bus Hold Parameters

Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option

to enable bus hold in user mode. Bus hold is always disabled in configuration mode.

Table 11: Bus Hold Parameters for MAX 10 Devices—Preliminary

V_CCIO(V)

Parameter

Condition

1.2

1.5

1.8

2.5

3

3.3

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Bus-hold low,

V_IN> V_IL

8

—

12

—

30

—

50

—

70

—

70

—

µA

V

sustaining current

(maximum)

Bus-hold high,

V_IN< V_IL

–8

—

125

–125

0.9

–12

—

–30

—

–50

—

300

–300

1.7

–70

—

500

–500

2

–70

—

500

–500

2

sustaining current

(minimum)

Bus-hold low,

0 V < V_IN

V_CCIO

<

175

200

overdrive current

Bus-hold high,

0 V < V_IN

V_CCIO

—

–175

—

–200

1.07

—

overdrive current

Bus-hold trip point

—

0.3

0.375 1.125 0.68

0.7

0.8

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Series OCT without Calibration Specifications

Table 12: Series OCT without Calibration Specifications for MAX 10 Devices—Preliminary

This table shows the variation of on-chip termination (OCT) without calibration across process, voltage, and temperature (PVT).

Resistance Tolerance

Description

V_CCIO(V)

Unit

–C7, –I6, –I7, –A7

–C8

30

35

40

50

60

3.00

2.50

1.80

1.50

1.35

1.20

35

40

45

%

Series OCT without calibration

Series OCT with Calibration at Device Power-Up Specifications

Table 13: Series OCT with Calibration at Device Power-Up Specifications for MAX 10 Devices—Preliminary

OCT calibration is automatically performed at device power-up for OCT enabled I/Os.

Description

V_CCIO(V)

Calibration Accuracy

Unit

3.00

12

%

2.50

1.80

Series OCT with calibration at device power-up

1.50

1.35

1.20

OCT Variation after Calibration at Device Power-Up

The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up.

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OCT Variation after Calibration at Device Power-Up

Use the following table and equation to determine the final OCT resistance considering the variations after calibration at device power-up.

Table 14: OCT Variation after Calibration at Device Power-Up for MAX 10 Devices—Preliminary

This table lists the change percentage of the OCT resistance with voltage and temperature.

Desccription

Nominal Voltage

dR/dT (%/°C)

0.25

dR/dV (%/mV)

–0.027

3.00

2.50

1.80

1.50

1.35

1.20

0.245

–0.04

0.242

–0.079

OCT variation after calibraiton at device power-up

0.235

–0.125

0.229

–0.16

0.197

–0.208

Figure 1: Equation for OCT Resistance after Calibration at Device Power-Up

For

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OCT Variation after Calibration at Device Power-Up

The definitions for equation are as follows:

•

T₁is the initial temperature.

T₂is the final temperature.

MF is multiplication factor.

R_initialis initial resistance.

R_finalis final resistance.

Subscript x refers to both V and T.

∆R_Vis variation of resistance with voltage.

∆R_Tis variation of resistance with temperature.

dR/dT is the change percentage of resistance with temperature after calibration at device power-up.

dR/dV is the change percentage of resistance with voltage after calibration at device power-up.

V₁is the initial voltage.

V₂is final voltage.

The following figure shows the example to calculate the change of 50 Ω I/O impedance from 25°C at 3.0 V to 85°C at 3.15 V.

Figure 2: Example for OCT Resistance Calculation after Calibration at Device Power-Up

B

1

B

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Pin Capacitance

Table 15: Pin Capacitance for MAX 10 Devices—Preliminary

Symbol

Parameter

Value

Unit

pF

C_IOB

Input capacitance on bottom I/O pins

8

7

8

C_IOLRT

C_LVDSB

Input capacitance on left/right/top I/O pins

pF

Input capacitance on bottom I/O pins with dedicated LVDS

pF

output ⁽⁹⁾

C_ADCL

Input capacitance on left I/O pins with ADC input ⁽¹⁰⁾

9

pF

C_VREFLRT

Input capacitance on left/right/top dual purpose V_REFpin when

used as V_REFor user I/O pin ⁽¹¹⁾

48

C_VREFB

Input capacitance on bottom dual purpose V_REFpin when used

as V_REFor user I/O pin

50

pF

C_CLKB

Input capacitance on bottom dual purpose clock input pins ⁽¹²⁾

7

6

pF

C_CLKLRT

Input capacitance on left/right/top dual purpose clock input

pins ⁽¹²⁾

Internal Weak Pull-Up Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.

(9)

(10)

(11)

Dedicated LVDS output buffer is only available at bottom I/O banks.

ADC pins are only available at left I/O banks.

When V_REFpin is used as regular input or output, F_maxperformance is reduced due to higher pin capacitance. Using the V_REFpin capacitance

specification from device datasheet, perform SI analysis on your board setup to determine the F_maxof your system.

10M40 and 10M50 devices have dual purpose clock input pins at top/bottom I/O banks.

(12)

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Internal Weak Pull-Up Resistor

Table 16: Internal Weak Pull-Up Resistor for MAX 10 Devices—Preliminary

Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO

.

Symbol

Parameter

Condition

V_CCIO= 3.3 V 5%

V_CCIO= 3.0 V 5%

V_CCIO= 2.5 V 5%

V_CCIO= 1.8 V 5%

V_CCIO= 1.5 V 5%

V_CCIO= 1.2 V 5%

Min

Typ

12

13

15

25

36

82

Max

18

Unit

kΩ

7

8

20

Value of I/O pin pull-up resistor before

and during configuration, as well as user

mode if the programmable pull-up

resistor option is enabled

10

16

20

33

25

R__PU

46

82

175

The internal weak pull-up resistor is defined in the following equation:

Figure 3: Internal Weak Pull-Up Resistor

Minimum condition: –40°C; V_CCIO= V_CC+ 5%; V_I= V_CC+ 5% – 50mV;

Typical condition: 25°C; V_CCIO= V_CC; V_I= 0 V;

Maximum condition: 125°C; V_CCIO= V_CC– 5%; V_I= 0 V;

where V_Irefers to the input voltage at the I/O pin.

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Hot-Socketing Specifications

Table 17: Hot-Socketing Specifications for MAX 10 Devices—Preliminary

Symbol

Parameter

Maximum

I_IOPIN(DC)

I_IOPIN(AC)

DC current per I/O pin

AC current per I/O pin

300 µA

8 mA ⁽¹³⁾

Hysteresis Specifications for Schmitt Trigger Input

MAX 10 devices support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved

noise immunity, especially for signal with slow edge rate.

Table 18: Hysteresis Specifications for Schmitt Trigger Input for MAX 10 Devices—Preliminary

Symbol

Parameter

Condition

Minimum

180

Unit

mV

V_CCIO= 3.3 V

V_CCIO= 2.5 V

V_CCIO= 1.8 V

V_CCIO= 1.5 V

150

V_HYS

Hysteresis for Schmitt trigger input

120

110

(13)

The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I_IOPIN| = C dv/dt, in which C is I/O pin capacitance and dv/dt is the slew rate.

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Hysteresis Specifications for Schmitt Trigger Input

Figure 4: LVTTL/LVCMOS Input Standard Voltage Diagram

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I/O Standards Specifications

Figure 5: Schmitt Trigger Input Standard Voltage Diagram

V_HYS

I/O Standards Specifications

Tables in this section list input voltage (V_IHand V_IL), output voltage (V_OHand V_OL), and current drive characteristics (I_OHand I_OL) for various

I/O standards supported by MAX 10 devices.

For minimum voltage values, use the minimum V_CCIOvalues. For maximum voltage values, use the maximum V_CCIOvalues.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

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Single-Ended I/O Standards Specifications

Table 19: Single-Ended I/O Standards Specifications for MAX 10 Devices—Preliminary

To meet the I_OLand I_OHspecifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4

mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the I_OLand I_OHspecifications in the datasheet.

V_CCIO(V)

V_IL(V)

V_IH(V)

V_OL(V)

Max

0.45

0.2

V_OH(V)

I/O Standard

I_OL(mA)

I_OH(mA)

Min

Typ

Max

3.465

Min

–0.3

Max

0.8

Min

1.7

Max

3.6

Min

3.3 V LVTTL

3.135

3.3

2.4

4

2

–4

–2

3.3 V LVCMOS

3.3

0.8

3.6

V_CCIO

0.2

–

3.0 V LVTTL

2.85

3

3.15

–0.3

0.8

1.7

V_CCIO

0.3

+

0.45

0.2

2.4

4

0.1

1

–4

–0.1

–1

–2

—

3.0 V LVCMOS

3

V_CCIO

0.3

V_CCIO

0.2

–

2.5 V LVTTL and

LVCMOS

2.375

1.71

2.5

1.8

1.5

1.2

3.3

2.5

1.8

1.5

2.625

1.89

0.7

V_CCIO

0.3

0.4

2

1.8 V LVTTL and

LVCMOS

0.35 ×

0.65 ×

V_CCIO

2.25

0.45

V_CCIO

0.45

–

2

V_CCIO

1.5 V LVCMOS

1.425

1.14

1.575

1.26

0.35 ×

V_CCIO

0.65 ×

V_CCIO

0.3

+

0.25 ×

V_CCIO

0.75 ×

V_CCIO

2

1.2 V LVCMOS

0.35 ×

V_CCIO

0.65 ×

V_CCIO

0.3

0.25 ×

V_CCIO

0.75 ×

V_CCIO

2

3.3 V Schmitt

Trigger

3.135

2.375

1.71

3.465

2.625

1.89

0.8

1.7

V_CCIO

0.3

—

2.5 V Schmitt

Trigger

0.7

1.7

V_CCIO

0.3

—

1.8 V Schmitt

Trigger

0.35 ×

V_CCIO

0.65 ×

V_CCIO

0.3

—

1.5 V Schmitt

Trigger

1.425

1.575

0.35 ×

V_CCIO

0.65 ×

V_CCIO

0.3

—

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Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

V_CCIO(V)

V_IL(V)

V_IH(V)

V_OL(V)

Max

V_OH(V)

Min

I/O Standard

I_OL(mA)

I_OH(mA)

Min

Typ

Max

Min

Max

Min

Max

3.0 V PCI

2.85

3

3.15

—

0.3 ×

0.5 ×

V_CCIO

0.3

+

0.1 ×

0.9 ×

1.5

–0.5

V_CCIO

Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 20: Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for MAX 10 Devices—Preliminary

(14)

V_CCIO(V)

Typ

V_REF(V)

Typ

V_TT(V)

I/O Standard

Min

Max

Min

Max

Min

Typ

Max

SSTL-2 Class I,

II

2.375

2.5

2.625

1.19

1.25

1.31

V_REF– 0.04

V_REF

V_REF+ 0.04

SSTL-18 Class

I, II

1.7

1.8

1.5

1.9

0.833

0.9

0.5 × V_CCIO

0.9

0.969

V_REF– 0.04

V_REF

0.5 × V_CCIO

0.9

V_REF+ 0.04

0.51 × V_CCIO

0.95

SSTL-15 Class

I, II

1.425

1.283

1.71

1.575

1.45

0.49 ×

V_CCIO

0.51 ×

V_CCIO

0.49 ×

V_CCIO

SSTL-135 Class

I, II

1.35

1.8

0.49 ×

V_CCIO

0.51 ×

V_CCIO

0.49 ×

V_CCIO

HSTL-18 Class

I, II

1.89

0.85

0.95

0.85

HSTL-15 Class

I, II

1.425

1.5

1.575

0.71

0.75

0.79

0.71

0.75

0.79

(15)

0.48 ×

0.5 × V_CCIO

0.52 ×

(15)

V_CCIO

HSTL-12 Class

I, II

1.14

1.2

1.26

—

0.5 × V_CCIO

—

0.47 ×

0.5 × V_CCIO0.53 × V_CCIO

(16) (16)

(16)

V_CCIO

(14)

(15)

(16)

V_TTof transmitting device must track V_REFof the receiving device.

Value shown refers to DC input reference voltage, V_REF(DC)

Value shown refers to AC input reference voltage, V_REF(AC)

.

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Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

V_CCIO(V)

(14)

V_REF(V)

Typ

V_TT(V)

Typ

I/O Standard

Min

Typ

Max

Min

Max

Min

Max

HSUL-12

1.14

1.2

1.3

0.49 ×

V_CCIO

0.5 × V_CCIO

0.51 ×

V_CCIO

—

Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

Table 21: Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for MAX 10 Devices—Preliminary

To meet the I_OLand I_OHspecifications, you must set the current strength settings accordingly. For example, to meet the SSTL-15 Class I specification (8

mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OLand I_OHspecifications in the datasheet.

V_IL(DC)(V)

V_IH(DC)(V)

V_IL(AC)(V)

V_IH(AC)(V)

V_OL(V)

V_OH(V)

I/O Standard

I_OL(mA)

I_OH(mA)

Min

Max

Min Max

Min

Max

Min Max

Max

Min

SSTL-2

Class I

—

V_REF

0.18

–

V_REF

+

—

V_REF

0.31

–

V_REF

+

—

V_TT

–

V_TT

+

8.1

–8.1

0.18

0.31

0.57

SSTL-2

Class II

V_REF

0.18

V_REF

0.18

V_REF

0.31

V_REF

0.31

V_TT

–

V_TT

+

16.4

6.7

13.4

8

–16.4

–6.7

–13.4

–8

0.76

SSTL-18

Class I

V_REF

0.25

V_REF

0.25

V_TT

–

V_TT+

0.125

0.475

SSTL-18

Class II

V_REF

–

V_REF

+

V_REF

0.25

V_REF

0.25

0.28

V_CCIO

0.28

–

0.125

SSTL-15

Class I

V_REF

0.1

–

V_REF

0.1

+

V_REF

0.2 ×

0.8 ×

0.175

V_CCIO

SSTL-15

Class II

V_REF

0.1

–

V_REF

0.1

+

V_REF

–

V_REF

+

0.2 ×

0.8 ×

16

—

–16

—

0.175

V_CCIO

SSTL-135

V_REF

0.09

V_REF

0.09

V_REF

0.16

–

V_REF

+

0.2 ×

0.8 ×

0.16

V_CCIO

HSTL-18

Class I

V_REF

0.1

V_REF

0.1

V_REF

0.2

–

V_REF

0.2

+

0.4

V_CCIO

0.4

–

8

–8

(14)

V_TTof transmitting device must track V_REFof the receiving device.

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Differential SSTL I/O Standards Specifications

V_IL(DC)(V)

V_IH(DC)(V)

Min Max

V_IL(AC)(V)

V_IH(AC)(V)

Min Max

V_OL(V)

Max

V_OH(V)

Min

I/O Standard

I_OL(mA)

I_OH(mA)

Min

Max

Min

Max

HSTL-18

Class II

—

V_REF

0.1

–

V_REF

0.1

+

—

V_REF

0.2

–

V_REF

0.2

+

—

0.4

V_CCIO

0.4

–

16

–16

HSTL-15

Class I

—

V_REF

0.1

V_REF

0.1

—

V_REF

0.2

V_REF

0.2

0.4

V_CCIO

0.4

–

8

–8

–16

–8

HSTL-15

Class II

—

V_REF

0.1

V_REF

0.1

—

V_REF

0.2

V_REF

0.2

V_CCIO

0.4

16

8

HSTL-12

Class I

–0.15

—

V_REF

0.08

V_REF

0.08

V_CCIO

0.15

+

–0.24

—

V_REF

0.15

V_REF

0.15

V_CCIO

0.24

+

0.25 ×

V_CCIO

0.75 ×

V_CCIO

HSTL-12

Class II

V_REF

0.08

V_REF

0.08

V_CCIO

0.15

V_REF

0.15

V_REF

0.15

V_CCIO

0.24

0.25 ×

V_CCIO

0.75 ×

V_CCIO

14

—

–14

—

HSUL-12

V_REF

0.13

V_REF

0.13

—

V_REF

0.22

V_REF

0.22

—

0.1 ×

0.9 ×

V_CCIO

Differential SSTL I/O Standards Specifications

Differential SSTL requires a V_REFinput.

Table 22: Differential SSTL I/O Standards Specifications for MAX 10 Devices—Preliminary

V_CCIO(V)

Typ

V_Swing(DC)(V)

V_X(AC)(V)

V_Swing(AC)(V)

I/O Standard

Min

Max

Min

Max⁽¹⁷⁾

Min

Typ

Max

Min

Max

SSTL-2 Class I, II

2.375

2.5

2.625

0.36

V_CCIOV_CCIO/2 –

0.2

—

V_CCIO/2+

0.2

0.7

V_CCIO

SSTL-18 Class I, II

SSTL-15 Class I, II

1.7

1.8

1.5

1.9

0.25

0.2

V_CCIOV_CCIO/2 –

0.175

—

V_CCIO/2+

0.175

0.5

V_CCIO

1.425

1.575

—

V_CCIO/2 –

0.15

V_CCIO/2 + 2(V_IH(AC)

0.15 – V_REF

2(V_IL(AC)

V_REF

–

)

(17)

The maximum value for V_SWING(DC)is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC)

and V_IL(DC)).

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Differential HSTL and HSUL I/O Standards Specifications

V_CCIO(V)

V_Swing(DC)(V)

V_X(AC)(V)

Typ

V_Swing(AC)(V)

Min Max

I/O Standard

Min

Typ

Max

Min

Max⁽¹⁷⁾

Min

Max

SSTL-135

1.283

1.35

1.45

0.18

—

V_REF

–

0.5 ×

V_REF

+

2(V_IH(AC)

2(V_IL(AC)

V_REF

–

0.135

V_CCIO

0.135

– V_REF

)

Differential HSTL and HSUL I/O Standards Specifications

Differential HSTL requires a V_REFinput.

Table 23: Differential HSTL and HSUL I/O Standards Specifications for MAX 10 Devices—Preliminary

V_CCIO(V)

Typ

V_DIF(DC)(V)

V_X(AC)(V)

Typ

V_CM(DC)(V)

Typ

V_DIF(AC)(V)

Min

I/O Standard

Min

Max

Min

Max

Min

Max

Min

Max

HSTL-18 Class

I, II

1.71

1.8

1.89

0.2

—

0.85

—

0.95

0.85

—

0.95

0.4

HSTL-15 Class

I, II

1.425

1.14

1.5

1.2

1.575

1.26

1.3

0.2

—

V_CCIO

—

0.71

—

0.79

0.71

—

0.79

0.4

0.3

HSTL-12 Class

I, II

0.16

0.26

0.48 ×

V_CCIO

0.5 ×

0.52 ×

V_CCIO

0.48 ×

V_CCIO

0.5 ×

0.52 ×

V_CCIO

HSUL-12

0.5 ×

0.4 ×

0.5 ×

0.6 ×

0.44

V_CCIO

0.12

–

V_CCIOV_CCIO

0.12

+

V_CCIO

(17)

The maximum value for V_SWING(DC)is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC)

and V_IL(DC)).

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Differential I/O Standards Specifications

Table 24: Differential I/O Standards Specifications for MAX 10 Devices—Preliminary

(18)

(19)(20)

(19)

V_CCIO(V)

Typ

V_ID(mV)

V_ICM(V)

V_OD(mV)

V_OS(V)

Typ

I/O Standard

Min

Max

Min

Max

Min

Condition

Max

1.8

Min

Typ

Max

Min

Max

0.05 D_MAX≤ 500 Mbps

0.55 500 Mbps ≤ D_MAX

≤ 700 Mbps

1.8

LVPECL ⁽²¹⁾2.375

2.5

2.625

100

—

1.05

D_MAX> 700 Mbps

1.55

1.8

0.05 D_MAX≤ 500 Mbps

0.55 500 Mbps ≤ D_MAX

≤ 700 Mbps

1.8

LVDS

2.375

2.625

—

247

—

600

1.125

1.25

1.375

1.05

—

D_MAX> 700 Mbps

1.55

—

(22)

BLVDS

2.5

2.625

100

—

1

—

mini-LVDS 2.375

—

300

600

1.2

1.4

(23)

RSDS ⁽²³⁾

2.375

2.5

2.625

—

100

200

600

0.5

1.2

1.5

1.4

PPDS (Row 2.375

(23)

I/Os)

(18)

(19)

(20)

(21)

(22)

(23)

V_INrange: 0 V ≤ V_IN≤ 1.85 V.

R_Lrange: 90 ≤ R_L≤ 110 Ω.

Low V_ODsetting is only supported for RSDS standard.

LVPECL input standard is only supported at clock input. Output standard is not supported.

No fixed V_IN, V_OD, and V_OSspecifications for Bus LVDS (BLVDS). They are dependent on the system topology.

Mini-LVDS, RSDS, and Point-to-Point Differential Signaling (PPDS) standards are only supported at the output pins for MAX 10 devices.

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Switching Characteristics

(18)

(19)(20)

(19)

V_CCIO(V)

V_ID(mV)

V_ICM(V)

Condition

V_OD(mV)

V_OS(V)

Typ

I/O Standard

Min

Typ

Max

Min

Max

Min

Max

1.8

Min

Typ

Max

Min

—

Max

0.05 D_MAX≤ 500 Mbps

0.55 500 Mbps ≤ D_MAX

≤ 700 Mbps

1.8

TMDS⁽²⁴⁾

2.375

2.5

2.625

100

—

1

1.05

0.55

D_MAX> 700 Mbps

—

1.55

1.25

(26)

Sub-LVDS

1.71

1.8

2.5

1.89

100

—

0.8

0.9

(25)

(27)

SLVS

HiSpi

2.375

2.625

0.05

—

1.1

1.8

0.05 D_MAX≤ 500 Mbps

0.55 500 Mbps ≤ D_MAX

≤ 700 Mbps

2.375

2.5

2.625

100

—

1.05

D_MAX> 700 Mbps

1.55

Related Information

MAX 10 LVDS SERDES I/O Standards Support, MAX 10 High-Speed LVDS I/O User Guide

Provides the list of I/O standards supported in single supply and dual supply devices.

Switching Characteristics

This section provides the performance characteristics of MAX 10 core and periphery blocks.

(18)

V_INrange: 0 V ≤ V_IN≤ 1.85 V.

(19)

R_Lrange: 90 ≤ R_L≤ 110 Ω.

(20)

Low V_ODsetting is only supported for RSDS standard.

(24)

Supported with requirement of an external level shift

(25)

Sub-LVDS input buffer is using 2.5 V differential buffer.

(26)

Differential output depends on the values of the external termination resistors.

(27)

Differential output offset voltage depends on the values of the external termination resistors.

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Core Performance Specifications

Clock Tree Specifications

Table 25: Clock Tree Specifications for MAX 10 Devices—Preliminary

Performance

–I7

Device

Unit

–I6

450

–C7

416

–A7

382

–C8

10M02

10M04

10M08

10M16

10M25

10M40

10M50

416

402

MHz

416

PLL Specifications

Table 26: PLL Specifications for MAX 10 Devices—Preliminary

V_{CCD_PLL}should always be connected to V_CCINTthrough decoupling capacitor and ferrite bead.

Symbol

Parameter

Condition

Min

Typ

—

Max

472.5

325

Unit

(28)

f_IN

Input clock frequency

—

5

MHz

f_INPFD

Phase frequency detector (PFD) input

frequency

—

(29)

f_VCO

PLL internal voltage-controlled

oscillator (VCO) operating range

—

600

—

1300

MHz

(28)

(29)

This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.

The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO

post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCOspecification.

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PLL Specifications

Symbol

Parameter

Condition

Min

40

—

Typ

—

Max

60

Unit

%

f_INDUTY

Input clock duty cycle

—

F_INPFD≥ 100 MHz

F_INPFD< 100 MHz

—

0.15

750

UI

t_{INJITTER_CCJ}

Input clock cycle-to-cycle jitter

(30)

—

ps

(28)

f_{OUT_EXT}

PLL output frequency for external clock

output

—

472.5

MHz

–6 speed grade

–7 speed grade

–8 speed grade

Duty cycle set to 50%

—

45

—

50

—

472.5

450

402.5

55

MHz

%

f_OUT

PLL output frequency to global clock

t_OUTDUTY

t_LOCK

Duty cycle for external clock output

Time required to lock from end of

device configuration

1

ms

t_DLOCK

Time required to lock dynamically

After switchover,

reconfiguring any non-

post-scale counters or

delays, or when areset is

deasserted

—

1

ms

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

—

10

—

650

75

ps

mUI

ps

t_{OUTJITTER_}

Regular I/O period jitter

(31)

PERIOD_IO

650

75

t_{OUTJITTER_CCJ_}

Regular I/O cycle-to-cycle jitter

(31)

IO

mUI

ps

t_{PLL_PSERR}

t_ARESET

Accuracy of PLL phase shift

50

Minimum pulse width on areset signal.

—

ns

(30)

A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than

200 ps.

(31)

Peak-to-peak jitter with a probability level of 10^–12(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the

intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.

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PLL Specifications

Unit

Symbol

Parameter

Condition

Min

Typ

Max

(32)

t_CONFIGPLL

Time required to reconfigure scan

chains for PLLs

—

3.5

—

SCANCLK cycles

f_SCANCLK

scanclk frequency

—

100

MHz

Table 27: PLL Specifications for MAX 10 Single Supply Devices—Preliminary

For V36 package, the PLL specification is based on single supply devices.

Symbol

Parameter

Condition

Max

660

66

Unit

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

ps

mUI

ps

t_{OUTJITTER_PERIOD_}

Dedicated clock output period jitter

(31)

DEDCLK

660

66

t_{OUTJITTER_CCJ_}

Dedicated clock output cycle-to-cycle jitter

(31)

DEDCLK

mUI

Table 28: PLL Specifications for MAX 10 Dual Supply Devices—Preliminary

Symbol

Parameter

Condition

Max

300

30

Unit

ps

F_OUT≥ 100 MHz

F_OUT< 100 MHz

F_OUT≥ 100 MHz

F_OUT< 100 MHz

t_{OUTJITTER_PERIOD_}

Dedicated clock output period jitter

(31)

DEDCLK

mUI

ps

300

30

t_{OUTJITTER_CCJ_}

Dedicated clock output cycle-to-cycle jitter

(31)

DEDCLK

mUI

(32)

With 100 MHz scanclk frequency.

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Embedded Multiplier Specifications

Table 29: Embedded Multiplier Specifications for MAX 10 Devices—Preliminary

Performance

–C7, –I7, –A7

183

Mode

Number of Multipliers

Power Supply Mode

Unit

–I6

198

234

198

234

–C8

160

180

160

180

Single supply mode

Dual supply mode

Single supply mode

Dual supply mode

MHz

9 × 9-bit multiplier

18 × 18-bit multiplier

1

212

183

212

Memory Block Performance Specifications

Table 30: Memory Block Performance Specifications for MAX 10 Devices—Preliminary

Resources Used

Performance

Memory

Mode

Power Supply Mode

Unit

LEs

M9K

–I6

–C7, –I7, –A7

–C8

Memory

Single supply mode

Dual supply mode

Single supply mode

Dual supply mode

Single supply mode

Dual supply mode

Single supply mode

Dual supply mode

232

284

232

284

232

284

232

284

219

260

219

260

219

260

219

260

204

238

204

238

204

238

204

238

MHz

FIFO 256 × 36

47

0

1

Single-port 256 × 36

M9K Block

Simple dual-port

0

256 × 36 CLK

True dual port

0

512 × 18 single CLK

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Internal Oscillator Specifications

Table 31: Internal Oscillator Frequencies for MAX 10 Devices—Preliminary

You can access to the internal oscillator frequencies in this table. The duty cycle of internal oscillator is approximately 45%–55%.

Device

10M02

10M04

10M08

10M16

10M25

10M40

10M50

Operating Frequency

Unit

55 – 116

MHz

35 – 77

MHz

UFM Performance Specifications

Table 32: UFM Performance Specifications for MAX 10 Devices—Preliminary

Performance

Block

Mode

Interface

Unit

–I6, –C7, –I7, –A7, –C8

Parallel

Serial

116

MHz

UFM

Avalon-MM slave

7.25

ADC Performance Specifications

Single Supply Devices ADC Performance Specifications

Table 33: ADC Performance Specifications for MAX 10 Single Supply Devices—Preliminary

Parameter

Symbol

Condition

Min

Typ

Max

Unit

ADC resolution

—

12

bits

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Single Supply Devices ADC Performance Specifications

Parameter

ADC supply voltage

Symbol

V_{CC_ONE}

V_REF

Condition

Min

Typ

3.0/3.3

—

Max

3.465

Unit

V

—

2.85

External reference voltage

V_{CC_ONE}

0.5

–

V_{CC_ONE}

V

Sampling rate

F_S

Accumulative sampling

rate

—

1

MSPS

Operating junction temperature range

Analog input voltage

Input resistance

T_J

—

–40

0

25

—

125

V_REF

3.6

—

°C

V

Prescalar disabled

Prescalar enabled ⁽³³⁾

—

V_IN

R_IN

C_IN

0

—

(34)

V

—

kΩ

pF

(34)

Dedicated analog input

Dual function pin

Prescalar disabled

Prescalar enabled

Prescalar disabled

Prescalar enabled

—

Input capcitance

—

pF

–0.2

–0.5

–0.75

–0.9

—

0.2

0.5

0.75

0.9

%FS

LSB

Offset error and drift

E_offset

Gain error and drift

DC Accuracy

E_gain

External V_REF, no

missing code

Differential non linearity

Integral non linearity

DNL

INL

Internal V_REF, no

missing code

–1

–2

—

1.7

2

LSB

—

(33)

Prescalar function divides the analog input voltage by half. The analog input handles up to 3.6 V for the MAX 10 single supply devices.

Refer to the MAX 10 Analog-to-Digital Converter User Guide for the RC equation.

(34)

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Single Supply Devices ADC Performance Specifications

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Total harmonic distortion

THD

F_IN= 50 kHz, F_S= 1

MHz, PLL

–65 ⁽³⁵⁾

—

dB

Signal-to-noise ratio

SNR

F_IN= 50 kHz, F_S= 1

MHz, PLL

54 ⁽³⁶⁾

53 ⁽³⁷⁾

—

dB

AC Accuracy

Signal-to-noise and distortion

SINAD

F_IN= 50 kHz, F_S= 1

MHz, PLL

Temperature sampling rate

Absolute accuracy

T_S

—

50

10

kSPS

°C

–40 to 125°C,

On-Chip Tempera‐

ture Sensor

with 64 samples

averaging

(38)

Single measurement

—

1

Cycle

Continuous

Conversion Rate ⁽³⁹⁾Conversion time

—

measurement

Temperature

measurement

—

1

Cycle

Related Information

Guidelines: Board Design for Analog Input, MAX 10 Analog-to-Digital Converter User Guide

Provides more information about the conversion rate and RC equation.

(35)

(36)

(37)

(38)

THD with prescalar enabled is 6dB less than the specification.

SNR with prescalar enabled is 6dB less than the specification.

SINAD with prescalar enabled is 6dB less than the specification.

For the Quartus II software version 15.0 and later, Altera Modular ADC and Altera Modular Dual ADC IP cores handle the 64 samples averaging.

For the Quartus II software versions prior to 14.1, you need to implement your own averaging calculation.

(39)

For more detailed description, refer to Timing section in the MAX 10 Analog-to-Digital Converter User Guide.

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Dual Supply Devices ADC Performance Specifications

Table 34: ADC Performance Specifications for MAX 10 Dual Supply Devices—Preliminary

Parameter

Symbol

—

Condition

Min

—

Typ

—

Max

12

Unit

bits

V

ADC resolution

—

Analog supply voltage

Digital supply voltage

External reference voltage

V_{CCA_ADC}

V_CCINT

V_REF

2.375

1.15

2.5

1.2

—

2.625

1.25

V

V_{CCA_ADC}

– 0.5

V_{CCA_ADC}

V

Sampling rate

F_S

Accumulative sampling

rate

—

1

MSPS

Operating junction temperature range

Analog input voltage

T_J

—

–40

0

25

—

125

V_REF

3

°C

V

Prescalar disabled

Prescalar enabled ⁽⁴⁰⁾

Average current

—

V_IN

0

—

V

Analog supply current (DC)

Digital supply current (DC)

Input resistance

I_{ACC_ADC}

I_CCINT

R_IN

—

275

450

150

—

µA

kΩ

pF

65

(41)

Dedicated analog input

Dual function pin

—

Input capcitance

C_IN

—

(40)

(41)

Prescalar function divides the analog input voltage by half. The analog input handles up to 3 V input for the MAX 10 dual supply devices.

Refer to the MAX 10 Analog-to-Digital Converter User Guide for the RC equation.

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Dual Supply Devices ADC Performance Specifications

Parameter

Symbol

Condition

Min

–0.2

–0.5

–0.75

–0.9

Typ

—

Max

0.2

Unit

%FS

LSB

Prescalar disabled

Prescalar enabled

Prescalar disabled

Prescalar enabled

Offset error and drift

E_offset

0.5

Gain error and drift

E_gain

DNL

0.75

0.9

DC Accuracy

External V_REF, no

missing code

Differential non linearity

Internal V_REF, no

missing code

–1

—

1.7

LSB

Integral non linearity

INL

—

–2

–70 ^(42)(43)

—

2

LSB

dB

Total harmonic distortion

THD

F_IN= 50 kHz, F_S= 1

MHz, PLL

—

Signal-to-noise ratio

SNR

F_IN= 50 kHz, F_S= 1

MHz, PLL

62 ^(44)(45)

—

dB

AC Accuracy

Signal-to-noise and distortion

SINAD

F_IN= 50 kHz, F_S= 1

MHz, PLL

61.5 ^(46)(47)

(42)

(43)

(44)

(45)

(46)

(47)

Total harmonic distortion is –65 dB for dual function pin.

THD with prescalar enabled is 6dB less than the specification.

Signal-to-noise ratio is 54 dB for dual function pin.

SNR with prescalar enabled is 6dB less than the specification.

Signal-to-noise and distortion is 53 dB for dual function pin.

SINAD with prescalar enabled is 6dB less than the specification.

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Periphery Performance Specifications

Parameter

Symbol

T_S

Condition

—

Min

—

Typ

—

Max

50

5

Unit

Temperature sampling rate

Absolute accuracy

kSPS

°C

—

–40 to 125°C,

—

On-Chip Tempera‐

ture Sensor

with 64 samples

averaging

(48)

Single measurement

—

1

Cycle

Continuous

Conversion Rate ⁽⁴⁹⁾Conversion time

—

measurement

Temperature

measurement

—

1

Cycle

Related Information

Guidelines: Board Design for Analog Input, MAX 10 Analog-to-Digital Converter User Guide

Provides more information about the conversion rate and RC equation.

Periphery Performance Specifications

This section describes the periphery performance, high-speed I/O, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/

IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

For more information about the high-speed and low-speed I/O performance pins, refer to the respective device pin-out files.

Related Information

Documentation: Pin-Out Files for Altera Devices

(48)

For the Quartus II software version 15.0 and later, Altera Modular ADC and Altera Modular Dual ADC IP cores handle the 64 samples averaging.

For the Quartus II software versions prior to 14.1, you need to implement your own averaging calculation.

(49)

For more detailed description, refer to Timing section in the MAX 10 Analog-to-Digital Converter User Guide.

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True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications

Table 35: True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary

True PPDS transmitter is only supported at bottom I/O banks. Emulated PPDS transmitter is supported at the output pin of all I/O banks.

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

5

Typ

—

Max

155

310

150

300

Min

5

Max

155

310

150

300

Min

5

Max

155

310

150

300

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

MHz

Mbps

MHz

5

Input clock

5

frequency (high-

speed I/O

f_HSCLK

5

performance pin)

5

100

80

70

40

20

10

5

100

80

70

40

20

10

5

100

80

70

40

20

10

5

Data rate (high-

HSIODR speed I/O

performance pin)

5

Input clock

5

frequency (low-

speed I/O

f_HSCLK

5

performance pin)

5

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True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

100

80

Typ

—

Max

300

55

Min

100

80

Max

300

55

Min

100

80

Max

300

55

×10

×8

×7

×4

×2

×1

—

Mbps

%

—

Data rate (low-

70

—

70

—

HSIODR speed I/O

40

—

40

—

performance pin)

20

—

20

—

10

—

10

—

t_DUTY

Duty cycle on

transmitter output

clock

45

—

45

—

TCCS⁽⁵⁰⁾Transmitter

—

410

425

470

—

410

425

470

—

410

425

470

ps

channel-to-channel

skew

Output jitter (high-

speed I/O

performance pin)

(51)

t_{x Jitter}

Output jitter (low-

speed I/O

performance pin)

t_RISE

Rise time

20 – 80%,

—

500

—

500

—

500

—

ps

C_LOAD= 5 pF

t_FALL

Fall time

20 – 80%,

C_LOAD= 5 pF

(50)

TCCS specifications apply to I/O banks from the same side only.

TX jitter is the jitter induced from core noise and I/O switching noise.

(51)

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True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

Typ

Max

Min

Max

Min

Max

t_LOCK

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

1

—

1

—

1

ms

configuration

True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

Table 36: True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary

True RSDS transmitter is only supported at bottom I/O banks. Emulated RSDS transmitter is supported at the output pin of all I/O banks.

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

5

Typ

—

Max

155

310

Min

5

Max

155

310

Min

5

Max

155

310

×10

×8

×7

×4

×2

×1

MHz

5

—

5

—

Input clock

5

—

5

—

frequency (high-

speed I/O

f_HSCLK

5

—

5

—

performance pin)

5

—

5

—

5

—

5

—

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True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

100

80

70

40

20

10

5

Typ

—

Max

310

150

300

55

Min

100

80

70

40

20

10

5

Max

310

150

300

55

Min

100

80

70

40

20

10

5

Max

310

150

300

55

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

Mbps

MHz

Mbps

%

Data rate (high-

HSIODR speed I/O

performance pin)

5

Input clock

5

frequency (low-

speed I/O

f_HSCLK

5

performance pin)

5

100

80

70

40

20

10

45

100

80

70

40

20

10

45

100

80

70

40

20

10

45

Data rate (low-

HSIODR speed I/O

performance pin)

t_DUTY

Duty cycle on

transmitter output

clock

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True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

Typ

Max

Min

Max

Min

Max

TCCS⁽⁵²⁾Transmitter

—

410

—

410

—

410

ps

channel-to-channel

skew

Output jitter (high-

speed I/O

—

425

470

—

425

470

—

425

470

ps

performance pin)

(53)

t_{x Jitter}

Output jitter (low-

speed I/O

performance pin)

t_RISE

Rise time

Fall time

20 – 80%,

—

500

—

1

—

500

—

1

—

500

—

1

ps

C_LOAD= 5 pF

t_FALL

t_LOCK

20 – 80%,

C_LOAD= 5 pF

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

ms

configuration

(52)

(53)

TCCS specifications apply to I/O banks from the same side only.

TX jitter is the jitter induced from core noise and I/O switching noise.

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Emulated RSDS_E_1R Transmitter Timing Specifications

Table 37: Emulated RSDS_E_1R Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary

Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

5

Typ

—

Max

85

Min

5

Max

85

Min

5

Max

85

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

MHz

Mbps

MHz

5

85

5

85

5

85

Input clock

5

85

5

85

5

85

frequency (high-

speed I/O

f_HSCLK

5

85

5

85

5

85

performance pin)

5

85

5

85

5

85

5

170

85

5

170

85

5

170

85

100

80

70

40

20

10

5

100

80

70

40

20

10

5

100

80

70

40

20

10

5

Data rate (high-

HSIODR speed I/O

performance pin)

5

85

5

85

5

85

Input clock

5

85

5

85

5

85

frequency (low-

speed I/O

f_HSCLK

5

85

5

85

5

85

performance pin)

5

85

5

85

5

85

5

170

5

170

5

170

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Emulated RSDS_E_1R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

100

80

Typ

—

Max

170

55

Min

100

80

Typ

—

Max

170

55

Min

100

80

Max

170

55

×10

×8

×7

×4

×2

×1

—

Mbps

%

—

Data rate (low-

70

—

HSIODR speed I/O

40

—

performance pin)

20

—

10

—

t_DUTY

Duty cycle on

transmitter output

clock

45

—

TCCS⁽⁵⁴⁾Transmitter

—

410

425

470

—

410

425

470

—

410

425

470

ps

channel-to-channel

skew

Output jitter (high-

speed I/O

performance pin)

(55)

t_{x Jitter}

Output jitter (low-

speed I/O

performance pin)

t_RISE

Rise time

20 – 80%,

—

500

—

500

—

500

—

ps

C_LOAD= 5 pF

t_FALL

Fall time

20 – 80%,

C_LOAD= 5 pF

(54)

(55)

TCCS specifications apply to I/O banks from the same side only.

TX jitter is the jitter induced from core noise and I/O switching noise.

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True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

Typ

Max

Min

Max

Min

Max

t_LOCK

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

1

—

1

—

1

ms

configuration

True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications

Table 38: True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary

True mini-LVDS transmitter is only supported at the bottom I/O banks. Emulated mini-LVDS_E_3R transmitter is supported at the output pin of all I/O

banks.

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

5

Typ

—

Max

155

310

Min

5

Max

155

310

Min

5

Max

155

310

×10

×8

×7

×4

×2

×1

MHz

5

—

5

—

Input clock

5

—

5

—

frequency (high-

speed I/O

f_HSCLK

5

—

5

—

performance pin)

5

—

5

—

5

—

5

—

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True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

100

80

70

40

20

10

5

Typ

—

Max

310

150

300

55

Min

100

80

70

40

20

10

5

Max

310

150

300

55

Min

100

80

70

40

20

10

5

Max

310

150

300

55

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

Mbps

MHz

Mbps

%

Data rate (high-

HSIODR speed I/O

performance pin)

5

Input clock

5

frequency (low-

speed I/O

f_HSCLK

5

performance pin)

5

100

80

70

40

20

10

45

100

80

70

40

20

10

45

100

80

70

40

20

10

45

Data rate (low-

HSIODR speed I/O

performance pin)

t_DUTY

Duty cycle on

transmitter output

clock

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True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

Typ

Max

Min

Max

Min

Max

TCCS⁽⁵⁶⁾Transmitter

—

410

—

410

—

410

ps

channel-to-channel

skew

Output jitter (high-

speed I/O

—

425

470

—

425

470

—

425

470

performance pin)

(57)

t_{x Jitter}

Output jitter (low-

speed I/O

performance pin)

t_RISE

Rise time

Fall time

20 – 80%,

—

500

—

1

—

500

—

1

—

500

—

1

ps

C_LOAD= 5 pF

t_FALL

t_LOCK

20 – 80%,

C_LOAD= 5 pF

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

ms

configuration

(56)

TCCS specifications apply to I/O banks from the same side only.

TX jitter is the jitter induced from core noise and I/O switching noise.

(57)

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True LVDS Transmitter Timing

Single Supply Devices True LVDS Transmitter Timing Specifications

Table 39: True LVDS Transmitter Timing Specifications for MAX 10 Single Supply Devices—Preliminary

True LVDS transmitter is only supported at the bottom I/O banks.

–C7, –I7

Typ

—

–A7

Typ

—

–C8

Symbol

Parameter

Mode

Unit

Min

5

Max

145

290

55

Min

5

Max

100

200

55

Min

5

Typ

—

Max

100

200

55

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

MHz

Mbps

%

5

—

5

—

5

Input clock

f_HSCLK

frequency

Data rate

5

—

5

—

5

—

5

100

80

70

40

20

10

45

—

100

80

70

40

20

10

45

100

80

70

40

20

10

45

—

HSIODR

—

t_DUTY

Duty cycle on

transmitter output

clock

—

TCCS⁽⁵⁸⁾

Transmitter

channel-to-

channel skew

—

410

—

410

—

410

ps

(58)

TCCS specifications apply to I/O banks from the same side only.

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Single Supply Devices True LVDS Transmitter Timing Specifications

–C7, –I7

Typ

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

—

Max

1,000

—

Min

—

Max

1,000

—

Min

—

Max

1,000

—

(59)

t_{x Jitter}

Output jitter

Rise time

—

ps

t_RISE

20 – 80%, C_LOAD

= 5 pF

—

500

—

500

—

500

t_FALL

t_LOCK

Fall time

20 – 80%, C_LOAD

= 5 pF

—

500

—

1

—

500

—

1

—

500

—

1

ps

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

ms

configuration

(59)

TX jitter is the jitter induced from core noise and I/O switching noise.

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Dual Supply Devices True LVDS Transmitter Timing Specifications

Table 40: True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary

True LVDS transmitter is only supported at the bottom I/O banks.

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

Typ

Max

Min

Max

Min

Max

×10

5

—

360 ⁽⁶⁰⁾

,

5

310

5

300

MHz

335 ⁽⁶¹⁾

360

×8

×7

5

—

5

—

320

310

5

—

320

300

MHz

360 ⁽⁶⁰⁾

,

Input clock

frequency

335 ⁽⁶¹⁾

f_HSCLK

×4

×2

5

—

360

5

—

320

620

5

—

320

600

MHz

Mbps

×1

5

×10

100

720 ⁽⁶⁰⁾

,

100

670 ⁽⁶¹⁾

×8

×7

80

70

—

720

80

70

—

640

620

80

70

—

640

600

Mbps

720 ⁽⁶⁰⁾

,

670 ⁽⁶¹⁾

HSIODR

Data rate

×4

×2

×1

—

40

20

10

45

—

720

360

55

40

20

10

45

—

640

320

55

40

20

10

45

—

640

320

55

Mbps

%

t_DUTY

Duty cycle on

transmitter output

clock

(60)

(61)

Applicable to –I6 speed grade.

Applicable to –C7 and –I7 speed grades.

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Dual Supply Devices True LVDS Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

Typ

Max

Min

Max

Min

Max

TCCS⁽⁶²⁾

Transmitter

—

410

—

410

—

410

ps

channel-to-

channel skew

(63)

t_{x Jitter}

Output jitter

Rise time

—

380

—

380

—

380

—

ps

t_RISE

20 – 80%, C_LOAD

= 5 pF

500

t_FALL

t_LOCK

Fall time

20 – 80%, C_LOAD

= 5 pF

—

500

—

1

—

500

—

1

—

500

—

1

ps

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

ms

configuration

(62)

TCCS specifications apply to I/O banks from the same side only.

TX jitter is the jitter induced from core noise and I/O switching noise.

(63)

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Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications

Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications

Table 41: Emulated LVDS_E_3R Transmitter Timing Specifications for MAX 10 Single Supply Devices—Preliminary

Emulated LVDS_E_3R transmitters are supported at the output pin of all I/O banks.

–C7, –I7

Typ

—

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

5

Max

142.5

285

Min

5

Max

100

200

100

200

Min

5

Max

100

200

100

200

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

MHz

Mbps

MHz

5

—

5

Input clock

5

—

5

frequency (high-

speed I/O

f_HSCLK

5

—

5

performance pin)

5

—

5

—

5

100

80

70

40

20

10

5

—

285

100

80

70

40

20

10

5

100

80

70

40

20

10

5

—

285

Data rate (high-

—

285

HSIODR speed I/O

—

285

performance pin)

—

285

—

285

—

100

5

—

100

5

Input clock

5

—

100

5

frequency (low-

speed I/O

f_HSCLK

5

—

100

5

performance pin)

5

—

100

5

—

200

5

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Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications

–C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

100

80

Typ

—

Max

200

55

Min

100

80

Max

200

55

Min

100

80

Max

200

55

×10

×8

×7

×4

×2

×1

—

Mbps

%

—

Data rate (low-

70

—

70

—

HSIODR speed I/O

40

—

40

—

performance pin)

20

—

20

—

10

—

10

—

t_DUTY

Duty cycle on

transmitter output

clock

45

—

45

—

TCCS⁽⁶⁴⁾Transmitter

—

410

—

410

—

410

ps

channel-to-channel

skew

(65)

t_{x Jitter}

t_RISE

Output jitter

Rise time

—

1,000

—

1,000

—

1,000

—

ps

20 – 80%,

500

C_LOAD= 5 pF

t_FALL

Fall time

20 – 80%,

—

500

—

1

—

500

—

1

—

500

—

1

ps

C_LOAD= 5 pF

t_LOCK

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

ms

configuration

(64)

TCCS specifications apply to I/O banks from the same side only.

TX jitter is the jitter induced from core noise and I/O switching noise.

(65)

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Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications

Table 42: Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices—Preliminary

Emulated LVDS_E_3R, SLVS, and Sub-LVDS transmitters are supported at the output pin of all I/O banks.

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

5

Typ

—

Max

300

600

300

150

300

Min

5

Max

275

550

275

150

300

Min

5

Max

275

550

275

150

300

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

MHz

Mbps

MHz

5

Input clock

5

frequency (high-

speed I/O

f_HSCLK

5

performance pin)

5

100

80

70

40

20

10

5

100

80

70

40

20

10

5

100

80

70

40

20

10

5

Data rate (high-

HSIODR speed I/O

performance pin)

5

Input clock

5

frequency (low-

speed I/O

f_HSCLK

5

performance pin)

5

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Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

100

80

Typ

—

Max

300

55

Min

100

80

Max

300

55

Min

100

80

Max

300

55

×10

×8

×7

×4

×2

×1

—

Mbps

%

—

Data rate (low-

70

—

70

—

HSIODR speed I/O

40

—

40

—

performance pin)

20

—

20

—

10

—

10

—

t_DUTY

Duty cycle on

transmitter output

clock

45

—

45

—

TCCS⁽⁶⁶⁾Transmitter

—

410

425

470

—

410

425

470

—

410

425

470

ps

channel-to-channel

skew

Output jitter (high-

speed I/O

performance pin)

(67)

t_{x Jitter}

Output jitter (low-

speed I/O

performance pin)

t_RISE

Rise time

20 – 80%,

—

500

—

500

—

500

—

ps

C_LOAD= 5 pF

t_FALL

Fall time

20 – 80%,

C_LOAD= 5 pF

(66)

TCCS specifications apply to I/O banks from the same side only.

TX jitter is the jitter induced from core noise and I/O switching noise.

(67)

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LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

–I6, –C7, –I7

–A7

Typ

—

–C8

Typ

—

Symbol

Parameter

Mode

Unit

Min

Typ

Max

Min

Max

Min

Max

t_LOCK

Time required for

the PLL to lock,

after CONF_DONE

signal goes high,

indicating the

completion of

device

—

1

—

1

—

1

ms

configuration

LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

Single Supply Devices LVDS Receiver Timing Specifications

Table 43: LVDS Receiver Timing Specifications for MAX 10 Single Supply Devices—Preliminary

LVDS receivers are supported at all banks.

–C7, –I7

–A7

–C8

Symbol

Parameter

Mode

Unit

Min

5

Max

145

290

Min

5

Max

100

200

Min

Max

100

200

×10

×8

×7

×4

×2

×1

5

MHz

5

Input clock frequency

(high-speed I/O

5

f_HSCLK

5

performance pin)

5

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Single Supply Devices LVDS Receiver Timing Specifications

–C7, –I7

–A7

–C8

Symbol

Parameter

Mode

Unit

Min

100

80

70

40

20

10

5

Max

290

100

200

800

Min

100

80

70

40

20

10

5

Max

200

100

200

800

Min

100

80

70

40

20

10

5

Max

200

100

200

800

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

Mbps

MHz

Mbps

ps

Data rate (high-speed I/

O performance pin)

HSIODR

5

Input clock frequency

(low-speed I/O

5

f_HSCLK

5

performance pin)

5

100

80

70

40

20

10

—

100

80

70

40

20

10

—

100

80

70

40

20

10

—

Data rate (low-speed I/

O performance pin)

HSIODR

Sampling window

(high-speed I/O

performance pin)

SW

Sampling window (low-

speed I/O performance

pin)

—

1,000

—

1,000

—

1,000

ps

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Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

–C7, –I7

–A7

–C8

Symbol

Parameter

Mode

Unit

Min

—

Max

Min

—

Max

1,000

1

Min

—

Max

1,000

1

(68)

t_{x Jitter}

t_LOCK

Input jitter

—

1,000

1

ps

Time required for the

PLL to lock, after CONF_

DONE signal goes high,

indicating the

—

ms

completion of device

configuration

Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

Table 44: LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for MAX 10 Dual Supply Devices—Preliminary

LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS receivers are supported at all banks.

–I6, –C7, –I7

–A7

–C8

Symbol

Parameter

Mode

Unit

Min

Max

360

Min

5

Max

320

Min

5

Max

320

×10

×8

×7

×4

×2

×1

5

MHz

5

Input clock frequency

(high-speed I/O

5

f_HSCLK

5

performance pin)

5

(68)

TX jitter is the jitter induced from core noise and I/O switching noise.

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Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

–I6, –C7, –I7

–A7

–C8

Symbol

Parameter

Mode

Unit

Min

100

80

70

40

20

10

5

Max

720

360

150

300

400

500

Min

100

80

70

40

20

10

5

Max

640

320

150

300

400

500

Min

100

80

70

40

20

10

5

Max

640

320

150

300

400

500

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

Mbps

MHz

Mbps

ps

Data rate (high-speed I/

O performance pin)

HSIODR

5

Input clock frequency

(low-speed I/O

5

f_HSCLK

5

performance pin)

5

100

80

70

40

20

10

—

100

80

70

40

20

10

—

100

80

70

40

20

10

—

Data rate (low-speed I/

O performance pin)

HSIODR

SW

Sampling window

Input jitter

(69)

t_{x Jitter}

—

ps

(69)

TX jitter is the jitter induced from core noise and I/O switching noise.

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Memory Output Clock Jitter Specifications

–C8

–I6, –C7, –I7

–A7

Symbol

Parameter

Mode

Unit

Min

Max

Min

Max

Min

Max

t_LOCK

Time required for the

PLL to lock, after CONF_

DONE signal goes high,

indicating the

—

1

—

1

—

1

ms

completion of device

configuration

Memory Output Clock Jitter Specifications

MAX 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for MAX 10 devices calibrate automatically.

The memory output clock jitter measurements are for 200 consecutive clock cycles.

The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a PHY clock

network.

DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.

Table 45: Memory Output Clock Jitter Specifications for MAX 10 Devices—Preliminary

–6 Speed Grade

–7 Speed Grade

Parameter

Symbol

Unit

Min

Max

100

200

Min

Max

125

250

Clock period jitter

t_JIT(per)

t_JIT(cc)

–100

—

–125

—

ps

Cycle-to-cycle period jitter

Related Information

Literature: External Memory Interfaces

Provides more information about external memory system performance specifications, board design guidelines, timing analysis, simulation, and

debugging information.

Configuration Specifications

This section provides configuration specifications and timing for MAX 10 devices.

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JTAG Timing Parameters

Table 46: JTAG Timing Parameters for MAX 10 Devices—Preliminary

The values are based on C_L= 10 pF of TDO .

The affected Boundary Scan Test (BST) instructions are SAMPLE/PRELOAD, EXTEST, INTEST, and CHECK_STATUS.

Non-BST and non-CONFIG_IO Operation

BST and CONFIG_IO Operation

Symbol

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

t_JCP

TCK clock period

40

20

2

—

50

25

2

—

ns

t_JCH

TCK clock high time

TCK clock low time

JTAG port setup time

JTAG port hold time

t_JCL

t_{JPSU_TDI}

t_{JPSU_TMS}

t_JPH

3

10

—

10

—

t_JPCO

JTAG port clock to

output

•

15 (for V_CCIO= 3.3,

3.0, and 2.5 V)

17 (for V_CCIO= 1.8

and 1.5 V)

•

18 (for V_CCIO= 3.3,

3.0, and 2.5 V)

20 (for V_CCIO= 1.8

and 1.5 V)

t_JPZX

JTAG port high

impedance to valid

output

—

ns

•

15 (for V_CCIO= 3.3,

3.0, and 2.5 V)

17 (for V_CCIO= 1.8

and 1.5 V)

•

15 (for V_CCIO= 3.3,

3.0, and 2.5 V)

17 (for V_CCIO= 1.8

and 1.5 V)

t_JPXZ

JTAG port valid output

to high impedance

•

15 (for V_CCIO= 3.3,

3.0, and 2.5 V)

17 (for V_CCIO= 1.8

and 1.5 V)

•

15 (for V_CCIO= 3.3,

3.0, and 2.5 V)

17 (for V_CCIO= 1.8

and 1.5 V)

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POR Specifications

Table 47: POR Delay Specifications for MAX 10 Devices—Preliminary

POR Delay

Don’t Care

Fast

Condition

Minimum

Maximum

Unit

—

Instant-on enabled

Instant-on disabled

No delay

3

9

ms

Standard

50

200

Remote System Upgrade Circuitry Timing Specifications

Table 48: Remote System Upgrade Circuitry Timing Specifications for MAX 10 Devices—Preliminary

Parameter

Device

All

Minimum

—

Maximum

Unit

MHz

ns

t_{MAX_RU_CLK}

t_{RU_nCONFIG}

40

—

10M02, 10M04, 10M08, 10M16, 10M25

10M40, 10M50

250

350

ns

10M02, 10M04, 10M08, 10M16, 10M25

10M40, 10M50

300

ns

t_{RU_nRSTIMER}

500

ns

User Watchdog Internal Circuitry Timing Specifications

Table 49: User Watchdog Timer Specifications for MAX 10 Devices—Preliminary

The specifications are subject to PVT changes.

Parameter

Device

Minimum

Typical

Maximum

Unit

10M02, 10M04, 10M08,

10M16, 10M25

3.4

5.1

7.3

MHz

User watchdog frequency

10M40, 10M50

2.2

3.3

4.8

MHz

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Uncompressed Raw Binary File (.rbf) Sizes

Table 50: Uncompressed .rbf Sizes and Internal Configuration Time for MAX 10 Devices—Preliminary

The internal configuration time is based on the uncompressed, unencrypted, and without memory initialization files. Turn on instant-on feature to

measure the internal configuration time. The internal configuration time measurement is from the minimum value of V_{CC_ONE}(for single supply devices)

or V_CC(for dual supply devices) to user mode entry.

CFM Data Size (bits)

Device

Internal Configuration Time (ms)

Without Memory Initialization With Memory Initialization

10M02

10M04

10M08

10M16

10M25

10M40

10M50

554,000

1,540,000

2,800,000

4,140,000

7,840,000

676,000

1,880,000

3,430,000

4,780,000

9,670,000

3

4

5

9

Related Information

Instant-on, MAX 10 FPGA Configuration User Guide

Provides more information about instant-on feature.

I/O Timing

The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis.

The Quartus II Timing Analyzer provides a more accurate and precise I/O timing data based on the specific device and design after you complete

place-and-route.

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Programmable IOE Delay

Table 51: I/O Timing for MAX 10 Devices—Preliminary

These I/O timing parameters are for the 3.3-V LVTTL I/O standard with the maximum drive strength and fast slew rate for 10M08DAF484 device.

Symbol

Parameter

–C7, –I7

–0.750

1.180

–C8

–0.808

1.215

5.575

5.467

Unit

T_su

Global clock setup time

Global clock hold time

ns

T_h

ns

T_co

T_pd

Global clock to output delay

5.131

ns

Best case pin-to-pin propagation delay through one LUT

4.907

ns

Programmable IOE Delay

Programmable IOE Delay On Row Pins

Table 52: IOE Programmable Delay on Row Pins for MAX 10 Devices—Preliminary

The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of

the Quartus II software.

The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.

Maximum Offset

Number

Minimum

Offset

Parameter

Paths Affected

of

Fast Corner

Slow Corner

Unit

Settings

–I7

–C8

–C7

–C8

–I7

–A7

Input delay from pin Pad to I/O

7

8

2

0

0.782

0.887

0.460

0.838

1.738

1.799

2.040

1.073

1.796

1.673

ns

to internal cells

dataout to core

Input delay from pin Pad to I/O

0.953

0.493

1.973

1.027

2.042

1.061

1.902

0.977

to input register

input register

I/O output

Delay from output

register to output pin register to pad

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Programmable IOE Delay for Column Pins

Table 53: IOE Programmable Delay on Column Pins for MAX 10 Devices—Preliminary

The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of

the Quartus II software.

The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.

Maximum Offset

Number

Minimum

Offset

Parameter

Paths Affected

of

Fast Corner

Slow Corner

Unit

Settings

–I7

–C8

–C7

–C8

–I7

–A7

Input delay from pin Pad to I/O

7

8

2

0

0.777

0.877

0.417

0.833

1.73

1.79

2.017

0.973

1.788

1.666

ns

to internal cells

dataout to core

Input delay from pin Pad to I/O

0.942

0.447

1.951

0.931

2.018

0.961

1.882

0.887

to input register

input register

I/O output

Delay from output

register to output pin register to pad

Glossary

Table 54: Glossary

Term

Definition

Preliminary

Some tables show the designation as “Preliminary”. Preliminary characteristics are created using simulation

results, process data, and other known parameters.

Final numbers are based on actual silicon characterization and testing. The numbers reflect the actual perform‐

ance of the device under worst-case silicon process, voltage, and junction temperature conditions. There are no

preliminary designations on finalized tables.

R_L

Receiver differential input discrete resistor (external to MAX 10 devices).

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Glossary

Term

Definition

RSKM (Receiver input skew

margin)

HIGH-SPEED I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM =

(TUI – SW – TCCS) / 2.

Sampling window (SW)

HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it correctly. The

setup and hold times determine the ideal strobe position in the sampling window.

Single-ended voltage referenced

I/O standard

The AC input signal values indicate the voltage levels at which the receiver must meet its timing specifications.

The DC input signal values indicate the voltage levels at which the final logic state of the receiver is unambigu‐

ously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is

intended to provide predictable receiver timing in the presence of input waveform ringing.

t_C

High-speed receiver/transmitter input and output clock period.

TCCS (Channelto- channel-

skew)

HIGH-SPEED I/O block: The timing difference between the fastest and slowest output edges, including t_CO

variation and clock skew. The clock is included in the TCCS measurement.

t_cin

Delay from clock pad to I/O input register.

Delay from clock pad to I/O output.

t_CO

t_cout

Delay from clock pad to I/O output register.

HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.

Signal high-to-low transition time (80–20%).

Input register hold time.

t_DUTY

t_FALL

t_H

Timing Unit Interval (TUI)

HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data sampling window.

(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w).

t_INJITTER

t_{OUTJITTER_DEDCLK}

t_{OUTJITTER_IO}

t_pllcin

Period jitter on PLL clock input.

Period jitter on dedicated clock output driven by a PLL.

Period jitter on general purpose I/O driven by a PLL.

Delay from PLL inclk pad to I/O input register.

Delay from PLL inclk pad to I/O output register.

Signal low-to-high transition time (20–80%).

t_pllcout

t_RISE

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Glossary

Term

Definition

t_SU

Input register setup time.

V_CM(DC)

V_DIF(AC)

V_DIF(DC)

V_HYS

DC common mode input voltage.

AC differential input voltage: The minimum AC input differential voltage required for switching.

DC differential input voltage: The minimum DC input differential voltage required for switching.

Hysteresis for Schmitt trigger input.

V_ICM

Input common mode voltage: The common mode of the differential signal at the receiver.

V_ID

Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors

of a differential transmission at the receiver.

V_IH

Voltage input high: The minimum positive voltage applied to the input which is accepted by the device as a logic

high.

V_IH(AC)

V_IH(DC)

V_IL

High-level AC input voltage.

High-level DC input voltage.

Voltage input low: The maximum positive voltage applied to the input which is accepted by the device as a logic

low.

V_{IL (AC)}

V_{IL (DC)}

V_IN

Low-level AC input voltage.

Low-level DC input voltage.

DC input voltage.

V_OCM

V_OD

Output common mode voltage: The common mode of the differential signal at the transmitter.

Output differential voltage swing: The difference in voltage between the positive and complementary conductors

of a differential transmission at the transmitter. V_OD= V_OH– V_OL

.

V_OH

V_OL

Voltage output high: The maximum positive voltage from an output which the device considers is accepted as the

minimum positive high level.

Voltage output low: The maximum positive voltage from an output which the device considers is accepted as the

maximum positive low level.

V_OS

Output offset voltage: V_OS= (V_OH+ V_OL) / 2.

V_{OX (AC)}

AC differential Output cross point voltage: The voltage at which the differential output signals must cross.

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Glossary

Term

Definition

V_REF

V_REF(AC)

Reference voltage for SSTL, HSTL, and HSUL I/O Standards.

AC input reference voltage for SSTL, HSTL, and HSUL I/O Standards. V_REF(AC)= V_REF(DC)+ noise. The peak-to-

peak AC noise on V_REFshould not exceed 2% of V_REF(DC)

.

V_REF(DC)

DC input reference voltage for SSTL, HSTL, and HSUL I/O Standards.

V_{SWING (AC)}

V_{SWING (DC)}

V_TT

AC differential input voltage: AC Input differential voltage required for switching.

DC differential input voltage: DC Input differential voltage required for switching.

Termination voltage for SSTL, HSTL, and HSUL I/O Standards.

V_{X (AC)}

AC differential Input cross point voltage: The voltage at which the differential input signals must cross.

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Document Revision History for MAX 10 FPGA Device Datasheet

Date

Version

Changes

May 2015

2015.05.04

•

Updated a note to V_CCIOfor both single supply and dual supply power supplies recommended operating

conditions tables. Note updated: V_CCIOfor all I/O banks must be powered up during user mode because

V_CCIOI/O banks are used for the ADC and I/O functionalities.

•

Updated Example for OCT Resistance Calculation after Calibration at Device Power-Up.

Removed a note to BLVDS in Differential I/O Standards Specifications for MAX 10 Devices table. BLVDS is

now supported in MAX 10 single supply devices. Note removed: BLVDS TX is not supported in single

supply devices.

•

Updated ADC Performance Specifications for both single supply and dual supply devices.

•

Changed the symbol for Operating junction temperature range parameter from T_Ato T_J.

Edited sampling rate maximum value from 1000 kSPS to 1 MSPS.

Added a note to analog input voltage parameter.

Removed input frequency, f_INspecification.

Updated the condition for DNL specification: External V_REF, no missing code. Added DNL specification

for condition: Internal V_REF, no missing code.

•

Added notes to AC accuracy specifications that the value with prescalar enabled is 6dB less than the

specification.

Added a note to On-Chip Temperature Sensor (absolute accuracy) parameter about the averaging

calculation.

•

Updated ADC Performance Specifications for MAX 10 Single Supply Devices table.

•

Added condition for On-Chip Temperature Sensor (absolute accuracy) parameter: with 64 samples

averaging.

Updated ADC Performance Specifications for MAX 10 Dual Supply Devices table.

•

Updated Digital Supply Voltage minimum value from 1.14 V to 1.15 V and maximum value from 1.26 V

to 1.25 V.

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Document Revision History for MAX 10 FPGA Device Datasheet

Changes

Date

Version

•

Updated f_HSCLKand HSIODR specifications for –A7 speed grade in the following tables:

•

True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

•

True LVDS Transmitter Timing Specifications for MAX 10 Single Supply Devices

True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices

Emulated LVDS_E_3R Transmitter Timing Specifications for MAX 10 Single Supply Devices

Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

•

LVDS Receiver Timing Specifications for MAX 10 Single Supply Devices

LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for MAX 10 Dual Supply

Devices

•

Updated TCCS specifications in the following tables:

•

True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

•

True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

•

Emulated RSDS_E_1R Transmitter Timing Specifications for MAX 10 Dual Supply Devices

True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

•

True LVDS Transmitter Timing Specifications for MAX 10 Single Supply Devices

True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices

Emulated LVDS_E_3R Transmitter Timing Specifications for MAX 10 Single Supply Devices

Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

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Document Revision History for MAX 10 FPGA Device Datasheet

Date

Version

Changes

•

Updated t_{x Jitter}specifications in the following tables:

•

True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

•

True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

•

Emulated RSDS_E_1R Transmitter Timing Specifications for MAX 10 Dual Supply Devices

True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

•

True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices

Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

•

Updated SW specifications in LVDS Receiver Timing Specifications for MAX 10 Single Supply Devices

table.

Added a note to t_{x Jitter}for all LVDS tables. Note: TX jitter is the jitter induced from core noise and I/O

switching noise.

Updated the description for t_LOCKfor all LVDS tables: Time required for the PLL to lock, after CONF_DONE

signal goes high, indicating the completion of device configuration.

Updated Memory Output Clock Jitter Specifications section.

•

Updated maximum external memory interfaces frequency from 300 MHz to 303 MHz.

Updated PLL output routing from global clock network to PHY clock network.

•

Added I/O Timing for MAX 10 Devices table.

Added V_HYSin the Glossary table.

January 2015

2015.01.23

•

Removed a note to V_CCAin Power Supplies Recommended Operating Conditions for MAX 10 Dual Supply

Devices table. This note is not valid: All V_CCApins must be connected together for EQFP package.

Corrected the maximum value for t_{OUTJITTER_CCJ_ IO}(F_OUT≥ 100 MHz) from 60 ps to 650 ps in PLL Specifi‐

cations for MAX 10 Devices table.

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Document Revision History for MAX 10 FPGA Device Datasheet

Changes

Date

Version

December 2014

2014.12.15

•

Restructured Programming/Erasure Specifications for MAX 10 Devices table to add temperature specifica‐

tions that affect the data retention duration.

Added statements in the I/O Pin Leakage Current section: Input channel leakage of ADC I/O pins due to

hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled

or disabled. This is applicable to all MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16,

10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A.

•

Added a statement in the I/O Standards Specifications section: You must perform timing closure analysis to

determine the maximum achievable frequency for general purpose I/O standards.

Updated SSTL-2 Class I and II I/O standard specifications for JEDEC compliance as follows:

•

VIL(AC) Max: Updated from V_REF– 0.35 to V_REF– 0.31

VIH(AC) Min: Updated from V_REF+ 0.35 to V_REF+ 0.31

•

Added a note to BLVDS in Differential I/O Standards Specifications for MAX 10 Devices table: BLVDS TX

is not supported in single supply devices.

Added a link to MAX 10 High-Speed LVDS I/O User Guide for the list of I/O standards supported in single

supply and dual supply devices.

Added a statement in PLL Specifications for MAX 10 Single Supply Device table: For V36 package, the PLL

specification is based on single supply devices.

•

Added Internal Oscillator Specifications from MAX 10 Clocking and PLL User Guide.

Added UFM specifications for serial interface.

Updated total harmonic distortion (THD) specifications as follows:

•

Single supply devices: Updated from 65 dB to –65 dB

Dual supply devices: Updated from 70 dB to –70 dB (updated from 65 dB to –65 dB for dual function

pin)

•

Added condition for On-Chip Temperature Sensor—Absolute accuracy parameter in ADC Performance

Specifications for MAX 10 Dual Supply Devices table. The condition is: with 64 samples averaging.

Updated the description in Periphery Performance Specifications to mention that proper timing closure is

required in design.

Updated HSIODR and f_HSCLKspecifications for x10 and x7 modes in True LVDS Transmitter Timing

Specifications for MAX 10 Dual Supply Devices.

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Document Revision History for MAX 10 FPGA Device Datasheet

Date

Version

Changes

•

Added specifications for low-speed I/O performance pin sampling window in LVDS Receiver Timing

Specifications for MAX 10 Single Supply Devices table: Max = 900 ps for –C7, –I7, –A7, and –C8 speed

grades.

•

Added t_{RU_nCONFIG}and t_{RU_nRSTIMER}specifications for different devices in Remote System Upgrade

Circuitry Timing Specifications for MAX 10 Devices table.

Removed the word "internal oscillator" in User Watchdog Timer Specifications for MAX 10 Devices table to

avoid confusion.

Added IOE programmable delay specifications.

September 2014

2014.09.22 Initial release.

MAX 10 FPGA Device Datasheet

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型号：	10M08SFE144C7G
厂家：	INTEL
描述：	Field Programmable Gate Array, 8000-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, EQFP-144 栅
文件：	总68页 (文件大小：976K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

10M08SFE144C7G [INTEL]

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