5AGXFA7G6F27C6N [INTEL]
Field Programmable Gate Array, 500MHz, PBGA672, ROHS COMPLIANT, FBGA-672;
| 型号： | 5AGXFA7G6F27C6N |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, 500MHz, PBGA672, ROHS COMPLIANT, FBGA-672 栅 |
| 文件： | 总122页 (文件大小：2542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Arria V GX, GT, SX, and ST Device
Datasheet
December 2013
AV-51002-3.6
AV-51002-3.6
Datasheet
This datasheet describes the electrical characteristics, switching characteristics,
configuration specifications, and I/O timing for Arria® V devices.
Arria V devices are offered in commercial and industrial grades. Commercial devices
are offered in –C4 (fastest), –C5, and –C6 speed grades. Industrial grade devices are
offered in the –I3 and –I5 speed grades.
f
For more information about the densities and packages of devices in the Arria V
family, refer to the Arria V Device Overview.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of
Arria V devices.
Operating Conditions
Arria V devices are rated according to a set of defined parameters. To maintain the
highest possible performance and reliability of the Arria V devices, you must consider
the operating requirements described in this section.
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ISO
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products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
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for products or services.
December 2013 Altera Corporation
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Page 2
Electrical Characteristics
Absolute Maximum Ratings
This section defines the maximum operating conditions for Arria V devices. The
values are based on experiments conducted with the devices and theoretical modeling
of breakdown and damage mechanisms.
The functional operation of the device is not implied for these conditions.
c
Conditions outside the range listed in Table 1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 1. Absolute Maximum Ratings for Arria V Devices
Symbol Description
VCC
Minimum
Maximum
Unit
Core voltage power supply
–0.50
1.43
V
Periphery circuitry, PCIe® hard IP block, and transceiver physical
coding sublayer (PCS) power supply
VCCP
–0.50
1.43
V
VCCPGM
VCC_AUX
VCCBAT
Configuration pins power supply
Auxiliary supply
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–0.50
–25
3.90
3.25
3.90
3.90
3.90
1.80
3.25
3.25
1.80
1.50
1.50
1.50
3.80
1.43
3.90
3.90
3.25
3.25
40
V
V
Battery back-up power supply for design security volatile key register
I/O pre-driver power supply
V
VCCPD
V
VCCIO
I/O power supply
V
VCCD_FPLL
VCCA_FPLL
VCCA_GXB
VCCH_GXB
VCCR_GXB
VCCT_GXB
VCCL_GXB
VI
Phase-locked loop (PLL) digital power supply
PLL analog power supply
V
V
Transceiver high voltage power
Transmitter output buffer power
Receiver power
V
V
V
Transmitter power
V
Transceiver clock network power
DC input voltage
V
V
VCC_HPS
VCCPD_HPS
VCCIO_HPS
HPS core voltage and periphery circuitry power supply
HPS I/O pre-driver power supply
HPS I/O power supply
V
V
V
VCCRSTCLK_HPS HPS reset and clock input pins power supply
V
VCCPLL_HPS
IOUT
HPS PLL analog power supply
DC output current per pin
V
mA
°C
°C
TJ
Operating junction temperature
Storage temperature (No bias)
–55
125
TSTG
–65
150
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 3
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time
over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the
lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years.
Table 2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime.
Table 2. Maximum Allowed Overshoot During Transitions for Arria V Devices
Symbol Description Condition (V)
Overshoot Duration as % of High Time
Unit
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
3.8
3.85
3.9
100
68
45
28
15
13
11
9
3.95
4
4.05
4.1
4.15
AC input
voltage
Vi (AC)
4.2
4.25
4.3
8
7
5.4
3.2
1.9
1.1
0.6
0.4
0.2
4.35
4.4
4.45
4.5
4.55
4.6
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 4
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for
Arria V devices.
Table 3 lists the steady-state voltage values expected from Arria V devices. Power
supply ramps must all be strictly monotonic, without plateaus.
Table 3. Recommended Operating Conditions for Arria V Devices (Part 1 of 2)
Symbol
VCC
Description
Condition
Minimum
1.07
Typical
1.1
Maximum Unit
–C4, –I5, –C5, –C6
1.13
1.18
V
V
V
V
V
V
V
V
V
Core voltage power supply
–I3
1.12
1.15
1.1
–C4, –I5, –C5, –C6
1.07
1.13
Periphery circuitry, PCIe hard IP block, and
transceiver PCS power supply
VCCP
–I3
—
—
—
—
—
1.12
1.15
3.3
1.18
Configuration pins (3.3 V) power supply
Configuration pins (3.0 V) power supply
Configuration pins (2.5 V) power supply
Configuration pins (1.8 V) power supply
Auxiliary supply
3.135
2.85
3.465
3.15
3.0
VCCPGM
2.375
1.71
2.5
2.625
1.89
1.8
VCC_AUX
2.375
2.5
2.625
Battery back-up power supply
(For design security volatile key register)
(1)
VCCBAT
—
1.2
—
3.0
V
I/O pre-driver (3.3 V) power supply
I/O pre-driver (3.0 V) power supply
I/O pre-driver (2.5 V) power supply
I/O buffers (3.3 V) power supply
I/O buffers (3.0 V) power supply
I/O buffers (2.5 V) power supply
I/O buffers (1.8 V) power supply
I/O buffers (1.5 V) power supply
I/O buffers (1.35 V) power supply
I/O buffers (1.25 V) power supply
I/O buffers (1.2 V) power supply
PLL digital voltage regulator power supply
PLL analog voltage regulator power supply
DC input voltage
—
3.135
2.85
2.375
3.135
2.85
2.375
1.71
1.425
1.283
1.19
1.14
1.425
2.375
–0.5
0
3.3
3.0
2.5
3.3
3.0
2.5
1.8
1.5
1.35
1.25
1.2
1.5
2.5
—
3.465
3.15
2.625
3.465
3.15
2.625
1.89
1.575
1.418
1.31
1.26
1.575
2.625
3.6
V
V
(2)
VCCPD
—
—
V
—
V
—
V
—
V
—
V
VCCIO
—
V
—
V
—
V
—
V
VCCD_FPLL
VCCA_FPLL
VI
—
—
V
V
—
V
VO
Output voltage
—
—
VCCIO
85
V
Commercial
Industrial
0
—
°C
°C
TJ
Operating junction temperature
–40
—
100
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 5
Table 3. Recommended Operating Conditions for Arria V Devices (Part 2 of 2)
Symbol
Description
Condition
Standard POR
Fast POR
Minimum
200 µs
Typical
—
Maximum Unit
100 ms
4 ms
—
—
(3)
tRAMP
Power supply ramp time
200 µs
—
Notes to Table 3:
(1) If you do not use the design security feature in Arria V devices, connect VCCBAT to a 1.5-V, 2.5-V or 3.0-V power supply. Arria V power-on reset (POR)
circuitry monitors VCCBAT. Arria V devices do not exit POR if VCCBAT is not powered up.
(2) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO is 3.3 V.
(3) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP
specifications for fast POR when HPS_PORSEL = 1.
Table 4 lists recommended operating conditions for Arria V transceiver power
supplies.
Table 4. Transceiver Power Supply Operating Conditions for Arria V Devices
Symbol
VCCA_GXBL
VCCA_GXBR
VCCR_GXBL
VCCR_GXBR
VCCR_GXBL
VCCR_GXBR
VCCT_GXBL
VCCT_GXBR
VCCT_GXBL
VCCT_GXBR
VCCH_GXBL
VCCH_GXBR
VCCL_GXBL
VCCL_GXBR
VCCL_GXBL
VCCL_GXBR
Note to Table 4:
Description
Minimum
Typical
Maximum Unit
Transceiver high voltage power (left side)
2.375
2.500
2.625
V
V
V
V
V
V
V
V
Transceiver high voltage power (right side)
GX and SX speed grades—receiver power (left side)
GX and SX speed grades—receiver power (right side)
GT and ST speed grades—receiver power (left side)
GT and ST speed grades—receiver power (right side)
GX and SX speed grades—transmitter power (left side)
GX and SX speed grades—transmitter power (right side)
GT and ST speed grades—transmitter power (left side)
GT and ST speed grades—transmitter power (right side)
Transmitter output buffer power (left side)
1.08/1.12 1.1/1.15 (1) 1.14/1.18
1.17
1.20
1.23
1.08/1.12 1.1/1.15 (1) 1.14/1.18
1.17
1.20
1.23
1.425
1.500
1.575
Transmitter output buffer power (right side)
GX and SX speed grades—clock network power (left side)
GX and SX speed grades—clock network power (right side)
GT and ST speed grades—clock network power (left side)
GT and ST speed grades—clock network power (right side)
1.08/1.12 1.1/1.15 (1) 1.14/1.18
1.17
1.20
1.23
(1) For data rate <=3.2 Gbps, connect VCCR_GXBL/R, VCCT_GXBL/R, or VCCL_GXBL/R to either 1.1-V or 1.15-V power supply. For data rate >3.2 Gbps,
connect VCCR_GXBL/R, VCCT_GXBL/R, or VCCL_GXBL/R to a 1.15-V power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin
Connection Guidelines.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 6
Electrical Characteristics
Table 5 lists the steady-state voltage and current values expected from Arria V
system-on-a-chip (SoC) devices with ARM®-based hard processor system (HPS).
Power supply ramps must all be strictly monotonic, without plateaus.
Table 5. HPS Power Supply Operating Conditions for Arria V SX and ST Devices (1)
Symbol
VCC_HPS
Description
Minimum
1.07
Typical
1.1
3.3
3.0
2.5
3.3
3.0
2.5
1.8
1.5
1.35
1.2
3.3
3.0
2.5
1.8
2.5
2.5
Maximum
1.13
Unit
V
HPS Core voltage and periphery circuitry power supply
HPS I/O pre-driver (3.3 V) power supply
HPS I/O pre-driver (3.0 V) power supply
HPS I/O pre-driver (2.5 V) power supply
HPS I/O buffers (3.3 V) power supply
HPS I/O buffers (3.0 V) power supply
HPS I/O buffers (2.5 V) power supply
HPS I/O buffers (1.8 V) power supply
HPS I/O buffers (1.5 V) power supply
3.135
2.85
3.465
3.15
V
(2)
VCCPD_HPS
V
2.375
3.135
2.85
2.625
3.465
3.15
V
V
V
2.375
1.71
2.625
1.89
V
VCCIO_HPS
V
1.425
1.283
1.14
1.575
1.418
1.26
V
(3)
HPS I/O buffers (1.35 V) power supply
V
HPS I/O buffers (1.2 V) power supply
V
HPS reset and clock input pins (3.3 V) power supply
HPS reset and clock input pins (3.0 V) power supply
HPS reset and clock input pins (2.5 V) power supply
HPS reset and clock input pins (1.8 V) power supply
HPS PLL analog voltage regulator power supply
3.135
2.85
3.465
3.15
V
V
VCCRSTCLK_HPS
2.375
1.71
2.625
1.89
V
V
VCCPLL_HPS
2.375
2.375
2.625
2.625
V
VCC_AUX_SHARED HPS and FPGA shared auxiliary power supply
V
Notes to Table 5:
(1) Refer to Table 3 for the steady-state voltage values expected from the FPGA portion of the Arria V SoC devices.
(2) VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when
CCIO_HPS is 3.3 V.
(3) VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.
V
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 7
DC Characteristics
This section lists the following specifications:
■
■
■
■
■
■
Supply Current and Power Consumption
I/O Pin Leakage Current
Bus Hold Specifications
OCT Specifications
Pin Capacitance
Hot Socketing
Supply Current and Power Consumption
Standby current is the current drawn from the respective power rails used for power
budgeting.
Altera offers two ways to estimate power for your design—the Excel-based Early
Power Estimator (EPE) and the Quartus® II PowerPlay Power Analyzer feature.
Use the Excel-based Early Power Estimator (EPE) before you start your design to
estimate the supply current for your design. The EPE provides a magnitude estimate
of the device power because these currents vary greatly with the resources you use.
The Quartus II PowerPlay Power Analyzer provides better quality estimates based on
the specifics of the design after you complete place-and-route. The PowerPlay Power
Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yields very
accurate power estimates.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
I/O Pin Leakage Current
Table 6 lists the Arria V I/O pin leakage current specifications.
Table 6. I/O Pin Leakage Current for Arria V Devices
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
–30
–30
Typ
—
Max
30
Unit
µA
—
30
µA
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 8
Electrical Characteristics
Bus Hold Specifications
Table 7 lists the Arria V device bus hold specifications. The bus-hold trip points are
based on calculated input voltages from the JEDEC standard.
Table 7. Bus Hold Parameters for Arria V Devices
V
CCIO (V)
Parameter Symbol Conditions
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max
Min
Max
Min Max Min Max Min Max Min Max
Bus-hold,
low,
sustaining
current
VIN > VIL
(max.)
ISUSL
ISUSH
IODL
8
—
—
12
—
30
–30
—
—
—
50
–50
—
—
—
70
–70
—
—
—
70
-70
—
—
—
µA
µA
µA
Bus-hold,
high,
sustaining
current
VIN < VIH
(min.)
–8
—
–12
—
—
Bus-hold,
low,
overdrive
current
0V < VIN
VCCIO
<
125
175
-175
200
-200
300
500
500
Bus-hold,
high,
overdrive
current
0V < VIN
VCCIO
<
IODH
—
-125
0.9
—
—
—
-300
1.7
—
-500
2
—
-500 µA
Bus-hold
trip point
VTRIP
—
0.3
0.375 1.125 0.68 1.07 0.7
0.8
0.8
2
V
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 9
OCT Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically
performed at power up for I/Os connected to the calibration block.
Table 8 lists the Arria V OCT termination calibration accuracy specifications. The OCT
calibration accuracy is valid at the time of calibration only.
Table 8. OCT Calibration Accuracy Specifications for Arria V Devices
Calibration Accuracy
Symbol
Description
Conditions (V)
Unit
%
I3, C4
I5, C5
C6
Internal series termination
with calibration
(25-Ωsetting)
V
V
CCIO = 3.0, 2.5, 1.8,
1.5, 1.2
25-ΩRS
50-ΩRS
15
15
15
15
15
Internal series termination
with calibration
(50-Ωsetting)
CCIO = 3.0, 2.5, 1.8,
1.5, 1.2
15
15
15
15
%
Internal series termination
with calibration
(34-Ωand 40-Ωsetting)
VCCIO = 1.5, 1.35,
1.25, 1.2
34-Ωand 40-ΩRS
%
Internal series termination
with calibration
(48-Ω, 60-Ω, and 80-Ω
setting)
48-Ω, 60-Ω, and
80-ΩRS
VCCIO = 1.2
15
15
15
%
%
Internal parallel
termination with
calibration (50-Ωsetting)
V
CCIO = 2.5, 1.8, 1.5,
1.2
50-ΩRT
–10 to +40 –10 to +40 –10 to +40
Internal parallel
termination with
calibration
(20-Ω, 30-Ω, 40-Ω,
60-Ω, and 120-Ωsetting)
20-Ω, 30-Ω,
40-Ω,60-Ω, and
120-ΩRT
VCCIO = 1.5, 1.35, 1.25 –10 to +40 –10 to +40 –10 to +40
%
Internal parallel
termination with
calibration
60-Ωand 120-Ω RT
VCCIO = 1.2
–10 to +40 –10 to +40 –10 to +40
%
%
(60-Ωand 120-Ωsetting)
Internal left shift series
termination with
calibration
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2
25-ΩRS_left_shift
15
15
15
(25-ΩRS_left_shift setting)
1
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and
on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration,
the tolerance may change.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 10
Electrical Characteristics
Table 9 lists the Arria V OCT without calibration resistance tolerance to PVT changes.
Table 9. OCT Without Calibration Resistance Tolerance Specifications for Arria V Devices
Resistance Tolerance
Symbol
Description
Conditions (V)
VCCIO = 3.0 and 2.5
VCCIO = 1.8 and 1.5
VCCIO = 1.2
Unit
%
I3, C4
I5, C5
C6
Internal series termination
without calibration
(25-Ωsetting)
25-ΩRS
30
30
35
30
30
40
40
Internal series termination
without calibration
(25-Ωsetting)
25-ΩRS
25-ΩRS
50-ΩRS
50-ΩRS
40
50
40
40
40
50
40
40
%
Internal series termination
without calibration
(25-Ωsetting)
%
Internal series termination
without calibration (50-Ω
setting)
V
CCIO = 3.0 and 2.5
%
Internal series termination
without calibration
(50-Ωsetting)
VCCIO = 1.8 and 1.5
%
Internal series termination
without calibration
(50-Ωsetting)
50-Ω RS
VCCIO = 1.2
VCCIO = 2.5
35
25
50
40
50
40
%
%
Internal differential
termination (100-Ωsetting)
100-Ω RD
Use Table 10 to determine the OCT variation after power-up calibration and
Equation 1 to determine the OCT variation without recalibration.
Equation 1. OCT Variation Without Recalibration (1), (2), (3), (4), (5), (6)
dR
dT
dR
dV
⎛
⎞
------
-------
× ΔV〉
ROCT = RSCAL 1 + 〈
× ΔT〉 〈
⎝
⎠
Notes to Equation 1:
(1) The ROCT value calculated from Equation 1 shows the range of OCT resistance with the variation of temperature and
VCCIO
.
(2) RSCAL is the OCT resistance value at power-up.
(3) ΔT is the variation of temperature with respect to the temperature at power up.
(4) ΔV is the variation of voltage with respect to the VCCIO at power up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 11
Table 10 lists OCT variation with temperature and voltage after power-up calibration.
The OCT variation is valid for a VCCIO range of 5% and a temperature range of 0° to
85°C.
Table 10. OCT Variation after Power-Up Calibration for Arria V Devices
Symbol
Description
V
CCIO (V)
3.0
Value
0.100
0.100
0.100
0.100
0.150
0.150
0.150
0.189
0.208
0.266
0.273
0.200
0.200
0.317
Unit
2.5
1.8
OCT variation with voltage without
recalibration
dR/dV
1.5
%/mV
1.35
1.25
1.2
3.0
2.5
1.8
OCT variation with temperature
without recalibration
dR/dT
1.5
%/°C
1.35
1.25
1.2
Pin Capacitance
Table 11 lists the Arria V pin capacitance.
Table 11. Pin Capacitance for Arria V Devices
Symbol
CIOTB
Description
Value
Unit
pF
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
6
6
CIOLR
pF
COUTFB
CIOVREF
Input capacitance on dual-purpose clock output/feedback pins
Input capacitance on REF pins
6
pF
V
48
pF
Hot Socketing
Table 12 lists the hot socketing specifications for Arria V devices.
Table 12. Hot Socketing Specifications for Arria V Devices
Symbol
IIOPIN (DC)
Description
DC current per I/O pin
Maximum
300 μA
(1)
IIOPIN (AC)
AC current per I/O pin
8 mA
DC current per transceiver transmitter (TX)
pin
IXCVR-TX (DC)
100 mA
50 mA
IXCVR-RX (DC)
DC current per transceiver receiver (RX) pin
Note to Table 12:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 12
Electrical Characteristics
Internal Weak Pull-Up Resistor
Table 13 lists the weak pull-up resistor values for Arria V devices.
All I/O pins have an option to enable weak pull-up except the configuration, test, and
JTAG pins. For more information about the pins that support internal weak pull-up
and internal weak pull-down features, refer to the Arria V GT, GX, ST, and SX Device
Family Pin Connection Guidelines.
Table 13. Internal Weak Pull-Up Resistor Values for Arria V Devices
Symbol
Description
Conditions (V) (1)
Value (2) Unit
VCCIO = 3.3 5%
25
25
25
25
25
25
25
25
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
VCCIO = 3.0 5%
VCCIO = 2.5 5%
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
V
CCIO = 1.8 5%
CCIO = 1.5 5%
RPU
V
V
V
CCIO = 1.35 5%
CCIO = 1.25 5%
VCCIO = 1.2 5%
Notes to Table 13:
(1) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
(2) Valid with 10% tolerances to cover changes over PVT.
.
I/O Standard Specifications
Table 14 through Table 19 list the input voltage (VIH and VIL), output voltage (VOH and
OL), and current drive characteristics (IOH and IOL) for various I/O standards
V
supported by Arria V devices.
For an explanation of terms used in Table 14 through Table 19, refer to “Glossary” on
page 1–64.
Table 14. Single-Ended I/O Standards for Arria V Devices (Part 1 of 2)
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
(1)
(1)
IOL
IOH
I/O Standard
(mA) (mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
3.3-V LVTTL
3.135
3.3
3.465 –0.3
0.8
1.7
3.6
0.45
2.4
4
2
–4
–2
3.3-V
LVCMOS
3.135
2.85
2.85
3.3
3
3.465 –0.3
0.8
0.8
1.7
1.7
1.7
3.6
3.6
3.6
0.2
0.4
0.2
VCCIO – 0.2
2.4
3.0-V LVTTL
3.15
3.15
–0.3
–0.3
2
–2
3.0-V
LVCMOS
3
0.8
V
CCIO – 0.2
0.1
–0.1
3.0-V PCI
3.0-V PCI-X
2.5 V
2.85
2.85
3
3
3.15
3.15
—
—
0.3 x VCCIO
0.5 x VCCIO VCCIO + 0.3 0.1 x VCCIO
0.9 x VCCIO
0.9 x VCCIO
2
1.5
1.5
1
–0.5
–0.5
–1
0.35 x VCCIO 0.5 x VCCIO VCCIO + 0.3 0.1 x VCCIO
2.375
2.5
2.625 –0.3
1.89 –0.3 0.35 x VCCIO
1.575 –0.3 0.35 x VCCIO
0.7
1.7
3.6
0.4
0.65 x
VCCIO
1.8 V
1.5 V
1.71
1.8
1.5
VCCIO + 0.3
0.45
VCCIO – 0.45
2
2
–2
–2
0.65 x
VCCIO
1.425
VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 13
Table 14. Single-Ended I/O Standards for Arria V Devices (Part 2 of 2)
VCCIO (V)
Typ
VIL (V)
Max
VIH (V)
VOL (V)
Max
VOH (V)
Min
(1)
(1)
IOL
IOH
I/O Standard
(mA) (mA)
Min
Max
Min
Min
Max
0.65 x
VCCIO
1.2 V
1.14
1.2
1.26
–0.3 0.35 x VCCIO
VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO
2
–2
Note to Table 14:
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4 mA), you
should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook.
Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria V Devices
VCCIO(V)
Typ
VREF(V)
Typ
VTT(V)
Typ
I/O Standard
Min
Max
Min
Max
Min
Max
SSTL-2
Class I, II
2.375
2.5
1.8
2.625
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO
0.833 0.9 0.969
VREF – 0.04
VREF
VREF
VREF + 0.04
SSTL-18
Class I, II
1.71
1.425
1.283
1.19
1.89
1.575
1.418
1.26
V
REF – 0.04
VREF + 0.04
SSTL-15
Class I, II
1.5
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO
0.5 x VCCIO 0.51 x VCCIO
0.5 x VCCIO 0.51 x VCCIO
0.5 x VCCIO 0.51 x VCCIO
SSTL-135
Class I, II
1.35
1.25
1.8
SSTL-125
Class I, II
HSTL-18
Class I, II
1.71
1.89
0.85
0.68
0.9
0.95
0.9
—
—
VCCIO/2
CCIO/2
—
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.75
V
HSTL-12
Class I, II
1.14
1.14
1.2
1.2
1.26
1.3
0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO
0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO
—
—
VCCIO/2
—
—
—
HSUL-12
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V Devices (Part 1 of 2)
VIL(DC) (V)
VIH(DC) (V)
Min Max
VREF
VIL(AC) (V) VIH(AC) (V)
Max Min
VOL (V)
Max
VOH (V)
Min
(1)
(1)
Iol
Ioh
I/O Standard
(mA)
8.1
16.2
6.7
13.4
8
(mA)
–8.1
–16.2
–6.7
–13.4
–8
Min
Max
SSTL-2
Class I
VREF
–0.15
+
VCCIO
0.3
+
+
+
+
VREF
0.31
–
–0.3
VREF + 0.31 VTT – 0.608 VTT + 0.608
VREF + 0.31 VTT – 0.81 VTT + 0.81
VREF + 0.25 VTT – 0.603 VTT + 0.603
0.15
SSTL-2
Class II
VREF
–0.15
VREF
0.15
+
VCCIO
0.3
VREF
0.31
–
–0.3
–0.3
–0.3
—
SSTL-18
Class I
VREF
–0.125
VREF
0.125
+
VCCIO
0.3
VREF
0.25
–
SSTL-18
Class II
VREF
–0.125
VREF
0.125
+
VCCIO
0.3
VREF
0.25
–
VREF + 0.25
VREF
0.28
VCCIO –0.28
0.8 x VCCIO
0.8 x VCCIO
SSTL-15
Class I
VREF
0.1
–
VREF
0.1
+
+
VREF
–
+
—
—
0.2 x VCCIO
0.2 x VCCIO
0.175
0.175
SSTL-15
Class II
VREF
0.1
–
VREF
0.1
VREF
0.175
–
VREF
0.175
+
—
16
–16
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 14
Electrical Characteristics
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V Devices (Part 2 of 2)
VIL(DC) (V)
VIH(DC) (V)
Min Max
VREF
VIL(AC) (V) VIH(AC) (V)
Max Min
VOL (V)
Max
VOH (V)
Min
(1)
(1)
Iol
Ioh
I/O Standard
(mA)
—
—
8
(mA)
Min
Max
VREF
0.09
–
+
VREF
0.16
–
SSTL-135
SSTL-125
—
—
—
—
—
—
—
VREF + 0.16 0.2 x VCCIO
VREF + 0.15 0.2 x VCCIO
0.8 x VCCIO
0.8 x VCCIO
VCCIO – 0.4
VCCIO – 0.4
VCCIO – 0.4
VCCIO –0.4
—
0.09
VREF
0.85
–
VREF
+
VREF
0.15
–
—
—
—
0.85
HSTL-18
Class I
VREF
–0.1
VREF
0.1
+
VREF
0.2
–
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
0.4
0.4
0.4
0.4
–8
HSTL-18
Class II
VREF
0.1
–
VREF
0.1
+
+
+
+
VREF
0.2
–
–
–
–
—
16
8
–16
–8
HSTL-15
Class I
VREF
0.1
–
–
–
VREF
0.1
VREF
0.2
—
HSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
0.2
—
16
8
–16
–8
HSTL-12
Class I
VREF
VREF
VCCIO
+
+
VREF
–0.15
–0.15
—
VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO
VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO
0.08
VREF
0.08
VREF
0.13
0.08
VREF
0.08
VREF
0.13
0.15
0.15
HSTL-12
Class II
–
+
VCCIO
0.15
VREF
–
16
—
–16
—
0.15
–
+
VREF
0.22
–
HSUL-12
—
VREF + 0.22 0.1 x VCCIO
0.9 x VCCIO
Note to Table 16:
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA),
you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook.
Table 17. Differential SSTL I/O Standards for Arria V Devices
VCCIO (V)
Typ
VSWING(DC) (V)
VX(AC) (V)
Typ
VSWING(AC) (V)
I/O Standard
Min
Max
Min
Max
Min
Max
Min
Max
VCCIO
0.6
+
VCCIO/2 –
0.2
VCCIO/2 +
0.2
VCCIO
0.6
+
SSTL-2 Class I, II
SSTL-18 Class I, II
2.375
2.5
1.8
1.5
2.625
0.3
—
—
0.62
VCCIO
0.6
+
VCCIO/2 –
0.175
VCCIO/2 +
0.175
VCCIO
0.6
+
1.71
1.89
1.575
1.45
0.25
0.2
0.5
VCCIO/2 –
0.15
VCCIO/2 + 2(VIH(AC)
0.15 VREF
–
–
–
2(VIL(AC)
VREF
–
–
–
(1)
(1)
(1)
SSTL-15 Class I, II 1.425
—
)
)
VCCIO/2 –
0.15
V
CCIO/2 + 2(VIH(AC)
0.15 VREF
2(VIL(AC)
VREF
SSTL-135
1.283 1.35
1.19 1.25
0.18
0.18
VCCIO/2
VCCIO/2
)
)
VCCIO/2 –
0.15
V
CCIO/2 + 2(VIH(AC)
0.15 VREF
2(VIL(AC)
VREF
SSTL-125
1.31
)
)
Note to Table 17:
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits
(VIH(DC) and VIL(DC)).
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 15
Table 18. Differential HSTL and HSUL I/O Standards for Arria V Devices
VCCIO (V)
Typ
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
I/O
Standard
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
HSTL-18
Class I, II
1.71
1.8
1.5
1.2
1.89
0.2
0.2
—
0.78
—
—
1.12
0.78
—
—
1.12
0.4
—
HSTL-15
Class I, II
1.425
1.14
1.575
1.26
—
0.68
—
0.9
—
0.68
0.9
0.4
0.3
—
HSTL-12
Class I, II
VCCIO
+ 0.3
0.5 x
VCCIO
0.4 x V 0.5 x V 0.6 x
VCCIO
VCCIO
+ 0.48
0.16
CCIO
CCIO
0.5 x
VCCIO
+0.12
0.5 x VCCIO 0.5 x
– 0.12 VCCIO
0.4 x V 0.5 x V 0.6 x
VCCIO
HSUL-12
1.14
1.2
1.3
0.26 0.26
0.44
0.44
CCIO
CCIO
Table 19. Differential I/O Standard Specifications for Arria V Devices
(2)
(2), (7)
VCCIO (V)
VID (mV) (1)
VICM(DC) (V)
Condition
VOD (V)
VOCM (V)
I/O Standard
Min Typ Max Min Condition Max Min
Max Min Typ Max Min Typ Max
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For
PCML
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 20 and Table 21.
DMAX
≤1.25 Gbps
—
—
—
0.05
1.05
0.25
1.80
1.55
1.45
2.5 V LVDS
VCM
1.25 V
=
2.375 2.5 2.625 100
0.247
0.1
—
0.6 1.125 1.25 1.375
(3)
DMAX
>1.25 Gbps
RSDS (HIO)
VCM =
1.25 V
2.375 2.5 2.625 100
2.375 2.5 2.625 200
—
—
0.2 0.6
0.5
1
1.2
1.2
1.4
1.4
(4)
Mini-LVDS
(HIO) (5)
—
600 0.300
1.425 0.25
—
—
0.6
—
DMAX
≤700 Mbps
0.60
—
1.80
—
1.60
LVPECL (6)
2.375 2.5 2.625 300
—
—
—
—
DMAX
>700 Mbps
1.00
Notes to Table 19:
(1) The minimum VID value is applicable over the entire common mode range, VCM
.
(2) RL range: 90 ≤RL ≤110 Ω.
(3) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0V to 1.6V for data rates above 1.25 Gbps and 0 V to 1.85 V for
data rates below 1.25 Gbps.
(4) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.
(5) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V.
(6) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to
1.95 V for data rates below 700 Mbps.
(7) This applies to default pre-emphasis setting only.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 16
Switching Characteristics
Switching Characteristics
This section provides performance characteristics of Arria V core and periphery
blocks for commercial grade devices.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 20 and Table 21 list the Arria V transceiver specifications.
Table 20. Transceiver Specifications for Arria V GX and SX Devices (Part 1 of 4)
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Min Typ Max Min Typ Max
Symbol/
Description
Conditions
Unit
Reference Clock
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2), HCSL, and
Supported I/O Standards
LVDS
Input frequency from REFCLK
input pins
—
27
—
—
—
710
400
27
—
—
—
710
400
MHz
ps
20% to 80% of
rising clock edge
Rise time
80% to 20% of
falling clock edge
Fall time
—
45
—
—
—
400
55
—
45
—
—
—
400
55
ps
%
Duty cycle
—
Peak-to-peak differential
input voltage
300/
300/
—
200
200
mV
2000 (3)
2000 (3)
Spread-spectrummodulating
clock frequency
PCI Express®
(PCIe®)
30
—
—
33
—
30
—
—
33
—
kHz
—
0 to
–0.5%
100
0 to
–0.5%
100
Spread-spectrum
downspread
PCIe
On-chip termination resistors
—
—
—
—
—
—
—
—
—
—
Ω
1.1/1.15
1.1/1.15
VICM (AC coupled)
V
(4)
(4)
HCSL I/O standard
for the PCIe
VICM (DC coupled)
250
—
550
250
—
550
mV
reference clock
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Transmitter REFCLK Phase
Noise (1)
-110
-120
-120
-130
-110
-120
-120
-130
10 KHz
100 KHz
≥1 MHz
2000
1%
2000
1%
RREF
—
—
—
—
—
Ω
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 17
Table 20. Transceiver Specifications for Arria V GX and SX Devices (Part 2 of 4)
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Transceiver Clocks
PCIe
Receiver Detect
fixedclkclock frequency
—
75
125
—
—
—
75
125
—
—
MHz
MHz
Transceiver Reconfiguration
Controller IP
—
125
125
(mgmt_clk_clk) clock
frequency
Receiver
Supported I/O Standards
Data rate (14)
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
—
—
611
—
6553.6
611
—
3125
1.2
Mbps
V
Absolute VMAX for a receiver
—
—
1.2
—
—
(5)
pin
Absolute VMIN for a receiver
pin
—
—
–0.4
—
—
—
—
–0.4
—
—
—
—
V
V
Maximum peak-to-peak
differential input voltage VID
(diff p-p) before device
configuration
1.6
1.6
Maximum peak-to-peak
differential input voltage VID
(diff p-p) after device
configuration
—
—
—
—
2.2
—
—
—
2.2
V
Minimum differential eye
opening at the receiver serial
—
—
85
—
—
—
85
—
—
—
mV
mV
(6)
input pins
650/800
650/800
VICM (AC coupled)
VICM (DC coupled)
(7)
(7)
≤ 3.2 Gbps (8)
85-Ωsetting
100-Ωsetting
120-Ωsetting
150-Ωsetting
—
670
—
—
—
—
—
4
700
85
730
—
—
—
—
10
—
—
—
670
—
—
—
—
—
4
700
85
730
—
—
—
—
10
—
—
—
mV
Ω
100
120
150
—
100
120
150
—
Ω
Differential on-chip
termination resistors
Ω
Ω
(9)
tLTR
µs
µs
µs
µs
(10)
tLTD
—
—
—
(11)
tLTD_manual
—
4
—
4
—
(12)
tLTR_LTD_manual
—
15
—
15
—
Programmable ppm detector
—
—
62.5, 100, 125, 200, 250, 300, 500, and 1000
200 200
ppm
UI
(13)
Run Length
—
—
—
—
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 18
Switching Characteristics
Table 20. Transceiver Specifications for Arria V GX and SX Devices (Part 3 of 4)
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Symbol/
Description
Conditions
Unit
Max
Min
Typ
Max
Min
Typ
AC gain setting =
0 to 3 (16)
Programmable equalization
(AC) and DC gain
Refer to Figure 1 and Figure 2
dB
DC gain setting =
0 to 1
Transmitter
Supported I/O standards
Data rate
1.5 V PCML
—
611
—
—
6553.6
—
611
—
—
3125
—
Mbps
mV
mV
Ω
VOCM (AC coupled)
—
650
700
85
650
700
85
VOCM (DC coupled)
≤ 3.2 Gbps (8)
85-Ωsetting
100-Ωsetting
120-Ωsetting
150-Ωsetting
670
—
730
—
670
—
730
—
—
100
120
150
—
—
100
120
150
—
Ω
Differential on-chip
termination resistors
—
—
—
—
Ω
—
—
—
—
Ω
TX VCM = 0.65 V
(AC coupled) and
slew rate of 15 ps
Intra-differential pair skew
—
—
—
—
—
—
15
—
—
—
—
—
—
15
ps
ps
ps
Intra-transceiver block
transmitter channel-to-
channel skew
x6 PMA bonded
mode
180
500
180
500
Inter-transceiver block
transmitter channel-to-
channel skew (15)
xN PMA bonded
mode
CMU PLL
Supported data range
fPLL supported data range
—
—
611
611
—
—
6553.6
3125
611
611
—
—
3125
3125
Mbps
Mbps
Transceiver-FPGA Fabric Interface
Interface speed
(single-width mode)
—
25
—
187.5
25
—
187.5
MHz
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 19
Table 20. Transceiver Specifications for Arria V GX and SX Devices (Part 4 of 4)
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Interface speed (double-
width mode)
—
25
—
163.84
25
—
163.84
MHz
Notes to Table 20:
(1) The transmitter REFCLKphase jitter is 30 ps p-p at bit error rate (BER) 10-12
.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link.
(4) For data rate <=3.2 Gbps, connect VCCR_GXBL/R to either 1.1-V or 1.15-V power supply. For data rate >3.2 Gbps, connect VCCR_GXBL/R to a 1.15-V
power supply. For details, refer to the Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines.
(5) The device cannot tolerate prolonged operation at this absolute maximum.
(6) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you
enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(7) The AC coupled VICM is 650 mV for PCIe mode only.
(8) For standard protocol compliance, use AC coupling.
(9) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(10) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
(11) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the
CDR is functioning in the manual mode.
(12) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when
the CDR is functioning in the manual mode.
(13) The rate match FIFO supports only up to 300 parts per million (ppm).
(14) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
(15) This specification is only applicable to channels on one side of the device across two transceiver banks.
(16) The Quartus II software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 20
Switching Characteristics
Table 21. Transceiver Specifications for Arria V GT and ST Devices (Part 1 of 3)
Transceiver Speed Grade 3
Symbol/
Description
Conditions
Unit
Max
Min
Typ
Reference Clock
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2)
HCSL, and LVDS
,
Supported I/O Standards
Input frequency from REFCLKinput pins
Rise time
—
27
—
710
MHz
20% to 80% of rising clock
edge
—
—
400
ps
80% to 20% of falling clock
edge
Fall time
—
45
—
—
—
400
55
ps
%
Duty cycle
—
300/2000
Peak-to-peak differential input voltage
—
200
mV
(3)
Spread-spectrum modulating clock
frequency
PCI Express (PCIe)
PCIe
30
—
—
33
—
kHz
—
0 to
–0.5%
100
Spread-spectrum downspread
On-chip termination resistors
—
—
—
—
—
—
Ω
VICM (AC coupled)
1.2
V
HCSL I/O standard for the
VICM (DC coupled)
250
—
550
mV
PCIe reference clock
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Transmitter REFCLK Phase Noise (1)
-110
-120
-120
-130
10 KHz
100 KHz
≥1 MHz
2000
1%
RREF
—
—
—
Ω
Transceiver Clocks
fixedclkclock frequency
Transceiver Reconfiguration Controller IP
PCIe Receiver Detect
—
—
75
125
—
—
MHz
MHz
125
(mgmt_clk_clk) clock frequency
Receiver
Supported I/O Standards
Data rate (6-Gbps Transceiver) (15)
Data rate (10-Gbps transceiver) (15)
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
—
—
—
—
611
0.611
—
—
—
—
—
6553.6
10.3125
1.2
Mbps
Gbps
V
(4)
Absolute VMAX for a receiver pin
Absolute VMIN for a receiver pin
–0.4
—
V
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 21
Table 21. Transceiver Specifications for Arria V GT and ST Devices (Part 2 of 3)
Transceiver Speed Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Maximum peak-to-peak differential input
voltage VID (diff p-p) before device
configuration
—
—
—
—
1.6
V
V
Maximum peak-to-peak differential input
voltage VID (diff p-p) after device
configuration
—
85
—
—
2.2
—
Minimum differential eye opening at the
—
—
mV
mV
(5)
receiver serial input pins
650/800
VICM (AC coupled)
VICM (DC coupled)
—
—
(6)
≤ 3.2 Gbps (7)
85-Ωsetting
100-Ωsetting
120-Ωsetting
150-Ωsetting
—
670
700
85
730
mV
Ω
100
120
150
—
Ω
Differential on-chip termination resistors
Ω
Ω
(8)
tLTR
—
4
10
—
—
—
µs
µs
µs
µs
(9)
tLTD
—
—
(10)
tLTD_manual
—
4
—
(11)
tLTR_LTD_manual
—
15
—
62.5, 100, 125, 200, 250, 300,
500, and 1000
(12)
Programmable ppm detector
—
ppm
UI
Run Length
—
—
—
200
AC gain setting = 0 to 3 (17)
Programmable equalization (AC)
and DC gain
Refer to Figure 1 and Figure 2
DC gain setting = 0 to 1
Transmitter
Supported I/O Standards
Data rate (6-Gbps transceiver)
Data rate (10-Gbps transceiver)
1.5 V PCML
—
611
0.611
—
—
—
6553.6
10.3125
—
Mbps
Gbps
mV
mV
Ω
—
V
OCM (AC coupled)
OCM (DC coupled)
—
650
700
85
V
≤3.2 Gbps (7)
85-Ωsetting
100-Ωsetting
120-Ωsetting
150-Ωsetting
670
—
730
—
—
100
120
150
—
Ω
Differential on-chip termination resistors
—
—
Ω
—
—
Ω
TX VCM = 0.65 V (AC
coupled) and slew rate of
15 ps
Intra-differential pair skew
—
—
15
ps
Intra-transceiver block transmitter
channel-to-channel skew
x6 PMA bonded mode
—
—
—
—
180
500
ps
ps
Inter-transceiver block transmitter
channel-to-channel skew (16)
xN PMA bonded mode
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 22
Switching Characteristics
Table 21. Transceiver Specifications for Arria V GT and ST Devices (Part 3 of 3)
Transceiver Speed Grade 3
Symbol/
Description
Conditions
Unit
Max
Min
Typ
CMU PLL
Supported data range
—
—
0.611
611
—
—
10.3125
3125
Gbps
Mbps
fPLL supported data range
Transceiver-FPGA Fabric Interface
153.6 (13)
161 (14)
,
Interface speed (PMA direct mode)
—
50
—
MHz
Interface speed
(single-width mode)
—
—
25
25
—
—
187.5
MHz
MHz
Interface speed (double-width mode)
163.84
Notes to Table 21:
(1) The transmitter REFCLKphase jitter is 30 ps p-p (5 ps RMS) with bit error rate (BER) 10-12, equivalent to 14 sigma.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you
enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(6) The AC coupled VICM is 650 mV for PCIe mode only.
(7) For standard protocol compliance, use AC coupling.
(8) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(9) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
(10) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the
CDR is functioning in the manual mode.
(11) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when
the CDR is functioning in the manual mode.
(12) The rate match FIFO supports only up to 300 ppm.
(13) The maximum frequency when core transceiver local routing is selected.
(14) The maximum frequency when core transceiver network routing (GCLK, RCLK, or PCLK) is selected.
(15) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
(16) This specification is only applicable to channels on one side of the device across two transceiver banks.
(17) The Quartus II software allows AC gain setting = 3 for design with data rate between 611 Mbps and 1.25 Gbps only.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 23
Figure 1 shows the continuous time-linear equalizer (CTLE) response at data rates
> 3.25 Gbps across supported AC gain and DC gain settings for Arria V GX, GT, SX,
and ST devices.
Figure 1. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST
Devices
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 24
Switching Characteristics
Figure 2 shows the CTLE response at data rates ≤3.25 Gbps across supported AC gain
and DC gain settings for Arria V GX, GT, SX, and ST devices.
Figure 2. CTLE Response at Data Rates ≤3.25 Gbps across Supported AC Gain and DC Gain for Arria V GX, GT, SX, and ST
Devices
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 25
Table 22 lists the TX VOD settings for Arria V transceiver channels.
Table 22. Typical TX VOD Setting for Arria V Transceiver Channels with termination of 100 Ω
VOD
VOD Value
(mV)
VOD
VOD Value
(mV)
Symbol
Setting (1)
Setting (1)
6 (2)
7 (2)
8 (2)
9
120
140
160
180
200
220
240
260
280
300
320
340
360
380
400
420
440
460
480
500
520
540
560
580
600
620
640
660
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
680
700
720
740
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
760
780
800
820
840
860
880
900
920
940
V
OD differential peak to peak
typical
960
980
1000
1020
1040
1060
1080
1100
1120
1140
1160
1180
1200
Notes to Table 22:
(1) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA
analog controls.
(2) Only valid for data rates ≤ 5 Gbps.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 26
Switching Characteristics
Table 23 lists the simulation data on the transmitter pre-emphasis levels in dB for the
first post tap under the following conditions:
■
low-frequency data pattern—five 1s and five 0s
data rate—2.5 Gbps
■
The levels listed are a representation of possible pre-emphasis levels under the
specified conditions only and the pre-emphasis levels may change with data pattern
and data rate.
Arria V devices only support 1st post tap pre-emphasis with the following conditions:
■
The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤60 where
|B| = VOD setting with termination value, RTERM = 100 Ωand |C| = 1st post tap
pre-emphasis setting
■
■
|B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates
> 5 Gbps.
(VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|.
Exception for PCIe Gen2 design:
OD setting = 43 and pre-emphasis setting = 19 are allowed for PCIe Gen2 design
V
with transmit de-emphasis –6dB setting (pipe_txdeemp= 1’b0) using Altera PCIe
Hard IP and PIPE megafunctions.
For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The
following conditions show that the 1st post tap pre-emphasis setting = 2 is a valid:
■
■
■
|B| + |C| ≤60 →40 + 2 = 42
|B| – |C| > 5 →40 – 2 = 38
(VMAX/VMIN – 1)% < 600% →(42/38 – 1)% = 10.52%
f
To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Arria V HSSI HSPICE models.
Table 23. Transmitter Pre-Emphasis Levels for Arria V Devices (Part 1 of 2)
Quartus II VOD Setting
35
Quartus II 1st Post Tap
Pre-Emphasis Setting
Unit
10
(200 mV)
20
(400 mV)
30
(600 mV) (700 mV)
40
45
50
(800 mV) (900 mV) (1000 mV)
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
dB
dB
dB
dB
dB
dB
dB
dB
dB
1.97
3.58
5.35
7.27
—
0.88
1.67
2.48
3.31
4.19
5.08
5.99
6.92
0.43
0.95
1.49
2
0.32
0.76
1.2
0.24
0.61
1
0.19
0.5
0.13
0.41
0.69
0.96
1.26
1.56
1.87
2.11
0.83
1.14
1.49
1.83
2.18
2.48
1.63
2.1
1.36
1.76
2.17
2.58
2.93
2.55
3.11
3.71
4.22
—
2.56
3.06
3.47
—
—
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 27
Table 23. Transmitter Pre-Emphasis Levels for Arria V Devices (Part 2 of 2)
Quartus II VOD Setting
Quartus II 1st Post Tap
Pre-Emphasis Setting
Unit
10
(200 mV)
20
(400 mV)
30
35
40
45
50
(600 mV)
(700 mV)
(800 mV)
(900 mV) (1000 mV)
9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.92
9.04
10.2
11.56
12.9
14.44
—
4.86
5.46
6.09
6.74
7.44
8.12
8.87
9.56
10.43
11.23
12.18
13.17
14.2
15.38
—
4
3.38
3.79
4.23
4.68
5.12
5.57
6.06
6.49
7.02
7.52
8.02
8.59
—
2.87
3.23
3.61
3.97
4.36
4.76
5.14
—
2.46
2.77
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
4.51
5.01
5.51
6.1
6.64
7.21
7.73
8.39
9.03
9.7
—
—
—
—
—
—
—
—
10.34
11.1
11.87
12.67
13.48
14.37
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 28
Switching Characteristics
Table 24 lists the physical medium attachment (PMA) specification compliance of all
supported protocol for Arria V GX, GT, SX, and ST devices. For more information
about the protocol parameter details and compliance specifications, contact your
Altera Sales Representative.
Table 24. Transceiver Compliance Specification for All Supported Protocol for Arria V GX, GT,
SX, and ST Devices (Part 1 of 2)
Protocol
Sub-protocol
PCIe Gen1
Data Rate (Mbps)
2,500
PCIe
XAUI
PCIe Gen2
5,000
PCIe Cable
2,500
XAUI 2135
3,125
SRIO 1250 SR
SRIO 1250 LR
SRIO 2500 SR
SRIO 2500 LR
SRIO 3125 SR
SRIO 3125 LR
SRIO 5000 SR
SRIO 5000 MR
SRIO 5000 LR
SRIO_6250_SR
SRIO_6250_MR
SRIO_6250_LR
CPRI E6LV
1,250
1,250
2,500
2,500
3,125
3,125
Serial RapidIO® (SRIO)
5,000
5,000
5,000
6,250
6,250
6,250
614.4
CPRI E6HV
614.4
CPRI E6LVII
CPRI E12LV
CPRI E12HV
CPRI E12LVII
CPRI E24LV
CPRI E24LVII
CPRI E30LV
CPRI E30LVII
CPRI E48LVII
CPRI E60LVII
CPRI E96LVIII (1)
GbE 1250
614.4
1,228.8
1,228.8
1,228.8
2,457.6
2,457.6
3,072
Common Public Radio Interface
(CPRI)
3,072
4,915.2
6,144
9,830.4
1,250
Gbps Ethernet (GbE)
OBSAI
OBSAI 768
768
OBSAI 1536
OBSAI 3072
OBSAI 6144
1,536
3,072
6,144
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 29
Table 24. Transceiver Compliance Specification for All Supported Protocol for Arria V GX, GT,
SX, and ST Devices (Part 2 of 2)
Protocol
Sub-protocol
SDI 270 SD
SDI 1485 HD
SDI 2970 3G
SONET 155
SONET 622
SONET 2488
GPON 155
Data Rate (Mbps)
270
Serial digital interface (SDI)
SONET
1,485
2,970
155.52
622.08
2,488.32
155.52
GPON 622
622.08
Gigabit-capable passive optical
network (GPON)
GPON 1244
GPON 2488
QSGMII 5000
1,244.16
2,488.32
5,000
QSGMII
Note to Table 24:
(1) You can achieve compliance with TX channel restriction of one HSSI channel per six-channel transceiver bank.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 30
Switching Characteristics
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks and temperature sensing diode specifications.
Clock Tree Specifications
Table 25 lists the clock tree specifications for Arria V devices.
Table 25. Clock Tree Performance for Arria V Devices
Performance
Parameter
–I3, –C4
Unit
–I5, –C5
625
–C6
525
350
Global clock and Regional clock
Peripheral clock
625
450
MHz
MHz
400
PLL Specifications
Table 26 lists the Arria V PLL block specifications. Arria V PLL block does not include
HPS PLL.
Table 26. PLL Specifications for Arria V Devices (Part 1 of 3)
Symbol
Parameter
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
(1)
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input clock frequency (–5 speed grade)
Input clock frequency (–6 speed grade)
Integer input clock frequency to the PFD
Fractional input clock frequency to the PFD
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
PLL VCO operating range (–5 speed grade)
PLL VCO operating range (–6 speed grade)
Input clock or external feedback clock input duty cycle
800
800
750
625
(1)
(1)
(1)
5
fIN
5
5
fINPFD
5
325
fFINPFD
50
600
600
600
600
40
160
1600
1600
1600
1300
60
(2)
fVCO
tEINDUTY
Output frequency for internal global or regional clock
(–3 speed grade)
(3)
—
—
—
—
—
—
—
—
500
500
500
400
MHz
MHz
MHz
MHz
Output frequency for internal global or regional clock
(–4 speed grade)
(3)
(3)
(3)
fOUT
Output frequency for internal global or regional clock
(–5 speed grade)
Output frequency for internal global or regional clock
(–6 speed grade)
(3)
(3)
(3)
(3)
Output frequency for external clock output (–3 speed grade)
Output frequency for external clock output (–4 speed grade)
Output frequency for external clock output (–5 speed grade)
Output frequency for external clock output (–6 speed grade)
Duty cycle for external clock output (when set to 50%)
—
—
—
—
45
—
—
—
—
50
670
670
622
500
MHz
MHz
MHz
MHz
%
fOUT_EXT
tOUTDUTY
55
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 31
Table 26. PLL Specifications for Arria V Devices (Part 2 of 3)
Symbol
tFCOMP
tDYCONFIGCLK
Parameter
Min
—
Typ
—
Max
10
Unit
ns
External feedback clock compensation time
Dynamic configuration clock for mgmt_clkand scanclk
—
—
100
MHz
Time required to lock from end-of-device configuration or
deassertion of areset
tLOCK
tDLOCK
—
—
—
—
1
1
ms
ms
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
—
—
—
—
10
—
—
0.3
1.5
4
—
—
MHz
MHz
fCLBW
PLL closed-loop medium bandwidth
(8)
PLL closed-loop high bandwidth
—
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
50
ps
Minimum pulse width on the aresetsignal
Input clock cycle-to-cycle jitter (FREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (FREF < 100 MHz)
—
ns
0.15
750
UI (p-p)
ps (p-p)
(4), (5)
tINCCJ
Period jitter for dedicated clock output in integer PLL
(FOUT ≥ 100 MHz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
175
ps (p-p)
mUI (p-p)
ps (p-p)
(6)
tOUTPJ_DC
Period jitter for dedicated clock output in integer PLL
(FOUT < 100 MHz)
17.5
Period jitter for dedicated clock output in fractional PLL
(FOUT ≥ 100 MHz)
250 (10)
,
175 (11)
(6)
tFOUTPJ_DC
tOUTCCJ_DC
tFOUTCCJ_DC
Period jitter for dedicated clock output in fractional PLL
(FOUT < 100 MHz)
25 (10)
,
mUI (p-p)
ps (p-p)
17.5 (11)
Cycle-to-cycle jitter for dedicated clock output in integer
PLL (FOUT ≥ 100 MHz)
175
(6)
Cycle-to-cycle jitter for dedicated clock output in integer
PLL (FOUT < 100 MHz)
17.5
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT ≥ 100 MHz)
250 (10)
175 (11)
,
(6)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT < 100 MHz)
25 (10)
,
mUI (p-p)
ps (p-p)
17.5 (11)
Period jitter for clock output on a regular I/O in integer PLL
(FOUT ≥ 100 MHz)
600
(6),
tOUTPJ_IO
(9)
Period jitter for clock output on a regular I/O in integer PLL
(FOUT < 100 MHz)
60
600
60
mUI (p-p)
ps (p-p)
Period jitter for clock output on a regular I/O in fractional
PLL (FOUT ≥ 100 MHz)
(6),
tFOUTPJ_IO
(9), (10)
Period jitter for clock output on a regular I/O in fractional
PLL (FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output on a regular I/O in
integer PLL (FOUT ≥ 100 MHz)
600
60
(6),
tOUTCCJ_IO
(9)
Cycle-to-cycle jitter for clock output on a regular I/O in
integer PLL (FOUT < 100 MHz)
mUI (p-p)
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 32
Switching Characteristics
Table 26. PLL Specifications for Arria V Devices (Part 3 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Cycle-to-cycle jitter for clock output on a regular I/O in
fractional PLL (FOUT ≥ 100 MHz)
—
—
600
ps (p-p)
(6),
tFOUTCCJ_IO
(9), (10)
Cycle-to-cycle jitter for clock output on a regular I/O in
fractional PLL (FOUT < 100 MHz)
—
—
—
—
—
—
—
60
mUI (p-p)
ps (p-p)
mUI (p-p)
%
Period jitter for dedicated clock output in cascaded PLLs
(FOUT ≥ 100 MHz)
175
17.5
tCASC_OUTPJ_DC
(6), (7)
Period jitter for dedicated clock output in cascaded PLLs
(FOUT < 100 MHz)
Frequency drift after PFDENAis disabled for a duration of
100 µs
tDRIFT
—
24
10
32
dKBIT
Bit number of Delta Sigma Modulator (DSM)
Numerator of fraction
8
bits
—
kVALUE
128
8388608 2147483648
5.96 0.023
fRES
Resolution of VCO frequency (fINPFD =100 MHz)
390625
Hz
Notes to Table 26:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) The voltage-controlled oscillator (VCO) frequency reported by the Quartus II software takes into consideration the VCO post-scale counter value.
Therefore, if the counter has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
K
K
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(5) FREF is fIN/N, specification applies when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Table 35 on page 1–39.
(7) The cascaded PLL specification is only applicable with the following conditions:
a. Upstream PLL: 0.59 MHz ≤Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which are available in Table 35 on page 1–39.
(10) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
DSP Block Specifications
Table 27 lists the Arria V DSP block performance specifications.
Table 27. DSP Block Performance Specifications for Arria V Devices (Part 1 of 2)
Performance
Mode
Unit
–I3, –C4
–I5, –C5
–C6
Modes using One DSP Block
Independent 9 x 9 Multiplication
370
370
370
370
310
370
370
310
310
310
310
250
310
310
220
220
220
220
200
220
220
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Independent 18 x 19 Multiplication
Independent 18 x 25 Multiplication
Independent 20 x 24 Multiplication
Independent 27 x 27 Multiplication
Two 18 x 19 Multiplier Adder Mode
18 x 18 Multiplier Added Summed with 36-bit Input
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 33
Table 27. DSP Block Performance Specifications for Arria V Devices (Part 2 of 2)
Performance
Mode
Unit
–I3, –C4
–I5, –C5
–C6
Modes using Two DSP Blocks
Complex 18 x 19 multiplication
370
310
220
MHz
Memory Block Specifications
Table 28 lists the Arria V memory block specifications.
To achieve the maximum memory block performance, use a memory block clock that
comes through global clock routing from an on-chip PLL and set to 50% output duty
cycle. Use the Quartus II software to report timing for the memory block clocking
schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no
degradation in fMAX
.
Table 28. Memory Block Performance Specifications for Arria V Devices
Resources Used
Performance
Memory
Mode
Unit
ALUTs
Memory
–I3, –C4
500
–I5, –C5
450
–C6
400
400
Single port, all supported widths
0
0
1
1
MHz
MHz
Simple dual-port, all supported widths
500
450
MLAB
Simple dual-port with read and write at the
same address
0
1
400
350
300
MHz
ROM, all supported width
—
0
—
1
500
400
400
450
350
350
400
285
285
MHz
MHz
MHz
Single-port, all supported widths
Simple dual-port, all supported widths
0
1
M10K
Block
Simple dual-port with the read-during-write
option set to Old Data, all supported widths
0
1
315
275
240
MHz
True dual port, all supported widths
ROM, all supported widths
0
0
1
1
400
400
350
350
285
285
MHz
MHz
Temperature Sensing Diode Specifications
Table 29 lists the specifications for the Arria V internal temperature sensing diode.
Table 29. Internal Temperature Sensing Diode Specifications for Arria V Devices
Offset
Temperature
Range
Conversion
Time
Minimum Resolution with no
Missing Codes
Accuracy Calibrated Sampling Rate
Option
Resolution
Frequency:
1 MHz
–40 to 100°C
8°C
No
< 100 ms
8 bits
8 bits
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 34
Switching Characteristics
Periphery Performance
This section describes the periphery performance, high-speed I/O, and external
memory interface.
1
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 30 lists high-speed I/O timing for Arria V devices.
Table 30. High-Speed I/O Specifications for Arria V Devices (1), (2), (3) (Part 1 of 3)
–I3, –C4
–I5, –C5
Min Typ
–C6
Min Typ
Symbol
Conditions
Unit
Min Typ
Max
Max
Max
f
HSCLK_in (input clock
frequency) True
Differential I/O
Standards
Clock boost factor W = 1 to
5
5
—
—
800
5
5
—
—
750
5
5
—
625
MHz
(6)
40
fHSCLK_in (input clock
frequency) Single
Clock boost factor W = 1 to
625
420
625
420
—
500
420
MHz
(6)
Ended I/O Standards
40
(4)
fHSCLK_in (input clock
frequency) Single
Clock boost factor W = 1 to
5
5
—
—
5
5
—
—
5
5
—
—
MHz
MHz
(6)
Ended I/O Standards
40
(5)
fHSCLK_OUT (output
clock frequency)
(7)
(7)
(7)
—
625
625
500
Transmitter
SERDES factor
J = 3 to 10 (8)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
—
—
—
1250
—
—
—
1250
—
—
—
1050
Mbps
Mbps
Mbps
SERDES factor J ≥ 8 (8), (10)
True Differential I/O
Standards - fHSDR (data
rate)
LVDS TX with RX DPA
1600
1500
1250
SERDES factor J = 1 to 2
Uses DDR Registers
(11)
(11)
(11)
Emulated Differential
I/O Standards with
Three External Output
Resistor Network -
(9)
(9)
(9)
(9)
(9)
(9)
SERDES factor J = 4 to 10
SERDES factor J = 4 to 10
—
—
945
200
—
—
945
200
—
—
945
200
Mbps
Mbps
(12)
fHSDR (data rate)
Emulated Differential
I/O Standards with
One External Output
Resistor Network -
(12)
fHSDR (data rate)
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 35
Table 30. High-Speed I/O Specifications for Arria V Devices (1), (2), (3) (Part 2 of 3)
–I3, –C4
–I5, –C5
Min Typ
–C6
Min Typ
Symbol
Conditions
Unit
Min Typ
Max
Max
Max
Total Jitter for Data Rate,
600 Mbps - 1.25 Gbps
—
—
—
—
—
—
160
—
—
—
—
—
—
160
—
—
—
—
160
0.1
ps
UI
ps
tx Jitter - True
Differential I/O
Standards
Total Jitter for Data Rate,
< 600 Mbps
0.1
0.1
—
—
tx Jitter - Emulated
Differential I/O
Total Jitter for Data Rate,
600 Mbps – 1.25 Gbps
260
300
350
Standards with Three
External Output
Resistor Network
Total Jitter for Data Rate
< 600 Mbps
—
—
—
—
0.16
0.15
—
—
—
—
0.18
0.15
—
—
—
—
0.21
0.15
UI
UI
tx Jitter - Emulated
Differential I/O
Standards with One
External Output
Resistor Network
—
TX output clock duty cycle
for both True and Emulated
Differential I/O Standards
tDUTY
45
—
50
—
55
45
—
50
—
55
45
—
50
—
55
%
True Differential I/O
Standards (13)
160
180
200
ps
Emulated Differential I/O
Standards with Three
External Output Resistor
Network
—
—
—
—
250
500
—
—
—
—
250
500
—
—
—
—
300
500
ps
ps
tRISE & tFALL
Emulated Differential I/O
Standards with One
External Output Resistor
Network
True Differential I/O
Standards
—
—
—
—
150
300
—
—
—
—
150
300
—
—
—
—
150
300
ps
ps
TCCS
Emulated Differential I/O
Standards
Receiver
SERDES factor
J = 3 to 10 (8)
150
—
1250
150
—
1250
150
—
1050
Mbps
True Differential I/O
Standards - fHSDRDPA
(data rate)
SERDES factor J ≥ 8 with
150
—
—
—
1600
150
—
—
—
1500
150
—
—
—
1250
Mbps
Mbps
Mbps
DPA (8), (10)
(9)
(14)
(9)
(14)
(9)
(14)
SERDES factor J = 3 to 10
fHSDR (data rate)
SERDES factor J = 1 to 2
Uses DDR Registers
(9)
(11)
(9)
(11)
(9)
(11)
DPA Mode
DPA run length
—
—
—
—
—
—
10000
300
—
—
—
—
10000
300
—
—
—
—
10000
300
UI
Soft CDR mode
Soft-CDR ppm
tolerance
ppm
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 36
Switching Characteristics
Table 30. High-Speed I/O Specifications for Arria V Devices (1), (2), (3) (Part 3 of 3)
–I3, –C4
–I5, –C5
Min Typ
–C6
Symbol
Conditions
Unit
Min Typ
Max
Max
Min Typ
Max
Non DPA Mode
Sampling Window
Notes to Table 30:
—
—
—
300
—
—
300
—
—
300
ps
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) For LVDS applications, you must use the PLLs in integer PLL mode.
(4) This applies to DPA and soft-CDR modes only.
(5) This applies to non-DPA mode only.
(6) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
(7) This is achieved by using the LVDS clock network.
(8) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent
and requires timing analysis.
(9) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you
use. The I/O differential buffer and input register do not have a minimum toggle rate.
(10) The VCC and VCCP must be on a separate power layer and a maximum load of 5 pF for chip-to-chip interface.
(11) The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal
integrity simulation is clean.
(12) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
(13) This applies to default pre-emphasis and VOD settings only.
(14) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin,
transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Figure 3 shows the DPA lock time specifications with the DPA PLL calibration option
enabled.
Figure 3. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 37
Table 31 lists the DPA lock time specifications for Arria V devices, which are
applicable to both commercial and industrial grades. The DPA lock time is for one
channel. One data transition is defined as a 0-to-1 or 1-to-0 transition.
Table 31. DPA Lock Time Specifications for Arria V Devices
Number of Data
Number of
Transitions in One
Repetition of the
Training Pattern
Maximum Data
Transition
Standard
Training Pattern
Repetitions per 256
(1)
Data Transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640
640
640
640
640
Parallel Rapid I/O
10010000
10101010
32
Miscellaneous
01010101
32
Note to Table 31:
(1) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 4 shows the LVDS soft-clock data recovery (CDR)/DPA sinusoidal jitter
tolerance specification for a data rate equal to 1.25 Gbps.
Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.35
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 38
Switching Characteristics
Table 32 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate equal to 1.25 Gbps.
Table 32. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps
Jitter Frequency (Hz) Sinusoidal Jitter (UI)
F1
F2
F3
F4
10,000
17,565
25.000
25.000
0.350
1,493,000
50,000,000
0.350
Figure 5 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate less than 1.25 Gbps.
Figure 5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 39
DLL Range, DQS Logic Block, and Memory Output Clock Jitter Specifications
Table 33 lists the DLL frequency range specifications for Arria V devices.
Table 33. DLL Frequency Range Specifications for Arria V Devices
Parameter
–I3, –C4
–I5, –C5
–C6
Unit
DLL operating frequency
range
200 – 667
200 – 667
200 – 667
MHz
Table 34 lists the DQS phase shift error for Arria V devices. This error specification is
the absolute maximum and minimum error.
Table 34. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V
Devices
Number of DQS Delay
–I3, –C4
–I5, –C5
–C6
Unit
Buffer
2
40
80
80
ps
Table 35 lists the memory output clock jitter specifications for Arria V devices.
The memory output clock jitter measurements are for 200 consecutive clock cycles, as
specified in the JEDEC DDR2/DDR3 SDRAM standard.
The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is
applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK
connections for better jitter performance.
Table 35. Memory Output Clock Jitter Specification for Arria V Devices
–I3, –C4
Clock
–I5, –C5
–C6
Parameter
Symbol
Unit
Network
Min
Max
Min
–50
Max
Min
Max
Clock period jitter
PHYCLK
PHYCLK
tJIT(per)
tJIT(cc)
–41
41
50
–55
55
ps
ps
Cycle-to-cycle period jitter
63
90
94
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 40
Switching Characteristics
OCT Calibration Block Specifications
Table 36 lists the OCT calibration block specifications for Arria V devices.
Table 36. OCT Calibration Block Specifications for Arria V Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTCAL
—
—
1000
32
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
TOCTSHIFT
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
TRS_RT
—
2.5
—
ns
Figure 6 shows the TRS_RT for oeand dyn_term_ctrlsignals.
Figure 6. Timing Diagram for oe and dyn_term_ctrl Signals
Tristate
TX
Tristate
RX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Duty Cycle Distortion (DCD) Specifications
Table 37 lists the worst-case DCD for Arria V devices. The output DCD cycle only
applies to the I/O buffer. It does not cover the system DCD.
Table 37. Worst-Case DCD on Arria V I/O Pins
–I3, –C4
Symbol
–C5,–I5
–C6
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 41
HPS Specifications
This section provides HPS specifications and timing for Arria V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset
signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.
HPS Clock Performance
Table 38 lists the HPS clock performance for Arria V devices.
Table 38. HPS Clock Performance for Arria V Devices
Symbol/Description
mpu_base_clk (microprocessor unit clock)
main_base_clk (L3/L4 interconnect clock)
h2f_user0_clk
–I3
1050
525
100
100
200
–C4
925
462
100
100
200
–C5, –I5
800
–C6
700
350
100
100
160
Unit
MHz
MHz
MHz
MHz
MHz
400
100
h2f_user1_clk
100
h2f_user2_clk
200
HPS PLL Specifications
HPS PLL VCO Frequency Range
Table 39 lists the HPS PLL VCO frequency range for Arria V devices. This
specification applies to all speed grade.
Table 39. HPS PLL VCO Frequency Range for Arria V Devices
Description
Minimum
Maximum
Unit
VCO range
320
1,600
MHz
HPS PLL Input Clock Range
The HPS PLL input clock range is 10 – 50 MHz.
For more information about the clock range for different values of clock select (CSEL),
refer to the Booting and Configuration chapter.
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the
HPS PLLs can tolerate.
Maximum input jitter = Input clock period x Divide value (NR) x 0.02
Table 40 shows the examples of the maximum input jitter calculated with the
equation.
Table 40. Examples of Maximum Input Jitter
Input Reference Clock Period
Divide Value (NR)
Maximum Jitter
Unit
ns
40 ns
40 ns
40 ns
1
2
4
0.8
1.6
3.2
ns
ns
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 42
Switching Characteristics
QSPI Timing Characteristics
Table 41 lists the queued serial peripheral interface (QSPI) timing characteristics for
Arria V devices.
Table 41. QSPI Timing Requirements for Arria V Devices
Symbol Description
Fclk CLK clock frequency
Tdutycycle
Min
—
Typ
—
Max
108
55
Unit
MHz
%
QSPI_CLK duty cycle
45
—
1/2 cycle of
QSPI_CLK
Tdssfrst
Output delay QSPI_SS valid before first clock edge
—
—
ns
Tdsslst
Tdio
Output delay QSPI_SS valid after last clock edge
IO Data output delay
–1
–1
—
—
1
1
ns
ns
Maximum data input delay from falling edge of
QSPI_CLK to data arrival at SoC. The delay field of
the qspiregs.rddatacapregister can be
programmed to adjust the capture logic of the
incoming data.
Tdinmax
—
—
—
—
Figure 7 shows the timing diagram for QSPI timing characteristics. This timing
diagram illustrates clock polarity mode 0 and clock phase mode 0.
Figure 7. QSPI Timing Diagram
Tdsslst
QSPI_SS
Tdssfrst
QSPI_CLK
QSPI_DATA
Tdio
Tdinmax
Data Out
Data In
SPI Timing Characteristics
Table 42 lists the serial peripheral interface (SPI) master timing characteristics for
Arria V devices. The setup and hold times can be used for Texas Instruments SSP
mode and National Semiconductor Microwire mode.
Table 42. SPI Master Timing Requirements for Arria V Devices
Symbol Description
Tclk
Min
—
45
8
Max
16.67
55
Unit
ns
CLK clock period
Tdutycycle
Tdssfrst
Tdsslst
Tdio
SPI_CLK duty cycle
%
Output delay SPI_SS valid before first clock edge
Output delay SPI_SS valid after last clock edge
Master-out slave-in (MOSI) output delay
—
ns
8
—
ns
–1
1
ns
Maximum data input delay from falling edge of SPI_CLK to
data arrival at SoC. The RX sample delay register can be
programmed to control the capture of input data.
Tdinmax
—
—
—
500
ns
ns
Slave select pulse width (Texas Instruments SSP mode)
16.67
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 43
Figure 8 shows the timing diagram for SPI master timing characteristics.
Figure 8. SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdinmax
Tdio
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdinmax
Table 43 lists the SPI slave timing characteristics for Arria V devices. The setup and
hold times can be used for Texas Instruments SSP mode and National Semiconductor
Microwire mode.
Table 43. SPI Slave Timing Requirements for Arria V Devices
Symbol Description
Min
20
5
Max
—
—
—
—
—
6
Unit
ns
ns
ns
ns
ns
ns
ns
Tclk
Ts
CLK clock period
MOSI Setup time
MOSI Hold time
Th
5
Tsuss
Thss
Td
Setup time SPI_SS valid before first clock edge
Hold time SPI_SS valid after last clock edge
Master-in slave-out (MISO) output delay
8
8
—
20
—
Slave select pulse width (Texas Instruments SSP mode)
—
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 44
Switching Characteristics
Figure 9 shows the timing diagram for SPI slave timing characteristics.
Figure 9. SPI Slave Timing Diagram
Thss
SPI_SS
Tsuss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO (scph = 1)
SPI_MOSI (scph = 1)
Td
Ts
Th
Td
SPI_MISO (scph = 0)
SPI_MOSI (scph = 0)
Ts
Th
SD/MMC Timing Characteristics
Table 44 lists the secure digital (SD)/MultiMediaCard (MMC) timing characteristics
for Arria V devices.
Table 44. SD/MMC Timing Requirements for Arria V Devices
Symbol
Description
Min
20
Max
—
—
55
6
Unit
ns
SDMMC_CLK_OUT clock period (High speed mode)
SDMMC_CLK_OUT clock period (Default speed mode)
SDMMC_CLK_OUT duty cycle
Tclk
40
ns
Tdutycycle
Td
45
%
SDMMC_CMD/SDMMC_D output delay
—
ns
Maximum input delay from rising edge of SDMMC_CLK to
data arrival at SoC
Tdinmax
—
25
ns
Figure 10 shows the timing diagram for SD/MMC timing characteristics.
Figure 10. SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD & SDMMC_D (Out)
SDMMC_CMD & SDMMC_D (In)
Command/Data Out
Tdinmax
Command/Data In
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 45
USB Timing Characteristics
Table 45 lists the USB timing characteristics for Arria V devices.
Table 45. USB Timing Requirements for Arria V Devices
Symbol Description
USB CLK clock period
Min
—
Typ
16.67
—
Max
—
Unit
Tclk
Td
ns
ns
ns
ns
CLK to USB_STP/USB_DATA[7:0] output delay
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]
7.5
2
11
Tsu
Th
—
—
2.5
—
—
Figure 11 shows the timing diagram for USB timing characteristics.
Figure 11. USB Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
Tsu Th
USB_DIR & USB_NXT
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 46 lists the reduced gigabit media independent interface (RGMII) TX timing
characteristics for Arria V devices.
Table 46. RGMII TX Timing Requirements for Arria V Devices
Symbol Description
Tclk (1000Base-T) TX_CLK clock period
clk (100Base-T) TX_CLK clock period
Min
—
Typ
8
Max
—
Unit
ns
T
—
40
400
—
—
—
ns
T
clk (10Base-T)
Tdutycycle
Td
TX_CLK clock period
—
—
ns
TX_CLK duty cycle
45
55
%
TX_CLK to TXD/TX_CTL output data delay
–0.85
0.15
ns
Figure 12 shows the timing diagram for RGMII TX timing characteristics.
Figure 12. RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
Td
TX_CTL
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 46
Switching Characteristics
Table 47 lists the RGMII RX timing characteristics for Arria V devices.
Table 47. RGMII RX Timing Requirements for Arria V Devices
Symbol
Description
RX_CLK clock period
Min
—
—
—
1
Typ
Unit
ns
Tclk (1000Base-T)
8
T
clk (100Base-T)
clk (10Base-T)
Tsu
RX_CLK clock period
RX_CLK clock period
RX_D/RX_CTL setup time
40
ns
T
400
—
ns
ns
Figure 13 shows the timing diagram for RGMII RX timing characteristics.
Figure 13. RGMII RX Timing Diagram
RX_CLK
Tsu
RX_D[3:0]
RX_CTL
Table 48 lists the management data input/output (MDIO) timing characteristics for
Arria V devices.
Table 48. MDIO Timing Requirements for Arria V Devices
Symbol Description
Min
—
10
10
0
Typ
400
—
Unit
ns
Tclk
Td
Ts
MDC clock period
MDC to MDIO output data delay
Setup time for MDIO data
Hold time for MDIO data
ns
—
ns
Th
—
ns
Figure 14 shows the timing diagram for MDIO timing characteristics.
Figure 14. MDIO Timing Diagram
MDC
Td
MDIO_OUT
MDIO_IN
Th
Tsu
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 47
I2C Timing Characteristics
Table 49 lists the I2C timing characteristics for Arria V devices.
Table 49. I2C Timing Requirements for Arria V Devices
Standard Mode
Fast Mode
Symbol
Description
Unit
Min
—
4.7
4
Max
10
Min
Max
2.5
—
Tclk
Tclkhigh
Tclklow
Serial clock (SCL) clock period
SCL high time
—
0.6
1.3
µs
µs
µs
—
SCL low time
—
—
Setup time for serial data line (SDA) data to
SCL
Ts
0.25
—
0.1
—
µs
Th
Hold time for SCL to SDA data
0
—
4.7
4
3.45
0.2
—
0
0.9
0.2
—
µs
µs
µs
µs
µs
Td
SCL to SDA output data delay
—
Tsu_start
Thd_start
Tsu_stop
Setup time for a repeated start condition
Hold time for a repeated start condition
Setup time for a stop condition
0.6
0.6
0.6
—
—
4
—
—
Figure 15 shows the timing diagram for I2C timing characteristics.
Figure 15. I2C Timing Diagram
I2C_SCL
Td
Ts
Tsu_stop
Tsu_start Thd_start
Th
Data In
Data Out
I2C_SDA
NAND Timing Characteristics
Table 50 lists the NAND timing characteristics for Arria V devices.
The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5
timing as well as legacy NAND devices. The following table lists the requirements for
ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by
programming the C4output of the main HPS PLL and timing registers provided in the
NAND controller.
Table 50. NAND ONFI 1.0 Timing Requirements for Arria V Devices (Part 1 of 2)
Symbol
(1)
Description
Write enable pulse width
Min
10
7
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
Twp
Twh
(1)
Write enable hold time
(1)
Trp
Read Enable pulse width
10
7
(1)
(1)
Treh
Read enable hold time
Tclesu
Command latch enable to write enable setup time
Command latch enable to write enable hold time
Chip enable to write enable setup time
10
5
(1)
Tcleh
(1)
Tcesu
15
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 48
Switching Characteristics
Table 50. NAND ONFI 1.0 Timing Requirements for Arria V Devices (Part 2 of 2)
Symbol
(1)
Description
Chip enable to write enable hold time
Address latch enable to write enable setup time
Address latch enable to write enable hold time
Data to write enable setup time
Min
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tceh
—
—
—
—
—
25
16
100
—
(1)
Talesu
10
5
(1)
Taleh
Tdsu
(1)
10
5
(1)
Tdh
Tcea
Trea
Trhz
Trr
Data to write enable hold time
Chip enable to data access time
—
—
—
20
Read enable to data access time
Read enable to data high impedance
Ready to read enable low
Note to Table 50:
(1) Timing of the NAND interface is controlled through the NAND Configuration registers.
Figure 16 shows the timing diagram for NAND command latch timing characteristics.
Figure 16. NAND Command Latch Timing Diagram
NAND_CLE
NAND_CE
Tclesu
Tcesu
Tcleh
Twp
Tceh
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Command
Tdh
NAND_DQ[7:0]
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 49
Figure 17 shows the timing diagram for NAND address latch timing characteristics.
Figure 17. NAND Address Latch Timing Diagram
NAND_CLE
NAND_CE
Tcesu
Tclesu
Twp
Twh
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Tdh
NAND_DQ[7:0]
Address
Figure 18 shows the timing diagram for NAND data write timing characteristics.
Figure 18. NAND Data Write Timing Diagram
NAND_CLE
NAND_CE
Tcleh
Tceh
Twp
NAND_WE
NAND_ALE
Talesu
Tdsu
Tdh
NAND_DQ[7:0]
Din
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 50
Switching Characteristics
Figure 19 shows the timing diagram for NAND data read timing characteristics.
Figure 19. NAND Data Read Timing Diagram
Tcea
NAND_CE
Trr
Trp
Treh
NAND_RE
Trhz
NAND_RB
Trea
NAND_DQ[7:0]
Dout
ARM Trace Timing Characteristics
Table 51 lists the ARM trace timing characteristics for Arria V devices.
Most debugging tools have a mechanism to adjust the capture point of trace data.
Table 51. ARM Trace Timing Requirements for Arria V Devices
Description
Min
12.5
45
Max
—
55
1
Unit
ns
CLK clock period
CLK maximum duty cycle
%
CLK to D0 –D7 output data delay
–1
ns
UART Interface
The maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
The minimum detectable general-purpose I/O (GPIO) pulse width is 2 µs. The pulse
width is based on a debounce clock frequency of 1 MHz.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 51
Configuration Specification
This section provides configuration specifications and timing for Arria V devices.
POR Specifications
Table 52 lists the specifications for fast and standard POR for Arria V devices.
Table 52. Fast and Standard POR Delay Specification for Arria V Devices (1)
POR Delay
Minimum
Maximum
12 (2)
Unit
Fast
4
ms
ms
Standard
100
300
Notes to Table 52:
(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Arria V Devices”
table in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(2) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize
after the POR trip.
JTAG Configuration Timing
Table 53 lists the JTAG timing parameters and values for Arria V devices.
Table 53. JTAG Timing Parameters and Values for Arria V Devices
Symbol
Description
Min
30
167 (1)
14
14
2
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCP
tJCH
tJCL
TCK clock period
TCK clock period
TCK clock high time
TCK clock low time
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
3
5
(2)
tJPCO
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
—
—
—
12
14
14
(2)
(2)
tJPZX
tJPXZ
Notes to Table 53:
(1) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile
key programming.
(2) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 13 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 52
Configuration Specification
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Arria V devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[]ratio when you turn on
encryption or the compression feature.
Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r
times the DATA[]rate in byte per second (Bps) or word per second (Wps). For
example, in FPP x16 where the r is 2, the DCLKfrequency must be 2 times the DATA[]
rate in Wps.
Table 54 lists the DCLK-to-DATA[]ratio for each combination.
Table 54. DCLK-to-DATA[] Ratio for Arria V Devices
Configuration Scheme
Encryption
Compression
DCLK-to-DATA[] ratio (r)
Off
On
Off
On
Off
On
Off
On
Off
Off
On
On
Off
Off
On
On
1
1
2
2
1
2
4
4
FPP (8-bit wide)
FPP (16-bit wide)
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 53
FPP Configuration Timing when DCLK to DATA[] = 1
Figure 20 shows the timing waveform for a FPP configuration when using a MAX® II
device as an external host. This timing waveform shows timing when the DCLK-to-
DATA[]ratio is 1.
1
When you enable decompression or the design security feature, the DCLK-to-DATA[]
ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[]ratio, refer to
Table 54.
(1)
Figure 20. DCLK-to-DATA[] FPP Configuration Timing Waveform When the Ratio is 1
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
(6)
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
Word 0 Word 1 Word 2 Word 3
DATA[15..0](5)
Word n-2 Word n-1
User Mode
User Mode
tDSU
High-Z
User I/O
(7)
INIT_DONE
tCD2UM
Notes to Figure 20:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONEare at logic-high levels. When
nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds nSTATUSlow for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(5) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[15..5]are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high when the Arria V device
receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization and
enter user mode.
(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONE goes low.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 54
Configuration Specification
Table 55 lists the timing parameters for Arria V devices for FPP configuration when
the DCLK-to-DATA[]ratio is 1.
Table 55. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is 1
Symbol
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
Minimum
Maximum
600
Unit
ns
—
—
600
ns
nCONFIGlow pulse width
2
268
—
—
µs
µs
µs
µs
µs
(1)
nSTATUSlow pulse width
1506
(2)
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
1506
(3)
1506
2
—
—
tCF2CK
tST2CK
tDSU
(3)
DATA[]setup time before rising edge on
DCLK
5.5
—
ns
DATA[]hold time after rising edge on DCLK
DCLKhigh time
0
—
—
ns
s
tDH
0.45 x 1/fMAX
tCH
DCLKlow time
0.45 x 1/fMAX
—
s
tCL
DCLKperiod
1/fMAX
—
s
tCLK
fMAX
tCD2UM
tCD2CU
DCLKfrequency (FPP x8/ x16)
—
175
125
437
—
MHz
µs
—
(4)
CONF_DONEhigh to user mode
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLKperiod
tCD2CU + (Tinit
x CLKUSR
CONF_DONEhigh to user mode with CLKUSR
option on
tCD2UMC
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 55:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIGor the nSTATUSlow pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding the nSTATUSlow.
(3) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 55
FPP Configuration Timing when DCLK to DATA[] > 1
Figure 21 shows the timing waveform for a FPP configuration when using a MAX II
device or microprocessor as an external host. This waveform shows timing when the
DCLK-to-DATA[]ratio is more than 1.
(1)
Figure 21. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
CONF_DONE (3)
t
CL
tCF2CD
(7)
tST2CK
t
CH
DCLK (5)
DATA[15..0] (7)
User I/O
(6)
(4)
1
2
1
1
2
r
1
2
r
r
t
CLK
Word 0
Word 1
Word (n-1)
User Mod
User Mod
Word 3
t
t
tDSU
DH
DH
High-Z
(8)
INIT_DONE
tCD2UM
Notes to Figure 21:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONEare at logic high levels.
When nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds nSTATUSlow for the time as specified by the POR delay.
(3) After power up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(5) “r” denotes the DCLK-to-DATA[]ratio. For the DCLK-to-DATA[]ratio based on the decompression and the design security feature enable
settings, refer to Table 54 on page 1–52.
(6) If needed, pause DCLKby holding it low. When DCLKrestarts, the external host must provide data on the DATA[15..0]pins prior to sending
the first DCLKrising edge.
(7) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high after the Arria V device
receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization
and enter user mode.
(8) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 56
Configuration Specification
Table 56 lists the timing parameters for Arria V devices when the DCLK-to-DATA[]ratio
is more than 1.
Table 56. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is >1 (1)
Symbol
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
Minimum
Maximum
600
Unit
ns
—
—
600
ns
nCONFIGlow pulse width
2
268
—
—
µs
µs
µs
µs
µs
(2)
nSTATUSlow pulse width
1506
(3)
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
1506
(4)
1506
2
—
—
tCF2CK
tST2CK
tDSU
(4)
DATA[]setup time before rising edge on
DCLK
5.5
—
—
ns
ns
(5)
N – 1/fDCLK
tDH
DATA[]hold time after rising edge on DCLK
DCLKhigh time
DCLKlow time
0.45 x 1/fMAX
—
—
s
s
tCH
tCL
tCLK
fMAX
tR
0.45 x 1/fMAX
DCLKperiod
1/fMAX
—
s
DCLKfrequency (FPP x8/ x16)
Input rise time
—
125
40
MHz
ns
ns
µs
—
—
Input fall time
—
175
40
tF
(6)
CONF_DONEhigh to user mode
437
—
tCD2UM
tCD2CU
CONF_DONEhigh to CLKUSRenabled
4 × maximum DCLKperiod
tCD2CU + (Tinit
x CLKUSR
CONF_DONEhigh to user mode with CLKUSR
option on
tCD2UMC
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 56:
(1) Use these timing parameters when you use decompression and the design security features.
(2) This value can be obtained if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(3) This value can be obtained if you do not delay configuration by externally holding nSTATUSlow.
(4) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
(5) N is the DCLK-to-DATA[]ratio and fDCLK is the DCLKfrequency of the system.
(6) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 57
AS Configuration Timing
Figure 22 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Figure 22. AS Configuration Timing Waveform
t
CF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
t
CO
t
DH
Read Address
AS_DATA0/ASDO
AS_DATA1 (1)
t
SU
bit (n − 2) bit (n − 1)
bit 1
bit 0
t
(2)
CD2UM
INIT_DONE (3)
User I/O
User Mode
Notes to Figure 22:
(1) If you are using AS x4 mode, this signal represents the AS_DATA[3..0]and EPCQ sends in 4-bits of data for each DCLKcycle.
(2) The initialization clock can be from the internal oscillator or CLKUSRpin.
(3) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
Table 57 lists the timing parameters for AS x1 and AS x4 configurations in Arria V
devices.
The minimum and maximum numbers apply to both the internal oscillator and
CLKUSRwhen either one is used as the clock source for device configuration.
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the
timing parameters for passive serial (PS) mode listed in Table 59 on page 1–59. You
can obtain the tCF2ST1 value if you do not delay configuration by externally holding
nSTATUSlow.
Table 57. AS Timing Parameters for AS x1 and x4 Configurations in Arria V Devices
Symbol
tCO
Parameter
Minimum
Maximum Unit
DCLK falling edge to the AS_DATA0
/
ASDOoutput
—
4
ns
ns
ns
µs
—
tSU
Data setup time before the falling edge on DCLK
Data hold time after the falling edge on DCLK
CONF_DONEhigh to user mode
1.5
—
—
437
—
tDH
0
175
tCD2UM
tCD2CU
tCD2UMC
CONF_DONEhigh to CLKUSRenabled
4 x maximum DCLKperiod
t
CD2CU + (Tinit x CLKUSR
CONF_DONEhigh to user mode with CLKUSRoption on
—
—
—
period)
17,408
Number of clock cycles required for device initialization
Cycles
Tinit
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 58
Configuration Specification
Table 58 lists the internal clock frequency specification for the AS configuration
scheme.
The DCLKfrequency specification applies when you use the internal oscillator as the
configuration clock source.
The AS multi-device configuration scheme does not support DCLKfrequency of
100 MHz.
Table 58. DCLK Frequency Specification in the AS Configuration Scheme
Parameter
Minimum
5.3
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLK frequency in AS
configuration scheme
21.3
50.0
42.6
100.0
Remote update only in AS
mode
—
—
12.5
MHz
PS Configuration Timing
Figure 23 shows the timing waveform for a PS configuration when using a MAX II
device or microprocessor as an external host.
(1)
Figure 23. PS Configuration Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
(5)
t CLK
CONF_DONE (3)
tCH
tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
Bit 2 Bit 3
Bit (n-1)
Bit 0 Bit 1
DATA0
tDSU
High-Z
User I/O
User Mod
INIT_DONE (6)
tCD2UM
Notes to Figure 23:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONEare at logic high levels. When
nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds nSTATUSlow for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(5) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high after the Arria V device
receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization
and enter user mode.
(6) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 59
Table 59 lists the PS timing parameter for Arria V devices.
Table 59. PS Timing Parameters for Arria V Devices
Symbol
tCF2CD
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
Minimum
Maximum
600
Unit
ns
—
—
tCF2ST0
600
ns
nCONFIGlow pulse width
2
—
µs
µs
µs
µs
µs
ns
ns
s
tCFG
(1)
nSTATUSlow pulse width
268
1506
tSTATUS
tCF2ST1
(2)
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
—
1506
(3)
1506
—
—
tCF2CK
(3)
2
tST2CK
5.5
—
tDSU
0
—
tDH
0.45 x 1/fMAX
—
tCH
DCLKlow time
0.45 x 1/fMAX
—
s
tCL
DCLKperiod
1/fMAX
—
s
tCLK
DCLKfrequency
—
175
125
437
—
MHz
µs
—
fMAX
tCD2UM
tCD2CU
tCD2UMC
CONF_DONEhigh to user mode (4)
CONF_DONEhigh to CLKUSRenabled
4 x maximum DCLKperiod
t
CD2CU + (Tinit x CLKUSR
CONF_DONEhigh to user mode with CLKUSRoption on
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 59:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUSlow.
(3) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 60
Configuration Specification
Initialization
Table 60 lists the initialization clock source option, the applicable configuration
schemes, and the maximum frequency for Arria V devices.
Table 60. Initialization Clock Source Option and the Maximum Frequency for Arria V Devices
Maximum
Frequency
(MHz)
Minimum Number of
Initialization Clock Source Configuration Schemes
Clock Cycles
Internal Oscillator
AS, PS, and FPP
PS and FPP
AS
12.5
125
100
Tinit
(1)
CLKUSR
Note to Table 60:
(1) To enable CLKUSRas the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General panel of the Device and Pin Options dialog box.
Configuration Files
Use Table 61 to estimate the file size before design compilation. Different
configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf)
format, have different file sizes.
For the different types of configuration file and file sizes, refer to the Quartus II
software. However, for a specific version of the Quartus II software, any design
targeted for the same device has the same uncompressed configuration file size.
Table 61 lists the uncompressed raw binary file (.rbf) sizes for Arria V devices.
Table 61. Uncompressed .rbf Sizes for Arria V Devices
Variant
Member Code
Configuration .rbf Size (bits)
71,015,552
IOCSR .rbf Size (bits)
439,960
439,960
446,360
446,360
457,368
457,368
463,128
463,128
439,960
446,360
457,368
463,128
450,968
450,968
450,968
450,968
A1
A3
A5
A7
B1
B3
B5
B7
C3
C7
D3
D7
B3
B5
D3
D5
71,015,552
101,740,640
101,740,640
137,784,928
137,784,928
185,915,648
185,915,648
71,015,552
Arria V GX
101,740,640
137,784,928
185,915,648
185,903,520
185,903,520
185,903,520
185,903,520
Arria V GT
Arria V SX
Arria V ST
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 61
Table 62 lists the minimum configuration time estimation for Arria V devices. The
estimated values are based on the configuration .rbf sizes in Table 61.
Table 62. Minimum Configuration Time Estimation for Arria V Devices
Active Serial (1)
Fast Passive Parallel (2)
Minimum
Configuration
Time (ms)
Minimum
Configuration Time
(ms)
Variant
Member Code
DCLK
(MHz)
DCLK
(MHz)
Width
Width
A1
A3
A5
A7
B1
B3
B5
B7
C3
C7
D3
D7
B3
B5
D3
D5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
178
178
255
255
344
344
465
465
178
255
344
465
465
465
465
465
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
36
36
51
51
69
69
93
93
36
51
69
93
93
93
93
93
Arria V GX
Arria V GT
Arria V SX
Arria V ST
Notes to Table 62:
(1) DCLK frequency of 100 MHz using external CLKUSR
.
(2) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Remote System Upgrades Circuitry Timing Specification
Table 63 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 63. Remote System Upgrade Circuitry Timing Specification (Part 1 of 2)
Parameter
Minimum
—
Maximum
Unit
MHz
ns
(1)
40
—
tMAX_RU_CLK
(2)
tRU_nCONFIG
250
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 62
Configuration Specification
Table 63. Remote System Upgrade Circuitry Timing Specification (Part 2 of 2)
Parameter
Minimum
Maximum
Unit
(3)
tRU_nRSTIMER
250
—
ns
Notes to Table 63:
(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE
megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.
(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “Remote System Upgrade State Machine”
section in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(3) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “User Watchdog Timer” section in the
Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
User Watchdog Internal Oscillator Frequency Specification
Table 64 lists the frequency specifications for the user watchdog internal oscillator.
Table 64. User Watchdog Internal Oscillator Frequency Specifications
Parameter
Minimum
Typical
Maximum
Unit
User watchdog internal
oscillator frequency
5.3
7.9
12.5
MHz
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
I/O Timing
Page 63
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis.
The Quartus II Timing Analyzer provides a more accurate and precise I/O timing
data based on the specifics of the design after you complete place-and-route.
f
You can download the Excel-based I/O Timing spreadsheet from the Arria V Devices
Documentation webpage.
Programmable IOE Delay
Table 65 lists the Arria V I/O element (IOE) programmable delay settings.
Table 65. IOE Programmable Delay for Arria V Devices
Fast Model
Industrial Commercial
Slow Model
Available Minimum
Settings Offset (2)
Parameter (1)
Unit
–C4
–C5
1.063
3.496
1.063
1.063
–C6
–I3
–I5
D1
32
8
0
0
0
0
0.508
1.763
0.508
0.508
0.517
1.795
0.518
0.517
0.870
2.999
0.869
0.870
1.063
3.571
1.063
1.063
0.872
3.031
1.063
0.872
1.057
3.643
1.057
1.057
ns
ns
ns
ns
D3
D4
32
32
D5
Notes to Table 65:
(1) You can set this value in the Quartus II software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.
(2) Minimum offset does not include the intrinsic delay.
Programmable Output Buffer Delay
Table 66 lists the delay chain settings that control the rising and falling edge delays of
the output buffer. The default delay is 0 ps.
You can set the programmable output buffer delay in the Quartus II software by
setting the Output Buffer Delay Control assignment to either positive, negative, or
both edges, with the specific values stated here (in ps) for the Output Buffer Delay
assignment.
Table 66. Programmable Output Buffer Delay
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
Rising and/or falling edge
delay
DOUTBUF
100
ps
150
ps
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 64
Glossary
Glossary
Table 67 lists the glossary for this datasheet.
Table 67. Glossary Table (Part 1 of 4)
Letter
Subject
Definitions
A
B
C
—
—
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
Ground
IL
V
CM
Differential Waveform
V
ID
p - n = 0 V
V
ID
Differential I/O
Standards
D
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p - n = 0 V
V
OD
E
F
—
—
fHSCLK
Left/right PLL input clock frequency.
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDR
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
G
H
I
—
—
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Glossary
Page 65
Table 67. Glossary Table (Part 2 of 4)
Letter
Subject
Definitions
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
J
TMS
TDI
tJCP
J
JTAG Timing
Specifications
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
K
L
M
N
O
—
—
(1)
Diagram of PLL Specifications
CLKOUT Pins
fOUT_EXT
Switchover
4
CLK
fIN
fINPFD
N
GCLK
RCLK
Counters
C0..C17
fVCO
VCO
fOUT
PFD
CP
LF
Core Clock
PLL
Specifications
P
Delta Sigma
Modulator
Key
External Feedback
Reconfigurable in User Mode
Note:
(1) Core Clockcan only be fed by dedicated clock input pins or PLL outputs.
Q
R
—
—
RL
Receiver differential input discrete resistor (external to the Arria V device).
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 66
Glossary
Table 67. Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position in the sampling
window, as shown:
Sampling
Bit Time
window (SW)
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing.
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
VCCIO
referenced I/O
standard
VOH
VIH
(
)
AC
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
VOL
VSS
tC
High-speed receiver/transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including the tCO
variation and clock skew, across channels driven by the same PLL. The clock is included in
the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
TCCS (channel-
to-channel-skew)
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and the data sampling window.
T
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80–20%)
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the GPIO driven by a PLL
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20–80%)
—
tINCCJ
tOUTPJ_IO
tOUTPJ_DC
tRISE
U
—
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Glossary
Page 67
Table 67. Glossary Table (Part 4 of 4)
Letter
Subject
VCM(DC)
Definitions
DC Common mode input voltage.
VICM
Input Common mode voltage—The common mode of the differential signal at the receiver.
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VDIF(AC)
VDIF(DC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH
VIH(AC)
VIH(DC)
High-level AC input voltage
High-level DC input voltage
V
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL
VIL(AC)
VIL(DC)
Low-level AC input voltage
Low-level DC input voltage
Output Common mode voltage—The common mode of the differential signal at the
transmitter.
VOCM
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
VX
Differential input voltage
Input differential cross point voltage
Output differential cross point voltage
High-speed I/O block—Clock Boost Factor
VOX
W
W
X,
Y,
Z
—
—
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 68
Document Revision History
Document Revision History
Table 68 lists the revision history for this document.
Table 68. Document Revision History (Part 1 of 2)
Date
Version
Changes
■ Added “HPS PLL Specifications”.
■ Added Table 24, Table 39, and Table 40.
■ Updated Table 1, Table 3, Table 5, Table 19, Table 20, Table 21, Table 38, Table 41,
Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, Table 48, Table 49, Table 50,
Table 51, Table 55, Table 56, and Table 59.
December 2013
3.6
■ Updated Figure 7, Figure 13, Figure 15, Figure 16, and Figure 19.
■ Removed table: GPIO Pulse Width for Arria V Devices.
■ Removed “Pending silicon characterization” note in Table 29.
■ Updated Table 25.
August 2013
August 2013
3.5
3.4
■ Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7,
Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19,
Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Table 28,
Table 29, Table 30, Table 31, Table 35, Table 36, Table 51, Table 53, Table 54, Table 55,
Table 56, Table 57, Table 60, Table 62, and Table 64.
■ Updated Table 1, Table 3, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, and
Table 29.
June 2013
May 2013
3.3
3.2
Updated Table 20, Table 21, Table 25, and Table 38.
■ Added Table 37.
■ Updated Figure 8, Figure 9, Figure 20, Figure 22, and Figure 23.
■ Updated Table 1, Table 5, Table 10, Table 13, Table 19, Table 20, Table 21, Table 23,
Table 29, Table 39, Table 40, Table 46, Table 56, Table 57, Table 60, and Table 64.
■ Updated industrial junction temperature range for –I3 speed grade in “PLL
Specifications” section.
■ Added HPS reset information in the “HPS Specifications” section.
■ Added Table 60.
March 2013
3.1
3.0
■ Updated Table 1, Table 3, Table 17, Table 20, Table 29, and Table 59.
■ Updated Figure 21.
■ Updated Table 2, Table 4, Table 9, Table 14, Table 16, Table 17, Table 20, Table 21,
Table 25, Table 29, Table 36, Table 56, Table 57, and Table 60.
■ Removed table: Transceiver Block Jitter Specifications for Arria V Devices.
■ Added HPS information:
■ Added “HPS Specifications” section.
November 2012
■ Added Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45,
Table 46, Table 47, Table 48, Table 49, and Table 50.
■ Added Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,
Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, and Figure 19.
■ Updated Table 3 and Table 5.
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Document Revision History
Page 69
Table 68. Document Revision History (Part 2 of 2)
Date
October 2012
August 2012
Version
Changes
■ Updated Arria V GX VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R minimum and maximum
values, and data rate in Table 4.
2.4
■ Added receiver VICM (AC coupled) and VICM (DC coupled) values, and transmitter VOCM
(AC coupled) and VOCM (DC coupled) values in Table 20 and Table 21.
2.3
■ Updated the SERDES factor condition in Table 30.
■ Updated the maximum voltage for VI (DC input voltage) in Table 1.
■ Updated Table 20 to include the Arria V GX -I3 speed grade.
■ Updated the minimum value of the fixedclkclock frequency in Table 20 and Table 21.
■ Updated the SERDES factor condition in Table 30.
July 2012
June 2012
2.2
2.1
■ Updated Table 50 to include the IOE programmable delay settings for the Arria V GX -I3
speed grade.
Updated VCCR_GXBL/R, VCCT_GXBL/R, and VCCL_GXBL/R values in Table 4.
Updated for the Quartus II software v12.0 release:
■ Restructured document.
■ Updated “Supply Current and Power Consumption” section.
■ Updated Table 20, Table 21, Table 24, Table 25, Table 26, Table 35, Table 39, Table 43, and
June 2012
2.0
Table 52.
■ Added Table 22, Table 23, and Table 33.
■ Added Figure 1–1 and Figure 1–2.
■ Added “Initialization” and “Configuration Files” sections.
■ Updated Table 2–1.
February 2012
December 2011
November 2011
August 2011
1.3
1.2
1.1
1.0
■ Updated Transceiver-FPGA Fabric Interface rows in Table 2–20.
■ Updated VCCP description.
■ Updated Table 2–1 and Table 2–3.
■ Updated Table 2–1, Table 2–19, Table 2–26, and Table 2–36.
■ Added Table 2–5.
■ Added Figure 2–4.
Initial release.
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
Page 70
Document Revision History
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
Arria V GZ Device Datasheet
AV-51002-3.6
This document covers the electrical and switching characteristics for Arria® V GZ
devices. Electrical characteristics include operating conditions and power
consumption. Switching characteristics include transceiver specifications, core, and
periphery performance. This document also describes I/O timing, including
programmable I/O element (IOE) delay and programmable output buffer delay.
f
For information regarding the densities and packages of devices in the Arria V GZ
family, refer to the Arria V Device Overview.
Electrical Characteristics
The following sections describe the electrical characteristics of Arria V GZ devices.
Operating Conditions
When you use Arria V GZ devices, they are rated according to a set of defined
parameters. To maintain the highest possible performance and reliability of
Arria V GZ devices, you must consider the operating requirements described in this
datasheet.
Arria V GZ devices are offered in commercial and industrial temperature grades.
Commercial devices are offered in –3 (fastest) and –4 core speed grades. Industrial
devices are offered in –3L and –4 core speed grades. Arria V GZ devices are offered in
–2 and –3 transceiver speed grades.
Table 1 lists the industrial and commercial speed grades for the Arria V GZ devices.
Table 1. Commercial and Industrial Speed Grade Offering for Arria V GZ Devices (1), (2), (3)
Core Speed Grade
Transceiver Speed Grade
C3
Yes
—
C4
—
I3L
Yes
—
I4
—
2
3
Yes
Yes
Notes to Table 1:
(1) C = Commercial temperature grade; I = Industrial temperature grade.
(2) Lower number refers to faster speed grade.
(3) L = Low power devices.
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December 2013 Altera Corporation
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Page 2
Electrical Characteristics
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Arria V GZ
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
c
Conditions other than those listed in Table 2 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 2. Absolute Maximum Ratings for Arria V GZ Devices
Symbol
VCC
Description
Power supply for core voltage and periphery circuitry
Power supply for programmable power technology
Power supply for configuration pins
Auxiliary supply for the programmable power technology
Battery back-up power supply for design security volatile key register
I/O pre-driver power supply
Minimum
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–55
Maximum
1.35
1.8
Unit
V
VCCPT
VCCPGM
VCC_AUX
VCCBAT
VCCPD
VCCIO
V
3.9
V
3.4
V
3.9
V
3.9
V
I/O power supply
3.9
V
VCCD_FPLL
VCCA_FPLL
VI
PLL digital power supply
1.8
V
PLL analog power supply
3.4
V
DC input voltage
3.8
V
TJ
Operating junction temperature
125
150
40
°C
°C
mA
TSTG
Storage temperature (No bias)
–65
IOUT
DC output current per pin
–25
Table 3 lists the absolute conditions for the transceiver power supply for Arria V GZ
devices.
Table 3. Transceiver Power Supply Absolute Conditions for Arria V GZ Devices
Symbol
VCCA_GXBL
VCCA_GXBR
VCCHIP_L
Description
Transceiver channel PLL power supply (left side)
Transceiver channel PLL power supply (right side)
Transceiver hard IP power supply (left side)
Transceiver PCS power supply (left side)
Minimum
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
Maximum
3.75
3.75
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.8
Unit
V
V
V
VCCHSSI_L
VCCHSSI_R
VCCR_GXBL
VCCR_GXBR
VCCT_GXBL
VCCT_GXBR
VCCH_GXBL
VCCH_GXBR
V
Transceiver PCS power supply (right side)
Receiver analog power supply (left side)
V
V
Receiver analog power supply (right side)
Transmitter analog power supply (left side)
Transmitter analog power supply (right side)
Transmitter output buffer power supply (left side)
Transmitter output buffer power supply (right side)
V
V
V
V
1.8
V
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 3
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 4 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time
over the lifetime of the device. A DC signal is equivalent to 100% of the duty cycle.
For example, a signal that overshoots to 3.95 V can be at 3.95 V for only ~21% over the
lifetime of the device; for a device lifetime of 10 years, the overshoot duration
amounts to ~2 years.
Table 4 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime.
Table 4. Maximum Allowed Overshoot During Transitions for Arria V GZ Devices
Overshoot Duration as %
Symbol
Description
Condition (V)
Unit
@ TJ = 100°C
3.8
3.85
3.9
100
64
36
21
12
7
%
%
%
%
%
%
%
%
%
3.95
4
Vi (AC)
AC input voltage
4.05
4.1
4
4.15
4.2
2
1
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 4
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operating limits for the AC and DC parameters for
Arria V GZ devices.
Table 5 lists the steady-state voltage and current values expected from Arria V GZ
devices. Power supply ramps must all be strictly monotonic, without plateaus.
Table 5. Recommended Operating Conditions for Arria V GZ Devices
Symbol
VCC
Description
Condition
Minimum
Typical
Maximum Unit
Core voltage and periphery circuitry power
supply (3)
—
0.82
0.85
0.88
1.55
V
V
V
Power supply for programmable power
technology
VCCPT
—
—
1.45
1.50
2.5
Auxiliary supply for the programmable
power technology
VCC_AUX
2.375
2.625
I/O pre-driver (3.0 V) power supply
I/O pre-driver (2.5 V) power supply
I/O buffers (3.0 V) power supply
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.85
2.375
2.85
3.0
2.5
3.0
2.5
1.8
1.5
1.35
1.25
1.2
3.0
2.5
1.8
2.5
1.5
3.15
2.625
3.15
V
V
V
V
V
V
V
V
V
V
V
V
V
V
(1)
VCCPD
I/O buffers (2.5 V) power supply
2.375
1.71
2.625
1.89
I/O buffers (1.8 V) power supply
VCCIO
I/O buffers (1.5 V) power supply
1.425
1.283
1.19
1.575
1.45
I/O buffers (1.35 V) power supply
I/O buffers (1.25 V) power supply
I/O buffers (1.2 V) power supply
1.31
1.14
1.26
Configuration pins (3.0 V) power supply
Configuration pins (2.5 V) power supply
Configuration pins (1.8 V) power supply
PLL analog voltage regulator power supply
PLL digital voltage regulator power supply
2.85
3.15
VCCPGM
2.375
1.71
2.625
1.89
VCCA_FPLL
VCCD_FPLL
2.375
1.45
2.625
1.55
Battery back-up power supply (For design
security volatile key register)
(2)
VCCBAT
—
1.2
—
3.0
V
VI
DC input voltage
Output voltage
—
–0.5
0
—
—
—
—
—
—
3.6
VCCIO
85
V
VO
—
V
Commercial
Industrial
Standard POR
Fast POR
0
°C
°C
—
—
TJ
Operating junction temperature
Power supply ramp time
–40
100
200 µs
200 µs
100 ms
4 ms
tRAMP
Notes to Table 5:
(1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(2) If you do not use the design security feature in Arria V GZ devices, connect VCCBAT to a 1.2- to 3.0-V power supply. Arria V GZ power-on-reset
(POR) circuitry monitors VCCBAT. Arria V GZ devices do not exit POR if VCCBAT is not powered up.
(3) The VCC core supply must be set to 0.9 V if the Partial Reconfiguration (PR) feature is used.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 5
Table 6 lists the transceiver power supply recommended operating conditions for
Arria V GZ devices.
Table 6. Recommended Transceiver Power Supply Operating Conditions for Arria V GZ Devices
Symbol
Description
Minimum
2.85
Typical
3.0
Maximum
3.15
Unit
(1), (3)
VCCA_GXBL
Transceiver channel PLL power supply (left side)
V
2.375
2.85
2.5
2.625
3.15
3.0
(1), (3)
VCCA_GXBR
Transceiver channel PLL power supply (right side)
V
2.375
0.82
2.5
2.625
0.88
VCCHIP_L
VCCHSSI_L
VCCHSSI_R
Transceiver hard IP power supply (left side)
Transceiver PCS power supply (left side)
Transceiver PCS power supply (right side)
0.85
0.85
0.85
0.85
1.0
V
V
V
0.82
0.88
0.82
0.88
0.82
0.88
(2)
(2)
(2)
(2)
VCCR_GXBL
VCCR_GXBR
VCCT_GXBL
VCCT_GXBR
Receiver analog power supply (left side)
Receiver analog power supply (right side)
Transmitter analog power supply (left side)
Transmitter analog power supply (right side)
0.97
1.03
V
V
V
V
1.03
1.05
0.85
1.0
1.07
0.82
0.88
0.97
1.03
1.03
1.05
0.85
1.0
1.07
0.82
0.88
0.97
1.03
1.03
1.05
0.85
1.0
1.07
0.82
0.88
0.97
1.03
1.03
1.05
1.5
1.07
VCCH_GXBL
VCCH_GXBR
Transmitter output buffer power supply (left side)
Transmitter output buffer power supply (right side)
1.425
1.425
1.575
1.575
V
V
1.5
Notes to Table 6:
(1) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps,
you can connect this supply to either 3.0 V or 2.5 V.
(2) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps, and to 1.05 V if configured at a data
rate > 10.3 Gbps when DFE is used. For data rate up to 6.5 Gbps, you can connect this supply to 0.85 V.
(3) When using ATX PLLs, the supply must be 3.0 V.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 6
Electrical Characteristics
Table 7 shows the transceiver power supply voltage requirements for various
conditions.
Table 7. Transceiver Power Supply Voltage Requirements for Arria V GZ Devices
(2)
Conditions
If BOTH of the following conditions are true:
■ Data rate > 10.3 Gbps.
VCCR_GXB and VCCT_GXB
VCCA_GXB
VCCH_GXB
Unit
1.05
■ DFE is used.
(1)
If ANY of the following conditions are true
■ ATX PLL is used.
:
3.0
1.0
■ Data rate > 6.5Gbps.
1.5
V
■ DFE (data rate ≤10.3 Gbps), AEQ, or EyeQ
feature is used.
If ALL of the following conditions are true:
■ ATX PLL is not used.
0.85
2.5
■ Data rate <= 6.5Gbps.
■ DFE, AEQ, and EyeQ are not used.
Notes to Table 7:
(1) Choose this power supply voltage requirement option if you plan to upgrade your design later with any of the listed conditions.
(2) If the VCCR_GXB and VCCT_GXB supplies are set to 1.0 V or 1.05 V, they cannot be shared with the VCC core supply. If the VCCR_GXB and
VCCT_GXB are set to 0.85 V, they can be shared with the VCC core supply.
DC Characteristics
This section lists the following specifications:
■
■
■
■
■
■
Supply Current
I/O Pin Leakage Current
Bus Hold Specifications
On-Chip Termination (OCT) Specifications
Pin Capacitance
Hot Socketing
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting.
Use the Excel-based Early Power Estimator (EPE) to get supply current estimates for
your design because these currents vary greatly with the resources you use.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 7
I/O Pin Leakage Current
Table 8 lists the Arria V GZ I/O pin leakage current specifications.
Table 8. I/O Pin Leakage Current for Arria V GZ Devices (1)
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
–30
–30
Typ
—
Max
30
Unit
µA
—
30
µA
Note to Table 8:
(1) If VO = VCCIO to VCCIOMax, 100 µA of leakage current per I/O is expected.
Bus Hold Specifications
Table 9 lists the Arria V GZ device family bus hold specifications.
Table 9. Bus Hold Parameters for Arria V GZ Devices
VCCIO
Parameter Symbol Conditions
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
Min Max
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Low
sustaining
current
VIN > VIL
ISUSL
ISUSH
IODL
22.5
–22.5
—
—
25.0
–25.0
—
—
30.0
–30.0
—
—
50.0
–50.0
—
—
70.0
–70.0
—
—
—
µA
µA
µA
(maximum)
High
sustaining
current
VIN < VIH
—
—
—
—
(minimum)
Low
overdrive
current
0V < VIN
VCCIO
<
120
160
200
300
500
High
overdrive
current
0V < VIN
VCCIO
<
IODH
—
–120
—
–160
—
–200
—
–300
—
–500 µA
Bus-hold
trip point
VTRIP
—
0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00
V
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block.
Table 10 lists the Arria V GZ OCT termination calibration accuracy specifications.
Table 10. OCT Calibration Accuracy Specifications for Arria V GZ Devices (1) (Part 1 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
C3, I3L
C4, I4
Internal series termination with VCCIO = 3.0, 2.5, 1.8, 1.5,
calibration (25-Ωsetting) 1.2 V
25-ΩRS
50-ΩRS
15
15
%
%
Internal series termination with VCCIO = 3.0, 2.5, 1.8, 1.5,
calibration (50-Ωsetting) 1.2 V
15
15
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 8
Electrical Characteristics
Table 10. OCT Calibration Accuracy Specifications for Arria V GZ Devices (1) (Part 2 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
C3, I3L
C4, I4
Internal series termination with
calibration (34-Ωand 40-Ω
setting)
VCCIO = 1.5, 1.35, 1.25,
1.2 V
34-Ωand 40-ΩRS
15
15
%
Internal series termination with
calibration (48-Ω,
48-Ω, 60-Ω, and
80-ΩRS
VCCIO = 1.2 V
15
15
%
%
60-Ω, and 80-Ωsetting)
Internal parallel termination
with calibration (50-Ωsetting)
50-ΩRT
V
CCIO = 2.5, 1.8, 1.5, 1.2 V –10 to +40
–10 to +40
Internal parallel termination
with calibration (20-Ω, 30-Ω,
40-Ω, 60-Ω, and 120-Ω
setting)
20-Ω, 30-Ω,
40-Ω,60-Ω, and
120-ΩRT
VCCIO = 1.5, 1.35, 1.25 V
–10 to +40
–10 to +40
%
Internal parallel termination
with calibration (60-Ωand
120-Ωsetting)
60-Ωand 120-Ω RT
VCCIO = 1.2
–10 to +40
15
–10 to +40
15
%
%
Internal left shift series
termination with calibration
(25-ΩRS_left_shift setting)
V
CCIO = 3.0, 2.5, 1.8, 1.5,
1.2 V
25-ΩRS_left_shift
Note to Table 10:
(1) OCT calibration accuracy is valid at the time of calibration only.
Table 11 lists the Arria V GZ OCT without calibration resistance tolerance to PVT
changes.
Table 11. OCT Without Calibration Resistance Tolerance Specifications for Arria V GZ Devices
Resistance Tolerance
Symbol
Description
Conditions
Unit
C3, I3L
C4, I4
Internal series termination
without calibration (25-Ωsetting)
25-Ω R, 50-Ω RS
25-Ω RS
VCCIO = 3.0 and 2.5 V
VCCIO = 1.8 and 1.5 V
VCCIO = 1.2 V
40
40
%
%
%
%
%
%
Internal series termination
without calibration (25-Ωsetting)
40
50
40
50
25
40
50
40
50
25
Internal series termination
without calibration (25-Ωsetting)
25-Ω RS
Internal series termination
without calibration (50-Ωsetting)
50-Ω RS
VCCIO = 1.8 and 1.5 V
Internal series termination
without calibration (50-Ωsetting)
50-Ω RS
V
V
CCIO = 1.2 V
CCIO = 2.5 V
Internal differential termination
(100-Ωsetting)
100-Ω RD
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 9
Table 12 lists the OCT variation with temperature and voltage after power-up
calibration. Use Table 12 to determine the OCT variation after power-up calibration
and Equation 1 to determine the OCT variation without re-calibration.
Equation 1. OCT Variation Without Re-Calibration for Arria V GZ Devices (1), (2), (3), (4), (5), (6)
dR
dT
dR
dV
⎛
⎞
------
-------
× ΔV〉
ROCT = RSCAL 1 + 〈
× ΔT〉 〈
⎝
⎠
Notes to Equation 1:
(1) The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO
(2) RSCAL is the OCT resistance value at power-up.
.
(3) ΔT is the variation of temperature with respect to the temperature at power-up.
(4) ΔV is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 12 lists the on-chip termination variation after power-up calibration.
Table 12. OCT Variation after Power-Up Calibration for Arria V GZ Devices (1)
Symbol
Description
VCCIO (V)
3.0
Typical
0.0297
0.0344
0.0499
0.0744
0.1241
0.189
Unit
2.5
OCT variation with voltage without
re-calibration
dR/dV
1.8
%/mV
1.5
1.2
3.0
2.5
0.208
OCT variation with temperature without
re-calibration
dR/dT
1.8
0.266
%/°C
1.5
0.273
1.2
0.317
Note to Table 12:
(1) Valid for a VCCIO range of 5% and a temperature range of 0° to 85°C.
Pin Capacitance
Table 13 lists the Arria V GZ pin capacitance.
Table 13. Pin Capacitance for Arria V GZ Devices
Symbol
Description
Value
Unit
pF
CIOTB
Input capacitance on the top and bottom I/O pins
Input capacitance on the left and right I/O pins
6
6
6
CIOLR
COUTFB
pF
Input capacitance on dual-purpose clock output and feedback pins
pF
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 10
Electrical Characteristics
Hot Socketing
Table 14 lists the hot socketing specifications for Arria V GZ devices.
Table 14. Hot Socketing Specifications for Arria V GZ Devices
Symbol Description
IIOPIN (DC)
Maximum
300 μA
8 mA (1)
100 mA
50 mA
DC current per I/O pin
AC current per I/O pin
IIOPIN (AC)
IXCVR-TX (DC)
DC current per transceiver transmitter pin
DC current per transceiver receiver pin
IXCVR-RX (DC)
Note to Table 14:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the
slew rate.
Internal Weak Pull-Up Resistor
Table 15 lists the weak pull-up resistor values for Arria V GZ devices.
Table 15. Internal Weak Pull-Up Resistor for Arria V GZ Devices (1), (2)
Symbol
Description
VCCIO Conditions (V) (3)
3.0 5%
Value (4)
25
Unit
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
2.5 5%
25
1.8 5%
25
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you enable the
programmable pull-up resistor option.
RPU
1.5 5%
25
1.35 5%
1.25 5%
1.2 5%
25
25
25
Notes to Table 15:
(1) All I/O pins have an option to enable the weak pull-up resistor except the configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCKpin. The typical value for this internal weak pull-down resistor is
approximately 25 kΩ.
(3) The pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(4) These specifications are valid with a 10% tolerance to cover changes over PVT.
I/O Standard Specifications
Table 16 through Table 21 list the input voltage (VIH and VIL), output voltage (VOH and
OL), and current drive characteristics (IOH and IOL) for various I/O standards
V
supported by Arria V GZ devices. The VOL and VOH values are valid at the
corresponding IOH and IOL, respectively.
For an explanation of the terms used in Table 16 through Table 21, refer to “Glossary”
on page 48.
Table 16. Single-Ended I/O Standards for Arria V GZ Devices (Part 1 of 2)
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
I/O
IOL
IOH
Standard
(mA)
(mA)
Min
2.85
2.85
Typ
3
Max
3.15
3.15
Min
–0.3
–0.3
Max
0.8
Min
1.7
1.7
Max
3.6
Max
0.4
Min
2.4
LVTTL
2
–2
LVCMOS
3
0.8
3.6
0.2
VCCIO – 0.2
0.1
–0.1
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 11
Table 16. Single-Ended I/O Standards for Arria V GZ Devices (Part 2 of 2)
V
CCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
VOH (V)
I/O
Standard
IOL
(mA)
IOH
(mA)
Min
Typ
Max
Min
Min
Max
Max
Min
2.5 V
1.8 V
2.375
2.5
2.625
–0.3
0.7
1.7
3.6
0.4
2
1
2
–1
–2
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
0.3
+
+
+
VCCIO
0.45
–
1.71
1.425
1.14
1.8
1.5
1.2
1.89
1.575
1.26
–0.3
–0.3
–0.3
0.45
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
1.5 V
1.2 V
2
2
–2
–2
0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
Table 17. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Arria V GZ Devices
VCCIO (V)
Typ
VREF (V)
Typ
VTT (V)
Typ
I/O Standard
Min
Max
Min
Max
Min
Max
VREF
0.04
SSTL-2
Class I, II
0.49 ×
VCCIO
0.51 ×
VCCIO
VREF
–
+
2.375
2.5
1.8
2.625
0.5 × VCCIO
0.9
VREF
VREF
0.04
SSTL-18
Class I, II
VREF
–
VREF
+
1.71
1.425
1.283
1.19
1.89
1.575
1.418
1.26
1.26
1.89
1.575
1.26
1.3
0.833
0.969
0.04
0.04
SSTL-15
Class I, II
0.49 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 ×
VCCIO
0.51 ×
VCCIO
1.5
0.5 × VCCIO
0.5 × VCCIO
0.5 × VCCIO
0.5 × VCCIO
0.9
SSTL-135
Class I, II
0.49 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 ×
VCCIO
0.51 ×
VCCIO
1.35
1.25
1.20
1.8
SSTL-125
Class I, II
0.49 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 ×
VCCIO
0.51 ×
VCCIO
SSTL-12
Class I, II
0.49 ×
VCCIO
0.51 ×
VCCIO
0.49 ×
VCCIO
0.5 ×
VCCIO
0.51 ×
VCCIO
1.14
HSTL-18
Class I, II
1.71
0.85
0.68
0.95
0.9
—
—
—
—
VCCIO/2
VCCIO/2
VCCIO/2
—
—
—
—
—
HSTL-15
Class I, II
1.425
1.14
1.5
0.75
HSTL-12
Class I, II
0.47 ×
VCCIO
0.53 ×
VCCIO
1.2
0.5 × VCCIO
0.5 × VCCIO
0.49 ×
VCCIO
0.51 ×
VCCIO
HSUL-12
1.14
1.2
Table 18. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V GZ Devices (Part 1 of 2)
V
IL(DC) (V)
Max
VREF
VIH(DC) (V)
Min Max
VREF
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
I/O Standard
Iol (mA) Ioh (mA)
Min
SSTL-2
Class I
–
+
VCCIO
0.3
+
+
+
VREF
–
VTT
–
VTT
+
–0.3
–0.3
–0.3
VREF + 0.31
VREF + 0.31
VREF + 0.25
8.1
16.2
6.7
–8.1
–16.2
–6.7
0.15
0.15
0.31
0.608
0.608
SSTL-2
Class II
VREF
–
VREF
0.15
+
VCCIO
0.3
VREF
–
VTT
–
VTT
+
0.15
0.31
0.81
0.81
SSTL-18
Class I
VREF
–
VREF
0.125
+
VCCIO
0.3
VREF
–
VTT
–
VTT +
0.603
0.125
0.25
0.603
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 12
Electrical Characteristics
Table 18. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Arria V GZ Devices (Part 2 of 2)
V
IL(DC) (V)
Max
VREF
VIH(DC) (V)
Min Max
VREF
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
I/O Standard
Iol (mA) Ioh (mA)
Min
SSTL-18
Class II
–
+
VCCIO
0.3
+
VREF
–
VCCIO
–
–0.3
—
VREF + 0.25
0.28
13.4
8
–13.4
–8
0.125
0.125
0.25
0.28
SSTL-15
Class I
VREF
0.1
–
–
–
VREF
0.1
+
+
+
VREF
–
VREF
+
0.2 ×
VCCIO
0.8 ×
VCCIO
—
—
—
—
—
—
—
—
—
0.175
0.175
SSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
–
VREF
+
0.2 ×
VCCIO
0.8 ×
VCCIO
—
16
—
—
—
8
–16
—
0.175
0.175
SSTL-135
Class I, II
VREF
VREF
0.09
VREF
–
0.2 *
VCCIO
0.8 *
VCCIO
—
VREF + 0.16
0.09
0.16
SSTL-125
Class I, II
VREF
–
VREF
0.85
+
VREF
–
0.2 *
VCCIO
0.8 *
VCCIO
—
VREF + 0.15
VREF + 0.15
—
0.85
0.15
SSTL-12
Class I, II
VREF
0.1
–
VREF
0.1
+
VREF
–
0.2 *
VCCIO
0.8 *
VCCIO
—
—
0.15
HSTL-18
Class I
VREF
0.1
–
–
–
–
–
VREF
0.1
+
+
+
+
+
VCCIO
0.4
–
—
VREF – 0.2 VREF + 0.2
VREF – 0.2 VREF + 0.2
VREF – 0.2 VREF + 0.2
VREF – 0.2 VREF + 0.2
0.4
0.4
0.4
0.4
–8
HSTL-18
Class II
VREF
0.1
VREF
0.1
VCCIO
0.4
–
–
–
—
16
8
–16
–8
HSTL-15
Class I
VREF
0.1
VREF
0.1
VCCIO
0.4
—
HSTL-15
Class II
VREF
0.1
VREF
0.1
VCCIO
0.4
—
16
8
–16
–8
HSTL-12
Class I
VREF
VREF
VCCIO
+
+
VREF
–
0.25 ×
VCCIO
0.75 ×
VCCIO
–0.15
–0.15
—
VREF + 0.15
VREF + 0.15
VREF + 0.22
0.08
0.08
0.15
0.15
HSTL-12
Class II
VREF
–
VREF
+
VCCIO
0.15
VREF
–
0.25 ×
VCCIO
0.75 ×
VCCIO
16
—
–16
—
0.08
0.08
0.15
VREF
–
VREF
0.13
+
VREF
–
0.1 ×
VCCIO
0.9 ×
VCCIO
HSUL-12
—
0.13
0.22
Table 19. Differential SSTL I/O Standards for Arria V GZ Devices (Part 1 of 2)
V
CCIO (V)
Typ
VSWING(DC) (V)
VX(AC) (V)
VSWING(AC) (V)
Min Max
I/O Standard
Min
Max
Min
Max
Min
Typ
Max
SSTL-2 Class
I, II
VCCIO
0.6
+
VCCIO/2 –
0.2
VCCIO/2 +
0.2
VCCIO
0.6
+
2.375
2.5
1.8
2.625
0.3
0.25
0.2
—
0.62
0.5
SSTL-18Class
I, II
VCCIO
0.6
+
VCCIO/2 –
0.175
VCCIO/2 +
0.175
VCCIO
0.6
+
1.71
1.425
1.283
1.19
1.89
1.575
1.45
—
SSTL-15Class
I, II
VCCIO/2 –
0.15
VCCIO/2 +
0.15
(1)
(1)
(1)
1.5
—
0.35
—
SSTL-135
Class I, II
VCCIO/2 –
0.15
VCCIO/2 + 2(VIH(AC) 2(VIL(AC)
1.35
1.25
0.2
VCCIO/2
VCCIO/2
0.15
VCCIO/2 + 2(VIH(AC)
0.15 - VREF
- VREF
)
- VREF
)
SSTL-125
Class I, II
VCCIO/2 –
0.15
1.31
0.18
—
)
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 13
Table 19. Differential SSTL I/O Standards for Arria V GZ Devices (Part 2 of 2)
VCCIO (V)
Typ
VSWING(DC) (V)
VX(AC) (V)
Typ
VSWING(AC) (V)
I/O Standard
Min
Max
Min
0.18
Max
Min
Max
Min
Max
SSTL-12
Class I, II
VREF
–0.15
VREF
+
1.14
1.2
1.26
—
VCCIO/2
–0.30
0.30
0.15
Notes to Table 19:
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits
(VIH(DC) and VIL(DC)).
Table 20. Differential HSTL and HSUL I/O Standards for Arria V GZ Devices
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
Min Max
I/O
Standard
Min Typ Max Min
Max
Min
Max
Min
Max
HSTL-18
Class I, II
1.71 1.8 1.89
0.2
0.2
—
0.78
—
—
1.12
0.78
—
—
1.12
0.4
0.4
0.3
—
—
HSTL-15
Class I, II
1.42
5
1.57
5
1.5
—
0.68
0.9
0.68
0.9
HSTL-12
Class I, II
VCCIO
+ 0.3
0.5 ×
VCCIO
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
VCCIO
+ 0.48
1.14 1.2 1.26 0.16
—
—
0.5 ×
0.5 ×
0.5 ×
VCCIO
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
HSUL-12
1.14 1.2
1.3
0.26 0.26 VCCIO
–
VCCIO
+
0.44
0.44
0.12
0.12
Table 21. Differential I/O Standard Specifications for Arria V GZ Devices (Part 1 of 2)
(6)
(6)
V
CCIO (V) (9)
VID (mV) (7)
VICM(DC) (V)
VOD (V)
VOCM (V)
Typ
I/O
Standard
Min Typ Max Min Condition Max Min Condition Max
Min Typ Max Min
Max
Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 22 on page 15.
PCML
DMAX
700 Mbps
≤
—
0.05
1.8 0.247
1.55 0.247
—
0.6 1.125 1.25 1.375
0.6 1.125 1.25 1.375
2.5 V
LVDS
VCM
1.25 V
=
2.375 2.5 2.625 100
(1)
DMAX
700 Mbps
>
—
—
—
1.05
—
—
—
BLVDS (5) 2.375 2.5 2.625 100
RSDS
—
—
—
—
—
—
—
—
VCM
1.25 V
=
2.375 2.5 2.625 100
0.3
—
—
1.4
0.1
0.2 0.6
0.5
1.2
1.4
(2)
(HIO)
Mini-
LVDS
(HIO)
2.375 2.5 2.625 200
—
600 0.4
1.325 0.25
—
0.6
1
1.2
1.4
(3)
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 14
Electrical Characteristics
Table 21. Differential I/O Standard Specifications for Arria V GZ Devices (Part 2 of 2)
(6)
(6)
VCCIO (V) (9)
VID (mV) (7)
VICM(DC) (V)
VOD (V)
VOCM (V)
I/O
Standard
Min Typ Max Min Condition Max Min Condition Max
Min Typ Max Min
Typ
Max
DMAX
700 Mbps
≤
2.375 2.5 2.625 300
2.375 2.5 2.625 300
—
—
—
—
0.6
1
1.8
1.6
—
—
—
—
—
—
—
—
—
—
LVPECL (8)
, (4)
DMAX
700 Mbps
>
—
—
Notes to Table 21:
(1) For optimized LVDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.6 V for data rates above 700 Mbps, and 0 V to 1.85
V for data rates below 700 Mbps.
(2) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.
(3) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V.
(4) For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V
to 1.95 V for data rate below 700 Mbps.
(5) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.
(6) RL range: 90 ≤RL ≤110 Ω.
(7) The minimum VID value is applicable over the entire common mode range, VCM.
(8) LVPECL is only supported on dedicated clock input pins.
(9) Differential inputs are powered by VCCPD which requires 2.5 V.
Power Consumption
Altera offers two ways to estimate power consumption for a design—the Excel-based
Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature.
1
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 15
Switching Characteristics
This section provides performance characteristics of the Arria V GZ core and
periphery blocks.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 22 lists the Arria V GZ transceiver specifications.
Table 22. Transceiver Specifications for Arria V GZ Devices (1) (Part 1 of 5)
Transceiver Speed
Grade 2
Transceiver Speed
Symbol/
Description
Grade 3
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Reference Clock
Dedicated reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML,
Differential LVPECL, LVDS, and HCSL
Supported I/O Standards
RX reference clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference Clock Frequency
(CMU PLL) (7)
—
40
—
—
710
710
40
—
—
710
710
MHz
MHz
Input Reference Clock Frequency
(ATX PLL) (7)
—
100
100
Rise time
Fall time
20% to 80%
80% to 20%
—
—
—
45
—
—
—
400
400
55
—
—
45
—
—
—
400
400
55
ps
Duty cycle
%
Spread-spectrum modulating
clock frequency
PCI Express® (PCIe®)
30
—
—
33
—
30
—
—
33
—
kHz
0 to
–0.5
100
0 to
–0.5
100
Spread-spectrum downspread
On-chip termination resistors
PCIe
—
%
—
—
—
—
—
—
Ω
Dedicated reference
clock pin
—
1.6
—
1.6
Absolute VMAX
V
RX reference clock pin
—
—
—
—
1.2
—
—
—
—
1.2
—
Absolute VMIN
–0.4
–0.4
V
Peak-to-peak differential input
voltage
—
200
—
1600
200
—
1600
mV
Dedicated reference
clock pin
(2)
(2)
1000/900/850
1000/900/850
mV
mV
mV
VICM (AC coupled)
VICM (DC coupled)
RX reference clock pin
1.0/0.9/0.85 (3)
550
1.0/0.9/0.85 (3)
550
HCSL I/O standard for
PCIe reference clock
250
—
250
—
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 16
Switching Characteristics
Table 22. Transceiver Specifications for Arria V GZ Devices (1) (Part 2 of 5)
Transceiver Speed
Transceiver Speed
Symbol/
Grade 2
Grade 3
Conditions
Unit
Description
Min
—
—
—
—
—
Typ
—
—
—
—
—
Max
-70
Min
—
—
—
—
—
Typ
—
—
—
—
—
Max
-70
100 Hz
1 kHz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-90
-90
Transmitter REFCLK Phase
Noise (622 MHz) (18)
10 kHz
100 kHz
≥1 MHz
-100
-110
-120
-100
-110
-120
Transmitter REFCLK Phase Jitter
(100 MHz) (15)
10 kHz to 1.5 MHz
(PCIe)
ps
(rms)
—
—
—
3
—
—
—
3
1800
1%
1800
1%
RREF
—
—
—
Ω
Transceiver Clocks
PCIe
Receiver Detect
100or
125
100or
125
fixedclkclock frequency
Reconfiguration clock
—
—
—
—
MHz
MHz
—
100
—
125
100
—
125
(mgmt_clk_clk) frequency
Receiver
Supported I/O Standards
Data rate (Standard PCS)
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
(8) (19)
,
—
—
600
600
—
—
9900
600
600
—
—
8800
Mbps
Data rate (10G PCS) (8)
,
12500
10312.5 Mbps
(19)
Absolute VMAX for a receiver pin
—
—
—
—
—
1.2
—
—
—
—
1.2
—
V
V
(4)
Absolute VMIN for a receiver pin
–0.4
–0.4
Maximum peak-to-peak
differential input voltage VID (diff
p-p) before device configuration
—
—
—
1.6
—
—
1.6
V
VCCR_GXB = 1.0 V
(VICM = 0.75 V)
Maximum peak-to-peak
differential input voltage VID (diff
p-p) after device
—
—
—
—
1.8
2.4
—
—
—
—
1.8
2.4
V
V
V
CCR_GXB = 0.85 V
(VICM = 0.6 V)
configuration (16)
Minimum differential eye
opening at receiver serial input
—
85
—
—
85
—
—
mV
(5)
pins
85
30%
85
30%
85−Ωsetting
100−Ωsetting
120−Ωsetting
150-Ωsetting
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Ω
Ω
Ω
Ω
100
30%
100
30%
Differential on-chip termination
resistors
120
30%
120
30%
150
30%
150
30%
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 17
Table 22. Transceiver Specifications for Arria V GZ Devices (1) (Part 3 of 5)
Transceiver Speed
Transceiver Speed
Grade 3
Symbol/
Description
Grade 2
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
VCCR_GXB = 0.85 V
full bandwidth
—
600
600
700
700
—
—
—
—
—
600
—
—
—
—
mV
mV
mV
mV
VCCR_GXB = 0.85 V
half bandwidth
—
—
—
—
—
—
600
700
700
VICM (AC and DC coupled)
VCCR_GXB = 1.0 V
full bandwidth
VCCR_GXB = 1.0 V
half bandwidth
(9)
tLTR
—
—
—
—
—
4
—
—
—
—
10
—
—
—
—
4
—
—
—
—
10
—
—
—
µs
µs
µs
µs
(10)
tLTD
(11)
tLTD_manual
4
4
(12)
tLTR_LTD_manual
15
15
Data rate: 600 Mbps to
1 Gbps
—
—
300
—
—
100
CDR PPM Tolerance
Data rate: 1 Gbps to
6 Gbps
PPM
—
—
—
—
300
300
—
—
—
—
100
100
Data rate: ≥ 6 Gbps
Full bandwidth
(6.25 GHz)
Programmable equalization
(AC Gain)
—
—
16
—
—
16
dB
Half bandwidth
(3.125 GHz)
DC gain setting = 0
DC gain setting = 1
DC gain setting = 2
DC gain setting = 3
DC gain setting = 4
—
—
—
—
—
0
2
4
6
8
—
—
—
—
—
—
—
—
—
—
0
2
4
6
8
—
—
—
—
—
dB
dB
dB
dB
dB
Programmable DC gain
Transmitter
Supported I/O Standards
Data rate (Standard PCS)
Data rate (10G PCS)
1.4-V and 1.5-V PCML
—
—
600
600
—
—
9900
600
600
—
—
8800
Mbps
12500
10312.5 Mbps
85
20%
85
20%
85-Ωsetting
100-Ωsetting
120-Ωsetting
—
—
—
—
—
—
—
—
—
—
—
—
Ω
Ω
Ω
100
20%
100
20%
Differential on-chip termination
resistors
120
20%
120
20%
150
20%
150
20%
150-Ωsetting
—
—
—
—
—
—
—
—
Ω
VOCM (AC coupled)
0.65-V setting
650
650
mV
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 18
Switching Characteristics
Table 22. Transceiver Specifications for Arria V GZ Devices (1) (Part 4 of 5)
Transceiver Speed
Transceiver Speed
Symbol/
Grade 2
Grade 3
Conditions
Unit
Description
Min
—
Typ
650
650
—
Max
—
Min
—
Typ
650
650
—
Max
—
<=6.5 Gbps
>6.5 Gbps
—
mV
mV
ps
VOCM (DC coupled)
—
—
—
—
(6)
Rise time
Fall time
30
160
160
30
160
160
(6)
—
30
—
30
—
ps
Tx VCM = 0.5 V and slew
rate of 15 ps
Intra-differential pair skew
—
—
15
—
—
15
ps
Intra-transceiver block
transmitter channel-to-channel
skew
x6 PMA bonded mode
xN PMA bonded mode
—
—
120
—
—
120
ps
Inter-transceiver block
transmitter channel-to-channel
skew
—
—
500
—
—
500
ps
CMU PLL
Supported data range
—
—
—
600
1
—
—
—
12500
—
600
1
—
—
—
10312.5 Mbps
(13)
tpll_powerdown
—
10
µs
µs
(14)
tpll_lock
10
—
ATX PLL
VCO post-divider
L = 2
8000
—
12500 8000
—
10312.5 Mbps
Supported data range
L = 4
4000
1000
1
—
—
—
—
6600
3300
—
4000
1000
1
—
—
—
—
6600
3300
—
Mbps
Mbps
µs
(17)
L = 8
(13)
tpll_powerdown
—
—
(14)
tpll_lock
—
10
—
10
µs
fPLL
Supported data range
—
—
600
1
—
—
3250
—
600
1
—
—
3250
—
Mbps
µs
(13)
tpll_powerdown
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 19
Table 22. Transceiver Specifications for Arria V GZ Devices (1) (Part 5 of 5)
Transceiver Speed
Transceiver Speed
Grade 3
Symbol/
Description
Grade 2
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
10
(14)
tpll_lock
—
—
—
10
—
µs
Notes to Table 22:
(1) Speed grades shown in Table 22 refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the
Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination
offered. For more information about device ordering codes, refer to the Arria V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) This supply follows VCCR_GXB.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(6) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(7) The input reference clock frequency options depend on the data rate and the device speed grade.
(8) The line data rate may be limited by PCS-FPGA interface speed grade.
(9) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(10) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
(11) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the
CDR is functioning in the manual mode.
(12) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when
the CDR is functioning in the manual mode.
(13) tpll_powerdown is the PLL powerdown minimum pulse width.
(14) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(15) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(16) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(17) This clock can be further divided by central or local clock dividers making it possible to use ATX PLL for data rates < 1 Gbps. For more
information about ATX PLLs, refer to the Transceiver Clocking in Arria V Devices chapter and the Dynamic Reconfiguration in Arria V Devices
chapter.
(18) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(19) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
Table 23 shows the maximum transmitter data rate for the clock network.
(1)
Table 23. Clock Network Maximum Data Rate Transmitter Specifications
(Part 1 of 2)
ATX PLL
CMU PLL (2)
fPLL
Non-
bonded
Mode
Non-
Non-
Bonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Clock Network
Channel bonded
Channel bonded
Channel
Span
Span
Mode
(Gbps)
Span
Mode
(Gbps)
(Gbps)
x1 (3)
x6 (3)
12.5
—
—
6
6
12.5
—
—
6
6
3.125
—
—
3
6
12.5
12.5
3.125
x6 PLL
Side-
wide
Side-
wide
—
—
12.5
8.0
—
—
12.5
5.0
—
—
—
—
—
—
Feedback (4)
xN (PCIe)
8
8
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 20
Switching Characteristics
(1)
Table 23. Clock Network Maximum Data Rate Transmitter Specifications
(Part 2 of 2)
ATX PLL
CMU PLL (2)
fPLL
Non-
bonded
Mode
Non-
Non-
Bonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Bonded
Channel
Mode
Clock Network
Channel bonded
Channel bonded
Span
Mode
(Gbps)
Span
Mode
(Gbps)
Span
(Gbps)
(Gbps)
Up to 13
channels
above
and
below
PLL
8.0
—
8.0
Up to 13
channels
above
and
below
PLL
Up to 13
channels
above
and
below
PLL
xN (Native PHY IP)
7.99
7.99
3.125
3.125
Up to 7
channels
above
and
8.01 to
9.8304
below
PLL
Notes to Table 23:
(1) Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the
MegaWizard message during the PHY IP instantiation.
(2) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
(3) Channel span is within a transceiver bank.
(4) Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
Table 24 shows the approximate maximum data rate using the standard PCS.
(2)
Table 24. Standard PCS Approximate Maximum Date Rate (Gbps) for Arria V GZ Devices
PMA Width
20
40
20
20
16
32
16
16
10
20
10
10
8
8
8
Transceiver
Speed Grade
(1)
Mode
PCS/Core Width
16
C3, I3L
core speed grade
2
3
2
3
9.9
8.8
9.9
8.8
9
7.84
7.2
7.2
6.56
7.2
5.3
4.8
4.9
4.4
4.7
4.3
4.,5
4.1
4.24
3.84
3.92
3.52
3.76
3.44
3.6
FIFO
C4, I4
core speed grade
8.2
9
C3, I3L
core speed grade
7.92
7.04
Register
C4, I4
core speed grade
8.2
6.56
3.28
Notes to Table 24:
(1) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
(2) The maximum data rate is also constrained by the transceiver speed grade. Refer to Table 1 on page 1 for the transceiver speed grade.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 21
Table 25 shows the approximate maximum data rate using the 10G PCS
Table 25. 10G PCS Approximate Maximum Data Rate (Gbps) for Arria V GZ Devices
PMA Width
PCS Width
64
64
40
40
50
40
40
32
32
32
Transceiver
Speed Grade
(1)
Mode
66/67
64/66/67
C3, I3L
core speed grade
2
3
2
3
12.5
10.3125
12.5
12.5
10.3125
12.5
10.69
10.69
10.69
10.69
12.5
10.3125
12.5
10.88
9.92
10.88
FIFO
C4, I4
core speed grade
9.92
10.88
9.92
C3,I3L
core speed grade
10.88
9.92
Register
C4, I4
core speed grade
10.3125
10.3125
10.3125
Note to Table 25:
(1) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 22
Switching Characteristics
Table 26 shows the VOD settings for the Arria V GZ channel.
Table 26. Typical VOD Setting for Arria V GZ Channel, TX Termination = 100 Ω(2)
V
OD Value
(mV)
V
OD Value
(mV)
Symbol
VOD Setting
VOD Setting
0 (1)
1 (1)
2 (1)
3 (1)
4 (1)
5 (1)
6
0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
640
660
20
40
680
60
700
80
720
100
120
140
160
180
200
220
240
260
280
300
320
340
360
380
400
420
440
460
480
500
520
540
560
580
600
620
740
760
7
780
8
800
9
820
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
840
860
880
900
920
940
V
OD differential peak to peak typical
960
980
1000
1020
1040
1060
1080
1100
1120
1140
1160
1180
1200
1220
1240
1260
Notes to Table 26:
(1) If TX termination resistance = 100Ω, this VOD setting is illegal.
(2) The tolerance is +/-20% for all VOD settings except for settings 2 and below.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 23
Figure 1 shows the AC gain curves for Arria V GZ channels.
Figure 1. AC Gain Curves for Arria V GZ Channels (full bandwidth)
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks, configuration, and JTAG specifications.
Clock Tree Specifications
Table 27 lists the clock tree specifications for Arria V GZ devices.
Table 27. Clock Tree Performance for Arria V GZ Devices
Performance
Symbol
Unit
C3, I3L
C4, I4
580
Global and Regional Clock
Periphery Clock
650
500
MHz
MHz
500
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 24
Switching Characteristics
PLL Specifications
Table 28 lists the Arria V GZ PLL block performance specifications.
Table 28. PLL Specifications for Arria V GZ Devices (Part 1 of 3)
Symbol
Parameter
Min
5
Typ
—
—
—
—
—
—
—
—
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Input clock frequency (C1, C2, I2 speed grade)
Input clock frequency (C3, I3 speed grade)
Input clock frequency (C4, I4 speed grade)
Input frequency to the PFD
800
800
(1)
fIN
5
5
650
fINPFD
5
325
fFINPFD
Fractional Input clock frequency to the PFD
PLL VCO operating range (C1, C2, I2 speed grade)
PLL VCO operating range (C3, I3 speed grade)
PLL VCO operating range (C4, I4 speed grade)
50
600
600
600
160
1600
1600
1300
(9)
fVCO
Input clock or external feedback clock input duty
cycle
tEINDUTY
40
—
—
—
—
—
—
—
—
—
—
—
—
—
60
%
Output frequency for an internal global or regional
clock (C1, C2, I2 speed grade)
717
650
580
800
667
533
MHz
MHz
MHz
MHz
MHz
MHz
Output frequency for an internal global or regional
clock (C3, I3 speed grade)
(2)
fOUT
Output frequency for an internal global or regional
clock (c4, I4 speed grade)
Output frequency for an external clock output (C1,
C2, I2 speed grade)
Output frequency for an external clock output (C3, I3
speed grade)
(2)
fOUT_EXT
Output frequency for an external clock output (C4, I4
speed grade)
Duty cycle for a dedicated external clock output
(when set to 50%)
tOUTDUTY
tFCOMP
fDYCONFIGCLK
tLOCK
45
—
—
50
—
—
55
10
%
ns
External feedback clock compensation time
Dynamic configuration clock for mgmt_clkand
scanclk
100
MHz
Time required to lock from the end-of-device
configuration or deassertion of areset
—
—
—
—
1
1
ms
ms
Time required to lock dynamically (after switchover
or reconfiguring any non-post-scale counters/delays)
tDLOCK
PLL closed-loop low bandwidth
—
—
0.3
1.5
4
—
—
MHz
MHz
fCLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth (7)
—
—
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
—
50
ps
Minimum pulse width on the aresetsignal
Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (fREF < 100 MHz)
10
—
ns
—
0.15
+750
UI (p-p)
ps (p-p)
(3), (4)
tINCCJ
-750
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 25
Table 28. PLL Specifications for Arria V GZ Devices (Part 2 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Period Jitter for dedicated clock output in integer PLL
(fOUT ≥ 100 MHz)
—
—
175
ps (p-p)
mUI (p-p)
ps (p-p)
(5)
tOUTPJ_DC
Period Jitter for dedicated clock output in integer PLL
(fOUT < 100 Mhz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17.5
Period Jitter for dedicated clock output in fractional
PLL (fOUT ≥ 100 MHz)
250 (10)
,
175 (11)
(5)
tFOUTPJ_DC
Period Jitter for dedicated clock output in fractional
PLL (fOUT < 100 MHz)
25 (10)
,
mUI (p-p)
ps (p-p)
17.5 (11)
Cycle-to-cycle Jitter for a dedicated clock output in
integer PLL (fOUT ≥ 100 MHz)
175
(5)
tOUTCCJ_DC
Cycle-to-cycle Jitter for a dedicated clock output in
integer PLL (fOUT < 100 MHz)
17.5
mUI (p-p)
ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT ≥ 100 MHz)
250 (10)
175 (11)
,
(5)
tFOUTCCJ_DC
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT < 100 MHz)
25 (10)
,
mUI (p-p)
ps (p-p)
17.5 (11)
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT ≥ 100 MHz)
600
(5), (8)
tOUTPJ_IO
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT < 100 MHz)
60
600
60
mUI (p-p)
ps (p-p)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT ≥ 100 MHz)
(5), (8),
tFOUTPJ_IO
(10)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in integer PLL (fOUT ≥ 100 MHz)
600
60
(5), (8)
(5),
tOUTCCJ_IO
Cycle-to-cycle Jitter for a clock output on a regular
I/O in integer PLL (fOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in fractional PLL (fOUT ≥ 100 MHz)
600
60
tFOUTCCJ_IO
(8), (10)
Cycle-to-cycle Jitter for a clock output on a regular
I/O in fractional PLL (fOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT ≥ 100 MHz)
175
tCASC_OUTPJ_DC
(5), (6)
Period Jitter for a dedicated clock output in cascaded
PLLS (fOUT < 100 MHz)
—
24
17.5
32
mUI (p-p)
dKBIT
Bit number of Delta Sigma Modulator (DSM)
Numerator of Fraction
8
Bits
—
kVALUE
128
8388608 2147483648
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 26
Switching Characteristics
Table 28. PLL Specifications for Arria V GZ Devices (Part 3 of 3)
Symbol
fRES
Parameter
Min
Typ
Max
0.023
Unit
Resolution of VCO frequency (fINPFD = 100 MHz)
390625
5.96
Hz
Notes to Table 28:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter
< 120 ps.
(4) The fREF is fIN/N specification applies when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 41 on page 35.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz ≤Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) The external memory interface clock output jitter specifications use a different measurement method, which is available in Table 39 on page 33.
(9) The VCO frequency reported by the Quartus II software in the PLL Usage Summary section of the compilation report takes into consideration
the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(10) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
DSP Block Specifications
Table 29 lists the Arria V GZ DSP block performance specifications.
Table 29. DSP Block Performance Specifications for Arria V GZ Devices (Part 1 of 2)
Performance
Mode
Unit
C3, I3L
C4
I4
Modes using One DSP Block
Three 9 × 9
480
480
480
400
400
400
400
400
420
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
One 18 × 18
420
420
400
400
Two partial 18 × 18 (or 16 × 16)
One 27 × 27
350
350
350
350
350
One 36 × 18
One sum of two 18 × 18 (One sum of two 16 × 16)
One sum of square
One 18 × 18 plus 36 (a × b) + c
Modes using Two DSP Blocks
Three 18 × 18
400
380
380
380
400
380
350
300
MHz
MHz
MHz
MHz
MHz
MHz
One sum of four 18 × 18
One sum of two 27 × 27
One sum of two 36 × 18
One complex 18 × 18
One 36 × 36
300
275
290
265
300
350
300
Modes using Three DSP Blocks
One complex 18 × 25
340
MHz
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 27
Table 29. DSP Block Performance Specifications for Arria V GZ Devices (Part 2 of 2)
Performance
Mode
Unit
C3, I3L
C4
I4
Modes using Four DSP Blocks
One complex 27 × 27
350
310
MHz
Memory Block Specifications
Table 30 lists the Arria V GZ memory block specifications.
Table 30. Memory Block Performance Specifications for Arria V GZ Devices (1), (2)
Resources Used
Performance
Memory
Mode
Unit
ALUTs
Memory
C3
C4
I3L
400
400
533
500
500
I4
Single port, all supported widths
Simple dual-port, x32/x64 width
Simple dual-port, x16 width (3)
ROM, all supported widths
0
0
0
0
0
1
1
1
1
1
400
400
533
500
650
315
315
400
450
550
315
315
400
450
450
MHz
MHz
MHz
MHz
MHz
MLAB
Single-port, all supported widths
Simple dual-port, all supported
widths
0
0
0
0
1
1
1
1
650
455
400
500
550
400
350
450
500
455
400
500
450
400
350
450
MHz
MHz
MHz
MHz
Simple dual-port with the
read-during-write option set to Old
Data, all supported widths
M20K
Block
Simple dual-port with ECC enabled,
512 × 32
Simple dual-port with ECC and
optional pipeline registers enabled,
512 × 32
True dual port, all supported widths
ROM, all supported widths
0
0
1
1
650
650
550
550
500
500
450
450
MHz
MHz
Notes to Table 30:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX
.
(3) The FMAX specification is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled.
Temperature Sensing Diode Specifications
Table 31 lists the internal temperature sensing diode (TSD) specification.
Table 31. Internal Temperature Sensing Diode Specification
Minimum
Resolution
with no
Offset
Calibrated
Option
Temperature
Range
Conversion
Time
Accuracy
Sampling Rate
Resolution
Missing Codes
–40°C to 100°C
8°C
No
1 MHz, 500 kHz
< 100 ms
8 bits
8 bits
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 28
Switching Characteristics
Table 32 lists the specifications for the Arria V GZ external temperature sensing diode.
Table 32. External Temperature Sensing Diode Specifications for Arria V GZ Devices
Description
Ibias, diode source current
bias, voltage across diode
Min
8
Typ
—
Max
200
Unit
μA
V
V
0.3
—
0.9
Series resistance
—
—
< 1
Ω
Diode ideality factor
1.006
1.008
1.010
—
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of a typical 167 MHz and 1.2-LVCMOS at 100 MHz interfacing frequency
with a 10 pF load.
1
The actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 33 lists high-speed I/O timing for Arria V GZ devices.
Table 33. High-Speed I/O Specifications for Arria V GZ Devices (1), (2) (Part 1 of 3)
C3, I3L
C4, I4
Typ
Symbol
Conditions
Unit
MHz
MHz
Min
Typ
Max
Min
Max
f
HSCLK_in (input clock
Clock boost factor
W = 1 to 40
frequency) True
Differential I/O Standards
5
—
625
5
—
—
525
(4)
f
HSCLK_in (input clock
Clock boost factor
W = 1 to 40
frequency) Single Ended
5
—
625
420
5
525
420
(4)
I/O Standards (3)
fHSCLK_in (input clock
Clock boost factor
frequency) Single Ended
I/O Standards
5
5
—
—
5
5
—
—
MHz
MHz
(4)
W = 1 to 40
fHSCLK_OUT (output clock
frequency)
(5)
(5)
—
625
525
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 29
Table 33. High-Speed I/O Specifications for Arria V GZ Devices (1), (2) (Part 2 of 3)
C3, I3L
C4, I4
Typ
Symbol
Conditions
Unit
Min
Typ
Max
Min
Max
Transmitter
SERDES factor J = 3 to 10
(6)
(6)
(6)
(6)
—
—
1250
1600
—
—
1050
1250
Mbps
Mbps
(9), (10)
SERDES factor J ≥ 4
(12)
True Differential I/O
Standards - fHSDR (data
rate)
LVDS TX with DPA
,
(14), (15), (16)
SERDES factor J = 2,
uses DDR Registers
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
—
—
—
—
Mbps
Mbps
SERDES factor J = 1,
uses SDR Register
Emulated Differential I/O
Standards with Three
(6)
(6)
External Output Resistor SERDES factor J = 4 to 10
Networks - fHSDR (data
—
840
—
840
Mbps
(11)
rate)
Total Jitter for Data Rate
600 Mbps - 1.25 Gbps
—
—
—
—
—
—
—
—
160
0.1
300
0.2
—
—
—
—
—
—
—
—
160
0.1
ps
UI
ps
UI
tx Jitter - True Differential
I/O Standards
Total Jitter for Data Rate
< 600 Mbps
Total Jitter for Data Rate
600 Mbps - 1.25 Gbps
tx Jitter - Emulated
Differential I/O Standards
with Three External
325
0.25
Total Jitter for Data Rate
< 600 Mbps
Output Resistor Network
Transmitter output clock
duty cycle for both True
and Emulated Differential
I/O Standards
tDUTY
45
—
—
50
—
—
55
45
—
—
50
—
—
55
%
ps
ps
True Differential I/O
Standards
200
250
200
300
Emulated Differential I/O
Standards with three
external output resistor
networks
tRISE & tFALL
True Differential I/O
Standards
—
—
—
—
150
300
—
—
—
—
150
300
ps
ps
TCCS
Emulated Differential I/O
Standards
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 30
Switching Characteristics
Table 33. High-Speed I/O Specifications for Arria V GZ Devices (1), (2) (Part 3 of 3)
C3, I3L
C4, I4
Typ
Symbol
Conditions
Unit
Max
Min
Typ
Max
Min
Receiver
SERDES factor
(12), (13),
J = 3 to 10 (10),
150
—
1250
150
—
1050
Mbps
(14), (15), (16)
SERDES factor J ≥ 4
True Differential I/O
Standards - fHSDRDPA (data
rate)
(12),
150
—
—
1600
150
—
—
1250
Mbps
Mbps
LVDS RX with DPA
(14), (15), (16)
SERDES factor J = 2,
uses DDR Registers
(6)
(7)
(6)
(7)
SERDES factor J = 1,
uses SDR Register
(6)
(6)
(6)
(7)
(8)
(7)
(6)
(6)
(6)
(7)
(8)
(7)
—
—
—
—
—
—
Mbps
Mbps
Mbps
SERDES factor J = 3 to 10
SERDES factor J = 2,
uses DDR Registers
fHSDR (data rate)
SERDES factor J = 1,
uses SDR Register
(6)
(7)
(6)
(7)
—
—
Mbps
DPA Mode
DPA run length
—
—
—
—
—
—
—
—
—
10000
300
—
—
—
—
—
—
10000
300
UI
Soft CDR mode
Soft-CDR ppm tolerance
ppm
ps
Non DPA Mode
Sampling Window
Notes to Table 33:
300
300
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) This only applies to DPA and soft-CDR modes.
(4) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(5) This is achieved by using the LVDS clock network.
(6) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(7) The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing
and the signal integrity simulation is clean.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
(9) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(10) The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which
is design dependent and requires timing analysis.
(11) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(12) Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
(13) Arria V GZ LVDS serialization and de-serialization factor needs to be x4 and above.
(14) Requires package skew compensation with PCB trace length.
(15) Do not mix single-ended I/O buffer within LVDS I/O bank.
(16) Chip-to-chip communication only with a maximum load of 5 pF.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 31
Figure 2 shows the dynamic phase alignment (DPA) lock time specifications with the
DPA PLL calibration option enabled.
Figure 2. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Table 34 lists the DPA lock time specifications for Arria V GZ devices.
Table 34. DPA Lock Time Specifications for Arria V GZ Devices (1), (2), (3)
Number of Data
Number of
Transitions in One
Standard
Training Pattern
Repetitions per 256
Maximum
Repetition of the
Training Pattern
(4)
Data Transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Parallel Rapid I/O
10010000
10101010
32
Miscellaneous
01010101
32
Notes to Table 34:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 3 shows the LVDS soft-clock data recovery (CDR)/DPA sinusoidal jitter
tolerance specification for a data rate ≥ 1.25 Gbps.
Figure 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate ≥ 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.35
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 32
Switching Characteristics
Table 35 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate ≥ 1.25 Gbps.
Table 35. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate ≥ 1.25 Gbps
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
25.000
F1
F2
F3
F4
10,000
17,565
25.000
1,493,000
50,000,000
0.350
0.350
Figure 4 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate < 1.25 Gbps.
Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate < 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
DLL Range, DQS Logic Block, and Memory Output Clock Jitter Specifications
Table 36 lists the DLL range specification for Arria V GZ devices. The DLL is always
in 8-tap mode in Arria V GZ devices.
(1)
Table 36. DLL Range Specifications for Arria V GZ Devices
Parameter
DLL operating frequency range
Note to Table 36:
C3, I3L
C4, I4
Unit
300 – 890
300 – 890
MHz
(1) Arria V GZ devices support memory interface frequencies lower than 300 MHz, although the reference clock that feeds the DLL must be at least
300 MHz. To support interfaces below 300 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported
range of the DLL.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 33
Table 37 lists the DQS phase offset delay per stage for Arria V GZ devices.
Table 37. DQS Phase Offset Delay Per Setting for Arria V GZ Devices (1), (2)
Speed Grade
C3, I3L
Min
8
Max
15
Unit
ps
C4, I4
8
16
ps
Notes to Table 37:
(1) The typical value equals the average of the minimum and maximum values.
(2) The delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when using a –3 speed grade and
applying a 10-phase offset setting to a 90° phase shift at 400 MHz, the expected average cumulative delay is
[625 ps + (10 × 11 ps) 20 ps] = 735 ps 20 ps.
Table 38 lists the DQS phase shift error for Arria V GZ devices.
Table 38. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V GZ Devices (1)
Number of DQS Delay Buffers
C3, I3L
C4, I4
Unit
1
2
3
4
30
60
32
64
ps
ps
ps
ps
90
96
120
128
Note to Table 38:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a –3 speed grade is
84 ps or 42 ps.
Table 39 lists the memory output clock jitter specifications for Arria V GZ devices.
Table 39. Memory Output Clock Jitter Specification for Arria V GZ Devices (1), (2), (3) (Part 1 of 2)
C3, I3L
C4, I4
Clock
Parameter
Clock period jitter
Symbol
Unit
Network
Min
–55
Max
55
Min
–55
Max
55
tJIT(per)
tJIT(cc)
ps
ps
ps
ps
ps
ps
Regional
Global
Cycle-to-cycle period jitter
Duty cycle jitter
–110
–82.5
–82.5
–165
–90
110
82.5
82.5
165
90
–110
–82.5
–82.5
–165
–90
110
82.5
82.5
165
90
tJIT(duty)
tJIT(per)
tJIT(cc)
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
tJIT(duty)
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 34
Switching Characteristics
Table 39. Memory Output Clock Jitter Specification for Arria V GZ Devices (1), (2), (3) (Part 2 of 2)
C3, I3L
C4, I4
Clock
Parameter
Clock period jitter
Symbol
Unit
Network
Min
–30
–60
–45
Max
30
Min
–35
–70
–56
Max
35
tJIT(per)
tJIT(cc)
ps
ps
ps
PHY Clock
Cycle-to-cycle period jitter
Duty cycle jitter
60
70
tJIT(duty)
45
56
Notes to Table 39:
(1) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by
a PLL output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible.
(2) The clock jitter specification applies to the memory output clock pins clocked by an integer PLL.
(3) The memory output clock jitter is applicable when an input jitter of 30 ps peak-to-peak is applied with bit error rate (BER) -12, equivalent to 14
sigma.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 35
OCT Calibration Block Specifications
Table 40 lists the OCT calibration block specifications for Arria V GZ devices.
Table 40. OCT Calibration Block Specifications for Arria V GZ Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by the OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for OCT RS/RT
calibration
TOCTCAL
—
—
1000
32
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for the OCT
code to shift out
TOCTSHIFT
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT RS and RT (Figure 5)
TRS_RT
—
2.5
—
ns
Figure 5 shows the timing diagram for the oeand dyn_term_ctrlsignals.
Figure 5. Timing Diagram for oe and dyn_term_ctrl Signals
Tristate
Tristate
RX
TX
RX
oe
dyn_term_ctrl
T
T
RS_RT
RS_RT
Duty Cycle Distortion (DCD) Specifications
Table 41 lists the worst-case DCD for Arria V GZ devices.
Table 41. Worst-Case DCD on Arria V GZ I/O Pins (1)
C3, I3L
C4, I4
Symbol
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Note to Table 41:
(1) The DCD numbers do not cover the core clock network.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 36
Configuration Specification
Configuration Specification
This section provides configuration specifications and timing for Arria V GZ devices.
POR Specifications
Table 42 lists the specifications for fast and standard POR for Arria V GZ devices.
Table 42. Fast and Standard POR Delay Specification for Arria V GZ Devices (1)
POR Delay
Fast
Minimum (ms)
Maximum (ms)
12 (2)
4
Standard
100
300
Notes to Table 42:
(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Arria V Devices”
table in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter
(2) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize
after the POR trip.
JTAG Configuration Specifications
Table 43 lists the JTAG timing parameters and values for Arria V GZ devices.
Table 43. JTAG Timing Parameters and Values for Arria V GZ Devices
Symbol
Description
Min
30
167 (1)
14
14
2
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCP
tJCH
tJCL
TCK clock period
TCK clock period
TCK clock high time
TCK clock low time
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
3
5
(2)
tJPCO
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
—
—
—
11
14
14
(2)
(2)
tJPZX
tJPXZ
Notes to Table 43:
(1) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2V-1.5V when you perform the volatile
key programming.
(2) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 37
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Arria V GZ devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[]ratio when you turn on
encryption or the compression feature.
Table 44 lists the DCLK-to-DATA[]ratio for each combination.
Table 44. DCLK-to-DATA[] Ratio for Arria V GZ Devices (1)
Configuration
Scheme
DCLK-to-DATA[]
Ratio
Decompression
Design Security
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
1
1
2
2
1
2
4
4
1
4
8
8
FPP ×8
FPP ×16
FPP ×32
Note to Table 44:
(1) Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the data rate in bytes
per second (Bps), or words per second (Wps). For example, in FPP ×16 when the DCLK-to-DATA[]ratio is 2, the
DCLKfrequency must be 2 times the data rate in Wps. Arria V GZ devices use the additional clock cycles to decrypt
and decompress the configuration data.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 38
Configuration Specification
FPP Configuration Timing when DCLK to DATA[] = 1
Figure 6 shows the timing waveform for FPP configuration when using a MAX® II or
MAX V device as an external host. This waveform shows timing when the DCLK-to-
DATA[]ratio is 1.
1
When you enable the decompression or design security feature, the DCLK-to-DATA[]
ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the respective DCLK-to-DATA[]ratio,
refer to Table 44.
Figure 6. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1 (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
(6)
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
Word 0 Word 1 Word 2 Word 3
DATA[31..0](5)
Word n-2 Word n-1
User Mode
User Mode
tDSU
High-Z
User I/O
(7)
INIT_DONE
tCD2UM
Notes to Figure 6:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONEare at logic-high levels. When
nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power-up, the Arria V GZ device holds nSTATUSlow for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(5) For FPP ×16, use DATA[15..0]. For FPP ×8, use DATA[7..0]. DATA[31..0]are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONEis released high when the Arria V GZ
device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization
and enter user mode.
(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 39
Table 45 lists the timing parameters for Arria V GZ devices for FPP configuration
when the DCLK-to-DATA[]ratio is 1.
Table 45. FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is 1 (1)
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
Minimum
Maximum
600
600
—
1,506 (2)
1,506 (3)
—
Unit
ns
ns
μs
μs
μs
μs
μs
ns
ns
s
—
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
—
2
tSTATUS
tCF2ST1
nSTATUSlow pulse width
268
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
—
(6)
tCF2CK
1,506
(6)
tST2CK
2
—
tDSU
tDH
tCH
5.5
0
—
—
0.45 × 1/fMAX
0.45 × 1/fMAX
1/fMAX
—
tCL
DCLKlow time
—
s
tCLK
DCLK period
—
s
DCLKfrequency (FPP × 8/× 16)
DCLKfrequency (FPP × 32)
—
125
100
437
MHz
MHz
μs
fMAX
—
(4)
tCD2UM
tCD2CU
CONF_DONEhigh to user mode
175
4 × maximum
DCLKperiod
CONF_DONEhigh to CLKUSRenabled
—
—
—
tCD2CU
+
tCD2UMC CONF_DONEhigh to user mode with CLKUSRoption on
(17,408 × CLKUSR
—
period) (5)
Notes to Table 45:
(1) Use these timing parameters when the decompression and design security features are disabled.
(2) This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(3) This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(5) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
“Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(6) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 40
Configuration Specification
FPP Configuration Timing when DCLK to DATA[] > 1
Figure 7 shows the timing waveform for FPP configuration when using a MAX II
device, MAX V device, or microprocessor as an external host. This waveform shows
timing when the DCLK-to-DATA[]ratio is more than 1.
(1), (2)
Figure 7. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
tSTATUS
tCF2ST0
CONF_DONE (4)
t
CL
tCF2CD
(8)
tST2CK
t
CH
DCLK (6)
DATA[31..0] (8)
User I/O
(7)
(5)
1
2
1
1
2
r
1
2
r
r
t
CLK
Word 0
Word 1
Word (n-1)
User Mod
User Mod
Word 3
t
t
tDSU
DH
DH
High-Z
(9)
INIT_DONE
tCD2UM
Notes to Figure 7:
(1) To find out the DCLK-to-DATA[]ratio for your system, refer to Table 44 on page 37.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONEare at logic high levels.
When nCONFIGis pulled low, a reconfiguration cycle begins.
(3) After power-up, the Arria V GZ device holds nSTATUSlow for the time as specified by the POR delay.
(4) After power-up, before and during configuration, CONF_DONEis low.
(5) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(6) “r” denotes the DCLK-to-DATA[]ratio. For the DCLK-to-DATA[]ratio based on the decompression and the design security feature enable
settings, refer to Table 44 on page 37.
(7) If needed, pause DCLKby holding it low. When DCLKrestarts, the external host must provide data on the DATA[31..0]pins prior to sending
the first DCLKrising edge.
(8) To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONEis released high after the Arria V GZ
device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin
initialization and enter user mode.
(9) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 41
Table 46 lists the timing parameters for Arria V GZ devices for FPP configuration
when the DCLK-to-DATA[]ratio is more than 1.
Table 46. FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1 (1)
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
Minimum
Maximum
600
600
—
1,506 (2)
1,506 (3)
—
Unit
ns
ns
μs
μs
μs
μs
μs
ns
s
—
—
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
nSTATUSlow pulse width
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
2
tSTATUS
tCF2ST1
268
—
(7)
tCF2CK
1,506
2
(7)
tST2CK
—
tDSU
tDH
tCH
5.5
—
(4)
N–1/fDCLK
—
0.45 × 1/fMAX
—
s
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
DCLKperiod
1/fMAX
—
—
s
DCLKfrequency (FPP × 8/× 16)
DCLKfrequency (FPP × 32)
Input rise time
125
100
40
MHz
MHz
ns
ns
μs
fMAX
—
tR
—
tF
Input fall time
—
40
(5)
tCD2UM
CONF_DONEhigh to user mode
175
437
4 × maximum
DCLKperiod
tCD2CU
CONF_DONEhigh to CLKUSRenabled
—
—
tCD2CU
+
tCD2UMC CONF_DONEhigh to user mode with CLKUSRoption on
(17,408 × CLKUSR
—
—
period) (6)
Notes to Table 46:
(1) Use these timing parameters when you use the decompression and design security features.
(2) You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(3) You can obtain this value if you do not delay configuration by externally holding the nSTATUSlow.
(4) N is the DCLK-to-DATAratio and fDCLK is the DCLKfrequency the system is operating.
(5) The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
(6) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
“Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(7) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 42
Configuration Specification
Active Serial Configuration Timing
Figure 8 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Figure 8. AS Configuration Timing
t
CF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
t
CO
t
DH
Read Address
AS_DATA0/ASDO
AS_DATA1 (1)
t
SU
bit (n − 2) bit (n − 1)
bit 1
bit 0
t
(2)
CD2UM
INIT_DONE (3)
User I/O
User Mode
Notes to Figure 8:
(1) If you are using AS ×4 mode, this signal represents the AS_DATA[3..0]and EPCQ sends in 4-bits of data for each DCLKcycle.
(2) The initialization clock can be from internal oscillator or CLKUSRpin.
(3) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
Table 47 lists the timing parameters for AS x1 and AS x4 configurations in Arria V GZ
devices.
Table 47. AS Timing Parameters for AS x1 and AS x4 Configurations in Arria V GZ Devices (1), (2)
Symbol
tCO
Parameter
Minimum
Maximum
Unit
ns
DCLKfalling edge to AS_DATA0/ASDOoutput
Data setup time before falling edge on DCLK
Data hold time after falling edge on DCLK
—
1.5
0
4
tSU
—
ns
tH
—
ns
(3)
tCD2UM
CONF_DONEhigh to user mode
175
437
μs
4 × maximum DCLK
tCD2CU
CONF_DONEhigh to CLKUSRenabled
—
—
—
—
period
tCD2CU + (17,408 ×
CLKUSRperiod)
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
Notes to Table 47:
(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(2) tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in Table 49 on page 44.
(3) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to the
“Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 43
Table 48 lists the internal clock frequency specification for the AS configuration
scheme.
Table 48. DCLK Frequency Specification in the AS Configuration Scheme (1), (2)
Minimum
5.3
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
21.3
50.0
42.6
100.0
Notes to Table 48:
(1) This applies to the DCLKfrequency specification when using the internal oscillator as the configuration clock source.
(2) The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.
Passive Serial Configuration Timing
Figure 9 shows the timing waveform for a passive serial (PS) configuration when
using a MAX II device, MAX V device, or microprocessor as an external host.
(1)
Figure 9. PS Configuration Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
(6)
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
(5)
DCLK
tDH
Bit 2 Bit 3
Bit 0 Bit 1
DATA0
Bit (n-1)
tDSU
High-Z
User I/O
User Mode
INIT_DONE (7)
tCD2UM
Notes to Figure 9:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONEare at logic high levels. When
nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power-up, the Arria V GZ device holds nSTATUSlow for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA0is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins
Option.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONEis released high after the Arria V GZ
device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin
initialization and enter user mode.
(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 44
Configuration Specification
Table 49 lists the PS configuration timing parameters for Arria V GZ devices.
Table 49. PS Timing Parameters for Arria V GZ Devices
Symbol
tCF2CD
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
600
600
—
1,506 (1)
1,506 (2)
—
Unit
ns
ns
μs
μs
μs
μs
μs
ns
ns
s
—
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
2
nSTATUSlow pulse width
268
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
—
(5)
tCF2CK
1,506
(5)
tST2CK
2
—
tDSU
tDH
5.5
—
0
0.45 × 1/fMAX
0.45 × 1/fMAX
1/fMAX
—
tCH
—
tCL
DCLKlow time
—
s
tCLK
fMAX
tCD2UM
DCLKperiod
—
s
DCLKfrequency
—
125
437
MHz
μs
(3)
CONF_DONEhigh to user mode
175
4 × maximum
DCLKperiod
tCD2CU
CONF_DONEhigh to CLKUSRenabled
—
—
tCD2CU
+
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
(17,408 × CLKUSR
—
—
(4)
period)
Notes to Table 49:
(1) This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(2) This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
(3) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(4) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
“Initialization” section of the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(5) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
Initialization
Table 50 lists the initialization clock source option, the applicable configuration
schemes, and the maximum frequency.
Table 50. Initialization Clock Source Option and the Maximum Frequency for Arria V GZ Devices
Maximum
Initialization Clock Source
Configuration Schemes
Minimum Number of Clock Cycles
Frequency (MHz)
Internal Oscillator
AS, PS, FPP
PS, FPP
AS
12.5
125
100
17,408
(1)
CLKUSR
Note to Table 50:
(1) To enable CLKUSRas the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software
from the General panel of the Device and Pin Options dialog box.
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 45
Configuration Files
Use Table 51 to estimate the file size before design compilation. Different
configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf)
format, have different file sizes.
For the different types of configuration file and file sizes, refer to the Quartus II
software. However, for a specific version of the Quartus II software, any design
targeted for the same device has the same uncompressed configuration file size.
Table 51 lists the uncompressed raw binary file (.rbf) sizes for Arria V GZ devices.
Table 51. Uncompressed .rbf Sizes for Arria V GZ Devices
Configuration .rbf Size
(bits)
Variant
Member Code
IOCSR .rbf Size (bits)
E1
E3
E5
E7
137,598,720
137,598,720
213,798,720
213,798,720
562,208
562,208
561,760
561,760
Arria V GZ
Table 52 lists the minimum configuration time estimates for Arria V GZ devices.
Table 52. Minimum Configuration Time Estimation for Arria V GZ Devices
Active Serial (1)
Fast Passive Parallel (2)
Member
Variant
Min Config
Time (ms)
Min Config
Code
Width
DCLK (MHz)
Width
DCLK (MHz)
Time (ms)
E1
E3
E5
E7
4
4
4
4
100
100
100
100
344
344
534
534
32
32
32
32
100
100
100
100
43
43
67
67
Arria V GZ
Notes to Table 52:
(1) DCLK frequency of 100 MHz using external CLKUSR.
(2) Max FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Remote System Upgrades Circuitry Timing Specification
Table 53 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 53. Remote System Upgrade Circuitry Timing Specifications (Part 1 of 2)
Parameter
Minimum
—
Maximum
Unit
MHz
ns
(1)
fMAX_RU_CLK
40
—
(2)
tRU_nCONFIG
250
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 46
I/O Timing
Table 53. Remote System Upgrade Circuitry Timing Specifications (Part 2 of 2)
Parameter
Minimum
Maximum
Unit
(3)
tRU_nRSTIMER
250
—
ns
Notes to Table 53:
(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE
megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.
(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. refer to the “Remote System Upgrade State Machine” section in the Configuration,
Design Security, and Remote System Upgrades in Arria V Devices chapter.
(3) This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “User Watchdog Timer” section in the
Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
User Watchdog Internal Oscillator Frequency Specification
Table 54 lists the frequency specifications for the user watchdog internal oscillator.
Table 54. User Watchdog Internal Oscillator Frequency Specifications
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis.
The Quartus II Timing Analyzer provides a more accurate and precise I/O timing
data based on the specifics of the design after you complete place-and-route.
f
You can download the Excel-based I/O Timing spreadsheet from the Arria V Devices
Documentation webpage.
Programmable IOE Delay
Table 55 lists the Arria V GZ IOE programmable delay settings.
Table 55. IOE Programmable Delay for Arria V GZ Devices (Part 1 of 2)
Fast Model
Available
Slow Model
(1)
(2)
Parameter
Min Offset
Unit
Settings
Industrial
0.464
Commercial
0.493
C3
C4
I3L
I4
D1
D2
D3
D4
D5
64
32
8
0
0
0
0
0
0.924
0.459
2.992
0.924
0.924
1.011
0.503
3.192
1.011
1.011
0.921
0.456
3.047
0.920
0.921
1.006
0.500
3.257
1.006
1.006
ns
ns
ns
ns
ns
0.230
0.244
1.587
1.699
64
64
0.464
0.492
0.464
0.493
Arria V GZ Device Datasheet
December 2013 Altera Corporation
I/O Timing
Page 47
Table 55. IOE Programmable Delay for Arria V GZ Devices (Part 2 of 2)
Fast Model
Available
Slow Model
(1)
(2)
Parameter
Min Offset
Unit
Settings
Industrial
Commercial
C3
C4
I3L
I4
D6
32
0
0.229
0.244
0.458
0.503
0.456
0.499
ns
Notes to Table 55:
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column of Assignment Editor.
(2) Minimum offset does not include the intrinsic delay.
Programmable Output Buffer Delay
Table 56 lists the delay chain settings that control the rising and falling edge delays of
the output buffer. The default delay is 0 ps.
Table 56. Programmable Output Buffer Delay for Arria V GZ Devices (1)
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
Rising and/or falling edge
delay
DOUTBUF
100
ps
150
ps
Notes to Table 56:
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 48
Glossary
Glossary
Table 57 lists the glossary for this chapter.
Table 57. Glossary (Part 1 of 4)
Letter
Subject
Definitions
A
B
C
—
—
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
Ground
IL
V
CM
Differential Waveform
V
ID
p − n = 0 V
V
ID
Differential I/O
Standards
D
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p − n = 0 V
V
OD
E
F
—
—
fHSCLK
Left and right PLL input clock frequency.
High-speed I/O block—Maximum and minimum LVDS data transfer rate
fHSDR
(fHSDR = 1/TUI), non-DPA.
High-speed I/O block—Maximum and minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
G
H
I
—
—
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Glossary
Page 49
Table 57. Glossary (Part 2 of 4)
Letter
Subject
Definitions
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
J
TMS
TDI
tJCP
J
JTAG Timing
Specifications
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
K
L
M
N
O
—
—
(1)
Diagram of PLL Specifications
CLKOUT Pins
fOUT_EXT
Switchover
4
CLK
fIN
fINPFD
N
GCLK
RCLK
Counters
C0..C17
fVCO
VCO
fOUT
PFD
CP
LF
Core Clock
PLL
Specifications
P
Delta Sigma
Modulator
Key
External Feedback
Reconfigurable in User Mode
Note:
(1) Core Clockcan only be fed by dedicated clock input pins or PLL outputs.
Q
R
—
—
RL
Receiver differential input discrete resistor (external to the Arria V GZ device).
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 50
Glossary
Table 57. Glossary (Part 3 of 4)
Letter
Subject
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
SW (sampling
window)
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
The JEDEC standard for SSTL and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing:
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
VCCIO
referenced I/O
standard
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
VOL
VSS
tC
High-speed receiver and transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
TCCS (channel-
to-channel-skew)
High-speed I/O block—Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and the data sampling window.
T
(TUI = 1/(receiver input clock frequency multiplication factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the general purpose I/O driven by a PLL.
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20-80%)
—
tINCCJ
tOUTPJ_IO
tOUTPJ_DC
tRISE
U
—
Arria V GZ Device Datasheet
December 2013 Altera Corporation
Document Revision History
Page 51
Table 57. Glossary (Part 4 of 4)
Letter
Subject
VCM(DC)
Definitions
DC common mode input voltage.
VICM
Input common mode voltage—The common mode of the differential signal at the receiver.
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VDIF(AC)
VDIF(DC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH
VIH(AC)
VIH(DC)
High-level AC input voltage
High-level DC input voltage
V
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL
VIL(AC)
VIL(DC)
Low-level AC input voltage
Low-level DC input voltage
Output common mode voltage—The common mode of the differential signal at the
transmitter.
VOCM
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
VX
Differential input voltage
Input differential cross point voltage
Output differential cross point voltage
High-speed I/O block—clock boost factor
VOX
W
W
X
Y
Z
—
—
Document Revision History
Table 58 lists the revision history for this document.
Table 58. Document Revision History (Part 1 of 2)
Date
Version
3.6
Changes
■ Updated Table 2, Table 13, Table 18, Table 19, Table 22, Table 30, Table 33, Table 37,
Table 38, Table 45, Table 46, Table 47, Table 56, Table 49
December 2013
August 2013
■ Updated “PLL Specifications”
3.5
Updated Table 28.
■ Removed Preliminary tags for Table 2, Table 4, Table 5, Table 14, Table 27, Table 28,
Table 29, Table 31, Table 32, Table 43, Table 45, Table 46, Table 47, Table 48, Table 49,
Table 50, and Table 54
August 2013
June 2013
3.4
3.3
■ Updated Table 2 and Table 28
Updated Table 23, Table 28, Table 51, and Table 55
December 2013 Altera Corporation
Arria V GZ Device Datasheet
Page 52
Document Revision History
Table 58. Document Revision History (Part 2 of 2)
Date
Version
Changes
Added Table 23
May 2013
3.2
Updated Table 5, Table 22, Table 26, and Table 57
Updated Figure 6, Figure 7, Figure 8, and Figure 9
Updated Table 2, Table 6, Table 7, Table 8, Table 19, Table 22, Table 26, Table 29, Table 52
Updated “Maximum Allowed Overshoot and Undershoot Voltage”
Initial release.
March 2013
3.1
3.0
December 2012
Arria V GZ Device Datasheet
December 2013 Altera Corporation
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SI9122E
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