5CEBA2M13C7N [INTEL]
Field Programmable Gate Array, PBGA383, ROHS COMPLIANT, MBGA-383;
| 型号： | 5CEBA2M13C7N |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, PBGA383, ROHS COMPLIANT, MBGA-383 LTE 栅 可编程逻辑 |
| 文件： | 总64页 (文件大小：1355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Cyclone V Device Datasheet
December 2013
CV-51002-3.7
CV-51002-3.7
Datasheet
This datasheet describes the electrical characteristics, switching characteristics,
configuration specifications, and I/O timing for Cyclone® V devices.
Cyclone V devices are offered in commercial and industrial grades. Commercial
devices are offered in –C6 (fastest), –C7, and –C8 speed grades. Industrial devices are
offered in the –I7 speed grade. Automotive devices are offered in the –A7 speed
grade.
f
For more information about the densities and packages of devices in the Cyclone V
family, refer to the Cyclone V Device Overview.
Electrical Characteristics
The following sections describe the electrical characteristics of Cyclone V devices.
Operating Conditions
Cyclone V devices are rated according to a set of defined parameters. To maintain the
highest possible performance and reliability of the Cyclone V devices, you must
consider the operating requirements described in this datasheet.
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their
respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
ISO
9001:2008
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Registered
December 2013 Altera Corporation
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Page 2
Electrical Characteristics
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Cyclone V
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms.
The functional operation of the device is not implied for these conditions.
c Conditions other than those listed in Table 1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 1 lists the Cyclone V absolute maximum ratings.
Table 1. Absolute Maximum Ratings for Cyclone V Devices
Symbol
VCC
Description
Core voltage and periphery circuitry power supply
Configuration pins power supply
Auxiliary supply
Minimum
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–25
Maximum
1.43
3.90
3.25
3.90
3.90
3.90
3.25
3.25
1.50
1.50
3.80
1.43
3.90
3.90
3.25
3.25
40
Unit
V
VCCPGM
VCC_AUX
VCCBAT
V
V
Battery back-up power supply for design security volatile key register
I/O pre-driver power supply
V
VCCPD
V
VCCIO
I/O power supply
V
VCCA_FPLL
VCCH_GXB
VCCE_GXB
VCCL_GXB
VI
PLL analog power supply
V
Transceiver high voltage power
Transceiver power
V
V
Transceiver clock network power
DC input voltage
V
V
VCC_HPS
VCCPD_HPS
VCCIO_HPS
HPS core voltage and periphery circuitry power supply
HPS I/O pre-driver power supply
HPS I/O power supply
V
V
V
VCCRSTCLK_HPS HPS reset and clock input pins power supply
V
VCCPLL_HPS
IOUT
HPS PLL analog power supply
DC output current per pin
V
mA
°C
°C
TJ
Operating junction temperature
Storage temperature (No bias)
–55
125
TSTG
–65
150
Cyclone V Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 3
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2 and
undershoot to -2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time
over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the
lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years.
Table 2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime.
Table 2. Maximum Allowed Overshoot During Transitions for Cyclone V Devices
Symbol
Description
Condition (V)
3.8
Overshoot Duration as % of High Time
Unit
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
100
68
45
28
15
13
11
9
3.85
3.9
3.95
4
4.05
4.1
4.15
4.2
Vi (AC)
AC input voltage
8
4.25
4.3
7
5.4
3.2
1.9
1.1
0.6
0.4
0.2
4.35
4.4
4.45
4.5
4.55
4.6
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 4
Electrical Characteristics
Recommended Operating Conditions
Recommended operating conditions are the functional operation limits for the AC
and DC parameters for Cyclone V devices.
Table 3 lists the steady-state voltage values expected from Cyclone V devices. Power
supply ramps must all be strictly monotonic, without plateaus.
Table 3. Recommended Operating Conditions for Cyclone V Devices (Part 1 of 2)
Symbol
Description
Condition
Minimum Typical Maximum Unit
Core voltage, periphery circuitry power supply,
transceiver physical coding sublayer (PCS)
power supply, and transceiver PCI Express®
(PCIe®) hard IP digital power supply
VCC
—
1.07
1.1
1.13
V
VCC_AUX
Auxiliary supply
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.375
3.135
2.85
2.5
3.3
3.0
2.5
3.3
3.0
2.5
1.8
1.5
1.35
1.25
1.2
3.3
3.0
2.5
1.8
2.5
2.625
3.465
3.15
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
I/O pre-driver (3.3 V) power supply
I/O pre-driver (3.0 V) power supply
I/O pre-driver (2.5 V) power supply
I/O buffers (3.3 V) power supply
I/O buffers (3.0 V) power supply
I/O buffers (2.5 V) power supply
I/O buffers (1.8 V) power supply
I/O buffers (1.5 V) power supply
I/O buffers (1.35 V) power supply
I/O buffers (1.25 V) power supply
I/O buffers (1.2 V) power supply
Configuration pins (3.3 V) power supply
Configuration pins (3.0 V) power supply
Configuration pins (2.5 V) power supply
Configuration pins (1.8 V) power supply
PLL analog voltage regulator power supply
(1)
VCCPD
2.375
3.135
2.85
2.625
3.465
3.15
2.375
1.71
2.625
1.89
VCCIO
1.425
1.283
1.19
1.575
1.418
1.31
1.14
1.26
3.135
2.85
3.465
3.15
VCCPGM
2.375
1.71
2.625
1.89
(2)
VCCA_FPLL
2.375
2.625
Battery back-up power supply
(For design security volatile key register)
(3)
VCCBAT
—
1.2
—
3.0
V
VI
DC input voltage
Output voltage
—
–0.5
0
—
—
—
—
—
3.6
VCCIO
85
V
VO
—
V
Commercial
Industrial
Automotive
0
°C
°C
°C
TJ
Operating junction temperature
–40
–40
100
125
Cyclone V Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 5
Table 3. Recommended Operating Conditions for Cyclone V Devices (Part 2 of 2)
Symbol
Description
Power supply ramp time
Condition
Standard POR
Fast POR
Minimum Typical Maximum Unit
200 µs
200 µs
—
—
100 ms
4 ms
—
—
(4)
tRAMP
Notes to Table 3:
(1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO
is 3.3 V.
(2) PLL digital voltage is regulated from VCCA_FPLL
.
(3) If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. The power-on reset
(POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT is not powered up.
(4) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and
tRAMP specifications for fast POR when HPS_PORSEL = 1.
Table 4 lists the transceiver power supply recommended operating conditions for
Cyclone V GX, GT, SX, and ST devices.
Table 4. Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices
Symbol
VCCH_GXBL
Description
Minimum
2.375
Typical
2.5
Maximum
2.625
Unit
V
Transceiver high voltage power (left side)
Transmitter and receiver power (left side)
Clock network power (left side)
(1), (2)
VCCE_GXBL
VCCL_GXBL
1.07/1.17
1.07/1.17
1.1/1.2
1.1/1.2
1.13/1.23
1.13/1.23
V
(1), (2)
V
Notes to Table 4:
(1) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full
compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in
Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(2) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter
specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144Gbps (Cyclone V GT devices only). For more information about the
maximum full duplex channels recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations
in Cyclone V Devices chapter.
Table 5 lists the steady-state voltage values expected from Cyclone V
system-on-a-chip (SoC) devices with ARM®-based hard processor system (HPS).
Power supply ramps must all be strictly monotonic, without plateaus.
Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices (1) (Part 1 of 2)
Symbol
VCC_HPS
Description
Minimum
Typical
Maximum
Unit
HPS core voltage and periphery circuitry power
supply
1.07
1.1
1.13
V
HPS I/O pre-driver (3.3 V) power supply
HPS I/O pre-driver (3.0 V) power supply
HPS I/O pre-driver (2.5 V) power supply
HPS I/O buffers (3.3 V) power supply
HPS I/O buffers (3.0 V) power supply
HPS I/O buffers (2.5 V) power supply
HPS I/O buffers (1.8 V) power supply
HPS I/O buffers (1.5 V) power supply
3.135
2.85
3.3
3.0
2.5
3.3
3.0
2.5
1.8
1.5
1.35
1.2
3.465
3.15
V
V
V
V
V
V
V
V
V
V
(2)
VCCPD_HPS
2.375
3.135
2.85
2.625
3.465
3.15
2.375
1.71
2.625
1.89
VCCIO_HPS
1.425
1.283
1.14
1.575
1.418
1.26
(3)
HPS I/O buffers (1.35 V) power supply
HPS I/O buffers (1.2 V) power supply
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 6
Electrical Characteristics
Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices (1) (Part 2 of 2)
Symbol
Description
Minimum
3.135
2.85
Typical
3.3
Maximum
3.465
3.15
Unit
V
HPS reset and clock input pins (3.3 V) power supply
HPS reset and clock input pins (3.0 V) power supply
HPS reset and clock input pins (2.5 V) power supply
HPS reset and clock input pins (1.8 V) power supply
HPS PLL analog voltage regulator power supply
HPS and FPGA shared auxiliary power supply
3.0
V
VCCRSTCLK_HPS
2.375
1.71
2.5
2.625
1.89
V
1.8
V
VCCPLL_HPS
2.375
2.375
2.5
2.625
2.625
V
VCC_AUX_SHARED
Notes to Table 5:
2.5
V
(1) Refer to Table 3 for the steady-state voltage values expected from the FPGA portion of the Cyclone V SoC devices.
(2) VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when
VCCIO_HPS is 3.3 V.
(3) VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.
DC Characteristics
This section lists the following specifications:
■
■
■
■
■
■
Supply Current and Power Consumption
I/O Pin Leakage Current
Bus Hold Specifications
OCT Specifications
Pin Capacitance
Hot Socketing
Supply Current and Power Consumption
Standby current is the current drawn from the respective power rails used for power
budgeting.
Altera offers two ways to estimate power for your design—the Excel-based Early
Power Estimator (EPE) and the Quartus® II PowerPlay Power Analyzer feature.
Use the Excel-based Early Power Estimator (EPE) before you start your design to
estimate the supply current for your design. The EPE provides a magnitude estimate
of the device power because these currents vary greatly with the resources you use.
The Quartus II PowerPlay Power Analyzer provides better quality estimates based on
the specifics of the design after you complete place-and-route. The PowerPlay Power
Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yields very
accurate power estimates.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 7
I/O Pin Leakage Current
Table 6 lists the Cyclone V I/O pin leakage current specifications.
Table 6. I/O Pin Leakage Current for Cyclone V Devices
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
–30
–30
Typ
—
Max
30
Unit
µA
—
30
µA
Bus Hold Specifications
Table 7 lists the Cyclone V device bus hold specifications. The bus-hold trip points are
based on calculated input voltages from the JEDEC standard.
Table 7. Bus Hold Parameters for Cyclone V Devices
VCCIO (V)
Parameter Symbol Conditions
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold,
low,
sustaining
current
VIN > VIL
(max.)
ISUSL
ISUSH
IODL
8
—
—
12
–12
—
—
—
30
–30
—
—
—
50
–50
—
—
—
70
–70
—
—
—
70
–70
—
—
—
µA
µA
Bus-hold,
high,
sustaining
current
VIN < VIH
(min.)
–8
—
Bus-hold,
low,
overdrive
current
0V < VIN
VCCIO
<
125
–125
175
–175
200
–200
300
500
500 µA
–500 µA
Bus-hold,
high,
overdrive
current
0V < VIN
VCCIO
<
IODH
—
—
—
—
–300
1.7
—
–500
2
—
Bus-hold
trip point
VTRIP
—
0.3
0.9 0.375 1.125 0.68 1.07 0.7
0.8
0.8
2
V
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 8
Electrical Characteristics
OCT Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically
performed at power up for I/Os connected to the calibration block.
Table 8 lists the Cyclone V OCT termination calibration accuracy specifications. The
OCT calibration accuracy is valid at the time of calibration only.
Table 8. OCT Calibration Accuracy Specifications for Cyclone V Devices
Calibration Accuracy
–C7, –I7
Symbol
Description
Conditions (V)
Unit
%
–C6
–C8, –A7
Internal series termination
with calibration
(25-Ω setting)
V
CCIO = 3.0, 2.5,
1.8, 1.5, 1.2
25-Ω RS
15
15
15
15
15
Internal series termination
with calibration
(50-Ω setting)
V
CCIO = 3.0, 2.5,
1.8, 1.5, 1.2
50-Ω RS
15
15
15
15
%
Internal series termination
V
CCIO = 1.5, 1.35,
1.25, 1.2
34-Ω and 40-Ω RS with calibration
%
(34-Ω and 40-Ω setting)
Internal series termination
with calibration
(48-Ω, 60-Ω, and 80-Ω
setting)
48-Ω, 60-Ω, and
80-Ω RS
V
CCIO = 1.2
15
15
15
%
%
%
Internal parallel
termination with calibration
(50-Ω setting)
V
CCIO = 2.5, 1.8,
1.5, 1.2
50-Ω RT
-10 to +40
-10 to +40
-10 to +40
-10 to +40
-10 to +40
-10 to +40
Internal parallel
20-Ω, 30-Ω,
40-Ω, 60-Ω, and
120-Ω RT
termination with calibration
(20-Ω, 30-Ω, 40-Ω,
60-Ω, and 120-Ω setting)
V
CCIO = 1.5, 1.35,
1.25
Internal parallel
60-Ω and 120-Ω RT termination with calibration
V
CCIO = 1.2
-10 to +40
15
-10 to +40
15
-10 to +40
15
%
%
(60-Ω and 120-Ω setting)
Internal left shift series
termination with calibration
(25-Ω RS_left_shift setting)
V
CCIO = 3.0, 2.5,
1.8, 1.5, 1.2
25-Ω RS_left_shift
1
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and
on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration,
the tolerance may change.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 9
Table 9 lists the Cyclone V OCT without calibration resistance tolerance to PVT
changes.
Table 9. OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices
Resistance Tolerance
Symbol
Description
Conditions (V)
CCIO = 3.0 and 2.5
CCIO = 1.8 and 1.5
Unit
%
–C6
–C7, –I7
–C8, –A7
Internal series termination
without calibration
(25-Ω setting)
25-Ω RS
V
V
30
40
40
40
50
40
40
50
40
Internal series termination
without calibration
(25-Ω setting)
25-Ω RS
25-Ω RS
50-Ω RS
50-Ω RS
50-Ω RS
100-Ω RD
30
35
30
30
35
25
40
50
40
40
50
40
%
Internal series termination
without calibration
(25-Ω setting)
VCCIO = 1.2
%
Internal series termination
without calibration (50-Ω
setting)
V
CCIO = 3.0 and 2.5
CCIO = 1.8 and 1.5
%
Internal series termination
without calibration
(50-Ω setting)
V
%
Internal series termination
without calibration
(50-Ω setting)
V
CCIO = 1.2
CCIO = 2.5
%
Internal differential
termination (100-Ω
setting)
V
%
Use Table 10 to determine the OCT variation after power-up calibration and
Equation 1 to determine the OCT variation without recalibration.
(2), (3), (4), (5), (6)
Equation 1. OCT Variation Without Recalibration (1),
dR
dT
dR
dV
⎛
⎞
⎠
ROCT = RSCAL 1 + 〈------ × ΔT〉 〈------- × ΔV〉
⎝
Notes to Equation 1:
(1) The ROCT value calculated from Equation 1 shows the range of OCT resistance with the variation of temperature and
VCCIO
.
(2) RSCAL is the OCT resistance value at power-up.
(3) ΔT is the variation of temperature with respect to the temperature at power up.
(4) ΔV is the variation of voltage with respect to VCCIO at power up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 10
Electrical Characteristics
Table 10 lists the OCT variation with temperature and voltage after the power-up
calibration. The OCT variation is valid for a VCCIO range of 5% and a temperature
range of 0° to 85°C.
Table 10. OCT Variation after Power-Up Calibration for Cyclone V Devices
Symbol
Description
VCCIO (V)
3.0
Typical
0.100
0.100
0.100
0.100
0.150
0.150
0.150
0.189
0.208
0.266
0.273
0.200
0.200
0.317
Unit
2.5
1.8
OCT variation with voltage without
recalibration
dR/dV
1.5
%/mV
1.35
1.25
1.2
3.0
2.5
1.8
OCT variation with temperature
without recalibration
dR/dT
1.5
%/°C
1.35
1.25
1.2
Pin Capacitance
Table 11 lists the Cyclone V device family pin capacitance.
Table 11. Pin Capacitance for Cyclone V Devices
Symbol
CIOTB
Description
Value
Unit
pF
Input capacitance on top and bottom I/O pins
Input capacitance on left and right I/O pins
6
6
6
CIOLR
pF
COUTFB
Input capacitance on dual-purpose clock output and feedback pins
pF
Hot Socketing
Table 12 lists the hot socketing specifications for Cyclone V devices.
Table 12. Hot Socketing Specifications for Cyclone V Devices
Symbol
IIOPIN (DC)
Description
DC current per I/O pin
Maximum
300 μA
(1)
IIOPIN (AC)
AC current per I/O pin
8 mA
IXCVR-TX (DC)
IXCVR-RX (DC)
Note to Table 12:
DC current per transceiver transmitter (TX) pin
DC current per transceiver receiver (RX) pin
100 mA
50 mA
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 11
Internal Weak Pull-Up Resistor
Table 13 lists the weak pull-up resistor values for Cyclone V devices.
All I/O pins have an option to enable weak pull-up except the configuration, test, and
JTAG pins. For more information about the pins that support internal weak pull-up
and internal weak pull-down features, refer to the Cyclone V Device Family Pin
Connection Guidelines.
Table 13. Internal Weak Pull-Up Resistor Values for Cyclone V Devices
Symbol
Description
Conditions (V) (1)
CCIO = 3.3 5%
Typ (2)
25
Unit
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
V
VCCIO = 3.0 5%
VCCIO = 2.5 5%
VCCIO = 1.8 5%
VCCIO = 1.5 5%
VCCIO = 1.35 5%
VCCIO = 1.25 5%
VCCIO = 1.2 5%
25
25
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
25
RPU
25
25
25
25
Notes to Table 13:
(1) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(2) These specifications are valid with 10% tolerances to cover changes over PVT.
I/O Standard Specifications
Table 14 through Table 19 list the input voltage (VIH and VIL), output voltage (VOH and
VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by Cyclone V devices.
For an explanation of terms used in Table 14 through Table 19, refer to “Glossary” on
page 1–58.
Table 14. Single-Ended I/O Standards for Cyclone V Devices (Part 1 of 2)
VCCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
Max
VOH (V)
Min
(1)
(1)
I/O
Standard
IOL
IOH
(mA) (mA)
Min Typ Max Min
Min
Max
3.3-V
LVTTL
3.135 3.3 3.465 –0.3
3.135 3.3 3.465 –0.3
0.8
0.8
0.8
1.7
3.6
0.45
0.2
0.4
0.2
2.4
CCIO – 0.2
2.4
4
2
2
–4
–2
–2
3.3-V
LVCMOS
1.7
1.7
3.6
3.6
3.6
V
V
3.0-V
LVTTL
2.85
3
3
3.15 –0.3
3.15 –0.3
3.0-V
LVCMOS
2.85
2.85
0.8
1.7
CCIO – 0.2 0.1 –0.1
3.0-V PCI
3
3
3.15
3.15
—
—
0.3 x VCCIO
0.5 x VCCIO
VCCIO + 0.3 0.1 x VCCIO 0.9 x VCCIO
VCCIO + 0.3 0.1 x VCCIO 0.9 x VCCIO
1.5 –0.5
1.5 –0.5
3.0-V PCI-X 2.85
0.35 x VCCIO 0.5 x VCCIO
0.7 1.7
1.71 1.8 1.89 –0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3
2.5 V
1.8 V
1.5 V
2.375 2.5 2.625 –0.3
3.6
0.4
2
1
2
2
–1
–2
–2
0.45
VCCIO – 0.45
1.425 1.5 1.575 –0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 12
Electrical Characteristics
Table 14. Single-Ended I/O Standards for Cyclone V Devices (Part 2 of 2)
VCCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
Max
VOH (V)
(1)
(1)
I/O
Standard
IOL
IOH
(mA) (mA)
Min Typ Max Min
Min
Max
Min
1.2 V
1.14 1.2 1.26 –0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO
2
–2
Note to Table 14:
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification
(4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the
handbook.
Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Cyclone V Devices
VCCIO(V)
Typ
VREF(V)
Typ
VTT(V)
Typ
I/O
Standard
Min
Max
Min
Max
Min
Max
SSTL-2
Class I, II
2.375
2.5
1.8
1.5
2.625 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO
1.89 0.833 0.9 0.969
1.575 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO
VREF – 0.04
VREF
VREF
VREF + 0.04
SSTL-18
Class I, II
1.71
V
REF – 0.04
VREF + 0.04
SSTL-15
Class I, II
1.425
0.5 x VCCIO 0.51 x VCCIO
0.5 x VCCIO 0.51 x VCCIO
0.5 x VCCIO 0.51 x VCCIO
SSTL-135
Class I, II
1.283 1.35 1.418 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO
SSTL-125
Class I, II
1.19
1.71
1.25
1.8
1.26 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO
HSTL-18
Class I, II
1.89
0.85
0.68
0.9
0.95
0.9
—
—
V
V
CCIO/2
CCIO/2
—
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.75
HSTL-12
Class I, II
1.14
1.14
1.2
1.2
1.26 0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO
1.3 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO
—
—
VCCIO/2
—
—
—
HSUL-12
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices (Part 1 of 2)
VIL(DC) (V)
Max
VIH(DC) (V)
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
(1)
(1)
I/O
Iol
Ioh
Standard
(mA)
(mA)
–8.1
–16.2
–6.7
–13.4
–8
Min
Min
Max
SSTL-2
Class I
–0.3
V
V
REF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.608 VTT + 0.608
8.1
SSTL-2
Class II
–0.3
–0.3
–0.3
—
REF – 0.15 VREF + 0.15 VCCIO + 0.3 VREF – 0.31 VREF + 0.31 VTT – 0.81
VTT + 0.81
16.2
6.7
SSTL-18
Class I
VREF
–
V
REF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25 VTT – 0.603 VTT + 0.603
0.125
SSTL-18
Class II
VREF –
0.125
V
REF + 0.125 VCCIO + 0.3 VREF – 0.25 VREF + 0.25
0.28
VCCIO – 0.28 13.4
SSTL-15
Class I
VREF
–
V
REF – 0.1
VREF + 0.1
VREF + 0.1
—
—
V
REF + 0.175 0.2 x VCCIO 0.8 x VCCIO
REF + 0.175 0.2 x VCCIO 0.8 x VCCIO
8
0.175
SSTL-15
Class II
VREF
–
—
VREF – 0.1
V
16
–16
0.175
Cyclone V Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 13
Table 16. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Cyclone V Devices (Part 2 of 2)
VIL(DC) (V)
Max
VIH(DC) (V)
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
(1)
(1)
I/O
Iol
Ioh
Standard
(mA)
(mA)
Min
—
Min
Max
—
SSTL-135
SSTL-125
VREF – 0.09 VREF + 0.09
VREF – 0.85 VREF + 0.85
VREF – 0.16 VREF + 0.16 0.2 x VCCIO 0.8 x VCCIO
VREF – 0.15 VREF + 0.15 0.2 x VCCIO 0.8 x VCCIO
—
—
—
—
—
—
HSTL-18
Class I
—
—
—
—
V
V
V
V
REF – 0.1
REF – 0.1
REF – 0.1
REF – 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
—
—
—
—
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF – 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
0.4
0.4
0.4
0.4
VCCIO – 0.4
VCCIO – 0.4
VCCIO – 0.4
VCCIO – 0.4
8
16
8
–8
–16
–8
HSTL-18
Class II
HSTL-15
Class I
HSTL-15
Class II
16
8
–16
–8
HSTL-12
Class I
–0.1
5
VREF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO
HSTL-12
Class II
–0.1
5
V
V
REF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO
16
—
–16
—
HSUL-12
—
REF – 0.13 VREF + 0.13
—
VREF – 0.22 VREF + 0.22 0.1 x VCCIO 0.9 x VCCIO
Note to Table 16:
(1) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you
should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook.
Table 17. Differential SSTL I/O Standards for Cyclone V Devices
VCCIO (V)
Typ
VSWING(DC) (V)
VX(AC) (V)
Typ
VSWING(AC) (V)
Min Max
I/O Standard
Min
Max
Min
Max
Min
Max
VCCIO
0.6
+
VCCIO/2–
0.2
V
V
V
V
V
CCIO/2+
0.2
SSTL-2 Class I, II
2.375
2.5
1.8
1.5
2.625
0.3
—
—
—
0.62
0.5
V
V
CCIO + 0.6
CCIO + 0.6
VCCIO
0.6
+
VCCIO/2–
0.175
CCIO/2+
0.175
SSTL-18 Class I, II 1.71
SSTL-15 Class I, II 1.425
1.89
1.575
1.45
0.25
0.2
VCCIO/2–
0.15
CCIO/2+ 2(VIH(AC)
0.15 VREF
–
–
–
2(VIL(AC)
VREF
–
–
–
(1)
(1)
(1)
)
)
VCCIO/2–
0.15
CCIO/2+ 2(VIH(AC)
0.15 VREF
2(VIL(AC)
VREF
SSTL-135
1.283 1.35
0.18
0.18
V
CCIO/2
CCIO/2
)
)
VCCIO/2–
0.15
CCIO/2+ 2(VIH(AC)
0.15 VREF
2(VIL(AC)
VREF
SSTL-125
1.19
1.25
1.31
V
)
)
Note to Table 17:
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits
(VIH(DC) and VIL(DC)).
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 14
Electrical Characteristics
Table 18. Differential HSTL and HSUL I/O Standards for Cyclone V Devices
VCCIO (V)
Typ
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
I/O
Standard
Min
Max Min Max
Min
Max
Min
Max
Min Max
HSTL-18
Class I, II
1.71
1.8
1.89 0.2
—
—
0.78
—
—
1.12
0.78
—
—
1.12
0.4
0.4
0.3
—
—
HSTL-15
Class I, II
1.425 1.5 1.575 0.2
0.68
—
0.9
—
0.68
0.9
HSTL-12
Class I, II
VCCIO
+ 0.3
0.5 x
VCCIO
0.4 x V 0.5 x
CCIO
0.6 x
VCCIO
VCCIO
+ 0.48
1.14
1.14
1.2
1.2
1.26 0.16
VCCIO
0.5 x
VCCIO
+0.12
0.5 x VCCIO 0.5 x
– 0.12 VCCIO
0.4 x V 0.5 x
CCIO
0.6 x
VCCIO
HSUL-12
1.3 0.26 0.26
0.44 0.44
VCCIO
Table 19. Differential I/O Standard Specifications for Cyclone V Devices (Part 1 of 2)
(2)
(2), (9)
VCCIO (V)
VID (mV) (1)
VICM(DC) (V)
VOD (V)
VOCM (V)
I/O Standard
Min Typ Max Min Condition Max Min
Condition Max Min Typ Max Min Typ Max
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For
PCML
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 20.
DMAX
≤700 Mbps
0.05
1.80
VCM
1.25 V
=
2.5 V LVDS (3) 2.375 2.5 2.625 100
—
0.247
—
—
—
0.6 1.125 1.25 1.375
DMAX
>700 Mbps
1.05
—
1.55
—
BLVDS (4), (5)
2.375 2.5 2.625 100
—
—
—
—
—
—
—
—
VCM
1.25 V
=
RSDS (HIO) (6) 2.375 2.5 2.625 100
0.25
—
1.45
0.1 0.2 0.6
0.5
1.2
1.4
Mini-LVDS
2.375 2.5 2.625 200
(HIO) (7)
—
600 0.300
—
1.425 0.25
—
—
0.6
—
1
1.2
—
1.4
—
DMAX
≤700 Mbps
0.60
—
1.80
—
1.60
LVPECL (8)
2.375 2.5 2.625 300
—
—
DMAX
>700 Mbps
1.00
VCM
1.25 V
=
SLVS
2.375 2.5 2.625 100
2.375 2.5 2.625 100
—
—
0.05
0.05
—
—
1.8
1.8
—
—
—
—
—
—
—
—
—
—
—
—
VCM
1.25 V
=
Sub-LVDS
Cyclone V Device Datasheet
December 2013 Altera Corporation
Electrical Characteristics
Page 15
Table 19. Differential I/O Standard Specifications for Cyclone V Devices (Part 2 of 2)
(2)
(2), (9)
VCCIO (V)
Min Typ Max Min Condition Max Min
VCM
VID (mV) (1)
VICM(DC) (V)
VOD (V)
VOCM (V)
I/O Standard
Condition Max Min Typ Max Min Typ Max
1.8
=
HiSpi
2.375 2.5 2.625 100
—
0.05
—
—
—
—
—
—
—
1.25 V
Notes to Table 19:
(1) The minimum VID value is applicable over the entire common mode range, VCM
.
(2) RL range: 90 ≤ RL ≤ 110 Ω
(3) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rate above 700 Mbps and 0.00 V to 1.85 V
for data rate below 700 Mbps.
(4) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.
(5) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interface in Supported Altera Device Families.
(6) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.
(7) For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.
(8) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to
1.95 V for data rate below 700 Mbps.
(9) This applies to default pre-emphasis setting only.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 16
Switching Characteristics
Switching Characteristics
This section provides performance characteristics of Cyclone V core and periphery
blocks for commercial grade devices.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 20 lists the Cyclone V GX, GT, SX, and ST transceiver specifications.
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices (Part 1 of 4)
Transceiver
Transceiver
Transceiver
Speed Grade 5 (1)
Speed Grade 6
Speed Grade 7
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2), HCSL, and LVDS
Input frequency from
—
27
—
—
—
550
400
27
—
—
—
550
400
27
—
—
—
550
400
MHz
ps
REFCLK input pins (3)
20% to 80% of
rising clock edge
Rise time
80% to 20% of
falling clock
edge
Fall time
—
—
400
—
—
400
—
—
400
ps
Duty cycle
—
45
—
—
55
45
—
—
55
45
—
—
55
%
Peak-to-peak
differential input voltage
—
200
2000
200
2000
200
2000
mV
Spread-spectrum
modulating clock
frequency
PCIe
PCIe
30
—
33
30
—
33
30
—
33
kHz
—
0 to
0 to
0 to
Spread-spectrum
downspread
—
—
—
—
—
—
—
—
—
—
—
—
–0.5%
–0.5%
–0.5%
On-chip termination
resistors
—
—
100
100
100
Ω
V
ICM (AC coupled)
VCCE_GXBL supply (5), (6)
VCCE_GXBL supply
VCCE_GXBL supply
V
HCSL I/O
standard for the
PCIe reference
clock
VICM (DC coupled)
250
—
550
250
—
550
250
—
550
mV
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
dBc/Hz
dBc/Hz
–110
–120
–120
–130
–110
–120
–120
–130
–110 dBc/Hz
–120 dBc/Hz
–120 dBc/Hz
–130 dBc/Hz
Transmitter REFCLK
Phase Noise (4)
10 KHz
100 KHz
≥1 MHz
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 17
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices (Part 2 of 4)
Transceiver
Transceiver
Transceiver
Speed Grade 7
Speed Grade 5 (1)
Speed Grade 6
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
2000
1%
2000
1%
2000
1%
RREF
—
—
—
—
—
—
—
—
—
—
Ω
Transceiver Clocks
fixedclk clock
frequency
PCIe
Receiver Detect
—
75
125
—
—
75
125
—
—
75
125
—
MHz
MHz
Transceiver
Reconfiguration
Controller IP
100/
100/
100/
—
125 (7)
125 (7)
125 (7)
(mgmt_clk_clk) clock
frequency
Receiver
Supported I/O
Standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
5000/
Data rate (16)
—
—
—
614
—
—
—
—
614
—
—
—
—
3125
1.2
614
—
—
—
—
2500
1.2
Mbps
6144 (6)
Absolute VMAX for a
receiver pin (8)
1.2
V
V
Absolute VMIN for a
receiver pin
–0.4
—
–0.4
—
–0.4
—
Maximum peak-to-peak
differentialinputvoltage
—
—
—
—
—
85
—
—
—
1.6
—
—
85
—
—
—
1.6
2.2
—
—
—
85
—
—
—
1.6
2.2
—
V
V
VID (diff p-p) before
device configuration
Maximum peak-to-peak
differentialinputvoltage
2.2
—
VID (diff p-p) after
device configuration
Minimum differential
eye opening at the
receiver serial input
mV
(9)
pins
85−Ω setting
100−Ω setting
120−Ω setting
150-Ω setting
—
—
—
—
85
—
—
—
—
—
—
—
—
85
—
—
—
—
—
—
—
—
85
—
—
—
—
Ω
Ω
Ω
Ω
100
120
150
100
120
150
100
120
150
Differential on-chip
termination resistors
2.5 V PCML,
LVPECL, and
LVDS
V
CCE_GXBL supply (5), (6)
VCCE_GXBL supply
0.65 (15)/0.8
VCCE_GXBL supply
V
VICM (AC coupled)
1.5 V PCML
V
(10)
tLTR
—
—
—
—
—
—
—
—
—
10
4
—
—
—
—
10
—
—
—
—
10
µs
µs
µs
(11)
tLTD
—
—
4
4
—
—
4
4
(12)
tLTD_manual
4
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 18
Switching Characteristics
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices (Part 3 of 4)
Transceiver
Transceiver
Transceiver
Speed Grade 5 (1)
Speed Grade 6
Speed Grade 7
Symbol/
Conditions
Unit
Description
Min
Typ
Max
Min
15
Typ
Max
Min
Typ
Max
(13)
tLTR_LTD_manual
—
—
—
15
—
—
—
—
15
—
—
µs
ppm
UI
Programmable PPM
detector (14)
62.5, 100, 125, 200, 250, 300, 500, and 1000
Run Length
—
—
200
—
—
200
—
—
200
AC gain setting =
0 to 3 (17)
Programmable
equalization (AC)
and DC gain
Refer to Figure 1 and Figure 2
dB
DC gain setting =
0 to 1
Transmitter
Supported I/O
Standards
1.5 V PCML
5000/
Data rate
—
614
—
614
—
3125
614
—
2500 Mbps
6144 (6)
V
OCM (AC coupled)
—
—
—
—
—
—
650
85
—
—
—
—
—
—
—
—
—
—
650
85
—
—
—
—
—
—
—
—
—
—
650
85
—
—
—
—
—
mV
Ω
85−Ω setting
100−Ω setting
120−Ω setting
150-Ω setting
100
120
150
100
120
150
100
120
150
Ω
Differential on-chip
termination resistors
Ω
Ω
TX VCM = 0.65 V
and slew rate of
15 ps
Intra-differential pair
skew
—
—
—
—
—
—
15
—
—
—
—
—
—
15
—
—
—
—
—
—
15
ps
ps
ps
Intra-transceiver block
transmitter channel-to-
channel skew
x6 PMA bonded
mode
180
500
180
500
180
500
Inter-transceiver block
transmitter channel-to-
channel skew
xN PMA bonded
mode
CMU PLL
5000/
Supported data range
—
—
614
614
—
—
614
614
—
—
3125
3125
614
614
—
—
2500
2500
Mbps
Mbps
6144 (6)
fPLL supported data
range
3125
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 19
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices (Part 4 of 4)
Transceiver
Transceiver
Transceiver
Speed Grade 7
Speed Grade 5 (1)
Speed Grade 6
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Transceiver-FPGA Fabric Interface
Interface speed
—
25
25
—
—
187.5
25
25
—
—
187.5
25
25
—
—
163.84 MHz
156.25 MHz
(single-width mode)
Interface speed
—
163.84
163.84
(double-width mode)
Notes to Table 20:
(1) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about
CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(4) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12
.
(5) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full compliance
to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices
under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(6) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at
4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT devices only). For more information about the maximum full duplex channels
recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(7) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
(8) The device cannot tolerate prolonged operation at this absolute maximum.
(9) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(10) tLTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset.
(11) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(12) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(13) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR
is functioning in the manual mode.
(14) The rate matcher supports only up to 300 parts per million (ppm).
(15) The AC coupled VICM is 650 mV for PCIe mode only.
(16) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
(17) The Quartus II software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 20
Switching Characteristics
Figure 1 shows the continuous time-linear equalizer (CTLE) response at data rates
> 3.25 Gbps across supported AC gain and DC gain settings for Cyclone V GX, GT,
SX, and ST devices.
Figure 1. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and
ST Devices
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 21
Figure 2 shows the CTLE response at data rates ≤ 3.25 Gbps across supported AC gain
and DC gain settings for Cyclone V GX, GT, SX, and ST devices.
Figure 2. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and
ST Devices
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 22
Switching Characteristics
Table 21 lists the TX VOD settings for Cyclone V transceiver channels.
Table 21. Typical TX VOD Setting for Cyclone V Transceiver Channels = 100 Ω
Symbol
VOD Setting (1) VOD Value (mV) VOD Setting (1) VOD Value (mV)
6 (2)
7 (2)
8 (2)
9
120
140
160
180
200
220
240
260
280
300
320
340
360
380
400
420
440
460
480
500
520
540
560
580
600
620
640
660
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
680
700
720
740
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
760
780
800
820
840
860
880
900
920
940
VOD differential peak to peak
typical
960
980
1000
1020
1040
1060
1080
1100
1120
1140
1160
1180
1200
Notes to Table 21:
(1) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA
analog controls.
(2) Only valid for data rates ≤ 5 Gbps.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 23
Table 22 lists the simulation data on the transmitter pre-emphasis levels in dB for the
first post tap under the following conditions:
■
Low-frequency data pattern—five 1s and five 0s
Data rate—2.5 Gbps
■
The levels listed are a representation of possible pre-emphasis levels under the
specified conditions only and the pre-emphasis levels may change with data pattern
and data rate.
Cyclone V devices only support 1st post tap pre-emphasis with the following
conditions:
■
The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where
|B| = VOD setting with termination value, RTERM = 100 Ω and |C| = 1st post tap
pre-emphasis setting
■
■
|B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates
> 5 Gbps.
(VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|.
Exception for PCIe Gen2 design:
■
VOD setting = 50 and pre-emphasis setting = 22 are allowed for PCIe Gen2 design
with transmit de-emphasis –6dB setting (pipe_txdeemp = 1’b0) using Altera PCIe
Hard IP and PIPE megafunctions.
■
VOD setting = 50 and pre-emphasis setting = 12 are allowed for PCIe Gen2 design
with transmit de-emphasis –3.5dB setting (pipe_txdeemp = 1’b1) using Altera PCIe
Hard IP and PIPE megafunctions.
For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The
following conditions show that the 1st post tap pre-emphasis setting = 2 is valid:
■
■
■
|B| + |C| ≤ 60 → 40 + 2 = 42
|B| – |C| > 5 → 40 – 2 = 38
(VMAX/VMIN – 1)% < 600% → (42/38 – 1)% = 10.52%
1
To predict the pre-emphasis level for your specific data rate and pattern, run
simulations using the Cyclone V HSSI HSPICE models.
Table 22. Transmitter Pre-Emphasis Levels for Cyclone V Devices (Part 1 of 2)
Quartus II VOD Setting
Quartus II 1st Post Tap
Unit
10
20
30
35
40
45
50
Pre-Emphasis Setting
(200 mV) (400 mV) (600 mV) (700 mV) (800 mV) (900 mV) (1000 mV)
0
1
2
3
4
5
0
0
0
0
0
0
0
dB
dB
dB
dB
dB
dB
1.97
3.58
5.35
7.27
—
0.88
1.67
2.48
3.31
4.19
0.43
0.95
1.49
2
0.32
0.76
1.2
0.24
0.61
1
0.19
0.5
0.13
0.41
0.69
0.96
1.26
0.83
1.14
1.49
1.63
2.1
1.36
1.76
2.55
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 24
Switching Characteristics
Table 22. Transmitter Pre-Emphasis Levels for Cyclone V Devices (Part 2 of 2)
Quartus II VOD Setting
Quartus II 1st Post Tap
Unit
50
10
20
30
35
40
45
Pre-Emphasis Setting
(200 mV) (400 mV) (600 mV) (700 mV) (800 mV) (900 mV) (1000 mV)
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.08
5.99
6.92
7.92
9.04
10.2
11.56
12.9
14.44
—
3.11
3.71
4.22
4.86
5.46
6.09
6.74
7.44
8.12
8.87
9.56
10.43
11.23
12.18
13.17
14.2
15.38
—
2.56
3.06
3.47
4
2.17
2.58
2.93
3.38
3.79
4.23
4.68
5.12
5.57
6.06
6.49
7.02
7.52
8.02
8.59
—
1.83
2.18
2.48
2.87
3.23
3.61
3.97
4.36
4.76
5.14
—
1.56
1.87
2.11
2.46
2.77
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
4.51
5.01
5.51
6.1
—
—
6.64
7.21
7.73
8.39
9.03
9.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10.34
11.1
11.87
12.67
13.48
14.37
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 25
Table 23 lists the physical medium attachment (PMA) specification compliance of all
supported protocol for Cyclone V GX, GT, SX, and ST devices. For more information
about the protocol parameter details and compliance specifications, contact your
Altera Sales Representative.
Table 23. Transceiver Compliance Specification for All Supported Protocol for Cyclone V
Devices (Part 1 of 2)
Protocol
Sub-protocol
Data Rate (Mbps)
2,500
PCIe Gen1
(1)
PCIe
XAUI
PCIe Gen2
5,000
PCIe Cable
XAUI 2135
2,500
3,125
SRIO 1250 SR
SRIO 1250 LR
SRIO 2500 SR
SRIO 2500 LR
SRIO 3125 SR
SRIO 3125 LR
SRIO 5000 SR
SRIO 5000 MR
SRIO 5000 LR
CPRI E6LV
1,250
1,250
2,500
2,500
Serial RapidIO® (SRIO)
3,125
3,125
5,000
5,000
5,000
614.4
CPRI E6HV
614.4
CPRI E6LVII
CPRI E12LV
CPRI E12HV
CPRI E12LVII
CPRI E24LV
CPRI E24LVII
CPRI E30LV
CPRI E30LVII
614.4
1,228.8
1,228.8
1,228.8
2,457.6
2,457.6
3,072
Common Public Radio Interface
(CPRI)
3,072
(2)
CPRI E48LVII
CPRI E60LVII
GbE 1250
4,915.2
6,144
(2)
Gbps Ethernet (GbE)
OBSAI
1,250
OBSAI 768
OBSAI 1536
OBSAI 3072
SDI 270 SD
768
1,536
3,072
270
Serial digital interface (SDI)
VbyOne
SDI 1485 HD
SDI 2970 3G
VbyOne 3750
1,485
2,970
3,750
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 26
Switching Characteristics
Table 23. Transceiver Compliance Specification for All Supported Protocol for Cyclone V
Devices (Part 2 of 2)
Protocol
Sub-protocol
Data Rate (Mbps)
HiGig+
HIGIG 3750
3,750
Notes to Table 23:
(1) For PCIe Gen2 sub-protocol, Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V
to 1.2 V for Cyclone V GT FPGA systems which ensure full compliance to the PCIe Gen2 transmit jitter
specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and
ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(2) For CPRI E48LVII and E60LVII, Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V
to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and
6.144 Gbps (Cyclone V GT devices only). For more information about the maximum full duplex channels
recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in
Cyclone V Devices chapter.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 27
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), and memory block specifications.
Clock Tree Specifications
Table 24 lists the clock tree specifications for Cyclone V devices.
Table 24. Clock Tree Performance for Cyclone V Devices
Performance
Parameter
–C6
Unit
–C7, –I7
550
–C8, –A7
460
Global clock and Regional clock
Peripheral clock
550
155
MHz
MHz
155
155
PLL Specifications
Table 25 lists the Cyclone V PLL block specifications. Cyclone V PLL block does not
include HPS PLL.
Table 25. PLL Specifications for Cyclone V Devices (Part 1 of 3)
Symbol Parameter
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
Max
670 (1)
622 (1)
500 (1)
325
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
–C6 speed grade
fIN
Input clock frequency
–C7, –I7 speed grades
–C8, –A7 speed grades
5
5
fINPFD
Integer input clock frequency to the PFD
Fractional input clock frequency to the PFD
5
fFINPFD
50
600
600
600
40
—
—
—
—
—
—
45
—
—
160
–C6 speed grade
1600
1400
1300
60
550 (3)
550 (3)
460 (3)
667 (3)
667 (3)
533 (3)
55
(2)
fVCO
PLL VCO operating range
–C7, –I7 speed grades
–C8, –A7 speed grades
tEINDUTY
Input clock or external feedback clock input duty cycle
–C6 speed grade
MHz
MHz
MHz
MHz
MHz
MHz
%
Output frequency for internal global
or regional clock
fOUT
–C7, –I7 speed grades
–C8, –A7 speed grades
–C6 speed grade
Output frequency for external clock
output
fOUT_EXT
–C7, –I7 speed grades
–C8, –A7 speed grades
tOUTDUTY
tFCOMP
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
10
ns
tDYCONFIGCLK
Dynamic configuration clock for mgmt_clk and scanclk
100
MHz
Time required to lock from end-of-device configuration or
deassertion of areset
tLOCK
—
—
—
—
1
1
ms
ms
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
tDLOCK
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 28
Switching Characteristics
Table 25. PLL Specifications for Cyclone V Devices (Part 2 of 3)
Symbol
Parameter
PLL closed-loop low bandwidth
Min
—
—
—
—
10
—
—
Typ
0.3
1.5
4
Max
—
Unit
MHz
MHz
fCLBW
PLL closed-loop medium bandwidth
—
(8)
PLL closed-loop high bandwidth
—
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
50
ps
Minimum pulse width on the areset signal
Input clock cycle-to-cycle jitter (FREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (FREF < 100 MHz)
—
ns
0.15
750
UI (p-p)
ps (p-p)
(4), (5)
tINCCJ
Period jitter for dedicated clock output in integer PLL
(FOUT ≥ 100 MHz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
ps (p-p)
mUI (p-p)
ps (p-p)
(6)
tOUTPJ_DC
Period jitter for dedicated clock output in integer PLL
(FOUT < 100 MHz)
30
Period jitter for dedicated clock output in fractional PLL
(FOUT ≥ 100 MHz)
425 (10)
,
300 (11)
(6)
tFOUTPJ_DC
tOUTCCJ_DC
tFOUTCCJ_DC
Period jitter for dedicated clock output in fractional PLL
(FOUT < 100 MHz)
42.5 (10)
,
mUI (p-p)
ps (p-p)
30 (11)
Cycle-to-cycle jitter for dedicated clock output in integer PLL
(FOUT ≥ 100 MHz)
300
30
(6)
Cycle-to-cycle jitter for dedicated clock output in integer PLL
(FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT ≥ 100 MHz)
425 (10)
300 (11)
,
(6)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT < 100 MHz)
42.5 (10)
,
mUI (p-p)
ps (p-p)
30 (11)
Period jitter for clock output on a regular I/O in integer PLL
(FOUT ≥ 100 MHz)
650
65
(6), (9)
(6), (9),
tOUTPJ_IO
Period jitter for clock output on a regular I/O in integer PLL
(FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Period jitter for clock output on a regular I/O in fractional PLL
(FOUT ≥ 100 MHz)
650
65
tFOUTPJ_IO
(10)
Period jitter for clock output on a regular I/O in fractional PLL
(FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output on regular I/O in integer
PLL (FOUT ≥ 100 MHz)
650
65
(6), (9)
tOUTCCJ_IO
Cycle-to-cycle jitter for clock output on regular I/O in integer
PLL (FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output on regular I/O in
fractional PLL (FOUT ≥ 100 MHz)
650
65
(6),
tFOUTCCJ_IO
(9), (10)
Cycle-to-cycle jitter for clock output on regular I/O in
fractional PLL (FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Period jitter for dedicated clock output in cascaded PLLs (FOUT
≥ 100 MHz)
300
30
tCASC_OUTPJ_DC
(6), (7)
Period jitter for dedicated clock output in cascaded PLLs (FOUT
< 100 MHz)
mUI (p-p)
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 29
Table 25. PLL Specifications for Cyclone V Devices (Part 3 of 3)
Symbol
tDRIFT
Parameter
Min
Typ
—
Max
10
Unit
Frequency drift after PFDENA is disabled for a duration of
—
%
100 µs
dKBIT
Bit number of Delta Sigma Modulator (DSM)
Numerator of fraction
8
24
32
Bits
—
kVALUE
128
8388608 2147483648
5.96 0.023
fRES
Resolution of VCO frequency (fINPFD =100 MHz)
390625
Hz
Notes to Table 25:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) The VCO frequency reported by the Quartus II software takes into consideration the VCO post-scale counter
value of 2, the frequency reported can be lower than the fVCO specification.
K value. Therefore, if the counter K has a
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(5) FREF is fIN/N, specification applies when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Table 31 on page 1–33.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 31 on page 1–33.
(10) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
DSP Block Specifications
Table 26 lists the Cyclone V DSP block performance specifications.
Table 26. DSP Block Performance Specifications for Cyclone V Devices
Performance
Mode
Unit
–C6
–C7, –I7
–C8, –A7
Modes using One DSP Block
Independent 9 x 9 Multiplication
Independent 18 x 19 Multiplication
Independent 18 x 18 Multiplication
Independent 27 x 27 Multiplication
Independent 18 x 25 Multiplication
Independent 20 x 24 Multiplication
Two 18 x 19 Multiplier Adder Mode
18 x 18 Multiplier Added Summed with 36-bit Input
Modes using Two DSP Blocks
340
287
287
250
310
310
310
310
300
250
250
200
250
250
250
250
260
200
200
160
200
200
200
200
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Complex 18 x 19 multiplication
310
250
200
MHz
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 30
Switching Characteristics
Memory Block Specifications
Table 27 lists the Cyclone V memory block specifications.
To achieve the maximum memory block performance, use a memory block clock that
comes through global clock routing from an on-chip PLL and set to 50% output duty
cycle. Use the Quartus II software to report timing for the memory block clocking
schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no
degradation in fMAX
.
Table 27. Memory Block Performance Specifications for Cyclone V Devices
Resources Used
Performance
Memory
Mode
Unit
ALUTs
Memory
–C6
–C7, –I7
–C8, –A7
Single port, all supported widths
0
1
420
350
300
MHz
MHz
Simple dual-port, all supported
widths
0
0
1
1
420
340
350
290
300
240
MLAB
Simple dual-port with read and
write at the same address
MHz
ROM, all supported width
0
0
1
1
420
315
350
275
300
240
MHz
MHz
Single-port, all supported widths
Simple dual-port, all supported
widths
0
1
315
275
240
MHz
Simple dual-port with the
read-during-write option set to
Old Data, all supported widths
M10K
Block
0
1
275
240
180
MHz
True dual port, all supported
widths
0
0
1
1
315
315
275
275
240
240
MHz
MHz
ROM, all supported widths
Periphery Performance
This section describes periphery performance and the high-speed I/O and external
memory interface.
1
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 31
High-Speed I/O Specifications
Table 28 lists high-speed I/O timing for Cyclone V devices.
Table 28. High-Speed I/O Specifications for Cyclone V Devices (1), (2), (3) (Part 1 of 2)
–C6
Min Typ
–C7, –I7
Max Min Typ
–C8, –A7
Min Typ
Symbol
Conditions
Unit
Max
Max
f
HSCLK_in (input
clock frequency)
True Differential I/O
Standards
Clock boost factor W = 1
5
—
437.5
5
—
420
5
—
320
MHz
(4)
to 40
fHSCLK_in (input
clock frequency)
Single Ended I/O
Standards
Clock boost factor W = 1
5
5
—
—
320
420
5
5
—
—
320
370
5
5
—
—
275
320
MHz
MHz
(4)
to 40
fHSCLK_OUT (output
clock frequency)
—
Transmitter
SERDES factor
J = 4 to 10 (5)
(6)
(6)
(6)
(6)
(6)
(6)
—
—
840
—
—
740
—
—
640 Mbps
True Differential I/O
Standards - fHSDR
(data rate)
SERDES factor J = 1 to 2,
Uses DDR Registers
(8)
(8)
(8)
Mbps
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - fHSDR
(6)
(6)
(6)
SERDES factor J = 4 to 10
SERDES factor J = 4 to 10
—
—
640
170
—
—
640
170
—
—
550 Mbps
(7)
(data rate)
Emulated
Differential I/O
Standards with One
External Output
(6)
(6)
(6)
170 Mbps
Resistor Network -
(7)
fHSDR (data rate)
Total Jitter for Data Rate,
600 Mbps - 840 Mbps
—
—
—
—
350
—
—
—
—
380
—
—
—
—
500
ps
UI
tx Jitter - True
Differential I/O
Standards
Total Jitter for Data Rate,
< 600 Mbps
0.21
0.23
0.30
tx Jitter - Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks
Total Jitter for Data Rate
< 640 Mbps
—
—
—
—
500
—
—
—
—
500
—
—
—
—
500
ps
UI
tx Jitter - Emulated
Differential I/O
Standards with One
External Output
Resistor Network
Total Jitter for Data Rate
< 640 Mbps
0.15
0.15
0.15
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 32
Switching Characteristics
Table 28. High-Speed I/O Specifications for Cyclone V Devices (1), (2), (3) (Part 2 of 2)
–C6
Min Typ
–C7, –I7
Max Min Typ
–C8, –A7
Unit
Symbol
Conditions
Max
Min Typ
Max
TX output clock duty
cycle for both True and
Emulated Differential I/O
Standards
tDUTY
45
—
—
50
—
—
55
45
—
—
50
—
—
55
45
—
—
50
—
—
55
%
ps
ps
True Differential I/O
Standards
200
250
200
250
200
300
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
tRISE & tFALL
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
—
—
—
—
300
200
300
—
—
—
—
—
—
300
250
300
—
—
—
—
—
—
300
250
300
ps
ps
ps
True Differential I/O
Standards
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
TCCS
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
300
—
—
300
—
—
300
ps
Receiver
SERDES factor
J = 4 to 10 (5)
(6)
(6)
(6)
—
875 (7)
(8)
—
840 (7)
(8)
—
640 (7) Mbps
f
HSDR (data rate)
SERDES factor J = 1 to 2,
Uses DDR Registers
(6)
(6)
(6)
(8)
—
—
—
—
—
—
Mbps
Sampling Window
—
—
350
—
350
—
350
ps
Notes to Table 28:
(1) When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.
(2) For LVDS applications, you must use the PLLs in integer PLL mode.
(3) This is achieved by using the LVDS clock network.
(4) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
(5) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
(6) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
(8) The maximum ideal data rate is the SERDES factor (J) x PLL max output frequency (fout), provided you can close the design timing and the signal
integrity simulation is clean.You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 33
DLL Range, DQS Logic Block and Memory Output Clock Jitter Specifications
Table 29 lists the DLL operating frequency range specifications for Cyclone V devices.
Table 29. DLL Operating Frequency Range Specifications for Cyclone V Devices
Unit
Parameter
–C6
–C7, –I7
–C8
DLL operating frequency range
167 – 400
167 – 400
167 – 333
MHz
Table 30 lists the DQS phase shift error for Cyclone V devices. This error specification
is the absolute maximum and minimum error.
Table 30. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V
Devices
Number of DQS Delay Buffer
–C6
–C7, –I7
–C8
Unit
2
40
80
80
ps
Table 31 lists the memory output clock jitter specifications for Cyclone V devices.
The memory output clock jitter measurements are for 200 consecutive clock cycles, as
specified in the JEDEC DDR2/DDR3 SDRAM standard.
The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is
applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK
connections for better jitter performance.
Table 31. Memory Output Clock Jitter Specification for Cyclone V Devices
–C6
–C7, –I7
–C8
Clock
Parameter
Symbol
Unit
Network
PHYCLK
PHYCLK
Min
Max
Min
Max
Min
Max
Clock period jitter
tJIT(per)
tJIT(cc)
–60
60
–70
—
70
–70
70
ps
ps
Cycle-to-cycle period
jitter
—
90
100
—
100
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 34
Switching Characteristics
OCT Calibration Block Specifications
Table 32 lists the OCT calibration block specifications for Cyclone V devices.
Table 32. OCT Calibration Block Specifications for Cyclone V Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTCAL
—
—
1000
32
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
TOCTSHIFT
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
TRS_RT
—
2.5
—
ns
Figure 3 shows the timing diagram for the oe and dyn_term_ctrl signals.
Figure 3. Timing Diagram for the oe and dyn_term_ctrl Signals
Tristate
TX
Tristate
RX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Duty Cycle Distortion (DCD) Specifications
Table 33 lists the worst-case DCD for Cyclone V devices. The output DCD cycle only
applies to the I/O buffer. It does not cover the system DCD.
Table 33. Worst-Case DCD on I/O Pins for Cyclone V Devices
–C6
–C7, –I7
–C8, –A7
Symbol
Unit
Min
Max
Min
45
Max
Min
45
Max
Output Duty Cycle
45
55
55
55
%
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 35
HPS Specifications
This section provides HPS specifications and timing for Cyclone V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset
signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.
HPS Clock Performance
Table 34 lists the HPS clock performance for Cyclone V devices.
Table 34. HPS Clock Performance for Cyclone V Devices
Symbol/Description
mpu_base_clk (microprocessor unit clock)
main_base_clk (L3/L4 interconnect clock)
h2f_user0_clk
–C6
925
462
100
100
100
–C7, –I7
800
–A7
700
350
100
100
160
–C8
600
300
100
100
160
Unit
MHz
MHz
MHz
MHz
MHz
400
100
h2f_user1_clk
100
h2f_user2_clk
100
HPS PLL Specifications
HPS PLL VCO Frequency Range
Table 35 lists the HPS PLL VCO frequency range for Cyclone V devices. This
specification applies to all speed grade.
Table 35. HPS PLL VCO Frequency Range for Cyclone V Devices
Description
Minimum
Maximum
Unit
VCO range
320
1,600
MHz
HPS PLL Input Clock Range
The HPS PLL input clock range is 10 – 50 MHz.
For more information about the clock range for different values of clock select (CSEL),
refer to the Booting and Configuration chapter.
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the
HPS PLLs can tolerate.
Maximum input jitter = Input clock period x Divide value (NR) x 0.02
Table 36 shows the examples of the maximum input jitter calculated with the
equation.
Table 36. Examples of Maximum Input Jitter
Input Reference Clock Period
Divide Value (NR)
Maximum Jitter
Unit
ns
40 ns
40 ns
40 ns
1
2
4
0.8
1.6
3.2
ns
ns
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 36
Switching Characteristics
QSPI Timing Characteristics
Table 37 lists the queued serial peripheral interface (QSPI) timing characteristics for
Cyclone V devices.
Table 37. QSPI Timing Requirements for Cyclone V Devices
Symbol Description
Fclk CLK clock frequency
Tdutycycle
Tdssfrst
Min
—
Typ
—
Max
108
55
Unit
MHz
%
QSPI_CLK duty cycle
45
—
1/2 cycle of
QSPI_CLK
Output delay QSPI_SS valid before first clock edge
—
—
ns
Tdsslst
Tdio
Output delay QSPI_SS valid after last clock edge
IO Data output delay
–1
–1
—
—
1
1
ns
ns
Maximum data input delay from falling edge of
QSPI_CLK to data arrival at SoC. The delay field of
the qspiregs.rddatacap register can be
programmed to adjust the capture logic of the
incoming data.
Tdinmax
—
—
—
—
Figure 4 shows the timing diagram for QSPI timing characteristics. This timing
diagram illustrates clock polarity mode 0 and clock phase mode 0.
Figure 4. QSPI Timing Diagram
Tdsslst
QSPI_SS
Tdssfrst
QSPI_CLK
QSPI_DATA
Tdio
Tdinmax
Data Out
Data In
SPI Timing Characteristics
Table 38 lists the serial peripheral interface (SPI) master timing characteristics for
Cyclone V devices. The setup and hold times can be used for Texas Instruments SSP
mode and National Semiconductor Microwire mode.
Table 38. SPI Master Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
45
8
Max
16.67
55
Unit
ns
Tclk
CLK clock period
Tdutycycle
Tdssfrst
Tdsslst
Tdio
SPI_CLK duty cycle
%
Output delay SPI_SS valid before first clock edge
Output delay SPI_SS valid after last clock edge
Master-out slave-in (MOSI) output delay
—
ns
8
—
ns
–1
1
ns
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 37
Table 38. SPI Master Timing Requirements for Cyclone V Devices
Symbol
Description
Min
—
Max
500
Unit
Maximum data input delay from falling edge of SPI_CLK to
data arrival at SoC. The RX sample delay register can be
programmed to control the capture of input data.
Tdinmax
ns
ns
—
Slave select pulse width (Texas Instruments SSP mode)
—
16.67
Figure 5 shows the timing diagram for SPI master timing characteristics.
Figure 5. SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdinmax
Tdio
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdinmax
Table 39 lists the SPI slave timing characteristics for Cyclone V devices. The setup and
hold times can be used for Texas Instruments SSP mode and National Semiconductor
Microwire mode.
Table 39. SPI Slave Timing Requirements for Cyclone V Devices
Symbol Description
Min
20
5
Max
—
—
—
—
—
6
Unit
ns
ns
ns
ns
ns
ns
ns
Tclk
Ts
CLK clock period
MOSI Setup time
MOSI Hold time
Th
5
Tsuss
Thss
Td
Setup time SPI_SS valid before first clock edge
Hold time SPI_SS valid after last clock edge
Master-in slave-out (MISO) output delay
8
8
—
20
—
Slave select pulse width (Texas Instruments SSP mode)
—
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 38
Switching Characteristics
Figure 6 shows the timing diagram for SPI slave timing characteristics.
Figure 6. SPI Slave Timing Diagram
Thss
SPI_SS
Tsuss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO (scph = 1)
SPI_MOSI (scph = 1)
Td
Ts
Th
Td
SPI_MISO (scph = 0)
SPI_MOSI (scph = 0)
Ts
Th
SD/MMC Timing Characteristics
Table 40 lists the secure digital (SD)/MultiMediaCard (MMC) timing characteristics
for Cyclone V devices.
Table 40. SD/MMC Timing Requirements for Cyclone V Devices
Symbol
Description
Min
20
Max
—
—
55
6
Unit
ns
SDMMC_CLK_OUT clock period (High speed mode)
SDMMC_CLK_OUT clock period (Default speed mode)
SDMMC_CLK_OUT duty cycle
Tclk
40
ns
Tdutycycle
Td
45
%
SDMMC_CMD/SDMMC_D output delay
—
ns
Maximum input delay from rising edge of SDMMC_CLK to
data arrival at SoC
Tdinmax
—
25
ns
Figure 7 shows the timing diagram for SD/MMC timing characteristics.
Figure 7. SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD & SDMMC_D (Out)
SDMMC_CMD & SDMMC_D (In)
Command/Data Out
Tdinmax
Command/Data In
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 39
USB Timing Characteristics
Table 41 lists the USB timing characteristics for Cyclone V devices.
Table 41. USB Timing Requirements for Cyclone V Devices
Symbol Description
USB CLK clock period
Min
—
Typ
16.67
—
Max
—
Unit
Tclk
Td
ns
ns
ns
ns
CLK to USB_STP/USB_DATA[7:0] output delay
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]
7.5
2
11
Tsu
Th
—
—
2.5
—
—
Figure 8 shows the timing diagram for USB timing characteristics.
Figure 8. USB Timing Diagram
USB_CLK
USB_STP
Td
USB_DATA[7:0]
To PHY
From PHY
Tsu Th
USB_DIR & USB_NXT
Ethernet Media Access Controller (EMAC) Timing Characteristics
Table 42 lists the reduced gigabit media independent interface (RGMII) TX timing
characteristics for Cyclone V devices.
Table 42. RGMII TX Timing Requirements for Cyclone V Devices
Symbol Description
clk (1000Base-T) TX_CLK clock period
Tclk (100Base-T) TX_CLK clock period
Min
—
Typ
8
Max
—
Unit
ns
T
—
40
400
—
—
—
ns
Tclk (10Base-T)
Tdutycycle
Td
TX_CLK clock period
—
—
ns
TX_CLK duty cycle
45
55
%
TX_CLK to TXD/TX_CTL output data delay
–0.85
0.15
ns
Figure 9 shows the timing diagram for RGMII TX timing characteristics.
Figure 9. RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
Td
TX_CTL
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 40
Switching Characteristics
Table 43 lists the RGMII RX timing characteristics for Cyclone V devices.
Table 43. RGMII RX Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
—
—
1
Typ
Unit
ns
T
clk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tsu
RX_CLK clock period
RX_CLK clock period
RX_CLK clock period
8
40
ns
400
—
ns
RX_D/RX_CTL setup time
ns
Figure 10 shows the timing diagram for RGMII RX timing characteristics.
Figure 10. RGMII RX Timing Diagram
RX_CLK
Tsu
RX_D[3:0]
RX_CTL
Table 44 lists the management data input/output (MDIO) timing characteristics for
Cyclone V devices.
Table 44. MDIO Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
10
10
0
Typ
400
—
Unit
ns
Tclk
Td
Ts
MDC clock period
MDC to MDIO output data delay
Setup time for MDIO data
Hold time for MDIO data
ns
—
ns
Th
—
ns
Figure 11 shows the timing diagram for MDIO timing characteristics.
Figure 11. MDIO Timing Diagram
MDC
Td
MDIO_OUT
MDIO_IN
Th
Tsu
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 41
I2C Timing Characteristics
Table 45 lists the I2C timing characteristics for Cyclone V devices.
Table 45. I2C Timing Requirements for Cyclone V Devices
Standard Mode
Fast Mode
Symbol
Description
Unit
Min
—
4.7
4
Max
10
Min
Max
2.5
—
Tclk
Tclkhigh
Tclklow
Serial clock (SCL) clock period
SCL high time
—
0.6
1.3
µs
µs
µs
—
SCL low time
—
—
Setup time for serial data line (SDA) data to
SCL
Ts
0.25
—
0.1
—
µs
Th
Hold time for SCL to SDA data
0
—
4.7
4
3.45
0.2
—
0
0.9
0.2
—
—
—
µs
µs
µs
µs
µs
Td
SCL to SDA output data delay
—
Tsu_start
Thd_start
Tsu_stop
Setup time for a repeated start condition
Hold time for a repeated start condition
Setup time for a stop condition
0.6
0.6
0.6
—
4
—
Figure 12 shows the timing diagram for I2C timing characteristics.
Figure 12. I2C Timing Diagram
I2C_SCL
Td
Ts
Tsu_stop
Tsu_start Thd_start
Th
Data In
Data Out
I2C_SDA
NAND Timing Characteristics
Table 46 lists the NAND timing characteristics for Cyclone V devices.
The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5
timing as well as legacy NAND devices. The following table lists the requirements for
ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by
programming the C4 output of the main HPS PLL and timing registers provided in the
NAND controller.
Table 46. NAND ONFI 1.0 Timing Requirements for Cyclone V Devices (Part 1 of 2)
Symbol
(1)
Description
Write enable pulse width
Min
10
7
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
Twp
Twh
(1)
Write enable hold time
(1)
Trp
Read Enable pulse width
10
7
(1)
(1)
Treh
Read enable hold time
Tclesu
Command latch enable to write enable setup time
Command latch enable to write enable hold time
Chip enable to write enable setup time
10
5
(1)
Tcleh
Tcesu
(1)
15
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 42
Switching Characteristics
Table 46. NAND ONFI 1.0 Timing Requirements for Cyclone V Devices (Part 2 of 2)
Symbol
(1)
Description
Chip enable to write enable hold time
Address latch enable to write enable setup time
Address latch enable to write enable hold time
Data to write enable setup time
Min
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tceh
—
—
—
—
—
25
16
100
—
(1)
Talesu
10
5
(1)
Taleh
(1)
Tdsu
10
5
(1)
Tdh
Tcea
Trea
Trhz
Trr
Data to write enable hold time
Chip enable to data access time
—
—
—
20
Read enable to data access time
Read enable to data high impedance
Ready to read enable low
Note to Table 46:
(1) Timing of the NAND interface is controlled through the NAND Configuration registers.
Figure 13 shows the timing diagram for NAND command latch timing characteristics.
Figure 13. NAND Command Latch Timing Diagram
NAND_CLE
NAND_CE
Tclesu
Tcesu
Tcleh
Twp
Tceh
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Command
Tdh
NAND_DQ[7:0]
Cyclone V Device Datasheet
December 2013 Altera Corporation
Switching Characteristics
Page 43
Figure 14 shows the timing diagram for NAND address latch timing characteristics.
Figure 14. NAND Address Latch Timing Diagram
NAND_CLE
NAND_CE
Tcesu
Tclesu
Twp
Twh
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Tdh
NAND_DQ[7:0]
Address
Figure 15 shows the timing diagram for NAND data write timing characteristics.
Figure 15. NAND Data Write Timing Diagram
NAND_CLE
NAND_CE
Tcleh
Tceh
Twp
NAND_WE
NAND_ALE
Talesu
Tdsu
Tdh
NAND_DQ[7:0]
Din
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 44
Switching Characteristics
Figure 16 shows the timing diagram for NAND data read timing characteristics.
Figure 16. NAND Data Read Timing Diagram
Tcea
NAND_CE
Trr
Trp
Treh
NAND_RE
Trhz
NAND_RB
Trea
NAND_DQ[7:0]
Dout
ARM Trace Timing Characteristics
Table 47 lists the ARM trace timing characteristics for Cyclone V devices.
Most debugging tools have a mechanism to adjust the capture point of trace data.
Table 47. ARM Trace Timing Requirements for Cyclone V Devices
Description
Min
12.5
45
Max
—
55
1
Unit
ns
CLK clock period
CLK maximum duty cycle
%
CLK to D0 –D7 output data delay
–1
ns
UART Interface
The maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
The minimum detectable general-purpose I/O (GPIO) pulse width is 2 µs. The pulse
width is based on a debounce clock frequency of 1 MHz.
CAN Interface
The maximum controller area network (CAN) data rate is 1 Mbps.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 45
Configuration Specification
This section provides configuration specifications and timing for Cyclone V devices.
POR Specifications
Table 48 lists the specifications for fast and standard POR delay for Cyclone V devices.
Table 48. Fast and Standard POR Delay Specification for Cyclone V Devices (1)
POR Delay
Minimum
Maximum
12
Unit
ms
Fast (2)
4
Standard
100
300
ms
Notes to Table 48:
(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Cyclone V
Devices” table in the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
(2) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize
after the POR trip.
JTAG Configuration Timing
Table 49 lists the JTAG timing parameters and values for Cyclone V devices.
Table 49. JTAG Timing Parameters and Values for Cyclone V Devices
Symbol
Description
Min
30
167 (1)
14
14
1
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCP
tJCH
tJCL
TCK clock period
TCK clock period
TCK clock high time
TCK clock low time
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
3
5
(2)
tJPCO
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
—
—
—
11
14
14
(2)
(2)
tJPZX
tJPXZ
Notes to Table 49:
(1) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile
key programming.
(2) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 46
Configuration Specification
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Cyclone V devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[] ratio when you turn on
encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r
times the DATA[] rate in byte per second (Bps) or word per second (Wps). For
example, in FPP x16 where the r is 2, the DCLK frequency must be 2 times the DATA[]
rate in Wps.
Cyclone V devices use additional clock cycles to decrypt and decompress the
configuration data.
Table 50 lists the DCLK-to-DATA[] ratio for each combination.
Table 50. DCLK-to-DATA[] Ratio for Cyclone V Devices
Configuration Scheme
Encryption
Compression
DCLK-to-DATA[] ratio (r)
Off
On
Off
On
Off
On
Off
On
Off
Off
On
On
Off
Off
On
On
1
1
2
2
1
2
4
4
FPP (8-bit wide)
FPP (16-bit wide)
1
If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only
stop the DCLK DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into
the Cyclone V device.
(
Cyclone V Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 47
FPP Configuration Timing when DCLK to DATA[] = 1
Figure 17 shows the timing waveform for an FPP configuration when using a
MAX® II device as an external host. This waveform shows timing when the
DCLK-to-DATA[] ratio is 1.
1
When you enable decompression or the design security feature, the DCLK-to-DATA[]
ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[] ratio, refer to
Table 50 on page 1–46.
Figure 17. DCLK-to-DATA[] FPP Configuration Timing Waveform for Cyclone V Devices When the Ratio is 1 (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
(6)
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
Word 0 Word 1 Word 2 Word 3
Word n-2 Word n-1
DATA[15..0](5)
User Mode
User Mode
tDSU
High-Z
User I/O
(7)
INIT_DONE
tCD2UM
Notes to Figure 17:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
nCONFIG is pulled low, a reconfiguration cycle begins.
, nSTATUS, and CONF_DONE are at logic-high levels. When
(2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[15..0] are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(6) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high when the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
(7) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 48
Configuration Specification
Table 51 lists the timing parameters for Cyclone V devices for an FPP configuration
when the DCLK-to-DATA[] ratio is 1.
Table 51. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices When the Ratio is 1
Symbol
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
Minimum
Maximum
600
Unit
ns
—
—
600
ns
nCONFIG low pulse width
2
268
—
—
µs
µs
µs
µs
µs
(1)
nSTATUS low pulse width
1506
(2)
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
1506
(3)
1506
2
—
—
tCF2CK
tST2CK
tDSU
(3)
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
DATA[] hold time after rising edge on DCLK
DCLK high time
0
—
—
ns
s
tDH
0.45 x 1/fMAX
tCH
DCLK low time
0.45 x 1/fMAX
—
s
tCL
DCLK period
1/fMAX
—
s
tCLK
fMAX
tCD2UM
tCD2CU
DCLK frequency (FPP x8 and x16)
—
175
125
437
—
MHz
µs
—
(4)
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK period
t
CD2CU + (Tinit x CLKUSR
CONF_DONE high to user mode with CLKUSR
option on
tCD2UMC
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 51:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(3) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 49
FPP Configuration Timing when DCLK to DATA[] > 1
Figure 18 shows the timing waveform for an FPP configuration when using a MAX II
device or microprocessor as an external host. This waveform shows timing when the
DCLK-to-DATA[]ratio is more than 1.
(1)
Figure 18. FPP Configuration Timing Waveform for Cyclone V Devices When the DCLK-to-DATA[] Ratio is > 1
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
CONF_DONE (3)
t
CL
tCF2CD
(7)
tST2CK
t
CH
DCLK (5)
DATA[15..0] (7)
User I/O
(6)
(4)
1
2
1
1
2
r
1
2
r
r
t
CLK
Word 0
Word 1
Word (n-1)
User Mod
User Mod
Word 3
t
t
tDSU
DH
DH
High-Z
(8)
INIT_DONE
tCD2UM
Notes to Figure 18:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power up, the Cyclone V device holds nSTATUS low for the time as specified by the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable
settings, refer to Table 50 on page 1–46.
(6) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[15..0] pins prior to sending
the first DCLK rising edge.
(7) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high after the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(8) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 50
Configuration Specification
Table 52 lists the timing parameters for Cyclone V devices when the
DCLK-to-DATA[]ratio is more than 1.
Table 52. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices when the Ratio is > 1 (1)
Symbol
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
Minimum
Maximum
600
Unit
ns
—
—
600
ns
nCONFIG low pulse width
2
268
—
—
µs
µs
µs
µs
µs
(2)
nSTATUS low pulse width
1506
(3)
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
1506
(4)
1506
2
—
—
tCF2CK
tST2CK
tDSU
(4)
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
(5)
DATA[] hold time after rising edge on DCLK
DCLK high time
N – 1/fDCLK
—
—
s
s
tDH
tCH
tCL
tCLK
fMAX
tR
0.45 x 1/fMAX
DCLK low time
0.45 x 1/fMAX
—
s
DCLK period
1/fMAX
—
s
DCLK frequency (FPP x8 and x16)
Input rise time
—
125
40
MHz
ns
ns
µs
—
—
Input fall time
—
175
40
tF
CONF_DONE high to user mode (6)
CONF_DONE high to CLKUSR enabled
437
—
tCD2UM
tCD2CU
4 × maximum DCLK period
t
CD2CU + (Tinit x CLKUSR
CONF_DONE high to user mode with CLKUSR
option on
tCD2UMC
—
—
—
period)
Number of clock cycles required for device
initialization
Tinit
17,408
Cycles
Notes to Table 52:
(1) Use these timing parameters when you use decompression and the design security features.
(2) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) This value can be obtained if you do not delay configuration by externally holding nSTATUS low.
(4) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
(5) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.
(6) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 51
AS Configuration Timing
Figure 19 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Figure 19. AS Configuration Timing Waveform for Cyclone V Devices
t
CF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
t
CO
t
DH
Read Address
AS_DATA0/ASDO
AS_DATA1 (1)
t
SU
bit (n − 2) bit (n − 1)
bit 1
bit 0
t
(2)
CD2UM
INIT_DONE (3)
User I/O
User Mode
Notes to Figure 19:
(1) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
(2) The initialization clock can be from the internal oscillator or the CLKUSR pin.
(3) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Table 53 lists the timing parameters for AS x1 and AS x4 configurations in Cyclone V
devices.
The minimum and maximum numbers apply to both the internal oscillator and
CLKUSR when either one is used as the clock source for device configuration.
The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the
timing parameters for passive serial (PS) mode listed in Table 55 on page 1–53. You
can obtain the tCF2ST1 value if you do not delay configuration by externally holding
nSTATUS low.
Table 53. AS Timing Parameters for AS x1 and x4 Configurations in Cyclone V Devices
Symbol
tCO
Parameter
Minimum
Maximum
Unit
ns
DCLK falling edge to the AS_DATA0
/ASDO output
—
4
tSU
Data setup time before the falling edge on DCLK
Data hold time after the falling edge on DCLK
CONF_DONE high to user mode
1.5
—
—
437
—
ns
tDH
0
175
ns
tCD2UM
tCD2CU
tCD2UMC
µs
CONF_DONE high to CLKUSR enabled
4 x maximum DCLK period
—
t
CD2CU + (Tinit x CLKUSR
CONF_DONE high to user mode with CLKUSR option on
—
—
—
period)
17,408
Number of clock cycles required for device initialization
Cycles
Tinit
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 52
Configuration Specification
Table 54 lists the internal clock frequency specification for the AS configuration
scheme.
The DCLK frequency specification applies when you use the internal oscillator as the
configuration clock source.
The AS multi-device configuration scheme does not support DCLK frequency of
100 MHz.
Table 54. DCLK Frequency Specification in the AS Configuration Scheme for Cyclone V Devices
Parameter
Minimum
5.3
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLK frequency in AS
configuration scheme
21.3
50.0
42.6
100.0
Remote update only in AS
mode
—
—
12.5
MHz
PS Configuration Timing
Figure 20 shows the timing waveform for a PS configuration when using a MAX II
device or microprocessor as an external host.
Figure 20. PS Configuration Timing Waveform for Cyclone V Devices (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
(5)
t CLK
CONF_DONE (3)
tCH
tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
Bit 2 Bit 3
Bit (n-1)
Bit 0 Bit 1
DATA0
tDSU
High-Z
User I/O
User Mod
INIT_DONE (6)
tCD2UM
Notes to Figure 20:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
nCONFIG is pulled low, a reconfiguration cycle begins.
, nSTATUS, and CONF_DONE are at logic high levels. When
(2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high after the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(6) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 53
Table 55 lists the PS timing parameter for Cyclone V devices.
Table 55. PS Timing Parameters for Cyclone V Devices
Symbol
tCF2CD
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
Minimum
Maximum
600
Unit
ns
—
—
tCF2ST0
600
ns
nCONFIG low pulse width
2
—
µs
µs
tCFG
(1)
nSTATUS low pulse width
268
1506
tSTATUS
tCF2ST1
(2)
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLK high time
—
1506
µs
(3)
1506
—
—
µs
tCF2CK
(3)
2
µs
tST2CK
5.5
—
ns
tDSU
tDH
0
—
ns
0.45 x 1/fMAX
—
s
tCH
DCLK low time
0.45 x 1/fMAX
—
s
tCL
DCLK period
1/fMAX
—
s
tCLK
DCLK frequency
—
175
125
437
—
MHz
µs
fMAX
tCD2UM
tCD2CU
tCD2UMC
Tinit
CONF_DONE high to user mode (4)
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
Number of clock cycles required for device initialization
4 x maximum DCLK period
—
—
Cycles
tCD2CU + (Tinit
x
CLKUSR period)
—
17,408
—
Notes to Table 55:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(3) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 54
Configuration Specification
Initialization
Table 56 lists the initialization clock source option, the applicable configuration
schemes, and the maximum frequency for Cyclone V devices.
Table 56. Initialization Clock Source Option and the Maximum Frequency for Cyclone V Devices
Maximum
Frequency
(MHz)
Minimum Number of
Initialization Clock Source Configuration Schemes
Clock Cycles
Internal Oscillator
AS, PS, and FPP
PS and FPP
AS
12.5
125
100
Tinit
(1)
CLKUSR
Note to Table 56:
(1) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General panel of the Device and Pin Options dialog box.
Configuration Files
Use Table 57 to estimate the file size before design compilation. Different
configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf)
format, have different file sizes.
For the different types of configuration file and file sizes, refer to the Quartus II
software. However, for a specific version of the Quartus II software, any design
targeted for the same device has the same uncompressed configuration file size.
Table 57 lists the uncompressed raw binary file (.rbf) sizes for Cyclone V devices.
Table 57. Uncompressed .rbf Sizes for Cyclone V Devices (Part 1 of 2)
Variant
Member Code
Configuration .rbf Size (bits)
21,061,120
IOCSR .rbf Size (bits)
275,608
275,608
322,072
435,288
400,408
320,280
322,072
322,072
435,288
400,408
322,072
435,288
400,408
322,072
322,072
324,888
324,888
A2
A4
21,061,120
Cyclone V E (1)
A5
33,958,336
A7
56,167,328
A9
102,871,552
14,512,096
C3
C4
33,958,336
Cyclone V GX
C5
33,958,336
C7
56,167,328
C9
102,871,552
33,958,336
D5
D7
D9
A2 (2)
A4 (2)
A5
Cyclone V GT
56,167,328
102,871,552
33,958,336
33,958,336
Cyclone V SE (1)
56,057,408
A6
56,057,408
Cyclone V Device Datasheet
December 2013 Altera Corporation
Configuration Specification
Page 55
Table 57. Uncompressed .rbf Sizes for Cyclone V Devices (Part 2 of 2)
Variant
Member Code
Configuration .rbf Size (bits)
33,958,336
IOCSR .rbf Size (bits)
322,072
C2 (2)
C4 (2)
C5
33,958,336
322,072
Cyclone V SX
56,057,408
324,888
C6
56,057,408
324,888
D5
56,057,408
324,888
Cyclone V ST
D6
56,057,408
324,888
Notes to Table 57:
(1) No PCIe hard IP, configuration via protocol (CvP) is not supported in this family.
(2) This device will be supported in a future release of the Quartus II software.
Table 58 lists the minimum configuration time estimation for Cyclone V devices. The
estimated values are based on the configuration .rbf sizes in Table 57.
Table 58. Minimum Configuration Time Estimation for Cyclone V Devices (Part 1 of 2)
Active Serial (1) Fast Passive Parallel (2)
Minimum
Configuration
Time (ms)
Minimum
Configuration Time
(ms)
Variant
Member Code
DCLK
(MHz)
DCLK
(MHz)
Width
Width
A2
A4
A5
A7
A9
C3
C4
C5
C7
C9
D5
D7
D9
A2
A4
A5
A6
C2
C4
C5
C6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
53
53
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
11
11
17
28
51
7
Cyclone V E
85
140
257
36
85
17
17
28
51
17
28
51
17
17
28
28
17
17
28
28
Cyclone V GX
85
140
257
85
Cyclone V GT
Cyclone V SE
140
257
85
85
140
140
85
85
Cyclone V SX
140
140
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 56
Configuration Specification
Table 58. Minimum Configuration Time Estimation for Cyclone V Devices (Part 2 of 2)
Active Serial (1)
Fast Passive Parallel (2)
Minimum
Configuration
Time (ms)
Minimum
Configuration Time
(ms)
Variant
Member Code
DCLK
(MHz)
DCLK
(MHz)
Width
Width
D5
D6
4
4
100
100
140
140
16
16
125
125
28
28
Cyclone V ST
Notes to Table 57:
(1) DCLK frequency of 100 MHz using external CLKUSR
.
(2) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Remote System Upgrades Circuitry Timing Specification
Table 59 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 59. Remote System Upgrade Circuitry Timing Specification for Cyclone V Devices
Parameter
Minimum
Maximum
Unit
(1)
(3)
—
40
MHz
tMAX_RU_CLK
(2)
tRU_nCONFIG
250
250
—
—
ns
ns
tRU_nRSTIMER
Notes to Table 59:
(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE
megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.
(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “Remote System Upgrade State Machine”
section in the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
(3) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “User Watchdog Timer” section in the
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
User Watchdog Internal Oscillator Frequency Specification
Table 60 lists the frequency specifications for the user watchdog internal oscillator.
Table 60. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices
Parameter
Minimum
Typical
Maximum
Unit
User watchdog internal
oscillator frequency
5.3
7.9
12.5
MHz
Cyclone V Device Datasheet
December 2013 Altera Corporation
I/O Timing
Page 57
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis.
The Quartus II Timing Analyzer provides a more accurate and precise I/O timing
data based on the specifics of the design after you complete place-and-route.
f
You can download the Excel-based I/O Timing spreadsheet from the Cyclone V
Devices Documentation webpage.
Programmable IOE Delay
Table 61 lists the Cyclone V IOE programmable delay settings.
Table 61. IOE Programmable Delay for Cyclone V Devices
Fast Model
Slow Model
Parameter Available Minimum
Unit
(1)
Settings
Offset (2)
Industrial Commercial
–C6
–C7
–C8
–I7
–A7
D1
D3
D4
D5
32
8
0
0
0
0
0.508
1.761
0.510
0.508
0.517
1.793
0.519
0.517
0.971
3.291
1.180
0.970
1.187
4.022
1.187
1.186
1.194
3.961
1.195
1.194
1.179
3.999
1.180
1.179
1.160
3.929
1.160
1.179
ns
ns
ns
ns
32
32
Notes to Table 61:
(1) You can set this value in the Quartus II software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.
(2) Minimum offset does not include the intrinsic delay.
Programmable Output Buffer Delay
Table 62 lists the delay chain settings that control the rising and falling edge delays of
the output buffer. The default delay is 0 ps.
You can set the programmable output buffer delay in the Quartus II software by
setting the Output Buffer Delay Control assignment to either positive, negative, or
both edges, with the specific values stated here (in ps) for the Output Buffer Delay
assignment.
Table 62. Programmable Output Buffer Delay for Cyclone V Devices
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
Rising and/or falling edge
delay
DOUTBUF
100
ps
150
ps
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 58
Glossary
Glossary
Table 63 lists the glossary for this datasheet.
Table 63. Glossary Table (Part 1 of 4)
Letter
Subject
Definitions
A
B
C
—
—
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
Ground
IL
V
CM
Differential Waveform
V
ID
p − n = 0 V
V
ID
Differential I/O
Standards
D
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p − n = 0 V
V
OD
E
F
—
—
fHSCLK
Left/right PLL input clock frequency.
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI).
fHSDR
G
H
I
—
—
Cyclone V Device Datasheet
December 2013 Altera Corporation
Glossary
Page 59
Table 63. Glossary Table (Part 2 of 4)
Letter
Subject
Definitions
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
J
TMS
TDI
tJCP
J
JTAG Timing
Specifications
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
K
L
M
N
O
—
—
(1)
Diagram of PLL Specifications
CLKOUT Pins
fOUT_EXT
Switchover
4
CLK
fIN
fINPFD
N
GCLK
RCLK
Counters
C0..C17
fVCO
VCO
fOUT
PFD
CP
LF
Core Clock
PLL
Specifications
P
Delta Sigma
Modulator
Key
External Feedback
Reconfigurable in User Mode
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Q
R
—
—
RL
Receiver differential input discrete resistor (external to the Cyclone V device).
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 60
Glossary
Table 63. Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Samplingwindow
(SW)
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing.
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
VCCIO
referenced I/O
standard
VOH
VIH
(
)
AC
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
VOL
VSS
tC
High-speed receiver/transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including the tCO
variation and clock skew, across channels driven by the same PLL. The clock is included in
the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
TCCS (channel-
to-channel-skew)
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and the data sampling window.
T
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input
Period jitter on the general purpose I/O driven by a PLL
Period jitter on the dedicated clock output driven by a PLL
Signal low-to-high transition time (20–80%)
—
tINCCJ
tOUTPJ_IO
tOUTPJ_DC
tRISE
U
—
Cyclone V Device Datasheet
December 2013 Altera Corporation
Document Revision History
Page 61
Table 63. Glossary Table (Part 4 of 4)
Letter
Subject
VCM(DC)
Definitions
DC common mode input voltage.
VICM
Input common mode voltage—The common mode of the differential signal at the receiver.
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VDIF(AC)
VDIF(DC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH
VIH(AC)
VIH(DC)
High-level AC input voltage
High-level DC input voltage
V
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL
VIL(AC)
VIL(DC)
Low-level AC input voltage
Low-level DC input voltage
Output common mode voltage—The common mode of the differential signal at the
transmitter.
VOCM
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VOD
VSWING
VX
Differential input voltage
Input differential cross point voltage
Output differential cross point voltage
High-speed I/O block—Clock Boost Factor
VOX
W
W
X
Y
Z
—
—
Document Revision History
Table 64 lists the revision history for this document.
Table 64. Document Revision History (Part 1 of 3)
Date
Version
3.7
Changes
■ Updated Table 1, Table 3, Table 19, Table 20, Table 23, Table 25, Table 27, Table 34,
Table 44, Table 51, Table 52, Table 55, and Table 61.
■ Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7,
Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19,
Table 20, Table 24, Table 25, Table 26, Table 27, Table 28, Table 32, Table 33, Table 49,
Table 50, Table 51, Table 52, Table 53, Table 54, Table 55, Table 57, Table 58, Table 59,
Table 60, and Table 62.
December 2013
November 2013
3.6
Updated Table 23, Table 30, and Table 31.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 62
Document Revision History
Table 64. Document Revision History (Part 2 of 3)
Date
Version
Changes
■ Added “HPS PLL Specifications”.
■ Added Table 23, Table 35, and Table 36.
■ Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25,
Table 28, Table 34, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43,
Table 44, Table 45, Table 46, Table 47, and Table 53.
October 2013
3.5
■ Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16.
■ Removed table: GPIO Pulse Width for Cyclone V Devices.
■ Updated Table 20, Table 27, and Table 34.
■ Updated “UART Interface” and “CAN Interface” sections.
■ Removed the following tables:
June 2013
May 2013
3.4
3.3
■ Table 45. UART Baud Rate for Cyclone V Devices
■ Table 47. CAN Pulse Width for Cyclone V Devices
■ Added Table 33.
■ Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20.
■ Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26,
Table 32, Table 35, Table 36, Table 43, Table 53, Table 54, Table 57, and Table 61.
■ Added HPS reset information in the “HPS Specifications” section.
■ Added Table 57.
March 2013
3.2
3.1
■ Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.
■ Updated Figure 18.
January 2013
Updated Table 4, Table 20, and Table 56.
■ Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19,
Table 20, Table 25, Table 28, Table 52, Table 55, Table 56, and Table 59.
■ Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices.
■ Added HPS information:
■ Added “HPS Specifications” section.
November 2012
3.0
■ Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40,
Table 41, Table 42, Table 43, Table 44, Table 45, and Table 46.
■ Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11,
Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16.
■ Updated Table 3.
Updated for the Quartus II software v12.0 release:
■ Restructured document.
■ Removed “Power Consumption” section.
■ Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30,
Table 31, Table 34, Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and
Table 46.
June 2012
2.0
■ Added Table 22, Table 23, and Table 29.
■ Added Figure 1 and Figure 2.
■ Added “Initialization” and “Configuration Files” sections.
Cyclone V Device Datasheet
December 2013 Altera Corporation
Document Revision History
Page 63
Table 64. Document Revision History (Part 3 of 3)
Date
Version
Changes
■ Added automotive speed grade information.
■ Added Figure 2–1.
■ Updated Table 2–3, Table 2–8, Table 2–9, Table 2–19, Table 2–20, Table 2–21,
February 2012
1.2
Table 2–22, Table 2–23, Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28,
Table 2–30, Table 2–35, and Table 2–43.
■ Minor text edits.
■ Added Table 2–5.
November 2011
October 2011
1.1
1.0
■ Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21.
Initial release.
December 2013 Altera Corporation
Cyclone V Device Datasheet
Page 64
Document Revision History
Cyclone V Device Datasheet
December 2013 Altera Corporation
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