5SGTMC7K3F40I3 [INTEL]
Field Programmable Gate Array, 622000-Cell, CMOS, PBGA1517, FBGA-1517;
| 型号： | 5SGTMC7K3F40I3 |
| 厂家： | 
INTEL |
| 描述： | Field Programmable Gate Array, 622000-Cell, CMOS, PBGA1517, FBGA-1517 栅 |
| 文件： | 总72页 (文件大小：1228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stratix V Device Datasheet
SV53001-3.6
This document covers the electrical and switching characteristics for Stratix® V
devices. Electrical characteristics include operating conditions and power
consumption. Switching characteristics include transceiver specifications, core, and
periphery performance. This document also describes I/O timing, including
programmable I/O element (IOE) delay and programmable output buffer delay.
f
For information regarding the densities and packages of devices in the Stratix V
family, refer to the Stratix V Device Overview.
Electrical Characteristics
The following sections describe the electrical characteristics of Stratix V devices.
Operating Conditions
When you use Stratix V devices, they are rated according to a set of defined
parameters. To maintain the highest possible performance and reliability of Stratix V
devices, you must consider the operating requirements described in this chapter.
Stratix V devices are offered in commercial and industrial temperature grades.
Commercial devices are offered in –1 (fastest), –2, –3, and –4 core speed grades.
Industrial devices are offered in –2, –3, and –4 core speed grades. Stratix V E devices
are offered based on core speed grades while Stratix V GX, GS, and GT devices are
also offered in -1, -2, and -3 transceiver speed grades.
Table 1 lists the industrial and commercial speed grades for the Stratix V GX and
Stratix V GS devices.
(1), (2), (3)
Table 1. Stratix V GX and GS Commercial and Industrial Speed Grade Offering
(Part 1 of 2)
Core Speed Grade
Transceiver Speed
Grade
C1
C2, C2L
C3
C4
I2, I2L
I3, I3L
I3YY
I4
1
Yes
Yes
—
—
Yes
—
—
—
GX channel—14.1 Gbps
2
Yes
Yes
Yes
—
Yes
Yes
—
—
GX channel—12.5 Gbps
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
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respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
ISO
9001:2008
Registered
101 Innovation Drive
San Jose, CA 95134
www.altera.com
December 2015 Altera Corporation
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Page 2
Electrical Characteristics
(1), (2), (3)
Table 1. Stratix V GX and GS Commercial and Industrial Speed Grade Offering
(Part 2 of 2)
Core Speed Grade
Transceiver Speed
Grade
C1
C2, C2L
C3
C4
I2, I2L
I3, I3L
I3YY
I4
3
—
Yes
Yes
Yes
—
Yes
Yes (4)
Yes
GX channel—8.5 Gbps
Notes to Table 1:
(1) C = Commercial temperature grade; I = Industrial temperature grade.
(2) Lower number refers to faster speed grade.
(3) C2L, I2L, and I3L speed grades are for low-power devices.
(4) I3YY speed grades can achieve up to 10.3125 Gbps.
Table 2 lists the industrial and commercial speed grades for the Stratix V GT devices.
(1), (2)
Table 2. Stratix V GT Commercial and Industrial Speed Grade Offering
Core Speed Grade
Transceiver Speed Grade
C1
C2
I2
I3
2
Yes
Yes
—
—
GX channel—12.5 Gbps
GT channel—28.05 Gbps
3
Yes
Yes
Yes
Yes
GX channel—12.5 Gbps
GT channel—25.78 Gbps
Notes to Table 2:
(1) C = Commercial temperature grade; I = Industrial temperature grade.
(2) Lower number refers to faster speed grade.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Stratix V
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
c
Conditions other than those listed in Table 3 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 3. Absolute Maximum Ratings for Stratix V Devices (Part 1 of 2)
Symbol
VCC
Description
Power supply for core voltage and periphery circuitry
Power supply for programmable power technology
Power supply for configuration pins
Minimum
–0.5
Maximum
1.35
1.8
Unit
V
VCCPT
–0.5
V
VCCPGM
VCC_AUX
VCCBAT
VCCPD
VCCIO
–0.5
3.9
V
Auxiliary supply for the programmable power technology
Battery back-up power supply for design security volatile key register
I/O pre-driver power supply
–0.5
3.4
V
–0.5
3.9
V
–0.5
3.9
V
I/O power supply
–0.5
3.9
V
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 3
Table 3. Absolute Maximum Ratings for Stratix V Devices (Part 2 of 2)
Symbol
VCCD_FPLL
VCCA_FPLL
VI
Description
Minimum
–0.5
Maximum
1.8
Unit
PLL digital power supply
PLL analog power supply
DC input voltage
V
V
–0.5
3.4
–0.5
3.8
V
TJ
Operating junction temperature
Storage temperature (No bias)
–55
125
°C
°C
TSTG
–65
150
Table 4 lists the absolute conditions for the transceiver power supply for Stratix V GX,
GS, and GT devices.
Table 4. Transceiver Power Supply Absolute Conditions for Stratix V GX, GS, and GT Devices
Symbol
VCCA_GXBL
VCCA_GXBR
VCCA_GTBR
VCCHIP_L
Description
Devices
GX, GS, GT
GX, GS
Minimum Maximum Unit
Transceiver channel PLL power supply (left side)
Transceiver channel PLL power supply (right side)
Transceiver channel PLL power supply (right side)
Transceiver hard IP power supply (left side)
Transceiver hard IP power supply (right side)
Transceiver PCS power supply (left side)
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
3.75
3.75
3.75
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.35
1.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
GT
VCCHIP_R
VCCHSSI_L
VCCHSSI_R
VCCR_GXBL
VCCR_GXBR
VCCR_GTBR
VCCT_GXBL
VCCT_GXBR
VCCT_GTBR
VCCL_GTBR
VCCH_GXBL
VCCH_GXBR
Transceiver PCS power supply (right side)
Receiver analog power supply (left side)
Receiver analog power supply (right side)
Receiver analog power supply for GT channels (right side)
Transmitter analog power supply (left side)
Transmitter analog power supply (right side)
Transmitter analog power supply for GT channels (right side)
Transmitter clock network power supply (right side)
Transmitter output buffer power supply (left side)
Transmitter output buffer power supply (right side)
GX, GS, GT
GX, GS, GT
GT
GT
GX, GS, GT
GX, GS, GT
1.8
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 5 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 4
Electrical Characteristics
Table 5 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime. The maximum allowed
overshoot duration is specified as a percentage of high time over the lifetime of the
device. A DC signal is equivalent to 100% of the duty cycle. For example, a signal that
overshoots to 3.95 V can be at 3.95 V for only ~21% over the lifetime of the device; for
a device lifetime of 10 years, the overshoot duration amounts to ~2 years.
Table 5. Maximum Allowed Overshoot During Transitions
Overshoot Duration as %
Symbol
Description
Condition (V)
Unit
@ TJ = 100°C
3.8
3.85
3.9
100
64
36
21
12
7
%
%
%
%
%
%
%
%
%
3.95
4
Vi (AC)
AC input voltage
4.05
4.1
4
4.15
4.2
2
1
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 5
Recommended Operating Conditions
This section lists the functional operating limits for the AC and DC parameters for
Stratix V devices. Table 6 lists the steady-state voltage and current values expected
from Stratix V devices. Power supply ramps must all be strictly monotonic, without
plateaus.
Table 6. Recommended Operating Conditions for Stratix V Devices (Part 1 of 2)
Symbol
Description
Condition
Min (4)
Typ
Max (4)
Unit
Core voltage and periphery circuitry power
supply (C1, C2, I2, and I3YY speed grades)
—
0.87
0.9
0.93
V
VCC
Core voltage and periphery circuitry power
supply (C2L, C3, C4, I2L, I3, I3L, and I4
speed grades) (3)
—
0.82
0.85
0.88
V
Power supply for programmable power
technology
VCCPT
—
—
1.45
1.50
2.5
1.55
V
V
Auxiliary supply for the programmable
power technology
VCC_AUX
2.375
2.625
I/O pre-driver (3.0 V) power supply
I/O pre-driver (2.5 V) power supply
I/O buffers (3.0 V) power supply
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.85
2.375
2.85
3.0
2.5
3.0
2.5
1.8
1.5
1.35
1.25
1.2
3.0
2.5
1.8
2.5
1.5
3.15
2.625
3.15
V
V
V
V
V
V
V
V
V
V
V
V
V
V
(1)
VCCPD
I/O buffers (2.5 V) power supply
2.375
1.71
2.625
1.89
I/O buffers (1.8 V) power supply
VCCIO
I/O buffers (1.5 V) power supply
1.425
1.283
1.19
1.575
1.45
I/O buffers (1.35 V) power supply
I/O buffers (1.25 V) power supply
I/O buffers (1.2 V) power supply
1.31
1.14
1.26
Configuration pins (3.0 V) power supply
Configuration pins (2.5 V) power supply
Configuration pins (1.8 V) power supply
PLL analog voltage regulator power supply
PLL digital voltage regulator power supply
2.85
3.15
VCCPGM
2.375
1.71
2.625
1.89
VCCA_FPLL
VCCD_FPLL
2.375
1.45
2.625
1.55
Battery back-up power supply (For design
security volatile key register)
(2)
VCCBAT
—
1.2
—
3.0
V
VI
DC input voltage
Output voltage
—
—
–0.5
0
—
—
—
—
3.6
VCCIO
85
V
V
VO
Commercial
Industrial
0
°C
°C
TJ
Operating junction temperature
–40
100
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 6
Electrical Characteristics
Table 6. Recommended Operating Conditions for Stratix V Devices (Part 2 of 2)
Symbol
tRAMP
Description
Condition
Standard POR
Fast POR
Min (4)
200 µs
200 µs
Typ
—
Max (4)
100 ms
4 ms
Unit
—
Power supply ramp time
—
—
Notes to Table 6:
(1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(2) If you do not use the design security feature in Stratix V devices, connect VCCBAT to a 1.2- to 3.0-V power supply. Stratix V power-on-reset (POR)
circuitry monitors VCCBAT. Stratix V devices will not exit POR if VCCBAT stays at logic low.
(3) C2L and I2L can also be run at 0.90 V for legacy boards that were designed for the C2 and I2 speed grades.
(4) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance
requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
Table 7 lists the transceiver power supply recommended operating conditions for
Stratix V GX, GS, and GT devices.
Table 7. Recommended Transceiver Power Supply Operating Conditions for Stratix V GX, GS, and GT Devices
(Part 1 of 2)
Symbol
Description
Devices
Minimum (4)
2.85
Typical Maximum (4) Unit
3.0
2.5
3.0
2.5
3.15
2.625
3.15
VCCA_GXBL
Transceiver channel PLL power supply (left
side)
GX, GS, GT
V
V
(1), (3)
2.375
2.85
VCCA_GXBR Transceiver channel PLL power supply (right
GX, GS
(1), (3)
side)
2.375
2.625
Transceiver channel PLL power supply (right
VCCA_GTBR
side)
GT
2.85
0.87
3.0
0.9
3.15
0.93
V
V
Transceiver hard IP power supply (left side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
VCCHIP_L
VCCHIP_R
VCCHSSI_L
VCCHSSI_R
Transceiver hard IP power supply (left side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
GX, GS, GT
0.82
0.87
0.82
0.87
0.82
0.87
0.82
0.85
0.9
0.88
0.93
0.88
0.93
0.88
0.93
0.88
V
V
V
V
V
V
V
Transceiver hard IP power supply (right side;
C1, C2, I2, and I3YY speed grades)
Transceiver hard IP power supply (right side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
0.85
0.9
Transceiver PCS power supply (left side;
C1, C2, I2, and I3YY speed grades)
Transceiver PCS power supply (left side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
0.85
0.9
Transceiver PCS power supply (right side;
C1, C2, I2, and I3YY speed grades)
Transceiver PCS power supply (right side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
0.85
0.82
0.87
0.97
1.03
0.85
0.90
1.0
0.88
0.93
1.03
1.07
VCCR_GXBL
Receiver analog power supply (left side)
GX, GS, GT
V
(2)
1.05
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 7
Table 7. Recommended Transceiver Power Supply Operating Conditions for Stratix V GX, GS, and GT Devices
(Part 2 of 2)
Symbol
Description
Devices
Minimum (4)
0.82
Typical Maximum (4) Unit
0.85
0.90
1.0
0.88
0.93
1.03
1.07
0.87
VCCR_GXBR
Receiver analog power supply (right side)
GX, GS, GT
V
V
V
(2)
0.97
1.03
1.05
Receiver analog power supply for GT
channels (right side)
VCCR_GTBR
GT
1.02
1.05
1.08
0.82
0.87
0.97
1.03
0.82
0.87
0.97
1.03
0.85
0.90
1.0
0.88
0.93
1.03
1.07
0.88
0.93
1.03
1.07
VCCT_GXBL
Transmitter analog power supply (left side)
GX, GS, GT
(2)
1.05
0.85
0.90
1.0
VCCT_GXBR
Transmitter analog power supply (right side) GX, GS, GT
V
(2)
1.05
Transmitter analog power supply for GT
channels (right side)
VCCT_GTBR
VCCL_GTBR
VCCH_GXBL
GT
1.02
1.02
1.05
1.05
1.5
1.08
1.08
V
V
V
Transmitter clock network power supply
GT
Transmitter output buffer power supply (left
side)
GX, GS, GT
1.425
1.575
Transmitter output buffer power supply
(right side)
VCCH_GXBR
GX, GS, GT
1.425
1.5
1.575
V
Notes to Table 7:
(1) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps,
you can connect this supply to either 3.0 V or 2.5 V.
(2) Refer to Table 8 to select the correct power supply level for your design.
(3) When using ATX PLLs, the supply must be 3.0 V.
(4) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to
the PDN tool for the additional budget for the dynamic tolerance requirements.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 8
Electrical Characteristics
Table 8 shows the transceiver power supply voltage requirements for various
conditions.
Table 8. Transceiver Power Supply Voltage Requirements
VCCR_GXB &
Conditions
Core Speed Grade
VCCA_GXB VCCH_GXB Unit
(2)
VCCT_GXB
If BOTH of the following
conditions are true:
All
1.05
■ Data rate > 10.3 Gbps.
■ DFE is used.
If ANY of the following
(1)
conditions are true
:
3.0
■ ATX PLL is used.
All
1.0
■ Data rate > 6.5Gbps.
1.5
V
■ DFE (data rate
10.3 Gbps), AEQ, or
EyeQ feature is used.
If ALL of the following
conditions are true:
C1, C2, I2, and I3YY
0.90
0.85
2.5
2.5
■ ATX PLL is not used.
■ Data rate 6.5Gbps.
C2L, C3, C4, I2L, I3, I3L, and I4
■ DFE, AEQ, and EyeQ are
not used.
Notes to Table 8:
(1) Choose this power supply voltage requirement option if you plan to upgrade your design later with any of the listed conditions.
(2) If the VCCR_GXB and VCCT_GXB supplies are set to 1.0 V or 1.05 V, they cannot be shared with the VCC core supply. If the VCCR_GXB and
VCCT_GXB are set to either 0.90 V or 0.85 V, they can be shared with the VCC core supply.
DC Characteristics
This section lists the supply current, I/O pin leakage current, input pin capacitance,
on-chip termination tolerance, and hot socketing specifications.
Supply Current
Supply current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 9
I/O Pin Leakage Current
Table 9 lists the Stratix V I/O pin leakage current specifications.
Table 9. I/O Pin Leakage Current for Stratix V Devices (1)
Symbol
II
IOZ
Description
Input pin
Tri-stated I/O pin
Conditions
VI = 0 V to VCCIOMAX
VO = 0 V to VCCIOMAX
Min
–30
–30
Typ
—
Max
30
Unit
µA
—
30
µA
Note to Table 9:
(1) If VO = VCCIO to VCCIOMax, 100 µA of leakage current per I/O is expected.
Bus Hold Specifications
Table 10 lists the Stratix V device family bus hold specifications.
Table 10. Bus Hold Parameters for Stratix V Devices
VCCIO
Parameter Symbol Conditions
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
Min Max
Unit
Min Max Min
Max Min Max Min Max
Low
sustaining
current
VIN > VIL
ISUSL
ISUSH
IODL
22.5
–22.5
—
—
—
25.0
–25.0
—
—
—
30.0
–30.0
—
—
—
50.0
–50.0
—
—
—
70.0
–70.0
—
—
—
µA
µA
(maximum)
High
sustaining
current
VIN < VIH
(minimum)
Low
overdrive
current
0V < VIN
VCCIO
<
120
–120
160
–160
200
–200
300
–300
500 µA
–500 µA
High
overdrive
current
0V < VIN
VCCIO
<
IODH
—
—
—
—
—
Bus-hold
trip point
VTRIP
—
0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70
0.80
2.00
V
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block. Table 11 lists the Stratix V OCT termination
calibration accuracy specifications.
Table 11. OCT Calibration Accuracy Specifications for Stratix V Devices (1) (Part 1 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
C3,I3,
C1
C2,I2
I3YY
C4,I4
Internal series termination
with calibration (25-
setting)
V
CCIO = 3.0, 2.5,
25- RS
15
15
15
15
%
1.8, 1.5, 1.2 V
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 10
Electrical Characteristics
Table 11. OCT Calibration Accuracy Specifications for Stratix V Devices (1) (Part 2 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
C3,I3,
C1
C2,I2
I3YY
C4,I4
Internal series termination
with calibration (50-
setting)
V
CCIO = 3.0, 2.5,
50- RS
15
15
15
15
15
15
15
%
%
1.8, 1.5, 1.2 V
Internal series termination
with calibration (34- and
40- setting)
34- and
40- RS
VCCIO = 1.5, 1.35,
1.25, 1.2 V
15
15
Internal series termination
with calibration (48-
60-80-and -
setting)
48--
80-and
240-RS
VCCIO = 1.2 V
15
15
15
%
%
Internal parallel
termination with
calibration (50- setting)
VCCIO = 2.5, 1.8,
1.5, 1.2 V
50- RT
–10 to +40 –10 to +40 –10 to +40 –10 to +40
–10 to +40 –10 to +40 –10 to +40 –10 to +40
Internal parallel
20-, 30-,
40-,60-
and
termination with
calibration (20-, 30-
40-60-and 120-
setting)
VCCIO = 1.5, 1.35,
1.25 V
%
120- RT
Internal parallel
60- and
120-RT
termination with
calibration (60- and
120- setting)
VCCIO = 1.2
–10 to +40 –10 to +40 –10 to +40 –10 to +40
%
%
Internal left shift series
termination with
calibration (25-
RS_left_shift setting)
25-
RS_left_shift
V
CCIO = 3.0, 2.5,
1.8, 1.5, 1.2 V
15
15
15
15
Note to Table 11:
(1) OCT calibration accuracy is valid at the time of calibration only.
Table 12 lists the Stratix V OCT without calibration resistance tolerance to PVT
changes.
Table 12. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices (Part 1 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Unit
C3, I3,
I3YY
C1
C2,I2
C4, I4
Internal series termination
25- R, 50- RS without calibration (25-
VCCIO = 3.0 and 2.5 V
VCCIO = 1.8 and 1.5 V
VCCIO = 1.2 V
30
30
40
40
50
40
%
%
%
setting)
Internal series termination
without calibration (25-
setting)
25- RS
25- RS
30
35
30
35
40
50
Internal series termination
without calibration (25-
setting)
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 11
Table 12. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices (Part 2 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Unit
C3, I3,
I3YY
C1
C2,I2
C4, I4
Internal series termination
without calibration (50-
setting)
50- RS
VCCIO = 1.8 and 1.5 V
VCCIO = 1.2 V
30
30
40
40
%
Internal series termination
without calibration (50-
setting)
50- RS
35
25
35
25
50
25
50
25
%
%
Internal differential
termination (100- setting)
100- RD
VCCIO = 2.5 V
Calibration accuracy for the calibrated series and parallel OCTs are applicable at the
moment of calibration. When voltage and temperature conditions change after
calibration, the tolerance may change.
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 13 lists the OCT variation with temperature and voltage after power-up
calibration. Use Table 13 to determine the OCT variation after power-up calibration
and Equation 1 to determine the OCT variation without recalibration.
(4), (5), (6)
Equation 1. OCT Variation Without Recalibration for Stratix V Devices (1), (2), (3),
dR
dT
dR
dV
------
-------
V
ROCT = R
1 +
T
SCAL
Notes to Equation 1:
(1) The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO
(2) RSCAL is the OCT resistance value at power-up.
.
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 13 lists the on-chip termination variation after power-up calibration.
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 1 of 2) (1)
Symbol
Description
VCCIO (V)
3.0
Typical
0.0297
0.0344
0.0499
0.0744
0.1241
Unit
2.5
OCT variation with voltage without
recalibration
dR/dV
1.8
%/mV
1.5
1.2
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 12
Electrical Characteristics
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 2 of 2) (1)
Symbol
Description
VCCIO (V)
3.0
Typical
0.189
0.208
0.266
0.273
0.317
Unit
2.5
OCT variation with temperature
without recalibration
dR/dT
1.8
%/°C
1.5
1.2
Note to Table 13:
(1) Valid for a VCCIO range of 5% and a temperature range of 0° to 85°C.
Pin Capacitance
Table 14 lists the Stratix V device family pin capacitance.
Table 14. Pin Capacitance for Stratix V Devices
Symbol
Description
Value
Unit
pF
CIOTB
Input capacitance on the top and bottom I/O pins
Input capacitance on the left and right I/O pins
6
6
6
CIOLR
COUTFB
pF
Input capacitance on dual-purpose clock output and feedback pins
pF
Hot Socketing
Table 15 lists the hot socketing specifications for Stratix V devices.
Table 15. Hot Socketing Specifications for Stratix V Devices
Symbol
IIOPIN (DC)
Description
DC current per I/O pin
Maximum
300 A
8 mA (1)
100 mA
50 mA
IIOPIN (AC)
AC current per I/O pin
IXCVR-TX (DC)
DC current per transceiver transmitter pin
DC current per transceiver receiver pin
IXCVR-RX (DC)
Note to Table 15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 13
Internal Weak Pull-Up Resistor
Table 16 lists the weak pull-up resistor values for Stratix V devices.
Table 16. Internal Weak Pull-Up Resistor for Stratix V Devices (1), (2)
V
CCIO Conditions
(V) (3)
Symbol
Description
Value (4) Unit
3.0 5%
2.5 5%
1.8 5%
1.5 5%
1.35 5%
1.25 5%
1.2 5%
25
25
25
25
25
25
25
k
k
k
k
k
k
k
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if you enable the programmable
pull-up resistor option.
RPU
Notes to Table 16:
(1) All I/O pins have an option to enable the weak pull-up resistor except the configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCKpin. The typical value for this internal weak
pull-down resistor is approximately 25 k
(3) The pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(4) These specifications are valid with a 10% tolerance to cover changes over PVT.
I/O Standard Specifications
Table 17 through Table 22 list the input voltage (VIH and VIL), output voltage (VOH and
OL), and current drive characteristics (IOH and IOL) for various I/O standards
V
supported by Stratix V devices. These tables also show the Stratix V device family I/O
standard specifications. The VOL and VOH values are valid at the corresponding IOH
and IOL, respectively.
For an explanation of the terms used in Table 17 through Table 22, refer to “Glossary”
on page 65. For tolerance calculations across all SSTL and HSTL I/O standards, refer
to Altera knowledge base solution rd07262012_486.
Table 17. Single-Ended I/O Standards for Stratix V Devices
VCCIO (V)
VIL (V)
Max
VIH (V)
VOL (V)
VOH (V)
I/O
IOL
IOH
Standard
(mA)
(mA)
Min
2.85
2.85
2.375
Typ
3
Max
3.15
Min
–0.3
–0.3
–0.3
Min
1.7
1.7
1.7
Max
3.6
3.6
3.6
Max
0.4
0.2
0.4
Min
2.4
LVTTL
LVCMOS
2.5 V
0.8
0.8
0.7
2
0.1
1
–2
–0.1
–1
3
3.15
V
CCIO – 0.2
2
2.5
2.625
0.35 *
VCCIO
0.65 * VCCIO
VCCIO 0.3
+
+
+
VCCIO
0.45
–
1.8 V
1.5 V
1.2 V
1.71
1.425
1.14
1.8
1.5
1.2
1.89
1.575
1.26
–0.3
–0.3
–0.3
0.45
2
2
2
–2
–2
–2
0.35 *
VCCIO
0.65 * VCCIO
VCCIO 0.3
0.25 *
VCCIO
0.75 *
VCCIO
0.35 *
VCCIO
0.65 * VCCIO
VCCIO 0.3
0.25 *
VCCIO
0.75 *
VCCIO
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 14
Electrical Characteristics
Table 18. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Stratix V Devices
VCCIO (V)
Typ
VREF (V)
Typ
VTT (V)
Typ
I/O Standard
Min
Max
Min
Max
Min
Max
SSTL-2
Class I, II
0.49 *
VCCIO
0.51 *
VCCIO
VREF
0.04
–
VREF
0.04
+
2.375
2.5
1.8
2.625
0.5 * VCCIO
0.9
VREF
VREF
SSTL-18
Class I, II
VREF
0.04
–
VREF
0.04
+
1.71
1.425
1.283
1.19
1.89
1.575
1.418
1.26
1.26
1.89
1.575
1.26
1.3
0.833
0.969
SSTL-15
Class I, II
0.49 *
VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
1.5
0.5 * VCCIO
0.5 * VCCIO
0.5 * VCCIO
0.5 * VCCIO
0.9
SSTL-135
Class I, II
0.49 *
VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
1.35
1.25
1.20
1.8
SSTL-125
Class I, II
0.49 *
VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
SSTL-12
Class I, II
0.49 *
VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
1.14
HSTL-18
Class I, II
1.71
0.85
0.68
0.95
0.9
—
—
—
—
VCCIO/2
—
—
—
—
HSTL-15
Class I, II
1.425
1.14
1.5
0.75
VCCIO/2
HSTL-12
Class I, II
0.47 *
VCCIO
0.53 *
VCCIO
1.2
0.5 * VCCIO
0.5 * VCCIO
VCCIO/2
—
0.49 *
VCCIO
0.51 *
VCCIO
HSUL-12
1.14
1.2
Table 19. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix V Devices (Part 1 of 2)
VIL(DC) (V)
VIH(DC) (V)
Min Max
VREF
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
Ioh
I/O Standard
Iol (mA)
(mA)
Min
Max
VREF
0.15
SSTL-2
Class I
–
+
VCCIO
0.3
+
+
+
+
VREF
–
VTT
–
VTT
+
–0.3
VREF + 0.31
VREF + 0.31
VREF + 0.25
VREF + 0.25
8.1
16.2
6.7
13.4
8
–8.1
–16.2
–6.7
–13.4
–8
0.15
0.31
0.608
0.608
SSTL-2
Class II
VREF
0.15
–
VREF
0.15
+
VCCIO
0.3
VREF
–
VTT
–
VTT
+
–0.3
–0.3
–0.3
—
0.31
0.81
0.81
SSTL-18
Class I
VREF
0.125
–
VREF
0.125
+
VCCIO
0.3
VREF
–
VTT
–
VTT +
0.603
0.25
0.603
SSTL-18
Class II
VREF
0.125
–
VREF
0.125
+
VCCIO
0.3
VREF
–
VCCIO
–
0.28
0.25
0.28
SSTL-15
Class I
VREF
0.1
–
–
–
VREF
0.1
+
+
+
VREF
–
VREF
+
0.2 *
VCCIO
0.8 *
VCCIO
—
—
—
—
—
0.175
0.175
SSTL-15
Class II
VREF
0.1
VREF
0.1
VREF
–
VREF
+
0.2 *
VCCIO
0.8 *
VCCIO
—
16
–16
—
0.175
0.175
SSTL-135
Class I, II
VREF
0.09
VREF
0.09
VREF
–
0.2 *
VCCIO
0.8 *
VCCIO
—
VREF + 0.16
—
0.16
SSTL-125
Class I, II
VREF
0.85
–
VREF
0.85
+
VREF
–
0.2 *
VCCIO
0.8 *
VCCIO
—
VREF + 0.15
VREF + 0.15
—
—
0.15
SSTL-12
Class I, II
VREF
0.1
–
VREF
0.1
+
VREF
–
0.2 *
VCCIO
0.8 *
VCCIO
—
—
—
0.15
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 15
Table 19. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix V Devices (Part 2 of 2)
V
IL(DC) (V)
Max
VIH(DC) (V)
Min Max
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
Ioh
(mA)
I/O Standard
Iol (mA)
Min
HSTL-18
Class I
VREF
0.1
–
–
–
–
–
VREF
0.1
+
+
+
+
+
VCCIO
0.4
–
–
–
–
—
—
—
—
—
—
VREF – 0.2 VREF + 0.2
VREF – 0.2 VREF + 0.2
VREF – 0.2 VREF + 0.2
VREF – 0.2 VREF + 0.2
0.4
0.4
0.4
0.4
8
16
8
–8
–16
–8
HSTL-18
Class II
VREF
0.1
VREF
0.1
VCCIO
0.4
HSTL-15
Class I
VREF
0.1
VREF
0.1
VCCIO
0.4
—
HSTL-15
Class II
VREF
0.1
VREF
0.1
VCCIO
0.4
—
16
8
–16
–8
HSTL-12
Class I
VREF
0.08
VREF
0.08
VCCIO
0.15
+
+
VREF
–
0.25*
VCCIO
0.75*
VCCIO
–0.15
–0.15
—
VREF + 0.15
VREF + 0.15
VREF + 0.22
0.15
HSTL-12
Class II
VREF
0.08
–
VREF
0.08
+
VCCIO
0.15
VREF
–
0.25*
VCCIO
0.75*
VCCIO
16
—
–16
—
0.15
VREF
0.13
–
VREF
0.13
+
VREF
–
0.1*
VCCIO
0.9*
VCCIO
HSUL-12
—
0.22
Table 20. Differential SSTL I/O Standards for Stratix V Devices
VCCIO (V)
Typ
VSWING(DC) (V)
VX(AC) (V)
VSWING(AC) (V)
I/O Standard
Min
Max
Min
Max
Min
Typ
Max
Min
Max
SSTL-2 Class
I, II
VCCIO
0.6
+
VCCIO/2 –
0.2
VCCIO/2 +
0.2
VCCIO
0.6
+
2.375
2.5
1.8
2.625
0.3
0.25
0.2
—
0.62
SSTL-18Class
I, II
VCCIO
0.6
+
VCCIO/2 –
0.175
VCCIO/2 +
0.175
VCCIO
0.6
+
1.71
1.425
1.283
1.19
1.89
1.575
1.45
1.31
1.26
—
0.5
SSTL-15Class
I, II
VCCIO/2 –
0.15
VCCIO/2 +
0.15
(1)
(1)
(1)
1.5
—
0.35
—
SSTL-135
Class I, II
VCCIO/2 –
0.15
V
CCIO/2 + 2(VIH(AC)
0.15 VREF
-
-
2(VIL(AC)
- VREF
1.35
1.25
1.2
0.2
VCCIO/2
VCCIO/2
VCCIO/2
)
)
SSTL-125
Class I, II
VCCIO/2 –
0.15
V
CCIO/2 + 2(VIH(AC)
0.15 VREF
0.18
0.18
—
)
SSTL-12
Class I, II
VREF
–0.15
VREF
+
1.14
—
–0.30
0.30
0.15
Note to Table 20:
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits
(VIH(DC) and VIL(DC)).
Table 21. Differential HSTL and HSUL I/O Standards for Stratix V Devices (Part 1 of 2)
VCCIO (V)
Typ
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
Min Max
I/O
Standard
Min
Max
Min
Max
Min
Max
Min
Max
HSTL-18
Class I, II
1.71
1.8
1.5
1.89
0.2
0.2
—
0.78
—
—
1.12
0.78
—
—
1.12
0.4
0.4
—
—
HSTL-15
Class I, II
1.425
1.575
—
0.68
0.9
0.68
0.9
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 16
Electrical Characteristics
Table 21. Differential HSTL and HSUL I/O Standards for Stratix V Devices (Part 2 of 2)
V
CCIO (V)
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
VDIF(AC) (V)
I/O
Standard
Min
Typ
Max
Min
0.16
Max
Min
Max
Min
Typ
Max
Min
Max
HSTL-12
Class I, II
VCCIO
+ 0.3
0.5*
VCCIO
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
VCCIO
+ 0.48
1.14
1.2
1.2
1.26
—
—
0.3
0.5*VCCIO 0.5* 0.5*VCCIO 0.4*
– 0.12 VCCIO + 0.12 VCCIO
0.5*
VCCIO
0.6*
VCCIO
HSUL-12
1.14
1.3
0.26 0.26
0.44
0.44
Table 22. Differential I/O Standard Specifications for Stratix V Devices (7)
(10)
(6)
(6)
V
CCIO (V)
VID (mV) (8)
VICM(DC) (V)
VOD (V)
VOCM (V)
Typ
I/O
Standard
Min Typ Max Min Condition Max Min Condition Max
Min Typ Max Min
Max
Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 23 on page 18.
PCML
D
MAX
—
0.05
1.8 0.247
1.55 0.247
—
0.6 1.125 1.25 1.375
0.6 1.125 1.25 1.375
700 Mbps
2.5 V
LVDS
VCM
1.25 V
=
2.375 2.5 2.625 100
(1)
DMAX
700 Mbps
>
—
—
—
1.05
—
—
—
BLVDS (5) 2.375 2.5 2.625 100
RSDS
—
—
—
—
—
—
—
—
VCM
1.25 V
=
2.375 2.5 2.625 100
0.3
—
—
1.4
0.1
0.2 0.6
0.5
1.2
1.4
(2)
(HIO)
Mini-
LVDS
(HIO)
2.375 2.5 2.625 200
—
600 0.4
1.325 0.25
—
0.6
1
1.2
1.4
(3)
D
MAX
—
—
—
—
—
—
—
—
—
—
—
—
0.6
1
1.8
1.6
—
—
—
—
—
—
—
—
—
—
—
—
LVPECL (4
700 Mbps
), (9)
DMAX
700 Mbps
>
Notes to Table 22:
(1) For optimized LVDS receiver performance, the receiver voltage input range must be between 1.0 V to 1.6 V for data rates above 700 Mbps, and 0 V to 1.85
V for data rates below 700 Mbps.
(2) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.
(3) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V.
(4) For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V
to 1.95 V for data rate below 700 Mbps.
(5) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.
(6) RL range: 90 RL 110 .
(7) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 18.
(8) The minimum VID value is applicable over the entire common mode range, VCM.
(9) LVPECL is only supported on dedicated clock input pins.
(10) Differential inputs are powered by VCCPD which requires 2.5 V.
Power Consumption
Altera offers two ways to estimate power consumption for a design—the Excel-based
Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature.
Stratix V Device Datasheet
December 2015 Altera Corporation
Electrical Characteristics
Page 17
1
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 18
Switching Characteristics
Switching Characteristics
This section provides performance characteristics of the Stratix V core and periphery
blocks.
These characteristics can be designated as Preliminary or Final.
■
■
Preliminary characteristics are created using simulation results, process data, and
other known parameters. The title of these tables show the designation as
“Preliminary.”
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 23 lists the Stratix V GX and GS transceiver specifications.
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 1 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
Reference Clock
Dedicated
reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and
HCSL
Supported I/O
Standards
RX reference
clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference
Clock Frequency
(CMU PLL) (8)
—
—
40
—
—
710
710
40
—
—
710
710
40
—
—
710
710
MHz
MHz
Input Reference
Clock Frequency
(ATX PLL) (8)
100
100
100
Measure at
60 mV of
differential
signal (26)
Rise time
—
—
—
—
400
400
—
—
—
—
400
400
—
—
—
—
400
400
ps
Measure at
60 mV of
differential
signal (26)
Fall time
Duty cycle
—
45
30
—
—
55
33
45
30
—
—
55
33
45
30
—
—
55
33
%
Spread-spectrum
modulating clock
frequency
PCI Express®
(PCIe®)
kHz
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 19
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 2 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Conditions
Unit
Description
Min
Typ
0 to
–0.5
Max
Min
Typ
0 to
–0.5
Max
Min Typ
Max
0 to
—
Spread-spectrum
downspread
PCIe
—
—
—
—
—
—
%
–0.5
On-chip
termination
—
—
100
—
—
—
—
100
—
—
—
—
100
—
—
resistors (21)
Dedicated
reference
clock pin
1.6
1.6
1.6
(5)
Absolute VMAX
V
RX reference
clock pin
—
—
—
1.2
—
—
—
—
1.2
—
—
—
—
1.2
—
Absolute VMIN
—
–0.4
–0.4
–0.4
V
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
200
—
1600
mV
Dedicated
reference
clock pin
(2)
(2)
(2)
1050/1000/900/850
1.0/0.9/0.85 (4)
1050/1000/900/850
1.0/0.9/0.85 (4)
1050/1000/900/850
1.0/0.9/0.85 (4)
mV
V
V
ICM (AC
coupled) (3)
RX reference
clock pin
HCSL I/O
standard for
PCIe
VICM (DC coupled)
250
—
550
250
—
550
250
—
550
mV
reference
clock
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
-70
-90
—
—
—
—
—
—
—
—
—
—
-70
-90
—
—
—
—
—
—
—
—
—
—
-70
-90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Transmitter
REFCLK Phase
Noise
10 kHz
100 kHz
≥1 MHz
-100
-110
-120
-100
-110
-120
-100
-110
-120
(622 MHz) (20)
Transmitter
REFCLK Phase
Jitter
10 kHz to
1.5 MHz
(PCIe)
ps
(rms)
—
—
—
3
—
—
—
3
—
—
—
3
(100 MHz) (17)
180
0
1%
1800
1%
1800
1%
(19)
RREF
—
—
—
—
Transceiver Clocks
PCIe
Receiver
Detect
100
or
125
100
or
125
100
or
125
fixedclkclock
frequency
—
—
—
—
—
—
MHz
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 20
Switching Characteristics
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 3 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
Reconfiguration
clock
—
100
—
125
100
—
125
100
—
125
MHz
(mgmt_clk_clk)
frequency
Receiver
Supported I/O
Standards
—
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
8500/
Data rate
(Standard PCS)
600
600
—
—
12200
600
—
12200
600
—
10312.5
Mbps
Mbps
(9), (23)
(24)
8500/
Data rate
—
14100
600
—
12500
600
—
10312.5
(10G PCS) (9), (23)
(24)
Absolute VMAX for
a receiver pin
—
—
—
—
—
1.2
—
—
—
—
1.2
—
—
—
—
1.2
—
V
V
(5)
Absolute VMIN for
a receiver pin
–0.4
–0.4
–0.4
Maximum peak-
to-peak
differential input
voltage VID (diff p-
p) before device
configuration (22)
—
—
—
—
—
1.6
2.0
—
—
—
—
1.6
2.0
—
—
—
—
1.6
2.0
V
V
VCCR_GXB
1.0 V/1.05 V
(VICM
=
Maximum peak-
to-peak
=
0.70 V)
differential input
voltage VID (diff p-
p) after device
VCCR_GXB
0.90 V
(VICM = 0.6 V)
=
—
—
—
—
2.4
2.4
—
—
—
—
2.4
2.4
—
—
—
—
2.4
2.4
V
V
configuration (18)
,
(22)
VCCR_GXB
0.85 V
=
(VICM = 0.6 V)
Minimum
differential eye
opening at
—
85
—
—
85
—
—
85
—
—
mV
receiver serial
(6), (22),
input pins
(27)
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 21
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 4 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
85
30%
85
30%
85
—
85 setting
—
—
—
—
—
30%
100
100
100
—
100
setting
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30%
120
30%
120
30%
Differential on-
chip termination
resistors (21)
120
—
120
setting
30%
150
30%
150
30%
150
—
150-
setting
30%
30%
30%
VCCR_GXB
=
0.85 V or 0.9
V
full
bandwidth
—
—
600
—
—
—
—
600
—
—
—
—
600
600
—
—
mV
mV
VCCR_GXB
=
0.85 V or 0.9
V
600
600
VICM
(AC and DC
coupled)
half
bandwidth
VCCR_GXB
=
1.0 V/1.05 V
full
bandwidth
—
—
700
750
—
—
—
—
700
750
—
—
—
—
700
750
—
—
mV
mV
VCCR_GXB
1.0 V
=
half
bandwidth
(11)
tLTR
—
—
—
—
—
—
4
—
—
—
—
—
10
—
—
4
—
—
—
—
—
10
—
—
4
—
—
—
—
—
10
—
µs
µs
µs
µs
UI
(12)
tLTD
(13)
tLTD_manual
4
—
4
—
4
—
(14)
tLTR_LTD_manual
15
—
—
15
—
—
15
—
—
Run Length
200
200
200
Full
bandwidth
(6.25 GHz)
Programmable
equalization
—
—
16
—
—
16
—
—
16
dB
Half
bandwidth
(3.125 GHz)
(AC Gain) (10)
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 22
Switching Characteristics
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 5 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
DC Gain
Setting = 0
—
0
—
—
0
—
—
—
—
—
—
0
2
4
6
8
—
dB
dB
dB
dB
dB
DC Gain
Setting = 1
—
—
—
—
2
4
6
8
—
—
—
—
—
—
—
—
2
4
6
8
—
—
—
—
—
—
—
—
Programmable
DC gain
DC Gain
Setting = 2
DC Gain
Setting = 3
DC Gain
Setting = 4
Transmitter
Supported I/O
Standards
—
—
1.4-V and 1.5-V PCML
8500/
Data rate
(Standard PCS)
600
—
—
12200
600
—
—
12200
600
—
—
10312.5
Mbps
(24)
8500/
Data rate
(10G PCS)
—
600
—
14100
—
600
—
12500
—
600
—
10312.5
Mbps
(24)
85-
setting
85
20%
85
20%
85
20%
—
—
100
100
100
100-
setting
—
—
—
—
—
20%
120
20%
120
20%
120
Differential on-
chip termination
resistors
120-
setting
—
—
—
—
—
—
—
—
—
—
—
—
20%
150
20%
150
20%
150
150-
setting
20%
650
20%
650
20%
650
VOCM (AC
coupled)
0.65-V
setting
—
—
—
—
—
—
—
—
—
—
—
—
mV
mV
VOCM (DC
coupled)
—
650
650
650
(7)
Rise time
20% to 80%
80% to 20%
30
30
—
—
160
160
30
30
—
—
160
160
30
30
—
—
160
160
ps
ps
(7)
Fall time
Tx VCM
=
Intra-differential
pair skew
0.5 V and
slew rate of
15 ps
—
—
—
—
15
—
—
—
—
15
—
—
—
—
15
ps
ps
Intra-transceiver
block transmitter
channel-to-
x6 PMA
bonded mode
120
120
120
channel skew
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 23
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 6 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
Inter-transceiver
block transmitter
channel-to-
xN PMA
bonded mode
—
—
500
—
—
500
—
—
500
ps
channel skew
CMU PLL
8500/
Supported Data
Range
—
600
—
12500
600
—
12500
600
—
10312.5
Mbps
(24)
(15)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
1
—
—
—
10
µs
µs
(16)
tpll_lock
—
—
—
ATX PLL
VCO
8500/
post-divider 8000
L=2
—
14100 8000
—
12500 8000
—
10312.5
Mbps
(24)
L=4
L=8
4000
2000
—
—
7050
3525
4000
2000
—
—
6600
3300
4000
2000
—
—
6600
3300
Mbps
Mbps
Supported Data
Rate Range
L=8,
Local/Central
Clock Divider
=2
1000
—
1762.5 1000
—
1762.5 1000
—
1762.5
Mbps
(15)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
1
—
—
—
10
µs
µs
(16)
tpll_lock
—
—
—
fPLL
Supported Data
Range
3250/
3250/
3250/
—
—
600
1
—
—
600
1
—
—
600
1
—
—
Mbps
µs
3125 (25)
3125 (25)
3125 (25)
(15)
tpll_powerdown
—
—
—
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 24
Switching Characteristics
(1)
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
(Part 7 of 7)
Transceiver Speed
Grade 1
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
(16)
tpll_lock
—
—
—
10
—
—
10
—
—
10
µs
Notes to Table 23:
(1) Speed grades shown in Table 23 refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the
Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination
offered. For more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps, and to 1.05 V if configured at a data rate >
10.3 Gbps when DFE is used. For data rates up to 6.5 Gbps, you can connect this supply to 0.85 V.
(4) This supply follows VCCR_GXB.
(5) The device cannot tolerate prolonged operation at this absolute maximum.
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(8) The input reference clock frequency options depend on the data rate and the device speed grade.
(9) The line data rate may be limited by PCS-FPGA interface speed grade.
(10) Refer to Figure 1 for the GX channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(11) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(12) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(13) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(14) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
(15) tpll_powerdown is the PLL powerdown minimum pulse width.
(16) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(17) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(18) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(19) For ES devices, RREF is 2000 1%.
(20) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(21) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(22) Refer to Figure 1.
(23) For oversampling designs to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(24) I3YY devices can achieve data rates up to 10.3125 Gbps.
(25) When you use fPLL as a TXPLL of the transceiver.
(26) REFCLKperformance requires to meet transmitter REFCLKphase noise specification.
(27) Minimum eye opening of 85 mV is only for the unstressed input eye condition.
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 25
Table 24 shows the maximum transmitter data rate for the clock network.
(1)
Table 24. Clock Network Maximum Data Rate Transmitter Specifications
ATX PLL
CMU PLL (2)
fPLL
Non-
bonded
Mode
Non-
Non-
Bonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Clock Network
Channel bonded
Channel bonded
Channel
Span
Span
Mode
(Gbps)
Span
Mode
(Gbps)
(Gbps)
x1 (3)
x6 (3)
14.1
—
—
6
6
12.5
—
—
6
6
3.125
—
—
3
6
14.1
12.5
3.125
x6 PLL
Side-
wide
Side-
wide
—
—
14.1
8.0
—
—
12.5
5.0
—
—
—
—
—
—
Feedback (4)
xN (PCIe)
8
8
Up to 13
channels
above
and
below
PLL
8.0
—
8.0
Up to 13
channels
above
and
below
PLL
Up to 13
channels
above
and
below
PLL
xN (Native PHY IP)
7.99
7.99
3.125
3.125
Up to 7
channels
above
and
8.01 to
9.8304
below
PLL
Notes to Table 24:
(1) Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the
MegaWizard message during the PHY IP instantiation.
(2) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
(3) Channel span is within a transceiver bank.
(4) Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 26
Switching Characteristics
Table 25 shows the approximate maximum data rate using the standard PCS.
(1), (3)
Table 25. Stratix V Standard PCS Approximate Maximum Date Rate
PMA Width
20
40
20
20
16
32
16
16
10
20
10
10
8
8
8
Transceiver
Speed Grade
(2)
Mode
PCS/Core Width
16
C1, C2, C2L, I2, I2L
core speed grade
1
2
12.2
12.2
9.8
11.4
11.4
9.0
9.76
9.76
7.84
8.5
9.12
9.12
7.2
6.5
6.5
5.3
6.5
5.3
5.3
4.8
6.1
6.1
4.9
5.8
5.8
5.2 4.72
5.2 4.72
C1, C2, C2L, I2, I2L
core speed grade
C3, I3, I3L
core speed grade
4.7 4.24 3.76
5.8 5.2 4.72
C1, C2, C2L, I2, I2L
core speed grade
FIFO
8.5
8.5
8.5
I3YY
core speed grade
10.3125 10.3125
7.84
7.84
7.04
9.76
9.76
7.92
7.2
4.7 4.24 3.76
4.7 4.24 3.76
4.2 3.84 3.44
5.7 4.88 4.56
5.7 4.88 4.56
4.5 3.96 3.6
5.7 4.88 4.56
4.5 3.96 3.6
4.5 3.96 3.6
4.1 3.52 3.28
3
C3, I3, I3L
core speed grade
8.5
8.5
8.5
8.2
7.2
C4, I4
core speed grade
6.56
9.12
9.12
7.2
C1, C2, C2L, I2, I2L
core speed grade
1
2
12.2
12.2
9.8
11.4
11.4
9.0
C1, C2, C2L, I2, I2L
core speed grade
C3, I3, I3L
core speed grade
C1, C2, C2L, I2, I2L
core speed grade
Register
10.3125 10.3125 10.3125 10.3125 6.1
I3YY
core speed grade
10.3125 10.3125
7.92
7.92
7.04
7.2
7.2
4.9
4.9
4.4
3
C3, I3, I3L
core speed grade
8.5
8.5
8.5
8.2
C4, I4
core speed grade
6.56
Notes to Table 25:
(1) The maximum data rate is in Gbps.
(2) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
(3) The maximum data rate is also constrained by the transceiver speed grade. Refer to Table 1 for the transceiver speed grade.
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 27
Table 26 shows the approximate maximum data rate using the 10G PCS.
(1)
Table 26. Stratix V 10G PCS Approximate Maximum Data Rate
PMA Width
PCS Width
64
64
40
40
50
40
40
32
32
32
Transceiver
Speed Grade
(2)
Mode
66/67
64/66/67
C1, C2, C2L, I2, I2L
core speed grade
1
2
14.1
12.5
12.5
14.1
12.5
12.5
10.69
10.69
10.69
14.1
12.5
12.5
13.6
12.5
13.6
12.5
C1, C2, C2L, I2, I2L
core speed grade
C3, I3, I3L
core speed grade
10.88
10.88
FIFO or
Register
C1, C2, C2L, I2, I2L
core speed grade
C3, I3, I3L
core speed grade
8.5 Gbps
3
C4, I4
core speed grade
I3YY
core speed grade
10.3125 Gbps
Notes to Table 26:
(1) The maximum data rate is in Gbps.
(2) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 28
Switching Characteristics
Table 27 shows the VOD settings for the GX channel.
Table 27. Typical VOD Setting for GX Channel, TX Termination = 100 (2)
V
OD Value
(mV)
V
OD Value
(mV)
Symbol
VOD Setting
VOD Setting
32
0 (1)
1 (1)
2 (1)
3 (1)
4 (1)
5 (1)
6
0
640
20
40
60
80
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
660
680
700
720
100
120
140
160
180
200
220
240
260
280
300
320
340
360
380
400
420
440
460
480
500
520
540
560
580
600
620
740
760
7
780
8
800
9
820
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
840
860
880
900
920
940
V
OD differential peak to peak
(3)
typical
960
980
1000
1020
1040
1060
1080
1100
1120
1140
1160
1180
1200
1220
1240
1260
Note to Table 27:
(1) If TX termination resistance = 100this VOD setting is illegal.
(2) The tolerance is +/-20% for all VOD settings except for settings 2 and below.
(3) Refer to Figure 1.
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 29
Figure 1 shows the differential transmitter output waveform.
Figure 1. Differential Transmitter Output Waveform
Single-Ended Waveform
Positive Channel (p)
(single-ended)
/V
V
OD ID
Negative Channel (n)
Ground
V
CM
Differential Waveform
V
/V (differential peak to peak typical) = 2 x V /V (single-ended)
OD ID OD ID
(single-ended)
/V
V
OD ID
(single-ended)
/V
V
OD ID
Figure 2 shows the Stratix V AC gain curves for GX channels.
Figure 2. AC Gain Curves for GX Channels (full bandwidth)
1
Stratix V GT devices contain both GX and GT channels. All transceiver specifications
for the GX channels not listed in Table 28 are the same as those listed in Table 23.
Table 28 lists the Stratix V GT transceiver specifications.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 30
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 1 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Max
Description
Min
Typ
Max
Min
Typ
Reference Clock
Dedicated
reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS,
and HCSL
Supported I/O
Standards
RX reference
clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference Clock
Frequency (CMU
PLL) (6)
—
40
—
710
40
—
710
MHz
MHz
Input Reference Clock
Frequency (ATX PLL) (6)
—
100
—
710
100
—
710
Rise time
Fall time
20% to 80%
80% to 20%
—
—
—
45
—
—
—
400
400
55
—
—
45
—
—
—
400
400
55
ps
%
Duty cycle
Spread-spectrum
modulating clock
frequency
PCI Express
(PCIe)
30
—
33
30
—
33
kHz
Spread-spectrum
downspread
PCIe
—
—
—
0 to –0.5
100
—
—
—
—
0 to –0.5
100
—
—
%
On-chip termination
resistors (19)
Dedicated
reference
clock pin
—
—
1.6
—
—
1.6
(3)
Absolute VMAX
V
RX reference
clock pin
—
—
—
1.2
—
—
—
—
1.2
—
Absolute VMIN
—
-0.4
-0.4
V
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
mV
Dedicated
reference
clock pin
1050/1000 (2)
1050/1000 (2)
mV
V
VICM (AC coupled)
RX reference
clock pin
1.0/0.9/0.85 (22)
1.0/0.9/0.85 (22)
HCSL I/O
standard for
PCIe
VICM (DC coupled)
250
—
550
250
—
550
mV
reference
clock
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 31
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 2 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Description
Min
—
—
—
—
—
Typ
Max
-70
-90
Min
—
—
—
—
—
Typ
Max
-70
-90
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
Transmitter REFCLK
Phase Noise (622
MHz) (18)
10 kHz
100 kHz
≥ 1 MHz
-100
-110
-120
-100
-110
-120
dBc/Hz
Transmitter REFCLK
Phase Jitter (100
MHz) (15)
10 kHz to
1.5 MHz
(PCIe)
—
—
—
3
—
—
—
3
ps (rms)
1800
1%
1800
1%
RREF (17)
—
—
—
Transceiver Clocks
PCIe
Receiver
Detect
fixedclkclock
frequency
100 or
125
100 or
125
—
—
—
—
MHz
MHz
Reconfiguration clock
(mgmt_clk_clk
)
—
100
—
125
100
—
125
frequency
Receiver
Supported I/O
Standards
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate
GX channels
600
—
8500
600
—
8500
Mbps
(Standard PCS) (21)
Data rate
GX channels
GT channels
GT channels
600
19,600
—
—
—
—
12,500
28,050
1.2
600
19,600
—
—
—
—
12,500
25,780
1.2
Mbps
Mbps
V
(10G PCS) (21)
Data rate
Absolute VMAX for a
receiver pin
(3)
Absolute VMIN for a
receiver pin
GT channels
–0.4
—
—
—
—
–0.4
—
—
—
—
V
V
Maximum peak-to-peak GT channels
differential input
1.6
1.6
voltage VID (diff p-p)
(8)
GX channels
before device
configuration (20)
GT channels
Maximum peak-to-peak
differential input
voltage VID (diff p-p)
VCCR_GTB
1.05 V
=
—
—
—
2.2
—
—
—
—
2.2
—
V
(VICM
=
after device
0.65 V)
(20)
configuration (16)
,
(8)
GX channels
GT channels
Minimum differential
200
200
mV
eye opening at receiver
(8)
GX channels
(4) (20)
serial input pins
,
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 32
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 3 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Max
Description
Min
Typ
Max
Min
Typ
Differential on-chip
GT channels
—
100
—
—
100
—
—
—
—
termination resistors (7)
85
30%
85-setting
—
—
—
85 30%
—
—
—
—
—
—
100-
setting
100
30%
100
30%
Differential on-chip
termination resistors
for GX channels (19)
120-
setting
120
30%
120
30%
150-
setting
150
30%
150
30%
—
—
—
—
—
—
—
—
VICM (AC coupled)
GT channels
650
650
mV
VCCR_GXB=
0.85 V or
0.9 V
—
—
—
600
—
—
—
—
—
—
600
—
—
—
mV
mV
mV
VICM (AC and DC
coupled) for GX
Channels
VCCR_GXB=
1.0 V full
bandwidth
700
750
700
750
VCCR_GXB=
1.0 V half
bandwidth
(9)
tLTR
—
—
4
—
—
—
—
—
10
—
—
—
72
—
4
—
—
—
—
—
10
—
—
—
72
µs
µs
(10)
tLTD
—
(11)
tLTD_manual
—
4
4
µs
(12)
tLTR_LTD_manual
—
15
—
15
µs
GT channels
GX channels
GT channels
GX channels
GT channels
—
(8)
CID
Run Length
CDR PPM
—
—
—
—
1000
14
—
(8)
—
—
1000
14
PPM
dB
Programmable
equalization
(AC Gain) (5)
—
(8)
GX channels
GT channels
GX channels
—
—
—
7.5
—
—
(8)
—
7.5
—
dB
Programmable
DC gain (6)
Differential on-chip
GT channels
100
—
100
termination resistors (7)
Transmitter
Supported I/O
Standards
—
1.4-V and 1.5-V PCML
Data rate
(Standard PCS)
GX channels
GX channels
600
600
—
—
8500
12,500
600
600
—
8500
Mbps
Mbps
Data rate
(10G PCS)
—
12,500
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 33
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 4 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Description
Min
19,600
—
Typ
—
Max
28,050
—
Min
Typ
—
Max
25,780
—
Data rate
GT channels
GT channels
GX channels
GT channels
GX channels
GT channels
GX channels
19,600
Mbps
100
—
(8)
100
Differential on-chip
termination resistors
—
—
500
15
—
—
—
(8)
500
15
—
—
mV
ps
VOCM (AC coupled)
Rise/Fall time
—
(8)
Intra-differential pair
skew
(8)
(8)
GX channels
Intra-transceiver block
transmitter channel-
to-channel skew
GX channels
Inter-transceiver block
transmitter channel-
to-channel skew
(8)
GX channels
CMU PLL
Supported Data Range
—
—
—
600
1
—
—
—
12500
—
600
1
—
—
—
8500
—
Mbps
µs
(13)
tpll_powerdown
(14)
tpll_lock
—
10
—
10
µs
ATX PLL
VCO post-
divider L=2
8000
—
12500
8000
—
8500
Mbps
L=4
L=8
4000
2000
—
—
6600
3300
4000
2000
—
—
6600
3300
Mbps
Mbps
Supported Data Rate
Range for GX Channels
L=8,
Local/Central
Clock Divider
=2
1000
9800
—
1762.5
1000
9800
—
1762.5
Mbps
Supported Data Rate
Range for GT Channels
VCO post-
divider L=2
—
14025
—
12890
Mbps
(13)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
µs
µs
(14)
tpll_lock
—
—
fPLL
3250/
3250/
Supported Data Range
—
—
600
1
—
—
600
1
—
Mbps
µs
3.125 (23)
3.125 (23)
—
(13)
tpll_powerdown
—
—
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 34
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 5 of 5) (1)
Transceiver
Transceiver
Symbol/
Speed Grade 2
Speed Grade 3
Conditions
Unit
Max
Description
Min
Typ
Max
Min
Typ
(14)
tpll_lock
—
—
—
10
—
—
10
µs
Notes to Table 28:
(1) Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS
speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For
more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The differential eye opening specification at the receiver input pins assumes that receiver equalization is disabled. If you enable receiver
equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(5) Refer to Figure 4 for the GT channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(6) Refer to Figure 5 for the GT channel DC gain curves.
(7) CFP2 optical modules require the host interface to have the receiver data pins differentially terminated with 100 . The internal OCT feature is
available after the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the
optical module. Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(8) Specifications for this parameter are the same as for Stratix V GX and GS devices. See Table 23 for specifications.
(9) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(10) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.
(11) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the
CDR is functioning in the manual mode.
(12) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when
the CDR is functioning in the manual mode.
(13) tpll_powerdownis the PLL powerdown minimum pulse width.
(14) tpll_lockis the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(15) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(16) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(17) For ES devices, RREF is 2000 1%.
(18) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(19) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(20) Refer to Figure 3.
(21) For oversampling design to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(22) This supply follows VCCR_GXB for both GX and GT channels.
(23) When you use fPLL as a TXPLL of the transceiver.
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 35
Table 29 shows the VOD settings for the GT channel.
Table 29. Typical VOD Setting for GT Channel, TX Termination = 100
Symbol
VOD Setting
VOD Value (mV)
0
1
2
3
4
5
0
200
400
600
800
1000
V
OD differential peak to peak typical (1)
Note:
(1) Refer to Figure 3.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 36
Switching Characteristics
Figure 3 shows the differential transmitter output waveform.
Figure 3. Differential Transmitter/Receiver Output/Input Waveform
Single-Ended Waveform
Positive Channel (p)
(single-ended)
/V
V
OD ID
Negative Channel (n)
Ground
V
CM
Differential Waveform
V
/V (differential peak to peak typical) = 2 x V /V (single-ended)
OD ID OD ID
(single-ended)
/V
V
OD ID
(single-ended)
/V
V
OD ID
Figure 4 shows the Stratix V AC gain curves for GT channels.
Figure 4. AC Gain Curves for GT Channels
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 37
Figure 5 shows the Stratix V DC gain curves for GT channels.
Figure 5. DC Gain Curves for GT Channels
Transceiver Characterization
This section summarizes the Stratix V transceiver characterization results for
compliance with the following protocols:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Interlaken
40G (XLAUI)/100G (CAUI)
10GBase-KR
QSGMII
XAUI
SFI
Gigabit Ethernet (Gbe / GIGE)
SPAUI
Serial Rapid IO (SRIO)
CPRI
OBSAI
Hyper Transport (HT)
SATA
SAS
CEI
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 38
Switching Characteristics
■
■
■
■
■
■
■
■
■
■
■
■
XFI
ASI
HiGig/HiGig+
HiGig2/HiGig2+
Serial Data Converter (SDC)
GPON
SDI
SONET
Fibre Channel (FC)
PCIe
QPI
SFF-8431
Download the Stratix V Characterization Report Tool to view the characterization
report summary for these protocols.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks, configuration, and JTAG specifications.
Clock Tree Specifications
Table 30 lists the clock tree specifications for Stratix V devices.
(1)
Table 30. Clock Tree Performance for Stratix V Devices
Performance
Symbol
Unit
C1, C2, C2L, I2, and
I2L
C3, I3, I3L, and
I3YY
C4, I4
Global and
Regional Clock
717
550
650
500
580
500
MHz
MHz
Periphery Clock
Note to Table 30:
(1) The Stratix V ES devices are limited to 600 MHz core clock tree performance.
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 39
PLL Specifications
Table 31 lists the Stratix V PLL specifications when operating in both the commercial
junction temperature range (0° to 85°C) and the industrial junction temperature range
(–40° to 100°C).
Table 31. PLL Specifications for Stratix V Devices (Part 1 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Input clock frequency (C1, C2, C2L, I2, and I2L speed
grades)
5
—
800 (1)
MHz
fIN
Input clock frequency (C3, I3, I3L, and I3YY speed
grades)
5
—
800 (1)
MHz
Input clock frequency (C4, I4 speed grades)
Input frequency to the PFD
5
5
—
—
—
650 (1)
325
MHz
MHz
MHz
fINPFD
fFINPFD
Fractional Input clock frequency to the PFD
50
160
PLL VCO operating range (C1, C2, C2L, I2, I2L speed
grades)
600
600
—
—
1600
1600
MHz
MHz
(9)
fVCO
PLL VCO operating range (C3, I3, I3L, I3YY speed
grades)
PLL VCO operating range (C4, I4 speed grades)
600
40
—
—
1300
60
MHz
%
tEINDUTY
Input clock or external feedback clock input duty cycle
Output frequency for an internal global or regional
clock (C1, C2, C2L, I2, I2L speed grades)
—
—
—
—
—
—
—
—
—
—
—
—
717 (2)
MHz
MHz
MHz
MHz
MHz
MHz
Output frequency for an internal global or regional
clock (C3, I3, I3L speed grades)
(2)
fOUT
650
Output frequency for an internal global or regional
clock (C4, I4 speed grades)
580 (2)
800 (2)
Output frequency for an external clock output (C1, C2,
C2L, I2, I2L speed grades)
Output frequency for an external clock output (C3, I3,
I3L speed grades)
(2)
fOUT_EXT
667
Output frequency for an external clock output (C4, I4
speed grades)
(2)
553
Duty cycle for a dedicated external clock output (when
set to 50%)
tOUTDUTY
tFCOMP
45
—
—
50
—
—
55
10
%
ns
External feedback clock compensation time
Dynamic Configuration Clock used for mgmt_clkand
scanclk
fDYCONFIGCLK
100
MHz
Time required to lock from the end-of-device
configuration or deassertion of areset
tLOCK
—
—
—
—
1
1
ms
ms
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
tDLOCK
PLL closed-loop low bandwidth
—
—
—
—
10
0.3
1.5
4
—
—
—
50
—
MHz
MHz
MHz
ps
fCLBW
PLL closed-loop medium bandwidth
(7)
PLL closed-loop high bandwidth
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
Minimum pulse width on the aresetsignal
ns
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 40
Switching Characteristics
Table 31. PLL Specifications for Stratix V Devices (Part 2 of 3)
Symbol
Parameter
Min
—
Typ
—
Max
0.15
+750
Unit
Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (fREF < 100 MHz)
UI (p-p)
ps (p-p)
(3), (4)
tINCCJ
–750
—
Period Jitter for dedicated clock output (fOUT
100 MHz)
≥
(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
175
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
(5)
tOUTPJ_DC
Period Jitter for dedicated clock output (fOUT
100 MHz)
<
(1)
17.5
Period Jitter for dedicated clock output in fractional
PLL (fOUT 100 MHz)
250 (11)
175 (12)
,
(5)
tFOUTPJ_DC
tOUTCCJ_DC
tFOUTCCJ_DC
Period Jitter for dedicated clock output in fractional
PLL (fOUT < 100 MHz)
25 (11)
,
17.5 (12)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT ≥ 100 MHz)
175
(5)
(5)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT < 100 MHz)
17.5
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT 100 MHz)
250 (11)
175 (12)
,
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT < 100 MHz)+
25 (11)
,
17.5 (12)
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT ≥ 100 MHz)
600
(5),
tOUTPJ_IO
(8)
Period Jitter for a clock output on a regular I/O
(fOUT < 100 MHz)
60
600 (10)
60 (10)
600
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT 100 MHz)
(5),
tFOUTPJ_IO
(8) (11)
,
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT < 100 MHz)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT 100 MHz)
(5),
(5),
tOUTCCJ_IO
(8)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT < 100 MHz)
60 (10)
600 (10)
60
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT 100 MHz)
tFOUTCCJ_IO
(8) (11)
,
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT < 100 MHz)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT ≥ 100 MHz)
175
tCASC_OUTPJ_DC
(5), (6)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT < 100 MHz)
17.5
Frequency drift after PFDENA is disabled for a duration
of 100 µs
fDRIFT
—
24
10
32
dKBIT
Bit number of Delta Sigma Modulator (DSM)
Numerator of Fraction
8
Bits
—
kVALUE
128
8388608 2147483648
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 41
Table 31. PLL Specifications for Stratix V Devices (Part 3 of 3)
Symbol
fRES
Parameter
Min
Typ
Max
Unit
Hz
Resolution of VCO frequency (fINPFD = 100 MHz)
390625
5.96
0.023
Notes to Table 31:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(4) fREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 44 on page 52.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) The external memory interface clock output jitter specifications use a different measurement method, which is available in Table 42 on page 50.
(9) The VCO frequency reported by the Quartus II software in the PLL Usage Summary section of the compilation report takes into consideration
the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(10) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05 - 0.95 must be 1000 MHz, while fVCO
for fractional value range 0.20 - 0.80 must be 1200 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05-0.95 must be 1000 MHz.
(12) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20-0.80 must be 1200 MHz.
DSP Block Specifications
Table 32 lists the Stratix V DSP block performance specifications.
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 1 of 2)
Peformance
Mode
Unit
I3, I3L,
I3YY
C1
C2, C2L I2, I2L
C3
C4
I4
Modes using one DSP
Three 9 x 9
One 18 x 18
600
600
600
600
500
500
600
600
600
500
500
480
480
480
480
400
400
420
420
MHz
600
600
500
500
480
480
400
400
420
420
350
350
400
400
350
350
MHz
MHz
MHz
MHz
Two partial 18 x 18 (or 16 x 16)
One 27 x 27
One 36 x 18
One sum of two 18 x 18(One sum of
2 16 x 16)
500
500
500
400
400
350
350
MHz
One sum of square
500
500
500
500
500
500
400
400
400
400
350
350
350
350
MHz
MHz
One 18 x 18 plus 36 (a x b) + c
Modes using two DSPs
Three 18 x 18
500
475
465
475
500
475
500
475
465
475
500
475
500
475
450
475
500
475
400
380
380
380
400
380
400
380
380
380
400
380
350
300
300
300
350
300
350
300
290
300
350
300
MHz
MHz
MHz
MHz
MHz
MHz
One sum of four 18 x 18
One sum of two 27 x 27
One sum of two 36 x 18
One complex 18 x 18
One 36 x 36
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 42
Switching Characteristics
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 2 of 2)
Peformance
Mode
Unit
I4
I3, I3L,
I3YY
C1
C2, C2L I2, I2L
C3
C4
Modes using Three DSPs
425 415 340
Modes using Four DSPs
465 465 380
One complex 18 x 25
One complex 27 x 27
425
340
275
265
290
MHz
MHz
465
380
300
Memory Block Specifications
Table 33 lists the Stratix V memory block specifications.
Table 33. Memory Block Performance Specifications for Stratix V Devices (1), (2) (Part 1 of 2)
Resources Used
ALUTs Memory
Performance
I3,
Memory
Mode
Unit
C2,
C2L
C1
C3
C4
I2, I2L I3L,
I3YY
I4
Single port, all
supported widths
0
0
0
0
1
1
1
1
450
450
675
600
450
450
675
600
400
400
533
500
315
315
400
450
450
450
675
600
400
400
533
500
315 MHz
315 MHz
400 MHz
450 MHz
Simple dual-port,
x32/x64 depth
MLAB
Simple dual-port, x16
depth (3)
ROM, all supported
widths
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 43
Table 33. Memory Block Performance Specifications for Stratix V Devices (1), (2) (Part 2 of 2)
Resources Used
Performance
I3,
Memory
Mode
Unit
C2,
C2L
ALUTs Memory
C1
C3
C4
I2, I2L I3L,
I3YY
I4
Single-port, all
supported widths
0
0
1
1
700
700
700
700
650
650
550
550
700
700
500
500
450 MHz
450 MHz
Simple dual-port, all
supported widths
Simple dual-port with
the read-during-write
option set to Old Data,
all supported widths
0
0
0
1
1
1
525
450
600
525
450
600
455
400
500
400
350
450
525
450
600
455
400
500
400 MHz
350 MHz
450 MHz
M20K
Block
Simple dual-port with
ECC enabled, 512 × 32
Simple dual-port with
ECC and optional
pipeline registers
enabled, 512 × 32
True dual port, all
supported widths
0
0
1
1
700
700
700
700
650
650
550
550
700
700
500
500
450 MHz
450 MHz
ROM, all supported
widths
Notes to Table 33:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX
.
(3) The FMAX specification is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled.
Temperature Sensing Diode Specifications
Table 34 lists the internal TSD specification.
Table 34. Internal Temperature Sensing Diode Specification
Minimum
Resolution
with no
Offset
Calibrated
Option
Temperature
Range
Conversion
Time
Accuracy
Sampling Rate
Resolution
Missing Codes
–40°C to 100°C
8°C
No
1 MHz, 500 KHz
< 100 ms
8 bits
8 bits
Table 35 lists the specifications for the Stratix V external temperature sensing diode.
Table 35. External Temperature Sensing Diode Specifications for Stratix V Devices
Description
Min
8
Typ
—
Max
200
0.9
Unit
A
V
Ibias, diode source current
V
bias, voltage across diode
0.3
—
Series resistance
—
—
< 1
Diode ideality factor
1.006
1.008
1.010
—
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 44
Switching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of a typical 167 MHz and 1.2-LVCMOS at 100 MHz interfacing frequency
with a 10 pF load.
1
The actual achievable frequency depends on design- and system-specific factors.
Ensure proper timing closure in your design and perform HSPICE/IBIS simulations
based on your specific design and system setup to determine the maximum
achievable frequency in your system.
High-Speed I/O Specification
Table 36 lists high-speed I/O timing for Stratix V devices.
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 1 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK_in(input
clock
frequency)
True
Clock boost factor
W = 1 to 40
5
5
—
—
800
800
5
5
—
—
800
800
5
5
—
—
625
5
5
—
—
525
MHz
(4)
Differential
I/O Standards
fHSCLK_in(input
clock
frequency)
Single Ended
I/O
Clock boost factor
W = 1 to 40
625
420
525
420
MHz
(4)
Standards (3)
fHSCLK_in(input
clock
frequency)
Single Ended
I/O Standards
Clock boost factor
5
5
—
—
520
800
5
5
—
—
520
800
5
5
—
—
5
5
—
—
MHz
MHz
(4)
W = 1 to 40
fHSCLK_OUT
(output clock
frequency)
625
525
—
(5)
(5)
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 45
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 2 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Transmitter
SERDES factor J
(9), (11),
= 3 to 10
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
—
—
1600
1600
—
—
1434
1600
—
—
1250
1600
—
—
1050 Mbps
1250 Mbps
(12), (13), (14), (15),
(16)
SERDES factor J
4
True
LVDS TX with
(12) (14), (15),
Differential
I/O Standards
- fHSDR (data
rate)
DPA
,
(16)
SERDES factor J
= 2,
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
—
—
—
—
—
—
—
—
Mbps
uses DDR
Registers
SERDES factor J
= 1,
(7)
Mbps
uses SDR
Register
Emulated
Differential
I/O Standards
with Three
External
SERDES factor J
= 4 to 10
(6)
(6)
(6)
(6)
—
1100
—
1100
—
840
—
840 Mbps
(17)
Output
Resistor
Networks -
fHSDR (data
(10)
rate)
Total Jitter for
Data Rate
600 Mbps -
1.25 Gbps
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
—
—
—
—
—
—
160
0.1
ps
UI
ps
tx Jitter - True
Differential
I/O Standards
Total Jitter for
Data Rate
< 600 Mbps
tx Jitter
-
Total Jitter for
Data Rate
600 Mbps - 1.25
Gbps
Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
300
300
300
325
Total Jitter for
Data Rate
< 600 Mbps
—
—
0.2
—
—
0.2
—
—
0.2
—
—
0.25
UI
Network
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 46
Switching Characteristics
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 3 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Unit
Symbol
Conditions
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Transmitter
output clock duty
cycle for both
True and
tDUTY
45 50
55
45 50
55
45 50
55
45 50
55
%
Emulated
Differential I/O
Standards
True Differential
I/O Standards
—
—
—
—
160
250
—
—
—
—
160
250
—
—
—
—
200
250
—
—
—
—
200
300
ps
ps
Emulated
Differential I/O
Standards with
three external
output resistor
networks
tRISE & tFALL
True Differential
I/O Standards
—
—
—
—
150
300
—
—
—
—
150
300
—
—
—
—
150
300
—
—
—
—
150
300
ps
ps
TCCS
Emulated
Differential I/O
Standards
Receiver
SERDES factor J
(11), (12),
= 3 to 10
150
150
—
—
1434 150
1600 150
—
—
1434 150
1600 150
—
—
1250 150
1600 150
—
—
1050 Mbps
1250 Mbps
(13), (14), (15), (16)
SERDES factor J
4
LVDS RX with
True
(12), (14), (15),
DPA
Differential
I/O Standards
- fHSDRDPA
(data rate)
(16)
SERDES factor J
= 2,
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
(7)
(6)
(6)
(7)
—
—
—
—
—
—
—
—
Mbps
uses DDR
Registers
SERDES factor J
= 1,
(7)
Mbps
uses SDR
Register
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 47
Table 36. High-Speed I/O Specifications for Stratix V Devices (1), (2) (Part 4 of 4)
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Symbol
Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
SERDES factor J
= 3 to 10
(6)
(6)
(8)
(7)
(6)
(6)
(8)
(7)
(6)
(6)
(8)
(7)
(6)
(6)
(8)
(7)
—
—
—
—
—
—
—
—
Mbps
SERDES factor J
= 2,
Mbps
Mbps
fHSDR (data
rate)
uses DDR
Registers
SERDES factor J
= 1,
(6)
(7)
(6)
(7)
(6)
(7)
(6)
(7)
—
—
—
—
uses SDR
Register
DPA Mode
DPA run
length
1000
0
1000
0
1000
0
1000
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UI
Soft CDR mode
Soft-CDR
PPM
tolerance
300
300
300
300
300
300
300
300
PPM
ps
Non DPA Mode
Sampling
Window
Notes to Table 36:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) This only applies to DPA and soft-CDR modes.
(4) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(5) This is achieved by using the LVDS clock network.
(6) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(7) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing
and the signal integrity simulation is clean.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
(9) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(10) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(11) The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which
is design-dependent and requires timing analysis.
(12) Stratix V RX LVDS will need DPA. For Stratix V TX LVDS, the receiver side component must have DPA.
(13) Stratix V LVDS serialization and de-serialization factor needs to be x4 and above.
(14) Requires package skew compensation with PCB trace length.
(15) Do not mix single-ended I/O buffer within LVDS I/O bank.
(16) Chip-to-chip communication only with a maximum load of 5 pF.
(17) When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 48
Switching Characteristics
Figure 6 shows the dynamic phase alignment (DPA) lock time specifications with the
DPA PLL calibration option enabled.
Figure 6. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Table 37 lists the DPA lock time specifications for Stratix V devices.
Table 37. DPA Lock Time Specifications for Stratix V GX Devices Only (1), (2), (3)
Number of Data
Number of
Transitions in One
Standard
Training Pattern
Repetitions per 256
Maximum
Repetition of the
Training Pattern
(4)
Data Transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Parallel Rapid I/O
10010000
10101010
32
Miscellaneous
01010101
32
Notes to Table 37:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 7 shows the LVDS soft-clock data recovery (CDR)/DPA sinusoidal jitter
tolerance specification for a data rate 1.25 Gbps. Table 38 lists the LVDS
soft-CDR/DPA sinusoidal jitter tolerance specification for a data rate 1.25 Gbps.
Figure 7. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.35
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 49
Table 38. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate 1.25 Gbps
Jitter Frequency (Hz) Sinusoidal Jitter (UI)
F1
F2
F3
F4
10,000
17,565
25.000
25.000
0.350
1,493,000
50,000,000
0.350
Figure 8 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate < 1.25 Gbps.
Figure 8. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate < 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
20 MHz
baud/1667
DLL Range, DQS Logic Block, and Memory Output Clock Jitter Specifications
Table 39 lists the DLL range specification for Stratix V devices. The DLL is always in
8-tap mode in Stratix V devices.
(1)
Table 39. DLL Range Specifications for Stratix V Devices
C1
300-933
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Unit
300-933
300-890
300-890
MHz
Note to Table 39:
(1) Stratix V devices support memory interface frequencies lower than 300 MHz, although the reference clock that feeds the DLL must be at least
300 MHz. To support interfaces below 300 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported
range of the DLL.
Table 40 lists the DQS phase offset delay per stage for Stratix V devices.
(1), (2)
Table 40. DQS Phase Offset Delay Per Setting for Stratix V Devices
(Part 1 of 2)
Unit
Speed Grade
C1
Min
8
Max
14
ps
ps
ps
C2, C2L, I2, I2L
C3,I3, I3L, I3YY
8
14
8
15
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 50
Switching Characteristics
(Part 2 of 2)
(1), (2)
Table 40. DQS Phase Offset Delay Per Setting for Stratix V Devices
Speed Grade
Min
Max
16
Unit
C4,I4
8
ps
Notes to Table 40:
(1) The typical value equals the average of the minimum and maximum values.
(2) The delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when
using a –2 speed grade and applying a 10-phase offset setting to a 90° phase shift at 400 MHz, the expected
average cumulative delay is [625 ps + (10 × 10 ps) 20 ps] = 725 ps 20 ps.
Table 41 lists the DQS phase shift error for Stratix V devices.
Table 41. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Stratix V Devices (1)
Number of DQS Delay
C1
C2, C2L, I2, I2L C3, I3, I3L, I3YY
C4,I4
Unit
Buffers
1
2
3
28
56
28
56
30
60
32
64
ps
ps
ps
ps
84
84
90
96
4
112
112
120
128
Notes to Table 41:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a –2 speed grade
is 78 ps or 39 ps.
Table 42 lists the memory output clock jitter specifications for Stratix V devices.
Table 42. Memory Output Clock Jitter Specification for Stratix V Devices (1), (Part 1 of 2) (2), (3)
C3, I3, I3L,
C1
C2, C2L, I2, I2L
C4,I4
Max
Clock
I3YY
Parameter
Symbol
Unit
Network
Min
Max
Min
Max
Min
Max
Min
Clock period jitter
tJIT(per)
tJIT(cc)
–50
50
–50
50
–55
55
–55
55
ps
ps
Cycle-to-cycle period
jitter
Regional
Global
–100
100
–100
100
–110
110
–110
110
Duty cycle jitter
tJIT(duty)
tJIT(per)
–50
–75
50
75
–50
–75
50
75
–82.5
–82.5
82.5
82.5
–82.5
–82.5
82.5
82.5
ps
ps
Clock period jitter
Cycle-to-cycle period
jitter
tJIT(cc)
–150
–75
150
75
–150
–75
150
75
–165
–90
165
90
–165
–90
165
90
ps
ps
Duty cycle jitter
tJIT(duty)
Stratix V Device Datasheet
December 2015 Altera Corporation
Switching Characteristics
Page 51
Table 42. Memory Output Clock Jitter Specification for Stratix V Devices (1), (Part 2 of 2) (2), (3)
C3, I3, I3L,
C1
C2, C2L, I2, I2L
C4,I4
Max
Clock
I3YY
Parameter
Symbol
Unit
Network
Min
Max
Min
Max
Min
Max
Min
Clock period jitter
tJIT(per)
tJIT(cc)
–25
25
–25
25
–30
30
–35
35
70
56
ps
ps
ps
PHY
Clock
Cycle-to-cycle period
jitter
–50
50
–50
50
–60
–45
60
45
–70
–56
Duty cycle jitter
tJIT(duty)
–37.5
37.5
–37.5
37.5
Notes to Table 42:
(1) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
PLL output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible.
(2) The clock jitter specification applies to the memory output clock pins clocked by an integer PLL.
(3) The memory output clock jitter is applicable when an input jitter of 30 ps peak-to-peak is applied with bit error rate (BER) -12, equivalent to 14
sigma.
OCT Calibration Block Specifications
Table 43 lists the OCT calibration block specifications for Stratix V devices.
Table 43. OCT Calibration Block Specifications for Stratix V Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by the OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for OCT RS/RT
calibration
TOCTCAL
—
—
1000
32
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for the OCT
code to shift out
TOCTSHIFT
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT RS and RT (Figure 9)
TRS_RT
—
2.5
—
ns
Figure 9 shows the timing diagram for the oe and dyn_term_ctrlsignals.
Figure 9. Timing Diagram for oe and dyn_term_ctrl Signals
Tristate
Tristate
RX
TX
RX
oe
dyn_term_ctrl
T
T
RS_RT
RS_RT
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 52
Configuration Specification
Duty Cycle Distortion (DCD) Specifications
Table 44 lists the worst-case DCD for Stratix V devices.
Table 44. Worst-Case DCD on Stratix V I/O Pins (1)
C3, I3, I3L,
I3YY
C1
C2, C2L, I2, I2L
C4,I4
Symbol
Unit
Min
Max
Min
Max
Min
45
Max
Min
Max
55
Output Duty Cycle
45
55
45
55
55
45
%
Note to Table 44:
(1) The DCD numbers do not cover the core clock network.
Configuration Specification
POR Delay Specification
Power-on reset (POR) delay is defined as the delay between the time when all the
power supplies monitored by the POR circuitry reach the minimum recommended
operating voltage to the time when the nSTATUSis released high and your device is
ready to begin configuration.
f
For more information about the POR delay, refer to the Hot Socketing and Power-On
Reset in Stratix V Devices chapter.
Table 45 lists the fast and standard POR delay specification.
(1)
Table 45. Fast and Standard POR Delay Specification
POR Delay
Minimum
4 ms
Maximum
12 ms
Fast
Standard
100 ms
300 ms
Note to Table 45:
(1) You can select the POR delay based on the MSELsettings as described in the MSEL Pin Settings section of the
“Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
JTAG Configuration Specifications
Table 46 lists the JTAG timing parameters and values for Stratix V devices.
Table 46. JTAG Timing Parameters and Values for Stratix V Devices
Symbol
Description
TCK clock period (2)
TCK clock period (2)
TCK clock high time (2)
TCK clock low time (2)
TDI JTAG port setup time
TMS JTAG port setup time
Min
30
167
14
14
2
Max
—
Unit
ns
tJCP
tJCP
tJCH
tJCL
—
ns
—
ns
—
ns
tJPSU (TDI)
tJPSU (TMS)
—
ns
3
—
ns
Stratix V Device Datasheet
December 2015 Altera Corporation
Configuration Specification
Page 53
Table 46. JTAG Timing Parameters and Values for Stratix V Devices
Symbol
tJPH
Description
JTAG port hold time
Min
5
Max
Unit
—
ns
ns
ns
ns
(1)
tJPCO
JTAG port clock to output
—
—
—
11
14
14
(1)
(1)
tJPZX
JTAG port high impedance to valid output
JTAG port valid output to high impedance
tJPXZ
Notes to Table 46:
(1) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
(2) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2V-1.5V when you perform the volatile
key programming.
Raw Binary File Size
For the POR delay specification, refer to the “POR Delay Specification” section of the
“Configuration, Design Security, and Remote System Upgrades in Stratix V Devices”.
Table 47 lists the uncompressed raw binary file (.rbf) sizes for Stratix V devices.
Table 47. Uncompressed .rbf Sizes for Stratix V Devices
Family
Device
Package
Configuration .rbf Size (bits) IOCSR .rbf Size (bits) (4), (5)
H35, F40, F35 (2)
H29, F35 (3)
213,798,880
137,598,880
213,798,880
269,979,008
269,979,008
342,742,976
342,742,976
270,528,640
270,528,640
342,742,976
342,742,976
269,979,008
269,979,008
137,598,880
213,798,880
137,598,880
213,798,880
293,441,888
293,441,888
562,392
564,504
563,672
562,392
562,392
700,888
700,888
584,344
584,344
700,888
700,888
562,392
562,392
564,504
563,672
564,504
563,672
565,528
565,528
5SGXA3
5SGXA4
5SGXA5
5SGXA7
5SGXA9
5SGXAB
5SGXB5
5SGXB6
5SGXB9
5SGXBB
5SGTC5
5SGTC7
5SGSD3
—
—
—
Stratix V GX
—
—
—
—
—
—
—
Stratix V GT
Stratix V GS
—
—
F1517
—
5SGSD4
5SGSD5
5SGSD6
5SGSD8
—
—
—
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 54
Configuration Specification
Table 47. Uncompressed .rbf Sizes for Stratix V Devices
Family
Device
5SEE9
5SEEB
Package
Configuration .rbf Size (bits) IOCSR .rbf Size (bits) (4), (5)
—
—
342,742,976
342,742,976
700,888
700,888
Stratix V E (1)
Notes to Table 47:
(1) Stratix V E devices do not have PCI Express (PCIe) hard IP. Stratix V E devices do not support the CvP configuration scheme.
(2) 36-transceiver devices.
(3) 24-transceiver devices.
(4) File size for the periphery image.
(5) The IOCSR .rbf size is specifically for the CvP feature.
Use the data in Table 47 to estimate the file size before design compilation. Different
configuration file formats, such as a hexadecimal (.hex) or tabular text file (.ttf)
format, have different file sizes. For the different types of configuration file and file
sizes, refer to the Quartus II software. However, for a specific version of the Quartus II
software, any design targeted for the same device has the same uncompressed
configuration file size. If you are using compression, the file size can vary after each
compilation because the compression ratio depends on your design.
f
For more information about setting device configuration options, refer to
Configuration, Design Security, and Remote System Upgrades in Stratix V Devices. For
creating configuration files, refer to the Quartus II Help.
Table 48 lists the minimum configuration time estimates for Stratix V devices.
Table 48. Minimum Configuration Time Estimation for Stratix V Devices
Active Serial (1)
Fast Passive Parallel (2)
Member
Variant
Min Config
Time (s)
Min Config
Code
Width
DCLK (MHz)
Width
DCLK (MHz)
Time (s)
0.067
0.043
0.067
0.084
0.084
0.107
0.107
0.085
0.085
0.107
0.107
0.084
0.084
4
4
4
4
4
4
4
4
4
4
4
4
4
100
100
100
100
100
100
100
100
100
100
100
100
100
0.534
0.344
0.534
0.675
0.675
0.857
0.857
0.676
0.676
0.857
0.857
0.675
0.675
32
32
32
32
32
32
32
32
32
32
32
32
32
100
100
100
100
100
100
100
100
100
100
100
100
100
A3
A4
A5
A7
A9
AB
B5
B6
B9
BB
C5
C7
GX
GT
Stratix V Device Datasheet
December 2015 Altera Corporation
Configuration Specification
Page 55
Table 48. Minimum Configuration Time Estimation for Stratix V Devices
Active Serial (1)
Fast Passive Parallel (2)
Member
Variant
Min Config
Time (s)
Min Config
Time (s)
Code
Width
DCLK (MHz)
Width
DCLK (MHz)
D3
D4
4
4
4
4
4
4
4
4
100
100
100
100
100
100
100
100
0.344
0.534
0.344
0.534
0.741
0.741
0.857
0.857
32
32
32
32
32
32
32
32
100
100
100
100
100
100
100
100
0.043
0.067
0.043
0.067
0.093
0.093
0.107
0.107
GS
D5
D6
D8
E9
EB
E
Notes to Table 48:
(1) DCLK frequency of 100 MHz using external CLKUSR.
(2) Max FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Fast Passive Parallel Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Stratix V devices.
DCLK-to-DATA[] Ratio for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[]ratio when you enable the
design security, decompression, or both features. Table 49 lists the DCLK-to-DATA[]ratio
for each combination.
(1)
Table 49. DCLK-to-DATA[] Ratio
Configuration
(Part 1 of 2)
DCLK-to-DATA[]
Ratio
Decompression
Design Security
Disabled
Scheme
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
1
1
2
2
1
2
4
4
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
FPP ×8
FPP ×16
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 56
Configuration Specification
(1)
Table 49. DCLK-to-DATA[] Ratio
Configuration
(Part 2 of 2)
DCLK-to-DATA[]
Ratio
Decompression
Design Security
Disabled
Scheme
Disabled
1
4
8
8
Disabled
Enabled
Enabled
Enabled
Disabled
Enabled
FPP ×32
Note to Table 49:
(1) Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the data rate in bytes
per second (Bps), or words per second (Wps). For example, in FPP ×16 when the DCLK-to-DATA[]ratio is 2, the
DCLKfrequency must be 2 times the data rate in Wps. Stratix V devices use the additional clock cycles to decrypt
and decompress the configuration data.
1
If the DCLK-to-DATA[]ratio is greater than 1, at the end of configuration, you can only
stop the DCLK(DCLK-to-DATA[]ratio – 1) clock cycles after the last data is latched into
the Stratix V device.
Figure 10 shows the configuration interface connections between the Stratix V device
and a MAX II or MAX V device for single device configuration.
Figure 10. Single Device FPP Configuration Using an External Host
Memory
V
(1) V
(1)
CCPGM
CCPGM
ADDR DATA[7..0]
Stratix V Device
(3)
MSEL[4..0]
CONF_DONE
nSTATUS
External Host
nCE
nCEO
N.C. (2)
(MAX II Device,
MAX V Device, or
Microprocessor)
GND
DATA[31..0]
(4)
nCONFIG
DCLK
Notes to Figure 10:
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high
enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up
all configuration system I/Os with VCCPGM
.
(2) You can leave the nCEOpin unconnected or use it as a user I/O pin when it does not feed another device's nCEpin.
(3) The MSELpin settings vary for different data width, configuration voltage standards, and POR delay. To connect MSEL
refer to the MSEL Pin Settings section of the “Configuration, Design Security, and Remote System Upgrades in Stratix
V Devices” chapter.
,
(4) If you use FPP ×8, use DATA[7..0]. If you use FPP ×16, use DATA[15..0]
.
Stratix V Device Datasheet
December 2015 Altera Corporation
Configuration Specification
Page 57
FPP Configuration Timing when DCLK-to-DATA [] = 1
Figure 11 shows the timing waveform for FPP configuration when using a MAX II or
MAX V device as an external host. This waveform shows timing when the DCLK-to-
DATA[]ratio is 1.
(1), (2)
Figure 11. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
tSTATUS
(7)
tCF2ST0
tCLK
CONF_DONE (4)
t
CH tCL
tCF2CD
tST2CK
(5)
DCLK
tDH
Word 0 Word 1 Word 2 Word 3
DATA[31..0](6)
Word n-2 Word n-1
User Mode
User Mode
tDSU
High-Z
User I/O
(8)
INIT_DONE
tCD2UM
Notes to Figure 11:
(1) Use this timing waveform when the DCLK-to-DATA[]ratio is 1.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONEare at logic-high levels. When
nCONFIGis pulled low, a reconfiguration cycle begins.
(3) After power-up, the Stratix V device holds nSTATUSlow for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONEis low.
(5) Do not leave DCLKfloating after configuration. DCLKis ignored after configuration is complete. It can toggle high or low if required.
(6) For FPP ×16, use DATA[15..0]. For FPP ×8, use DATA[7..0]. DATA[31..0]are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(7) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONEis released high when the Stratix V
device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization
and enter user mode.
(8) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 58
Configuration Specification
Table 50 lists the timing parameters for Stratix V devices for FPP configuration when
the DCLK-to-DATA[]ratio is 1.
Table 50. FPP Timing Parameters for Stratix V Devices (1)
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
Minimum
Maximum
600
600
—
1,506 (2)
1,506 (3)
—
Units
ns
—
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
—
ns
2
s
s
s
s
s
ns
tSTATUS
tCF2ST1
nSTATUSlow pulse width
268
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
—
(6)
tCF2CK
1,506
(6)
tST2CK
2
—
tDSU
tDH
tCH
5.5
0
—
—
ns
0.45 1/fMAX
0.45 1/fMAX
1/fMAX
—
s
tCL
DCLKlow time
—
s
tCLK
DCLK period
—
s
DCLKfrequency (FPP 8/16)
DCLKfrequency (FPP 32)
—
125
100
437
MHz
MHz
s
fMAX
—
(4)
tCD2UM
tCD2CU
CONF_DONEhigh to user mode
175
4 × maximum
DCLKperiod
CONF_DONEhigh to CLKUSRenabled
—
—
—
—
tCD2CU
+
tCD2UMC CONF_DONEhigh to user mode with CLKUSRoption on
(17,408 CLKUSR
period) (5)
Notes to Table 50:
(1) Use these timing parameters when the decompression and design security features are disabled.
(2) This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(3) This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(5) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
Initialization section of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
(6) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
FPP Configuration Timing when DCLK-to-DATA [] > 1
Figure 12 shows the timing waveform for FPP configuration when using a MAX II
device, MAX V device, or microprocessor as an external host. This waveform shows
timing when the DCLK-to-DATA[]ratio is more than 1.
Stratix V Device Datasheet
December 2015 Altera Corporation
Configuration Specification
Page 59
(1), (2)
Figure 12. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
tSTATUS
tCF2ST0
CONF_DONE (4)
t
CL
tCF2CD
(8)
tST2CK
t
CH
DCLK (6)
DATA[31..0] (8)
User I/O
(7)
(5)
1
2
1
1
2
r
1
2
r
r
t
CLK
Word 0
Word 1
Word (n-1)
User Mod
Word 3
t
t
tDSU
DH
DH
User Mod
High-Z
(9)
INIT_DONE
tCD2UM
Notes to Figure 12:
(1) Use this timing waveform and parameters when the DCLK-to-DATA[]ratio is >1. To find out the DCLK-to-DATA[]ratio for your system, refer
to Table 49 on page 55.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONEare at logic high levels.
When nCONFIGis pulled low, a reconfiguration cycle begins.
(3) After power-up, the Stratix V device holds nSTATUSlow for the time as specified by the POR delay.
(4) After power-up, before and during configuration, CONF_DONEis low.
(5) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(6) “r” denotes the DCLK-to-DATA[]ratio. For the DCLK-to-DATA[]ratio based on the decompression and the design security feature enable
settings, refer to Table 49 on page 55.
(7) If needed, pause DCLKby holding it low. When DCLKrestarts, the external host must provide data on the DATA[31..0]pins prior to sending
the first DCLKrising edge.
(8) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONEis released high after the Stratix V
device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin
initialization and enter user mode.
(9) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 60
Configuration Specification
Table 51 lists the timing parameters for Stratix V devices for FPP configuration when
the DCLK-to-DATA[]ratio is more than 1.
Table 51. FPP Timing Parameters for Stratix V Devices When the DCLK-to-DATA[] Ratio is >1 (1)
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
Minimum
Maximum
600
600
—
1,506 (2)
1,506 (2)
—
Units
ns
ns
s
s
s
s
s
ns
s
—
—
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
nSTATUSlow pulse width
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
2
tSTATUS
tCF2ST1
268
—
(5)
tCF2CK
1,506
2
(5)
tST2CK
—
tDSU
tDH
tCH
5.5
—
(5)
N–1/fDCLK
—
0.45 1/fMAX
—
s
tCL
DCLKlow time
0.45 1/fMAX
—
s
tCLK
DCLKperiod
1/fMAX
—
—
s
DCLKfrequency (FPP 8/16)
DCLKfrequency (FPP 32)
Input rise time
125
100
40
MHz
MHz
ns
ns
s
fMAX
—
tR
—
tF
Input fall time
—
40
(3)
tCD2UM
CONF_DONEhigh to user mode
175
437
4 × maximum
DCLKperiod
tCD2CU
CONF_DONEhigh to CLKUSRenabled
—
—
tCD2CU
+
tCD2UMC CONF_DONEhigh to user mode with CLKUSRoption on
(17,408 CLKUSR
—
—
period) (4)
Notes to Table 51:
(1) Use these timing parameters when you use the decompression and design security features.
(2) You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(3) The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
(4) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
Initialization section of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
(5) N is the DCLK-to-DATAratio and fDCLK is the DCLKfrequency the system is operating.
(6) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
Stratix V Device Datasheet
December 2015 Altera Corporation
Configuration Specification
Page 61
Active Serial Configuration Timing
Table 52 lists the DCLKfrequency specification in the AS configuration scheme.
Table 52. DCLK Frequency Specification in the AS Configuration Scheme (1), (2)
Minimum
Typical
7.9
Maximum
12.5
Unit
MHz
MHz
MHz
MHz
5.3
10.6
15.7
31.4
62.9
25.0
21.3
50.0
42.6
100.0
Notes to Table 52:
(1) This applies to the DCLKfrequency specification when using the internal oscillator as the configuration clock
source.
(2) The AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.
Figure 13 shows the single-device configuration setup for an AS ×1 mode.
Figure 13. AS Configuration Timing
t
CF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
t
CO
t
DH
Read Address
AS_DATA0/ASDO
AS_DATA1 (1)
t
SU
bit (n − 2) bit (n − 1)
bit 1
bit 0
t
(2)
CD2UM
INIT_DONE (3)
User I/O
User Mode
Notes to Figure 13:
(1) If you are using AS ×4 mode, this signal represents the AS_DATA[3..0]and EPCQ sends in 4-bits of data for each DCLKcycle.
(2) The initialization clock can be from internal oscillator or CLKUSRpin.
(3) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
Table 53 lists the timing parameters for AS 1 and AS 4 configurations in Stratix V
devices.
Table 53. AS Timing Parameters for AS 1 and AS 4 Configurations in Stratix V Devices (1), (2) (Part 1 of 2)
Symbol
tCO
Parameter
Minimum
Maximum
Units
ns
DCLKfalling edge to AS_DATA0/ASDOoutput
Data setup time before falling edge on DCLK
Data hold time after falling edge on DCLK
—
1.5
0
2
tSU
tH
—
—
ns
ns
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 62
Configuration Specification
Table 53. AS Timing Parameters for AS 1 and AS 4 Configurations in Stratix V Devices (1), (2) (Part 2 of 2)
Symbol
Parameter
Minimum
Maximum
Units
(3)
tCD2UM
CONF_DONEhigh to user mode
175
437
s
4 × maximum DCLK
tCD2CU
CONF_DONEhigh to CLKUSRenabled
—
—
—
—
period
tCD2CU + (17,408
CLKUSRperiod)
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
Notes to Table 53:
(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(2) tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in Table 54 on page 63.
(3) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to the
Initialization section of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
Passive Serial Configuration Timing
Figure 14 shows the timing waveform for a passive serial (PS) configuration when
using a MAX II device, MAX V device, or microprocessor as an external host.
(1)
Figure 14. PS Configuration Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
(6)
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
(5)
DCLK
tDH
Bit 2 Bit 3
Bit 0 Bit 1
DATA0
Bit (n-1)
tDSU
High-Z
User I/O
User Mode
INIT_DONE (7)
tCD2UM
Notes to Figure 14:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONEare at logic high levels. When
nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power-up, the Stratix V device holds nSTATUSlow for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA0is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins
Option.
(6) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONEis released high after the Stratix V
device receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin
initialization and enter user mode.
(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONEgoes low.
Stratix V Device Datasheet
December 2015 Altera Corporation
Configuration Specification
Page 63
Table 54 lists the PS configuration timing parameters for Stratix V devices.
Table 54. PS Timing Parameters for Stratix V Devices
Symbol
tCF2CD
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
600
600
—
1,506 (1)
1,506 (2)
—
Units
ns
ns
s
s
s
s
s
ns
ns
s
—
tCF2ST0
tCFG
tSTATUS
tCF2ST1
—
2
nSTATUSlow pulse width
268
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time after rising edge on DCLK
DCLKhigh time
—
(5)
tCF2CK
1,506
(5)
tST2CK
2
—
tDSU
tDH
5.5
—
0
0.45 1/fMAX
0.45 1/fMAX
1/fMAX
—
tCH
—
tCL
DCLKlow time
—
s
tCLK
fMAX
tCD2UM
DCLKperiod
—
s
DCLKfrequency
—
125
437
MHz
s
(3)
CONF_DONEhigh to user mode
175
4 × maximum
DCLKperiod
tCD2CU
CONF_DONEhigh to CLKUSRenabled
—
—
tCD2CU
(17,408 CLKUSR
+
tCD2UMC
CONF_DONEhigh to user mode with CLKUSRoption on
—
—
(4)
period)
Notes to Table 54:
(1) This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
(2) This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
(3) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(4) To enable the CLKUSRpin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
“Initialization” section.
(5) If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
Initialization
Table 55 lists the initialization clock source option, the applicable configuration
schemes, and the maximum frequency.
Table 55. Initialization Clock Source Option and the Maximum Frequency
Initialization Clock
Source
Maximum
Frequency
Minimum Number of Clock
Configuration Schemes
(1)
Cycles
Internal Oscillator
CLKUSR
AS, PS, FPP
12.5 MHz
125 MHz
125 MHz
(2)
AS, PS, FPP
17,408
DCLK
PS, FPP
Notes to Table 55:
(1) The minimum number of clock cycles required for device initialization.
(2) To enable CLKUSRas the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General panel of the Device and Pin Options dialog box.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 64
I/O Timing
Remote System Upgrades
Table 56 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 56. Remote System Upgrade Circuitry Timing Specifications
Parameter
Minimum
250
Maximum
Unit
ns
(1)
tRU_nCONFIG
—
—
(2)
tRU_nRSTIMER
250
ns
Notes to Table 56:
(1) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the Remote System Upgrade State Machine section
of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
(2) This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the User Watchdog Timer section of the
“Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
User Watchdog Internal Circuitry Timing Specification
Table 57 lists the operating range of the 12.5-MHz internal oscillator.
Table 57. 12.5-MHz Internal Oscillator Specifications
Minimum
Typical
Maximum
Units
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
f
You can download the Excel-based I/O Timing spreadsheet from the Stratix V
Devices Documentation web page.
Programmable IOE Delay
Table 58 lists the Stratix V IOE programmable delay settings.
Table 58. IOE Programmable Delay for Stratix V Devices (Part 1 of 2)
Fast Model
Slow Model
C4 I2
Min
Parameter Available
Offset
(1)
I3,
I3YY
Settings
(2)
Industrial Commercial
C1
C2
C3
I4
Unit
D1
D2
64
32
0
0
0.464
0.230
0.493
0.244
0.838 0.838 0.924 1.011 0.844 0.921 1.006 ns
0.415 0.415 0.459 0.503 0.417 0.456 0.500 ns
Stratix V Device Datasheet
December 2015 Altera Corporation
Glossary
Page 65
Table 58. IOE Programmable Delay for Stratix V Devices (Part 2 of 2)
Fast Model
Slow Model
C4 I2
Min
Parameter Available
Offset
(1)
I3,
I3YY
Settings
(2)
Industrial Commercial
C1
C2
C3
I4
Unit
D3
8
0
0
0
0
1.587
0.464
0.464
0.229
1.699
0.492
0.493
0.244
2.793 2.793 2.992 3.192 2.811 3.047 3.257 ns
0.838 0.838 0.924 1.011 0.843 0.920 1.006 ns
0.838 0.838 0.924 1.011 0.844 0.921 1.006 ns
0.415 0.415 0.458 0.503 0.418 0.456 0.499 ns
D4
64
64
32
D5
D6
Notes to Table 58:
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D5, and D6 in the Assignment Name column of Assignment Editor.
(2) Minimum offset does not include the intrinsic delay.
Programmable Output Buffer Delay
Table 59 lists the delay chain settings that control the rising and falling edge delays of
the output buffer. The default delay is 0 ps.
Table 59. Programmable Output Buffer Delay for Stratix V Devices (1)
Symbol
Parameter
Typical
Unit
ps
0 (default)
25
50
75
ps
Rising and/or falling edge
delay
DOUTBUF
ps
ps
Note to Table 59:
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
Glossary
Table 60 lists the glossary for this chapter.
Table 60. Glossary (Part 1 of 4)
Letter
Subject
Definitions
A
B
C
D
E
—
—
—
—
—
—
fHSCLK
Left and right PLL input clock frequency.
High-speed I/O block—Maximum and minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDR
F
High-speed I/O block—Maximum and minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
fHSDRDPA
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 66
Glossary
Table 60. Glossary (Part 2 of 4)
Letter
Subject
Definitions
G
H
I
—
—
J
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
TMS
TDI
tJCP
J
JTAG Timing
Specifications
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
K
L
M
N
O
—
—
(1)
Diagram of PLL Specifications
CLKOUT Pins
fOUT_EXT
Switchover
4
CLK
fIN
fINPFD
N
GCLK
RCLK
Counters
C0..C17
fVCO
VCO
fOUT
PFD
CP
LF
Core Clock
PLL
Specifications
P
Delta Sigma
Modulator
Key
External Feedback
Reconfigurable in User Mode
Note:
(1) Core Clockcan only be fed by dedicated clock input pins or PLL outputs.
Q
R
—
—
RL
Receiver differential input discrete resistor (external to the Stratix V device).
Stratix V Device Datasheet
December 2015 Altera Corporation
Glossary
Page 67
Table 60. Glossary (Part 3 of 4)
Letter
Subject
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
SW (sampling
window)
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
The JEDEC standard for SSTL and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing:
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
VCCIO
referenced I/O
standard
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
VOL
VSS
tC
High-speed receiver and transmitter input and output clock period.
The timing difference between the fastest and slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
TCCS (channel-
to-channel-skew)
High-speed I/O block—Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and the data sampling window.
T
(TUI = 1/(receiver input clock frequency multiplication factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on the PLL clock input.
Period jitter on the general purpose I/O driven by a PLL.
Period jitter on the dedicated clock output driven by a PLL.
Signal low-to-high transition time (20-80%)
—
tINCCJ
tOUTPJ_IO
tOUTPJ_DC
tRISE
U
—
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 68
Document Revision History
Table 60. Glossary (Part 4 of 4)
Letter
Subject
VCM(DC)
Definitions
DC common mode input voltage.
VICM
Input common mode voltage—The common mode of the differential signal at the receiver.
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VDIF(AC)
VDIF(DC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH
VIH(AC)
VIH(DC)
High-level AC input voltage
High-level DC input voltage
V
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL
VIL(AC)
VIL(DC)
Low-level AC input voltage
Low-level DC input voltage
Output common mode voltage—The common mode of the differential signal at the
transmitter.
VOCM
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
VX
Differential input voltage
Input differential cross point voltage
Output differential cross point voltage
High-speed I/O block—clock boost factor
VOX
W
W
X
Y
Z
—
—
Document Revision History
Table 61 lists the revision history for this chapter.
Table 61. Document Revision History (Part 1 of 4)
Date
December
Version
Changes
3.6
■ Added a footnote to the “High-Speed I/O Specifications for Stratix V Devices” table.
■ Changed the transmitter, receiver, and ATX PLL data rate specifications in the
“Transceiver Specifications for Stratix V GX and GS Devices” table.
December 2015
3.5
■ Changed the configuration .rbf sizes in the “Uncompressed .rbf Sizes for Stratix V
Devices” table.
Stratix V Device Datasheet
December 2015 Altera Corporation
Document Revision History
Page 69
Table 61. Document Revision History (Part 2 of 4)
Date
Version
Changes
■ Changed the data rate specification for transceiver speed grade 3 in the following tables:
■ “Transceiver Specifications for Stratix V GX and GS Devices”
■ “Stratix V Standard PCS Approximate Maximum Date Rate”
■ “Stratix V 10G PCS Approximate Maximum Data Rate”
■ Changed the conditions for reference clock rise and fall time, and added a note to the
“Transceiver Specifications for Stratix V GX and GS Devices” table.
July 2015
3.4
■ Added a note to the “Minimum differential eye opening at receiver serial input pins”
specification in the “Transceiver Specifications for Stratix V GX and GS Devices” table.
■ Changed the tCO maximum value in the “AS Timing Parameters for AS ´1 and AS ´4
Configurations in Stratix V Devices” table.
■ Removed the CDR ppm tolerance specification from the “Transceiver Specifications for
Stratix V GX and GS Devices” table.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 70
Document Revision History
Table 61. Document Revision History (Part 3 of 4)
Date
Version
Changes
■ Added the I3YY speed grade and changed the data rates for the GX channel in Table 1.
■ Added the I3YY speed grade to the VCC description in Table 6.
■ Added the I3YY speed grade to VCCHIP_L, VCCHIP_R, VCCHSSI_L, and VCCHSSI_R descriptions in
Table 7.
■ Added 240-to Table 11.
■ Changed CDR PPM tolerance in Table 23.
■ Added additional max data rate for fPLL in Table 23.
■ Added the I3YY speed grade and changed the data rates for transceiver speed grade 3 in
Table 25.
■ Added the I3YY speed grade and changed the data rates for transceiver speed grade 3 in
Table 26.
■ Changed CDR PPM tolerance in Table 28.
■ Added additional max data rate for fPLL in Table 28.
■ Changed the mode descriptions for MLAB and M20K in Table 33.
■ Changed the Max value of fHSCLK_OUT for the C2, C2L, I2, I2L speed grades in Table 36.
■ Changed the frequency ranges for C1 and C2 in Table 39.
■ Changed the .rbf file sizes for 5SGSD6 and 5SGSD8 in Table 47.
■ Added note about nSTATUSto Table 50, Table 51, Table 54.
■ Changed the available settings in Table 58.
■ Changed the note in “Periphery Performance”.
■ Updated the “I/O Standard Specifications” section.
■ Updated the “Raw Binary File Size” section.
■ Updated the receiver voltage input range in Table 22.
■ Updated the max frequency for the LVDS clock network in Table 36.
■ Updated the DCLKnote to Figure 11.
November 2014
3.3
■ Updated Table 23 VOCM (DC Coupled) condition.
■ Updated Table 6 and Table 7.
■ Added the DCLKspecification to Table 55.
■ Updated the notes for Table 47.
■ Updated the list of parameters for Table 56.
■ Updated Table 28
November 2013
November 2013
November 2013
October 2013
3.2
3.1
3.0
2.9
■ Updated Table 33
■ Updated Table 23 and Table 28
■ Updated the “Transceiver Characterization” section
■ Updated Table 3, Table 12, Table 14, Table 19, Table 20, Table 23, Table 24, Table 28,
Table 30, Table 31, Table 32, Table 33, Table 36, Table 39, Table 40, Table 41, Table 42,
Table 47, Table 53, Table 58, and Table 59
October 2013
2.8
■ Added Figure 1 and Figure 3
■ Added the “Transceiver Characterization” section
■ Removed all “Preliminary” designations.
Stratix V Device Datasheet
December 2015 Altera Corporation
Document Revision History
Page 71
Table 61. Document Revision History (Part 4 of 4)
Date
Version
Changes
■ Updated Table 2, Table 6, Table 7, Table 20, Table 23, Table 27, Table 47, Table 60
■ Added Table 24, Table 48
May 2013
2.7
■ Updated Figure 9, Figure 10, Figure 11, Figure 12
■ Updated Table 7, Table 9, Table 20, Table 23, Table 27, Table 30, Table 31, Table 35,
Table 46
February 2013
2.6
2.5
■ Updated “Maximum Allowed Overshoot and Undershoot Voltage”
■ Updated Table 3, Table 6, Table 7, Table 8, Table 23, Table 24, Table 25, Table 27,
Table 30, Table 32, Table 35
■ Added Table 33
■ Added “Fast Passive Parallel Configuration Timing”
■ Added “Active Serial Configuration Timing”
■ Added “Passive Serial Configuration Timing”
■ Added “Remote System Upgrades”
■ Added “User Watchdog Internal Circuitry Timing Specification”
■ Added “Initialization”
December 2012
■ Added “Raw Binary File Size”
■ Added Figure 1, Figure 2, and Figure 3.
■ Updated Table 1, Table 2, Table 3, Table 6, Table 11, Table 22, Table 23, Table 27,Table 29,
Table 30, Table 31, Table 32, Table 35, Table 38, Table 39, Table 40, Table 41, Table 43,
Table 56, and Table 59.
June 2012
2.4
■ Various edits throughout to fix bugs.
■ Changed title of document to Stratix V Device Datasheet.
■ Removed document from the Stratix V handbook and made it a separate document.
■ Updated Table 1–22, Table 1–29, Table 1–31, and Table 1–31.
■ Added Table 2–31.
February 2012
December 2011
2.3
2.2
■ Updated Table 2–28 and Table 2–34.
■ Added Table 2–2 and Table 2–21 and updated Table 2–5 with information about
Stratix V GT devices.
November 2011
May 2011
2.1
2.0
■ Updated Table 2–11, Table 2–13, Table 2–20, and Table 2–25.
■ Various edits throughout to fix SPRs.
■ Updated Table 2–4, Table 2–18, Table 2–19, Table 2–21, Table 2–22, Table 2–23, and
Table 2–24.
■ Updated the “DQ Logic Block and Memory Output Clock Jitter Specifications” title.
■ Chapter moved to Volume 1.
■ Minor text edits.
■ Updated Table 1–2, Table 1–4, Table 1–19, and Table 1–23.
■ Converted chapter to the new template.
■ Minor text edits.
December 2010
July 2010
1.1
1.0
Initial release.
December 2015 Altera Corporation
Stratix V Device Datasheet
Page 72
Document Revision History
Stratix V Device Datasheet
December 2015 Altera Corporation
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