80C186XL_技术文档

80C186XL/80C188XL

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

Y

Low Power, Fully Static Versions of

80C186/80C188

Completely Object Code Compatible

with Existing 8086/8088 Software and

Has 10 Additional Instructions over

8086/8088

Operation Modes:

Ð Enhanced Mode

Y

Ð DRAM Refresh Control Unit

Ð Power-Save Mode

Ð Direct Interface to 80C187

(80C186XL Only)

Ð Compatible Mode

Speed Versions Available

Ð 25 MHz (80C186XL25/80C188XL25)

Ð 20 MHz (80C186XL20/80C188XL20)

Ð 12 MHz (80C186XL12/80C188XL12)

Y

Direct Addressing Capability to

1 MByte Memory and 64 Kbyte I/O

Ð NMOS 80186/80188 Pin-for-Pin

Replacement for Non-Numerics

Applications

Available in 68-Pin:

Ð Plastic Leaded Chip Carrier (PLCC)

Ð Ceramic Pin Grid Array (PGA)

Ð Ceramic Leadless Chip Carrier

(JEDEC A Package)

Y

Integrated Feature Set

Ð Static, Modular CPU

Ð Clock Generator

Ð 2 Independent DMA Channels

Ð Programmable Interrupt Controller

Ð 3 Programmable 16-Bit Timers

Ð Dynamic RAM Refresh Control Unit

Ð Programmable Memory and

Peripheral Chip Select Logic

Ð Programmable Wait State Generator

Ð Local Bus Controller

Y

Available in 80-Pin:

Ð Quad Flat Pack (EIAJ)

Ð Shrink Quad Flat Pack (SGFP)

Available in Extended Temperature

b

a

Range ( 40 C to 85 C)

§

Ð Power-Save Mode

Ð System-Level Testing Support (High

Impedance Test Mode)

The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor. It offers higher speed

and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com-

patibility. Packaging and pinout are also identical.

272431-1

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

October 1995

COPYRIGHT INTEL CORPORATION, 1995

Order Number: 272431-004

©

1

80C186XL/80C188XL

16-Bit High-Integration Embedded Processors

CONTENTS

PAGE

CONTENTS

PAGE

INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

Major Cycle Timings (Read Cycle) ÀÀÀÀÀÀÀÀÀ 24

Major Cycle Timings (Write Cycle) ÀÀÀÀÀÀÀÀÀ 26

80C186XL CORE ARCHITECTURE ÀÀÀÀÀÀÀÀ 4

80C186XL Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

Major Cycle Timings (Interrupt

Acknowledge Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27

Software Halt Cycle Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

Clock Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

80C186XL PERIPHERAL

ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

Chip-Select/Ready Generation Logic ÀÀÀÀÀÀÀ 5

DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

Enhanced Mode Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

Queue-Status Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

DRAM Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Power-Save Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Ready, Peripheral and Queue Status

Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

Reset and Hold/HLDA Timings ÀÀÀÀÀÀÀÀÀÀÀÀ 31

AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

AC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

EXPLANATION OF THE AC

SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39

Interface for 80C187 Math Coprocessor

(80C186XL Only) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

80C186XL/80C188XL EXPRESS ÀÀÀÀÀÀÀÀÀ 41

ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

80C186XL/80C188XL EXECUTION

TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41

PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 42

REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48

ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48

PRODUCT IDENTIFICATION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 48

80C186XL/80C188XL Pinout

Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 22

Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

Power Supply Current ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

2

80C186XL/80C188XL

NOTE:

Pin names in parentheses applies to 80C188XL.

Figure 1. 80C186XL/80C188XL Block Diagram

3

80C186XL/80C188XL

(2a)

272431–3

272431–4

(2b)

Note 1:

XTAL Frequency

20 MHz

25 MHz

L1 Value

g

8.2 mH 20%

12.0 mH 20%

g

4.7 mH 20%

g

3.0 mH 20%

32 MHz

40 MHz

LC network is only required when using a third

overtone crystal.

Figure 2. Oscillator Configurations (see text)

The 80C186XL oscillator circuit is designed to be

INTRODUCTION

used either with a parallel resonant fundamental or

third-overtone mode crystal, depending upon the

frequency range of the application. This is used as

the time base for the 80C186XL.

Unless specifically noted, all references to the

80C186XL apply to the 80C188XL. References to

pins that differ between the 80C186XL and the

80C188XL are given in parentheses.

The output of the oscillator is not directly available

outside the 80C186XL. The recommended crystal

configuration is shown in Figure 2b. When used in

third-overtone mode, the tank circuit is recommend-

ed for stable operation. Alternately, the oscillator

may be driven from an external source as shown in

Figure 2a.

The following Functional Description describes the

base architecture of the 80C186XL. The 80C186XL

is a very high integration 16-bit microprocessor. It

combines 15–20 of the most common microproces-

sor system components onto one chip. The

80C186XL is object code compatible with the

8086/8088 microprocessors and adds 10 new in-

struction types to the 8086/8088 instruction set.

The crystal or clock frequency chosen must be twice

the required processor operating frequency due to

the internal divide by two counter. This counter is

used to drive all internal phase clocks and the exter-

nal CLKOUT signal. CLKOUT is a 50% duty cycle

processor clock and can be used to drive other sys-

tem components. All AC Timings are referenced to

CLKOUT.

The 80C186XL has two major modes of operation,

Compatible and Enhanced. In Compatible Mode the

80C186XL is completely compatible with NMOS

80186, with the exception of 8087 support. The En-

hanced mode adds three new features to the system

design. These are Power-Save control, Dynamic

RAM refresh, and an asynchronous Numerics Co-

processor interface (80C186XL only).

Intel recommends the following values for crystal se-

lection parameters.

Temperature Range:

Application Specific

80C186XL CORE ARCHITECTURE

80C186XL Clock Generator

ESR (Equivalent Series Resistance):

60X max

C

(Shunt Capacitance of Crystal):

(Load Capacitance):

7.0 pF max

0

1

g

20 pF 2 pF

The 80C186XL provides an on-chip clock generator

for both internal and external clock generation. The

clock generator features a crystal oscillator, a divide-

by-two counter, synchronous and asynchronous

ready inputs, and reset circuitry.

Drive Level:

2 mW max

4

80C186XL/80C188XL

spond to bus cycles. An offset map of the 256-byte

control register block is shown in Figure 3.

Bus Interface Unit

The 80C186XL provides a local bus controller to

generate the local bus control signals. In addition, it

employs a HOLD/HLDA protocol for relinquishing

the local bus to other bus masters. It also provides

outputs that can be used to enable external buffers

and to direct the flow of data on and off the local

bus.

Chip-Select/Ready Generation Logic

The 80C186XL contains logic which provides

programmable chip-select generation for both mem-

ories and peripherals. In addition, it can be

programmed to provide READY (or WAIT state) gen-

eration. It can also provide latched address bits A1

and A2. The chip-select lines are active for all mem-

ory and I/O cycles in their programmed areas,

whether they be generated by the CPU or by the

integrated DMA unit.

The bus controller is responsible for generating 20

bits of address, read and write strobes, bus cycle

status information and data (for write operations) in-

formation. It is also responsible for reading data

from the local bus during a read operation. Synchro-

nous and asynchronous ready input pins are provid-

ed to extend a bus cycle beyond the minimum four

states (clocks).

The 80C186XL provides 6 memory chip select out-

puts for 3 address areas; upper memory, lower

memory, and midrange memory. One each is provid-

ed for upper memory and lower memory, while four

are provided for midrange memory.

The 80C186XL bus controller also generates two

control signals (DEN and DT/R) when interfacing to

external transceiver chips. This capability allows the

addition of transceivers for simple buffering of the

multiplexed address/data bus.

OFFSET

Relocation Register

FEH

During RESET the local bus controller will perform

the following action:

DAH

D0H

DMA Descriptors Channel 1

Drive DEN, RD and WR HIGH for one clock cy-

cle, then float them.

#

Drive S0–S2 to the inactive state (all HIGH) and

then float.

#

CAH

C0H

DMA Descriptors Channel 0

Chip-Select Control Registers

Drive LOCK HIGH and then float.

#

Float AD0–15 (AD0–8), A16–19 (A9–A19), BHE

(RFSH), DT/R.

A8H

A0H

Drive ALE LOW

#

Drive HLDA LOW.

#

66H

RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/

ERROR and TEST/BUSY pins have internal pullup

devices which are active while RES is applied. Ex-

cessive loading or grounding certain of these pins

causes the 80C186XL to enter an alternative mode

of operation:

Time 2 Control Registers

Time 1 Control Registers

Time 0 Control Registers

60H

5EH

58H

56H

50H

RD/QSMD low results in Queue Status Mode.

#

UCS and LCS low results in ONCE Mode.

#

3EH

20H

TEST/BUSY low (and high later) results in En-

hanced Mode.

#

Interrupt Controller Registers

Figure 3. Internal Register Map

80C186XL PERIPHERAL

ARCHITECTURE

The 80C186XL provides a chip select, called UCS,

for the top of memory. The top of memory is usually

used as the system memory because after reset the

80C186XL begins executing at memory location

FFFF0H.

All the 80C186XL integrated peripherals are con-

trolled by 16-bit registers contained within an inter-

nal 256-byte control block. The control block may be

mapped into either memory or I/O space. Internal

logic will recognize control block addresses and re-

5

80C186XL/80C188XL

The 80C186XL provides a chip select for low memo-

ry called LCS. The bottom of memory contains the

interrupt vector table, starting at location 00000H.

mum of 8 clocks), one cycle to fetch data and the

other to store data.

The 80C186XL provides four MCS lines which are

active within a user-locatable memory block. This

block can be located within the 80C186XL 1 Mbyte

memory address space exclusive of the areas de-

fined by UCS and LCS. Both the base address and

size of this memory block are programmable.

Timer/Counter Unit

The 80C186XL provides three internal 16-bit pro-

grammable timers. Two of these are highly flexible

and are connected to four external pins (2 per timer).

They can be used to count external events, time ex-

ternal events, generate nonrepetitive waveforms,

etc. The third timer is not connected to any external

pins, and is useful for real-time coding and time de-

lay applications. In addition, the third timer can be

used as a prescaler to the other two, or as a DMA

request source.

The 80C186XL can generate chip selects for up to

seven peripheral devices. These chip selects are ac-

tive for seven contiguous blocks of 128 bytes above

a programmable base address. The base address

may be located in either memory or I/O space.

The 80C186XL can generate a READY signal inter-

nally for each of the memory or peripheral CS lines.

The number of WAIT states to be inserted for each

peripheral or memory is programmable to provide

0–3 wait states for all accesses to the area for

which the chip select is active. In addition, the

80C186XL may be programmed to either ignore ex-

ternal READY for each chip-select range individually

or to factor external READY with the integrated

ready generator.

Interrupt Control Unit

The 80C186XL can receive interrupts from a number

of sources, both internal and external. The

80C186XL has 5 external and 2 internal interrupt

sources (Timer/Couners and DMA). The internal in-

terrupt controller serves to merge these requests on

a priority basis, for individual service by the CPU.

Enhanced Mode Operation

Upon RESET, the Chip-Select/Ready Logic will per-

form the following actions:

In Compatible Mode the 80C186XL operates with all

the features of the NMOS 80186, with the exception

of 8087 support (i.e. no math coprocessing is possi-

ble in Compatible Mode). Queue-Status information

is still available for design purposes other than 8087

support.

All chip-select outputs will be driven HIGH.

#

Upon leaving RESET, the UCS line will be pro-

#

grammed to provide chip selects to a 1K block

with the accompanying READY control bits set at

011 to insert 3 wait states in conjunction with ex-

ternal READY (i.e., UMCS resets to FFFBH).

All the Enhanced Mode features are completely

masked when in Compatible Mode. A write to any of

the Enhanced Mode registers will have no effect,

while a read will not return any valid data.

No other chip select or READY control registers

#

have any predefined values after RESET. They

will not become active until the CPU accesses

their control registers.

In Enhanced Mode, the 80C186XL will operate with

Power-Save, DRAM refresh, and numerics coproc-

essor support (80C186XL only) in addition to all the

Compatible Mode features.

DMA Unit

The 80C186XL DMA controller provides two inde-

pendent high-speed DMA channels. Data transfers

can occur between memory and I/O spaces (e.g.,

Memory to I/O) or within the same space (e.g.,

Memory to Memory or I/O to I/O). Data can be

transferred either in bytes (8 bits) or in words (16

bits) to or from even or odd addresses.

If connected to a math coprocessor (80C186XL

only), this mode will be invoked automatically. With-

out an NPX, this mode can be entered by tying the

RESET output signal from the 80C186XL to the

TEST/BUSY input.

NOTE:

Only byte transfers are possible on the 80C188XL.

Queue-Status Mode

The queue-status mode is entered by strapping the

RD pin low. RD is sampled at RESET and if LOW,

the 80C186XL will reconfigure the ALE and WR pins

to be QS0 and QS1 respectively. This mode is avail-

able on the 80C186XL in both Compatible and En-

hanced Modes.

Each DMA channel maintains both a 20-bit source

and destination pointer which can be optionally in-

cremented or decremented after each data transfer

(by one or two depending on byte or word transfers).

Each data transfer consumes 2 bus cycles (a mini-

6

80C186XL/80C188XL

functions as in compatible mode, and may be pro-

grammed for activity with ready logic and wait states

accordingly. As in Compatible Mode, MCS2 will func-

tion for one-fourth a programmed block size.

DRAM Refresh Control Unit

The Refresh Control Unit (RCU) automatically gen-

erates DRAM refresh bus cycles. The RCU operates

only in Enhanced Mode. After a programmable peri-

od of time, the RCU generates a memory read re-

quest to the BIU. If the address generated during a

refresh bus cycle is within the range of a properly

programmed chip select, that chip select will be acti-

vated when the BIU executes the refresh bus cycle.

Table 1. MCS Assignments

Compatible

Enhanced Mode

Mode

MCS0

MCS1

MCS2

MCS3

PEREQ Processor Extension Request

ERROR NPX Error

MCS2 Mid-Range Chip Select

Power-Save Control

NPS

Numeric Processor Select

The 80C186XL, when in Enhanced Mode, can enter

a power saving state by internally dividing the proc-

essor clock frequency by a programmable factor.

This divided frequency is also available at the

CLKOUT pin.

ONCE Test Mode

To facilitate testing and inspection of devices when

fixed into a target system, the 80C186XL has a test

mode available which allows all pins to be placed in

a high-impedance state. ONCE stands for ‘‘ON Cir-

cuit Emulation’’. When placed in this mode, the

80C186XL will put all pins in the high-impedance

state until RESET.

All internal logic, including the Refresh Control Unit

and the timers, have their clocks slowed down by

the division factor. To maintain a real time count or a

fixed DRAM refresh rate, these peripherals must be

re-programmed when entering and leaving the pow-

er-save mode.

The ONCE mode is selected by tying the UCS and

the LCS LOW during RESET. These pins are sam-

pled on the low-to-high transition of the RES pin.

The UCS and the LCS pins have weak internal pull-

up resistors similar to the RD and TEST/BUSY pins

to guarantee ONCE Mode is not entered inadver-

tently during normal operation. LCS and UCS must

be held low at least one clock after RES goes high

to guarantee entrance into ONCE Mode.

Interface for 80C187 Math

Coprocessor (80C186XL Only)

In Enhanced Mode, three of the mid-range memory

chip selects are redefined according to Table 1 for

use with the 80C187. The fourth chip select, MCS2

7

80C186XL/80C188XL

proper operation. Stated simply, missing

a setup or hold on an asynchronous pin

will result in something minor (i.e., a tim-

er count will be missed) whereas miss-

ing a setup or hold on a synchronous pin

result in system failure (the system will

‘‘lock up’’).

PACKAGE INFORMATION

This section describes the pin functions, pinout and

thermal characteristics for the 80C186XL in the

Quad Flat Pack (QFP), Plastic Leaded Chip Carrier

(PLCC), Leadless Chip Carrier (LCC) and the Shrink

Quad Flat Pack (SQFP). For complete package

specifications and information, see the Intel Packag-

ing Outlines and Dimensions Guide (Order Number:

231369).

An input pin may also be edge or level

sensitive.

Column 4: Output States (for O and I/O types

only)

The state of an output or I/O pin is de-

pendent on the operating mode of the

device. There are four modes of opera-

tion that are different from normal active

mode: Bus Hold, Reset, Idle Mode, Pow-

erdown Mode. This column describes

the output pin state in each of these

modes.

Pin Descriptions

Each pin or logical set of pins is described in Table

3. There are four columns for each entry in the Pin

Description Table. The following sections describe

each column.

Column 1: Pin Name

In this column is a mnemonic that de-

scribes the pin function. Negation of the

signal name (i.e., RESIN) implies that

the signal is active low.

The legend for interpreting the information in the Pin

Descriptions is shown in Table 2.

Column 2: Pin Type

As an example, please refer to the table entry for

AD7:0. The ‘‘I/O’’ signifies that the pins are bidirec-

tional (i.e., have both an input and output function).

The ‘‘S’’ indicates that, as an input the signal must

be synchronized to CLKOUT for proper operation.

The ‘‘H(Z)’’ indicates that these pins will float while

the processor is in the Hold Acknowledge state.

R(Z) indicates that these pins will float while RESIN

is low.

A pin may be either power (P), ground

(G), input only (I), output only (O) or in-

put/output (I/O). Please note that some

pins have more than one function.

Column 3: Input Type (for I and I/O types only)

These are two different types of input

pins on the 80C186XL: asynchronous

and synchronous. Asynchronous pins

require that setup and hold times be met

only to guarantee recognition. Synchro-

nous input pins require that the setup

and hold times be met to guarantee

All pins float while the processor is in the ONCE

Mode (with the exception of X2).

8

80C186XL/80C188XL

Table 2. Pin Description Nomenclature

Symbol Description

a

P

Power Pin (apply

V

voltage)

CC

G

I

Ground (connect to V

Input only pin

Output only pin

)

SS

O

I/O

Input/Output pin

S(E)

S(L)

A(E)

A(L)

Synchronous, edge sensitive

Synchronous, level sensitive

Asynchronous, edge sensitive

Asynchronous, level sensitive

H(1)

H(0)

H(Z)

H(Q)

H(X)

Output driven to V during bus hold

CC

Output driven to V during bus hold

SS

Output floats during bus hold

Output remains active during bus hold

Output retains current state during bus hold

R(WH)

R(1)

R(0)

Output weakly held at V during reset

CC

Output driven to V during reset

CC

Output driven to V during reset

SS

Output floats during reset

R(Z)

R(Q)

R(X)

Output remains active during reset

Output retains current state during reset

9

80C186XL/80C188XL

Table 3. Pin Descriptions

Output

Input

Type

Pin Description

Name

Type

States

a

System Power: 5 volt power supply.

V

P

G

O

CC

SS

System Ground.

RESET

H(0)

R(1)

RESET Output indicates that the CPU is being reset, and can

be used as a system reset. It is active HIGH, synchronized

with the processor clock, and lasts an integer number of

clock periods corresponding to the length of the RES signal.

Reset goes inactive 2 clockout periods after RES goes

inactive. When tied to the TEST/BUSY pin, RESET forces

the processor into enhanced mode. RESET is not floated

during bus hold.

X1

X2

I

A(E)

Crystal Inputs X1 and X2 provide external connections for a

fundamental mode or third overtone parallel resonant crystal

for the internal oscillator. X1 can connect to an external

clock instead of a crystal. In this case, minimize the

capacitance on X2. The input or oscillator frequency is

internally divided by two to generate the clock signal

(CLKOUT).

O

H(Q)

R(Q)

CLKOUT

RES

O

I

H(Q)

R(Q)

Clock Output provides the system with a 50% duty cycle

waveform. All device pin timings are specified relative to

CLKOUT. CLKOUT is active during reset and bus hold.

A(L)

An active RES causes the processor to immediately

terminate its present activity, clear the internal logic, and

enter a dormant state. This signal may be asynchronous to

the clock. The processor begins fetching instructions

approximately 6(/2 clock cycles after RES is returned HIGH.

For proper initialization, V must be within specifications

CC

and the clock signal must be stable for more than 4 clocks

with RES held LOW. RES is internally synchronized. This

input is provided with a Schmitt-trigger to facilitate power-on

RES generation via an RC network.

TEST/BUSY

(TEST)

I

A(E)

The TEST pin is sampled during and after reset to determine

whether the processor is to enter Compatible or Enhanced

Mode. Enhanced Mode requires TEST to be HIGH on the

rising edge of RES and LOW four CLKOUT cycles later. Any

other combination will place the processor in Compatible

Mode. During power-up, active RES is required to configure

TEST/BUSY as an input. A weak internal pullup ensures a

HIGH state when the input is not externally driven.

TESTÐIn Compatible Mode this pin is configured to operate

as TEST. This pin is examined by the WAIT instruction. If the

TEST input is HIGH when WAIT execution begins, instruction

execution will suspend. TEST will be resampled every five

clocks until it goes LOW, at which time execution will

resume. If interrupts are enabled while the processor is

waiting for TEST, interrupts will be serviced.

BUSY (80C186XL Only)ÐIn Enhanced Mode, this pin is

configured to operate as BUSY. The BUSY input is used to

notify the 80C186XL of Math Coprocessor activity. Floating

point instructions executing in the 80C186XL sample the

BUSY pin to determine when the Math Coprocessor is ready

to accept a new command. BUSY is active HIGH.

NOTE:

Pin names in parentheses apply to the 80C188XL.

10

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Input

Output

States

Pin Description

Name

Type

TMR IN 0

TMR IN 1

I

A(L)

A(E)

Timer Inputs are used either as clock or control signals,

depending upon the programmed timer mode. These

inputs are active HIGH (or LOW-to-HIGH transitions are

counted) and internally synchronized. Timer Inputs must

be tied HIGH when not being used as clock or retrigger

inputs.

TMR OUT 0

TMR OUT 1

O

I

H(Q)

R(1)

Timer outputs are used to provide single pulse or

continuous waveform generation, depending upon the

timer mode selected. These outputs are not floated

during a bus hold.

DRQ0

DRQ1

A(L)

A(E)

DMA Request is asserted HIGH by an external device

when it is ready for DMA Channel 0 or 1 to perform a

transfer. These signals are level-triggered and internally

synchronized.

NMI

I

The Non-Maskable Interrupt input causes a Type 2

interrupt. An NMI transition from LOW to HIGH is

latched and synchronized internally, and initiates the

interrupt at the next instruction boundary. NMI must be

asserted for at least one CLKOUT period. The Non-

Maskable Interrupt cannot be avoided by programming.

INT0

INT1/SELECT

I

A(E)

A(L)

Maskable Interrupt Requests can be requested by

activating one of these pins. When configured as inputs,

these pins are active HIGH. Interrupt Requests are

synchronized internally. INT2 and INT3 may be

configured to provide active-LOW interrupt-

INT2/INTA0

INT3/INTA1/IRQ

I/O

A(E)

A(L)

H(1)

R(Z)

acknowledge output signals. All interrupt inputs may be

configured to be either edge- or level-triggered. To

ensure recognition, all interrupt requests must remain

active until the interrupt is acknowledged. When Slave

Mode is selected, the function of these pins changes

(see Interrupt Controller section of this data sheet).

A19/S6

A18/S5

A17/S4

A16/S3

(A8–A15)

O

H(Z)

R(Z)

Address Bus Outputs and Bus Cycle Status (3–6)

indicate the four most significant address bits during T .

These signals are active HIGH.

1

During T , T , T and T , the S6 pin is LOW to indicate

W

2

3

4

a CPU-initiated bus cycle or HIGH to indicate a DMA-

initiated or refresh bus cycle. During the same T-states,

S3, S4 and S5 are always LOW. On the 80C188XL,

A15–A8 provide valid address information for the entire

bus cycle.

AD0–AD15

(AD0–AD7)

I/O

S(L)

H(Z)

R(Z)

Address/Data Bus signals constitute the time

multiplexed memory or I/O address (T ) and data (T ,

1

T , T and T ) bus. The bus is active HIGH. For the

2

3

W

4

80C186XL, A is analogous to BHE for the lower byte of

0

the data bus, pins D through D . It is LOW during T

7

0

1

when a byte is to be transferred onto the lower portion

of the bus in memory or I/O operations.

NOTE:

Pin names in parentheses apply to the 80C188XL.

11

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Input Output

Pin Description

Name

Type Type States

BHE

(RFSH)

O

H(Z)

R(Z)

The BHE (Bus High Enable) signal is analogous to A0 in that it is

used to enable data on to the most significant half of the data bus,

pins D15–D8. BHE will be LOW during T when the upper byte is

1

transferred and will remain LOW through T and T . BHE does not

W

3

need to be latched. On the 80C188XL, RFSH is asserted LOW to

indicate a refresh bus cycle.

In Enhanced Mode, BHE (RFSH) will also be used to signify DRAM

refresh cycles. A refresh cycle is indicated by both BHE (RFSH) and

A0 being HIGH.

80C186XL BHE and A0 Encodings

BHE

A0

Function

Value Value

0

1

Word Transfer

Byte Transfer on upper half of data bus

(D15–D8)

1

0

1

Byte Transfer on lower half of data bus (D –D )

7 0

Refresh

ALE/QS0

WR/QS1

O

H(0)

R(0)

Address Latch Enable/Queue Status 0 is provided by the processor

to latch the address. ALE is active HIGH, with addresses guaranteed

valid on the trailing edge.

H(Z)

R(Z)

Write Strobe/Queue Status 1 indicates that the data on the bus is to

be written into a memory or an I/O device. It is active LOW. When

the processor is in Queue Status Mode, the ALE/QS0 and WR/QS1

pins provide information about processor/instruction queue

interaction.

QS1

QS0

Queue Operation

0

1

0

1

0

No queue operation

First opcode byte fetched from the queue

Subsequent byte fetched from the queue

Empty the queue

RD/QSMD

O

H(Z)

R(1)

Read Strobe is an active LOW signal which indicates that the

processor is performing a memory or I/O read cycle. It is guaranteed

not to go LOW before the A/D bus is floated. An internal pull-up

ensures that RD/QSMD is HIGH during RESET. Following RESET

the pin is sampled to determine whether the processor is to provide

ALE, RD, and WR, or queue status information. To enable Queue

Status Mode, RD must be connected to GND.

ARDY

I

A(L)

S(L)

Asynchronous Ready informs the processor that the addressed

memory space or I/O device will complete a data transfer. The

ARDY pin accepts a rising edge that is asynchronous to CLKOUT

and is active HIGH. The falling edge of ARDY must be synchronized

to the processor clock. Connecting ARDY HIGH will always assert

the ready condition to the CPU. If this line is unused, it should be tied

LOW to yield control to the SRDY pin.

NOTE:

Pin names in parentheses apply to the 80C188XL.

12

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Output

Input

Type

Pin Description

Name

Type

States

SRDY

I

S(L)

Ð

Synchronous Ready informs the processor that the addressed

memory space or I/O device will complete a data transfer. The

SRDY pin accepts an active-HIGH input synchronized to CLKOUT.

The use of SRDY allows a relaxed system timing over ARDY. This

is accomplished by elimination of the one-half clock cycle required

to internally synchonize the ARDY input signal. Connecting SRDY

high will always assert the ready condition to the CPU. If this line is

unused, it should be tied LOW to yield control to the ARDY pin.

LOCK

O

Ð

H(Z)

R(Z)

LOCK output indicates that other system bus masters are not to

gain control of the system bus. LOCK is active LOW. The LOCK

signal is requested by the LOCK prefix instruction and is activated

at the beginning of the first data cycle associated with the

instruction immediately following the LOCK prefix. It remains active

until the completion of that instruction. No instruction prefetching

will occur while LOCK is asserted.

S0

S1

S2

H(Z)

R(1)

Bus cycle status S0–S2 are encoded to provide bus-transaction

information:

Bus Cycle Status Information

S2

S1

S0

Bus Cycle Initiated

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Interrupt Acknowledge

Read I/O

Write I/O

Halt

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (no bus cycle)

S2 may be used as a logical M/IO indicator, and S1 as a DT/R

indicator.

HOLD

HLDA

I

A(L)

Ð

HOLD indicates that another bus master is requesting the local bus.

The HOLD input is active HIGH. The processor generates HLDA

(HIGH) in response to a HOLD request. Simultaneous with the

issuance of HLDA, the processor will float the local bus and control

lines. After HOLD is detected as being LOW, the processor will

lower HLDA. When the processor needs to run another bus cycle, it

will again drive the local bus and control lines.

O

H(1)

R(0)

In Enhanced Mode, HLDA will go low when a DRAM refresh cycle

is pending in the processor and an external bus master has control

of the bus. It will be up to the external master to relinquish the bus

by lowering HOLD so that the processor may execute the refresh

cycle.

NOTE:

Pin names in parentheses apply to the 80C188XL.

13

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Input

Type

Output

Pin Description

Name

Type

States

UCS

I/O

A(L)

H(1)

R(WH)

Upper Memory Chip Select is an active LOW output

whenever a memory reference is made to the defined

upper portion (1K–256K block) of memory. The

address range activating UCS is software

programmable.

UCS and LCS are sampled upon the rising edge of

RES. If both pins are held low, the processor will enter

ONCE Mode. In ONCE Mode all pins assume a high

impedance state and remain so until a subsequent

RESET. UCS has a weak internal pullup that is active

during RESET to ensure that the processor does not

enter ONCE Mode inadvertently.

LCS

I/O

A(L)

H(1)

R(WH)

Lower Memory Chip Select is active LOW whenever a

memory reference is made to the defined lower portion

(1K–256K) of memory. The address range activating

LCS is software programmable.

UCS and LCS are sampled upon the rising edge of

RES. If both pins are held low, the processor will enter

ONCE Mode. In ONCE Mode all pins assume a high

impedance state and remain so until a subsequent

RESET. LCS has a weak internal pullup that is active

only during RESET to ensure that the processor does

not enter ONCE mode inadvertently.

MCS0/PEREQ

MCS1/ERROR

I/O

O

A(L)

H(1)

R(WH)

Mid-Range Memory Chip Select signals are active LOW

when a memory reference is made to the defined mid-

range portion of memory (8K–512K). The address

ranges activating MCS0–3 are software programmable.

MCS2

MCS3/NPS

H(1)

R(1)

On the 80C186XL, in Enhanced Mode, MCS0 becomes

a PEREQ input (Processor Extension Request). When

connected to the Math Coprocessor, this input is used

to signal the 80C186XL when to make numeric data

transfers to and from the coprocessor. MCS3 becomes

NPS (Numeric Processor Select) which may only be

activated by communication to the 80C187. MCS1

becomes ERROR in Enhanced Mode and is used to

signal numerics coprocessor errors.

PCS0

PCS1

PCS2

PCS3

PCS4

O

H(1)

R(1)

Peripheral Chip Select signals 0–4 are active LOW

when a reference is made to the defined peripheral

area (64 Kbyte I/O or 1 MByte memory space). The

address ranges activating PCS0–4 are software

programmable.

PCS5/A1

H(1)/H(X)

R(1)

Peripheral Chip Select 5 or Latched A1 may be

programmed to provide a sixth peripheral chip select, or

to provide an internally latched A1 signal. The address

range activating PCS5 is software-programmable.

PCS5/A1 does not float during bus HOLD. When

programmed to provide latched A1, this pin will retain

the previously latched value during HOLD.

NOTE:

Pin names in parentheses apply to the 80C188XL.

14

80C186XL/80C188XL

Table 3. Pin Descriptions (Continued)

Input

Type

Output

Pin Description

Name

Type

States

PCS6/A2

O

Ð

H(1)/H(X)

R(1)

Peripheral Chip Select 6 or Latched A2 may be programmed

to provide a seventh peripheral chip select, or to provide an

internally latched A2 signal. The address range activating

PCS6 is software-programmable. PCS6/A2 does not float

during bus HOLD. When programmed to provide latched A2,

this pin will retain the previously latched value during HOLD.

DT/R

DEN

O

Ð

H(Z)

R(Z)

Data Transmit/Receive controls the direction of data flow

through an external data bus transceiver. When LOW, data is

transferred to the procesor. When HIGH the processor

places write data on the data bus.

H(Z)

R(1,Z)

Data Enable is provided as a data bus transceiver output

enable. DEN is active LOW during each memory and I/O

access (including 80C187 access). DEN is HIGH whenever

DT/R changes state. During RESET, DEN is driven HIGH for

one clock, then floated.

N.C.

Ð

Not connected. To maintain compatibility with future

products, do not connect to these pins.

NOTE:

Pin names in parentheses apply to the 80C188XL.

15

80C186XL/80C188XL

Ceramic Leadless Chip Carrier (JEDEC Type A)

Contacts Facing Up Contacts Facing Down

272431–5

Ceramic Pin Grid Array

Pins Facing Up

Pins Facing Down

272431–6

NOTE:

XXXXXXXXC indicates the Intel FPO number.

Figure 4. 80C186XL/80C188XL Pinout Diagrams

16

80C186XL/80C188XL

Shrink Quad Flat Pack

272431–22

NOTE:

XXXXXXXXC indicates the Intel FPO number.

Figure 4. 80C186XL/80C188XL Pinout Diagrams (Continued)

17

80C186XL/80C188XL

Plastic Leaded Chip Carrier

Contacts Facing Up

Contacts Facing Down

272431–7

80-Pin Quad Flat Pack (EIAJ)

Contacts

Facing Up

Contacts

Facing Down

272431–8

NOTE:

XXXXXXXXA indicates the Intel FPO number.

Figure 4. 80C186XL/80C288XL Pinout Diagrams (Continued)

18

80C186XL/80C188XL

Table 4. LCC/PLCC Pin Functions with Location

Bus Control Processor Control

ALE/QS0

AD Bus

I/O

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

17

15

13

11

8

61

64

52

53

54

62

63

55

49

39

40

48

50

51

RES

24

UCS

LCS

34

33

BHE (RFSH)

S0

S1

RESET

X1

X2

57

59

58

56

47

46

45

44

42

41

MCS0/PEREQ

MCS1/ERROR

MCS2

38

37

36

35

S2

CLKOUT

TEST/BUSY

NMI

6

RD/QSMD

WR/QS1

ARDY

SRDY

DEN

4

MCS3/NPS

2

INT0

AD8 (A8)

AD9 (A9)

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13 (A13)

AD14 (A14)

AD15 (A15)

A16/S3

16

14

12

10

7

INT1/SELECT

INT2/INTA0

INT3/INTA1

PCS0

PCS1

25

27

28

29

30

31

32

DT/R

PCS2

PCS3

LOCK

HOLD

HLDA

PCS4

PCS5/A1

PCS6/A2

Power and Ground

5

V

9

3

CC

SS

V

43

26

60

1

68

67

66

65

TMR IN 0

TMR IN 1

20

21

22

23

A17/S4

A18/S5

A19/S6

TMR OUT 0

TMR OUT 1

DRQ0

DRQ1

18

19

NOTE:

Pin names in parentheses apply to the 80C188XL.

Table 5. LCC/PGA/PLCC Pin Locations with Pin Names

1

2

AD15 (A15)

AD7

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

DRQ0

DRQ1

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

MCS3/NPS

MCS2

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

S0

S1

3

AD14 (A14)

AD6

TMR IN 0

TMR IN 1

TMR OUT 0

TMR OUT 1

RES

MCS1/ERROR

MCS0/PEREQ

DEN

S2

4

ARDY

CLKOUT

RESET

X2

5

AD13 (A13)

AD5

6

DT/R

INT3/INTA1

INT2/INTA0

7

AD12 (A12)

AD4

8

PCS0

X1

V

SS

9

V

SS

PCS1

V

CC

10

11

12

13

14

15

16

17

AD11 (A11)

AD3

INT1/SELECT

INT0

NMI

ALE/QS0

RD/QSMD

WR/QS1

BHE (RFSH)

A19/S2

PCS2

PCS3

PCS4

AD10 (A10)

AD2

TEST/BUSY

LOCK

SRDY

AD9 (A9)

AD1

PCS5/A1

PCS6/A2

LCS

A18/S3

A17/S4

A16/S3

AD8 (A8)

AD0

HOLD

HLDA

UCS

NOTE:

Pin names in parentheses apply to the 80C188XL.

19

80C186XL/80C188XL

AD Bus

Table 6. QFP Pin Functions with Location

Bus Control Processor Control

ALE/QS0

I/O

AD0

AD1

64

66

68

70

74

76

78

80

65

67

69

71

75

77

79

1

10

7

RES

55

UCS

LCS

45

46

BHE (RFSH)

S0

S1

RESET

X1

X2

18

16

17

19

29

30

31

32

35

36

AD2

AD3

23

22

21

9

MCS0/PEREQ

MCS1/ERROR

MCS2

39

40

41

42

AD4

AD5

S2

CLKOUT

TEST/BUSY

NMI

RD/QSMD

WR/QS1

ARDY

SRDY

DEN

AD6

AD7

8

MCS3/NPS

20

27

38

37

28

26

25

INT0

AD8 (A8)

AD9 (A9)

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13 (A13)

AD14 (A14)

AD15 (A15)

A16/S3

A17/S4

A18/S5

A19/S6

INT1/SELECT

INT2/INTA0

INT3/INTA1

PCS0

PCS1

54

52

51

50

49

48

47

DT/R

PCS2

PCS3

LOCK

HOLD

HLDA

PCS4

PCS5/A1

PCS6/A2

Power and Ground

V

33

CC

SS

V

34

72

73

12

13

53

No Connection

3

TMR IN 0

TMR IN 1

59

58

57

56

N.C.

2

11

14

15

24

43

44

62

63

4

5

TMR OUT 0

TMR OUT 1

6

DRQ0

DRQ1

61

60

NOTE:

Pin names in parentheses apply to the 80C188XL.

Table 7. QFP Pin Locations with Pin Names

1

2

AD15 (A15)

N.C.

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

S2

S1

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

MCS2

MCS3/NPS

N.C.

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

DRQ0

N.C.

3

A16/S3

A17/S4

A18/S5

A19/S6

BHE/(RFSH)

WR/QS1

RD/QSMD

ALE/QS0

N.C.

S0

N.C.

4

N.C.

UCS

AD0

AD8 (A8)

AD1

5

HLDA

HOLD

SRDY

LOCK

TEST/BUSY

NMI

6

LCS

7

PCS6/A2

PCS5/A1

PCS4

AD9 (A9)

AD2

8

9

AD10 (A10)

AD3

AD11 (A11)

10

11

12

13

14

15

16

17

18

19

20

PCS3

PCS2

PCS1

INT0

INT1/SELECT

V

SS

CC

V

SS

PCS0

CC

N.C.

AD4

AD12 (A12)

AD5

CC

INT2/INTA0

INT3/INTA1

DT/R

RES

X1

X2

TMR OUT 1

TMR OUT 0

TMR IN 1

TMR IN 0

DRQ1

AD13 (A13)

AD6

RESET

CLKOUT

ARDY

DEN

MCS0/PEREQ

MCS1/ERROR

AD14 (A14)

AD7

NOTE:

Pin names in parentheses apply to the 80C188XL.

20

80C186XL/80C188XL

Table 8. SQFP Pin Functions with Location

Bus Control Processor Control

ALE/QS0

AD Bus

I/O

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

1

3

29

26

40

39

38

28

27

37

44

56

54

45

43

42

RES

73

UCS

LCS

62

63

BHE (RFSH)

S0

S1

RESET

X1

X2

34

32

33

36

46

47

48

49

52

53

6

8

MCS0/PEREQ

MCS1/ERROR

MCS2

57

58

59

60

12

14

16

18

2

S2

CLKOUT

TEST/BUSY

NMI

RD/QSMD

WR/QS1

ARDY

SRDY

DEN

MCS3/NPS

INT0

AD8 (A8)

AD9 (A9)

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13 (A13)

AD14 (A14)

AD15 (A15)

A16/S3

INT1/SELECT

INT2/INTA0

INT3/INTA1

PCS0

PCS1

71

69

68

67

66

65

64

5

7

DT/R

PCS2

PCS3

9

LOCK

HOLD

HLDA

13

15

17

19

21

22

23

24

PCS4

PCS5/A1

PCS6/A2

Power and Ground

V

10

CC

SS

V

11

20

50

51

61

30

31

41

70

80

No Connection

TMR IN 0

TMR IN 1

77

76

75

74

N.C.

4

25

35

55

72

A17/S4

A18/S5

A19/S6

TMR OUT 0

TMR OUT 1

DRQ0

DRQ1

79

78

NOTE:

Pin names in parentheses apply to the 80C188XL.

Table 9. SQFP Pin Locations with Pin Names

1

2

AD0

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

A16/S3

A17/S4

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

V

HLDA

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

V

CC

UCS

SS

AD8 (A8)

AD1

N.C.

3

A18/S5

A19/S6

N.C.

HOLD

SRDY

LOCK

LCS

4

PCS6/A2

PCS5/A1

PCS4

5

AD9 (A9)

AD2

6

BHE (RFSH)

WR/QS1

RD/QSMD

ALE/QS0

TEST/BUSY

NMI

INT0

7

AD10 (A10)

AD3

AD11 (A11)

PCS3

PCS2

PCS1

8

9

INT1/SELECT

10

11

12

13

14

15

16

17

18

19

20

V

SS

PCS0

CC

SS

CC

SS

AD4

AD12 (A12)

AD5

X1

X2

INT2/INTA0

INT3/INTA1

DT/R

N.C.

RES

RESET

N.C.

CLKOUT

ARDY

S2

TMR OUT 1

TMR OUT 0

TMR IN 1

TMR IN 0

DRQ1

AD13 (A13)

AD6

N.C.

DEN

AD14 (A14)

AD7

AD15 (A15)

MCS0/PEREQ

MCS1/ERROR

MCS2

S1

S0

DRQ0

V

SS

V

MCS3/NPS

CC

NOTE:

Pin names in parentheses apply to the 80C188XL.

21

80C186XL/80C188XL

ELECTRICAL SPECIFICATIONS

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

Absolute Maximum Ratings*

a

Ambient Temperature under Bias ÀÀÀÀ0 C to 70 C

§

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

§

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

b

a

§

Voltage on Any Pin with

Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀ 1.0V to 7.0V

b

a

Package Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W

Not to exceed the maximum allowable die tempera-

ture based on thermal resistance of the package.

NOTICE: The specifications are subject to change

without notice.

e

a

0 C to 70 C, V

e

CC

g

5V 10%

DC SPECIFICATIONS T

§

A

Symbol

Parameter

Min

Max

Units

Test Conditions

b

0.3

V

Input Low Voltage

(Except X1)

0.5

0.2 V

V

IL

CC

b

Clock Input Low

Voltage (X1)

0.5

0.6

V

IL1

IH

a

Input High Voltage

(All except X1 and RES)

0.2 V

0.9

V

CC

0.5

CC

a

V

Input High Voltage (RES)

3.0

3.9

V

0.5

V

IH1

IH2

CC

Clock Input High

Voltage (X1)

CC

e

V

Output Low Voltage

0.45

V

I

2.5 mA (S0, 1, 2)

2.0 mA (others)

OL

(4)

@

2.4 mA 2.4V

e b

Output High Voltage

2.4

V

I

OH

CC

OH

(4)

@

b

0.5

V

0.5

200 mA

V

CC

@

25 MHz, 0 C

I

Power Supply Current

100

mA

§

CC

(3)

5.5V

e

V

CC

@

90

mA

V

20 MHz, 0 C

§

(3)

5.5V

e

V

CC

@

62.5

100

12 MHz, 0 C

§

(3)

e

V

CC

5.5V

@

DC 0 C

§

e

V

CC

5.5V

@

g

I

Input Leakage Current

Output Leakage Current

Clock Output Low

10

0.5 MHz,

s

LI

s

0.45V

V

IN

CC

@

0.5 MHz,

s

LO

(1)

s

0.45V

V

OUT

V

CC

e

4.0 mA

V

0.45

I

CLO

22

80C186XL/80C188XL

Test Conditions

e

a

0 C to 70 C, V

e

5V 10%

CC

g

DC SPECIFICATIONS (Continued) T

§

A

Symbol

Parameter

Clock Output High

Input Capacitance

Min

Max

Units

V

b

e b

500 mA

V

0.5

I

CHO

CC

(2)

@

C

10

20

pF

1 MHz

IN

IO

(2)

Output or I/O Capacitance

pF

NOTES:

1. Pins being floated during HOLD or by invoking the ONCE Mode.

e

a

5.0V or 0.45V. This

2. Characterization conditions are a) Frequency

parameter is not tested.

3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open.

1 MHz; b) Unmeasured pins at GND; c) V at

IN

4. RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR and TEST/BUSY pins have internal pullup devices. Loading some

e b

Local Bus Controller and Reset for details.

of these pins above I

200 mA can cause the processor to go into alternative modes of operation. See the section on

OH

Power Supply Current

Current is linearly proportional to clock frequency

and is measured with the device in RESET with X1

and X2 driven and all other non-power pins open.

e

c

freq.

Maximum current is given by I

a

5 mA

CC

(MHz)

I

.

QL

I

is the quiescent leakage current when the clock

QL

is static. I is typically less than 100 mA.

QL

272431–9

Figure 5. I vs Frequency

CC

23

80C186XL/80C188XL

AC SPECIFICATIONS

MAJOR CYCLE TIMINGS (READ CYCLE)

e

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

g

5V 10%

T

A

0 C to 70 C, V

§

CC

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25

Min Max

80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

80C186XL20

80C186XL12 Unit

Conditions

Min Max

Min

Max

T

Data in Setup (A/D)

Data in Hold (A/D)

8

3

10

3

15

3

ns

DVCL

CLDX

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

T

Status Active Delay

Status Inactive Delay

Address Valid Delay

Address Hold

3

20

3

25

27

3

35 ns

36 ns

ns

CHSV

CLSH

CLAV

CLAX

CLDV

CHDX

CHLH

LHLL

CHLL

AVLL

3

0

Data Valid Delay

Status Hold Time

ALE Active Delay

ALE Width

3

20

3

27

20

3

36 ns

ns

10

25 ns

ns

b

15

CLCL

T

15

10

T

15

T

CLCL

CLCH

CLCL

ALE Inactive Delay

Address Valid to ALE Low

25 ns

ns

b

T

10

T

15

Equal

Loading

CLCH

CHCL

CLCH

CHCL

b

T

Address Hold from ALE

Inactive

T

8

ns

Equal

Loading

LLAX

CHCL

T

Address Valid to Clock High

Address Float Delay

0

ns

25 ns

33 ns

ns

AVCH

CLAZ

T

20

T

20

25

T

CLAX

3

CLAX

3

CLAX

3

Chip-Select Active Delay

CLCSV

CXCSX

b

Chip-Select Hold from

Command Inactive

T

10

T

10

T

10

Equal

Loading

CLCH

T

Chip-Select Inactive Delay

DEN Inactive to DT/R Low

3

17

3

20

3

30 ns

ns

CHCSX

DXDL

0

Equal

Loading

T

Control Active Delay 1

DEN Inactive Delay

3

17

20

17

3

22

3

37 ns

CVCTV

CVDEX

CHCTV

CLLV

Control Active Delay 2

LOCK Valid/Invalid Delay

24

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

MAJOR CYCLE TIMINGS (READ CYCLE) (Continued)

e

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

g

5V 10%

T

0 C to 70 C, V

§

A

CC

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25

Min Max

80C186XL TIMING RESPONSES (Read Cycle)

80C186XL20

80C186XL12

Unit

Conditions

Min

Max

Min

Max

T

Address Float

to RD Active

0

3

0

3

ns

AZRL

T

RD Active Delay

RD Pulse Width

RD Inactive Delay

3

20

27

37

ns

CLRL

RLRH

CLRH

RHLH

b

25

CLCL

2T

15

2T

20

2T

CLCL

3

b

RD Inactive

to ALE High

T

14

15

T

14

15

T

CLCH

14

15

Equal

Loading

CLCH

T

RD Inactive to

Address Active

T

CLCL

ns

Equal

Loading

RHAV

CLCL

25

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

MAJOR CYCLE TIMINGS (WRITE CYCLE)

e

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

g

5V 10%

T

0 C to 70 C, V

§

A

CC

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25

Min Max

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

80C186XL20

80C186XL12

Unit

Conditions

Min

Max

Min

Max

T

Status Active Delay

Status Inactive Delay

Address Valid Delay

Address Hold

3

20

3

25

27

3

35 ns

36 ns

ns

CHSV

CLSH

CLAV

CLAX

CLDV

CHDX

CHLH

LHLL

CHLL

AVLL

3

0

Data Valid Delay

Status Hold Time

ALE Active Delay

ALE Width

3

20

3

27

20

3

36 ns

ns

10

25 ns

ns

b

15

CLCL

T

15

T

15

T

CLCL

ALE Inactive Delay

Address Valid to ALE Low

25 ns

ns

b

T

10

T

10

T

15

Equal

CLCH

CHCL

CLCH

Loading

T

Address Hold from ALE

Inactive

ns

Equal

LLAX

CHCL

Loading

T

Address Valid to Clock High

Data Hold Time

0

ns

AVCH

3

CLDOX

CVCTV

CVCTX

CLCSV

CXCSX

Control Active Delay 1

Control Inactive Delay

Chip-Select Active Delay

20

17

20

25

37 ns

33 ns

ns

b

Chip-Select Hold from

Command Inactive

T

10

T

10

T

10

Equal

CLCH

Loading

T

Chip-Select Inactive Delay

DEN Inactive to DT/R Low

3

0

17

3

0

20

22

3

0

30 ns

ns

CHCSX

DXDL

Equal

Loading

T

LOCK Valid/Invalid Delay

3

37 ns

CLLV

80C186XL TIMING RESPONSES (Write Cycle)

b

T

WR Pulse Width

2T

15

14

2T

20

14

2T

25

14

ns

WLWH

WHLH

CLCL

WR Inactive to ALE High

T

CLCH

T

CLCH

Equal

CLCH

Loading

b

T

Data Hold after WR

T

10

T

15

10

T

20

10

ns

Equal

WHDX

CLCL

Loading

WR Inactive to DEN Inactive T

T

CLCH

T

CLCH

Equal

WHDEX

CLCH

Loading

26

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE)

e

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

g

5V 10%

T

0 C to 70 C, V

§

A

CC

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25

Min Max

80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

80C186XL20

80C186XL12 Unit

Conditions

Min Max

Min

Max

T

Data in Setup (A/D)

Data in Hold (A/D)

8

3

10

3

15

3

ns

DVCL

CLDX

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

T

Status Active Delay

Status Inactive Delay

Address Valid Delay

Address Valid to Clock High

Address Hold

3

20

3

25

27

3

35 ns

36 ns

ns

CHSV

CLSH

CLAV

AVCH

CLAX

CLDV

CHDX

CHLH

LHLL

CHLL

AVLL

3

0

ns

Data Valid Delay

3

20

3

27

20

3

36 ns

ns

Status Hold Time

10

ALE Active Delay

ALE Width

25 ns

ns

b

15

CLCL

T

15

T

15

T

CLCL

ALE Inactive Delay

Address Valid to ALE Low

25 ns

ns

b

T

10

T

10

T

15

Equal

Loading

CLCH

CHCL

CLCH

CHCL

T

Address Hold to ALE

Inactive

ns

Equal

Loading

LLAX

CHCL

T

Address Float Delay

T

20

17

T

20

25

T

25 ns

37 ns

ns

CLAZ

CLAX

3

CLAX

3

CLAX

3

Control Active Delay 1

Control Inactive Delay

DEN Inactive to DT/R Low

CVCTV

CVCTX

DXDL

3

0

3

0

3

0

Equal

Loading

T

Control Active Delay 2

3

20

17

3

22

3

37 ns

CHCTV

CVDEX

DEN Inactive Delay

(Non-Write Cycles)

T

LOCK Valid/Invalid Delay

3

17

3

22

3

37 ns

CLLV

27

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

SOFTWARE HALT CYCLE TIMINGS

e

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

g

5V 10%

T

0 C to 70 C, V

§

A

CC

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25

Min Max

80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

80C186XL20

80C186XL12 Unit

Conditions

Min Max

Min

Max

T

Status Active Delay

Status Inactive Delay

Address Valid Delay

ALE Active Delay

3

20

3

25

27

20

3

35 ns

36 ns

25 ns

ns

CHSV

CLSH

CLAV

CHLH

LHLL

CHLL

DXDL

b

15

CLCL

ALE Width

T

15

T

15

T

CLCL

ALE Inactive Delay

DEN Inactive to DT/R Low

20

0

20

0

25 ns

0

ns

Equal

Loading

T

Control Active Delay 2

3

20

3

22

3

37 ns

CHCTV

28

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

CLOCK TIMINGS

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

e

CC

g

5V 10%

T

0 C to 70 C, V

§

A

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25

Min Max

80C186XL20

80C186XL12

Unit

Conditions

Min

Max

Min

Max

(1)

80C186XL CLKIN REQUIREMENTS

%

5

%

5

%

5

T

CLKIN Period

20

8

25

10

40

16

ns

CKIN

(2)

CLKIN Low Time

CLKIN High Time

CLKIN Fall Time

CLKIN Rise Time

ns 1.5V

CLCK

CHCK

CKHL

CKLH

(2)

8

ns 3.5 to 1.0V

ns 1.0 to 3.5V

5

80C186XL CLKOUT TIMING

T

CLKIN to

CLKOUT Skew

17

21 ns

CICO

%

T

CLKOUT Period

40

50

80

ns

CLCL

CLCH

(3)

(4)

b

e

CLKOUT

Low Time

0.5 T

5

0.5 T

5

0.5 T

5

ns

C

100 pF

CLCL

L

T

CLKOUT

High Time

ns

CHCL

CLCL

L

CLKOUT

Rise Time

6

8

10 ns 1.0 to 3.5V

10 ns 3.5 to 1.0V

CH1CH2

CL2CL1

CLKOUT

Fall Time

NOTES:

1. External clock applied to X1 and X2 not connected.

2. T and T (CLKIN Low and High times) should not have a duration less than 40% of T .

CKIN

CLCK

CHCK

e

3. Tested under worst case conditions: V

4. Tested under worst case conditions: V

5.5V. T

4.5V. T

70 C.

0 C.

§

CC

A

§

29

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

READY, PERIPHERAL AND QUEUE STATUS TIMINGS

e

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

g

5V 10%

T

0 C to 70 C, V

§

A

CC

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25 80C186XL20 80C186XL12 Unit

Conditions

Min

Max

Min

Max

Min

Max

80C186XL READY AND PERIPHERAL TIMING REQUIREMENTS (Listed More Than Once)

T

Synchronous Ready (SRDY)

(1)

Transition Setup Time

8

10

15

ns

SRYCL

(1)

T

SRDY Transition Hold Time

8

10

15

ns

CLSRY

ARYCH

ARDY Resolution Transition

(2)

Setup Time

(1)

T

ARDY Active Hold Time

8

10

15

25

ns

CLARX

ARDY Inactive Holding Time

ARYCHL

ARYLCL

Asynchronous Ready

(1)

(ARDY) Setup Time

10

T

INTx, NMI, TEST/BUSY,

(2)

TMR IN Setup Time

8

10

15

ns

INVCH

(2)

T

DRQ0, DRQ1 Setup Time

8

10

INVCL

80C186XL PERIPHERAL AND QUEUE STATUS TIMING RESPONSES

T

Timer Output Delay

Queue Status Delay

17

22

27

33

32

ns

CLTMV

CHQSV

NOTES:

1. To guarantee proper operation.

2. To guarantee recognition at clock edge.

30

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

RESET AND HOLD/HLDA TIMINGS

e

a

e

All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.

g

5V 10%

T

0 C to 70 C, V

§

A

CC

e

All output test conditions are with C

e

50 pF.

e

L

0.45V and V

e

b

V 0.5V.

CC

For AC tests, input V

2.4V except at X1 where V

IL

IH

Values

Test

Symbol

Parameter

80C186XL25 80C186XL20 80C186XL12 Unit

Conditions

Min

Max

Min

Max

Min

Max

80C186XL RESET AND HOLD/HLDA TIMING REQUIREMENTS

T

RES Setup

15

8

15

10

15

ns

RESIN

(1)

HOLD Setup

HVCL

80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

T

Address Float Delay

Address Valid Delay

T

20

T

20

22

T

25

36

ns

CLAZ

CLAX

3

CLAV

80C186XL RESET AND HOLD/HLDA TIMING RESPONSES

T

Reset Delay

17

22

20

22

25

26

33

36

ns

CLRO

CLHAV

CHCZ

CHCV

HLDA Valid Delay

Command Lines Float Delay

3

Command Lines Valid Delay

(after Float)

NOTE:

1. To guarantee recognition at next clock.

31

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

272431–10

NOTES:

1. Status inactive in state preceding T .

4

2. If latched A and A are selected instead of PCS5 and PCS6, only T is applicable.

1

2

3. For write cycle followed by read cycle.

CLCSV

4. T of next bus cycle.

1

5. Changes in T-state preceding next bus cycle if followed by write.

Pin names in parentheses apply to the 80C188XL.

Figure 6. Read Cycle Waveforms

32

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

272431–11

NOTES:

1. Status inactive in state preceding T .

4

2. If latched A and A are selected instead of PCS5 and PCS6, only T is applicable.

1

2

CLCSV

3. For write cycle followed by read cycle.

4. T of next bus cycle.

1

5. Changes in T-state preceding next bus cycle if followed by read, INTA, or halt.

Pin names in parentheses apply to the 80C188XL.

Figure 7. Write Cycle Waveforms

33

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

272431–12

NOTES:

1. Status inactive in state preceding T .

4

2. The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to T

3. INTA occurs one clock later in Slave Mode.

4. For write cycle followed by interrupt acknowledge cycle.

(min).

CLDX

5. LOCK is active upon T of the first interrupt acknowledge cycle and inactive upon T of the second interrupt acknowl-

2

1

edge cycle.

6. Changes in T-state preceding next bus cycle if followed by write.

Pin names in parentheses apply to the 80C188XL.

Figure 8. Interrupt Acknowledge Cycle Waveforms

34

80C186XL/80C188XL

AC SPECIFICATIONS (Continued)

272431–13

NOTE:

1. For write cycle followed by halt cycle.

Pin names in parentheses apply to the 80C188XL.

Figure 9. Software Halt Cycle Waveforms

35

80C186XL/80C188XL

WAVEFORMS

272431–14

Figure 10. Clock Waveforms

272431–15

Figure 11. Reset Waveforms

272431–16

Figure 12. Synchronous Ready (SRDY) Waveforms

36

80C186XL/80C188XL

AC CHARACTERISTICS

272431–23

Figure 13. Asynchronous Ready (ARDY) Waveforms

272431–17

Figure 14. Peripheral and Queue Status Waveforms

37

80C186XL/80C188XL

AC CHARACTERISTICS (Continued)

272431–24

Figure 15. HOLDA/HLDA Waveforms (Entering Hold)

272431–18

Figure 16. HOLD/HLDA Waveforms (Leaving Hold)

38

80C186XL/80C188XL

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has from 5 to 7 characters. The first character is always a ‘T’ (stands for time). The other

characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The

following is a list of all the characters and what they stand for.

A:

ARY: Asynchronous Ready Input

C: Clock Output

Address

CK: Clock Input

CS: Chip Select

CT: Control (DT/R, DEN, . . . )

D:

Data Input

DE: DEN

H:

Logic Level High

OUT: Input (DRQ0, TIM0, . . . )

L:

Logic Level Low or ALE

Output

O:

QS: Queue Status (QS1, QS2)

R:

S:

RD Signal, RESET Signal

Status (S0, S1, S2)

SRY: Synchronous Ready Input

V:

W:

X:

Z:

Valid

WR Signal

No Longer a Valid Logic Level

Float

Examples:

T

Ð Time from Clock low to Address valid

Ð Time from Clock high to ALE high

Ð Time from Clock low to Chip Select valid

CLAV

CHLH

CLCSV

39

80C186XL/80C188XL

DERATING CURVES

Typical Output Delay Capacitive Derating

272431–19

Figure 17. Capacitive Derating Curve

Typical Rise and Fall Times for TTL Voltage Levels

272431–20

Figure 18. TTL Level Rise and Fall Times for Output Buffers

Typical Rise and Fall Times for CMOS Voltage Levels

272431–21

Figure 19. CMOS Level Rise and Fall Times for Output Buffers

40

80C186XL/80C188XL

80C186XL/80C188XL EXPRESS

80C186XL/80C188XL EXECUTION

TIMINGS

The Intel EXPRESS system offers enhancements to

the operational specifications of the 80C186XL mi-

croprocessor. EXPRESS products are designed to

meet the needs of those applications whose operat-

ing requirements exceed commercial standards.

A determination of program execution timing must

consider the bus cycles necessary to prefetch in-

structions as well as the number of execution unit

cycles necessary to execute instructions. The fol-

lowing instruction timings represent the minimum ex-

ecution time in clock cycles for each instruction. The

timings given are based on the following assump-

tions:

The 80C186XL EXPRESS program includes an ex-

tended temperature range. With the commercial

standard temperature range, operational character-

istics are guaranteed over the temperature range of

The opcode, along with any data or displacement

#

a

0 C to 70 C. With the extended temperature range

option, operational characteristics are guaranteed

§

required for execution of a particular instruction,

has been prefetched and resides in the queue at

the time it is needed.

b

a

over the range of 40 C to 85 C.

§

No wait states or bus HOLDs occur.

#

Package types and EXPRESS versions are identified

by a one or two-letter prefix to the part number. The

prefixes are listed in Table 10. All AC and DC specifi-

cations not mentioned in this section are the same

for both commercial and EXPRESS parts.

All word-data is located on even-address bound-

aries (80C186XL only).

All jumps and calls include the time required to fetch

the opcode of the next instruction at the destination

address.

Table 10. Prefix Identification

Package

Type

Temperature

Range

Prefix

All instructions which involve memory accesses can

require one or two additional clocks above the mini-

mum timings shown due to the asynchronous hand-

shake between the bus interface unit (BIU) and exe-

cution unit.

A

N

PGA

PLCC

LCC

Commercial

Extended

R

With a 16-bit BIU, the 80C186XL has sufficient bus

performance to ensure that an adequate number of

prefetched bytes will reside in the queue (6 bytes)

most of the time. Therefore, actual program execu-

tion time will not be substantially greater than that

derived from adding the instruction timings shown.

S

QFP

SB

TA

TN

TR

TS

SQFP

PGA

PLCC

LCC

Extended

The 80C188XL 8-bit BIU is limited in its performance

relative to the execution unit. A sufficient number of

prefetched bytes may not reside in the prefetch

queue (4 bytes) much of the time. Therefore, actual

program execution time will be substantially greater

than that derived from adding the instruction timings

shown.

QFP

Extended

41

80C186XL/80C188XL

INSTRUCTION SET SUMMARY

80C186XL 80C188XL

Function

Format

Clock

Comments

Cycles

DATA TRANSFER

e

MOV

Move:

Register to Register/Memory

Register/memory to register

Immediate to register/memory

Immediate to register

1 0 0 0 1 0 0 w

1 0 0 0 1 0 1 w

1 1 0 0 0 1 1 w

1 0 1 1 w reg

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

mod reg r/m

mod 000 r/m

data

2/12

2/9

12/13

3/4

8

2/12*

2/9*

12/13

3/4

e

data

data if w

1

8/16-bit

e

data if w

1

Memory to accumulator

addr-low

addr-high

8*

Accumulator to memory

addr-low

9

9*

Register/memory to segment register

Segment register to register/memory

mod 0 reg r/m

2/9

2/11

2/13

2/15

e

PUSH

Push:

Memory

Register

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

0 1 1 0 1 0 s 0

mod 1 1 0 r/m

16

10

9

20

14

13

14

Segment register

Immediate

e

data

data if s

0

10

e

PUSHA

Push All

Pop:

Memory

0 1 1 0 0 0 0 0

36

68

e

POP

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

mod 0 0 0 r/m

(regⁱ01)

20

10

8

24

14

12

Register

Segment register

e

POPA

Pop All

0 1 1 0 0 0 0 1

51

83

XCHG

Exchange:

Register/memory with register

Register with accumulator

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

mod reg r/m

4/17

3

4/17*

3

e

IN

Input from:

Fixed port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

port

10

8

10*

8*

Variable port

e

OUT

Output to:

Fixed port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

9

7

9*

7*

15

6

Variable port

e

XLAT

Translate byte to AL

11

6

e

LEA

LDS

LES

Load EA to register

Load pointer to DS

Load pointer to ES

mod reg r/m

(modⁱ11)

18

2

26

2

e

LAHF

SAHF

Load AH with flags

Store AH into flags

e

3

e

PUSHF

Push flags

9

13

12

e

POPF

Pop flags

8

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

42

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

80C186XL 80C188XL

Function

Format

Clock

Comments

Cycles

DATA TRANSFER (Continued)

e

SEGMENT

Segment Override:

CS

0 0 1 0 1 1 1 0

0 0 1 1 0 1 1 0

0 0 1 1 1 1 1 0

0 0 1 0 0 1 1 0

2

SS

DS

ES

ARITHMETIC

e

ADD

Add:

Reg/memory with register to either

Immediate to register/memory

Immediate to accumulator

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

mod reg r/m

mod 0 0 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4

e

data if s w 01

data

e

data if w

1

8/16-bit

e

ADC

Add with carry:

Reg/memory with register to either

Immediate to register/memory

Immediate to accumulator

0 0 0 1 0 0 d w

1 0 0 0 0 0 s w

0 0 0 1 0 1 0 w

mod reg r/m

mod 0 1 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4

e

data if s w 01

data

data if w

e

INC

Increment:

Register/memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

mod 0 0 0 r/m

3/15

3

3/15*

3

e

SUB

Subtract:

Reg/memory and register to either

Immediate from register/memory

Immediate from accumulator

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4

e

data if s w 01

data

e

data if w

1

8/16-bit

e

SBB

Subtract with borrow:

Reg/memory and register to either

Immediate from register/memory

Immediate from accumulator

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

mod reg r/m

mod 0 1 1 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4*

e

data if s w 01

data

data if w

e

DEC

Decrement

Register/memory

Register

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

mod 0 0 1 r/m

3/15

3

3/15*

3

e

CMP

Compare:

Register/memory with register

Register with register/memory

Immediate with register/memory

Immediate with accumulator

0 0 1 1 1 0 1 w

0 0 1 1 1 0 0 w

1 0 0 0 0 0 s w

0 0 1 1 1 1 0 w

1 1 1 1 0 1 1 w

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

mod reg r/m

mod 1 1 1 r/m

data

3/10

3/4

3/10

8

3/10*

3/4

3/10*

8

e

data if s w 01

data

e

data if w

1

8/16-bit

e

NEG

AAA

DAA

AAS

DAS

Change sign register/memory

ASCII adjust for add

mod 0 1 1 r/m

Decimal adjust for add

4

ASCII adjust for subtract

Decimal adjust for subtract

7

4

e

MUL

Multiply (unsigned):

1 1 1 1 0 1 1 w

mod 100 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

26–28

35–37

32–34

41–43

26–28

35–37

32–34

41–43*

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

43

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

80C186XL 80C188XL

Function

Format

Clock

Comments

Cycles

ARITHMETIC (Continued)

e

IMUL

Integer multiply (signed):

1 1 1 1 0 1 1 w

mod 1 0 1 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

25–28

34–37

31–34

40–43

25–28

34–37

32–34

40–43*

e

(signed)

e

0

IMUL

Integer Immediate multiply

0 1 1 0 1 0 s 1

1 1 1 1 0 1 1 w

mod reg r/m

data

data if s

22–25/

29–32

22–25/

29–32

e

DIV

Divide (unsigned):

mod 1 1 0 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

29

38

35

44

29

38

35

44*

e

IDIV

Integer divide (signed):

1 1 1 1 0 1 1 w

mod 1 1 1 r/m

Register-Byte

Register-Word

Memory-Byte

Memory-Word

44–52

53–61

50–58

59–67

44-52

53–61

50–58

59–67*

e

AAM

AAD

CBW

CWD

ASCII adjust for multiply

ASCII adjust for divide

Convert byte to word

1 1 0 1 0 1 0 0

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

0 0 0 0 1 0 1 0

19

15

2

19

15

2

Convert word to double word

4

LOGIC

Shift/Rotate Instructions:

Register/Memory by 1

1 1 0 1 0 0 0 w

1 1 0 1 0 0 1 w

1 1 0 0 0 0 0 w

mod TTT r/m

2/15

a

Register/Memory by CL

5

n/17

n

5

n/17

n

a

Register/Memory by Count

mod TTT r/m

count

TTT Instruction

0 0 0

0 0 1

0 1 0

0 1 1

ROL

ROR

RCL

RCR

1 0 0 SHL/SAL

1 0 1

1 1 1

SHR

SAR

e

AND

And:

Reg/memory and register to either

Immediate to register/memory

Immediate to accumulator

0 0 1 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

mod reg r/m

mod 1 0 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4*

e

data

data if w

1

e

data if w

1

8/16-bit

e

TEST And function to flags, no result:

Register/memory and register

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

1 0 1 0 1 0 0 w

mod reg r/m

mod 0 0 0 r/m

data

3/10

4/10

3/4

3/10*

4/10*

3/4

Immediate data and register/memory

Immediate data and accumulator

data

e

data if w

e

OR Or:

Reg/memory and register to either

Immediate to register/memory

Immediate to accumulator

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

mod reg r/m

mod 0 0 1 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4*

data

e

data if w

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

44

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

80C186XL 80C188XL

Function

Format

Clock

Comments

Cycles

LOGIC (Continued)

e

XOR

Exclusive or:

Reg/memory and register to either

Immediate to register/memory

Immediate to accumulator

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

1 1 1 1 0 1 1 w

mod reg r/m

mod 1 1 0 r/m

data

3/10

4/16

3/4

3/10*

4/16*

3/4

e

1

data

data if w

e

data if w

1

8/16-bit

e

NOT

Invert register/memory

mod 0 1 0 r/m

3/10

3/10*

STRING MANIPULATION

e

MOVS

CMPS

SCAS

LODS

STOS

Move byte/word

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

0 1 1 0 1 1 0 w

0 1 1 0 1 1 1 w

14

22

15

12

10

14

14*

22*

15*

12*

10*

14

Compare byte/word

Scan byte/word

Load byte/wd to AL/AX

Store byte/wd from AL/AX

e

INS

Input byte/wd from DX port

e

OUTS

Output byte/wd to DX port

14

Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)

e

a

8 8n*

MOVS

CMPS

SCAS

LODS

STOS

Move string

Compare string

Scan string

Load string

1 1 1 1 0 0 1 0

1 1 1 1 0 0 1 z

1 1 1 1 0 0 1 0

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

0 1 1 0 1 1 0 w

8

8n

a

5

6

22n

15n

11n

5

6

22n*

15n*

11n*

a

Store string

6

9n

8n

6

9n*

8n*

e

a

INS

Input string

8

e

OUTS

Output string

1 1 1 1 0 0 1 0

0 1 1 0 1 1 1 w

8n

8n*

CONTROL TRANSFER

e

CALL

Call:

Direct within segment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

disp-low

disp-high

15

19

Register/memory

mod 0 1 0 r/m

13/19

17/27

indirect within segment

Direct intersegment

1 0 0 1 1 0 1 0

1 1 1 1 1 1 1 1

segment offset

segment selector

23

31

i

(mod 11)

Indirect intersegment

mod 0 1 1 r/m

38

54

e

JMP

Unconditional jump:

Short/long

1 1 1 0 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 1 1 1

disp-low

14

Direct within segment

disp-high

Register/memory

mod 1 0 0 r/m

11/17

11/21

indirect within segment

Direct intersegment

Indirect intersegment

1 1 1 0 1 0 1 0

segment offset

segment selector

14

26

14

34

i

(mod 11)

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

45

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

80C186XL

Clock

80C188XL

Clock

Function

Format

Comments

Cycles

CONTROL TRANSFER (Continued)

e

RET

Return from CALL:

Within segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

1 1 0 0 1 0 1 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

0 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 0 0 0 0 0

16

20

Within seg adding immed to SP

Intersegment

data-low

data-high

18

22

30

Intersegment adding immediate to SP

data-low

disp

25

33

e

JE/JZ

Jump on equal/zero

4/13

5/15

6/16

4/13

5/15

6/16

JMP not

taken/JMP

taken

e

JL/JNGE

JLE/JNG

JB/JNAE

JBE/JNA

Jump on less/not greater or equal

Jump on less or equal/not greater

Jump on below/not above or equal

Jump on below or equal/not above

e

JP/JPE

Jump on parity/parity even

Jump on overflow

Jump on sign

e

JO

JS

e

JNE/JNZ

JNL/JGE

JNLE/JG

JNB/JAE

JNBE/JA

JNP/JPO

Jump on not equal/not zero

Jump on not less/greater or equal

Jump on not less or equal/greater

Jump on not below/above or equal

Jump on not below or equal/above

Jump on not par/par odd

e

JNO

JNS

Jump on not overflow

Jump on not sign

e

JCXZ

LOOP

Jump on CX zero

Loop CX times

e

LOOP not

taken/LOOP

taken

e

LOOPZ/LOOPE

LOOPNZ/LOOPNE

Loop while zero/equal

e

Loop while not zero/equal

e

ENTER

Enter Procedure

1 1 0 0 1 0 0 0

data-low

data-high

L

e

l

L

0

1

15

25

19

29

a

b

a

b

22 16(n 1) 26 20(n 1)

e

LEAVE

Leave Procedure

1 1 0 0 1 0 0 1

8

e

INT

Interrupt:

Type specified

Type 3

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

type

47

45

47

45

if INT. taken/

if INT. not

taken

e

INTO

Interrupt on overflow

48/4

e

IRET

Interrupt return

1 1 0 0 1 1 1 1

0 1 1 0 0 0 1 0

28

e

BOUND

Detect value out of range

mod reg r/m

33–35

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

46

80C186XL/80C188XL

INSTRUCTION SET SUMMARY (Continued)

80C186XL 80C188XL

Function

Format

Clock

Comments

Cycles

PROCESSOR CONTROL

e

CLC

CMC

STC

CLD

STD

Clear carry

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 1 1 0 0 0 0

2

6

2

3

2

6

2

3

Complement carry

Set carry

Clear direction

Set direction

e

CLI

STI

Clear interrupt

Set interrupt

e

HLT

Halt

e

0

WAIT

LOCK

Wait

if TEST

e

Bus lock prefix

e

NOP

No Operation

1 0 0 1 0 0 0 0

(TTT LLL are opcode to processor extension)

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

The Effective Address (EA) of the memory operand

is computed according to the mod and r/m fields:

reg is assigned according to the following:

Segment

e

if mod

11 then r/m is treated as a REG field

e

00 then DISP

high are absent

0*, disp-low and disp-

reg

00

01

10

11

Register

ES

CS

e

tended to 16-bits, disp-high is absent

if mod

01 then DISP

disp-low sign-ex-

SS

DS

e

if mod

if r/m

10 then DISP

disp-high: disp-low

e

a

000 then EA

001 then EA

010 then EA

011 then EA

100 then EA

101 then EA

110 then EA

111 then EA

(BX)

(SI)

(DI)

(SI)

(DI)

DISP

e

(BX)

(BP)

REG is assigned according to the following table:

e

0)

e

16-Bit (w

1)

8-Bit (w

000 AL

a

(SI)

DISP

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

a

(DI)

(BP)

(BX)

DISP

DISP*

DISP

001 CL

010 DL

011 BL

100 AH

101 CH

110 DH

111 BH

a

DISP follows 2nd byte of instruction (before data if

required)

e

110 then EA

*except if mod

disp-high: disp-low.

00 and r/m

111 DI

The physical addresses of all operands addressed

by the BP register are computed using the SS seg-

ment register. The physical addresses of the desti-

nation operands of the string primitive operations

(those addressed by the DI register) are computed

using the ES segment, which may not be overridden.

EA calculation time is 4 clock cycles for all modes,

and is included in the execution times given whenev-

er appropriate.

Segment Override Prefix

0

1

reg

1

0

47

80C186XL/80C188XL

1. An internal condition with the interrupt controller

can cause no acknowledge cycle on the INTA1

line in response to INT1. This errata only occurs

when Interrupt 1 is configured in cascade mode

and a higher priority interrupt exists. This errata

will not occur consistently, it is dependent on in-

terrupt timing.

REVISION HISTORY

This data sheet replaces the following data sheets:

272031-002 80C186XL

#

270975-002 80C188XL

272309-001 SB80C186XL

272310-001 SB80C188XL

#

The C step 80C186XL/80C188XL has no known er-

rata. The C step can be identified by the presence of

a ‘‘C’’ or ‘‘D’’ alpha character next to the FPO num-

ber. The FPO number location is shown in Figure 4.

ERRATA

An A or B step 80C186XL/80C188XL has the follow-

ing errata. The A or B step 80C186XL/80C188XL

can be identified by the presence of an ‘‘A’’ or ‘‘B’’

alpha character, respectively, next to the FPO num-

ber. The FPO number location is shown in Figure 4.

PRODUCT IDENTIFICATION

Intel 80C186XL devices are marked with a 9-charac-

ter alphanumeric Intel FPO number underneath the

product number. This data sheet (272431-001) is

valid for devices with an ‘‘A’’, ‘‘B’’, ‘‘C’’, or ‘‘D’’ as

the ninth character in the FPO number, as illustrated

in Figure 4.

48


型号：	80C186XL
厂家：	INTEL
描述：	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS 16位高集成嵌入式处理器
文件：	总48页 (文件大小：561K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

80C186XL [INTEL]

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