82801AB_技术文档

®

Intel 82801AA (ICH) and Intel

82801AB (ICH0) I/O Controller

Hub

Datasheet

June 1999

Order Number: 290655-002

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

The Intel^®82801AA (ICH) and Intel^®82801AB (ICH0) may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available upon request.

I²C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I²C bus/protocol and was developed by Intel.

Implementations of the I²C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and

North American Philips Corporation.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:

calling 1-800-548-4725 or

by visiting Intel's website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

ii

82801AA and 82801AB Datasheet

®

Intel 82801AA (I CH) and Intel 82801AB (ICH0)

Features

■ PCI Bus Interface

■ GPIO

— TTL, Open-Drain, Inversion

— Supports PCI at 33 MHz

— Supports PCI Rev 2.2 Specification

— 133 MByte/sec Maximum Throughput

■ Power Management Logic

— ACPI 1.0 Compliant

— Support for APM-Based Legacy Power

Management for Non-ACPI Implementations

— ACPI Defined Power States (S1, S3, S4, S5)

— ACPI Power Management Timer

— SMI# Generation

— All Registers Readable/Restorable for Proper

Resume from 0 V Suspend States

— PCI PME#

— Master PCI Device Support: up to 6 for the

ICH and up to 4 for the ICH0

■ Integrated IDE Controller

— Independent Timing of Up to 4 Drives

— The ICH Supports Ultra ATA/66 Mode (66

Mbytes/sec)

— Supports Ultra ATA/33 Mode

(33 Mbytes/sec)

■ Low Pin count (LPC) Interface

— Allows Connection of Legacy ISA and

X-Bus Devices such as Super I/O

— PIO Mode 4 Transfers up to 14 Mbytes/s

— Separate IDE Connections for Primary and

Secondary Cables

— Implements Write Ping-Pong Buffer for

faster write performance

— Supports Two Master/DMA Devices.

■ Enhanced DMA Controller

— Two Cascaded 8237 DMA Controllers

■ USB

— PCI DMA: Supports PC/PCI — Includes

Two PC/PCI REQ#/GNT# Pairs

— Supports LPC DMA

— UHCI Implementation With 2 Ports

— Supports Wake-up From Sleeping States

S1-S4

— Supports DMA Collection Buffer to Provide

Type-F DMA Performance for All DMA

Channels

— Supports Legacy Keyboard/Mouse Software

— USB Revision 1.1 Compliant

■ AC'97 Link for Audio and Telephony CODECs

■ Real - Time Clock

— AC’97 2.1 Compliant

— 256-byte Battery-Backed CMOS RAM

— Hardware implementation to indicate

Century Rollover

— 5 Independent Bus Master Logic for PCM In,

PCM Out, Mic Input, Modem In, Modem

Out

■ System TCO Reduction Circuits

— Timers to Generate SMI# and Reset Upon

Detection of locked system

— Separate Independent PCI Functions for

Audio and Modem

— Supports wake-up events

— Timers to Detect Improper Processor Reset

— Integrated Processor Frequency Strap Logic

■ Interrupt Controller

— Two Cascaded 82C59

■ SM Bus

— Integrated I/O APIC Capability

— 15 Interrupts Support in 8259 Mode, 24

Supported in I/O APIC Mode.

— Host Interface Allows Processor to

Communicate via SM Bus

— Compatible With Most 2-Wire Components

that are Also I²C compatible

— Supports Serial Interrupt Protocol

■ Timers Based on 82C54

■ Supports ISA Bus via External PCI-ISA Bridge

■ Firmware Hub (FWH) Interface

■ System Timer, Refresh Request, Speaker Tone

Output

■ 3.3 V Operation With 5 V Tolerant Buffers for

■ The 82801AA provides Alert On LAN*

IDE and PCI signals.

Support

■ 241 BGA package

This datasheet describes the Intel^®82801AA and Intel^®82801AB components. Non-shaded areas

describe the functionality of both components.

Shading,as is shown here, indicates differences between the two components.

The Intel^®82801AA and Intel^®82801AB may contain design defects or errors known as errata which may cause the

products to deviate from published specifications. Current characterized errata are available on request.

82801AA and 82801AB Datasheet

iii

Intel^®82801AA (ICH) and Intel^®82801AB (ICH0) Simplified Block Diagram

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

PDCS1#

SDCS1#

PDCS3#

SDCS3#

PDA[2:0]

SDA[2:0]

PDD[15:0]

SDD[15:0]

PDDREQ

SDDREQ

PDDACK#

SDDACK#

PDIOR#

IDE

Interface

TRDY#

STOP#

PAR

(ICH)

/GPIO7

PERR#

REQ[0:3]#

(ICH)

PCI

Interface

REQ[4]#

(ICH) REQ5#/REQB#/GPIO1

REQA#

GNT[0:3]#

(ICH) GNT[4]#

(ICH) GNT5#/GNTB#/GPIO17

GNTA#

SDIOR#

PDIOW#

SDIOW#

PIORDY

SIORDY

PCICLK

PCIRST#

PLOCK#

SERR#

PME#

THRM#

SLP_S3/GPIO24

SLP_S5#

PWROK

Power

Mgnt

PWRBTN#

RI#

RSMRST#

SUS_STAT#

SUSCLK/GPIO26 (ICH)

A20M#

CPUSLP#

FERR#

IGNNE#

INIT#

/GPIO25

CPU

Interface

INTR

AC_RST#

NMI

AC_SYNC

SMI#

STPCLK#

RCIN#

AC'97

Link

AC_BIT_CLK

AC_SDOUT

AC_SDIN0

AC_SDIN1/GPIO9

A20GATE

SERIRQ

PIRQ[A:D]#

IRQ[14:15]

APICCLK

HL[10:0] (ICH0); HL11:0] (ICH)

HL_STB

HL_STB#

Hub

Interface

Interrupt

USB

HLCOMP

APICD[1:0]

Firmware

Hub

USBP1P

USBP1N

USBP0P

USBP0N

OC[1:0]#

FWH[3:0]/LAD[3:0]

FWH[4]/LFRAME#

LAD[3:0]/FWH[4]

LPC

Interface

/FWH[4]

LFRAME#

LDRQ[0]#

LDRQ[1]#

RTCX1

RTCX2

VBIAS

/GPIO[8]

RTC

SMBDATA

SMBCLK

SMBus

Interface

/GPIO[11]

SMBALERT#

CLK14

CLK48

CLK66

Clocks

INTRUDER#

ALERTCLK/GPIO[27] (ICH)

ALERTDATA/GPIO[28] (ICH)

SPKR

RTCRST#

Misc.

Signals

System

Mgnt

GPIO[0,1,5:13]

GPIO[16,17, 21:26]

GPIO[27:28]

General

Purpose

I/O

Note

1. Shaded areas: PERR#, REQ[4,5]#, GNT[4,5]#, HL[11], SUSCLK, ALERTCLK, and ALERTDATA are ICH

(82801AA) Signals only. The associated GPIOx signals are multiplexed on the ICH and are

non-multiplexed on ICH0.

2. General Purpose I/O Unit. Some GPIO signals are multiplexed with signals in other functional units.

iv

82801AA and 82801AB Datasheet

System Block Diagram

Processor

Host

Controller

Main

Memory

Graphics

Controller¹

Hub Interface

PCI Slots

SMBus

Device(s)

SMBus

PCI Bus

I/O Controller Hub

AC'97 Codec(s)

(optional)

PCI Agent

AC'97 2.1

ISA Bridge

(optional)

- 82801AB (ICH0)

or

- 82801AA (ICH)

ATA/66 for ICH

ATA/33 for ICH0

LPC I/F

4 IDE Drives

2xUSB

GPIO

Super I/O

(required)

Keyboard, Mouse,

FD, PP, SP, IR

FWH

Note:

1. The 82801AB ICH0 is intended to be used with the Intel^®82810 Graphics and Memory

Controller (GMCH) as the Host Controller. The graphics controller is integrated on the GMCH.

82801AA and 82801AB Datasheet

v

Contents

1

Introduction................................................................................................................1-1

1.1

1.2

About this Manual.........................................................................................1-1

Overview.......................................................................................................1-3

2

Signal Description......................................................................................................2-1

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Hub Interface ................................................................................................2-1

Firmware Hub Interface ................................................................................2-1

PCI Interface.................................................................................................2-2

IDE Interface.................................................................................................2-4

Low Pin Count (LPC) Interface.....................................................................2-5

Interrupt Interface .........................................................................................2-6

USB Interface ...............................................................................................2-6

Power Management Interface.......................................................................2-7

Processor Interface.......................................................................................2-8

SMBus Interface ...........................................................................................2-9

System Management Interface.....................................................................2-9

Real Time Clock Interface ............................................................................2-9

Other Clocks...............................................................................................2-10

Miscellaneous Signals ................................................................................2-10

AC’97 Link ..................................................................................................2-10

General Purpose I/O...................................................................................2-11

Power and Ground......................................................................................2-12

Pin Straps ...................................................................................................2-12

2.18.1 Functional Strap.............................................................................2-12

2.18.2 Test Straps ....................................................................................2-13

2.18.3 External RTC Circuitry...................................................................2-13

2.18.4 5VREF / Vcc3_3 Sequencing Requirements.................................2-14

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

2.17

2.18

3

Power Planes and Pin States ....................................................................................3-1

3.1

3.2

3.3

3.4

3.5

Power Planes................................................................................................3-1

Output and I/O Signal Planes and States.....................................................3-1

Power Planes for Input Signals.....................................................................3-4

Integrated Pull-Ups and Pull-Downs.............................................................3-5

IDE Integrated Series Termination Resistors ...............................................3-5

4

5

Clock Domains...........................................................................................................4-1

Functional Description ...............................................................................................5-1

5.1

Hub Interface to PCI Bridge (D30:F0)...........................................................5-1

5.1.1 PCI Bus Interface.............................................................................5-1

5.1.2 PCI-to-PCI Bridge Model .................................................................5-1

5.1.3 IDSEL to Device Number Mapping..................................................5-2

5.1.4 SERR#/PERR#/NMI# Functionality.................................................5-2

vi

82801AA and 82801AB Datasheet

5.2

LPC Bridge (with System & Management Functions) (D31:F0)....................5-4

5.2.1 LPC Interface...................................................................................5-4

5.2.1.1 LPC Cycle Types..............................................................5-5

5.2.1.2 Start Field Definition .........................................................5-5

5.2.1.3 Cycle Type / Direction (CYCTYPE + DIR)........................5-6

5.2.1.4 SIZE..................................................................................5-6

5.2.1.5 SYNC................................................................................5-6

5.2.1.6 SYNC Time-out ................................................................5-7

5.2.1.7 SYNC Error Indication ......................................................5-7

5.2.1.8 LFRAME# Usage..............................................................5-7

5.2.1.9 I/O Cycles.........................................................................5-9

5.2.1.10 Bus Master Cycles............................................................5-9

5.2.1.11 Configuration and ICH Implications..................................5-9

DMA Operation (D31:F0)..............................................................................5-9

5.3.1 Channel Priority .............................................................................5-10

5.3.2 Address Compatibility Mode ..........................................................5-11

5.3.3 Summary of DMA Transfer Sizes ..................................................5-11

5.3.4 Autoinitialize...................................................................................5-12

5.3.5 Software Commands .....................................................................5-12

PCI DMA.....................................................................................................5-13

5.4.1 PCI DMA Expansion Protocol........................................................5-13

5.4.2 PCI DMA Expansion Cycles ..........................................................5-14

5.4.3 DMA Addresses.............................................................................5-15

5.4.4 DMA Data Generation....................................................................5-15

5.4.5 DMA Byte Enable Generation........................................................5-15

5.4.6 DMA Cycle Termination.................................................................5-16

LPC DMA....................................................................................................5-16

5.5.1 Asserting DMA Requests...............................................................5-16

5.5.2 Abandoning DMA Requests...........................................................5-17

5.5.3 General Flow of DMA Transfers ....................................................5-17

5.5.4 Terminal Count ..............................................................................5-18

5.5.5 Verify Mode....................................................................................5-18

5.5.6 DMA Request Deassertion ............................................................5-18

5.5.7 SYNC Field / LDRQ# Rules...........................................................5-19

8254 Timers (D31:F0).................................................................................5-20

5.6.1 Timer Programming .......................................................................5-20

5.6.2 Reading from the Interval Timer ....................................................5-21

8259 Interrupt Controllers (PIC) (D31:F0)...................................................5-23

5.7.1 Interrupt Handling ..........................................................................5-23

5.7.2 Initialization Command Words (ICWx)...........................................5-25

5.7.3 Operation Command Words (OCW)..............................................5-26

5.7.4 Modes of Operation .......................................................................5-26

5.7.5 Masking Interrupts .........................................................................5-29

5.7.6 Steering PCI Interrupts ..................................................................5-29

Advanced Interrupt Controller (APIC) (D31:F0)..........................................5-30

5.8.1 Interrupt Handling ..........................................................................5-30

5.8.2 Interrupt Mapping...........................................................................5-30

5.8.3 APIC Bus Functional Description...................................................5-31

5.8.3.1 Physical Characteristics of APIC....................................5-31

5.8.3.2 APIC Bus Arbitration.......................................................5-31

5.8.3.3 Bus Message Formats....................................................5-32

5.3

5.4

5.5

5.6

5.7

5.8

82801AA and 82801AB Datasheet

vii

5.9

Serial Interrupt (D31:F0).............................................................................5-37

5.9.1 Start Frame....................................................................................5-37

5.9.2 Data Frames..................................................................................5-37

5.9.3 Stop Frame....................................................................................5-38

5.9.4 Specific Interrupts not Supported via SERIRQ..............................5-38

5.9.5 Data Frame Format .......................................................................5-39

Real Time Clock (D31:F0) ..........................................................................5-40

5.10.1 Update Cycles ...............................................................................5-40

5.10.2 Interrupts........................................................................................5-41

5.10.3 Lockable RAM Ranges..................................................................5-41

5.10.4 Century Rollover............................................................................5-41

5.10.5 Clearing Battery-Backed RTC RAM...............................................5-41

Processor Interface (D31:F0) .....................................................................5-43

5.11.1 Processor Interface Signals...........................................................5-43

5.11.2 Dual Processor Issues (ICH: 82801AA only).................................5-45

5.11.2.1 Signal Differences (ICH: 82801AA only) ........................5-45

5.11.2.2 Power Management (ICH: 82801AA only) .....................5-45

5.11.3 Speed Strapping for Processor......................................................5-46

Power Management (D31:F0) ....................................................................5-47

5.12.1 ICH and System Power States ......................................................5-47

5.12.2 System Power Planes....................................................................5-48

5.12.3 SMI#/SCI Generation.....................................................................5-49

5.12.4 Dynamic System Clock Control .....................................................5-50

5.12.4.1 Entering/Exiting the C1 State .........................................5-50

5.12.4.2 Entering/Exiting the C2 State .........................................5-51

5.12.4.3 Throttling Using STPCLK# .............................................5-51

5.12.4.4 Transition Rules Among S0/Cx and Throttling States....5-52

5.12.5 Sleep States ..................................................................................5-52

5.12.5.1 Sleep State Overview.....................................................5-52

5.12.5.2 Initiating Sleep State ......................................................5-52

5.12.5.3 Exiting Sleep States .......................................................5-53

5.12.5.4 Sx-G3-Sx, Handling Power Failures...............................5-54

5.12.6 Thermal Management....................................................................5-55

5.12.6.1 THRM# Signal................................................................5-55

5.12.6.2 THRM# Initiated Passive Cooling...................................5-55

5.12.6.3 Processor Initiated Passive Cooling

5.10

5.11

5.12

(Via Programmed Duty Cycle on STPCLK#)..................5-56

5.12.6.4 Active Cooling ................................................................5-56

5.12.7 Event Input Signals and Their Usage ............................................5-56

5.12.7.1 PWRBTN#—Power Button.............................................5-56

5.12.7.2 RI#—Ring Indicate .........................................................5-57

5.12.7.3 PME#—PCI Power Management Event.........................5-57

5.12.8 Alt Access Mode ............................................................................5-57

5.12.8.1 Write Only Registers with Read Paths in

Alternate Access Mode5-58

5.12.8.2 PIC Reserved Bits..........................................................5-59

5.12.8.3 Read Only Registers with Write Paths in

Alternate Access Mode ..................................................5-60

5.12.9 System Power Supplies, Planes, and Signals...............................5-60

5.12.10 Clock Generators...........................................................................5-61

5.12.11 Legacy Power Management Theory of Operation .........................5-61

viii

82801AA and 82801AB Datasheet

5.13

5.14

System Management (D31:F0)...................................................................5-62

5.13.1 Overview of System Management Functions ................................5-62

5.13.2 Theory of Operation.......................................................................5-62

5.13.2.1 Handling an ECC Error or Other Memory Error..............5-63

5.13.3 Alert on LAN* (ICH: 82801AA only) ...............................................5-63

IDE Controller (D31:F1) ..............................................................................5-66

5.14.1 PIO Transfers.................................................................................5-67

5.14.1.1 PIO IDE Timing Modes...................................................5-67

5.14.1.2 IORDY Masking..............................................................5-68

5.14.1.3 PIO 32 Bit IDE Data Port Accesses................................5-68

5.14.1.4 PIO IDE Data Port Prefetching and Posting...................5-68

5.14.2 Bus Master Function......................................................................5-68

5.14.2.1 Physical Region Descriptor Format................................5-68

5.14.2.2 Line Buffer ......................................................................5-69

5.14.2.3 Bus Master IDE Timings.................................................5-69

5.14.2.4 Interrupts ........................................................................5-70

5.14.2.5 Bus Master IDE Operation..............................................5-70

5.14.2.6 Error Conditions..............................................................5-71

5.14.2.7 8237 Like Protocol..........................................................5-71

5.14.3 Ultra ATA/33 Protocol ....................................................................5-72

5.14.3.1 Signal Descriptions.........................................................5-72

5.14.3.2 Operation........................................................................5-73

5.14.3.3 CRC Calculation.............................................................5-73

5.14.3.4 Synchronous DMA Timings............................................5-73

5.14.3.5 Ultra ATA/66 (ICH: 82801AA only).................................5-74

USB Controller (Device 31:Function 2).......................................................5-74

5.15.1 Data Structures in Main memory ...................................................5-75

5.15.1.1 Frame List Pointer ..........................................................5-75

5.15.1.2 Transfer Descriptor (TD).................................................5-76

5.15.1.3 Queue Head (QH) ..........................................................5-80

5.15.2 Data Transfers To/From Main Memory..........................................5-81

5.15.2.1 Executing the Schedule..................................................5-81

5.15.2.2 Processing Transfer Descriptors ....................................5-81

5.15.2.3 Command Register, Status Register, and

5.15

TD Status Bit Interaction.................................................5-82

5.15.2.4 Transfer Queuing............................................................5-83

5.15.3 Data Encoding and Bit Stuffing......................................................5-86

5.15.4 Bus Protocol...................................................................................5-86

5.15.4.1 Bit Ordering ....................................................................5-86

5.15.4.2 SYNC Field.....................................................................5-86

5.15.4.3 Packet Field Formats......................................................5-87

5.15.4.4 Address Fields................................................................5-88

5.15.4.5 Frame Number Field.......................................................5-88

5.15.4.6 Data Field .......................................................................5-88

5.15.4.7 Cyclic Redundancy Check (CRC) ..................................5-88

5.15.5 Packet Formats..............................................................................5-89

5.15.5.1 Token Packets................................................................5-89

5.15.5.2 Start of Frame Packets...................................................5-89

5.15.5.3 Data Packets ..................................................................5-90

5.15.5.4 Handshake Packets........................................................5-90

5.15.5.5 Handshake Responses ..................................................5-90

82801AA and 82801AB Datasheet

ix

5.15.6 USB Interrupts ...............................................................................5-91

5.15.6.1 Transaction Based Interrupts .........................................5-91

5.15.6.2 Non-Transaction Based Interrupts .................................5-93

5.15.7 USB Power Management ..............................................................5-94

5.15.8 USB Legacy Keyboard Operation..................................................5-94

SMBus Controller Functional Description (D31:F3)....................................5-97

5.16.1 Host Controller...............................................................................5-97

5.16.1.1 Command Protocols.......................................................5-97

5.16.1.2 I²C Behavior.................................................................5-104

5.16.2 Bus Arbitration .............................................................................5-105

5.16.3 Interrupts / SMI# ..........................................................................5-105

5.16.4 SMBALERT# ...............................................................................5-105

ICH AC’97 2.1 Functional Description ......................................................5-106

5.17.1 AC-link Overview .........................................................................5-108

5.17.2 AC-link Output Frame (SDOUT)..................................................5-110

5.17.3 AC-link Input Frame (SDIN).........................................................5-112

5.17.4 Register Access...........................................................................5-114

AC-Link Low Power Mode ........................................................................5-115

5.18.1 External Wake Event ...................................................................5-116

5.18.2 AC‘97 Cold Reset ........................................................................5-116

5.18.3 AC‘97 Warm Reset......................................................................5-116

5.18.4 System Reset ..............................................................................5-117

5.16

5.17

5.18

6

Register and Memory Mapping..................................................................................6-1

6.1

6.2

6.3

PCI Devices and Functions ..........................................................................6-2

6.1.1 PCI Configuration Map ....................................................................6-2

6.1.2 Standard PCI Bus Configuration Mechanism ..................................6-3

I/O Map.........................................................................................................6-4

6.2.1 Fixed I/O Address Ranges...............................................................6-4

6.2.2 Variable I/O Decode Ranges...........................................................6-6

Memory Map.................................................................................................6-7

7

Hub Interface-to-PCI Bridge Registers (D30:F0).......................................................7-1

7.1

PCI Configuration Registers (D30:F0)..........................................................7-1

7.1.1 VID—Vendor ID Register (HUB-PCI—D30:F0)...............................7-2

7.1.2 DID—Device ID Register (HUB-PCI—D30:F0)................................7-2

7.1.3 CMD—Command Register (HUB-PCI—D30:F0).............................7-3

7.1.4 PD_STS—Primary Device Status Register

(HUB-PCI—D30:F0)7-4

7.1.5 RID—Revision ID Register (HUB-PCI—D30:F0).............................7-5

7.1.6 SCC—Sub-Class Code Register (HUB-PCI—D30:F0)....................7-5

7.1.7 BCC—Base-Class Code Register (HUB-PCI—D30:F0)..................7-5

7.1.8 PMLT—Primary Master Latency Timer Register

(HUB-PCI—D30:F0) ........................................................................7-5

7.1.9 HEADTYP—Header Type Register (HUB-PCI—D30:F0)................7-6

7.1.10 PBUS_NUM—Primary Bus Number Register

(HUB-PCI—D30:F0)7-6

7.1.11 SBUS_NUM—Secondary Bus Number Register

(HUB-PCI—D30:F0) ........................................................................7-6

7.1.12 SUB_BUS_NUM—Subordinate Bus Number Register

(HUB-PCI—D30:F0) ........................................................................7-6

x

82801AA and 82801AB Datasheet

7.1.13 SMLT—Secondary Master Latency Timer Register

(HUB-PCI—D30:F0) ........................................................................7-7

7.1.14 IOBASE—I/O Base Register (HUB-PCI—D30:F0)..........................7-7

7.1.15 IOLIM—I/O Limit Register (HUB-PCI—D30:F0) ..............................7-7

7.1.16 SECSTS—Secondary Status Register (HUB-PCI—D30:F0)...........7-8

7.1.17 MEMBASE—Memory Base Register (HUB-PCI—D30:F0) .............7-9

7.1.18 MEMLIM—Memory Limit Register (HUB-PCI—D30:F0) .................7-9

7.1.19 PREF_MEM_BASE—Prefetchable Memory Base Register

(HUB-PCI—D30:F0) ........................................................................7-9

7.1.20 PREF_MEM_MLT—Prefetchable Memory Limit Register

(HUB-PCI—D30:F0) ......................................................................7-10

7.1.21 IOBASE_HI—I/O Base Upper 16 Bits Register

(HUB-PCI—D30:F0) ......................................................................7-10

7.1.22 IOLIM_HI—I/O Limit Upper 16 Bits Register

(HUB-PCI—D30:F0) ......................................................................7-10

7.1.23 INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0) ..............7-10

7.1.24 BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0) .....7-11

7.1.25 CNF—ICH Configuration Register (HUB-PCI—D30:F0) ...............7-12

7.1.26 MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0) ......7-13

7.1.27 PCI_MAST_STS—PCI Master Status Register

(HUB-PCI—D30:F0) ......................................................................7-13

7.1.28 ERR_CMD—Error Command Register (HUB-PCI—D30:F0)........7-14

7.1.29 ERR_STS—Error Status Register (HUB-PCI—D30:F0)................7-14

8

LPC Interface Bridge Registers (D31:F0) ..................................................................8-1

8.1

PCI Configuration Registers (D31:F0) ..........................................................8-1

8.1.1 VID—Vendor ID Register (LPC I/F—D31:F0)..................................8-2

8.1.2 DID—Device ID Register (LPC I/F—D31:F0) ..................................8-2

8.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)................8-3

8.1.4 PCISTA—PCI Device Status (LPC I/F—D31:F0) ............................8-4

8.1.5 RID—Revision ID Register (LPC I/F—D31:F0) ...............................8-5

8.1.6 PI—Programming Interface (LPC I/F—D31:F0) ..............................8-5

8.1.7 SCC—Sub-Class Code Register (LPC I/F—D31:F0) ......................8-5

8.1.8 BCC—Base-Class Code Register (LPC I/F—D31:F0) ....................8-5

8.1.9 HEADTYP—Header Type Register (LPC I/F—D31:F0) ..................8-5

8.1.10 PMBASE—ACPI Base Address (LPC I/F—D31:F0)........................8-6

8.1.11 ACPI_CNTL—ACPI Control (LPC I/F — D31:F0)............................8-6

8.1.12 BIOS_CNTL (LPC I/F—D31:F0)......................................................8-7

8.1.13 TCO_CNTL — TCO Control (LPC I/F — D31:F0) ...........................8-7

8.1.14 GPIOBASE—GPIO Base Address (LPC I/F—D31:F0) ...................8-8

8.1.15 GPIO_CNTL—GPIO Control (LPC I/F—D31:F0) ............................8-8

8.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control

(LPC I/F—D31:F0)...........................................................................8-9

8.1.17 SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)................8-9

8.1.18 D31_ERR_CFG—Device 31 Error Config Register

(LPC I/F—D31:F0).........................................................................8-10

8.1.19 D31_ERR_STS—Device 31 Error Status Register

(LPC I/F—D31:F0).........................................................................8-10

8.1.20 PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0) .....8-11

8.1.21 GEN_CNTL — General Control Register (LPC I/F — D31:F0) .....8-11

8.1.22 GEN_STA—General Status (LPC I/F—D31:F0)............................8-13

8.1.23 RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0).....8-14

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xi

8.1.24 COM_DEC—LPC I/F Communication Port Decode Ranges

(LPC I/F—D31:F0).........................................................................8-14

8.1.25 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges

(LPC I/F—D31:F0).........................................................................8-15

8.1.26 SND_DEC—LPC I/F Sound Decode Ranges

(LPC I/F—D31:F0).........................................................................8-15

8.1.27 GEN1_DEC—LPC I/F Generic Decode Range 1

(LPC I/F—D31:F0).........................................................................8-16

8.1.28 GEN2_DEC—LPC I/F Generic Decode Range 2

(LPC I/F—D31:F0).........................................................................8-16

8.1.29 LPC_EN—LPC I/F Enables (LPC I/F—D31:F0)............................8-17

8.1.30 FWH_DEC_EN—FWH Decode Enable Register

(LPC I/F—D31:F0).........................................................................8-18

8.1.31 FWH_SEL—FWH Select Register (LPC I/F—D31:F0)..................8-19

8.1.32 FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) .........8-20

DMA I/O Registers......................................................................................8-21

8.2.1 DMABASE_CA—DMA Base and Current Address Registers.......8-22

8.2.2 DMABASE_CC—DMA Base and Current Count Registers...........8-23

8.2.3 DMAMEM_LP—DMA Memory Low Page Registers .....................8-23

8.2.4 DMACMD—DMA Command Register ...........................................8-24

8.2.5 DMASTA—DMA Status Register...................................................8-24

8.2.6 DMA_WRSMSK—DMA Write Single Mask Register.....................8-25

8.2.7 DMACH_MODE—DMA Channel Mode Register...........................8-25

8.2.8 DMA Clear Byte Pointer Register ..................................................8-26

8.2.9 DMA Master Clear Register...........................................................8-26

8.2.10 DMA_CLMSK—DMA Clear Mask Register ...................................8-26

8.2.11 DMA_WRMSK—DMA Write All Mask Register .............................8-27

Timer I/O Registers.....................................................................................8-28

8.3.1 TCW—Timer Control Word Register .............................................8-28

8.3.1.1 RDBK_CMD—Read Back Command ............................8-29

8.3.1.2 LTCH_CMD—Counter Latch Command........................8-30

8.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register..........8-30

8.3.3 Counter Access Ports Register......................................................8-31

8259 Interrupt Controller (PIC) Registers ...................................................8-32

8.4.1 Interrupt Controller I/O MAP ..........................................................8-32

8.4.2 ICW1—Initialization Command Word 1 Register...........................8-33

8.4.3 ICW2—Initialization Command Word 2 Register...........................8-34

8.4.4 ICW3—Master Controller Initialization Command

8.2

8.3

8.4

Word 3 Register.............................................................................8-34

8.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register.............................................................................8-35

8.4.6 ICW4—Initialization Command Word 4 Register...........................8-35

8.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register....8-35

8.4.8 OCW2—Operational Control Word 2 Register ..............................8-36

8.4.9 OCW3—Operational Control Word 3 Register ..............................8-37

8.4.10 ELCR1—Master Controller Edge/Level Triggered Register ..........8-38

8.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............8-38

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82801AA and 82801AB Datasheet

8.5

Advanced Interrupt Controller (APIC) .........................................................8-39

8.5.1 APIC Register Map ........................................................................8-39

8.5.2 IND—Index Register......................................................................8-39

8.5.3 DAT—Data Register ......................................................................8-40

8.5.4 ID—Identification Register .............................................................8-40

8.5.5 VER—Version Register .................................................................8-40

8.5.6 ARBID—Arbitration ID Register.....................................................8-41

8.5.7 Redirection Table...........................................................................8-41

8.5.8 IRQPA—IRQ Pin Assertion Register .............................................8-43

8.5.9 EOIR—EOI Register......................................................................8-43

Real Time Clock Registers .........................................................................8-44

8.6.1 I/O Register Address Map..............................................................8-44

8.6.2 Indexed Registers..........................................................................8-45

8.6.2.1 RTC_REGA—Register A................................................8-46

8.6.2.2 RTC_REGB—Register B (General Configuration).........8-47

8.6.2.3 RTC_REGC—Register C (Flag Register) ......................8-48

8.6.2.4 RTC_REGD—Register D (Flag Register) ......................8-48

Processor Interface Registers.....................................................................8-49

8.7.1 NMI_SC—NMI Status and Control Register..................................8-49

8.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) ....................8-50

8.7.3 PORT92—Fast A20 and Init Register............................................8-50

8.7.4 COPROC_ERR—Coprocessor Error Register ..............................8-50

8.7.5 RST_CNT—Reset Control Register ..............................................8-51

Power Management Registers (D31:F0) ....................................................8-52

8.8.1 Power Management PCI Configuration Registers (D31:F0)..........8-52

8.8.1.1 GEN_PMCON_1—General PM Configuration 1

8.6

8.7

8.8

Register (PM—D31:F0)..................................................8-52

8.8.1.2 GEN_PMCON_2—General PM Configuration 2

Register (PM—D31:F0)..................................................8-53

8.8.1.3 GEN_PMCON_3—General PM Configuration 3

Register (PM—D31:F0)..................................................8-53

8.8.1.4 GPI_ROUT—GPI Routing Control Register

(PM—D31:F0) ................................................................8-54

8.8.1.5 IO_MON_RNG1—IO Monitor Range 1 Register

(PM—D31:F0) ................................................................8-54

8.8.1.6 IO_MON_RNG2—IO Monitor Range 2 Register

(PM—D31:F0) ................................................................8-55

8.8.1.7 IO_MON_MSK—IO Monitor Range Mask Register

(PM—D31:F0) ................................................................8-55

8.8.2 APM I/O Decode............................................................................8-56

8.8.2.1 APM_CNT—Advanced Power Management

Control Port Register......................................................8-56

8.8.2.2 APM_STS—Advanced Power Management

Status Port Register .......................................................8-56

82801AA and 82801AB Datasheet

xiii

8.8.3 Power Management I/O Registers.................................................8-57

8.8.3.1 PM1_STS—Power Management 1 Status Register.......8-58

8.8.3.2 PM1_EN—Power Management 1 Enables Register......8-59

8.8.3.3 PM1_CNT—Power Management 1 Control ...................8-60

8.8.3.4 PM1_TMR—Power Management 1 Timer Register.......8-60

8.8.3.5 PROC_CNT—Processor Control Register.....................8-61

8.8.3.6 LV2 — Level 2 Register .................................................8-62

8.8.3.7 GPE0_STS—General Purpose Event 0 Status

Register..........................................................................8-62

8.8.3.8 GPE0_EN—General Purpose Event 0 Enables

Register..........................................................................8-63

8.8.3.9 GPE1_STS—General Purpose Event 1

Status Register...............................................................8-64

8.8.3.10 GPE1_EN—General Purpose Event 1

Enable Register..............................................................8-65

8.8.3.11 SMI_EN—SMI Control and Enable Register..................8-65

8.8.3.12 SMI_STS—SMI Status Register ....................................8-66

8.8.3.13 IOMON_STS_EN — I/O Monitor Status and

Enable Register..............................................................8-67

8.8.3.14 DEVACT_STS — Device Activity Status Register .........8-68

8.8.3.15 BUS_ADDR_TRACK— Bus Address Tracker ...............8-69

8.8.3.16 BUS_CYC_TRACK— Bus Cycle Tracker ......................8-69

System Management TCO Registers (D31:F0)..........................................8-70

8.9.1 TCO Register I/O Map...................................................................8-70

8.9.2 TCO1_RLD—TCO Timer Reload and Current Value ....................8-70

8.9.3 TCO1_TMR—TCO Timer Initial Value...........................................8-70

8.9.4 TCO1_DAT_IN—TCO Data In Register ........................................8-71

8.9.5 TCO1_DAT_OUT—TCO Data Out Register..................................8-71

8.9.6 TCO1_STS—TCO1 Status Register..............................................8-71

8.9.7 TCO2_STS—TCO2 Status Register..............................................8-72

8.9.8 TCO1_CNT—TCO1 Control Register............................................8-73

8.9.9 TCO2_CNT—TCO2 Control Register............................................8-73

8.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers

8.9

(ICH 82801AA only).......................................................................8-74

8.9.11 TCO_WDSTATUS—TCO2 Control Register

(ICH 82801AA only).......................................................................8-74

General Purpose I/O Registers (D31:F0) ...................................................8-75

8.10.1 GPIO Register I/O Address Map....................................................8-78

8.10.2 GPIO_USE_SEL—GPIO Use Select Register ..............................8-79

8.10.3 GP_IO_SEL—GPIO Input/Output Select Register ........................8-80

8.10.4 GP_LVL—GPIO Level for Input or Output Register.......................8-81

8.10.5 GPO_TTL—GPIO TTL Select Register.........................................8-81

8.10.6 GPO_BLINK—GPO Blink Enable Register....................................8-82

8.10.7 GPI_INV—GPIO Signal Invert Register.........................................8-82

8.10

xiv

82801AA and 82801AB Datasheet

9

IDE Controller Registers (D31:F1).............................................................................9-1

9.1

PCI Configuration Registers (IDE—D31:F1).................................................9-1

9.1.1 VID—Vendor ID Register (IDE—D31:F1)........................................9-2

9.1.2 DID—Device ID Register (IDE—D31:F1) ........................................9-2

9.1.3 CMD—Command Register (IDE—D31:F1) .....................................9-2

9.1.4 STA—Device Status Register (IDE—D31:F1).................................9-3

9.1.5 RID—Revision ID Register (IDE—D31:F1)......................................9-3

9.1.6 PI—Programming Interface (IDE—D31:F1).....................................9-3

9.1.7 SCC—Sub Class Code (IDE—D31:F1)...........................................9-4

9.1.8 BCC—Base Class Code (IDE—D31:F1) .........................................9-4

9.1.9 MLT—Master Latency Timer (IDE—D31:F1)...................................9-4

9.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ..................9-4

9.1.11 BM_BASE—Bus Master Base Address Register

(IDE—D31:F1) .................................................................................9-5

9.1.12 SVID—Subsystem Vendor ID Register (IDE—D31:F1)...................9-5

9.1.13 SID—Subsystem ID Register (IDE—D31:F1)..................................9-5

9.1.14 IDE_TIM—IDE Timing Register (IDE—D31:F1) ..............................9-6

9.1.15 SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1) .................................................................................9-7

9.1.16 SDMA_CNT—Synchronous DMA Control Register

(IDE—D31:F1) .................................................................................9-8

9.1.17 SDMA_TIM—Synchronous DMA Timing Register

(IDE—D31:F1) .................................................................................9-9

9.1.18 IDE_CONFIG—IDE I/O Configuration Register.............................9-10

Bus Master IDE I/O Registers (D31:F1)......................................................9-11

9.2.1 BMIC[P,S]—Bus Master IDE Command Register .........................9-12

9.2.2 BMIS[P,S]—Bus Master IDE Status Register................................9-13

9.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register ...9-13

9.2

10

USB Controller Registers (D31:F2)..........................................................................10-1

10.1

PCI Configuration Registers (D31:F2) ........................................................10-1

10.1.1 VID—Vendor Identification Register (USB—D31:F2)....................10-2

10.1.2 DID—Device Identification Register (USB—D31:F2) ....................10-2

10.1.3 CMD—Command Register (USB—D31:F2)..................................10-2

10.1.4 STA—Device Status Register (USB—D31:F2)..............................10-3

10.1.5 RID—Revision Identification Register (USB—D31:F2)..................10-3

10.1.6 PI—Programming Interface (USB—D31:F2) .................................10-3

10.1.7 SCC—Sub Class Code Register (USB—D31:F2) .........................10-4

10.1.8 BCC—Base Class Code Register (USB—D31:F2) .......................10-4

10.1.9 HEADTYP—Header Type Register (USB—D31:F2).....................10-4

10.1.10 BASE—Base Address Register (USB—D31:F2)...........................10-4

10.1.11 SVID—Subsystem Vendor ID Register (USB—D31:F2) ...............10-5

10.1.12 SID—Subsystem ID Register (USB—D31:F2) ..............................10-5

10.1.13 INTR_LN—Interrupt Line Register (USB—D31:F2).......................10-5

10.1.14 INTR_PN—Interrupt Pin Register (USB—D31:F2)........................10-5

10.1.15 SB_RELNUM—Serial Bus Release Number Register

(USB—D31:F2)..............................................................................10-6

10.1.16 USB_LEGKEY—USB Legacy Keyboard/Mouse Control

Register (USB—D31:F2) ...............................................................10-6

10.1.17 USB_RES—USB Resume Enable Register (USB—D31:F2)........10-7

82801AA and 82801AB Datasheet

xv

10.2

USB I/O Registers ......................................................................................10-8

10.2.1 USBCMD—USB Command Register ............................................10-8

10.2.2 USBSTA—USB Status Register..................................................10-11

10.2.3 USBINTR—Interrupt Enable Register..........................................10-12

10.2.4 FRNUM—Frame Number Register..............................................10-12

10.2.5 FRBASEADD—Frame List Base Address...................................10-13

10.2.6 SOFMOD—Start of Frame Modify Register.................................10-13

10.2.7 PORTSC[0,1]—Port Status and Control Register........................10-14

11

SMBus Controller Registers (D31:F3) .....................................................................11-1

11.1

PCI Configuration Registers (SMBUS—D31:F3)........................................11-1

11.1.1 VID—Vendor Identification Register (SMBUS—D31:F3)...............11-2

11.1.2 DID—Device Identification Register (SMBUS—D31:F3)...............11-2

11.1.3 CMD—Command Register (SMBUS—D31:F3).............................11-2

11.1.4 STA—Device Status Register (SMBUS—D31:F3) ........................11-3

11.1.5 RID—Revision ID Register (SMBUS—D31:F3).............................11-3

11.1.6 PI—Programming Interface (SMBUS—D31:F3)............................11-3

11.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3)....................11-4

11.1.8 BCC—Base Class Code Register (SMBUS—D31:F3)..................11-4

11.1.9 HEADTYP—Header Type Register (SMBUS—D31:F3)................11-4

11.1.10 SMB_BASE—SMBus Base Address Register

(SMBUS—D31:F3) ........................................................................11-4

11.1.11 SVID—Subsystem Vendor ID Register (SMBUS—D31:F3)..........11-5

11.1.12 SID—Subsystem ID Register (SMBUS—D31:F3).........................11-5

11.1.13 INTR_LN—Interrupt Line Register (SMBUS—D31:F3) .................11-5

11.1.14 INTR_PN—Interrupt Pin Register (SMBUS—D31:F3) ..................11-5

11.1.15 HOSTC—Host Configuration Register (SMBUS—D31:F3)...........11-6

SMBus I/O Registers ..................................................................................11-6

11.2.1 HST_STA—Host Status Register..................................................11-7

11.2.2 HST_CNT—Host Control Register ................................................11-8

11.2.3 HST_CMD—Host Command Register...........................................11-9

11.2.4 XMIT_SLVA—Transmit Slave Address Register...........................11-9

11.2.5 D0—Data 0 Register......................................................................11-9

11.2.6 D1—Data 1 Register......................................................................11-9

11.2.7 BLOCK_DB—Block Data Byte Register......................................11-10

11.2

12

AC’97 Audio Controller Registers (D31:F5).............................................................12-1

12.1

AC’97 Audio PCI Configuration Space (D31:F5)........................................12-1

12.1.1 VID—Vendor Identification Register (Audio—D31:F5) ..................12-2

12.1.2 DID—Device Identification Register (Audio—D31:F5)...................12-2

12.1.3 PCICMD—PCI Command Register (Audio—D31:F5)...................12-2

12.1.4 PCISTA—PCI Device Status Register (Audio—D31:F5)...............12-3

12.1.5 RID—Revision Identification Register (Audio—D31:F5)................12-3

12.1.6 PI—Programming Interface Register (Audio—D31:F5).................12-3

12.1.7 SCC—Sub Class Code Register (Audio—D31:F5) .......................12-4

12.1.8 BCC—Base Class Code Register (Audio—D31:F5)......................12-4

12.1.9 HEADTYP—Header Type Register (Audio—D31:F5)...................12-4

12.1.10 NAMBAR—Native Audio Mixer Base Address Register

(Audio—D31:F5)............................................................................12-5

12.1.11 NABMBAR—Native Audio Bus Mastering Base Address

Register (Audio—D31:F5)..............................................................12-5

12.1.12 SVID—Subsystem Vendor ID Register (Audio—D31:F5)..............12-6

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82801AA and 82801AB Datasheet

12.1.13 SID—Subsystem ID Register (Audio—D31:F5).............................12-6

12.1.14 INTR_LN—Interrupt Line Register (Audio—D31:F5).....................12-6

12.1.15 INTR_PN—Interrupt Pin Register (Audio—D31:F5)......................12-7

AC’97 Audio I/O Space (D31:F5)................................................................12-7

12.2.1 x_BDBAR—Buffer Descriptor Base Address Register ................12-10

12.2.2 x_CIV—Current Index Value Register .........................................12-10

12.2.3 x_LVI—Last Valid Index Register ................................................12-10

12.2.4 x_SR—Status Register................................................................12-11

12.2.5 x_PICB—Position In Current Buffer Register ..............................12-12

12.2.6 x_PIV—Prefetched Index Value Register....................................12-12

12.2.7 x_CR—Control Register ..............................................................12-13

12.2.8 GLOB_CNT—Global Control Register.........................................12-14

12.2.9 GLOB_STA—Global Status Register ..........................................12-14

12.2.10 CAS—Codec Access Semaphore Register.................................12-16

12.2

13

AC ’97 Modem Controller Registers (D31:F6) .........................................................13-1

13.1

AC ’97 Modem PCI Configuration Space (D31:F6) ....................................13-1

13.1.1 VID—Vendor Identification Register (Modem—D31:F6) ...............13-2

13.1.2 DID—Device Identification Register (Modem—D31:F6)................13-2

13.1.3 PCICMD—PCI Command Register (Modem—D31:F6) ................13-2

13.1.4 PCISTA—Device Status Register (Modem—D31:F6)...................13-3

13.1.5 RID—Revision Identification Register (Modem—D31:F6).............13-3

13.1.6 PI—Programming Interface Register (Modem—D31:F6) ..............13-3

13.1.7 SCC—Sub Class Code Register (Modem—D31:F6).....................13-4

13.1.8 BCC—Base Class Code Register (Modem—D31:F6)...................13-4

13.1.9 HEDTYP—Header Type Register (Modem—D31:F6)...................13-4

13.1.10 MMBAR—Modem Mixer Base Address Register

(Modem—D31:F6) .........................................................................13-5

13.1.11 MBAR—Modem Base Address Register (Modem—D31:F6) ........13-5

13.1.12 SVID—Subsystem Vendor ID (Modem—D31:F6) .........................13-6

13.1.13 SID—Subsystem ID (Modem—D31:F6) ........................................13-6

13.1.14 INTR_LN—Interrupt Line Register (Modem—D31:F6)..................13-7

13.1.15 INT_PIN—Interrupt Pin (Modem—D31:F6) ...................................13-7

AC’97 Modem I/O Space (D31:F6).............................................................13-8

13.2.1 x_BDBAR—Buffer Descriptor List Base Address Register..........13-10

13.2.2 x_CIV—Current Index Value Register .........................................13-10

13.2.3 x_LVI—Last Valid Index Register ................................................13-10

13.2.4 x_SR—Status Register................................................................13-11

13.2.5 x_PICB—Position In Current Buffer Register ..............................13-12

13.2.6 x_PIV—Prefetch Index Value Register........................................13-12

13.2.7 x_CR—Control Register ..............................................................13-13

13.2.8 GLOB_CNT—Global Control Register.........................................13-14

13.2.9 GLOB_STA—Global Status Register ..........................................13-14

13.2.10 CAS—Codec Access Semaphore Register.................................13-15

13.2

14

Electrical Characteristics..........................................................................................14-1

14.1

14.2

14.3

14.4

14.5

Absolute Maximum Ratings ........................................................................14-1

Thermal Characteristics..............................................................................14-1

D.C. Characteristics....................................................................................14-1

A.C. Characteristics ....................................................................................14-6

Timing Diagrams.......................................................................................14-16

82801AA and 82801AB Datasheet

xvii

15

16

Pinout and Package Information..............................................................................15-1

15.1

15.2

Pinout Information.......................................................................................15-1

Package Information...................................................................................15-8

Testability.................................................................................................................16-1

16.2

16.3

Tri-state Mode.............................................................................................16-2

NAND tree Mode ........................................................................................16-2

A

B

Register Index........................................................................................................... A-1

Register Bit Index ..................................................................................................... B-1

xviii

82801AA and 82801AB Datasheet

Revision History

Revision

Description

Date

April 1999

-001

Initial Release

•

Editorial changes throughout for clarity.

Added SVID Register (2Ch) and SID Register (2Eh) to the following

functions:

- IDE Controller (D31:F1)

- USB Controller (D31:F2)

- SMBus Controller (D31:F3)

•

Ballout Change: Ball G3 has changed from Vss to a No Connect.

Change to Figure 2-1, “Required External RTC Circuit”. C1

capacitor value changed from 0.047 uF to 2200 pF.

•

Chapter 14, “Electrical Characteristics. Made the following changes:

- Table 14-5. VOL2 changed from 0.4V max to 0.45V max; the

corrsponding IOL2 changed from 10 mA to 16 mA.

002

June 1999

- Table 14-7. The previous revision had TBDs for the Hub Interface

timngs t31-t34. The TBDs have been replaced timing values.

•

Updated the notes at the beginning of:

- Section 5.1.1, “PCI Bus Timing”.

- Section 5.2, “LPC Bridge”.

- Section 5.12.5.4,

- Section 5.15, “USB Controller (Device 31:Function2)”.

- Section 5.17, “ICH/97 2.1 Functional description”.

•

Clarified IRQEN Bit description (Section 8.1.16, “PIRQ[n]_ROUT—

PIRQ[A,B,C,D] Routing Control (LPC I/F—D31:F0)”.

Added Register Bit Index (Appendix B)

82801AA and 82801AB Datasheet

xix

xx

82801AA and 82801AB Datasheet

Introduction

1

The ICH is a highly integrated multifunctional I/O Controller Hub that provides the interface to the

PCI Bus and integrates many of the functions needed in today’s PC platforms. The ICH

communicates with the host controller over a dedicated hub interface. There are two versions of the

ICH (82801AA: ICH and 82801AB: ICH0). This provides added flexibility in designing cost-

effective system solutions. These devices are pin compatible and are in 241-pin packages.

This datasheet describes the 82801AA (ICH) and 82801AB (ICH0) components. Unless otherwise

specified, all non-shaded areas describe the functionality of both components. In the non-shaded

areas, the term I/O Controller Hub (ICH) refers to both the 82801AB and 82801AA products.

Shading, as is shown here, indicates differences between the two components. In the shaded areas

ICH refers to the 82801AA and ICH0 refers to the 82801AB.

1.1

About this Manual

This datasheet is intended for Original Equipment Manufacturers and BIOS vendors creating ICH-

based products. The datasheet assumes a working knowledge of the vocabulary and principles of

USB, IDE, AC’97, SMBus, PCI, ACPI and LPC. Although some details of these features are

described within this datasheet, refer to the individual industry specifications listed in Table 1-1 for

additional details.

Table 1-1. Industry Specifications

Specification

Location

LPC

AC’97

SMBus

PCI

http://developer.intel.com/design/pcisets/lpc/

http://developer.intel.com/pc-supp/platform/ac97/

http://www.sbs-forum.org/specs.htm

http://pcisig.com/specs.htm

USB

http://www.teleport.com/~usb/docs.htm

http://www.teleport.com/~acpi/

ACPI

Chapter 1. Introduction

Chapter 1 introduces the ICH and provides information on datasheet organization.

Chapter 2. Signal Description

Chapter 2 provides a detailed description of each ICH signal. Signals are arranged according to

interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of

the signals.

Chapter 3. ICH Power Planes and Pin States

Chapter 3 provides a complete list of signals, their associated power well, their logic level in each

suspend state, and their logic level before and after reset.

Chapter 4. ICH and System Clock Domains

Chapter 4 provides a list of each clock domain associated with the ICH in an ICH-based system.

82801AA and 82801AB Datasheet

1-1

Introduction

Chapter 5. Functional Description

Chapter 5 provides a detailed description of the functions in the ICH. All functions in this datasheet

are abbreviated using the following nomenclature; Device:Function. This manual abbreviates

devices with D30 and D31 and functions with F0, F1, F2, F3, F4, F5 and F6. For example, Device

31 Function 5 is abbreviated as D31:F5.

Chapter 6. Register Memory and I/O Address Maps

Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges, and memory

ranges decoded by the ICH.

Chapter 7. Hub Interface to PCI Bridge Registers

Chapter 7 provides a detail description of all registers that reside in the Hub Link to PCI bridge.

This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 8. LPC Bridge Registers

Chapter 8 provides a detail description of all registers that reside in the LPC bridge. This bridge

resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units

within the ICH including DMA, Timers, Interrupts, Processor Interface, GPIO, Power

Management, System Management and RTC.

Chapter 9. IDE Controller Registers

Chapter 9 provides a detail description of all registers that reside in the IDE controller. This

controller resides at Device 31, Function 1 (D31:F1).

Chapter 10. USB Controller Registers

Chapter 10 provides a detail description of all registers that reside in the USB controller. This

controller resides at Device 31, Function 2 (D31:F2).

Chapter 11. SMBus Controller Registers

Chapter 11 provides a detail description of all registers that reside in the SMBus controller. This

controller resides at Device 31, Function 3 (D31:F3).

Chapter 12. AC’97 Audio Controller Registers

Chapter 12 provides a detail description of all registers that reside in the audio controller. This

controller resides at Device 31, Function 5 (D31:F5). Note that this section of the EDS does not

include the native audio mixer registers. Accesses to the mixer registers are forwarded over the

AC-link to the codec where the registers reside.

Chapter 13. AC’97 Modem Controller Registers

Chapter 13 provides a detail description of all registers that reside in the modem controller. This

controller resides at Device 31, Function 6 (D31:F6). Note that this section of the EDS does not

include the modem mixer registers. Accesses to the mixer registers are forwarded over the AC-link

to the codec where the registers reside.

Chapter 14. Electrical Characteristics

Chapter 14 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 15. Pinout and Package Information

Chapter 15 provides a table of each signal and its ball assignment in the 241 BGA package. A

footprint of the ballout is also provided. This chapter also provides the physical dimensions and

characteristics of the 241 BGA package.

Chapter 16. Testability

Chapter 17 provides details about the implementation of two test modes provided in the ICH;

NAND Tree and High-Z.

Appendix A. Register Index

Appendix A provides a list of registers and the location within the datasheet where the register

description can be found.

Appendix B. Register Bit Index

Appendix B provides an alphabetical list of the register bits (by bit name) and the location within

the datasheet where the register bit description can be found.

1-2

82801AA and 82801AB Datasheet

Introduction

1.2

Overview

Both ICH (82801AA) and ICH0 (82801AB) provide extensive I/O support. The 82801AA (ICH) /

82801AB (ICH0) functions and capabilities include:

• PCI Rev 2.2 compliant with support for 33 MHz PCI operations.

• PCI slots:

ICH0 Supports up to 4 Req/Gnt pairs;

ICH supports up to 6 Req/Gnt pairs

• ACPI Power Management Logic Support

• Enhanced DMA Controller, Interrupt Controller and Timer Functions

• Integrated IDE controller support.

:ICH0 supports Ultra ATA/33

ICH supports Ultra ATA/66)

• USB host interface with support for 2 USB ports

• System Management Bus (SMBus) with additional support for I²C devices

• AC’97 2.1 Compliant Link for Audio and Telephony CODECs

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support:.

• Alert On LAN* (82801AA ICH only)

The ICH incorporates a variety of PCI functions that are divided into two logical devices (30 and

31). Device 30 is the Hub Interface-To-PCI bridge. Device 31 contains all the other PCI functions

as shown in Table 1-2.

Table 1-2. PCI Devices and Functions

Device:Function

Function Description

Hub Interface to PCI Bridge

Device 30:Function 0

PCI to LPC Bridge

(includes: DMA, Timers, compatible interrupt controller, APIC,

RTC, processor interface control, power management control,

System Management control, and GPIO control)

Device 31:Function 0

Device 31:Function 1

Device 31:Function 2

Device 31:Function 3

Device 31:Function 4

Device 31:Function 5

Device 31:Function 6

IDE Controller

USB Controller

SMBus Controller

Reserved

AC’97 Audio Controller

AC’97 Modem Controller

82801AA and 82801AB Datasheet

1-3

Introduction

The following sub-sections provide an overview of I/O Controller Hub capabilities.

Hub Architecture

As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become

significant. With the addition of AC’97 and Ultra ATA/66, coupled with the existing USB, I/O

requirements could impact PCI bus performance. The Intel 810 chipset’s hub interface

architecture ensures that the I/O subsystem; both PCI and the integrated I/O features (IDE, AC’97,

USB, etc.), will receive adequate bandwidth. By placing the I/O bridge on the hub interface

(instead of PCI), the hub architecture ensures that both the I/O functions integrated into the ICH

and the PCI peripherals obtain the bandwidth necessary for peak performance.

PCI Interface

The ICH PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals are

5V tolerant, except PME#. The ICH integrates a PCI arbiter that supports up to four

(ICH0: 82801AB) or six (ICH: 82801AA) external PCI bus masters in addition to the internal ICH

requests.

IDE Interface (Bus Master capability and synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks

and CD ROMs. Each IDE device can have independent timings. The IDE interface supports PIO

IDE transfers up to 14 Mbytes/sec and Bus Master IDE transfers up to 33 Mbytes/sec for the ICH0

(82801AB) and 66 Mbytes/sec for the ICH (82801AA). It does not consume any ISA DMA

resources. The IDE interface integrates 16x32-bit buffers for optimal transfers.

The ICH’s IDE system contains two independent IDE signal channels. They can be electrically

isolated independently. They can be configured to the standard primary and secondary channels

(four devices). There are integrated series resistors on the data and control lines (see Section 5.14,

“IDE Controller (D31:F1)” on page 5-66 for details).

Low Pin Count (LPC) Interface

The ICH implements an LPC Interface as described in the LPC 1.0 specification. The Low Pin

Count (LPC) Bridge function of the ICH resides in PCI Device 31:Function 0. In addition to the

LPC bridge interface function, D31:F0 contains other functional units including DMA, Interrupt

Controllers, Timers, Power Management, System Management, GPIO, and RTC.

Note that in the Intel 810 chipset platform, the Super I/O (SIO) component has migrated to the

Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O

designs.

1-4

82801AA and 82801AB Datasheet

Introduction

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt

Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven

independently programmable channels. Channels [0:3] are hardwired to 8-bit, count-by-byte

transfers, and channels [5:7] are hardwired to 16-bit, count-by-word transfers. Any two of the

seven DMA channels can be programmed to support fast Type-F transfers.

The ICH supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA DMA.

LPC DMA and PC/PCI DMA use the ICH’s DMA controller. The PC/PCI protocol allows

PCI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PCI

REQ#/GNT# pairs.

LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encodings

on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the

LPC interface. Channel’s 0 - 3 are 8 bit channels. Channel’s 5 - 7 are 16 bit channels. Channel 4 is

reserved as a generic bus master request.

The timer/counter block contains three counters that are equivalent in function to those found in

one 82C54 programmable interval timer. These three counters are combined to provide the system

timer function, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for

these three counters.

The ICH provides an ISA-Compatible interrupt controller that incorporates the functionality of two

82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two

internal interrupts are possible. In addition, the ICH supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save and restore

system state after power has been removed and restored to the circuit.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible interrupt controller (PIC) described in the previous

section, the ICH incorporates the Advanced Programmable Interrupt Controller (APIC). While the

standard interrupt controller is intended for use in a uni-processor system, APIC can be used in

either a uni-processor or multi-processor system.

Enhanced Universal Serial Bus (USB) Controller

The USB controller provides enhanced support for the Universal Host Controller Interface (UHCI).

This includes support that allows legacy software to use a USB-based keyboard and mouse. The

ICH is USB Revision 1.1 compliant.

82801AA and 82801AB Datasheet

1-5

Introduction

RTC

The ICH contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-

backed RAM. The real-time clock performs two key functions: keeping track of the time of day

and storing system data, even when the system is powered down. The RTC operates on a

32.768 KHz crystal and a separate 3V lithium battery that provides up to 7 years of protection.

The RTC also supports two lockable memory ranges. By setting bits in the configuration space,

two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of

passwords or other system security information.

The RTC also supports a date alarm, that allows for scheduling a wake up event up to 30 days in

advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design. The number of

inputs and outputs varies depending on ICH configuration.

Enhanced Power Management

The ICH’s power management functions include enhanced clock control, local and global

monitoring support for 14 individual devices, and various low-power (suspend) states (e.g.,

Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit permits

software-independent entrance to low-power states. The ICH contains full support for the

Advanced Configuration and Power Interface (ACPI) Specification.

System Management Bus (SMBus)

The ICH contains an SMBus Host interface that allows the processor to communicate with SMBus

slaves. This interface is compatible with most I²C devices. Special I²C commands are implemented

(e.g., the I²C Read that allows the ICH to perform block reads of I²C devices).

The ICH’s SMBus host controller provides a mechanism for the processor to initiate

communications with SMBus peripherals (slaves). The host controller supports seven SMBus

interface command protocols for communicating with SMBus slave devices (see System

Management Bus Specifications, Rev 1.0): Quick Command, Send Byte, Receive Byte, Write

Byte/Word, Read Byte/Word, Process Call, and Block Read/Write.

1-6

82801AA and 82801AB Datasheet

Introduction

Manageability

The ICH integrates several functions designed to manage the system and lower the total cost of

ownership (TC0) of the system. These system management functions are designed to report errors,

diagnose the system, and recover from system lockups without the aid of an external

microcontroller.

• TCO Timer. The ICH’s integrated programmable TC0 Timer is used to detect system locks.

The first expiration of the timer generates an SMI# that the system can use to recover from a

software lock. The second expiration of the timer causes a system reset to recover from a

hardware lock.

• Processor Present Indicator. The ICH looks for the processor to fetch the first instruction

after reset. If the processor does not fetch the first instruction, the ICH will reboot the system

at the safe-mode frequency multiplier.

• ECC Error Reporting. When detecting an ECC error, the host controller has the ability to

send one of several messages to the ICH. The host controller can instruct the ICH to generate

either an SMI#, NMI, SERR#, or TCO interrupt.

• Function Disable. The ICH provides the ability to disable the following functions: AC’97

Modem, AC’97 Audio, IDE, USB, or SMBus. Once disabled, these functions no longer

decode I/O, memory, or PCI configuration space. Also, no interrupts or power management

events are generated from the disable functions.

• Intruder Detect. The ICH provides an input signal (INTRUDER#) that can be attached to a

switch that is activated by the system case being opened. The ICH can be programmed to

generate an SMI# or TCO interrupt due to an active INTRUDER# signal.

• SMBus. The ICH integrates an SMBus controller that provides an interface to manage

peripherals (e.g., serial presence detection (SPD) or RIMMs and thermal sensors).

• Alert-On-LAN (82801AA only). The ICH (82801AA only) supports Alert-On-LAN. In

response to a TCO event (intruder detect, thermal event, processor not booting) the ICH sends

a message over the SMBus. A LAN controller can decode this SMBus message and send a

message over the network to alert the network manager.

82801AA and 82801AB Datasheet

1-7

Introduction

AC’97 2.1 Controller

The digital link in the ICH is AC’97 Revision 2.1 compliant, supporting two codecs with

independent PCI functions for audio and modem. Microphone input and left and right audio

channels are supported for a high-quality two-speaker audio solution. Wake on ring from suspend

is also supported with an appropriate modem codec.

The Audio Codec ‘97 (AC’97) Specification defines a digital link that can be used to attach an

audio codec (AC), a modem codec (MC), an audio/modem codec (AMC), or both an AC and an

MC. The AC’97 Specification defines the interface between the system logic and the audio or

modem codec known as the AC’97 Digital Link.

The ability to add cost-effective audio and modem solutions as the platform migrates away from

ISA is important. In addition, the AC’97 audio and modem components are software configurable.

This reduces configuration errors. The ICH’s AC’97 (with the appropriate codecs) not only

replaces ISA audio and modem functionality, but also improves overall platform integration by

incorporating the AC’97 digital link. Using the ICH’s integrated AC’97 digital link reduces cost

and eases migration from ISA.

By using an audio codec, the AC’97 digital link allows for cost-effective, high-quality, integrated

audio using the ICH. In addition, an AC’97 soft modem can be implemented with the use of a

modem codec. Several system options exist when implementing AC’97. The ICH’s integrated

digital link allows two external codecs to be connected to the ICH. The system designer can

provide audio with an audio codec, or a modem with a modem codec. For system requiring both

audio an a modem, there are two solutions. The audio codec and the modem codec can be

integrated into an AMC or separate audio and modem codecs can be connected to the ICH.

Modem implementation for different countries must be considered as telephone systems may vary.

By using a split design, the audio codec can be on-board and the modem codec can be placed on a

riser. Intel is developing an AC’97 digital link connector. With a single integrated codec (or AMC),

both audio and modem can be routed to a connector near the rear panel where the external ports can

be located.

1-8

82801AA and 82801AB Datasheet

Signal Description

2

This chapter provides a detailed description of each signal. The signals are arranged in functional

groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when

the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high

voltage level.

The following notations are used to describe the signal type:

I

Input Pin

O

Output Pin

OD

I/O

Open Drain Output Pin.

Bi-directional Input / Output Pin.

2.1

Hub Interface

Table 2-1. Hub Interface Signals

Name

Type

Description

HL[10:0]

I/O

Hub Interface Signals.

HL[11]

(ICH only)

I/O

Hub Interface Signals (82801AA ICH only).

Hub Interface Strobe: One of two differential strobe signals used to transmit

and receive data through the hub interface.

HL_STB

Hub Interface Strobe Complement: Second of the two differential strobe

signals.

HL_STB#

HLCOMP

I/O

Hub Interface Compensation: Used for Hub Interface buffer compensation.

2.2

Firmware Hub Interface

Table 2-2. Firmware Hub Interface Signals

Name

Type

Description

FWH[3:0] /

LAD[3:0]

I/O

Firmware Hub Signals.

Firmware Hub Signals

FWH[4] /

LFRAME#

I/O

82801AA and 82801AB Datasheet

2-1

Signal Description

2.3

PCI Interface

Table 2-3. PCI Interface Signals (Sheet 1 of 3)

Name

Type

Description

PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first

clock of a transaction, AD[31:0] contain a physical address (32 bits). During

subsequent clocks, AD[31:0] contain data. The ICH drives all 0’s on AD[31:0] during the

address phase of PCI Interrupt Acknowledge cycles.

AD[31:0]

I/O

Bus Command and Byte Enables: The command and byte enable signals are

multiplexed on the same PCI pins. During the address phase of a transaction,

C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the

Byte Enables.

C/BE[3:0]#

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 1 0

0 1 1 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 1 0

1 1 1 1

Command Type

Interrupt Acknowledge

Special Cycle

I/O Read

I/O Write

Memory Read

Memory Write

C/BE[3:0]#

I/O

Configuration Read

Configuration Write

Memory Read Multiple

Memory Read Line

Memory Write and Invalidate

NOTE: All command encodings not shown are reserved. The ICH does not decode

reserved values, and, therefore, does not respond if a PCI master generates a

cycle using one of the reserved values.

Device Select: The ICH asserts DEVSEL# to claim a PCI transaction. As an output,

the ICH asserts DEVSEL# when a PCI master peripheral attempts an access to an

internal ICH register or man memory. As an input, DEVSEL# indicates the response to

an ICH-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading

edge of PCIRST#. DEVSEL# remains tri-stated by the ICH until driven by a Target

device.

DEVSEL#

FRAME#

I/O

Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and

duration of a PCI transaction. While the initiator asserts FRAME#, data transfers

continue. When the initiator negates FRAME#, the transaction is in the final data

phase. FRAME# is an input to the ICH when the ICH is the target, and FRAME# is an

output from the ICH when the ICH is the Initiator. FRAME# remains tri-stated by the

ICH until driven by an Initiator.

Initiator Ready: IRDY# indicates the ICH's ability, as an Initiator, to complete the

current data phase of the transaction. It is used in conjunction with TRDY#. A data

phase is completed on any clock both IRDY# and TRDY# are sampled asserted.

During a write, IRDY# indicates the ICH has valid data present on AD[31:0]. During a

read, it indicates the ICH is prepared to latch data. IRDY# is an input to the ICH when

the ICH is the Target and an output from the ICH when the ICH is an Initiator. IRDY#

remains tri-stated by the ICH until driven by an Initiator.

IRDY#

I/O

Target Ready: TRDY# indicates the ICH's ability as a Target to complete the current

data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase

is completed when both TRDY# and IRDY# are sampled asserted. During a read,

TRDY# indicates that the ICH, as a Target, has placed valid data on AD[31:0]. During a

write, TRDY# indicates the ICH, as a Target is prepared to latch data. TRDY# is an

input to the ICH when the ICH is the Initiator and an output from the ICH when the ICH

is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-

stated by the ICH until driven by a target.

TRDY#

2-2

82801AA and 82801AB Datasheet

Signal Description

Table 2-3. PCI Interface Signals (Sheet 2 of 3)

Name

Type

Description

Stop: STOP# indicates that the ICH, as a Target, is requesting the Initiator to stop the

current transaction. STOP# causes the ICH, as an Initiator, to stop the current

transaction. STOP# is an output when the ICH is a Target and an input when the ICH is

an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-

stated until driven by the ICH.

STOP#

I/O

Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0]

plus C/BE[3:0]#. "Even" parity means that the ICH counts the number of "1"s within the

36 bits plus PAR and the sum is always even. The ICH always calculates PAR on 36

bits regardless of the valid byte enables. The ICH generates PAR for address and data

phases and only guarantees PAR to be valid one PCI clock after the corresponding

address or data phase. The ICH drives and tri-states PAR identically to the AD[31:0]

lines except that the ICH delays PAR by exactly one PCI clock. PAR is an output during

the address phase (delayed one clock) for all ICH initiated transactions. PAR is an

output during the data phase (delayed one clock) when the ICH is the Initiator of a PCI

write transaction, and when it is the Target of a read transaction. ICH checks parity

when it is the Target of a PCI write transaction. If a parity error is detected, the ICH sets

the appropriate internal status bits and has the option to generate an NMI# or SMI#.

PAR

I/O

Parity Error (82801AA ICH only): An external PCI device drives PERR# when it

receives data that has a parity error. For the 82801AA, the ICH drives PERR# when it

detects a parity error. The ICH can either generate an NMI# or SMI# upon detecting a

parity error (either detected internally or reported via the PERR# signal).

PERR# /

GPIO[7]

I/O

(ICH only)

If this signal is not used for PERR#, it can instead be used as a GPIO.

NOTE: GPIO[7] is a non-muliplexed signal on the ICH0 (82801AB).

PCI Requests (REQ[0:3]):

REQ[0:3]#

REQ[4]#

I

NOTE: Note:REQ[0]# is programmable to have improved arbitration latency for

supporting PCI-based 1394 controllers.

PCI Requests (REQ[4,5]) (82801AA ICH only): REQ[5]# is multiplexed with

PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI or

PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1].

REQ[5]# /

REQ[B]# /

GPIO[1]

I

NOTES:

1. REQ[B]# and GPIO[1] are on both the ICH (82801AA) and

ICH0 (82801AB) components.

2. GPIO[1] is only muliplexed with REQ[B]#l on the ICH0 (82801AB).

(ICH only)

GNT[0:3]#

PCI Grants: Pullup resistors are not required on these signals. If pullups are used, they

should be tied to the Vcc3_3 power rail.

O

PCI Grants (GNT[4,5]) (82801AA ICH only): Pullup resistors are not required on these

signals. If pullups are used, they should be tied to the Vcc3_3 power rail.

GNT[4]#

GNT[5]# is multiplexed with PC/PCI GNT[B]# (must choose one or the other, but not

both). If not needed for PCI or PC/PCI, GNT[5]# can instead be used as a GPIO.

GNT[5]#/

GNT[B]# /

GPIO[17]#

O

NOTES:

1. GNT[B]# and GPIO[17] are on both the ICH (82801AA) and

ICH0 (82801AB) components.

2. GPIO[17] is only muliplexed with GNT[B]#l on the ICH0 (82801AB).

(ICH only)

PCICLK

I

PCI Clock: 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus.

PCI Reset: ICH asserts PCIRST# to reset devices that reside on the PCI bus. The ICH

asserts PCIRST# during power-up and when S/W initiates a hard reset sequence

through the RC (CF9h) register. The ICH drives PCIRST# inactive a minimum of 1 ms

after PWROK is driven active. The ICH drives PCIRST# active a minimum of 1 ms

when initiated through the RC register.

PCIRST#

PLOCK#

O

PCI Lock: Indicates an exclusive bus operation and may require multiple transactions

to complete. ICH asserts PLOCK# when it performs non-exclusive transactions on the

PCI bus. PLOCK# is ignored when PCI masters are granted the bus.

I/O

82801AA and 82801AB Datasheet

2-3

Signal Description

Table 2-3. PCI Interface Signals (Sheet 3 of 3)

Name

Type

Description

System Error: SERR# can be pulsed active by any PCI device that detects a system

error condition. Upon sampling SERR# active, the ICH has the ability to generate an

NMI, SMI#, or interrupt.

SERR#

I

PCI Power Management Event: PCI peripherals drive PME# to wake the system from

low-power states S1-S5.

PME#

I

PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the

purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by

devices such as PCI based Super I/O or audio codecs which need to perform legacy

8237 DMA but have no ISA bus.

REQ[A]# /

GPIO [0]

When not used for PC/PCI requests, these signals can be used as General Purpose

Inputs.

REQ[B]#/

REQ[5]# /

GPIO[1]

NOTES:

1. For the 82810AA, REQ[B]# can instead be used as the 6th PCI bus request.

2. REQ[5]# (shown in column 1) is only available on the ICH (82801AA).

PC/PCI DMA Acknowledges [A: B]: This grant serializes an ISA-like DACK# for the

purpose of running DMA/ISA Master cycles over the PCI bus. This is used by devices

such as PCI based Super/IO or audio codecs that need to perform legacy 8237 DMA

but have no ISA bus. External pull-up resistors are not required. If external pull-up

resistors are used, they must be tied to the VCC3_3 power rail.

GNT[A]#/

GPIO[16]

O

GNT[B]#/

GNT[5]# /

GPIO[17]

When not used for PC/PCI, these signals can be used as General Purpose Outputs.

NOTES:

1. For the 82810AA, GNTB# can also be used as the 6th PCI bus master grant

output.

2. GNT[5]# (shown in column 1) is only available on the ICH (82801AA).

2.4

IDE Interface

Table 2-4. IDE Interface Signals (Sheet 1 of 2)

Name

Type

Description

Primary and Secondary IDE Device Chip Selects for 100 Range: For ATA

command register block. This output signal is connected to the corresponding

signal on the primary or secondary IDE connector.

PDCS1#,

SDCS1#

O

Primary and Secondary IDE Device Chip Select for 300 Range: For ATA control

register block. This output signal is connected to the corresponding signal on the

primary or secondary IDE connector.

PDCS3#,

SDCS3#

O

Primary and Secondary IDE Device Address: These output signals are

connected to the corresponding signals on the primary or secondary IDE

connectors. They are used to indicate which byte in either the ATA command block

or control block is being addressed.

PDA[2:0],

SDA[2:0]

O

PDD[15:0],

SDD[15:0]

Primary and Secondary IDE Device Data: These signals directly drive the

corresponding signals on the primary or secondary IDE connector.

I/O

Primary and Secondary IDE Device DMA Request: These input signals are

directly driven from the DRQ signals on the primary or secondary IDE connector. It

is asserted by the IDE device to request a data transfer, and used in conjunction

with the PCI bus master IDE function and are not associated with any AT

compatible DMA channel.

PDDREQ,

SDDREQ

I

2-4

82801AA and 82801AB Datasheet

Signal Description

Table 2-4. IDE Interface Signals (Sheet 2 of 2)

Name

Type

Description

Primary and Secondary IDE Device DMA Acknowledge: These signals directly

drive the DAK# signals on the primary and secondary IDE connectors. Each is

asserted by the ICH to indicate to IDE DMA slave devices that a given data

transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This

signal is used in conjunction with the PCI bus master IDE function and are not

associated with any AT-compatible DMA channel.

PDDACK#,

SDDACK#

O

Primary and Secondary Disk I/O Read (PIO and Non-Ultra ATA): This is the

command to the IDE device that it may drive data onto the PDD or SDD lines. Data

is latched by the ICH on the deassertion edge of PDIOR# or SDIOR#. The IDE

device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#,

PDCS3# or SDCS1#) and the PDA or SDA lines, or the IDE DMA acknowledge

(PDDAK# or SDDAK#).

PDIOR# /

(PDWSTB /

PRDMARDY#)

O

Primary and Secondary Disk Write Strobe (Ultra ATA Writes to Disk): This is

the data write strobe for writes to disk. When writing to disk, ICH drives valid data

on rising and falling edges of PDWSTB or SDWSTB.

SDIOR# /

(SDWSTB /

SRDMARDY#)

Primary and Secondary Disk DMA Ready (Ultra ATA Reads from Disk): This is

the DMA ready for reads from disk. When reading from disk, ICH deasserts

PRDMARDY# or SRDMARDY# to pause burst data transfers.

Primary and Secondary Disk I/O Write (PIO and Non-Ultra ATA): This is the

command to the IDE device that it may latch data from the PDD or SDD lines. Data

is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The

IDE device is selected either by the ATA register file chip selects (PDCS1# or

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA

acknowledge (PDDAK# or SDDAK#).

PDIOW# /

(PDSTOP)

O

SDIOW# /

(SDSTOP)

Primary and Secondary Disk Stop (Ultra ATA): ICH asserts this signal to

terminate a burst.

Primary and Secondary I/O Channel Ready (PIO): This signal will keep the

strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes)

longer than the minimum width. It adds wait states to PIO transfers.

PIORDY /

(PDRSTB /

PWDMARDY#)

Primary and Secondary Disk Read Strobe (Ultra ATA Reads from Disk): When

reading from disk, ICH latches data on rising and falling edges of this signal from

the disk.

I

SIORDY /

(SDRSTB /

SWDMARDY#)

Primary and Secondary Disk DMA Ready (Ultra ATA Writes to Disk): When

writing to disk, this is deasserted by the disk to pause burst data transfers.

2.5

Low Pin Count (LPC) Interface

Table 2-5. LPC Interface Signals

Name

Type

Description

LAD[3:0] /

FWH[3:0]

I/O

LPC Multiplexed Command, Address, Data: Internal pull-ups are provided.

LFRAME# /

FWH[4]

O

I

LPC Frame: Indicates the start of an LPC cycle, or an abort.

LPC Serial DMA/Master Request Inputs: Used to request DMA or bus master

access. Typically connected to external Super I/O device.

LDRQ[0]#

LDRQ[1]# /

GPIO[8]

LPC Serial DMA/Master Request Inputs: Second DMA or bus master request. If

LDRQ[1]# is not needed, it can be used as a General Purpose Input.

I

82801AA and 82801AB Datasheet

2-5

Signal Description

2.6

Interrupt Interface

Table 2-6. Interrupt Signals

Name

Type

Description

SERIRQ

I/O

Serial Interrupt Request: This pin implements the serial interrupt protocol.

PCI Interrupt Requests: The PIRQx# signals can be routed to interrupts 3:7, 9:12, 14

or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate

Route Control Register.

PIRQ[A:D]# I/OD

In APIC mode, these signals are connected to the internal I/O APIC in the following

fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and

PIRQD# to IRQ19. This frees the ISA interrupts.

Interrupt Request 14, 15: These interrupt inputs are connected to the IDE drives.

IRQ14 is used by the drives connected to the Primary controller and IRQ15 is used by

the drives connected to the Secondary controller.

IRQ[14,15]

APICCLK

I

APIC Clock: This clock can run at 16.66667 MHz and is the APIC bus clock.

APIC Data: These bi-directional open drain signals are used to send and receive data

APICD[1:0]

I/OD over the APIC bus. As inputs the data is valid on the rising edge of APICCLK. As

outputs, new data is driven from the rising edge of the APICCLK.

2.7

USB Interface

Table 2-7. USB Interface Signals

Name

Type

Description

USBP1P

USBP1N

I/O

Universal Serial Bus Port 1 Differential: Bus Data/Address/Command Bus

USBP0P

USBP0N

I/O

I

Universal Serial Bus Port 0 Differential: Bus Data/Address/Command Bus

Overcurrent Indicators: These signals set corresponding bits in the USB controller to

indicate that an overcurrent condition has occurred.

OC[1:0]#

2-6

82801AA and 82801AB Datasheet

Signal Description

2.8

Power Management Interface

Table 2-8. Power Management Interface Signals

Name

Type

Description

Thermal Alarm: Active low signal generated by external hardware to start the

Hardware clock throttling mode. Can also generate an SMI# or an SCI.

THRM#

I

S3 Sleep Control: Power plane control. The signal is used to shut power off to all

non-critical systems when in S3 (Suspend To RAM) state. It can be used as General

Purpose Output if STR is not supported.

SLP_S3#/

GPIO[24]

O

I

S5 Sleep Control: Power plane control. The signal is used to shut power off to all

non-critical systems when in the S4 (Suspend To Disk) or S5 (Soft Off) states.

SLP_S5#

PWROK

Power OK: When asserted, PWROK is an indication to the ICH that core power and

PCICLK have been stable for at least 1 ms. PWROK can be driven asynchronously.

When PWROK is negated, the ICH asserts PCIRST#.

Power Button: The Power Button will cause SMI# or SCI to indicate a system

request to go to a sleep state. If the system is already in a sleep state, this signal will

cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause

an unconditional transition (power button override) to the S5 state with only the

PWRBTN# available as a wake event. Override will occur, even if the system is in the

S1-S4 states.

PWRBTN#

I

Ring Indicate: From the modem interface. Can be enabled as a wake event and this

is preserved across power failures.

RI#

I

RSMRST#

Resume Well Reset: Used for resetting the resume power plane logic.

Suspend Status: This signal is asserted by the ICH to indicate that the system will

be entering a low power state soon. This can be monitored by devices with memory

that need to switch from normal refresh to suspend refresh mode. It can also be used

by other peripherals as an indication that they should isolate their outputs that may

be going to powered-off planes. This signal is called LPCPD# on the LPC Interface.

SUS_STAT#/

GPIO[25]

O

NOTE: Can be used as General Purpose Output if external logic does not require

this signal.

Suspend Clock (82801AA only): Output of the RTC generator circuit to use by

other chips for refresh clock.

SUSCLK/

GPIO[26]

NOTES:

(82801AA

only)

1. Can be used as General Purpose Output if external logic does not require this

signal.

2. GPIO[26] is a non-muliplexed signal on the ICH0 (82801AB).

82801AA and 82801AB Datasheet

2-7

Signal Description

2.9

Processor Interface

Table 2-9. Processor Interface Signals

Name

Type

Description

Mask A20: A20M# will go active based on either setting the appropriate bit in the Port

92h register, or based on the A20GATE input being active.

A20M#

OD

Speed Strap: During the reset sequence, ICH drives A20M# high if the corresponding

bit is set in the FREQ_STRP register.

Processor Sleep: This signal puts the processor into a state that saves substantial

power compared to Stop-Grant state. However, during that time, no snoops occur. The

ICH can optionally assert the processor SLP# signal when going to the S1 state.

CPUSLP#

FERR#

OD

Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the

processor. IGNNE# is only used if the ICH coprocessor error reporting function is

enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If

FERR# is asserted, the ICH generates an internal IRQ13 to its interrupt controller unit. It

is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the

processor unless FERR# is active. FERR# requires an external weak pull-up to ensure

a high level when the coprocessor error function is disabled.

I

Ignore Numeric Error: This signal is connected to the ignore error pin on the

processor. IGNNE# is only used if the ICH coprocessor error reporting function is

enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If

FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error

Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until

FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is

written, the IGNNE# signal is not asserted.

IGNNE#

OD

Speed Strap: During the reset sequence, ICH drives IGNNE# high if the corresponding

bit is set in the FREQ_STRP register.

Initialization: INIT# is asserted by the ICH for 16 PCI clocks to reset the processor.

The 82810AA can be configured to support Processor BIST. In that case, INIT# will

be active when PCIRST# is active.

INIT#

INTR

OD

Processor Interrupt: INTR is released by the ICH to signal the processor that an

interrupt request is pending and needs to be serviced. It is an asynchronous output and

normally driven low.

Speed Strap: During the reset sequence, ICH drives INTR high if the corresponding bit

is set in the FREQ_STRP register.

Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the

processor. The ICH can generate an NMI when either SERR# or IOCHK# is asserted.

The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by

setting the corresponding NMI source enable/disable bit in the NMI Status and Control

Register.

NMI

OD

Speed Strap: During the reset sequence, ICH drives NMI high if the corresponding bit

is set in the FREQ_STRP register.

System Management Interrupt: SMI# is an active low output synchronous to PCICLK.

It is asserted by the ICH in response to one of many enabled hardware or software

events.

SMI#

OD

Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is

asserted by the ICH in response to one of many hardware or software events. When the

processor samples STPCLK# asserted, it responds by stopping its internal clock.

STPCLK# is floated during PCIRST#.

STPCLK#

Keyboard Controller Reset Processor: The keyboard controller can generate INIT#

to the processor. This saves the external OR gate with the ICH’s other sources of INIT#.

When the ICH detects the assertion of this signal, INIT# is generated for 16 PCI clocks.

RCIN#

I

A20 Gate: From the keyboard controller. Acts as an alternative method to force the

A20M# signal active. Saves the external OR gate needed with various other PCIsets.

A20GATE

2-8

82801AA and 82801AB Datasheet

Signal Description

2.10

SMBus Interface

This is accessed from the PCI Device 31:Function 3.

Note: Although this is called the SMBus logic, it has capability to access slaves that are I²C compatible.

Table 2-10. SM Bus Interface Signals

Name

Type

Description

SMBus Data: External pull-up is required.

SMBDATA

SMBCLK

I/OD

SMBus Clock: External pull-up is required.

SMBALERT#/

GPIO[11]

SMBus Alert: This signal is used to wake the system or generate SMI#. If not

used for SMBALERT#, it can be used as GPIO[11].

I

2.11

System Management Interface

Table 2-11. System Management Signal

Name

Type

Description

Intruder Detect: Disables system if box detected open. If this signal is not connected

to a switch, the software can directly read the state of the input and use it as a GPI.

INTRUDER#

I

Alert On LAN* Clock (82801AA only): External pull-up is required

ALERTCLK

GPIO[27]

I/OD NOTES:

1. This signal requires a pull-up resistor, even if it is not used.

(82801AA

only)

2. GPIO[27] is a non-muliplexed signal on the ICH0 (82801AB).

Alert On LAN* Data (82801AA only): External pull-up is required

ALERTDATA

GPIO[28]

I/OD NOTES:

(82801AA

only)

1. This signal requires a pull-up resistor, even if it is not used.

2. GPIO[28] is a non-muliplexed signal on the ICH0 (82801AB).

2.12

Real Time Clock Interface

Table 2-12. Real Time Clock Interface

Name

Type

Description

Crystal Input 1: Connected to the 32.768 KHz crystal. If no external crystal is used,

then RTCX1 can be driven with the desired clock rate.

RTCX1

Special

Crystal Input 2: Connected to the 32.768 KHz crystal. If no external crystal is used,

then RTCX2 should be left floating.

RTCX2

VBIAS

Special

I

RTC Bias Voltage: This pin is used to provide a reference voltage. The DC voltage

applied to this pin sets a current which is mirrored throughout the oscillator and

buffer circuitry.

82801AA and 82801AB Datasheet

2-9

Signal Description

2.13

Other Clocks

Table 2-13. Other Clocks

Name

Type

Description

Oscillator Clock: Used for 8254 timers. Runs at 14.31818 MHz. This clock is permitted

to stop during S3 (or lower) states.

CLK14

I

48 MHz Clock: Used to run the USB controller. Runs at 48 MHz. This clock is permitted

to stop during S3 (or lower) states.

CLK48

CLK66

I

66 MHz Clock: Used to run the hub interface. Runs at 66 MHz. This clock is permitted to

stop during S3 (or lower) states.

2.14

Miscellaneous Signals

Table 2-14. Miscellaneous Signals

Name

SPKR

Type

Description

Speaker: The SPKR signal is the output of counter 2 and is internally "ANDed" with

Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker

driver device, which in turn drives the system speaker. Upon PCIRST#, its output state

is 1.

O

Note: SPKR is sampled at the rising edge of PWROK as a functional strap. See

Section 2.18.1 for more details.

RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the

RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This signal is also used to enter

the test modes documented in Section 2.18.2.

RTCRST#

I

2.15

AC’97 Link

These signals are for Device 31:Functions 5 and 6.

.

Table 2-15. AC’97 Link Signals

Name

AC_RST#

Type

Description

O

AC97 Reset: Master H/W reset to external Codec(s)

AC_SYNC

O

I

AC97 Sync: 48 KHz fixed rate sample sync to the Codec(s)

AC97 Bit Clock: 12.288 MHz serial data clock generated by the external Codec(s)

AC97 Serial Data Out: Serial TDM data output to the Codec(s)

AC_BIT_CLK

AC_SDOUT

AC_SDIN 0

O

Note: AC_SDOUT is sampled at the rising edge of PWROK as a functional strap.

See Section 2.18.1 for more details.

I

AC97 Serial Data In 0: Serial TDM data input from a Codec

AC97 Serial Data In 1: Serial TDM data input from a Codec.

AC_SDIN 1/

GPIO[9]

Note: If a separate codec is not used, this signal can be used as a GPI.

2-10

82801AA and 82801AB Datasheet

Signal Description

2.16

General Purpose I/O

Table 2-16. General Purpose I/O Signals

Name

Type

Description

Fixed as Input only. Main Power Well. Can instead be used for PC/PCI REQ[A:B]#.

For the ICH (82801AA), GPIO[1] can alternatively be used for PCI REQ[5]#.

GPIO[0:1]

I

GPIO[2:4]

GPIO[5:6]

I

Not implemented

Fixed as Input only. Main Power Well.

GPIO[7]

I

For the ICH (82801AA), this signal can instead be used as PERR#.

GPIO[8]

GPIO[9]

I

Fixed as Input only. Resume Power Well. Can instead be used for LDRQ[1]#.

Fixed as Input only. Resume Power Well. Can instead be used for AC_SDIN[1].

Not implemented.

GPIO[10]

GPIO[11]

Fixed as Input only. Resume Power Well. Can instead be used for SMBALERT#.

Fixed as Input only. Resume Power Well.

GPIO[12:13]

GPIO[14:15]

Not implemented.

Fixed as Output only. Main Power Well. Can instead be used for PC/PCI

GNT[A:B]#.

GPIO[16:17]

O

For the ICH (82801AA), GPIO[17] can alternatively be used for PCI GNT[5]#

GPIO[18:20]

GPIO[21:22]

GPIO[23]

O

Not implemented

Fixed as Output only. Main Power Well

OD

O

Fixed as Output only. Main Power Well.

GPIO[24]

Fixed as Output only. Resume Power Well. Can instead be used for SLP_S3#

Fixed as Output only. Resume Power Well. Can instead be used for SUS_STAT#.

GPIO[25]

O

Fixed as Output only. Resume Power Well.

GPIO[26]

O

For the ICH (82801AA), this signal can instead be used for SUS_CLK.

Can be Input or Output. Resume Power Well.

GPIO[27:28]

GPIO[29:31]

OD

I/O

For the ICH (82801AA), this signal can instead be used for ALERTCLK and

ALERTDATA.

Not implemented

82801AA and 82801AB Datasheet

2-11

Signal Description

2.17

Power and Ground

Table 2-17. Power and Ground Signals

Name

Description

Vcc3_3

Vcc1_8

Power for Core: 3.3V. This power will be shut off in S3, S5, or G3 states.

Power for the Hub Interface: 1.8V. This power will be shut off in S3, S4, or G3 states.

Power for Resume Well: 3.3V. This power is not expected to be shut off unless the

system is unplugged.

VccSUS

Power for RTC Well: 3.3V. (Although can drop to 2.0V if the system is in G3 state). This

power is not expected to be shut off unless the RTC battery is removed or drained.

VccRTC

Note: Implementations should not attempt to clear CMOS by using a jumper to pull

VccRTC low. Clearing CMOS in an ICH-based platform can be done by using a jumper on

RTCRST# or GPI, or using SAFEMODE strap.

VBIAS

5VREF

RTC Bias Voltage: See Section 2.12, “Real Time Clock Interface” on page 2-9.

Reference for 5V tolerance on inputs: This power will be shut off in S3, S5, or G3

states.

Reference for the Hub Interface: 0.9V. This power will be shut off in S3, S4, or G3

states.

HUBREF

Vss

Grounds.

2.18

Pin Straps

2.18.1

Functional Strap

Table 2-18 shows signals that are used for static configuration. They are sampled at the rising edge

of PWROK to select configurations and then revert later to their normal usage. To envoke the

associated mode, the signal should be driven at least 4 PCI clocks prior to the time it is sampled.

Table 2-18. Functional Strap Definitions

Signal

Usage

When Sampled

Comment

The signal has a weak internal pull-up. If the signal is sampled

low, this indicates that the system is strapped to the “No

Reboot” mode (ICH will disable the TCO Timer system reboot

feature). The status of this strap is readable via the

NO_REBOOT bit (bit 1, D31: F0, Offset D4h).

NO

Rising Edge of

SPKR

REBOOT PWROK

The signal has a weak internal pull-down. If the signal is

sampled high, the ICH will set the processor speed strap pins

for safe mode. Refer to processor specification for speed

strapping definition. The status of this strap is readable via the

SAFE_MODE bit (bit 2, D31: F0, Offset D4h).

SAFE

MODE

Rising Edge of

PWROK

AC_SDOUT

2-12

82801AA and 82801AB Datasheet

Signal Description

2.18.2

Test Straps

When PWROK is active (high), driving RTCRST# low for a number of PCI clocks (33 MHz) will

activate a particular test mode as specified in Table 2-19.

Note: RTCRST# can be driven anytime after PCIRST# is inactive but it is better to drive it as soon as

PWROK goes high to enter a test mode.

Refer to Chapter 16 for a description of each test mode.

Table 2-19. Test Strap Definition

Number of PCI Clocks RTCRST# Driven Low

Test Mode

After PWROK Active

<4

No Test Mode Invoked

NAND Chain 1

4

5

NAND Chain 2

6

7

NAND Chain 3

NAND Chain 4

8

All “Z”

9

No Test Mode Invoked

RESERVED - DO NOT ATTEMPT

No Test Mode Invoked

10-24

>24

2.18.3

External RTC Circuitry

To reduce RTC well power consumption, the ICH implements a new internal oscillator circuit that

is sensitive to step voltage changes in VccRTC and VBIAS. Figure 2-1 shows a schematic diagram

of the circuitry required to condition these voltages to ensure correct operation of the ICH RTC

.

Figure 2-1. Required External RTC Circuit

3.3V

VCCSUS

VCCRTC

RTCX2

RTCX1

VBIAS

1 k

1

F

µ

Ω

32768 Hz

Xtal

R1

10 M

Vbatt

Ω

C1

2200 pF

C3

12.5 pF

R2

10 M

C2

12.5 pF

VSSRTC

Note: Capacitor C2 and C3 values are crystal-dependent.

82801AA and 82801AB Datasheet

2-13

Signal Description

2.18.4

5VREF / Vcc3_3 Sequencing Requirements

The 5VREF pin is the reference voltage for 5V tolerance on inputs to the ICH. The 5VREF pin

must power up before or simultaneous to Vcc3_3, and must power down after or simultaneous to

Vcc3_3. Refer to Figure 2-2 for an example circuit schematic that may be used to ensure proper

5VREF sequencing.

Figure 2-2. Example 5VREF Sequencing Circuit

VCC Supply

(3.3V)

5V Supply

1k

Schottky

Diode

1 uF

To System

5VREF

To System

2-14

82801AA and 82801AB Datasheet

Power Planes and Pin States

3

3.1

Power Planes

The ICH has five main power planes, as shown in Table 3-1.

Table 3-1. ICH Power Planes

Plane

Description

Core

Powered by the main power supply. When the system is in the S3, S4, S5, or G3 state,

this plane is assumed to be shut off.

(3.3V)

Hub Interface

(1.8V)

Powered by the main power supply. When the system is in the S3, S4, S5, or G3 state,

this plane is assumed to be shut off.

Resume

Powered by the trickle power supply. In the G3 state, this plane is assumed to be shut

off.

(3.3V Stand-By)

When other power is available (from the main supply), external diode coupling will

provide power to reduce the drain on the RTC battery. Operations from 3.3V down to

2.0V.

RTC

3.2

Output and I/O Signal Planes and States

Table 3-2 shows the power plane associated with the output and I/O signals, as well as the state at

various times. Within the table, the following terms are used:

“High-Z”

“High”

Tri-state. ICH not driving the signal high or low

ICH is driving the signal to a logic ‘1’

“Low”

ICH is driving the signal to a logic ‘0’

“Defined”

“Undefined”

“Running”

“Off”

Driven to a level that is defined by the function (will be high or low)

ICH is driving the signal, but the value is indeterminate

Clock is toggling or signal is transitioning because function not stopping

The power plane is off, so ICH is not driving

Still needs to be defined.

“?”

Note that the signal levels are the same in S4 and S5

82801AB and 82801AA Datasheet

3-1

Power Planes and Pin States

Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 1 of 2)

Immediate

During

Signal Name

Power Plane

after

S1

S3

S4/S5

PCIRST#

PCI Bus

AD[31:0]

C/BE#[3:0]

DEVSEL#

FRAME#

Core

High-Z

High

Low

High

Low

High

Off

High-Z

High

High-Z

High

GNT[0:3]#

GNT[4:5]#

(ICH only: 82801AA)

Core

High

Off

GNT[A:B]#

IRDY#, TRDY#

PAR

Core

High-Z

Low

High

High-Z

Low

High

High-Z

Low

Off

Core

Off

PCIRST#

Resume

High

Low

PERR#

(ICH only: 82801AA)

Periphery

High-Z

Off

PLOCK#

STOP#

Core

High-Z

Off

LPC Interface

LAD[3:0]

Core

High

Off

LFRAME#

IDE Interface

PDA[2:0], SDA[2:0]

PDCS1#, PDCS3#

PDD[15:0], SDD[15:0]

PDDACK#, DDACK#

PDIOR#, PDIOW#

SDCS1#, SDCS3#

SDIOR#, SDIOW#

Core

Low

High

High-Z

High

Undefined

High

Low

High

Off

High-Z

High

Interrupts

PIRQ[A:D]#

SERIRQ

Core

High-Z

Off

APICD[1:0]

USB Interface

USBP0P, USBP0N

USBP1P,USBP1N

Resume

High-Z

3-2

82801AB and 82801AA Datasheet

Power Planes and Pin States

Table 3-2. Power Plane and States for Output and I/O Signals (Sheet 2 of 2)

Immediate

after

PCIRST#

During

PCIRST#

Signal Name

Power Plane

S1

S3

S4/S5

Power Management

SLP_S3#

SLP_S5#

Resume

High

Low

High

Low

SUS_STAT#

SUSCLK

(ICH only: 82801AA)

Resume

Running

Processor Interface

A20M#

IGNNE#

INIT#

Core

Note 1

High-Z

Note 1

High-Z

Low

High-Z

Low

Off

INTR

NMI

Low

SMI#

High-Z

Low

STPCLK#

SMBus Interface

SMBCLK, SMBDATA

Resume

Core

High-Z

Low

High-Z

Off

High-Z

Off

Miscellaneous Signals

Tri-stated

with

internal

pull-up

SPKR

Low

AC’97 Interface

Cold

Reset Bit

(High)

AC_RST#

Resume

Low

AC_SDOUT

AC_SYNC

Core

Low

Running

Low

Off

Unmuxed GPIO Signals

GPIO[21]

GPIO[22]

GPIO[23]

Core

High

Low

High

Defined

Off

Low

GPIO[26]

(unmuxed in ICH0 only:

82801AB)

Resume

Low

Defined

GPIO[27:28]

(unmuxed in ICH0 only:

82801AB)

Note: 1. ICH sets these signals at reset for processor frequency strap.

82801AB and 82801AA Datasheet

3-3

Power Planes and Pin States

3.3

Power Planes for Input Signals

Table 3-3 shows the power plane associated with each input signal, as well as what device drives

the signal at various times. Valid states include:

High

Low

Static: Will be high or low, but will not change

Driven: Will be high or low, and is allowed to change

Running: For input clocks

Table 3-3. Power Plane for Input Signals

Signal Name

Power Well

Driver During Reset

S1

S3

S5

A20GATE

AC_BIT_CLK

AC_SDIN[1:0]

APICCLK

CLK14

Core

External Microcontroller

AC’97 Codec

Static

Low

Resume

Core

AC’97 Codec

Low

Clock Generator

Processor

Running

Static

Low

Core

Low

CLK48

Core

Low

FERR#

Core

Low

CLK66

Hub Interface

RTC

Clock Generator

External Switch

IDE

Running

Driven

High

Low

INTRUDER#

IRQ[15:14]

LDRQ[0]#

LDRQ[1]#

OC[1:0]#

PCICLK

Driven

Low

Driven

Low

Core

LPC Devices

Low

Resume

Core

LPC Devices

High

Low

External Pull-Ups

Clock Generator

IDE Device

Defined

Running

Static

Defined

Low

Defined

Low

PDDREQ

PIORDY

Core

Low

Core

IDE Device

Static

Low

PME#

Resume

Core

Internal Pull-Up

System Power Supply

External Microcontroller

PCI Master

Driven

High

Driven

Low

Driven

Low

PWRBTN#

PWROK

RCIN#

Core

Low

REQ[0:3]#

Core

Driven

Low

REQ[4:5]#

(ICH only: 82801AA)

Core

PCI Master

Driven

Low

REQ[B:A]#

RI#

Core

Resume

RTC

PC/PCI Devices

Serial Port Buffer

External RC circuit

IDE Drive

Driven

High

Low

Defined

High

Low

Defined

High

Low

RSMRST#

RTCRST#

SDDREQ

SERR#

RTC

High

Core

Static

High

Core

PCI Bus Peripherals

IDE Drive

Low

SIORDY

THRM#

Core

Static

Driven

Low

Core

Thermal Sensor

Low

3-4

82801AB and 82801AA Datasheet

Power Planes and Pin States

3.4

Integrated Pull-Ups and Pull-Downs

Table 3-4 shows the ICH signals that have integrated pull-up or pull-down resistors.

Table 3-4. Integrated Pull-Ups and Pull-Downs

Signal

Resistor Value

Resistor Type

PME#

PWRBTN#

9K ±3K

pull-up

LAD[3:0]# / FWH[3:0]#

SPKR¹

9K ±3K

pull-up

22K ±4K

pull-up

AC_SDOUT¹

pull-down

AC_SDIN[1] / GPIO[9]²

AC_SDIN[0]²

AC_BITCLK²

NOTES:

1. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

2. The pull-down resistor on this signal is only enabled when the ACLINK Shut Off bit in the AC’97 Global

Control Register (in AC’97 I/O space) is set to 1. At all other times, the pull-down resistor is disabled.

3.5

IDE Integrated Series Termination Resistors

Table 3-5 shows the ICH IDE signals that have integrated series termination resistors.

Table 3-5. IDE Series Termination Resistors

Signal

Integrated Series Termination Resistor Value

Notes

PDD[15:0], SDD[15:0]

approximately 33 ohms

1

PDIOW#, SDIOW#, PDIOR#, PDIOW#,

PDREQ, SDREQ, PDDACK#, SDDACK#,

PIORDY, SIORDY, PDA[2:0], SDA[2:0],

PDCS1#, SDCS1#, PDCS3#, SDCS3#,

IRQ14, IRQ15

approximately 22 ohms

2

NOTES:

1. Simulation data indicates that these integrated series termination resistors are a nominal 33 ohms; they can

range from 28 ohms to 46 ohms.

2. Simulation data indicates that these integrated series termination resistors are a nominal 22 ohms; they can

range from 19 ohms to 29 ohms.

82801AB and 82801AA Datasheet

3-5

Power Planes and Pin States

3-6

82801AB and 82801AA Datasheet

Clock Domains

4

Table 4-1 shows the system clock domains. Figure 4-1 shows the assumed connection of the

various system components, including the clock generator. For complete details of the system

clocking solution, refer to the system’s clock generator component specification.

Table 4-1. ICH and System Clock Domains

Clock Domain

Frequency

Source

Usage

Main Clock

Generator

ICH CLK66

66 MHz

Hub Interface. Shut off during S3 or below.

Main Clock

Generator

PCI Clock. This clock remains on during S0 state, but can

be shut off during S3 or below.

ICH PCICLK

System PCI

ICH USB

33 MHz

Main Clock

Generator

PCI Bus, LPC interface. These only go to external PCI and

LPC devices.

Main Clock

Generator

48 MHz

USB Controller.

Main Clock

Generator

ICH CLK14

14.31818 MHz

Used for ACPI timer

ICH AC’97

RTC

12.288 MHz

32.768 kHz

AC’97 Codec AC’97 Link. Generated by AC’97 CODEC

ICH

RTC, Power Management. ICH has its own oscillator.

Used for ICH-CPU interrupt messages.

Main Clock

Generator

ICH APIC

16.667 MHz

Figure 4-1. Conceptual System Clock Diagram

Hub Interface (66 MHz)

PCI (33 MHz)

APIC CLK

Clock

Outputs

I/O Controller

Hub

Clock

Generator

14.31818 MHz

48 MHz

32 kHz

XTAL

SUSCLK (32 kHz)

(ICH: 82801AA only)

82801AA and 82801AB Datasheet

4-1

Clock Domains

4-2

82801AA and 82801AB Datasheet

Functional Description

5

5.1

Hub Interface to PCI Bridge (D30:F0)

The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the

ICH implements the buffering and control logic between PCI and the Hub Interface. The

arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must

decode the ranges for the Hub Interface. All register contents are lost when core well power is

removed.

5.1.1

PCI Bus Interface

The ICH PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals are

5V tolerant, except PME#. The ICH integrates a PCI arbiter that supports up to four

(ICH0: 82801AB) or six (ICH: 82801AA) external PCI bus masters in addition to the internal ICH

requests.

Note: Most transactions targeted to the ICH first appear on the external PCI bus before being claimed

back by the ICH. The exceptions are I/O cycles involving USB, IDE, and AC’97. These

transactions complete over the Hub Interface without appearing on the external PCI bus.

Configuration cycles targeting USB, IDE or AC’97 appears on the PCI bus.

Note: If the ICH is programmed for positive decode, the ICH grabs the cycles appearing on the external

PCI bus in medium decode time. If the ICH is programmed for subtractive decode, the ICH grabs

these cycles in subtractive time. If the ICH is programmed for subtractive decode, these cycles can

be grabbed by another positive decode agent out on PCI.

Note: This architecture enables the ability to boot off of a PCI card that positively decodes the boot

cycles. To boot off a PCI card it is necessary to keep the ICH in subtractive decode mode. When

booting off a PCI card, the BOOT_STS bit (bit 2, TCO2 Status Register) is set.

Note: PCI configuration write cycles, initiated by the processor, with the following characteristics are

converted to a special cycle with the Shutdown message type.

— Device Number (AD[15:11]) = 11111

— Function Number (AD[10:8]) = 111

— Register Number (AD[7:2]) = 000000

— Data = 00h

— Bus number matches secondary bus number

5.1.2

PCI-to-PCI Bridge Model

From a software perspective, the ICH contains a PCI-to-PCI bridge. This bridge connects the hub

interface to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH can have its

decode ranges programmed by existing plug-and-play software such that PCI ranges do not

conflict with graphics ranges in the host controller.

82801AA and 82801AB Datasheet

5-1

Functional Description

5.1.3

5.1.4

IDSEL to Device Number Mapping

When addressing devices on the external PCI bus (with the PCI slots) the ICH asserts one address

signal as an IDSEL. When accessing device 0, the ICH asserts AD16. When accessing Device 1,

the ICH asserts AD17. This mapping continues all the way up to device 15 where the ICH asserts

AD31. Note that the ICH’s internal functions (AC’97, IDE, USB, and PCI Bridge) are enumerated

like they are on a separate PCI bus (the Hub Interface) from the external PCI bus.

SERR#/PERR#/NMI# Functionality

Figure 5-1, Figure 5-2, and Figure 5-3 show the logic used to generate/report SERR#, PERR#, and

NMI#. Note that PERR# is only on the ICH (82801AA).

There are several internal and external sources that can cause SERR#. The ICH can be

programmed to cause an NMI based on detecting that an SERR# condition has occurred. The NMI

can also be routed to instead cause an SMI#. Note that the ICH does not drive the external PCI bus

SERR# signal active onto the PCI bus. The external SERR# signal is an input into the ICH driven

only by external PCI devices.

The ICH (82801AA) can detect and report different parity errors in the system. The ICH can be

programmed to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error.

Figure 5-1. NMI# Generation Logic

NMI_SC

[IOCHK_NMI_STS]

IOCHK From SERIRQ Logic

AND

NMI_SC

[IOCHK_NMI_EN]

NMI_SC

[SERR#_NMI_STS]

NMI_SC

[PCI_SERR_EN]

AND

D30:F0 SECSTS

[SSE]

OR

D30:F0 PDSTS

To NMI#

Output

and

Gating

Logic

[SSE]

TCO1_STS

[HCNMI_STS]

OR

AND

TCO1_CNT

[NMI_NOW]

OR

Hub Interface Parity

Error Detected

AND

D30:F0 CMD

[Parity Error Response]

D30:F0 PD_STS

[DPD]

PCI Parity Error detected

during AC'97, IDE or USB

Master Cycle

OR

D30:F0 BRIDGE_CNT

[Parity Error Response

Enable]

D30:F0 SECSTS

[Data Parity Error

Detected]

NMI_EN

[NMI_EN]

PCI Parity Error detected

during LPC or Legacy DMA

Master Cycle

D31:F0 PCISTA

[DPED]

AND

D31:F0 PCICMD

[PER]

Note: Shaded area above is for ICH (82801AA) only

ich_nmi.vsd

5-2

82801AA and 82801AB Datasheet

Functional Description

Figure 5-2. Primary Device Status Register Error Reporting Logic

D30:F0 BRIDGE_CNT

[Parity Error Response Enable]

AND

D30:F0 BRIDGE_CNT

[SERR# Enable]

AND

PCI Address Parity Error

D30:F0 PD_STS

[SSE]

D30:F0 CMD

[SERR_EN]

OR

D30:F0 ERR_STS

[SERR_DTT]

D30:F0 CMD

[SERR_EN]

Delayed Transaction Timeout

AND

D30:F0 ERR_CMD

[SERR_DTT_EN]

AND

SERR# Pin

AND

OR

D30:F0 BRIDGE_CNT

[SERR# Enable]

D30:F0 ERR_CMD

[SERR_RTA_EN]

Received Target Abort

D30:F0 ERR_STS

[SERR_RTA]

Note: Shaded area is for ICH (82801AA) only.

Figure 5-3. Secondary Status Register Error Reporting Logic

D30:F0 BRIDGE_CNT

[SERR# Enable]

AND

D30:F0 SECSTS

[SSE]

PCI Delayed Transaction Timeout

AND

D31:F0 D31_ERR_CFG

[SERR_DTT_EN]

LPC Device Signaling an Error

IOCHK# via SERIRQ

OR

TCO1_STS

[HCSERR_STS]

D31:F0 D31_ERR_CFG

[SERR_RTA_EN]

AND

Received Target Abort

82801AA and 82801AB Datasheet

5-3

Functional Description

5.2

LPC Bridge (with System & Management Functions)

(D31:F0)

The Low Pin Count (LPC) Bridge function of the ICH resides in PCI Device 31:Function 0. In

addition to the LPC bridge function, D31:F0 contains other functional units including DMA,

Interrupt Controllers, Timers, Power Management, System Management, GPIO, and RTC. In this

chapter, registers and functions associated with other functional units (power management, GPIO,

USB, IDE, etc.) are described in their respective sections.

Note: There is a case where the ICH can not accept PCI write cycles from PCI-to-PCI bridges or devices

with similar characteristics to a LPC device. The write cycles can not be accepted by the ICH if the

PCI-to-PCI bridge has an enabled “Retry Read” feature and if there is an outstanding LPC read

cycle towards the same PCI device or bridge. These cycles are not part of normal system operation,

but may be encountered as part of platform validation testing using custom test fixtures.

5.2.1

LPC Interface

The ICH implements an LPC Interface as described in the LPC 1.0 specification. The LPC

Interface to the ICH is shown in Figure 5-4. Note that the ICH implements all of the signals that are

shown as optional, but peripherals are not required to do so.

Figure 5-4. LPC Interface Diagram

PCI Bus

PCI

CLK

RST#

SERIRQ

PME#

LAD[3:0]

LFRAME#

ICH

LDRQ#

(optional)

Super I/O

LPCPD#

(optional)

SUS_STAT#

GPI

LSMI#

(optional)

5-4

82801AA and 82801AB Datasheet

Functional Description

5.2.1.1

LPC Cycle Types

The ICH implements all of the cycle types described in the LPC Interface 1.0 specification.

Table 5-1 shows the cycle types supported by the ICH.

Table 5-1. LPC Cycle Types Supported

Cycle Type

Comment

Memory Read

Memory Write

Single: 1 byte only

1 byte only. ICH breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers.

I/O Read

I/O Write

1 byte only. ICH breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers.

DMA Read

DMA Write

Can be 1, or 2 bytes

Bus Master Read

Bus Master Write

Can be 1, 2, or 4 bytes. (See Note below)

NOTE: Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to

any address. However, the 2-byte transfer must be word aligned (i.e., with an address where A0=0). A

DWord transfer must be DWord-aligned (i.e., with an address where A1and A0 are both 0)

5.2.1.2

Start Field Definition

Table 5-2. Start Field Bit Definitions

Bits[3:0]

Encoding

Definition

0000

0010

0011

1111

Start of cycle for a generic target.

Grant for bus master 0.

Grant for bus master 1.

Stop/Abort: End of a cycle for a target.

NOTE: All other encodings are RESERVED.

82801AA and 82801AB Datasheet

5-5

Functional Description

5.2.1.3

Cycle Type / Direction (CYCTYPE + DIR)

The ICH always drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive

bit 0 to 0. Table 5-3 shows the valid bit encodings:

Table 5-3. Cycle Type Bit Definitions

Bits[3:2]

00

Bit[1]

Definition

0

I/O Read

00

01

10

1

0

1

0

1

I/O Write

Memory Read

Memory Write

DMA Read

DMA Write

Reserved. If a peripheral performing a bus master cycle generates this value, the

ICH aborts the cycle.

11

x

5.2.1.4

SIZE

Bits[3:2] are reserved. The ICH always drives them to 00. Peripherals running bus master cycles

are also supposed to drive 00 for bits 3:2; however, the ICH ignores those bits. Bits[1:0] are

encoded as shown in Table 5-4.

Table 5-4. Transfer Size Bit Definition

Bits[1:0]

00

Size

8 bit transfer (1 byte)

01

10

11

16-bit transfer (2 bytes)

Reserved. The ICH never drives this combination. If a peripheral running a bus master cycle

drives this combination, the ICH may abort the transfer.

32 bit transfer (4 bytes)

5.2.1.5

SYNC

Valid values for the SYNC field are shown in Table 5-5.

Table 5-5. SYNC Bit Definition

Bits[3:0]

Indication

Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request

deassertion and no more transfers desired for that channel.

0000

Short Wait: Part indicating wait states. For bus master cycles, the ICH does not use this

encoding. It, instead, uses the Long Wait encoding (see next encoding below).

0101

0110

Long Wait: Part indicating wait states, and many wait states will be added. This encoding

driven by the ICH for bus master cycles, rather than the Short Wait (0101).

Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and

more DMA transfers desired to continue after this transfer. This value is valid only on DMA

transfers and is not allowed for any other type of cycle.

1001

1010

Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK#

signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious

error in this transfer. For DMA transfers, this not only indicates an error, but also indicates

DMA request deassertion and no more transfers desired for that channel.

NOTE: All other combinations are RESERVED.

5-6

82801AA and 82801AB Datasheet

Functional Description

5.2.1.6

SYNC Time-out

There are several error cases that can occur on the LPC Interface. Table 5-6 indicates the failing

case and the ICH response.

Table 5-6. ICH Response to Sync Failures

Possible Sync Failure

ICH Response

ICH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after

4 consecutive clocks. This could occur if the processor tries to access an I/O

location to which no device is mapped.

ICH aborts the cycle after

the 4^thclock.

ICH drives a Memory, I/O, or DMA cycle, and a peripheral drives more than 8

consecutive valid SYNC to insert wait states using the Short (‘0101b’) encoding Continues waiting

for SYNC. This could occur if the peripheral is not operating properly.

ICH starts a Memory, I/O, or DMA cycle, and a peripheral drives an invalid

SYNC pattern. This could occur if the peripheral is not operating properly or if

there is excessive noise on the LPC Interface.

ICH aborts the cycle when

the invalid Sync is

recognized.

NOTE: There may be other peripheral failure conditions; however, these are not handled by the ICH.

5.2.1.7

SYNC Error Indication

The SYNC protocol allows the peripheral to report an error via the LAD[3:0] = ‘1010b’ encoding.

The intent of this encoding is to give peripherals a method of communicating errors to aid higher

layers with more robust error recovery.

If the ICH was reading data from a peripheral, data is still transferred in the next two nibbles. This

data may be invalid, but it must be transferred by the peripheral. If the ICH was writing data to the

peripheral, the data had already been transferred.

In the case of multiple byte cycles, such as for memory and DMA cycles, an error SYNC

terminates the cycle. Therefore, if the ICH is transferring 4 bytes from a device, if the device

returns the error SYNC in the first byte, the other three bytes are not transferred.

Upon recognizing the SYNC field indicating an error, the ICH treats this the same as IOCHK#

going active on the ISA bus.

5.2.1.8

LFRAME# Usage

Start of Cycle

For Memory, I/O, and DMA cycles, the ICH asserts LFRAME# for 1 clock at the beginning of the

cycle (Figure 5-5) During that clock, the ICH drives LAD[3:0] with the proper START field.

82801AA and 82801AB Datasheet

5-7

Functional Description

Figure 5-5. Typical Timing for LFRAME#

LCLK

LFRAME#

Start

ADDR

1 - 8

TAR

2

Data

Sync

1 - n

Start

TAR

2

LAD[3:0]#

1

CYCTYPE

2

1

Clock Dir & Size Clocks

Clocks Clocks

Clocks

Clock

Abort Mechanism

When performing an Abort, the ICH drives LFRAME# active for 4 consecutive clocks. On the 4^th

clock, it drives LAD[3:0] to ‘1111b’.

Figure 5-6. Abort Mechanism

LCLK

LFRAME#

Start

ADDR

TAR

Sync

Chipset will

drive high

Peripheral must

stop driving

LAD[3:0]#

CYCTYPE

Dir & Size

Too many

Syncs causes

timeout

The ICH performs an abort for the following cases (possible failure cases):

• ICH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after 4

consecutive clocks.

• ICH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.

• A peripheral drives an illegal address when performing bus master cycles.

• A peripheral drives an invalid value.

5-8

82801AA and 82801AB Datasheet

Functional Description

5.2.1.9

I/O Cycles

For I/O cycles targeting registers specified in the ICH’s decode ranges, the ICH performs I/O

cycles as defined in the LPC specification. These are 8-bit transfers. If the processor attempts a

16-bit or 32-bit transfer, the ICH breaks it up into multiple 8-bit transfers.

Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH returns a value of

all 1’s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up

resistors would keep the bus high if no device responds.

5.2.1.10

Bus Master Cycles

The ICH supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC

specification. The ICH has two LDRQ# inputs, and thus supports two separate bus master devices.

It uses the associated START fields for Bus Master 0 (‘0010b’) or Bus Master 1 (‘0011b’).

5.2.1.11

Configuration and ICH Implications

LPC Interface Decoders

To allow the I/O cycles and memory mapped cycles to go to the LPC Interface, the ICH includes

several decoders. During configuration, the ICH must be programmed with the same decode ranges

as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration space.

Bus Master Device Mapping and START Fields

Bus Masters must have a unique START field. In the case of the ICH, which supports 2 bus

masters, it drives 0010 for the START field for grants to bus master #0 (requested via LDRQ[0]#)

and 0011 for grants to bus master #1 (requested via LDRQ[1]#.). Thus no registers are needed to

config the START fields for a particular bus master.

5.3

DMA Operation (D31:F0)

The ICH supports two types of DMA: LPC, and PC/PCI. DMA via LPC is similar to ISA DMA.

LPC DMA and PC/PCI DMA use the ICH’s DMA controller.

The DMA controller has registers that are fixed in the lower 64 KB of I/O space. For PCI

configuration, the controller is configured using registers in the PCI configuration space. These

registers allow configuration of individual channels for use by LPC or PC/PCI DMA.

The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven

independently programmable channels (Figure 5-7). DMA Controller 1 (DMA-1) corresponds to

DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to Channels 5–7. DMA Channel

4 is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode

(DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests

from DMA slaves, the DMA controller also responds to requests that software initiates. Software

may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1.

82801AA and 82801AB Datasheet

5-9

Functional Description

Figure 5-7. ICH DMA Controller

Channel 4

Channel 0

Channel 1

Channel 2

Channel 3

Channel 5

Channel 6

Channel 7

DMA-1

DMA-2

Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0]

are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-

by-words (address shifted) transfers.

The ICH provides 24-bit addressing in compliance with the ISA-Compatible specification. Each

channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant

bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most

significant bits of address.

The DMA controller also features refresh address generation, and autoinitialization following a

DMA termination.

5.3.1

Channel Priority

For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and

channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA

Command Register.

DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a

software request for DMA service can be presented through each channel's DMA Request Register.

A software request is subject to the same prioritization as any hardware request. Please see the

detailed register description for Request Register programming information in the DMA Register

description section.

Fixed Priority

The initial fixed priority structure is as follows:

High priority.....Low priority

(0, 1, 2, 3)

(5, 6, 7)

The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, Channel 0 has the highest

priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority

position of Channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7.

Rotating Priority

Rotation allows for "fairness" in priority resolution. The priority chain rotates so that the last

channel serviced is assigned the lowest priority in the channel group (0–3, 5–7). Channels 0–3

rotate as a group of 4. They are always placed between Channel 5 and Channel 7 in the priority list.

Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three positions in

the rotation, while channel group (0–3) comprises the fourth position in the arbitration.

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82801AA and 82801AB Datasheet

Functional Description

5.3.2

5.3.3

Address Compatibility Mode

Whenever the DMA is operating, the addresses do not increment or decrement through the High

and Low Page Registers. Therefore, if a 24 bit address is 01FFFFh and increments, the next address

is 010000h, not 020000h. Similarly, if a 24 bit address is 020000h and decrements, the next address

is 02FFFFh, not 01FFFFh. This is compatible with the 82C37 and Page Register implementation

used in the PC-AT. This mode is set after CPURST is valid.

Summary of DMA Transfer Sizes

Table 5-7 lists each of the DMA device transfer sizes. The column labeled "Current Byte/Word

Count Register" indicates that the register contents represents either the number of bytes to transfer

or the number of 16-bit words to transfer. The column labeled "Current Address Increment/

Decrement" indicates the number added to or taken from the Current Address register after each

DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register

is incremented or decremented.

Address Shifting When Programmed for 16-Bit I/O Count by Words

Table 5-7. DMA Transfer Size

Current Byte/Word Count

Register

Current Address

Increment/Decrement

DMA Device Date Size And Word Count

8-Bit I/O, Count By Bytes

Bytes

1

16-Bit I/O, Count By Words (Address Shifted)

Words

The ICH maintains compatibility with the implementation of the DMA in the PC AT which used

the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words.

Note that the least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When

programming the Current Address Register (when the DMA channel is in this mode), the Current

Address must be programmed to an even address with the address value shifted right by one bit.

The address shifting is shown in Table 5-8.

Table 5-8. Address Shifting in 16-bit I/O DMA Transfers

16-Bit I/O Programmed Address

Output

Address

8-Bit I/O Programmed Address

(Ch 0–3)

(Ch 5–7)

(Shifted)

A0

0

A[16:1]

A[23:17]

A[16:1]

A[23:17]

A[15:0]

A[23:17]

NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

82801AA and 82801AB Datasheet

5-11

Functional Description

5.3.4

Autoinitialize

By programming a bit in the DMA Channel Mode Register, a channel may be set up as an

autoinitialize channel. When a channel undergoes autoinitialization, the original values of the

Current Page, Current Address and Current Byte/Word Count Registers are automatically restored

from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The

Base Registers are loaded simultaneously with the Current Registers by the microprocessor when

the DMA channel is programmed and remain unchanged throughout the DMA service. The mask

bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to

perform another DMA service, without processor intervention, as soon as a valid DREQ is

detected.

5.3.5

Software Commands

There are three additional special software commands that the DMA controller can execute. The

three software commands are:

1. Clear Byte Pointer Flip-Flop

2. Master Clear

3. Clear Mask Register

They do not depend on any specific bit pattern on the data bus.

Clear Byte Pointer Flip-Flop

This command is executed prior to writing or reading new address or word count information

to/from the DMA controller. This initializes the flip-flop to a known state so that subsequent

accesses to register contents by the microprocessor addresses upper and lower bytes in the correct

sequence.

When the Host processor is reading or writing DMA registers, two Byte Pointer flip-flops are used;

one for channels 0–3 and one for channels 4–7. Both of these act independently. There are separate

software commands for clearing each of them (0Ch for channels 0–3, 0D8h for channels 4–7).

DMA Master Clear

This software instruction has the same effect as the hardware reset. The Command, Status,

Request, and Internal First/Last Flip-Flop Registers are cleared and the Mask Register is set. The

DMA controller enters the idle cycle.

There are two independent master clear commands:

• 0Dh which acts on channels 0–3

• 0DAh which acts on channels 4–7.

Clear Mask Register

This command clears the mask bits of all four channels, enabling them to accept DMA requests.

I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7.

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82801AA and 82801AB Datasheet

Functional Description

5.4

PCI DMA

The ICH provides support for the PC/PCI DMA protocol. PC/PCI DMA uses dedicated REQUEST

and GRANT signals to permit PCI devices to request transfers associated with specific DMA

channels. Upon receiving a request and getting control of the PCI bus, ICH performs a two-cycle

transfer. For example, if data is to be moved from the peripheral to main memory, ICH first reads

data from the peripheral and then write it to main memory. The location in main memory is the

Current Address Registers in the 8237. ICH supports up to 2 PC/PCI REQ/GNT pairs, REQ[A:B]#

and GNT[A:B]#.

A 16-bit register is included in the ICH Function 0 configuration space at offset 90h. It is divided

into seven 2-bit fields that are used to configure the 7 DMA channels. Each DMA channel can be

configured to one of two options:

• LPC DMA

• PC/PCI style DMA using the REQ/GNT signals

It is not possible for a particular DMA channel to be configured for more than one style of DMA;

however, the seven channels can be programmed independently. For example, channel 3 could be

set up for PC/PCI and channel 5 set up for LPC DMA.

The ICH REQ[A:B]# and GNT[A:B]# can be configured for support of a PC/PCI DMA Expansion

agent. The PCI DMA Expansion agent can then provide DMA service or ISA Bus Master service

using the ICH DMA controller. The REQ#/GNT# pair must follow the PC/PCI serial protocol

described below.

5.4.1

PCI DMA Expansion Protocol

The PCI expansion agent must support the PCI expansion Channel Passing Protocol defined in

Figure 5-8 for both the REQ# and GNT# pins.

Figure 5-8. DMA Serial Channel Passing Protocol

PCICLK

REQ#

GNT#

Start CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

Start

Bit0

Bit1

Bit2

The requesting device must encode the channel request information as shown above, where

CH0–CH7 are one clock active high states representing DMA channel requests 0–7.

The ICH encodes the granted channel on the GNT# line as shown above, where the bits have the

same meaning as shown in Figure 5-8. For example, the sequence [start, bit 0, bit 1, bit 2]=[0,1,0,0]

grants DMA channel 1 to the requesting device, and the sequence [start, bit 0, bit 1, bit 2]=[0,0,1,1]

grants DMA channel 6 to the requesting device.

82801AA and 82801AB Datasheet

5-13

Functional Description

All PCI DMA expansion agents must use the channel passing protocol described above. They must

also work as follows:

1. If a PCI DMA expansion agent has more than one request active, it must resend the request

serial protocol after one of the requests has been granted the bus and it has completed its

transfer. The expansion device should drive its REQ# inactive for two clocks and then transmit

the serial channel passing protocol again, even if there are no new requests from the PCI

expansion agent to ICH. For example: If a PCI expansion agent had active requests for DMA

Channel 1 and Channel 5, it would pass this information to the ICH through the expansion

channel passing protocol. If after receiving GNT# (assume for CH5) and having the device

finish its transfer (device stops driving request to PCI expansion agent) it would then need to

re-transmit the expansion channel passing protocol to inform ICH that DMA channel 1 was

still requesting the bus, even if that was the only request the expansion device had pending.

2. If a PCI DMA expansion agent has a request go inactive before ICH asserts GNT#, it must

resend the expansion channel passing protocol to update ICH with this new request

information. For example: If a PCI expansion agent has DMA channel 1 and 2 requests

pending, it sends them serially to ICH using the expansion channel passing protocol. If,

however, DMA channel 1 goes inactive into the expansion agent before the expansion agent

receives a GNT# from ICH, the expansion agent MUST pull its REQ# line high for ONE clock

and resend the expansion channel passing information with only DMA channel 2 active. Note

that ICH does not do anything special to catch this case because a DREQ going inactive before

a DACK# is received is not allowed in the ISA DMA protocol and, therefore, does not need to

work properly in this protocol either. This requirement is needed to be able to support Plug-n-

Play ISA devices that toggle DREQ# lines to determine if those lines are free in the system.

3. If a PCI expansion agent has sent its serial request information and receives a new DMA

request before receiving GNT# the agent must resend the serial request with the new request

active. For example, if a PCI expansion agent has already passed requests for DMA channel 1

and 2 and sees DREQ 3 active before a GNT is received, the device must pull its REQ# line

high for one clock and resend the expansion channel passing information with all three

channels active.

The three cases above require the following functionality in the PCI DMA expansion device:

1. Drive REQ# inactive for one clock to signal new request information.

2. Drive REQ# inactive for two clocks to signal that a request that had been granted the bus has

gone inactive.

3. The REQ# and GNT# state machines must run independently and concurrently (i.e., a GNT#

could be received while in the middle of sending a serial REQ# or a GNT# could be active

while REQ# is inactive).

5.4.2

PCI DMA Expansion Cycles

The ICH’s support of the PC/PCI DMA Protocol currently consists of four types of cycles:

Memory to I/O, I/O to Memory, Verify, and ISA Master cycles. ISA Masters are supported through

the use of a DMA channel that has been programmed for cascade mode.

The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA

"fly-by" cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory

read or memory write bus cycle, its address representing the selected memory.

The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses

(Table 5-9). Note that these cycles must be qualified by an active GNT# signal to the requesting

device.

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82801AA and 82801AB Datasheet

Functional Description

Table 5-9. DMA Cycle vs. I/O Address

DMA Cycle Type

DMA I/O Address

PCI Cycle Type

Normal

Normal TC

Verify

00h

04h

I/O Read/Write

I/O Read

0C0h

0C4h

Verify TC

I/O Read

5.4.3

5.4.4

DMA Addresses

The memory portion of the cycle generates a PCI memory read or memory write bus cycle, its

address representing the selected memory. The I/O portion of the DMA cycle generates a PCI

I/O cycle to one of the four I/O addresses listed in Table 5-9.

DMA Data Generation

The data generated by PC/PCI devices on I/O reads when they have an active GNT# is on the lower

two bytes of the PCI AD bus. Table 5-10 lists the PCI pins that the data appears on for 8 and 16 bit

channels. Each I/O read results in one memory write, and each memory read results in one

I/O write. If the I/O device is 8 bit, the ICH performs an 8 bit memory write. The ICH does not

assemble the I/O read into a DWord for writing to memory. Similarly, the ICH does not

disassemble a DWord read from memory to the I/O device.

Table 5-10. PCI Data Bus vs. DMA I/O port size

PCI DMA I/O Port Size

PCI Data Bus Connection

Byte

AD[7:0]

Word

AD[15:0]

5.4.5

DMA Byte Enable Generation

The byte enables generated by the ICH on I/O reads and writes must correspond to the size of the

I/O device. Table 5-11 defines the byte enables asserted for 8 and 16 bit DMA cycles.

Table 5-11. DMA I/O Cycle Width vs. BE[3:0]#

BE[3:0]#

Description

1110b

1100b

8-bit DMA I/O Cycle: Channels 0-3

16-bit DMA I/O Cycle: Channels 5-7

NOTE: For verify cycles the value of the Byte Enables (BEs) is a “don’t care”.

82801AA and 82801AB Datasheet

5-15

Functional Description

5.4.6

DMA Cycle Termination

DMA cycles are terminated when a terminal count is reached in the DMA controller and the

channel is not in autoinitialize mode, or when the PC/PCI device deasserts its request. The PC/PCI

device must follow explicit rules when deasserting its request, or the ICH may not see it in time and

run an extra I/O and memory cycle.

The PC/PCI device must deassert its request 7 PCICLKs before it generates TRDY# on the I/O

read or write cycle, or the ICH is allowed to generate another DMA cycle. For transfers to memory,

this means that the memory portion of the cycle is run without an asserted PC/PCI REQ#.

5.5

LPC DMA

DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special

encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported

on the LPC interface. Channel’s 0 - 3 are 8 bit channels. Channel’s 5 - 7 are 16 bit channels.

Channel 4 is reserved as a generic bus master request.

5.5.1

Asserting DMA Requests

Peripherals that need DMA service encode their requested channel number on the LDRQ# signal.

To simplify the protocol, each peripheral on the LPC Interface has its own dedicated LDRQ# signal

(they may not be shared between two separate peripherals). The ICH has two LDRQ# inputs,

allowing at least two devices to support DMA or bus mastering.

LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-9 the peripheral uses the

following serial encoding sequence:

• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle

conditions.

• The next 3 bits contain the encoded DMA channel number (MSB first).

• The next bit (ACT) indicates whether the request for the indicated DMA channel is active or

inactive. The ACT bit is a 1 (high) to indicate if it is active and 0 (low) if it is inactive. The

case where ACT is low is rare, and is only used to indicate that a previous request for that

channel is being abandoned.

• After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After

that one clock, LDRQ# signal can be brought low to the next encoding sequence.

If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#.

For example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before

the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for

channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC

interface, and the I/O device does not need to self-arbitrate before sending the message.

Figure 5-9. DMA Request Assertion Through LDRQ#

LCLK

LDRQ#

Start

MSB

LSB

ACT

Start

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82801AA and 82801AB Datasheet

Functional Description

5.5.2

Abandoning DMA Requests

DMA Requests can be deasserted in two fashions: on error conditions by sending an LDRQ#

message with the ‘ACT’ bit set to ‘0’, or normally through a SYNC field during the DMA transfer.

This section describes boundary conditions where the DMA request needs to be removed prior to a

data transfer.

There may be some special cases where the peripheral desires to abandon a DMA transfer. The

most likely case of this occurring is due to a floppy disk controller which has overrun or underrun

its FIFO, or software stopping a device prematurely.

In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an

LDRQ# message with the ACT bit as ‘0’. However, since the DMA request was seen by the ICH,

there is no guarantee that the cycle has not been granted and will shortly run on LPC. Therefore,

peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not

to respond to this cycle, in which case the host aborts it, or it can choose to complete the cycle

normally with any random data.

This method of DMA deassertion should be prevented whenever possible, to limit boundary

conditions both on the ICH and the peripheral.

5.5.3

General Flow of DMA Transfers

Arbitration for DMA channels is performed through the 8237 within the host. Once the host has

won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC

Interface and begins the DMA transfer. The general flow for a basic DMA transfer is as follows:

1. ICH starts transfer by asserting ‘0000b’ on LAD[3:0] with LFRAME# asserted.

2. ICH asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.

3. ICH asserts channel number and, if applicable, terminal count.

4. ICH indicates the size of the transfer: 8 or 16 bits.

5. If a DMA read…

— The ICH drives the first 8 bits of data and turns the bus around.

— The peripheral acknowledges the data with a valid SYNC.

— If a 16 bit transfer, the process is repeated for the next 8 bits.

6. If a DMA write…

— The ICH turns the bus around and waits for data.

— The peripheral indicates data ready through SYNC and transfers the first byte.

— If a 16 bit transfer, the peripheral indicates data ready and transfers the next byte.

7. The peripheral turns around the bus.

82801AA and 82801AB Datasheet

5-17

Functional Description

5.5.4

Terminal Count

Terminal count is communicated through LAD[3] on the same clock that DMA channel is

communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last

byte of transfer, based upon the size of the transfer.

For example, on an 8 bit transfer size (SIZE field is ‘00b’), if the TC bit is set, then this is the last

byte. On a 16 bit transfer (SIZE field is ‘01b’), if the TC bit is set, then the second byte is the last

byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is

communicated, and only signal TC when the last byte of that transfer size has been transferred.

5.5.5

5.5.6

Verify Mode

Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a

DMA write, where the peripheral is transferring data to main memory. The indication from the host

is the same as a DMA write, so the peripheral will be driving data onto the LPC interface.

However, the host does not transfer this data into main memory.

DMA Request Deassertion

An end of transfer is communicated to the ICH through a special SYNC field transmitted by the

peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting

LDREQ#. If a DMA transfer is several bytes, such as a transfer from a demand mode device, the

ICH needs to know when to deassert the DMA request based on the data currently being

transferred.

The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to

the ICH whether this is the last byte of transfer or if more bytes are requested. To indicate the last

byte of transfer, the peripheral uses a SYNC value of ‘0000b’ (ready with no error), or ‘1010b’

(ready with error). These encodings tell the ICH that this is the last piece of data transferred on a

DMA read (ICH to peripheral), or the byte which follows is the last piece of data transferred on a

DMA write (peripheral to ICH).

When the ICH sees one of these two encodings, it ends the DMA transfer after this byte and

deasserts the DMA request to the 8237. Therefore, if the ICH indicated a 16 bit transfer, the

peripheral can end the transfer after one byte by indicating a SYNC value of ‘0000b’ or ‘1010b’.

The ICH does not attempt to transfer the second byte, and deasserts the DMA request internally.

If the peripheral indicates a ‘0000b’ or ‘1010b’ SYNC pattern on the last byte of the indicated size,

then the ICH only deasserts the DMA request to the 8237 since it does not need to end the transfer.

If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of ‘1001b’

(ready plus more data). This tells the 8237 that more data bytes are requested after the current byte

has been transferred, so the ICH keeps the DMA request active to the 8237. Therefore, on an 8 bit

transfer size, if the peripheral indicates a SYNC value of ‘1001b’ to the ICH, the data is transferred

and the DMA request remains active to the 8237. At a later time, the ICH then comes back with

another START - CYCTYPE - CHANNEL - SIZE etc. combination to initiate another transfer to

the peripheral.

The peripheral must not assume that the next START indication from the ICH is another grant to

the peripheral if it had indicated a SYNC value of ‘1001b’. On a single mode DMA device, the

8237 re-arbitrates after every transfer. Only demand mode DMA devices can be guaranteed that

they receive the next START indication from the ICH.

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82801AA and 82801AB Datasheet

Functional Description

Note: Indicating a ‘0000b’ or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit channel

(first byte of a 16 bit transfer) is an error condition.

Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on

DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred,

incrementing the 8237’s address and decrementing its byte count.

5.5.7

SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended

through a SYNC field during the DMA transfer, the peripheral must obey the following rule when

initiating back-to-back transfers from a DMA channel.

The peripheral must not assert another message for 8 LCLKs after a deassertion is indicated

through the SYNC field. This is needed to allow the 8237, which typically runs off a much slower

internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next

agent.

Under default operation, the host only performs 8 bit transfers on 8 bit channels and 16 bit transfers

on 16 bit channels.

The method by which this communication between host and peripheral through system BIOS is

performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are

motherboard devices, no “plug-n-play” registry is required.

The peripheral must not assume that the host is able to perform transfer sizes that are larger than

the size allowed for the DMA channel, and is willing to accept a SIZE field that is smaller than

what it may currently have buffered.

To that end, it is recommended that future devices which may appear on the LPC bus, which

require higher bandwidth than 8 bit or 16 bit DMA allow, do so with a bus mastering interface and

not rely on the 8237.

82801AA and 82801AB Datasheet

5-19

Functional Description

5.6

8254 Timers (D31:F0)

The ICH contains three counters which have fixed uses. All registers and functions associated with

the 8254 timers are in the Core well. The 8254 unit is clocked by a 14.31818 MHz clock.

Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is typically

programmed for Mode 3 operation. The counter produces a square wave with a period equal to the

product of the counter period (838 ns) and the initial count value. The counter loads the initial

count value one counter period after software writes the count value to the counter I/O address. The

counter initially asserts IRQ0 and decrements the count value by two each counter period. The

counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and

again decrements the initial count value by two each counter period. The counter then asserts IRQ0

when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately

asserting and negating IRQ0.

Counter 1, Refresh Request Signal

This counter provides the refresh request signal and is typically programmed for Mode 2 operation.

The counter negates refresh request for one counter period (838 ns) during each count cycle. The

initial count value is loaded one counter period after being written to the counter I/O address. The

counter initially asserts refresh request, and negates it for 1 counter period when the count value

reaches 1. The counter then asserts refresh request and continues counting from the initial count

value.

Counter 2, Speaker Tone

This counter provides the speaker tone and is typically programmed for Mode 3 operation. The

counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by

the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and

Control ports).

5.6.1

Timer Programming

The counter/timers are programmed in the following fashion:

1. Write a control word to select a counter

2. Write an initial count for that counter.

3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the

16-bit counter.

4. Repeat with other counters

Only two conventions need to be observed when programming the counters. First, for each counter,

the control word must be written before the initial count is written. Second, the initial count must

follow the count format specified in the control word (least significant byte only, most significant

byte only, or least significant byte and then most significant byte).

A new initial count may be written to a counter at any time without affecting the counter's

programmed mode. Counting is affected as described in the mode definitions. The new count must

follow the programmed count format.

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82801AA and 82801AB Datasheet

Functional Description

If a counter is programmed to read/write two-byte counts, the following precaution applies: A

program must not transfer control between writing the first and second byte to another routine

which also writes into that same counter. Otherwise, the counter is loaded with an incorrect count.

The Control Word Register at port 43h controls the operation of all three counters. Several

commands are available:

• Control Word Command. Specifies which counter to read or write, the operating mode, and

the count format (binary or BCD).

• Counter Latch Command. Latches the current count so that it can be read by the system. The

countdown process continues.

• Read Back Command. Reads the count value, programmed mode, the current state of the

OUT pins, and the state of the Null Count Flag of the selected counter.

Table 5-12 lists the six operating modes for the interval counters.

Table 5-12. Counter Operating Modes

Mode

Function

Out signal on end of count (=0)

Description

Output is ‘0’. When count goes to 0, output goes to ‘1’ and

stays at ‘1’ until counter is reprogrammed.

0

Output is ‘0’. When count goes to 0, output goes to ‘1’ for

one clock time.

1

2

Hardware retriggerable one-shot

Output is ‘1’. Output goes to ‘0’ for one clock time, then

back to ‘1’ and counter is reloaded.

Rate generator (divide by n counter)

Output is ‘1’. Output goes to ‘0’ when counter rolls over,

and counter is reloaded. Output goes to ‘1’ when counter

rolls over, and counter is reloaded, etc.

3

Square wave output

Output is ‘1’. Output goes to ‘0’ when count expires for

one clock time.

4

5

Software triggered strobe

Hardware triggered strobe

Output is ‘1’. Output goes to ‘0’ when count expires for

one clock time.

5.6.2

Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in progress. There

are three methods for reading the counters: a simple read operation, counter Latch Command, and

the Read-Back Command. Each is explained below.

With the simple read and counter latch command methods, the count must be read according to the

programmed format; specifically, if the counter is programmed for two byte counts, two bytes must

be read. The two bytes do not have to be read one right after the other. Read, write, or programming

operations for other counters may be inserted between them.

Simple Read

The first method is to perform a simple read operation. The counter is selected through port 40h

(counter 0), 41h (counter 1), or 42h (counter 2).

Note: Performing a direct read from the counter does not return a determinate value, because the counting

process is asynchronous to read operations. However, in the case of counter 2, the count can be

stopped by writing to the GATE bit in port 61h.

82801AA and 82801AB Datasheet

5-21

Functional Description

Counter Latch Command

The Counter Latch Command, written to port 43h, latches the count of a specific counter at the

time the command is received. This command is used to ensure that the count read from the counter

is accurate, particularly when reading a two-byte count. The count value is then read from each

counter's Count Register as was programmed by the Control Register.

The count is held in the latch until it is read or the counter is reprogrammed. The count is then

unlatched. This allows reading the contents of the counters on the fly without affecting counting in

progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter

Latch Commands do not affect the programmed mode of the counter in any way.

If a Counter is latched and then, some time later, latched again before the count is read, the second

Counter Latch Command is ignored. The count read is the count at the time the first Counter Latch

Command was issued.

Read Back Command

The Read Back Command, written to port 43h, latches the count value, programmed mode, and

current states of the OUT pin and Null Count flag of the selected counter or counters. The value of

the counter and its status may then be read by I/O access to the counter address.

The Read Back Command may be used to latch multiple counter outputs at one time. This single

command is functionally equivalent to several counter latch commands, one for each counter

latched. Each counter's latched count is held until it is read or reprogrammed. Once read, a counter

is unlatched. The other counters remain latched until they are read. If multiple count Read Back

Commands are issued to the same counter without reading the count, all but the first are ignored.

The Read Back Command may additionally be used to latch status information of selected

counters. The status of a counter is accessed by a read from that counter's I/O port address. If

multiple counter status latch operations are performed without reading the status, all but the first

are ignored.

Both count and status of the selected counters may be latched simultaneously. This is functionally

the same as issuing two consecutive, separate Read Back Commands. If multiple count and/or

status Read Back Commands are issued to the same counters without any intervening reads, all but

the first are ignored.

If both count and status of a counter are latched, the first read operation from that counter returns

the latched status, regardless of which was latched first. The next one or two reads, depending on

whether the counter is programmed for one or two type counts, return the latched count.

Subsequent reads return unlatched count.

5-22

82801AA and 82801AB Datasheet

Functional Description

5.7

8259 Interrupt Controllers (PIC) (D31:F0)

The ICH incorporates the functionality of two 8259 interrupt controllers that provide system

interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard

controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition,

this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the

compatible ISA interrupt line. Each 8259 core supports 8 interrupts, numbered 0 - 7. Table 5-13

shows how the cores are connected

.

Table 5-13. Interrupt Controller Core Connections

8259

Input

Typical Interrupt

Source

8259

Connected Pin / Function

0

1

2

3

4

5

6

7

0

1

2

3

4

Internal

Keyboard

Internal Timer / Counter 0 output

IRQ1 via SERIRQ

Internal

Slave Controller INTR output

IRQ3 via SERIRQ

Serial Port A

Serial Port B

Parallel Port / Generic

Floppy Disk

Master

IRQ4 via SERIRQ

IRQ5 via SERIRQ

IRQ6 via SERIRQ

Parallel Port / Generic

Internal Real Time Clock

Generic

IRQ7 via SERIRQ

Internal RTC

IRQ9 via SERIRQ

Generic

IRQ10 via SERIRQ

IRQ11 via SERIRQ

IRQ12 via SERIRQ

Generic

Slave

PS/2 Mouse

State Machine output based on processor FERR#

assertion.

5

Internal

6

7

Primary IDE cable

IRQ14 from input signal or via SERIRQ

IRQ15 from input signal or via SERIRQ

Secondary IDE Cable

The ICH cascades the slave controller onto the master controller through master controller

interrupt input 2. This means there are only 15 possible interrupts for the ICH PIC. Interrupts can

individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13.

Note: Previous devices internally latched IRQ12 and IRQ1 and required a port 60h read to clear the latch.

The ICH can be programmed to latch IRQ12 or IRQ1 (see bit 11 and bit 12 in General Control

Register, Section 8.1.21).

5.7.1

Interrupt Handling

Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt

level. These bits are used to determine the interrupt vector returned, and status of any other pending

interrupts. Table 5-14 defines the IRR, ISR and IMR.

82801AA and 82801AB Datasheet

5-23

Functional Description

Table 5-14. Interrupt Status Registers

Bit

Description

Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge

mode, and by an active high level in level mode. This bit is set whether or not the interrupt is

masked. However, a masked interrupt does not generate INTR.

IRR

Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt

acknowledge cycle is seen, and the vector returned is for that interrupt.

ISR

Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts do

not generate INTR.

IMR

Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle which is translated by the host bridge into

a PCI Interrupt Acknowledge Cycle to the ICH. The PIC translates this command into two internal

INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the

state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends

the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon

bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt

within that controller.

Table 5-15. Content of Interrupt Vector Byte

Master,Slave Interrupt

Bits [7:3]

Bits [2:0]

IRQ7,15

IRQ6,14

IRQ5,13

IRQ4,12

IRQ3,11

IRQ2,10

IRQ1,9

111

110

101

100

011

010

001

000

ICW2[7:3]

IRQ0,8

5-24

82801AA and 82801AB Datasheet

Functional Description

Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in

level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active (low) to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The

cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is

broadcast over PCI by the ICH.

4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH converts it into the two

cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt

acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers.

5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set

and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave

identification code is broadcast by the master to the slave on a private, internal three bit wide

bus. The slave controller uses these bits to determine if it must respond with an interrupt vector

during the second INTA# pulse.

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt

vector. If no interrupt request is present because the request was too short in duration, the PIC

returns vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second

INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued

at the end of the interrupt subroutine.

5.7.2

Initialization Command Words (ICWx)

Before operation can begin, each 8259 must be initialized. In the ICH, this is a four byte sequence.

The four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and

ICW4.

The base address for each 8259 initialization command word is a fixed location in the I/O memory

space: 20h for the master controller, and A0h for the slave controller.

ICW1

An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted

as a write to ICW1. Upon sensing this write, the ICH PIC expects three more byte writes to 21h for

the master controller, or A1h for the slave controller, to complete the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to

generate an interrupt.

2. The Interrupt Mask Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special Mask Mode is cleared and Status Read is set to IRR.

82801AA and 82801AB Datasheet

5-25

Functional Description

ICW2

The second write in the sequence, ICW2, is programmed to provide bits [7:3] of the interrupt

vector that is released during an interrupt acknowledge. A different base is selected for each

interrupt controller.

ICW3

The third write in the sequence, ICW3, has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the

slave controller. Within the ICH, IRQ2 is used. Therefore, bit 2 of ICW3 on the master

controller is set to a 1, and the other bits are set to 0's.

• For the slave controller, ICW3 is the slave identification code used during an interrupt

acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code

to the slave controller if the cascaded interrupt won arbitration on the master controller. The

slave controller compares this identification code to the value stored in its ICW3, and if it

matches, the slave controller assumes responsibility for broadcasting the interrupt vector.

ICW4

The final write in the sequence, ICW4, must be programmed both controllers. At the very least, bit

0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based

system.

5.7.3

5.7.4

Operation Command Words (OCW)

These command words reprogram the Interrupt Controller to operate in various interrupt modes.

• OCW1 masks and unmasks interrupt lines.

• OCW2 controls the rotation of interrupt priorities when in rotating priority mode, and controls

the EOI function.

• OCW3 is sets up ISR/IRR reads, enables/disables the Special Mask Mode SMM, and

enables/disables polled interrupt mode.

Modes of Operation

Fully Nested Mode

In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest.

When an interrupt is acknowledged, the highest priority request is determined and its vector placed

on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the

processor issues an EOI command immediately before returning from the service routine; or if in

AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further

interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt.

Interrupt priorities can be changed in the rotating priority mode.

5-26

82801AA and 82801AB Datasheet

Functional Description

Special Fully Nested Mode

This mode is used in the case of a system where cascading is used, and the priority has to be

conserved within each slave. In this case, the special fully nested mode is programmed to the

master controller. This mode is similar to the fully nested mode with the following exceptions:

• When an interrupt request from a certain slave is in service, this slave is not locked out from

the master's priority logic and further interrupt requests from higher priority interrupts within

the slave is recognized by the master and initiates interrupts to the processor. In the normal

nested mode, a slave is masked out when its request is in service.

• When exiting the Interrupt Service routine, software has to check whether the interrupt

serviced was the only one from that slave. This is done by sending a Non-Specific EOI

command to the slave and then reading its ISR. If it is 0, a non-specific EOI can also be sent to

the master.

Automatic Rotation Mode (Equal Priority Devices)

In some applications, there are a number of interrupting devices of equal priority. Automatic

rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest

priority after being serviced. In the worst case, a device requesting an interrupt has to wait until

each of seven other devices are serviced at most once.

There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific

EOI Command (R=1, SL=0, EOI=1) and the Rotate in Automatic EOI Mode which is set by (R=1,

SL=0, EOI=0).

Specific Rotation Mode (Specific Priority)

Software can change interrupt priorities by programming the bottom priority. For example, if IRQ5

is programmed as the bottom priority device, then IRQ6 is the highest priority device. The Set

Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO-L2 is the

binary priority level code of the bottom priority device.

In this mode, internal status is updated by software control during OCW2. However, it is

independent of the EOI command. Priority changes can be executed during an EOI command by

using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO-L2=IRQ level

to receive bottom priority.

Poll Mode

Poll Mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can

be serviced by one interrupt service routine do not need separate vectors if the service routine uses

the poll command. Polled Mode can also be used to expand the number of interrupts. The polling

interrupt service routine can call the appropriate service routine, instead of providing the interrupt

vectors in the vector table. In this mode, the INTR output is not used and the microprocessor

internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is

achieved by software using a Poll Command.

The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an

interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level.

Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read

contains a ‘1’ in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits

2:0.

82801AA and 82801AB Datasheet

5-27

Functional Description

Cascade Mode

The PIC in the ICH has one master 8259 and one slave 8259 cascaded onto the master through

IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the

slaves through a three bit internal bus. In the ICH, when the master drives 010b on this bus, the

slave controller takes responsibility for returning the interrupt vector. An EOI Command must be

issued twice: once for the master and once for the slave.

Edge and Level Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the

entire controller. In the ICH, this bit is disabled and a new register for edge and level triggered

mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1

and ELCR2.

If an ELCR bit is ‘0’, an interrupt request is recognized by a low to high transition on the

corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If

an ELCR bit is ‘1’, an interrupt request is recognized by a high level on the corresponding IRQ

input and there is no need for an edge detection. The interrupt request must be removed before the

EOI command is issued to prevent a second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling

edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7

vector is returned.

End of Interrupt Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC before

returning from a service routine, the EOI command; or automatically when AEOI bit in ICW1 is

set to 1.

Normal End of Interrupt

In Normal EOI, software writes an EOI command before leaving the interrupt service routine to

mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-

Specific. When a Non-Specific EOI command is issued, the PIC clears the highest ISR bit of those

that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the ICH, as

the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When

the PIC is operated in modes which preserve the fully nested structure, software can determine

which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked is not be cleared by a

Non-Specific EOI if the PIC is in the Special Mask Mode. An EOI command must be issued for

both the master and slave controller.

Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the trailing edge of

the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only

when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode

can only be used in the master controller and not the slave controller.

5-28

82801AA and 82801AB Datasheet

Functional Description

5.7.5

Masking Interrupts

Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This

register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking

IRQ2 on the master controller masks all requests for service from the slave controller.

Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the system priority

structure during its execution under software control. For example, the routine may wish to inhibit

lower priority requests for a portion of its execution but enable some of them for another portion.

The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register.

Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to

clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the Special Mask

Mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate

pattern. The special Mask Mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where

SSMM=1, SMM=0.

5.7.6

Steering PCI Interrupts

The ICH can be programmed to allow PIRQA#-PIRQD# to be internally routed to interrupts 3-7,

9-12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers,

located at 60-63h in function 0. One or more PIRQx# lines can be routed to the same IRQx input. If

interrupt steering is not required, the Route Registers can be programmed to disable steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI

Board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line,

software must change the IRQ's corresponding ELCR bit to level sensitive mode. The ICH

internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is

routed onto the PIC, the selected IRQ can no longer be used by an ISA device (through SERIRQ).

However, active low non-ISA interrupts can share their interrupt with PCI interrupts.

82801AA and 82801AB Datasheet

5-29

Functional Description

5.8

Advanced Interrupt Controller (APIC) (D31:F0)

In addition to the standard ISA compatible interrupt controller (PIC) described in the previous

chapter, the ICH incorporates the Advanced Programmable Interrupt Controller (APIC). While the

standard interrupt controller is intended for use in a uni-processor system, APIC can be used in

either a uni-processor or multi-processor system.

5.8.1

Interrupt Handling

The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:

• Method of Interrupt Transmission. The I/O APIC transmits interrupts through a three wire

bus, and interrupts are handled without the need for the processor to run an interrupt

acknowledge cycle.

• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt

number. For example, interrupt 10 can be given a higher priority than interrupt 3.

• More Interrupts. The I/O APIC in the ICH supports a total of 24 interrupts.

• Multiple Interrupt Controllers. The I/O APIC interrupt transmission protocol has an

arbitration phase, which allows for multiple I/O APICs in the system with their own interrupt

vectors. The ICH I/O APIC must arbitrate for the APIC bus before transmitting its interrupt

message.

5.8.2

Interrupt Mapping

The I/O APIC within the ICH supports 24 APIC interrupts. Each interrupt has its own unique

vector assigned by software. The interrupt vectors are mapped as shown in Table 5-16.

Table 5-16. APIC interrupt Mapping

I/O APIC Input

Interrupt

Comment

Interrupt 0

Interrupt 1

8259 INTR

ISA Interrupt 1

Interrupt 2

ISA Interrupt 0

Counter 0 output of 8254

Interrupts 3 - 12

Interrupt 13

ISA IRQ3-7,IRQ8#,IRQ9-12

ISA interrupt 13

IRQ8# is inverted internally

Internally generated off of FERR#

Comes from IRQ[14:15] input signals or from

SERIRQ

Interrupt 14 - 15

ISA Interrupt 14-15

Interrupt 16

Interrupt 17

Interrupt 18

Interrupt 19

Interrupt 20

Interrupt 21

Interrupt 22

Interrupt 23

PCI Interrupt A

PCI Interrupt B

PCI Interrupt C

PCI Interrupt D

IRQ20

Comes from PIRQA input signal or SERIRQ

Comes from PIRQB input signal or SERIRQ

Comes from PIRQC input signal or SERIRQ

Comes from PIRQD input signal or SERIRQ

Can come from internal modules

IRQ21

Can come from internal modules

IRQ22

Can come from internal modules

IRQ23

Can come from internal modules

5-30

82801AA and 82801AB Datasheet

Functional Description

5.8.3

APIC Bus Functional Description

5.8.3.1

Physical Characteristics of APIC

The APIC bus is a 3-wire synchronous bus connecting all I/O and local APICs. Two of these wires

are used for data transmission, and one wire is a clock. For bus arbitration, the APIC uses only one

of the data wires. The bus is logically a wire-OR and electrically an open-drain connection

providing for both bus use arbitration and arbitration for lowest priority. The APIC bus speed can

run from 16.67 MHz to 33 MHz.

5.8.3.2

APIC Bus Arbitration

The I/O APIC uses one wire arbitration to win bus ownership. A rotating priority scheme is used

for APIC bus arbitration. The winner of the arbitration becomes the lowest priority agent and

assumes an arbitration ID of 0. All other agents, except the agent whose arbitration ID is 15,

increment their Arbitration IDs by one. The agent whose ID was 15 takes the winner's arbitration

ID and increments it by one. Arbitration IDs are changed only for messages that are transmitted

successfully (except for the Low Priority messages). A message is transmitted successfully if no

CS error or acceptance error was reported for that message.

An APIC agent can use two different priority schemes: Normal or EOI. EOI has the highest

priority. EOI priority is used to send EOI messages for level interrupts from a local APIC to an I/O

APIC. When an agent requests the bus with EOI priority, all other agents requesting the bus with

normal priorities will back off.

When the ICH detects a bus idle condition on the APIC Bus, and it has an interrupt to send over the

APIC bus, it drives a start cycle to begin arbitration, by driving bit 0 to a ‘0’ on an APICCLK rising

edge. It then samples bit 1. If Bit 1 was a 0, then a local APIC started arbitration for an EOI

message on the same clock edge that the ICH started arbitration. The ICH has, thus, lost arbitration

and stops driving the APIC bus.

If the ICH did not see an EOI message start, it starts transferring its arbitration ID, located in bits

[27:24] of its Arbitration ID register (ARBID). Starting in Cycle 2, through Cycle 5, it tri-states bit

0, and drives bit 1 to a ‘0’ if ARBID[27] is a ‘1’. If ARBID[27] is a ‘0’, it also tri-states bit 1. At the

end of each cycle, the ICH samples the state of Bit 1 on the APIC bus. If the ICH did not drive Bit

1 (ARBID[27] = ‘0’), and it samples a ‘0’, then another APIC agent started arbitration for the APIC

bus at the same time as the ICH, and it has higher priority. The ICH stops driving the APIC bus.

Table 5-17 describes the arbitration cycles.

Table 5-17. Arbitration Cycles

Cycle

Bit 1

EOI

Bit 0

Comment

Bit 1 = 1: Normal, Bit 1 = 0: EOI

1

0

1

2

3

4

5

NOT (ARBID[27])

NOT (ARBID[26])

NOT (ARBID[25])

NOT (ARBID[24])

Arbitration ID. If ICH samples a different value than it sent, it

lost arbitration.

82801AA and 82801AB Datasheet

5-31

Functional Description

5.8.3.3

Bus Message Formats

After bus arbitration, the winner is granted exclusive use of the bus and drives its message. APIC

messages come in four formats, determined by the delivery mode bits. These four messages are of

different length, and are known by all APICs on the bus through the transmission of the Delivery

Mode bits.

Table 5-18. APIC Message Formats

# of

Cycles

Delivery Mode

Bits

Message

Comments

End of Interrupt transmission from Local APIC to I/O APIC

on Level interrupts. EOI is known by the EOI bit at the start

of arbitration.

EOI

14

xxx

001, 010, 100,

101, 111

I/O APIC delivery on Fixed, NMI, SMI, Reset, ExtINT, and

Lowest Priority with focus processor messages.

Short

21

Transmission of Lowest Priority interrupts when the status

field indicates that the processor does not have focus.

Lowest Priority

Remote Read

33

39

001

011

Message from one Local APIC to another to read registers.

EOI Message For Level Triggered Interrupts

EOI messages are used by local APICs to send an EOI cycle occurring for a level triggered

interrupt to an I/O APIC. This message is needed so that the I/O APIC can differentiate between a

new interrupt on the interrupt line versus the same interrupt on the interrupt line. The target of the

EOI is given by the local APIC through the transmission of the priority vector (V7 through V0) of

the interrupt. Upon receiving this message, the I/O APIC resets the Remote IRR bit for that

interrupt. If the interrupt signal is still active after the IRR bit is reset, the I/O APIC treats it as a

new interrupt.

Table 5-19. EOI Message

Cycle

Bit 1

Bit 0

Comments

1

0

1

EOI message

Arbitration ID

2 - 5

ARBID

Interrupt vector bits V7 - V0 from redirection table

register

6

NOT(V7)

NOT(V6)

7

NOT(V5)

NOT(V3)

NOT(V1)

NOT(C1)

1

NOT(V4)

NOT(V2)

NOT(V0)

NOT(C0)

1

8

9

10

11

12

13

14

Check Sum from Cycles 6 - 9

Postamble

NOT(A)

NOT(A1)

1

NOT(A)

NOT(A1)

1

Status Cycle 0

Status Cycle 1

Idle

5-32

82801AA and 82801AB Datasheet

Functional Description

Short Message

Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT and Lowest Priority

with Focus processor interrupts. The delivery mode bits (M2-M0) specify the message. All short

messages take 21 cycles including the idle cycle.

Table 5-20. Short Message

Cycle

Bit 1

Bit 0

Comments

1

0

1

Normal Arbitration

Arbitration ID

2 - 5

6

ARBID

DM¹= Destination Mode from bit 11 of the redirection table

register

NOT(DM)

NOT(M2)

NOT(M0)

M2-M0 = Delivery Mode from bits 10:8 of the redirection table

register

7

NOT(M1)

8

NOT(L)

NOT(V7)

NOT(V5)

NOT(V3)

NOT(V1)

NOT(D7)

NOT(D5)

NOT(D3)

NOT(D1)

NOT(C1)

1

NOT(TM)

NOT(V6)

NOT(V4)

NOT(V2)

NOT(V0)

NOT(D6)

NOT(D4)

NOT(D2)

NOT(D0)

NOT(C0)

1

L = Level, TM = Trigger Mode

9

10

11

12

13

14

15

16

17

18

19

20

21

Interrupt vector bits V7 - V0 from redirection table register

Destination field from bits 63:56 of redirection table register¹

Checksum for Cycles 6 - 16²

Postamble³

NOT(A)

NOT(A1)

1

NOT(A)

NOT(A1)

1

Status Cycle 0. See Table 5-21.

Status Cycle 1. See Table 5-21.

Idle

NOTES:

1. If DM is 0 (physical mode), then cycles 15 and 16 are the APIC ID and cycles 13 and 14 are sent as ‘1’. If DM

is 1 (logical mode), then cycles 13 through 16 are the 8-bit Destination field. The interpretation of the logical

mode 8-bit Destination field is performed by the local units using the Destination Format Register.

Shorthand’s of "all-incl-self" and "all-excl-self" both use Physical Destination mode and a destination field

containing APIC ID value of all ones. The sending APIC knows whether it should (incl) or should not (excl)

respond to its own message.

2. The checksum field is the cumulative add (mod 4) of all data bits (DM, M0-3, L, TM, V0-7,D0-7). The APIC

driving the message provides this checksum. This, in essence, is the lower two bits of an adder at the end of

the message.

3. This cycle allows all APICs to perform various internal computations based on the information contained in

the received message. One of the computations takes the checksum of the data received in cycles 6 through

16 and compares it with the value in cycle 18. If any APIC computes a different checksum than the one

passed in cycle 17, then that APIC signals an error on the APIC bus (“00”) in cycle 19. If this happens, all

APICs assume the message was never sent and the sender must try sending the message again. This

includes re-arbitrating for the APIC bus. In lowest priority delivery when the interrupt has a focus processor,

the focus processor signals this by driving a “01” during cycle 19. This instructs all the other APICs that the

interrupt has been accepted, the arbitration is preempted, and short message format is used. Cycle 19 and

20 indicates the status of the message (i.e., accepted, check sum error, retry or error). Table 5-21 shows the

status signal combinations and their meanings for all delivery modes.

82801AA and 82801AB Datasheet

5-33

Functional Description

Table 5-21. APIC Bus Status Cycle Definition

Delivery Mode

A

Comments

A1

Comments

11 Checksum OK

1x Error

01 Accepted

00 Retry

Fixed, EOI

10 Error

xx

01 Error

xx

00 Checksum Error

11 Checksum OK

xx

1x Error

01 Accepted

00 Error

NMI, SMM, Reset,

ExtINT

10 Error

xx

01 Error

00 Checksum Error

Checksum OK: No Focus

Processor

11

1x Error

01 End and Retry

00 Go for Low Priority Arbitration

xx

Lowest Priority

10 Error

Checksum OK: Focus

01

xx

Processor

00 Checksum Error

11 Checksum OK

10 Error

xx

Remote Read

01 Error

00 Checksum Error

5-34

82801AA and 82801AB Datasheet

Functional Description

Lowest Priority without Focus Processor (FP) Message

This message format is used to deliver an interrupt in the lowest priority mode in which it does not

have a Focus Process. Cycles 1 through 21 for this message is same as for the short message

discussed above. Status cycle 19 identifies if there is a Focus processor (10) and a status value of

11 in cycle 20 indicates the need for lowest priority arbitration.

Table 5-22. Lowest Priority Message (Without Focus Processor)

Cycle

Bit 1

Bit 0

Comments

1

2 - 5

6

1

0

1

Normal Arbitration

Arbitration ID

ARBID

NOT(DM)

NOT(M2)

DM = Destination Mode from bit 11 of the redirection table register

M2-M0 = Delivery Mode from bits 10:8 of the redirection table

register

7

NOT(M1)

NOT(M0)

8

NOT(L)

NOT(V7)

NOT(V5)

NOT(V3)

NOT(V1)

NOT(D7)

NOT(D5)

NOT(D3)

NOT(D1)

NOT(C1)

1

NOT(TM)

L = Level, TM = Trigger Mode

9

NOT(V6)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

NOT(V4)

Interrupt vector bits V7 - V0 from redirection table register

NOT(V2)

NOT(V0)

NOT(D6)

NOT(D4)

Destination field from bits 63:56 of redirection table register

NOT(D2)

NOT(D0)

NOT(C0)

Checksum for Cycles 6 - 16

Postamble

1

NOT(A)

NOT(A1)

P7

NOT(A)

Status Cycle 0.

NOT(A1)

Status Cycle 1.

1

S

1

P6

P5

P4

Inverted Processor Priority P7 - P0

P3

P2

P1

P0

ArbID3

ArbID2

ArbID1

ArbID0

S

Status

Idle

1

NOTES:

1. Cycle 21 through 28 are used to arbitrate for the lowest priority processor. The processor that takes part in

the arbitration drives the processor priority on the bus. Only the local APICs that have "free interrupt slots"

participates in the lowest priority arbitration.

2. Cycles 29 through 32 are used to break tie in case two more processors have lowest priority. The bus

arbitration ID's are used to break the tie.

82801AA and 82801AB Datasheet

5-35

Functional Description

Remote Read Message

Remote read message is used when a local APIC wishes to read the register in another local APIC.

The message format is same as short message for the first 21 cycles.

Table 5-23. Remote Read Message

Cycle

Bit 1

Bit 0

Comments

1

0

1

Normal Arbitration

Arbitration ID

2 - 5

6

ARBID

NOT(DM)

NOT(M2)

DM = Destination Mode from bit 11 of the redirection table register

M2-M0 = Delivery Mode from bits 10:8 of the redirection table

register

7

NOT(M1)

NOT(M0)

8

NOT(L)

NOT(V7)

NOT(V5)

NOT(V3)

NOT(V1)

NOT(D7)

NOT(D5)

NOT(D3)

NOT(D1)

NOT(C1)

1

NOT(TM)

NOT(V6)

NOT(V4)

NOT(V2)

NOT(V0)

NOT(D6)

NOT(D4)

NOT(D2)

NOT(D0)

NOT(C0)

1

L = Level, TM = Trigger Mode

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

Interrupt vector bits V7 - V0 from redirection table register

Destination field from bits 63:56 of redirection table register

Checksum for Cycles 6 - 16

Postamble

NOT(A)

NOT(A1)

d31

NOT(A)

NOT(A1)

d30

Status Cycle 0.

Status Cycle 1.

d29

d28

d27

d26

d25

d24

d23

d22

d21

d20

d19

d18

d17

d16

Remote register data 31-0

d15

d14

d13

d12

d11

d10

d09

d08

d07

d06

d05

d04

d03

d02

d01

d00

S

Data Status: 00 = valid, 11 = invalid

Check Sum for data d31-d00

Idle

C

1

NOTE: Cycle 21 through 36 contain the remote register data. The status information in cycle 37 specifies if the

data is good or not. Remote read cycle is always successful (although the data may be valid or invalid)

in that it is never retried. The reason for this is that Remote Read is a debug feature, and a "hung"

remote APIC that is unable to respond should not cause the debugger to hang.

5-36

82801AA and 82801AB Datasheet

Functional Description

5.9

Serial Interrupt (D31:F0)

The ICH supports a serial IRQ scheme. This allows a single signal to be used to report interrupt

requests. The signal used to transmit this information is shared between the host, the ICH, and all

peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock,

and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a

device has driven SERIRQ low, it first drives it high synchronous to PCI clock and releases it the

following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the

following fashion:

• S - Sample Phase. Signal driven low

• R - Recovery Phase. Signal driven high

• T - Turn-around Phase. Signal released

The ICH supports a message for 21 serial interrupts. These represent the 15 ISA interrupts

(IRQ[0,1, 2:15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ

protocol does not support the additional APIC interrupts (20:23).

5.9.1

Start Frame

The serial IRQ protocol has two modes of operation which affect the start frame. These two modes

are: Continuous, where the ICH is solely responsible for generating the start frame; and Quiet,

where a serial IRQ peripheral is responsible for beginning the start frame.

The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In

this mode, the ICH asserts the start frame. This start frame is 4, 6, or 8 PCI clocks wide based upon

the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This

is a polling mode.

When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line

remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the

SERIRQ signal low. The ICH senses the line low and continues to drive it low for the remainder of

the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this

mode, the ICH drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This

mode of operation allows for a quiet, and therefore lower power, operation.

5.9.2

Data Frames

Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames

based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1

clock each:

• Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the

corresponding interrupt signal is low. If the corresponding interrupt is high, then the SERIRQ

devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors.

• Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample

Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase.

• Turn-around Phase. The device tri-states the SERIRQ line

82801AA and 82801AB Datasheet

5-37

Functional Description

5.9.3

Stop Frame

After all data frames, a Stop Frame is driven by the ICH. The SERIRQ signal is driven low by the

ICH for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration

register. The number of clocks determines the next mode:

Table 5-24. Stop Frame Explanation

Stop Frame Width

Next Mode

2 PCI clocks

3 PCI clocks

Quiet Mode. Any SERIRQ device may initiate a Start Frame

Continuous Mode. Only the host (ICH) may initiate a Start Frame

5.9.4

Specific Interrupts not Supported via SERIRQ

There are three interrupts seen through the serial stream which are not supported by the ICH. These

interrupts are generated internally, and are not sharable with other devices within the system. These

interrupts are:

• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.

• IRQ8#. RTC interrupt can only be generated internally.

• IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#.

The ICH ignores the state of these interrupts in the serial stream, and does not adjust their level

based on the level seen in the serial stream. In addition, the interrupts IRQ14 and IRQ15 from the

serial stream are treated differently than their ISA counterparts. These two frames are not passed to

the Bus Master IDE logic. The Bus Master IDE logic expects IDE to be behind the ICH.

5-38

82801AA and 82801AB Datasheet

Functional Description

5.9.5

Data Frame Format

Table 5-25 shows the format of the data frames. For the PCI interrupts (A-D), the output from the

ICH is ANDed with the PCI input signal. This way, the interrupt can be signaled via both the PCI

interrupt input signal and via the SERIRQ signal (they are shared).

Table 5-25. Data Frame Format

Data

Frame #

Clocks Past

Start Frame

Interrupt

Comment

1

2

IRQ0

IRQ1

2

Ignored. IRQ0 can only be generated via the internal 8524

5

3

SMI#

8

Causes SMI# if low. Sets SERIRQ_SMI_STS status bit.

4

IRQ3

11

14

17

20

23

26

29

32

35

38

41

44

47

50

53

56

59

62

5

IRQ4

6

IRQ5

7

IRQ6

8

IRQ7

9

IRQ8

Ignored. IRQ8# can only be generated internally or on ISA.

10

11

12

13

14

15

16

17

18

19

20

21

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IOCHCK#

PCI INTA#

PCI INTB#

PCI INTC#

PCI INTD#

Ignored. IRQ13 can only be generated from FERR#

Do not include in BM IDE interrupt logic

Same as ISA IOCHCK# going active.

Drive PIRQA#

Drive PIRQB#

Drive PIRQC#

Drive PIRQD#

82801AA and 82801AB Datasheet

5-39

Functional Description

5.10

Real Time Clock (D31:F0)

The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device

with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for

general purpose usage. Three interrupt features are available: time of day alarm with once a second

to once a month range, periodic rates of 122us to 500ms, and end of update cycle notification.

Seconds, minutes, hours, days, day of week, month, and year are counted. Daylight savings

compensation is optional. The hour is represented in twelve or twenty-four hour format, and data

can be represented in BCD or binary format. The design is meant to be functionally compatible

with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source,

which is divided to achieve an update every second. The lower 14 bytes on the lower RAM block

has very specific functions. The first ten are for time and date information. The next four (0Ah to

0Dh) are registers, which configure and report RTC functions.

The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24

hour) as selected in register B. It is up to the programmer to make sure that data stored in these

locations is within the reasonable values ranges and represents a possible date and time. The

exception to these ranges is to store a value of C0 - FF in the Alarm bytes to indicate a don’t care

situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm

Interrupt if enabled. The SET bit of register B should be one while programming these locations to

avoid clashes with an update cycle. Access to time and date information is done through the RAM

locations. If a RAM read from the ten time and date bytes is attempted during an update cycle, the

value read does not necessarily represent the true contents of those locations. Any RAM writes

under the same conditions are ignored.

Note: The ICH supports the ability to generate an SMI# based on Year 2000 rollover. See Section 5.10.4

for more information on the century rollover.

The ICH does not implement month/year alarms.

5.10.1

Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide

chain is properly configured. During this procedure, the stored time and date are incremented,

overflow checked, a matching alarm condition checked, and the time and date rewritten to the

RAM locations. To maintain compatibility with the Motorola MS146818B, the update cycle starts

at least 244 us after the UIP bit of register A is asserted, and the entire cycle does not take more

than 1984 us to complete. The time and date RAM locations (0-9) will be disconnected from the

external bus during this time.

To avoid update and data corruption conditions, external RAM access to these locations can safely

occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read

and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at

least 244 us before the update cycle begins.

Warning: The overflow conditions for leap years and daylight savings adjustments are based on more than

one date or time item. To ensure proper operation when adjusting the time, the new time and data

values should be set at least two seconds before one of these conditions (leap year, daylight savings

time adjustments) occurs.

5-40

82801AA and 82801AB Datasheet

Functional Description

5.10.2

5.10.3

Interrupts

The real-time clock interrupt is internally routed within the ICH both to the I/O APIC and the 8259.

It is mapped to interrupt vector 8. This interrupt does not leave the ICH, nor is it shared with any

other interrupt. IRQ8# from the SERIRQ stream is ignored.

Lockable RAM Ranges

The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the

configuration space. If the locking bits are set, the corresponding range in the RAM is not readable

or writable. A write cycle to those locations have no effect. A read cycle to those locations does not

return the location’s actual value (may be all 0’s or all 1’s).

Once a range is locked, the range can be unlocked only by a hard reset, which invokes the BIOS

and allows it to relock the RAM range.

5.10.4

5.10.5

Century Rollover

The ICH detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form

99 to 00. Upon detecting the rollover, the ICH sets the NEWCENTURY_STS bit

(TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler

can update registers in the RTC RAM that are associated with century value. If the system is in a

sleep state (S1-S5) when the century rollover occurs, the ICH also sets the NEWCENTURY_STS

bit, but no SMI# is generated. When the system resumes from the sleep state, BIOS should check

the NEWCENTURY_STS bit and update the century value in the RTC RAM.

Clearing Battery-Backed RTC RAM

Clearing CMOS RAM in an ICH-based platform can be done by using a jumper on RTCRST# or

GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a

jumper to pull VccRTC low.

82801AA and 82801AB Datasheet

5-41

Functional Description

Using RTCRST# to clear CMOS

A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of

those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to

ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) is set and those configuration bits in the RTC

power well are set to their default state. BIOS can monitor the state of this bit, and manually clear

the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be

pulled up through a weak pull-up resistor. The following table shows which bits are set to their

default state when RTCRST# is asserted

.

Table 5-26. Configuration Bits Reset By RTCRST# Assertion

Bit Name

Default State

Register

General Status

Location

Bit(s)

CPU_BIST_EN

(ICH 82801AA only)

0

D31:F0:D7-D4

12

FREQ_STRAP[3:0]

0Fh

General Status

RTC Register A

RTC Register B

D31:F0:D7-D4

I/O space

11:8

ALL

6,4,3

7,6,5,4

7, 5:0

2

undefined

0, 0, 0

PIE, UIE, SQWE

IRQF, PF, AF, UF

VRT, Date Alarm

RTC_PWR_STS

PWR_FLR

I/O space

0, 0, undef, 0 RTC Register C

1, undefined RTC Register D

I/O space

0

General PM Configuration 3

D31:F0:A4

D31:F0 PMBase+0h

General PM Configuration 3

Power Management 1 Status

1

AFTERG3_EN

0

PRBTNOR_STS

PME_EN, RI_STS

NEW_CENTURY_STS

INTRD_DET

0

11

0, 0

0

General Purpose Event 0 Enable D31:F0 PMBase+2Ah

11,8

7

TCO1 Status

TCO2 Status

D31:F0 TCOBase+04h

D31:F0 TCOBase+06h

0

Using a GPI to Clear CMOS

A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this

GPI on system boot-up, and manually clear the CMOS array.

Using the SAFEMODE Strap to Clear CMOS

A jumper on AC_SDOUT (SAFEMODE strap) can also be used to clear CMOS values. BIOS

would detect the setting of the SAFE_MODE status bit (D31:F0: Offset D4h bit 2) on system boot-

up, and manually clear the CMOS array.

Note: Both the GPI & SAFEMODE strap techniques to clear CMOS require multiple steps to implement.

The system is booted with the jumper in new position, then powered back down. The jumper is

replaced back to the normal position, then the system is rebooted again. The RTCRST# jumper

technique allows the jumper to be moved and then replaced, all while the system is powered off.

Then, once booted, the RTC_PWR_STS can be detected in the set state.

Note: Clearing CMOS, using a jumper on VCCRTC, must NOT be implemented.

5-42

82801AA and 82801AB Datasheet

Functional Description

5.11

Processor Interface (D31:F0)

The ICH has the following outputs to the processor:

• A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP#

The ICH outputs to the processor use open drain buffers, which are pulled up at the system level to

the processor CMOS I/O buffer voltage. The ICH contains one input from the processor, FERR#,

which has special buffer requirements for the different voltage levels. The Vil threshold needs to be

compatible with processors that do not drive the signal above 1.8V.

The ICH also handles the speed setting for the processor by holding specific signals at certain

states just prior to CPURST going inactive. This avoids the glue often required with other PCIsets.

The ICH does not attempt to support the processor’s FRC mode, as this changes the behavior of

many signals.

5.11.1

Processor Interface Signals

This section describes each of the signals that interface between the ICH and the processor bus.

Note that the behavior of some signals may vary during processor reset, as the signals are used for

frequency strapping.

A20M#

The A20M# signal is active (low) when both of the following conditions are true:

• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a ‘0’

• The A20GATE input signal is a ‘0’

The A20GATE input signal is expected to be generated by the external microcontroller (KBC).

INIT#

The INIT# signal is active (driven low) based on any one of several events described in Table 5-27.

When any of these events occur, INIT# is driven low for 16 PCI clocks, then released (and pulled

high by external pull-up resistor).

Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if INIT# is

supposed to go active while STPCLK# is asserted, it actually goes active after STPCLK# goes

inactive.

82801AA and 82801AB Datasheet

5-43

Functional Description

Table 5-27. INIT# Going Active

Cause of INIT# Going Active

Shutdown special cycle from processor.

Comment

PORT92 write, where INIT_NOW (bit 0) transitions from a 0 to a 1.

PORTCF9 write, where RST_CPU (bit 2) was a 0 and SYS_RST(bit 1)

transitions from 0 to 1.

0 to 1 transition on RCIN# must

occur before the ICH arms

INIT# to be generated again.

RCIN# input signal goes low. RCIN# is expected to be driven by the

external microcontroller (KBC).

To enter BIST, the software

sets CPU_BIST_EN bit and

then does a full processor reset

using the CF9 register.

Processor BIST (ICH: 82801AA only)

FERR#/IGNNE# (Coprocessor Error)

The ICH supports the coprocessor error function with the FERR#/IGNNE# pins. The function is

enabled via the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, bit 13). FERR# is tied

directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the

processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register,

the ICH negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until

FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active.

Figure 5-10. Coprocessor Error Timing Diagram

FERR#

Internal IRQ13

I/O Write to F0h

IGNNE#

If COPROC_ERR_EN is not set, then the assertion of FERR# will have not generate an internal

IRQ13, nor will the write to F0h generate IGNNE#.

NMI

Non-Maskable Interrupts (NMIs) can be generated by several sources.

Table 5-28. NMI Sources

Cause of NMI

Comment

SERR# goes active (either internally, externally

via SERR# signal, or via message from the host

controller)

Can instead be routed to generate an SCI, through the

NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).

IOCHK# goes active via SERIRQ# stream

(ISA system Error)

Can instead be routed to generate an SCI, through the

NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).

5-44

82801AA and 82801AB Datasheet

Functional Description

STPCLK# and CPUSLP# Signals

The ICH power management logic controls these active-low open-drain signals. Refer to

Section 5.12 for more information on the functionality of these signals.

5.11.2

Dual Processor Issues (ICH: 82801AA only)

5.11.2.1

Signal Differences (ICH: 82801AA only)

In dual processor designs, some of the processor signals are unused or used differently than for

uniprocessor designs.

Table 5-29. DP Signal Differences

Signal

Difference

A20M# / A20GATE

Generally not used, but still supported by ICH.

Used for S1 State as well as preparation for entry to S3-S5

STPCLK#

Also allows for THERM# based throttling (not via ACPI control methods).

Should be connected to both processors.

FERR# / IGNNE#

Generally not used, but still supported by ICH.

5.11.2.2

Power Management (ICH: 82801AA only)

Attempting clock control with more than one processor is not feasible, because the MCH does not

provide any indication as to which processor is executing a particular Stop-Grant cycle. Without

this information, there is no way for the 82801AA ICH to know when it is safe to deassert

STPCLK#.

Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected

to both processors. However, for ACPI implementations, the ICH will not support the C2 state for

both processors, since there are not two processor control blocks. The BIOS must indicate that the

ICH only supports the C1 state for dual processor designs. However, the THRM# signal can be

used for overheat conditions to activate thermal throttling.

When entering S1, the ICH asserts STPCLK# to both processors. The ICH will then wait 8 PCI

clocks after receipt of the first Stop-Grant Acknowledge cycle before asserting CPUSLP# (if the

SLP_EN bit is set to 1).

Both processors must immediately respond to the STPCLK# assertion with stop grant acknowledge

cycles before the ICH asserts CPUSLP# in order to meet the processor setup time for CPUSLP#.

Meeting the processor setup time for CPUSLP# is not an issue if both processors are idle when the

system is entering S1. If you cannot guarantee that both processors will be idle, do not enable the

SLP_EN bit. Note that setting SLP_EN to 1 is not required to support S1 in a dual processor

configuration.

S2 is not supported for single or dual processor desktop designs.

In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state, and thus

STPCLK# and SLP# are also used.

During the S3, S4, and S5 states, both processors will lose power. Upon exit from those states, the

processors will have their power restored.

82801AA and 82801AB Datasheet

5-45

Functional Description

5.11.3

Speed Strapping for Processor

The ICH directly sets the speed straps for the processor, saving the external logic that has been

needed with prior PCIsets. Refer to processor specification for speed strapping definition.

The ICH performs the following to set the speed straps for the processor:

1. While PCIRST# is active, the ICH drives A20M#, IGNNE#, NMI, and INTR high.

2. As soon as PWROK goes active, the ICH reads the FREQ_STRAP field contents.

3. The next step depends on the power state being exited as described in Table 5-30.

Table 5-30. Frequency Strap Behavior Based on Exit State

State

Exiting

ICH

S1

There is no processor reset; Thus, there is no frequency strap logic is used.

Based on PWROK going active, the ICH deasserts PCIRST#, and based on the value of the

FREQ_STRAP field (D31:F0,Offset D4), the ICH drives the intended core frequency values on

A20M#, IGNNE#, NMI, and INTR. The ICH holds these signals for 120ns after CPURST# is

deasserted by the host controller.

S3, S4, S5,

or G3

Table 5-31. Frequency Strap Bit Mapping

FREQ_STRAP bits [3:0]

Sets High/Low level for corresponding signal

3

2

1

0

NMI

INTR

IGNNE#

A20M#

NOTE: The FREQ_STRAP register is in the RTC well. The value in the register can be forced to 1111h via a

pinstrap (AC_SDOUT signal), or the ICH can automatically force the speed strapping to 1111h if the

processor fails to boot.

Figure 5-11. ICH Signal Strapping

CPURST#

INIT#

Processor

Host Controller

A20M#, IGNE#, INTR, NMI

ICH

PCIRST#

Frequency

Strap

Regster

4x 2 to 1

Mux

P W R O K

5-46

82801AA and 82801AB Datasheet

Functional Description

5.12

Power Management (D31:F0)

5.12.1

ICH and System Power States

Table 5-32 shows the power states defined for ICH-based platforms. The state names generally match the

corresponding ACPI states.

Table 5-32. General Power States for Systems using ICH

State/

Substates

Legacy Name / Description

Full On: Processor operating. Individual devices may be shut down to save power. The

different processor operating levels are defined by Cx states, as shown in Table 5-33. Within

the C0 state, the ICH can throttle the STPCLK# signal to reduce power consumption. The

throttling can be initiated by software or by the THRM# input signal.

G0/S0/C0

Auto-Halt: Processor has executed a AutoHalt instruction and is not executing code. The

processor snoops the bus and maintains cache coherency.

G0/S0/C1

G0/S0/C2

Stop-Gran: The STPCLK# signal goes active to the processor. The processor performs a

Stop-Grant cycle, halts its instruction stream, and remain in that state until the STPCLK# signal

goes inactive. In the Stop-Grant state, the processor snoops the bus and maintains cache

coherency.

Stop-Grant: Similar to G0/S0/C2 state. ICH also has the option to assert the processor SLP#

signal to further reduce processor power consumption.

G1/S1

G1/S3

Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is

shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop

except RTC clock.

Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is

then shut off to the system except for the logic required to resume. Externally appears same as

S5, but may have different wake events.

G1/S4

G2/S5

Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic

required to restart. A full boot is required when waking.

Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the

RTC. No “Wake” events are possible, because the system does not have any power. This state

occurs if the user removes the batteries, turns off a mechanical switch, or if the system power

supply is at a level that is insufficient to power the “waking” logic. When system power returns,

transition depends on the state just prior to the entry to G3 and the AFTERG3 bit in the

GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-41 for more details.

G3

Table 5-33 shows the transitions rules among the various states. Note that transitions among the

various states may appear to temporarily transition through intermediate states. For example, in

going from S0 to S1, it may appear to pass through the G0/S0/C2 states. These intermediate

transitions and states are not listed in the table.

82801AA and 82801AB Datasheet

5-47

Functional Description

Table 5-33. State Transition Rules for ICH

Present

State

Transition Trigger

Next State

•

Processor halt instruction

Level 2 Read

•

G0/S0/C1

G0/S0/C2

G0/S0/C0

SLP_EN bit set

G1/Sx or G2/S5state

Power Button Override

Mechanical Off/Power Failure

G2/S5

G3

•

Any Enabled Break Event

STPCLK# goes active

Power Button Override

Power Failure

•

G0/S0/C0

G0/S0/C2

G2/S5

G0/S0/C1

G0/S0/C2

G3

•

Any Enabled Break Event

•

G0/S0/C0

G0/S0/C1

STPCLK# goes inactive and previously

in C1

•

Power Button Override

Power Failure

•

G2/S5

G3

•

Any Enabled Wake Event

Power Button Override

Power Failure

•

G0/S0/C0

G2/S5

G3

G1/S1,

G1/S3, or

G1/S4

•

Any Enabled Wake Event

Power Failure

•

G0/S0/C0

G3

G2/S5

G3

•

Optional to go to S0/C0 (reboot) or G2/S5

(stay off until power button pressed). (See

Note 1)

•

Power Returns

NOTE: Some wake events can be preserved through power failure.

5.12.2

System Power Planes

The system has several independent power planes, as described in Table 5-34. Note that when a

particular power plane is shut off, it should go to a 0V level.

s

Table 5-34. System Power Plane

Controlled

By

Plane

Description

When SLP_S3# goes active, power can be shut off to any circuit not

required to wake the system from the S3 state. Since the S3 state requires

that the memory context be preserved, power must be retained to the main

memory.

SLP_S3#

signal

MAIN

Devices on the PCI bus, LPC interface downstream Hub Interface (and AGP

for the ICH 82801AA) is, typically, shut off when the Main power plane is

shut; there may be small subsections powered.

When the SLP_S5# goes active, power can be shut off to any circuit not

required to wake the system from the S4 or S5 state. Since the memory

context does not need to be preserved in the S5 state, the power to the

memory can also be shut down.

SLP_S5#

signal

MEMORY

DEVICE[n]

Individual subsystems may have their own power plane. For example, GPIO

signals may be used to control the power to disk drives, audio amplifiers, or

the display screen.

GPIO

5-48

82801AA and 82801AB Datasheet

Functional Description

5.12.3

SMI#/SCI Generation

Upon any SMI# event taking place, the ICH asserts SMI# to the processor, which causes it to enter

SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes

inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI# is driven active again.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In

non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts

(IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that

interrupt.

In systems using the APIC, the SCI can still be routed to IRQ 9, 10, or 11, or it can be instead

routed to one of the APIC interrupts 20:23. In either case, the interrupt generated internally is

active low level. The interrupt remains low until all SCI sources are removed.

Table 5-35 shows which events can cause an SMI# and SCI. Note that some events can be

programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is

typically associated with an ACPI-based system. Each SMI# or SCI source has a corresponding

enable and status bit.

Table 5-35. Causes of SMI# and/or SCI

Event

SCI

SMI#

Comment

ACPI code in OS sets GBL_RLS bit to cause

BIOS_STS bit active, which causes SMI#.

Setting of the BIOS_STS bit

X

Setting of the LEGACY_USB_STS

bit

Bit set based on address decode or incoming USB

IRQ.

X

OS or BIOS writes to the APMC register. SMM handler

clears.

Write access to APM control register

SW SMI# Timer reaches 0

Allows SMM handler to exit temporarily. Another SMI#

occurs about 64 ms later.

Indicates that subsystems may need to be powered

back on.

Device Trap

X

TCO Event (Includes SERR#)

X

Can also cause IRQ (other than SCI).

Setting bits in GPE Status Register

with corresponding Enable bit set.

Bits in GPE Status Register include SMBus, TCO,

AC97, RI, PME, USB, THRM and GPIO[n].

This bit is set when the BIOS sets the BIOS_RLS bit.

The ACPI handler will clear the bit.

Setting of the GBL _STS bit

X

Setting any bit in the PM1_STS

register with corresponding _EN bit

set in the PM1_EN bit.

X

The SCI/SMI# should be generated, even if waking.

If GPIO programmed as input and individually

enabled, Can be Wake event.

GPIO[n]

Time-out every 2.34 seconds. If the timer is enabled,

will cause a) an SCI, if SCI_EN is set, or b) an SMI#, if

SCI_EN is not set.

Overflow of Power Management

Timer

The THRM# can cause an SMI# or SCI on either the

rising or falling edge. Causes SCI, if SCI_EN is set;

causes SMI#, if SCI_EN not set.

THRM# signal

X

PWRBTN signal

PCI PME# signal

Year 2000 Rollover

X

Can also cause Wake Event

Does not cause a Wake Event

82801AA and 82801AB Datasheet

5-49

Functional Description

5.12.4

Dynamic System Clock Control

The ICH has extensive control for dynamically starting and stopping system clocks. The clock

control is used for transitions among the various S0/Cx states, and processor throttling. Each

dynamic clock control method is described in this section. The various Sleep states may also

perform types of non-dynamic clock control.

The ICH supports the ACPI C0, C1, C2 states. The Dynamic Clock control is handled using the

STPCLK# to halt processor instruction stream. A C2 state ends due to a Break event. Based on the

break event, the ICH returns the system to C0 state. Table 5-36 lists the possible break events.

Table 5-36. Break Events

Event

Comment

IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC.

Since SCI is an interrupt, any SCI is also a break event.

Any unmasked interrupt goes active

Any internal event that causes an NMI or SMI#

Any internal event that causes INIT# to go active

Many possible sources

Could be indicated by the keyboard controller via the

RCIN input signal.

5.12.4.1

Entering/Exiting the C1 State

Causes of C1 Entry:

• From C0 State: Processor performs an Autohalt instruction.

• From C2 State: STPCLK# goes inactive and the processor had done an Autohalt instruction

prior to STPCLK# going active, and no break event has occurred. The C1 state persists until an

interrupt (regular interrupt, NMI, SMI#, or INIT#) occurs. This C1 state persists only for a few

clocks, since the cause of STPCLK# going inactive is some type of interrupt.

Causes of Exit from C1

• To C0 state: When an enabled interrupt (regular interrupt, NMI, SMI#, or INIT#) occurs.

• To C2 state: STPCLK# goes active. This causes a transition to the C2 state. This case can only

occur if the processor reads the Level 2 register (forcing a transition to C2 state) and the

processor does an autohalt instruction before it recognizes STPCLK# active.

5-50

82801AA and 82801AB Datasheet

Functional Description

5.12.4.2

Entering/Exiting the C2 State

Causes of S0/C2 Entry:

• From C0 state: Software reads the Level 2 Register

• From C1 state: STPCLK# goes active. This can only occur if the processor does an autohalt

instruction just after reading the Level 2 register (so that the autohalt instruction completes

prior to the processor recognizing the STPCLK#).

Note that in going to some of the lower power states, the system may appear to pass through the C2

state.

Causes of S0/C2 Exit:

• To C0 state: A Break event occurs. The transition back to the C0 state is qualified by the Stop-

Grant cycle being observed by the ICH. If the break event occurs prior to the Stop-Grant cycle

(associated with the prior assertion of STPCLK#), STPCLK# stays active until the Stop-Grant

cycle is observed.

• To C1 state: If STPCLK# goes inactive. The C1 state persists until an interrupt (regular

interrupt, NMI, SMI#, or INIT#) occurs.

5.12.4.3

Throttling Using STPCLK#

Throttling is used to lower power consumption or reduce heat. The ICH asserts STPCLK# to

throttle the processor clock and the processor appears to temporarily enter a C2 state. After a

programmable time, the ICH deasserts STPCLK# and the processor appears to return to the C0

state. This allows the processor to operate at reduced average power, with a corresponding decrease

in performance. Two methods are included to start throttling:

1. Software enables a timer with a programmable duty cycle. The duty cycle is set by the

THTL_DTY field and the throttling is enabled using the THTL_EN field. This is known as

Manual Throttling. The period is fixed to be in the non-audible range, due to the nature of

switching power supplies.

2. A Thermal Override condition (THRM# signal active for >2 seconds) occurs that

unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to

Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and

system. The Thermal Override condition ends when THRM# goes inactive.

Throttling due to the THRM# signal has higher priority than the software initiated throttling.

Throttling does not occur when the system is in C2 state, even if Thermal override occurs.

82801AA and 82801AB Datasheet

5-51

Functional Description

5.12.4.4

Transition Rules Among S0/Cx and Throttling States

The following priority rules and assumptions apply among the various S0/Cx and throttling states:

• Entry to any S0/Cx state is mutually exclusive with entry to any S1-S5 state. This is because

the processor can only perform one register access at a time and Sleep states have higher

priority than thermal throttling.

• When the SLP_EN bit is set (system going to a sleep state (S1-S5), the THTL_EN bit can be

internally treated as being disabled (no throttling while going to sleep state). Note that thermal

throttling (based on THRM# signal) cannot be disabled in an S0 state. However, once the

SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# is active in S1-S5 states).

• If the THTL_EN bit is set, and a Level 2 read then occurs, the system should immediately go

and stay in a C2 state until a break event occurs. A Level 2 read has higher priority than the

software initiated throttling or thermal throttling. If Thermal Override is causing throttling,

and a Level 2 read then occurs, the system stays in a C2 state until a break event occurs. A

Level 2 read has higher priority than the Thermal Override. However, if THRM# is still active

after a break event occurs, the system goes back to the C0 state and STPCLK# throttles (due to

the THRM# signal).

• After an exit from a C2 state (due to a Break event), and if the THTL_EN bit is still set, or if a

Thermal Override is still occurring, the system continues to throttle STPCLK#. Depending on

the time of break event, the first transition on STPCLK# active can be delayed by up to one

period.

• If in the C2 state after C1 (Halt), a break event returns the system to C1 state. If a break event

was an interrupt, then the INTR is sent to the processor and system transitions from C1 to C0

state.

5.12.5

Sleep States

5.12.5.1

Sleep State Overview

The ICH directly supports different sleep states (S1-S5), which are entered by setting the SLP_EN

bit, or due to a Power Button Override. The entry to the Sleep states are based on several

assumptions:

• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the

processor can only perform one register access at a time. A request to Sleep always has higher

priority than throttling.

• Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note

that thermal throttling cannot be disabled, but setting the SLP_EN bit disables thermal

throttling (since S1-S5 sleep state has higher priority).

• Upon exit from the ICH-controlled Sleep states, the WAK_STS bit is set to 1.

5.12.5.2

Initiating Sleep State

Sleep states (S1-S5) are initiated by:

• Setting the desired type in the SLP_TYP field and setting the SLP_EN bit.

• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override

event.

5-52

82801AA and 82801AB Datasheet

Functional Description

In case of the PWRBTN# override event, the transition to the S5 is less graceful, since there are no

dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC

clock.

Depending on the type of Sleep state desired, the next step the hardware takes is shown in

Table 5-37.

Table 5-37. Sleep Types

Sleep Type

Comment

ICH asserts the processor SLP# signal. This lowers the processor’s power consumption. No

snooping is possible in this state.

S1

S2

S3

Not supported.

ICH asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is

only retained to devices needed to wake from this sleeping state, as well as to the memory.

ICH asserts SLP_S3# and SLP_S5#. The SLP_S5# shuts off the power to the memory

subsystem. Only devices needed to wake from this state should be powered.

S4

S5

Same as S4. ICH asserts SLP_S3# and SLP_S5#. The SLP_S5# signal shuts off the power to

the memory subsystem. Only devices needed to wake from this state should be powered.

5.12.5.3

Exiting Sleep States

Sleep states (S1-S5) are exited based on Wake events. The Wake events force the system to a full

on state (S0), although some non-critical subsystems will still be shut off and have to be brought

back manually. For example, the hard disk may be shut off during a sleep state and have to be

enabled via a GPIO pin before it can be used.

To enable Wake Events, the possible causes of wake events (and their restrictions) are shown in

Table 5-38.

Table 5-38. Causes of Wake Events

States Can

Wake From

Cause

How Enabled

S1 - S5

(Note 2)

RTC Alarm

Set RTC_EN bit in PM1_EN Register

Always enabled as Wake event

S1 - S5

(Note 1)

Power Button

S1 - S5

(Note 2)

GPI[0:n]

USB

GPE1_EN register

S1 - S4

Set USB_EN bit in GPE0_EN Register

Set RI_EN bit in GPE0_EN Register

S1 - S5

(Note 2)

RI#

AC97

PME#

S1 - S4

Set AC97_EN bit in GPE0_EN Register

Set PME_EN bit in GPE0_EN Register.

SMB_WAK_EN in the GPE0 Register

S1 - S5

(Note 2)

SMBALERT#

S1-S4

NOTES:

1. If in the S5 state due to a powerbutton override, the only wake event is power button.

2. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP bits

via software.

82801AA and 82801AB Datasheet

5-53

Functional Description

It is important to understand that the various GPIs have different levels of functionality when used

as wake events. The GPIs that reside in the core power well can only generate wake events from an

S1 state. Also only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits

reside in ACPI I/O space. Table 5-39 summarizes the use of GPIs as wake events.

Table 5-39. GPI Wake Events

GPI

Power Well

Wake From

Notes

GPI[1:0], GPI[7:5]

GPI[13:8]

Core

S1

Resume

S1-S5

ACPI Compliant

GPIO[28:27]

The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply

design. Approximations are shown in Table 5-40. The time indicates from when the Wake event

occurs (signal transition) to when the processor is allowed to start its first cycle (CPURST# goes

inactive). There are very large additional delays for the processor to execute sufficient amounts of

BIOS to invoke the OS (such as coming out of S1-S3) or spinning up the hard drive (such as

coming out of S4 or S5).

Table 5-40. Sleep State Exit Latencies

State

Latency

<1 ms. Based on wake event to STPCLK# high + re-enumeration of PCI bus, USB, CardBus, etc.

Must also add PLL spin-up times

S1

S3

S4

S5

Power Supply ramp + 20 ms

5.12.5.4

Sx-G3-Sx, Handling Power Failures

Power failures can occur if the AC power is cut (a real power failure) or if the system is unplugged.

Depending on when the power failure occurs and how the system is designed, different transitions

could occur due to a power failure.

The AFTER_G3 bit provides the ability to program whether or not the system should boot once

power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state

(unless previously in S4). There are only three possible events that wake the system after a power

failure.

1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low

(G3 state), the PWRBTN_STS bit is reset. When the ICH exits G3 after power returns

(RSMRST# goes high), the PWRBTN# signal is already high (because Vcc-standby goes high

before RSMRST# goes high) and the PWRBTN_STS bit is 0.

2. RI#: RI# does not have an internal pull-up. This signal should be pulled-up to the suspend well

supply. After recovery from a power failure, the ICH samples RI# after RSMRST# is sampled

deasserted. At that time, RI# will be high (deasserted). The bit that enables RI# as a wake

event is preserved across power failures in the RTC Well supply.

3. RTC Alarm. The RTC_EN bit is in the RTC well and is preserved after a power loss. Like

PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.

5-54

82801AA and 82801AB Datasheet

Functional Description

The ICH monitors both PWROK and RSMRST# to detect for power failures. If PWROK goes low,

the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.

Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss.

PME_EN and PME_STS bits are cleared by RSMRST#

Table 5-41. Transitions Due To Power Failure

State at Power Failure

AFTERG3_EN bit

Transition When Power Returns

1

0

S5

S0

1

0

S5

S0

S1

S3

S4

S5

1

0

S5

S0

1

0

S4

S0

1

0

S5

S0

5.12.6

Thermal Management

The ICH has mechanisms to assist with managing thermal problems in the system.

5.12.6.1

THRM# Signal

The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal

going active, the ICH generates an SMI# or SCI (depending on SCI_EN).

If the THRM_POL bit is cleared to “0”, when the THRM# signal goes low, the THRM_STS bit is

set to “1”. This is an indicator that the thermal threshold has been exceeded. If the THRM_EN bit

is set, then when THRM_STS goes active, either an SMI# or SCI is generated (depending on the

SCI_EN bit being set).

The power management software (BIOS or ACPI) can then take measures to start reducing the

temperature. Examples include shutting off unwanted subsystems, or halting the processor.

By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated when the

THRM# signal goes back low. This allows the software (BIOS or ACPI) to turn off the cooling

methods.

5.12.6.2

THRM# Initiated Passive Cooling

If the THRM# signal remains active for some time greater than 2 seconds and the ICH is in the

S0/G0/C0 state, then the ICH enters an auto-throttling mode, in which it provides a duty cycle on

the STPCLK# signal. This reduces the overall power consumption by the system, and should cool

the system. The intended result of the cooling is that the THRM# signal should go back inactive.

For all programmed values (001 - 111), THRM# going active results in STPCLK# active for a

minimum time of 12.5% and a maximum of 87.5%. The period is 1024 PCI clocks. Thus, the

STPCLK# signal can be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The

82801AA and 82801AB Datasheet

5-55

Functional Description

actual slowdown (and cooling) of the processor depends on the instruction stream, because the

processor is allowed to finish the current instruction. Furthermore, the ICH waits for the

STOP-GRANT cycle before starting the count of the time the STPCLK# signal is active.

When THRM# goes inactive, the throttling stops. However, there is a small window where the ICH

may assert STPCLK# for one more throttling period after THERM# goes inactive.

In case that the ICH is already attempting throttling because the THTL_EN bit is set, the duty cycle

associated with the THRM# signal will have higher priority.

If the ICH is in the C2 or S1-S5 states, then no throttling will be caused by the THRM# signal

being active.

5.12.6.3

Processor Initiated Passive Cooling (Via Programmed Duty Cycle on

STPCLK#)

Using the THTL_EN and THTL_DTY bits, the ICH can force a programmed duty cycle on the

STPCLK# signal. This reduces the effective instruction rate of the processor and cut its power

consumption and heat generation.

5.12.6.4

Active Cooling

Active cooling involves fans. The GPIO signals from the ICH can be used to turn on/off a fan.

5.12.7

Event Input Signals and Their Usage

The ICH has various input signals that trigger specific events. This section describes these signals

and how they should be used.

5.12.7.1

PWRBTN#—Power Button

The ICH PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI

specification. PWRBTN# signal has a 16 ms debounce on the input. The state transition

descriptions are included in Table 5-42.

Note: The transitions start as soon as the PWRBTN# is pressed (but after the debounce logic) and does

not depend on when the Power Button is released.

Table 5-42. Transitions Due to Power Button

Present

State

Event

Transition/Action

Comment

SMI# or SCI generated

(depending on SCI_EN)

Software will typically initiate a

Sleep state.

S0/Cx

PWRBTN# goes low

Wake Event. Transitions to S0

state.

S1-S5

G3

Standard wakeup

No effect since no power.

Not latched nor detected.

PWRBTN# pressed

None

PWRBTN# held low for

at least 4 consecutive

seconds

No dependence on processor

(such as Stop-Grant cycles) or

any other subsystem.

Unconditional transition to S5

state.

S0-S4

5-56

82801AA and 82801AB Datasheet

Functional Description

Power Button Override: If PWRBTN# is observed active for at least 4 consecutive seconds, then

the state machine unconditionally transitions to the G2/S5 state, regardless of present state (S0-S4).

In this case, the transition to the G2/S5 state does not depend on any particular response from the

processor (such as a Stop-Grant cycle), nor any similar dependency from any other subsystem.

The PWRBTN# status is readable to check if the button is currently being pressed or has been

released. The status is taken after the debounce, and is readable via the PWRBTN_LVL bit.

Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The

4-second timer starts counting when the ICH is in a S0 state. If the PWRBTN# signal is asserted

and held active when the system is in a suspend state (S1-S5), the assertion causes a wake event.

Once the system has resumed to the S0 state, the 4-second timer starts.

Sleep Button: The ACPI specification defines an optional Sleep button. It differs from the power

button in that it only is a request to go from S0 to S1-S4 (not S5). Also, in an S5 state, the Power

Button can wake the system, but the Sleep Button cannot.

Although the ICH does not include a specific signal designated as a Sleep Button, one of the GPIO

signals can be used to create a “Control Method” Sleep Button. This requires some AML code to

be developed. Example code is provided in the ACPI specification.

5.12.7.2

RI#—Ring Indicate

The Ring Indicator can cause a wake event (if enabled) from the S1-S5 states. Table 5-43 shows

when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the

UART is configured to cause an interrupt based on RI# active, and the interrupt will be set up as a

break event.

Table 5-43. Transitions Due to RI# Signal

Present State

Event

RI_EN

Event

S0

RI# Active

X

0

1

Ignored

S1-S5

RI# Active

Wake Event

Filtering/Debounce on RI# is not be done in ICH. This can be in the modem or external.

5.12.7.3

PME#—PCI Power Management Event

The PME# signal comes from a PCI device to request that the system be restarted. The PME#

signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME#

signal goes from high to low. No event is caused when PME# goes from low to high.

5.12.8

Alt Access Mode

Before entering a low power state, several registers from powered down parts may need to be

saved. In the majority of cases, this is not an issue, as registers have read and write paths. However,

several of the ISA compatible registers are either read only or write only. To get data out of write-

only registers, and to restore data into read-only registers, the ICH implements an alternate access

mode.

82801AA and 82801AB Datasheet

5-57

Functional Description

5.12.8.1

Write Only Registers with Read Paths in Alternate Access Mode

The registers described in Table 5-44 have read paths in alternate access mode. The access number

field in the table indicates which register will be returned per access to that port.

Table 5-44. Write Only Registers with Read Paths in Alternate Access Mode (Sheet 1 of 2)

I/O

# of

Restore Data

Data

I/O

# of

Restore Data

Data

Addr Rds Access

DMA Chan 0 base address

low byte

Timer Counter 0 status, bits

[5:0]

00h

01h

02h

03h

04h

05h

06h

07h

08h

2

6

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

4

5

6

40h

7

1

2

3

4

5

6

7

DMA Chan 0 base address

high byte

Timer Counter 0 base count

low byte

DMA Chan 0 base count low

byte

Timer Counter 0 base count

high byte

DMA Chan 0 base count high

byte

Timer Counter 1 base count

low byte

DMA Chan 1 base address

low byte

Timer Counter 1 base count

high byte

DMA Chan 1 base address

high byte

Timer Counter 2 base count

low byte

DMA Chan 1 base count low

byte

Timer Counter 2 base count

high byte

DMA Chan 1 base count high

byte

Timer Counter 1 status, bits

[5:0]

41h

42h

70h

C4h

1

2

DMA Chan 2 base address

low byte

Timer Counter 2 status, bits

[5:0]

DMA Chan 2 base address

high byte

Bit 7 = NMI Enable,

Bits [6:0] = RTC Address

DMA Chan 2 base count low

byte

DMA Chan 5 base address

low byte

1

2

1

2

1

2

1

2

1

2

1

2

DMA Chan 2 base count high

byte

DMA Chan 5 base address

high byte

DMA Chan 3 base address

low byte

DMA Chan 5 base count low

byte

C6h

C8h

CAh

CCh

CEh

2

DMA Chan 3 base address

high byte

DMA Chan 5 base count high

byte

DMA Chan 3 base count low

byte

DMA Chan 6 base address

low byte

DMA Chan 3 base count high

byte

DMA Chan 6 base address

high byte

DMA Chan 6 base count low

byte

DMA Chan 0-3 Command²

DMA Chan 6 base count high

byte

DMA Chan 0-3 Request

DMA Chan 0 Mode:

Bits(1:0) = “00”

DMA Chan 7 base address

low byte

DMA Chan 1 Mode:

Bits(1:0) = “01”

DMA Chan 7 base address

high byte

DMA Chan 2 Mode:

Bits(1:0) = “10”

DMA Chan 7 base count low

byte

2

6

DMA Chan 3 Mode:

Bits(1:0) = “11”.

DMA Chan 7 base count high

byte

DMA Chan 4-7 Command²

20h

12

1

2

PIC ICW2 of Master controller D0h

PIC ICW3 of Master controller

1

2

DMA Chan 4-7 Request

5-58

82801AA and 82801AB Datasheet

Functional Description

Table 5-44. Write Only Registers with Read Paths in Alternate Access Mode (Sheet 2 of 2)

I/O

# of

Restore Data

Data

I/O

# of

Restore Data

Data

Addr Rds Access

DMA Chan 4 Mode:

Bits(1:0) = “00”

3

PIC ICW4 of Master controller

3

PIC OCW1 of Master

controller¹

DMA Chan 5 Mode:

Bits(1:0) = “01”

4

5

6

4

5

6

PIC OCW2 of Master

controller

DMA Chan 6 Mode:

Bits(1:0) = “10”

PIC OCW3 of Master

controller

DMA Chan 7 Mode:

Bits(1:0) = “11”.

7

8

9

PIC ICW2 of Slave controller

PIC ICW3 of Slave controller

PIC ICW4 of Slave controller

PIC OCW1 of Slave

controller¹

10

11

12

PIC OCW2 of Slave controller

PIC OCW3 of Slave controller

NOTE:

1. The OCW1 register must be read before entering Alternate Access Mode.

2. Bits 5, 3, 1, and 0 return 0.

5.12.8.2

PIC Reserved Bits

Many bits within the PIC are reserved, and must have certain values written for the PIC to operate

properly. Therefore, there is no need to return these values in alternate access mode. When reading

PIC registers from 20h and A0h, the reserved bits return the values listed in Table 5-45.

Table 5-45. PIC Reserved Bits Return Values

PIC Reserved Bits

Value Returned

ICW2(2:0)

ICW4(7:5)

ICW4(3:2)

ICW4(0)

000

00

0

OCW2(4:3)

OCW3(7)

OCW3(5)

OCW3(4:3)

00

0

Reflects bit 6

01

82801AA and 82801AB Datasheet

5-59

Functional Description

5.12.8.3

Read Only Registers with Write Paths in Alternate Access Mode

The registers described in Table 5-46 have write paths to them in alternate access mode. Software

restores these values after returning from a powered down state. These registers must be handled

special by software. When in normal mode, writing to the base address/count register also writes to

the current address/count register. Therefore, the base address/count must be written first, then the

part is put into alternate access mode and the current address/count register is written.

Table 5-46. Register Write Accesses in Alternate Access Mode

I/O Address

Register Write Value

08h

D0h

DMA Status Register for channel’s 0-3.

DMA Status Register for channel’s 4-7.

5.12.9

System Power Supplies, Planes, and Signals

Power Plane Control with SLP_S3# and SLP_S5#

The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes

active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH

Resume Well, and to any other circuits that need to generate Wake signals from the STR state.

Cutting power to the core may be done via the power supply, or by external FETs to the

motherboard. The SLP_S5# output signal can be used to cut power to the system core supply, as

well as power to the system memory, since the context of the system is saved on the disk. Cutting

power to the memory may be done via the power supply, or by external FETs to the motherboard.

PWROK Signal

The PWROK input should go active based on the core supply voltages becoming valid. PWROK

should go high at least 16 ms after the power is guaranteed valid.

Note: Traditional designs have a reset button logically AND’d with the PWROK signal from the power

supply and the processor’s voltage regulator module. If this is done with the ICH, the

PWROK_FLR bit is set. The ICH treats this internally as if the RSMRST# signal had gone active.

However, it is not treated as a full power failure. If PWROK goes inactive and then active (but

RSMRST# stays high), the ICH will reboot (regardless of the state of the AFTERG3 bit). If the

RSMRST# signal also goes low before PWROK goes high, this is a full power failure, and the

reboot policy is controlled by the AFTERG3 bit.

5-60

82801AA and 82801AB Datasheet

Functional Description

Controlling Leakage and Power Consumption During Low-Power States

To control leakage in the system, various signals tri-state or go low during some low-power states.

General principles:

• All signals going to powered down planes (either internally or externally) must be either

tri-stated or driven low.

• Signals with pull-up resistors should not be low during low-power states. This is to avoid the

power consumed in the pull-up resistor.

• Buses should be halted (and held) in a known state to avoid a floating input. (perhaps to some

other device) Floating inputs can cause extra power consumption.

Based on the above principles, the following measures are taken:

• During C2 or S3state, the processor signals that have pull-ups are tri-stated.

• During S3, all signals attached to powered down planes are tri-stated or driven low.

5.12.10 Clock Generators

The clock generator is expected to provide the frequencies shown in Table 5-47.

Table 5-47. ICH Input Clocks

Clock Name

Frequency

Event

CLK48

CLK14

48.00000 MHz This should be running in C0, C1, C2. Stops based on SLP_S3# being active.

14.31818 MHz This should be running in C0, C1, C2. Stop based on SLP_S3# being active.

66.66667 MHz This should be running in C0, C1, C2. Stops based on SLP_S3# being active

CLK66

APIC_CLK

16.67 MHz

This should be running in C0, C1, C2. Stops based on SLP_S3# being active.

The PCI clock starts/ stops based on the S3, S4, or S5 states. The PCI clock

is assumed always to be running in S0-S1 states.

PCICLK

33.33333 MHz

5.12.11 Legacy Power Management Theory of Operation

Instead of relying on ACPI software, legacy power management uses BIOS and various hardware

mechanisms. The ICH has a greatly simplified method for legacy power management compared

with previous generations.

The scheme relies on the concept of detecting when individual subsystems are idle, detecting when

the whole system is idle, and detecting accesses are attempted to idle subsystems.

However, the OS is assumed to be at least APM enabled. Without APM calls, there is no quick way

to know when the system is idle between keystrokes. The ICH does not support the burst modes

found in previous components.

APM Power Management

The ICH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable

register, generates an SMI# once per minute. The SMI handler can check for system activity by

reading the DEVACT_STS register. If none of the system bits are set, the SMI handler can

increment a software counter. When the counter reaches a sufficient number of consecutive

minutes with no activity, the SMI handler can then put the system into a lower power state.

82801AA and 82801AB Datasheet

5-61

Functional Description

If there is activity, various bits in the DEVACT_STS register are set to a 1. Software clears the bits

to 0 by writing a 1 to the bit position.

The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices

(SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI.

Other PCI activity can be monitored by checking the PCI interrupts.

5.13

System Management (D31:F0)

5.13.1

Overview of System Management Functions

The ICH provides various functions to make a system easier to manage and to lower the Total Cost

of Ownership (TCO) of the system. Features and functions can be augmented via external A/D

converters and GPIO, as well as an external microcontroller.

The following features and functions are supported by the ICH:

• Processor present detection.

— Detects if the processor fails to fetch the first instruction after reset.

• Various Error detection, reported by the host controller

— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt

• Intruder Detect input

— Can generate TCO interrupt or SMI# when the system cover is removed.

• Alert On LAN (ICH: 82801AA only)

— Sends hardcoded SMBus message over ALERTCLK and ALERTDATA pins to LAN

controller.

Note: Voltage ID from the processor can be read via GPI signals.

5.13.2

Theory of Operation

The System Management functions are designed to allow the system to diagnose failing

subsystems. The intent of this logic is that some of the system management functionality will be

provided without the aid of an external microcontroller.

Detecting a System Lockup

When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch

the first instruction after reset, the TCO timer times out twice and the ICH asserts PCIRST#.

Handling an Intruder

The ICH’s INTRUDER# input signal can be attached to a switch that is activated by the system’s

case being open. This input has a 2 RTC clock debounce. If INTRUDER# goes active (after the

debouncer), this sets the INTRD_DET bit in the TCO2_STS register. The INTRD_SEL bits in the

TCO2_CNT register can enable the ICH to cause an SMI# or interrupt. The BIOS or interrupt

handler can then cause a transition to the S5 state by writing to the SLP_EN bit.

5-62

82801AA and 82801AB Datasheet

Functional Description

The software can also directly read the status of the INTRUDER# signal (high or low) by clearing

and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder

function is not required.

5.13.2.1

Handling an ECC Error or Other Memory Error

The host controller provides a message to indicate that it would like to cause an SMI#, SCI,

SERR#, or NMI. The software must check the host controller as to the exact cause of the error.

5.13.3

Alert on LAN* (ICH: 82801AA only)

ICH can interface directly with an Alert On LAN enabled LAN controller to report messages to a

network management console without the aid of the system processor. This is crucial in cases

where the processor is malfunctioning or cannot function due to being in a low-power state.

The basic scheme is for the ICH to send specific messages via the SMBus Interface to the LAN

controller. Upon receiving the SMBus message, the network controller has a prepared Ethernet

message that it can send to a network management console. The prepared message is typically

stored in a non-volatile memory connected directly to the network controller.

Messages are sent by the ICH over the SMBus either because a specific event has occurred or they

are sent periodically (also known as a heartbeat). The event and heartbeat messages have the exact

same format. The event messages are sent based on events occurring. The heartbeat messages are

sent every 30 to 32 seconds. When an event occurs, the ICH sends a new message and increments

the SEQ[3:0] field. For heartbeat messages the sequence number does not increment.

If the policy is for the ICH to reboot the system after a hardware lockup, the ICH will not send an

Alert On LAN message. Instead, the BIOS detects the lockup and sends the appropriate message.

If the policy is for the ICH not to reboot after a hardware lockup, the ICH sends an Alert On LAN

message with the Watchdog (WD) Event Status bit set. This message is sent as soon as the lockup

is detected. The message is sent with the next incremented sequence number. Until the locked

system is suspended (via a power button override) the ICH continues to send Alert On LAN

messages every heartbeat period (30-32 seconds). If another event occurs prior to a power button

override, the ICH sends another Alert On LAN message with the next incremented sequence

number and appropriate status bit set.

If a boot is unsuccessful (processor does not fetch the first instruction), the ICH sends an Alert On

LAN message with the processor event status bit set and the next incremented sequence number.

This message is sent as soon as the lockup is detected (2 TCO timer timeouts).

82801AA and 82801AB Datasheet

5-63

Functional Description

Since some SMBus devices are not powered during some low power states, a separate SMBus

interface is provided to connect the ICH to the Alert On LAN network controller. The signals that

comprise this interface (referred to as ALERTCLK and ALERTDATA) are multiplexed with

GPIO[27:28]. At reset, these signals default to ALERTCLK and ALERTDATA. Note that Alert on

LAN messages are broadcast only over this separate interface, and the ICH looks for an ACK from

the LAN controller on the ALERTDATA signal.

If a unified SMBus architecture is desired, the SMBDATA and ALERTDATA (and SMBCLK and

ALERTCLK) signals can be “ORed” together since they are both open drain driven signals.

However, the ICH does not check to see if the SMBus is busy before broadcasting an Alert on

LAN message using the ALERTCLK and ALERTDATA signals. If the two interfaces are tied

together, it is important that there be no SMBus masters other than the ICH in the system. It is also

necessary to provide any necessary logic to isolate devices powered by standby from devices

powered by core power.

If the system is in a G1 (S1-S4) state, the ICH sends a heartbeat message every 30-32 seconds. If

an event occurs prior to the system being shutdown, the ICH immediately sends an event message

with the next incremented sequence number. After the event message, the ICH resumes sending

heartbeat messages.

Note that, for all message fields more than 1 bit, the most significant bit (MSB) is tranferred first.

The most significant bit is on the left. For example, for 100000 the “1” is the MSB.

All Alert On LAN messages are broadcast over the ALERTCLK and ALERTDATA pins that are

multiplexed with GPIO[27] and GPIO[28]. There are two types of Alert On LAN messages;

heartbeat messages and event messages. Heartbeat messages occur every 32 seconds. When

coming out of G3, the first heartbeat message could occur anytime within the first 32 seconds. The

second heartbeat message occurs 32 seconds after the first. However, event messages occur right

after certain events occur. One such event is the act of entering into the pre-boot state.

Coming out of a G3 state ALERTCLK/GPIO[27] and ALERTDATA/GPIO[28] default to

ALERTCLK and ALERTDATA. These signals can be programmed as GPIOs. However, before

the BIOS has a chance to program these signals to GPIOs, the pre-boot event message and

possibly a heartbeat message could be driven onto ALERTCLK and ALERTDATA.

If ALERTCLK and ALERTDATA are left floating, the SMBus state machine could get stuck in a

busy state indefinitely when an Alert On LAN message goes out. To prevent this condition, the

ICH requires external pull-ups to 3.3V standby on ALERTCLK and ALERTDATA.

If ALERTCLK and ALERTDATA are to be used as GPIOs, they need to be pulled up to 3.3V

standby to avoid the SMBus from getting stuck. Also, when coming out of a G3 state, the devices

that are connected to the GPIOs must be able to withstand the ICH driving Alert On LAN

messages on these pins until the BIOS has a chance to program these pins as GPIOs. Examples of

devices that would not be affected by this behavior include LEDs.

5-64

82801AA and 82801AB Datasheet

Functional Description

s

Table 5-48. Alert On LAN Message (ICH: 82801AA only)

Field

Comment

Cover Tamper Status

Temp Event Status

1 = This bit is set if the intruder detect bit is set (INTRD_DET).

1 = This bit is set if the ICH THERM# input signal is asserted.

1 = This bit is set if the processor failed to fetch the first instruction.

If the NO-REBOOT bit (D31:F0, Offset D4h, bit 1) is set and the

SECOND_TO_STS bit (TCO I/O offset 06h, bit 1) is set, and the

BOOT_STS bit (TCO I/O offset 06h, bit 2) is set, then the ICH sets

the processor Missing Event Status bit in the Alert On LAN message.

Processor Missing Event Status

If the NO-REBOOT bit is not set, and the SECOND_TO_STS bit is

set, the ICH attempts to reboot. After the reboot, the

SECOND_TO_STS bit is still set. If the processor fails to fetch the

first instruction, the BOOT_STS bit gets set. When the TCO timer

times out again, the ICH sets the processor Missing Event Status bit

in the Alert On LAN message.

TCO Timer Event Status

Software Event Status

1 = This bit is set when the TCO timer expires.

1 = This bit is set when software writes a 1 to the SEND_NOW bit.

1 = This bit is set when GPIO[11] signal is low.

GPIO Status

0 = This bit is cleared when GPIO[11] signal is high.

An event message is triggered on an transition of GPIO[11].

This is a sequence number. It is initially 0, and increments each time

the ICH sends a new message. When 1111 is reached, the sequence

number rolls over to 0000. MSB (SEQ3) sent first.

SEQ[3:0]

00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first

See Table 5-49 for a definition for each of these states.

System Power State

MESSAGE1

MESSAGE2

WDSTATUS

Same as the MESSAGE1 Register. MSB sent first.

Same as the MESSAGE2 Register. MSB sent first.

Same as the WDSTATUS Register. MSB sent first.

82801AA and 82801AB Datasheet

5-65

Functional Description

Table 5-49. System Power State Definition (ICH: 82801AA only)

State

Enter State

Exit State

CPURST# deasserted or powerbutton

override

Pre-Boot ICH has left G1 or G2 by deasserting SLP_S3#

Write to SLP_EN register or powerbutton

override

G0

G1

G2

CPURST# deasserted

ICH deasserts SLP_S3# after a wake event

or powerbutton override

Write to SLP_EN register with SLP_TYP for S1-S4

Write to SLP_EN register with SLP_TYP for S5 or

powerbutton override

ICH deasserts SLP_S3# after a wake event

5.14

IDE Controller (D31:F1)

The IDE interface of the ICH can support several types of data transfers:

• Programmed I/O (PIO): Processor is in control of the data transfer.

• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not

use the 8237 in the ICH. This protocol off loads the processor from moving data. This allows

higher transfer rate of up to 16 MB/s.

• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and

target throttling of data and transfer rates of up to 33 MB/s.

Note: The ICH0 (82801AB) does not support Ultra ATA/66. If software attempts to

program an IDE drive to run ATA/66 timings, the ICH0 will see short strobes

(from ATA/33 perspective) and will throttle the performance. This will result in

transfer rates that are slower than if the drive were programmed for ATA/33 mode.

• Ultra ATA/66 (ICH: 82801AA only): DMA protocol that redefines signals on the IDE cable

to allow both host and target throttling of data and transfer rates of up to 66 MB/s.

The ICH has integrated termination series resistors on the data and control lines as listed in

Table 5-50.

Table 5-50. IDE Integrated Series Termination Resistors

Integrated Series Termination

Resistor Value

Signal

Notes

PDD[15:0], SDD[15:0]

approximately 33 ohms

1

PDIOW#, SDIOW#, PDIOR#, PDIOW#, PDREQ,

SDREQ, PDDACK#, SDDACK#, PIORDY, SIORDY,

PDA[2:0], SDA[2:0], PDCS1#, SDCS1#, PDCS3#,

SDCS3#, IRQ14, IRQ15

approximately 22 ohms

2

NOTES:

1. Simulation data indicates that these integrated series termination resistors are a nominal 33 ohms but can

range from 28 ohms to 46 ohms.

2. Simulation data indicates that these integrated series termination resistors are a nominal 22 ohms but can

range from 19 ohms to 29 ohms.

5-66

82801AA and 82801AB Datasheet

Functional Description

5.14.1

PIO Transfers

The ICH IDE controller includes both compatible and fast timing modes. The fast timing modes

can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in

single transaction mode with compatible timings. The ICH IDE signals are controlled with the

granularity of the PCI clock.

Up to 2 IDE devices may be attached per IDE connector (drive 0 and drive 1). The IDETIM and

SIDETIM Registers permit different timing modes to be programmed for drive 0 and drive 1 of the

same connector.

The Ultra ATA/33 synchronous DMA timing modes can also be applied to each drive by

programming the SDMACTL and SDMATIM registers. When a drive is enabled for synchronous

DMA mode operation, the DMA transfers are executed with the synchronous DMA timings. The

PIO transfers are executed using compatible timings or fast timings if also enabled.

5.14.1.1

PIO IDE Timing Modes

IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency.

Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the

DA[2:0] and CSxx# lines are not set up. Startup latency provides the setup time for the DA[2:0]

and CSxx# lines prior to assertion of the read and write strobes (DIOR# and DIOW#).

Cycle latency consists of the I/O command strobe assertion length and recovery time. Recovery

time is provided so that transactions may occur back-to-back on the IDE interface (without

incurring startup and shutdown latency) without violating minimum cycle periods for the IDE

interface. The command strobe assertion width for the enhanced timing mode is selected by the

IDETIM Register and may be set to 2, 3, 4, or 5 PCI clocks. The recovery time is selected by the

IDETIM Register and may be set to 1, 2, 3, or 4 PCI clocks.

If IORDY is asserted when the initial sample point is reached, no wait states are added to the

command strobe assertion length. If IORDY is negated when the initial sample point is reached,

additional wait states are added. Since the rising edge of IORDY must be synchronized, at least

two additional PCI clocks are added.

Shutdown latency is incurred after outstanding scheduled IDE data port transactions (either a non-

empty write post buffer or an outstanding read prefetch cycles) have completed and before other

transactions can proceed. It provides hold time on the DA[2:0] and CSxx# lines with respect to the

read and write strobes (DIOR# and DIOW#). Shutdown latency is 2 PCI clocks in duration. The

IDE timings for various transaction types are shown in Table 5-51.

Note that bit 2 (16 bit I/O recovery enable) of the ISA I/O Recovery Timer Register does not add

wait states to IDE data port read accesses when any of the fast timing modes are enabled.

Table 5-51. IDE Transaction Timings (PCI Clocks)

Startup

IDE Transaction Type

Latency

IORDY Sample

Point (ISP)

Recovery Time

(RCT)

Shutdown

Latency

Non-Data Port Compatible

Data Port Compatible

Fast Timing Mode

4

3

2

11

6

22

14

2

2 - 5

1 - 4

82801AA and 82801AB Datasheet

5-67

Functional Description

5.14.1.2

5.14.1.3

IORDY Masking

The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) on

a drive by drive basis via the IDETIM Register.

PIO 32 Bit IDE Data Port Accesses

A 32-bit PCI transaction run to the IDE data address (01F0h primary, 0170h secondary) results in

two back to back 16-bit transactions to the IDE data port. The 32-bit data port feature is enabled for

all timings, not just enhanced timing. For compatible timings, a shutdown and startup latency is

incurred between the two 16-bit halves of the IDE transaction. This guarantees that the chip selects

will be deasserted for at least 2 PCI clocks between the 2 cycles.

5.14.1.4

PIO IDE Data Port Prefetching and Posting

The ICH can be programmed via the IDETIM registers to allow data to be posted to and prefetched

from the IDE data ports.

Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to

the IDE data ports and allows them to be performed back to back for the highest possible PIO data

transfer rates. The first data port read of a sector is called the demand read. Subsequent data port

reads from the sector are called prefetch reads. The demand read and all prefetch reads much be of

the same size (16 or 32 bits).

Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI

bus after the data is received by the ICH. The ICH will then run the IDE cycle to transfer the data to

the drive. If the ICH write buffer is non-empty and an unrelated (non-data or opposite channel) IDE

transaction occurs, that transaction will be stalled until all current data in the write buffer is

transferred to the drive.

5.14.2

Bus Master Function

The ICH can act as a PCI Bus master on behalf of an IDE slave device. Two PCI Bus master

channels are provided, one channel for each IDE connector (primary and secondary). By

performing the IDE data transfer as a PCI Bus master, the ICH off-loads the processor and

improves system performance in multitasking environments. Both devices attached to a connector

can be programmed for bus master transfers, but only one device per connector can be active at a

time.

5.14.2.1

Physical Region Descriptor Format

The physical memory region to be transferred is described by a Physical Region Descriptor (PRD).

The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until

all regions described by the PRDs in the table have been transferred. Note that the ICH bus master

IDE function does not support memory regions or Descriptor tables located on ISA.

Descriptor Tables must be aligned on 64 Kbyte boundaries. Each PRD entry in the table is 8 bytes

in length. The first 4 bytes specify the byte address of a physical memory region. This memory

region must be DWord-aligned and must not cross a 64 KByte boundary. The next two bytes

specify the size or transfer count of the region in bytes (64 KByte limit per region). A value of zero

in these two bytes indicates 64 Kbytes (thus the minimum transfer count is 1). If bit 7 (EOT) of the

last byte is a 1, it indicates that this is the final PRD in the Descriptor table. Bus master operation

terminates when the last descriptor has been retired.

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82801AA and 82801AB Datasheet

Functional Description

When the Bus Master IDE controller is reading data from the memory regions, bit 1 of the Base

Address is masked and byte enables are asserted for all read transfers. The controller reads to a

boundary of 64 bytes, regardless of byte count field of the PRD. Only the byte count value is

transferred to the drive however. When writing data, bit 1 of the Base Address is not masked and if

set, causes the lower Word byte enables to be deasserted for the first DWord transfer. The write to

PCI typically consists of a 32-byte cache line. If valid data ends prior to end of the cache line, the

byte enables are deasserted for invalid data.

The total sum of the byte counts in every PRD of the descriptor table must be equal to or greater

than the size of the disk transfer request. If greater than the disk transfer request, the driver must

terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to

0) when the drive issues an interrupt to signal transfer completion.

Figure 5-12. Physical Region Descriptor Table Entry

Main Memo ry

Mem ory

Region

Byte 3

Mem ory Region Physical Base Address [31:1]

EOT Reserved Byte C ount [15:1]

Byte 2

Byte 1

Byte 0

0

051910 _3 .drw

5.14.2.2

Line Buffer

A single line buffer exists for the ICH Bus master IDE interface. This buffer is not shared with any

other function. The buffer is maintained in either the read state or the write state. Memory writes

are typically 4-DWord bursts and invalid DWords have C/BE[3:0]#=0Fh. The line buffer allows

burst data transfers to proceed at peak transfer rates.

The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically when the

controller has transferred all data associated with a Descriptor Table (as determined by EOT bit in

last PRD). The IDE Interrupt Status bit is set when the IDE device generates an interrupt. These

events may occur prior to line buffer emptying for memory writes. If either of these conditions

exist, all PCI Master non-memory read accesses to ICH are retried until all data in the line buffers

has been transferred to memory.

5.14.2.3

Bus Master IDE Timings

The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The

DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for

DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster that

its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock

that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is deasserted on

the next PCI clock and no more transfers take place until DMA request is asserted again.

82801AA and 82801AB Datasheet

5-69

Functional Description

5.14.2.4

Interrupts

The ICH is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt.

This connection is done from the ISA pin, before any mask registers. This implies the following:

• Bus Master IDE is operating under an interrupt based driver. Therefore, it will not operate

under environments where the IDE device drives an interrupt but the interrupt is masked in the

system.

• Bus Master IDE devices are connected directly off of ICH. IDE interrupts cannot be

communicated through PCI devices or the serial stream.

5.14.2.5

Bus Master IDE Operation

To initiate a bus master transfer between memory and an IDE device, the following steps are

required:

1. Software prepares a PRD Table in system memory. The PRD Table must be DWord-aligned

and must not cross a 64K byte boundary.

2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer

Register. The direction of the data transfer is specified by setting the Read/Write Control bit.

The interrupt bit and Error bit in the Status register are cleared.

3. Software issues the appropriate DMA transfer command to the disk device.

4. The bus master function is engaged by software writing a '1' to the Start bit in the Command

Register. The first entry in the PRD table is fetched and loaded into two registers which are not

visible by software, the Current Base and Current Count registers. These registers hold the

current value of the address and byte count loaded from the PRD table. The value in these

registers is only valid when there is an active command to an IDE device.

5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.

6. The controller transfers data to/from memory responding to DMA requests from the IDE

device. The IDE device and the host controller may or may not throttle the transfer several

times. When the last data transfer for a region has been completed on the IDE interface, the

next descriptor is fetched from the table. The descriptor contents are loaded into the Current

Base and Current Count registers.

7. At the end of the transfer the IDE device signals an interrupt.

8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then

reads the controller status followed by the drive status to determine if the transfer completed

successfully.

The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers

terminate when the physical region described by the last PRD in the table has been completely

transferred. The active bit in the Status Register is reset and the DDRQ signal is masked.

The 64 byte buffer is flushed (when in the write state) or invalidated (when in the read state) when

a terminal count condition exists; that is, the current region descriptor has the EOL bit set and that

region has been exhausted. The buffer is also flushed (write state) or invalidated (read state) when

the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register

and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, can be assured

that all data destined for system memory has been transferred and that data is valid in system

memory. Table 5-52 describes how to interpret the Interrupt and Active bits in the Status Register

after a DMA transfer has started.

During concurrent DMA or Ultra-DMA transfers, the ICH IDE interface arbitrates between the

primary and secondary IDE cables when a PRD (Physical Region Descriptor) entry expires.

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Functional Description

Table 5-52. Interrupt/Active Bit Interaction Definition

Interrupt

Active

Description

0

1

DMA transfer is in progress. No interrupt has been generated by the IDE device.

The IDE device generated an interrupt. The controller exhausted the Physical Region

Descriptors. This is the normal completion case where the size of the physical

memory regions was equal to the IDE device transfer size.

1

0

1

The IDE device generated an interrupt. The controller has not reached the end of the

physical memory regions. This is a valid completion case where the size of the

physical memory regions was larger than the IDE device transfer size.

This bit combination signals an error condition. If the Error bit in the status register is

set, then the controller has some problem transferring data to/from memory. Specifics

of the error have to be determined using bus-specific information. If the Error bit is not

set, then the PRD's specified a smaller size than the IDE transfer size.

0

5.14.2.6

Error Conditions

IDE devices are sector based mass storage devices. The drivers handle errors on a sector basis;

either a sector is transferred successfully or it is not. A sector is 512 bytes.

If the IDE device does not complete the transfer due to a hardware or software error, the command

is eventually stopped by the driver setting Command Start bit to 0, when the driver times out the

disk transaction. Information in the IDE device registers help isolate the cause of the problem.

If the controller encounters an error while doing the bus master transfers, it stops the transfer (i.e.,

resets the Active bit in the Command register) and sets the Error bit in the Bus Master IDE Status

register. The controller does not generate an interrupt when this happens. The device driver can use

device specific information (PCI Configuration Space Status register and IDE Drive Register) to

determine what caused the error.

When a requested transfer does not complete properly, information in the IDE device registers

(Sector Count) can be used to determine how much of the transfer was completed and to construct

a new PRD table to complete the requested operation. In most cases the existing PRD table can be

used to complete the operation.

5.14.2.7

8237 Like Protocol

The 8237 mode DMA is similar in form to DMA used on the ISA bus. This mode uses pins

familiar to the ISA bus, namely a DMA Request, a DMA Acknowledge, and I/O read/write strobes.

These pins have similar characteristics to their ISA counterparts in terms of when data is valid

relative to strobe edges, and the polarity of the strobes; however, the ICH does not use the 8237 for

this mode.

82801AA and 82801AB Datasheet

5-71

Functional Description

5.14.3

Ultra ATA/33 Protocol

Ultra ATA/33 is enabled through configuration register 48h in Device 31:Function 1 for each IDE

device. The IDE signal protocols are significantly different under this mode than for the 8237

mode.

Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33 capable IDE

controller such as the ICH and one or more Ultra ATA/33 capable IDE devices. It utilizes the

standard Bus Master IDE functionality and interface to initiate and control the transfer. Ultra ATA/

33 utilizes a “source synchronous” signaling protocol to transfer data at rates up to 33 Mbytes/sec.

The Ultra ATA/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16) error

checking protocol.

5.14.3.1

Signal Descriptions

The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a

number of the standard IDE control signals when in Ultra ATA/33 mode. These redefinitions are

shown in Table 5-53. Read cycles are defined as transferring data from the IDE device to the ICH.

Write cycles are defined as transferring data from ICH to IDE device.

Table 5-53. Ultra ATA/33 Control Signal Redefinitions

Standard IDE

Signal Definition

Ultra ATA/33 Read

Cycle Definition

Ultra ATA/33 Write

Cycle Definition

ICH Primary

Channel Signal

ICH Secondary

Channel Signal

DIOW#

DIOR#

IORDY

STOP

PDIOW#

PDIOR#

PIORDY

SDIOW#

SDIOR#

SIORDY

DMARDY#

STROBE

DMARDY#

The DIOW# signal is redefined as STOP for both read and write transfers. This is always driven by

the ICH and is used to request that a transfer be stopped or as an acknowledgment to stop a request

from the IDE device.

The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device to the ICH

(read). It is used by the ICH to signal when it is ready to transfer data and to add wait states to the

current transaction. The DIOR# signal is redefined as STROBE for transferring data from the ICH

to the IDE device (write). It is the data strobe signal driven by the ICH on which data is transferred

during each rising and falling edge transition.

The IORDY signal is redefined as STROBE for transferring data from the IDE device to the ICH

(read). It is the data strobe signal driven by the IDE device on which data is transferred during each

rising and falling edge transition. The IORDY signal is redefined as DMARDY# for transferring

data from the ICH to the IDE device (write). It is used by the IDE device to signal when it is ready

to transfer data and to add wait states to the current transaction.

All other signals on the IDE connector retain their functional definitions during Ultra ATA/33

operation.

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Functional Description

5.14.3.2

Operation

Initial setup programming consists of enabling and performing the proper configuration of ICH and

the IDE device for Ultra ATA/33 operation. For the ICH, this consists of enabling Synchronous

DMA mode and setting up appropriate Synchronous DMA timings.

When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is

followed. Once programmed, the drive and ICH control the transfer of data via the Ultra ATA/33

protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase,

and a burst termination phase.

The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the

transfer, the ICH asserts the DMACK# signal. When DMACK# is asserted, the host controller

drives CS0# and CS1# inactive, DA0-DA2 low and the IDE device drives IOCS16# inactive. For

write cycles, the ICH deasserts STOP, waits for the IDE device to assert DMARDY#, and then

drives the first data word and STROBE signal. For read cycles, the ICH tri-states the DD lines,

deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word and

STROBE.

The data transfer phase continues the burst transfers with the data transmitter (ICH - writes, IDE

device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on

each rising and falling edge of STROBE. The transmitter can pause the burst by holding STROBE

high or low, resuming the burst by again toggling STROBE. The receiver can pause the burst by

deasserting DMARDY# and resumes the transfers by asserting DMARDY#. The ICH will pause a

burst transaction to prevent an internal line buffer over or under flow condition; resuming once the

condition has cleared. It may also pause a transaction if the current PRD byte count has expired;

resuming once it has fetched the next PRD.

The current burst can be terminated by either the transmitter or receiver. A burst termination

consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The ICH can stop a burst

by asserting STOP, with the IDE device acknowledging by deasserting DMARQ. The IDE device

stops a burst by deasserting DMARQ and the ICH acknowledges by asserting STOP. The

transmitter then drives the STROBE signal to high. The ICH will then drive the CRC value onto

the DD lines and deassert DMACK#. The IDE device latches the CRC value on the rising edge of

DMACK#. The ICH terminates a burst transfer if it needs to service the opposite IDE channel, if a

Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon

transferring the last data from the final PRD.

5.14.3.3

5.14.3.4

CRC Calculation

Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33 transfers. The

CRC value is calculated for all data by both the ICH and the IDE device over the duration of the

Ultra ATA/33 burst transfer segment. This segment is defined as all data transferred with a valid

STROBE edge from DDACK# assertion to DDACK# deassertion. At the end of the transfer burst

segment, the ICH will drive the CRC value onto the DD[15:0] signals. It is then latched by the IDE

device on deassertion of DDACK#. The IDE device compares the ICH CRC value to its own and

reports an error if there is a mismatch.

Synchronous DMA Timings

The timings for Ultra ATA/33 are programmed into the Synchronous DMA Timing Register. The

programmable timings include Cycle Time (CT) and Ready to Pause (RP) time. The Cycle Time

represents the minimum pulse width of active data strobe (STROBE) signal. The Ready to Pause

time represents the number of PCI clocks the ICH will wait from deassertion of DMARDY# to the

assertion of STOP when it desires to stop a burst read transaction.

82801AA and 82801AB Datasheet

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Functional Description

5.14.3.5

Ultra ATA/66 (ICH: 82801AA only)

The ICH (82801AA) supports both the Ultra ATA/33 and Ultra ATA/66 protocols. Ultra ATA/66 is

similar to the Ultra ATA/33 scheme and is intended to be device driver compatible. The

Ultra ATA/66 logic clocks at 66 MHz instead of 33 MHz, and can move 16 bits of data every 2

clocks (for a maximum of 66 MBytes/sec).

To achieve the higher data rate, the timings are shortened and the quality of the cable is improved

to reduce reflections, noise, and inductive coupling. Note that the improved cable is required and

still plug into the standard IDE connector.

The Ultra ATA/66 protocol also has a 44 Mbytes/sec mode where it uses three 66 MHz clocks. The

Ultra ATA/66 protocol is enabled via config bits 3:0 at offset 54h.

5.15

USB Controller (Device 31:Function 2)

The ICH contains one USB Host Controller. The Host Controller includes the root hub with two

separate USB ports. The ICH Host Controller supports the standard Universal Host Controller

Interface (UHCI) Rev 1.0. Overcurrent detection on two USB ports is supported. The overcurrent

signals can be used as GPIO if not needed. The ICH’s USB controller is arbitrated as differently

than standard PCI devices to improve arbitration latency.

Note: Poor performing PCI devices that cause long latencies (numerous retries) to CPU-to-PCI locked

cycles may starve isochronous transfers between USB or AC’97 devices and memory. This will

result in overrun or underrun, causing reduced quality of the isochronous data (e.g., audio).

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82801AA and 82801AB Datasheet

Functional Description

5.15.1

Data Structures in Main memory

This section describes the details of the data structures used to communicate control, status, and

data between software and the ICH: Frame Lists, Transfer Descriptors, and Queue Heads. Frame

Lists are aligned on 4-Kbyte boundaries. Transfer Descriptors and Queue Heads are aligned on

16-byte boundaries.

5.15.1.1

Frame List Pointer

The frame list pointer contains a link pointer to the first data object to be processed in the frame, as

well as the control bits defined in Table 5-54.

Table 5-54. Frame List Pointer Bit Description

Bit

Description

Frame List Pointer (FLP). This field contains the address of the first data object to be processed in

the frame and corresponds to memory address signals [31:4], respectively.

31:4

3:2

Reserved. These bits must be written as 0.

QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer

is a TD (Transfer Descriptor) or a QH (Queue Head). This allows the ICH to perform the proper type

of processing on the item after it is fetched.

1

0

1 = QH

0 = TD

Terminate (T). This bit indicates to the ICH whether the schedule for this frame has valid entries in it.

1 = Empty Frame (pointer is invalid).

0 = Pointer is valid (points to a QH or TD).

82801AA and 82801AB Datasheet

5-75

Functional Description

5.15.1.2

Transfer Descriptor (TD)

Transfer Descriptors (TDs) express the characteristics of the transaction requested on USB by a

client. TDs are always aligned on 16-byte boundaries, and the elements of the TD are shown in

Figure 5-13. The 4 different USB transfer types are supported by a small number of control bits in

the descriptor that the ICH interprets during operation. All Transfer Descriptors have the same

basic, 32-byte structure. During operation, the ICH hardware performs consistency checks on some

fields of the TD. If a consistency check fails, the ICH halts immediately and issues an interrupt to

the system. This interrupt cannot be masked within the ICH.

Figure 5-13. Transfer Descriptor

31 30 29 28 27 26 25 24 23 21 20 19 18 16 15 14

11 10 8 7

4 3

2

1

0

Link Pointer

0 Vf

Q

T

SPD C_ERR LS ISO IOC

R

Status

R

ActLen

PID

MaxLen

R

D

EndPt

Device Address

Buffer Pointer

R=Reserved

ICH Read/Write

ICH Read Only

Table 5-55. TD Link Pointer

Bit

Description

Link Pointer (LP). Bits [31:4] Correspond to memory address signals [31:4], respectively. This field

points to another TD or QH.

31:4

3

Reserved. Must be 0 when writing this field.

Depth/Breadth Select (VF). This bit is only valid for queued TDs and indicates to the hardware

whether it should process in a depth first or breadth first fashion. When set to depth first, it informs

the ICH to process the next transaction in the queue rather than starting a new queue.

2

1

1 = Depth first.

0 = Breadth first.

QH/TD Select (Q). This bit informs the ICH whether the item referenced by the link pointer is

another TD or a QH. This allows the ICH to perform the proper type of processing on the item after it

is fetched

1 = QH.

0 = TD.

Terminate (T). This bit informs the ICH that the link pointer in this TD does not point to another valid

entry. When encountered in a queue context, this bit indicates to the ICH that there are no more

valid entries in the queue. A TD encountered outside of a queue context with the T bit set informs

the ICH that this is the last TD in the frame.

0

1 = Link Pointer field not valid.

0 = Link Pointer field is valid.

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82801AA and 82801AB Datasheet

Functional Description

Table 5-56. TD Control and Status (Sheet 1 of 2)

Bit

Description

31:30 Reserved.

Short Packet Detect (SPD). When a packet has this bit set to 1 and the packet is an input packet, is

in a queue; and successfully completes with an actual length less than the maximum length then the

TD is marked inactive, the Queue Header is not updated and the USBINT status bit (Status

Register) is set at the end of the frame. In addition, if the interrupt is enabled, the interrupt is sent at

the end of the frame.

29

Note that any error (e.g., babble or FIFO error) prevents the short packet from being reported. The

behavior is undefined when this bit is set with output packets or packets outside of queues.

1 = Enable.

0 = Disable.

Error Counter (C_ERR). This field is a 2-bit down counter that keeps track of the number of Errors

detected while executing this TD. If this field is programmed with a non zero value during setup, the

ICH decrements the count and writes it back to the TD if the transaction fails. If the counter counts

from one to zero, the ICH marks the TD inactive, sets the “STALLED” and error status bit for the

error that caused the transition to zero in the TD. An interrupt is generated to Host Controller Driver

(HCD) if the decrement to zero was caused by Data Buffer error, Bit stuff error, or if enabled, a CRC

or Timeout error. If HCD programs this field to zero during setup, the ICH does not count errors for

this TD and there is no limit on the retries of this TD.

Bits[28:27]

Interrupt After

00

01

10

11

No Error Limit

1 Error

2 Errors

28:27

3 Errors

Error

Decrement Counter

Error

Decrement Counter

CRC Error

Yes

No

Data Buffer Error

Stalled

Bit stuff Error

Yes

No*

Yes

Timeout Error

NAK Received

Babble Detected

No*

* Detection of Babble or Stall automatically deactivates the TD. Thus, count is not decremented.

Low Speed Device (LS). This bit indicates that the target device (USB data source or sink) is a low

speed device, running at 1.5 Mb/s, instead of at full speed (12 Mb/sec). There are special

restrictions on schedule placement for low speed TDs. If an ICH root hub port is connected to a full

speed device and this bit is set to a 1 for a low speed transaction, the ICH sends out a low speed

preamble on that port before sending the PID. No preamble is sent if a ICH root hub port is

connected to a low speed device.

26

1 = Low Speed Device

0 = Full Speed Device

Isochronous Select (IOS). The field specifies the type of the data structure. If this bit is set to a 1,

then the TD is an isochronous transfer. Isochronous TDs are always marked inactive by the

hardware after execution, regardless of the results of the transaction.

25

24

1 = Isochronous Transfer Descriptor

0 = Non-isochronous Transfer Descriptor

Interrupt on Complete (IOC). This specifies that the ICH should issue an interrupt on completion of

the frame in which this Transfer Descriptor is executed. Even if the Active bit in the TD is already

cleared when the TD is fetched (no transaction will occur on USB), an IOC interrupt is generated at

the end of the frame.

1 = Issue IOC

Active. For ICH schedule execution operations, see the Data Transfers To/From Main Memory

section.

1 = Set to 1 by software to enable the execution of a message transaction by the ICH.

23

0 = When the transaction associated with this descriptor is completed, the ICH sets this bit to 0

indicating that the descriptor should not be executed when it is next encountered in the

schedule. The Active bit is also set to 0 if a stall handshake is received from the endpoint.

82801AA and 82801AB Datasheet

5-77

Functional Description

Table 5-56. TD Control and Status (Sheet 2 of 2)

Bit

Description

Stalled.

1 = Set to a 1 by the ICH during status updates to indicate that a serious error has occurred at the

device/endpoint addressed by this TD. This can be caused by babble, the error counter

counting down to zero, or reception of the STALL handshake from the device during the

transaction. Any time that a transaction results in the Stalled bit being set, the Active bit is also

cleared (set to 0). If a STALL handshake is received from a SETUP transaction, a Time Out

Error will also be reported.

22

Data Buffer Error (DBE).

21

1 = Set to a 1 by the ICH during status update to indicate that the ICH is unable to keep up with the

reception of incoming data (overrun) or is unable to supply data fast enough during transmission

(underrun). When this occurs, the actual length and Max Length field of the TD will not match. In

the case of an underrun, the ICH transmits an incorrect CRC (thus, invalidating the data at the

endpoint) and leaves the TD active (unless error count reached zero). If a overrun condition

occurs, the ICH forces a timeout condition on the USB, invalidating the transaction at the

source.

Babble Detected (BABD).

20

19

1 = Set to a 1 by the ICH during status update when “babble” is detected during the transaction

generated by this descriptor. Babble is unexpected bus activity for more than a preset amount of

time. In addition to setting this bit, the ICH also sets the” STALLED” bit (bit 22) to a 1. Since

”babble” is considered a fatal error for that transfer, setting the” STALLED” bit to a 1 insures that

no more transactions occur as a result of this descriptor. Detection of babble causes immediate

termination of the current frame. No further TDs in the frame are executed. Execution resumes

with the next frame list index.

Negative Acknowledgment (NAK) Received (NAKR).

1 = Set to a 1 by the ICH during status update when the ICH receives a “NAK” packet during the

transaction generated by this descriptor. If a NAK handshake is received from a SETUP

transaction, a Time Out Error is also reported.

CRC/Time Out Error (CRC_TOUT).

1 = Set to a 1 by the ICH as follows:

•

During a status update in the case that no response is received from the target device/endpoint

within the time specified by the protocol chapter of the USB specification.

During a status update when a Cycli Redundancy Check (CRC) error is detected during the

transaction associated with this transfer descriptor.

18

In the transmit case (OUT or SETUP Command), this is in response to the ICH detecting a

timeout from the target device/endpoint.

In the receive case (IN Command), this is in response to the ICH’s CRC checker circuitry

detecting an error on the data received from the device/endpoint or a NAK or STALL handshake

being received in response to a SETUP transaction.

Bit stuff Error (BSE).

17

16

1 = This bit is set to a 1 by the ICH during status update to indicate that the receive data stream

contained a sequence of more than 6 ones in a row.

Bus Turn Around Time-out (BTTO).

1 = This bit is set to a 1 by the ICH during status updates to indicate that a bus time-out condition

was detected for this USB transaction. This time-out is specially defined as not detecting an

IDLE-to ‘K’ state Start of Packet (SOP) transition from 16 to 18 bit times after the SE0-to IDE

transition of previous End of Packet (EOP).

15:11 Reserved

Actual Length (ACTLEN). The Actual Length field is written by the ICH at the conclusion of a USB

transaction to indicate the actual number of bytes that were transferred. It can be used by the

software to maintain data integrity. The value programmed in this register is encoded as n-1 (see

Maximum Length field description in the TD Token).

10:0

5-78

82801AA and 82801AB Datasheet

Functional Description

Table 5-57. TD Token

Bit

Description

Maximum Length (MAXLEN). The Maximum Length field specifies the maximum number of data

bytes allowed for the transfer. The Maximum Length value does not include protocol bytes, such as

Packet ID (PID) and CRC. The maximum data packet is 1280 bytes. The 1280 packet length is the

longest packet theoretically guaranteed to fit into a frame. Actual packet maximum lengths are set

by HCD according to the type and speed of the transfer. Note that the maximum length allowed by

the USB specification is 1023 bytes. The valid encodings for this field are:

0x000 = 1 byte

0x001 = 2 bytes

....

0x3FE = 1023 bytes

31:21

0x3FF = 1024 bytes

....

0x4FF = 1280 bytes

0x7FF = 0 bytes (null data packet)

Note that values from 500h to 7FEh are illegal and cause a consistency check failure.

In the transmit case, the ICH uses this value as a terminal count for the number of bytes it fetches

from host memory. In most cases, this is the number of bytes it will actually transmit. In rare cases,

the ICH may be unable to access memory (e.g., due to excessive latency) in time to avoid

underrunning the transmitter. In this instance the ICH would transmit fewer bytes than specified in

the Maximum Length field.

20

19

Reserved.

Data Toggle (D). This bit is used to synchronize data transfers between a USB endpoint and the

host. This bit determines which data PID is sent or expected (0=DATA0 and 1=DATA1). The Data

Toggle bit provides a 1-bit sequence number to check whether the previous packet completed. This

bit must always be 0 for Isochronous TDs.

Endpoint (ENDPT). This 4-bit field extends the addressing internal to a particular device by

18:15 providing 16 endpoints. This permits more flexible addressing of devices in which more than one

sub-channel is required.

14:8

Device Address. This field identifies the specific device serving as the data source or sink.

Packet Identification (PID). This field contains the Packet ID to be used for this transaction. Only

the IN (69h), OUT (E1h), and SETUP (2Dh) tokens are allowed. Any other value in this field causes

a consistency check failure resulting in an immediate halt of the ICH. Bits [3:0] are complements of

bits [7:4].

7:0

Table 5-58. TD Buffer Pointer

Bit

Description

Buffer Pointer (BUFF_PNT). Bits [31:0] corresponds to memory address [31:0], respectively. It

points to the beginning of the buffer that will be used during this transaction. This buffer must be at

least as long as the value in the Maximum Length field described int the TD Token. The data buffer

may be byte-aligned.

31:0

82801AA and 82801AB Datasheet

5-79

Functional Description

5.15.1.3

Queue Head (QH)

Queue heads are special structures used to support the requirements of Control, Bulk, and Interrupt

transfers. Since these TDs are not automatically retired after each use, their maintenance

requirements can be reduced by putting them into a queue. Queue Heads must be aligned on a

16-byte boundary, and the elements are shown in Table 5-59.

Table 5-59. Queue Head Block

Bytes

Description

Attributes

00-03

04-07

Queue Head Link Pointer

RO

Queue Element Link Pointer

R/W

Table 5-60. Queue Head Link Pointer

Bit

Description

Queue Head Link Pointer (QHLP). This field contains the address of the next data object to be

processed in the horizontal list and corresponds to memory address signals [31:4], respectively.

31:4

3:2

1

Reserved. These bits must be written as 0s.

QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer

is another TD or a QH.

1=QH

0=TD

Terminate (T). This bit indicates to the ICH that this is the last QH in the schedule. If there are active

TDs in this queue, they are the last to be executed in this frame.

0

1 = Last QH (pointer is invalid).

0 = Pointer is valid (points to a QH or TD).

Table 5-61. Queue Element Link Pointer

Bit

Description

Queue Element Link Pointer (QELP). This field contains the address of the next TD or QH to be

processed in this queue and corresponds to memory address signals [31:4], respectively.

31:4

3:2

Reserved.

QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer

is another TD or a QH. For entries in a queue, this bit is typically set to 0.

1

0

1 = QH

0 = TD

Terminate (T). This bit indicates to the ICH that there are no valid TDs in this queue. When HCD has

new queue entries it overwrites this value with a new TD pointer to the queue entry.

1 = Terminate (No valid queue entries).

0 = Pointer is valid.

5-80

82801AA and 82801AB Datasheet

Functional Description

5.15.2

Data Transfers To/From Main Memory

The following sections describe the details on how HCD and the ICH communicate via the

Schedule data structures. The discussion is organized in a top-down manner, beginning with the

basics of walking the Frame List, followed by a description of generic processing steps common to

all transfer descriptors, and finally a discussion on Transfer Queuing.

5.15.2.1

Executing the Schedule

Software programs the ICH with the starting address of the Frame List and the Frame List index,

then causes the ICH to execute the schedule by setting the Run/Stop bit in the Control register to

Run. The ICH processes the schedule one entry at a time: the next element in the frame list is not

fetched until the current element in the frame list is retired.

Schedule execution proceeds in the following fashion:

• The ICH first fetches an entry from the Frame List. This entry has three fields. Bit 0 indicates

whether the address pointer field is valid. Bit 1 indicates whether the address points to a

Transfer Descriptor or to a queue head. The third field is the pointer itself.

• If isochronous traffic is to be moved in a given frame, the Frame List entry points to a Transfer

Descriptor. If no isochronous data is to be moved in that frame, the entry points to a queue

head or the entry is marked invalid and no transfers are initiated in that frame.

• If the Frame List entry indicates that it points to a Transfer Descriptor, the ICH fetches the

entry and begins the operations necessary to initiate a transaction on USB. Each TD contains a

link field that points to the next entry, as well as indicating whether it is a TD or a QH.

• If the Frame List entry contains a pointer to a QH, the ICH processes the information from the

QH to determine the address of the next data object that it should process.

• The TD/QH process continues until the millisecond allotted to the current frame expires. At

this point, the ICH fetches the next entry from the Frame List. If the ICH is not able to process

all of the transfer descriptors during a given frame, those descriptors are retired by software

without having been executed.

5.15.2.2

Processing Transfer Descriptors

The ICH executes a TD using the following generalized algorithm. These basic steps are common

across all modes of TDs. Subsequent sections present processing steps unique to each TD mode.

1. ICH Fetches TD or QH from the current Link Pointer.

2. If a QH, go to 1 to fetch from the Queue Element Link Pointer. If inactive, go to 12

3. Build Token, actual bits are in TD Token.

4. If (Host-to-Function) then

[PCI Access] issue request for data, (referenced through TD.BufferPointer)

wait for first chunk data arrival

end if

5. [Begin USB Transaction] Issue Token (from token built in 2, above) and begin data transfer.

if (Host-to-Function) then Go to 6

else Go to 7

end if

6. Fetch data from memory (via TD BufferPointer) and transfer over USB until TD Max-Length

bytes have been read and transferred. [Concurrent system memory and USB Accesses].

Go to 8.

82801AA and 82801AB Datasheet

5-81

Functional Description

7. Wait for data to arrive (from USB). Write incoming bytes into memory beginning at TD

BufferPointer. Internal HC buffer should signal end of data packet. Number of bytes received

must be (TD Max-Length; The length of the memory area referenced by TD BufferPointer

must be (TD Max-Length. [Concurrent system memory and USB Accesses].

8. Issue handshake based on status of data received (Ack or Time-out). Go to 10.

9. Wait for handshake, if required [End of USB Transaction].

10. Update Status [PCI Access] (TD.Status and TD.ActualLength).

If the TD was an isochronous TD, mark the TD inactive. Go to 12.

If not an isochronous TD, and the TD completed successfully, mark the TD inactive. Go to 11.

If not successful, and the error count has not been reached, leave the TD active. If the error

count has been reached, mark the TD inactive. Go to 12.

11. Write the link pointer from the current TD into the element pointer field of the QH structure. If

the Vf bit is set in the TD link pointer, go to 2.

12. Proceed to next entry.

5.15.2.3

Command Register, Status Register, and TD Status Bit Interaction

Table 5-62. Command Register, Status Register, and TD Status Bit Interaction

Condition

ICH USB Status Register Actions

TD Status Register Actions

•

Clear Active bit¹and set

Stall bit¹

CRC/Time Out Error

•

Set USB Error Int bit¹, Clear HC Halted bit

•

Clear Run/Stop bit in command register

Set HC Process Error and HC Halted bits

Illegal PID, PID Error,

Max Length (illegal)

•

Clear Run/Stop bit in command register

Set Host System Error and HC Halted bits

PCI Master/Target

Abort

•

Clear Run/Stop bit in command register²

Set HC Halted bit

Suspend Mode

Resume Received and

Suspend Mode = 1

•

Set Resume received bit

•

Clear Run/Stop bit in command register

Set HC Halted bit

Run/Stop = 0

Config Flag Set

•

Set Config Flag in command register

Clear Run/Stop and Config Flag in command

register

HC Reset/Global Reset

•

Clear USB Int, USB Error Int, Resume

received, Host System Error, HC Process

Error, and HC Halted bits

IOC = 1 in TD Status

Stall

•

Set USB Int bit

•

Clear Active bit¹and set

Stall bit

Set USB Error Int bit

Bit Stuff/Data Buffer

Error

Clear Active bit¹and set

Stall bit¹

•

Set USB Error Int bit¹

Set USB Int bit

Short Packet Detect

Clear Active bit

NOTES:

1. Only If error counter counted down from 1 to 0

2. Suspend mode can be entered only when Run/Stop bit is 0

5-82

82801AA and 82801AB Datasheet

Functional Description

Note: If a NAK or STALL response is received from a SETUP transaction, a Time Out Error is reported.

This causes the Error counter to decrement and the CRC/Time-out Error status bit to be set within

the TD Control and Status DWord during write back. If the Error counter changes from 1 to 0, the

Active bit is reset to 0 and Stalled bit to 1 as normal.

5.15.2.4

Transfer Queuing

Transfer Queues are used to implement a guaranteed data delivery stream to a USB Endpoint.

Transfer Queues are composed of two parts: a Queue Header (QH) and a linked list. The linked list

of TDs and QHs has an indeterminate length (0 to n).

The QH contains two link pointers and is organized as two contiguous DWords. The first DWord is

a horizontal pointer (Queue Head Link Pointer), used to link a single transfer queue with either

another transfer queue, or a TD (target data structure depends on Q bit). If the T bit is set, this QH

represents the last data structure in the current Frame. The T bit informs the ICH that no further

processing is required until the beginning of the next frame. The second DWord is a vertical pointer

(Queue Element Link Pointer) to the first data structure (TD or QH) being managed by this QH. If

the T bit is set, the queue is empty. This pointer may reference a TD or another QH.

Figure 5-14 illustrates four example queue conditions. The first QH (on far left) is an example of

an “empty” queue; the termination bit (T Bit), in the vertical link pointer field, is set to 1. The

horizontal link pointer references another QH. The next queue is the expected typical

configuration. The horizontal link pointer references another QH, and the vertical link pointer

references a valid TD.

Typically, the vertical pointer in a QH points to a TD. However, as shown in Figure 5-14 (third

example from left side of figure) the vertical pointer could point to another QH. When this occurs,

a new Q Context is entered and the Q Context just exited is NULL (ICH will not update the vertical

pointer field).

The far right QH is an example of a frame ‘termination’ node. Since its horizontal link pointer has

its termination bit set, the ICH assumes there is no more work to complete for the current Frame.

Figure 5-14. Example Queue Conditions

31

Frame List Pointer

2

1

0

T

Q

Indicates 'Nil' Next Pointer

QH

31

2

1

0

T

31

2

1

0

T

31

2

1

0

T

31

2

1

0

T

Q

Link Pointer (Horiz)

Link Pointer (Vert)

Q

Link Pointer (Horiz)

Link Pointer (Vert)

Link Pointer (Horiz)

Link Pointer (Vert)

Q

Link Pointer (Horiz)

Link Pointer (Vert)

Q

Indicates 'Nil' Next Pointer

Indicates 'NULL' Queue Head

Link Pointer

TD

Q

T

Link Pointer

TD

Q T

QH

31

2

Link Pointer (Horiz)

Link Pointer (Vert)

1

0

T

Q

Link Pointer

TD

Link Pointer

TD

Q

T

Link Pointer (Horz)=Queue Head Link Pointer

field in QH DWord 0

Link Pointer (Vert)=Queue Element Link Pointer

field in QH DWord 1

Link Pointer

TD

82801AA and 82801AB Datasheet

5-83

Functional Description

Transfer Queues are based on the following characteristics:

• A QH’s vertical link pointer (Queue Element Link Pointer) references the ‘Top’ queue

member. A QH’s horizontal link pointer (Queue Head Link Pointer) references the “next”

work element in the Frame.

• Each queue member’s link pointer references the next element within the queue.

In the simplest model, the ICH follows vertical link point to a queue element, then executes the

element. If the completion status of the TD satisfies the advance criteria as shown in Table 5-63,

the ICH advances the queue by writing the just-executed TD’s link pointer back into the QH’s

Queue Element link pointer. The next time the queue head is traversed, the next queue element will

be the Top element.

The traversal has two options: Breadth first, or Depth first. A flag bit in each TD (Vf - Vertical

Traversal Flag) controls whether traversal is Breadth or Depth first. The default mode of traversal

is Breadth-First. For Breadth-First, the ICH only executes the top element from each queue. The

execution path is shown below:

1. QH (Queue Element Link Pointer)

2. TD

3. Write-Back to QH (Queue Element Link Pointer)

4. QH (Queue Head Link pointer).

Breadth-First is also performed for every transaction execution that fails the advance criteria. This

means that if a queued TD fails, the queue does not advance, and the ICH traverses the QH’s Queue

Head Link Pointer.

In a Depth-first traversal, the top queue element must complete successfully to satisfy theadvance

criteria for the queue. If the ICH is currently processing a queue, and the advance criteria are met,

and the Vf bit is set, the ICH follows the TD’s link pointer to the next schedule work item.

Note that regardless of traversal model, when the advance criteria are met, the successful TD’s link

pointer is written back to the QH’s Queue Element link pointer.

When the ICH encounters a QH, it caches the QH internally, and sets internal state to indicate it is

in a Q-context. It needs this state to update the correct QH (for auto advancement) and also to make

the correct decisions on how to traverse the Frame List.

Restricting the advancement of queues to advancement criteria implements a guaranteed data

delivery stream. A queue is never advanced on an error completion status (even in the event the

error count was exhausted). Table 5-63 lists the general queue advance criteria, which are based on

the execution status of the TD at the ’Top’ of a currently ‘active’ queue.

Table 5-63. Queue Advance Criteria

Function-to-Host (IN)

NULL Error/NAK

Advance Q Retry Q Element

Host-to-Function (OUT)

Non-NULL

NULL

Error/NAK

Retry Q Element

Advance Q

5-84

82801AA and 82801AB Datasheet

Functional Description

Table 5-63 is a decision table illustrating the valid combinations of link pointer bits and the valid

actions taken when advancement criteria for a queued transfer descriptor are met. The column

headings for the link pointer fields are encoded, based on the following list:

TD

QHLP

TDLP

Vf Q T

Q

T

QH

QE

QELP Vf

Q

T

Legends:

QH.LP = Queue Head Link Pointer (or Horizontal Link Pointer)

QE.LP = Queue Element Link Pointer (or Vertical Link Pointer)

TD.LP = TD Link Pointer

QH.Q = Q bit in QH

QH.T = T bit in QH

QE.Q = Q bit in QE

QE.T = T bit in QE

TD. Vf = Vf bit in TD

TD.Q = Q bit in TD

TD. T = T bit in TD

Table 5-64. USB Schedule List Traversal Decision Table

Q

QH.Q QH.T QE.Q QE.T TD.Vf TD.Q TD.T

Context

Description

Not in Queue - execute TD.

Use TD.LP to get next TD

0

-

x

0

x

0

1

Not in Queue - execute TD. End of

Frame

Not in Queue - execute TD.

Use TD.LP to get next (QH+QE).

Set Q Context to 1.

0

1

-

x

1

x

0

x

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with TD.LP.

0

Use QH.LP to get next TD.

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with TD.LP.

Use TD.LP to get next TD.

1

x

0

1

0

1

0

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with TD.LP.

Use TD.LP to get next (QH+QE).

In Queue. Empty queue.

1

0

x

0

x

1

0

x

-

x

-

x

-

Use QH.LP to get next TD

1

In Queue. Use QE.LP to get (QH+QE)

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with TD.LP.

End of Frame

1

x

1

0

x

0

1

0

x

0

x

In Queue. Empty queue. End of Frame

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with TD.LP.

Use QH.LP to get next (QH+QE).

In Queue. Empty queue.

1

0

x

1

x

Use QH.LP to get next (QH+QE)

82801AA and 82801AB Datasheet

5-85

Functional Description

5.15.3

Data Encoding and Bit Stuffing

The USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting packets.

In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in

level. A string of zeros causes the NRZI data to toggle each bit time. A string of ones causes long

periods with no transitions in the data. To ensure adequate signal transitions, bit stuffing is

employed by the transmitting device when sending a packet on the USB. A 0 is inserted after every

six consecutive 1’s in the data stream before the data is NRZI encoded to force a transition in the

NRZI data stream. This gives the receiver logic a data transition at least once every seven bit times

to guarantee the data and clock lock. A waveform of the data encoding is shown in Figure 5-15.

Figure 5-15. USB Data Encoding

CLOCK

Data

Bit Stuffed Data

NRZI Data

Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire transmission. The

data “one” that ends the Sync Pattern is counted as the first one in a sequence. Bit stuffing is always

enforced, without exception. If required by the bit stuffing rules, a zero bit is inserted, even if it is

the last bit before the end-of-packet (EOP) signal.

5.15.4

Bus Protocol

5.15.4.1

Bit Ordering

Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb, through to the

most significant bit (MSb) last.

5.15.4.2

SYNC Field

All packets begin with a synchronization (SYNC) field, which is a coded sequence that generates a

maximum edge transition density. The SYNC field appears on the bus as IDLE followed by the

binary string “KJKJKJKK,” in its NRZI encoding. It is used by the input circuitry to align

incoming data with the local clock and is defined to be eight bits in length. SYNC serves only as a

synchronization mechanism and is not shown in the following packet diagrams. The last two bits in

the SYNC field are a marker that is used to identify the first bit of the PID. All subsequent bits in

the packet must be indexed from this point.

5-86

82801AA and 82801AB Datasheet

Functional Description

5.15.4.3

Packet Field Formats

Field formats for the token, data, and handshake packets are described in the following section. The

effects of NRZI coding and bit stuffing have been removed for the sake of clarity. All packets have

distinct start and end of packet delimiters.

Table 5-65. PID Format

Bit

Data Sent

Bit

Data Sent

0

1

2

3

PID 0

PID 1

PID 2

PID 3

4

5

6

7

NOT(PID 0)

NOT(PID 1)

NOT(PID 2)

NOT(PID 3)

Packet Identifier Field

A packet identifier (PID) immediately follows the SYNC field of every USB packet. A PID

consists of a four bit packet type field followed by a four-bit check field as shown in Table 5-65.

The PID indicates the type of packet and, by inference, the format of the packet and the type of

error detection applied to the packet. The four-bit check field of the PID insures reliable decoding

of the PID so that the remainder of the packet is interpreted correctly. The PID check field is

generated by performing a ones complement of the packet type field.

Any PID received with a failed check field or which decodes to a non-defined value is assumed to

be corrupted and the remainder of the packet is assumed to be corrupted and is ignored by the

receiver. PID types, codes, and descriptions are listed in Table 5-66.

Table 5-66. PID Types

PID Type

PID Name

PID[3:0]

Description

Token

OUT

IN

b0001

b1001

b0101

Address + endpoint number in host -> function transaction

Address + endpoint number in function -> host transaction

Start of frame marker and frame number

SOF

Address + endpoint number in host -> function transaction

for setup to a control endpoint

SETUP

b1101

Data

DATA0

DATA1

ACK

b0011

b1011

b0010

Data packet PID even

Data packet PID odd

Handshake

Receiver accepts error free data packet

Rx device cannot accept data or Tx device cannot send

data

NAK

STALL

PRE

b1010

b1110

b1100

Endpoint is stalled

Host-issued preamble. Enables downstream bus traffic to

low speed devices.

Special

PIDs are divided into four coding groups: token, data, handshake, and special, with the first two

transmitted PID bits (PID[1:0]) indicating which group. This accounts for the distribution of PID

codes.

82801AA and 82801AB Datasheet

5-87

Functional Description

5.15.4.4

Address Fields

Function endpoints are addressed using two fields: the function address field and the endpoint

field.

Table 5-67. Address Field

Bit

Data Sent

Bit

Data Sent

0

1

2

3

ADDR 0

ADDR 1

ADDR 2

ADDR 3

4

5

6

ADDR 4

ADDR 5

ADDR 6

Address Field

The function address (ADDR) field specifies the function, via its address, that is either the source

or destination of a data packet, depending on the value of the token PID. As shown in Table 5-67, a

total of 128 addresses are specified as ADDR[6:0]. The ADDR field is specified for IN, SETUP,

and OUT tokens.

Endpoint Field

An additional four-bit endpoint (ENDP) field, shown in Table 5-68, permits more flexible

addressing of functions in which more than one sub-channel is required. Endpoint numbers are

function specific. The endpoint field is defined for IN, SETUP, and OUT token PIDs only.

Table 5-68. Endpoint Field

Bit

Data Sent

0

1

2

3

ENDP 0

ENDP 1

ENDP 2

ENDP 3

5.15.4.5

Frame Number Field

The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The

frame number field rolls over upon reaching its maximum value of x7FF, and is sent only for SOF

tokens at the start of each frame.

5.15.4.6

5.15.4.7

Data Field

The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits

within each byte are shifted out LSB first.

Cyclic Redundancy Check (CRC)

CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields

are considered to be protected fields. The PID is not included in the CRC check of a packet

containing CRC. All CRCs are generated over their respective fields in the transmitter before bit

stuffing is performed. Similarly, CRCs are decoded in the receiver after stuffed bits have been

removed. Token and data packet CRCs provide 100% coverage for all single and double bit errors.

A failed CRC is considered to indicate that one or more of the protected fields is corrupted and

causes the receiver to ignore those fields, and, in most cases, the entire packet.

5-88

82801AA and 82801AB Datasheet

Functional Description

5.15.5

Packet Formats

5.15.5.1

Token Packets

Table 5-69 shows the field formats for a token packet. A token consists of a PID, specifying either

IN, OUT, or SETUP packet type, and ADDR and ENDP fields. For OUT and SETUP transactions,

the address and endpoint fields uniquely identify the endpoint that receives the subsequent data

packet. For IN transactions, these fields uniquely identify which endpoint should transmit a data

packet. Only the ICH can issue token packets. IN PIDs define a data transaction from a function to

the ICH. OUT and SETUP PIDs define data transactions from the ICH to a function.

Token packets have a five-bit CRC which covers the address and endpoint fields as shown above.

The CRC does not cover the PID, which has its own check field. Token and SOF packets are

delimited by an EOP after three bytes of packet field data. If a packet decodes as an otherwise valid

token or SOF but does not terminate with an EOP after three bytes, it must be considered invalid

and ignored by the receiver.

Table 5-69. Token Format

Packet

Width

PID

8 bits

7 bits

4 bits

5 bits

ADDR

ENDP

CRC5

5.15.5.2

Start of Frame Packets

Table 5-70 shows a start of frame (SOF) packet. SOF packets are issued by the host at a nominal

rate of once every 1.00 ms 0.05. SOF packets consist of a PID indicating packet type followed by

an 11-bit frame number field.

The SOF token comprises the token-only transaction that distributes a start of frame marker and

accompanying frame number at precisely timed intervals corresponding to the start of each frame.

All full speed functions, including hubs, must receive and decode the SOF packet. The SOF token

does not cause any receiving function to generate a return packet; therefore, SOF delivery to any

given function cannot be guaranteed. The SOF packet delivers two pieces of timing information. A

function is informed that a start of frame has occurred when it detects the SOF PID. Frame timing

sensitive functions, which do not need to keep track of frame number, need only decode the SOF

PID; they can ignore the frame number and its CRC. If a function needs to track frame number, it

must comprehend both the PID and the time stamp.

Table 5-70. SOF Packet

Packet

Width

PID

Frame Number

CRC5

8 bits

11 bits

5 bits

82801AA and 82801AB Datasheet

5-89

Functional Description

5.15.5.3

Data Packets

A data packet consists of a PID, a data field, and a CRC as shown in Table 5-71. There are two

types of data packets, identified by differing PIDs: DATA0 and DATA1. Two data packet PIDs are

defined to support data toggle synchronization.

Data must always be sent in integral numbers of bytes. The data CRC is computed over only the

data field in the packet and does not include the PID, which has its own check field.

Table 5-71. Data Packet Format

Packet

Width

PID

8 bits

0-1023 bytes

16 bits

DATA

CRC16

5.15.5.4

Handshake Packets

Handshake packets consist of only a PID. Handshake packets are used to report the status of a data

transaction and can return values indicating successful reception of data, flow control, and stall

conditions. Only transaction types that support flow control can return handshakes. Handshakes are

always returned in the handshake phase of a transaction and may be returned, instead of data, in the

data phase. Handshake packets are delimited by an EOP after one byte of packet field. If a packet is

decoded as an otherwise valid handshake but does not terminate with an EOP after one byte, it

must be considered invalid and ignored by the receiver.

There are three types of handshake packets:

• ACK indicates that the data packet was received without bit stuff or CRC errors over the data

field and that the data PID was received correctly. An ACK handshake is applicable only in

transactions in which data has been transmitted and where a handshake is expected. ACK can

be returned by the host for IN transactions and by a function for OUT transactions.

• NAK indicates that a function was unable to accept data from the host (OUT) or that a

function has no data to transmit to the host (IN). NAK can only be returned by functions in the

data phase of IN transactions or the handshake phase of OUT transactions. The host can never

issue a NAK. NAK is used for flow control purposes to indicate that a function is temporarily

unable to transmit or receive data, but will eventually be able to do so without need of host

intervention. NAK is also used by interrupt endpoints to indicate that no interrupt is pending.

• STALL is returned by a function in response to an IN token or after the data phase of an OUT.

STALL indicates that a function is unable to transmit or receive data, and that the condition

requires host intervention to remove the stall. Once a function’s endpoint is stalled, the

function must continue returning STALL until the condition causing the stall has been cleared

through host intervention. The host is not permitted to return a STALL under any condition.

5.15.5.5

Handshake Responses

IN Transaction

A function may respond to an IN transaction with a STALL or NAK. If the token received was

corrupted, the function issues no response. If the function can transmit data, it issues the data

packet. The ICH, as the USB host, can return only one type of handshake on an IN transaction, an

ACK. If it receives a corrupted data, or cannot accept data due to a condition such as an internal

buffer overrun, it discards the data and issues no response.

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82801AA and 82801AB Datasheet

Functional Description

OUT Transaction

A function may respond to an OUT transaction with a STALL, ACK, or NAK. If the transaction

contained corrupted data, it issues no response.

SETUP Transaction

Setup defines a special type of host to function data transaction which permits the host to initialize

an endpoint’s synchronization bits to those of the host. Upon receiving a Setup transaction, a

function must accept the data. Setup transactions cannot be STALLed or NAKed and the receiving

function must accept the Setup transfer’s data. If a non-control endpoint receives a SETUP PID, it

must ignore the transaction and return no response.

5.15.6

USB Interrupts

There are two general groups of USB interrupt sources, those resulting from execution of

transactions in the schedule, and those resulting from an ICH operation error. All transaction-based

sources can be masked by software through the ICH’s Interrupt Enable register. Additionally,

individual transfer descriptors can be marked to generate an interrupt on completion.

When the ICH drives an interrupt for USB, it drives the PIRQD# pin active for interrupts occurring

due to ports 0 and 1 until all sources of the interrupt are cleared.

5.15.6.1

Transaction Based Interrupts

These interrupts are not signaled until after the status for the last complete transaction in the frame

has been written back to host memory. This guarantees that software can safely process through

(Frame List Current Index -1) when it is servicing an interrupt.

CRC Error / Time-out

A CRC/Time-out error occurs when a packet transmitted from the ICH to a USB device or a packet

transmitted from a USB device to the ICH generates a CRC error. The ICH is informed of this

event by a time-out from the USB device or by the ICH’s CRC checker generating an error on

reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not

respond to a transaction phase within 19 bit times of an EOP. Either of these conditions cause the

C_ERR field of the TD to decrement.

When the C_ERR field decrements to zero, the following occurs:

• The Active bit in the TD is cleared

• The Stalled bit in the TD is set

• The CRC/Time-out bit in the TD is set.

• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.

If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt is

signaled to the system.

82801AA and 82801AB Datasheet

5-91

Functional Description

Interrupt on Completion

Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The

completion of the transaction associated with that block causes the USB Interrupt bit in the HC

Status Register to be set at the end of the frame in which the transfer completed. When a TD is

encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of

the frame if the active bit in the TD is set to 0 (even if it was set to zero when initially read).

If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware

interrupt is signaled to the system. The USB Interrupt bit in the HC status register is set either when

the TD completes successfully or because of errors. If the completion is because of errors, the USB

Error bit in the HC status register is also set.

Short Packet Detect

A transfer set is a collection of data which requires more than 1 USB transaction to completely

move the data across the USB. An example might be a large print file which requires numerous

TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than

the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion

of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in

a TD indicates to the HC to set the USB Interrupt bit in the HC status register at the end of the

frame in which this event occurs. This feature streamlines the processing of input on these transfer

types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware

interrupt is signaled to the system at the end of the frame where the event occurred.

Serial Bus Babble

When a device transmits on the USB for a time greater than its assigned Max Length, it is said to

be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active

bit in the TD being cleared to 0 and the Stalled and Babble bits being set to one. The C_ERR field

is not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at

the end of the frame. A hardware interrupt is signaled to the system.

If an EOF babble was caused by the ICH (due to incorrect schedule for instance), the ICH forces a

bit stuff error followed by an EOP and the start of the next frame.

Stalled

This event indicates that a device/endpoint returned a STALL handshake during a transaction or

that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is

cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is

signaled to the system.

Data Buffer Error

This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred

for this transaction. This would generally be caused by the ICH not being able to access required

data buffers in memory within necessary latency requirements. Either of these conditions cause the

C_ERR field of the TD to be decremented.

When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is set, the USB

Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware

interrupt is signaled to the system.

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82801AA and 82801AB Datasheet

Functional Description

Bit Stuff Error

A bit stuff error results from the detection of a sequence of more that 6 ones in a row within the

incoming data stream. This causes the C_ERR field of the TD to be decremented. When the

C_ERR field decrements to zero, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1,

the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame, and a

hardware interrupt is signaled to the system.

5.15.6.2

Non-Transaction Based Interrupts

If an ICH process error or system error occur, the ICH halts and immediately issues a hardware

interrupt to the system.

Resume Received

This event indicates that the ICH received a RESUME signal from a device on the USB bus during

a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware interrupt is

signaled to the system allowing the USB to be brought out of the suspend state and returned to

normal operation.

ICH Process Error

The HC monitors certain critical fields during operation to ensure that it does not process corrupted

data structures. These include checking for a valid PID and verifying that the MaxLength field is

less than 1280. If it detects a condition that would indicate that it is processing corrupted data

structures, it immediately halts processing, sets the HC Process Error bit in the HC Status register,

and signals a hardware interrupt to the system.

This interrupt cannot be disabled through the Interrupt Enable register.

Host System Error

The ICH sets this bit to 1 when a PCI Parity error, PCI Master Abort, or PCI Target Abort occur.

When this error occurs, the ICH clears the Run/Stop bit in the Command register to prevent further

execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt Enable

register.

82801AA and 82801AB Datasheet

5-93

Functional Description

5.15.7

USB Power Management

The Host Controller can be put into a suspended state and its power can be removed. This requires

that certain bits of information are retained in the resume power plane of the ICH so that a device

on a port may wake the system. Such a device may be a fax-modem, which wakes up the machine

to receive a fax or take a voice message. The following bits in I/O space are to be maintained when

the ICH enters a low power state:

Table 5-72. Bits to be Maintained in Low Power States

Register

Offset

Bit

Description

Command

Status

00h

02h

3

2

Enter Global Suspend Mode (EGSM)

Resume Detect

Port Status and Control

10h & 12h

2

Port Enabled/Disabled

Resume Detect

6

8

Low Speed Device Attached

Suspend

12

When the ICH detects a resume event on any of its ports, it sets the USB_STS bit in ACPI space. If

USB is enabled as a wake/break event, the system wakes up and an SCI is generated.

5.15.8

USB Legacy Keyboard Operation

When a USB keyboard is plugged into the system and a standard keyboard is not plugged in, the

system may not boot, and DOS legacy software will not run, because the keyboard will not be

identified. The ICH implements a series of trapping operations which will snoop accesses that go to

the keyboard controller and put the expected data from the USB keyboard into the keyboard

controller.

Note: The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the

LPC bus.

This legacy operation is performed through SMM space.

Figure 5-16 shows the Enable and Status path. The latched SMI source (60R, 60W, 64R, 64W) is

available in the Status Register. Because the enable is after the latch, it is possible to check for

other events that didn't necessarily cause an SMI. It is the software's responsibility to logically

AND the value with the appropriate enable bits.

Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes

active) to ensure that the processor does not complete the cycle before the SMI is observed.

The logic will also need to block the accesses to the 8042. If there is an external 8042, this is

accomplished by not activating the 8042 CS. This is done by logically ANDing the 4 enables

(60R, 60W, 64R, 64W) with the 4 types of accesses to determine if 8042CS should go active. An

additional term is required for the “Pass-through” case. The state table for the diagram is shown in

Table 5-73.

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82801AA and 82801AB Datasheet

Functional Description

Figure 5-16. USB Legacy Keyboard Flow Diagram

82801AA and 82801AB Datasheet

5-95

Functional Description

Table 5-73. USB Legacy Keyboard State Transitions

Current State

Action

Data Value Next State

Comment

Standard D1 command. Cycle passed through to

8042. SMI# does not go active. PSTATE goes to 1.

IDLE

64h / Write

D1h

Not D1h

N/A

GateState1

IDLE

USB_LEGKEY[bit 3] determines if cycle passed

through to 8042 and if SMI# is generated.

IDLE

64h / Write

64h / Read

USB_LEGKEY[bit 2] determines if cycle passed

through to 8042 and if SMI# is generated.

IDLE

USB_LEGKEY[bit 1] determines if cycle passed

through to 8042 and if SMI# is generated.

60h / Write Don't Care

IDLE

USB_LEGKEY[bit 0] determines if cycle passed

through to 8042 and if SMI# is generated.

60h / Read

60h / Write

N/A

IDLE

Cycle passed through to 8042, even if trap enabled

in USB_LEGKEY[bit 1]. No SMI# is generated.

PSTATE remains 1. If data value is not DFh or

DDh, the 8042 may chose to ignore it.

GateState1

XXh

GateState2

GateState1

ILDE

Cycle passed through to 8042, even if trap enabled

via USB_LEGKEY[bit 3]. No SMI# generated.

PSTATE remains 1. Stay in GateState1 because

this is part of the double-trigger sequence.

64h / Write

D1h

USB_LEGKEY[bit 3] determines if cycle passed

through to 8042 and if SMI# generated. PSTATE

goes to 0. If USB_LEGKEY[bit 7] is set, then SMI#

should be generated.

Not D1h

This is an invalid sequence. USB_LEGKEY[bit 0]

determines if cycle passed through to 8042 and if

SMI# generated. PSTATE goes to 0. If

USB_LEGKEY[bit 7] is set, then SMI# should be

generated.

GateState1

60h / Read

N/A

IDLE

Just stay in same state. Generate an SMI# if

GateState1

GateState2

64h / Read

64 / Write

N/A

FFh

GateState1 enabled in USB_LEGKEY[bit 2]. PSTATE remains

1.

Standard end of sequence. Cycle passed through

IDLE

to 8042. PSTATE goes to 0. USB_LEGKEY[bit 7]

determines if SMI# should be generated.

Improper end of sequence. USB_LEGKEY[bit 3]

determines if cycle passed through to 8042 and if

SMI# generated. PSTATE goes to 0. If

USB_LEGKEY[bit 7] is set, then SMI# should be

generated.

GateState2

64h / Write

64h / Read

60h / Write

Not FFh

N/A

IDLE

Just stay in same state. Generate an SMI# if

GateState2 enabled in USB_LEGKEY[bit 2]. PSTATE remains

1.

Improper end of sequence. USB_LEGKEY[bit 1]

determines if cycle passed through to 8042 and if

SMI# generated. PSTATE goes to 0. If

USB_LEGKEY[bit 7] is set, then SMI# should be

generated.

XXh

IDLE

Improper end of sequence. USB_LEGKEY[bit 0]

determines if cycle passed through to 8042 and if

SMI# generated. PSTATE goes to 0. If

USB_LEGKEY[bit 7] is set, then SMI# should be

generated.

GateState2

60h / Read

N/A

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Functional Description

5.16

SMBus Controller Functional Description (D31:F3)

The ICH provides an SMBus host controller including an SMBus Master interface. The host

controller provides a mechanism for the processor to initiate communications with SMBus

peripherals (slaves). The ICH also can operate in a mode in which it can communicate with I²C

compatible devices.

The ICH SMBus logic exists in Device 31:Function 3 PCI configuration space, and consists of a

transmit data path and host controller. The transmit data path provides the data flow logic needed to

implement the seven different SMBus command protocols and is controlled by the host controller.

The ICH SMBus controller logic is clocked by RTC clock.

The programming model of the host controller is combined into two portions: a PCI configuration

portion, and a system I/O mapped portion. All static configuration (e.g., the I/O base address) is via

the PCI configuration space. Real-time programming of the Host interface is accomplished in

system I/O space.

5.16.1

Host Controller

The SMBus Host Controller is used to send commands to other SMBus slave devices. Software

sets up the host controller with an address, command, and, for writes, data, and then instructs the

controller to start. When the controller has finished transmitting data on writes, or receiving data on

reads, it generates an SMI# or interrupt, if enabled.

The host controller supports 7 command protocols of the SMBus interface (see System

Management Bus Specifications, Rev 1.0): Quick Command, Send Byte, Receive Byte, Write

Byte/Word, Read Byte/Word, Process Call, and Block Read/Write.

The SMBus Host Controller requires that the various data and command fields be setup for the type

of command to be sent. When software sets the START bit, the SMBus Host Controller performs

the requested transaction, and interrupts the processor (or generate an SMI#) when the transaction

is completed. Once a START command has been issued, the values of the “active registers” (Host

Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read

until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any

register values needed for computation purposes should be saved prior to issuing of a new

command, as the SMBus Host Controller will update all registers while completing the new

command.

5.16.1.1

Command Protocols

In all of the following commands, the Host Status Register (offset 00h) is used to determine the

progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the

command completes successfully and the INTREN bit is set to 1 in the Host Control Register, the

INTR bit is set in the Host Status Register. If the device does not respond with an acknowledge,

and the transaction times out, the DEV_ERR bit is set to 1. If software sets the KILL bit to 1 in the

Host Control Register while the command is running, the transaction stops and the FAILED bit is

set.

82801AA and 82801AB Datasheet

5-97

Functional Description

Quick Command

When programmed for a Quick Command, the Transmit Slave Address Register is sent. The format

of the protocol is shown in Table 5-74.

Table 5-74. Quick Protocol

Bit

Description

1

2:8

9

Start Condition

Slave Address - 7 bits

Read / Write Direction

Acknowledge from slave

Stop

10

11

Send Byte / Receive Byte

For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent

For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is

stored in the DATA0 register.

The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. The

format of the protocol is shown in Table 5-75.

Table 5-75. Send / Receive Byte Protocol

Send Byte Protocol

Description

Receive Byte Protocol

Description

Bit

1

2:8

9

Start

1

2:8

9

Start

Slave Address - 7 bits

Write

Slave Address - 7 bits

Read

10

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Stop

10

Acknowledge from slave

Data byte from slave

NOT Acknowledge

Stop

11:18

19

11:18

19

20

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82801AA and 82801AB Datasheet

Functional Description

Write Byte/Word

The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data

to be written. When programmed for a write byte/word command, the Transmit Slave Address,

Device Command, and Data0 Registers are sent. In addition, the Data1 Register is sent on a write

word command. The format of the protocol is shown in Table 5-76.

Table 5-76. Write Byte/Word Protocol

Write Byte Protocol

Description

Write Word Protocol

Description

Bit

1

2-8

9

Start

1

2:8

9

Start

Slave Address - 7 bits

Write

Slave Address - 7 bits

Write

10

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Data Byte - 8 bits

Acknowledge from Slave

Stop

10

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Data Byte Low - 8 bits

Acknowledge from Slave

Data Byte High - 8 bits

Acknowledge from slave

Stop