82801BA [INTEL]

Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile; 英特尔82801BA I / O控制器中枢2 （ ICH2 ）和英特尔82801BAM I / O控制器中枢2手机


型号：	82801BA
厂家：	INTEL
描述：	Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile 英特尔82801BA I / O控制器中枢2 （ ICH2 ）和英特尔82801BAM I / O控制器中枢2手机控制器手机
文件：	总498页 (文件大小：5264K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Intel 82801BA I/O Controller

Hub 2 (ICH2) and Intel 82801BAM

I/O Controller Hub 2 Mobile

(ICH2-M)

Datasheet

October 2000

Order Number: 290687-002

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

The Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 (ICH2-M) may contain design defects or errors known as

errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

I²C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I²C bus/protocol and was developed by Intel.

Implementations of the I²C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and

North American Philips Corporation.

Alert on LAN and Wake on LAN are results of the IBM/Intel Advanced Manageability Alliance and are trademarks of IBM Corporation.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:

calling 1-800-548-4725 or

by visiting Intel's website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Intel 82801BA/M ICH2/ICH2-M Features

PCI Bus I/F

— Supports PCI at 33 MHz

Power Management Logic

— ACPI 1.0 compliant

— Supports PCI Rev 2.2 Specification

— 133 MByte/sec maximum throughput

— Supports up to 6 master devices on PCI

— One PCI REQ/GNT pair can be given higher

arbitration priority (intended for external

1394 host controller)

Integrated LAN Controller

— WfM 2.0 Compliant

— Interface to discrete LAN Connect

component

— ACPI-defined power states

- C1–C2, S3–S5 (82801BA ICH2)

- C1–C3, S1, S3–S5 (82801BAM ICH2-M)

— Support for “Intel^®SpeedStep™

technology” processor power control

(82801BAM ICH2-M)

— PCI CLKRUN# support

(82801BAM ICH2-M)

— ACPI Power Management Timer

— 10/100 Mbit/sec Ethernet support

— 1 Mbit/sec HomePNA* support

Integrated IDE Controller

— PCI PME# support

— SMI# generation

— Independent timing of up to 4 drives

— Ultra ATA/100/66/33, BMIDE and PIO

modes

— All registers readable/restorable for proper

resume from 0V suspend states

— Support for APM-based legacy power

management for non-ACPI implementations

— Read transfers up to 100MB/s, Writes to

89 MB/s

External Glue Integration

— Separate IDE connections for Primary and

Secondary cables

— Implements Write Ping-Pong Buffer for

— Integrated Pull-up, Pull-down and Series

Termination resistors on IDE and processor

interface

faster write performance

Enhanced Hub I/F buffers improve routing

flexibility (Not available with all Memory

Controller Hubs)

— Tri-state modes to enable mobile swap bay

(82801BAM ICH2-M)

Firmware Hub (FWH) I/F supports BIOS

memory size up to 8 MBs

Low Pin count (LPC) I/F

— Allows connection of legacy ISA and X-Bus

devices such as Super I/O

— Supports two Master/DMA devices.

USB

— 2 UHCI Host Controllers with a total of

4 ports

— USB 1.1 compliant

— Supports wake-up from sleeping states

S1–S4

— Supports legacy Keyboard/Mouse software

Enhanced DMA Controller

AC'97 Link for Audio and Telephony CODECs

— AC’97 2.1 compliant

— Independent bus master logic for 5 channels

(PCM In/Out, Mic Input, Modem In/Out)

— Separate independent PCI functions for

Audio and Modem

— Support for up to six channels of PCM audio

output (full AC3 decode)

— Supports wake-up events

— Two cascaded 8237 DMA controllers

— PCI DMA: Supports PC/PCI — Includes

two PC/PCI REQ#/GNT# pairs

— Supports LPC DMA

— Supports DMA Collection Buffer to provide

Type-F DMA performance for all DMA

channels

Real-Time Clock

— 256-byte battery-backed CMOS RAM

— Hardware implementation to indicate century

rollover

Interrupt Controller

— Support up to 8 PCI interrupt pins

— Supports PCI 2.2 Message-Based Interrupts

— Two cascaded 82C59

System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang

— Timers to detect improper processor reset

— Integrated processor frequency strap logic

— Integrated I/O APIC capability

— 15 interrupts supported in 8259 mode, 24

supported in I/O APIC mode

— Supports Serial Interrupt Protocol

— Supports Front-Side Bus interrupt delivery

1.8 V operation with 3.3 V I/O

— 5V tolerant buffers on IDE, PCI, USB Over-

current and Legacy signals

SM Bus

— Host interface allows processor to

communicate via SM Bus

— Slave interface allows an external

Microcontroller to access system resources

— Compatible with most 2-Wire components

that are also I²C compatible

GPIO

— TTL, Open-Drain, Inversion

Timers Based on 82C54

— System timer, Refresh request, Speaker tone

output

Supports ISA bus via external PCI-ISA Bridge

360-pin EBGA package

Shading,as is shown here, indicates differences between the two components.

The Intel^®82801BA ICH2 and 82801BAM ICH2-M may contain design defects or errors known as errata which may cause the

products to deviate from published specifications. Current characterized errata are available on request.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

iii

Intel^®82801BA (ICH2) and 82801BAM (ICH2-M) Simplified Block Diagram

AD[31:0]

C/BE[3:0]#

DEVSEL#

PDCS1#

SDCS1#

PDCS3#

SDCS3#

PDA[2:0]

SDA[2:0]

PDD[15:0]

SDD[15:0]

PDDREQ

SDDREQ

PDDACK#

SDDACK#

PDIOR#

FRAME#

IRDY#

TRDY#

STOP#

PAR

IDE

Interface

PERR#

REQ[0:4]#

REQ5#/REQB#/GPIO1

REQA#/GPIO0

GNT[0:4]#

PCI

Interface

SDIOR#

GNT5#/GNTB#/GPIO17

GNTA#/GPIO16

PCICLK

PDIOW#

SDIOW#

PIORDY

SIORDY

PCIRST#

PLOCK#

SERR#

THRM#

SLP_S3

SLP_S5#

PME#

(ICH2-M)CLKRUN#

PWROK

PWRBTN#

RI#

RSMRST#

A20M#

CPUSLP#

FERR#

SUS_STAT#/LPCPD#

SUSCLK

RSM_PWROK (ICH2) or LAN_PWROK (ICH2-M)

IGNNE#

INIT#

INTR

Power

Mgnt.

Processor

Interface

VRMPWRGD

/ VGATE (ICH2-M)

NMI

SLP_S1# (ICH2-M)

SMI#

C3_STAT#/GPIO[21] (ICH2-M)

AGPBUSY# (ICH2-M)

STP_PCI# (ICH2-M)

STP_CPU# (ICH2-M)

BATLOW# (ICH2-M)

CPUPERF# (ICH2-M)

SSMUXSEL (ICH2-M)

STPCLK#

RCIN#

A20GATE

CPUPWRGD

SERIRQ

PIRQ[A:D]#

PIRQ[H:E]/GPIO[5:2]

IRQ[14:15]

Interrupt

AC_RST#

AC_SYNC

AC_BIT_CLK

AC_SDOUT

AC_SDIN0

AC_SDIN1

APICCLK

APICD[1:0]

AC'97

Link

USBP1P

USBP1N

USBP0P

USBP0N

OC[3:0]#

USB

HL11:0]

Hub

Interface

HL_STB

HL_STB#

HLCOMP

RTCX1

RTCX2

RTC

Firmware

Hub

FWH[3:0]/LAD[3:0]

FWH[4]/LFRAME#

CLK14

CLK48

CLK66

Clocks

LAD[3:0]/FWH[4]

LFRAME#/FWH[4]

LDRQ[0:1]#

LPC

Interface

SPKR

RTCRST#

(ICH2) TP0

FS0

Misc.

Signals

SMBDATA

SMBus

Interface

SMBCLK

SMBALERT#/GPIO[11]

GPIO[13:11,8:6,4:3,1:0]

GPIO[23:16]

General

Purpose

I/O

INTRUDER#

SMLINK[1:0]

System

Mgnt.

GPIO[28:24]

EE_SHCLK

EE_DIN

LAN_CLK

System

Mgnt.

LAN_RXD[2:0]

LAN_TXD[2:0]

LAN_RSTSYNC

System

Mgnt.

EE_DOUT

EE_CS

Note:

1. The GPIO signals listed above represent the GPIO signals for the 82801BA ICH2. Some of

these signals are not implemented in the 82801BAM ICH2-M. See Signal Description Chapter for details.

blk_ich2-ich2m

82801BA ICH2 and 82801BAM ICH2-M Datasheet

System Configuration

Processor

Main

Memory

Graphics

Controller

Host

Controller

Hub Interface

PCI Slots

SMBus

Device(s)

PCI Bus

AC'97 Codec(s)

(optional)

AC'97 2.1

PCI Agent

ISA Bridge

(optional)

I/O Controller Hub 2

82801BA (ICH2)

and

82801BAM (ICH2-M)

ATA/100/66/33

4 IDE Drives

Moon2

4xUSB

GPIO

Docking Bridge

(optional) (ICH2-M)

LPC I/F

LAN

Controller

Super I/O

(required)

FWH

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Contents

Introduction................................................................................................................1-1

1.1

1.2

About this Document ....................................................................................1-1

Overview.......................................................................................................1-3

Signal Description......................................................................................................2-1

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Hub Interface to Host Controller ...................................................................2-1

Link to LAN Connect.....................................................................................2-1

EEPROM Interface .......................................................................................2-2

Firmware Hub Interface ................................................................................2-2

PCI Interface.................................................................................................2-2

IDE Interface.................................................................................................2-5

LPC Interface................................................................................................2-6

Interrupt Interface .........................................................................................2-6

USB Interface ...............................................................................................2-7

Power Management Interface.......................................................................2-7

Processor Interface.......................................................................................2-9

SMBus Interface .........................................................................................2-10

System Management Interface...................................................................2-10

Real Time Clock Interface ..........................................................................2-11

Other Clocks...............................................................................................2-11

Miscellaneous Signals ................................................................................2-11

AC’97 Link ..................................................................................................2-12

General Purpose I/O...................................................................................2-12

Power and Ground......................................................................................2-13

Pin Straps ...................................................................................................2-14

2.20.1 Functional Straps...........................................................................2-14

2.20.2 Test Signals...................................................................................2-15

2.20.2.1 Test Mode Selection.......................................................2-15

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

2.17

2.18

2.19

2.20

2.20.2.2 Test Straps (82801BA ICH2 only)..................................2-15

2.20.3 External RTC Circuitry...................................................................2-16

2.20.4 V5REF / Vcc3_3 Sequencing Requirements.................................2-16

Power Planes and Pin States ....................................................................................3-1

3.1

3.2

3.3

3.4

3.5

Power Planes................................................................................................3-1

Integrated Pull-Ups and Pull-Downs.............................................................3-1

IDE Integrated Series Termination Resistors ...............................................3-2

Output and I/O Signals Planes and States ...................................................3-2

Power Planes for Input Signals.....................................................................3-6

System Clock Domains..............................................................................................4-1

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description ...............................................................................................5-1

5.1

Hub Interface to PCI Bridge (D30:F0)...........................................................5-1

5.1.1 PCI Bus Interface.............................................................................5-1

5.1.2 PCI-to-PCI Bridge Model .................................................................5-2

5.1.3 IDSEL to Device Number Mapping..................................................5-2

5.1.4 SERR# Functionality........................................................................5-2

5.1.5 Parity Error Detection.......................................................................5-4

5.1.6 Standard PCI Bus Configuration Mechanism ..................................5-5

5.1.7 PCI Dual Address Cycle (DAC) Support

(82801BA ICH2 only).......................................................................5-6

LAN Controller (B1:D8:F0)............................................................................5-6

5.2.1 LAN Controller Architectural Overview ............................................5-7

5.2.2 LAN Controller PCI Bus Interface ....................................................5-9

5.2.2.1 Bus Slave Operation.........................................................5-9

5.2.2.2 Bus Master Operation.....................................................5-10

5.2.3 CLOCKRUN# Signal (82801BAM ICH2-M only)............................5-13

5.2.3.1 PCI Power Management ................................................5-13

5.2.3.2 PCI Reset Signal ............................................................5-15

5.2.3.3 Wake-up Events .............................................................5-15

5.2.3.4 Wake on LAN (Preboot Wake-up)..................................5-16

5.2.4 Serial EEPROM Interface ..............................................................5-17

5.2.5 CSMA/CD Unit...............................................................................5-19

5.2.6 Media Management Interface ........................................................5-20

5.2.7 TCO Functionality ..........................................................................5-20

LPC Bridge (w/ System and Management Functions) (D31:F0).................5-20

5.3.1 LPC Interface.................................................................................5-21

5.3.1.1 LPC Cycle Types............................................................5-21

5.3.1.2 Start Field Definition .......................................................5-22

5.3.1.3 Cycle Type / Direction (CYCTYPE + DIR)......................5-22

5.3.1.4 Size.................................................................................5-22

5.3.1.5 SYNC..............................................................................5-23

5.3.1.6 SYNC Time-out ..............................................................5-23

5.3.1.7 SYNC Error Indication ....................................................5-23

5.3.1.8 LFRAME# Usage............................................................5-24

5.3.1.9 I/O Cycles.......................................................................5-25

5.3.1.10 Bus Master Cycles..........................................................5-25

5.3.1.11 LPC Power Management ...............................................5-25

5.3.1.12 Configuration and ICH2 Implications..............................5-25

DMA Operation (D31:F0)............................................................................5-26

5.4.1 Channel Priority .............................................................................5-26

5.4.2 Address Compatibility Mode ..........................................................5-27

5.4.3 Summary of DMA Transfer Sizes ..................................................5-27

5.4.4 Autoinitialize...................................................................................5-28

5.4.5 Software Commands .....................................................................5-29

PCI DMA.....................................................................................................5-30

5.5.1 PCI DMA Expansion Protocol........................................................5-30

5.5.2 PCI DMA Expansion Cycles ..........................................................5-32

5.5.3 DMA Addresses.............................................................................5-32

5.5.4 DMA Data Generation....................................................................5-32

5.5.5 DMA Byte Enable Generation........................................................5-33

5.5.6 DMA Cycle Termination.................................................................5-33

5.5.7 LPC DMA.......................................................................................5-33

5.2

5.3

5.4

5.5

82801BA ICH2 and 82801BAM ICH2-M Datasheet

vii

5.5.8 Asserting DMA Requests...............................................................5-33

5.5.9 Abandoning DMA Requests ..........................................................5-34

5.5.10 General Flow of DMA Transfers ....................................................5-35

5.5.11 Terminal Count ..............................................................................5-35

5.5.12 Verify Mode....................................................................................5-35

5.5.13 DMA Request Deassertion ............................................................5-36

5.5.14 SYNC Field / LDRQ# Rules...........................................................5-37

8254 Timers (D31:F0).................................................................................5-38

5.6.1 Timer Programming.......................................................................5-38

5.6.2 Reading from the Interval Timer ....................................................5-39

8259 Interrupt Controllers (PIC) (D31:F0) ..................................................5-41

5.7.1 Interrupt Handling ..........................................................................5-42

5.7.1.1 Generating Interrupts .....................................................5-42

5.7.1.2 Acknowledging Interrupts...............................................5-42

5.7.1.3 Hardware/Software Interrupt Sequence.........................5-43

5.7.2 Initialization Command Words (ICWx)...........................................5-43

5.7.3 Operation Command Words (OCW)..............................................5-44

5.7.4 Modes of Operation .......................................................................5-45

5.7.5 Masking Interrupts .........................................................................5-47

5.7.6 Steering PCI Interrupts ..................................................................5-47

Advanced Interrupt Controller (APIC) (D31:F0)..........................................5-48

5.8.1 Interrupt Handling ..........................................................................5-48

5.8.2 Interrupt Mapping...........................................................................5-49

5.8.3 APIC Bus Functional Description...................................................5-50

5.8.3.1 Physical Characteristics of APIC....................................5-50

5.8.3.2 APIC Bus Arbitration ......................................................5-50

5.8.3.3 Bus Message Formats ...................................................5-51

5.8.4 PCI Message-Based Interrupts......................................................5-56

5.8.4.1 Theory of Operation .......................................................5-56

5.8.4.2 Registers and Bits Associated with PCI Interrupt

5.6

5.7

5.8

Delivery ..........................................................................5-56

5.8.5 Front-Side Interrupt Delivery..........................................................5-57

5.8.5.1 Theory of Operation .......................................................5-57

5.8.5.2 Edge-Triggered Operation..............................................5-57

5.8.5.3 Level-Triggered Operation .............................................5-57

5.8.5.4 Registers Associated with Front-Side Bus Interrupt

Delivery ..........................................................................5-58

5.8.5.5 Interrupt Message Format..............................................5-58

Serial Interrupt (D31:F0).............................................................................5-60

5.9.1 Start Frame....................................................................................5-60

5.9.2 Data Frames..................................................................................5-60

5.9.3 Stop Frame....................................................................................5-61

5.9.4 Specific Interrupts not Supported via SERIRQ..............................5-61

5.9.5 Data Frame Format .......................................................................5-62

Real Time Clock (D31:F0) ..........................................................................5-63

5.10.1 Update Cycles ...............................................................................5-63

5.10.2 Interrupts........................................................................................5-64

5.10.3 Lockable RAM Ranges..................................................................5-64

5.10.4 Century Rollover............................................................................5-64

5.10.5 Clearing Battery-Backed RTC RAM...............................................5-64

5.9

5.10

viii

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5.11

Processor Interface (D31:F0)......................................................................5-66

5.11.1 Processor Interface Signals...........................................................5-66

5.11.1.1 A20M# ............................................................................5-66

5.11.1.2 INIT#...............................................................................5-66

5.11.1.3 FERR#/IGNNE# (Coprocessor Error).............................5-67

5.11.1.4 NMI.................................................................................5-67

5.11.1.5 STPCLK# and CPUSLP# Signals ..................................5-68

5.11.1.6 CPUPWRGOOD Signal..................................................5-68

5.11.2 Dual Processor Issues (82801BA ICH2 only)................................5-68

5.11.2.1 Signal Differences (82801BA ICH2 only) .......................5-68

5.11.2.2 Power Management (82801BA ICH2 only) ....................5-68

5.11.3 Speed Strapping for Processor......................................................5-69

Power Management (D31:F0).....................................................................5-71

5.12.1 ICH2 and System Power States ....................................................5-72

5.12.2 System Power Planes....................................................................5-74

5.12.3 ICH2 Power Planes........................................................................5-74

5.12.4 SMI#/SCI Generation.....................................................................5-74

5.12.5 Dynamic Processor Clock Control .................................................5-77

5.12.5.1 Throttling Using STPCLK# .............................................5-78

5.12.5.2 Transition Rules Among S0/Cx and Throttling States ....5-78

5.12.6 Dynamic PCI Clock Control (82801BAM ICH2-M).........................5-79

5.12.6.1 Conditions for Stopping the PCI Clock

5.12

(82801BAM ICH2-M)......................................................5-79

5.12.6.2 Conditions for Maintaining the PCI Clock

(82801BAM ICH2-M)......................................................5-79

5.12.6.3 Conditions for Stopping the PCI Clock

(82801BAM ICH2-M)......................................................5-79

5.12.6.4 Conditions for Re-Starting the PCI Clock

(82801BAM ICH2-M)......................................................5-80

5.12.6.5 Other Causes of CLKRUN# Going Active

(82801BAM ICH2-M)......................................................5-80

5.12.6.6 LPC Devices and CLKRUN# (82801BAM ICH2-M) .......5-80

5.12.7 Sleep States...................................................................................5-81

5.12.7.1 Initiating Sleep State.......................................................5-81

5.12.7.2 Exiting Sleep States .......................................................5-81

5.12.7.3 Sx–G3–Sx, Handling Power Failures .............................5-83

5.12.8 Thermal Management....................................................................5-84

5.12.8.1 THRM# Signal ................................................................5-84

5.12.8.2 THRM# Initiated Passive Cooling...................................5-84

5.12.8.3 THRM# Override Software Bit........................................5-84

5.12.8.4 Processor-Initiated Passive Cooling

(Via Programmed Duty Cycle on STPCLK#)..................5-85

5.12.8.5 Active Cooling.................................................................5-85

5.12.9 Intel^®SpeedStep™ Technology Protocol

(82801BAM ICH2-M only)..............................................................5-85

5.12.9.1 Intel^®SpeedStep™ Technology Processor

Requirements (82801BAM ICH2-M)...............................5-86

5.12.9.2 Intel^®SpeedStep™ Technology States

(82801BAM ICH2-M)......................................................5-86

5.12.9.3 Voltage Regulator Interface (82801BAM ICH2-M) .........5-87

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5.12.10 Event Input Signals and Their Usage ............................................5-87

5.12.10.1PWRBTN# — Power Button...........................................5-87

5.12.10.2RI# — Ring Indicate .......................................................5-88

5.12.10.3PME# — PCI Power Management Event.......................5-88

5.12.10.4AGPBUSY# (82801BAM ICH2-M) .................................5-88

5.12.11 Alt Access Mode ............................................................................5-89

5.12.11.1Write Only Registers with Read Paths in

Alternate Access Mode ..................................................5-89

5.12.11.2PIC Reserved Bits..........................................................5-91

5.12.11.3Read Only Registers with Write Paths in

Alternate Access Mode ..................................................5-91

5.12.12 System Power Supplies, Planes, and Signals...............................5-91

5.12.13 Clock Generators...........................................................................5-93

5.12.13.1Clock Control Signals from ICH2-M to Clock

Synthesizer (82801BAM ICH2-M only) ..........................5-93

5.12.14 Legacy Power Management Theory of Operation .........................5-94

5.12.14.1Desktop APM Power Management

(82801BA ICH2 only) .....................................................5-94

5.12.14.2Mobile APM Power Management

(82801BAM ICH2-M only) ..............................................5-94

5.13

System Management (D31:F0)...................................................................5-95

5.13.1 Theory of Operation.......................................................................5-95

5.13.2 Alert on LAN*.................................................................................5-96

General Purpose I/O...................................................................................5-98

IDE Controller (D31:F1)..............................................................................5-99

5.15.1 PIO Transfers ................................................................................5-99

5.15.2 Bus Master Function....................................................................5-101

5.15.3 Ultra ATA/33 Protocol..................................................................5-105

5.15.4 Ultra ATA/66 Protocol..................................................................5-107

5.15.5 Ultra ATA/100 Protocol................................................................5-107

5.15.6 Ultra ATA/33/66/100 Timing ........................................................5-107

5.15.7 Mobile IDE Swap Bay (82801BAM ICH2-M only)........................5-107

USB Controller (Device 31:Functions 2 and 4).........................................5-108

5.16.1 Data Structures in Main memory .................................................5-108

5.16.1.1 Frame List Pointer........................................................5-108

5.16.1.2 Transfer Descriptor (TD) ..............................................5-109

5.16.1.3 Queue Head (QH) ........................................................5-113

5.16.2 Data Transfers To/From Main Memory........................................5-114

5.16.2.1 Executing the Schedule................................................5-114

5.16.2.2 Processing Transfer Descriptors..................................5-114

5.16.2.3 Command Register, Status Register, and TD

5.14

5.15

5.16

Status Bit Interaction ....................................................5-115

5.16.2.4 Transfer Queuing .........................................................5-116

5.16.3 Data Encoding and Bit Stuffing....................................................5-119

5.16.4 Bus Protocol ................................................................................5-120

5.16.4.1 Bit Ordering ..................................................................5-120

5.16.4.2 SYNC Field...................................................................5-120

5.16.4.3 Packet Field Formats ...................................................5-120

5.16.4.4 Address Fields..............................................................5-121

5.16.4.5 Frame Number Field ....................................................5-122

5.16.4.6 Data Field.....................................................................5-122

5.16.4.7 Cyclic Redundancy Check (CRC) ................................5-122

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5.16.5 Packet Formats............................................................................5-123

5.16.5.1 Token Packets..............................................................5-123

5.16.5.2 Start of Frame Packets.................................................5-123

5.16.5.3 Data Packets ................................................................5-124

5.16.5.4 Handshake Packets......................................................5-124

5.16.5.5 Handshake Responses ................................................5-125

5.16.6 USB Interrupts .............................................................................5-125

5.16.6.1 Transaction Based Interrupts .......................................5-125

5.16.6.2 Non-Transaction Based Interrupts................................5-127

5.16.7 USB Power Management ............................................................5-127

5.16.8 USB Legacy Keyboard Operation................................................5-128

SMBus Controller Functional Description (D31:F3)..................................5-130

5.17.1 Host Controller.............................................................................5-130

5.17.1.1 Command Protocols.....................................................5-131

5.17.1.2 I²C Behavior .................................................................5-136

5.17.1.3 Heartbeat for Use With the External LAN Controller ....5-136

5.17.2 Bus Arbitration .............................................................................5-137

5.17.3 Interrupts / SMI# ..........................................................................5-137

5.17.4 SMBALERT#................................................................................5-138

5.17.5 SMBus Slave Interface ................................................................5-138

AC’97 Controller Functional Description

5.17

5.18

5.19

(Audio D31:F5, Modem D31:F6)5-142

5.18.1 AC-link Overview .........................................................................5-143

5.18.2 AC-Link Low Power Mode ...........................................................5-151

5.18.3 AC‘97 Cold Reset ........................................................................5-152

5.18.4 AC‘97 Warm Reset ......................................................................5-152

5.18.5 System Reset...............................................................................5-153

Firmware Hub Interface ............................................................................5-154

5.19.1 Field Definitions ...........................................................................5-154

5.19.2 Protocol........................................................................................5-155

6.1

6.2

6.3

PCI Devices and Functions...........................................................................6-1

PCI Configuration Map..................................................................................6-2

I/O Map .........................................................................................................6-2

6.3.1 Fixed I/O Address Ranges...............................................................6-3

6.3.2 Variable I/O Decode Ranges ...........................................................6-5

Memory Map.................................................................................................6-6

6.4.1 Boot-Block Update Scheme.............................................................6-7

6.4

LAN Controller Registers (B1:D8:F0).........................................................................7-1

7.1

PCI Configuration Registers (B1:D8:F0).......................................................7-1

7.1.1 VID—Vendor ID Register (LAN Controller—B1:D8:F0)...................7-2

7.1.2 DID—Device ID Register (LAN Controller—B1:D8:F0) ...................7-2

7.1.3 PCICMD—PCI Command Register

(LAN Controller—B1:D8:F0) ............................................................7-2

7.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0)...........7-3

7.1.5 REVID—Revision ID Register (LAN Controller—B1:D8:F0)............7-3

7.1.6 SCC—Sub-Class Code Register

(LAN Controller—B1:D8:F0) ............................................................7-4

7.1.7 BCC—Base-Class Code Register

(LAN Controller—B1:D8:F0) ............................................................7-4

7.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0)........7-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7.1.9 PMLT—PCI Master Latency Timer Register

(LAN Controller—B1:D8:F0)............................................................7-4

7.1.10 HEADTYP—Header Type Register

(LAN Controller—B1:D8:F0)............................................................7-5

7.1.11 CSR_MEM_BASE CSR—Memory-Mapped Base Address

7.1.12 CSR_IO_BASE—CSR I/O-Mapped Base Address Register

(LAN Controller—B1:D8:F0)............................................................7-5

7.1.13 SVID—Subsystem Vendor ID (LAN Controller—B1:D8:F0) ............7-6

7.1.14 SID—Subsystem ID (LAN Controller—B1:D8:F0) ...........................7-6

7.1.15 CAP_PTR—Capabilities Pointer (LAN Controller—B1:D8:F0)........7-6

7.1.16 INT_LN—Interrupt Line Register (LAN Controller—B1:D8:F0)........7-7

7.1.17 INT_PN—Interrupt Pin Register (LAN Controller—B1:D8:F0).........7-7

7.1.18 MIN_GNT—Minimum Grant Register

(LAN Controller—B1:D8:F0)............................................................7-7

7.1.19 MAX_LAT—Maximum Latency Register

(LAN Controller—B1:D8:F0)............................................................7-7

7.1.20 CAP_ID—Capability ID Register (LAN Controller—B1:D8:F0)........7-8

7.1.21 NXT_PTR—Next Item Pointer (LAN Controller—B1:D8:F0) ...........7-8

7.1.22 PM_CAP—Power Management Capabilities

(LAN Controller—B1:D8:F0)............................................................7-8

7.1.23 PMCSR—Power Management Control/Status Register

(LAN Controller—B1:D8:F0)............................................................7-9

7.1.24 DATA—Data Register (LAN Controller—B1:D8:F0)........................7-9

LAN Control / Status Registers (CSR)........................................................7-10

7.2.1 System Control Block Status Word Register .................................7-11

7.2.2 System Control Block Command Word Register...........................7-12

7.2.3 System Control Block General Pointer Register............................7-14

7.2.4 PORT Register ..............................................................................7-14

7.2.5 EEPROM Control Register ............................................................7-15

7.2.6 Management Data Interface (MDI) Control Register .....................7-16

7.2.7 Receive DMA Byte Count Register................................................7-16

7.2.8 Early Receive Interrupt Register....................................................7-17

7.2.9 Flow Control Register ....................................................................7-18

7.2.10 Power Management Driver (PMDR) Register................................7-19

7.2.11 General Control Register...............................................................7-19

7.2.12 General Status Register ................................................................7-20

7.2.13 Statistical Counters........................................................................7-20

7.2

Hub Interface to PCI Bridge Registers (D30:F0) .......................................................8-1

8.1

PCI Configuration Registers (D30:F0)..........................................................8-1

8.1.1 VID—Vendor ID Register (HUB-PCI—D30:F0)...............................8-2

8.1.2 DID—Device ID Register (HUB-PCI—D30:F0)................................8-2

8.1.3 CMD—Command Register (HUB-PCI—D30:F0).............................8-3

8.1.4 PD_STS—Primary Device Status Register

(HUB-PCI—D30:F0) ........................................................................8-4

8.1.5 REVID—Revision ID Register (HUB-PCI—D30:F0)........................8-4

8.1.6 SCC—Sub-Class Code Register (HUB-PCI—D30:F0)....................8-5

8.1.7 BCC—Base-Class Code Register (HUB-PCI—D30:F0)..................8-5

8.1.8 PMLT—Primary Master Latency Timer Register

(HUB-PCI—D30:F0) ........................................................................8-5

8.1.9 HEADTYP—Header Type Register (HUB-PCI—D30:F0)................8-5

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

8.1.10 PBUS_NUM—Primary Bus Number Register

(HUB-PCI—D30:F0) ........................................................................8-6

8.1.11 SBUS_NUM—Secondary Bus Number Register

(HUB-PCI—D30:F0) ........................................................................8-6

8.1.12 SUB_BUS_NUM—Subordinate Bus Number Register

(HUB-PCI—D30:F0) ........................................................................8-6

8.1.13 SMLT—Secondary Master Latency Timer Register

(HUB-PCI—D30:F0) ........................................................................8-6

8.1.14 IOBASE—I/O Base Register (HUB-PCI—D30:F0)..........................8-7

8.1.15 IOLIM—I/O Limit Register (HUB-PCI—D30:F0) ..............................8-7

8.1.16 SECSTS—Secondary Status Register (HUB-PCI—D30:F0)...........8-8

8.1.17 MEMBASE—Memory Base Register (HUB-PCI—D30:F0) .............8-9

8.1.18 MEMLIM—Memory Limit Register (HUB-PCI—D30:F0) .................8-9

8.1.19 PREF_MEM_BASE—Prefetchable Memory Base Register

(HUB-PCI—D30:F0) ........................................................................8-9

8.1.20 PREF_MEM_MLT—Prefetchable Memory Limit Register

(HUB-PCI—D30:F0) ......................................................................8-10

8.1.21 IOBASE_HI—I/O Base Upper 16 Bits Register

(HUB-PCI—D30:F0) ......................................................................8-10

8.1.22 IOLIM_HI—I/O Limit Upper 16 Bits Register

(HUB-PCI—D30:F0) ......................................................................8-10

8.1.23 INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0) ..............8-10

8.1.24 BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0) .....8-11

8.1.25 BRIDGE_CNT2—Bridge Control Register 2

(HUB-PCI—D30:F0) ......................................................................8-11

8.1.26 CNF—ICH2 Configuration Register (HUB-PCI—D30:F0) .............8-12

8.1.27 MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0) ......8-12

8.1.28 PCI_MAST_STS—PCI Master Status Register

(HUB-PCI—D30:F0) ......................................................................8-13

8.1.29 ERR_CMD—Error Command Register (HUB-PCI—D30:F0)........8-13

8.1.30 ERR_STS—Error Status Register (HUB-PCI—D30:F0)................8-14

LPC Interface Bridge Registers (D31:F0) ..................................................................9-1

9.1

PCI Configuration Registers (D31:F0) ..........................................................9-1

9.1.1 VID—Vendor ID Register (LPC I/F—D31:F0)..................................9-2

9.1.2 DID—Device ID Register (LPC I/F—D31:F0) ..................................9-2

9.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)................9-3

9.1.4 PCISTS—PCI Device Status (LPC I/F—D31:F0) ............................9-4

9.1.5 REVID—Revision ID Register (LPC I/F—D31:F0)...........................9-4

9.1.6 PI—Programming Interface (LPC I/F—D31:F0) ..............................9-5

9.1.7 SCC—Sub-Class Code Register (LPC I/F—D31:F0) ......................9-5

9.1.8 BCC—Base-Class Code Register (LPC I/F—D31:F0) ....................9-5

9.1.9 HEADTYP—Header Type Register (LPC I/F—D31:F0) ..................9-5

9.1.10 PMBASE—ACPI Base Address (LPC I/F—D31:F0)........................9-6

9.1.11 ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)..............................9-6

9.1.12 BIOS_CNTL (LPC I/F—D31:F0)......................................................9-7

9.1.13 TCO_CNTL—TCO Control (LPC I/F—D31:F0) ...............................9-7

9.1.14 GPIOBASE—GPIO Base Address (LPC I/F—D31:F0) ...................9-8

9.1.15 GPIO_CNTL—GPIO Control (LPC I/F—D31:F0) ............................9-8

9.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control

(LPC I/F—D31:F0)...........................................................................9-8

9.1.17 SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)................9-9

82801BA ICH2 and 82801BAM ICH2-M Datasheet

xiii

9.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control

(LPC I/F—D31:F0)...........................................................................9-9

9.1.19 D31_ERR_CFG—Device 31 Error Configuration Register

(LPC I/F—D31:F0).........................................................................9-10

9.1.20 D31_ERR_STS—Device 31 Error Status Register

(LPC I/F—D31:F0).........................................................................9-10

9.1.21 PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0) .....9-11

9.1.22 GEN_CNTL—General Control Register (LPC I/F—D31:F0) .........9-11

9.1.23 GEN_STS—General Status (LPC I/F—D31:F0)............................9-13

9.1.24 RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0).....9-14

9.1.25 COM_DEC—LPC I/F Communication Port Decode Ranges

(LPC I/F—D31:F0).........................................................................9-14

9.1.26 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges

(LPC I/F—D31:F0).........................................................................9-15

9.1.27 SND_DEC—LPC I/F Sound Decode Ranges

(LPC I/F—D31:F0).........................................................................9-15

9.1.28 FWH_DEC_EN1—FWH Decode Enable 1 Register

(LPC I/F—D31:F0).........................................................................9-16

9.1.29 GEN1_DEC—LPC I/F Generic Decode Range 1

(LPC I/F—D31:F0).........................................................................9-17

9.1.30 LPC_EN—LPC I/F Enables (LPC I/F—D31:F0)............................9-17

9.1.31 FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0).............9-19

9.1.32 GEN2_DEC—LPC I/F Generic Decode Range 2

(LPC I/F—D31:F0).........................................................................9-20

9.1.33 FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0).............9-20

9.1.34 FWH_DEC_EN2—FWH Decode Enable 2 Register

(LPC I/F—D31:F0).........................................................................9-21

9.1.35 FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) .........9-22

DMA I/O Registers......................................................................................9-23

9.2.1 DMABASE_CA—DMA Base and Current Address Registers.......9-24

9.2.2 DMABASE_CC—DMA Base and Current Count Registers...........9-25

9.2.3 DMAMEM_LP—DMA Memory Low Page Registers .....................9-25

9.2.4 DMACMD—DMA Command Register ...........................................9-26

9.2.5 DMASTS—DMA Status Register...................................................9-26

9.2.6 DMA_WRSMSK—DMA Write Single Mask Register.....................9-27

9.2.7 DMACH_MODE—DMA Channel Mode Register...........................9-27

9.2.8 DMA Clear Byte Pointer Register ..................................................9-28

9.2.9 DMA Master Clear Register...........................................................9-28

9.2.10 DMA_CLMSK—DMA Clear Mask Register ...................................9-28

9.2.11 DMA_WRMSK—DMA Write All Mask Register .............................9-29

Timer I/O Registers.....................................................................................9-30

9.3.1 TCW—Timer Control Word Register .............................................9-30

9.3.1.1 RDBK_CMD—Read Back Command ............................9-31

9.3.1.2 LTCH_CMD—Counter Latch Command........................9-31

9.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register..........9-32

9.3.3 Counter Access Ports Register......................................................9-32

8259 Interrupt Controller (PIC) Registers ...................................................9-33

9.4.1 Interrupt Controller I/O MAP ..........................................................9-33

9.4.2 ICW1—Initialization Command Word 1 Register...........................9-34

9.4.3 ICW2—Initialization Command Word 2 Register...........................9-35

9.4.4 ICW3—Master Controller Initialization Command Word 3

9.2

9.3

9.4

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

9.4.5 ICW3—Slave Controller Initialization Command Word 3

9.4.6 ICW4—Initialization Command Word 4 Register...........................9-36

9.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register....9-36

9.4.8 OCW2—Operational Control Word 2 Register ..............................9-37

9.4.9 OCW3—Operational Control Word 3 Register ..............................9-38

9.4.10 ELCR1—Master Controller Edge/Level Triggered Register ..........9-39

9.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............9-40

Advanced Interrupt Controller (APIC) .........................................................9-41

9.5.1 APIC Register Map ........................................................................9-41

9.5.2 IND—Index Register......................................................................9-41

9.5.3 DAT—Data Register ......................................................................9-42

9.5.4 IRQPA—IRQ Pin Assertion Register .............................................9-42

9.5.5 EOIR—EOI Register......................................................................9-43

9.5.6 ID—Identification Register .............................................................9-43

9.5.7 VER—Version Register .................................................................9-44

9.5.8 ARBID—Arbitration ID Register.....................................................9-44

9.5.9 BOOT_CONFIG—Boot Configuration Register.............................9-44

9.5.10 Redirection Table...........................................................................9-45

Real Time Clock Registers .........................................................................9-47

9.6.1 I/O Register Address Map..............................................................9-47

9.6.2 Indexed Registers..........................................................................9-47

9.6.2.1 RTC_REGA—Register A................................................9-48

9.6.2.2 RTC_REGB—Register B (General Configuration).........9-49

9.6.2.3 RTC_REGC—Register C (Flag Register) ......................9-50

9.6.2.4 RTC_REGD—Register D (Flag Register) ......................9-50

Processor Interface Registers.....................................................................9-51

9.7.1 NMI_SC—NMI Status and Control Register..................................9-51

9.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) ....................9-52

9.7.3 PORT92—Fast A20 and Init Register............................................9-52

9.7.4 COPROC_ERR—Coprocessor Error Register ..............................9-52

9.7.5 RST_CNT—Reset Control Register ..............................................9-53

Power Management Registers (D31:F0) ....................................................9-54

9.8.1 Power Management PCI Configuration Registers (D31:F0)..........9-54

9.8.1.1 GEN_PMCON_1—General PM Configuration 1

9.5

9.6

9.7

9.8

9.8.1.2 GEN_PMCON_2—General PM Configuration 2

9.8.1.3 GEN_PMCON_3—General PM Configuration 3

9.8.1.4 GPI_ROUT—GPI Routing Control Register

(PM—D31:F0) ................................................................9-57

9.8.1.5 TRP_FWD_EN—IO Monitor Trap Forwarding

Enable Register (PM—D31:F0)......................................9-58

9.8.1.6 MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range

9.8.1.7 MON_TRP_MSK—I/O Monitor Trap Range Mask

9.8.2 APM I/O Decode............................................................................9-60

9.8.2.1 APM_CNT—Advanced Power Management

Control Port Register......................................................9-60

9.8.2.2 APM_STS—Advanced Power Management

Status Port Register .......................................................9-60

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9.8.3 Power Management I/O Registers.................................................9-61

9.8.3.1 PM1_STS—Power Management 1 Status Register.......9-62

9.8.3.2 PM1_EN—Power Management 1 Enable Register........9-64

9.8.3.3 PM1_CNT—Power Management 1 Control Register.....9-65

9.8.3.4 PM1_TMR—Power Management 1 Timer Register.......9-66

9.8.3.5 PROC_CNT—Processor Control Register.....................9-66

9.8.3.6 LV2—Level 2 Register ...................................................9-67

9.8.3.7 LV3—Level 3 Register (82801BAM ICH2-M).................9-67

9.8.3.8 PM2_CNT—Power Management 2 Control

(82801BAM ICH2-M)......................................................9-68

9.8.3.9 GPE0_STS—General Purpose Event 0 Status

9.8.3.10 GPE0_EN—General Purpose Event 0 Enables

9.8.3.11 GPE1_STS—General Purpose Event 1 Status

9.8.3.12 GPE1_EN—General Purpose Event 1 Enable

9.8.3.13 SMI_EN—SMI Control and Enable Register..................9-72

9.8.3.14 SMI_STS—SMI Status Register ....................................9-74

9.8.3.15 MON_SMI—Device Monitor SMI Status and Enable

9.8.3.16 DEVACT_STS—Device Activity Status Register ...........9-76

9.8.3.17 DEVTRAP_EN—Device Trap Enable Register..............9-77

9.8.3.18 BUS_ADDR_TRACK—Bus Address Tracker Register..9-78

9.8.3.19 BUS_CYC_TRACK—Bus Cycle Tracker Register.........9-78

9.8.3.20 SS_CNT— SpeedStep™ Control Register

(82801BAM ICH2-M)......................................................9-78

9.9

System Management TCO Registers (D31:F0)..........................................9-79

9.9.1 TCO Register I/O Map...................................................................9-79

9.9.2 TCO1_RLD—TCO Timer Reload and Current Value Register......9-79

9.9.3 TCO1_TMR—TCO Timer Initial Value Register............................9-80

9.9.4 TCO1_DAT_IN—TCO Data In Register ........................................9-80

9.9.5 TCO1_DAT_OUT—TCO Data Out Register..................................9-80

9.9.6 TCO1_STS—TCO1 Status Register..............................................9-80

9.9.7 TCO2_STS—TCO2 Status Register..............................................9-82

9.9.8 TCO1_CNT—TCO1 Control Register............................................9-83

9.9.9 TCO2_CNT—TCO2 Control Register............................................9-83

9.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers....................9-84

9.9.11 TCO_WDSTATUS—TCO2 Control Register.................................9-84

9.9.12 SW_IRQ_GEN—Software IRQ Generation Register.....................9-84

General Purpose I/O Registers (D31:F0) ...................................................9-85

9.10.1 GPIO Register I/O Address Map....................................................9-87

9.10.2 GPIO_USE_SEL—GPIO Use Select Register ..............................9-87

9.10.3 GP_IO_SEL—GPIO Input/Output Select Register ........................9-88

9.10.4 GP_LVL—GPIO Level for Input or Output Register.......................9-89

9.10.5 GPO_BLINK—GPO Blink Enable Register....................................9-90

9.10.6 GPI_INV—GPIO Signal Invert Register.........................................9-91

9.10

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

IDE Controller Registers (D31:F1)...........................................................................10-1

10.1

PCI Configuration Registers (IDE—D31:F1)...............................................10-1

10.1.1 VID—Vendor ID Register (IDE—D31:F1)......................................10-2

10.1.2 DID—Device ID Register (IDE—D31:F1) ......................................10-2

10.1.3 CMD—Command Register (IDE—D31:F1) ...................................10-2

10.1.4 STS—Device Status Register (IDE—D31:F1)...............................10-3

10.1.5 RID—Revision ID Register (HUB-PCI—D30:F0)...........................10-3

10.1.6 PI—Programming Interface (IDE—D31:F1)...................................10-3

10.1.7 SCC—Sub Class Code (IDE—D31:F1).........................................10-4

10.1.8 BCC—Base Class Code (IDE—D31:F1) .......................................10-4

10.1.9 MLT—Master Latency Timer (IDE—D31:F1).................................10-4

10.1.10 BM_BASE—Bus Master Base Address Register

(IDE—D31:F1) ...............................................................................10-4

10.1.11 IDE_SVID—Subsystem Vendor ID (IDE—D31:F1) .......................10-5

10.1.12 IDE_SID—Subsystem ID (IDE—D31:F1) ......................................10-5

10.1.13 IDE_TIM—IDE Timing Register (IDE—D31:F1) ............................10-5

10.1.14 SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1) ...............................................................................10-7

10.1.15 SDMA_CNT—Synchronous DMA Control Register

(IDE—D31:F1) ...............................................................................10-8

10.1.16 SDMA_TIM—Synchronous DMA Timing Register

(IDE—D31:F1) ...............................................................................10-8

10.1.17 IDE_CONFIG—IDE I/O Configuration Register.............................10-9

Bus Master IDE I/O Registers (D31:F1)....................................................10-11

10.2.1 BMIC[P,S]—Bus Master IDE Command Register .......................10-11

10.2.2 BMIS[P,S]—Bus Master IDE Status Register..............................10-12

10.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register .10-12

10.2

USB Controller Registers.........................................................................................11-1

11.1

PCI Configuration Registers (D31:F2/F4)...................................................11-1

11.1.1 VID—Vendor Identification Register (USB—D31:F2/F4)...............11-1

11.1.2 DID—Device Identification Register (USB—D31:F2/F4) ...............11-2

11.1.3 CMD—Command Register (USB—D31:F2/F4).............................11-2

11.1.4 STA—Device Status Register (USB—D31:F2/F4) ........................11-3

11.1.5 RID—Revision Identification Register (USB—D31:F2/F4) ............11-3

11.1.6 PI—Programming Interface (USB—D31:F2/F4)............................11-3

11.1.7 SCC—Sub Class Code Register (USB—D31:F2/F4)....................11-4

11.1.8 BCC—Base Class Code Register (USB—D31:F2/F4) ..................11-4

11.1.9 BASE—Base Address Register (USB—D31:F2/F4)......................11-4

11.1.10 SVID—Subsystem Vendor ID (USB—D31:F2/F4).........................11-4

11.1.11 SID—Subsystem ID (USB—D31:F2/F4)........................................11-5

11.1.12 INTR_LN—Interrupt Line Register (USB—D31:F2/F4) .................11-5

11.1.13 INTR_PN—Interrupt Pin Register (USB—D31:F2/F4)...................11-5

11.1.14 SB_RELNUM—Serial Bus Release Number Register

(USB—D31:F2/F4).........................................................................11-5

11.1.15 USB_LEGKEY—USB Legacy Keyboard/Mouse Control

11.1.16 USB_RES—USB Resume Enable Register

(USB—D31:F2/F4).........................................................................11-7

USB I/O Registers.......................................................................................11-8

11.2.1 USBCMD—USB Command Register ............................................11-8

11.2.2 USBSTA—USB Status Register..................................................11-11

11.2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

xvii

11.2.3 USBINTR—Interrupt Enable Register..........................................11-12

11.2.4 FRNUM—Frame Number Register..............................................11-12

11.2.5 FRBASEADD—Frame List Base Address...................................11-13

11.2.6 SOFMOD—Start of Frame Modify Register.................................11-13

11.2.7 PORTSC[0,1]—Port Status and Control Register........................11-14

SMBus Controller Registers (D31:F3) .....................................................................12-1

12.1

PCI Configuration Registers (SMBUS—D31:F3)........................................12-1

12.1.1 VID—Vendor Identification Register (SMBUS—D31:F3)...............12-1

12.1.2 DID—Device Identification Register (SMBUS—D31:F3)...............12-1

12.1.3 CMD—Command Register (SMBUS—D31:F3).............................12-2

12.1.4 STA—Device Status Register (SMBUS—D31:F3) ........................12-2

12.1.5 RID—Revision ID Register (SMBUS—D31:F3).............................12-3

12.1.6 PI—Programming Interface (SMBUS—D31:F3)............................12-3

12.1.7 SCC—Sub Class Code Register (SMBUS—D31:F3)....................12-3

12.1.8 BCC—Base Class Code Register (SMBUS—D31:F3)..................12-3

12.1.9 SMB_BASE—SMBus Base Address Register

(SMBUS—D31:F3) ........................................................................12-4

12.1.10 SVID—Subsystem Vendor ID (SMBUS—D31:F2/F4)...................12-4

12.1.11 SID—Subsystem ID (SMBUS—D31:F2/F4)..................................12-4

12.1.12 INTR_LN—Interrupt Line Register (SMBUS—D31:F3) .................12-4

12.1.13 INTR_PN—Interrupt Pin Register (SMBUS—D31:F3) ..................12-5

12.1.14 HOSTC—Host Configuration Register (SMBUS—D31:F3)...........12-5

SMBus I/O Registers ..................................................................................12-6

12.2.1 HST_STS—Host Status Register..................................................12-7

12.2.2 HST_CNT—Host Control Register ................................................12-8

12.2.3 HST_CMD—Host Command Register...........................................12-9

12.2.4 XMIT_SLVA—Transmit Slave Address Register...........................12-9

12.2.5 HST_D0—Data 0 Register.............................................................12-9

12.2.6 HST_D1—Data 1 Register.............................................................12-9

12.2.7 BLOCK_DB—Block Data Byte Register......................................12-10

12.2.8 RCV_SLVA—Receive Slave Address Register...........................12-10

12.2.9 SLV_DATA—Receive Slave Data Register.................................12-10

12.2.10 SMLINK_PIN_CTL—SMLINK Pin Control Register.....................12-11

12.2.11 SMBUS_PIN_CTL—SMBus Pin Control Register.......................12-11

12.2

AC’97 Audio Controller Registers (D31:F5).............................................................13-1

13.1

AC’97 Audio PCI Configuration Space (D31:F5)........................................13-1

13.1.1 VID—Vendor Identification Register (Audio—D31:F5) ..................13-1

13.1.2 DID—Device Identification Register (Audio—D31:F5)...................13-2

13.1.3 PCICMD—PCI Command Register (Audio—D31:F5)...................13-2

13.1.4 PCISTS—PCI Device Status Register (Audio—D31:F5)...............13-3

13.1.5 RID—Revision Identification Register (Audio—D31:F5)................13-3

13.1.6 PI—Programming Interface Register (Audio—D31:F5).................13-3

13.1.7 SCC—Sub Class Code Register (Audio—D31:F5) .......................13-4

13.1.8 BCC—Base Class Code Register (Audio—D31:F5)......................13-4

13.1.9 HEDT—Header Type Register (Audio—D31:F5) ..........................13-4

13.1.10 NAMBAR—Native Audio Mixer Base Address Register

(Audio—D31:F5)............................................................................13-5

13.1.11 NABMBAR—Native Audio Bus Mastering Base Address

13.1.12 SVID—Subsystem Vendor ID Register (Audio—D31:F5)..............13-6

xviii

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13.1.13 SID—Subsystem ID Register (Audio—D31:F5).............................13-6

13.1.14 INTR_LN—Interrupt Line Register (Audio—D31:F5).....................13-6

13.1.15 INTR_PN—Interrupt Pin Register (Audio—D31:F5)......................13-7

AC’97 Audio I/O Space (D31:F5)................................................................13-7

13.2.1 x_BDBAR—Buffer Descriptor Base Address Register ..................13-9

13.2.2 x_CIV—Current Index Value Register .........................................13-10

13.2.3 x_LVI—Last Valid Index Register ................................................13-10

13.2.4 x_SR—Status Register................................................................13-11

13.2.5 x_PICB—Position In Current Buffer Register ..............................13-12

13.2.6 x_PIV—Prefetched Index Value Register....................................13-12

13.2.7 x_CR—Control Register ..............................................................13-13

13.2.8 GLOB_CNT—Global Control Register.........................................13-14

13.2.9 GLOB_STA—Global Status Register ..........................................13-15

13.2.10 CAS—Codec Access Semaphore Register.................................13-16

13.2

AC’97 Modem Controller Registers (D31:F6) ..........................................................14-1

14.1

AC’97 Modem PCI Configuration Space (D31:F6) .....................................14-1

14.1.1 VID—Vendor Identification Register (Modem—D31:F6) ...............14-1

14.1.2 DID—Device Identification Register (Modem—D31:F6)................14-2

14.1.3 PCICMD—PCI Command Register (Modem—D31:F6) ................14-2

14.1.4 PCISTA—Device Status Register (Modem—D31:F6)...................14-3

14.1.5 RID—Revision Identification Register (Modem—D31:F6).............14-3

14.1.6 PI—Programming Interface Register (Modem—D31:F6) ..............14-3

14.1.7 SCC—Sub Class Code Register (Modem—D31:F6).....................14-4

14.1.8 BCC—Base Class Code Register (Modem—D31:F6)...................14-4

14.1.9 HEDT—Header Type Register (Modem—D31:F6)........................14-4

14.1.10 MMBAR—Modem Mixer Base Address Register

(Modem—D31:F6) .........................................................................14-4

14.1.11 MBAR—Modem Base Address Register (Modem—D31:F6) ........14-5

14.1.12 SVID—Subsystem Vendor ID (Modem—D31:F6) .........................14-5

14.1.13 SID—Subsystem ID (Modem—D31:F6) ........................................14-6

14.1.14 INTR_LN—Interrupt Line Register (Modem—D31:F6)..................14-6

14.1.15 INT_PIN—Interrupt Pin (Modem—D31:F6) ...................................14-6

AC’97 Modem I/O Space (D31:F6).............................................................14-7

14.2.1 x_BDBAR—Buffer Descriptor List Base Address Register............14-8

14.2.2 x_CIV—Current Index Value Register ...........................................14-9

14.2.3 x_LVI—Last Valid Index Register ..................................................14-9

14.2.4 x_SR—Status Register................................................................14-10

14.2.5 x_PICB—Position In Current Buffer Register ..............................14-11

14.2.6 x_PIV—Prefetch Index Value Register........................................14-11

14.2.7 x_CR—Control Register ..............................................................14-11

14.2.8 GLOB_CNT—Global Control Register.........................................14-12

14.2.9 GLOB_STA—Global Status Register ..........................................14-13

14.2.10 CAS—Codec Access Semaphore Register.................................14-14

14.2

Pinout and Package Information..............................................................................15-1

15.1

15.2

Pinout..........................................................................................................15-1

Package Information.................................................................................15-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

xix

Electrical Characteristics .........................................................................................16-1

16.1

16.2

16.3

16.4

16.5

Absolute Maximum Ratings........................................................................16-1

Functional Operating Range.......................................................................16-1

D.C. Characteristics....................................................................................16-2

A.C. Characteristics....................................................................................16-7

Timing Diagrams.......................................................................................16-18

Testability.................................................................................................................17-1

17.1

17.2

17.3

Test Mode Description................................................................................17-1

Tri-state Mode.............................................................................................17-2

XOR Chain Mode........................................................................................17-2

17.3.1 XOR Chain Testability Algorithm Example ....................................17-2

17.3.1.1 Test Pattern Consideration for XOR Chain 4 .................17-3

I/O Register Index..................................................................................................... A-1

Register Bit Index ..................................................................................................... B-1

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Figures

2-1

2-2

4-1

4-2

Required External RTC Circuit....................................................................2-16

Example V5REF Sequencing Circuit ..........................................................2-16

ICH2 and System Clock Domains................................................................4-1

Conceptual System Clock Diagram (82801BA ICH2 and

82801BAM ICH2-M)......................................................................................4-2

Primary Device Status Register Error Reporting Logic.................................5-3

Secondary Status Register Error Reporting Logic........................................5-3

NMI# Generation Logic.................................................................................5-4

Integrated LAN Controller Block Diagram.....................................................5-7

64-Word EEPROM Read Instruction Waveform.........................................5-17

LPC Interface Diagram ...............................................................................5-21

Typical Timing for LFRAME#......................................................................5-24

Abort Mechanism........................................................................................5-24

ICH2 DMA Controller ..................................................................................5-26

DMA Serial Channel Passing Protocol .......................................................5-30

DMA Request Assertion Through LDRQ# ..................................................5-34

Coprocessor Error Timing Diagram ............................................................5-67

Signal Strapping..........................................................................................5-70

Intel^®SpeedStep™ Block Diagram (82801BAM ICH2-M only)..................5-85

Physical Region Descriptor Table Entry ...................................................5-101

Transfer Descriptor ...................................................................................5-109

Example Queue Conditions ......................................................................5-116

USB Data Encoding..................................................................................5-119

USB Legacy Keyboard Flow Diagram ......................................................5-128

ICH2 Based AC’97 2.1..............................................................................5-143

AC’97 2.1 Controller-Codec Connection...................................................5-144

AC-link Protocol ........................................................................................5-145

AC-link Powerdown Timing.......................................................................5-151

SDIN Wake Signaling ...............................................................................5-152

FWH Memory Cycle Preamble .................................................................5-155

Single Byte Read ......................................................................................5-155

Single Byte Write ......................................................................................5-156

ICH2 82801BA and ICH2-M 82801BAM Ballout

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

5-13

5-14

5-15

5-16

5-17

5-18

5-19

5-20

5-21

5-22

5-23

5-24

5-25

5-26

5-27

15-1

(Top view — Left side)................................................................................15-2

15-2

ICH2 82801BA and ICH2-M 82801BAM Ballout

(Top view — Right side)..............................................................................15-3

ICH2 / ICH2-M Package (Top and Side Views)........................................15-14

ICH2 / ICH2-M Package (Bottom View)....................................................15-15

Clock Timing .............................................................................................16-18

Valid Delay From Rising Clock Edge........................................................16-18

Setup And Hold Times..............................................................................16-18

Float Delay................................................................................................16-18

Pulse Width...............................................................................................16-19

Output Enable Delay.................................................................................16-19

IDE PIO Mode...........................................................................................16-19

IDE Multiword DMA...................................................................................16-20

Ultra ATA Mode (Drive Initiating a Burst Read) ........................................16-20

15-3

15-4

16-1

16-2

16-3

16-4

16-5

16-6

16-7

16-8

16-9

16-10 Ultra ATA Mode (Sustained Burst)............................................................16-21

16-11 Ultra ATA Mode (Pausing a DMA Burst)...................................................16-21

82801BA ICH2 and 82801BAM ICH2-M Datasheet

xxi

16-12 Ultra ATA Mode (Terminating a DMA Burst) ............................................16-22

16-13 USB Rise and Fall Times..........................................................................16-22

16-14 USB Jitter..................................................................................................16-22

16-15 USB EOP Width........................................................................................16-23

16-16 SMBus Transaction ..................................................................................16-23

16-17 SMBus Time-out.......................................................................................16-23

16-18 Power Sequencing and Reset Signal Timings

(82801BA ICH2 only)................................................................................16-24

16-19 Power Sequencing and Reset Signal Timings

(82801BAM ICH2-M only).........................................................................16-24

16-20 1.8V/3.3V Power Sequencing...................................................................16-25

16-21 G3 (Mechanical Off) to S0 Timings (82801BA ICH2 only)........................16-25

16-22 G3 (Mechanical Off) to S0 Timings (82801BAM ICH2-M only) ................16-26

16-23 S0 to S1 to S0 Timings (82801BA ICH2 only)..........................................16-26

16-24 S0 to S1 to S0 Timings (82801BAM ICH2-M only)...................................16-27

16-25 S0 to S5 to S0 Timings (82801BA ICH2 only)..........................................16-27

16-26 S0 to S5 to S0 Timings (82801BAM ICH2-M only)...................................16-28

16-27 C0 to C2 to C0 Timings ............................................................................16-28

16-28 C0 to C3 to C0 Timings (82801BAM ICH2-M only) ..................................16-29

17-1

17-2

Test Mode Entry (XOR Chain Example).....................................................17-1

Example XOR Chain Circuitry ....................................................................17-2

xxii

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Tables

1-1

1-2

2-1

2-2

2-3

2-4

2-5

2-6

Industry Specifications..................................................................................1-1

PCI Devices and Functions...........................................................................1-3

Hub Interface Signals....................................................................................2-1

LAN Connect Interface Signals.....................................................................2-1

EEPROM Interface Signals...........................................................................2-2

Firmware Hub Interface Signals....................................................................2-2

PCI Interface Signals ....................................................................................2-2

IDE Interface Signals ....................................................................................2-5

LPC Interface Signals ...................................................................................2-6

Interrupt Signals............................................................................................2-6

USB Interface Signals...................................................................................2-7

Power Management Interface Signals..........................................................2-7

Processor Interface Signals..........................................................................2-9

SM Bus Interface Signals............................................................................2-10

System Management Interface Signals ......................................................2-10

Real Time Clock Interface...........................................................................2-11

Other Clocks ...............................................................................................2-11

Miscellaneous Signals ................................................................................2-11

AC’97 Link Signals......................................................................................2-12

General Purpose I/O Signals ......................................................................2-12

Power and Ground Signals.........................................................................2-13

Functional Strap Definitions........................................................................2-14

Test Mode Selection ...................................................................................2-15

ICH2 Power Planes.......................................................................................3-1

Integrated Pull-Up and Pull-Down Resistors.................................................3-1

IDE Series Termination Resistors.................................................................3-2

Power Plane and States for Output and I/O Signals.....................................3-3

Power Plane for Input Signals.......................................................................3-6

Type 0 Configuration Cycle Device Number Translation..............................5-5

I/O Control Hub 2 EEPROM Address Map .................................................5-18

LPC Cycle Types Supported.......................................................................5-21

Start Field Bit Definitions.............................................................................5-22

Cycle Type Bit Definitions...........................................................................5-22

Transfer Size Bit Definition .........................................................................5-22

SYNC Bit Definition.....................................................................................5-23

ICH2 Response to Sync Failures................................................................5-23

DMA Transfer Size......................................................................................5-28

Address Shifting in 16-bit I/O DMA Transfers.............................................5-28

DMA Cycle vs. I/O Address ........................................................................5-32

PCI Data Bus vs. DMA I/O Port Size ..........................................................5-32

DMA I/O Cycle Width vs. BE[3:0]#..............................................................5-33

Counter Operating Modes...........................................................................5-39

Interrupt Controller Core Connections ........................................................5-41

Interrupt Status Registers ...........................................................................5-42

Content of Interrupt Vector Byte .................................................................5-42

APIC Interrupt Mapping ..............................................................................5-49

Arbitration Cycles........................................................................................5-50

APIC Message Formats..............................................................................5-51

EOI Message ..............................................................................................5-51

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-14

2-15

2-16

2-17

2-18

2-19

2-20

2-21

3-1

3-2

3-3

3-4

3-5

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

5-13

5-14

5-15

5-16

5-17

5-18

5-19

5-20

5-21

82801BA ICH2 and 82801BAM ICH2-M Datasheet

xxiii

5-22

5-23

5-24

5-25

5-26

5-27

5-28

5-29

5-30

5-31

5-32

5-33

5-34

5-35

5-36

5-37

5-38

5-39

5-40

5-41

5-42

5-43

5-44

5-45

5-46

5-47

5-48

5-49

5-50

5-51

5-52

5-53

5-54

5-55

5-56

5-57

5-58

5-59

5-60

5-61

5-62

5-63

5-64

5-65

5-66

5-67

5-68

5-69

5-70

5-71

5-72

Short Message............................................................................................5-52

APIC Bus Status Cycle Definition...............................................................5-53

Lowest Priority Message (Without Focus Processor).................................5-54

Remote Read Message..............................................................................5-55

Interrupt Message Address Format ............................................................5-58

Interrupt Message Data Format..................................................................5-59

Stop Frame Explanation .............................................................................5-61

Data Frame Format ....................................................................................5-62

Configuration Bits Reset By RTCRST# Assertion ......................................5-65

INIT# Going Active......................................................................................5-67

NMI Sources...............................................................................................5-67

DP Signal Differences (82801BA ICH2 only)..............................................5-68

Frequency Strap Behavior Based on Exit State .........................................5-69

Frequency Strap Bit Mapping .....................................................................5-69

General Power States for Systems using ICH2..........................................5-72

State Transition Rules for ICH2..................................................................5-73

System Power Plane ..................................................................................5-74

Causes of SMI# and SCI ............................................................................5-75

Break Events ..............................................................................................5-77

Sleep Types................................................................................................5-81

Causes of Wake Events .............................................................................5-82

GPI Wake Events .......................................................................................5-82

Sleep State Exit Latencies..........................................................................5-83

Transitions Due To Power Failure ..............................................................5-83

Transitions Due to Power Button................................................................5-87

Transitions Due to RI# signal......................................................................5-88

Write Only Registers with Read Paths in Alternate Access Mode..............5-89

PIC Reserved Bits Return Values...............................................................5-91

ICH2 Clock Inputs.......................................................................................5-93

Alert on LAN* Message Data......................................................................5-97

IDE Transaction Timings (PCI Clocks) .....................................................5-100

Interrupt/Active Bit Interaction Definition...................................................5-103

UltraATA/33 Control Signal Redefinitions.................................................5-105

Frame List Pointer Bit Description ............................................................5-108

TD Link Pointer.........................................................................................5-109

TD Control and Status ..............................................................................5-110

TD Token..................................................................................................5-112

TD Buffer Pointer......................................................................................5-112

Queue Head Block....................................................................................5-113

Queue Head Link Pointer .........................................................................5-113

Queue Element Link Pointer.....................................................................5-113

Command Register, Status Register and TD Status Bit Interaction .........5-115

Queue Advance Criteria ...........................................................................5-117

USB Schedule List Traversal Decision Table...........................................5-118

PID Format ...............................................................................................5-120

PID Types.................................................................................................5-121

Address Field............................................................................................5-121

Endpoint Field...........................................................................................5-122

Token Format ...........................................................................................5-123

SOF Packet ..............................................................................................5-123

xxiv

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-73

5-74

5-75

5-76

5-77

5-78

5-79

5-80

5-81

5-82

5-83

5-84

5-85

5-86

5-87

5-88

5-89

5-90

5-91

5-92

6-1

Data Packet Format..................................................................................5-124

Bits maintained in low power states..........................................................5-127

USB Legacy Keyboard State Transitions..................................................5-129

Quick Protocol...........................................................................................5-131

Send / Receive Byte Protocol ...................................................................5-131

Write Byte/Word Protocol..........................................................................5-132

Read Byte/Word Protocol .........................................................................5-132

Process Call Protocol................................................................................5-133

Block Read/Write Protocol........................................................................5-135

I²C Block Read .........................................................................................5-136

Slave Write Cycle Format .........................................................................5-139

Slave Write Registers ...............................................................................5-139

Command Types.......................................................................................5-140

Read Cycle Format...................................................................................5-140

Data Values for Slave Read Registers .....................................................5-141

Featured Supported by ICH2....................................................................5-142

AC’97 Signals ...........................................................................................5-144

Input Slot 1 Bit Definitions.........................................................................5-149

Output Tag Slot 0......................................................................................5-150

AC-link state during PCIRST# ..................................................................5-153

PCI Devices and Functions...........................................................................6-2

Fixed I/O Ranges Decoded by ICH2.............................................................6-3

Variable I/O Decode Ranges ........................................................................6-5

Memory Decode Ranges from Processor Perspective.................................6-6

PCI Configuration Map (LAN Controller—B1:D8:F0)....................................7-1

Configuration of Subsystem ID and Subsystem Vendor ID via

6-2

6-3

6-4

7-1

7-2

EEPROM ......................................................................................................7-6

Data Register Structure ..............................................................................7-10

ICH2 Integrated LAN Controller CSR Space ..............................................7-10

Self-Test Results Format ............................................................................7-15

Statistical Counters.....................................................................................7-20

PCI Configuration Map (HUB-PCI—D30:F0)................................................8-1

PCI Configuration Map (LPC I/F—D31:F0)...................................................9-1

DMA Registers............................................................................................9-23

PIC Registers..............................................................................................9-33

APIC Direct Registers.................................................................................9-41

APIC Indirect Registers...............................................................................9-41

RTC I/O Registers.......................................................................................9-47

RTC (Standard) RAM Bank ........................................................................9-47

PCI Configuration Map (PM—D31:F0) .......................................................9-54

APM Register Map......................................................................................9-60

ACPI and Legacy I/O Register Map............................................................9-61

TCO I/O Register Map ................................................................................9-79

Summary of GPIO Implementation.............................................................9-85

Registers to Control GPIO ..........................................................................9-87

PCI Configuration Map (IDE—D31:F1).......................................................10-1

Bus Master IDE I/O Registers...................................................................10-11

PCI Configuration Map (USB—D31:F2/F4) ................................................11-1

USB I/O Registers.......................................................................................11-8

Run/Stop, Debug Bit Interaction SWDBG (Bit 5),

7-3

7-4

7-5

7-6

8-1

9-1

9-2

9-3

9-4

9-5

9-6

9-7

9-8

9-9

9-10

9-11

9-12

9-13

10-1

10-2

11-1

11-2

11-3

Run/Stop (Bit 0) Operation........................................................................11-10

12-1

PCI Configuration Registers (SMBUS—D31:F3)........................................12-1

82801BA ICH2 and 82801BAM ICH2-M Datasheet

xxv

12-2

13-1

13-2

13-3

14-1

14-2

14-3

15-1

15-2

16-1

16-2

16-3

16-4

16-5

16-6

16-7

16-8

16-9

SMB I/O Registers......................................................................................12-6

PCI Configuration Map (Audio—D31:F5) ...................................................13-1

ICH2 Audio Mixer Register Configuration...................................................13-7

Native Audio Bus Master Control Registers ...............................................13-9

PCI Configuration Map (Modem—D31:F6).................................................14-1

ICH2 Modem Mixer Register Configuration................................................14-7

Modem Registers........................................................................................14-8

ICH2 82801BA Alphabetical Ball List by Signal Name ...............................15-4

ICH2-M 82801BAM Alphabetical Ball List by Signal Name........................15-9

ICH2-M Power Consumption Measurements .............................................16-2

DC Characteristic Input Signal Association ................................................16-2

DC Input Characteristics.............................................................................16-3

DC Characteristic Output Signal Association .............................................16-4

DC Output Characteristics..........................................................................16-5

Other DC Characteristics............................................................................16-6

Clock Timings .............................................................................................16-7

PCI Interface Timing...................................................................................16-9

IDE PIO & Multiword DMA Mode Timing..................................................16-10

16-10 Ultra ATA Timing (Mode 0, Mode 1, Mode 2)...........................................16-11

16-11 Ultra ATA Timing (Mode 3, Mode 4, Mode 5)...........................................16-11

16-12 Universal Serial Bus Timing......................................................................16-12

16-13 IOAPIC Bus Timing...................................................................................16-13

16-14 SMBus Timing ..........................................................................................16-13

16-15 AC’97 Timing ............................................................................................16-13

16-16 LPC Timing...............................................................................................16-14

16-17 Miscellaneous Timings .............................................................................16-14

16-18 Power Sequencing and Reset Signal Timings..........................................16-14

16-19 Power Management Timings....................................................................16-16

17-1

17-2

17-3

Test Mode Selection...................................................................................17-1

XOR Test Pattern Example ........................................................................17-2

XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks while

PWROK Active) ..........................................................................................17-4

17-4

17-5

17-6

XOR Chain #2 (RTCRST# Asserted for 5 PCI clocks while

PWROK Active) ..........................................................................................17-5

XOR Chain #3 (RTCRST# Asserted for 6 PCI Clocks while

PWROK Active) ..........................................................................................17-6

XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks while

PWROK Active) ..........................................................................................17-7

Signals Not in XOR Chain ..........................................................................17-8

ICH2 Fixed I/O Registers............................................................................. A-1

ICH2 Variable I/O Registers ........................................................................ A-6

17-7

A-1

A-2

xxvi

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Revision History

Revision

-001

-002

Description

Date

Initial Release.

June 2000

•

Edits throughout for clarity

Added ICH2-M: Initial Release

October 2000

82801BA ICH2 and 82801BAM ICH2-M Datasheet

xxvii

This page is intentionally left blank

xxviii

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Introduction

The Intel^®82801BA ICH2 and Intel^®82801BAM ICH2-M are a highly integrated multifunctional

I/O Controller Hubs that provide the interface to the PCI Bus and integrate many of the functions

needed in today’s PC platforms. The 82801BA is intended for desktop applications and the

82801BAM is intended for mobile applications. This datasheet provides a detailed description of

the 82801BA and 82801BAM functions and capabilities including, signals, registers, on-chip

functional units, interfaces, pinout, packaging, electrical characteristics, and testability.

Unless otherwise specified, all non-shaded areas describe the functionality of both components. In

the non-shaded areas, the term "ICH2" refers to both the 82801BA and 82801BAM components.

Shading, as is shown here, indicates differences between the two components. In the shaded areas

ICH2 refers to the 82801BA and ICH2-M refers to the 82801BAM.

1.1

About this Document

This datasheet is intended for Original Equipment Manufacturers and BIOS vendors creating

ICH2-based products. This document assumes a working knowledge of the vocabulary and

principles of USB, IDE, AC’97, SMBus, PCI, ACPI, LAN, and LPC. Although some details of

these features are described within this document, refer to the individual industry specifications

listed in Table 1-1 for the complete details.

Table 1-1. Industry Specifications

Specification

Location

LPC

AC’97

WfM

http://developer.intel.com/design/pcisets/lpc/

http://developer.intel.com/pc-supp/platform/ac97/

http://developer.intel.com/ial/WfM/usesite.htm

http://www.sbs-forum.org/specs.htm

http://pcisig.com/specs.htm

SMBus

PCI

USB

http://www.usb.org

ACPI

http://www.teleport.com/~acpi/

Chapter 1. Introduction

Chapter 1 introduces the ICH2 and provides information on document organization. This chapter

also describes the key features of the ICH2 and provides a brief description of the major functions.

Chapter 2. Signal Description

Chapter 2 provides a detailed description of each ICH2 signal. Signals are arranged according to

interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of

all signals.

Chapter 3. Power Planes and Pin States

Chapter 3 provides a complete list of signals, their associated power well, their logic level in each

suspend state, and their logic level before and after reset.

Chapter 4. System Clock Domains

Chapter 4 provides a list of each clock domain associated with the ICH2 in an ICH2-based system.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

1-1

Introduction

Chapter 5. Functional Description

Chapter 5 provides a detailed description of the functions in the ICH2. All PCI buses, devices and

functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function.

This datasheet abbreviates buses as B0 and B1, devices as D8, D30 and D31 and functions as F0,

F1, F2, F3, F4, F5 and F6. For example Device 31 Function 5 is abbreviated as D31:F5, Bus 1

Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and

can be considered to be Bus 0. Note that the ICH2’s external PCI bus is typically Bus 1; however, it

may be assigned a different number depending on system configuration.

Chapter 6. Register, Memory and I/O Address Maps

Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory

ranges decoded by the ICH2.

Chapter 7. LAN Controller Registers

Chapter 7 provides a detailed description of all registers that reside in the ICH2’s integrated LAN

Controller. The integrated LAN Controller resides on the ICH2’s external PCI bus (typically Bus 1)

at Device 8, Function 0 (B1:D8:F0).

Chapter 8. Hub Interface to PCI Bridge Registers

Chapter 8 provides a detailed description of all registers that reside in the Hub Interface to PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 9. LPC Bridge Registers

Chapter 9 provides a detailed description of all registers that reside in the LPC bridge. This bridge

resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units

within the ICH2 including DMA, Timers, Interrupts, CPU Interface, GPIO, Power Management,

System Management and RTC.

Chapter 10. IDE Controller Registers

Chapter 10 provides a detailed description of all registers that reside in the IDE controller. This

controller resides at Device 31, Function 1 (D31:F1).

Chapter 11. USB Controller Registers

Chapter 11 provides a detailed description of all registers that reside in the two USB controllers.

These controllers reside at Device 31, Functions 2 and 4 (D31:F2/F4).

Chapter 12. SMBus Controller Registers

Chapter 12 provides a detailed description of all registers that reside in the SMBus controller. This

controller resides at Device 31, Function 3 (D31:F3).

Chapter 13. AC’97 Audio Controller Registers

Chapter 13 provides a detailed description of all registers that reside in the audio controller. This

controller resides at Device 31, Function 5 (D31:F5). Note that this section of the datasheet does

not include the native audio mixer registers. Accesses to the mixer registers are forwarded over the

AC-link to the codec where the registers reside.

Chapter 14. AC’97 Modem Controller Registers

Chapter 14 provides a detailed description of all registers that reside in the modem controller. This

controller resides at Device 31, Function 6 (D31:F6). Note that this section of the datasheet does

not include the modem mixer registers. Accesses to the mixer registers are forwarded over the

AC-link to the codec where the registers reside.

Chapter 15. Pinout and Package Information

Chapter 15 provides the ball assignment for the 360 EBGA package. The chapter also provides the

physical dimensions and characteristics of the 360 EBGA package.

Chapter 16. Electrical Characteristics

Chapter 16 provides the AC and DC characteristics including timing diagrams.

Chapter 17. Testability

Chapter 17 provides details about the implementation of test modes on the ICH2.

Index

There are indexes listing registers and register bits.

1-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Introduction

1.2

Overview

The ICH2 provides extensive I/O support. Functions and capabilities include:

• PCI Rev 2.2 compliant with support for 33 MHz PCI operations.

• PCI slots (supports up to 6 Req/Gnt pairs)

• ACPI Power Management Logic Support

• Enhanced DMA Controller, Interrupt Controller, and Timer Functions

• Integrated IDE controller supports Ultra ATA100/66/33)

• USB host interface with support for 4 USB ports; 2 host controllers

• Integrated LAN Controller

• System Management Bus (SMBus) with additional support for I²C devices

• AC’97 2.1 Compliant Link for Audio and Telephony codecs (up to 6 channels)

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Alert On LAN* (AOL) and Alert On LAN 2 (AOL2)*

The ICH2 incorporates a variety of PCI functions that are divided into two logical devices

(30 and 31) on PCI Bus 0 and one device on Bus 1. Device 30 is the Hub Interface-To-PCI bridge.

Device 31 contains all the other PCI functions, except the LAN Controller as shown in Table 1-2.

The LAN controller is located on Bus 1.

Table 1-2. PCI Devices and Functions

Bus:Device:Function

Function Description

Hub Interface to PCI Bridge

Bus 0:Device 30:Function 0

PCI to LPC Bridge

(includes: DMA, Timers, compatible interrupt controller, APIC, RTC,

processor interface control, power management control, System

Management control, and GPIO control)

Bus 0:Device 31:Function 0

Bus 0:Device 31:Function 1

Bus 0:Device 31:Function 2

Bus 0:Device 31:Function 3

Bus 0:Device 31:Function 4

Bus 0:Device 31:Function 5

Bus 0:Device 31:Function 6

Bus 1:Device 8:Function 0

IDE Controller

USB Controller #1

SMBus Controller

USB Controller #2

AC’97 Audio Controller

AC’97 Modem Controller

LAN Controller

82801BA ICH2 and 82801BAM ICH2-M Datasheet

1-3

Introduction

The following sub-sections provide an overview of the ICH2 capabilities.

Hub Architecture

As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become

significant. With the addition of AC’97 and Ultra ATA/100, coupled with the existing USB, I/O

requirements could impact PCI bus performance. The chipset’s hub interface architecture ensures

that the I/O subsystem; both PCI and the integrated I/O features (IDE, AC’97, USB, etc.), will

receive adequate bandwidth. By placing the I/O bridge on the hub interface (instead of PCI), the

hub architecture ensures that both the I/O functions integrated into the ICH2 and the PCI

peripherals obtain the bandwidth necessary for peak performance.

PCI Interface

The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals

are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up to six external

PCI bus masters in addition to the internal ICH2 requests.

IDE Interface (Bus Master capability and synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks

and CD ROMs. Each IDE device can have independent timings. The IDE interface supports PIO

IDE transfers up to 14 Mbytes/sec and Bus Master IDE transfers up 100 Mbytes/sec. It does not

consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal

transfers.

The ICH2’s IDE system contains two independent IDE signal channels. They can be electrically

isolated independently. They can be configured to the standard primary and secondary channels

(four devices). There are integrated series resistors on the data and control lines (see Section 5.15,

“IDE Controller (D31:F1)” on page 5-99 for details).

Low Pin Count (LPC) Interface

The ICH2 implements an LPC Interface as described in the LPC 1.0 specification. The Low Pin

Count (LPC) Bridge function of the ICH2 resides in PCI Device 31:Function 0. In addition to the

LPC bridge interface function, D31:F0 contains other functional units including DMA, Interrupt

Controllers, Timers, Power Management, System Management, GPIO, and RTC.

Note that in the current chipset platform, the Super I/O (SIO) component has migrated to the Low

Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs.

1-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Introduction

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt

Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven

independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte

transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven

DMA channels can be programmed to support fast Type-F transfers.

The ICH2 supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA DMA.

LPC DMA and PC/PCI DMA use the ICH2’s DMA controller. The PC/PCI protocol allows

PCI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PCI

REQ#/GNT# pairs.

LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encodings

on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the

LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit channels. Channel 4 is

reserved as a generic bus master request.

The timer/counter block contains three counters that are equivalent in function to those found in

one 82C54 programmable interval timer. These three counters are combined to provide the system

timer function, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for

these three counters.

The ICH2 provides an ISA-Compatible interrupt controller that incorporates the functionality of

two 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and

two internal interrupts are possible. In addition, the ICH2 supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save and restore

system state after power has been removed and restored to the circuit.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible interrupt controller (PIC) described in the previous

section, the ICH2 incorporates the Advanced Programmable Interrupt Controller (APIC). While

the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in

either a uni-processor or multi-processor system.

Enhanced Universal Serial Bus (USB) Controller

The USB controller provides enhanced support for the Universal Host Controller Interface (UHCI).

This includes support that allows legacy software to use a USB-based keyboard and mouse. The

ICH2 is USB Revision 1.1 compliant. The ICH2 contains two USB Host Controllers. Each Host

Controller includes a root hub with two separate USB ports each, for a total of 4 USB ports. See

Section 5.16, “USB Controller (Device 31:Functions 2 and 4)” on page 5-108 for details.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

1-5

Introduction

LAN Controller

The ICH2’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced

scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed

data transfers over the PCI bus. Its bus master capabilities enable the component to process high-

level commands and perform multiple operations; this lowers processor utilization by off-loading

communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help

prevent data underruns and overruns while waiting for bus accesses. This enables the integrated

LAN Controller to transmit data with minimum interframe spacing (IFS).

The LAN Controller can operate in either full duplex or half duplex mode. In full duplex mode the

LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half duplex

performance is enhanced by a proprietary collision reduction mechanism. See Section 5.2, “LAN

Controller (B1:D8:F0)” on page 5-6 for details.

RTC

The ICH2 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of

battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of

day and storing system data, even when the system is powered down. The RTC operates on a

32.768 KHz crystal and a separate 3V lithium battery that provides up to 7 years of protection.

The RTC also supports two lockable memory ranges. By setting bits in the configuration space,

two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of

passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in

advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design. The number of

inputs and outputs varies depending on ICH2 configuration.

Enhanced Power Management

The ICH2’s power management functions include enhanced clock control, local and global

monitoring support for 14 individual devices, and various low-power (suspend) states

(e.g., Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit

permits software-independent entrance to low-power states. The ICH2 contains full support for the

Advanced Configuration and Power Interface (ACPI) Specification.

For the ICH2-M 82801BAM, the Intel^®SpeedStep^™technology feature enables a mobile system

to operate in multiple processor performance/thermal states and to transition smoothly between

them. The internal processor clock setting and processor supply voltage setting determines these

states. The ICH2-M supports one Low Power mode and one High Performance mode.

The ICH2-M’s PCI clock can be dynamically controlled independent of any other low-power state

(Dynamic PCI Clock control).

1-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Introduction

System Management Bus (SMBus)

The ICH2 contains an SMBus Host interface that allows the processor to communicate with

SMBus slaves. This interface is compatible with most I²C devices. Special I²C commands are

implemented (e.g., the I²C Read that allows the ICH2 to perform block reads of I²C devices).

The ICH2’s SMBus host controller provides a mechanism for the processor to initiate

communications with SMBus peripherals (slaves). The host controller supports seven SMBus

interface command protocols for communicating with SMBus slave devices (see System

Management Bus Specifications, Rev 1.0): Quick Command, Send Byte, Receive Byte, Write

Byte/Word, Read Byte/Word, Process Call, and Block Read/Write.

Manageability

The ICH2 integrates several functions designed to manage the system and lower the total cost of

ownership (TC0) of the system. These system management functions are designed to report errors,

diagnose the system, and recover from system lockups without the aid of an external

microcontroller.

• TCO Timer. The ICH2’s integrated programmable TC0 Timer is used to detect system locks.

The first expiration of the timer generates an SMI# that the system can use to recover from a

software lock. The second expiration of the timer causes a system reset to recover from a

hardware lock.

• Processor Present Indicator. The ICH2 looks for the processor to fetch the first instruction

after reset. If the processor does not fetch the first instruction, the ICH2 will reboot the system

at the safe-mode frequency multiplier.

• ECC Error Reporting. When detecting an ECC error, the host controller has the ability to

send one of several messages to the ICH2. The host controller can instruct the ICH2 to

generate either an SMI#, NMI, SERR#, or TCO interrupt.

• Function Disable. The ICH2 provides the ability to disable the following functions: AC’97

Modem, AC’97 Audio, IDE, USB, or SMBus. Once disabled, these functions no longer

decode I/O, memory, or PCI configuration space. Also, no interrupts or power management

events are generated from the disable functions.

• Intruder Detect. The ICH2 provides an input signal (INTRUDER#) that can be attached to a

switch that is activated by the system case being opened. The ICH2 can be programmed to

generate an SMI# or TCO interrupt due to an active INTRUDER# signal.

• SMBus. The ICH2 integrates an SMBus controller that provides an interface to manage

peripherals (e.g., serial presence detection (SPD) or RIMMs and thermal sensors).

• Alert-On-LAN*. The ICH2 supports Alert-On-LAN* and Alert-On-LAN* 2. In response to a

TCO event (intruder detect, thermal event, processor not booting) the ICH2 sends a message

over the SMBus. A LAN controller can decode this SMBus message and send a message over

the network to alert the network manager.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

1-7

Introduction

AC’97 2.1 Controller

The Audio Codec ’97 (AC’97) specification defines a digital interface that can be used to attach an

audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or both an AC and an

MC. The AC’97 specification defines the interface between the system logic and the audio or

modem codec, known as the AC’97 Digital Link.

The ICH2’s AC’97 (with the appropriate codecs) not only replaces ISA audio and modem

functionality, but also improves overall platform integration by incorporating the AC’97 digital

link. The use of the ICH2-integrated AC’97 digital link reduces cost and eases migration from ISA.

By using an audio codec, the AC’97 digital link allows for cost-effective, high-quality, integrated

audio on Intel’s chipset-based platform. In addition, an AC’97 soft modem can be implemented

with the use of a modem codec. Several system options exist when implementing AC’97. The

ICH2-integrated digital link allows several external codecs to be connected to the ICH2. The

system designer can provide audio with an audio codec, a modem with a modem codec, or an

integrated audio/modem codec. The digital link is expanded to support two audio codecs or a

combination of an audio and modem codec.

The modem implementations for different countries must be taken into consideration, because

telephone systems may vary. By using a split design, the audio codec can be on-board and the

modem codec can be placed on a riser. Intel is developing an AC’97 digital link connector. With a

single integrated codec, or AMC, both audio and modem can be routed to a connector near the rear

panel, where the external ports can be located.

The digital link in the ICH2 is compliant with revision 2.1 of the AC’97, so it supports two codecs

with independent PCI functions for audio and modem. Microphone input and left and right audio

channels are supported for a high quality, two-speaker audio solution. Wake on Ring from Suspend

also is supported with the appropriate modem codec.

The ICH2 expands the audio capability with support for up to six channels of PCM audio output

(full AC3 decode). Six-channel audio consists of Front Left, Front Right, Back Left, Back Right,

Center, and Woofer, for a complete surround-sound effect. ICH2 has expanded support for two

audio codecs on the AC’97 digital link.

1-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in functional

groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when

the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high

voltage level.

The following notations are used to describe the signal type:

Input Pin

Output Pin

I/O

Open Drain Output Pin.

Bi-directional Input / Output Pin.

2.1

Hub Interface to Host Controller

Table 2-1. Hub Interface Signals

Name

HL[11:0]

Type

I/O

Description

Hub Interface Signals

Hub Interface Strobe: One of two differential strobe signals used to transmit and

receive data through the hub interface.

HL_STB

I/O

Hub Interface Strobe Complement: Second of the two differential strobe

signals.

HL_STB#

HLCOMP

I/O

Hub Interface Compensation: Used for hub interface buffer compensation.

2.2

Link to LAN Connect

Table 2-2. LAN Connect Interface Signals

Name

Type

Description

LAN Interface Clock: This signal is driven by the LAN Connect component. The

frequency range is 0.8 MHz to 50 MHz.

LAN_CLK

Received Data: The LAN Connect component uses these signals to transfer

data and control information to the integrated LAN Controller. These signals have

integrated weak pull-up resistors.

LAN_RXD[2:0]

Transmit Data: The integrated LAN Controller uses these signals to transfer

data and control information to the LAN Connect component.

LAN_TXD[2:0]

LAN Reset/Sync: The LAN Connect component’s Reset and Sync signals are

multiplexed onto this pin.

LAN_RSTSYNC

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-1

Signal Description

2.3

EEPROM Interface

Table 2-3. EEPROM Interface Signals

Name

Type

Description

EE_SHCLK

EEPROM Shift Clock: EE_SHCLK is the serial shift clock output to the EEPROM.

EEPROM Data In: EE_DIN transfers data from the EEPROM to the ICH2. This

signal has an integrated pull-up resistor.

EE_DIN

EE_DOUT

EE_CS

EEPROM Data Out: EE_DOUT transfers data from the ICH2 to the EEPROM.

EEPROM Chip Select: EE_CS is a chip-select signal to the EEPROM.

2.4

Firmware Hub Interface

Table 2-4. Firmware Hub Interface Signals

Name

Type

Description

FWH[3:0] /

LAD[3:0]

I/O

Firmware Hub Signals: These signals are muxed with LPC address signals.

FWH[4] /

LFRAME#

I/O

Firmware Hub Signals: This signal is muxed with LPC LFRAME# signal.

2.5

PCI Interface

Table 2-5. PCI Interface Signals

Name

Type

Description

PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first

clock of a transaction, AD[31:0] contain a physical address (32 bits). During

subsequent clocks, AD[31:0] contain data. The ICH2 drives all 0s on AD[31:0]

during the address phase of all PCI Special Cycles.

AD[31:0]

I/O

Bus Command and Byte Enables: The command and byte enable signals are

multiplexed on the same PCI pins. During the address phase of a transaction,

C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the

Byte Enables.

C/BE[3:0]# Command Type

0000

0001

0010

0011

0110

0111

1010

1011

1100

1110

1111

Interrupt Acknowledge

Special Cycle

I/O Read

I/O Write

Memory Read

C/BE[3:0]#

I/O

Memory Write

Configuration Read

Configuration Write

Memory Read Multiple

Memory Read Line

Memory Write and Invalidate

All command encodings not shown are reserved. The ICH2 does not decode

reserved values, and therefore will not respond if a PCI master generates a cycle

using one of the reserved values.

2-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

Table 2-5. PCI Interface Signals (Continued)

Name

Type

Description

Device Select: The ICH2 asserts DEVSEL# to claim a PCI transaction. As an

output, the ICH2 asserts DEVSEL# when a PCI master peripheral attempts an

access to an internal ICH2 address or an address destined for the hub interface

(main memory or AGP). As an input, DEVSEL# indicates the response to an ICH2-

initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of

PCIRST#. DEVSEL# remains tri-stated by the ICH2 until driven by a target device.

DEVSEL#

I/O

Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and

duration of a PCI transaction. While the initiator asserts FRAME#, data transfers

continue. When the initiator negates FRAME#, the transaction is in the final data

phase. FRAME# is an input to the ICH2 when the ICH2 is the target, and FRAME# is

an output from the ICH2 when the ICH2 is the Initiator. FRAME# remains tri-stated

by the ICH2 until driven by an Initiator.

FRAME#

IRDY#

I/O

Initiator Ready: IRDY# indicates the ICH2's ability, as an Initiator, to complete the

current data phase of the transaction. It is used in conjunction with TRDY#. A data

phase is completed on any clock both IRDY# and TRDY# are sampled asserted.

During a write, IRDY# indicates the ICH2 has valid data present on AD[31:0]. During

a read, it indicates the ICH2 is prepared to latch data. IRDY# is an input to the ICH2

when the ICH2 is the Target and an output from the ICH2 when the ICH2 is an

Initiator. IRDY# remains tri-stated by the ICH2 until driven by an Initiator.

Target Ready: TRDY# indicates the ICH2's ability as a Target to complete the

current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A

data phase is completed when both TRDY# and IRDY# are sampled asserted.

During a read, TRDY# indicates that the ICH2, as a Target, has placed valid data on

AD[31:0]. During a write, TRDY# indicates the ICH2, as a Target is prepared to latch

data. TRDY# is an input to the ICH2 when the ICH2 is the Initiator and an output

from the ICH2 when the ICH2 is a Target. TRDY# is tri-stated from the leading edge

of PCIRST#. TRDY# remains tri-stated by the ICH2 until driven by a target.

TRDY#

STOP#

I/O

Stop: STOP# indicates that the ICH2, as a Target, is requesting the Initiator to stop

the current transaction. STOP# causes the ICH2, as an Initiatior, to stop the current

transaction. STOP# is an output when the ICH2 is a target and an input when the

ICH2 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP#

remains tri-stated until driven by the ICH2.

Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0]

plus C/BE[3:0]#. "Even" parity means that the ICH2 counts the number of 1s within

the 36 bits plus PAR and the sum is always even. The ICH2 always calculates PAR

on 36 bits, regardless of the valid byte enables. The ICH2 generates PAR for

address and data phases and only guarantees PAR to be valid one PCI clock after

the corresponding address or data phase. The ICH2 drives and tri-states PAR

identically to the AD[31:0] lines except that the ICH2 delays PAR by exactly one PCI

clock. PAR is an output during the address phase (delayed one clock) for all ICH2

initiated transactions. PAR is an output during the data phase (delayed one clock)

when the ICH2 is the Initiator of a PCI write transaction, and when it is the target of a

read transaction. ICH2 checks parity when it is the target of a PCI write transaction.

If a parity error is detected, the ICH2 sets the appropriate internal status bits, and

has the option to generate an NMI# or SMI#.

PAR

I/O

Parity Error: An external PCI device drives PERR# when it receives data that has a

parity error. The ICH2 drives PERR# when it detects a parity error. The ICH can

either generate an NMI# or SMI# upon detecting a parity error (either detected

internally or reported via the PERR# signal).

PERR#

I/O

PCI Requests: The ICH2 supports up to 6 masters on the PCI bus. REQ[5]# is

muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not

used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1].

REQ[0:4]#

REQ[5]# /

REQ[B]# /

GPIO[1]

Note: REQ[0]# is programmable to have improved arbitration latency for supporting

PCI-based 1394 controllers.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-3

Signal Description

Table 2-5. PCI Interface Signals (Continued)

Name

Type

Description

PCI Grants: The ICH2 supports up to 6 masters on the PCI bus. GNT[5]# is muxed

with PC/PCI GNT[B]# (must choose one or the other, but not both). If not needed for

PCI or PC/PCI, GNT[5]# can instead be used as a GPIO.

GNT[0:4]#

GNT[5]# /

GNT[B]# /

GPIO[17]#

Pull-up resistors are not required on these signals. If pullups are used, they should

be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-

up.

PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on

the PCI Bus. .

Note:For 82801BAM ICH2-M, this clock does not stop based on the STP_PCI#

signal. The PCI Clock only stops based on SLP_S1# or SLP_S3#.

PCICLK

PCI Reset: ICH2 asserts PCIRST# to reset devices that reside on the PCI bus. The

ICH2 asserts PCIRST# during power-up and when S/W initiates a hard reset

sequence through the RC (CF9h) register. The ICH2 drives PCIRST# inactive a

minimum of 1 ms after PWROK is driven active. The ICH2 drives PCIRST# active a

minimum of 1 ms when initiated through the RC register.

PCIRST#

PCI Lock: PLOCK# indicates an exclusive bus operation and may require multiple

transactions to complete. ICH2 asserts PLOCK# when it performs non-exclusive

transactions on the PCI bus.

PLOCK#

I/O

82801BA ICH2: PLOCK# is ignored when PCI masters are granted the bus.

82801BAM ICH2-M: Devices on the PCI bus (other than the ICH2-M) are not

permitted to assert the PLOCK# signal.

System Error: SERR# can be pulsed active by any PCI device that detects a

system error condition. Upon sampling SERR# active, the ICH2 has the ability to

generate an NMI, SMI#, or interrupt.

SERR#

PME#

PCI Power Management Event: PCI peripherals drive PME# to wake the system

from low-power states S1–S5. PME# assertion can also be enabled to generate an

SCI from the S0 state. In some cases the ICH2 may drive PME# active due to an

internal wake event. The ICH2 will not drive PME# high, but it will be pulled up to

VccSus3_3 by an internal pull-up resistor.

PCI Clock Run: For the ICH2-M, CLKRUN# is used to support PCI Clock Run

protocol. This signal connects to PCI devices that need to request clock re-start or

prevention of clock stopping.

CLKRUN#

(ICH2-M only)

I/O

PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the

purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by

devices such as PCI-based Super I/O or audio codecs that need to perform legacy

8237 DMA but have no ISA bus.

REQ[A]# /

GPIO[0]

REQ[B]# /

REQ[5]# /

GPIO[1]

When not used for PC/PCI requests, these signals can be used as General Purpose

Inputs. Instead, REQ[B]# can be used as the 6th PCI bus request.

PC/PCI DMA Acknowledges [A:B]: This grant serializes an ISA-like DACK# for the

purpose of running DMA/ISA master cycles over the PCI bus. This is used by

devices such as PCI-based Super/IO or audio codecs which need to perform legacy

8237 DMA but have no ISA bus.

GNT[A]# /

GPIO[16]

GNT[B]# /

GNT[5]# /

GPIO[17]

When not used for PC/PCI, these signals can be used as General Purpose Outputs.

GNTB# can also be used as the 6th PCI bus master grant output. These signal have

internal pull-up resistors.

2-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

2.6

IDE Interface

Table 2-6. IDE Interface Signals

Name

Type

Description

Primary and Secondary IDE Device Chip Selects for 100 Range: These

signals are for the ATA command register block. This output signal is connected

to the corresponding signal on the primary or secondary IDE connector.

PDCS1#,

SDCS1#

Primary and Secondary IDE Device Chip Select for 300 Range: These signals

are for the ATA control register block. This output signal is connected to the

corresponding signal on the primary or secondary IDE connector.

PDCS3#,

SDCS3#

Primary and Secondary IDE Device Address: These output signals are

connected to the corresponding signals on the primary or secondary IDE

connectors. They are used to indicate which byte in either the ATA command

block or control block is being addressed.

PDA[2:0],

SDA[2:0]

Primary and Secondary IDE Device Data: These signals directly drive the

corresponding signals on the primary or secondary IDE connector. There is a

weak internal pull-down resistor on PDD[7] and SDD[7].

PDD[15:0],

SDD[15:0]

I/O

Primary and Secondary IDE Device DMA Request: These input signals are

directly driven from the DRQ signals on the primary or secondary IDE connector.

It is asserted by the IDE device to request a data transfer, and used in

conjunction with the PCI bus master IDE function. They are not associated with

any AT-compatible DMA channel. There is a weak internal pull-down resistor on

these signals.

PDDREQ,

SDDREQ

Primary and Secondary IDE Device DMA Acknowledge: These signals

directly drive the DAK# signals on the primary and secondary IDE connectors.

Each signal is asserted by the ICH2 to indicate to the IDE DMA slave devices that

a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer

cycle. This signal is used in conjunction with the PCI bus master IDE function and

are not associated with any AT-compatible DMA channel.

PDDACK#,

SDDACK#

Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the

command to the IDE device that it may drive data on the PDD or SDD lines. Data

is latched by the ICH2 on the deassertion edge of PDIOR# or SDIOR#. The IDE

device is selected either by the ATA register file chip selects (PDCS1# or

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA

acknowledge (PDDAK# or SDDAK#).

PDIOR#

SDIOR#

Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is

the data write strobe for writes to disk. When writing to disk, ICH2 drives valid

data on rising and falling edges of PDWSTB or SDWSTB.

Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This

is the DMA ready for reads from disk. When reading from disk, ICH2 deasserts

PRDMARDY# or SRDMARDY# to pause burst data transfers.

Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the

command to the IDE device that it may latch data from the PDD or SDD lines.

Data is latched by the IDE device on the deassertion edge of PDIOW# or

SDIOW#. The IDE device is selected either by the ATA register file chip selects

(PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the

IDE DMA acknowledge (PDDAK# or SDDAK#).

PDIOW#

SDIOW#

Primary and Secondary Disk Stop (Ultra DMA): ICH2 asserts this signal to

terminate a burst.

Primary and Secondary I/O Channel Ready (PIO): This signal keeps the strobe

active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than

the minimum width. It adds wait states to PIO transfers.

PIORDY

SIORDY

Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk):

When reading from disk, ICH2 latches data on rising and falling edges of this

signal from the disk.

Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When

writing to disk, this is deasserted by the disk to pause burst data transfers.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-5

Signal Description

2.7

LPC Interface

Table 2-7. LPC Interface Signals

Name

Type

Description

LAD[3:0] /

FWH[3:0]

I/O

LPC Multiplexed Command, Address, Data: Internal pull-ups are provided.

LFRAME# /

FWH[4]

LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LPC Serial DMA/Master Request Inputs: These signals are used to request DMA or

bus master access. Typically, they are connected to external Super I/O device. An

internal pull-up resistor is provided on these signals.

LDRQ[1:0]#

2.8

Interrupt Interface

Table 2-8. Interrupt Signals

Name

SERIRQ

Type

I/O

Description

Serial Interrupt Request: This pin implements the serial interrupt protocol.

PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to

interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section. Each

PIRQx# line has a separate Route Control Register.

PIRQ[D:A]#

I/OD

In APIC mode, these signals are connected to the internal I/O APIC in the following

fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18,

and PIRQ[D]# to IRQ19. This frees the ISA interrupts.

PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to

interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section. Each

PIRQx# line has a separate Route Control Register.

PIRQ[H]#,

PIRQ[G:F]# /

GPIO[4:3],

In APIC mode, these signals are connected to the internal I/O APIC in the following

fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22,

and PIRQ[H]# to IRQ23. This frees the ISA interrupts. If not needed for interrupts,

PIRQ[G:F] can be used as GPIO.

PIRQ[E]#

Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives.

IRQ14 is used by the drives connected to the primary controller and IRQ15 is used

by the drives connected to the secondary controller.

IRQ[14:15]

APICCLK

APIC Clock: The APIC clock runs at 33.333 MHz.

APIC Data: These bi-directional open drain signals are used to send and receive

data over the APIC bus. As inputs, the data is valid on the rising edge of APICCLK.

As outputs, new data is driven from the rising edge of the APICCLK.

APICD[1:0]

I/OD

2-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

2.9

USB Interface

Table 2-9. USB Interface Signals

Name

Type

Description

USBP0P,

USBP0N,

USBP1P,

USBP1N

Universal Serial Bus Port 1:0 Differential: These differential pairs are used to

transmit Data/Address/Command signals for ports 0 and 1 (USB Controller 1).

I/O

USBP2P,

USBP2N,

USBP3P,

USBP3N

Universal Serial Bus Port 3:2 Differential: These differential pairs are used to

transmit Data/Address/Command signals for ports 2 and 3

(USB Controller 2).

I/O

Overcurrent Indicators: These signals set corresponding bits in the USB

controllers to indicate that an overcurrent condition has occurred.

OC[3:0]#

2.10

Power Management Interface

Table 2-10. Power Management Interface Signals

Name

Type

Description

Thermal Alarm: THRM# is an active low signal generated by external hardware to

start the hardware clock throttling mode. This signal can also generate an SMI# or

an SCI.

THRM#

S1 Sleep Control: Clock synthesizer or power plane control. This signal connects

to clock synthesizer’s PWRDWN# signal. An optional use is to shut off power to

non-critical systems when in the S1 (Powered On Suspend), S3 (Suspend To

RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

SLP_S1#

(ICH2-M only)

S3 Sleep Control: Power plane control. This signal is used to shut off power to all

non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk) or S5

(Soft Off) states.

SLP_S3#

SLP_S5#

PWROK

S5 Sleep Control: Power plane control. This signal is used to shut power off to all

non-critical systems when in the S4 (Suspend To Disk) or S5 (Soft Off) states.

Power OK: When asserted, PWROK is an indication to the ICH2 that core power

and PCICLK have been stable for at least 1 ms. PWROK can be driven

asynchronously. When PWROK is negated, the ICH2 asserts PCIRST#.

Resume Well Power OK: When asserted, this signal is an indication to the ICH2

that the resume well power (VccSus3_3, VccSus1_8) has been stable for at least

10 ms.

RSM_PWROK

(ICH2 0nly)

LAN Power OK: When asserted, this signal is an indication to the ICH2-M that the

LAN Controller power (VccLAN3_3, VccLAN1_8) has been stable for at least

10 ms.

LAN_PWROK

(ICH2-M only)

Power Button: The Power Button will cause SMI# or SCI to indicate a system

request to go to a sleep state. If the system is already in a sleep state, this signal

will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will

cause an unconditional transition (power button override) to the S5 state with only

the PWRBTN# available as a wake event. Override will occur even if the system is

in the S1-S4 states. This signal has an internal pull-up resistor.

PWRBTN#

Ring Indicate: From the modem interface. This signal can be enabled as a wake

event; this is preserved across power failures.

RI#

Resume Well Reset: RSMRST# is used for resetting the resume power plane

logic.

RSMRST#

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-7

Signal Description

Table 2-10. Power Management Interface Signals

Name

Type

Description

Suspend Status: This signal is asserted by the ICH2 to indicate that the system

will be entering a low power state soon. This can be monitored by devices with

memory that need to switch from normal refresh to suspend refresh mode. It can

also be used by other peripherals as an indication that they should isolate their

outputs that may be going to powered-off planes. This signal is called LPCPD# on

the LPC interface.

SUS_STAT# /

LPCPD#

C3_STAT# /

GPIO[21]

(ICH2-M only)

C3_STAT#: This ICH2-M signal is typically configured as C3_STAT#. It is used for

indicating to an AGP device that a C3 state transition is beginning or ending. If

C3_STAT# functionality is not required, this signal can be used as a GPO.

Suspend Clock: This signal is an output of the RTC generator circuit and is used

by other chips for the refresh clock.

SUSCLK

VRMPWRGD

(ICH2)

VRM Power Good (ICH2 and ICH2-M): VRMPWRGD should be connected to be

the processor’s VRM Power Good.

VRMPWRGD/

VGATE

(ICH2-M)

VRM Power Good Gate (ICH2-M): VGATE is used for Intel SpeedStep

technology support. It is an output from the processor’s voltage regulator to

VGATE /

VRMPWRGD

(ICH2-M only)

indicate that the voltage is stable. This signal can go inactive during a Intel

SpeedStep transition. In non-Intel SpeedStep technology systems this

signal should be connected to the processor VRM Power Good.

AGP Bus Busy: This signal supports the C3 state. It provides an indication that the

AGP device is busy. When this signal is asserted, the BM_STS bit will be set. If this

functionality is not needed, this signal may be configured as a GPI.

AGPBUSY#

(ICH2-M only)

Stop PCI Clock: This signal is an output to the external clock generator to turn off

the PCI clock. It is used to support PCI CLKRUN# protocol. If this functionality is

not needed, this signal can be configured as a GPO.

STP_PCI#

(ICH2-M only)

Stop CPU Clock: Output to the external clock generator to turn off the processor

clock. It is used to support the C3 state. If this functionality is not needed, this

signal can be configured as a GPO.

STP_CPU#

(ICH2-M only)

Battery Low: Input from battery to indicate that there is insufficient power to boot

the system. Assertion prevents wake from S1–S5 state. This signal can also be

enabled to cause an SMI# when asserted. In desktop configurations this signal

should be pulled high to VccSUS.

BATLOW#

(ICH2-M only)

CPU Performance: This signal is used for Intel SpeedStep technology

support. It selects which power state to put the processo in. If this functionality is

not needed, this signal can be configured as a GPO. This is an open-drain output

signal and requires an external pull-up to the processor I/O voltage.

CPUPERF#

(ICH2-M only)

SpeedStep Mux Select: This signal is used for Intel SpeedStep technology

support. It selects the voltage level for the processor. If this functionality is not

needed, this signal can be configured as a GPO.

SSMUXSEL

(ICH2-M only)

2-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

2.11

Processor Interface

Table 2-11. Processor Interface Signals

Name

Type

Description

Mask A20: A20M# goes active based on setting the appropriate bit in the Port 92h

A20M#

Speed Strap: During the reset sequence, ICH2 drives A20M# high if the

corresponding bit is set in the FREQ_STRP register.

Processor Sleep: This signal puts the processor into a state that saves

substantial power compared to Stop-Grant state. However, during that time, no

snoops occur. The ICH2 can optionally assert the CPUSLP# signal when going to

the S1 state.

CPUSLP#

FERR#

Numeric Coprocessor Error: This signal is tied to the coprocessor error signal

on the processor. FERR# is only used if the ICH2 coprocessor error reporting

function is enabled in the General Control Register (Device 31:Function 0, Offset

D0, bit 13). If FERR# is asserted, the ICH2 generates an internal IRQ13 to its

interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that

IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires

an external weak pull-up to ensure a high level when the coprocessor error

function is disabled.

Ignore Numeric Error: This signal is connected to the ignore error pin on the

processor. IGNNE# is only used if the ICH2 coprocessor error reporting function is

enabled in the General Control Register (Device 31:Function 0, Offset D0,

bit 13). If FERR# is active, indicating a coprocessor error, a write to the

Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE#

remains asserted until FERR# is negated. If FERR# is not asserted when the

Coprocessor Error Register is written, the IGNNE# signal is not asserted.

IGNNE#

Speed Strap: During the reset sequence, ICH2 drives IGNNE# high if the

corresponding bit is set in the FREQ_STRP register.

Initialization: INIT# is asserted by the ICH2 for 16 PCI clocks to reset the

processor. ICH2 can be configured to support processor BIST. In that case, INIT#

will be active when PCIRST# is active.

INIT#

INTR

Processor Interrupt: INTR is asserted by the ICH2 to signal the processor that

an interrupt request is pending and needs to be serviced. It is an asynchronous

output and normally driven low.

Speed Strap: During the reset sequence, ICH2 drives INTR high if the

corresponding bit is set in the FREQ_STRP register.

Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the

processor. The ICH2 can generate an NMI when either SERR# or IOCHK# is

asserted. The processor detects an NMI when it detects a rising edge on NMI.

NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI

Status and Control Register.

NMI

Speed Strap: During the reset sequence, ICH2 drives NMI high if the

corresponding bit is set in the FREQ_STRP register.

System Management Interrupt: SMI# is an active low output synchronous to

PCICLK. It is asserted by the ICH2 in response to one of many enabled hardware

or software events.

SMI#

Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK.

It is asserted by the ICH2 in response to one of many hardware or software

events. When the processor samples STPCLK# asserted, it responds by stopping

its internal clock.

STPCLK#

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-9

Signal Description

Table 2-11. Processor Interface Signals (Continued)

Name

Type

Description

Keyboard Controller Reset Processor: The keyboard controller can generate

INIT# to the processor. This saves the external OR gate with the ICH2’s other

sources of INIT#. When the ICH2 detects the assertion of this signal, INIT# is

generated for 16 PCI clocks..

Note

RCIN#

82801BA ICH2: The 82801BA ignores RCIN# assertion during transitions to the

S3, S4 and S5 states.

82801BAM ICH2-M: The 82801BAM ignores RCIN# assertion during transitions

to the S1, S3, S4 and S5 states.

A20 Gate: This signal is from the keyboard controller. It acts as an alternative

method to force the A20M# signal active. A20GATE saves the external OR gate

needed with various other PCIsets.

A20GATE

Processor Power Good (82801BA ICH2): This signal should be connected to

the processor’s PWRGOOD input. This is an open-drain output signal (external

pull-up resistor required) that represents a logical AND of the ICH2’s PWROK and

VRMPWRGD signals.

CPU Power Good (82801BAM ICH2-M): This signal should be connected to the

CPUPWRGD

processor’s PWRGOOD input. For Intel SpeedStep™ technology support, this

signal is kept high during a Intel SpeedStep™ technology state transition to

prevent loss of processor context. This is an open-drain output signal (external

pull-up resistor required) that represents a logical AND of the ICH2-M’s PWROK

and VGATE / VRMPWRGD signals.

2.12

SMBus Interface

Table 2-12. SM Bus Interface Signals

Name

Type

Description

SMBus Data: External pull-up is required.

SMBDATA

SMBCLK

I/OD

SMBus Clock: External pull-up is required.

SMBALERT#/

GPIO[11]

SMBus Alert: This signal is used to wake the system or generate an SMI#. If not

used for SMBALERT#, it can be used as a GPI.

2.13

System Management Interface

Table 2-13. System Management Interface Signals

Name

Type

Description

Intruder Detect: This signal can be set to disable system if box detected open.

This signal’s status is readable, so it can be used like a GPI if the Intruder

Detection is not needed.

INTRUDER#

System Management Link: These signals are an SMBus link to an optional

external system management ASIC or LAN controller. External pull-ups are

required.

SMLINK[1:0]

I/OD

Note that SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1]

corresponds to an SMBus Data signal.

2-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

2.14

2.15

Real Time Clock Interface

Table 2-14. Real Time Clock Interface

Name

Type

Description

Crystal Input 1: This signal is connected to the 32.768 KHz crystal. If no

external crystal is used, then RTCX1 can be driven with the desired clock rate.

RTCX1

Special

Crystal Input 2: This signal is connected to the 32.768 KHz crystal. If no

external crystal is used, then RTCX2 should be left floating.

RTCX2

Special

Other Clocks

Table 2-15. Other Clocks

Name

Type

Description

Oscillator Clock: CLK14 is used for 8254 timers and runs at 14.31818 MHz.

82801BA ICH2: This clock is permitted to stop during S3 (or lower) states.

82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states.

CLK14

CLK48

CLK66

48 MHz Clock: CLK48 is used to for the USB controller and runs at 48 MHz.

82801BA ICH2: This clock is permitted to stop during S3 (or lower) states.

82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states.

66 MHz Clock: CLK66 is used to for the hub interface and runs at 66 MHz.

82801BA ICH2: This clock is permitted to stop during S3 (or lower) states.

82801BAM ICH2-M: This clock is permitted to stop during S1 (or lower) states.

2.16

Miscellaneous Signals

Table 2-16. Miscellaneous Signals

Name

Type

Description

Speaker: The SPKR signal is the output of counter 2 and is internally "ANDed"

with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external

speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its

output state is 1.

SPKR

Note: SPKR is sampled at the rising edge of PWROK as a functional strap. See

Section 2.20.1for more details.

RTC Reset: When asserted, this signal resets register bits in the RTC well and

sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This signal is also

used to enter the test modes documented in Section 2.20.2.

RTCRST#

Note: Clearing CMOS in an ICH2-based platform can be done by using a jumper

on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not

attempt to clear CMOS by using a jumper to pull VccRTC low.

TP0

(ICH2 0nly)

Test Point (82801BA ICH2): This signal must have an external pull-up to

VccSus3_3.

Functional Strap: This signal is reserved for future use. There is an internal pull-

up resistor on this signal.

FS0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-11

Signal Description

2.17

AC’97 Link

Table 2-17. AC’97 Link Signals

Name

Type

Description

AC_RST#

AC_SYNC

AC97 Reset: Master H/W reset to external Codec(s)

AC97 Sync: 48 KHz fixed rate sample sync to the Codec(s)

AC97 Bit Clock: 12.288 MHz serial data clock generated by the external

Codec(s). See Note.

AC_BIT_CLK

AC97 Serial Data Out: Serial TDM data output to the Codec(s)

AC_SDOUT

Note: AC_SDOUT is sampled at the rising edge of PWROK as a functional

strap. See Section 2.20.1 for more details.

AC_SDIN[1:0]

AC97 Serial Data In 0: Serial TDM data inputs from the Codecs. See Note.

NOTE: If the ACLINK Shutoff bit in the AC’97 Global Control Register (See Section 13.2.8) is set to 1, internal

pull-down resistors will be enabled on AC_BIT_CLK and AC_SDATA_IN[1:0]. If ACLINK Shutoff is

cleared to 0, these pull-down resistors are disabled. If there is no codec down on the system board, the

two signals AC_SDIN[1:0] should be pulled down externally with a resistor to ground.

2.18

General Purpose I/O

Table 2-18. General Purpose I/O Signals

Name

GPIO[31:29]

Type

Description

Not implemented.

GPIO[28:27]

GPIO[26]

I/O

Can be input or output. Resume power well. Unmuxed.

Not implemented.

GPIO[25]

Can be input or output. Resume power well. Not Muxed.

GPIO[24]

I/O

Can be input or output. Resume power well.

Fixed as Output only. Main power well.

(ICH2 only)

GPIO[23]

(ICH2 only)

GPIO[22]

Fixed as Output only. Main power well. Open-drain output.

Fixed as Output only. Main power well.

(ICH2 only)

GPIO[21]

GPIO[20:18]

(ICH2 only)

Fixed as Output only. Main power well.

Fixed as Output only. Main Power Well. Can instead be used for PC/PCI

GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#. Integrated

pull-up resistor.

GPIO[17:16]

GPIO[15:14]

GPIO[13:12]

GPIO[11]

Not implemented.

Fixed as Input only. Resume Power Well. Not muxed.

Fixed as Input only. Resume Power Well. Can instead be used for SMBALERT#.

Not implemented.

GPIO[10:9]

GPIO[8]

Fixed as Input only. Resume Power Well. Not muxed.

Fixed as Input only. Main power well. Not muxed.

GPIO[7]

GPIO[6]

Fixed as Input only. Main power well.

(ICH2 only)

2-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

Table 2-18. General Purpose I/O Signals (Continued)

Name

Type

Description

GPIO[5]

GPIO[4:3]

GPIO[2]

Not implemented.

Fixed as Input only. Main power well. Can be used instead as PIRQ[G:F]#.

Not implemented.

Fixed as Input only. Main Power Well. Can instead be used for PC/PCI

REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#.

GPIO[1:0]

2.19

Power and Ground

Table 2-19. Power and Ground Signals

Name

Description

Vcc3_3

Vcc1_8

3.3V supply for Core well I/O buffers. This power may be shut off in S3, S5 or G3 states.

1.8V supply for Core well logic. This power may be shut off in S3, S5 or G3 states.

Reference for 5V tolerance on Core well inputs. This power may be shut off in S3, S5 or

G3 states.

V5REF

HUBREF

0.9V reference for the hub interface. This power may be shut off in S3, S5 or G3 states.

3.3V supply for Resume well I/O buffers. This power is not expected to be shut off unless

power is removed.

VccSus3_3

VccSus1_8

•

82801BA ICH2: The system is unplugged.

82801BAM ICH2-M: The main battery is removed or completely drained and AC

power is not available.

1.8V supply for Resume well logic. This power is not expected to be shut off unless power

is removed.

•

82801BA ICH2: The system is unplugged.

82801BAM ICH2-M: The main battery is removed or completely drained and AC

power is not available.

Reference for 5V tolerance on Resume well inputs. This power is not expected to be shut

off unless power is removed.

•

82801BA ICH2: The system is unplugged. Note that V5REF_SUS only affects 5V

tolerance for the USB OC[3:0]# pins and can be connected to VccSUS3_3 if 5V

tolerance on these signals is not required.

V5REF_SUS

VccRTC

•

82801BAM ICH2-M: The main battery is removed or completely drained and AC

power is not available.

3.3V (can drop to 2.0V min. in G3 state) supply for the RTC well. This power is not

expected to be shut off unless the RTC battery is removed or completely drained.

Note: Implementations should not attempt to clear CMOS by using a jumper to pull

VccRTC low. Clearing CMOS in an ICH2-based platform can be done by using a jumper

on RTCRST# or GPI, or using SAFEMODE strap.

3.3V supply for LAN Connect interface buffers. This is a separate power plane that may or

may not be energized in S3–S5 states depending upon the presence or absence of AC

power and network connectivity. This plane must be on in S0 and S1.

VccLAN3_3

(ICH2-M only)

1.8V supply for LAN controller logic. This is a separate power plane that may or may not

be energized in S3–S5 states depending upon the presence or absence of AC power and

network connectivity. This plane must be on in S0 and S1.

VccLAN1_8

(ICH2-M only)

RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is

mirrored throughout the oscillator and buffer circuitry. See Section 2.20.3.

VBIAS

processor interface outputs.

V_CPU_IO

Vss

Grounds.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-13

Signal Description

2.20

Pin Straps

2.20.1

Functional Straps

The following signals are used for static configuration. They are sampled at the rising edge of

PWROK to select configurations and then revert later to their normal usage. To invoke the

associated mode, the signal should be driven at least 4 PCI clocks prior to the time it is sampled.

Table 2-20. Functional Strap Definitions

When

Sampled

Signal

Usage

Comment

The signal has a weak internal pull-down. If the signal is sampled

high, the ICH2 sets the processor speed strap pins for safe mode.

Refer to processor specification for speed strapping definition. The

status of this strap is readable via the SAFE_MODE bit (bit 2, D31:

F0, Offset D4h).

Rising

Edge of

PWROK

SAFE

MODE

AC_SDOUT

System designers should include a placeholder for a pull-down

resistor on EE_DOUT but do not populate the resistor.

EE_DOUT Reserved

System designers should include a placeholder for a pull-down

resistor on FS[0] but do not populate the resistor.

FS[0]

Reserved

The signal has a weak internal pull-up. If the signal is sampled low,

the system is strapped to the “Top-Swap” mode (ICH2 will invert A16

for all cycles targeting FWH BIOS space). The status of this strap is

readable via the Top-Swap bit (bit 13, D31: F0, Offset D4h). Note that

software will not be able to clear the Top-Swap bit until the system is

rebooted without GNT[A]# being pulled down.

Rising

Edge of

PWROK

Top-Swap

Override

GNT[A]#

If this signal is sampled high (via an external pull-up to VCC1_8), the

normal hub interface buffer mode will be selected. If this signal is

sampled low (via an external pull-down), the enhanced hub interface

buffer mode will be selected.

Enhanced

Hub

Interface

Mode

During

PCIRST#

assertion

HLCOMP

SPKR

See the specific platform design guide for resistor values and routing

guidelines for each hub interface mode.

The signal has a weak internal pull-up. If the signal is sampled low,

the system is strapped to the “No Reboot” mode (ICH2 will disable

the TCO Timer system reboot feature). The status of this strap is

readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h).

Rising

Edge of

PWROK

Reboot

2-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Signal Description

2.20.2

Test Signals

2.20.2.1

Test Mode Selection

When PWROK is active (high), driving RTCRST# low for a number of PCI clocks (33 MHz) will

activate a particular test mode as specified in Table 2-21.

Note: RTCRST# may be driven low any time after PCIRST is inactive. Refer to Chapter 17, “Testability”

for a detailed description of the ICH2 test modes.

Table 2-21. Test Mode Selection

Number of PCI Clocks RTCRST#

Test Mode

driven low after PWROK active

No Test Mode Selected

XOR Chain 1

XOR Chain 2

XOR Chain 3

XOR Chain 4

All “Z”

9–24

>24

Reserved. DO NOT ATTEMPT

No Test Mode Selected

2.20.2.2

Test Straps (82801BA ICH2 only)

The ICH2’s TP[0] (Test Point) signal must be pulled to VccSus3_3 with an external pull-up

resistor.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-15

Signal Description

2.20.3

External RTC Circuitry

To reduce RTC well power consumption, the ICH2 implements an internal oscillator circuit that is

sensitive to step voltage changes in VccRTC and VBIAS. Figure 2-1 shows a schematic diagram of

the circuitry required to condition these voltages to ensure correct operation of the ICH2 RTC.

Figure 2-1. Required External RTC Circuit

3.3V

VCCSUS

VCCRTC

RTCX2

RTCX1

VBIAS

1 k

Ω

1 µF

32768 Hz

Xtal

10 M

1 k

Vbatt

Ω

0.047 uF

12.5 pF

10 M

Ω

12.5 pF

VSSRTC

Note: Capacitor C2 and C3 values are crystal-dependent.

2.20.4

V5REF / Vcc3_3 Sequencing Requirements

V5REF and V5REF_Sus are the reference voltages for 5V tolerance on inputs to the ICH2. V5REF

and V5REF_Sus must power up before or simultaneous to Vcc3_3 and VccSus3_3 respectively,

and must power down after or simultaneous to Vcc3_3 and VccSus3_3 respectively. Refer to

Figure 2-2 for an example circuit schematic that may be used to ensure proper V5REF sequencing.

Note that separate circuits must be implemented for both the Core and Suspend well supplies.

Figure 2-2. Example V5REF Sequencing Circuit

VCC Supply

(3.3V)

5V Supply

Schottky

Diode

1 uF

To System

5VREF

To System

2-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Power Planes and Pin States

3.1

Power Planes

Table 3-1. ICH2 Power Planes

Plane

Description

Main I/O

(3.3V)

Vcc3_3: Powered by the main power supply (or battery for the ICH2-M). When the

system is in the S3, S4, S5, or G3 state, this plane is assumed to be shut off.

Main Logic

(1.8V)

Vcc1_8: Powered by the main power supply (or battery for the ICH2-M). When the

system is in the S3, S4, S5, or G3 state, this plane is assumed to be shut off.

VccSUS3_3: Powered by the main power supply (or battery for the ICH2-M) in S0–S1

states. Powered by the trickle power supply (or battery for the ICH2-M) when the

system is in the S3, S4, S5, state. Assumed to be shut off only when in the G3 state

(system is unplugged for the ICH2 or battery removed for the ICH2-M).

Resume I/O

(3.3V Standby)

VccSUS1_8: Powered by the main power supply (or battery for the ICH2-M) in S0–S1

states. Powered by the trickle power supply (or battery for the ICH2-M) when the

system is in the S3, S4, S5, state. Assumed to be shut off only when in the G3 state

(system is unplugged for the ICH2 or batter removed for the ICH2-M).

Resume Logic

(1.8V Standby)

Processor Interface V_CPU_IO: Powered by the main power supply via processor voltage regulator. When

(1.3 ~ 2.5V)

the system is in the S3, S4, S5, or G3 state, this plane is assumed to be shut off.

LAN I/O

(3.3V)

(ICH2-M only)

VccLAN3_3: This is a separate power plane that may or may not be energized in S3 -

S5 states depending upon the presence or absence of AC power and network

connectivity. This plane must be on in the S0 and S1 states.

LAN Logic

(1.8V)

(ICH2-M only)

VccLAN1_8: This is a separate power plane that may or may not be energized in S3 -

S5 states depending upon the presence or absence of AC power and network

connectivity. This plane must be on in the S0 and S1 states.

VccRTC: When other power is available (from the main supply for the ICH2 or battery

for the ICH2-M), external diode coupling will provide power to reduce the drain on the

RTC battery. Assumed to operate from 3.3V down to 2.0V.

RTC

3.2

Integrated Pull-Ups and Pull-Downs

Table 3-2. Integrated Pull-Up and Pull-Down Resistors

Signal

Resistor Type

Nominal Value

Notes

EE_DIN

pull-up

pull-down

24 KΩ

20 KΩ

EE_DOUT

GNT[B:A]# / GNT[5]# / GPIO[17:16]

LAD[3:0]# / FWH[3:0]#

LDRQ[1:0]

PME#

PWRBTN#

SPKR

1, 5

2, 6

AC_BITCLK

82801BA ICH2 and 82801BAM ICH2-M Datasheet

3-1

Power Planes and Pin States

Table 3-2. Integrated Pull-Up and Pull-Down Resistors (Continued)

Signal

Resistor Type

Nominal Value

Notes

AC_SDIN[0]

AC_SDIN[1]

AC_SDOUT

AC_SYNC

pull-down

pull-up

20 KΩ

9 KΩ

2, 6

LAN_RXD[2:0]

PDD[7] / SDD[7]

pull-down

5.9 KΩ

PDDREQ / SDDREQ

NOTES:

1. Simulation data shows that these resistor values can range from 18 KΩ to 42 KΩ.

2. Simulation data shows that these resistor values can range from 13 KΩ to 38 KΩ.

3. Simulation data shows that these resistor values can range from 6 KΩ to 14 KΩ.

4. Simulation data shows that these resistor values can range from 4.3 KΩ to 20 KΩ.

5. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

6. This pull-down is only enabled when the ACLINK Shut Off bit in the AC’97 Global Control Register is set to 1.

3.3

IDE Integrated Series Termination Resistors

Table 3-3 shows the ICH2 IDE signals that have integrated series termination resistors.

Table 3-3. IDE Series Termination Resistors

Signal

Integrated Series Termination Resistor Value

PDD[15:0], SDD[15:0], PDIOW#, SDIOW#,

PDIOR#, PDIOW#, PDREQ, SDREQ,

PDDACK#, SDDACK#, PIORDY, SIORDY,

PDA[2:0], SDA[2:0], PDCS1#, SDCS1#,

PDCS3#, SDCS3#, IRQ14, IRQ15

approximately 33 Ω (See Note)

NOTE: Simulation data indicates that the integrated series termination resistors are a nominal 33 Ω but can

range from 31 Ω to 43 Ω.

3.4

Output and I/O Signals Planes and States

Table 3-4 shows the power plane associated with the output and I/O signals, as well as the state at

various times. Within the table, the following terms are used:

“High-Z”

“High”

Tri-state. ICH2 not driving the signal high or low.

ICH2 is driving the signal to a logic ‘1’

“Low”

ICH2 is driving the signal to a logic ‘0’

“Defined”

“Undefined”

“Running”

“Off”

Driven to a level that is defined by the function (will be high or low)

ICH2 is driving the signal, but the value is indeterminate.

Clock is toggling or signal is transitioning because function not stopping

The power plane is off, so ICH2 is not driving

Note that the signal levels are the same in S4 and S5.

3-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Power Planes and Pin States

Table 3-4.

Power Plane and States for Output and I/O Signals

Power

Plane

Immediately

after Reset

(ICH2-M)

Signal Name

Reset Signal

During Reset

S4/S5

PCI Bus

AD[31:0]

C/BE#[3:0]

CLKRUN# (ICH2-M)

DEVSEL#

FRAME#

Main I/O

Resume I/O

Main I/O

PCIRST#

RSMRST#

PCIRST#

High-Z

Low

Undefined

Low

Defined

High-Z

High

Defined

Off

Low

Off

Low

Off

High-Z

High

High-Z

High

High-Z

High

GNT[0:5]#

GNT[A:B]#

IRDY#, TRDY#

PAR

High-Z

Low

High

High-Z

Undefined

High

High-Z

Defined

High

High-Z

Defined

High

PCIRST#

PERR#

High-Z

PLOCK#

STOP#

LPC Interface

LAD[3:0]

Main I/O

PCIRST#

High

Defined

High

Off

LFRAME#

LAN Connect and EEPROM Interface

RSM_PWROK

(ICH2)

LAN_PWROK

(ICH2-M)

EE_CS

EE_DOUT

LAN I/O

Low

High

Low

High

Low

Running

Defined

Note 4

RSM_PWROK

(ICH2)

LAN_PWROK

(ICH2-M)

RSM_PWROK

(ICH2)

LAN_PWROK

(ICH2-M)

EE_SHCLK

RSM_PWROK

(ICH2)

LAN_PWROK

(ICH2-M)

LAN_RSTSYNC

LAN_TXD[2:0]

RSM_PWROK

(ICH2)

LAN_PWROK

(ICH2-M)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

3-3

Power Planes and Pin States

Table 3-4.

Power Plane and States for Output and I/O Signals (Continued)

Power

Plane

Immediately

after Reset

(ICH2-M)

Signal Name

Reset Signal

During Reset

S4/S5

IDE Interface

PDA[2:0], SDA[2:0]

PDCS1#, PDCS3#

PDD[15:0], SDD[15:0]

PDDACK#, SDDACK#

PDIOR#, PDIOW#

SDCS1#, SDCS3#

SDIOR#, SDIOW#

Main I/O

PCIRST#

Low

High

High-Z

High

Undefined

High

Undefined

High

Driven

High

High-Z

Off

High-Z

High

Defined

High

Off

High

Off

High

Off

Interrupts

PIRQ[A:H]#

SERIRQ

Main I/O

PCIRST#

High-Z

Defined

Running

High-Z

Off

APICD[1:0]

USB Interface

USBP[3:0][P:N]

Resume I/O

RSMRST#

High-Z

Power Management

CPUPERF# (ICH2-M)

Main I/O

PCIRST#

High-Z

High

High-Z

Defined

Low

Defined

Low

Off

C3_STAT# / GPIO[21]

(ICH2-M)

High

SSMUXSEL (ICH2-M)

SLP_S1# (ICH2-M)

SLP_S3#

Main I/O

PCIRST#

RSMRST#

PCIRST#

RSMRST#

Low

High

Low

High

Defined

High

Defined

Low

Off

Low

High

Low

Resume I/O

Main I/O

High

Low

SLP_S5#

High

STP_PCI# (ICH2-M)

STP_CPU# (ICH2-M)

SUS_STAT#

Defined

Low

Main I/O

Low

Resume I/O

Low

SUSCLK

Running

Processor Interface

A20M#

CPU I/O

Main I/O

PCIRST#

See Note 1

See Note 3

High

Defined

High-Z

High

Off

CPUPWRGD

High-Z

Defined

(ICH2)

CPUSLP#

CPU I/O

PCIRST#

High

Off

Low (ICH2-M)

IGNNE#

INIT#

CPU I/O

PCIRST#

See Note 1

High

Low

High

Off

High

INTR

See Note 1

High

Defined

Low

NMI

Low

SMI#

High

STPCLK#

High

Low

3-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Power Planes and Pin States

Table 3-4.

Power Plane and States for Output and I/O Signals (Continued)

Power

Plane

Immediately

after Reset

(ICH2-M)

Signal Name

Reset Signal

During Reset

S4/S5

SMBus Interface

SMBCLK, SMBDATA

SMLINK[1:0]

Resume I/O

RSMRST#

High-Z

Defined

System Management Interface

High-Z High-Z

Miscellaneous Signals

High-Z with

Low

SPKR

Main I/O

PCIRST#

Defined

Off

internal pull-up

AC’97 Interface

Cold Reset Bit

(High)

AC_RST#

Resume I/O

RSMRST#

Low

High

Low

AC_SDOUT

AC_SYNC

Main I/O

PCIRST#

Low

Running

Low

Off

Unmuxed GPIO Signals

GPIO[18] (ICH2)

GPIO[19:20] (ICH2)

GPIO[21] (ICH2)

GPIO[22] (ICH2)

GPIO[23] (ICH2)

GPIO[24] (ICH2)

GPIO[25]

Main I/O

PCIRST#

RSMRST#

High

See Note 2

—

Defined

Off

High

High-Z

Low

Main I/O

High

—

Off

Main I/O

High-Z

Low

—

Off

Main I/O

—

Off

Resume I/O

High-Z

HIgh-Z

High

—

Defined

GPIO[27:28]

NOTES:

1. ICH2 and ICH2-M: The ICH2/ICH2-M sets these signals at reset for processor frequency strap.

2. ICH2 and ICH2-M: GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH2 comes out of reset

3. ICH2 and ICH2-M: CPUPWRGD is an open-drain output that represents a logical AND of the ICH2’s VRMPWRGD

(VGATE / VRMPWRGD for the ICH2-M) and PWROK signals and, thus, are driven low by ICH2/ICH2-M when either

VRMPWRGD (VGATE / VRMPWRGD for the ICH2-M) or PWROK are inactive. During boot, or during a hard reset with power

cycling, CPUPWRGD will be expected to transition from low to High-Z.

4. ICH2-M Only: LAN Connect and EEPROM signals will either be "Defined" or "Off" in S3–S5 states depending on whether or

not the LAN power planes are active.

5. GPIO[24:25, 27:28] for the ICH2 and GPIO[25, 27:28] for the 82801BAM ICH2-M: These signals remain tri-stated for up to

110 ms after RSMRST# deassertion. At this point, they will be driven to their default (High) state.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

3-5

Power Planes and Pin States

3.5

Power Planes for Input Signals

Table 3-5 shows the power plane associated with each input signal, as well as what device drives

the signal at various times. Valid states include:

• High

• Low

• Static: Will be high or low, but will not change

• Driven: Will be high or low, and is allowed to change

• Running: For input clocks

Table 3-5. Power Plane for Input Signals

(ICH2-M)

Signal Name

Power Well

Driver During Reset

BATLOW#

(ICH2-M)

Resume I/O

Power Supply

High

A20GATE

AC_BIT_CLK

AC_SDIN[1:0]

Main I/O

External Microcontroller

AC’97 Codec

Static

Driven

Static

Low

Resume I/O

AC’97 Codec

Low

AGPBUSY#

(ICH2-M)

Main I/O

AGP Component

Driven

High

Low

APICCLK

CLK14

Main I/O

Main Logic

LAN I/O

Main I/O

RTC

Clock Generator

EEPROM component

CPU

Running

Driven

Low

CLK48

Low

CLK66

Low

EE_DIN

Driven

Static

Driven

Static

Driven

Note 1

Low

Note 1

Low

FERR#

Static

INTRUDER#

IRQ[15:14]

LAN_CLK

External Switch

IDE

Driven

Low

Driven

Low

Main I/O

LAN I/O

Driven

LAN Connect component

Driven

Note 1

RSM_PWROK

(ICH2)

External RC Circuit (ICH2)

Power Supply (ICH2-M)

Resume I/O

High

Static

LAN_PWROK

(ICH2-M)

LAN_RXD[2:0]

LDRQ[0]#

LDRQ[1]#

OC[3:0]#

PCICLK

LAN I/O

Main I/O

LAN Connect component

LPC Devices

Driven

Running

Driven

Static

Driven

High

Note 1

Low

Note 1

Low

Main I/O

LPC Devices

High

Low

Resume I/O

Main I/O

External Pull-Ups

Clock Generator

IDE Device

Driven

Low

Driven

Low

Driven

Low

PDDREQ

PIORDY

Main I/O

Static

Driven

High

Low

Main I/O

IDE Device

Low

PME#

Resume I/O

Main I/O

Internal Pull-Up

System Power Supply

External Microcontroller

PCI Master

Driven

High

Driven

Low

Driven

Low

PWRBTN#

PWROK

RCIN#

Main I/O

Low

REQ[0:5]#

REQ[B:A]#

Main I/O

Driven

Low

Main I/O

PC/PCI Devices

Low

3-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Power Planes and Pin States

Table 3-5. Power Plane for Input Signals (Continued)

(ICH2-M)

Signal Name

Power Well

Driver During Reset

RI#

Resume I/O

RTC

Serial Port Buffer

External RC circuit

IDE Drive

Driven

High

Driven

High

Driven

High

Low

Driven

High

Low

RSMRST#

RTCRST#

SDDREQ

SERR#

RTC

High

Main I/O

Resume I/O

Main I/O

Driven

Static

High

PCI Bus Peripherals

IDE Drive

Low

SIORDY

Static

Driven

Low

SMBALERT#

THRM#

External pull-up

Thermal Sensor

Driven

Low

Driven

Low

VRMPWRGD

(ICH2)

Main I/O

CPU Voltage Regulator

Driven

High

Low

VGATE /

VRMPWRGD

(ICH2-M)

NOTES:

1. LAN Connect and EEPROM signals will either be "Driven" or "Low" in S3–S5 states depending upon

whether or not the LAN power planes are active.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

3-7

Power Planes and Pin States

This page is intentionally left blank

3-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

System Clock Domains

Table 4-1 shows the system clock domains. Figure 4-2 shows the assumed connection of the

various system components, including the clock generator. For complete details of the system

clocking solution, refer to the system’s clock generator component specification.

Figure 4-1. ICH2 and System Clock Domains

Clock

Domain

Frequency

Source

Usage

Hub interface, processor interface. AGP.

ICH2

CLK66

Main Clock

Generator

66 MHz

82801BA ICH2: It is shut off during S3 or below.

82801BAM ICH2-M: It is shut off during S1 or below.

Free-running PCI Clock to ICH2/ICH2-M.

82801BA ICH2: This clock remains on during S0 and S1

state, and is expected to be shut off during S3 or below.

ICH2

PCICLK

Main Clock

Generator

33 MHz

48 MHz

82801BAM ICH2-M: This clock remains on during S0

state, and is expected to be shut off during S1 or below.

PCI Bus, LPC I/F. These only go to external PCI and

LPC devices.

Main Clock

Generator

System PCI

82801BAM ICH2-M: These will stop based on CLKRUN#

(and STP_PCI#)

Super I/O, USB Controller.

82801BA ICH2: Expected to be shut off during S3 or

below.

ICH2

CLK48

Main Clock

Generator

82801BAM ICH2-M: Expected to be shut off during S1

or below.

Used for ACPI timer.

82801BA ICH2: Expected to be shut off during S3 or

below.

ICH2

CLK14

Main Clock

Generator

14.31818 MHz

82801BAM ICH2-M: Expected to be shut off during S1 or

below.

AC’97 Link. Generated by AC’97 CODEC. Can be shut

off by codec in D3.

ICH2

AC_BIT_CLK

82801BA ICH2: Expected to be shut off during S3 or

below.

12.288 MHz

32.768 kHz

33.33 MHz

AC’97 Codec

ICH2

82801BAM ICH2-M: Expected to be shut off during S1 or

below.

RTC, Power Management. ICH2 has its own oscillator.

Always running, even in G3 state.

RTC

Used for ICH2/ICH2-M processor interrupt messages.

Runs at 33.33 MHz.

ICH2

APICCLK

Main Clock

Generator

82801BA ICH2: Expected to be shut off during S3 or

below.

82801BAM ICH2-M: Expected to be shut off during S1 or

below.

Generated by the LAN Connect component.

82801BA ICH2: Expected to be shut off during S3 or

below.

LAN Connect

Component

LAN_CLK

0.8 to 50 MHz

82801BAM ICH2-M: Expected to be shut off during S1 or

below.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

4-1

System Clock Domains

Figure 4-2. Conceptual System Clock Diagram (82801BA ICH2 and 82801BAM ICH2-M)

Hclock(s) (66/100/133 MHz)

Processor(s)

HClock (66/100/133 MHz)

AGP Clock (66 MHz)

AGP

Host

Controller

AGP Clock (66 MHz)

RDRAM

Clock

Memory

Generator

66 MHz

33 MHz

2 or 3

APIC CLK

14.31818 MHz

48 MHz

Clock

Generator

PCI Clocks

(33 MHz)

ICH2

14.31818 MHz

48 MHz

STP_CPU# (ICH2-M only)

STP_PCI# (ICH2-M only)

SLP_S1# (ICH2-M only)

12.288 MHz

AC'97 Codec(s)

LAN Connect

50 MHz

32 kHz

XTAL

SUSCLK# (32 kHz)

4-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.1

Hub Interface to PCI Bridge (D30:F0)

The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the

ICH2 implements the buffering and control logic between PCI and the hub interface. The

arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must

decode the ranges for the hub interface. All register contents will be lost when core well power is

removed.

5.1.1

PCI Bus Interface

The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals

are 5V tolerant. The ICH2 integrates a PCI arbiter that supports up to six external PCI bus masters

in addition to the internal ICH2 requests.

Note that most transactions targeted to the ICH2 will first appear on the external PCI bus before

being claimed back by the ICH2. The exceptions are I/O cycles involving USB, IDE, and AC’97.

These transactions will complete over the hub interface without appearing on the external PCI bus.

Configuration cycles targeting USB, IDE or AC’97 will appear on the PCI bus. If the ICH2 is

programmed for positive decode, the ICH2 will claim the cycles appearing on the external PCI bus

in medium decode time. If the ICH2 is programmed for subtractive decode, the ICH2 will claim

these cycles in subtractive time. If the ICH2 is programmed for subtractive decode, these cycles

can be claimed by another positive decode agent out on PCI. This architecture enables the ability to

boot off of a PCI card that positively decodes the boot cycles. To boot off a PCI card it is necessary

to keep the ICH2 in subtractive decode mode. When booting off a PCI card, the BOOT_STS bit

(bit 2, TCO2 Status Register) will be set.

For the 82801BAM ICH2-M, devices on the ICH2-M PCI bus (other than the ICH2-M) are not

permitted to assert the PLOCK# signal.

Note: The ICH2’s AC’97, IDE, and USB Controllers can not access PCI address ranges.

Note: PCI devices that cause long latencies (numerous retries) to processor-to-PCI Locked cycles may

starve isochronous transfers between USB or AC’97 devices and memory. This will result in

overrun or underrun, causing reduced quality of the isochronous data (e.g., audio).

Note: PCI configuration write cycles, initiated by the processor, with the following characteristics will be

converted to a Special Cycle with the Shutdown message type.

• Device Number (AD[15:11]) = ‘11111’

• Function Number (AD[10:8]) = ‘111’

• Register Number (AD[7:2]) = ‘000000’

• Data = 00h

• Bus number matches secondary bus number

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-1

Functional Description

Note: If the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the ICH2 will not

allow upstream requests to be performed until the cycle completion. This may be critical for

isochronous buses that assume certain timing for their data flow (e.g., AC’97 or USB). Devices on

these buses may suffer from underrun if the asynchronous traffic is too heavy. Underrun means that

the same data is sent over the bus while ICH2 is not able to issue a request for the next data. Snoop

cycles are not permitted while the front side bus is locked.

Note: Locked cycles are assumed to be rare. Locks by PCI targets are assumed to exist for a short

duration (a few microseconds at most). If a system has a very large number of locked cycles and

some that are very long, the system will definitely experience underruns and overruns. The units

most likely to have problems are the AC'97 controller and the USB controller. Other units could get

underruns/overruns, but are much less likely. The IDE controller (due to its stalling capability on

the cable) should not get any underruns or overruns.

Note: The ICH2 was designed to provide high performance support to PCI peripherals using its data

prefetch capabilities. If a PCI master is burst reading and is disconnected by the ICH2 to pre-fetch

the requested cache line, the ICH2 will Delay Transaction the cycle while it prefetches more data,

and give the bus to another agent. Once the bus is given back to this bus master, if it does not return

with the successive previously requested read address, which was prefetched by the ICH2, the

ICH2 will keep retrying the bus master until either it comes back for the prefetched data, or the

Delayed Transaction Discard Timer expires (1024 PCI clocks) before discarding this prefetched

data and servicing the request. This induces long latencies to PCI bus masters that behave this way.

To reduce this latency, the Discard Timer Mode bit (D30:F0;CNF(50-51h):[bit-2]) can be set to 1.

This will reduce the discard timer from 1024 PCI clocks (32 us) to 128 clocks (4 us) and improve

latency for masters with this behavior.

5.1.2

5.1.3

PCI-to-PCI Bridge Model

From a software perspective, the ICH2 contains a PCI-to-PCI bridge. This bridge connects the hub

interface to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH2 can have its

decode ranges programmed by existing plug-and-play software such that PCI ranges do not

conflict with AGP and graphics aperture ranges in the Host controller.

IDSEL to Device Number Mapping

When addressing devices on the external PCI bus (with the PCI slots), the ICH2 asserts one address

signal as an IDSEL. When accessing device 0, the ICH2 asserts AD16. When accessing Device 1,

the ICH2 asserts AD17. This mapping continues up to device 15 where the ICH2 asserts AD31.

Note that the ICH2’s internal functions (AC’97, IDE, USB, and PCI Bridge) are enumerated like

they are on a separate PCI bus (the hub interface) from the external PCI bus. The integrated LAN

Controller is Device 8 on the ICH2’s PCI bus and, hence, uses AD24 for IDSEL

5.1.4

SERR# Functionality

There are several internal and external sources that can cause SERR#. The ICH2 can be

programmed to cause an NMI based on detecting that an SERR# condition has occurred. The NMI

can also be routed to, instead, cause an SMI#. Note that the ICH2 does not drive the external PCI

bus SERR# signal active onto the PCI bus. The external SERR# signal is an input into the ICH2

driven only by external PCI devices. The conceptual logic diagrams in Figure 5-1 and Figure 5-2

illustrate all sources of SERR#, along with their respective enable and status bits. Figure 5-3 shows

how the ICH2 error reporting logic is configured for NMI# generation.

5-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Figure 5-1. Primary Device Status Register Error Reporting Logic

D30:F0 BRIDGE_CNT

[Parity Error Response Enable]

AND

D30:F0 BRIDGE_CNT

[SERR# Enable]

AND

PCI Address Parity Error

D30:F0 PD_STS

[SSE]

D30:F0 CMD

[SERR_EN]

D30:F0 ERR_STS

[SERR_DTT]

D30:F0 CMD

[SERR_EN]

Delayed Transaction Timeout

AND

D30:F0 ERR_CMD

[SERR_DTT_EN]

AND

SERR# Pin

AND

D30:F0 BRIDGE_CNT

[SERR# Enable]

D30:F0 ERR_CMD

[SERR_RTA_EN]

Received Target Abort

D30:F0 ERR_STS

[SERR_RTA]

Figure 5-2. Secondary Status Register Error Reporting Logic

D30:F0 BRIDGE_CNT

[SERR# Enable]

AND

D30:F0 SECSTS

[SSE]

PCI Delayed Transaction Timeout

AND

D31:F0 D31_ERR_CFG

[SERR_DTT_EN]

LPC Device Signaling an Error

IOCHK# via SERIRQ

TCO1_STS

[HUBERR_STS]

D31:F0 D31_ERR_CFG

[SERR_RTA_EN]

AND

Received Target Abort

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-3

Functional Description

Figure 5-3. NMI# Generation Logic

NMI_SC

[IOCHK_NMI_STS]

IOCHK From SERIRQ Logic

AND

NMI_SC

[IOCHK_NMI_EN]

NMI_SC

[SERR#_NMI_STS]

NMI_SC

[PCI_SERR_EN]

AND

D30:F0 SECSTS

[SSE]

D30:F0 PDSTS

To NMI#

Output

and

Gating

Logic

[SSE]

TCO1_STS

[HUBNMI_STS]

AND

TCO1_CNT

[NMI_NOW]

Hub Interface Parity

Error Detected

AND

D30:F0 CMD

[Parity Error Response]

D30:F0 PD_STS

[DPD]

PCI Parity Error detected

during AC'97, IDE or USB

Master Cycle

D30:F0 BRIDGE_CNT

[Parity Error Response

Enable]

D30:F0 SECSTS

[DPD]

NMI_EN

[NMI_EN]

PCI Parity Error detected

during LPC or Legacy DMA

Master Cycle

D31:F0 PCISTA

[DPED]

AND

D31:F0 PCICMD

[PER]

5.1.5

Parity Error Detection

The ICH2 can detect and report different parity errors in the system. The ICH2 can be programmed

to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error. The

conceptual logic diagram in Figure 5-3 details all the parity errors that the ICH2 can detect, along

with their respective enable bits, status bits, and the results.

Note: If NMIs are enabled and parity error checking on PCI is also enabled, then parity errors cause an

NMI. Some operating systems will not attempt to recover from this NMI, since it considers the

detection of a PCI error to be a catastrophic event.

5-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.1.6

Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to contain up to 8

functions with each function containing up to 256 8-bit configuration registers. The PCI

specification defines two bus cycles to access the PCI configuration space: Configuration Read and

Configuration Write. Memory and I/O spaces are supported directly by the processor.

Configuration space is supported by a mapping mechanism implemented within the ICH2. The PCI

specification defines two mechanisms to access configuration space (Mechanism #1 and

Mechanism #2). The ICH2 only supports Mechanism #1.

Configuration cycles for PCI Bus #0 devices #2 through #31, and for PCI Bus numbers greater than

0 will be sent towards the ICH2 from the host controller. The ICH2 compares the non-zero Bus

Number with the Secondary Bus Number and Subordinate Bus number registers of its P2P bridge

to determine if the configuration cycle is meant for Primary PCI or a downstream PCI bus.

Type 0 to Type 0 Forwarding

When a Type 0 configuration cycle is received on the hub interface, the ICH2 forwards these cycles

to PCI and then reclaims them. The ICH2 uses address bits AD[15:14] to communicate the ICH2

device numbers in Type 0 configuration cycles. If the Type 0 cycle on the hub interface specifies

any device number other than 30 or 31, the ICH2 will not set any address bits in the range

AD[31:11] during the corresponding transaction on PCI. Table 5-1 shows the device number

translation.

Table 5-1. Type 0 Configuration Cycle Device Number Translation

Device # In Hub Interface Type 0

AD[31:11] During Address Phase of Type 0 Cycle on PCI

Cycle

0 through 29

0000000000000000_00000b

0000000000000000_01000b

0000000000000000_10000b

The ICH2 logic generates single DWord configuration read and write cycles on the PCI bus. The

ICH2 generates a Type 0 configuration cycle for configurations to the bus number matching the

PCI bus. Type 1 configuration cycles are converted to Type 0 cycles in this case. If the cycle is

targeting a device behind an external bridge, the ICH2 runs a Type 1 cycle on the PCI bus.

Type 1 to Type 0 Conversion

When the bus number for the Type 1 configuration cycle matches the PCI (Secondary) bus number,

the ICH2 converts the address as follows:

• For device numbers 0 through 15, only one bit of the PCI address [31:16] is set. If the device

number is 0, AD[16] is set; if the device number is 1, AD[17] is set; etc.

• The ICH2 always drives 0s on bits AD[15:11] when converting Type 1 configurations cycles

to Type 0 configuration cycles on PCI.

• Address bits [10:1] are also passed unchanged to PCI.

• Address bit [0] is changed to 0.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-5

Functional Description

5.1.7

PCI Dual Address Cycle (DAC) Support

(82801BA ICH2 only)

The 82801BA ICH2 supports Dual Address Cycle (DAC) format on PCI for cycles from PCI

initiators to main memory. This allows PCI masters to generate an address up to 44 bits. The size

of the actual supported memory space will be determined by the memory controller and the

processor.

The DAC mode is only supported for PCI adapters and is not supported for any of the internal PCI

masters (IDE, LAN, USB, AC’97, 8237 DMA, etc.). ICH2 does not support DAC for processor-

initiated cycles.

When a PCI master wants to initiate a cycle with an address above 4 GB, it follows the following

behavioral rules (See PCI 2.2 Specification, section 3.9 for more details):

1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the DAC

encoding on the C/BE# signals. This unique encoding is 1101.

2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low address.

3. On the second clock, the peripheral drives AD[31:0] with the high address. The address is

right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is expected to be 0,

however the ICH2 will ignore these bits. C/BE# indicate the bus command type (Memory

Read, Memory Write, etc.)

4. The rest of the cycle proceeds normally.

5.2

LAN Controller (B1:D8:F0)

The ICH2’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced

scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed

data transfers over the PCI bus. Its bus master capabilities enable the component to process high

level commands and perform multiple operations, which lowers processor utilization by off-

loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB

each help prevent data underruns and overruns while waiting for bus accesses. This enables the

integrated LAN Controller to transmit data with minimum interframe spacing (IFS).

The ICH2 integrated LAN Controller can operate in either full duplex or half duplex mode. In full

duplex mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half

duplex performance is enhanced by a proprietary collision reduction mechanism.

The integrated LAN Controller also includes an interface to a serial (4-pin) EEPROM. The

EEPROM provides power-on initialization for hardware and software configuration parameters.

From a software perspective, the integrated LAN Controller appears to reside on the secondary side

of the ICH2’s virtual PCI-to-PCI Bridge (see Section 5.1.2). This is typically Bus 1; it may be

assigned a different number depending on system configuration.

5-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Feature Summary

• Compliance with Advanced Configuration and Power Interface and PCI Power Management

standards

• Support for wake-up on interesting packets and link status change

• Support for remote power-up using Wake on LAN* (WOL) technology

• Deep power-down mode support

• Support of Wired for Management (WfM) Rev 2.0

• Backward compatible software with 82557, 82558 and 82559

• TCP/UDP checksum offload capabilities

• Support for Intel’s Adaptive Technology

5.2.1

LAN Controller Architectural Overview

Figure 5-4 is a high level block diagram of the ICH2 integrated LAN Controller. It is divided into

four main subsystems: a Parallel subsystem, a FIFO subsystem and the Carrier-Sense Multiple

Access with Collision Detect (CSMA/CD) unit.

Figure 5-4. Integrated LAN Controller Block Diagram

EEPROM

Interface

PCI Target and

EEPROM Interface

3 Kbyte

Tx FIFO

Four Channel

Addressing Unit -

DMA

LAN

Connect

Interface

FIFO Control

CSMA/CD

Unit

Micro-

machine

PCI Bus

PCI

Interface

Interface Unit

(BIU)

3 Kbyte

Rx FIFO

Dual

Ported

FIFO

Data Interface Unit

(DIU)

Parallel Subsystem Overview

The parallel subsystem is divided into several functional blocks: a PCI bus master interface, a

micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/

EEPROM/ interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data

(e.g., transmit, receive, and configuration data) and command and status parameters between these

two blocks.

The PCI bus master interface provides a complete interface to the PCI bus and is compliant with

the PCI Bus Specification, Revision 2.2. The LAN Controller provides 32 bits of addressing and

data, as well as the complete control interface to operate on the PCI bus. As a PCI target, it follows

the PCI configuration format which allows all accesses to the LAN Controller to be automatically

mapped into free memory and I/O space upon initialization of a PCI system. For processing of

transmit and receive frames, the integrated LAN Controller operates as a master on the PCI bus,

initiating zero wait state transfers for accessing these data parameters.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-7

Functional Description

The LAN Controller Control/Status Register Block is part of the PCI target element. The Control/

Status Register block consists of the following LAN Controller internal control registers: System

Control Block (SCB), PORT, EEPROM Control and Management Data Interface (MDI) Control.

The micromachine is an embedded processing unit contained in the LAN Controller that enables

Adaptive Technology. The micromachine accesses the LAN Controller’s microcode ROM,

working its way through the opcodes (or instructions) contained in the ROM to perform its

functions. Parameters accessed from memory (e.g., pointers to data buffers) are also used by the

micromachine during the processing of transmit or receive frames by the LAN Controller. A

typical micromachine function is to transfer a data buffer pointer field to the LAN Controller’s

DMA unit for direct access to the data buffer. The micromachine is divided into two units, Receive

Unit and Command Unit that includes transmit functions. These two units operate independently

and concurrently. Control is switched between the two units according to the microcode instruction

flow. The independence of the Receive and Command units in the micromachine allows the LAN

Controller to execute commands and receive incoming frames simultaneously, with no real-time

processor intervention.

The LAN Controller contains an interface to an external serial EEPROM. The EEPROM is used to

store relevant information for a LAN connection such as node address, as well as board

manufacturing and configuration information. Both read and write accesses to the EEPROM are

supported by the LAN Controller. Information on the EEPROM interface is detailed in

Section 5.2.4.

FIFO Subsystem Overview

The ICH2 LAN Controller FIFO subsystem consists of a 3 KB transmit FIFO and 3 KB receive

FIFO. Each FIFO is unidirectional and independent of the other. The FIFO subsystem serves as the

interface between the LAN Controller parallel side and the serial CSMA/CD unit. It provides a

temporary buffer storage area for frames as they are either being received or transmitted by the

LAN Controller, which improves performance:

• Transmit frames can be queued within the transmit FIFO, allowing back-to-back transmission

within the minimum Interframe Spacing (IFS).

• The storage area in the FIFO allows the LAN Controller to withstand long PCI bus latencies

without losing incoming data or corrupting outgoing data.

• The ICH2 LAN Controller’s transmit FIFO threshold allows the transmit start threshold to be

tuned to eliminate underruns while concurrent transmits are being performed.

• The FIFO subsection allows extended PCI zero wait state burst accesses to or from the LAN

Controller for both transmit and receive frames since the transfer is to the FIFO storage area

rather than directly to the serial link.

• Transmissions resulting in errors (collision detection or data underrun) are retransmitted

directly from the LAN Controller’s FIFO, increasing performance and eliminating the need to

re-access this data from the host system.

• Incoming runt receive frames (in other words, frames that are less than the legal minimum

frame size) can be discarded automatically by the LAN Controller without transferring this

faulty data to the host system.

Serial CSMA/CD Unit Overview

The CSMA/CD unit of the ICH2 LAN Controller allows it to be connected to the 82562ET/EM

10/100 Mbps Ethernet LAN Connect components or the 82562EH 1 Mbps HomePNA*-compliant

LAN Connect component. The CSMA/CD unit performs all of the functions of the 802.3 protocol

such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. The

CSMA/CD unit can also be placed in a full duplex mode which allows simultaneous transmission

and reception of frames.

5-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.2.2

LAN Controller PCI Bus Interface

As a Fast Ethernet Controller, the role of the ICH2 integrated LAN Controller is to access

transmitted data or deposit received data. The LAN Controller, as a bus master device, initiates

memory cycles via the PCI bus to fetch or deposit the required data.

To perform these actions, the LAN Controller is controlled and examined by the processor via its

control and status structures and registers. Some of these control and status structures reside in the

LAN Controller and some reside in system memory. For access to the LAN Controller’s Control/

Status Registers (CSR), the LAN Controller acts as a slave (in other words, a target device). The

LAN Controller serves as a slave also while the processor accesses the EEPROM.

5.2.2.1

Bus Slave Operation

The ICH2 integrated LAN Controller serves as a target device in one of the following cases:

• Processor accesses to the LAN Controller System Control Block (SCB) Control/Status

Registers (CSR)

• Processor accesses to the EEPROM through its CSR

• Processor accesses to the LAN Controller PORT address via the CSR

• Processor accesses to the MDI control register in the CSR

• PCI Configuration cycles

The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The

LAN Controller treats accesses to these memory spaces differently.

Control/Status Register (CSR) Accesses

The integrated LAN Controller supports zero wait state single cycle memory or I/O mapped

accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O

space to accomplish this. Based on its needs, the software driver uses either memory or I/O

mapping to access these registers. The LAN Controller provides 4 KB of CSR space, which

includes the following elements:

• System Control Block (SCB) registers

• PORT register

• EEPROM control register

• MDI control register

• Flow control registers

In the case of accessing the Control/Status Registers, the processor is the initiator and the LAN

Controller is the target.

Read Accesses: The processor, as the initiator, drives address lines AD[31:0], the command and

byte enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. As a slave, the LAN

Controller controls the TRDY# signal and provides valid data on each data access. The LAN

Controller allows the processor to issue only one read cycle when it accesses the Control/Status

Registers, generating a disconnect by asserting the STOP# signal. The processor can insert wait

states by deasserting IRDY# when it is not ready.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-9

Functional Description

Write Accesses: The processor, as the initiator, drives the address lines AD[31:0], the command

and byte enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. It also provides the

LAN Controller with valid data on each data access immediately after asserting IRDY#. The LAN

Controller controls the TRDY# signal and asserts it from the data access. The LAN Controller

allows the processor to issue only one I/O write cycle to the Control/Status Registers, generating a

disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped

accesses.

Retry Premature Accesses

The LAN Controller responds with a retry to any configuration cycle accessing the LAN Controller

before the completion of the automatic read of the EEPROM. The LAN Controller may continue to

Retry any configuration accesses until the EEPROM read is complete. The LAN Controller does

not enforce the rule that the retried master must attempt to access the same address again to

complete any delayed transaction. Any master access to the LAN Controller after the completion of

the EEPROM read will be honored.

Error Handling

Data Parity Errors: The LAN Controller checks for data parity errors while it is the target of the

transaction. If an error was detected, the LAN Controller always sets the Detected Parity Error bit

in the PCI Configuration Status register, bit 15. The LAN Controller also asserts PERR#, if the

Parity Error Response bit is set (PCI Configuration Command register, bit 6). The LAN Controller

does not attempt to terminate a cycle in which a parity error was detected. This gives the initiator

the option of recovery.

Target-Disconnect: The LAN Controller terminates a cycle in the following cases:

• After accesses to its CSR

• After accesses to the configuration space

System Error: The LAN Controller reports parity error during the address phase using the SERR#

pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error

Response bit are not set, the LAN Controller only sets the Detected Parity Error bit (PCI

Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set,

the LAN Controller sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as

well as the Detected Parity Error bit and asserts SERR# for one clock.

The LAN Controller, when detecting system error, will claim the cycle if it was the target of the

transaction and continue the transaction as if the address was correct.

Note: The LAN Controller reports a system error for any error during an address phase, whether or not it

is involved in the current transaction.

5.2.2.2

Bus Master Operation

As a PCI Bus Master, the ICH2 integrated LAN Controller initiates memory cycles to fetch data for

transmission or deposit received data and for accessing the memory resident control structures. The

LAN Controller performs zero wait state burst read and write cycles to the host main memory. For

bus master cycles, the LAN Controller is the initiator and the host main memory (or the PCI host

bridge, depending on the configuration of the system) is the target.

The processor provides the LAN Controller with action commands and pointers to the data buffers

that reside in host main memory. The LAN Controller independently manages these structures and

initiates burst memory cycles to transfer data to and from them. The LAN Controller uses the

5-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the

Memory Read Line (MR Line) command for burst accesses to control structures. For all write

accesses to the control structure, the LAN Controller uses the Memory Write (MW) command. For

write accesses to the data structure, the LAN Controller may use either the Memory Write or

Memory Write and Invalidate (MWI) commands.

Read Accesses: The LAN Controller performs block transfers from host system memory to

perform frame transmission on the serial link. In this case, the LAN Controller initiates zero wait

state memory read burst cycles for these accesses. The length of a burst is bounded by the system,

the LAN Controller’s internal FIFO. The length of a read burst may also be bounded by the value

of the Transmit DMA Maximum Byte Count in the Configure command. The transmit DMA

Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles that will

be completed after a LAN Controller internal arbitration.

The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte

enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. The LAN Controller asserts

IRDY# to support zero wait state burst cycles. The target signals the LAN Controller that valid data

is ready to be read by asserting the TRDY# signal.

Write Accesses: The LAN Controller performs block transfers to host system memory during

frame reception. In this case, the LAN Controller initiates memory write burst cycles to deposit the

data, usually without wait states. The length of a burst is bounded by the system and the LAN

Controller’s internal FIFO threshold. The length of a write burst may also be bounded by the value

of the Receive DMA Maximum Byte Count in the configure command. The Receive DMA

Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that

will be completed before the LAN Controller internal arbitration.

The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte

enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. The LAN Controller asserts

IRDY# to support zero wait state burst cycles. The LAN Controller also drives valid data on

AD[31:0] lines during each data phase (from the first clock and on). The target controls the length

and signal’s completion of a data phase by deassertion and assertion of TRDY#.

Cycle Completion: The LAN Controller completes (terminates) its initiated memory burst cycles

in the following cases:

• Normal Completion: All transaction data has been transferred to or from the target device

(for example, host main memory).

• Backoff: Latency Timer has expired and the bus grant signal (GNT#) was removed from the

LAN Controller by the arbiter, indicating that the LAN Controller has been preempted by

another bus master.

• Transmit or Receive DMA Maximum Byte Count: The LAN Controller burst has reached

the length specified in the transmit or receive DMA Maximum Byte Count field in the

Configure command block.

• Target Termination: The target may request to terminate the transaction with a target-

disconnect, target-retry, or target-abort. In the first two cases, the LAN Controller initiates the

cycle again. In the case of a target-abort, the LAN Controller sets the Received Target-Abort

bit in the PCI Configuration Status field (PCI Configuration Status register, bit 12) and does

not re-initiate the cycle.

• Master Abort: The target of the transaction has not responded to the address initiated by the

LAN Controller (in other words, DEVSEL# has not been asserted). The LAN Controller

simply deasserts FRAME# and IRDY# as in the case of normal completion.

• Error Condition: In the event of parity or any other system error detection, the LAN

Controller completes its current initiated transaction. Any further action taken by the LAN

Controller depends on the type of error and other conditions.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-11

Functional Description

Memory Write and Invalidate

The LAN Controller has four Direct Memory Access (DMA) channels. Of these four channels (the

receive DMA channel) is used to deposit the large number of data bytes received from the link into

system memory. The receive DMA uses both the Memory Write (MW) and the Memory Write and

Invalidate (MWI) commands. To use MWI, the LAN Controller must guarantee the following:

1. Minimum transfer of one cache line

2. Active byte enable bits (or BE[3:0]# are all low) during MWI access

3. The LAN Controller may cross the cache line boundary only if it intends to transfer the next

cache line too.

To ensure the above conditions, the LAN Controller may use the MWI command only under the

following conditions:

1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16

DWords.

2. The accessed address is cache line aligned.

3. The LAN Controller has at least 8 or 16 DWords of data in its receive FIFO.

4. There are at least 8 or 16 DWords of data space left in the system memory buffer.

5. The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1.

6. The MWI Enable bit in the LAN Controller Configure command should is set to 1.

If any one of the above conditions does not hold, the LAN Controller will use the MW command.

If a MWI cycle has started and one of the conditions is no longer valid (for example, the data space

in the memory buffer is now less than CLS), then the LAN Controller terminates the MWI cycle at

the end of the cache line. The next cycle will be either a MW or MWI cycle depending on the

conditions listed above.

If the LAN Controller started a MW cycle and reached a cache line boundary, it either continues or

terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the LAN

Controller Configure command (byte 3, bit 3). If this bit is set, the LAN Controller terminates the

MW cycle and attempts to start a new cycle. The new cycle is a MWI cycle if this bit is set and all

of the above listed conditions are met. If the bit is not set, the LAN Controller continues the MW

cycle across the cache line boundary if required.

Read Align

The Read Align feature enhances the LAN Controller’s performance in cache line oriented

systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address

may cause low performance.

To resolve this performance anomaly, the LAN Controller attempts to terminate transmit DMA

cycles on a cache line boundary and start the next transaction on a cache line aligned address. This

feature is enabled when the Read Align Enable bit is set in the LAN Controller Configure

command (byte 3, bit 2).

If this bit is set, the LAN Controller operates as follows:

• When the LAN Controller is almost out of resources on the transmit DMA (i.e., the transmit

FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line

boundary when possible.

• When the arbitration counter’s feature is enabled (i.e., the Transmit DMA Maximum Byte

Count value is set in the Configure command), the LAN Controller switches to other pending

DMAs on cache line boundary only.

5-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Note: This feature is not recommended for use in non-cache line oriented systems since it may cause

shorter bursts and lower performance.

Note: This feature should be used only when the CLS register in PCI Configuration space is set to 8 or

16.

Note: The LAN Controller reads all control data structures (including Receive Buffer Descriptors) from

the first DWord (even if it is not required) to maintain cache line alignment.

Error Handling

Data Parity Errors: As an initiator, the LAN Controller checks and detects data parity errors that

occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command

Configuration Status register, bit 8). In addition, if the error was detected by the LAN Controller

during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).

5.2.3

CLOCKRUN# Signal (82801BAM ICH2-M only)

The ICH2-M receives a free-running 33 MHz clock. It does not stop based on the CLKRUN#

signal and protocol. When the LAN controller runs cycles on the PCI bus, the ICH2-M makes sure

that the STP_PCI# signal is high indictating that the PCI clock is running. This is to make sure that

any PCI tracker will not get confused by transactions on the PCI bus with its PCI clock stopped.

5.2.3.1

PCI Power Management

Enhanced support for the power management standard, PCI specification rev. 2.2, is provided in

the ICH2 integrated LAN Controller. The LAN Controller supports a large set of wake-up packets

and the capability to wake the system from a low power state on a link status change. The LAN

Controller enables the host system to be in a sleep state and remain virtually connected to the

network.

After a power management event or link status change is detected, the LAN Controller will wake

the host system. The sections below describe these events, the LAN Controller power states, and

estimated power consumption at each power state.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-13

Functional Description

Power States

The LAN Controller contains power management registers for PCI and implements all four power

states defined in the Power Management Network Device Class Reference Specification, Rev. 1.0.

The four states, D0 through D3, vary from maximum power consumption at D0 to the minimum

power consumption at D3. PCI transactions are only allowed in the D0 state, except for host

accesses to the LAN Controller’s PCI configuration registers. The D1 and D2 power management

states enable intermediate power savings while providing the system wake-up capabilities. In the

D3 state, the LAN Controller can provide wake-up capabilities. Wake-up indications from the LAN

Controller are provided by the Power Management Event (PME#) signal.

• D0 Power State. As defined in the Network Device Class Reference Specification, the device

is fully functional in the D0 power state. In this state, the LAN Controller receives full power

and should be providing full functionality. In the LAN Controller the D0 state is partitioned

into two substates, D0 Uninitialized (D0u) and D0 Active (D0a).

D0u is the LAN Controller’s initial power state following a PCI RST#. While in the D0u state,

the LAN Controller has PCI slave functionality to support its initialization by the host and

supports Wake on LAN* mode. Initialization of the CSR, Memory, or I/O Base Address

Registers (PCI Configuration space) switches the LAN Controller from D0u state to D0a state.

In the D0a state, the LAN Controller provides its full functionality and consumes its nominal

power. In addition, the LAN Controller supports wake on link status change (see

Section 5.2.3.3). While it is active, the LAN Controller requires a nominal PCI clock signal (in

other words, a clock frequency greater than 16 MHz) for proper operation. The LAN

Controller supports a dynamic standby mode. In this mode, the LAN Controller is able to save

almost as much power as it does in the static power-down states. The transition to or from

standby is done dynamically by the LAN Controller and is transparent to the software.

• D1 Power State. For a device to meet the D1 power state requirements, as specified in the

Advanced Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not

allow bus transmission or interrupts; however, bus reception is allowed. Therefore, device

context may be lost and the LAN Controller does not initiate any PCI activity. In this state, the

LAN Controller responds only to PCI accesses to its configuration space and system wake-up

events.

The LAN Controller retains link integrity and monitors the link for any wake-up events such

as wake-up packets or link status change. Following a wake-up event, the LAN Controller

asserts the PME# signal.

• D2 Power State. The ACPI D2 power state is similar in functionality to the D1 power state. In

addition to D1 functionality, the LAN Controller can provide a lower power mode with wake-

on-link status change capability. The LAN Controller may enter this mode if the link is down

while the LAN Controller is in the D2 state. In this state, the LAN Controller monitors the link

for a transition from an invalid to a valid link.

The sub-10 mA state due to an invalid link can be enabled or disabled by the PME_EN bit in

the Power Management Driver Register (PMDR). The LAN Controller will consume in D2

10 mA regardless of the link status. It is the LAN Connect component that consumes much

less power during link down, hence LAN Controller in this state can consume <10 mA.

• D3 Power State. In the D3 power state, the LAN Controller has the same capabilities and

consumes the same amount of power as it does in the D2 state. However, it enables the PCI

system to be in the B3 state. If the PCI system is in the B3 state (in other words, no PCI power

is present), the LAN Controller provides wake-up capabilities. If PME is disabled, the LAN

Controller does not provide wake-up capability or maintain link integrity. In this mode the

LAN Controller consumes its minimal power (if PME_EN=0).

The LAN Controller enables a system to be in a sub-5 watt state (low power state) and still be

virtually connected. More specifically, the LAN Controller supports full wake-up capabilities

while it is in the D3 cold state. The LAN Controller is in the ICH2 resume well and, thus, is

connected to an auxiliary power source (a separate LAN well). This enables it to provide

wake-up functionality while the PCI power is off.

5-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.2.3.2

PCI Reset Signal

The PCIRST# signal may be activated in one of the following cases:

• During S3-S5 states

• Due to a CF9h reset

If PME# is enabled (in the PCI power management registers), PCIRST# assertion does not affect

any PME# related circuits (in other words, PCI power management registers and the wake-up

packet would not be affected). While PCIRST# is active, the LAN Controller ignores other PCI

signals. The configuration of the LAN Controller registers associated with ACPI wake events is not

affected by PCIRST#.

The integrated LAN Controller uses the PCIRST# or the PWROK signal as an indication to ignore

the PCI interface. Following the deassertion of PCIRST#, the LAN Controller PCI Configuration

Space, MAC configuration, and memory structure are initialized while preserving the PME# signal

and its context.

5.2.3.3

Wake-up Events

There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two

events are detailed below.

Note: If the WOL bit in the EEPROM is not set, wake-up events are supported only if the PME Enable bit

in the Power Management Control/Status Register (PMCSR) is set. However, if the WOL bit in the

EEPROM is set, and Wake on Magic Packet or Wake on Link Status Change are enabled, the

Power Management Enable bit is ignored with respect to these events. In the latter case, PME#

would be asserted by these events.

"Interesting" Packet Event

In the power-down state, the LAN Controller is capable of recognizing “interesting” packets. The

LAN Controller supports pre-defined and programmable packets that can be defined as any of the

following:

• ARP Packets (with Multiple IP addresses)

• Direct Packets (with or without type qualification)

• Magic Packet*

• Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)

• NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)

• Internetwork Package Exchange* (IPX) Diagnostic Packet

This allows the LAN Controller to handle various packet types. In general, the LAN Controller

supports programmable filtering of any packet in the first 128 bytes.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-15

Functional Description

When the LAN Controller is in one of the low power states, it searches for a predefined pattern in

the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is

scanned for the entire frame. The LAN Controller will classify the incoming packets as one of the

following categories:

• No Match: The LAN Controller discards the packet and continues to process the incoming

packets.

• Wake-up Packet: The LAN Controller is capable of recognizing and storing the first

128 bytes of a wake-up packet. If a wake-up packet is larger than 128 bytes, its tail is discarded

by the LAN Controller. After the system is fully powered-up, software has the ability to

determine the cause of the wake-up event via the PMDR and dump the stored data to the host

memory.

Magic Packets are an exception. The magic packets may cause a power management event and

set an indication bit in the PMDR; however, it is not stored by the LAN Controller for use by

the system when it is woken up.

Link Status Change Event

The LAN Controller link status indication circuit is capable of issuing a PME on a link status

change from a valid link to an invalid link condition or vice versa. The LAN Controller reports a

PME link status event in all power states. If the WOL bit in the EEPROM is not set, the PME#

signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command.

5.2.3.4

Wake on LAN (Preboot Wake-up)

The LAN Controller enters WOL mode after reset if the WOL bit in the EEPROM is set. At this

point, the LAN Controller is in the D0u state.

When the LAN Controller is in WOL mode:

• The LAN Controller scans incoming packets for a Magic Packet and asserts the PME# signal

for 52 ms when a one is detected in Wake on LAN mode.

• The Activity LED changes its functionality to indicates that the received frame passed

Individual Address (IA) filtering or broadcast filtering.

• The PCI Configuration registers are accessible to the host.

The LAN Controller switches from WOL mode to the D0a power state following a setup of the

Memory or I/O Base Address Registers in the PCI configuration space.

5-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.2.4

Serial EEPROM Interface

The serial EEPROM stores configuration data for the ICH2 integrated LAN Controller and is a

serial in/serial out device. The LAN Controller supports a 64 word size or 256 register size

EEPROM and automatically detects the EEPROM’s size. A 256 word EEPROM device is required

for a Cardbus system and contains the CIS information. The EEPROM should operate at a

frequency of at least 1 MHz.

All accesses, either read or write, are preceded by a command instruction to the device. The

address field is six bits for a 64 word EEPROM or eight bits for a 256 register EEPROM. The end

of the address field is indicated by a dummy zero bit from the EEPROM, which indicates the entire

address field has been transferred to the device. An EEPROM read instruction waveform is shown

in Figure 5-5.

Figure 5-5. 64-Word EEPROM Read Instruction Waveform

EE_SHCLKK

EE_CS

A₅

A₄

A₂

A₀

A₃

EE_DIN

READ OP code

D₁₅

D₀

EE_DOUT

The LAN Controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch and Dh) of

the EEPROM after the deassertion of Reset. The ICH2 integrated LAN Controller’s EEPROM

format is shown below in Table 5-2. For additional information, refer to Application Note AP-409,

"I/O Controller Hub EEPROM Map and Programming Information"

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-17

Functional Description

Table 5-2. I/O Control Hub 2 EEPROM Address Map

Word

00h

HIgh Byte (Bits 15:8)

Low Byte (Bits 7:0)

Used by

Ethernet Individual Address Byte 2

Ethernet Individual Address Byte 4

Ethernet Individual Address Byte 6

Compatibility Byte 1

Ethernet Individual Address Byte 1

Ethernet Individual Address Byte 3

Ethernet Individual Address Byte 5

Compatibility Byte 0

Hardware

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

Intel driver

Reserved

Connector Type

PHY Device Record

Reserved

PWA Number Byte 3

PWA Number Byte 1

EEPROM ID

Controller Type (02 for ICH2)

Intel driver

PWA Number Byte 4

PWA Number Byte 2

Factory

Hardware

Subsystem ID

Subsystem Vendor ID

Alert on

LAN* driver

or hardware

Heartbeat Packet

Pointer

0Dh

0000b

SMB Address Field

0Eh–2Fh

30h

Reserved

Reserved for Intel Network Interface Division (NID) Boot Agent ROM Configuration

(PXE and RPL version)

Firmware

31h

Reserved for Intel NID Boot Agent ROM Configuration (PXE and RPL version)

Reserved

Firmware

32h

33h–3Ah

3Bh

Reserved for Intel Architecture Labs (IAL) Boot ROM Configuration (PXE only)

Firmware

3Ch–3Fh

Reserved

Alert on LAN alert packet structure

Checksum

Alert on LAN

driver

40h–FAh

FFh

Driver

Words 00h through 02h are used by the hardware and are common to all controllers.

5-18

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.2.5

CSMA/CD Unit

The ICH2 integrated LAN Controller CSMA/CD unit implements both the IEEE 802.3 Ethernet

10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It also supports the 1 Mbps Home

Phoneline Networking Alliance (HomePNA*) specification effort. It performs all the CSMA/CD

protocol functions such as transmission, reception, collision handling, etc. The LAN Controller

CSMA/CD unit interfaces to the 82562ET/EM 10/100 Mbps Ethernet or the 82562EH 1 Mbps

HomePNA*-compliant LAN Connect component through the ICH2’s LAN Connect interface

signals.

Full Duplex

When operating in full duplex mode, the LAN Controller can transmit and receive frames

simultaneously. Transmission starts regardless of the state of the internal receive path. Reception

starts when the LAN Connect component detects a valid frame on its receive differential pair.

When in Full Duplex mode, the ICH2 integrated LAN Controller also supports the IEEE 802.3x

flow control standard.

The LAN Controller operates in either half duplex mode or full duplex mode. For proper operation,

both the LAN Controller CSMA/CD module and the discrete LAN Connect component must be set

to the same duplex mode. The CSMA duplex mode is set by the LAN Controller Configure

command or forced by automatically tracking the mode in the LAN Connect component.

Following reset, the CSMA will default to automatically track the LAN Connect component

duplex mode.

The selection of duplex operation (full or half) and flow control is done in two levels: MAC and

LAN Connect.

Flow Control

The LAN Controller supports IEEE 802.3x frame based flow control frames only in full duplex

switched environments. The LAN Controller flow control feature is not intended to be used in

shared media environments.

Flow control is optional in full duplex mode and is selected through software configuration. There

are three modes of flow control that can be selected: frame-based transmit flow control, frame-

based receive flow control, and none.

Address Filtering Modifications

The LAN Controller can be configured to ignore one bit when checking for its Individual Address

(IA) on incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the

second least significant bit of the first byte of the IA. This bit may be used, in some cases, as a

priority indication bit. When configured to do so, the LAN Controller passes any frame that

matches all other 47 address bits of its IA, regardless of the U/L bit value.

This configuration only affects the LAN Controller specific IA and not multicast, multi-IA or

broadcast address filtering. The LAN Controller does not attribute any priority to frames with this

bit set, it simply passes them to memory regardless of this bit.

VLAN Support

The LAN Controller supports the IEEE 802.1 standard VLAN. All VLAN flows are implemented

by software. The LAN Controller supports the reception of long frames; specifically frames longer

than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration

command. Otherwise, “long” frames are discarded.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-19

Functional Description

5.2.6

Media Management Interface

The management interface allows the processor to control the LAN Connect component via a

control register in the ICH2 integrated LAN Controller. This allows the software driver to place the

LAN Connect in specific modes such as full duplex, loopback, power down, etc., without the need

for specific hardware pins to select the desired mode. This structure allows the LAN Controller to

query the LAN Connect component for status of the link. This register is the MDI Control Register

and resides at offset 10h in the LAN Controller CSR. The MDI registers reside within the LAN

Connect component, and are described in detail in the LAN Connect component’s datasheet. The

processor writes commands to this register and the LAN Controller reads or writes the control/

status parameters to the LAN Connect component through the MDI register.

5.2.7

TCO Functionality

The ICH2-M integrated LAN controller supports management communication to reduce Total Cost

of Ownership (TCO). It has a System Management Bus (SMB) on which the LAN controller is a

slave device. The SMB is used as an interface between the LAN controller and the integrated host

controller. An EEPROM of 256 words is required to support the heartbeat command.

Receive Functionality

In the power-up state, the LAN controller transfers TCO packets to the host as any other packet.

These packets include a new status indication bit in the Receive Frame Descriptor (RFD) status

state, the TCO packets are treated as wake-up packets. The ICH2-M integrated LAN controller

asserts the PME# signal and delivers the first 120 bytes of the packet to the host.

Transmit Functionality

The ICH2-M integrated LAN controller supports the Heartbeat (HB) transmission command from

the SMB interface. The send HB packet command includes a system health status issued by the

integrated system controller. The LAN controller computes a matched checksum and CRC and

transmits the HB packet from its serial EEPROM. The HB packet size and structure are not limited

as long as it fits within the EEPROM size. In this case, the EEPROM size is 256 words to enable

the storage of the HB packet (the first 64 words are used for driver specific data).

Note: On the SMB, the send heartbeat packet command is not normally used in the D0 power state. The

one exception in which it is used in the D0 state is when the system is hung. In normal operating

mode, the heartbeat packets are transmitted through the ICH2-M integrated LAN controller

software similar to other packets.

5.3

LPC Bridge (w/ System and Management Functions)

(D31:F0)

The LPC Bridge function of the ICH2 resides in PCI Device 31:Function 0. In addition to the LPC

bridge function, D31:F0 contains other functional units including DMA, Interrupt Controllers,

Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and

functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are

described in their respective sections.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.3.1

LPC Interface

The ICH2 implements an LPC interface as described in the LPC 1.0 specification. The LPC

interface to the ICH2 is shown in Figure 5-6. Note that the ICH2 implements all of the signals that

are shown as optional, but peripherals are not required to do so.

Figure 5-6. LPC Interface Diagram

PCI Bus

PCI

CLK

RST#

SERIRQ

PME#

LAD[3:0]

ICH2

ICH

LFRAME#

LDRQ#

(optional)

Super I/O

LPCPD#

SUS_STAT#

GPI

(optional)

LSMI#

(optional)

5.3.1.1

LPC Cycle Types

The ICH2 implements all of the cycle types described in the LPC I/F 1.0 specification. Table 5-3

shows the cycle types supported by the ICH2.

Table 5-3. LPC Cycle Types Supported

Cycle Type

Comment

Memory Read

Memory Write

Single: 1 byte only

1 byte only. ICH2 breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers. See Note 1 below.

I/O Read

I/O Write

1 byte only. ICH2 breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers. See Note 1 below.

DMA Read

DMA Write

Can be 1 or 2 bytes

Bus Master Read

Bus Master Write

Can be 1, 2, or 4 bytes. (See Note 2 below)

NOTES:

1. For memory cycles below 16 MB which do not target enabled FWH ranges, the ICH2will perform standard

LPC memory cycles. It will only attempt 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer, it will

appear as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on PCI,

it will appear as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it will be

subsequently aborted, and the ICH2 will return a value of all 1s to the processor. This is done to maintain

compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.

2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any

address. However, the 2-byte transfer must be word aligned (i.e. with an address where A0=0). A DWord

transfer must be DWord aligned (i.e., with an address where A1and A0 are both 0)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-21

Functional Description

5.3.1.2

Start Field Definition

Table 5-4. Start Field Bit Definitions

Bits[3:0]

Encoding

Definition

0000

0010

0011

1111

Start of cycle for a generic target.

Grant for bus master 0.

Grant for bus master 1.

Stop/Abort: End of a cycle for a target.

NOTE: All other encodings are Reserved.

5.3.1.3

Cycle Type / Direction (CYCTYPE + DIR)

The ICH2 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also

drive bit 0 to 0. Table 5-5 shows the valid bit encodings.

Table 5-5. Cycle Type Bit Definitions

Bits[3:2]

Bit[1]

Definition

I/O Read

I/O Write

Memory Read

Memory Write

DMA Read

DMA Write

Reserved. If a peripheral performing a bus master cycle generates this value, the

ICH2 will abort the cycle.

5.3.1.4

Size

Bits[3:2] are reserved. The ICH2 always drives them to 00. Peripherals running bus master cycles

are also supposed to drive 00 for bits 3:2; however, the ICH2 ignores those bits. Table 5-6 shows

the bit encodings for Bits[1:0].

Table 5-6. Transfer Size Bit Definition

Bits[1:0]

Size

8 bit transfer (1 byte)

16-bit transfer (2 bytes)

Reserved. The ICH2 never drives this combination. If a peripheral running a bus master cycle

drives this combination, the ICH2 may abort the transfer.

32 bit transfer (4 bytes)

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.3.1.5

SYNC

Valid values for the SYNC field are listed in Table 5-7.

Table 5-7. SYNC Bit Definition

Bits[3:0]

Indication

Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request

deassertion and no more transfers desired for that channel.

0000

Short Wait: Part indicating wait states. For bus master cycles, the ICH2 does not use this

encoding. It will instead use the Long Wait encoding (see next encoding below).

0101

0110

Long Wait: Part indicating wait states; many wait states will be added. This encoding driven by

the ICH2 for bus master cycles, rather than the Short Wait (0101).

Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more

DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers

and is not allowed for any other type of cycle.

1001

1010

Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal

on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this

transfer. For DMA transfers, this not only indicates an error, but also indicates DMA request

deassertion and no more transfers desired for that channel.

NOTE: All other combinations are Reserved.

5.3.1.6

SYNC Time-out

There are several error cases that can occur on the LPC interface. Table 5-8 indicates the failing

case and the ICH2 response.

Table 5-8. ICH2 Response to Sync Failures

Possible Sync Failure

ICH2 Response

ICH2 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC

after 4 consecutive clocks. This could occur if the processor tries to access an

I/O location to which no device is mapped.

ICH2 aborts the cycle after

the 4 clock.

ICH2 drives a Memory, I/O, or DMA cycle, and a peripheral drives more than 8

consecutive valid SYNC patterns to insert wait states using the Short (‘0101b’)

encoding for SYNC. This could occur if the peripheral is not operating properly.

Continues waiting

ICH2 starts a Memory, I/O, or DMA cycle, and a peripheral drives an invalid

SYNC pattern. This could occur if the peripheral is not operating properly or if

there is excessive noise on the LPC interface.

ICH2 aborts the cycle when

the invalid Sync is

recognized.

NOTE: There may be other peripheral failure conditions; however, these are not handled by the ICH2.

5.3.1.7

SYNC Error Indication

The SYNC protocol allows the peripheral to report an error via the LAD[3:0] = 1010b encoding.

The intent of this encoding is to give peripherals a method of communicating errors to aid higher

layers with more robust error recovery.

If the ICH2 was reading data from a peripheral, data will still be transferred in the next two nibbles.

This data may be invalid; however, it must be transferred by the peripheral. If the ICH2 was writing

data to the peripheral, the data had already been transferred.

In the case of multiple byte cycles (e.g., for memory and DMA cycles) an error SYNC terminates

the cycle. Therefore, if the ICH2 is transferring 4 bytes from a device and the device returns the

error SYNC in the first byte, the other three bytes are not transferred.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-23

Functional Description

When recognizing the SYNC field indicating an error, the ICH2 treats this the same as IOCHK#

going active on the ISA bus.

5.3.1.8

LFRAME# Usage

Start of Cycle

For Memory, I/O, and DMA cycles, the ICH2 asserts LFRAME# for 1 clock at the beginning of the

cycle (Figure 5-7) During that clock, the ICH2 drives LAD[3:0] with the proper START field.

Figure 5-7. Typical Timing for LFRAME#

LCLK

LFRAME#

Start

ADDR TAR

Data

Sync

Start

TAR

LAD[3:0]#

CYCTYPE 1 - 8

1 - n

Clock Dir & Size Clocks Clocks Clocks Clocks

Clocks

Clock

Abort Mechanism

When performing an Abort, the ICH2 drives LFRAME# active for 4 consecutive clocks. On the 4^th

clock, the ICH2 drives LAD[3:0] to ‘1111b’.

Figure 5-8. Abort Mechanism

LCLK

LFRAME#

Start

ADDR TAR

Chipset will

drive high

Sync

Peripheral must

stop driving

LAD[3:0]#

CYCTYPE

Dir & Size

Too many

Syncs causes

timeout

The ICH2 performs an abort for the following cases (possible failure cases):

• ICH2 starts a Memory, I/O, or DMA cycle and no device drives a valid SYNC after 4

consecutive clocks.

• ICH2 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.

• A peripheral drives an illegal address when performing bus master cycles.

• A peripheral drives an invalid value.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.3.1.9

I/O Cycles

For I/O cycles targeting registers specified in the ICH2’s decode ranges, the ICH2 performs I/O

cycles as defined in the LPC specification. These are 8-bit transfers. If the processor attempts a

16-bit or 32-bit transfer, the ICH2 will break the cycle up into multiple 8-bit transfers to

consecutive I/O addresses.

Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH2 returns all

1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up

resistors would keep the bus high if no device responds.

5.3.1.10

Bus Master Cycles

The ICH2 supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC

specification. The ICH2 has two LDRQ# inputs; thus, ICH2 supports two separate bus master

devices. It uses the associated START fields for Bus Master 0 (‘0010b’) or Bus Master 1 (‘0011b’).

Note: The ICH2 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only

perform memory read or memory write cycles.

5.3.1.11

LPC Power Management

LPCPD# Protocol

Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals will drive

LDRQ# low or tri-state it. ICH2 shuts off the LDRQ# input buffers. After driving SUS_STAT#

active, the ICH2 drives LFRAME# low and tri-states (or drive low) LAD[3:0].

CLKRUN# Protocol (82801BAM ICH2-M only)

For the ICH2-M, the CLKRUN# protocol is the same as the PCI specification. Stopping the PCI

clock stops the LPC clock.

5.3.1.12

Configuration and ICH2 Implications

LPC Interface Decoders

To allow the I/O cycles and memory mapped cycles to go to the LPC I/F, the ICH2 includes several

decoders. During configuration, the ICH2 must be programmed with the same decode ranges as the

peripheral. The decoders are programmed via the Device 31:Function 0 configuration space.

Note: The ICH2 can not accept PCI write cycles from PCI-to-PCI bridges or devices with similar

characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device

if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are

not part of normal system operation; however, they may be encountered as part of platform

validation testing using custom test fixtures.

Bus Master Device Mapping and START Fields

Bus Masters must have a unique START field. In the case of the ICH2, which supports 2 LPC bus

masters, it will drive 0010 for the START field for grants to bus master #0 (requested via

LDRQ[0]#) and 0011 for grants to bus master #1 (requested via LDRQ[1]#.). Thus, no registers are

needed to configure the START fields for a particular bus master.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-25

Functional Description

5.4

DMA Operation (D31:F0)

The ICH2 supports two types of DMA: LPC and PC/PCI. DMA via LPC is similar to ISA DMA.

LPC DMA and PC/PCI DMA use the ICH2’s DMA controller. The DMA controller has registers

that are fixed in the lower 64 KB of I/O space.

The DMA controller is configured using registers in the PCI configuration space. These registers

allow configuration of individual channels for use by LPC or PC/PCI DMA.

The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven

independently programmable channels (Figure 5-9). DMA Controller 1 (DMA-1) corresponds to

DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to Channels 5–7. DMA Channel

4 is used to cascade the two controllers and will default to cascade mode in the DMA Channel

Mode (DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting

requests from DMA slaves, the DMA controller also responds to requests that software initiates.

Software may initiate a DMA service request by setting any bit in the DMA Channel Request

Figure 5-9. ICH2 DMA Controller

Channel 4

Channel 0

Channel 1

Channel 2

Channel 3

Channel 5

Channel 6

Channel 7

DMA-1

DMA-2

Each DMA channel is hardwired to the compatible settings for DMA device size: channels 3–0 are

hardwired to 8-bit, count-by-bytes transfers and channels 7–5 are hardwired to 16-bit, count-by-

words (address shifted) transfers.

ICH2 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each

channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant

bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most

significant bits of address.

The DMA controller also features refresh address generation and autoinitialization following a

DMA termination.

5.4.1

Channel Priority

For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and

channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA

Command Register.

DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a

software request for DMA service can be presented through each channel's DMA Request Register.

A software request is subject to the same prioritization as any hardware request. See the detailed

description section.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Fixed Priority

The initial fixed priority structure is as follows:

High priority.....Low priority

(0, 1, 2, 3) (5, 6, 7)

The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, Channel 0 has the highest

priority and channel 7 has the lowest priority. Channels 3–0 of DMA-1 assume the priority position

of Channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7.

Rotating Priority

Rotation allows for "fairness" in priority resolution. The priority chain rotates so that the last

channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).

Channels 0–3 rotate as a group of 4. They are always placed between Channel 5 and Channel 7 in

the priority list.

Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three positions in

the rotation while channel group (0–3) form the fourth position in the arbitration.

5.4.2

5.4.3

Address Compatibility Mode

When the DMA is operating, the addresses do not increment or decrement through the High and

Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address

will be 010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next

address will be 02FFFFh, not 01FFFFh. This is compatible with the 82C37 and Page Register

implementation used in the PC-AT. This mode is set after CPURST is valid.

Summary of DMA Transfer Sizes

Table 5-9 lists each of the DMA device transfer sizes. The column labeled "Current Byte/Word

Count Register" indicates that the register contents represents either the number of bytes to transfer

or the number of 16-bit words to transfer. The column labeled "Current Address Increment/

Decrement" indicates the number added to or taken from the Current Address Register after each

DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register

is incremented or decremented.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-27

Functional Description

Address Shifting When Programmed for 16-Bit I/O Count by Words

Table 5-9. DMA Transfer Size

Current Byte/Word Count

Current Address

Increment/Decrement

DMA Device Date Size And Word Count

8-Bit I/O, Count By Bytes

Bytes

16-Bit I/O, Count By Words (Address Shifted)

Words

The ICH2 maintains compatibility with the implementation of the DMA in the PC-AT that used the

82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note

that the least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When

programming the Current Address Register (when the DMA channel is in this mode), the current

address must be programmed to an even address with the address value shifted right by one bit. The

address shifting is shown in Table 5-10.

Table 5-10. Address Shifting in 16-bit I/O DMA Transfers

16-Bit I/O Programmed Address

Output

Address

8-Bit I/O Programmed Address

(Ch 0–3)

(Ch 5–7)

(Shifted)

A[16:1]

A[23:17]

A[16:1]

A[23:17]

A[15:0]

A[23:17]

NOTE: NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

5.4.4

Autoinitialize

By programming a bit in the DMA Channel Mode Register, a channel may be set up as an

autoinitialize channel. When a channel undergoes autoinitialization, the original values of the

Current Page, Current Address and Current Byte/Word Count Registers are automatically restored

from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The

Base Registers are loaded simultaneously with the Current Registers by the processor when the

DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is

not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to

perform another DMA service, without processor intervention, as soon as a valid DREQ is

detected.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.4.5

Software Commands

There are three additional special software commands that the DMA controller can execute. The

three software commands are:

• Clear Byte Pointer Flip-Flop

• Master Clear

• Clear Mask Register

They do not depend on any specific bit pattern on the data bus.

Clear Byte Pointer Flip-Flop

This command is executed prior to writing or reading new address or word count information

to/from the DMA controller. This initializes the flip-flop to a known state so that subsequent

accesses to register contents by the processor addresses upper and lower bytes in the correct

sequence.

When the Host processor is reading or writing DMA registers, two Byte Pointer flip-flops are used;

one for channels 0–3 and one for channels 4–7. Both of these act independently. There are separate

software commands for clearing each of them (0Ch for channels 0–3, 0D8h for channels 4–7).

DMA Master Clear

This software instruction has the same effect as the hardware reset. The Command, Status,

Request, and Internal First/Last Flip-Flop Registers are cleared and the Mask Register is set. The

DMA controller enters the idle cycle.

There are two independent master clear commands; 0Dh acts on channels 0–3, and 0DAh acts on

channels 4–7.

Clear Mask Register

This command clears the mask bits of all four channels, enabling them to accept DMA requests.

I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-29

Functional Description

5.5

PCI DMA

The ICH2 provides support for the PC/PCI DMA protocol. PC/PCI DMA uses dedicated request

and grant signals to permit PCI devices to request transfers associated with specific DMA

channels. Upon receiving a request and getting control of the PCI bus, the ICH2 performs a two-

cycle transfer. For example, if data is to be moved from the peripheral to main memory, the ICH2

first reads data from the peripheral and then writes the data to main memory. The location in main

memory is the Current Address Registers in the 8237.

ICH2 supports up to 2 PC/PCI REQ/GNT pairs, REQ[A:B]# and GNT[A:B]#.

A 16-bit register is included in the ICH2 Function 0 PCI configuration space at offset 90h. It is

divided into seven 2-bit fields that are used to configure the 7 DMA channels.

Each DMA channel can be configured to one of two options:

• LPC DMA

• PC/PCI style DMA using the REQ/GNT signals

It is not possible for a particular DMA channel to be configured for more than one style of DMA;

however, the seven channels can be programmed independently. For example, channel 3 can be set

up for PC/PCI and channel 5 set up for LPC DMA.

The ICH2 REQ[A:B]# and GNT[A:B]# can be configured for support of a PC/PCI DMA

Expansion agent. The PCI DMA Expansion agent can then provide DMA service or ISA Bus

Master service using the ICH2 DMA controller. The REQ#/GNT# pair must follow the PC/PCI

serial protocol described in the following section.

5.5.1

PCI DMA Expansion Protocol

The PCI expansion agent must support the PCI expansion Channel Passing Protocol defined in

Figure 5-10 for both the REQ# and GNT# pins.

Figure 5-10. DMA Serial Channel Passing Protocol

PCICLK

REQ#

GNT#

Start CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

Start Bit0 Bit1 Bit2

The requesting device must encode the channel request information as shown above, where

CH0–CH7 are one clock active high states representing DMA channel requests 0–7.

The ICH2 encodes the granted channel on the GNT# line as shown above where the bits have the

same meaning as shown in Figure 5-10. For example, the sequence

[start, bit 0, bit 1, bit 2]=[0,1,0,0] grants DMA channel 1 to the requesting device, and the sequence

[start, bit 0, bit 1, bit 2]=[0,0,1,1] grants DMA channel 6 to the requesting device.

5-30

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

All PCI DMA expansion agents must use the channel passing protocol described above. They must

also work as follows:

1. If a PCI DMA expansion agent has more than one request active, it must resend the request

serial protocol after one of the requests has been granted the bus and it has completed its

transfer. The expansion device should drive its REQ# inactive for two clocks and then transmit

the serial channel passing protocol again, even if there are no new requests from the PCI

expansion agent to ICH2. For example, if a PCI expansion agent had active requests for DMA

Channel 1 and Channel 5, it would pass this information to the ICH2 through the expansion

channel passing protocol. If, after receiving GNT# (assume for CH5) and having the device

finish its transfer (device stops driving request to PCI expansion agent), it would then need to

re-transmit the expansion channel passing protocol to inform the ICH2 that DMA channel 1

was still requesting the bus, even if that was the only request the expansion device had

pending.

2. If a PCI DMA expansion agent has a request go inactive before ICH2 asserts GNT#, it must

resend the expansion channel passing protocol to update the ICH2 with this new request

information. For example, if a PCI expansion agent has DMA channel 1 and 2 requests

pending, it sends them serially to ICH2 using the expansion channel passing protocol. If,

however, DMA channel 1 goes inactive into the expansion agent before the expansion agent

receives a GNT# from ICH2, the expansion agent must pull its REQ# line high for 1clock and

resend the expansion channel passing information with only DMA channel 2 active. Note that

the ICH2 does not do anything special to catch this case because a DREQ going inactive

before a DACK# is received is not allowed in the ISA DMA protocol and, therefore, does not

need to work properly in this protocol either. This requirement is needed to be able to support

Plug-n-Play ISA devices that toggle DREQ# lines to determine if those lines are free in the

system.

3. If a PCI expansion agent has sent its serial request information and receives a new DMA

request before receiving GNT#, the agent must resend the serial request with the new request

active. For example, if a PCI expansion agent has already passed requests for DMA channel 1

and 2 and detects DREQ 3 active before a GNT is received, the device must pull its REQ# line

high for one clock and resend the expansion channel passing information with all three

channels active.

The three cases above require the following functionality in the PCI DMA expansion device:

• Drive REQ# inactive for one clock to signal new request information.

• Drive REQ# inactive for two clocks to signal that a request that had been granted the bus has

gone inactive.

• The REQ# and GNT# state machines must run independently and concurrently (i.e., a GNT#

could be received while in the middle of sending a serial REQ# or a GNT# could be active

while REQ# is inactive).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-31

Functional Description

5.5.2

PCI DMA Expansion Cycles

ICH2’s support of the PC/PCI DMA Protocol currently consists of four types of cycles: Memory-

to-I/O, I/O-to-Memory, Verify, and ISA Master cycles. ISA Masters are supported through the use

of a DMA channel that has been programmed for cascade mode.

The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA

"fly-by" cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory

read or memory write bus cycle, its address representing the selected memory.

The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses

(Table 5-11). Note that these cycles must be qualified by an active GNT# signal to the requesting

device.

Table 5-11. DMA Cycle vs. I/O Address

DMA Cycle Type

DMA I/O Address

PCI Cycle Type

Normal

Normal TC

Verify

00h

04h

I/O Read/Write

I/O Read

0C0h

0C4h

Verify TC

I/O Read

5.5.3

5.5.4

DMA Addresses

The memory portion of the cycle generates a PCI memory read or memory write bus cycle; its

address representing the selected memory. The I/O portion of the DMA cycle generates a PCI

I/O cycle to one of the four I/O addresses listed in Table 5-11.

DMA Data Generation

The data generated by PC/PCI devices on I/O reads when they have an active GNT# is on the lower

two bytes of the PCI AD bus. Table 5-12 lists the PCI pins that the data appears for 8 and 16 bit

channels. Each I/O read results in one memory write and each memory read results in one I/O

write. If the I/O device is 8 bit, the ICH2 performs an 8 bit memory write. The ICH2 does not

assemble the I/O read into a DWord for writing to memory. Similarly, the ICH2 does not

disassemble a DWord read from memory to the I/O device.

Table 5-12. PCI Data Bus vs. DMA I/O Port Size

PCI DMA I/O Port Size

PCI Data Bus Connection

Byte

AD[7:0]

Word

AD[15:0]

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.5.5

DMA Byte Enable Generation

The byte enables generated by the ICH2 on I/O reads and writes must correspond to the size of the

I/O device. Table 5-13 defines the byte enables asserted for 8 and 16 bit DMA cycles.

Table 5-13. DMA I/O Cycle Width vs. BE[3:0]#

BE[3:0]#

Description

1110b

1100b

8-bit DMA I/O Cycle: Channels 0-3

16-bit DMA I/O Cycle: Channels 5-7

NOTE: For verify cycles, the value of the Byte Enables (BEs) are a “don’t care”.

5.5.6

DMA Cycle Termination

DMA cycles are terminated when a terminal count is reached in the DMA controller and the

channel is not in autoinitialize mode or when the PC/PCI device deasserts its request. The PC/PCI

device must follow explicit rules when deasserting its request or the ICH2 may not see it in time

and run an extra I/O and memory cycle.

The PC/PCI device must deassert its request 7 PCICLKs before it generates TRDY# on the I/O

read or write cycle or the ICH2 is allowed to generate another DMA cycle. For transfers to

memory, this means that the memory portion of the cycle will be run without an asserted PC/PCI

REQ#.

5.5.7

5.5.8

LPC DMA

DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special

encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported

on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit channels. Channel 4

is reserved as a generic bus master request.

Asserting DMA Requests

Peripherals that need DMA service encode their requested channel number on the LDRQ# signal.

To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they

may not be shared between two separate peripherals). The ICH2 has two LDRQ# inputs, allowing

at least two devices to support DMA or bus mastering.

LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-11 the peripheral uses the

following serial encoding sequence:

• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle

conditions.

• The next 3 bits contain the encoded DMA channel number (MSB first).

• The next bit (ACT) indicates whether the request for the indicated DMA channel is active or

inactive. The ACT bit will be a 1 (high) to indicate if it is active and 0 (low) if it is inactive.

The case where ACT is low will be rare, and is only used to indicate that a previous request for

that channel is being abandoned.

• After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After

that one clock, LDRQ# signal can be brought low to the next encoding sequence.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-33

Functional Description

If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#.

For example, if an encoded request is sent for channel 2 and then channel 3 needs a transfer before

the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for

channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC

interface and the I/O device does not need to self-arbitrate before sending the message.

Figure 5-11. DMA Request Assertion Through LDRQ#

LCLK

LDRQ#

Start

MSB

LSB

ACT

Start

5.5.9

Abandoning DMA Requests

DMA requests can be deasserted in two fashions: on error conditions by sending an LDRQ#

message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the DMA transfer.

This section describes boundary conditions where the DMA request needs to be removed prior to a

data transfer.

There may be some special cases where the peripheral desires to abandon a DMA transfer. The

most likely case of this occurring is due to a floppy disk controller that has overrun or underrun its

FIFO, or software stopping a device prematurely.

In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an

LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the ICH2,

there is no guarantee that the cycle has not been granted and will shortly run on LPC. Therefore,

peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not

to respond to this cycle, in which case the host aborts it or the host can choose to complete the

cycle normally with any random data.

This method of DMA deassertion should be prevented when possible to limit boundary conditions

both on the ICH2 and the peripheral.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.5.10

General Flow of DMA Transfers

Arbitration for DMA channels is performed through the 8237 within the host. Once the host has

won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F

and begins the DMA transfer. The general flow for a basic DMA transfer is as follows:

1. ICH2 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.

2. ICH2 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.

3. ICH2 asserts channel number and, if applicable, terminal count.

4. ICH2 indicates the size of the transfer: 8 or 16 bits.

5. If a DMA read,

— The ICH2 drives the first 8 bits of data and turns the bus around.

— The peripheral acknowledges the data with a valid SYNC.

— If a 16 bit transfer, the process is repeated for the next 8 bits.

6. If a DMA write,

— The ICH2 turns the bus around and waits for data.

— The peripheral indicates data ready through SYNC and transfers the first byte.

— If a 16 bit transfer, the peripheral indicates data ready and transfers the next byte.

7. The peripheral turns around the bus.

5.5.11

5.5.12

Terminal Count

Terminal count is communicated through LAD[3] on the same clock that DMA channel is

communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last

byte of transfer, based upon the size of the transfer.

For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, this is the last byte.

On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, the second byte is the last byte.

Therefore, the peripheral must internalize the TC bit when the CHANNEL field is communicated

and only signal TC when the last byte of that transfer size has been transferred.

Verify Mode

Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a

DMA write where the peripheral is transferring data to main memory. The indication from the host

is the same as a DMA write, so the peripheral will be driving data onto the LPC interface.

However, the host does not transfer this data into main memory.

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Functional Description

5.5.13

DMA Request Deassertion

An end of transfer is communicated to the ICH2 through a special SYNC field transmitted by the

peripheral. An LPC device must not attempt to signal the end of a transfer by deasserting

LDREQ#. If a DMA transfer is several bytes (e.g., a transfer from a demand mode device), the

ICH2 needs to know when to deassert the DMA request based on the data currently being

transferred.

The DMA agent uses a SYNC encoding on each byte of data being transferred which indicates to

the ICH2 whether this is the last byte of transfer or if more bytes are requested. To indicate the last

byte of transfer, the peripheral uses a SYNC value of 0000b (ready with no error), or ‘1010b’

(ready with error). These encodings tell the ICH2 that this is the last piece of data transferred on a

DMA read (ICH2 to peripheral), or the byte which follows is the last piece of data transferred on a

DMA write (peripheral to ICH2).

When the ICH2 sees one of these two encodings, it ends the DMA transfer after this byte and

deasserts the DMA request to the 8237. Therefore, if the ICH2 indicated a 16 bit transfer, the

peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. The

ICH2 will not attempt to transfer the second byte, and will deassert the DMA request internally.

If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the indicated size,

then the ICH2 will only deassert the DMA request to the 8237 since it does not need to end the

transfer.

If the peripheral wishes to keep the DMA request active, it uses a SYNC value of 1001b (ready

plus more data). This indicates to the 8237 that more data bytes are requested after the current byte

has been transferred; the ICH2 keeps the DMA request active to the 8237. Therefore, on an 8-bit

transfer size, if the peripheral indicates a SYNC value of 1001b to the ICH2, the data will be

transferred and the DMA request remains active to the 8237. At a later time, the ICH2 will then

come back with another START - CYCTYPE - CHANNEL - SIZE etc. combination to initiate

another transfer to the peripheral.

The peripheral must not assume that the next START indication from the ICH2 is another grant to

the peripheral if it had indicated a SYNC value of 1001b. On a single mode DMA device, the 8237

re-arbitrates after every transfer. Only demand mode DMA devices can be guaranteed that they will

receive the next START indication from the ICH2.

Note: Indicating a 0000b or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit channel (first

byte of a 16 bit transfer) is an error condition.

Note: The host stops the transfer on the LPC bus as indicated, fill the upper byte with random data on

DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred,

incrementing the 8237’s address and decrementing its byte count.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.5.14

SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message and are ended

through a SYNC field during the DMA transfer, the peripheral must obey the following rule when

initiating back-to-back transfers from a DMA channel.

The peripheral must not assert another message for 8 LCLKs after a deassertion is indicated

through the SYNC field. This is needed to allow the 8237, which typically runs off a much slower

internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next

agent.

Under default operation, the host will only perform 8-bit transfers on 8-bit channels and 16-bit

transfers on 16-bit channels.

The method by which this communication between host and peripheral through system BIOS is

performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are

motherboard devices, no “plug-n-play” registry is required.

The peripheral must not assume that the host will be able to perform transfer sizes that are larger

than the size allowed for the DMA channel and be willing to accept a SIZE field that is smaller

than what it may currently have buffered.

To that end, it is recommended that future devices which may appear on the LPC bus, which

require higher bandwidth than 8 bit or 16 bit DMA allow, do so with a bus mastering interface and

not rely on the 8237.

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Functional Description

5.6

8254 Timers (D31:F0)

The ICH2 contains three counters that have fixed uses. All registers and functions associated with

the 8254 timers are in the Core well. The 8254 unit is clocked by a 14.31818 MHz clock.

Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is typically

programmed for Mode 3 operation. The counter produces a square wave with a period equal to the

product of the counter period (838 ns) and the initial count value. The counter loads the initial

count value one counter period after software writes the count value to the counter I/O address. The

counter initially asserts IRQ0 and decrements the count value by two each counter period. The

counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and

again decrements the initial count value by two each counter period. The counter then asserts IRQ0

when the count value reaches 0, reloads the initial count value, and repeats the cycle; alternately

asserting and negating IRQ0.

Counter 1, Refresh Request Signal

This counter provides the refresh request signal and is typically programmed for Mode 2 operation.

The counter negates refresh request for one counter period (838 ns) during each count cycle. The

initial count value is loaded one counter period after being written to the counter I/O address. The

counter initially asserts refresh request and negates it for 1 counter period when the count value

reaches 1. The counter then asserts refresh request and continues counting from the initial count

value.

Counter 2, Speaker Tone

This counter provides the speaker tone and is typically programmed for Mode 3 operation. The

counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by

the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and

Control ports).

5.6.1

Timer Programming

The counter/timers are programmed in the following fashion:

1. Write a control word to select a counter

2. Write an initial count for that counter.

3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the

16-bit counter.

4. Repeat with other counters

Only two conventions need to be observed when programming the counters. First, for each counter,

the control word must be written before the initial count is written. Second, the initial count must

follow the count format specified in the control word (least significant byte only, most significant

byte only, or least significant byte and then most significant byte).

A new initial count may be written to a counter at any time without affecting the counter's

programmed mode. Counting is affected as described in the mode definitions. The new count must

follow the programmed count format.

Caution: If a counter is programmed to read/write two-byte counts, the following applies: A program must

not transfer control between writing the first and second byte to another routine which also writes

into that same counter. Otherwise, the counter will be loaded with an incorrect count.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

The Control Word Register at port 43h controls the operation of all three counters. Several

commands are available:

• Control Word Command. Specifies which counter to read or write, the operating mode, and

the count format (binary or BCD).

• Counter Latch Command. Latches the current count so that it can be read by the system. The

countdown process continues.

• Read Back Command. Reads the count value, programmed mode, the current state of the

OUT pins, and the state of the Null Count Flag of the selected counter.

Table 5-14 lists the six operating modes for the interval counters.

Table 5-14. Counter Operating Modes

Mode

Function

Out signal on end of count (=0)

Description

Output is 0’. When count goes to 0, output goes to 1’ and

stays at 1’ until counter is reprogrammed.

Output is 0’. When count goes to 0, output goes to 1’ for

one clock time.

Hardware retriggerable one-shot

Output is 1’. Output goes to 0’ for one clock time, then

back to 1’ and counter is reloaded.

Rate generator (divide by n counter)

Output is 1’. Output goes to 0’ when counter rolls over,

and counter is reloaded. Output goes to 1’ when counter

rolls over, and counter is reloaded, etc.

Square wave output

Output is 1’. Output goes to 0’ when count expires for one

clock time.

Software triggered strobe

Hardware triggered strobe

Output is 1’. Output goes to 0’ when count expires for one

clock time.

5.6.2

Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in progress. There

are three methods for reading the counters: a simple read operation, counter Latch Command, and

the Read-Back Command. Each is explained below.

With the simple read and counter latch command methods, the count must be read according to the

programmed format; specifically, if the counter is programmed for two byte counts, two bytes must

be read. The two bytes do not have to be read one right after the other. Read, write, or programming

operations for other counters may be inserted between them.

Simple Read

The first method is to perform a simple read operation. The counter is selected through port 40h

(counter 0), 41h (counter 1), or 42h (counter 2).

Note: Performing a direct read from the counter will not return a determinate value because the counting

process is asynchronous to read operations. However, in the case of counter 2, the count can be

stopped by writing to the GATE bit in port 61h.

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Functional Description

Counter Latch Command

The Counter Latch Command, written to port 43h, latches the count of a specific counter at the

time the command is received. This command is used to ensure that the count read from the counter

is accurate, particularly when reading a two-byte count. The count value is then read from each

counter's Count Register as was programmed by the Control Register.

The count is held in the latch until it is read or the counter is reprogrammed. The count is then

unlatched. This allows reading the contents of the counters on the fly without affecting counting in

progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter

Latch Commands do not affect the programmed mode of the counter.

If a Counter is latched and then, some time later, latched again before the count is read, the second

Counter Latch Command is ignored. The count read will be the count at the time the first Counter

Latch Command was issued.

Read Back Command

The Read Back Command, written to port 43h, latches the count value, programmed mode, and

current states of the OUT pin and Null Count flag of the selected counter or counters. The value of

the counter and its status may then be read by I/O access to the counter address.

The Read Back Command may be used to latch multiple counter outputs at one time. This single

command is functionally equivalent to several counter latch commands, one for each counter

latched. Each counter's latched count is held until it is read or reprogrammed. Once read, a counter

is unlatched. The other counters remain latched until they are read. If multiple count Read Back

Commands are issued to the same counter without reading the count, all but the first are ignored.

The Read Back Command may additionally be used to latch status information of selected

counters. The status of a counter is accessed by a read from that counter's I/O port address. If

multiple counter status latch operations are performed without reading the status, all but the first

are ignored.

Both count and status of the selected counters may be latched simultaneously. This is functionally

the same as issuing two consecutive, separate Read Back Commands. If multiple count and/or

status Read Back Commands are issued to the same counters without any intervening reads, all but

the first are ignored.

If both count and status of a counter are latched, the first read operation from that counter will

return the latched status, regardless of which was latched first. The next one or two reads,

depending on whether the counter is programmed for one or two type counts, return the latched

count. Subsequent reads return unlatched count.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.7

8259 Interrupt Controllers (PIC) (D31:F0)

The ICH2 incorporates the functionality of two 8259 interrupt controllers that provide system

interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard

controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition,

this interrupt controller can support the PCI-based interrupts, by mapping the PCI interrupt onto the

compatible ISA interrupt line. Each 8259 core supports 8 interrupts, numbered 0–7. Table 5-15

shows how the cores are connected.

Table 5-15. Interrupt Controller Core Connections

8259

Input

Typical Interrupt

Source

8259

Connected Pin / Function

Internal

Keyboard

Internal Timer / Counter 0 output

IRQ1 via SERIRQ

Slave Controller INTR output

IRQ3 via SERIRQ

IRQ4 via SERIRQ

IRQ5 via SERIRQ

IRQ6 via SERIRQ

IRQ7 via SERIRQ

Internal

Serial Port A

Master

Serial Port B

Parallel Port / Generic

Floppy Disk

Parallel Port / Generic

Internal Real Time Clock Internal RTC

Generic

IRQ9 via SERIRQ

IRQ10 via SERIRQ

IRQ11 via SERIRQ

IRQ12 via SERIRQ

Generic

Slave

PS/2 Mouse

State Machine output based on processor FERR#

assertion.

Internal

Primary IDE cable

IRQ14 from input signal or via SERIRQ

IRQ15 from input signal or via SERIRQ

Secondary IDE Cable

The ICH2 cascades the slave controller onto the master controller through master controller

interrupt input 2. This means there are only 15 possible interrupts for the ICH2 PIC. Interrupts can

individually be programmed to be edge or level, except for IRQ[0, 2, 8#, 13].

Note that previous PIIXn devices internally latched IRQ[12 and 1] and required a port 60h read to

clear the latch. The ICH2 can be programmed to latch IRQ[12 or 1] (see bit 11 and bit 12 in

General Control Register, D31:F0, offset D0h).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

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Functional Description

5.7.1

Interrupt Handling

5.7.1.1

Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR for each interrupt

level. These bits are used to determine the interrupt vector returned, and status of any other pending

interrupts. Table 5-16 defines the IRR, ISR, and IMR.

Table 5-16. Interrupt Status Registers

Bit

Description

Interrupt Request Register. This bit is set on a low-to-high transition of the interrupt line in edge

mode and by an active high level in level mode. This bit is set whether or not the interrupt is masked.

However, a masked interrupt will not generate INTR.

IRR

Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt

acknowledge cycle is seen and the vector returned is for that interrupt.

ISR

Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will

not generate INTR.

IMR

5.7.1.2

Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle that is translated by the host bridge into a

PCI Interrupt Acknowledge Cycle to the ICH2. The PIC translates this command into two internal

INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the

state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends

the interrupt vector to the processor with the acknowledged interrupt code. This code is based on

bits [7:3] of the corresponding ICW2 register combined with three bits representing the interrupt

within that controller.

Table 5-17. Content of Interrupt Vector Byte

Master,Slave Interrupt

Bits [7:3]

Bits [2:0]

IRQ[7,15]

IRQ[6,14]

IRQ[5,13]

IRQ[4,12]

IRQ[3,11]

IRQ[2,10]

IRQ[1,9]

111

110

101

100

011

010

001

000

ICW2[7:3]

IRQ[0,8]

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.7.1.3

Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in

level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The

cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is

broadcast over PCI by the ICH2.

4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH2 converts it into the two

cycles that the internal 8259 pair can respond. Each cycle appears as an interrupt acknowledge

pulse on the internal INTA# pin of the cascaded interrupt controllers.

5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set

and the corresponding IRR bit is reset. On the trailing edge of the first pulse a slave

identification code is broadcast by the master to the slave on a private, internal three bit wide

bus. The slave controller uses these bits to determine if it must respond with an interrupt vector

during the second INTA# pulse.

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt

vector. If no interrupt request is present because the request was too short in duration, the PIC

will return vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second

INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued

at the end of the interrupt subroutine.

5.7.2

Initialization Command Words (ICWx)

Before the operation can begin, each 8259 must be initialized. In the ICH2 this is a four-byte

sequence. The four initialization command words are referred to by their acronyms: ICW1, ICW2,

ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the I/O memory

space: 20h for the master controller and A0h for the slave controller.

ICW1

An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted

as a write to ICW1. Upon sensing this write, the ICH2 PIC expects three more byte writes to 21h

for the master controller, or A1h for the slave controller, to complete the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to

generate an interrupt.

2. The Interrupt Mask Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special Mask Mode is cleared and Status Read is set to IRR.

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Functional Description

ICW2

The second write in the sequence (ICW2) is programmed to provide bits 7:3 of the interrupt vector

that will be released during an interrupt acknowledge. A different base is selected for each interrupt

controller.

ICW3

The third write in the sequence (ICW3) has a different meaning for each controller.

• For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the

slave controller. Within the ICH2, IRQ2 is used. Therefore, bit 2 of ICW3 on the master

controller is set to a 1 and the other bits are set to 0s.

• For the slave controller, ICW3 is the slave identification code used during an interrupt

acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code

to the slave controller if the cascaded interrupt won arbitration on the master controller. The

slave controller compares this identification code to the value stored in its ICW3, and if it

matches, the slave controller assumes responsibility for broadcasting the interrupt vector.

ICW4

The final write in the sequence (ICW4) must be programmed both controllers. At the very least, bit

0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based

system.

5.7.3

Operation Command Words (OCW)

These command words reprogram the Interrupt Controller to operate in various interrupt modes.

• OCW1 masks and unmasks interrupt lines.

• OCW2 controls the rotation of interrupt priorities when in rotating priority mode and controls

the EOI function.

• OCW3 is sets up ISR/IRR reads, enables/disables the Special Mask Mode SMM and enables/

disables polled interrupt mode.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.7.4

Modes of Operation

Fully Nested Mode

In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest.

When an interrupt is acknowledged, the highest priority request is determined and its vector placed

on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the

processor issues an EOI command immediately before returning from the service routine; or if in

AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further

interrupts of the same or lower priority are inhibited; higher levels will generate another interrupt.

Interrupt priorities can be changed in the rotating priority mode.

Special Fully Nested Mode

This mode will be used in the case of a system where cascading is used and the priority has to be

conserved within each slave. In this case, the special fully nested mode will be programmed to the

master controller. This mode is similar to the fully nested mode with the following exceptions:

• When an interrupt request from a certain slave is in service, this slave is not locked out from

the master's priority logic and further interrupt requests from higher priority interrupts within

the slave will be recognized by the master and will initiate interrupts to the processor. In the

normal nested mode, a slave is masked out when its request is in service.

• When exiting the Interrupt Service routine, software has to check whether the interrupt

serviced was the only one from that slave. This is done by sending a Non-Specific EOI

command to the slave and then reading its ISR. If it is 0, a non-specific EOI can also be sent to

the master.

Automatic Rotation Mode (Equal Priority Devices)

In some applications there are a number of interrupting devices of equal priority. Automatic

rotation mode provides for a sequential 8-way rotation. In this mode a device receives the lowest

priority after being serviced. In the worst case a device requesting an interrupt will have to wait

until each of seven other devices are serviced at most once.

There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific

EOI Command (R=1, SL=0, EOI=1) and the Rotate in Automatic EOI Mode which is set by

(R=1, SL=0, EOI=0).

Specific Rotation Mode (Specific Priority)

Software can change interrupt priorities by programming the bottom priority. For example, if IRQ5

is programmed as the bottom priority device, IRQ6 will be the highest priority device. The Set

Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO-L2 is the

binary priority level code of the bottom priority device.

In this mode, internal status is updated by software control during OCW2. However, it is

independent of the EOI command. Priority changes can be executed during an EOI command by

using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO–L2=IRQ level

to receive bottom priority.

Poll Mode

Poll Mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can

be serviced by one interrupt service routine do not need separate vectors if the service routine uses

the poll command. Polled Mode can also be used to expand the number of interrupts. The polling

interrupt service routine can call the appropriate service routine, instead of providing the interrupt

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-45

Functional Description

vectors in the vector table. In this mode, the INTR output is not used and the microprocessor

internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is

achieved by software using a Poll Command.

The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an

interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level.

Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read

will contain a 1’ in bit 7 if there is an interrupt, and the binary code of the highest priority level in

bits 2:0.

Cascade Mode

The PIC in the ICH2 has one master 8259 and one slave 8259 cascaded onto the master through

IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the

slaves through a 3-bit internal bus. In the ICH2, when the master drives 010b on this bus, the slave

controller takes responsibility for returning the interrupt vector. An EOI Command must be issued

twice: once for the master and once for the slave.

Edge-Triggered and Level-Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the

entire controller. In the ICH2, this bit is disabled and a new register for edge-triggered and level-

triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers

ELCR1 and ELCR2.

If an ELCR bit is 0’, an interrupt request will be recognized by a low to high transition on the

corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If

an ELCR bit is 1’, an interrupt request will be recognized by a high level on the corresponding IRQ

input and there is no need for an edge detection. The interrupt request must be removed before the

EOI command is issued to prevent a second interrupt from occurring.

In both the edge-triggered and level-triggered modes, the IRQ inputs must remain active until after

the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default

IRQ7 vector will be returned.

End of Interrupt Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC before

returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is

set to 1.

Normal End of Interrupt

In Normal EOI, software writes an EOI command before leaving the interrupt service routine to

mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-

Specific. When a Non-Specific EOI command is issued, the PIC will clear the highest ISR bit of

those that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the

ICH2, as the interrupt being serviced currently is the interrupt entered with the interrupt

acknowledge. When the PIC is operated in modes which preserve the fully nested structure,

software can determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked

will not be cleared by a Non-Specific EOI if the PIC is in the Special Mask Mode. An EOI

command must be issued for both the master and slave controller.

Automatic End of Interrupt Mode

In this mode, the PIC will automatically perform a Non-Specific EOI operation at the trailing edge

of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only

when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode

can only be used in the master controller and not the slave controller.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.7.5

Masking Interrupts

Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This

IRQ2 on the master controller will mask all requests for service from the slave controller.

Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the system priority

structure during its execution under software control. For example, the routine may wish to inhibit

lower priority requests for a portion of its execution but enable some of them for another portion.

The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register.

Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to

clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the Special Mask

Mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate

pattern. The special Mask Mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where

SSMM=1, SMM=0.

5.7.6

Steering PCI Interrupts

The ICH2 can be programmed to allow PIRQA#–PIRQH# to be internally routed to interrupts

[3:7, 9:12, 14 or 15]. The assignment is programmable through the PIRQx Route Control registers,

located at 60–63h and 68–6Bh in function 0. One or more PIRQx# lines can be routed to the same

IRQx input. If interrupt steering is not required, the Route Registers can be programmed to disable

steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI

Board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line,

software must change the IRQ's corresponding ELCR bit to level sensitive mode. The ICH2 will

internally invert the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is

routed onto the PIC, the selected IRQ can no longer be used by an ISA device (through SERIRQ).

However, active low non-ISA interrupts can share their interrupt with PCI interrupts.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-47

Functional Description

5.8

Advanced Interrupt Controller (APIC) (D31:F0)

In addition to the standard ISA compatible interrupt controller (PIC) described in the previous

section, the ICH2 incorporates the Advanced Programmable Interrupt Controller (APIC). While

the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in

either a uni-processor or multi-processor system.

5.8.1

Interrupt Handling

The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:

• Method of Interrupt Transmission. The I/O APIC transmits interrupts through a 3-wire bus

and interrupts are handled without the need for the processor to run an interrupt acknowledge

cycle.

• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt

number. For example, interrupt 10 can be given a higher priority than interrupt 3.

• More Interrupts. The I/O APIC in the ICH2 supports a total of 24 interrupts.

• Multiple Interrupt Controllers. The I/O APIC interrupt transmission protocol has an

arbitration phase that allows for multiple I/O APICs in the system with their own interrupt

vectors. The ICH2 I/O APIC must arbitrate for the APIC bus before transmitting its interrupt

message.

5-48

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.8.2

Interrupt Mapping

The I/O APIC within the ICH2 supports 24 APIC interrupts. Each interrupt has its own unique

vector assigned by software. The interrupt vectors are mapped as follows and match “configuration

6” of the Multi-processor specification.

Table 5-18. APIC Interrupt Mapping

Via

SERIRQ

Directfrom

Via PCI

message

IRQ #

Internal Modules

Cascade from 8259 #1

Yes

8254 Counter 0

Yes

RTC

Yes

Option for SCI, TCO

Yes

FERR# logic

Yes

PIRQA

PIRQB

PIRQC

PIRQD

N/A

PIRQA

PIRQB

PIRQC

PIRQD

PIRQE

PIRQF

PIRQG

PIRQH

AC’97 Audio, Modem, option for SMbus

USB #1

Yes

LAN, option for SCI, TCO

Option for SCI, TCO

USB #2, option for SCI, TCO

N/A

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-49

Functional Description

5.8.3

APIC Bus Functional Description

5.8.3.1

Physical Characteristics of APIC

The APIC bus is a 3-wire synchronous bus connecting all I/O and local APICs. Two of these wires

are used for data transmission and one wire is a clock. For bus arbitration, the APIC uses only one

of the data wires. The bus is logically a wire-OR and electrically an open-drain connection

providing for both bus use arbitration and arbitration for lowest priority. The APIC bus speed can

run from 16.67 MHz to 33 MHz.

5.8.3.2

APIC Bus Arbitration

The I/O APIC uses one wire arbitration to win bus ownership. A rotating priority scheme is used

for APIC bus arbitration. The winner of the arbitration becomes the lowest priority agent and

assumes an arbitration ID of 0. All other agents, except the agent whose arbitration ID is 15,

increment their Arbitration IDs by one. The agent whose ID was 15 will take the winner's

arbitration ID and will increment it by one. Arbitration IDs are changed only for messages that are

transmitted successfully (except for the Low Priority messages). A message is transmitted

successfully if no CS error or acceptance error was reported for that message.

An APIC agent can use two different priority schemes: Normal or EOI. EOI has the highest

priority. EOI priority is used to send EOI messages for level interrupts from a local APIC to an I/O

APIC. When an agent requests the bus with EOI priority, all other agents requesting the bus with

normal priorities will back off.

When ICH2 detects a bus idle condition on the APIC Bus and it has an interrupt to send over the

APIC bus, it drives a start cycle to begin arbitration, by driving bit 0 to a ‘0’ on an APICCLK rising

edge. It then samples bit 1. If Bit 1 was a ‘0’, then a local APIC started arbitration for an EOI

message on the same clock edge that the ICH2 started arbitration. Thus, the ICH2 has lost

arbitration and stops driving the APIC bus.

If the ICH2 did not detect an EOI message start, it will start transferring its arbitration ID, located

in bits [27:24] of its Arbitration ID register (ARBID). Starting in Cycle 2 through Cycle 5, it will

tri-state bit 0, and drive bit 1 to a ‘0’ if ARBID[27] is a ‘1’. If ARBID[27] is a ‘0’, it will also tri-

state bit 1. At the end of each cycle, the ICH2 samples the state of Bit 1 on the APIC bus. If the

ICH2 did not drive Bit 1 (ARBID[27] = ‘0’) and it samples a ‘0’, then another APIC agent started

arbitration for the APIC bus at the same time as the ICH2, and it has higher priority. The ICH2 will

stop driving the APIC bus. Table 5-19 describes the arbitration cycles.

Table 5-19. Arbitration Cycles

Cycle

Bit 1

EOI

Bit 0

Comment

Bit 1 = 1: Normal, Bit 1 = 0: EOI

NOT (ARBID[27])

NOT (ARBID[26])

NOT (ARBID[25])

NOT (ARBID[24])

Arbitration ID. If ICH2 samples a different value than it sent, it

lost arbitration.

5-50

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.8.3.3

Bus Message Formats

After bus arbitration, the winner is granted exclusive use of the bus and will drive its message.

APIC messages come in four formats determined by the delivery mode bits. These four messages

are of different length and are known by all APICs on the bus through the transmission of the

Delivery Mode bits.

Table 5-20. APIC Message Formats

# of

Cycles

Delivery Mode

Bits

Message

Comments

End of Interrupt transmission from Local APIC to I/O APIC

on Level interrupts. EOI is known by the EOI bit at the start

of arbitration.

EOI

xxx

001, 010, 100,

101, 111

I/O APIC delivery on Fixed, NMI, SMI, Reset, ExtINT, and

Lowest Priority with focus processor messages.

Short

Transmission of Lowest Priority interrupts when the status

field indicates that the processor does not have focus.

Lowest Priority

Remote Read

001

011

Message from one Local APIC to another to read registers.

EOI Message For Level-Triggered Interrupts

EOI messages are used by local APICs to send an EOI cycle occurring for a level-triggered

interrupt to an I/O APIC. This message is needed so that the I/O APIC can differentiate between a

new interrupt on the interrupt line versus the same interrupt on the interrupt line. The target of the

EOI is given by the local APIC through the transmission of the priority vector (V7 through V0) of

the interrupt. Upon receiving this message, the I/O APIC resets the Remote IRR bit for that

interrupt. If the interrupt signal is still active after the IRR bit is reset, the I/O APIC will treat it as a

new interrupt.

Table 5-21. EOI Message

Cycle

Bit 1

Bit 0

Comments

EOI message

Arbitration ID

2–5

ARBID

Interrupt vector bits V7 - V0 from redirection table

NOT(V7)

NOT(V6)

NOT(V5)

NOT(V3)

NOT(V1)

NOT(C1)

NOT(V4)

NOT(V2)

NOT(V0)

NOT(C0)

Check Sum from Cycles 6 - 9

Postamble

NOT(A)

NOT(A1)

NOT(A)

NOT(A1)

Status Cycle 0

Status Cycle 1

Idle

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-51

Functional Description

Short Message

Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT and Lowest Priority

with Focus processor interrupts. The delivery mode bits (M2-M0) specify the message. All short

messages take 21 cycles including the idle cycle.

Table 5-22. Short Message

Cycle

Bit 1

Bit 0

Comments

Normal Arbitration

2–5

ARBID

Arbitration ID

DM = Destination Mode from bit 11 of the redirection table

NOT(DM)

NOT(M2)

NOT(M0)

M2-M0 = Delivery Mode from bits 10:8 of the redirection table

NOT(M1)

NOT(L)

NOT(V7)

NOT(V5)

NOT(V3)

NOT(V1)

NOT(D7)

NOT(D5)

NOT(D3)

NOT(D1)

NOT(C1)

NOT(TM)

NOT(V6)

NOT(V4)

NOT(V2)

NOT(V0)

NOT(D6)

NOT(D4)

NOT(D2)

NOT(D0)

NOT(C0)

L = Level, TM = Trigger Mode

Interrupt vector bits V7–V0 from redirection table register

Destination field from bits 63:56 of redirection table register

Checksum for Cycles 6–16

Postamble

NOT(A)

NOT(A1)

NOT(A)

NOT(A1)

Status Cycle 0. See Table 5-23.

Status Cycle 1. See Table 5-23.

Idle

NOTES:

1. If DM is 0 (physical mode), then cycles 15 and 16 are the APIC ID and cycles 13 and 14 are sent as ‘1’. If DM

is 1 (logical mode), then cycles 13 through 16 are the 8-bit Destination field. The interpretation of the logical

mode 8-bit Destination field is performed by the local units using the Destination Format Register.

Shorthands of "all-incl-self" and "all-excl-self" both use Physical Destination mode and a destination field

containing APIC ID value of all ones. The sending APIC knows whether it should (incl) or should not (excl)

respond to its own message.

2. The checksum field is the cumulative add (mod 4) of all data bits (DM, M0-3, L, TM, V0-7,D0-7). The APIC

driving the message provides this checksum. This, in essence, is the lower two bits of an adder at the end of

the message.

3. This cycle allows all APICs to perform various internal computations based on the information contained in

the received message. One of the computations takes the checksum of the data received in cycles 6 through

16 and compares it with the value in cycle 18. If any APIC computes a different checksum than the one

passed in cycle 17, then that APIC will signal an error on the APIC bus (“00”) in cycle 19. If this happens, all

APICs will assume the message was never sent and the sender must try sending the message again, which

includes re-arbitrating for the APIC bus. In lowest priority delivery when the interrupt has a focus processor,

the focus processor will signal this by driving a “01” during cycle 19. This tells all the other APICs that the

interrupt has been accepted, the arbitration is preempted, and short message format is used. Cycle 19 and

20 indicates the status of the message (i.e., accepted, check sum error, retry or error). Table 5-23 shows the

status signal combinations and their meanings for all delivery modes.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-23. APIC Bus Status Cycle Definition

Delivery Mode

Comments

11 Checksum OK

1x Error

01 Accepted

00 Retry

Fixed, EOI

10 Error

01 Error

00 Checksum Error

11 Checksum OK

1x Error

01 Accepted

00 Error

NMI, SMM, Reset,

ExtINT

10 Error

01 Error

00 Checksum Error

Checksum OK: No Focus

Processor

1x Error

01 End and Retry

00 Go for Low Priority Arbitration

Lowest Priority

10 Error

Checksum OK: Focus

Processor

00 Checksum Error

11 Checksum OK

10 Error

Remote Read

01 Error

00 Checksum Error

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-53

Functional Description

Lowest Priority without Focus Processor (FP) Message

This message format is used to deliver an interrupt in the lowest priority mode in which it does not

have a Focus Process. Cycles 1 through 21 for this message are same as for the short message

discussed above. Status cycle 19 identifies if there is a Focus processor (10) and a status value of

11 in cycle 20 indicates the need for lowest priority arbitration.

Table 5-24. Lowest Priority Message (Without Focus Processor)

Cycle

Bit 1

Bit 0

Comments

2–5

Normal Arbitration

Arbitration ID

ARBID

NOT(DM)

NOT(M2)

DM = Destination Mode from bit 11 of the redirection table register

M2-M0 = Delivery Mode from bits 10:8 of the redirection table

NOT(M1)

NOT(M0)

NOT(L)

NOT(V7)

NOT(V5)

NOT(V3)

NOT(V1)

NOT(D7)

NOT(D5)

NOT(D3)

NOT(D1)

NOT(C1)

NOT(TM)

L = Level, TM = Trigger Mode

NOT(V6)

NOT(V4)

Interrupt vector bits V7–V0 from redirection table register

NOT(V2)

NOT(V0)

NOT(D6)

NOT(D4)

Destination field from bits 63:56 of redirection table register

NOT(D2)

NOT(D0)

NOT(C0)

Checksum for Cycles 6–16

Postamble

NOT(A)

NOT(A1)

NOT(A)

Status Cycle 0.

NOT(A1)

Status Cycle 1.

Inverted Processor Priority P7–P0

ArbID3

ArbID2

ArbID1

ArbID0

Status

Idle

NOTES:

1. Cycle 21 through 28 are used to arbitrate for the lowest priority processor. The processor that takes part in

the arbitration drives the processor priority on the bus. Only the local APICs that have "free interrupt slots" will

participate in the lowest priority arbitration.

2. Cycles 29 through 32 are used to break tie in case two more processors have lowest priority. The bus

arbitration IDs are used to break the tie.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Remote Read Message

Remote read message is used when a local APIC wishes to read the register in another local APIC.

The message format is same as short message for the first 21 cycles.

Table 5-25. Remote Read Message

Cycle

Bit 1

Bit 0

Comments

Normal Arbitration

Arbitration ID

2–5

ARBID

NOT(DM)

NOT(M2)

DM = Destination Mode from bit 11 of the redirection table register

M2-M0 = Delivery Mode from bits 10:8 of the redirection table

NOT(M1)

NOT(M0)

NOT(L)

NOT(V7)

NOT(V5)

NOT(V3)

NOT(V1)

NOT(D7)

NOT(D5)

NOT(D3)

NOT(D1)

NOT(C1)

NOT(TM)

NOT(V6)

NOT(V4)

NOT(V2)

NOT(V0)

NOT(D6)

NOT(D4)

NOT(D2)

NOT(D0)

NOT(C0)

L = Level, TM = Trigger Mode

Interrupt vector bits V7 - V0 from redirection table register

Destination field from bits 63:56 of redirection table register

Checksum for Cycles 6 - 16

Postamble

NOT(A)

NOT(A1)

d31

NOT(A)

NOT(A1)

d30

Status Cycle 0.

Status Cycle 1.

d29

d28

d27

d26

d25

d24

d23

d22

d21

d20

d19

d18

d17

d16

Remote register data 31-0

d15

d14

d13

d12

d11

d10

d09

d08

d07

d06

d05

d04

d03

d02

d01

d00

Data Status: 00 = valid, 11 = invalid

Check Sum for data d31-d00

Idle

NOTE: Cycle 21 through 36 contain the remote register data. The status information in cycle 37 specifies if the

data is good or not. Remote read cycle is always successful (although the data may be valid or invalid)

in that it is never retried. The reason for this is that Remote Read is a debug feature, and a "hung"

remote APIC that is unable to respond should not cause the debugger to hang.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-55

Functional Description

5.8.4

PCI Message-Based Interrupts

5.8.4.1

Theory of Operation

The following scheme is only supported when the internal I/O(x) APIC is used (rather than just the

8259). The ICH2 supports the new method for PCI devices to deliver interrupts as write cycles,

rather than using the traditional PIRQ[A:D] signals. Essentially, the PCI devices are given a write

path directly to a register that will cause the desired interrupt. This mode is only supported when

the ICH2’s internal I/O APIC is enabled. Upon recognizing the write from the peripheral, the ICH2

sends the interrupt message to the processor using the I/O APIC’s serial bus.

The interrupts associated with the PCI Message-based interrupt method must be set up for edge-

triggered mode (rather than level-triggered) since the peripheral only does the write to indicate the

edge.

The following sequence is used:

1. During PCI PnP, the PCI peripheral is first programmed with an address

(MESSAGE_ADDRESS) and data value (MESSAGE_DATA) that will be used for the

interrupt message delivery. For the ICH2, the MESSAGE_ADDRESS is the IRQ Pin

Assertion Register, which is mapped to memory location: FEC0_0020h (same as APIC).

2. To cause the interrupt, the PCI peripheral requests the PCI bus and when granted, writes the

MESSAGE_DATA value to the location indicated by the MESSAGE_ADDRESS. The

MESSAGE_DATA value indicates which interrupt occurred. This MESSAGE_DATA value is

a binary encoded. For example, to indicate that interrupt 7 should go active, the peripheral will

write a binary value of 0000111. The MESSAGE_DATA will be a 32-bit value, although only

the lower 5 bits are used.

3. If the PRQ bit in the APIC Version Register is set, the ICH2 positively decodes the cycles (as a

slave) in medium time.

4. The ICH2 decodes the binary value written to MESSAGE_ADDRESS and sets the appropriate

IRR bit in the internal I/O APIC. The corresponding interrupt must be set up for edge-

triggered interrupts. The ICH2 supports interrupts 00h through 23h. Binary values outside this

range will not cause any action.

5. After sending the interrupt message to the processor, the ICH2 automatically clears the

interrupt.

Because they are edge-tiggered, the interrupts that are allocated to the PCI bus for this scheme may

not be shared with any other interrupt (e.g., the standard PCI PIRQ[A:D], those received via

SERIRQ#, or the internal level-triggered interrupts such as SCI or TCO).

The ICH2 ignores interrupt messages sent by PCI masters that attempt to use IRQ[0,2,8, or 13].

5.8.4.2

Registers and Bits Associated with PCI Interrupt Delivery

Capabilities Indication

The capability to support PCI interrupt delivery will be indicated via ACPI configuration

techniques. This involves the BIOS creating a data structure that gets reported to the ACPI

configuration software. The operating system reads the PRQ bit in the APIC Version Register to

see if the ICH2 is capable of support PCI-based interrupt messages. As a precaution, the PRQ bit is

not set if the XAPIC_EN bit is not set.

Interrupt Message Register

The PCI devices all write their message into the IRQ Pin Assertion Register, which is a memory-

mapped register located at the APIC base memory location + 20h.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.8.5

Front-Side Interrupt Delivery

5.8.5.1

Theory of Operation

For processors that support Front-Side Bus interrupt delivery, the ICH2 has an option to let the

integrated I/O APIC behave as an I/O (x) APIC. In this case, it delivers interrupt messages to the

processor in a parallel manner, rather than using the I/O APIC serial scheme. The ICH2 is intended

to be compatible with the I/O (x) APIC specification, Revision 1.1.

This is done by the ICH2 writing (via the Hub Interface) directly to a memory location that is

snooped by the processor(s). The processor(s) snoop the cycle to know which one goes active.

The processor enables the mode by setting the I/O APIC Enable (APIC_EN) bit and by setting the

DT bit in the I/O APIC ID register.

The following sequence is used:

1. When the ICH2 detects an interrupt event (active edge for edge-triggered mode or a change for

level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt.

2. Internally, the ICH2 requests to use the bus in a way the automatically flushes upstream

buffers. This can be internally implemented similar to a DMA device request.

3. The ICH2 then delivers the message by performing a write cycle to the appropriate address

with the appropriate data. The address and data formats are described below in Section 5.8.5.5.

Notes:

1. FSB Interrupt Delivery compatibility with processor clock control depends on the processor,

not the ICH2.

2. FSB Interrupt Delivery compatibility with processor clock control depends on the processor,

not the ICH2.

3. 82801BAM (ICH2-M): FSB is not recommended in a mobile environment. For ICH2-M, if

FSB Interrupt Delivery Mode is used, the system cannot support Intel^®SpeedStep^TM

technology, C2, C3, software clock throttling or hardware thermal throttling.

5.8.5.2

5.8.5.3

Edge-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.

The “Deassert Message” is not used.

Level-Triggered Operation

In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.

If after the EOI the interrupt is still active, then another “Assert Message” is sent to indicate that the

interrupt is still active.

If the interrupt was active but goes inactive before the EOI is received, the “Deassert Message” is

sent.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-57

Functional Description

5.8.5.4

Registers Associated with Front-Side Bus Interrupt Delivery

Capabilities Indication

The capability to support Front-Side bus interrupt delivery will be indicated via ACPI

configuration techniques. This involves BIOS creating a data structure that gets reported to the

ACPI configuration software.

DT bit in the Boot Configuration Register

This enables the ICH2 to deliver interrupts as memory writes. This bit is ignored if the APIC mode

is not enabled.

5.8.5.5

Interrupt Message Format

ICH2 writes the message to PCI (and to the Host Controller) as a 32-bit memory write cycle. It uses

the formats shown in Table 5-26 and Table 5-27 for the address and data.

Table 5-26. Interrupt Message Address Format

Bit

Description

31:20

19:12

11:4

Will always be FEEh

Destination ID: This is the same as bits 63:56 of the I/O Redirection Table entry for the interrupt

associated with this message.

Reserved (will always be 0)

Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be

redirected.

0 = The message will be delivered to the agent (processor) listed in bits 19:4.

1 = The message will be delivered to an agent with a lower interrupt priority This can be derived from

bits 10:8 in the Data Field (see below).

The Redirection Hint bit = 1 if bits 10:8 in the Delivery Mode field associated with corresponding

interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit = 0.

Destination Mode: This bit is used only the Redirection Hint bit = 1. If the Redirection Hint bit and

the Destination Mode bit are both set to 1, the logical destination mode is used and the redirection is

limited only to those processors that are part of the logical group as based on the logical ID.

1:0

Will always be 00.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-27. Interrupt Message Data Format

Bit

Description

31:16

Will always be 0000h.

Trigger Mode: Same as the corresponding bit in the I/O Redirection Table for that interrupt.

1 = Level

0 = Edge.

Delivery Status: If using edge-triggered interrupts, then this bit will always be 1, since only the

assertion is sent. If using level-triggered interrupts, then this bit indicates the state of the interrupt

input.

1 = Assert

0 = Deassert

13:12

Will always be 00

Destination Mode: Same as the corresponding bit in the I/O Redirection Table for that interrupt.

1 = Logical.

0 = Physical.

Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that

interrupt.

000 = Fixed

100 = NMI

10:8

7:0

001 = Lowest Priority

010 = SMI/PMI

011 = Reserved

101 = INIT

110 = Reserved

111 = ExtINT

Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-59

Functional Description

5.9

Serial Interrupt (D31:F0)

ICH2 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt

requests. The signal (used to transmit this information) is shared between the host, the ICH2, and

all peripherals that support serial interrupts. The signal line (SERIRQ) is synchronous to PCI clock

and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a

device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the

following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the

following fashion:

• S - Sample Phase. Signal driven low

• R - Recovery Phase. Signal driven high

• T - Turn-around Phase. Signal released

The ICH2 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts

(IRQ[0,1, 2:15]), the four PCI interrupts, and the SMI# and IOCHK# control signals. The serial

IRQ protocol does not support the additional APIC interrupts (20–23).

5.9.1

Start Frame

The serial IRQ protocol has two modes of operation which affect the start frame. These two modes

are:

• Continuous, where the ICH2 is solely responsible for generating the start frame

• Quiet, where a serial IRQ peripheral is responsible for beginning the start frame.

The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In

this mode, the ICH2 will assert the start frame. This start frame is 4, 6, or 8 PCI clocks wide based

upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space.

This is a polling mode.

When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line

remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the

SERIRQ signal low. The ICH2 senses the line low and continues to drive it low for the remainder

of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this

mode, the ICH2 drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This

mode of operation allows for a quiet and, therefore, lower power operation.

5.9.2

Data Frames

Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames

based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of

1 clock each:

• Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the

corresponding interrupt signal is low. If the corresponding interrupt is high, the SERIRQ

devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors. A

low level during the IRQ0-1 and IRQ2-15 frames indicates that an active-high ISA interrupt is

not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame

indicates that an active-low interrupt is being requested.

• Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample

Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase.

• Turn-around Phase. The device will tri-state the SERIRQ line.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.9.3

Stop Frame

After all data frames, a Stop Frame is driven by ICH2. The SERIRQ signal is driven low by ICH2

for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration register.

The number of clocks determines the next mode.

Table 5-28. Stop Frame Explanation

Stop Frame Width

Next Mode

2 PCI clocks

3 PCI clocks

Quiet Mode. Any SERIRQ device may initiate a Start Frame

Continuous Mode. Only the host (ICH2) may initiate a Start Frame

5.9.4

Specific Interrupts not Supported via SERIRQ

There are three interrupts seen through the serial stream that are not supported by the ICH2. These

interrupts are generated internally and are not sharable with other devices within the system. These

interrupts are:

• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.

• IRQ8#. RTC interrupt can only be generated internally.

• IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#.

ICH2 ignores the state of these interrupts in the serial stream, and does not adjust their level based

on the level seen in the serial stream. In addition, the interrupts IRQ14 and IRQ15 from the serial

stream are treated differently than their ISA counterparts. These two frames are not passed to the

Bus Master IDE logic. The Bus Master IDE logic expects IDE to be behind the ICH2.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-61

Functional Description

5.9.5

Data Frame Format

Table 5-29 shows the format of the data frames. For the PCI interrupts (A-D), the output from the

ICH2 is ANDed with the PCI input signal. Thus, the interrupt can be signaled via both the PCI

interrupt input signal and via the SERIRQ signal (they are shared).

Table 5-29. Data Frame Format

Data

Frame #

Clocks Past

Start Frame

Interrupt

Comment

IRQ0

IRQ1

Ignored. IRQ0 can only be generated via the internal 8524

SMI#

Causes SMI# if low. Sets the SERIRQ_SMI_STS bit.

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

Ignored. IRQ8# can only be generated internally or on ISA.

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IOCHCK#

PCI INTA#

PCI INTB#

PCI INTC#

PCI INTD#

Ignored. IRQ13 can only be generated from FERR#

Do not include in BM IDE interrupt logic

Same as ISA IOCHCK# going active.

Drive PIRQA#

Drive PIRQB#

Drive PIRQC#

Drive PIRQD#

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.10

Real Time Clock (D31:F0)

The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device

with two banks of static RAM (128 bytes each); the first bank has 114 bytes for general purpose

usage. Three interrupt features are available: time of day alarm with once a second to once a month

range, periodic rates of 122 us to 500 ms, and end of update cycle notification. Seconds, minutes,

hours, days, day of week, month, and year are counted. Daylight savings compensation is optional.

The hour is represented in twelve or twenty-four hour format, and data can be represented in BCD

or binary format. The design is meant to be functionally compatible with the Motorola*

MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided to

achieve an update every second. The lower 14 bytes on the lower RAM block has very specific

functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers

that configure and report RTC functions.

The time and calendar data should match the data mode (BCD or binary) and hour mode

(12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in

these locations is within the reasonable values ranges and represents a possible date and time. The

exception to these ranges is to store a value of C0–FFh in the Alarm bytes to indicate a don’t care

situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm

Interrupt, if enabled. The SET bit must be 1 while programming these locations to avoid clashes

with an update cycle. Access to time and date information is done through the RAM locations. If a

RAM read from the ten time and date bytes is attempted during an update cycle, the value read will

not necessarily represent the true contents of those locations. Any RAM writes under the same

conditions will be ignored.

Note: The ICH2 supports the ability to generate an SMI# based on year 2000 rollover. See Section 5.10.4

for more information on the century rollover.

The ICH2 does not implement month/year alarms.

5.10.1

Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide

chain is properly configured. During this procedure, the stored time and date is incremented,

overflow checked, a matching alarm condition checked, and the time and date are rewritten to the

RAM locations. The update cycle starts at least 488 us after the UIP bit of register A is asserted and

the entire cycle does not take more than 1984 us to complete. The time and date RAM locations

(0–9) are disconnected from the external bus during this time.

To avoid update and data corruption conditions, external RAM access to these locations can safely

occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read

and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at

least 488 us before the update cycle begins.

Warning: The overflow conditions for leap years and daylight savings adjustments are based on more than

one date or time item. To ensure proper operation when adjusting the time, the new time and data

values should be set at least two seconds before one of these conditions (leap year, daylight savings

time adjustments) occurs.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-63

Functional Description

5.10.2

5.10.3

Interrupts

The real-time clock interrupt is internally routed within the ICH2 both to the I/O APIC and the

8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH2, nor is it shared with

any other interrupt. IRQ8# from the SERIRQ stream is ignored.

Lockable RAM Ranges

The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the

configuration space. If the locking bits are set, the corresponding range in the RAM are not

readable or writable. A write cycle to those locations has no effect. A read cycle to those locations

does not return the location’s actual value (may be all 0s or all 1s).

Once a range is locked, the range can be unlocked only by a hard reset, which invokes BIOS and

allows it to relock the RAM range.

5.10.4

5.10.5

Century Rollover

ICH2 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form

99 to 00. Upon detecting the rollover, the ICH2 sets the NEWCENTURY_STS bit

(TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler

can update registers in the RTC RAM that are associated with century value. If the system is in a

sleep state (S1–S5) when the century rollover occurs, the ICH2 also sets the NEWCENTURY_STS

bit; no SMI# is generated. When the system resumes from the sleep state, BIOS should check the

NEWCENTURY_STS bit and update the century value in the RTC RAM.

Clearing Battery-Backed RTC RAM

Clearing CMOS RAM in an ICH2-based platform can be done by using a jumper on RTCRST# or

GPI or using the SAFEMODE strap. Implementations should not attempt to clear CMOS by using

a jumper to pull VccRTC low.

Using RTCRST# to clear CMOS

A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of

the configuration bits that reside in the RTC power well. When the RTCRST# is strapped to

ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) is set and the configuration bits in the RTC

power well are set to their default state. BIOS can monitor the state of this bit and manually clear

the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be

pulled up through a weak pull-up resistor. Table 5-30 shows which bits are set to their default state

when RTCRST# is asserted.

RTCRST# should be used to reset configuration bits (and signal BIOS to clear CMOS) ONLY in a

G3 state. Additionally, RTCRST# assertion while power is on must ONLY be done to invoke the

test modes, and that it should only be asserted for the specific number of clocks to invoke the

desired test mode. Assertion for any other number of clocks may put the component into an

indeterminate state, which is not supported.

5-64

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-30. Configuration Bits Reset By RTCRST# Assertion

Bit Name

GEN_STS

Location

D31:F0:D4h

Bits

Default Value

FREQ_STRAP[3:0]

AIE

11:8

1111b

RTC Reg B

RTC Reg C

GEN_PMCON_3

PM1_STS

I/O space

PWR_FLR

D31:F0:A4h

PMBase + 00h

AFTERG3_EN

RTC_PWR_STS

PRBTNOR_STS

PME_EN

GPE0_EN

PMBase + 2Ah

TCOBase + 04h

TCOBase + 06h

D31:F0:D4h

RI_EN

GPE0_EN

NEW_CENTURY_STS

INTRD_DET

TOP_SWAP

RTC_EN

TCO1_STS

TCO2_STS

GEN_STS

PM1_EN

PMBase + 02h

BATLOW_EN

(ICH2-M only)

GPE0_EN

PMBase + 2Ah

Using a GPI to clear CMOS

A jumper on a GPI can also be used to clear CMOS values. BIOS detects the setting of this GPI on

system boot-up and manually clear the CMOS array.

Using the SAFEMODE Strap to clear CMOS

A jumper on AC_SDOUT (SAFEMODE strap) can also be used to clear CMOS values. BIOS

detects the setting of the SAFE_MODE status bit (D31:F0: Offset D4h bit 2) on system boot-up,

and manually clear the CMOS array.

Note: Both the GPI and SAFEMODE strap techniques to clear CMOS require multiple steps to

implement. The system is booted with the jumper in a new position, then powered back down. The

jumper is replaced back to the normal position, then the system is rebooted again. The RTCRST#

jumper technique allows the jumper to be moved and then replaced, all while the system is

powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state.

Note: Clearing CMOS, using a jumper on VCCRTC, must NOT be implemented.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-65

Functional Description

5.11

Processor Interface (D31:F0)

The ICH2 interfaces to the processor with a variety of signals:

• Standard outputs to the processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#,

CPUSLP#

• Standard input from the processor: FERR#

• For ICH2-M, Intel^®SpeedStep^TMOutput to the processor: CPUPWRGOOD

Most ICH2 outputs to the processor use standard buffers. The ICH2 has a separate Vcc signal that

is pulled up at the system level to the processor voltage and thus, determines Voh for the outputs to

the processor. Note that this is different than previous generations of chips that have used open-

drain outputs. This new method saves up to 12 external pull-up resistors.

The ICH2 also handles the speed setting for the processor by holding specific signals at certain

states just prior to CPURST going inactive. This avoids the glue often required with other chipsets.

The ICH2 does not support the processor’s FRC mode.

5.11.1

Processor Interface Signals

This section describes each of the signals that interface between the ICH2 and the processor(s).

Note that the behavior of some signals may vary during processor reset, as the signals are used for

frequency strapping.

5.11.1.1

A20M#

The A20M# signal is active (low) when both of the following conditions are true:

• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0

• The A20GATE input signal is a 0

The A20GATE input signal is expected to be generated by the external microcontroller (KBC).

5.11.1.2

INIT#

The INIT# signal is active (driven low) based on any one of several events described in Table 5-31.

When any of these events occur, INIT# is driven low for 16 PCI clocks, then driven high.

Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if INIT# is

supposed to go active while STPCLK# is asserted, it actually goes active after STPCLK# goes

inactive.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-31. INIT# Going Active

Cause of INIT# Going Active

Comment

Shutdown special cycle from the processor.

PORT92 write, where INIT_NOW (bit 0) transitions

from a 0 to a 1.

PORTCF9 write, where RST_CPU (bit 2) was a 0

and SYS_RST(bit 1) transitions from 0 to 1.

RCIN# input signal goes low. RCIN# is expected to 0 to 1 transition on RCIN# must occur before the ICH2

be driven by the external microcontroller (KBC).

arms INIT# to be generated again.

To enter BIST, the software sets CPU_BIST_EN bit and

then does a full processor reset using the CF9 register.

Processor BIST

5.11.1.3

FERR#/IGNNE# (Coprocessor Error)

The ICH2 supports the coprocessor error function with the FERR#/IGNNE# pins. The function is

enabled via the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, bit 13). FERR# is tied

directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the

processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register,

the ICH2 negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until

FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active.

Figure 5-12. Coprocessor Error Timing Diagram

FERR#

Internal IRQ13

I/O Write to F0h

IGNNE#

If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal IRQ13; the

write to F0h will not generate IGNNE#.

5.11.1.4

NMI

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-32.

Table 5-32. NMI Sources

Cause of NMI

Comment

SERR# goes active (either internally, externally Can instead be routed to generate an SCI, through the

via SERR# signal, or via message from MCH)

NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).

IOCHK# goes active via SERIRQ# stream

(ISA system Error)

Can instead be routed to generate an SCI, through the

NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-67

Functional Description

5.11.1.5

5.11.1.6

STPCLK# and CPUSLP# Signals

The ICH2 power management logic controls these active-low signals. Refer to Section 5.12 for

more information on the functionality of these signals.

CPUPWRGOOD Signal

This signal is connected to the processor’s PWRGOOD input. This is an open-drain output signal

(external pull-up resistor required) that represents a logical AND of the ICH2’s PWROK and

VRMPWRGD (VGATE/VRMPWRGD for ICH2-M) signals.

82801BAM ICH2-M: For Intel^®SpeedStep^TMtechnology support, this signal is kept high during

a Intel^®SpeedStep^TMstate transition to prevent loss of processor context.

5.11.2

Dual Processor Issues (82801BA ICH2 only)

5.11.2.1

Signal Differences (82801BA ICH2 only)

In dual-processor designs, some of the processor signals are unused or used differently than for

uniprocessor designs.

Table 5-33. DP Signal Differences (82801BA ICH2 only)

Signal

Difference

A20M# / A20GATE

Generally not used, but still supported by the 82801BA ICH2.

Used for S1 State as well as preparation for entry to S3–S5

STPCLK#

Also allows for THERM# based throttling (not via ACPI control methods).

Should be connected to both processors.

FERR# / IGNNE#

Generally not used, but still supported by 82801BA ICH2.

5.11.2.2

Power Management (82801BA ICH2 only)

For the 82801BA ICH2, attempting clock control with more than one processor is not feasible.

This is because the host controller does not provide any indication as to which processor is

executing a particular Stop-Grant cycle. Without this information, there is no way for the ICH2 to

know when it is safe to deassert STPCLK#.

Because the S1 state has the STPCLK# signal active, the STPCLK# signal can be connected to

both processors. However, for ACPI implementations, the ICH2 does not support the C2 state for

both processors, since there are not two processor control blocks. BIOS must indicate that the

ICH2 only supports the C1 state for dual-processor designs. However, the THRM# signal can be

used for overheat conditions to activate thermal throttling.

When entering S1, the ICH2 asserts STPCLK# to both processors. To meet the processor

specifications, the CPUSLP# signal has to be delayed until the 2^ndStop-Grant cycle occurs. To

ensure this, the ICH2 waits a minimum or 60 PCI clocks after receipt of the first Stop-Grant cycle

before asserting CPUSLP# (if the SLP_EN bit is set to 1).

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Both processors must immediately respond to the STPCLK# assertion with stop grant

acknowledge cycles before the 82801BA ICH2 asserts CPUSLP# to meet the processor setup time

for CPUSLP#. Meeting the processor setup time for CPUSLP# is not an issue if both processors

are idle when the system is entering S1. If it cannot be guaranteed that both processors will be idle,

the SLP_EN bit must not be enabled. Note that setting SLP_EN to 1 is not required to support S1

in a dual-processor configuration.

In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state and thus,

STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose

power. Upon exit from those states, the processors will have their power restored.

5.11.3

Speed Strapping for Processor

The ICH2 directly sets the speed straps for the processor, saving the external logic that has been

needed with prior PCIsets. Refer to the processor specification for speed strapping definition. The

ICH2 performs the following to set the speed straps for the processor:

1. While PWROK is active, the ICH2 drives A20M#, IGNNE#, NMI, and INTR high.

2. As soon as PWROK goes active, the ICH2 reads the FREQ_STRAP field contents.

3. The next step depends on the power state being exited as described in Table 5-34.

Table 5-34. Frequency Strap Behavior Based on Exit State

State

Exiting

ICH2

There is no processor reset, so no frequency strap logic is used.

Based on PWROK going active, the ICH2 deasserts PCIRST#, and based on the value of the

FREQ_STRAP field (D31:F0,Offset D4), the ICH2 drives the intended core frequency values on

A20M#, IGNNE#, NMI, and INTR. The ICH2 holds these signals for 120 ns after CPURST# is

deasserted by the Host controller.

S3, S4, S5,

or G3

Table 5-35. Frequency Strap Bit Mapping

FREQ_STRAP bits [3:0]

Sets High/Low Level for the Corresponding Signal

NMI

INTR

IGNNE#

A20M#

NOTE: The FREQ_STRAP register is in the RTC well. The value in the register can be forced to 1111 via a

pinstrap (AC_SDOUT signal), or the ICH2 can automatically force the speed strapping to 1111 if the

processor fails to boot.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-69

Functional Description

Figure 5-13. Signal Strapping

CPURST#

Host Controller

Processor

CPU

INIT#

A20M#, IGNE#, INTR, NMI

ICH2

ICH

PCIRST#

Freq.

strap reg

4x 2 to 1

MUX

PWROK

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.12

Power Management (D31:F0)

Features

• ACPI Power and Thermal Management Support

— ACPI 24-Bit Timer

— Software initiated throttling of processor performance for Thermal and Power Reduction

— Hardware Override to throttle processor performance if system too hot

— SCI and SMI# Generation

• PCI PME# Signal for Wake Up from Low-Power states

• System Clock Control

— ACPI C2 state: Stop-Grant (or Quickstart for the 82801BAM ICH2-M) state (using

STPCLK# signal) halts processor’s instruction stream

— ACPI C3 State (82801BAM ICH2-M): Ability to halt processor clock (but not hub

interface or memory clock)

— 82801BAM ICH2-M: CLKRUN# protocol for PCI clock starting/stopping

• System Sleeping State Control

— ACPI S1 state (82801BA ICH2): Like C2 state (only STPCLK# active, and SLP#

optional)

— ACPI S1 state (82801BAM ICH2-M): Powered On Suspend (POS)

— ACPI S1 state: Like C2 state (only STPCLK# active, and SLP# optional)

— ACPI S3 state - Suspend to RAM (STR)

— ACPI S4 state - Suspend-to-Disk (STD)

— ACPI G2/S5 state - Soft Off (SOFF)

— Power Failure Detection and Recovery

• Streamlined Legacy Power Management Support for APM-Based Systems

• 82801BAM ICH2-M: Intel^®SpeedStep^TMtransition logic

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-71

Functional Description

5.12.1

ICH2 and System Power States

Table 5-36 shows the power states defined for ICH2-based platforms. The state names generally

match the corresponding ACPI states.

Table 5-36. General Power States for Systems using ICH2

State/

Substates

Legacy Name / Description

Full On: Processor operating. Individual devices may be shut down to save power. The

different processor operating levels are defined by Cx states, as shown in Table 5-37. Within

the C0 state, the ICH2 can throttle the STPCLK# signal to reduce power consumption. The

throttling can be initiated by software or by the THRM# input signal.

G0/S0/C0

Auto-Halt: The processor has executed an AutoHalt instruction and is not executing code.

The processor snoops the bus and maintains cache coherency.

G0/S0/C1

G0/S0/C2

Stop-Grant (ICH2) / Quickstart (ICH2-M): The STPCLK# signal goes active to the

processor. The processor performs a Stop-Grant cycle, halts its instruction stream, and

remains in that state until the STPCLK# signal goes inactive. In the Stop-Grant (ICH2) /

Quickstart (ICH2-M) state, the processor snoops the bus and maintains cache coherency.

Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a

Stop-Grant cycle, halts its instruction stream. ICH2-M then asserts STP_CPU#, which forces

G0/S0/C3

(ICH2-M only)

the clock generator to stop the processor clock. This is also used for Intel SpeedStep

technology support. Accesses to memory (by AGP, PCI, or internal units) is not permitted

while in a C3 state. It is assumed that the ARB_DIS bit is set prior to entering C3 state.

Stop-Grant: Similar to G0/S0/C2 state. The ICH2 also has the option to assert the CPUSLP#

signal to further reduce processor power consumption.

G1/S1

(ICH2 only)

Note: The behavior for this state is slightly different when supporting iA64 processors.

Powered-On-Suspend (POS): In this state, all clocks (except the 32.768 kHz clock) are

G1/S1

stopped. The system context is maintained in system DRAM. Power is maintained to PCI, the

(ICH2-M only) processor, memory controller, memory, and all other criticial subsystems. Note that this state

does not preclude power being removed from non-essential devices (e.g., disk drives).

Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is

G1/S3

shut off to non-critical circuits. Memory is retained and refreshes continue. All clocks stop

except RTC clock.

Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is

then shut off to the system except for the logic required to resume. Externally appears same

as S5, but may have different wake events.

G1/S4

G2/S5

Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic

required to restart. A full boot is required when waking.

Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the

RTC. No “Wake” events are possible, because the system does not have any power. This

state occurs if the user removes the batteries, turns off a mechanical switch, or if the system

power supply is at a level that is insufficient to power the “waking” logic. When system power

returns, transition depends on the state just prior to the entry to G3 and the AFTERG3 bit in

the GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-45 for more details.

Table 5-37 shows the transitions rules among the various states. Note that transitions among the

various states may appear to temporarily transition through intermediate states. For example, in

going from S0 to S1, it may appear to pass through the G0/S0/C2 states. These intermediate

transitions and states are not listed in the table.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-37. State Transition Rules for ICH2

Present State

Transition Trigger

Next State

•

Processor halt instruction

Level 2 Read

•

G0/S0/C1

G0/S0/C2

G0/S0/C3

Level 3 Read

G0/S0/C0

SLP_EN bit set

G1/Sx or G2/S5state

Power Button Override

Mechanical Off/Power Failure

G2/S5

•

Any Enabled Break Event

STPCLK# goes active

Power Button Override

Power Failure

•

G0/S0/C0

G0/S0/C2

G2/S5

G0/S0/C1

G0/S0/C2

•

Any Enabled Break Event

•

G0/S0/C0

G0/S0/C1

STPCLK# goes inactive and previously

in C1

•

Power Button Override

Power Failure

•

G2/S5

•

Any Enabled Break Event

•

G0/S0/C0

G0/S0/C1

STPCLK# goes inactive and previously

in C1

G0/S0/C3

(ICH2-M only)

•

Power Button Override

Power Failure

•

G2/S5

•

Any Enabled Wake Event

Power Button Override

Power Failure

•

G0/S0/C0 (For ICH2-M, see note 2)

G1/S1,

G1/S3, or

G1/S4

G2/S5

•

Any Enabled Wake Event

Power Failure

•

G0/S0/C0 (For ICH2-M, see note 2)

G2/S5

•

Optional to go to S0/C0 (reboot) or G2/

S5 (stay off until power button pressed or

other wake event). (For ICH2 and

ICH2-M, see Note 1) (For ICH2-M, see

note 2)

•

Power Returns

NOTES:

1. Some wake events can be preserved through power failure.

2. 82801BAM ICH2-M, transitions from the S1-S5 or G3 states to the S0 state are deferred until BATLOW# is

inactive.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-73

Functional Description

5.12.2

System Power Planes

The system has several independent power planes, as described in Table 5-38. Note that when a

particular power plane is shut off, it should go to a 0V level.

Table 5-38. System Power Plane

Controlled

Plane

Description

SLP_S1# puts the clock generator into a low-power state, but does not cut

the power to the processor. The SLP_S3# signal can be used to cut the

processor’s power completely.

CPU

(ICH2-M only)

SLP_S3#

signal

When SLP_S3# goes active, power can be shut off to any circuit not

required to wake the system from the S3 state. Since the S3 state

requires that the memory context be preserved, power must be retained

to the main memory.

SLP_S3#

signal

MAIN

The processor, devices on the PCI bus, LPC interface, downstream hub

interface and AGP will typically be shut off when the Main power plane is

shut, although there may be small subsections powered.

When the SLP_S5# goes active, power can be shut off to any circuit not

required to wake the system from the S4 or S5 state. Since the memory

context does not need to be preserved in the S5 state, the power to the

memory can also be shut down.

SLP_S5#

signal

MEMORY

DEVICE[n]

Individual subsystems may have their own power plane. For example,

GPIO signals may be used to control the power to disk drives, audio

amplifiers, or the display screen.

GPIO

5.12.3

ICH2 Power Planes

The ICH2 power planes were previously defined in Section 3.1.

Although not specific power planes within the ICH2, there are many interface signals that go to

devices that may be powered down. These include:

• IDE: ICH2 can tri-state or drive low all IDE output signals and shut off input buffers.

• USB: ICH2 can tri-state USB output signals and shut off input buffers if USB wakeup is not

desired

• AC’97: ICH2 can drive low the outputs and shut off inputs

5.12.4

SMI#/SCI Generation

Upon any SMI# event taking place, ICH2 asserts SMI# to the processor which causes it to enter

SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes

inactive for a minimum of 4 PCICLKs. If another SMI event occurs, SMI# is driven active again.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In

non-APIC systems (the default), the SCI IRQ is routed to one of the 8259 interrupts

(IRQ[9,10, or 11]). The 8259 interrupt controller must be programmed to level mode for that

interrupt.

In systems using the APIC, the SCI can still be routed to IRQ[9, 10, or 11] or it can be instead

routed to one of the APIC interrupts 20:23. In the case where the SCI is routed to

IRQ[20, 21, 22, or 23], the interrupt generated internally is an active low level. The interrupt

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

remains low until all SCI sources are removed. In the case where the SCI is routed to

IRQ[9, 10, or 11], the interrupt generated internally is active high. The interrupt remains high until

all SCI sources are removed.

Table 5-39 shows which events can cause an SMI# and SCI. Note that some events can be

programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is

typically associated with an ACPI-based system. Each SMI# or SCI source has a corresponding

enable and status bits.

Table 5-39. Causes of SMI# and SCI

Cause

SCI

SMI

Additional Enables

Where Reported

Comment

PME#

Yes

PME_EN=1

PWRBTN_EN=1

RTC_EN=1

PME_STS

PWRBTN_STS

RTC_STS

Can also cause Wake Event

Power Button Press

RTC Alarm

Ring Indicate

AC’97 wakes

USB#1 wakes

USB#2 wakes

RI_EN=1

RI_STS

AC97_EN=1

USB1_EN=1

USB2_EN=1

AC97_STS

USB1_STS

USB2_STS

The THRM# can cause an

SMI# or SCI on either the

rising or falling edge. Causes

SCI if SCI_EN is set, causes

SMI# if SCI_EN not set.

THRM# pin active

Yes

THRM_EN=1

THRM_STS

ACPI Timer overflow

(2.34 sec.)

Yes

TMROF_EN=1

TMROF_STS

GPI[x]_Route=10 (SCI)

GPI[x]_Route=01 (SMI)

GPE1[x]_EN=1

GPI[x]_STS

GPE1_STS

Any GPI

Can also cause IRQ (other

than SCI).

TCO SCI Logic

Yes

TCOSCI_EN=1

none

TCOSCI_STS

MCHSCI_STS

TCO_STS

TCO SCI message

from MCH

Can also cause IRQ (other

than SCI).

TCO SMI Logic

Yes

TCO_EN=1

none

TCO SMI: Year 2000

Rollover

NEWCENTURY_STS

TIMEOUT

TCO SMI: TCO

TIMEROUT

none

TCO SMI: OS writes

to TCO_DAT_IN

Yes

none

OS_TCO_SMI

MCHSMI_STS

NMI2SMI_STS

TCO SMI: Message

from MCH

TCO SMI: NMI

occurred (and NMI’s

mapped to SMI)

NMI2SMI_EN=1

TCO SMI:

INTRUDER# signal

goes active

Yes

INTRD_SEL=10

INTRD_DET

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-75

Functional Description

Table 5-39. Causes of SMI# and SCI (Continued)

Cause

SCI

SMI

Additional Enables

Where Reported

Comment

TCO SMI: Change of

the BIOSWP bit from

0 to 1

Yes

BLD=1

BIOSWR_STS

TCO SMI: Write

attempted to BIOS

Yes

BIOSWP=1

GBL_EN=1

BIOSWR_STS

GBL_STS

ACPI code in OS sets

GBL_RLS bit to cause

BIOS_STS bit active, which

causes SMI#.

BIOS_RLS writen to

GBL_RLS written to

Yes

This bit is set when the BIOS

sets the BIOS_RLS bit. The

ACPI handler will clear the

bit.

Yes

BIOS_EN=1

BIOS_STS

OS or BIOS writes to the

APMC register. SMM handler

clears.

Write to B2h register

Periodic timer expires

64 ms timer expires

Yes

none

APM_STS

PERIODIC_EN=1

SWSMI_TMR_EN=1

PERIODIC_STS

SWSMI_TMR_STS

Allows SMM handler to exit

temporarily. Another SMI#

occurs about 64 ms later.

Bit set based on address

decode or incoming USB

IRQ.

Legacy USB logic

Yes

LEGACY_USB_EN=1

none

LEGACY_USB_STS

SERIRQ_SMI_STS

Serial IRQ SMI reported

Device Trap: Device

monitors match address

in its range

Indicates that subsystems

may need to be powered

back on.

DEVMON_STS,

DEV[n]_TRAP_EN=1

DEV[n]_TRAP_STS

SMBus Host Controller

SMBus Slave SMI

Yes

SMB_SMI_EN

none

SMBus host status reg.

SMBUS_SMI_STS

BATLOW# assertion

(ICH2-M)

Yes

BATLOW_EN=1.

BATLOW_STS

Global Standby Timer

expires in S1 state

(ICH2-M)

When activated, only counts

when in the S1 state.

Access to Microcontroller

range (62h/66h) with

MCSMI_EN set.

Access microcontroller

62h/66h

Yes

MCSMI_EN

MCSMI_STS

SLP_EN bit written to 1

SMI_ON_SLP_EN=1

SMI_ON_SLP_EN_STS

NOTES:

1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.

2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).

3. GBL_SMI_EN must be 1 to enable SMI.

4. EOS must be written to 1 to re-enable SMI for the next one.

5. The GPI[x]_ Route bits can enable GPIs to generate SMIs regardless of the state of SMI_EN.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.12.5

Dynamic Processor Clock Control

ICH2 has extensive control for dynamically starting and stopping system clocks. The clock control

is used for transitions among the various S0/Cx states and processor throttling. Each dynamic clock

control method is described in this section. The various Sleep states may also perform types of non-

dynamic clock control.

The ICH2 supports the ACPI C0, C1 and C2 states.

In addition to C0, C1, and C2 states, the 82801BAM ICH2-M supports the ACPI C3 states.

The dynamic processor clock control is handled using the following signals:

• STPCLK#: Used to halt processor instruction stream.

• C3_STAT# (ICH2-M only): Used to signal an AGP device that the system is about to enter, or

has just exited a C3 state.

• STP_CPU# (ICH2-M only): Used to stop CPU’s clock

• CPUSLP#: Must be asserted prior to STP_CPU# (in Stop Grant mode)

The C1 state is entered based on the processor performing an autohalt instruction. The C2 state is

entered based on the processor reading the Level 2 register in the ICH2.

For the ICH2-M, the C3 state is entered based on the processor reading the Level 3 register in the

ICH2-M. Note that a Intel^®SpeedStep^TMtransition may appear to temporarily pass through a C3

state; however, it is a separate transition and documented separately in ??.

A C1 or C2 state (C1, C2, or C3 state for the 82801BAM ICH2-M) ends due to a break event.

Based on the break event, the ICH2-M returns the system to C0 state. Table 5-40 lists the possible

break events from C2 (C2 or C3 for the ICH2-M). The break events from C1 are indicated in the

processor’s datasheet.

Table 5-40. Break Events

Event

Breaks from

Comment

IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC.

Since SCI is an interrupt, any SCI will also be a break

event.

C2 (ICH2)

Any unmasked interrupt goes

active

C2, C2 (ICH2-M)

C2 (ICH2)

Any internal event that will

cause an NMI or SMI#

Many possible sources

C2, C3 (ICH2-M)

C2 (ICH2)

Any internal event that will

cause INIT# to go active

Could be indicated by the keyboard controller via the

RCIN input signal.

C2, C3 (ICH2-M)

Any bus master request

(internal, external or DMA)

goes active

C3 only

Need to wake up processor so it can do snoops

(ICH2-M only)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-77

Functional Description

5.12.5.1

Throttling Using STPCLK#

Throttling is used to lower power consumption or reduce heat. The ICH2 asserts STPCLK# to

throttle the processor clock and the processor appears to temporarily enter a C2 state. After a

programmable time, the ICH2 deasserts STPCLK# and the processor appears to return to the C0

state. This allows the processor to operate at reduced average power, with a corresponding decrease

in performance. Two methods are included to start throttling:

• Software enables a timer with a programmable duty cycle. The duty cycle is set by the

THTL_DTY field and the throttling is enabled using the THTL_EN field. This is known as

Manual Throttling. The period is fixed to be in the non-audible range, due to the nature of

switching power supplies.

• A Thermal Override condition (THRM# signal active for >2 seconds) occurs that

unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to

Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and

system. The Thermal Override condition will end when THRM# goes inactive.

Throttling due to the THRM# signal has higher priority than the software-initiated throttling.

Throttling does not occur when the system is in a C2 state (C2 or C3 for the ICH2-M), even if

Thermal override occurs.

5.12.5.2

Transition Rules Among S0/Cx and Throttling States

The following priority rules and assumptions apply among the various S0/Cx and throttling states:

• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because

the processor can only perform one register access at a time and Sleep states have higher

priority than thermal throttling.

• When the SLP_EN bit is set (system going to a sleep state (S1–S5), the THTL_EN bit can be

internally treated as being disabled (no throttling while going to sleep state). Note that thermal

throttling (based on THRM# signal) cannot be disabled in an S0 state. However, once the

SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# will be active in S1–S5

states).

• If the THTL_EN bit is set, and a Level 2 (Level 2 or Level 3 for the ICH2-M) read then occurs,

the system should immediately go and stay in a C2 (C2 or C3 for the ICH2-M) state until a

break event occurs. A Level 2 (Level 2 or Level 3 for the ICH2-M) read has higher priority

than the software-initiated throttling or thermal throttling.

• If Thermal Override is causing throttling and a Level 2 (Level 2 or Level 3 for the ICH2-M)

read then occurs, the system will stay in a C2 (C2 or C3 for the ICH2-M) state until a break

event occurs. A Level 2 (Level 2 or Level 3 for the ICH2-M) read has higher priority than the

Thermal Override.

• After an exit from a C2 (C2 or C3 for the ICH2-M) state (due to a Break event), and if the

THTL_EN bit is still set, or if a Thermal Override is still occurring, the system will continue to

throttle STPCLK#. Depending on the time of the break event, the first transition on STPCLK#

active can be delayed by up to one period.

• The Host controller must post Stop-Grant cycles in such a way that the processor gets an

indication of the end of the special cycle prior to the ICH2 observing the Stop-Grant cycle.

This ensures that the STPCLK# signals stays active for a sufficient period after the processor

observes the response phase.

• If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-

Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should

return to the C1 state.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.12.6

Dynamic PCI Clock Control (82801BAM ICH2-M)

For the ICH2-M, the PCI clock can be dynamically controlled independent of any other low-

power state. This control is accomplished using the CLKRUN# protocol as described in the PCI

Mobile Design Guide, and is transparent to software.

The Dynamic PCI Clock control is handled using the following signals:

• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run

• STP_PCI#: Used to stop the system PCI clock

Note: The 33 MHz clock to the ICH2-M is “free-running” and is not affected by the STP_PCI#

signal.

5.12.6.1

Conditions for Stopping the PCI Clock (82801BAM ICH2-M)

When there is a lack of PCI activity, the ICH2-M has the capability to stop the PCI clocks to

conserve power. “PCI activity” is defined as any activity that requires the PCI clock to be running.

Any of the following conditions indicates that it is NOT OK to stop the PCI clock:

• Cycles on PCI or LPC

• Cycles of any internal device that would need to go on the PCI bus

• Cycles using PC/PCI DMA

• SERIRQ activity

Behavioral Descripion

• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH2-M deassert

(drive high) CLKRUN# for 1 clock and then tri-state the signal.

5.12.6.2

Conditions for Maintaining the PCI Clock (82801BAM ICH2-M)

PCI master that wish to maintain the PCI clock running will observe the CLKRUN# signal

deasserted, and then must re-assert if (drive it low) within 3 clocks.

Behavioral Description

• When the ICH2-M has tri-stated the CLKRUN# signal after deasserting it, the ICH2-M then

checks to see if the signal has been re-asserted (externally).

• After observing the CLKRUN# signal asserted for 1 clock, the ICH2-M again starts asserting

the signal.

• If an internal device needs the PCI bus, the ICH2-M asserts the CLKRUN# signal.

5.12.6.3

Conditions for Stopping the PCI Clock (82801BAM ICH2-M)

Behavioral Description

• If no device re-asserts CLKRUN# once it has been deasserted for 3 clocks, the ICH2-M stops

the PCI clock by asserting the STP_PCI# signal to the clock synthesizer.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-79

Functional Description

5.12.6.4

Conditions for Re-Starting the PCI Clock (82801BAM ICH2-M)

Behavioral Description

• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.

• When the ICH2-M observes the CLKRUN# signal asserted for 1 (free running) clock, the

ICH2-M deasserts the STP_PCI# signal to the clock synthesizer within 4 (free running)

clocks.

• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the ICH2-M

again starts driving CLKRUN# asserted.

If an internal source requests the clock to be re-started, the ICH2-M re-asserts CLKRUN#, and

simultaneously deasserts the STP_PCI# signal.

5.12.6.5

Other Causes of CLKRUN# Going Active (82801BAM ICH2-M)

The following causes the ICH2-M to assert and/or maintain the CLKRUN# signal active (low):

• PC/PCI activity, which is started by one of the REQx# signals going active. It is expected that

a PC/PCI device asserts CLKRUN# prior to starting the start bit on the REQ# signal. Once the

start bit is recognized, the ICH2-M makes sure CLKRUN# goes active if it should go inactive

during the sequence.

• SERIRQ activity, which is started by the SERIRQ signal going low (in Quiet mode), or the

SERIRQ logic being in the Continuous Mode. It is expected that a SERIRQ device asserts

CLKRUN# prior to starting the start bit on the SEIRQ signal. Once the start bit is recognized,

the ICH2-M makes sure CLKRUN# goes active if it should go inactive during the sequence.

• Any internal or external bus master request, including LPC masters. Once the master request

is detected (via PCI REQ or LPC LDRQ[1:0]#), the ICH2-M maintains CLKRUN# active

until the end of the sequence. This includes:

— Any PCI REQ# low

— Bus Master or DMA request pending (having come in via LDRQ[1:0]#)

— Any cycle coming down from hub interface1 to PCI

— Any PCI cycle currently in progress. For example, cycle forward by the ICH2-M from

the hub interface to PCI, and then claimed by ICH2-M's PCI-to-LPC logic. That cycle

runs as a Delayed Transaction on PCI. CLKRUN# should stay low until the cycle

completes (without Delayed Transaction).

• Any bus master below PCI that needs to run a cycle. This could include the Front-Side-Bus

interrupt logic for the I/O APIC (if it is downstream of PCI).

5.12.6.6

LPC Devices and CLKRUN# (82801BAM ICH2-M)

If an LPC device (of any type) needs the 33 MHz PCI clock (e.g., for LPC DMA or LPC serial

interrupt), it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles do

not need to assert CLKRUN#, since the ICH2-M asserts it on their behalf.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.12.7

Sleep States

The ICH2 directly supports different sleep states (S1–S5), which are entered by setting the

SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several

assumptions:

• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the

processor can only perform one register access at a time. A request to Sleep always has higher

priority than throttling.

• Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note

that thermal throttling cannot be disabled, but setting the SLP_EN bit will disable thermal

throttling (since S1–S5 sleep state has higher priority).

• The G3 state cannot be entered via any software mechanism. The G3 state indicates a

complete loss of power.

5.12.7.1

Initiating Sleep State

Sleep states (S1–S5) are initiated by:

• Masking interrupts, turning off all bus master enable bits, setting the desired type in the

SLP_TYP field, and then setting the SLP_EN bit. The hardware will then attempt to gracefully

put the system into the corresponding Sleep state by first going to a C2 (C2 or C3 for the

ICH2-M) state. See Section 5.12.5 for details on going to the C2 (C2 or C3 for the ICH2-M)

state.

• Pressing the PWRBTN# signal for more than 4 seconds to cause a Power Button Override

event. In this case the transition to the S5 state will be less graceful, since there will be no

dependencies on observing Stop-Grant cycles from the processor or on clocks other than the

RTC clock.

Table 5-41. Sleep Types

Sleep Type

Comment

ICH2 asserts the CPUSLP# signal. This lowers the processor’s power consumption. No

snooping is possible in this state.

(ICH2 only)

ICH2-M asserts the SLP_S1# signal. This can be connected to the system clock generator

to either put it into a low-power mode or to remove its power altogether. No snooping is

possible in this state.

(ICH2-M only)

ICH2 asserts SLP_S3# (ICH2-M asserts SLP_S1# and SLP_S3#). The SLP_S3# signal

controls the power to non-critical circuits. Power is only be retained to devices needed to

wake from this sleeping state, as well as to the memory.

ICH2 asserts SLP_S3# and SLP_S5# (ICH2-M asserts SLP_S1#, SLP_S3# and

SLP_S5#). The SLP_S5# signal shuts off the power to the memory subsystem. Only

devices needed to wake from this state should be powered.

Same as S4. ICH2 asserts SLP_S3# and SLP_S5# (ICH2-M asserts SLP_S1#, SLP_S3#

and SLP_S5#). The SLP_S5# signal shuts off the power to the memory subsystem. Only

devices needed to wake from this state should be powered.

5.12.7.2

Exiting Sleep States

Sleep states (S10–S5) are exited based on Wake events. The Wake events will force the system to a

full on state (S0), although some non-critical subsystems might still be shut off and have to be

brought back manually. For example, the hard disk may be shut off during a sleep state, and have to

be enabled via a GPIO pin before it can be used.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-81

Functional Description

Upon exit from the ICH2-controlled Sleep states, the WAK_STS bit will be set. The possible

causes of Wake Events (and their restrictions) are shown in Table 5-42.

Notes:

• If in the S5 state due to a powerbutton override, the only wake event is power button.

• For the ICH2-M, if the BATLOW# signal is asserted, the ICH2-M will not attempt to wake

from an S1 (Mobile) – S5 state, even if the power button is pressed. This prevents the system

from waking when the battery power is insufficient to wake the system. Wake events that

occur while BATLOW# is asserted are latched by the ICH2-M, and the system wakes after

BATLOW# is deasserted.

Table 5-42. Causes of Wake Events

States Can

Wake From

Cause

How Enabled

S1–S5

(Note 1)

RTC Alarm

Power Button

GPI[0:n]

Set RTC_EN bit in PM1_EN Register

Always enabled as Wake event

GPE1_EN register

S1–S5

(Note 1)

USB

LAN

S1–S4

S1–S5

Set USB1_EN and USB2_EN bits in GPE0_EN Register

Will use PME#. Wake enable set with LAN logic.

S1–S5

(Note 1)

RI#

Set RI_EN bit in GPE0_EN Register

AC97

PME#

S1–S5

Set AC97_EN bit in GPE0_EN Register

Set PME_EN bit in GPE0_EN Register.

S1–S5

(Note 1)

GST Timeout

SMBALERT#

S1M

Setting the GST Timeout range to a value other than 00h.

SMB_WAK_EN in the GPE0 Register

S1–S4

S1–S5

SMBus Slave Message

Always enabled as a Wake Event

NOTES:

1. This will be a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP

bits via software.

It is important to understand that the various GPIs have different levels of functionality when used

as wake events. The GPIs that reside in the core power well can only generate wake events from an

S1 state. Also, only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits

reside in ACPI I/O space. Table 5-43 summarizes the use of GPIs as wake events.

Table 5-43. GPI Wake Events

GPI

Power Well

Wake From

Notes

GPI[7:0], GPI[23:16]

GPI[15:8]

Core

Resume

S1–S5

ACPI Compliant

The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply

design. Approximations are shown in Table 5-44. The time indicates from when the Wake event

occurs (signal transition) to when the processor is allowed to start its first cycle (CPURST# goes

inactive). There will be very large additional delays for the processor to execute sufficient amounts

of BIOS to invoke the OS (such as coming out of S1–S3) or spinning up the hard drive

(e.g., coming out of S4 or S5).

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-44. Sleep State Exit Latencies

State

Latency

<1 ms. Based on wake event to STPCLK# high + re-enumeration of PCI bus, USB, CardBus,

etc. Must also add PLL spin-up times.

Power Supply ramp + 20 ms

5.12.7.3

Sx–G3–Sx, Handling Power Failures

82801BAM ICH2-M: A power failure in a mobile system is a rare event, since the power

subsystem should provide sufficient warning when the batteries are low. However, if the user

removes the battery or leaves the system in an STR state for too long, a power failure could occur.

82801BA ICH2: In desktop systems, power failures can occur if the AC power is cut (a real power

failure) or if the system is unplugged. In either case, PWROK and RSMRST# are assumed to go

low.

Depending on when the power failure occurs and how the system is designed, different transitions

can occur due to a power failure.

The AFTER_G3 bit provides the ability to program whether or not the system should boot once

power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state

(unless previously in S4). There are only three possible events that will wake the system after a

power failure.

• PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3

state), the PWRBTN_STS bit is reset. When the ICH2 exits G3 after power returns

(RSMRST# goes high), the PWRBTN# signal is already high (because Vcc-standby goes high

before RSMRST# goes high) and the PWRBTN_STS bit is 0.

• RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event,

it is important to keep this signal powered during the power loss event. If this signal goes low

(active), when power returns, the RI_STS bit is set and the system interprets this as a wake

event.

• RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like

PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.

The ICH2 monitors both PWROK and RSMRST# to detect power failures. If PWROK goes low,

the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.

Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss.

PME_EN and PME_STS bits are cleared by RSMRST#

Table 5-45. Transitions Due To Power Failure

State at Power Failure

AFTERG3_EN bit

Transition When Power Returns

S0, S1, S3

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Functional Description

5.12.8

Thermal Management

The ICH2 has mechanisms to assist with managing thermal problems in the system.

5.12.8.1

THRM# Signal

The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal

going active, the ICH2 generates an SMI# or SCI (depending on SCI_EN).

If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit will be

set. This is an indicator that the thermal threshold has been exceeded. If the THRM_EN bit is set,

then when THRM_STS goes active, either an SMI# or SCI is generated (depending on the SCI_EN

bit being set).

The power management software (BIOS or ACPI) can then take measures to start reducing the

temperature. Examples include shutting off unwanted subsystems, or halting the processor.

By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated when the

THRM# signal goes back high. This allows the software (BIOS or ACPI) to turn off the cooling

methods.

5.12.8.2

THRM# Initiated Passive Cooling

If the THRM# signal remains active for some time greater than 2 seconds and the ICH2 is in the

S0/G0/C0 state, then the ICH2 enters an auto-throttling mode, in which it provides a duty cycle on

the STPCLK# signal. This will reduce the overall power consumption by the system, and should

cool the system. The intended result of the cooling is that the THRM# signal should go back

inactive.

For all programmed values (001–111), THRM# going active will result in STPCLK# active for a

minimum time of 12.5% and a maximum of 87.5%. The period is 1024 PCI clocks. Thus, the

STPCLK# signal can be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The

actual slowdown (and cooling) of the processor will depend on the instruction stream, because the

processor is allowed to finish the current instruction. Furthermore, the ICH2 waits for the STOP-

GRANT cycle before starting the count of the time the STPCLK# signal is active.

When THRM# goes inactive, throttling stops. In case that the ICH2 is already attempting throttling

because the THTL_EN bit is set, the duty cycle associated with the THRM# signal will have higher

priority. If the ICH2 is in the C2 (C2 and C3 for the ICH2-M) or S1–S5 states, then no throttling

will be caused by the THRM# signal being active.

5.12.8.3

THRM# Override Software Bit

The FORCE_THTL bit allows BIOS to force passive cooling, just as if the THRM# signal had

been active for 2 seconds. If this bit is set, the ICH2 starts throttling using the ratio in the

THRM_DTY field.

When this bit is cleared, the ICH2 stops throttling, unless the THRM# signal has been active for

2 seconds or if the THTL_EN bit is set (indicating that ACPI software is attempting throttling).

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Functional Description

5.12.8.4

Processor-Initiated Passive Cooling (Via Programmed Duty Cycle on

STPCLK#)

Using the THTL_EN and THTL_DTY bits, the ICH2 can force a programmed duty cycle on the

STPCLK# signal. This reduces the effective instruction rate of the processor and cut its power

consumption and heat generation.

5.12.8.5

Active Cooling

Active cooling involves fans. The GPIO signals from the ICH2 can be used to turn on/off a fan.

™

5.12.9

Intel SpeedStep Technology Protocol

(82801BAM ICH2-M only)

The Intel^®SpeedStep^™technology feature enables a mobile system to operate in multiple

processor performance/thermal states and to transition smoothly between them. The internal

processor clock setting and processor supply voltage setting determines these states. The ICH2-M

supports one Low Power mode and one High Performance mode.

Figure 5-14. Intel^®SpeedStep^™Block Diagram (82801BAM ICH2-M only)

CPUPERF#

SpeedStep™

CPUPW RGD

Enabled Mobile

Intel^®Processors

STPCLK#

VddCore

ICH2-M

VGATE

PW ROK

Processor's

Voltage Regulator

Module (VRM)

GMUXSEL

From Main

Power Supply

High Voltage

Low Voltage

VRCODE[4:0]

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Functional Description

5.12.9.1

Intel SpeedStep™ Technology Processor Requirements

(82801BAM ICH2-M)

Non-Intel^®SpeedStep^™technology processors use the A20M#, IGNNE#, NMI, and INTR input

signals to determine the multiplier used by the processor’s PLL for the internal clock. In first-

generation Intel^®SpeedStep^™technology processors, two multiplier values (one for the high

performance state, a second for the low power state) are hard-wired within the processor. The

ICH2-M CPUPERF signal is used to select the processor state, based on ICH2-M control logic.

The operating bus ratio must be available to the programmer and is, therefore, suggested that it be

read in a processor MSR. Also, the processor must return an indication that it is Intel^®

SpeedStep^™technology enabled, which should be in the form of a status bit in a processor MSR

or in the CPUID register.

The ICH2-M is not capable of determining whether it is attached to a Intel^®SpeedStep^™or non-

Intel^®SpeedStep^™processor. When used with a non-Intel^®SpeedStep^™processor, software

should not write or read the ICH2-M Intel^®SpeedStep^™registers.

5.12.9.2

Intel SpeedStep™ Technology States (82801BAM ICH2-M)

The ICH2-M supports two system-level performance states: Low Power mode and High

Performance mode. Processor states are defined by valid combinations of core voltage levels and

core clock speeds. These processor states can be used to alter the processor and system

performance to conform to conditions of power and environment.

The Low Power mode is used primarily when the system is powered from the battery, with the

purpose being to maximize battery life. Mobile system performance is limited by thermal design

and battery capacity. To improve thermal capacity, active cooling solutions (e.g., a fan can be

used) in addition to a passive cooling solution.

The High Performance mode assume that the mobile system is powered from an external AC/DC

source. The purpose of this state is to maximize performance subject to thermal constraints. The

ICH2-M does not implement any restrictions on entry into High Performance mode. It will

unconditionally transition into High Performance mode upon software command.

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Functional Description

5.12.9.3

Voltage Regulator Interface (82801BAM ICH2-M)

The voltage regulator interface is critical to the Intel^®SpeedStep^™technology concept. The

power dissipation of the processor is proportional to the internal clock speed and to the square of

the core supply voltage. As the internal clock speed of the processor changes, the minimum

required core voltage supply level also changes. The interface signals are designed to allow the

voltage regulator to change settings without causing a power-on reset.

• VRCODE[4:0] is a 5-bit input to the Voltage Regulator. These signals are not outputs from

the ICH2-M; instead, they are outputs from an external muliplexer. Future voltage regulators

may integrate this multiplexer.

• The SSMUXSEL# signal is an ICH2-M output. It can be used directly to control the external

muliplexer that selects the high or low values for VRCODE[4:0].

• VRON (aka PWROK from main power supply) is an input to the regulator. When VRON is

asserted, the regulator turns on and settles to the output defined by VRCODE[4:0].

VGATE is an input from the regulator indicating that all of the outputs from the regulator are on

and within specification. When the system is transitioning between performance states, the voltage

regulator output may be required to change. It is not desirable, however, that CPUPWRGOOD

becomes deasserted during these transitions. Normally, this would indicate to the system that a

power-on reset be performed, which would invalidate the system context. The ICH2-M prevents

this from occurring by maintaining CPUPWRGOOD during the transition. CPUPWRGOOD must

also be maintained during an S1 state.

5.12.10 Event Input Signals and Their Usage

The ICH2 has various input signals that trigger specific events. This section describes those signals

and how they should be used.

5.12.10.1 PWRBTN# — Power Button

The ICH2 PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI

specification. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition

descriptions are included in the following table. Note that the transitions start as soon as the

PWRBTN# is pressed (but after the debounce logic), and does not depend on when the Power

Button is released.

Table 5-46. Transitions Due to Power Button

Present

State

Event

Transition/Action

Comment

SMI# or SCI generated

(depending on SCI_EN)

Software will typically initiate a

Sleep state.

S0/Cx

PWRBTN# goes low

Wake Event. Transitions to S0

state.

S1–S5

Standard wakeup

No effect since no power.

Not latched nor detected.

PWRBTN# pressed

None

PWRBTN# held low for

at least 4 consecutive

seconds

No dependence on processor

(such as Stop-Grant cycles) or

any other subsystem.

Unconditional transition to S5

state.

S0–S4

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Functional Description

Power Button Override Function

If PWRBTN# is observed active for at least 4 consecutive seconds, the state machine should

unconditionally transition to the G2/S5 state, regardless of present state (S0–S4). In this case, the

transition to the G2/S5 state should not depend on any particular response from the processor

(e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem.

The PWRBTN# status is readable to check if the button is currently being pressed or has been

released. The status is taken after the de-bounce, and is readable via the PWRBTN_LVL bit.

Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The

4-second timer starts counting when the ICH2 is in a S0 state. If the PWRBTN# signal is asserted

and held active when the system is in a suspend state (S1–S5), the assertion causes a wake event.

Once the system has resumed to the S0 state, the 4-second timer starts.

Sleep Button

The ACPI specification defines an optional Sleep button. It differs from the power button in that it

only is a request to go from S0 to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake

the system, but the Sleep Button cannot.

Although the ICH2 does not include a specific signal designated as a Sleep Button, one of the

GPIO signals can be used to create a “Control Method” Sleep Button. See the ACPI specification

for implementation details.

5.12.10.2 RI# — Ring Indicate

The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-47 shows

when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH2

generates an interrupt based on RI# active and the interrupt is set up as a break event.

Table 5-47. Transitions Due to RI# signal

Present State

Event

RI_EN

Event

RI# Active

Ignored

S1–S5

RI# Active

Wake Event

Note: Filtering/Debounce on RI# will not be done in ICH2. Can be in modem or external.

5.12.10.3 PME# — PCI Power Management Event

The PME# signal comes from a PCI device to request that the system be restarted. The PME#

signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME#

signal goes from high to low. No event is caused when it goes from low to high.

5.12.10.4 AGPBUSY# (82801BAM ICH2-M)

The AGPBUSY# signal is an input from the AGP graphics component to indicate if it is busy. If

prior to going to the C3 state the AGPBUSY# signal is active, then the BM_STS bit will be set. If

after going to the C3 state, the AGPBUSY# signal goes back active, the ICH2-M will treat this as

if one of the PCI REQ# signals went active. This will be treated as a break event.

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Functional Description

5.12.11 Alt Access Mode

Before entering a low power state, several registers from powered down parts may need to be

saved. In the majority of cases, this is not an issue, as registers have read and write paths. However,

several of the ISA compatible registers are either read only or write only. To get data out of write-

only registers and to restore data into read-only registers, the ICH2 implements an alternate access

mode.

5.12.11.1 Write Only Registers with Read Paths in Alternate Access Mode

The registers described in the following table have read paths in alternate access mode. The access

number field in the table indicates which register will be returned per access to that port.

Table 5-48. Write Only Registers with Read Paths in Alternate Access Mode

Restore Data

I/O

# of

I/O

# of

Access

Data

Access

Data

Addr Rds

DMA Chan 0 base

address low byte

Timer Counter 0 status, bits

[5:0]

00h

01h

02h

03h

04h

05h

06h

07h

DMA Chan 0 base

address high byte

Timer Counter 0 base count low

byte

DMA Chan 0 base count

low byte

Timer Counter 0 base count

high byte

DMA Chan 0 base count

high byte

Timer Counter 1 base count low

byte

40h

DMA Chan 1 base

address low byte

Timer Counter 1 base count

high byte

DMA Chan 1 base

address high byte

Timer Counter 2 base count low

byte

DMA Chan 1 base count

low byte

Timer Counter 2 base count

high byte

DMA Chan 1 base count

high byte

Timer Counter 1 status, bits

[5:0]

41h

42h

70h

DMA Chan 2 base

address low byte

Timer Counter 2 status, bits

[5:0]

DMA Chan 2 base

address high byte

Bit 7 = NMI Enable,

Bits [6:0] = RTC Address

DMA Chan 2 base count

low byte

DMA Chan 5 base address low

byte

C4h

C6h

C8h

DMA Chan 2 base count

high byte

DMA Chan 5 base address high

byte

DMA Chan 3 base

address low byte

DMA Chan 5 base count low

byte

DMA Chan 3 base

address high byte

DMA Chan 5 base count high

byte

DMA Chan 3 base count

low byte

DMA Chan 6 base address low

byte

DMA Chan 3 base count

high byte

DMA Chan 6 base address high

byte

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Functional Description

Table 5-48. Write Only Registers with Read Paths in Alternate Access Mode (Continued)

Restore Data

I/O

# of

I/O

# of

Access

Data

Access

Data

Addr Rds

DMA Chan 0–3

DMA Chan 6 base count low

byte

Command

CAh

CCh

CEh

DMA Chan 6 base count high

byte

DMA Chan 0–3 Request

DMA Chan 0 Mode:

Bits(1:0) = “00”

DMA Chan 7 base address low

byte

08h

DMA Chan 1 Mode:

Bits(1:0) = “01”

DMA Chan 7 base address high

byte

DMA Chan 2 Mode:

Bits(1:0) = “10”

DMA Chan 7 base count low

byte

DMA Chan 3 Mode:

Bits(1:0) = “11”.

DMA Chan 7 base count high

byte

PIC ICW2 of Master

controller

DMA Chan 4–7 Command

PIC ICW3 of Master

controller

DMA Chan 4–7 Request

PIC ICW4 of Master

controller

DMA Chan 4 Mode:

Bits(1:0) = “00”

D0h

PIC OCW1 of Master

DMA Chan 5 Mode:

Bits(1:0) = “01”

controller

PIC OCW2 of Master

controller

DMA Chan 6 Mode:

Bits(1:0) = “10”

PIC OCW3 of Master

controller

DMA Chan 7 Mode:

Bits(1:0) = “11”.

20h

PIC ICW2 of Slave

controller

PIC ICW3 of Slave

controller

PIC ICW4 of Slave

controller

PIC OCW1 of Slave

controller

PIC OCW2 of Slave

controller

PIC OCW3 of Slave

controller

NOTE:

1. The OCW1 register must be read before entering Alternate Access Mode.

2. Bits 5, 3, 1, and 0 return 0.

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Functional Description

5.12.11.2 PIC Reserved Bits

Many bits within the PIC are reserved, and must have certain values written for the PIC to operate

properly. Therefore, there is no need to return these values in alternate access mode. When reading

PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-49.

Table 5-49. PIC Reserved Bits Return Values

PIC Reserved Bits

Value Returned

ICW2(2:0)

ICW4(7:5)

ICW4(3:2)

ICW4(0)

000

OCW2(4:3)

OCW3(7)

OCW3(5)

OCW3(4:3)

Reflects bit 6

5.12.11.3 Read Only Registers with Write Paths in Alternate Access Mode

The registers described in Table 5-50 have write paths alternate access mode. Software restores

these values after returning from a powered down state. These registers must be handled specially

by software. When in normal mode, writing to the Base Address and Count Register also writes to

the Current Address and Count Register. Therefore, the Base Address and Count must be written

first, then the part is put into alternate access mode and the Current Address and Count Register is

written.

Table 5-50. Register Write Accesses in Alternate Access Mode

I/O Address

08h

D0h

DMA Status Register for channels 0–3.

DMA Status Register for channels 4–7.

5.12.12 System Power Supplies, Planes, and Signals

Power Plane Control with SLP_S3# and SLP_S5#

The SLP_S3# output signal can be used to cut power to the system core supply, since it will only go

active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH2

Resume Well, and to any other circuits that need to generate Wake signals from the STR state.

Cutting power to the core may be done via the power supply, or by external FETs to the

motherboard. The SLP_S5# output signal can be used to cut power to the system core supply, as

well as power to the system memory, since the context of the system is saved on the disk. Cutting

power to the memory may be done via the power supply, or by external FETs to the motherboard.

SLP_S1# Signal (82801BAM ICH2-M)

For the ICH2-M, the SLP_S1# output signal will typically be connected to the clock synthesizer’s

PWRDWN# input to stop the clock synthesizer’s PLL. Alternative implementations may use this

signal to cut power to non-critical subsystems while in the S1 state.

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Functional Description

PWROK Signal

The PWROK input should go active based on the core supply voltages becoming valid. PWROK

should go active no sooner than 10 ms after Vcc3_3 and VCC1_8 have reached their nominal

values.

Note: Traditional designs have a reset button logically AND’d with the PWROK signal from the power

supply and the processor’s voltage regulator module. If this is done with the ICH2, the

PWROK_FLR bit will be set. The ICH2 treats this internally as if the RSMRST# signal had gone

active. However, it is not treated as a full power failure. If PWROK goes inactive and then active

(but RSMRST# stays high), the ICH2 reboots (regardless of the state of the AFTERG3 bit). If the

RSMRST# signal also goes low before PWROK goes high, this is a full power failure and the

reboot policy is controlled by the AFTERG3 bit.

VRMPWRGD Signal

This signal is connected to the processor’s VRM and is internally AND’d with the PWROK signal

that comes from the system power supply. This is needed for Intel^®SpeedStep^TMtechnology

support in mobile systems (ICH2-M 82801BAM) and saves the external AND gate found in

desktop systems (82801BA ICH2).

BATLOW#—Battery Low (82801BAM ICH2-M)

For the ICH2-M, the BATLOW# input can inhibit waking from a sleep state if there is not

sufficient power. It will also cause an SMI#, if the system is already in an S0 state.

Controlling Leakage and Power Consumption During Low-Power States

To control leakage in the system, various signals will tri-state or go low during some low-power

states.

General principles

• All signals going to powered down planes (either internally or externally) must be either tri-

stated or driven low.

• Signals with pull-up resistors should not be low during low-power states. This is to avoid the

power consumed in the pull-up resistor.

• Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some

other device). Floating inputs can cause extra power consumption.

Based on the above principles, the following measures are taken:

• During C2 or S3 state (C2, S3, or C3 state for ICH2-M), the processor signals that have pull-

ups will be tri-stated or driven low.

• During S3 (STR), all signals attached to powered down planes will be tri-stated or driven low.

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Functional Description

5.12.13 Clock Generators

The clock generator is expected to provide the frequencies shown in Table 5-51.

Table 5-51. ICH2 Clock Inputs

Clock

Domain

Frequency

Source

Usage

Should be running in all Cx states. Stopped in S3 ~ S5

based on SLP_S3# assertion.

Main Clock

Generator

CLK66

66 MHz

33 MHz

82801BAM ICH2-M: It is also stopped in the S1 state based

on the assertion of SLP_S1# assertion.

Free-running PCI Clock to ICH2. Stopped in S3 ~ S5 based

on SLP_S3# assertion.

82801BAM ICH2-M: Free-running (not affected by

STP_PCI#) PCI Clock to ICH2-M. This is not the system PCI

clock. This clock must keep running in S0 while the system

PCI clock may stop based on CLKRUN# protocol . This clock

is stopped in S1 based on SLP_S1# assertion. Stopped in

S3 ~ S5 based on SLP_S3# assertion.

Main Clock

Generator

PCICLK

Used by USB Controllers. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

Main Clock

Generator

CLK48

CLK14

48 MHz

82801BAM ICH2-M: This clock is also stopped in S1 based

on SLP_S1# assertion.

Used by ACPI timers. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

Main Clock

Generator

14.318 MHz

82801BAM ICH2-M: This clock is also stopped in S1 based

on SLP_S1# assertion.

AC_BIT_CLK 12.288 MHz

AC’97 Codec

AC’97 Link. Control policy is determined by the clock source.

Used for ICH2-processor interrupt messages. Should be

running in C0, C1 and C2. Stopped in S3 ~ S5 based on

SLP_S3# assertion.

16.67 MHz

APICCLK

Main Clock

Generator

or 33 MHz

82801BAM ICH2-M: Also stopped in C3 based on

STP_CPU# assertion. Stopped in S1 based on SLP_S1#

assertion.

0.8 to

LAN_CLK

LAN Connect link. Control policy is determined by the clock

source.

LAN Connect

50 MHz

5.12.13.1 Clock Control Signals from ICH2-M to Clock Synthesizer

(82801BAM ICH2-M only)

The clock generator is assumed to have direct connect from the following ICH2-M signals:

• STP_CPU# Stops CPU clocks in C3 state

• STP_PCI# Stops system PCI clocks (not the ICH2-m free-running 33 MHz clock) due to

CLKRUN# protocol

• SLP_S1# Stops all clocks in S1

82801BA ICH2 and 82801BAM ICH2-M Datasheet

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Functional Description

5.12.14 Legacy Power Management Theory of Operation

Instead of relying on ACPI software, legacy power management uses BIOS and various hardware

mechanisms. ICH2 has a greatly simplified method for legacy power management compared with

previous generations (e.g., PIIX4).

The scheme relies on the concept of detecting when individual subsystems are idle, detecting when

the whole system is idle, and detecting when accesses are attempted to idle subsystems.

However, the operating system is assumed to be at least APM enabled. Without APM calls, there is

no quick way to know when the system is idle between keystrokes. The ICH2 does not support the

burst modes found in previous components (e.g., PIIX4).

5.12.14.1 Desktop APM Power Management (82801BA ICH2 only)

The ICH2 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable

reading the DEVACT_STS register. If none of the system bits are set, the SMI handler can

increment a software counter. When the counter reaches a sufficient number of consecutive

minutes with no activity, the SMI handler can then put the system into a lower power state.

If there is activity, various bits in the DEVACT_STS register are set. Software clears the bits by

writing a 1 to the bit position.

The DEVACT_STS Register allows for monitoring various internal devices, or Super I/O devices

(SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI.

Other PCI activity can be monitored by checking the PCI interrupts.

5.12.14.2 Mobile APM Power Management (82801BAM ICH2-M only)

In mobile systems, there are additional requirements associated with device power management.

To handle this, the ICH2-M has specific SMI# traps available. The following algorithm is used:

1. The periodic SMI# timer checks if a device is idle for the require time. If so, it puts to the

device into a low-power states and sets the associated SMI# trap.

2. When software (not the SMI# handler) attempts to access the device, a trap occurs (the cycle

doesn’t really go to the device and an SMI# is generated).

3. The SMI# handler turns on the device and turns off the trap

The SMI# handler exits with an I/O restart. This allows the original software to continue.

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Functional Description

5.13

System Management (D31:F0)

The ICH2 provides various functions to make a system easier to manage and to lower the Total

Cost of Ownership (TCO) of the system. Features and functions can be augmented via external

A/D converters and GPIO, as well as an external microcontroller. The following features and

functions are supported by the ICH2:

• Processor present detection.

— Detects if processor fails to fetch the first instruction after reset.

• Various Error detection (e.g., ECC Errors) indicated by Host Controller

— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt

• Intruder Detect input

— Can generate TCO interrupt or SMI# when the system cover is removed.

— INTRUDER# allowed to go active in any power state, including G3.

• Detection of bad FWH programming

— Detects if data on first read is FFh (indicates unprogrammed FWH)

Note: Voltage ID from the processor can be read via GPI signals.

5.13.1

Theory of Operation

The System Management functions are designed to allow the system to diagnose failing

subsystems. The intent of this logic is that some of the system management functionality be

provided without the aid of an external microcontroller.

Detecting a System Lockup

When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch

the first instruction after reset, the TCO timer times out twice and the ICH2 asserts PCIRST#.

Handling an Intruder

The ICH2 has an input signal (INTRUDER#) that can be attached to a switch that is activated by

the system’s case being open. This input has a 2 RTC clock debounce. If INTRUDER# goes active

(after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The INTRD_SEL

bits in the TCO_CNT register can enable the ICH2 to cause an SMI# or interrupt. The BIOS or

interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit.

The software can also directly read the status of the INTRUDER# signal (high or low) by clearing

and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder

function is not required.

Note: The INTRD_DET bit resides in the ICH2’s RTC well, and is set and cleared synchronously with

the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a “1” to the bit

location) there may be as much as 2 RTC clocks (about 65 µs) delay before the bit is actually

cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to guarantee that

the INTRD_DET bit will be set.

Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the

bit will remain set and the SMI will be generated again immediately. The SMI handler can clear the

INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and

then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no

SMI# be generated.

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Functional Description

Detecting Improper FWH Programming

The ICH2 can detect the case where the FWH is not programmed. This results in the first

instruction fetched to have a value of FFh. If this occurs, the ICH2 sets the BAD_BIOS bit, which

can then be reported via the Heartbeat and Event reporting using an external, Alert on LAN*

enabled LAN Controller (See Section 5.13.2).

Handling an ECC Error or Other Memory Error

The Host Controller provides a message to indicate that it would like to cause an SMI#, SCI,

SERR#, or NMI. The software must check the Host Controller as to the exact cause of the error.

5.13.2

Alert on LAN*

The ICH2 integrated LAN controller supports Alert on LAN* functionality when used with the

82562EM Platform LAN Connect component. This allows the integrated LAN controller to report

messages to a network management console without the aid of the system processor. This is crucial

in cases where the processor is malfunctioning or cannot function due to being in a low-power

state.

The ICH2 also features an independent, dedicated SMBus interface, referred to as the SMLINK

interface that can be used with an external Alert on LAN* (or Alert on LAN 2*) enabled LAN

Controller. This separate interface is required, since devices on the system SMBus will be powered

down during some low power states.

The basic scheme is for the ICH2 integrated LAN Controller to send a prepared Ethernet message

to a network management console. The prepared message is stored in the non-volatile EEPROM

that is connected to the ICH2.

Messages are sent by the LAN Controller either because a specific event has occurred or they are

sent periodically (also known as a heartbeat). The event and heartbeat messages have the exact

same format. The event messages are sent based on events occurring. The heartbeat messages are

sent every 30 to 32 seconds. When an event occurs, the ICH2 sends a new message and increments

the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment.

If the policy is for the ICH2 to reboot the system after a hardware lockup, the ICH2 does not

immediately send an Alert on LAN* message. It first attempts to reboot the processor and let the

BIOS perform the appropriate recovery (and potentially send the message). However, if the boot

fails, the ICH2 sends the message.

If the policy is for the ICH2 not to reboot after a hardware lockup, the ICH2 sends an Alert on

LAN* message with the Watchdog (WD) Event Status bit set. This message is sent as soon as the

lockup is detected. The message is sent with the next incremented sequence number. If a system is

locked, the ICH2 continues sending the Alert on LAN* messages every heartbeat period

(30–32 seconds) unless one of the following occurs:

• The system is suspended via a PowerButton Override.

• The NO_REBOOT bit (D31:F0, offset D4h, bit 1) is set and the system is reset using PWROK,

or the system is reset remotely by SMLINK SMBus Slave write and BIOS clears the

SECOND_TO_STS bit before a TCO timeout can occur.

• The NO_REBOOT bit (D31:F0, offset D4h, bit 1) is not set causing the system to reboot

automatically.

If another event occurs prior to a power button override, the ICH2 will send another Alert on LAN*

message with the next incremented sequence number and appropriate status bit set.

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Functional Description

If a boot is unsuccessful (processor does not fetch the first instruction), then the ICH2 will send an

Alert on LAN* message with the processor event status bit set and the next incremented sequence

number. This message will be sent as soon as the lockup is detected (2 TCO timer time-outs).

If the system is in a G1 (S1–S4) state the ICH2 will send a heartbeat message every 30–32 seconds.

If an event occurs prior to the system being shutdown, the ICH2 immediately sends an event

message with the next incremented sequence number. After the event message, the ICH2 resumes

sending heartbeat messages.

Note: Normally, the ICH2 does not send heartbeat messages while in the G0 state (except in the case of a

lockup). However, if a hardware event (or heartbeat) occurs just as the system is transitioning into

a G0 state, the hardware continues to send the message even though the system is in a G0 state (and

the status bits may indicate this).

When used with an external Alert on LAN* enabled LAN controller, the ICH2 sends these

messages via the SMLINK signals. When sending messages via these signals, the ICH2 abides by

the SMBus rules associated with collision detection. It delays starting a message until the bus is

idle and detects collisions. If a collision is detected, the ICH2 waits until the bus is idle and tries

again. Table 5-52 shows the data included in the Alert on LAN* messages.

Table 5-52. Alert on LAN* Message Data

Field

Comment

Cover Tamper Status

Temp Event Status

1 = This bit will be set if the intruder detect bit is set (INTRD_DET).

1 = This bit will be set if the ICH2THERM# input signal is asserted.

Processor Missing Event

Status

1 = This bit will be set if the processor failed to fetch the first instruction.

TCO Timer Event Status

Software Event Status

1 = This bit is set when the TCO timer expires.

1 = This bit is set when software writes a 1 to the SEND_NOW bit.

Unprogrammed FWH Event 1 = First BIOS fetch returned a value of FFh, indicating that the FWH has not

Status

yet been programmed (still erased).

1 = This bit is set when GPIO[11] signal is high.

0 = This bit is cleared when GPIO[11] signal is low.

GPIO Status

This is a sequence number. It will initially be 0, and will increment each time the

ICH2 sends a new message. Upon reaching 1111, then the sequence number

will roll over to 0000. MSB (SEQ3) sent first.

SEQ[3:0]

System Power State

MESSAGE1

00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first

Same as the MESSAGE1 Register. MSB sent first.

Same as the MESSAGE2 Register. MSB sent first.

Same as the WDSTATUS Register. MSB sent first.

MESSAGE2

WDSTATUS

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Functional Description

5.14

General Purpose I/O

Power Wells

Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO signals are

not driven high into powered-down planes.

Some ICH2 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs

are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override

event will result in the ICH2 driving a pin to a logic 1 to another device that is powered down.

SMI# and SCI Routing

The routing bits for GPIO[13:11,8:6,4:3,1:0] (GPIO[13:11,8:7,4:3,1:0] for the ICH2-M) allow an

input to be routed to SMI# or SCI, or neither. Note that a bit can be routed to either an SMI# or an

SCI, but not both.

Power Wells

GPIO[13:11,8:6,4:3,1] (GPIO[13:11,8:7,4:3,1:0] for the ICH2-M) have "sticky" bits on the input.

Refer to the GPE1_STS register. As long as the signal goes active for at least 2 clocks, the ICH2

will keep the sticky status bit active. The active level can be selected in the GP_LVL register.

For the 82801BA ICH2, if the system is in an S0 or an S1 state, the GPI inputs are sampled at

33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S3–S5 states,

the GPI inputs are sampled at 32.768 KHz, and thus must be active for at least 61 microseconds to

be latched.

For the 82801BAM ICH2-M, if the system is in an S0 state, the GPI inputs are sampled at

33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S1 or S3–S5

states, the GPI inputs are sampled at 32.768 KHz, and thus must be active for at least

61 microseconds to be latched.

If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger

is not required. This makes these signals "level" triggered inputs.

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Functional Description

5.15

IDE Controller (D31:F1)

The ICH2 IDE controller features two sets of interface signals (Primary and Secondary) that can be

independently enabled, tri-stated or driven low.

The IDE interfaces of the ICH2 can support several types of data transfers:

• Programmed I/O (PIO): Processor is in control of the data transfer.

• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not

use the 8237 in the ICH2. This protocol off loads the processor from moving data. This allows

higher transfer rate of up to 16 MB/s.

• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both host and

target throttling of data and transfer rates of up to 33 MB/s.

• Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both host and

target throttling of data and transfer rates of up to 66 MB/s.

• Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both host and

target throttling of data and transfer rates of up to 100 MB/s.

5.15.1

PIO Transfers

The ICH2 IDE controller includes both compatible and fast timing modes. The fast timing modes

can be enabled only for the IDE data ports. All other transactions to the IDE registers are run in

single transaction mode with compatible timings.

Up to 2 IDE devices may be attached per IDE connector (drive 0 and drive 1). The IDETIM and

SIDETIM Registers permit different timing modes to be programmed for drive 0 and drive 1 of the

same connector.

The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each drive by

programming the IDE I/O Configuration register and the Synchronous DMA Control and Timing

registers. When a drive is enabled for synchronous DMA mode operation, the DMA transfers are

executed with the synchronous DMA timings. The PIO transfers are executed using compatible

timings or fast timings if also enabled.

PIO IDE Timing Modes

IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency:

• Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and

the DA[2:0] and CSxx# lines are not set up. Startup latency provides the setup time for the

DA[2:0] and CSxx# lines prior to assertion of the read and write strobes (DIOR# and

DIOW#).

• Cycle latency consists of the I/O command strobe assertion length and recovery time.

Recovery time is provided so that transactions may occur back-to-back on the IDE interface

(without incurring startup and shutdown latency) without violating minimum cycle periods for

the IDE interface. The command strobe assertion width for the enhanced timing mode is

selected by the IDETIM Register and may be set to 2, 3, 4, or 5 PCI clocks. The recovery time

is selected by the IDETIM Register and may be set to 1, 2, 3, or 4 PCI clocks.

If IORDY is asserted when the initial sample point is reached, no wait states are added to the

command strobe assertion length. If IORDY is negated when the initial sample point is

reached, additional wait states are added. Since the rising edge of IORDY must be

synchronized, at least two additional PCI clocks are added.

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Functional Description

• Shutdown latency is incurred after outstanding scheduled IDE data port transactions (either a

non-empty write post buffer or an outstanding read prefetch cycles) have completed and

before other transactions can proceed. It provides hold time on the DA[2:0] and CSxx# lines

with respect to the read and write strobes (DIOR# and DIOW#). Shutdown latency is 2 PCI

clocks in duration.

The IDE timings for various transaction types are shown in Table 5-53. Note that bit 2 (16 bit I/O

recovery enable) of the ISA I/O Recovery Timer Register does not add wait states to IDE data port

read accesses when any of the fast timing modes are enabled.

Table 5-53. IDE Transaction Timings (PCI Clocks)

Startup

Latency

IORDY Sample

Point (ISP)

Recovery Time

(RCT)

Shutdown

Latency

IDE Transaction Type

Non-Data Port Compatible

Data Port Compatible

Fast Timing Mode

2 – 5

1 – 4

IORDY Masking

The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) on

a drive by drive basis via the IDETIM Register.

PIO 32 Bit IDE Data Port Accesses

A 32-bit PCI transaction run to the IDE data address (01F0h primary, 0170h secondary) results in

two back-to-back 16-bit transactions to the IDE data port. The 32-bit data port feature is enabled

for all timings, not just enhanced timing. For compatible timings, a shutdown and startup latency is

incurred between the two 16-bit halves of the IDE transaction. This guarantees that the chip selects

will be deasserted for at least 2 PCI clocks between the 2 cycles.

PIO IDE Data Port Prefetching and Posting

The ICH2 can be programmed via the IDETIM registers to allow data to be posted to and

prefetched from the IDE data ports.

Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to

the IDE data ports and allows them to be performed back to back for the highest possible PIO data

transfer rates. The first data port read of a sector is called the demand read. Subsequent data port

reads from the sector are called prefetch reads. The demand read and all prefetch reads much be of

the same size (16 or 32 bits).

Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI

bus after the data is received by the ICH2. The ICH2 then runs the IDE cycle to transfer the data to

the drive. If the ICH2 write buffer is non-empty and an unrelated (non-data or opposite channel)

IDE transaction occurs, that transaction is stalled until all current data in the write buffer is

transferred to the drive.

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Functional Description

5.15.2

Bus Master Function

The ICH2 can act as a PCI Bus master on behalf of an IDE slave device. Two PCI Bus master

channels are provided, one channel for each IDE connector (primary and secondary). By

performing the IDE data transfer as a PCI Bus master, the ICH2 off-loads the processor and

improves system performance in multitasking environments. Both devices attached to a connector

can be programmed for bus master transfers, but only one device per connector can be active at a

time.

Physical Region Descriptor Format

The physical memory region to be transferred is described by a Physical Region Descriptor (PRD).

The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until

all regions described by the PRDs in the table have been transferred. Note that the ICH2 bus master

IDE function does not support memory regions or Descriptor tables located on ISA.

Descriptor Tables must be aligned on 64 KB boundaries. Each PRD entry in the table is 8 bytes in

length. The first 4 bytes specify the byte address of a physical memory region. This memory region

must be DWord aligned and must not cross a 64 KB boundary. The next two bytes specify the size

or transfer count of the region in bytes (64 KB limit per region). A value of zero in these two bytes

indicates 64 KB (thus the minimum transfer count is 1). If bit 7 (EOT) of the last byte is a 1, it

indicates that this is the final PRD in the Descriptor table. Bus master operation terminates when

the last descriptor has been retired.

When the Bus Master IDE controller is reading data from the memory regions, bit 1 of the Base

Address is masked and byte enables are asserted for all read transfers. When writing data, bit 1 of

the Base Address is not masked and if set, causes the lower Word byte enables to be deasserted for

the first DWord transfer. The write to PCI typically consists of a 32-byte cache line. If valid data

ends prior to end of the cache line, the byte enables will be deasserted for invalid data.

The total sum of the byte counts in every PRD of the descriptor table must be equal to or greater

than the size of the disk transfer request. If greater than the disk transfer request, the driver must

terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to

0) when the drive issues an interrupt to signal transfer completion.

Figure 5-15. Physical Region Descriptor Table Entry

Main Memory

Main Region

Byte 3

Memory Region Physical Base Address [31:1]

Reserved Byte Count [15:1]

Byte 2

Byte 1

Byte 0

EOT

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Functional Description

Line Buffer

A single line buffer exists for the ICH2 Bus master IDE interface. This buffer is not shared with

any other function. The buffer is maintained in either the read state or the write state. Memory

writes are typically 4-DWord bursts and invalid DWords have C/BE[3:0]#=0Fh. The line buffer

allows burst data transfers to proceed at peak transfer rates.

The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically when the

controller has transferred all data associated with a Descriptor Table (as determined by EOT bit in

last PRD). The IDE Interrupt Status bit is set when the IDE device generates an interrupt. These

events may occur prior to line buffer emptying for memory writes. If either of these conditions

exist, all PCI Master non-memory read accesses to ICH2 are retried until all data in the line buffers

has been transferred to memory.

Bus Master IDE Timings

The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The

DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for

DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster that

its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock

that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is deasserted on

the next PCI clock and no more transfers take place until DMA request is asserted again.

Interrupts

The ICH2 is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt.

This connection is done from the ISA pin, before any mask registers. This implies the following:

• Bus Master IDE is operating under an interrupt based driver. Therefore, it does not operate

under environments where the IDE device drives an interrupt but the interrupt is masked in the

system.

• Bus Master IDE devices are connected directly off of ICH2. IDE interrupts cannot be

communicated through PCI devices or the serial stream.

Bus Master IDE Operation

To initiate a bus master transfer between memory and an IDE device, the following steps are

required:

1. Software prepares a PRD Table in system memory. The PRD Table must be DWord aligned

and must not cross a 64 KB boundary.

2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer

The interrupt bit and Error bit in the Status register are cleared.

3. Software issues the appropriate DMA transfer command to the disk device.

4. The bus master function is engaged by software writing a '1' to the Start bit in the Command

visible by software, the Current Base and Current Count registers. These registers hold the

current value of the address and byte count loaded from the PRD table. The value in these

registers is only valid when there is an active command to an IDE device.

5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.

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Functional Description

6. The controller transfers data to/from memory responding to DMA requests from the IDE

device. The IDE device and the host controller may or may not throttle the transfer several

times. When the last data transfer for a region has been completed on the IDE interface, the

next descriptor is fetched from the table. The descriptor contents are loaded into the Current

Base and Current Count registers.

7. At the end of the transfer the IDE device signals an interrupt.

8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then

reads the controller status followed by the drive status to determine if the transfer completed

successfully.

The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers

terminate when the physical region described by the last PRD in the table has been completely

transferred. The active bit in the Status Register is reset and the DDRQ signal masked.

The buffer is flushed (when in the write state) or invalidated (when in the read state) when a

terminal count condition exists (i.e., the current region descriptor has the EOL bit set and that

region has been exhausted). The buffer is also flushed (write state) or invalidated (read state) when

the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register

and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, can be assured

that all data destined for system memory has been transferred and that data is valid in system

memory. Table 5-54 describes how to interpret the Interrupt and Active bits in the Status Register

after a DMA transfer has started.

During concurrent DMA or Ultra ATA transfers, the ICH2 IDE interface arbitrates between the

primary and secondary IDE cables when a PRD expires.

Table 5-54. Interrupt/Active Bit Interaction Definition

Interrupt

Active

Description

DMA transfer is in progress. No interrupt has been generated by the IDE device.

The IDE device generated an interrupt. The controller exhausted the Physical

Region Descriptors. This is the normal completion case where the size of the

physical memory regions was equal to the IDE device transfer size.

The IDE device generated an interrupt. The controller has not reached the end of the

physical memory regions. This is a valid completion case where the size of the

physical memory regions was larger than the IDE device transfer size.

This bit combination signals an error condition. If the Error bit in the status register is

set, then the controller has some problem transferring data to/from memory.

Specifics of the error have to be determined using bus-specific information. If the

Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size.

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Functional Description

Error Conditions

IDE devices are sector based mass storage devices. The drivers handle errors on a sector basis;

either a sector is transferred successfully or it is not. A sector is 512 bytes.

If the IDE device does not complete the transfer due to a hardware or software error, the command

will eventually be stopped by the driver setting Command Start bit to zero when the driver times

out the disk transaction. Information in the IDE device registers help isolate the cause of the

problem.

If the controller encounters an error while doing the bus master transfers it stops the transfer

(i.e., reset the Active bit in the Command register) and sets the Error bit in the Bus Master IDE

Status register. The controller does not generate an interrupt when this happens. The device driver

can use device specific information (PCI Configuration Space Status register and IDE Drive

When a requested transfer does not complete properly, information in the IDE device registers

(Sector Count) can be used to determine how much of the transfer was completed and to construct

a new PRD table to complete the requested operation. In most cases the existing PRD table can be

used to complete the operation.

8237-Like Protocol

The 8237 mode DMA is similar in form to DMA used on the ISA bus. This mode uses pins

familiar to the ISA bus, namely a DMA Request, a DMA Acknowledge, and I/O read/write strobes.

These pins have similar characteristics to their ISA counterparts in terms of when data is valid

relative to strobe edges, and the polarity of the strobes, however the ICH2 does not use the 8237 for

this mode.

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Functional Description

5.15.3

Ultra ATA/33 Protocol

Ultra ATA/33 is enabled through configuration register 48h in Device 31:Function 1 for each IDE

device. The IDE signal protocols are significantly different under this mode than for the 8237

mode.

Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33 capable IDE

controller such as the ICH2 and one or more Ultra ATA/33 capable IDE devices. It utilizes the

standard Bus Master IDE functionality and interface to initiate and control the transfer. Ultra

ATA/33 utilizes a “source synchronous” signaling protocol to transfer data at rates up to 33 MB/s.

The Ultra ATA/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16) error

checking protocol.

Signal Descriptions

The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does redefine a

number of the standard IDE control signals when in Ultra ATA/33 mode. These redefinitions are

shown in Table 5-55. Read cycles are defined as transferring data from the IDE device to the ICH2.

Write cycles are defined as transferring data from ICH2 to IDE device.

Table 5-55. UltraATA/33 Control Signal Redefinitions

Standard IDE

Signal Definition

Ultra ATA/33 Read

Cycle Definition

Ultra ATA/33 Write

Cycle Definition

ICH2 Primary

Channel Signal

ICH2 Secondary

Channel Signal

DIOW#

DIOR#

IORDY

STOP

PDIOW#

PDIOR#

PIORDY

SDIOW#

SDIOR#

SIORDY

DMARDY#

STROBE

DMARDY#

The DIOW# signal is redefined as STOP for both read and write transfers. This is always driven by

the ICH2 and is used to request that a transfer be stopped or as an acknowledgment to stop a

request from the IDE device.

The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device to the

ICH2 (read). It is used by the ICH2 to signal when it is ready to transfer data and to add wait states

to the current transaction. The DIOR# signal is redefined as STROBE for transferring data from the

ICH2 to the IDE device (write). It is the data strobe signal driven by the ICH2 on which data is

transferred during each rising and falling edge transition.

The IORDY signal is redefined as STROBE for transferring data from the IDE device to the ICH2

(read). It is the data strobe signal driven by the IDE device on which data is transferred during each

rising and falling edge transition. The IORDY signal is redefined as DMARDY# for transferring

data from the ICH2 to the IDE device (write). It is used by the IDE device to signal when it is ready

to transfer data and to add wait states to the current transaction.

All other signals on the IDE connector retain their functional definitions during Ultra ATA/33

operation.

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Functional Description

Operation

Initial setup programming consists of enabling and performing the proper configuration of ICH2

and the IDE device for Ultra ATA/33 operation. For ICH2, this consists of enabling Synchronous

DMA mode and setting up appropriate Synchronous DMA timings.

When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is

followed. Once programmed, the drive and ICH2 control the transfer of data via the Ultra ATA/33

protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase,

and a burst termination phase.

The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the

transfer, the ICH2 asserts the DMACK# signal. When DMACK# signal is asserted, the host

controller drives CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the ICH2 deasserts

STOP, waits for the IDE device to assert DMARDY#, and then drives the first data word and

STROBE signal. For read cycles, the ICH2 tri-states the DD lines, deasserts STOP, and asserts

DMARDY#. The IDE device then sends the first data word and STROBE.

The data transfer phase continues the burst transfers with the data transmitter (ICH2 - writes, IDE

device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on

each rising and falling edge of STROBE. The transmitter can pause the burst by holding STROBE

high or low, resuming the burst by again toggling STROBE. The receiver can pause the burst by

deasserting DMARDY# and resumes the transfers by asserting DMARDY#. The ICH2 pauses a

burst transaction to prevent an internal line buffer over or under flow condition, resuming once the

condition has cleared. It may also pause a transaction if the current PRD byte count has expired,

resuming once it has fetched the next PRD.

The current burst can be terminated by either the transmitter or receiver. A burst termination

consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The ICH2 can stop a burst

by asserting STOP; the IDE device acknowledges by deasserting DMARQ. The IDE device stops a

burst by deasserting DMARQ and the ICH2 acknowledges by asserting STOP. The transmitter then

drives the STROBE signal to a high level. The ICH2 then drives the CRC value on the DD lines

and deasserts DMACK#. The IDE device latches the CRC value on the rising edge of DMACK#.

The ICH2 terminates a burst transfer if it needs to service the opposite IDE channel, if a

Programmed I/O (PIO) cycle is executed to the IDE channel currently running the burst, or upon

transferring the last data from the final PRD.

CRC Calculation

Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33 transfers. The

CRC value is calculated for all data by both the ICH2 and the IDE device over the duration of the

Ultra ATA/33 burst transfer segment. This segment is defined as all data transferred with a valid

STROBE edge from DDACK# assertion to DDACK# deassertion. At the end of the transfer burst

segment, the ICH2 drives the CRC value onto the DD[15:0] signals. It is then latched by the IDE

device on deassertion of DDACK#. The IDE device compares the ICH2 CRC value to its own and

reports an error if there is a mismatch.

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Functional Description

5.15.4

Ultra ATA/66 Protocol

In addition to Ultra ATA/33, the ICH2 supports the Ultra ATA/66 protocol. The Ultra ATA/66

protocol is enabled via configuration bits 3:0 at offset 54h. The two protocols are similar, and are

intended to be device driver compatible. The Ultra ATA/66 logic can achieve transfer rates of up to

66 MB/s.

To achieve the higher data rate, the timings are shortened and the quality of the cable is improved

to reduce reflections, noise, and inductive coupling. Note that the improved cable is required and

will still plug into the standard IDE connector. The Ultra ATA/66 protocol also supports a 44 MB/s

mode.

5.15.5

5.15.6

Ultra ATA/100 Protocol

When the ATA_FAST bit is set for any of the 4 IDE devices, the timings for the transfers to and

from the corresponding device run at a higher rate. The ICH2 Ultra ATA/100 logic can achieve

read transfer rates up to 100 MB/s and write transfer rates up to 88.9 MB/s.

The cable improvements required for Ultra ATA/66 are sufficient for Ultra ATA/100, so no further

cable improvements are required when implementing Ultra ATA/100.

Ultra ATA/33/66/100 Timing

The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing

in the system. The Base Clock frequency for each drive is selected in the IDE Configuration

Clock) are programmed in the Synchronous DMA Timing Register. The Cycle Time represents the

minimum pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the

number of Base Clock periods that the ICH2 will wait from deassertion of DMARDY# to the

assertion of STOP when it desires to stop a burst read transaction.

Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT)

must be set for 3 Base Clocks. The ICH2, thus, toggles the write strobe signal every 22.5 ns,

transferring two bytes of data on each strobe edge. This means that the ICH2 performs Mode 5

write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe is driven by the

ATA/100 device; the ICH2 supports reads at the maximum rate of 100 MB/s.

5.15.7

Mobile IDE Swap Bay (82801BAM ICH2-M only)

To support a mobile swap bay, the ICH2-M allows the IDE output signals to be tri-stated and input

buffers to be turned off. This should be done prior to the removal of the drive.

The output signals can also be driven low. This can be used to remove charge built up on the

signals.New configuration bits are included in the IDE I/O Configuration Register, offset 54h in

the IDE PCI configuration space.

WARNING: The software should NOT attempt to control the outputs (either tri-state or driving

low), while an IDE transfer is in progress. Unpredictable results could occur,

including a system lockup.

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Functional Description

5.16

USB Controller (Device 31:Functions 2 and 4)

The ICH2 contains two USB Host Controllers. Each Host Controller includes a root hub with two

separate USB ports each, for a total of 4 USB ports. The ICH2 Host Controllers support the

standard Universal Host Controller Interface (UHCI) Rev 1.1.

Overcurrent detection on all 4 USB ports is supported. The overcurrent inputs are 5V-tolerant, and

can be used as GPIs if not needed.

The ICH2’s USB controllers are arbitrated as differently than standard PCI devices to improve

arbitration latency.

5.16.1

Data Structures in Main memory

This section describes the details of the data structures used to communicate control, status, and

data between software and the ICH2: Frame Lists, Transfer Descriptors, and Queue Heads. Frame

Lists are aligned on 4-KB boundaries. Transfer Descriptors and Queue Heads are aligned on

16-byte boundaries.

5.16.1.1

Frame List Pointer

The frame list pointer contains a link pointer to the first data object to be processed in the frame, as

well as the control bits defined in Table 5-56.

Table 5-56. Frame List Pointer Bit Description

Bit

Description

Frame List Pointer (FLP). This field contains the address of the first data object to be processed in

the frame and corresponds to memory address signals [31:4], respectively.

31:4

3:2

Reserved. These bits must be written as 0.

QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer

is a TD (Transfer Descriptor) or a QH (Queue Head). This allows the ICH2 to perform the proper type

of processing on the item after it is fetched.

1 = QH

0 = TD

Terminate (T). This bit indicates to the ICH2 whether the schedule for this frame has valid entries in

it.

1 = Empty Frame (pointer is invalid).

0 = Pointer is valid (points to a QH or TD).

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Functional Description

5.16.1.2

Transfer Descriptor (TD)

Transfer Descriptors (TDs) express the characteristics of the transaction requested on USB by a

client. TDs are always aligned on 16-byte boundaries, and the elements of the TD are shown in

Figure 5-16. The 4 different USB transfer types are supported by a small number of control bits in

the descriptor that the ICH2 interprets during operation. All Transfer Descriptors have the same

basic, 32-byte structure. During operation, the ICH2 hardware performs consistency checks on

some fields of the TD. If a consistency check fails, the ICH2 halts immediately and issues an

interrupt to the system. This interrupt cannot be masked within the ICH2.

Figure 5-16. Transfer Descriptor

31 30 29 28 27 26 25 24 23 21 20 19 18 16 15 14

11 10 8 7

4 3

Link Pointer

ActLen

PID

SPD C_ERR LS ISOISC

MaxLen

Status

EndPt

Device Address

Buffer Pointer

R = Reserved

ICH2 Read/Write

ICH2 Read Only

Table 5-57. TD Link Pointer

Bit

Description

Link Pointer (LP). Bits [31:4] Correspond to memory address signals [31:4], respectively. This field

points to another TD or QH.

31:4

Reserved. Must be 0 when writing this field.

Depth/Breadth Select (VF). This bit is only valid for queued TDs and indicates to the hardware

whether it should process in a depth first or breadth first fashion. When set to depth first, it informs

the ICH2 to process the next transaction in the queue rather than starting a new queue.

1 = Depth first.

0 = Breadth first.

QH/TD Select (Q). This bit informs the ICH2 whether the item referenced by the link pointer is

another TD or a QH. This allows the ICH2 to perform the proper type of processing on the item after

it is fetched

1 = QH.

0 = TD.

Terminate (T). This bit informs the ICH2 that the link pointer in this TD does not point to another

valid entry. When encountered in a queue context, this bit indicates to the ICH2 that there are no

more valid entries in the queue. A TD encountered outside of a queue context with the T bit set

informs the ICH2 that this is the last TD in the frame.

1 = Link Pointer field not valid.

0 = Link Pointer field is valid.

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Functional Description

Table 5-58. TD Control and Status

Bit

Description

31:30 Reserved.

Short Packet Detect (SPD). When a packet has this bit set to 1 and the packet is an input packet, is

in a queue; and successfully completes with an actual length less than the maximum length then the

TD is marked inactive, the Queue Header is not updated and the USBINT status bit (Status

sent at the end of the frame.

Note that any error (e.g., babble or FIFO error) prevents the short packet from being reported. The

behavior is undefined when this bit is set with output packets or packets outside of queues.

1 = Enable.

0 = Disable.

Error Counter (C_ERR). This field is a 2-bit down counter that keeps track of the number of Errors

detected while executing this TD. If this field is programmed with a non zero value during setup, the

ICH2 decrements the count and writes it back to the TD if the transaction fails. If the counter counts

from one to zero, the ICH2 marks the TD inactive, sets the “STALLED” and error status bit for the

error that caused the transition to zero in the TD. An interrupt will be generated to Host Controller

Driver (HCD) if the decrement to zero was caused by Data Buffer error, Bit stuff error, or if enabled,

a CRC or Timeout error. If HCD programs this field to zero during setup, the ICH2 will not count

errors for this TD and there will be no limit on the retries of this TD.

Bits[28:27]

Interrupt After

No Error Limit

1 Error

2 Errors

3 Errors

28:27

Error

Decrement Counter

Error

Decrement Counter

CRC Error

Yes

Data Buffer Error

Stalled

Yes

No*

Yes

Timeout Error

NAK Received

Babble Detected

Bit stuff Error

No*

*Detection of Babble or Stall automatically deactivates the TD. Thus, count is not decremented.

* Detection of Babble or Stall automatically deactivates the TD. Thus, count is not decremented.

Low Speed Device (LS). This bit indicates that the target device (USB data source or sink) is a low

speed device, running at 1.5 Mb/s, instead of at full speed (12 Mb/sec). There are special

restrictions on schedule placement for low speed TDs. If an ICH2 root hub port is connected to a full

speed device and this bit is set to a 1 for a low speed transaction, the ICH2 sends out a low speed

preamble on that port before sending the PID. No preamble is sent if a ICH2 root hub port is

connected to a low speed device.

1 = Low Speed Device

0 = Full Speed Device

Isochronous Select (IOS). The field specifies the type of the data structure. If this bit is set to a 1,

then the TD is an isochronous transfer. Isochronous TDs are always marked inactive by the

hardware after execution, regardless of the results of the transaction.

1 = Isochronous Transfer Descriptor

0 = Non-isochronous Transfer Descriptor

Interrupt on Complete (IOC). This specifies that the ICH2 should issue an interrupt on completion

of the frame in which this Transfer Descriptor is executed. Even if the Active bit in the TD is already

cleared when the TD is fetched (no transaction will occur on USB), an IOC interrupt is generated at

the end of the frame.

1 = Issue IOC

Active. For ICH2 schedule execution operations, see the Data Transfers To/From Main Memory

section.

1 = Set to 1 by software to enable the execution of a message transaction by the ICH2.

0 = When the transaction associated with this descriptor is completed, the ICH2 sets this bit to 0

indicating that the descriptor should not be executed when it is next encountered in the

schedule. The Active bit is also set to 0 if a stall handshake is received from the endpoint.

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Functional Description

Table 5-58. TD Control and Status (Continued)

Bit

Description

Stalled.

1 = Set to a 1 by the ICH2 during status updates to indicate that a serious error has occurred at the

device/endpoint addressed by this TD. This can be caused by babble, the error counter

counting down to zero, or reception of the STALL handshake from the device during the

transaction. Any time that a transaction results in the Stalled bit being set, the Active bit is also

cleared (set to 0). If a STALL handshake is received from a SETUP transaction, a Time Out

Error will also be reported.

Data Buffer Error (DBE).

1 = Set to a 1 by the ICH2 during status update to indicate that the ICH2 is unable to keep up with

the reception of incoming data (overrun) or is unable to supply data fast enough during

transmission (underrun). When this occurs, the actual length and Max Length field of the TD will

not match. In the case of an underrun, the ICH2 transmits an incorrect CRC (thus invalidating

the data at the endpoint) and leaves the TD active (unless error count reached zero). If a

overrun condition occurs, the ICH2 forces a timeout condition on the USB, invalidating the

transaction at the source.

Babble Detected (BABD).

1 = Set to a 1 by the ICH2 during status update when “babble” is detected during the transaction

generated by this descriptor. Babble is unexpected bus activity for more than a preset amount of

time. In addition to setting this bit, the ICH2 also sets the” STALLED” bit (bit 22) to a 1. Since

”babble” is considered a fatal error for that transfer, setting the” STALLED” bit to a 1 insures that

no more transactions occur as a result of this descriptor. Detection of babble causes immediate

termination of the current frame. No further TDs in the frame are executed. Execution resumes

with the next frame list index.

Negative Acknowledgment (NAK) Received (NAKR).

1 = Set to a 1 by the ICH2 during status update when the ICH2 receives a “NAK” packet during the

transaction generated by this descriptor. If a NAK handshake is received from a SETUP

transaction, a Time Out Error is also be reported.

CRC/Time Out Error (CRC_TOUT).

1 = Set to a 1 by the ICH2 as follows:

During a status update in the case that no response is received from the target device/endpoint

within the time specified by the protocol chapter of the USB specification.

During a status update when a Cycli Redundancy Check (CRC) error is detected during the

transaction associated with this transfer descriptor.

In the transmit case (OUT or SETUP Command), this is in response to the ICH2 detecting a

timeout from the target device/endpoint.

In the receive case (IN Command), this is in response to the ICH2’s CRC checker circuitry

detecting an error on the data received from the device/endpoint or a NAK or STALL handshake

being received in response to a SETUP transaction.

Bit stuff Error (BSE).

1 = This bit is set to a 1 by the ICH2 during status update to indicate that the receive data stream

contained a sequence of more than 6 ones in a row.

Bus Turn Around Time-out (BTTO).

1 = This bit is set to a 1 by the ICH2 during status updates to indicate that a bus time-out condition

was detected for this USB transaction. This time-out is specially defined as not detecting an

IDLE-to ‘K’ state Start of Packet (SOP) transition from 16 to 18 bit times after the SE0-to IDE

transition of previous End of Packet (EOP).

15:11 Reserved

Actual Length (ACTLEN). The Actual Length field is written by the ICH2 at the conclusion of a USB

transaction to indicate the actual number of bytes that were transferred. It can be used by the

software to maintain data integrity. The value programmed in this register is encoded as n-1 (see

Maximum Length field description in the TD Token).

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Functional Description

Table 5-59. TD Token

Bit

Description

Maximum Length (MAXLEN). The Maximum Length field specifies the maximum number of data

bytes allowed for the transfer. The Maximum Length value does not include protocol bytes, such as

Packet ID (PID) and CRC. The maximum data packet is 1280 bytes. The 1280 packet length is the

longest packet theoretically guaranteed to fit into a frame. Actual packet maximum lengths are set

by HCD according to the type and speed of the transfer. Note that the maximum length allowed by

the USB specification is 1023 bytes. The valid encodings for this field are:

0x000 = 1 byte

0x001 = 2 bytes

....

0x3FE = 1023 bytes

31:21

0x3FF = 1024 bytes

....

0x4FF = 1280 bytes

0x7FF = 0 bytes (null data packet)

Note that values from 500h to 7FEh are illegal and cause a consistency check failure.

In the transmit case, the ICH2 uses this value as a terminal count for the number of bytes it fetches

from host memory. In most cases, this is the number of bytes it will actually transmit. In rare cases,

the ICH2 may be unable to access memory (e.g., due to excessive latency) in time to avoid

underrunning the transmitter. In this instance the ICH2 would transmit fewer bytes than specified in

the Maximum Length field.

Reserved.

Data Toggle (D). This bit is used to synchronize data transfers between a USB endpoint and the

host. This bit determines which data PID is sent or expected (0=DATA0 and 1=DATA1). The Data

Toggle bit provides a 1-bit sequence number to check whether the previous packet completed. This

bit must always be 0 for Isochronous TDs.

Endpoint (ENDPT). This 4-bit field extends the addressing internal to a particular device by

18:15 providing 16 endpoints. This permits more flexible addressing of devices in which more than one

sub-channel is required.

14:8

Device Address. This field identifies the specific device serving as the data source or sink.

Packet Identification (PID). This field contains the Packet ID to be used for this transaction. Only

the IN (69h), OUT (E1h), and SETUP (2Dh) tokens are allowed. Any other value in this field causes

a consistency check failure resulting in an immediate halt of the ICH2. Bits [3:0] are complements of

bits [7:4].

7:0

Table 5-60. TD Buffer Pointer

Bit

Description

Buffer Pointer (BUFF_PNT). Bits [31:0] corresponds to memory address [31:0], respectively. It

points to the beginning of the buffer that will be used during this transaction. This buffer must be at

least as long as the value in the Maximum Length field described int the TD Token. The data buffer

may be byte-aligned.

31:0

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Functional Description

5.16.1.3

Queue Head (QH)

Queue heads are special structures used to support the requirements of Control, Bulk and Interrupt

transfers. Since these TDs are not automatically retired after each use, their maintenance

requirements can be reduced by putting them into a queue. Queue Heads must be aligned on a

16-byte boundary; the elements are shown in Table 5-61.

Table 5-61. Queue Head Block

Bytes

Description

Attributes

00:03

04:07

Queue Head Link Pointer

Queue Element Link Pointer

R/W

Table 5-62. Queue Head Link Pointer

Bit

Description

Queue Head Link Pointer (QHLP). This field contains the address of the next data object to be

processed in the horizontal list and corresponds to memory address signals [31:4], respectively.

31:4

3:2

Reserved. These bits must be written as 0s.

QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer

is another TD or a QH.

1=QH

0=TD

Terminate (T). This bit indicates to the ICH2 that this is the last QH in the schedule. If there are active

TDs in this queue, they are the last to be executed in this frame.

1 = Last QH (pointer is invalid).

0 = Pointer is valid (points to a QH or TD).

Table 5-63. Queue Element Link Pointer

Bit

Description

Queue Element Link Pointer (QELP). This field contains the address of the next TD or QH to be

processed in this queue and corresponds to memory address signals [31:4], respectively.

31:4

3:2

Reserved.

QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer

is another TD or a QH. For entries in a queue, this bit is typically set to 0.

1 = QH

0 = TD

Terminate (T). This bit indicates to the ICH2 that there are no valid TDs in this queue. When HCD

has new queue entries it overwrites this value with a new TD pointer to the queue entry.

1 = Terminate (No valid queue entries).

0 = Pointer is valid.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

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Functional Description

5.16.2

Data Transfers To/From Main Memory

The following sections describe the details on how HCD and the ICH2 communicate via the

Schedule data structures. The discussion is organized in a top-down manner, beginning with the

basics of walking the Frame List, followed by a description of generic processing steps common to

all transfer descriptors, and finally a discussion on Transfer Queuing.

5.16.2.1

Executing the Schedule

Software programs the ICH2 with the starting address of the Frame List and the Frame List index,

then causes the ICH2 to execute the schedule by setting the Run/Stop bit in the Control register to

Run. The ICH2 processes the schedule one entry at a time. The next element in the frame list is not

fetched until the current element in the frame list is retired.

Schedule execution proceeds in the following fashion:

• The ICH2 first fetches an entry from the Frame List. This entry has three fields. Bit 0 indicates

whether the address pointer field is valid. Bit 1 indicates whether the address points to a

Transfer Descriptor or to a queue head. The third field is the pointer itself.

• If isochronous traffic is to be moved in a given frame, the Frame List entry points to a Transfer

Descriptor. If no isochronous data is to be moved in that frame, the entry points to a queue

head or the entry is marked invalid and no transfers are initiated in that frame.

• If the Frame List entry indicates that it points to a Transfer Descriptor, the ICH2 fetches the

entry and begins the operations necessary to initiate a transaction on USB. Each TD contains a

link field that points to the next entry, as well as indicating whether it is a TD or a QH.

• If the Frame List entry contains a pointer to a QH, the ICH2 processes the information from

the QH to determine the address of the next data object that it should process.

• The TD/QH process continues until the millisecond allotted to the current frame expires. At

this point, the ICH2 fetches the next entry from the Frame List. If the ICH2 is not able to

process all of the transfer descriptors during a given frame, those descriptors are retired by

software without having been executed.

5.16.2.2

Processing Transfer Descriptors

The ICH2 executes a TD using the following generalized algorithm. These basic steps are common

across all modes of TDs. Subsequent sections present processing steps unique to each TD mode.

1. ICH2 Fetches TD or QH from the current Link Pointer.

2. If a QH, go to 1 to fetch from the Queue Element Link Pointer. If inactive, go to 12

3. Build Token, actual bits are in TD Token.

4. If (Host-to-Function) then

[PCI Access] issue request for data, (referenced through TD.BufferPointer)

wait for first chunk data arrival

end if

5. [Begin USB Transaction] Issue Token (from token built in 2, above) and begin data transfer.

if (Host-to-Function) then Go to 6

else Go to 7

end if

6. Fetch data from memory (via TD BufferPointer) and transfer over USB until TD Max-Length

bytes have been read and transferred. [Concurrent system memory and USB Accesses]. Go to

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Functional Description

7. Wait for data to arrive (from USB). Write incoming bytes into memory beginning at TD

BufferPointer. Internal HC buffer should signal end of data packet. Number of bytes received

must be (TD Max-Length; The length of the memory area referenced by TD BufferPointer

must be (TD Max-Length. [Concurrent system memory and USB Accesses].

8. Issue handshake based on status of data received (Ack or Time-out). Go to 10.

9. Wait for handshake, if required [End of USB Transaction].

10. Update Status [PCI Access] (TD.Status and TD.ActualLength).

If the TD was an isochronous TD, mark the TD inactive. Go to 12.

If not an isochronous TD, and the TD completed successfully, mark the TD inactive. Go to 11.

If not successful, and the error count has not been reached, leave the TD active. If the error

count has been reached, mark the TD inactive. Go to 12.

11. Write the link pointer from the current TD into the element pointer field of the QH structure. If

the Vf bit is set in the TD link pointer, go to 2.

12. Proceed to next entry.

5.16.2.3

Command Register, Status Register, and TD Status Bit Interaction

Table 5-64. Command Register, Status Register and TD Status Bit Interaction

Condition

ICH2 USB Status Register Actions

TD Status Register Actions

Clear Active bit and set Stall

bit

CRC/Time Out Error

Set USB Error Int bit , Clear HC Halted bit

Illegal PID, PID Error,

Max Length (illegal)

Clear Run/Stop bit in command register

Set HC Process Error and HC Halted bits

Clear Run/Stop bit in command register

Set Host System Error and HC Halted bits

PCI Master/Target

Abort

Clear Run/Stop bit in command register

Suspend Mode

Set HC Halted bit

Resume Received and

Suspend Mode = 1

Set Resume received bit

Clear Run/Stop bit in command register

Set HC Halted bit

Run/Stop = 0

configuration Flag Set

Set configuration Flag in command register

Clear Run/Stop and configuration Flag in

command register

HC Reset/Global Reset

Clear USB Int, USB Error Int, Resume received,

Host System Error, HC Process Error, and HC

Halted bits

IOC = 1 in TD Status

Stall

Set USB Int bit

Set USB Error Int bit

Clear Active bit and set Stall bit

Bit Stuff/Data Buffer

Error

Clear Active bit and set Stall

bit

Set USB Error Int bit

Short Packet Detect

Set USB Int bit

Clear Active bit

NOTES:

1. Only If error counter counted down from 1 to 0

2. Suspend mode can be entered only when Run/Stop bit is 0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

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Functional Description

Note that, if a NAK or STALL response is received from a SETUP transaction, a Time Out Error

will be reported. This causes the Error counter to decrement and the CRC/Time-out Error status bit

to be set within the TD Control and Status DWord during write back. If the Error counter changes

from 1 to 0, the Active bit is reset to 0 and Stalled bit to 1 as normal.

5.16.2.4

Transfer Queuing

Transfer Queues are used to implement a guaranteed data delivery stream to a USB Endpoint.

Transfer Queues are composed of two parts: a Queue Header (QH) and a linked list. The linked list

of TDs and QHs has an indeterminate length (0 to n).

The QH contains two link pointers and is organized as two contiguous DWords. The first DWord is

a horizontal pointer (Queue Head Link Pointer), used to link a single transfer queue with either

another transfer queue, or a TD (target data structure depends on Q bit). If the T bit is set, this QH

represents the last data structure in the current Frame. The T bit informs the ICH2 that no further

processing is required until the beginning of the next frame. The second DWord is a vertical pointer

(Queue Element Link Pointer) to the first data structure (TD or QH) being managed by this QH. If

the T bit is set, the queue is empty. This pointer may reference a TD or another QH.

Figure 5-17 illustrates four example queue conditions. The first QH (on far left) is an example of

an “empty” queue; the termination bit (T Bit), in the vertical link pointer field, is set to 1. The

horizontal link pointer references another QH. The next queue is the expected typical

configuration. The horizontal link pointer references another QH, and the vertical link pointer

references a valid TD.

Typically, the vertical pointer in a QH points to a TD. However, as shown in Figure 5-17 (third

example from left side of figure) the vertical pointer could point to another QH. When this occurs,

a new Q Context is entered and the Q Context just exited is NULL (ICH2 does not update the

vertical pointer field).

The far right QH is an example of a frame ‘termination’ node. Since its horizontal link pointer has

its termination bit set, the ICH2 assumes there is no more work to complete for the current Frame.

Figure 5-17. Example Queue Conditions

Frame List Pointer

Indicates "Nil" Next Pointer

Link Pointer (Horiz)

Link Pointer (Vert)

Link Pointer (Horiz)

Link Pointer (Vert)

Link Pointer (Horiz)

Link Pointer (Vert)

Link Pointer (Horiz)

Link Pointer (Vert)

Indicates "Nil" Next Pointer

Indicates "Null" Queue Head

Link Pointer

Q T

Link Pointer (Horiz)

Link Pointer (Vert)

Link Pointer

Notes:

1. Link Pointer (Horiz) = Queue Head Link Pointer

field in QH DWord 0

2. Link Pointer (Vert) = Queue Element Link Pointer

field in QH DWord 1

Link Pointer

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Functional Description

Transfer Queues are based on the following characteristics:

• A QH’s vertical link pointer (Queue Element Link Pointer) references the ‘Top’ queue

member. A QH’s horizontal link pointer (Queue Head Link Pointer) references the “next”

work element in the Frame.

• Each queue member’s link pointer references the next element within the queue.

In the simplest model, the ICH2 follows vertical link point to a queue element, then executes the

element. If the completion status of the TD satisfies the advance criteria as shown in Table 5-65,

the ICH2 advances the queue by writing the just-executed TD’s link pointer back into the QH’s

Queue Element link pointer. The next time the queue head is traversed, the next queue element will

be the Top element.

The traversal has two options: Breadth first, or Depth first. A flag bit in each TD (Vf - Vertical

Traversal Flag) controls whether traversal is Breadth or Depth first. The default mode of traversal

is Breadth-First. For Breadth-First, the ICH2 only executes the top element from each queue. The

execution path is shown below:

1. QH (Queue Element Link Pointer)

2. TD

3. Write-Back to QH (Queue Element Link Pointer)

4. QH (Queue Head Link pointer).

Breadth-First is also performed for every transaction execution that fails the advance criteria. This

means that if a queued TD fails, the queue does not advance, and the ICH2 traverses the QH’s

Queue Head Link Pointer.

In a Depth-first traversal, the top queue element must complete successfully to satisfy the advance

criteria for the queue. If the ICH2 is currently processing a queue, and the advance criteria are met,

and the Vf bit is set, the ICH2 follows the TD’s link pointer to the next schedule work item.

Note that regardless of traversal model, when the advance criteria are met, the successful TD’s link

pointer is written back to the QH’s Queue Element link pointer.

When the ICH2 encounters a QH, it caches the QH internally, and sets internal state to indicate it is

in a Q-context. It needs this state to update the correct QH (for auto advancement) and also to make

the correct decisions on how to traverse the Frame List.

Restricting the advancement of queues to advancement criteria implements a guaranteed data

delivery stream.

A queue is never advanced on an error completion status (even in the event the error count was

exhausted).

Table 5-65 lists the general queue advance criteria, which are based on the execution status of the

TD at the "Top" of a currently "active" queue.

Table 5-65. Queue Advance Criteria

Function-to-Host (IN)

NULL Error/NAK

Advance Q Retry Q Element

Host-to-Function (OUT)

Non-NULL

NULL

Error/NAK

Retry Q Element

Advance Q

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5-117

Functional Description

Table 5-66 is a decision table illustrating the valid combinations of link pointer bits and the valid

actions taken when advancement criteria for a queued transfer descriptor are met. The column

headings for the link pointer fields are encoded, based on the following list:

QHLP

QELP

TDLP

Legends:

QH.LP = Queue Head Link Pointer (or Horizontal Link Pointer)

QE.LP = Queue Element Link Pointer (or Vertical Link Pointer)

TD.LP = TD Link Pointer

QE.Q = Q bit in QE

QE.T = T bit in QE

TD. Vf = Vf bit in TD

TD.Q = Q bit in TD

TD. T = T bit in TD

QH.Q = Q bit in QH

QH.T = T bit in QH

Table 5-66. USB Schedule List Traversal Decision Table

QH.Q QH.T QE.Q QE.T TD.Vf TD.Q

TD.T

Description

Context

•

Not in Queue - execute TD.

Use TD.LP to get next TD

•

Not in Queue - execute TD. End of

Frame

•

Not in Queue - execute TD.

Use TD.LP to get next (QH+QE).

Set Q Context to 1.

•

In Queue. Use QE.LP to get TD.

Execute TD. Update QE.LP with

TD.LP.

•

Use QH.LP to get next TD.

•

In Queue. Use QE.LP to get TD.

Execute TD. Update QE.LP with

TD.LP.

•

Use TD.LP to get next TD.

•

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with

TD.LP.

•

Use TD.LP to get next (QH+QE).

•

In Queue. Empty queue.

Use QH.LP to get next TD

•

In Queue. Use QE.LP to get

(QH+QE)

•

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with

TD.LP.

•

End of Frame

In Queue. Empty queue. End of

Frame

5-118

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-66. USB Schedule List Traversal Decision Table (Continued)

QH.Q QH.T QE.Q QE.T TD.Vf TD.Q

TD.T

Description

Context

•

In Queue. Use QE.LP to get TD.

execute TD. Update QE.LP with

TD.LP.

•

Use QH.LP to get next (QH+QE).

•

In Queue. Empty queue.

Use QH.LP to get next (QH+QE)

5.16.3

Data Encoding and Bit Stuffing

The USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting packets.

In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in

level. A string of zeros causes the NRZI data to toggle each bit time. A string of ones causes long

periods with no transitions in the data. To ensure adequate signal transitions, bit stuffing is

employed by the transmitting device when sending a packet on the USB. A 0 is inserted after every

six consecutive 1s in the data stream before the data is NRZI encoded to force a transition in the

NRZI data stream. This gives the receiver logic a data transition at least once every seven bit times

to guarantee the data and clock lock. A waveform of the data encoding is shown in Figure 5-18.

Figure 5-18. USB Data Encoding

CLOCK

Data

Bit Stuffed Data

NRZI Data

Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire transmission. The

data “one” that ends the Sync Pattern is counted as the first one in a sequence. Bit stuffing is always

enforced, without exception. If required by the bit stuffing rules, a zero bit will be inserted even if

it is the last bit before the end-of-packet (EOP) signal.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-119

Functional Description

5.16.4

Bus Protocol

5.16.4.1

Bit Ordering

Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb, through to the

most significant bit (MSb) last.

5.16.4.2

5.16.4.3

SYNC Field

All packets begin with a synchronization (SYNC) field, which is a coded sequence that generates a

maximum edge transition density. The SYNC field appears on the bus as IDLE followed by the

binary string “KJKJKJKK,” in its NRZI encoding. It is used by the input circuitry to align

incoming data with the local clock and is defined to be eight bits in length. SYNC serves only as a

synchronization mechanism and is not shown in the following packet diagrams. The last two bits in

the SYNC field are a marker that is used to identify the first bit of the PID. All subsequent bits in

the packet must be indexed from this point.

Packet Field Formats

Field formats for the token, data, and handshake packets are described in the following section. The

effects of NRZI coding and bit stuffing have been removed for the sake of clarity. All packets have

distinct start and end of packet delimiters.

Table 5-67. PID Format

Bit

Data Sent

Bit

Data Sent

PID 0

PID 1

PID 2

PID 3

NOT(PID 0)

NOT(PID 1)

NOT(PID 2)

NOT(PID 3)

Packet Identifier Field

A packet identifier (PID) immediately follows the SYNC field of every USB packet. A PID

consists of a four bit packet type field followed by a four-bit check field as shown in Table 5-67.

The PID indicates the type of packet and, by inference, the format of the packet and the type of

error detection applied to the packet. The four-bit check field of the PID insures reliable decoding

of the PID so that the remainder of the packet is interpreted correctly. The PID check field is

generated by performing a ones complement of the packet type field.

Any PID received with a failed check field or which decodes to a non-defined value is assumed to

be corrupted and the remainder of the packet is assumed to be corrupted and is ignored by the

receiver. PID types, codes, and descriptions are listed in Table 5-68.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-68. PID Types

PID Type

PID Name

PID[3:0]

Description

Token

OUT

b0001

b1001

b0101

Address + endpoint number in host -> function transaction

Address + endpoint number in function -> host transaction

Start of frame marker and frame number

SOF

Address + endpoint number in host -> function transaction

for setup to a control endpoint

SETUP

b1101

Data

DATA0

DATA1

ACK

b0011

b1011

b0010

Data packet PID even

Data packet PID odd

Handshake

Receiver accepts error free data packet

Rx device cannot accept data or Tx device cannot send

data

NAK

STALL

PRE

b1010

b1110

b1100

Endpoint is stalled

Host-issued preamble. Enables downstream bus traffic to

low speed devices.

Special

PIDs are divided into four coding groups: token, data, handshake, and special, with the first two

transmitted PID bits (PID[1:0]) indicating which group. This accounts for the distribution of PID

codes.

5.16.4.4

Address Fields

Function endpoints are addressed using two fields: the function address field and the endpoint

field.

Table 5-69. Address Field

Bit

Data Sent

Bit

Data Sent

ADDR 0

ADDR 1

ADDR 2

ADDR 3

ADDR 4

ADDR 5

ADDR 6

Address Field

The function address (ADDR) field specifies the function, via its address, that is either the source

or destination of a data packet, depending on the value of the token PID. As shown in Table 5-69, a

total of 128 addresses are specified as ADDR[6:0]. The ADDR field is specified for IN, SETUP,

and OUT tokens.

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Functional Description

Endpoint Field

An additional four-bit endpoint (ENDP) field, shown in Table 5-70, permits more flexible

addressing of functions in which more than one sub-channel is required. Endpoint numbers are

function specific. The endpoint field is defined for IN, SETUP, and OUT token PIDs only.

Table 5-70. Endpoint Field

Bit

Data Sent

ENDP 0

ENDP 1

ENDP 2

ENDP 3

5.16.4.5

Frame Number Field

The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The

frame number field rolls over upon reaching its maximum value of x7FFh and is sent only for SOF

tokens at the start of each frame.

5.16.4.6

5.16.4.7

Data Field

The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits

within each byte are shifted out LSB first.

Cyclic Redundancy Check (CRC)

CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields

are considered to be protected fields. The PID is not included in the CRC check of a packet

containing CRC. All CRCs are generated over their respective fields in the transmitter before bit

stuffing is performed. Similarly, CRCs are decoded in the receiver after stuffed bits have been

removed. Token and data packet CRCs provide 100% coverage for all single and double bit errors.

A failed CRC is considered to indicate that one or more of the protected fields is corrupted and

causes the receiver to ignore those fields, and, in most cases, the entire packet.

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Functional Description

5.16.5

Packet Formats

5.16.5.1

Token Packets

Table 5-71 shows the field formats for a token packet. A token consists of a PID, specifying either

IN, OUT, or SETUP packet type, and ADDR and ENDP fields. For OUT and SETUP transactions,

the address and endpoint fields uniquely identify the endpoint that will receive the subsequent data

packet. For IN transactions, these fields uniquely identify which endpoint should transmit a data

packet. Only the ICH2 can issue token packets. IN PIDs define a data transaction from a function

to the ICH2. OUT and SETUP PIDs define data transactions from the ICH2 to a function.

Token packets have a five-bit CRC that covers the address and endpoint fields as shown above. The

CRC does not cover the PID, which has its own check field. Token and SOF packets are delimited

by an EOP after three bytes of packet field data. If a packet decodes as an otherwise valid token or

SOF but does not terminate with an EOP after three bytes, it must be considered invalid and

ignored by the receiver.

Table 5-71. Token Format

Packet

Width

PID

8 bits

7 bits

4 bits

5 bits

ADDR

ENDP

CRC5

5.16.5.2

Start of Frame Packets

Table 5-72 shows a start of frame (SOF) packet. SOF packets are issued by the host at a nominal

rate of once every 1.00 ms. SOF packets consist of a PID indicating packet type followed by an 11-

bit frame number field.

The SOF token comprises the token-only transaction that distributes a start of frame marker and

accompanying frame number at precisely timed intervals corresponding to the start of each frame.

All full speed functions, including hubs, must receive and decode the SOF packet. The SOF token

does not cause any receiving function to generate a return packet; therefore, SOF delivery to any

given function cannot be guaranteed. The SOF packet delivers two pieces of timing information. A

function is informed that a start of frame has occurred when it detects the SOF PID. Frame timing

sensitive functions, that do not need to keep track of frame number, need only decode the SOF PID;

they can ignore the frame number and its CRC. If a function needs to track frame number, it must

comprehend both the PID and the time stamp.

Table 5-72. SOF Packet

Packet

Width

PID

Frame Number

CRC5

8 bits

11 bits

5 bits

82801BA ICH2 and 82801BAM ICH2-M Datasheet

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Functional Description

5.16.5.3

Data Packets

A data packet consists of a PID, a data field, and a CRC as shown in Table 5-73. There are two

types of data packets identified by differing PIDs: DATA0 and DATA1. Two data packet PIDs are

defined to support data toggle synchronization.

Data must always be sent in integral numbers of bytes. The data CRC is computed over only the

data field in the packet and does not include the PID, which has its own check field.

Table 5-73. Data Packet Format

Packet

Width

PID

8 bits

0–1023 bytes

16 bits

DATA

CRC16

5.16.5.4

Handshake Packets

Handshake packets consist of only a PID. Handshake packets are used to report the status of a data

transaction and can return values indicating successful reception of data, flow control, and stall

conditions. Only transaction types that support flow control can return handshakes. Handshakes are

always returned in the handshake phase of a transaction and may be returned, instead of data, in the

data phase. Handshake packets are delimited by an EOP after one byte of packet field. If a packet is

decoded as an otherwise valid handshake but does not terminate with an EOP after one byte, it

must be considered invalid and ignored by the receiver.

There are three types of handshake packets:

• ACK indicates that the data packet was received without bit stuff or CRC errors over the data

field and that the data PID was received correctly. An ACK handshake is applicable only in

transactions in which data has been transmitted and where a handshake is expected. ACK can

be returned by the host for IN transactions and by a function for OUT transactions.

• NAK indicates that a function was unable to accept data from the host (OUT) or that a

function has no data to transmit to the host (IN). NAK can only be returned by functions in the

data phase of IN transactions or the handshake phase of OUT transactions. The host can never

issue a NAK. NAK is used for flow control purposes to indicate that a function is temporarily

unable to transmit or receive data, but will eventually be able to do so without need of host

intervention. NAK is also used by interrupt endpoints to indicate that no interrupt is pending.

• STALL is returned by a function in response to an IN token or after the data phase of an OUT.

STALL indicates that a function is unable to transmit or receive data, and that the condition

requires host intervention to remove the stall. Once a function’s endpoint is stalled, the

function must continue returning STALL until the condition causing the stall has been cleared

through host intervention. The host is not permitted to return a STALL under any condition.

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Functional Description

5.16.5.5

Handshake Responses

IN Transaction

A function may respond to an IN transaction with a STALL or NAK. If the token received was

corrupted, the function issues no response. If the function can transmit data, it issues the data

packet. The ICH2, as the USB host, can return only one type of handshake on an IN transaction, an

ACK. If it receives a corrupted data or cannot accept data due to a condition such as an internal

buffer overrun, it discards the data and issues no response.

OUT Transaction

A function may respond to an OUT transaction with a STALL, ACK, or NAK. If the transaction

contained corrupted data, it will issue no response.

SETUP Transaction

Setup defines a special type of host to function data transaction which permits the host to initialize

an endpoint’s synchronization bits to those of the host. Upon receiving a Setup transaction, a

function must accept the data. Setup transactions cannot be STALLed or NAKed and the receiving

function must accept the Setup transfer’s data. If a non-control endpoint receives a SETUP PID, it

must ignore the transaction and return no response.

5.16.6

USB Interrupts

There are two general groups of USB interrupt sources, those resulting from execution of

transactions in the schedule, and those resulting from an ICH2 operation error. All transaction-

based sources can be masked by software through the ICH2’s Interrupt Enable register.

Additionally, individual transfer descriptors can be marked to generate an interrupt on completion.

When the ICH2 drives an interrupt for USB, it drives the PIRQD# pin active for interrupts

occurring due to ports 0 and 1 until all sources of the interrupt are cleared.

5.16.6.1

Transaction Based Interrupts

These interrupts are not signaled until after the status for the last complete transaction in the frame

has been written back to host memory. This guarantees that software can safely process through

(Frame List Current Index -1) when it is servicing an interrupt.

CRC Error / Time-out

A CRC/Time-out error occurs when a packet transmitted from the ICH2 to a USB device or a

packet transmitted from a USB device to the ICH2 generates a CRC error. The ICH2 is informed of

this event by a time-out from the USB device or by the ICH2’s CRC checker generating an error on

reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not

respond to a transaction phase within 19 bit times of an EOP. Either of these conditions will cause

the C_ERR field of the TD to decrement. When the C_ERR field decrements to zero, the following

occurs:

• The Active bit in the TD is cleared

• The Stalled bit in the TD is set

• The CRC/Time-out bit in the TD is set.

• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.

If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt is

signaled to the system.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-125

Functional Description

Interrupt on Completion

Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The

completion of the transaction associated with that block causes the USB Interrupt bit in the HC

Status Register to be set at the end of the frame in which the transfer completed. When a TD is

encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of

the frame if the active bit in the TD is set to 0 (even if it was set to zero when initially read).

If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware

interrupt is signaled to the system. The USB Interrupt bit in the HC Status register is set either

when the TD completes successfully or because of errors. If the completion is because of errors,

the USB Error bit in the HC Status register is also set.

Short Packet Detect

A transfer set is a collection of data which requires more than 1 USB transaction to completely

move the data across the USB. An example might be a large print file which requires numerous

TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than

the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion

of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in

a TD indicates to the HC to set the USB Interrupt bit in the HC Status register at the end of the

frame in which this event occurs. This feature streamlines the processing of input on these transfer

types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware

interrupt is signaled to the system at the end of the frame where the event occurred.

Serial Bus Babble

When a device transmits on the USB for a time greater than its assigned Max Length, it is said to

be babbling. Since isochrony can be destroyed by a babbling device, this error results in the Active

bit in the TD being cleared to 0 and the Stalled and Babble bits being set to one. The C_ERR field

is not decremented for a babble. The USB Error Interrupt bit in the HC Status register is set to 1 at

the end of the frame. A hardware interrupt is signaled to the system.

If an EOF babble was caused by the ICH2 (due to incorrect schedule for instance), the ICH2 forces

a bit stuff error followed by an EOP and the start of the next frame.

Stalled

This event indicates that a device/endpoint returned a STALL handshake during a transaction or

that the transaction ended in an error condition. The TDs Stalled bit is set and the Active bit is

cleared. Reception of a STALL does not decrement the error counter. A hardware interrupt is

signaled to the system.

Data Buffer Error

This event indicates that an overrun of incoming data or a under-run of outgoing data has occurred

for this transaction. This would generally be caused by the ICH2 not being able to access required

data buffers in memory within necessary latency requirements. Either of these conditions causes

the C_ERR field of the TD to be decremented.

When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is set, the USB

Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a hardware

interrupt is signaled to the system.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Bit Stuff Error

A bit stuff error results from the detection of a sequence of more that 6 ones in a row within the

incoming data stream. This will cause the C_ERR field of the TD to be decremented. When the

C_ERR field decrements to zero, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1,

the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a

hardware interrupt is signaled to the system.

5.16.6.2

Non-Transaction Based Interrupts

If an ICH2 process error or system error occur, the ICH2 halts and immediately issues a hardware

interrupt to the system.

Resume Received

This event indicates that the ICH2 received a RESUME signal from a device on the USB bus

during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware

interrupt will be signaled to the system allowing the USB to be brought out of the suspend state and

returned to normal operation.

ICH2 Process Error

The HC monitors certain critical fields during operation to ensure that it does not process corrupted

data structures. These include checking for a valid PID and verifying that the MaxLength field is

less than 1280. If it detects a condition that would indicate that it is processing corrupted data

structures, it immediately halts processing, sets the HC Process Error bit in the HC Status Register

and signals a hardware interrupt to the system.

This interrupt cannot be disabled through the Interrupt Enable Register.

Host System Error

The ICH2 sets this bit to 1 when a PCI Parity error, PCI Master Abort, or PCI Target Abort occurs.

When this error occurs, the ICH2 clears the Run/Stop bit in the Command Register to prevent

further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt

Enable Register.

5.16.7

USB Power Management

The Host Controller can be put into a suspended state and its power can be removed. This requires

that certain bits of information are retained in the resume power plane of the ICH2 so that a device

on a port may wake the system. Such a device may be a fax-modem, that wakes up the machine to

receive a fax or takes a voice message. The settings of the following bits in I/O space is maintained

when the ICH2 enters the S3, S4 or S5 states.

Table 5-74. Bits maintained in low power states

Command

Offset

Bit

Description

00h

02h

Enter Global Suspend Mode (EGSM)

Resume Detect

Status

Port Status and Control

10h & 12h

Port Enabled/Disabled

Resume Detect

Low Speed Device Attached

Suspend

When the ICH2 detects a resume event on any of its ports, it sets the corresponding USB_STS bit

in ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI is

generated.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-127

Functional Description

5.16.8

USB Legacy Keyboard Operation

When a USB keyboard is plugged into the system and a standard keyboard is not, the system may

not boot and DOS legacy software will not run; this is because the keyboard is not identified. The

ICH2 implements a series of trapping operations which snoop accesses that go to the keyboard

controller and put the expected data from the USB keyboard into the keyboard controller.

Note: The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the

LPC bus.

This legacy operation is performed through SMM space.

Figure 5-19 shows the Enable and Status path. The latched SMI source (60R, 60W, 64R, 64W) is

available in the Status Register. Because the enable is after the latch, it is possible to check for

other events that didn't necessarily cause an SMI. It is the software's responsibility to logically

AND the value with the appropriate enable bits.

Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes

active) to ensure that the processor does not complete the cycle before the SMI is observed. This

method is used on MPIIX and has been validated.

The logic will also need to block the accesses to the 8042. If there is an external 8042, this is

accomplished by not activating the 8042 CS. This is done by logically ANDing the 4 enables

(60R, 60W, 64R, 64W) with the 4 types of accesses to determine if the 8042CS should go active.

An additional term is required for the “Pass-through” case. The state table for the diagram is shown

in Table 5-75.

Figure 5-19. USB Legacy Keyboard Flow Diagram

To Individual

"Caused By"

KBC Accesses

60 READ

"Bits"

Clear SMI_60_R

AND

PCI Config

Comb.

Decoder

Read, Write

EN_SMI_ON_60R

SMI

Same for 60W, 64R, 64W

EN_PIRQD#

AND

To PIRQD#

To "Caused By" Bit

USB_IRQ

Clear USB_IRQ

AND

EN_SMI_ON_IRQ

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Functional Description

Table 5-75. USB Legacy Keyboard State Transitions

Current State

Action

Data Value Next State

Comment

Standard D1 command. Cycle passed through to

8042. SMI# doesn't go active. PSTATE goes to 1.

IDLE

64h / Write

D1h

Not D1h

N/A

GateState1

IDLE

Bit 3 in configuration Register determines if cycle

passed through to 8042 and if SMI# generated.

IDLE

64h / Write

64h / Read

60h / Write

60h / Read

Bit 2 in configuration Register determines if cycle

passed through to 8042 and if SMI# generated.

IDLE

Bit 1 in configuration Register determines if cycle

passed through to 8042 and if SMI# generated.

Don't Care

N/A

IDLE

Bit 0 in configuration Register determines if cycle

passed through to 8042 and if SMI# generated.

IDLE

Cycle passed through to 8042, even if trap

enabled in Bit 1 in configuration Register. No

GateState1

60h / Write

XXh

GateState2 SMI# generated. PSTATE remains 1. If data

value is not DFh or DDh then the 8042 may

chose to ignore it.

Cycle passed through to 8042, even if trap

enabled via Bit 3 in configuration Register. No

GateState1 SMI# generated. PSTATE remains 1. Stay in

GateState1 because this is part of the double-

trigger sequence.

GateState1

64h / Write

60h / Read

D1h

Not D1h

N/A

Bit 3 in configuration space determines if cycle

passed through to 8042 and if SMI# generated.

PSTATE goes to 0. If Bit 7 in configuration

ILDE

This is an invalid sequence. Bit 0 in configuration

IDLE

8042 and if SMI# generated. PSTATE goes to 0.

If Bit 7 in configuration Register is set, then SMI#

should be generated.

Just stay in same state. Generate an SMI# if

GateState1

GateState2

64h / Read

64 / Write

N/A

FFh

GateState1 enabled in Bit 2 of configuration Register.

PSTATE remains 1.

Standard end of sequence. Cycle passed through

IDLE

to 8042. PSTATE goes to 0. Bit 7 in configuration

Space determines if SMI# should be generated.

Improper end of sequence. Bit 3 in configuration

8042 and if SMI# generated. PSTATE goes to 0.

If Bit 7 in configuration Register is set, then SMI#

should be generated.

GateState2

64h / Write

64h / Read

60h / Write

Not FFh

N/A

IDLE

Just stay in same state. Generate an SMI# if

GateState2 enabled in Bit 2 of configuration Register.

PSTATE remains 1.

Improper end of sequence. Bit 1 in configuration

8042 and if SMI# generated. PSTATE goes to 0.

If Bit 7 in configuration Register is set, then SMI#

should be generated.

XXh

IDLE

Improper end of sequence. Bit 0 in configuration

8042 and if SMI# generated. PSTATE goes to 0.

If Bit 7 in configuration Register is set, then SMI#

should be generated.

GateState2

60h / Read

N/A

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-129

Functional Description

5.17

SMBus Controller Functional Description (D31:F3)

The ICH2 provides an SMBus Host Controller as well as an SMBus Slave Interface.

The Host Controller provides a mechanism for the processor to initiate communications with

SMBus peripherals (slaves). The ICH2 is also capable of operating in a mode in which it can

communicate with I²C compatible devices.

The Slave Interface allows an external master to read from or write to the ICH2. Write cycles can

be used to cause certain events or pass messages and the read cycles can be used to determine the

state of various status bits. The ICH2’s internal Host Controller cannot access the ICH2’s internal

Slave Interface.

The ICH2 SMBus logic exists in Device 31:Function 3 configuration space and consists of a

transmit data path and host controller. The transmit data path provides the data flow logic needed to

implement the seven different SMBus command protocols and is controlled by the host controller.

The ICH2 SMBus controller logic is clocked by RTC clock.

The programming model of the host controller is combined into two portions: a PCI configuration

portion and a system I/O mapped portion. All static configuration (e.g., the I/O base address) is

done via the PCI configuration space. Real-time programming of the Host interface is done in

system I/O space.

5.17.1

Host Controller

The SMBus Host Controller is used to send commands to other SMBus slave devices. Software

sets up the host controller with an address, command, and, for writes, data, and then tells the

controller to start. When the controller has finished transmitting data on writes, or receiving data on

reads, it will generate an SMI# or interrupt, if enabled.

The host controller supports 7 command protocols of the SMBus interface (see System

Management Bus Specification, Rev 1.0): Quick Command, Send Byte, Receive Byte, Write Byte/

Word, Read Byte/Word, Process Call, and Block Read/Write.

The SMBus Host Controller requires that the various data and command fields be setup for the type

of command to be sent. When software sets the START bit, the SMBus Host Controller performs

the requested transaction and interrupts the processor (or generate an SMI#) when the transaction is

completed. Once a START command has been issued, the values of the “active registers” (Host

Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read

until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any

command, as the SMBus Host Controller will update all registers while completing the new

command.

Using the SMB Host Controller to send commands to the ICH2's SMB slave port is not supported.

5-130

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Functional Description

5.17.1.1

Command Protocols

In all of the following commands, the Host Status Register (offset 00h) is used to determine the

progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the

command completes successfully, the INTR bit is set in the Host Status Register. If the device does

not respond with an acknowledge and the transaction times out, the DEV_ERR bit is set. If

software sets the KILL bit in the Host Control Register while the command is running, the

transaction will stop and the FAILED bit will be set.

Quick Command

When programmed for a Quick Command, the Transmit Slave Address Register is sent. The format

of the protocol is shown in Table 5-76.

Table 5-76. Quick Protocol

Bit

Description

Start Condition

2:8

Slave Address - 7 bits

Read / Write Direction

Acknowledge from slave

Stop

Send Byte / Receive Byte

For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent

For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is

stored in the DATA0 register.

The Receive Byte is similar to a Send Byte; the only difference is the direction of data transfer. The

format of the protocol is shown in Table 5-77.

Table 5-77. Send / Receive Byte Protocol

Send Byte Protocol

Description

Receive Byte Protocol

Description

Bit

2:8

Start

2:8

Start

Slave Address - 7 bits

Write

Slave Address - 7 bits

Read

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Stop

Acknowledge from slave

Data byte from slave

NOT Acknowledge

Stop

11:18

Write Byte/Word

The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data

to be written. When programmed for a write byte/word command, the Transmit Slave Address,

Device Command and Data0 Registers are sent. In addition, the Data1 Register is sent on a write

word command. The format of the protocol is shown in Table 5-78.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-131

Functional Description

Table 5-78. Write Byte/Word Protocol

Write Byte Protocol

Write Word Protocol

Description

Bit

Description

Bit

2:8

Start

2:8

Start

Slave Address - 7 bits

Write

Slave Address - 7 bits

Write

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Data Byte - 8 bits

Acknowledge from Slave

Stop

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Data Byte Low - 8 bits

Acknowledge from Slave

Data Byte High - 8 bits

Acknowledge from slave

Stop

11:18

20:27

29:36

Read Byte/Word

Reading data is slightly more complicated than writing data. First the ICH2 must write a command

to the slave device. Then it must follow that command with a repeated start condition to denote a

read from that device's address. The slave then returns 1 or 2 bytes of data.

When programmed for the read byte/word command, the Transmit Slave Address and Device

Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and

DATA1 registers on the read word. The format of the protocol is shown in Table 5-79.

Table 5-79. Read Byte/Word Protocol

Read Byte Protocol

Description

Read Word Protocol

Description

Bit

2:8

Start

2:8

Start

Slave Address - 7 bits

Write

Slave Address - 7 bits

Write

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Repeated Start

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Repeated Start

11:18

21:27

Slave Address - 7 bits

Read

21:27

Slave Address - 7 bits

Read

Acknowledge from slave

Data from slave - 8 bits

NOT acknowledge

Stop

Acknowledge from slave

Data Byte Low from slave - 8 bits

Acknowledge

30:37

39:46

Data Byte High from slave - 8 bits

NOT acknowledge

Stop

5-132

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Process Call

The process call is so named because a command sends data and waits for the slave to return a

value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but

without a second command or stop condition.

When programmed for the Process Call command, the ICH2 transmits the Transmit Slave Address,

Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the

DATA0 and DATA1 registers. The format of the protocol is shown in Table 5-80.

Note: For process call command, the value written into bit 0 of the Transmit Slave Address Register

(SMB I/O register, offset 04h) needs to be 0.

Table 5-80. Process Call Protocol

Bit

Description

2:8

Start

Slave Address - 7 bits

Write

Acknowledge from Slave

Command code - 8 bits

Acknowledge from slave

Data byte Low - 8 bits

Acknowledge from slave

Data Byte High - 8 bits

Acknowledge from slave

Repeated Start

11:18

20:27

29:36

39:45

Slave Address - 7 bits

Read

Acknowledge from slave

Data Byte Low from slave - 8 bits

Acknowledge

48:55

57:64

Data Byte High from slave - 8 bits

NOT acknowledge

Stop

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-133

Functional Description

Block Read/Write

The Block Write begins with a slave address and a write condition. After the command code, the

ICH2 issues a byte count which describes how many more bytes will follow in the message. If a

slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of

data. The byte count may not be 0.

Note that, unlike the PIIX4, which implements 32-byte buffer for Block Read/Write command, the

ICH2 implements the Block Data Byte register (D31:F3, I/O offset 07h) for Block Read/Write

command.

When programmed for a block write command, the Transmit Slave Address, Host Command, and

Data0 (count) registers are sent. Data is then sent from the Block Data Byte register. After the byte

has been sent, the ICH2 sets the BYTE_DONE_STS bit in the Host Status register. If there are

more bytes to send, software writes the next byte to the Block Data Byte register and also clears the

BYTE_DONE_STS bit. The ICH2 then sends the next byte. When doing a block write, first poll

the BYTE_DONE_STS register until it is set, then write the next byte, then clear the

BYTE_DONE_STS register.

On block read commands, after the byte count is stored in the DATA 0 register, the first data byte

goes in the Block Data Byte Register; the ICH2 will then set the BYTE_DONE_STS bit and

generate an SMI# or interrupt. The SMI# or interrupt handler reads the byte and then clears the

BYTE_DONE_STS bit to allow the next byte to be read into the Block Data Byte register. Note

that after receiving data byte N-1 of the block, the software needs to set the LAST_BYTE bit in the

Host Control Register; this allows the ICH2 to send a NOT ACK (instead of an ACK) after

receiving the last data byte (byte N) of the block.

After each byte of a block message the ICH2 sets the BYTE_DONE_STS bit and generates an

interrupt or SMI#. Software clears the BYTE_DONE_STS bit before the next transfer occurs.

When the interrupt handler clears the BYTE_DONE_STS bit after the last byte has been

transferred, the ICH2 sets the INTR bit and generates another interrupt to signal the end of the

block transfer. Thus, for a block message of n bytes, the ICH2 generates n+1 interrupts. The

interrupt handler needs to be implemented to handle all of these interrupts

The format of the Block Read/Write protocol is shown in Table 5-81.

Note: For Block Write, if the I²C_EN bit is set, the format of the command changes slightly. The ICH2

still sends the number of bytes indicated in the DATA0 register. However, it does not send the

contents of the Data 0 register as part of the message.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-81. Block Read/Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

Description

Bit

2:8

Start

2:8

Start

Slave Address - 7 bits

Write

Slave Address - 7 bits

Write

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Byte Count - 8 bits

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

11:18

20:27

Repeated Start

(Skip this step if I C_En bit set)

Acknowledge from Slave

21:27

Slave Address - 7 bits

(Skip this step if I2C_EN bit set)

29:36

Data Byte 1 - 8 bits

Read

Acknowledge from Slave

Data Byte 2–8 bits

Acknowledge from slave

Byte Count from slave - 8 bits

Acknowledge

38:45

30:37

Acknowledge from slave

Data Bytes / Slave

Acknowledges...

...

39:46

Data Byte 1 from slave - 8 bits

...

Data Byte N - 8 bits

Acknowledge from Slave

Stop

48:55

Acknowledge

Data Byte 2 from slave - 8 bits

Acknowledge

...

Data Bytes from slave/Acknowledge

Data Byte N from slave - 8 bits

NOT Acknowledge

...

Stop

I²C Read

This command allows the ICH2 to perform block reads to certain I²C devices (e.g., serial

E²PROMs). The SMBus Block Read sends both the 7-bit address, as well as the Command field.

This command field could be used as the extended 10-bit address for accessing I²C devices that use

10-bit addressing.

However, this does not allow access to devices using the I²C “Combined Format” that has data

bytes after the address. Typically, these data bytes correspond to an offset (address) within the

serial memory chips.

Note: This new command is supported independent of the setting of the I²C_EN bit.

For I²C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB

I/O register, offset 04h) needs to be 0. The format that is used for the new command is shown in

Table 5-82:

82801BA ICH2 and 82801BAM ICH2-M Datasheet

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Functional Description

Table 5-82. I²C Block Read

Bit

Description

2:8

Start

Slave Address - 7 bits

Write

Acknowledge from slave

Command code - 8 bits

Acknowledge from slave

Send DATA0 register

Acknowledge from slave

Send DATA1 register

Acknowledge from slave

Repeated start

11:18

20:27

29:36

39:45

Slave Address - 7 bits

Read

Acknowledge from slave

Data byte from slave

Acknowledge

48:55

57:64

Data byte 2 from slave - 8 bits

Acknowledge

Data bytes from slave / Acknowledge

Data byte N from slave - 8 bits

NOT Acknowledge

Stop

The ICH2 continues reading data from the peripheral until the NAK is received.

5.17.1.2

5.17.1.3

5-136

I C Behavior

When the I²C_EN bit is set, the ICH2 SMBus logic is instead set to communicate with I²C devices.

This forces the following changes:

1. The Process Call command will skip the Command code (and its associated acknowledge)

2. The Block Write command will skip sending the Byte Count (DATA0)

In addition, the ICH2 supports the new I²C Read command. This is independent of the I²C_EN bit.

Heartbeat for Use With the External LAN Controller

This method allows the ICH2 to send messages to an external LAN Controller when the processor

is otherwise unable to do so. It uses the SMLINK I/F between the ICH2 and the external LAN

Controller. The actual Heartbeat message is a Block Write. Only 8 bytes are sent.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.17.2

Bus Arbitration

Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low

to signal a start condition. The ICH2 continuously monitors the SMBDATA line. When the ICH2 is

attempting to drive the bus to a 1 by letting go of the SMBDATA line and it samples SMBDATA

low, then some other master is driving the bus and the ICH2 stops transferring data.

If the ICH2 sees that it has lost arbitration, the condition is called a collision. The ICH2 sets the

BUS_ERR bit in the Host Status Register, and, if enabled, generates an interrupt or SMI#. The

processor is responsible for restarting the transaction.

When the ICH2 is a SMBus master, it drives the clock. When the ICH2 is sending address or

command as an SMBus master or data bytes as a master on writes, it drives data relative to the

clock it is also driving. It does not start toggling the clock until the start or stop condition meets

proper setup and hold time. The ICH2 also guarantees minimum time between SMBus transactions

as a master.

The ICH2 supports the same arbitration protocol for both the SMBus and the System Management

(SMLINK) interfaces.

Clock Stretching

Some devices may not be able to handle their clock toggling at the rate that the ICH2, as an SMBus

master, would like. They have the capability of stretching the low time of the clock. When the

ICH2 attempts to release the clock (allowing the clock to go high), the clock will remain low for an

extended period of time.

The ICH2 monitors the SMBus clock line after it releases the bus to determine whether to enable

the counter for the high time of the clock. While the bus is still low, the high time counter must not

be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not

ready to send or receive data.

The ICH2 SMBus Host Controller will never stretch the low period of the clock (SMBCLK). It

always has the data to transfer on writes and it always has a spot for the data on reads.

The SMLINK interface, however, always stretches the low period of the clock, effectively forcing

transfers down to 16 KHz.

Bus Time Out (ICH2 as SMBus Master)

If there is an error in the transaction, such that an SMBus device does not signal an acknowledge or

holds the clock lower than the allowed time-out time, the transaction times out. The ICH2 discards

the cycle and sets the DEV_ERR bit. The time-out minimum is 25 ms. The time-out counter inside

the ICH2 starts after the last bit of data is transferred by the ICH2 and it is waiting for a response.

The 25 ms is a count of 800 RTC clocks.

5.17.3

Interrupts / SMI#

The ICH2 SMBus controller uses PIRQB# as its interrupt pin. However, the system can

alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN

bit.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-137

Functional Description

5.17.4

SMBALERT#

SMBALERT# is multiplexed with GPIO[11]. When enabled and the signal is asserted, the ICH2

can generate an interrupt, an SMI#, or a wake event from S1-S4. To resume using SMBALERT#,

the SMB_SMI_EN bit must be enabled to generate an SMI (see Section 12.1.14, “HOSTC—Host

Configuration Register (SMBUS—D31:F3)” on page 12-5).

Note: As long as SMBALERT# is enabled and asserted, the ICH2 will continue to assert PIRQ[B]# or

SMI# (depending on the state of the SMB_SMI_EN bit). To avoid continuous SMIs or interrupts,

the interrupt or SMI handler should:

1. Disable SMBALERT# by setting GPIO_USE_SEL[11] (GPIOBase + 00h, bit 11)

2. Use the SMBus Host Controller to service the peripheral that is asserting SMBALERT#

(causing the device to deassert the signal)

3. Re-enable SMBALERT# by clearing GPIO_USE_SEL[11].

5.17.5

SMBus Slave Interface

The ICH2’s SMBus Slave interface is accessed via the SMLINK[1:0] signals. The slave interface

allows the ICH2 to decode cycles and allows an external microcontroller to perform specific

actions. Key features and capabilities include:

• Supports decode of two messages type: Write and Read

• Receive Slave Address register: This is the address that the ICH2 decodes. A default value is

provided so that the slave interface can be used without the processor having to program this

• Receive Slave Data register in the SMBus I/O space that includes the data written by the

external microcontroller

• Registers that the external microcontroller can read to get the state of the ICH2. See Table 5-87

• Status bit to indicate that the SMBus logic caused an SMI# due to the reception of a message

that matched the slave address. See Section 9.8.3.14.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Format of Slave Write Cycle

The external master performs Byte Write commands to the ICH2 SMBus Slave I/F. The

“Command” field (bits 11-18) indicate which register is being accessed. The Data field (bits 20-27)

indicate the value that should be written to that register.

The Write Cycle format is shown in Table 5-83. Table 5-84 lists the values associated with the

registers.

Table 5-83. Slave Write Cycle Format

Bits

Description

Start Condition

Driven by

Comment

External Microcontroller

Must match value in Receive Slave Address

2:8

Slave Address - 7 bits

External Microcontroller

Write

ACK

External Microcontroller Always 0

ICH2

This field indicates which register will be

accessed.

11:18 Command

External Microcontroller

See Table 5-84 below for the register

definitions

ACK

ICH2

See Table 5-84 below for the register

definitions

20:27 Register Data

External Microcontroller

ACK

Stop

ICH2

External Microcontroller

Table 5-84. Slave Write Registers

Function

1–3

Command Register. See Table 65 below for legal values written to this register.

Reserved

Data Message Byte 0

Data Message Byte 1

6–7

Reserved

Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be ignored.

Reserved

9–FFh

NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data

byte registers until they have been read by the system processor. The ICH2 overwrites the old value

with any new value received. A race condition is possible where the new value is being written to the

(i.e., unpredictable results in this case).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-139

Functional Description

Table 5-85. Command Types

Command

Type

Description

Reserved

WAKE/SMI#: Wake system if it is not already awake. If the system is already awake, an

SMI# is generated.

Note that the SMB_WAK_STS bit will be set by this command, even if the system is already

awake. The SMI handler should then clear this bit.

Unconditional Powerdown: This command sets the PWRBTNOR_STS bit and has the

same effect as the Powerbutton Override occurring. This functionality depends upon the

BIOS having cleared the PWRBTN_STS bit.

Hard Reset without Cycling: This causes a hard reset of the system (does not include

cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1

set to 1, but bit 3 set to 0.

Hard Reset System: This causes a hard reset of the system (including cycling of the power

supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.

Disable the TCO Messages. This command disables the ICH2 from sending Heartbeat and

Event messages (as described in Section 5.13.2). Once this command has been executed,

Heartbeat and Event message reporting can only be re-enabled by assertion and

deassertion of the RSMRST# signal.

WD RELOAD: Reload watchdog timer.

7–FFh

Reserved

Format of Read Command

The external master performs Byte Read commands to the ICH2 SMBus Slave interface. The

“Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 30:37)

contain the value that should be read from that register. Table 5-86 shows the Read Cycle format.

Table 5-87 shows the register mapping for the data byte.

Table 5-86. Read Cycle Format

Bit

Description

Driven by

Comment

Start

External Microcontroller

Must match value in Receive Slave Address

2:8

Slave Address - 7 bits

External Microcontroller

Write

ACK

External Microcontroller Always 0

ICH2

Indicates which register is being accessed.

See Table 5-87.

11:18 Command code – 8 bits

External Microcontroller

ACK

ICH2

Repeated Start

External Microcontroller

Must match value in Receive Slave Address

21:27 Slave Address - 7 bits

External Microcontroller

Read

ACK

External Microcontroller Always 1

ICH2

Value depends on register being accessed.

See Table 5-87.

30:37 Data Byte

ICH2

NOT ACK

Stop

External Microcontroller

ICH2

5-140

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-87. Data Values for Slave Read Registers

Bits

Description

7:0

Reserved.

System Power State

2:0

000 = S0 001 = S1 010 = Reserved 011 = S3

100 = S4 101 = S5 110 = Reserved 111 = Reserved

7:3

3:0

7:4

5:0

7:6

Reserved

Frequency Strap Register

Reserved

Watchdog Timer current value

Reserved

1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has

probably been opened.

1 = BTI Temperature Event occurred. This bit is set if the ICH2’s THRM# input signal is

active. Need to take after polarity control.

DOA processor status. This bit is 1 to indicate that the processor is dead.

1 = Watchdog timer expired. This bit is set if the ICH2’s TCO timers have timed out.

Reserved.

6:4

Will reflect the state of the ICH2’s GPIO[11].

Unprogrammed FWH bit. This bit will be 1 to indicate that the first BIOS fetch returned

FFh, which indicates that the FWH is probably blank.

7:1

7:0

Reserved

Contents of the Message 1 register. See Section 9.9.10.

Contents of the Message 2 register. See Section 9.9.10.

Contents of the WDSTATUS register. See Section 9.9.11.

Reserved

9–FFh

Behavioral Notes

According to SMBus protocol, Read and Write messages always begin with a

Start bit - Address - Write bit sequence. When the ICH2 detects that the address matches the value

in the Receive Slave Address register, it assumes that the protocol is always followed and ignores

the Write bit (bit 9) and signal an Acknowledge during bit 10 (See Table 5-83 and Table 5-86). In

other words, if a Start - Address - Read occurs (which is illegal for SMBus Read or Write protocol),

and the address matches the ICH2’s Slave Address, the ICH2 will still grab the cycle.

Also according to SMBus protocol, a Read cycle contains a Repeated Start - Address - Read

sequence beginning at bit 20 (See Table 5-86). Once again, if the Address matches the ICH2’s

Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with

the Slave Read cycle.

Note: An external microcontroller must not attempt to access the ICH2’s SMBus Slave logic until at least

1 second after both RTCRST# and RSMRST# are deasserted (high).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-141

Functional Description

5.18

AC’97 Controller Functional Description

(Audio D31:F5, Modem D31:F6)

Note: All references to AC’97 in this document refer to the AC’97 2.1 specification. For further

information on the operation of the AC-link protocol, see the AC’97 specification.

The ICH2 AC ‘97 Controller features include:

• Independent PCI functions for audio and modem.

• Independent bus master logic for Mic input, PCM Audio input (2-channel stereo), PCM audio

output (2, 4 or 6-channel stereo), Modem input and Modem output.

• 16 bit sample resolution

• Multiple sample rates up to 48 KHz

• 16 GPIOs

• Single modem line

• Dual codec configuration with two SDIN pins

Table 5-88 shows a detailed list of features supported by the ICH2 AC’97 digital controller.

Table 5-88. Featured Supported by ICH2

Feature

Description

•

Isochronous low latency bus master memory interface

Scatter/gather support for word-aligned buffers in memory

(all mono or stereo 16-bit data types are supported, no 8-bit data types are supported)

•

Data buffer size in system memory from 3 to 65535 samples per input

Data buffer size in system memory from 0 to 65535 samples per output

Independent PCI audio and modem functions with configuration and IO spaces

AC’97 codec registers are shadowed in system memory via driver (not PCI IO space)

System Interface

AC’97 codec register accesses are serialized via semaphore bit in PCI IO space (new

accesses are not allowed while a prior access is still in progress)

•

Power management via ACPI control methods

Support for audio states: D0, D2, D3hot, D3cold

Support for modem states: D0, D3hot, D3cold

Power

Management

•

SCI event generation for PCI modem function with wake-up from D3cold

Independent codec D3 w/ Link down event, synchronized via two bit semaphore (in

PCI IO Space)

•

Read/write access to audio codec registers 00h-3Ah and vendor registers 5Ah–7Eh

16-bit stereo PCM output, up to 48 kHz (L,R, Center, Sub-woofer, L-rear and R-rear

channels on slots 3,4,6,7,8.9)

•

16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4)

PCI Audio

Function

16-bit mono mic in w/ or w/o mono mix, up to 48 kHz (L,R channel, slots 3,4) (mono

mix supports mono hardware AEC reference for speakerphone)

•

16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6)

(supports speech recognition or stereo hardware AEC ref for speakerphone)

During cold reset AC_RST# is held low until after POST and software deassertion of

AC_RST# (supports passive PC_BEEP to speaker connection during POST)

5-142

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

Table 5-88. Featured Supported by ICH2 (Continued)

Feature

Description

•

Read/write access to modem codec registers 3Ch-58h and vendor registers 5Ah–7Eh

16-bit mono modem line1 output and input, up to 48 kHz (slot 5)

PCI Modem

function

Low latency GPIO[13:11,8:6,4:3,1:0] (GPIO[13:11,8:7,4:3,1:0] for the ICH2-M) via

hardwired update between slot 12 and PCI IO register

•

Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT

SCI event generation on primary or secondary SDIN wake-up signal

•

AC’97 2.1 compliant AC-link interface

Variable sample rate output support via AC’97 SLOTREQ protocol

(slots 3,4,5,6,7,8,9)

•

Variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6)

3.3 V digital operation meets AC’97 2.1 DC switching levels

AC-link

AC-Link IO driver capability meets AC‘97 2.1 dual codec specifications

Codec register status reads must be returned with data in the next AC-link frame, per

AC’97 2.1 specification.

•

Dual codec addressing: All AC’97 codec register accesses are addressable to codec

ID 00 (primary) or codec ID 01 (secondary)

Multiple Codec

Dual codec receive capability via primary and secondary SDIN pins

(primary, secondary SDIN frames are internally validated, synchronized, and OR’d)

Note: Throughout this document, references to D31:F5 indicate that the audio function exists in PCI

Device 31, Function 5. References to D31:F6 indicate that the modem function exists in PCI

Device 31, Function 6.

Figure 5-20. ICH2 Based AC’97 2.1

Audio In (Record)

Audio Out (Playback)

Modem

Mic.

5.18.1

AC-link Overview

The ICH2 is an AC’97 2.1 compliant controller that communicates with companion codecs via a

digital serial link called the AC-link. All digital audio/modem streams and command/status

information is communicated over the AC-link.

The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data

streams, as well as control register accesses, employing a time division multiplexed (TDM)

scheme. The AC-link architecture provides for data transfer through individual frames transmitted

in a serial fashion. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots.

The architecture of the ICH2 AC-link allows a maximum of two codecs to be connected.

Figure 5-21 shows a two codec topology of the AC-link for the ICH2.

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Functional Description

Figure 5-21. AC’97 2.1 Controller-Codec Connection

Digital AC '97 2.1

Controller

AC '97 / AC' 97 2.1 /

AMC '97 2.1

RESET#

SDOUT

SYNC

AC '97 2.1

controller

section of the

ICH2

Primary

Codec

BIT_CLK

SDIN 0

SDIN 1

AC '97 / MC '97 2.1 /

AMC '97 2.1

Secondary

Codec

The AC-link consists of a five signal interface between the controller and codec. Table 5-89

indicates the AC-link signal pins on the ICH2 and their associated power wells.

Table 5-89. AC’97 Signals

Signal Name

Type

Power Well*

Description

AC_RESET#

AC_SYNC

Output

Input

Resume

Core

Master hardware reset

48 KHz fixed rate sample sync

12.288 MHz Serial data clock

Serial output data

AC_BIT_CLK

AC_SDOUT

AC_SDIN 0

AC_SDIN 1

Core

Output

Input

Core

Resume

Serial input data

Input

Serial input data

NOTE: Power well voltage levels are 3.3V

ICH2 core well outputs may be used as strapping options for the ICH2, sampled during system

reset. These signals may have weak pull-ups/put-downs; however, this will not interfere with link

operation. ICH2 inputs integrate weak put-downs to prevent floating traces when a secondary

codec is not attached. When the Shut Off bit in the control register is set, all buffers will be turned

off and the pins will be held in a steady state, based on these pull-ups/put-downs.

BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the necessary

clocking to support the twelve 20 bit time slots. AC-link serial data is transitioned on each rising

edge of BIT_CLK. The receiver of AC-link data samples each serial bit on the falling edge of

BIT_CLK.

Synchronization of all AC-link data transactions is signaled by the AC’97 controller via the

AC_SYNC signal, as shown in Figure 5-22. The primary codec drives the serial bit clock onto the

AC-link, which the AC’97 controller then qualifies with the AC_SYNC signal to construct data

frames. AC_SYNC, fixed at 48 KHz, is derived by dividing down BIT_CLK. AC_SYNC remains

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Functional Description

high for a total duration of 16 BIT_CLKs at the beginning of each frame. The portion of the frame

where AC_SYNC is high is defined as the tag phase. The remainder of the frame where AC_SYNC

is low is defined as the data phase. Each data bit is sampled on the falling edge of BIT_CLK.

Figure 5-22. AC-link Protocol

Tag Phase

Data Phase

20.8uS

(48 KHz)

12.288 MHz

SYNC

81.4 nS

BIT_CLK

SDIN

Codec

Ready

slot(1) slot(2)

slot(12) "0"

"0"

End of previous

Audio Frame

Time Slot "Valid"

Bits

Slot 12

Slot 1

Slot 2

Slot 3

("1" = time slot contains valid PCM

The ICH2 has two SDIN pins allowing a single or dual codec configuration. When two codecs are

connected, the primary and secondary codecs can be connected to either SDIN line, however it is

recommended that the primary codec be attached to SDIN [0]. The ICH2 does not distinguish

between primary and secondary codecs on its SDIN[1:0] pins; however, the registers do distinguish

between SDIN[0] and SDIN[1] for wake events, etc. The primary codec can be an AC (audio

codec), MC (modem codec), or AMC (audio/modem codec) device. The secondary codec can be

an AC, MC, or AMC device.

The MC can be either on the primary or the secondary codec, while the AC can be either on the

primary or the secondary codec, or BOTH the primary or the secondary codec.

The ICH2 does not support optional test modes as outlined in the AC’97 specification.

AC-link Output Frame (SDOUT)

A new audio output frame begins with a low to high transition of AC_SYNC. AC_SYNC is

synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of

BIT_CLK, the codec samples the assertion of AC_SYNC. This falling edge marks the time when

both sides of AC-link are aware of the start of a new frame. On the next rising edge of BIT_CLK,

the ICH2 transitions SDOUT into the first bit position of slot 0, or the valid frame bit. Each new bit

position is presented to the AC-link on a rising edge of BIT_CLK, and subsequently sampled by

the codec on the following falling edge of BIT_CLK. This sequence ensures that data transitions

and subsequent sample points for both incoming and outgoing data streams are time aligned.

The output frame data phase corresponds to the multiplexed bundles of all digital output data

targeting codec DAC inputs and control registers. Each output frame supports up to twelve

outgoing data time slots. The ICH2 generates 16 bit samples and, in compliance with the AC’97

specification, pads the 4 least significant bits of valid slots with zeros.

The output data stream is sent with the most significant bit first and all invalid slots are stuffed with

0s. When mono audio sample streams are output from the ICH2, software must ensure both left and

right sample stream time slots are filled with the same data.

Output Slot 0: Tag Phase

Slot 0 is considered the tag phase. The tag phase is a special 16 bit time slot wherein each bit

conveys a valid tag for its corresponding time slot within the current frame. A one in a given bit

position of slot 0 indicates that the corresponding time slot within the current frame has been

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Functional Description

assigned to a data stream and contains valid data. If a slot is tagged invalid with a zero in the

corresponding bit position of slot 0, the ICH2 stuffs the corresponding slot with zeros during that

slot’s active time.

Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire

frame. If the valid frame bit is set to one, this indicates that the current frame contains at least one

slot with valid data. When there is no transaction in progress, the ICH2 deasserts the frame valid

bit. Note that after a write to slot 12, that slot always stays valid; therefore, the frame valid bit

remains set.

The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time

slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to distinguish between

separate codecs on the link.

Using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted

across the link at its fixed 48 KHz frame rate. The codec can control the output sample rate of the

ICH2 using the SLOTREQ bits as described in the AC’97 specification.

Output Slot 1: Command Address Port

The command port is used to control features and monitor status of AC‘97 functions including, but

not limited to, mixer settings and power management.

The control interface architecture supports up to 64 16-bit read/write registers, addressable on even

byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Output frame slot 1

communicates control register address and write/read command information.

In the case of the split codec implementation, accesses to the codecs are differentiated by the driver

using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh for the

secondary codec. The differentiation on the link, however, is done via the codec ID bits. See

Section for further details.

Output Slot 2: Command Data Port

The command data port is used to deliver 16-bit control register write data in the event that the

current command port operation is a write cycle as indicated in slot 1, bit 19. If the current

command port operation is a read then the entire slot time stuffed with 0s by the ICH2. Bits [19:4]

contain the write data. Bits [3:0] are reserved and are stuffed with zeros.

Output Slot 3: PCM Playback Left Channel

Output frame slot 3 is the composite digital audio left playback stream. Typically, this slot is

composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH2

transmits sample streams of 16 bits and stuffs the remaining bits with zeros.

Data in output slots 3 and 4 from the ICH2 should be duplicated by software if there is only a single

channel out.

Output Slot 4: PCM Playback Right Channel

Output frame slot 4 is the composite digital audio right playback stream. Typically, this slot is

composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH2

transmits sample streams of 16 bits and stuffs the remaining bits with zeros.

Data in output slots 3 and 4 from the ICH2 should be duplicated by software if there is only a single

channel out.

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Functional Description

Output Slot 5: Modem Codec

Output frame slot 5 contains modem DAC data. The modem DAC output supports 16 bit

resolution. At boot time, if the modem codec is supported, the AC’97 controller driver determines

the DAC resolution. During normal runtime operation the ICH2 stuffs trailing bit positions within

this time slot with 0s.

Output Slot 6: PCM Playback Center Front Channel

When set up for 6 channel mode, this slot is used for the front center channel. The format is the

same as Slots 3. If not set up for 6 channel mode, this channel will always be stuffed with 0s by

ICH2.

Output Slots 7–8: PCM Playback Left and Right Rear Channels

When set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear Left and Right channels.

The format for these two channels are the same as Slots 3 and 4.

Output Slot 9: Playback SubWoofer Channel

When set for 6 channel mode, this slot is used for the SubWoofer. The format is the same as Slots 3.

If not set up for 6 channel mode, this channel will always be stuffed with 0s by ICH2.

Output Slots 10–11: Reserved

Output frame slots 10–11 are reserved and are always stuffed with 0s by the ICH2 AC’97

controller.

Output Slot 12: I/O Control

The 16 bits of DAA and GPIO control (output) and status (input) have been directly assigned to

bits on slot 12 to minimize latency of access to changing conditions.

The value of the bits in this slot are the values written to the GPIO control register at offset 54h and

D4h (in the case of a secondary codec) in the modem codec I/O space. The following rules govern

the usage of slot 12.

1. Slot 12 is marked invalid by default on coming out of AC-link reset and will remain invalid

until a register write to 54h/D4h.

2. A write to offset 54h/D4h in codec I/O space will cause the write data to be transmitted on slot

12 in the next frame, with slot 12 marked valid, and the address/data information to also be

transmitted on slots 1 and 2.

3. After the first write to offset 54h/D4h, slot 12 remains valid for all following frames. The data

transmitted on slot 12 is the data last written to offset 54h/D4h. Any subsequent write to the

4. Slot 12 will get invalidated after the following events: PCI reset, AC'97 cold reset, warm reset,

and hence a wake from S3, S4, or S5. Slot 12 will remain invalid until the next write to offset

54h/D4h.

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Functional Description

AC-link Input Frame (SDIN)

There are two SDIN lines on the ICH2 for use with a primary and secondary codec. Each SDIN pin

can have a codec attached. Depending upon which codec (AC, MC, or AMC) is attached, various

slots will be valid or invalid. The data slots on the two inputs must be completely orthogonal

(except for the tag slot 0), that is, no two data slots at the same location will be valid on both lines.

This precludes the use of two similar codecs (e.g., two ACs or MCs) which use the same time slots.

The input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC’97 controller. As in the case for the output frame, each AC-link input frame

consists of twelve time slots.

A new audio input frame begins with a low-to-high transition of AC_SYNC. AC_SYNC is

synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of

BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks the time when

both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of

BIT_CLK, the codec transitions SDIN into the first bit position of slot 0 (codec ready bit). Each

new bit position is presented to AC-link on a rising edge of BIT_CLK and subsequently sampled

by the ICH2 on the following falling edge of BIT_CLK. This sequence ensures that data transitions

and subsequent sample points for both incoming and outgoing data streams are time aligned.

SDIN data stream must follow the AC’97 specification and be MSB justified with all non-valid bit

positions (for assigned and/or unassigned time slots) stuffed with zeros. SDIN data is sampled by

the ICH2 on the falling edge of BIT_CLK.

Input Slot 0: Tag Phase

Input slot 0 consists of a codec ready bit (bit 15) and slot valid bits for each subsequent slot in the

frame (bits [14:3]).

The codec ready bit within slot 0 (bit 15) indicates whether the codec on the AC-link is ready for

operation. If the codec ready bit in slot 0 is a zero, the codec is not ready for normal operation.

When the AC-link codec ready bit is a 1, it indicates that the AC-link and codec control and status

registers are in a fully operational state. The codec ready bits are visible through the Global Status

codec to determine exactly which subsections, if any, are ready.

Bits [14:3] in slot 0 indicate which slots of the input stream to the ICH2 contain valid data, just as

in the output frame. The remaining bits in this slot are stuffed with zeros.

Input Slot 1: Status Address Port / Slot Request Bits

The status port is used to monitor status of codec functions including, but not limited to, mixer

settings and power management.

Slot 1 must echo the control register index, for historical reference, for the data to be returned in

slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in slot 0.

For multiple sample rate output, the codec examines its sample rate control registers, the state of its

FIFOs, and the incoming SDOUT tag bits at the beginning of each audio output frame to determine

which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current audio input

frame signal which output slots require data from the controller in the next audio output frame. For

fixed 48 kHz operation the SLOTREQ bits are always set active (low) and a sample is transferred

each frame.

For multiple sample rate input, the tag bit for each input slot indicates whether valid data is present

or not.

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Functional Description

Table 5-90. Input Slot 1 Bit Definitions

Bit

Description

18:12

Reserved (Set to zero)

Control Register Index (Stuffed with zeros if tagged invalid)

Slot 3 Request: PCM Left Channel*

Slot 4 Request: PCM Right Channel*

Slot 5 Request: Modem Line 1

Slot 6 Request: PCM Center Channel*

Slot 7 Request: PCM Left Surround*

Slot 8 Request: PCM Right Surround*

Slot 9 Request: PCM LFE Channel*

Slot Request 10-12: Not Implemented

Reserved (Stuffed with zeros)

4:2

1:0

NOTE: *Slot 3 Request and Slot 4 Request bits must be the same value, i.e. set or cleared in tandem. This is

also true for the Slot 7 and Slot 8 Request bits, as well as the Slot 6 and Slot 9 Request bits.

As shown in Table 5-90, slot 1 delivers codec control register read address and multiple sample rate

slot request flags for all output slots of the controller. When a slot request bit is set by the codec, the

controller returns data in that slot in the next output frame. Slot request bits for slots 3 and 4 are

always set or cleared in tandem (i.e., both are set or cleared).

When set, the input slot 1 tag bit only pertains to Status Address Port data from a previous read.

SLOTREQ bits are always valid independent of the slot 1 tag bit.

Input Slot 2: Status Data Port

The status data port receives 16-bit control register read data.

Bit [19:4]: Control Register Read Data

Bit [3:0]: Reserved.

Input Slot 3: PCM Record Left Channel

Input slot 3 is the left channel input of the codec. ICH2 supports 16 bit sample resolution. Samples

transmitted to the ICH2 must be in left/right channel order.

Input Slot 4: PCM Record Right Channel

Input slot 4 is the right channel input of the codec. The ICH2 supports 16 bit sample resolution.

Samples transmitted to the ICH2 must be in left/right channel order.

Input Slot 5: Modem Line

Input slot 5 contains MSB justified modem data. The ICH2 supports 16 bit sample resolution.

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Functional Description

Input Slot 6: Optional Dedicated Microphone Record Data

Input slot 6 is a third PCM system input channel available for dedicated use by a microphone. This

input channel supplements a true stereo output that enables more precise echo cancellation

algorithm for speakerphone applications. The ICH2 supports 16 bit resolution for slot 6 input.

Input Slots 7-11: Reserved

Input frame slots 7–11 are reserved for future use and should be stuffed with zeros by the codec,

per the AC’97 specification.

Input Slot 12: I/O status

The status of the GPIOs configured as inputs are to be returned on this slot in every frame. The data

returned on the latest frame is accessible to software by reading the register at offset 54h/D4h in the

codec I/O space. Only the 16 MSBs are used to return GPI status. Bit 0 of this slot indicates the

GPI status. When a GPI changes state, this bit gets set for one frame by the codec. This bit can

cause an interrupt to the processor if enabled via the Global Control register.

Reads from 54h/D4h are not transmitted across the link in slot 1 and 2. The data from the most

recent slot 12 is returned on reads from offset 54h/D4h.

In the ICH2 implementation of the AC-link, up to two codecs can be connected to the SDOUT pin.

The following mechanism is used to address the primary and secondary codecs individually.

The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of

slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for

slots 1 and 2 must be set in slot 0, as shown in Table 5-91. Slot 1 is used to transmit the register

address and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should be

valid since only an address is transmitted. For I/O reads, only slot 1 valid bit is set; for I/O writes,

both slots 1 and 2 valid bits are set.

The secondary codec registers are accessed using slots 1 and 2 as described above, however the slot

valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bit 0 (bit 0 of slot 0) is set

to 1. This allows the secondary codec to monitor the slot valid bits of slots 1and 2, and bit 0 of slot

0 to determine if the access is directed to the secondary codec. If the register access is targeted to

the secondary codec, slot 1 and 2 will contain the address and data for the register access. Since

slots 1 and 2 are marked invalid, the primary codec will ignore these accesses.

Table 5-91. Output Tag Slot 0

Primary Access Secondary Access

Bit

Description

Example

Frame Valid

Slot 1 Valid, Command Address bit (Primary codec only)

Slot 2 Valid, Command Data bit (Primary codec only)

Slot 3-12 Valid

12:3

Reserved

1:0

Codec ID (00 reserved for primary; 01 indicate secondary)

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Functional Description

When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any

time. The ICH2 implements write posting on I/O writes across the AC-link (i.e., writes across the

link are indicated as complete before they are actually sent across the link). To prevent a second

I/O write from occurring before the first one is complete, software must monitor the CAS bit in the

Codec Access Semaphore register which indicates that a codec access is pending. Once the CAS

bit is cleared, then another codec access (read or write) can go through. The exception is reads to

offset 54h/D4h (slot 12) which are returned immediately with the most recently received slot 12

data. Writes to offset 54h and D4h (primary and secondary codecs), get transmitted across the

AC-link in slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect

the data being written.

The controller will not issue back-to-back reads. It must get a response to the first read before

issuing a second. In addition, codec reads and writes are only executed once across the link, and are

not repeated.

5.18.2

AC-Link Low Power Mode

The AC-link signals can be placed in a low power mode. When the AC‘97 Powerdown Register

(26h), is programmed to the appropriate value, both BIT_CLK and SDIN will be brought to and

held at a logic low voltage level.

Figure 5-23. AC-link Powerdown Timing

SYNC

BIT_CLK

SDOUT

SDIN

Write to

0x20

Data

PR4

slot 12

prev. frame

TAG

slot 12

prev. frame

Note:

BIT_CLK not to scale

BIT_CLK and SDIN transition low immediately following a write to the Powerdown Register

(26h) with PR4. When the AC‘97 controller driver is at the point where it is ready to program the

AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio

output frame.

The AC‘97 controller also drives AC_SYNC, and SDOUT low after programming AC‘97 to this

low power, halted mode. Once the codec has been instructed to halt BIT_CLK, a special wake up

protocol must be used to bring the AC-link to the active mode since normal output and input

frames can not be communicated in the absence of BIT_CLK. Once in a low power mode, the

ICH2 provides three methods for waking up the AC-link; external wake event, cold reset and warm

reset.

Note: Before entering any low power mode where the link interface to the codec is expected to be

powered down while the rest of the system is awake, the software must set the "Shut Off" bit in the

control register.

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Functional Description

External Wake Event

Codecs can signal the controller to wake the AC-link and wake the system using SDIN. The

minimum SDIN wake up pulse width is 1 us. The rising edge of SDIN[0] or SDIN[1] causes the

ICH2 to sequence through an AC-link warm reset and set the AC97_STS bit in the GPE0_STS

before restarting BIT_CLK as diagrammed in Figure 5-24. The codec that signaled the wake event

must keep its SDIN high until it has sampled AC_SYNC having gone high, and then low.

Figure 5-24. SDIN Wake Signaling

Power Down

Frame

New Audio

Frame

Sleep State

Wake Event

SYNC

BIT_CLK

SDOUT

SDIN

slot 12

Write to

0x20

Data

PR4

TAG

Slot 1

Slot 2

prev. frame

slot 12

Slot 2

prev. frame

The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on

the system’s current power down state. Unless a cold or register reset (a write to the Reset register

in the codec) is performed, wherein the AC‘97 codec registers are initialized to their default values,

registers are required to keep state during all power down modes.

Once powered down, activation of the AC-link via re-assertion of the AC_SYNC signal must not

occur for a minimum of 4 audio frame times following the frame in which the power down was

triggered. When AC-link powers up, it indicates readiness via the codec ready bit.

5.18.3

5.18.4

AC‘97 Cold Reset

A cold reset is achieved by asserting AC_RST# for 1 us. By driving AC_RST# low, BIT_CLK, and

SDOUT will be activated and all codec registers will be initialized to their default power on reset

values. AC_RST# is an asynchronous AC‘97 input to the codec.

AC‘97 Warm Reset

A warm reset re-activates the AC-link without altering the current codec register values. A warm

reset is signaled by driving AC_SYNC high for a minimum of 1 us in the absence of BIT_CLK.

Within normal frames, AC_SYNC is a synchronous AC‘97 input to the codec. However, in the

absence of BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec used in the

generation of a warm reset.

The codec must not respond with the activation of BIT_CLK until AC_SYNC has been sampled

low again by the codec. This will prevent the false detection of a new frame.

Note: On receipt of wake up signalling from the codec, the digital controller will issue an interrupt if

enabled. Software will then have to issue a warm or cold reset to the codec by setting the

appropriate bit in the Global Control Register.

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5.18.5

System Reset

Table 5-92 indicates the states of the link during various system reset and sleep conditions.

Table 5-92. AC-link state during PCIRST#

During

PCIRST#/

After

PCIRST#/

Signal

Power Plane

I/O

S4/S5

Cold

Reset

bit (Hi)

AC_RST#

Resume

Output Low

Low

AC_SDOUT

AC_SYNC

Core

Output Low

Running

Low

Core

Driven by

codec

2,4

BIT_CLK

SDIN[1:0]

Core

Input

Running

Low

Driven by

codec

2,4

Resume

Low

NOTE:

1. ICH2 core well outputs are used as strapping options for the ICH2. They are sampled during system reset.

These signals may have weak pull-ups/put-downs. The ICH2 outputs are driven to the appropriate level prior

to AC_RST# being deasserted, preventing a codec from entering test mode. Straps are tied to the core well

to prevent leakage during a suspend state.

2. The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC’97 Global

Control Register is set to 1. All other times, the pull-down resistor is disabled.

3. AC_RST# will be held low during S3–S5. It cannot be programmed high during a suspend state.

4. BIT_CLK and SDIN[1:0] are driven low by the codecs during normal states. If the codec is powered during

suspend states, it holds these signals low. However, if the codec is not present or not powered in suspend,

external pull-down resistors are required.

The transition of AC_RST# to the deasserted state only occurs under driver control. In the S1sleep

state, the state of the AC_RST# signal is controlled by the AC’97 Cold Reset# bit (bit 1) in the

Global Control register. AC_RST# will be asserted (low) by the ICH2 under the following

conditions:

• RSMRST# (system reset, including the a reset of the resume well and PCIRST#)

• Mechanical power up (causes PCIRST#)

• Write to CF9h hard reset (causes PCIRST#)

• Transition to S3/S4/S5 sleep states (causes PCIRST#)

• Write to AC’97 Cold Reset# bit in the Global Control Register.

Hardware will never deassert AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically.

Only software can deassert the Cold Reset# bit and, hence, the AC_RST# signal. This bit, while it

resides in the core well, remains cleared upon return from S3/S4/S5 sleep states. The AC_RST#

pin remains actively driven from the resume well as indicated.

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Functional Description

5.19

Firmware Hub Interface

This section describes the memory cycle type to be used on the Firmware Hub (FWH) interface.

Below are the various types of cycles that are supported by the product.

Cycle Type

Comment

FWH Memory Read

FWH Memory Write

New chip select and addressing are used.

5.19.1

Field Definitions

START

This one clock field indicates the start of a cycle. It is valid on the last clock that LFRAME# is

sampled low. The two start fields that are used for the cycle are shown in the table below. If the

start field that is sampled is not one of these values, then the cycle attempted is not a FWH Memory

Cycle. It may be a valid memory cycle that the FWH component may wish to decode (i.e., it may

be of the LPC memory cycle variety).

AD[3:0]

Indication

FWH Memory Read

FWH Memory Write

1101

1110

IDSEL (Device Select)

This one clock field is used to indicate which FWH component is being selected. The four bits

transmitted over AD[3:0] during this clock are compared with values strapped onto pins on the

FWH component. If there is a match, the FWH component will continue to decode the cycle to

determine which bytes are requested on a read or which bytes to update on a write. If there is not a

match, the FWH component may discard the rest of the cycle and go into a standby power state.

MSIZE (Memory Size)

The value ‘0000b’ is sent in this field. A value of ‘0000b’ corresponds to a single byte transfer.

Other encodings of this field are reserved for future use.

MADDR (Memory Address)

This is a 7-clock field that provides a 28 bit memory address. This allows for up to 256 MB per

memory device, for a total of a 4 GB addressable space. The address is transferred with the most

significant nibble first.

SYNC

The SYNC protocol is the same as described in the LPC specification.

TAR

The TAR fields are the same as described in the LPC specification. Refer to this specification for

further details.

5-154

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Functional Description

5.19.2

Protocol

The FWH Memory cycles use a sequence of events that start with a START field (LFRAME#

active with appropriate AD[3:0] combination) and end with the data transfer. The following

sections describe the cycles in detail.

Preamble

The initiation of the FWH Memory cycles is shown in Figure 5-25. The FWH Memory transaction

begins with LFRAME# going low and a START field driven on AD[3:0]. For FWH Memory Read

cycles, the START field must be ‘1101b’; for FWH Memory Write cycles, the START field must be

‘1110b’. Following the START field is the IDSEL field. This field acts like a chip select in that it

indicates which device should respond to the current transaction. The next seven clocks are the 28-

bit address from where to begin reading in the selected device. Next, an MSIZE value of 0

indicates the master is requesting a single byte.

Figure 5-25. FWH Memory Cycle Preamble

T10

T11

CLK

FRAME#

AD[3:0]

28 Bit Address

START IDSEL

MSIZE

Read Cycle (Single Byte)

For read cycles, after the pre-amble (described above), the host drives a TAR field to give

ownership of the bus to the FWH. After the second clock of the TAR phase, the target device

assumes the bus and begins driving SYNC values. When it is ready, it drives the low nibble, then

the high nibble of data, followed by a TAR to give control back to the host.

Figure 5-26. Single Byte Read

T10

T11

T12

T13

CLK

FRAME#

AD[3:0]

Preamble

TAR

SYNC

D_Lo

D_Hi

TAR

Figure 5-26 shows a device that requires 3 SYNC clocks to access data. Since the access time can

begin once the address phase has been completed, the two clocks of the TAR phase can be

considered as part of the access time of the part. For example, a device with a 120 ns access time

could assert ‘0101b’ for clocks 1 and 2 of the SYNC phase and ‘0000b’ for the last clock of the

SYNC phase. This would be equivalent to 5 clocks worth of access time if the device started that

access at the conclusion of the Preamble phase. Once SYNC is achieved, the device returns the

data in two clocks and gives ownership of the bus back to the host with a TAR phase.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-155

Functional Description

Write Cycles (Single Byte)

All devices that support FWH memory write cycles must support single byte writes. FWH memory

write cycles use the same preamble as FWH memory read cycles that is described above.

Figure 5-27. Single Byte Write

T10

T11

CLK

FRAME#

AD[3:0]

Preamble

D_Lo

D_Hi

TAR

SYNC

TAR

Figure 5-27 shows an FWH memory write cycle where a single byte is transferred. The master

asserts an MSIZE value of 0. After the address has been transferred, the 2 clock data phase begins.

Following the data phase, bus ownership is transferred to the FWH component with a TAR cycle.

Following the TAR phase, the device must assert a SYNC value of ‘0000b’ (ready) or ‘1010b’

(error) indicating the data has been received. Bus ownership is then given back to the master with

another TAR phase.

FWH Memory Writes only allow one clock for the SYNC phase. The TAR + SYNC + TAR phases

at the end of FWH memory write cycles must be exactly 5 clocks.

Error Reporting

There is no error reporting over the FWH interface for FWH memory cycles. If an error occurs

(e.g., an address out of range or an unsupported memory size), the cycle will continue from the host

unabated. This is because these errors are the result of illegal programming, and there is no

efficient error reporting method that can be done to counter the programming error.

Therefore, the FWH component must not report the error conditions over the FWH interface. It

must only report wait states and the ‘ready’ condition. It may choose to log the error internally to

be debugged, but it must not signal an error through the FWH interface itself

5-156

82801BA ICH2 and 82801BAM ICH2-M Datasheet

The ICH2 contains registers that are located in the processor’s I/O space and memory space and

sets of PCI configuration registers that are located in PCI configuration space. This chapter

describes the ICH2 I/O and memory maps at the register-set level. Register access is also

described. Register-level address maps and Individual register bit descriptions are provided in the

following chapters. The following notations and definitions are used in the register/instruction

description chapters.

Read Only. In some cases, If a register is read only, writes to this register location have

no effect. However, in other cases, two separate registers are located at the same

location where a read accesses one of the registers and a write accesses the other

Write Only. In some cases, If a register is write only, reads to this register location have

no effect. However, in other cases, two separate registers are located at the same

location where a read accesses one of the registers and a write accesses the other

R/W

Read/Write. A register with this attribute can be read and written.

R/WC

Read/Write Clear. A register bit with this attribute can be read and written. However,

a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect.

Default

When ICH2 is reset, it sets its registers to predetermined default states. The default

state represents the minimum functionality feature set required to successfully bring

up the system. Hence, it does not represent the optimal system configuration. It is the

responsibility of the system initialization software to determine configuration,

operating parameters, and optional system features that are applicable, and to program

the ICH2 registers accordingly.

Bold

ICH2. Register bits that are not implemented or are rewired will remain in plain text.

6.1

PCI Devices and Functions

The ICH2 incorporates a variety of PCI functions as shown in Table 6-1. These functions are

divided into three logical devices (B0:D30, B0:D31 and B1:D8). D30 is the hub interface-to-PCI

bridge, D31 contains the PCI-to-LPC Bridge, IDE Controller, USB Controllers, SMBus Controller

and the AC’97 Audio and Model Controller functions. B1:D8 is the integrated LAN Controller.

Note: From a software perspective, the integrated LAN Controller resides on the ICH2’s external PCI bus

(See Section 5.1.2). This is typically Bus 1, but may be assigned a different number depending on

system configuration.

If a particular system platform does not want to support any one of Device 31’s Functions 1–6, they

can individually be disabled. The integrated LAN Controller will be disabled if no Platform LAN

Connect component is detected (See Section 5.2, “LAN Controller (B1:D8:F0)” on page 5-6).

When a function is disabled, it does not appear at all to the software. A disabled function will not

respond to any register reads or writes. This is intended to prevent software from thinking that a

function is present (and reporting it to the end-user).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

6-1

Table 6-1. PCI Devices and Functions

Bus:Device:Function

Function Description

Bus 0:Device 30:Function 0

Bus 0:Device 31:Function 0

Bus 0:Device 31:Function 1

Bus 0:Device 31:Function 2

Bus 0:Device 31:Function 3

Bus 0:Device 31:Function 4

Bus 0:Device 31:Function 5

Bus 0:Device 31:Function 6

Bus 1:Device 8:Function 0

Hub Interface to PCI Bridge

PCI to LPC Bridge

IDE Controller

USB Controller #1

SMBus Controller

USB Controller #2

AC’97 Audio Controller

AC’97 Modem Controller

LAN Controller

NOTES:

1. The PCI to LPC bridge contains registers that control LPC, Power Management, System Management,

GPIO, processor interface, RTC, Interrupts, Timers, DMA.

6.2

PCI Configuration Map

Each PCI function on the ICH2 has a set of PCI configuration registers. The register address map

tables for these register sets are included at the beginning of the chapter for the particular function.

Configuration Space registers are accessed through configuration cycles on the PCI bus by the

Host bridge using configuration mechanism #1 detailed in the PCI 2.1 specification.

Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are

reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on

reserved bits being any particular value. On writes, software must ensure that the values of

reserved bit positions are preserved. That is, the values of reserved bit positions must first be read,

merged with the new values for other bit positions and then written back. Note the software does

not need to perform read, merge, write operation for the configuration address register.

In addition to reserved bits within a register, the configuration space contains reserved locations.

Software should not write to reserved PCI configuration locations in the device-specific region

(above address offset 3Fh).

6.3

I/O Map

The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved. In

some cases they can be disabled. Variable ranges can be moved and can also be disabled.

6-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

6.3.1

Fixed I/O Address Ranges

Table 6-2 shows the fixed I/O decode ranges from the processor perspective. Note that for each I/O

range, there may be a separate behavior for reads and writes. The hub interface cycles that go to

target ranges that are marked as “Reserved” are not decoded by the ICH2; they are passed to PCI. If

a PCI master targets one of the fixed I/O target ranges, it will be positively decoded by the ICH2 in

Medium speed.

Refer to Table A-1 for a complete list of all fixed I/O registers. Address ranges that are not listed or

marked “Reserved” are NOT decoded by the ICH2 (unless assigned to one of the variable ranges).

Table 6-2. Fixed I/O Ranges Decoded by ICH2

I/O Address

Read Target

DMA Controller

Write Target

DMA Controller

Internal Unit

DMA

00h–08h

09h–0Eh

0Fh

RESERVED

DMA Controller

Interrupt Controller

LPC SIO

DMA

DMA Controller

RESERVED

DMA

10h–18h

19h–1Eh

1Fh

DMA

DMA Controller

Interrupt Controller

LPC SIO

DMA

20h–21h

24h–25h

28h–29h

2Ch–2Dh

2Eh–2Fh

30h–31h

34h–35h

38h–39h

3Ch–3Dh

40h–42h

43h

Interrupt

Forwarded to LPC

Interrupt

Interrupt Controller

Timer/Counter

RESERVED

Interrupt Controller

Timer/Counter

Interrupt

PIT (8254)

PIT

Timer/Counter

4E–4F

50h–52h

53h

LPC SIO

Forwarded to LPC

PIT

Timer/Counter

RESERVED

Timer/Counter

PIT

60h

Microcontroller

NMI Controller

Microcontroller

NMI Controller

Microcontroller

NMI Controller

Microcontroller

NMI Controller

Microcontroller

Forwarded to LPC

processor I/F

Forwarded to LPC

processor I/F

Forwarded to LPC

processor I/F

Forwarded to LPC

processor I/F

RTC

61h

NMI Controller

62h

Microcontroller

63h

NMI Controller

64h

Microcontroller

65h

NMI Controller

66h

Microcontroller

67h

NMI Controller

70h

RESERVED

NMI and RTC Controller

RTC Controller

NMI and RTC Controller

RTC Controller

NMI and RTC Controller

71h

RTC Controller

RTC

72h

RTC

73h

RTC

74h

RTC

82801BA ICH2 and 82801BAM ICH2-M Datasheet

6-3

Table 6-2. Fixed I/O Ranges Decoded by ICH2 (Continued)

I/O Address

75h

Read Target

RTC Controller

Write Target

RTC Controller

Internal Unit

RTC

76h

RTC Controller

NMI and RTC Controller

RTC Controller

RTC

77h

RTC Controller

RTC

80h

DMA Controller

Reset Generator

DMA Controller

Interrupt Controller

Power Management

Interrupt Controller

DMA Controller

RESERVED

DMA Controller and LPC or PCI

DMA Controller

DMA

81h–83h

84h–86h

87h

DMA

DMA Controller and LPC or PCI

DMA Controller

DMA

88h

DMA Controller and LPC or PCI

DMA Controller

DMA

89h–8Bh

8Ch–8Eh

08Fh

DMA

DMA Controller and LPC or PCI

DMA Controller

DMA

90h–91h

92h

DMA Controller

DMA

Reset Generator

processor I/F

DMA

93h–9Fh

A0h–A1h

A4h–A5h

A8h–A9h

ACh–ADh

B0h–B1h

B2h–B3h

B4h–B5h

B8h–B9h

BCh–BDh

C0h–D1h

D2h–DDh

DEh–DFh

DMA Controller

Interrupt Controller

Power Management

Interrupt Controller

DMA Controller

Interrupt

Power Management

Interrupt

DMA

DMA Controller

DMA

DMA Controller

DMA

FERR#/IGNNE# / Interrupt

Controller

F0h

See Note 3

processor interface

170h–177h

1F0h–1F7h

376h

IDE Controller

Forwarded to IDE

Interrupt

IDE Controller

3F6h

IDE Controller

4D0h–4D1h

CF9h

Interrupt Controller

Reset Generator

Interrupt Controller

Reset Generator

processor interface

NOTES:

1. Only if IDE Standard I/O space is enabled for Primary Drive. Otherwise, the target is PCI.

2. Only if IDE Standard I/O space is enabled for Secondary Drive. Otherwise, the target is PCI.

3. If POS_DEC_EN bit is enabled, reads from F0h will not be decoded by the ICH2. If POS_DEC_EN is not

enabled, reads from F0h will forward to LPC.

6-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

6.3.2

Variable I/O Decode Ranges

Table 6-3 shows the Variable I/O Decode Ranges. They are set using Base Address Registers

(BARs) or other configuration bits in the various PCI configuration spaces. The PNP software (PCI

or ACPI) can use their configuration mechanisms to set and adjust these values.

When a cycle is detected on the hub interface, the ICH2 positively decodes the cycle. If the

response is on the behalf of an LPC device, ICH2 will forward the cycle to the LPC interface.

Refer to Table A-2 for a complete list of all variable I/O registers.

Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges. Unpredictable

results if the configuration software allows conflicts to occur. The ICH2 does not perform any

checks for conflicts.

Table 6-3. Variable I/O Decode Ranges

Range Name

Mappable

Size (Bytes)

Target

ACPI

IDE

Anywhere in 64 KB I/O Space

96 Bytes above ACPI Base

Anywhere in 64 KB I/O Space

3 ranges in 64 KB I/O Space

8 Ranges in 64 KB I/O Space

2 Ranges in 64 KB I/O Space

4 Ranges in 64 KB I/O Space

2 Ranges in 64 KB I/O Space

Anywhere in 64 KB I/O Space

256

Power Management

IDE Unit

USB #1

USB Unit 1

SMBus

SMB Unit

AC’97 Audio Mixer

AC’97 Bus Master

AC’97 Modem Mixer

TCO

AC’97 Unit

TCO Unit

GPIO

GPIO Unit

Parallel Port

Serial Port 1

Serial Port 2

Floppy Disk Controller

MIDI

LPC Peripheral

LAN Unit

MSS

SoundBlaster

LAN

128

USB #2

USB Unit 2

LPC Generic 1

LPC Generic 2

LPC Peripheral

LPC Peripheral or Trap on

PCI

Monitors 4:7

Anywhere in 64 KB I/O Space

82801BA ICH2 and 82801BAM ICH2-M Datasheet

6-5

6.4

Memory Map

Table 6-4 shows (from the processor perspective) the memory ranges that the ICH2 decodes.

Cycles that arrive from the MCH will first be driven out on PCI. The ICH2 may then claim the

cycle for it to be forwarded to LPC or claimed by the internal APIC. If subtractive decode is

enabled, the cycle can be forwarded to LPC.

PCI cycles generated by an external PCI master will be positively decoded unless it falls in the

PCI-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-peer traffic). If the

cycle is not in the I/O APIC or LPC ranges, it will be forwarded up the hub interface to the Host

Controller.

Table 6-4. Memory Decode Ranges from Processor Perspective

Memory Range

Target

Dependency/Comments

0000 0000h–000D FFFFh

Main Memory

TOM registers in Host Controller

0010 0000–TOM (Top of

Memory)

000E 0000h–000F FFFFh

FEC0 0000h–FEC0 0100h

FWH

Bit 7 in FWH Decode Enable Register is set

I/O APIC inside ICH2

FFC0 0000h–FFC7 FFFFh

FF80 0000h–FF87 FFFFh

FWH

Bit 0 in FWH Decode Enable Register

FFC8 0000h–FFCF FFFFh

FF88 0000h–FF8F FFFFh

Bit 1 in FWH Decode Enable Register

FFD0 0000h–FFD7 FFFFh

FF90 0000h–FF97 FFFFh

Bit 2 in FWH Decode Enable Register is set

Bit 3 in FWH Decode Enable Register is set

Bit 4 in FWH Decode Enable Register is set

Bit 5 in FWH Decode Enable Register is set

Bit 6 in FWH Decode Enable Register is set.

FFD8 0000h–FFDF FFFFh

FF98 0000h–FF9F FFFFh

FFE0 000h–FFE7 FFFFh

FFA0 0000h–FFA7 FFFFh

FFE8 0000h–FFEF FFFFh

FFA8 0000h–FFAF FFFFh

FFF0 0000h–FFF7 FFFFh

FFB0 0000h–FFB7 FFFFh

Always enabled.

The top two 64 KB blocks of this range can be

swapped as described in Section 6.4.1.

FFF8 0000h–FFFF FFFFh

FFB8 0000h–FFBF FFFFh

FWH

FF70 0000h–FF7F FFFFh

FF30 0000h–FF3F FFFFh

FWH

Bit 3 in FWH Decode Enable 2 Register is set

Bit 2 in FWH Decode Enable 2 Register is set

Bit 1 in FWH Decode Enable 2 Register is set

Bit 0 in FWH Decode Enable 2 Register is set

FF60 0000h–FF6F FFFFh

FF20 0000h–FF2F FFFFh

FF50 0000h–FF5F FFFFh

FF10 0000h–FF1F FFFFh

FF40 0000h–FF4F FFFFh

FF00 0000h–FF0F FFFFh

Enable via BAR in Device 29:Function 0 (D110 LAN

Controller)

Anywhere in 4 GB range

All other

D110 LAN Controller

PCI

None

6-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

6.4.1

Boot-Block Update Scheme

The ICH2 supports a “Top-Block Swap” mode that has the ICH2 swap the top block in the FWH

(the boot block) with another location. This allows for safe update of the Boot Block (even if a

power failure occurs). When the “top-swap” enable bit is set, the ICH2 will invert A16 for cycles

targeting FWH BIOS space. When this bit is 0, the ICH2 will not invert A16. This bit is

automatically set to 0 by RTCRST#, but not by PCIRST#.

The scheme is based on the concept that the top block is reserved as the “boot” block, and the block

immediately below the top block is reserved for doing boot-block updates.

The algorithm is:

1. Software copies the top block to the block immediately below the top

2. Software checks that the copied block is correct. This could be done by performing a

checksum calculation.

3. Software sets the “Top-Block Swap” bit. This inverts A16 for cycles going to the FWH.

Processor access to FFFF_0000 through FFFF_FFFF are directed to FFFF_0000 through

FFFE_FFFF in the FWH. Processor accesses to FFFE_0000 through FFFE_FFFF are directed

to FFFF_0000 through FFFF_FFFF.

4. Software erases the top block

5. Software writes the new top block

6. Software checks the new top block

7. Software clears the top-block swap bit

If a power failure occurs at any point after step 3, the system will be able to boot from the copy of

the boot block that is stored in the block below the top. This is because the top-swap bit is backed

in the RTC well.

Note: The Top-Block Swap mode may be forced by an external strapping option (See Section 2.20.1).

When Top-Block Swap mode is forced in this manner, the Top-Swap bit cannot be cleared by

software. A re-boot with the strap removed will be required to exit a forced Top-Block Swap mode.

Note: top-Block Swap mode only affects accesses to the FWH BIOS space, not feature space.

Note: The Top Block Swap mode has no effect on accesses below FFFE_0000.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

6-7

This page is intentionally left blank.

6-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

LAN Controller Registers (B1:D8:F0) 7

The ICH2 integrated LAN Controller appears to reside at PCI Device 8, Function 0 on the

secondary side of the ICH2’s virtual PCI-to-PCI Bridge (See Table 5.1.2). This is typically Bus 1,

but may be assigned a different number depending upon system configuration. The LAN

Controller acts as both a master and a slave on the PCI bus. As a master, the LAN Controller

interacts with the system main memory to access data for transmission or deposit received data. As

a slave, some of the LAN Controller’s control structures are accessed by the host processor to read

or write information to the on-chip registers. The processor also provides the LAN Controller with

the necessary commands and pointers that allow it to process receive and transmit data.

7.1

PCI Configuration Registers (B1:D8:F0)

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

Table 7-1. PCI Configuration Map (LAN Controller—B1:D8:F0)

Offset

Mnemonic

Vendor ID

Default

Type

00–01h

VID

8086h

02–03h

04–05h

06–07h

08h

DID

PCICMD

PCISTS

REVID

SCC

Device ID

2449h

0000h

0290h

Note 1

00h

R/W

PCI Device Command Register

PCI Device Status Register

Revision ID

0Ah

Sub Class Code

0Bh

BCC

Base Class Code

PCI Master Latency Timer

Header Type

02h

0Dh

PMLT

00h

R/W

0Eh

HEADTYP

00h

10–13h

14–17h

2C–2Dh

2E–2Fh

34h

CSR_MEM_BASE CSR Memory-mapped Base Address

0008h

0001h

0000h

DCh

00h

R/W

CSR_IO_BASE

SVID

CSR I/O-mapped Base Address

Subsystem Vendor ID

Subsystem ID

SID

CAP_PTR

INT_LN

Capabilities Pointer

Interrupt Line

3Ch

R/W

3Dh

INT_PN

Interrupt Pin

01h

3Eh

MIN_GNT

MAX_LAT

CAP_ID

NXT_PTR

Minimum Grant

08h

3Fh

Maximum Latency

Capability ID

38h

DCh

01h

DDh

Next Item Pointer

00h

FE21h (ICH2)

7E21 (ICH2-M)

DE–DFh

PM_CAP

Power Management Capabilities

E0–E1h

E3h

PMCSR

DATA

Power Management Control/Status

Data

0000h

00h

R/W

NOTE: Refer to the Specification Update for the value of the Revision ID Register.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-1

LAN Controller Registers (B1:D8:F0)

7.1.1

7.1.2

VID—Vendor ID Register (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

00–01h

8086h

Attribute:

Size:

16 bits

Bit

Description

15:0

Vendor Identification Number. This is a 16-bit value assigned to Intel.

DID—Device ID Register (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

02–03h

2449h

Attribute:

Size:

16 bits

Bit

Description

Device Identification Number. This is a 16 bit value assigned to the ICH2 integrated LAN

Controller.

15:0

7.1.3

PCICMD—PCI Command Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

04–05h

0000h

Attribute:

Size:

RO, R/W

16 bits

Bit

Description

15:10

Reserved.

Fast Back to Back Enable (FBE)—RO. Hardwired to 0. The integrated LAN Controller will not run

fast back-to-back PCI cycles.

SERR# Enable (SERR_EN)—R/W.

1 = Enable. Allow SERR# to be generated.

0 = Disable.

Wait Cycle Control (WCC)—RO. Hardwired to 0. Not implemented.

Parity Error Response (PER)—R/W

1 = The integrated LAN Controller will take normal action when a PCI parity error is detected. The

generation of parity is also enabled on the hub interface.

0 = The LAN Controller will ignore PCI parity errors.

VGA Palette Snoop (VPS)—RO. Hardwired to 0. Not Implemented.

Memory Write and Invalidate Enable (MWIE)—R/W.

0 = Disable. The LAN Controller will not use the Memory Write and Invalidate command.

1 = Enable.

Special Cycle Enable (SCE)—RO. Hardwired to 0. The LAN Controller ignores special cycles.

Bus Master Enable (BME)—R/W.

1 = Enable. The ICH2’s integrated may function as a PCI bus master.

0 = Disable.

Memory Space Enable (MSE)—R/W.

1 = Enable. The ICH2’s integrated LAN Controller will respond to the memory space accesses.

0 = Disable.

I/O Space Enable (IOE)—R/W.

1 = Enable. The ICH2’s integrated LAN Controller will respond to the I/O space accesses.

0 = Disable.

7-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

7.1.4

PCISTS—PCI Status Register (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

06–07h

0290h

Attribute:

Size:

RO, R/WC

16 bits

Bit

Description

Detected Parity Error (DPE)—R/WC.

1 = The ICH2’s integrated LAN Controller has detected a parity error on the PCI bus (will be set

even if Parity Error Response is disabled in the PCI Command register).

0 = This bit is cleared by writing a 1 to the bit location.

Signaled System Error (SSE)—R/WC.

1 = The ICH2’s integrated LAN Controller has asserted SERR#. (SERR# can be routed to cause

NMI, SMI# or interrupt.

0 = This bit is cleared by writing a 1 to the bit location.

Master Abort Status (RMA)—R/WC.

1 = The ICH2’s integrated LAN Controller (as a PCI master) has generated a master abort.

0 = This bit is cleared by writing a 1 to the bit location.

Received Target Abort (RTA)—R/WC.

1 = The ICH2’s integrated LAN Controller (as a PCI master) has received a target abort.

0 = This bit is cleared by writing a 1 to the bit location.

Signaled Target Abort (STA)—RO. Hardwired to 0. The device will never signal Target Abort.

DEVSEL# Timing Status (DEV_STS)—RO.

01h = Medium timing.

10:9

Data Parity Error Detected (DPED)—R/WC.

1 = All of the following three conditions have been met:

1.The LAN Controller is acting as bus master

2.The LAN Controller has asserted PERR# (for reads) or detected PERR# asserted (for

writes)

3.The Parity Error Response bit in the LAN Controller’s PCI Command Register is set.

0 = This bit is cleared by writing a 1 to the bit location.

Fast Back to Back (FB2B)—RO. Hardwired to 1. The device can accept fast back-to-back

transactions.

User Definable Features (UDF)—RO. Hardwired to 0. Not implemented.

66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0. The device does not support 66MHz PCI.

Capabilities List (CAP_LIST)—RO.

1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management.

0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power

Management.

3:0

Reserved.

7.1.5

REVID—Revision ID Register (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

08h

00h

Attribute:

Size:

8 bits

Bit

Description

Revision Identification Number. 8-bit value that indicates the revision number for the integrated

LAN Controller. The three least significant bits in this register may be overridden by the ID and REV

ID fields in the EEPROM.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-3

LAN Controller Registers (B1:D8:F0)

7.1.6

7.1.7

7.1.8

SCC—Sub-Class Code Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

0Ah

00h

Attribute:

Size:

8 bits

Bit

Description

7:0

Sub-Class Code. 8-bit value that specifies the sub-class of the device as an Ethernet controller.

BCC—Base-Class Code Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

0Bh

02h

Attribute:

Size:

8 bits

Bit

Description

7:0

Base Class Code. 8-bit value that specifies the base class of the device as a network controller.

CLS—Cache Line Size Register (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

0Ch

00h

Attribute:

Size:

8 bits

Bit

Description

7:5

4:3

2:0

Reserved.

Cache Line Size (CLS)—RW.

00 = Memory Write and Invalidate (MWI) command will not be used by the integrated LAN Controller.

01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a value of 08h is

written to this register).

10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a value of 10h is

written to this register).

11 = Invalid. MWI command will not be used.

Reserved.

7.1.9

PMLT—PCI Master Latency Timer Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

0Dh

00h

Attribute:

Size:

8 bits

Bit

Description

Master Latency Timer Count (MLTC)—RW. Defines the number of PCI clock cycles that the

integrated LAN Controller may own the bus while acting as bus master.

7:3

2:0

Reserved.

7-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

7.1.10

HEADTYP—Header Type Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

0Eh

00h

Attribute:

Size:

8 bits

Bit

Description

Multi-function Device—RO. Hardwired to 0 to indicate a single function device.

Header Type—RO. 7-bit field identifies the header layout of the configuration space as an Ethernet

controller.

6:0

7.1.11

CSR_MEM_BASE CSR—Memory-Mapped Base Address

Offset Address:

Default Value:

10–13h

0000 0008h

Attribute:

Size:

R/W, RO

32 bits

Note: The ICH2’s integrated LAN Controller requires one BAR for memory mapping. Software

determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.

Bit

Description

Base Address—R/W. Upper 20 bits of the base address provides 4 KB of memory-mapped space for

the LAN Controller’s Control/Status Registers.

31:12

11:4 Reserved.

Pre-fetchable—RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory-mapped

address range.

2:1

Type—RO. Hardwired to 00b to indicate the memory-mapped address range may be located

anywhere in 32-bit address space.

Memory-Space Indicator—RO. Hardwired to 0 to indicate that this base address maps to memory

space.

7.1.12

CSR_IO_BASE—CSR I/O-Mapped Base Address Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

14–17h

0000 0001h

Attribute:

Size:

R/W

32 bits

Note: The ICH2’s integrated LAN Controller requires one BAR for memory mapping. Software

determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.

Bit

Description

31:16 Reserved.

Base Address—R/W. Provides 64 bytes of I/O-mapped address space for the LAN Controller’s

Control/Status Registers.

15:6

5:1

Reserved.

I/O Space Indicator—RO. Hardwired to 1 to indicate that this base address maps to I/O space.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-5

LAN Controller Registers (B1:D8:F0)

7.1.13

7.1.14

SVID—Subsystem Vendor ID (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

2C–2D

0000h

Attribute:

Size:

16 bits

Bit

Description

15:0

Subsystem Vendor ID—RO.

SID—Subsystem ID (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

2E–2Fh

0000h

Attribute:

Size:

16 bits

Bit

Description

15:0

Subsystem ID—RO.

Note: The ICH2’s integrated LAN Controller provides support for configureable Subsystem ID and

Subsystem Vendor ID fields. After reset, the LAN Controller automatically reads addresses Ah

through Ch of the EEPROM. The LAN Controller checks bits 15:13 in the EEPROM word Ah, and

functions according to Table 7-2.

Table 7-2. Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM

Subsystem

Vendor ID

Bits 15:14 Bit 13 Device ID Vendor ID

Revision ID

Subsystem ID

11b, 10b,

00b

2449h

8086h

00h

0000h

01b

Word Bh

Word Ch

Word Ah,

bits 10:8

01b

Word Bh

Word Ch

7.1.15

CAP_PTR—Capabilities Pointer

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

34h

DCh

Attribute:

Size:

8 bits

Bit

Description

Capabilities Pointer (CAP_PTR)—RO. Hardwired to DCh to indicate the offset within configuration

space for the location of the Power Management registers.

7:0

7-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

7.1.16

7.1.17

INT_LN—Interrupt Line Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

3Ch

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Interrupt Line (INT_LN)—R/W. Identifies the system interrupt line to which the LAN Controller’s

PCI interrupt request pin (as defined in the Interrupt Pin Register) is routed.

7:0

INT_PN—Interrupt Pin Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

3Dh

01h

Attribute:

Size:

8 bits

Bit

Description

Interrupt Pin (INT_PN)—RO. Hardwired to 01h to indicate that the LAN Controller’s interrupt

request is connected to PIRQA#. However, in the ICH2 implementation, when the LAN Controller

interrupt is generated PIRQ[E]# will go active, not PIRQ[A]#.

7:0

7.1.18

7.1.19

MIN_GNT—Minimum Grant Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

3Eh

08h

Attribute:

Size:

8 bits

Bit

Description

Minimum Grant (MIN_GNT)—RO. Indicates the amount of time (in increments of 0.25 µs) that the

LAN Controller needs to retain ownership of the PCI bus when it initiates a transaction.

7:0

MAX_LAT—Maximum Latency Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

3Fh

38h

Attribute:

Size:

8 bits

Bit

Description

Maximum Latency (MAX_LAT)—RO. Defines how often (in increments of 0.25 µs) the LAN

Controller needs to access the PCI bus.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-7

LAN Controller Registers (B1:D8:F0)

7.1.20

CAP_ID—Capability ID Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

DCh

01h

Attribute:

Size:

8 bits

Bit

Description

Capability ID (CAP_ID)—RO. Hardwired to 01h to indicate that the ICH2’s integrated LAN

Controller supports PCI Power Management.

7:0

7.1.21

7.1.22

NXT_PTR—Next Item Pointer (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

DDh

00h

Attribute:

Size:

8 bits

Bit

Description

Next Item Pointer (NXT_PTR)—RW. Hardwired to 00b to indicate that power management is the

last item in the Capabilities list.

7:0

PM_CAP—Power Management Capabilities

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

DE–DFh

FE22h

Attribute:

Size:

16 bits

Bit

Description

PME Support. Hardwired to 11111b. This 5-bit field indicates the power states in which the LAN

Controller may assert PME#. The LAN Controller supports wake-up in all power states.

15:11

D2 Support. Hardwired to 1 to indicate that the LAN Controller supports the D2 power state.

D1 Support. Hardwired to 1 to indicate that the LAN Controller supports the D1 power state.

Auxiliary Current. Hardwired to 000b to indicate that the LAN Controller implements the Data

registers. The auxiliary power consumption is the same as the current consumption reported in the

D3 state in the Data register.

8:6

Device Specific Initialization (DSI). Hardwired to 1 to indicate that special initialization of this

function is required (beyond the standard PCI configuration header) before the generic class device

driver is able to use it. DSI is required for the LAN Controller after D3-to-D0 reset.

Reserved

PME Clock. Hardwired to 0 to indicate that the LAN Controller does not require a clock to generate

a power management event.

Version. Hardwired to 010b to indicate that the LAN Controller complies with of the PCI Power

Management Specification, Revision 1.1.

2:0

7-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

7.1.23

PMCSR—Power Management Control/Status Register

(LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

E0–E1h

0000h

Attribute:

Size:

RO, R/W, R/WC

16 bits

Bit

Description

PME Status—R/WC.

1 = Set upon occurrence of a wake-up event, independent of the state of the PME Enable bit.

0 = Software clears this bit by writing a 1 to the bit location. This also deasserts the PME# signal

and clears the PME status bit in the Power Management Driver Register. When the PME#

signal is enabled, the PME# signal reflects the state of the PME status bit.

Data Scale—RO. This field indicates the data register scaling factor. It equals 10b for registers zero

through eight and 00b for registers nine through fifteen, as selected by the "Data Select" field.

14:13

12:9

Data Select—R/W. This field is used to select which data is reported through the Data register and

Data Scale field.

PME Enable—R/W. This bit enables the ICH2’s integrated LAN controller to assert PME#.

1 = Enable PME# assertion when PME Status is set.

0 = The device will not assert PME#.

Reserved.

7:5

Dynamic Data—RO. Hardwired to 0 to indicate that the device does not support the ability to

monitor the power consumption dynamically.

3:2

Reserved.

Power State—R/W. This 2-bit field is used to determine the current power state of the integrated

LAN Controller, and to put it into a new power state. The definition of the field values is as follows:

00 = D0

01 = D1

10 = D2

11 = D3

1:0

7.1.24

DATA—Data Register (LAN Controller—B1:D8:F0)

Offset Address:

Default Value:

E3h

00h

Attribute:

Size:

8 bits

Bit

Description

7:0

Data Value. State dependent power consumption and heat dissipation data.

Note: The data register is an 8-bit read only register that provides a mechanism for the ICH2’s integrated

LAN Controller to report state dependent maximum power consumption and heat dissipation. The

value reported in this register depends on the value written to the Data Select field in the PMCSR

with 0.01 W resolution, scaled according to the Data Scale field in the PMCSR. The structure of

the Data Register is given in Table 7-3.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-9

LAN Controller Registers (B1:D8:F0)

Table 7-3. Data Register Structure

Data Select

Data Scale

Data Reported

D0 Power Consumption

D1 Power Consumption

D2 Power Consumption

D3 Power Consumption

D0 Power Dissipated

D1 Power Dissipated

D2 Power Dissipated

D3 Power Dissipated

Common Function Power Dissipated

Reserved

9–15

7.2

LAN Control / Status Registers (CSR)

Table 7-4. ICH2 Integrated LAN Controller CSR Space

Offset

SCB Status Word

Default

Type

01h–00h

03h–02h

07h–04h

0Bh–08h

0Dh–0Ch

0Eh

0000h

0000 0000h

—

R/WC

SCB Command Word

SCB General Pointer

PORT

R/W

R/W (special)

Reserved

—

R/W

EEPROM Control Register

Reserved

0Fh

—

13h–10h

17h–14h

18h

MDI Control Register

Receive DMA Byte Count

Early Receive Interrupt

Flow Control Register

PMDR

0000 0000h

00h

R/W (special)

R/W

1A–19h

1Bh

0000h

00h

R/W

R/WC

R/W

1Ch

General Control

General Status

1Dh

N/A

1Eh–3Ch

Reserved

—

7-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

7.2.1

System Control Block Status Word Register

Offset Address:

Default Value:

00–01h

0000h

Attribute:

Size:

R/WC, RO

16 bits

The ICH2’s integrated LAN Controller places the status of its Command and Receive units and

interrupt indications in this register for the processor to read.

Bit

Description

Command Unit (CU) Executed (CX)—R/WC.

1 = Interrupt signaled because the CU has completed executing a command with its interrupt bit set.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

Frame Received (FR)—R/WC.

1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

CU Not Active (CNA)—R/WC.

1 = The Command Unit left the Active state or entered the Idle state. There are 2 distinct states of

the CU. When configured to generate CNA interrupt, the interrupt will be activated when the CU

leaves the Active state and enters either the Idle or the Suspended state. When configured to

generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

Receive Not Ready (RNR)—R/WC.

1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU

Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame

Descriptor.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

Management Data Interrupt (MDI)—R/WC.

1 = Set when a Management Data Interface read or write cycle has completed. The management

data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data

Interface Control register in the CSR).

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

Software Interrupt (SWI)—R/WC.

1 = Set when software generates an interrupt.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

Early Receive (ER)—R/WC.

1 = Indicates the occurrence of an Early Receive Interrupt.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

Flow control Pause (FCP)—R/WC.

1 = Indicates Flow Control Pause interrupt.

0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.

Command Unit Status (CUS)—RO.

00 = Idle

01 = Suspended

7:6

10 = LPQ (Low Priority Queue) active

11 = HPQ (High Priority Queue) active

Receive Unit Status (RUS)—RO.

0000 = Idle

1000 = Reserved

0001 = Suspended

0010 = No Resources

0011 = Reserved

0100 = Ready

0101 = Reserved

0110 = Reserved

0111 = Reserved

1001 = Suspended with no more RBDs

1010 = No resources due to no more RBDs

1011 = Reserved

1100 = Ready with no RBDs present

1101 = Reserved

5:2

1:0

1110 = Reserved

1111 = Reserved

Reserved.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-11

LAN Controller Registers (B1:D8:F0)

7.2.2

System Control Block Command Word Register

Offset Address:

Default Value:

02–03h

0000h

Attribute:

Size:

R/W

16 bits

The processor places commands for the Command and Receive units in this register. Interrupts are

also acknowledged in this register.

Bit

Description

CX Mask—R/W.

0 = Interrupt not masked.

1 = Disable the generation of a CX interrupt.

FR Mask—R/W.

0 = Interrupt not masked.

1 = Disable the generation of an FR interrupt.

CNA Mask—R/W.

0 = Interrupt not masked.

1 = Disable the generation of a CNA interrupt.

RNR Mask—R/W.

0 = Interrupt not masked.

1 = Disable the generation of an RNR interrupt.

ER Mask—R/W.

0 = Interrupt not masked.

1 = Disable the generation of an ER interrupt.

FCP Mask—R/W.

0 = Interrupt not masked.

1 = Disable the generation of an FCP interrupt.

Software Generated Interrupt (SI)—WO.

0 = No Effect.

1 = Setting this bit causes the LAN Controller to generate an interrupt.

Interrupt Mask (IM)—R/W. This bit enables or disables the LAN Controller’s assertion of the INTA#

signal. This bit has higher precedence that the Specific Interrupt Mask bits and the SI bit.

0 = Enable the assertion of INTA#.

1 = Disable the assertion of INTA#.

7-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

Bit

Description

Command Unit Command (CUC). Valid values are listed below. All other values are Reserved.

0000 = NOP: Does not affect the current state of the unit.

0001 = CU Start: Start execution of the first command on the CBL. A pointer to the first CB of the

CBL should be placed in the SCB General Pointer before issuing this command. The CU

Start command should only be issued when the CU is in the Idle or Suspended states

(never when the CU is in the active state), and all of the previously issued Command

Blocks have been processed and completed by the CU. Sometimes it is only possible to

determine that all Command Blocks are completed by checking that the Complete bit is set

in all previously issued Command Blocks.

0010 = CU Resume: Resume operation of the Command unit by executing the next command.

This command will be ignored if the CU is idle.

0011 = CU HPQ Start: Start execution of the first command on the high priority CBL. A pointer to

the first CB of the HPQ CBL should be placed in the SCB General POinter before issuing

this command.

0100 = Load Dump Counters Address: Tells the device where to write dump data when using the

Dump Statistical Counters or Dump and Reset Statistical Counters commands. This

command must be executed at least once before any usage of the Dump Statistical

Counters or Dump and Reset Statistical Counters commands. The address of the dump

area must be placed in the General Pointer register.

7:4

0101 = Dump Statistical Counters: Tells the device to dump its statistical counters to the area

designated by the Load Dump Counters Address command.

0110 = Load CU Base: The device’s internal CU Base Register is loaded with the value in the

CSB General Pointer.

0111 = Dump and Reset Statistical Counters: Tells the device to dump its statistical counters to

the area designated by the Load Dump Counters Address command, and then to clear

these counters.

1010 = CU Static Resume: Resume operation of the Command unit by executing the next

command. This command will be ignored if the CU is idle. This command should be used

only when the CU is in the Suspended state and has no pending CU Resume commands.

1011 = CU HPQ Resume: Resume execution of the first command on the HPQ CBL. this

command will be ignored if the HPQ was never started.

Reserved.

Receive Unit Command (RUC). Valid values are:

000 = NOP: Does not affect the current state of the unit.

001 = RU Start: Enables the receive unit. The pointer to the RFA must be placed in the SCB

General POinter before using this command. The device pre-fetches the first RFD and the

first RBD (if in flexible mode) in preparation to receive incoming frames that pass its address

filtering.

010 = RU Resume: Resume frame reception (only when in suspended state).

011 = RCV DMA Redirect: Resume the RCV DMA when configured to "Direct DMA Mode." The

buffers are indicated by an RBD chain which is pointed to by an offset stored in the General

Pointer Register (this offset will be added to the RU Base).

2:0

100 = RU Abort: Abort RU receive operation immediately.

101 = Load Header Data Size (HDS): This value defines the size of the Header portion of the RFDs

or Receive buffers. The HDS value is defined by the lower 14 bits of the SCB General Pointer,

so bits 31:15 should always be set to zeros when using this command. Once a Load HDS

command is issued, the device expects only to find Header RFDs, or be used in "RCV Direct

DMA mode" until it is reset. Note that the value of HDS should be an even, non-zero number.

110 = Load RU Base: The device’s internal RU Base Register is loaded with the value in the SCB

General Pointer.

111 = RBD Resume: Resume frame reception into the RFA. This command should only be used

when the RU is already in the "No Resources due to no RBDs" state or the "Suspended with

no more RBDs" state.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-13

LAN Controller Registers (B1:D8:F0)

7.2.3

System Control Block General Pointer Register

Offset Address:

Default Value:

04–07h

0000 0000h

Attribute:

Size:

R/W

32 bits

Bit

Description

SCB General Pointer. The SCB General Pointer register is programmed by software to point to

various data structures in main memory depending on the current SCB Command word.

15:0

7.2.4

PORT Register

Offset Address:

Default Value:

08–0Bh

0000 0000h

Attribute:

Size:

R/W (special)

32 bits

The PORT interface allows the processor to reset the ICH2’s internal LAN Controller or perform

an internal self test. The PORT DWord may be written as a 32-bit entity, two 16-bit entities, or four

8-bit entities. The LAN Controller will only accept the command after the high byte (offset 0Bh) is

written; therefore, the high byte must be written last.

Bit

Description

Pointer Field. A 16-byte aligned address must be written to this field when issuing a Self-Test

command to the PORT interface.The results of the Self Test will be written to the address specified

by this field.

31:4

PORT Function Selection. Valid values are listed below. All other values are Reserved.

0000 = PORT Software Reset: Completely resets the LAN Controller (all CSR and PCI registers).

This command should not be used when the device is active. If a PORT Software Reset is

desired, software should do a Selective Reset (described below), wait for the PORT

Software Reset command. Software should wait approximately 10 µs after issuing this

command before attempting to access the LAN Controller’s registers again.

0001 = Self Test: The Self-Test begins by issuing an internal Selective Reset followed by a

general internal self-test of the LAN Controller. The results of the self-test are written to

memory at the address specified in the Pointer field of this register. The format of the self-

test result is shown in Table 7-5. After completing the self-test and writing the results to

memory, the LAN Controller will execute a full internal reset and will re-initialize to the

default configuration. Self-Test does not generate an interrupt of similar indicator to the

host processor upon completion.

3:0

0010 = Selective Reset: Sets the CU and RU to the Idle state, but otherwise maintains the current

configuration parameters (RU and CU Base, HDSSize, Error Counters, Configure

information and Individual/Multicast Addresses are preserved). Software should wait

approximately 10 µs after issuing this command before attempting to access the LAN

Controller’s registers again.

7-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

Table 7-5. Self-Test Results Format

Bit

Description

31:13

11:6

Reserved

General Self-Test Result.

0 = Pass

1 = Fail

Reserved

Diagnose Result. This bit provides the result of an internal diagnostic test of the Serial Subsystem.

0 = Pass

1 = Fail

Reserved

0 = Pass

1 = Fail

ROM Content Result. This bit provides the result of a test of the internal microcode ROM.

0 = Pass

1 = Fail

1:0

Reserved

7.2.5

EEPROM Control Register

Offset Address:

Default Value:

0Eh

00h

Attribute:

Size:

RO, R/W

8 bits

The EEPROM Control Register is a 16-bit field that enables a read from and a write to the external

EEPROM.

Bit

Description

7:4

Reserved

EEPROM Serial Clock (EESK)—R/W. Toggling this bit clocks data into or out of the EEPROM.

Software must ensure that this bit is toggled at a rate that meets the EEPROM component’s

minimum clock frequency specification.

0 = Drives the ICH2’s EE_SHCLK signal low.

1 = Drives the ICH2’s EE_SHCLK signal high.

EEPROM Chip Select (EECS)—R/W.

0 = Drives the ICH2’s EE_CS signal low, to disable the EEPROM. this bit must be set to 0 for a

minimum of 1µs between consecutive instruction cycles.

1 = Drives the ICH2’s EE_CS signal high, to enable the EEPROM.

EEPROM Serial Data In (EEDI)—WO. Note that this bit represents "Data In" from the perspective

of the EEPROM device. The value of this bit is written to the EEPROM when performing write

operations.

EEPROM Serial Data Out (EEDO)—RO. Note that this bit represents "Data Out" from the

perspective of the EEPROM device. This bit contains the value read from the EEPROM when

performing read operations.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-15

LAN Controller Registers (B1:D8:F0)

7.2.6

Management Data Interface (MDI) Control Register

Offset Address:

Default Value:

10–13h

0000 0000h

Attribute:

Size:

R/W (special)

32 bits

The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and

write bits from the LAN Connect component. This register may be written as a 32-bit entity, two

16-bit entities, or four 8-bit entities. The LAN Controller will only accept the command after the

high byte (offset 13h) is written; therefore, the high byte must be written last.

Bit

Description

These bits are reserved and should be set to 00b.

31:30

Interrupt Enable.

1 = Enables the LAN Controller to assert an interrupt to indicate the end of an MDI cycle.

0 = Disable.

Ready.

1 = Set by the LAN Controller at the end of an MDI transaction.

0 = Expected to be reset by software at the same time the command is written.

Opcode. These bits define the opcode:

00 = Reserved

27:26

01 = MDI write

10 = MDI read

11 = Reserved

25:21

20:16

LAN Connect Address. This field of bits contains the LAN Connect address.

LAN Connect Register Address. This field of bits contains the LAN Connect Register Address.

Data. In a write command, software places the data bits in this field, and the LAN Controller

transfers the data to the external LAN Connect component. During a read command, the LAN

Controller reads these bits serially from the LAN Connect, and software reads the data from this

location.

15:0

7.2.7

Receive DMA Byte Count Register

Offset Address:

Default Value:

14–17h

0000 0000h

Attribute:

Size:

32 bits

Bit

Description

Receive DMA Byte Count—RO. Keeps track of how many bytes of receive data have been passed

into host memory via DMA.

31:0

7-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

7.2.8

Early Receive Interrupt Register

Offset Address:

Default Value:

18h

00h

Attribute:

Size:

R/W

8 bits

The Early Receive Interrupt register allows the internal LAN Controller to generate an early

interrupt depending on the length of the frame. The LAN Controller will generate an interrupt at

the end of the frame, regardless of whether or not Early Receive Interrupts are enabled.

Note: It is recommended that software NOT utilize this register unless receive interrupt latency is a

critical performance issue in that particular software environment. Using this feature may reduce

receive interrupt latency, but will also result in the generation of more interrupts, which can

degrade system efficiency and performance in some environments.

Bit

Description

Early Receive Count—R/W. When some non-zero value x is programmed into this register, the

LAN controller sets the ER bit in the SCB Status Word Register and assert INTA# when the byte

count indicates that there are x quadwords remaining to be received in the current frame (based on

the Type/Length field of the received frame). No Early Receive interrupt will be generated if a value

of 00h (the default value) is programmed into this register.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-17

LAN Controller Registers (B1:D8:F0)

7.2.9

Flow Control Register

Offset Address:

Default Value:

19–1Ah

0000h

Attribute:

Size:

RO, R/W (special)

16 bits

Bit

Description

15:13

Reserved

FC Paused Low—RO.

1 = Set when the LAN Controller receives a Pause Low command with a value greater than zero.

0 = Cleared when the FC timer reaches zero, or a Pause frame is received.

FC Paused—RO.

1 = Set when the LAN Controller receives a Pause command regardless of its cause (FIFO

reaching Flow Control Threshold, fetching a Receive Frame Descriptor with its Flow Control

Pause bit set, or software writing a 1 to the Xoff bit).

0 = Cleared when the FC timer reaches zero.

FC Full—RO.

1 = Set when the LAN Controller sends a Pause command with a value greater than zero.

0 = Cleared when the FC timer reaches zero.

Xoff—R/W (special). This bit should only be used if the LAN Controller is configured to operate with

IEEE frame-based flow control.

1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN Controller to behave as if

the FIFO extender is full. This bit will also be set to 1 when an Xoff request due to an "RFD

Xoff" bit.

0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register).

Xon—WO. This bit should only be used if the LAN Controller is configured to operate with IEEE

frame-based flow control.

1 = Writing a 1 to this bit resets the Xoff request to the LAN Controller, clearing bit 9 in this register.

0 = This bit always returns 0 on reads.

Reserved

7:3

Flow Control Threshold—R/W. The LAN Controller can generate a Flow Control Pause frame

when its Receive FIFO is almost full. The value programmed into this field determines the number of

bytes still available in the Receive FIFO when the Pause frame is generated.

Free Bytes

Bits 2:0 in Receive FIFO Comment

000

001

010

011

100

101

110

111

0.50 KB

1.00 KB

1.25 KB

1.50 KB

1.75 KB

2.00 KB

2.25 KB

2.50 KB

Fast system (recommended default)

2:0

Slow system

7-18

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

7.2.10

Power Management Driver (PMDR) Register

Offset Address:

Default Value:

1Bh

00h

Attribute:

Size:

R/WC

8 bits

The ICH2’s internal LAN Controller provides an indication in the PMDR that a wake-up event has

occurred.

Bit

Description

Link Status Change Indication—R/WC.

1 = The link status change bit is set following a change in link status.

0 = Software clears this bit by writing a 1 to the bit location.

Magic Packet—R/WC.

1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable

bit in the configuration command and the PME Enable bit in the Power Management Control/

Status Register.

0 = Software clears this bit by writing a 1 to the bit location.

Interesting Packet—R/WC.

1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the

LAN Controller packet filters.

0 = Software clears this bit by writing a 1 to the bit location.

Reserved.

4:1

PME Status—R/WC. This bit is a reflection of the PME Status bit in the Power Management

Control/Status Register (PMCSR).

1 = Set upon a wake-up event, independent of the PME Enable bit.

0 = Software clears this bit by writing a 1 to the bit location. This also clears the PME Status bit in

the PMCSR and deasserts the PME signal.

7.2.11

General Control Register

Offset Address:

Default Value:

1Ch

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

7:4

Reserved. These bits should be set to 0000b.

LAN Connect Software Reset—R/W.

1 = Software can set this bit to force a reset condition on the LAN Connect interface.

0 = Cleared by software to begin normal LAN Connect operating mode. Software must not attempt

to access the LAN Connect interface for at least 1 ms after clearing this bit.

Reserved. This bit should be set to 0.

Deep Power-Down on Link Down Enable.

1 = Enable. The ICH2’s internal LAN Controller may enter a deep power-down state (sub 3 mA) in

the D2 and D3 power states while the link is down. In this state, the LAN Controller does not

keep link integrity. This state is not supported for point-to-point connection of two end stations.

0 = Disable

Reserved.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-19

LAN Controller Registers (B1:D8:F0)

7.2.12

General Status Register

Offset Address:

Default Value:

1Dh

N/A

Attribute:

Size:

8 bits

Bit

Description

7:3

Reserved.

Duplex Mode. This bit indicates the wire duplex mode.

1 = Full duplex

0 = Half duplex

Speed. This bit indicates the wire speed:

1 = 100 Mbps

0 = 10 Mbps

Link Status Indication. This bit indicates the status of the link:

1 = Valid

0 = Invalid

7.2.13

Statistical Counters

The ICH2’s integrated LAN Controller provides information for network management statistics by

providing on-chip statistical counters that count a variety of events associated with both transmit

and receive. The counters are updated by the LAN Controller when it completes the processing of a

frame (i.e., when it has completed transmitting a frame on the link or when it has completed

receiving a frame). The Statistical Counters are reported to the software on demand by issuing the

Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB

Command Unit Command (CUC) field.

Table 7-6. Statistical Counters

Counter

Description

This counter contains the number of frames that were transmitted properly on

the link. It is updated only after the actual transmission on the link is

completed, not when the frame was read from memory as is done for the

Transmit Command Block status.

Transmit Good

Frames

Transmit Maximum

Collisions

(MAXCOL) Errors

This counter contains the number of frames that were not transmitted

because they encountered the configured maximum number of collisions.

Transmit Late

Collisions

(LATECOL) Errors

This counter contains the number of frames that were not transmitted since

they encountered a collision later than the configured slot time.

A transmit underrun occurs because the system bus cannot keep up with the

transmission. This counter contains the number of frames that were either

not transmitted or retransmitted due to a transmit DMA underrun. If the LAN

Controller is configured to retransmit on underrun, this counter may be

updated multiple times for a single frame.

Transmit Underrun

Errors

Transmit Lost

Carrier Sense

(CRS)

This counter contains the number of frames that were transmitted by the LAN

Controller despite the fact that it detected the deassertion of CRS during the

transmission.

This counter contains the number of frames that were deferred before

transmission due to activity on the link.

Transmit Deferred

Transmit Single

Collisions

This counter contains the number of transmitted frames that encountered

one collision.

7-20

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LAN Controller Registers (B1:D8:F0)

Table 7-6. Statistical Counters

Counter

Description

Transmit Multiple

Collisions

This counter contains the number of transmitted frames that encountered

more than one collision.

This counter contains the total number of collisions that were encountered

while attempting to transmit. This count includes late collisions and frames

that encountered MAXCOL.

Transmit Total

Collisions

This counter contains the number of frames that were received properly from

the link. It is updated only after the actual reception from the link is completed

and all the data bytes are stored in memory.

Receive Good

Frames

This counter contains the number of aligned frames discarded because of a

CRC error. This counter is updated, if needed, regardless of the Receive Unit

state. The Receive CRC Errors counter is mutually exclusive of the Receive

Alignment Errors and Receive Short Frame Errors counters.

Receive CRC Errors

This counter contains the number of frames that are both misaligned (for

example, CRS deasserts on a non-octal boundary) and contain a CRC error.

The counter is updated, if needed, regardless of the Receive Unit state. The

Receive Alignment Errors counter is mutually exclusive of the Receive CRC

Errors and Receive Short Frame Errors counters.

Receive Alignment

Errors

This counter contains the number of good frames discarded due to

unavailability of resources. Frames intended for a host whose Receive Unit is

in the No Resources state fall into this category. If the LAN Controller is

configured to Save Bad Frames and the status of the received frame

indicates that it is a bad frame, the Receive Resource Errors counter is not

updated.

Receive Resource

Errors

This counter contains the number of frames known to be lost because the

local system bus was not available. If the traffic problem persists for more

than one frame, the frames that follow the first are also lost; however,

because there is no lost frame indicator, they are not counted.

Receive Overrun

Errors

Receive Collision

Detect (CDT)

This counter contains the number of frames that encountered collisions

during frame reception.

This counter contains the number of received frames that are shorter than

the minimum frame length. The Receive Short Frame Errors counter is

mutually exclusive to the Receive Alignment Errors and Receive CRC Errors

counters. A short frame will always increment only the Receive Short Frame

Errors counter.

Receive Short

Frame Errors

This counter contains the number of Flow Control frames transmitted by the

LAN Controller. This count includes both the Xoff frames transmitted and Xon

(PAUSE(0)) frames transmitted.

Flow Control

Transmit Pause

This counter contains the number of Flow Control frames received by the

LAN Controller. This count includes both the Xoff frames received and Xon

(PAUSE(0)) frames received.

Flow Control

Receive Pause

This counter contains the number of MAC Control frames received by the

LAN Controller that are not Flow Control Pause frames. These frames are

valid MAC control frames that have the predefined MAC control Type value

and a valid address but has an unsupported opcode.

Flow Control

Receive

Unsupported

Receive TCO

Frames

This counter contains the number of TCO packets received by the LAN

Controller.

Transmit TCO

Frames

This counter contains the number of TCO packets transmitted.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

7-21

LAN Controller Registers (B1:D8:F0)

The Statistical Counters are initially set to zero by the ICH2’s integrated LAN Controller after

reset. They cannot be preset to anything other than zero. The LAN Controller increments the

counters by internally reading them, incrementing them and writing them back. This process is

invisible to the processor and PCI bus. In addition, the counters adhere to the following rules:

• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around

to 0.

• The LAN Controller updates the required counters for each frame. It is possible for more than

one counter to be updated as multiple errors can occur in a single frame.

• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1

standard. The LAN Controller supports all mandatory and recommend statistics functions

through the status of the receive header and directly through these Statistical Counters.

The processor can access the counters by issuing a Dump Statistical Counters SCB command. This

provides a “snapshot”, in main memory, of the internal LAN Controller statistical counters. The

LAN Controller supports 21 counters. The dump could consist of the either 16, 19, or all 21

counters, depending on the status of the Extended Statistics Counters and TCO Statistics

configuration bits in the Configuration command.

7-22

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Hub Interface to PCI Bridge Registers (D30:F0)

Hub Interface to PCI Bridge Registers

(D30:F0)

The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the

ICH2 implements the buffering and control logic between PCI and the hub interface. The

arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must

decode the ranges for the hub interface. All register contents will be lost when core well power is

removed.

8.1

PCI Configuration Registers (D30:F0)

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

Table 8-1. PCI Configuration Map (HUB-PCI—D30:F0)

Offset

Mnemonic

Vendor ID

Default

Type

00–01h

VID

8086h

244Eh (ICH2)

02–03h

DID

Device ID

2448h (ICH2-M)

04–05h

06–07h

08h

CMD

PD_STS

REVID

PCI Device Command Register

PCI Device Status Register

Revision ID

0001h

0080h

See Note

04h

R/W

0Ah

SCC

Sub Class Code

0Bh

BCC

Base Class Code

06h

0Dh

PMLT

Primary Master Latency Timer

Header Type

00h

0Eh

HEADTYP

PBUS_NUM

SBUS_NUM

SUB_BUS_NUM

SMLT

01h

18h

Primary Bus Number

Secondary Bus Number

Subordinate Bus Number

Secondary Master Latency Timer

IO Base Register

00h

19h

00h

R/W

1Ah

00h

1Bh

00h

1Ch

IOBASE

IOLIM

F0h

1Dh

IO Limit Register

00h

1E–1Fh

20–21h

22–23h

SECSTS

MEMBASE

MEMLIM

Secondary Status Register

Memory Base

0280h

FFF0h

0000h

Memory Limit

PREF_MEM_BAS

24–25h

Prefetchable Memory Base

0000h

26–27h

30–31h

32–33h

PREF_MEM_MLT Prefetchable Memory Limit

0000h

IOBASE_HI

IOLIMIT_HI

I/O Base Upper 16 Bits

I/O Limit Upper 16 Bits

82801BA ICH2 and 82801BAM ICH2-M Datasheet

8-1

Hub Interface to PCI Bridge Registers (D30:F0)

Table 8-1. PCI Configuration Map (HUB-PCI—D30:F0) (Continued)

Offset

Mnemonic

Interrupt Line

Default

Type

3Ch

3E–3Fh

40h

INT_LINE

BRIDGE_CNT

BRIDGE_CNT2

CNF

00h

0000h

Bridge Control

R/W

Bridge Control 2

50–51h

70h

ICH2 Configuration Register

Multi-Transaction Timer

PCI Master Status

0000h

20h

MTT

82h

PCI_MAST_STS

ERR_CMD

ERR_STS

00h

90h

Error Command Register

Error Status Register

00h

92h

00h

NOTE: Refer to the Specification Update for the value of the Revision ID Register

8.1.1

8.1.2

VID—Vendor ID Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

00–01h

8086h

Attribute:

Size:

16 bits

Bit

Description

15:0

Vendor Identification Number—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.

DID—Device ID Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

02–03h

Attribute:

Size:

16 bits

244Eh (82801BA ICH2)

2448h (82801BAM ICH2-M)

Bit

Description

Device Identification Number—RO. This is a 16 bit value assigned to the ICH2 hub interface to

PCI bridge (i.e., Device #2).

15:0

8-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.3

CMD—Command Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

04–05h

0001h

Attribute:

Size:

R/W

16 bits

Bit

Description

15:10

Reserved.

Fast Back to Back Enable (FBE)—RO. Hardwired to 0. The ICH2 does not support this capability.

SERR# Enable (SERR_EN)—R/W.

1 = Enable the ICH2 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit

(offset 06h, bit 14) is set.

0 = Disable.

Wait Cycle Control—RO. Hardwired to 0

.Parity Error Response—R/W.

1 = The ICH2 is allowed to report parity errors detected on the hub interface.

0 = The ICH2 will ignore parity errors on the hub interface.

VGA Palette Snoop—RO. Hardwired to 0.

Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.

Special Cycle Enable (SCE)—RO. Hardwired to 0 by P2P Bridge specification.

Bus Master Enable (BME)—R/W.

1 = Allows the Hub interface-to-PCI bridge to accept cycles from PCI to run on the hub interface.

Note: This bit does not affect the CF8h and CFCh I/O accesses.

0 = Disable

Memory Space Enable (MSE)—R/W. The ICH2 provides this bit as read/writable for software only.

However, the ICH2 ignores the programming of this bit, and runs hub interface memory cycles to

PCI.

I/O Space Enable (IOE)—R/W. The ICH2 provides this bit as read/writable for software only.

However, the ICH2 ignores the programming of this bit and runs hub interface I/O cycles to PCI that

are not intended for USB, IDE, or AC’97.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

8-3

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.4

PD_STS—Primary Device Status Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

06–07h

0080h

Attribute:

Size:

R/WC

16 bits

For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no

effect.

Bit

Description

Detected Parity Error (DPE)—R/WC.

1 = Indicates that the ICH2 detected a parity error on the hub interface. This bit gets set even if the

Parity Error Response bit (offset 04, bit 6) is not set.

0 = Software clears this bit by writing a 1 to the bit location.

Received System Error (SSE)—R/WC.

1 = An address, or command parity error, or special cycles data parity error has been detected on

the PCI bus, and the Parity Error Response bit (D30:F0, Offset 04h, bit 6) is set. If this bit is set

because of parity error and the D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the ICH2

will generate an NMI (or SMI# if NMI routed to SMI#)

0 = Software clears this bit by writing a 1 to the bit location.

Received Master Abort (RMA)—R/WC.

1 = ICH2 received a master abort from the hub interface device.

0 = Software clears this bit by writing a 1 to the bit location.

Received Target Abort (RTA)—R/WC.

1 = ICH2 received a target abort from the hub interface device. The TCO logic can cause an SMI#,

NMI, or interrupt based on this bit getting set.

0 = Software clears this bit by writing a 1 to the bit location.

Signaled Target Abort (STA)—R/WC.

1 = ICH2 signals a target abort condition on the hub interface.

0 = Software clears this bit by writing a 1 to the bit location.

DEVSEL# Timing Status—RO.

10:9

00h = Fast timing. This register applies to the hub interface; therefore, this field does not matter.

Data Parity Error Detected (DPD)—R/WC. Since this register applies to the hub interface, the

ICH2 must interpret this bit differently than it is in the PCI specification.

1 = ICH2 detects a parity error on the hub interface and the Parity Error Response bit in the

Command Register (offset 04h, bit 6) is set.

0 = Software clears this bit by writing a 1 to the bit location.

Fast Back to Back—RO. Hardwired to 1.

User Definable Features (UDF)—RO. Hardwired to 0.

66 MHz Capable—RO. Hardwired to 0.

Reserved.

4:0

8.1.5

REVID—Revision ID Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

08h

Attribute:

Size:

8 bits

See bit description

Bit

Description

Revision Identification Number—RO. 8-bit value that indicates the revision number for the ICH2

hub interface to PCI bridge. Refer to the Specification Update for the value of the Revision ID

7:0

8-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.6

8.1.7

8.1.8

SCC—Sub-Class Code Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

0Ah

04h

Attribute:

Size:

8 bits

Bit

Description

Sub-Class Code—RO. This 8-bit value indicates the category of bridge for the ICH2 hub interface to

PCI bridge. The code is 04h indicating a PCI-to-PCI bridge.

7:0

BCC—Base-Class Code Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

0Bh

06h

Attribute:

Size:

8 bits

Bit

Description

Base Class Code—RO. This 8-bit value indicates the type of device for the ICH2 hub interface to PCI

bridge. The code is 06h indicating a bridge device.

7:0

PMLT—Primary Master Latency Timer Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

0Dh

00h

Attribute:

Size:

8 bits

This register does not apply to hub interface.

Bit

Description

7:3

2:0

Master Latency Count. Not implemented.

Reserved.

8.1.9

HEADTYP—Header Type Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

0Eh

01h

Attribute:

Size:

8 bits

Bit

Description

Multi-function Device—RO. This bit is 0 to indicate a single function device.

Header Type—RO. 8-bit field identifies the header layout of the configuration space, which is a PCI-

to-PCI bridge in this case.

6:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

8-5

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.10

PBUS_NUM—Primary Bus Number Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

18h

00h

Attribute:

Size:

8 bits

Bit

Description

Primary Bus Number—RO. This field indicates the bus number of the hub interface and is hardwired

to 00h.

7:0

8.1.11

SBUS_NUM—Secondary Bus Number Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

19h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Secondary Bus Number—R/W. This field indicates the bus number of PCI. Note that when this

number is equal to the primary bus number (i.e., bus #0), the ICH2 will run hub interface configuration

cycles to this bus number as Type 1 configuration cycles on PCI.

7:0

8.1.12

SUB_BUS_NUM—Subordinate Bus Number Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Subordinate Bus Number—R/W. This field specifies the highest PCI bus number below the hub

interface to PCI bridge. If a Type 1 configuration cycle from the hub interface does not fall in the

Secondary-to-Subordinate Bus ranges of Device 30, the ICH2 indicates a master abort back to the

hub interface.

7:0

8.1.13

SMLT—Secondary Master Latency Timer Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

1Bh

00h

Attribute:

Size:

R/W

8 bits

This Master Latency Timer (MLT) controls the amount of time that the ICH2 continues to burst

data as a master on the PCI bus. When the ICH2 starts the cycle after being granted the bus, the

counter is loaded and starts counting down from the assertion of FRAME#. If the internal grant to

this device is removed, then the expiration of the MLT counter results in the deassertion of

FRAME#. If the internal grant has not been removed, the ICH2 can continue to own the bus.

Bit

Description

Master Latency Count—R/W. This 5-bit value indicates the number of PCI clocks, in 8-clock

increments, that the ICH2 remains as master of the bus.

7:3

2:0

Reserved.

8-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.14

IOBASE—I/O Base Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

1Ch

F0h

Attribute:

Size:

R/W

8 bits

Bit

Description

I/O Address Base bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4 KB

alignment. Bits 11:0 are assumed to be padded to 000h.

7:4

3:0

I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface to PCI

bridge does not support 32-bit I/O addressing. This means that the I/O Base Register and I/O Limit

Upper Address registers must be read only.

8.1.15

IOLIM—I/O Limit Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

1Dh

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

I/O Address Limit bits [15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4 KB

alignment. Bits 11:0 are assumed to be padded to FFFh.

7:4

3:0

I/O Addressing Capability—RO. This is hardwired to 0h, indicating that the hub interface-to-PCI

bridge does not support 32-bit I/O addressing. This means that the I/O Base Register and I/O Limit

Upper Address registers must be read only.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

8-7

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.16

SECSTS—Secondary Status Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

1E–1Fh

0280h

Attribute:

Size:

R/W

16 bits

For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no

effect.

Bit

Description

Detected Parity Error (DPE)—R/WC.

1 = ICH2 detected a parity error on the PCI bus.

0 = Software clears this bit by writing a 1 to the bit position.

Received System Error (SSE)—R/WC.

1 = SERR# assertion is received on PCI.

0 = Software clears this bit by writing a 1 to the bit position.

Received Master Abort (RMA)—R/WC.

1 = Hub interface to PCI cycle is master-aborted on PCI.

0 = Software clears this bit by writing a 1 to the bit position.

Received Target Abort (RTA)—R/WC.

1 = Hub interface to PCI cycle is target-aborted on PCI. For “completion required” cycles from the

hub interface, this event should also set the Signaled Target Abort in the Primary Status

interface.

0 = Software clears this bit by writing a 1 to the bit position.

Signaled Target Abort (STA)—RO. The ICH2 does not generate target aborts.

DEVSEL# Timing Status—RO.

01h = Medium timing.

10:9

Data Parity Error Detected (DPD)—R/WC.

1 = The ICH2 sets this bit when all of the following three conditions are met:

- The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is set

- USB, AC’97 or IDE is a Master

- PERR# asserts during a write cycle OR a parity error is detected internally during a read cycle

0 = Software clears this bit by writing a 1 to the bit position.

Fast Back to Back—RO. Hardwired to 1 to indicate that the PCI to hub interface target logic is

capable of receiving fast back-to-back cycles.

User Definable Features (UDF)—RO. Hardwired to 0.

66 MHz Capable—RO. Hardwired to 0.

Reserved.

4:0

8-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.17

8.1.18

8.1.19

MEMBASE—Memory Base Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

20–21h

FFF0h

Attribute:

Size:

R/W

16 bits

This register defines the base of the hub interface to PCI non-prefetchable memory range. Since the

ICH2 forwards all hub interface memory accesses to PCI, the ICH2 only uses this information for

determining when not to accept cycles as a target.

This register must be initialized by the configuration software. For the purpose of address decode,

address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range

will be aligned to a 1 MB boundary.

Bit

Description

Memory Address Base—R/W. Defines the base of the memory range for PCI. These 12 bits

correspond to address bits 31:20.

15:4

3:0

Reserved.

MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

22–23h

0000h

Attribute:

Size:

R/W

16 bits

This register defines the upper limit of the hub interface to PCI non-prefetchable memory range.

Since the ICH2 will forward all hub interface memory accesses to PCI, the ICH2 will only use this

information for determining when not to accept cycles as a target.

This register must be initialized by the configuration software. For the purpose of address decode,

address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range

will be aligned to a 1 MB boundary.

Bit

Description

Memory Address Limit—R/W. Defines the top of the memory range for PCI. These 12 bits

correspond to address bits 31:20.

15:4

3:0

Reserved.

PREF_MEM_BASE—Prefetchable Memory Base Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

24h–25h

0000FFF0h

Attribute:

Size:

R/W

16-bit

Bit

Description

Prefetchable Memory Address Base—R/W. Defines the base address of the prefetchable memory

address range for PCI. These 12 bits correspond to address bits 31:20.

15:4

3:0

Reserved. RO.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

8-9

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.20

PREF_MEM_MLT—Prefetchable Memory Limit Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

26h–27h

00000000h

Attribute:

Size:

R/W

16-bit

Bit

Description

Prefetchable Memory Address Limit—RW. Defines the limit address of the prefetchable memory

address range for PCI. These 12 bits correspond to address bits 31:20.

15:4

3:0

Reserved. RO

8.1.21

8.1.22

8.1.23

IOBASE_HI—I/O Base Upper 16 Bits Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

30–31h

0000h

Attribute:

Size:

16 bits

Bit

Description

15:0

I/O Address Base Upper 16 bits [31:16]—RO. Not supported; hardwired to 0.

IOLIM_HI—I/O Limit Upper 16 Bits Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

32–33h

0000h

Attribute:

Size:

16 bits

Bit

Description

15:0

I/O Address Limit Upper 16 bits [31:16]—RO. Not supported; hardwired to 0.

INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

3Ch

00h

Attribute:

Size:

8 bits

Bit

Description

Interrupt Line Routing—RO. Hardwired to 00h. The bridge does not generate interrupts, and

interrupts from downstream devices are routed around the bridge.

7:0

8-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.24

BRIDGE_CNT—Bridge Control Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

3E–3Fh

0000h

Attribute:

Size:

R/W

16 bits

Bit

Description

15:8 Reserved.

Fast Back to Back Enable—RO. Hardwired to 0. The PCI logic will not generate fast back-to-back

cycles on the PCI bus.

Secondary Bus Reset—RO. hardwired to 0. The ICH2 does not follow the P2P bridge reset scheme;

Software-controlled resets are implemented in the PCI-LPC device.

Master Abort Mode—R/W. The ICH2 ignores this bit. However, this bit is read/write for software

compatibility. The ICH2 must handle master aborts as if this bit is reset to 0.

Reserved.

VGA Enable—R/W.

1 = Enable. Indicates that the VGA device is on PCI. Therefore, the PCI to hub interface decoder will

not accept memory cycles in the range A0000h–BFFFFh. Note that the ICH2 will never take I/O

cycles in the VGA range from PCI.

0 = No VGA device on PCI.

ISA Enable—R/W. The ICH2 ignores this bit. However, this bit is read/write for software compatibility.

Since the ICH2 forwards all I/O cycles that are not in the USB, AC’97, or IDE ranges to PCI, this bit

would have no effect.

SERR# Enable—R/W.

1 = Enable. If this bit is set AND bit 8 in CMD register (D30:F0 Offset 04h) is also set, the ICH2 sets

the SSE bit in PD_STS register (D30:F0, offset 06h, bit 14) AND also generate an NMI (or SMI#

if NMI routed to SMI) when the SERR# signal is asserted.

0 = Disable

Parity Error Response Enable—R/W.

1 = Enable the hub interface to PCI bridge for parity error detection and reporting on the PCI bus.

0 = Disable

8.1.25

BRIDGE_CNT2—Bridge Control Register 2

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

40h

00h

Attribute:

Size

R/W

8 bits

Bit

Description

7:1

Reserved

PCI_DAC_EN—R/W. Allows ICH2 to recognize external PCI masters performing DAC on PCI.

0 = Disable.

1 = Enable.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

8-11

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.26

CNF—ICH2 Configuration Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

50–51h

0000h

Attribute:

Size:

R/W

16 bits

Bit

Description

15:10

Reserved.

HP_PCI_EN—R/W. High Priority PCI Enable.

1 = Enables a mode where the REQ[0]#/GNT[0]# signal pair has a higher arbitration priority.

0 = All PCI REQ#/GNT pairs have the same arbitration priority.

Hole Enable (15 MB–16 MB)—R/W.

1 = Enables the 15 MB to 16 MB hole in the DRAM.

0 = Disable

7:3

Reserved.

Discard Timer Mode. This bit shortens all of the Delayed Transaction discard timers to 128 PCI

clocks. It controls how long the ICH2-M will wait before flushing previously requested prefetched

read data due to a Delayed Transaction, and then servicing a different request.

0 = 1024 PCI clocks (32 us) (Default).

1 = 128 PCI clocks (4 us).

32-Clock Retry Enable—R/W. System BIOS must set this bit for PCI compliance.

1 = When a PCI device is running a locked memory read cycle, while all other bus masters are

waiting to run locked cycles, concurrent with a LPC DMA transfer, this bit, when set allows the

ICH2 to retry the locked memory read cycle.

0 = If this bit is not set, under the same circumstance, the bus will not be released since all other

masters see the lock in use.

Reserved.

8.1.27

MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

70h

20h

Attribute:

Size:

R/W

8 bits

MTT is an 8-bit register that controls the amount of time that the ICH2’s arbiter allows a PCI

initiator to perform multiple back-to-back transactions on the PCI bus. The ICH2’s MTT

mechanism is used to guarantee a fair share of the Primary PCI bandwidth to an initiator that

performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence

it can not use long burst transfers).

The number of clocks programmed in the MTT represents the guaranteed time slice (measured in

PCI clocks) allotted to the current agent, after which the arbiter grants another agent that is

requesting the bus. The MTT value must be programmed with 8 clock granularity in the same

manner as MLT. For example, if the MTT is programmed to 18h, the selected value corresponds to

the time period of 24 PCI clocks.The default value of MTT is 20h (32 PCI clocks).

Note: Programming the MTT to a value of 00h disables this function, which could cause starvation issues

for some PCI master devices. Programming of the MTT to anything less than 16 clocks will not

allow the Grant-to-FRAME# latency to be 16 clocks. The MTT timer will time-out before the

Grant-to-FRAME# trigger causing a re-arbitration.

Bit

Description

Multi-Transaction Timer Count Value—R/W. This field specifies the amount of time that grant

remains asserted to a master continuously asserting its request for multiple transfers. This field

specifies the count in an 8-clock (PCI clock) granularity.

7:3

2:0

Reserved.

8-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.28

PCI_MAST_STS—PCI Master Status Register

(HUB-PCI—D30:F0)

Offset Address:

Default Value:

82h

00h

Attribute:

Size:

R/WC

8 bits

Bit

Description

Internal PCI Master Request Status (INT_MREQ_STS)—R/WC.

1 = The ICH2’s internal DMA controller or LPC has requested use of the PCI bus.

0 = Software clears this bit by writing a 1 to the bit position.

Internal LAN Master Request Status (LAN_MREQ_STS)—R/WC.

1 = The ICH2’s internal LAN controller has requested use of the PCI bus.

0 = Software clears this bit by writing a 1 to the bit position.

PCI Master Request Status (PCI_MREQ_STS)—R/WC. Allows software to see if a particular bus

master has requested use of the PCI bus. For example, bit 0 will be set if ICH2 has detected

REQ[0]# asserted and bit 5 will be set if ICH2 detected REQ[5]# asserted.

5:0

1 = The associated PCI master has requested use of the PCI bus.

0 = Software clears these bits by writing a 1 to the bit position.

8.1.29

ERR_CMD—Error Command Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

Lockable:

90h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

This register configures the ICH2’s Device 30 responses to various system errors. The actual

assertion of the internal SERR# (routed to cause NMI# or SMI#) is enabled via the PCI Command

Bit

Description

7:3

Reserved.

SERR# enable on receiving target abort (SERR_RTA_EN)—R/W.

1 = Enable. When SERR_EN is set, the ICH2 will report SERR# when SERR_RTA is set.

0 = Disable

SERR# enable on Delayed Transaction Time-out (SERR_DTT_EN)—R/W.

1 = Enable. When SERR_EN is set, the ICH2 will report SERR# when SERR_DTT is set.

0 = Disable.

Reserved.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

8-13

Hub Interface to PCI Bridge Registers (D30:F0)

8.1.30

ERR_STS—Error Status Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

Lockable:

92h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

This register records the cause of system errors in Device 30. The actual assertion of SERR# is

enabled via the PCI Command register.

Bit

Description

7:3

Reserved.

SERR# Due to Received Target Abort (SERR_RTA)—R/W.

1 = The ICH2 sets this bit when the ICH2 receives a target abort. If SERR_EN, the ICH2 will also

generate an SERR# when SERR_RTA is set.

0 = This bit is cleared by writing a 1.

SERR# Due to Delayed Transaction Time-out (SERR_DTT)—R/W.

1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH2

clears the delayed transaction, and sets this bit. If both SERR_DTT_EN and SERR_EN are

set, then ICH2 will also generate an SERR# when SERR_DTT is set.

0 = This bit is cleared by writing a 1.

Reserved.

8-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

LPC Interface Bridge Registers

(D31:F0)

The LPC Bridge function of the ICH2 resides in PCI Device 31:Function 0. This function contains

many other functional units (e.g., DMA and Interrupt Controllers, Timers, Power Management,

System Management., GPIO, RTC, and LPC Configuration Registers).

Registers and functions associated with other functional units (power management, GPIO, USB,

IDE, etc.) are described in their respective sections.

9.1

PCI Configuration Registers (D31:F0)

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

Table 9-1. PCI Configuration Map (LPC I/F—D31:F0)

Offset

Mnemonic

Default

Type

00h–01h

VID

Vendor ID

Device ID

8086h

2440h (ICH2)

02h–03h

DID

244Ch (ICH2-M)

04h–05h

06h–07h

08h

PCICMD

PCISTS

RID

PCI Command Register

PCI Device Status Register

Revision ID

000Fh

0280h

See Note

00h

R/W

09h

Programming Interface

Sub Class Code

0Ah

SCC

01h

0Bh

BCC

Base Class Code

06h

0Eh

HEADT

Header Type

80h

40h–43h

44h

PMBASE

ACPI_CNTL

BIOS_CNTL

TCO_CNTL

GPIO_BASE

GPIO_CNTL

ACPI Base Address Register

ACPI Control

00000001h

00h

R/W

4Eh–4Fh

54h

BIOS Control Register

TCO Control

0000h

00h

58h–5Bh

5Ch

GPIO Base Address Register

GPIO Control Register

00000001h

00h

60h–63h

64h

PIRQ[n]_ROUT PIRQ[A–D] Routing Control

SIRQ_CNTL Serial IRQ Control Register

80808080h

10h

68h–6Bh

88h

PIRQ[n]_ROUT PIRQ[E–H] Routing Control

80808080h

00h

D31_ERR_CFG Device 31 Error configuration Register

D31_ERR_STS Device 31 Error Status Register

8Ah

00h

90h–91h

PCI_DMA_C

PCI DMA Configuration Registers

0000h

Power Management Registers

See Section 9.8.1

A0h–CFh

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-1

LPC Interface Bridge Registers (D31:F0)

Table 9-1. PCI Configuration Map (LPC I/F—D31:F0) (Continued)

Offset

Mnemonic

General Control

Default

Type

D0h–D3h

D4h–D7h

D8h

GEN_CNTL

GEN_STS

00000000h

00000F00h

00h

R/W

General Status

RTC_CONF

COM_DEC

LPCFDD_DEC

SND_DEC

Real Time Clock Configuration

LPC I/F COM Port Decode Ranges

LPC I/F FDD & LPT Decode Ranges

LPC I/F Sound Decode Ranges

E0h

00h

E1h

00h

E2h

00h

E3h

FWH_DEC_EN1 FWH Decode Enable 1

FFh

E4h–E5h

E6h–E7h

E8h–EBh

ECh–EDh

EEh–EFh

F0h

GEN1_DEC

LPC_EN

LPC I/F General 1 Decode Range

0000h

00h

LPC I/F Enables

FWH_SEL1

GEN2_DEC

FWH_SEL2

FWH Select 1

00112233h

0000h

5678h

0Fh

LPC I/F General 2 Decode Range

FWH Select 2

FWH_DEC_EN2 FWH Decode Enable 2

FUNC_DIS Function Disable Register

F2h

00h

NOTE: Refer to the Specification Update for the value of the Revision ID Register.

9.1.1

9.1.2

VID—Vendor ID Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

00–01h

8086h

Attribute:

Size:

Power Well:

16-bit

Core

Bit

Description

15:0

Vendor ID Value. This is a 16 bit value assigned to Intel. Intel VID = 8086h

DID—Device ID Register (LPC I/F—D31:F0)

Offset Address:

Lockable:

02–03h

Attribute:

Size:

Power Well:

16-bit

Core

Default Value:

2440h (82801BA ICH2)

244Ch (82801BAM ICH2-M)

Bit

Description

15:0

Device ID Value. This is a 16 bit value assigned to the ICH2 LPC Bridge.

9-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.3

PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

04–05h

000Fh

Attribute:

Size:

Power Well:

R/W

16-bit

Core

Bit

Description

15:10

Reserved.

Fast Back to Back Enable (FBE)—RO. Hardwired to 0.

SERR# Enable (SERR_EN)—R/W.

1 = Enable. Allow SERR# to be generated.

0 = Disable.

Wait Cycle Control (WCC)—RO. Hardwired to 0.

Parity Error Response (PER)—R/W.

1 = The ICH will take normal action when a parity error is detected.

0 = No action is taken when detecting a parity error.

VGA Palette Snoop (VPS)—RO. Hardwired to 0

Postable Memory Write Enable (PMWE)—RO. Hardwired to 0

Special Cycle Enable (SCE). Hardwired to 1.

Bus Master Enable (BME)—RO. Hardwired to 1 to indicate that bus mastering can not be disabled

for function 0 (DMA/ISA Master).

Memory Space Enable (MSE)—RO. Hardwired to 1 to indicate that memory space can not be

disabled for Function 0 (LPC I/F).

I/O Space Enable (IOE)—RO. Hardwired to 1 to indicate that the I/O space cannot be disabled for

function 0 (LPC I/F).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-3

LPC Interface Bridge Registers (D31:F0)

9.1.4

PCISTS—PCI Device Status (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

06–07h

0280h

Attribute:

Size:16-bit

Power Well:

R/WC

Core

Bit

Description

Detected Parity Error (DPE)—R/W.

1 = PERR# signal goes active. Set even if the PER bit is 0.

0 = This bit is cleared by software writing a 1 to the bit position.

Signaled System Error (SSE)—R/W.

1 = Set by the ICH2 if the SERR_EN bit is set and the ICH2 generates an SERR# on function 0. The

ERR_STS register can be read to determine the cause of the SERR#. The SERR# can be routed

to cause SMI#, NMI, or interrupt.

0 = This bit is cleared by software writing a 1 to the bit position.

Master Abort Status (RMA)—R/W.

1 = ICH2 generated a master abort on PCI due to LPC I/F master or DMA cycles.

0 = This bit is cleared by software writing a 1 to the bit position.

Received Target Abort (RTA)—R/W.

1 = ICH2 received a target abort during LPC I/F master or DMA cycles to PCI.

0 = This bit is cleared by software writing a 1 to the bit position.

Signaled Target Abort (STA)—R/W.

1 = ICH2 generated a target abort condition on PCI cycles claimed by the ICH2 for ICH2 internal

registers or for going to LPC I/F.

0 = This bit is cleared by software writing a 1 to the bit position.

DEVSEL# Timing Status (DEV_STS)—RO.

10:9

01 = Medium Timing.

Data Parity Error Detected (DPED)—R/WC.

1 = Set when all three of the following conditions are true:

- The ICH2 is the initiator of the cycle,

- The ICH2 asserted PERR# (for reads) or observed PERR# (for writes), and

- The PER bit is set.

0 = This bit is cleared by software writing a 1 to the bit position.

Fast Back to Back (FB2B)—RO. Always 1. Indicates ICH2 as a target can accept fast back-to-back

transactions.

User Definable Features (UDF). Hardwired to 0

66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0

Reserved.

4:0

9.1.5

REVID—Revision ID Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

08h

Attribute:

Size:

8 bits

See bit description

Bit

Description

Revision Identification Number. 8-bit value that indicates the revision number for the LPC bridge.

For the A-0 stepping, this value is 00h. Refer to the Specification Update for the value of the Revision

ID Register

7:0

9-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.6

9.1.7

9.1.8

PI—Programming Interface (LPC I/F—D31:F0)

Offset Address:

Default Value:

09h

00h

Attribute:

Size:

8 bits

Bit

Description

7:0

Programming Interface Value.

SCC—Sub-Class Code Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

0Ah

01h

Attribute:

Size:

8 bits

Bit

Description

7:0

Sub-Class Code. This 8-bit value indicates the category of bridge for the LPC PCI bridge.

BCC—Base-Class Code Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

0Bh

06h

Attribute:

Size:

8 bits

Bit

Description

Base Class Code. This 8-bit value indicates the type of device for the LPC bridge. The code is 06h

indicating a bridge device.

7:0

9.1.9

HEADTYP—Header Type Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

0Eh

80h

Attribute:

Size:

8 bits

Bit

Description

Multi-function Device—RO. This bit is 1 to indicate a multi-function device.

6:0

Header Type—RO. This 8-bit field identifies the header layout of the configuration space.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-5

LPC Interface Bridge Registers (D31:F0)

9.1.10

PMBASE—ACPI Base Address (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

40–43h

00000001h

Attribute:

Size:

Usage:

R/W

32-bit

ACPI, Legacy

Core

Power Well:

Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. Can be mapped

anywhere in the 64 KB I/O space on 128-byte boundaries.

Bit

Description

31:16

Reserved.

Base Address—R/W. Provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is

placed on a 128-byte boundary.

15:7

6:1

Reserved.

Resource Indicator—RO. Tied to 1 to indicate I/O space.

9.1.11

ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

44h

00h

Attribute:

Size:

Usage:

R/W

8-bit

ACPI, Legacy

Core

Power Well:

Bit

Description

7:5

Reserved.

ACPI Enable (ACPI_EN)—R/W.

1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power

management function is enabled. Note that the APM power management ranges (B2/B3h) are

always enabled and are not affected by this bit.

0 = Disable.

Reserved.

SCI IRQ Select (SCI_IRQ_SEL)—R/W. Specifies on which IRQ the SCI will internally appear. If not

using the APIC, the SCI must be routed to IRQ[9:11], and that interrupt is not sharable with the

SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be

mapped to IRQ[20:23], and can be shared with other interrupts.

000 = IRQ9

001 = IRQ10

2:0

010 = IRQ11

011 = Reserved

100 = IRQ20 (Only available if APIC enabled)

101 = IRQ21 (Only available if APIC enabled)

110 = RQ22 (Only available if APIC enabled)

111 = IRQ23 (Only available if APIC enabled)

9-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.12

BIOS_CNTL (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

4E–4Fh

0000h

Attribute:

Size:

Power Well:

R/W

16-bit

Core

Bit

Description

15:2

Reserved.

BIOS Lock Enable (BLE)—R/W.

1 = Enables setting the BIOSWE bit to cause SMIs.

0 = Setting the BIOSWE will not cause SMIs. Once set, this bit can only be cleared by a

PCIRST#.

BIOS Write Enable (BIOSWE)—R/W.

1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written

from a 0 to a 1 and BIOS lock Enable (BLE) is also set, an SMI# is generated. This ensures

that only SMM code can update BIOS.

0 = Only read cycles result in FWH interface cycles.

9.1.13

TCO_CNTL—TCO Control (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

54h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:4

Reserved.

TCO Interrupt Enable (TCO_INT_EN)—R/W. This bit enables/disables the TCO interrupt.

1 = Enables TCO Interrupt, as selected by the TCO_INT_SEL field.

0 = Disables TCO interrupt.

TCO Interrupt Select (TCO_INT_SEL)—R/W. Specifies which IRQ the TCO internally appears. If

not using the APIC, the TCO interrupt must be routed to IRQ[9:11], and that interrupt is not

sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the

TCO interrupt can also be mapped to IRQ[20:23], and can be shared with other interrupt. Note that

if the TCOSCI_EN bit is set (bit 6 in the GPE0_EN register), then the TCO interrupt will be sent to

the same interrupt as the SCI, and the TCO_INT_SEL bits will have no meaning. When the TCO

interrupt is mapped to APIC interrupts 10 or 11, the signal is, in fact, active high. When the TCO

interrupt is mapped to IRQ[20, 21, or 22], the signal is active low and can be shared with PCI

interrupts that may be mapped to the same signals (IRQs).

2:0

000 = IRQ9

001 = IRQ10

010 = IRQ11

011 = Reserved

100 = IRQ20 (Only available if APIC enabled)

101 = IRQ21 (Only available if APIC enabled)

110 = IRQ22 (Only available if APIC enabled)

111 = IRQ23 (Only available if APIC enabled)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-7

LPC Interface Bridge Registers (D31:F0)

9.1.14

GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

58h–5Bh

00000001h

Attribute:

Size:

Power Well:

R/W

32-bit

Core

Bit

Description

31:16

15:6

5:1

Reserved.

Base Address—R/W. Provides the 64 bytes of I/O space for GPIO.

Reserved.

Resource Indicator—RO. Tied to 1 to indicate I/O space.

9.1.15

GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

5Ch

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:5

Reserved.

GPIO Enable (GPIO_EN)—R/W. This bit enables/disables decode of the I/O range pointed to by

the GPIO base register and enables/disables the GPIO function.

1 = Enable

0 = Disable

Reserved.

3:0

9.1.16

PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control

(LPC I/F—D31:F0)

Offset Address:

PIRQA–60h, PIRQB–61h,

PIRQC–62h, PIRQD–63h

Attribute:

R/W

Default Value:

Lockable:

80h

Size:

Power Well:

8-bit

Core

Bit

Description

Interrupt Routing Enable (IRQEN)—R/W. Note that BIOS must program this bit to 0 during POST

for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the

OS when setting up for I/O APIC interrupt delivery mode.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].

1 = The PIRQ is not routed to the 8259.

6:4

Reserved.

IRQ Routing—R/W. (ISA compatible)

0000 = Reserved

0001 = Reserved

0010 = Reserved

0011 = IRQ3

0100 = IRQ4

0101 = IRQ5

1000 = Reserved

1001 = IRQ9

1010 = IRQ10

1011 = IRQ11

1100 = IRQ12

1101 = Reserved

1110 = IRQ14

1111 = IRQ15

3:0

0110 = IRQ6

0111 = IRQ7

9-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.17

SERIRQ_CNTL—Serial IRQ Control (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

64h

10h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

Serial IRQ Enable (SIRQEN)—R/W.

1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.

0 = The buffer is input only and internally SERIRQ will be a 1.

Serial IRQ Mode Select (SIRQMD)—R/W. For systems using Quiet Mode, this bit should be set to 1

(Continuous Mode) for at least one frame after coming out of reset before switching back to Quiet

Mode. Failure to do so will result in the ICH2 not recognizing SERIRQ interrupts.

1 = The serial IRQ machine will be in continuous mode.

0 = The serial IRQ machine will be in quiet mode.

Serial IRQ Frame Size (SIRQSZ)—R/W. Fixed field that indicates the size of the SERIRQ frame. In

the ICH2, this field needs to be programmed to 21 frames (0100). This is an offset from a base of 17

which is the smallest data frame size.

5:2

Start Frame Pulse Width (SFPW)—R/W. This is the number of PCI clocks that the SERIRQ pin will

be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH2 will

drive the start frame for the number of clocks specified. In quiet mode, the ICH2 will drive the start

frame for the number of clocks specified minus one, as the first clock was driven by the peripheral.

1:0

00 = 4 clocks

01 = 6 clocks

10 = 8 clocks

11 = Reserved

9.1.18

PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control

(LPC I/F—D31:F0)

Offset Address:

PIRQE–68h, PIRQF–69h,

PIRQG–6Ah, PIRQH–6Bh

Attribute:

R/W

Default Value:

Lockable:

80h

Size:

Power Well:

8-bit

Core

Bit

Description

Interrupt Routing Enable (IRQEN)—R/W. Note that BIOS must program this bit to 0 during POST

for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the

OS when setting up for I/O APIC interrupt delivery mode.

0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].

1 = The PIRQ is not routed to the 8259.

6:4

Reserved.

IRQ Routing—R/W. (ISA compatible)

0000 = Reserved

0001 = Reserved

0010 = Reserved

0011 = IRQ3

1000 = Reserved

1001 = IRQ9

1010 = IRQ10

1011 = IRQ11

1100 = IRQ12

1101 = Reserved

1110 = IRQ14

1111 = IRQ15

3:0

0100 = IRQ4

0101 = IRQ5

0110 = IRQ6

0111 = IRQ7

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-9

LPC Interface Bridge Registers (D31:F0)

9.1.19

D31_ERR_CFG—Device 31 Error Configuration Register

(LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

88h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

This register configures the ICH2’s Device 31 responses to various system errors. The actual

assertion of SERR# is enabled via the PCI Command register

Bit

Description

7:3

Reserved.

SERR# on Received Target Abort Enable (SERR_RTA_EN)—R/W.

1 = The ICH2 will generate SERR# when SERR_RTA is set if SERR_EN is set.

0 = Disable. No SERR# assertion on Received Target Abort.

SERR# on Delayed Transaction Time-out Enable (SERR_DTT_EN)—R/W.

1 = The ICH2 will generate SERR# when SERR_DTT bit is set if SERR_EN is set.

0 = Disable. No SERR# assertion on Delayed Transaction Time-out.

Reserved

9.1.20

D31_ERR_STS—Device 31 Error Status Register

(LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

8Ah

00h

Attribute:

Size:

Power Well:

R/WC

8-bit

Core

This register configures the ICH2’s Device 31 responses to various system errors. The actual

assertion of SERR# is enabled via the PCI Command register.

Bit

Description

7:3

Reserved.

SERR# Due to Received Target Abort (SERR_RTA)—R/WC.

1 = The ICH2 sets this bit when it receives a target abort. If SERR_EN, the ICH2 will also generate

an SERR# when SERR_RTA is set.

0 = Software clears this bit by writing a 1 to the bit location.

SERR# Due to Delayed Transaction Time-out (SERR_DTT)—R/WC.

1 = When a PCI master does not return for the data within 1 ms of the cycle’s completion, the ICH2

clears the delayed transaction and sets this bit. If both SERR_DTT_EN and SERR_EN are set,

then ICH2 will also generate an SERR# when SERR_DTT is set.

0 = Software clears this bit by writing a 1 to the bit location.

Reserved.

9-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.21

PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

90h–91h

0000h

Attribute:

Size:

Power Well:

R/W

16-bit

Core

Bit

Description

Channel 7 Select—R/W.

00 = Reserved

15:14 01 = PC/PCI DMA

10 = Reserved

11 = LPC I/F DMA

13:12 Channel 6 Select—R/W. Same bit decode as for Channel 7

11:10 Channel 5 Select—R/W. Same bit decode as for Channel 7

9:8

7:6

5:4

3:2

1:0

Reserved.

Channel 3 Select—R/W. Same bit decode as for Channel 7

Channel 2 Select—R/W. Same bit decode as for Channel 7

Channel 1 Select—R/W. Same bit decode as for Channel 7

Channel 0 Select—R/W. Same bit decode as for Channel 7

9.1.22

GEN_CNTL—General Control Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

D0h–D3h

00000000h

Attribute:

Size:

Power Well:

R/W

32-bit

Core

Bit

Description

31:26

Reserved.

REQ[5]#/GNT[5]# PC/PCI protocol select (PCPCIB_SEL)—R/W.

1 = When this bit is set to a 1, the PCI REQ[5]#/GNT[5]# signal pair will use the PC/PCI protocol as

REQ[B]#/GNT[B]. The corresponding bits in the GPIO_USE_SEL register must also be set to a

0. If the corresponding bits in the GPIO_USE_SEL register are set to a 1, the signals will be

used as a GPI and GPO.

0 = The REQ[5]#/GNT[5]# pins will function as a standard PCI REQ/GNT signal pair.

Hide ISA Bridge (HIDE_ISA)—R/W.

1 = Software sets this bit to 1 to disable configuration cycle from being claimed by a PCI-to-ISA

bridge. This prevents the operating system PCI PnP from getting confused by seeing two ISA

bridges. It is required for the ICH2 PCI address line AD22 to connect to the PCI-to-ISA bridge’s

IDSEL input. When this bit is 1, the ICH2 does not assert AD22 during configuration cycles to

the PCI-to-ISA bridge.

0 = The ICH2 does not prevent AD22 from asserting during configuration cycles to the PCI-to-ISA

bridge.

23:14

Reserved.

Coprocessor Error Enable (COPR_ERR_EN)—R/W.

1 = When FERR# is low, ICH2 generates IRQ13 internally and holds it until an I/O write to port F0h.

It will also drive IGNNE# active.

0 = FERR# will not generate IRQ13 nor IGNNE#.

Keyboard IRQ1 Latch Enable (IRQ1LEN)—R/W.

1 = The active edge of IRQ1 will be latched and held until a port 60h read.

0 = IRQ1 will bypass the latch.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-11

LPC Interface Bridge Registers (D31:F0)

Bit

Description

Mouse IRQ12 Latch Enable (IRQ12LEN)—R/W.

1 = The active edge of IRQ12 will be latched and held until a port 60h read.

0 = IRQ12 will bypass the latch.

10:9

Reserved

APIC Enable (APIC_EN)—R/W.

1 = Enables the internal I/O (x) APIC and its address decode.

0 = Disables internal I/O (x) APIC.

Enables I/O (x) Extension Enable (XAPIC_EN)—R/W. Note that this bit is only valid if the

AIPC_EN bit (bit 8) is also set to 1.

1 = Enables the extra features (beyond standard I/O APIC) associated with the I/O (x) APIC.

0 = The I/O (x) APIC extensions are not supported.

Alternate Access Mode Enable (ALTACC_EN)—R/W.

1 = Alternate Access Mode Enable

0 = Alternate Access Mode Disabled (default). Alternate Access Mode allows reads to otherwise

unreadable registers and writes otherwise unwriteable registers.

5:3

Reserved.

DMA Collection Buffer Enable (DCB_EN)—R/W.

1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/PCI DMA.

0 = DCB disabled.

Delayed Transaction Enable (DTE)—R/W.

1 = ICH2 enables delayed transactions for internal register, FWH, and LPC interface accesses.

0 = Delayed transactions disabled.

Positive Decode Enable (POS_DEC_EN)—R/W.

1 = Enables ICH2 to only perform positive decode on the PCI bus.

0 = The ICH2 performs subtractive decode on the PCI bus and forward the cycles to LPC interface

if not to an internal register or other known target on the LPC interface. Accesses to internal

registers and to known LPC interface devices are still be positively decoded.

NOTES:

1. Rule 1: If bit 8 is 0, the ICH2 does not decode any of the registers associated with the I/O APIC or I/O (x)

APIC. The state of bit 7 is a “Don’t Care” in this case.

Rule 2: If bit 8 is 1 and bit 7 is 0, the ICH2 decodes the memory space associated with the I/O APIC, but not

the extra registers associated with the I/O (x) APIC.

Rule 3: If bit 8 is 1 and bit 7 is 1, the ICH2 decodes the memory space associated with both the I/O APIC and

the I/O (x) APIC. This also enables PCI masters to write directly to the register to cause interrupts (PCI

Message Interrupt).

Note that there is no separate way to disable PCI Message Interrupts if the I/O (x) APIC is enabled. This is

not considered necessary.

9-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.23

GEN_STS—General Status (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

D4h–D7h

00000F0Xh

Attribute:

Size:

Power Well:

R/W

32-bit

Core(0:7), RTC (8:15)

Bit

Description

31:14 Reserved.

TOP_SWAP—R/W.

1 = ICH2 will invert A16 for cycles targeting FWH BIOS space (Does not affect accesses to FWH

feature space).

0 = ICH2 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other type of

reset.

CPU BIST Enable (CPU_BIST_EN)—R/W. This bit is in the Resume Well and is reset by

RSMRST# (not in the RTC Well and not reset by RTEST#).

1 = The INIT# signal is driven active when CPURST# is active. INIT# goes inactive with the same

timings as the other processor interface signals (Hold Time after CPURST# inactive). Note that

CPURST# is generated by the memory controller hub; however, the ICH2 has a hub interface

special cycle that allows the ICH2 to control the assertion/deassertion of CPURST#.

0 = Disable.

Processor Frequency Strap (FREQ_STRAP[3:0])—R/W. These bits determine the internal

frequency multiplier of the processor. These bits can be reset to 1111 based on an external pin strap

or via the RTCRST# input signal. Software must program this field based on the processor’s

specified frequency. These bits are in the RTC well.

11:8

This field is only writeable when SAFE_MODE (bit 2) is cleared to 0. SAFE_MODE is only cleared

by a PWROK rising edge.

7:3

Reserved

SAFE_MODE—RO.

1 = ICH2 sampled AC_SDOUT high on the rising edge of PWROK. ICH2 will force

FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier).

0 = ICH2 sampled AC_SDOUT low on the rising edge of PWROK.

NO_REBOOT—R/W (special).

1 = ICH2 will disable the TCO Timer system reboot feature. This bit is set either by hardware when

SPKR is sampled low on the rising edge of PWROK or by software writing a 1 to the bit.

0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO time-out).

Note that this bit cannot be cleared while an external jumper is in place on the SPKR signal.

Reserved.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-13

LPC Interface Bridge Registers (D31:F0)

9.1.24

RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

D8h

00h

Yes

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:5

Reserved.

Upper 128-byte Lock (U128LOCK)—R/W (special).

1 = Lock reads and writes to bytes 38h–3Fh in the upper 128 byte bank of the RTC CMOS RAM.

Write cycles to this range will have no effect and read cycles will not return any particular

guaranteed value. This is a write once register that can only be reset by a hardware reset.

0 = Access to these bytes in the upper CMOS RAM range have not been locked.

Lower 128-byte Lock (L128LOCK)—R/W (special).

1 = Locks reads and writes to bytes 38h–3Fh in the lower 128 byte bank of the RTC CMOS RAM.

Write cycles to this range will have no effect and read cycles will not return any particular

guaranteed value. This is a write once register that can only be reset by a hardware reset.

0 = Access to these bytes in the lower CMOS RAM range have not been locked.

Upper 128-byte Enable (U128E)—R/W.

1 = Enables access to the upper 128 byte bank of RTC CMOS RAM.

0 = Disable.

Reserved.

1:0

9.1.25

COM_DEC—LPC I/F Communication Port Decode Ranges

(LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

E0h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

Reserved

COMB Decode Range—R/W. This field determines which range to decode for the COMB Port.

000 = 3F8h–3FFh (COM1)

001 = 2F8h–2FFh (COM2)

010 = 220h–227h

6:4

011 = 228h–22Fh

100 = 238h–23Fh

101 = 2E8h–2EFh (COM4)

110 = 338h–33Fh

111 = 3E8h–3EFh (COM3)

Reserved

COMA Decode Range—R/W. This field determines which range to decode for the COMA Port.

000 = 3F8h–3FFh (COM1)

001 = 2F8h–2FFh (COM2)

010 = 220h–227h

2:0

011 = 228h–22Fh

100 = 238h–23Fh

101 = 2E8h–2EFh (COM4)

110 = 338h–33Fh

111 = 3E8h–3EFh (COM3)

9-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.26

FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges

(LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

E1h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:5

Reserved

FDD Decode Range—R/W. Determines which range to decode for the FDD Port

0 = 3F0h–3F5h, 3F7h (Primary)

1 = 370h–2FFh (Secondary)

3:2

Reserved

LPT Decode Range—R/W. This field determines which range to decode for the LPT Port.

00 = 378h–37Fh and 778h–77Fh

1:0

01 = 278h–27Fh (port 279h is read only) and 678h–67Fh

10 = 3BCh–3BEh and 7BCh–7BEh

11 = Reserved

9.1.27

SND_DEC—LPC I/F Sound Decode Ranges

(LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

E2h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:6

5:4

Reserved

MSS Decode Range—R/W. This field determines which range to decode for the Microsoft* Sound

System (MSS).

00 = 530h–537h

01 = 604h–60Bh

10 = E80h–E87h

11 = F40h–F47h

MIDI Decode Range—R/W. This bit determines which range to decode for the Midi Port.

0 = 330h–331h

1 = 300h–301h

Reserved

SB16 Decode Range—R/W. This field determines which range to decode for the Sound Blaster 16

(SB16) Port.

00 = 220h–233h

01 = 240h–253h

10 = 260h–273h

11 = 280h–293h

1:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-15

LPC Interface Bridge Registers (D31:F0)

9.1.28

FWH_DEC_EN1—FWH Decode Enable 1 Register

(LPC I/F—D31:F0)

Offset Address:

Default Value:

E3h

FFh

Attribute:

Size:

R/W

8 bits

This register determines which memory ranges will be decoded on the PCI bus and forwarded to

the FWH. The ICH2 will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1.

Bit

Description

FWH Address Range Enable (FWH_F8_EN)—RO. Enables decoding two 512 KB FWH memory

ranges and one 128 KB memory range.

1 = Enable the following ranges for the FWH

FFF80000h–FFFFFFFFh

FFB80000h–FFBFFFFFh

000E0000h–000FFFFFh

FWH Address Range Enable (FWH_F0_EN)—R/W. Enables decoding two 512 KB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH:

FFF00000h–FFF7FFFFh

FFB00000h–FFB7FFFFh

FWH Address Range Enable (FWH_E8_EN)—R/W. Enables decoding two 512 KB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH:

FFE80000h–FFEFFFFh

FFA80000h–FFAFFFFFh

FWH Address Range Enable (FWH_E0_EN)—R/W. Enables decoding two 512 KB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH:

FFE00000h–FFE7FFFFh

FFA00000h–FFA7FFFFh

FWH Address Range Enable (FWH_D8_EN)—R/W. Enables decoding two 512 KB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FFD80000h–FFDFFFFFh

FF980000h–FF9FFFFFh

FWH Address Range Enable (FWH_D0_EN)—R/W. Enables decoding two 512 KB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FFD00000h–FFD7FFFFh

FF900000h–FF97FFFFh

FWH Address Range Enable (FWH_C8_EN)—R/W. Enables decoding two 512 KB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FFC80000h–FFCFFFFFh

FF880000h–FF8FFFFFh

FWH Address Range Enable (FWH_C0_EN)—R/W. Enables decoding two 512 KB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FFC00000h–FFC7FFFFh

FF800000h–FF87FFFFh

9-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.29

GEN1_DEC—LPC I/F Generic Decode Range 1

(LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

E4h–E5h

00h

Yes

Attribute:

Size:

Power Well:

R/W

16-bit

Core

Bit

Description

Generic I/O Decode Range 1 Base Address (GEN1_BASE)—R/W. This address is aligned on a

128-byte boundary, and must have address lines 31:16 as 0.

15:7

Note that this generic decode is for I/O addresses only, not memory addresses. The size of this

range is 128 bytes.

6:1

Reserved.

Generic Decode Range 1 Enable (GEN1_EN)—R/W.

0 = Disable.

1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F

9.1.30

LPC_EN—LPC I/F Enables (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

E6h–E7h

00h

Yes

Attribute:

Size:

Power Well:

R/W

16-bit

Core

Bit

Description

15:14

Reserved

Microcontroller Address Range Enable (CNF2_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used

for a microcontroller.

Super I/O Address Range Enable (CNF1_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used

for Super I/O devices.

Microcontroller Address Range Enable (MC_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used

for a microcontroller.

Microcontroller Address Range Enable (KBC_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used

for a microcontroller.

Game Port Address Range Enable (GAMEH_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is

used for a gameport.

Game Port Address Range Enable (GAMEL_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is

used for a gameport.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-17

LPC Interface Bridge Registers (D31:F0)

Bit

Description

ADLIB Address Range Enable (ADLIB_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the I/O locations 388h–38Bh to the LPC interface.

MSS Address Range Enable (MSS_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the MSS range to the LPC interface. This range is selected in the

LPC_Sound Decode Range Register.

MIDI Address Range Enable (MIDI_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the MIDI range to the LPC interface. This range is selected in the

LPC_Sound Decode Range Register.

Sound Blaster Address Range Enable (SB16_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the SB16 range to the LPC interface. This range is selected in the

LPC_Sound Decode Range Register.

FDD Address Range Enable (FDD_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the

LPC_FDD/LPT Decode Range Register.

LPT Address Range Enable (LPT_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the LPT range to the LPC interface. This range is selected in the

LPC_FDD/LPT Decode Range Register.

COM B Address Range Enable (COMB_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the

LPC_COM Decode Range Register.

Com A Address Range Enable (COMA_LPC_EN)—R/W.

0 = Disable.

1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the

LPC_COM Decode Range Register.

9-18

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.31

FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

E8h

00112233h

Attribute:

Size:

R/W

32 bits

Bit

Description

FWH Address Range Select (FWH_F8_IDSEL)—RO. IDSEL for two 512 KB FWH memory ranges

and one 128KB memory range. This field is fixed at 0000. The IDSEL in this field addresses the

following memory ranges:

FFF8 0000h–FFFF FFFFh

FFB8 0000h–FFBF FFFFh

000E 0000h–000F FFFFh

31:28

FWH Address Range Select (FWH_F0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory

ranges. The IDSEL programmed in this field addresses the following memory ranges:

FFF0 0000h–FFF7 FFFFh

27:24

23:20

19:16

15:12

11:8

FFB0 0000h–FFB7 FFFFh

FWH Address Range Select (FWH_E8_IDSEL)—R/W. IDSEL for two 512 KB FWH memory

ranges. The IDSEL programmed in this field addresses the following memory ranges:

FFE8 0000h–FFEF FFFFh

FFA8 0000h–FFAF FFFFh

FWH Address Range Select (FWH_E0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory

ranges. The IDSEL programmed in this field addresses the following memory ranges:

FFE0 0000h–FFE7 FFFFh

FFA0 0000h–FFA7 FFFFh

FWH Address Range Select (FWH_D8_IDSEL)—R/W. IDSEL for two 512 KB FWH memory

ranges. The IDSEL programmed in this field addresses the following memory ranges:

FFD8 0000h–FFDF FFFFh

FF98 0000h–FF9F FFFFh

FWH Address Range Select (FWH_D0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory

ranges. The IDSEL programmed in this field addresses the following memory ranges:

FFD0 0000h–FFD7 FFFFh

FF90 0000h–FF97 FFFFh

FWH Address Range Select (FWH_C8_IDSEL)—R/W. IDSEL for two 512 KB FWH memory

ranges. The IDSEL programmed in this field addresses the following memory ranges:

FFC8 0000h–FFCF FFFFh

7:4

FF88 0000h–FF8F FFFFh

FWH Address Range Select (FWH_C0_IDSEL)—R/W. IDSEL for two 512 KB FWH memory

ranges. The IDSEL programmed in this field addresses the following memory ranges:

FFC0 0000h–FFC7 FFFFh

3:0

FF80 0000h–FF87 FFFFh

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-19

LPC Interface Bridge Registers (D31:F0)

9.1.32

GEN2_DEC—LPC I/F Generic Decode Range 2

(LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

ECh–EDh

00h

Yes

Attribute:

Size:

Power Well:

R/W

16-bit

Core

Bit

Description

Generic I/O Decode Range 2 Base Address (GEN2_BASE)—R/W. This address is aligned on a

64-byte boundary and must have address lines 31:16 as 0.

15:4

Note that this generic decode is for I/O addresses only; not memory addresses. The size of this

range is 16 bytes.

3:1

Reserved. Read as 0

Generic I/O Decode Range 2 Enable (GEN2_EN)—R/W.

0 = Disable.

1 = Accesses to the GEN2 I/O range will be forwarded to the LPC interface.

9.1.33

FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

EEh–EFh

4567h

Attribute:

Size:

R/W

32 bits

Bit

Description

FWH Address Range Select (FWH_70_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF70 0000h–FF7F FFFFh

15:12

11:8

7:4

FF30 0000h–FF3F FFFFh

FWH Address Range Select (FWH_60_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF60 0000h–FF6F FFFFh

FF20 0000h–FF2F FFFFh

FWH Address Range Select (FWH_50_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF50 0000h–FF5F FFFFh

FF10 0000h–FF1F FFFFh

FWH Address Range Select (FWH_40_IDSEL)—R/W. IDSEL for two 1 MB FWH memory ranges.

The IDSEL programmed in this field addresses the following memory ranges:

FF40 0000h–FF4F FFFFh

3:0

FF00 0000h–FF0F FFFFh

9-20

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.1.34

FWH_DEC_EN2—FWH Decode Enable 2 Register

(LPC I/F—D31:F0)

Offset Address:

Default Value:

F0h

0Fh

Attribute:

Size:

R/W

8 bits

This register determines which memory ranges are decoded on the PCI bus and forwarded to the

FWH. The ICH2 subtractively decodes cycles on PCI unless POS_DEC_EN is set to 1.

Bit

Description

7:4

Reserved.

FWH Address Range Enable (FWH_70_EN)—R/W. Enables decoding two 1 MB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FF70 0000h–FF7F FFFFh

FF30 0000h–FF3F FFFFh

FWH Address Range Enable (FWH_60_EN)—R/W. Enables decoding two 1 MB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FF60 0000h–FF6F FFFFh

FF20 0000h–FF2F FFFFh

FWH Address Range Enable (FWH_50_EN)—R/W. Enables decoding two 1 MB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FF50 0000h–FF5F FFFFh

FF10 0000h–FF1F FFFFh

FWH Address Range Enable (FWH_40_EN)—R/W. Enables decoding two 1 MB FWH memory

ranges.

0 = Disable.

1 = Enable the following ranges for the FWH

FF40 0000h–FF4F FFFFh

FF00 0000h–FF0F FFFFh

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-21

LPC Interface Bridge Registers (D31:F0)

9.1.35

FUNC_DIS—Function Disable Register (LPC I/F—D31:F0)

Offset Address:

Default Value:

Lockable:

F2h

00h

Attribute:

Size:

Power Well:

R/W

16-bit

Core

Bit

Description

15:9

Reserved

SMBus For BIOS (SMB_FOR_BIOS)—R/W. This bit is used in conjunction with bit 3 in this

0 = No effect.

1 = Allows the SMBus I/O space to be accessible by software when bit 3 in this register is set. The

PCI configuration space is hidden in this case. Note that if bit 3 is set alone, the decode of both

SMBus PCI configuration and I/O space will be disabled.

Reserved

AC’97 Modem Disable (F6_Disable)—R/W. Software sets this bit to disable the AC’97 modem

controller function. BIOS must not enable I/O or memory address space decode, interrupt

generation or any other functionality for functions that are to be disabled.

0 = AC’97 Modem is enabled

1 = AC’97 Modem is disabled

AC’97 Audio Controller Disable (F5_Disable)—R/W. Software sets this bit to disable the AC’97

audio controller function. BIOS must not enable I/O or memory address space decode, interrupt

generation or any other functionality for functions that are to be disabled.

0 = AC’97 audio controller is enabled

1 = AC’97 audio controller is disabled

USB Controller 2 Disable (F4_Disable)—R/W. Software sets this bit to disable the USB Controller

#2 function. BIOS must not enable I/O or memory address space decode, interrupt generation or

any other functionality for functions that are to be disabled.

0 = USB Controller #2 is enabled

1 = USB Controller #2 is disabled

SMBus Controller Disable (F3_Disable)—R/W. Software sets this bit to disable the SMBus Host

Controller function. BIOS must not enable I/O or memory address space decode, interrupt

generation or any other functionality for functions that are to be disabled.

0 = SMBus controller is enabled

1 = SMBus controller is disabled

USB Controller 1 Disable (F2_Disable)—R/W. Software sets this bit to disable the USB Controller

#1 function. BIOS must not enable I/O or memory address space decode, interrupt generation or

any other functionality for functions that are to be disabled.

0 = USB Controller #1 is enabled

1 = USB Controller #1 is disabled

IDE Controller Disable (F1_Disable)—R/W. Software sets this bit to disable the IDE controller

function. BIOS must not enable I/O or memory address space decode, interrupt generation or any

other functionality for functions that are to be disabled.

0 = IDE controller is enabled

1 = IDE controller is disabled

Reserved.

9-22

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.2

DMA I/O Registers

Table 9-2. DMA Registers

Port

Alias

Default

Type

00h

01h

02h

03h

04h

05h

06h

07h

10h

11h

12h

13h

14h

15h

16h

17h

Channel 0 DMA Base & Current Address Register

Channel 0 DMA Base & Current Count Register

Channel 1 DMA Base & Current Address Register

Channel 1 DMA Base & Current Count Register

Channel 2 DMA Base & Current Address Register

Channel 2 DMA Base & Current Count Register

Channel 3 DMA Base & Current Address Register

Channel 3 DMA Base & Current Count Register

Channel 0–3 DMA Command Register

Undefined

000001XXb

000000XXb

Undefined

0Fh

R/W

08h

18h

Channel 0–3 DMA Status Register

0Ah

0Bh

1Ah

1Bh

Channel 0–3 DMA Write Single Mask Register

Channel 0–3 DMA Channel Mode Register

Channel 0–3 DMA Clear Byte Pointer Register

Channel 0–3 DMA Master Clear Register

Channel 0–3 DMA Clear Mask Register

Channel 0–3 DMA Write All Mask Register

Reserved Page Register

R/W

0Ch

0Dh

0Eh

1Ch

1Dh

1Eh

0Fh

1Fh

80h

90h

Undefined

81h

91h

Channel 2 DMA Memory Low Page Register

Channel 3 DMA Memory Low Page Register

Channel 1 DMA Memory Low Page Register

Reserved Page Registers

82h

–

83h

93h

84h–86h

87h

94h–96h

97h

Channel 0 DMA Memory Low Page Register

Reserved Page Register

88h

98h

89h

99h

Channel 6 DMA Memory Low Page Register

Channel 7 DMA Memory Low Page Register

Channel 5 DMA Memory Low Page Register

Reserved Page Registers

8Ah

9Ah

8Bh

9Bh

8Ch–8Eh

8Fh

9Ch–9Eh

9Fh

Refresh Low Page Register

C0h

C2h

C4h

C6h

C8h

CAh

CCh

C1h

C3h

C5h

C7h

C9h

CBh

CDh

Channel 4 DMA Base & Current Address Register

Channel 4 DMA Base & Current Count Register

Channel 5 DMA Base & Current Address Register

Channel 5 DMA Base & Current Count Register

Channel 6 DMA Base & Current Address Register

Channel 6 DMA Base & Current Count Register

Channel 7 DMA Base & Current Address Register

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-23

LPC Interface Bridge Registers (D31:F0)

Table 9-2. DMA Registers (Continued)

Port

Alias

Default

Type

CEh

CFh

Channel 7 DMA Base & Current Count Register

Channel 4–7 DMA Command Register

Channel 4–7 DMA Status Register

Undefined

000001XXb

000000XXb

Undefined

0Fh

R/W

D0h

D1h

D4h

D6h

D8h

DAh

DCh

DEh

D5h

D7h

D9h

DBh

DDh

DFh

Channel 4–7 DMA Write Single Mask Register

Channel 4–7 DMA Channel Mode Register

Channel 4–7 DMA Clear Byte Pointer Register

Channel 4–7 DMA Master Clear Register

Channel 4–7 DMA Clear Mask Register

Channel 4–7 DMA Write All Mask Register

R/W

9.2.1

DMABASE_CA—DMA Base and Current Address Registers

I/O Address:

Ch. #0 = 00h; Ch. #1 = 02h

Ch. #2 = 04h; Ch. #3 = 06h

Ch. #5 = C4h Ch. #6 = C8h

Ch. #7 = CCh;

Attribute:

Size:

16-bit (per channel),

but accessed in two 8-bit

quantities

Default Value:

Lockable:

Undef

Power Well:

Core

Bit

Description

Base and Current Address—R/W. This register determines the address for the transfers to be

performed. The address specified points to two separate registers. On writes, the value is stored in

the Base Address register and copied to the Current Address register. On reads, the value is returned

from the Current Address register.

The address increments/decrements in the Current Address register after each transfer, depending

on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will

be reloaded from the Base Address register after a terminal count is generated.

15:0

For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit location. Bit 15

will be shifted out. Therefore, if bit 15 was a 1, it will be lost.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop.

Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the

low byte is accessed first.

9-24

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.2.2

DMABASE_CC—DMA Base and Current Count Registers

I/O Address:

Ch. #0 = 01h; Ch. #1 = 03h

Ch. #2 = 05h; Ch. #3 = 07h

Ch. #5 = C6h; Ch. #6 = CAh

Ch. #7 = CEh;

Attribute:

Size:

R/W

16-bit (per channel),

but accessed in two 8-bit

quantities

Default Value:

Lockable:

Undefined

Power Well:

Core

Bit

Description

Base and Current Count—R/W. This register determines the number of transfers to be performed.

The address specified points to two separate registers. On writes the value is stored in the Base

Count register and copied to the Current Count register. On reads the value is returned from the

Current Count register.

The actual number of transfers is one more than the number programmed in the Base Count Register

(i.e., programming a count of 4h results in 5 transfers). The count is decrements in the Current Count

is generated. If the channel is in auto-initialize mode, the Current Count register will be reloaded from

the Base Count register after a terminal count is generated.

15:0

For transfers to/from an 8-bit slave (channels 0–3), the count register indicates the number of bytes to

be transferred. For transfers to/from a 16-bit slave (channels 5–7), the count register indicates the

number of words to be transferred.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop.

Before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low

byte is accessed first.

9.2.3

DMAMEM_LP—DMA Memory Low Page Registers

I/O Address:

Ch. #0 = 87h; Ch. #1 = 83h

Ch. #2 = 81h; Ch. #3 = 82h

Ch. #5 = 8Bh; Ch. #6 = 89h

Ch. #7 = 8Ah;

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Default Value:

Lockable:

Undefined

Bit

Description

DMA Low Page (ISA Address bits [23:16])—R/W. This register works in conjunction with the DMA

controller's Current Address Register to define the complete 24-bit address for the DMA channel.

This register remains static throughout the DMA transfer.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-25

LPC Interface Bridge Registers (D31:F0)

9.2.4

DMACMD—DMA Command Register

I/O Address:

Ch. #0–3 = 08h;

Ch. #4–7 = D0h

Undefined

Attribute:

Size:

Power Well:

8-bit

Core

Default Value:

Lockable:

Bit

Description

7:5

Reserved. Must be 0.

DMA Group Arbitration Priority—WO. Each channel group is individually assigned either fixed or

rotating arbitration priority. At part reset, each group is initialized in fixed priority.

0 = Fixed priority to the channel group

1 = Rotating priority to the group.

Reserved. Must be 0

DMA Channel Group Enable—WO. Both channel groups are enabled following part reset.

0 = Enable the DMA channel group.

1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded

through channel 4.

1:0

Reserved. Must be 0.

9.2.5

DMASTS—DMA Status Register

I/O Address:

Ch. #0–3 = 08h;

Ch. #4–7 = D0h

Undefined

Attribute:

Size:

Power Well:

8-bit

Core

Default Value:

Lockable:

Bit

Description

Channel Request Status—RO. When a valid DMA request is pending for a channel, the

corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the

corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note

that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the

request status for channels 0 through 3.

7:4

4 = Channel 0

5 = Channel 1 (5)

6 = Channel 2 (6)

7 = Channel 3 (7)

Channel Terminal Count Status—RO. When a channel reaches terminal count (TC), its status bit is

set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade,

so the TC bit response for channel 4 is irrelevant.

0 = Channel 0

3:0

1 = Channel 1 (5)

2 = Channel 2 (6)

3 = Channel 3 (7)

9-26

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.2.6

DMA_WRSMSK—DMA Write Single Mask Register

I/O Address:

Ch. #0–3 = 0Ah;

Ch. #4–7 = D4h

0000 01xx

Attribute:

Size:

Power Well:

8-bit

Core

Default Value:

Lockable:

Bit

Description

7:3

Reserved. Must be 0.

Channel Mask Select—WO.

0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore,

only one channel can be masked / unmasked at a time.

1 = Disable DREQ for the selected channel.

DMA Channel Select—WO. These bits select the DMA Channel Mode Register to program.

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

1:0

9.2.7

DMACH_MODE—DMA Channel Mode Register

I/O Address:

Ch. #0–3 = 0Bh;

Ch. #4–7 = D6h

0000 00xx

Attribute:

Size:

Power Well:

8-bit

Core

Default Value:

Lockable:

Bit

Description

DMA Transfer Mode—WO. Each DMA channel can be programmed in one of four different modes:

00 = Demand mode

01 = Single mode

10 = Reserved

7:6

11 = Cascade mode

Address Increment/Decrement Select—WO. This bit controls address increment/decrement during

DMA transfers.

0 = Address increment. (default after part reset or Master Clear)

1 = Address decrement.

Autoinitialize Enable—WO.

0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset or

Master Clear disables autoinitialization.

1 = DMA restores the Base Address and Count registers to the current registers following a terminal

count (TC).

DMA Transfer Type—WO. These bits represent the direction of the DMA transfer. When the channel

is programmed for cascade mode, (bits[7:6] = “11”) the transfer type is irrelevant.

00 = Verify - No I/O or memory strobes generated

01 = Write - Data transferred from the I/O devices to memory

10 = Read - Data transferred from memory to the I/O device

11 = Illegal

3:2

1:0

DMA Channel Select—WO. These bits select the DMA Channel Mode Register that will be written

by bits [7:2].

00 = Channel 0 (4)

01 = Channel 1 (5)

10 = Channel 2 (6)

11 = Channel 3 (7)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-27

LPC Interface Bridge Registers (D31:F0)

9.2.8

DMA Clear Byte Pointer Register

I/O Address:

Ch. #0–3 = 0Ch;

Ch. #4–7 = D8h

xxxx xxxx

Attribute:

Size:

Power Well:

8-bit

Core

Default Value:

Lockable:

Bit

Description

Clear Byte Pointer—WO. No specific pattern. Command enabled with a write to the I/O port address.

Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch

used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is

also cleared by part reset and by the Master Clear command. This command precedes the first

access to a 16-bit DMA controller register. The first access to a 16 bit register will then access the

significant byte, and the second access automatically accesses the most significant byte.

7:0

9.2.9

DMA Master Clear Register

I/O Address:

Ch. #0–3 = 0Dh;

Ch. #4–7 = DAh

xxxx xxxx

Attribute:

Size:

8-bit

Default Value:

Bit

Description

Master Clear—WO. No specific pattern. Enabled with a write to the port. This has the same effect as

the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared

and the Mask Register is set.

7:0

9.2.10

DMA_CLMSK—DMA Clear Mask Register

I/O Address:

Ch. #0–3 = 0Eh;

Ch. #4–7 = DCh

xxxx xxxx

Attribute:

Size:

Power Well:

8-bit

Core

Default Value:

Lockable:

Bit

Description

7:0

Clear Mask Register—WO. No specific pattern. Command enabled with a write to the port.

9-28

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.2.11

DMA_WRMSK—DMA Write All Mask Register

I/O Address:

Ch. #0–3 = 0Fh;

Ch. #4–7 = DEh

0000 1111

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Default Value:

Lockable:

Bit

Description

7:4

Reserved. Must be 0.

Channel Mask Bits—R/W. This register permits all four channels to be simultaneously enabled/

disabled instead of enabling/disabling each channel individually, as is the case with the Mask

channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/

Word Count Register reaches terminal count (unless the channel is in auto-initialization mode).

Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the

corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits [3:0]

indicate the DMA channel [3:0] ([7:4]) mask status.

3:0

Bit 0 = Channel 0 (4) 1 = Masked, 0 = Not Masked

Bit 1 = Channel 1 (5) 1 = Masked, 0 = Not Masked

Bit 2 = Channel 2 (6) 1 = Masked, 0 = Not Masked

Bit 3 = Channel 3 (7) 1 = Masked, 0 = Not Masked

Note: Disabling channel 4 also disables channels 0–3 due to the cascade of channels 0–3 through

channel 4.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-29

LPC Interface Bridge Registers (D31:F0)

9.3

Timer I/O Registers

Port

Aliases

Default Value

Type

Counter 0 Interval Time Status Byte Format

Counter 0 Counter Access Port Register

Counter 1 Interval Time Status Byte Format

Counter 1 Counter Access Port Register

Counter 2 Interval Time Status Byte Format

Counter 2 Counter Access Port Register

Timer Control Word Register

0XXXXXXXb

Undefined

0XXXXXXXb

Undefined

0XXXXXXXb

Undefined

XXXXXXX0b

X0h

R/W

40h

50h

41h

42h

51h

52h

R/W

43h

53h

Timer Control Word Register Read Back

Counter Latch Command

9.3.1

TCW—Timer Control Word Register

I/O Address:

Default Value:

43h

Attribute:

Size:

8 bits

All bits undefined

This register is programmed prior to any counter being accessed to specify counter modes.

Following part reset, the control words for each register are undefined and each counter output is 0.

Each timer must be programmed to bring it into a known state.

Bit

Description

Counter Select—WO. The Counter Selection bits select the counter the control word acts upon as

shown below. The Read Back Command is selected when bits[7:6] are both 1.

00 = Counter 0 select

01 = Counter 1 select

10 = Counter 2 select

11 = Read Back Command

7:6

Read/Write Select—WO. These bits are the read/write control bits. The actual counter programming

is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2).

00 = Counter Latch Command

5:4

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

Counter Mode Selection—WO. These bits select one of six possible modes of operation for the

selected counter.

000 = Mode 0

001 = Mode 1

x10 = Mode 2

x11 = Mode 3

100 = Mode 4

101 = Mode 5

Out signal on end of count (=0)

Hardware retriggerable one-shot

Rate generator (divide by n counter)

Square wave output

3:1

Software triggered strobe

Hardware triggered strobe

Binary/BCD Countdown Select—WO.

0 = Binary countdown is used. The largest possible binary count is 2

1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 10

9-30

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

There are two special commands that can be issued to the counters through this register, the Read

Back Command and the Counter Latch Command. When these commands are chosen, several bits

within this register are redefined. These register formats are described below.

9.3.1.1

RDBK_CMD—Read Back Command

The Read Back Command is used to determine the count value, programmed mode, and current

states of the OUT pin and Null count flag of the selected counter or counters. Status and/or count

may be latched in any or all of the counters by selecting the counter during the register write. The

count and status remain latched until read, and further latch commands are ignored until the count

is read. Both count and status of the selected counters may be latched simultaneously by setting

both bit 5 and bit 4 to 0. If both are latched, the first read operation from that counter returns the

latched status. The next one or two reads, depending on whether the counter is programmed for one

or two byte counts, returns the latched count. Subsequent reads return an unlatched count.

Bit

Description

7:6

Read Back Command. This field must be “11” to select the Read Back Command.

Latch Count of Selected Counters.

0 = Current count value of the selected counters will be latched

1 = Current count will not be latched

Latch Status of Selected Counters.

0 = Status of the selected counters will be latched

1 = Status will not be latched

Counter 2 Select.

1 = Counter 2 count and/or status will be latched

Counter 1 Select.

1 = Counter 1 count and/or status will be latched

Counter 0 Select.

1 = Counter 0 count and/or status will be latched.

Reserved. Must be 0.

9.3.1.2

LTCH_CMD—Counter Latch Command

The Counter Latch Command latches the current count value. This command is used to insure that

the count read from the counter is accurate. The count value is then read from each counter's count

42h for counter 2). The count must be read according to the programmed format (i.e., if the counter

is programmed for two byte counts, two bytes must be read). The two bytes do not have to be read

one right after the other (read, write, or programming operations for other counters may be inserted

between the reads). If a counter is latched once and then latched again before the count is read, the

second Counter Latch Command is ignored.

Bit

Description

Counter Selection. These bits select the counter for latching. If “11” is written, then the write is

interpreted as a read back command.

00 = Counter 0

7:6

01 = Counter 1

10 = Counter 2

Counter Latch Command.

5:4

3:0

00 = Selects the Counter Latch Command.

Reserved. Must be 0.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-31

LPC Interface Bridge Registers (D31:F0)

9.3.2

SBYTE_FMT—Interval Timer Status Byte Format Register

I/O Address:

Counter 0 = 40h,

Counter 1 = 41h,

Counter 2 = 42h

Attribute:

Size:

8 bits per counter

Default Value:

Bits[6:0] undefined, Bit 7=0

Each counter's status byte can be read following a Read Back Command. If latch status is chosen

(bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the

counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter

2) returns the status byte. The status byte returns the following:

Bit

Description

Counter OUT Pin State—RO.

0 = OUT pin of the counter is also a 0.

1 = OUT pin of the counter is also a 1.

Count Register Status—RO. This bit indicates when the last count written to the Count Register

(CR) has been loaded into the counting element (CE). The exact time this happens depends on the

counter mode, but until the count is loaded into the counting element (CE), the count value will be

incorrect.

0 = Count has been transferred from CR to CE and is available for reading.

1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading.

Read/Write Selection Status—RO. These reflect the read/write selection made through bits[5:4] of

the control register. The binary codes returned during the status read match the codes used to

program the counter read/write selection.

00 = Counter Latch Command

5:4

01 = Read/Write Least Significant Byte (LSB)

10 = Read/Write Most Significant Byte (MSB)

11 = Read/Write LSB then MSB

Mode Selection Status—RO. These bits return the counter mode programming. The binary code

returned matches the code used to program the counter mode, as listed under the bit function above.

000 = Mode 0

001 = Mode 1

x10 = Mode 2

x11 = Mode 3

100 = Mode 4

101 = Mode 5

Out signal on end of count (=0)

Hardware retriggerable one-shot

Rate generator (divide by n counter)

Square wave output

3:1

Software triggered strobe

Hardware triggered strobe

Countdown Type Status—RO. This bit reflects the current countdown type.

0 = Binary countdown

1 = Binary Coded Decimal (BCD) countdown.

9.3.3

Counter Access Ports Register

I/O Address:

Counter 0 –40h,

Counter 1 –41h,

Counter 2–42h

All bits undefined

Attribute:

Size:

R/W

8 bit

Default Value:

Bit

Description

Counter Port—R/W. Each counter port address is used to program the 16-bit Count Register. The

order of programming (either LSB only, MSB only, or LSB then MSB) is defined with the Interval

Counter Control Register at port 43h. The counter port is also used to read the current count from the

Count Register, and return the status of the counter programming following a Read Back Command.

7:0

9-32

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.4

8259 Interrupt Controller (PIC) Registers

9.4.1

Interrupt Controller I/O MAP

The interrupt controller registers are located at 20h and 21h for the master controller (IRQ[0:7]),

and at A0h and A1h for the slave controller (IRQ[8:13]). These registers have multiple functions

depending on the data written to them. Table 9-3 lists the different register possibilities for each

address.

Table 9-3. PIC Registers

Port

Aliases

Default Value

Type

Master PIC ICW1 Init. Cmd Word 1 Register

Master PIC OCW2 Op Ctrl Word 2 Register

Master PIC OCW3 Op Ctrl Word 3 Register

Master PIC ICW2 Init. Cmd Word 2 Register

Master PIC ICW3 Init. Cmd Word 3 Register

Master PIC ICW4 Init. Cmd Word 4 Register

Master PIC OCW1 Op Ctrl Word 1 Register

Slave PIC ICW1 Init. Cmd Word 1 Register

Slave PIC OCW2 Op Ctrl Word 2 Register

Slave PIC OCW3 Op Ctrl Word 3 Register

Slave PIC ICW2 Init. Cmd Word 2 Register

Slave PIC ICW3 Init. Cmd Word 3 Register

Slave PIC ICW4 Init. Cmd Word 4 Register

Slave PIC OCW1 Op Ctrl Word 1 Register

Master PIC Edge/Level Triggered Register

Slave PIC Edge/Level Triggered Register

Undefined

001XXXXXb

X01XXX10b

Undefined

01h

R/W

24h, 28h,

2Ch, 30h,

20h

34h, 38h, 3Ch

25h, 29h,

2Dh, 31h,

21h

A0h

A1h

35h, 39h, 3Dh

00h

Undefined

001XXXXXb

X01XXX10b

Undefined

01h

A4h, A8h,

ACh, B0h,

B4h, B8h, BCh

A5h, A9h,

ADh, B1h,

B5h, B9h, BDh

00h

4D0h

4D1h

–

00h

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-33

LPC Interface Bridge Registers (D31:F0)

9.4.2

ICW1—Initialization Command Word 1 Register

Offset Address:

Default Value:

Master Controller–020h

Slave Controller–0A0h

All bits undefined

Attribute:

Size:

8 bit /controller

A write to Initialization Command Word 1 starts the interrupt controller initialization sequence,

during which the following occurs:

1. The Interrupt Mask register is cleared.

2. IRQ7 input is assigned priority 7.

3. The slave mode address is set to 7.

4. Special Mask Mode is cleared and Status Read is set to IRR.

Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the

initialization sequence.

Bit

Description

ICW/OCW select—WO. These bits are MCS-85 specific, and not needed.

7:5

000 = Should be programmed to “000”

ICW/OCW select—WO.

1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence.

Edge/Level Bank Select (LTIM)—WO. Disabled. Replaced by the edge/level triggered control

registers (ELCR).

ADI—WO.

0 = Ignored for the ICH2. Should be programmed to 0.

Single or Cascade (SNGL)—WO.

0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.

ICW4 Write Required (IC4)—WO.

1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.

9-34

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.4.3

ICW2—Initialization Command Word 2 Register

Offset Address:

Default Value:

Master Controller–021h

Slave Controller–0A1h

All bits undefined

Attribute:

Size:

8 bit /controller

ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt

vector address. The value programmed for bits[7:3] is used by the processor to define the base

address in the interrupt vector table for the interrupt routines associated with each IRQ on the

controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave

controller.

Bit

Description

Interrupt Vector Base Address—WO. Bits [7:3] define the base address in the interrupt vector

table for the interrupt routines associated with each interrupt request level input.

7:3

Interrupt Request Level—WO. When writing ICW2, these bits should all be 0. During an interrupt

acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be

serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus

during the second INTA# cycle. The code is a three bit binary code:

Code

000

001

010

011

100

101

110

111

Master Interrupt Slave Interrupt

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

2:0

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

9.4.4

ICW3—Master Controller Initialization Command Word 3

Offset Address:

Default Value:

21h

Attribute:

Size:

8 bits

All bits undefined

Bit

Description

7:3

0 = These bits must be programmed to zero.

Cascaded Interrupt Controller IRQ Connection—WO. This bit indicates that the slave controller is

cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through the slave controller’s priority

resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through the master

controller’s priority solver. If it wins, the INTR signal is asserted to the processor, and the returning

interrupt acknowledge returns the interrupt vector for the slave controller.

1 = This bit must always be programmed to a 1.

1:0

0 = These bits must be programmed to zero.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-35

LPC Interface Bridge Registers (D31:F0)

9.4.5

ICW3—Slave Controller Initialization Command Word 3

Offset Address:

Default Value:

A1h

Attribute:

Size:

8 bits

All bits undefined

Bit

Description

7:3

0 = These bits must be programmed to zero.

Slave Identification Code—WO. These bits are compared against the slave identification code

broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing

edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code

broadcast by the master controller. When 02h is broadcast by the master controller during the INTA#

sequence, the slave controller assumes responsibility for broadcasting the interrupt vector.

2:0

9.4.6

ICW4—Initialization Command Word 4 Register

Offset Address:

Master Controller–021h

Slave Controller–0A1h

Attribute:

Size:

8 bits

Bit

Description

7:5

0 = These bits must be programmed to zero.

Special Fully Nested Mode (SFNM)—WO.

0 = Should normally be disabled by writing a 0 to this bit.

1 = Special fully nested mode is programmed.

Buffered Mode (BUF)—WO.

0 = Must be programmed to 0 for the ICH2. This is non-buffered mode.

Master/Slave in Buffered Mode—WO. Not used.

0 = Should always be programmed to 0.

Automatic End of Interrupt (AEOI)—WO.

0 = This bit should normally be programmed to 0. This is the normal end of interrupt.

1 = Automatic End of Interrupt (AEOI) mode is programmed. AEOI is discussed in Section 5.7.4.

Microprocessor Mode—WO.

1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-

based system.

9.4.7

OCW1—Operational Control Word 1 (Interrupt Mask)

Offset Address:

Default Value:

Master Controller–021h

Slave Controller–0A1h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Interrupt Request Mask—R/W. When a 1 is written to any bit in this register, the corresponding IRQ

line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is

cleared and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master

controller will also mask the interrupt requests from the slave controller.

7:0

9-36

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.4.8

OCW2—Operational Control Word 2 Register

Offset Address:

Default Value:

Master Controller–020h

Slave Controller–0A0h

Bit[4:0]=undefined, Bit[7:5]=001

Attribute:

Size:

8 bits

Following a part reset or ICW initialization, the controller enters the fully nested mode of

operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI

mode are disabled following initialization.

Bit

Description

Rotate and EOI Codes (R, SL, EOI)—WO. These three bits control the Rotate and End of Interrupt

modes and combinations of the two.

000 = Rotate in Auto EOI Mode (Clear)

001 = Non-specific EOI command

010 = No Operation

011 = Specific EOI Command

100 = Rotate in Auto EOI Mode (Set)

101 = Rotate on Non-Specific EOI Command

110 = *Set Priority Command

7:5

111 = *Rotate on Specific EOI Command

*L0–L2 Are Used

4:3

2:0

OCW2 Select—WO. When selecting OCW2, bits 4:3 = “00”

Interrupt Level Select (L2, L1, L0)—WO. L2, L1, and L0 determine the interrupt level acted upon

when the SL bit is active. A simple binary code, outlined below, selects the channel for the command

to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2,

L1 and L0 to 0 is sufficient in this case.

Bits

000

001

010

011

Interrupt Level

IRQ0/8

Bits

100

101

110

111

Interrupt Level

IRQ4/12

IRQ1/9

IRQ5/13

IRQ2/10

IRQ6/14

IRQ3/11

IRQ7/15

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-37

LPC Interface Bridge Registers (D31:F0)

9.4.9

OCW3—Operational Control Word 3 Register

Offset Address:

Default Value:

Master Controller–020h

Slave Controller–0A0h

Bit[6,0]=0, Bit[7,4:2]=undefined,

Bit[5,1]=1

Attribute:

Size:

8 bits

Bit

Description

Reserved. Must be 0.

Special Mask Mode (SMM)—WO.

1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the

system priority structure while the routine is executing, through selective enabling/disabling of

the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning.

Enable Special Mask Mode (ESMM)—WO.

0 = Disable. The SMM bit becomes a "don't care".

1 = Enable the SMM bit to set or reset the Special Mask Mode.

4:3

OCW3 Select—WO. When selecting OCW3, bits 4:3 = “01”

Poll Mode Command—WO.

0 = Disable. Poll Command is not issued.

1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle.

An encoded byte is driven onto the data bus, representing the highest priority level requesting

service.

and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection.

When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR

will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port

address read will be "read IRR". To retain the current selection (read ISR or read IRR), always write a

0 to bit 1 when programming this register. The selected register can be read repeatedly without

reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior to

attempting the read.

1:0

00 = No Action

01 = No Action

10 = Read IRQ Register

11 = Read IS Register

9-38

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.4.10

ELCR1—Master Controller Edge/Level Triggered Register

Offset Address:

Default Value:

4D0h

00h

Attribute:

Size:

R/W

8 bits

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode

(bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat

timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.

Bit

Description

IRQ7 ECL—R/W.

0 = Edge.

1 = Level.

IRQ6 ECL—R/W.

0 = Edge.

1 = Level.

IRQ5 ECL—R/W.

0 = Edge.

1 = Level.

IRQ4 ECL—R/W.

0 = Edge.

1 = Level.

IRQ3 ECL—R/W.

0 = Edge.

1 = Level.

2:0

Reserved. Must be 0.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-39

LPC Interface Bridge Registers (D31:F0)

9.4.11

ELCR2—Slave Controller Edge/Level Triggered Register

Offset Address:

Default Value:

4D1h

00h

Attribute:

Size:

R/W

8 bits

In edge mode (bit[x] = 0) the interrupt is recognized by a low-to-high transition. In level mode

(bit[x] = 1) the interrupt is recognized by a high level. The real time clock interrupt (IRQ8#) and

the floating point error interrupt (IRQ13) cannot be programmed for level mode.

Bit

Description

IRQ15 ECL—R/W.

0 = Edge.

1 = Level.

IRQ14 ECL—R/W.

0 = Edge.

1 = Level.

Reserved. Must be 0.

IRQ12 ECL—R/W.

0 = Edge.

1 = Level.

IRQ11 ECL—R/W.

0 = Edge.

1 = Level.

IRQ10 ECL—R/W.

0 = Edge.

1 = Level.

IRQ9 ECL—R/W.

0 = Edge.

1 = Level.

Reserved. Must be 0.

9-40

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.5

Advanced Interrupt Controller (APIC)

9.5.1

APIC Register Map

The APIC is accessed via an indirect addressing scheme. Two registers are visible by software for

manipulation of most of the APIC registers. These registers are mapped into memory space. The

registers are shown in Table 9-4.

Table 9-4. APIC Direct Registers

Address

Size

Type

FEC0_0000h

FEC0_0010h

FECO_0020h

FECO_0040h

Index Register

Data Register

8 bits

32 bits

8 bits

R/W

IRQ Pin Assertion Register

EOI Register

Table 9-5 lists the registers which can be accessed within the APIC via the Index Register. When

accessing these registers, accesses must be done a DWord at a time. For example, software should

never access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not

attempt to recover from a bad programming model in this case.

Table 9-5. APIC Indirect Registers

Index

00h

Size

Type

32 bits

R/W

01h

02h

Version

Arbitration ID

Boot Configuration

Reserved

03h

R/W

03h–0Fh

10h –11h

12h–13h

...

Redirection Table 0

Redirection Table 1

...

64 bits

...

R/W

...

3Eh–3Fh

40h–FFh

Redirection Table 23

Reserved

64 bits

R/W

9.5.2

IND—Index Register

Memory Address FEC0_0000h

Attribute:

Size:

R/W

8 bits

Default Value:

00h

The Index Register will select which APIC indirect register to be manipulated by software. The

selector values for the indirect registers are listed in Table 9-5. Software programs this register to

select the desired APIC internal register

Bit

Description

7:0

APIC Index—R/W. This is an 8 bit pointer into the I/O APIC register table.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-41

LPC Interface Bridge Registers (D31:F0)

9.5.3

DAT—Data Register

Memory Address FEC0_0010h

Attribute:

Size:

R/W

32 bits

Default Value:

00000000h

This is a 32 bit register specifying the data to be read or written to the register pointed to by the

Index register. This register can only be accessed in DWord quantities.

Bit

Description

APIC Data—R/W. This is a 32 bit register for the data to be read or written to the APIC indirect

7:0

9.5.4

IRQPA—IRQ Pin Assertion Register

Memory Address FEC0_0020h

Default Value: N/A

Attribute:

Size:

32 bits

The IRQ Pin Assertion Register is present to provide a mechanism to scale the number of interrupt

inputs into the I/O APIC without increasing the number of dedicated input pins. When a device that

supports this interrupt assertion protocol requires interrupt service, that device will issue a write to

this register. Bits 4:0 written to this register contain the IRQ number for this interrupt. The only

valid values are 0–23. Bits 31:5 are ignored. To provide for future expansion, peripherals should

always write a value of 0 for Bits 31:5.

See Section 5.8.4 for more details on how PCI devices will use this field.

Note: Writes to this register are only allowed by the processor and by masters on the ICH2’s PCI bus.

Writes by devices on PCI buses above the ICH2 (e.g., a PCI segment on a P64H) are not supported.

Bit

Description

31:5

Reserved. Bits 31:5 are ignored.

IRQ Number—WO. Bits 4:0 written to this register contain the IRQ number for this interrupt. The

only valid values are 0–23.

4:0

9-42

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.5.5

EOIR—EOI Register

Memory Address FEC0_0040h

Attribute:

Size:

32 bits

Default Value:

N/A

The EOI register is present to provide a mechanism to maintain the level triggered semantics for

level-triggered interrupts issued on the parallel bus.

When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this

match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.

Note: This is similar to what already occurs when the APIC sees the EIO message on the serial bus. Note

that if multiple I/O Redirection entries, for any reason, assign the same vector for more than one

interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which

was prematurely reset will not be lost because if its input remained active when the Remote_IRR

bit is cleared, the interrupt will be reissued and serviced at a later time. Note: Only bits 7:0 are

actually used. Bits 31:8 are ignored by the ICH2.

Note: To provide for future expansion, the processor should always write a value of 0 to Bits 31:8.

Bit

Description

Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits

31:8.

31:8

Redirection Entry Clear—WO. When a write is issued to this register, the I/O APIC will check

this field, and compare it with the vector field for each entry in the I/O Redirection Table. When a

match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.

7:0

9.5.6

ID—Identification Register

Index Offset:

Default Value:

00h

00000000h

Attribute:

Size:

R/W

32 bits

The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is

derived from its I/O APIC ID. This register is reset to zero on power up reset.

Bit

Description

31:28 Reserved.

27:24 APIC ID—R/W. Software must program this value before using the APIC.

23:0 Reserved.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-43

LPC Interface Bridge Registers (D31:F0)

9.5.7

VER—Version Register

Index Offset:

Default Value:

01h

00170002h

Attribute:

Size:

32 bits

Each I/O APIC contains a hardwired Version Register that identifies different implementation of

APIC and their versions. The maximum redirection entry information also is in this register, to let

software know how many interrupt are supported by this APIC.

Bit

Description

31:24 Reserved.

Maximum Redirection Entries—RO. This is the entry number (0 being the lowest entry) of the

23:16 highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and

is in the range 0 through 239. In the ICH2 this field is hardwired to 17h to indicate 24 interrupts.

PRQ—RO. This bit is set to 1 to indicate that this version of the I/O APIC implements the IRQ

Assertion register and allows PCI devices to write to it to cause interrupts.

14 :8

7:0

Reserved.

Version—RO. This is a version number that identifies the implementation version.

9.5.8

ARBID—Arbitration ID Register

Index Offset:

Default Value:

02h

00000000h

Attribute:

Size:

32 bits

This register contains the bus arbitration priority for the APIC. This register is loaded whenever the

APIC ID register is loaded. A rotating priority scheme is used for APIC bus arbitration. The winner

of the arbitration becomes the lowest priority agent and assumes an arbitration ID of 0.

Bit

Description

31:28

27:24

23:0

Reserved.

I/O APIC Identification—RO. This 4 bit field contains the I/O APIC Arbitration ID.

Reserved.

9.5.9

BOOT_CONFIG—Boot Configuration Register

Index Offset:

Default Value:

03h

00000000h

Attribute:

Size:

R/W

32 bits

This register is used to control the interrupt delivery mechanism for the APIC.

Bit

Description

31:1

Reserved.

Delivery Type (DT)—R/W.

0 = Interrupt delivery mechanism is via the APIC serial bus (default).

1 = Interrupt delivery mechanism is a front-side bus message.

9-44

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.5.10

Redirection Table

Index Offset:

10h–11h (vector 0) through

3E–3Fh (vector 23)

Bit 16–1, Bits[15:12]=0.

All other bits undefined

Attribute:

Size:

R/W

Default Value:

64 bits each, (accessed as

two 32 bit quantities)

The Redirection Table has a dedicated entry for each interrupt input pin. The information in the

Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin

into an APIC message.

The APIC will respond to an edge-triggered interrupt as long as the interrupt is held until after the

acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the

I/O APIC is set. The state machine will step ahead and wait for an acknowledgment from the APIC

bus unit that the interrupt message was sent over the APIC bus. Only then will the I/O APIC be

able to recognize a new edge on that interrupt pin. That new edge will only result in a new

invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request

destination.)

Bit

Description

Destination—R/W. If bit 11 of this entry is 0 [Physical], then bits [59:56] specifies an APIC ID. If

bit 11 of this entry is 1 [Logical], then bits [63:56] specify the logical destination address of a set of

processors.

63:56

55:17

Reserved.

Mask—R/W.

0 = Not masked: An edge or level on this interrupt pin results in the delivery of the interrupt to the

destination.

1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is

accepted by a local APIC has no effect on that interrupt. This behavior is identical to the

device withdrawing the interrupt before it is posted to the processor. It is software's

responsibility to deal with the case where the mask bit is set after the interrupt message has

been accepted by a local APIC unit but before the interrupt is dispensed to the processor.

Trigger Mode—R/W. This field indicates the type of signal on the interrupt pin that triggers an

interrupt.

0 = Edge triggered.

1 = Level triggered.

Remote IRR—R/W. This bit is used for level triggered interrupts; its meaning is undefined for

edge triggered interrupts.

0 = Reset when an EOI message is received from a local APIC.

1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.

Interrupt Input Pin Polarity—R/W. This bit specifies the polarity of each interrupt signal

connected to the interrupt pins.

0 = Active high.

1 = Active low.

Delivery Status—RO. This field contains the current status of the delivery of this interrupt. Writes

to this bit have no effect.

0 = Idle. No activity for this interrupt.

1 = Pending. Interrupt has been injected, but delivery is held up due to the APIC bus being busy

or the inability of the receiving APIC unit to accept the interrupt at this time.

Destination Mode—R/W. This field determines the interpretation of the Destination field.

0 = Physical. Destination APIC ID is identified by bits [59:56].

1 = Logical. Destinations are identified by matching bit [63:56] with the Logical Destination in the

Destination Format Register and Logical Destination Register in each Local APIC.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-45

LPC Interface Bridge Registers (D31:F0)

Bit

Description

Delivery Mode—R/W. This field specifies how the APICs listed in the destination field should act

upon reception of this signal. Certain Delivery Modes will only operate as intended when used in

conjunction with a specific trigger mode. These encodings are:

000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.

Trigger Mode can be edge or level.

001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing

at the lowest priority among all the processors listed in the specified destination. Trigger

Mode can be edge or level.

010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge

triggered. The vector information is ignored but must be programmed to all zeroes for future

compatibility.

011 = Reserved

100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination.

Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is

programmed as level triggered. For proper operation this redirection table entry must be

programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. Once the

interrupt is detected, it will be sent over the APIC bus.

10:8

If the redirection table is incorrectly set to level, the loop count will continue counting

through the redirection table addresses. Once the count for the NMI pin is reached again,

the interrupt will be sent over the APIC bus again.

101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT

signal. All addressed local APICs will assume their INIT state. INIT is always treated as an

edge triggered interrupt even if programmed as level triggered. For proper operation this

redirection table entry must be programmed to edge triggered. The INIT delivery mode

does not set the RIRR bit. Once the interrupt is detected, it will be sent over the APIC bus.

If the redirection table is incorrectly set to level, the loop count will continue counting

through the redirection table addresses. Once the count for the INIT pin is reached again,

the interrupt will be sent over the APIC bus again

110 = Reserved

111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination

as an interrupt that originated in an externally connected 8259A compatible interrupt

controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the

external controller that is expected to supply the vector. Requires the interrupt to be

programmed as edge triggered.

Vector—R/W. This field contains the interrupt vector for this interrupt. Values range between 10h

and FEh.

7:0

9-46

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.6

Real Time Clock Registers

9.6.1

I/O Register Address Map

The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the

standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date

information along with four registers, A–D, that are used for configuration of the RTC. The

extended bank contains a full 128 bytes of battery backed SRAM and will be accessible even when

the RTC module is disabled (via the RTC configuration register). Registers A–D do not physically

exist in the RAM.

All data movement between the host processor and the real-time clock is done through registers

mapped to the standard I/O space. The register map appears in Table 9-6.

Table 9-6. RTC I/O Registers

I/O Locations

If U128E bit = 0

Function

70h and 74h Also alias to 72h and 76h

71h and 75h Also alias to 73h and 77h

72h and 76h

Real-Time Clock (Standard RAM) Index Register

Real-Time Clock (Standard RAM) Target Register

Extended RAM Index Register (if enabled)

Extended RAM Target Register (if enabled)

73h and 77h

NOTES:

1. I/O locations 70h and 71h are the standard ISA location for the real-time clock. The map for this bank is

shown in Table 9-7. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank

is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address

73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not

needed, it may be disabled.

2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to these addresses,

software must first read the value, and then write the same value for bit 7 during the sequential address

write.

9.6.2

Indexed Registers

The RTC contains two sets of indexed registers that are accessed using the two separate Index and

Target registers (70h/71h or 72h/73h), as shown in Table 9-7.

Table 9-7. RTC (Standard) RAM Bank

Index

00h

Name

Index

Name

Seconds

08h

09h

Month

01h

02h

03h

04h

05h

06h

07h

Seconds Alarm.

Minutes

Year

0Ah

Minutes Alarm

Hours

0Bh

0Ch

Hours Alarm

Day of Week

Day of Month

0Dh

0Eh–7Fh

114 Bytes of User RAM

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-47

LPC Interface Bridge Registers (D31:F0)

9.6.2.1

RTC_REGA—Register A

RTC Index:

Default Value:

Lockable:

Undefined

Attribute:

Size:

Power Well:

R/W

8-bit

RTC

This register is used for general configuration of the RTC functions. None of the bits are affected

by RSMRST# or any other ICH2 reset signal.

Bit

Description

Update In Progress (UIP)—R/W. This bit may be monitored as a status flag.

0 = The update cycle will not start for at least 492us. The time, calendar, and alarm information in

RAM is always available when the UIP bit is 0.

1 = The update is soon to occur or is in progress.

Division Chain Select (DV[2:0])—R/W. These three bits control the divider chain for the oscillator,

and are not affected by RSMRST# or any other reset signal. DV[2] corresponds to bit 6.

010 = Normal Operation

11X = Divider Reset

101 = Bypass 15 stages (test mode only)

100 = Bypass 10 stages (test mode only)

011 = Bypass 5 stages (test mode only)

001 = Invalid

6:4

000 = Invalid

RS[3:0] Rate Select—R/W. Selects one of 13 taps of the 15 stage divider chain. The selected tap

can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF

flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to zero. RS3

corresponds to bit 3.

0000 = Interrupt never toggles

0001 = 3.90625 ms

0010 = 7.8125 ms

1000 = 3.90625 ms

1001 = 7.8125 ms

1010 = 15.625 ms

1011 = 31.25 ms

1100 = 62.5 ms

1101 = 125 ms

3:0

0011 = 122.070 us

0100 = 244.141 us

0101 = 488.281 us

0110 = 976.5625 us

0111 = 1.953125 ms

1110 = 250 ms

1111= 500 ms

9-48

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.6.2.2

RTC_REGB—Register B (General Configuration)

RTC Index:

Default Value:

Lockable:

0Bh

Attribute:

Size:

Power Well:

R/W

8-bit

RTC

U0U00UUU (U: Undefined)

Bit

Description

Update Cycle Inhibit (SET)—R/W. Enables/Inhibits the update cycles. This bit is not affected by

RSMRST# nor any other reset signal.

0 = Update cycle occurs normally once each second.

1 = A current update cycle will abort and subsequent update cycles will not occur until SET is

returned to zero. When set is one, the BIOS may initialize time and calendar bytes safely.

Periodic Interrupt Enable (PIE)—R/W. This bit is cleared by RSMRST#, but not on any other reset.

0 = Disable.

1 = Allows an interrupt to occur with a time base set with the RS bits of register A.

Alarm Interrupt Enable (AIE)—R/W. This bit is cleared by RSMRST#, but not on any other reset.

0 = Disable.

1 = Allows an interrupt to occur when the AF is set by an alarm match from the update cycle. An

alarm can occur once a second, one an hour, once a day, or one a month.

Update-ended Interrupt Enable (UIE)—R/W. This bit is cleared by RSMRST#, but not on any other

reset.

0 = Disable.

1 = Allows an interrupt to occur when the update cycle ends.

Square Wave Enable (SQWE)—R/W. This bit serves no function in the ICH2. It is left in this register

bank to provide compatibility with the Motorola* 146818B. The ICH2 has no SQW pin. This bit is

cleared by RSMRST#, but not on any other reset.

Data Mode (DM)—R/W. Specifies either binary or BCD data representation. This bit is not affected by

RSMRST# nor any other reset signal.

0 = BCD

1 = Binary

Hour Format (HOURFORM)—R/W. Indicates the hour byte format. This bit is not affected by

RSMRST# nor any other reset signal.

0 = Twelve-hour mode. In twelve hour mode, the seventh bit represents AM as zero and PM as one.

1 = Twenty-four hour mode.

Daylight Savings Enable (DSE)—R/W. Triggers two special hour updates per year. The days for the

hour adjustment are those specified in United States federal law as of 1987, which is different than

previous years. This bit is not affected by RSMRST# nor any other reset signal.

0 = Daylight Savings Time updates do not occur.

1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to 3:00:00 AM.

b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it is changed to

1:00:00 AM. The time must increment normally for at least two update cycles (seconds) previous

to these conditions for the time change to occur properly.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-49

LPC Interface Bridge Registers (D31:F0)

9.6.2.3

RTC_REGC—Register C (Flag Register)

RTC Index:

Default Value:

Lockable:

0Ch

Attribute:

Size:

Power Well:

8-bit

RTC

00U00000 (U: Undefined)

Writes to Register C have no effect.

Bit

Description

Interrupt Request Flag (IRQF)—RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This also causes

the CH_IRQ_B signal to be asserted. This bit is cleared upon RSMRST# or a read of Register C.

Periodic Interrupt Flag (PF)—RO. This bit is cleared upon RSMRST# or a read of Register C.

0 = If no taps are specified via the RS bits in Register A, this flag will not be set.

1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is 1.

Alarm Flag (AF)—RO.

0 = This bit is cleared upon RTCRST# or a read of Register C.

1 = Alarm Flag will be set after all Alarm values match the current time.

Update-ended Flag (UF)—RO.

0 = The bit is cleared upon RSMRST# or a read of Register C.

1 = Set immediately following an update cycle for each second.

3:0

Reserved. Will always report 0.

9.6.2.4

RTC_REGD—Register D (Flag Register)

RTC Index:

Default Value:

Lockable:

0Dh

Attribute:

Size:

Power Well:

R/W

8-bit

RTC

10UUUUUU (U: Undefined)

Bit

Description

Valid RAM and Time Bit (VRT)—R/W.

0 = This bit should always be written as a 0 for write cycle; however, it will return a 1 for read cycles.

1 = The Valid Ram and Time bit is set to 1 when the PWRGD (power good) signal provided is high.

This feature is not typically used.

Reserved. This bit always returns a 0 and should be set to 0 for write cycles.

Date Alarm—R/W. These bits store the date of month alarm value. If set to 000000b, then a don’t

care state is assumed. The host must configure the date alarm for these bits to do anything, yet they

can be written at any time. If the date alarm is not enabled, these bits will return zeros to mimic the

functionality of the Motorola* 146818B. These bits are not affected by RESET.

5:0

9-50

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.7

Processor Interface Registers

9.7.1

NMI_SC—NMI Status and Control Register

I/O Address:

Default Value:

Lockable:

61h

00h

Attribute:

Size:

Power Well:

R/W (some bits RO)

8-bit

Core

Bit

Description

SERR# NMI Source Status (SERR#_NMI_STS)—RO.

1 = PCI agent detected a system error and pulses the PCI SERR# line. This interrupt source is

enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing

to port 61h, this bit must be 0.

IOCHK# NMI Source Status (IOCHK_NMI_STS)—RO.

1 = An ISA agent (via SERIRQ) asserted IOCHK# on the ISA bus. This interrupt source is enabled

by setting bit 3 to 0. To reset the interrupt, set bit 3 to 0 and then set it to 1. When writing to port

61h, this bit must be a 0.

Timer Counter 2 OUT Status (TMR2_OUT_STS)—RO. This bit reflects the current state of the 8254

counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a

determinate value. When writing to port 61h, this bit must be a 0.

Refresh Cycle Toggle (REF_TOGGLE)—RO. This signal toggles from either 0 to 1 or 1 to 0 at a rate

that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a 0.

IOCHK# NMI Enable (IOCHK_NMI_EN)—R/W.

0 = Enabled.

1 = Disabled and cleared.

PCI SERR# Enable (PCI_SERR_EN)—R/W.

0 = SERR# NMIs are enabled.

1 = SERR# NMIs are disabled and cleared.

Speaker Data Enable (SPKR_DAT_EN)—R/W.

0 = SPKR output is a 0.

1 = SPKR output is equivalent to the Counter 2 OUT signal value.

Timer Counter 2 Enable (TIM_CNT2_EN)—R/W.

0 = Disable.

1 = Enable

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-51

LPC Interface Bridge Registers (D31:F0)

9.7.2

NMI_EN—NMI Enable (and Real Time Clock Index)

I/O Address:

Default Value:

Lockable:

70h

80h

Attribute:

Size:

Power Well:

R/W (Special)

8-bit

Core

Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt-Access

Mode. Note, however, that this register is aliased to Port 74h (documented in Table 19-2), and all

bits are readable at that address.

Bits

Description

NMI Enable (NMI_EN)—R/W.

0 = Enable NMI sources.

1 = Disable All NMI sources.

Real Time Clock Index Address (RTC_INDX)—R/W. This data goes to the RTC to select which

6:0

9.7.3

PORT92—Fast A20 and Init Register

I/O Address:

Default Value:

Lockable:

92h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:2

Reserved.

Alternate A20 Gate (ALT_A20_GATE)—R/W. This bit is ORed with the A20GATE input signal to

generate A20M# to the processor.

0 = A20M# signal can potentially go active.

1 = This bit is set when INIT# goes active.

Interrupt Now (INIT_NOW)—R/W. When this bit transitions from a 0 to a 1, the ICH2 will force

INIT# active for 16 PCI clocks.

9.7.4

COPROC_ERR—Coprocessor Error Register

I/O Address:

Default Value:

Lockable:

F0h

00h

Attribute:

Size:

Power Well:

8-bits

Core

Bits

Description

Coprocessor Error (COPROC_ERR)—WO. Any value written to this register will cause IGNNE# to

go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13,

the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, Bit 13) must be 1.

7:0

9-52

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.7.5

RST_CNT—Reset Control Register

I/O Address:

Default Value:

Lockable:

CF9h

00h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:4

Reserved.

Full Reset (FULL_RST)—R/W. This bit is used to determine the states of SLP_S3# and SLP_S5#

after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low (with

RSMRST# high), or after two TCO time-outs.

1 = ICH2 will drive SLP_S3# and SLP_S5# low for 3–5 seconds.

0 = ICH2 will keep SLP_S3# and SLP_S5# high.

Reset Processor (RST_CPU)—R/W. When this bit transitions from a 0 to a 1, it initiates a hard or

soft reset, as determined by the SYS_RST bit (bit 1 of this register).

System Reset (SYS_RST)—R/W. This bit is used to determine a hard or soft reset to the

processor.

1 = When RST_CPU bit goes from 0 to 1, the ICH2 performs a hard reset by activating PCIRST# for

1 millisecond. It also resets the resume well bits (except for those noted throughout the

datasheet).

0 = When RST_CPU bit goes from 0 to 1, the ICH2 performs a soft reset by activating INIT# for 16

PCI clocks.

Reserved.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-53

LPC Interface Bridge Registers (D31:F0)

9.8

Power Management Registers (D31:F0)

The power management registers are distributed within the PCI Device 31: Function 0 space, as

well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in

the main (core) power well.

Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved

bit, the value should always be 0. Software should not attempt to use the value read from a reserved

bit, as it may not be consistently 1 or 0.

9.8.1

Power Management PCI Configuration Registers (D31:F0)

Table 9-8 shows a small part of the configuration space for PCI Device 31: Function 0. It includes

only those registers dedicated for power management. Some of the registers are only used for

Legacy Power management schemes.

Table 9-8. PCI Configuration Map (PM—D31:F0)

Offset

Mnemonic

ACPI Base Address

Default

Type

40h–43h

44h

ACPI_BASE

ACPI_CNTL

00000001h

00h

R/W

ACPI Control

A0h

GEN_PMCON_1

GEN_PMCON_2

GEN_PMCON_3

GPI_ROUT

General Power Management Configuration 1

General Power Management Configuration 2

General Power Management Configuration 3

GPI Route Control

0000h

A2h

0000h

A4h

00h

B8–BBh

00000000h

TRP_FWD_EN

MON[n]_TRP_RNG

MON_TRP_MSK

I/O Monitor Trap Forwarding Enable

I/O Monitor[4:7] Trap Range

C4–CAh

CCh

0000h

R/W

I/O Monitor Trap Range Mask

9.8.1.1

GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)

Offset Address:

Default Value:

Lockable:

A0h

00h

Attribute:

Size:

Usage:

R/W

16-bit

ACPI, Legacy

Core

Power Well:

Bit

Description

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

15:12

Global Standby Timer Timeout Count (GST_TIMEOUT) — R/W. For the ICH2-M, this field sets

the number of clock ticks that the Global Standby Timer counts before generating a wake event.

The GST starts counting when the ICH2-M enters the S1 state. If a value of 0h is entered in this

field, the GST does not count and no wake event is generated. The GST_TICK bit sets the tick rate.

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

Global Standby Timer Tick Rate (GST_TICK) — R/W.

0 = 1 minute resolution. This yields a GST timeout range of 1 to 15 minutes.

1 = 32 minute resolution, This yields a GST timeout range of 32 minutes to 8 hours.

9-54

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

Software SMI Rate Select (SWSMI_RATE_SEL)—R/W.

0 = SWSMI Timer will time out in 64 ms ± ±4 ms (default).

1 = SWSMI Timer will time out in 1.5 ms ± ±0.5 ms.

PWRBTN# Level (PWRBTN_LVL)—RO. This read-only bit indicates the current state of the

PWRBTN# signal.

8:7

0 = Low.

1 = High.

Reserved.

iiA64 Processor Mode Enable (A64_EN)—R/W. Set by software to indicate the presence of an

iA64 processor.

0 = iA32 processor mode.

1 = iA64 processor mode.

CPU SLP# Enable (CPUSLP_EN)—R/W.

0 = Disable..

ICH2 (82801BA):

1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the processor power.

Note that CPUSLP# will go active on entry to S3, S4 and S5 even if this bit is not set.

ICH2-M (82801BAM):

1 = Enables the CPUSLP# signal to go active in the C3 state. This reduces the processor power.

Note that CPUSLP# goes active during SpeedStep™ transitions and on entry to S1, S3, S4 and

S5 even if this bit is not set.

Reserved.

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

™

Intel SpeedStep Enable (SS_EN)— R/W.

™

0 = Intel SpeedStep logic is disabled and the SS_CNT register will not be visible (reads to

SS_CNT return 00h and writes have no effect).

™

1 = Intel SpeedStep logic is enabled.

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

PCI CLKRUN# Enable (CLKRUN_EN)— R/W.

0 = Disable. ICH2-M drives the CLKRUN# signal low.

1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and STP_PCI#

signals.

Note that when the SLP_EN# bit is set, the ICH2-M drives the CLKRUN# signal low, regardless of

the state of the CLKRUN_EN bit. This ensures that the PCI and LPC clocks continue running during

a transition to a sleep state.

Periodic SMI# rate Select (PER_SMI_SEL)—R/W. Set by software to control the rate at which

periodic SMI# is generated.

00 = 1 minute

1:0

01 = 32 seconds

10 = 16 seconds

11 = 8 seconds

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-55

LPC Interface Bridge Registers (D31:F0)

9.8.1.2

GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0)

Offset Address:

Default Value:

Lockable:

A2h

00h

Attribute:

Size:

Usage:

R/WC

16-bit

ACPI, Legacy

Resume

Power Well:

Bit

Description

7:2

Reserved.

CPU Power Failure (CPUPWR_FLR)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position..

ICH2 (82801BA):

1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low.

ICH2-M (82801BAM):

1 = Indicates that the VGATE signal from the processor’s VRM went low. This bit will not be set if

™

VGATE went low due to a Intel SpeedStep transition.

PWROK Failure (PWROK_FLR)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position, or when the system goes into a G3

state.

1 = This bit will be set any time PWROK goes low, when the system was in S0 or S1 state. The bit

will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state.

Note: Traditional designs have a reset button logically ANDed with the PWROK signal from the

power supply and the processor’s voltage regulator module. If this is done with the ICH2, the

PWROK_FLR bit will be set. The ICH2 treats this internally as if the RSMRST# signal had

gone active. However, it is not treated as a full power failure. If PWROK goes inactive and

then active (but RSMRST# stays high), then the ICH2 will reboot (regardless of the state of

the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high, then this

is a full power failure and the reboot policy is controlled by the AFTERG3 bit.

9-56

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.8.1.3

GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0)

Offset Address:

Default Value:

Lockable:

A4h

00h

Attribute:

Size:

Usage:

R/W

8-bit

ACPI, Legacy

RTC

Power Well:

Bit

Description

7:3

Reserved.

RTC Power Status (RTC_PWR_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Indicates that the RTC battery was removed or failed. This bit is set when RTCRST# signal is

low.

Note: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or

GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using

a jumper to pull VccRTC low.

Power Failure (PWR_FLR)—R/WC. This bit is in the RTC well and is not cleared by any type of

reset except RTCRST#.

0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software

clears this bit by writing a 1 to the bit position.

1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed.

Note: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or

GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using

a jumper to pull VccRTC low.

After G3 State Select (AFTERG3_EN)—R/W. Determines what state to go to when power is re-

applied after a power failure (G3 state). This bit is in the RTC well and is not cleared by any type of

reset except writes to CF9h or RTCRST#.

0 = System will return to S0 state (boot) after power is re-applied.

1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the

S5 state, the only enabled wake event is the Power Button or any enabled wake event that was

preserved through the power failure.

9.8.1.4

GPI_ROUT—GPI Routing Control Register (PM—D31:F0)

Offset Address:

Default Value:

Lockable:

B8h–BBh

0000h

Attribute:

Size:

Power Well:

R/W

32-bit

Resume

Bit

Description

GPI[15] Route—R/W. See bits 1:0 for description.

Same pattern for GPI[14] through GPI[3]

31:30

5:4

3:2

GPI[2] Route—R/W. See bits 1:0 for description.

GPI[1] Route—R/W. See bits 1:0 for description.

GPI[0] Route—R/W. GPIO[13:11,8:6,4:3,1:0] can be routed to cause an SMI or SCI when the

GPI[n]_STS bit is set. If the GPIO is not set to an input, this field has no effect.

If the system is in an S1–S5 state and if the GPE1_EN bit is also set, then the GPI can cause a

Wake event, even if the GPI is NOT routed to cause an SMI# or SCI.

1:0

00 = No effect.

01 = SMI# (if corresponding GPE1_EN bit is also set)

10 = SCI (if corresponding GPE1_EN bit is also set)

11 = Reserved

Note: GPIOs that are not implemented will not have the corresponding bits implemented in this register.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-57

LPC Interface Bridge Registers (D31:F0)

9.8.1.5

TRP_FWD_EN—IO Monitor Trap Forwarding Enable Register

(PM—D31:F0)

Offset Address:

Default Value:

Lockable:

C0h

00h

Attribute:

Size:

Usage:

R/W (Special)

8 bits

Legacy Only

Power Well:

Core

The ICH2 uses this register to enable the monitors to forward cycles to LPC, independent of the

POS_DEC_EN bit and the bits that enable the monitor to generate an SMI#. The only criteria is

that the address passes the decoding logic as determined by the MON[n]_TRP_RNG and

MON_TRP_MSK register settings.

Bit

Description

Monitor 7 Forward Enable (MON7_FWD_EN)—R/W.

0 = Disable. Cycles trapped by I/O Monitor 7 will not be forwarded to LPC.

1 = Enable. Cycles trapped by I/O Monitor 7 will be forwarded to LPC.

Monitor 6 Forward Enable (MON6_FWD_EN)—R/W.

0 = Disable. Cycles trapped by I/O Monitor 6 will not be forwarded to LPC.

1 = Enable. Cycles trapped by I/O Monitor 6 will be forwarded to LPC.

Monitor 5 Forward Enable (MON5_FWD_EN)—R/W.

0 = Disable. Cycles trapped by I/O Monitor 5 will not be forwarded to LPC.

1 = Enable. Cycles trapped by I/O Monitor 5 will be forwarded to LPC.

Monitor 4 Forward Enable (MON4_FWD_EN)—R/W.

0 = Disable. Cycles trapped by I/O Monitor 4 will not be forwarded to LPC.

1 = Enable. Cycles trapped by I/O Monitor 4 will be forwarded to LPC.

3:0

Reserved.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.8.1.6

MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register for

Devices 4–7 (PM—D31:F0)

Offset Address:

Default Value:

Lockable:

C4h, C6h, C8h, CAh

00h

Attribute:

Size:

Usage:

R/W

16 bits

Legacy Only

Power Well:

Core

These registers set the ranges that Device Monitors 4–7 should trap. Offset 4Ch corresponds to

Monitor 4. Offset C6h corresponds to Monitor 5, etc.

If the trap is enabled in the MON_SMI register and the address is in the trap range (and passes the

mask set in the MON_TRP_MSK register) the ICH2 generates an SMI#. This SMI# occurs if the

address is positively decoded by another device on PCI or by the ICH2 (because it would be

forwarded to LPC or some other ICH2 internal registers). The trap ranges should not point to

registers in the ICH2’s internal IDE, USB, AC’97 or LAN I/O space. If the cycle is to be claimed

by the ICH2 and targets one of the permitted ICH2 internal registers (interrupt controller, RTC,

etc.), the cycle will complete to the intended target and an SMI# will be generated (this is the same

functionality as the ICH component). If the cycle is to be claimed by the ICH2 and the intended

target is on LPC, an SMI# will be generated but the cycle will only be forwarded to the intended

target if forwarding to LPC is enabled via the TRP_FWD_EN register settings.

Bit

Description

Monitor Trap Base Address (MON[n]_TRAP_BASE)—R/W. Base I/O locations that MON[n] traps

(where n = 4, 5, 6 or 7). The range can be mapped anywhere in the processor I/O space

(0–64 KB).

15:0

Any access to the range will generate an SMI# if enabled by the associated DEV[n]_TRAP_EN bit in

the MON_SMI register (PMBASE +40h).

9.8.1.7

MON_TRP_MSK—I/O Monitor Trap Range Mask Register for

Devices 4–7 (PM—D31:F0)

Offset Address:

Default Value:

Lockable:

CCh

00h

Attribute:

Size:

Usage:

R/W

16 bits

Legacy Only

Power Well:

Core

Bit

Description

Monitor 7 Forward Mask (MON7_MASK)—R/W. Selects low 4-bit mask for the I/O locations that

MON7 will trap. Similar to MON4_MASK.

15:12

11:8

7:4

Monitor 6 Forward Mask (MON6_MASK)—R/W. Selects low 4-bit mask for the I/O locations that

MON6 will trap. Similar to MON4_MASK.

Monitor 5 Forward Mask (MON5_MASK)—R/W. Selects low 4-bit mask for the I/O locations that

MON5 will trap. Similar to MON4_MASK.

Monitor 4 Forward Mask (MON4_MASK)—R/W. Selects low 4-bit mask for the I/O locations that

MON7 will trap. When a mask bit is set to a 1, the corresponding bit in the base I/O selection will not

be decoded.

3:0

For example, if MON4_TRAP_BASE = 1230h, and MON4_MSK = 0011b, the ICH2 will decode

1230h, 1231h, 1232h, and 1233h for Monitor 4.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-59

LPC Interface Bridge Registers (D31:F0)

9.8.2

APM I/O Decode

Table 9-9 shows the I/O registers associated with APM support. This register space is enabled in

the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location).

Table 9-9. APM Register Map

Address

Mnemonic

Default

Type

B2h

B3h

APM_CNT

APM_STS

Advanced Power Management Control Port

Advanced Power Management Status Port

00h

R/W

9.8.2.1

APM_CNT—Advanced Power Management Control Port Register

I/O Address:

Default Value:

Lockable:

B2h

00h

Attribute:

Size:

Usage:

R/W

8-bit

Legacy Only

Power Well:

Core

Bit

Description

Used to pass an APM command between the OS and the SMI handler. Writes to this port not only

store data in the APMC register but also generate an SMI# when the APMC_EN bit is set.

7:0

9.8.2.2

APM_STS—Advanced Power Management Status Port Register

I/O Address:

Default Value:

Lockable:

B3h

00h

Attribute:

Size:

Usage:

R/W

8-bit

Legacy Only

Power Well:

Core

Bit

Description

Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and

is not effected by any other register or function (other than a PCI reset).

7:0

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.8.3

Power Management I/O Registers

Table 9-10 shows the registers associated with ACPI and Legacy power management support.

These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be

moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the

ACPI 1.0 specification, and use the same bit names.

Note: All reserved bits and registers will always return 0 when read, and will have no effect when written.

Table 9-10. ACPI and Legacy I/O Register Map

PMBASE+

Offset

ACPI Pointer

Default

Attributes

00–01h

02–03h

04–07h

08–0Bh

0Ch

PM1 Status

PM1 Enable

PM1 Control

PM1 Timer

Reserved

PM1a_EVT_BLK

PM1a_EVT_BLK+2

PM1a_CNT_BLK

PMTMR_BLK

—

0000h

R/W

00000000h

—

10h–13h

14h

Processor Control

Level 2

P_BLK

00000000h

00h

R/W

P_BLK+4

ICH2 (82801BA):

Reserved

—

15h

16–19h

20h

ICH2-M (82801BAM):

Level 3

P_BLK+5

—

0000h

—

Reserved

ICH2 (82801BA):

Reserved

—

ICH2-M (82801BAM):

PM2 Control

PM2a_CNT_BLK

0000h

—

R/W

28–29h

2A–2Bh

2C–2D

2E–2F

30–31h

34–35h

36–3Fh

40h

General Purpose Event 0 Status

General Purpose Event 0 Enables

General Purpose Event 1 Status

General Purpose Event 1 Enables

SMI# Control and Enable

SMI Status Register

GPE0_BLK

GPE0_BLK+2

GPE1_BLK

GPE1_BLK+2

—

Reserved

Monitor SMI Status

R/W

—

42h

Reserved

44h

Device Trap Status

0000h

Last Cycle

R/W

48h

Trap Enable register

4Ch–4Dh

4Eh

Bus Address Tracker

Bus Cycle Tracker

ICH2 (82801BA):

Reserved

—

50h

ICH2-M (82801BAM):

SpeedStep™ Control

—

00h

—

51–5Fh

Reserved

60h–7Fh

Reserved for TCO Registers

—

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-61

LPC Interface Bridge Registers (D31:F0)

9.8.3.1

PM1_STS—Power Management 1 Status Register

I/O Address:

PMBASE + 00h

(ACPI PM1a_EVT_BLK)

0000h

Attribute:

Size:

Usage:

R/WC

16-bit

ACPI or Legacy

Default Value:

Lockable:

Power Well:

Bits 0–7: Core,

Bits 8–15: Resume,

except Bit 11 in RTC

If bit 10 or 8 in this register is 1 and the corresponding _EN bit is set in the PM1_EN register, ICH2

generates a Wake Event. Once back in an S0 state (or if already in S0 state when the event occurs),

ICH2 also generates an SCI if the SCI_EN bit is set or an SMI# if the SCI_EN bit is not set.

Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an

SMI# or SCI.

Bit

Description

Wake Status (WAK_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write but

is reset by RSMRST#.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN bit) and an

enabled wake event occurs. Upon setting this bit, the ICH2 will transition the system to the ON

state.

If the AFTERG3_EN bit is not set and a power failure occurs without the SLP_EN bit set, the system

will return to an S0 state when power returns, and the WAK_STS bit will not be set. For the

82801BAM ICH2-M, power failure could result from removing the batteries.

If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set,

the system will go into an S5 state when power returns and a subsequent wake event will cause the

WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by either a

Power Button press or an enabled wake event that was preserved through the power failure (enable

bit in the RTC well).

14:12 Reserved

Power Button Override Status (PRBTNOR_STS)—R/WC. This bit is not affected by hard resets

caused by a CF9 write and is not reset by RSMRST#. Thus, this bit will be preserved through a

power failure.

0 = The BIOS or SCI handler can clear this bit by writing a 1 to it.

1 = Set by hardware anytime a Power Button Override Event occurs which occurs when the power

button is pressed for at least 4 consecutive seconds. The power button override causes an

unconditional transition to the S5 state and sets the AFTERG3 bit. This bit can also be set by

the SMBus Slave logic.

RTC Status (RTC_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write but is

reset by RSMRST#.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal).

Additionally if the RTC_EN bit is set, the setting of the RTC_STS bit will generate a wake event.

Reserved

Power Button Status (PWRBTN_STS)—R/WC. This bit is not affected by hard resets caused by a

CF9 write.

1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any

other enable bit.

In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if

SCI_EN is not set) will be generated.

In any sleeping state S1–S5, while PWRBTN_EN and PWRBTN_STS are both set, a wake

event is generated.

0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the

PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state

with only PWRBTN# enabled as a wake event.

This bit can be cleared by software by writing a one to the bit position.

9-62

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

7:6

Reserved

Global Status (GBL _STS)—R/WC.

1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has

a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit.

0 = The SCI handler should then clear this bit by writing a 1 to the bit location.

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

Bus Master Status (BM_STS)— R/WC.

1 = Set by the ICH2-M when a bus master requests a break from the C3 state (the bus master

break events are generated by PIRQ[x]# assertion or bus master activity by any of ICH2-M’s

internal bus masters). Bus master activity is detected by any of the PCI requests being active,

any internal bus master request being active, the AGPBUSY# signal being active, or activity on

either of the ICH2-M’s USB Controllers. A USB Controller is considered active if all three of the

following conditions are true

1. The controller is not in Global Suspend

2. At least one of the controller’s ports is not suspended

3. The USB RUN bit is set

Bus Master IDE Controller activity also causes BM_STS to be set. The ICH2-M’s BMIDE

Controller is considered active when the Controller’s Start bit is set.

0 = Software clears this bit by writing a 1 to the bit position.

Reserved

3:1

Timer Overflow Status (TMROF_STS)—R/WC.

1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23).

This will occur every 2.3435 seconds. When the TMROF_EN bit is set, then the setting of the

TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN).

0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-63

LPC Interface Bridge Registers (D31:F0)

9.8.3.2

PM1_EN—Power Management 1 Enable Register

I/O Address:

PMBASE + 02h

(ACPI PM1a_EVT_BLK + 2)

0000h

Attribute:

Size:

Usage:

R/W

16-bit

ACPI or Legacy

Default Value:

Lockable:

Power Well:

Bits 0–7: Core,

Bits 8–15: Resume

Bit

Description

15:11 Reserved.

RTC Event Enable (RTC_EN)—R/W. This bit is in the RTC well to allow an RTC event to wake after

a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override

event.

1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes

active.

0 = No SCI (or SMI#) or wake event is generated then RTC_STS goes active.

Power Button Enable (PWRBTN_EN)—R/W. This bit is used to enable the setting of the

PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no

effect on the PWRBTN_STS bit being set by the assertion of the power button. The Power Button is

always enabled as a Wake event.

0 = Disable.

1 = Enable.

Global Enable (GBL_EN)—R/W. When both the GBL_EN and the GBL_STS are set, an SCI is

raised.

0 = Disable.

1 = Enable SCI on GBL_STS going active.

Timer Overflow Interrupt Enable (TMROF_EN)—R/W. Works in conjunction with the SCI_EN bit

as described below:

TMROF_EN

SCI_EN

Effect when TMROF_STS is set

No SMI# or SCI

SMI#

SCI

9-64

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.8.3.3

PM1_CNT—Power Management 1 Control Register

I/O Address:

PMBASE + 04h

(ACPI PM1a_CNT_BLK)

0000h

Attribute:

Size:

R/W

32-bit

Default Value:

Lockable:

Usage:

ACPI or Legacy

Power Well:

Bits 0–7: Core,

Bits 8–15: Resume

Bit

Description

Sleep Enable (SLP_EN)—WO. Setting this bit causes the system to sequence into the Sleep state

defined by the SLP_TYP field.

Sleep Type (SLP_TYP)—R/W. This 3-bit field defines the type of Sleep the system should enter

when the SLP_EN bit is set to 1.

000 = ON: Typically maps to S0 state..

001 = ICH2 (82801BA): Assert STPCLK#. Puts processor in Stop-Grant state. Optional to assert

CPUSLP# to put processor in sleep state: Typically, maps to S1 state.

ICH2-M (82801BAM): Reserved.

010 = ICH2 (82801BA): Reserved

ICH2-M (82801BAM): Assert SLP_S1#: Typically, maps to S1 state.

12:10

011 = Reserved

100 = Reserved

101 = Suspend-To-RAM. Assert SLP_S1# and SLP_S3#; typically, maps to S3 state.

110 = Suspend-To-Disk. Assert SLP_S1#, SLP_S3#, and SLP_S5# SLP_S3# and, SLP_S5#;

typically, maps to S4 state.

111 = Soft Off. Assert SLP_S1#, SLP_S3#, and SLP_S5# SLP_S3#, and SLP_S5#; typically, maps

to S5 state.

Global Release (GBL_RLS)—WO.

1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has

corresponding enable and status bits to control its ability to receive ACPI events.

0 = This bit always reads as 0.

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

Bus Master Reload (BM_RLD)— R/W. This bit is reset to 0 by PCIRST#

0 = Bus master requests do not cause a break from the C3 state.

1 = Enable Bus Master requests (internal, external or AGPBUSY#) to cause a break from the C3

state.

SCI Enable (SCI_EN)—R/W. Selects the SCI interrupt or the SMI# interrupt for various events

including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS.

0 = These events will generate an SMI#.

1 = These events will generate an SCI.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-65

LPC Interface Bridge Registers (D31:F0)

9.8.3.4

PM1_TMR—Power Management 1 Timer Register

I/O Address:

PMBASE + 08h

(ACPI PMTMR_BLK)

Attribute:

Size:

Usage:

32-bit

ACPI

Default Value:

Lockable:

Power Well:

xx000000h

Core

Bit

Description

31:24 Reserved

Timer Value (TMR_VAL)—RO. Returns the running count of the PM timer. This counter runs off a

3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to zero during a PCI reset and then

continues counting as long as the system is in the S0 state.

23:0

Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit is

set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit is set, an SCI

interrupt is also generated.

9.8.3.5

PROC_CNT—Processor Control Register

I/O Address:

PMBASE + 10h

(ACPI P_BLK)

00000000h

Attribute:

Size:

Usage:

R/W

32-bit

ACPI or Legacy

Default Value:

Lockable:

No (bits 7:5 are write once)

Power Well:

Core

Bit

Description

31:18 Reserved.

Throttle Status (THTL_STS)—RO.

0 = No clock throttling is occurring (maximum processor performance).

1 = Indicates that the clock state machine is in some type of low power state (where the processor

is not running at its maximum performance): thermal throttling or hardware throttling.

16:9

Reserved

Force Thermal Throttling (FORCE_THTL)—R/W. Software can set this bit to force the thermal

throttling function. This has the same effect as the THRM# signal being active for 2 seconds.

0 = No forced throttling.

1 = Throttling at the duty cycle specified in THRM_DTY starts immediately (no 2 second delay), and

no SMI# is generated.

Thermal Duty Cycle (THRM_DTY). This write-once 3-bit field determines the duty cycle of the

throttling when the thermal override condition occurs. The duty cycle indicates the approximate

percentage of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK# throttle

period is 1024 PCICLKs. Note that the throttling only occurs if the system is in the C0 state. If in the

C2 state, no throttling occurs.

There is no enable bit for thermal throttling, because it should not be disabled. Once the

THRM_DTY field is written, any subsequent writes will have no effect until PCIRST# goes active.

THRM_DTY

Throttle Mode

PCI Clocks

000

RESERVED (Default)

(Will be 50%)

512

7:5

001

010

011

100

101

110

111

87.5%

75.0%

62.5%

50%

896

768

640

512

384

256

128

37.5%

25%

12.5%

9-66

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

Throttling Enable (THTL_EN). When this bit is set and the system is in a C0 state, processor-

controlled STPCLK# throttling is enabled. The duty cycle is selected in the THTL_DTY field.

0 = Disable

1 = Enable

Throttling Duty Cycle (THTL_DTY). This 3-bit field determines the duty cycle of the throttling when

the THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the STPCLK#

signal is asserted (low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs.

THTL_DTY

Throttle Mode

PCI Clocks

000

RESERVED (Default)

(Will be 50%)

512

001

010

011

100

101

110

111

87.5%

75.0%

62.5%

50%

896

768

640

512

384

256

128

3:1

37.5%

25%

12.5%

Reserved

9.8.3.6

LV2—Level 2 Register

I/O Address:

PMBASE + 14h

(ACPI P_BLK+4)

00h

Attribute:

Size:

Usage:

8-bit

ACPI or Legacy

Default Value:

Lockable:

Power Well:

Core

Bit

Description

Reads to this register return all zeros; writes have no effect. Reads to this register generate a “enter

a level 2 power state” (C2) to the clock control logic. This causes the STPCLK# signal to go active,

and stay active until a break event occurs. Throttling (due either to THTL_EN or THRM# override)

will be ignored.

7:0

9.8.3.7

LV3—Level 3 Register (82801BAM ICH2-M)

I/O Address:

PMBASE + 15h (ACPI P_BLK + 5)

Attribute:

Default Value:

Lockable:

00h

Size:

Usage:

Power Well:

8-bit

ACPI or Legacy

Core

Bit

Description

Reads to this register return all zeros, writes to this register have no effect. Reads to this register

generate an “enter a C3 power state” to the clock control logic. The C3 state persists until a break

event occurs.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-67

LPC Interface Bridge Registers (D31:F0)

9.8.3.8

PM2_CNT—Power Management 2 Control (82801BAM ICH2-M)

I/O Address:

PMBASE + 20h

(ACPI PM2_BLK)

00h

Attribute:

Size:

Usage:

R/W

8-bit

ACPI

Default Value:

Lockable:

Power Well:

Core

Bit

Description

7:1

Reserved.

Arbiter Disable (ARB_DIS)— R/W.

0 = Enable system arbiter. The arbiter can grant the bus to bus masters (internal devices or external

PCI devices), other than the processor.

1 = Disable system arbiter (default). Processor has ownership of the system bus and memory. No

bus masters (internal or external) are granted the bus. Note that after the arbiter is disabled, the

processor must not initiate any down-bound reads to PCI devices that may have up-bound

posted data, as this will result in system deadlock.

9.8.3.9

GPE0_STS—General Purpose Event 0 Status Register

I/O Address:

PMBASE + 28h

(ACPI GPE0_BLK)

0000h

Attribute:

Size:

Usage:

R/WC

16-bit

ACPI

Default Value:

Lockable:

Power Well:

Resume

Note: This register is symmetrical to the General Purpose Event 0 Enable Register. If the corresponding

seen bit is set, then when the _STS bit get set, ICH2 generates a Wake Event. Once back in an S0

state (or if already in an S0 state when the event occurs), ICH2 also generates an SCI if the SCI_EN

bit is set, or an SMI# if the SCI_EN bit is not set. There will be no SCI/SMI# or wake event on

THRMOR_STS since there is no corresponding x_EN bit. None of these bits are reset by CF9h

write. All are reset by RSMRST#.

Bit

Description

15:12 Reserved.

PME Status (PME_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set, and

the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or SMI#

(if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1–S4 state (or S5 state

due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a

wake event, and an SCI will be generated. If the system is in an S5 state due to power button

override or a power failure, then PME_STS will not cause a wake event or SCI.

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

BATLOW_STS — R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when the BATLOW# signal is asserted.

9-68

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

Global Standby Timer Status (GST_STS)— R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware to indicate that the wake event was due to GST timeout. This bit will only be

set when the system was in the S1 state.

RI_STS—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when the RI# input signal goes active.

SMBus Wake Status (SMB_WAK_STS)—R/WC. SMBus Wake Status—R/WC. The SMBus

controller can independently cause an SMI# or SCI; thus, this bit does not need to do so (unlike the

other bits in this register).

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware to indicate that the wake event was caused by the ICH2’s SMBus logic. This

bit is set by the WAKE/SMI# command type, even if the system is already awake. The SMI

handler should then clear this bit.

TCO SCI Status (TCOSCI_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when the TCO logic causes an SCI.

AC97 Status (AC97_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit gets

set only from the following two cases:

1. ACSDIN[1] or ACSDIN[0] is high and BITCLK is not oscillating, or

2. The GSCI bit is set (section 13.2.9, NAMBAR +30h, bit 0)

USB Controller 2 Status (USB2_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when USB Controller 2 needs to cause a wake. Wake event will be generated

if the corresponding USB2_EN bit is set.

USB Controller 1 Status (USB1_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware when USB Controller 1 needs to cause a wake. Wake event will be generated

if the corresponding USB1_EN bit is set.

Reserved.

Thermal Interrupt Override Status (THRMOR_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = This bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling the

processor’s clock at the THRM_DTY ratio. This will not cause an SMI#, SCI, or wake event.

Thermal Interrupt Status (THRM_STS)—R/WC.

0 = Software clears this bit by writing a 1 to the bit position.

1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL bit.

Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also generate

a power management event (SCI or SMI#).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-69

LPC Interface Bridge Registers (D31:F0)

9.8.3.10

GPE0_EN—General Purpose Event 0 Enables Register

I/O Address:

PMBASE + 2Ah

(ACPI GPE0_BLK + 2)

0000h

Attribute:

Size:

Usage:

R/W

16-bit

ACPI

Default Value:

Lockable:

Power Well:

Bits 0–7 Resume,

Bits 8–15 RTC

Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this

cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.

Bit

Description

15:12

Reserved.

PME# Enable (PME_EN)—R/W.

0 = Disable.

1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be

a wake event from the S1–S4 state or from S5 (if entered via SLP_EN, but not power button

override).

ICH2 (82801BA):

Reserved

ICH2-M (82801BAM):

BATLOW_EN — R/W.

0 = Disable.

1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when

it goes low. This bit does not prevent the BATLOW# signal from inhibiting the wake event.

Reserved

RI_EN—R/W. The value of this bit will be maintained through a G3 state and is not affected by a

hard reset caused by RSMRST# or a CF9h write. Assertion of RTCRST# resets this bit.

0 = Disable.

1 = Enables the setting of the RI_STS to generate a wake event.

Reserved

TCO SCI Enable (TCOSCI_EN)—R/W.

0 = Disable.

1 = Enables the setting of the TCOSCI_STS to generate an SCI.

AC97 Enable (AC97_EN)—R/W.

0 = Disable.

1 = Enables the setting of the AC97_STS to generate a wake event.

USB Controller 2 Enable (USB2_EN)—R/W.

0 = Disable.

1 = Enables the setting of the USB2_STS to generate a wake event.

USB Controller 1 Enable (USB1_EN)—R/W.

0 = Disable.

1 = Enables the setting of the USB1_STS to generate a wake event.

Thermal Pin Polarity (THRM#_POL)—R/W. This bit controls the polarity of the THRM# pin

needed to set the THRM_STS bit.

0 = Low value on the THRM# signal will set the THRM_STS bit.

1 = HIGH value on the THRM# signal will set the THRM_STS bit.

Reserved.

Thermal Signal Reporting Enable (THRM_EN)—R/W.

0 = Disable.

1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the

THRM_STS bit and generate a power management event (SCI or SMI).

9-70

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.8.3.11

GPE1_STS—General Purpose Event 1 Status Register

I/O Address:

PMBASE + 2Ch

(ACPI GPE1_BLK)

0000h

Attribute:

Size:

Usage:

R/WC

16-bit

ACPI

Default Value:

Lockable:

Power Well:

Resume

Note: This register is symmetrical to the General Purpose Event 1 Enable Register. GPIOs that are not

implemented will not have the corresponding bits implemented in this register.

Note: Bits 5 and 2 are not implemented since GPIO5 and GPIO2 are not implemented.

Bit

Description

GPI[15:6] Status (GPI[15:6]_STS)—R/WC.

0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal

is not active. (The status bit cannot be cleared while the corresponding signal is still active).

1 = These bits are set any time the corresponding GPIO is set up as an input and the

corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set).

15:6

If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is

set, then:

- If the system is in an S1_S5 state, the event will also wake the system.

- If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will

be generated, depending on the GPI_ROUT bits for the corresponding GPI.

Reserved

GPI[4:3] Status (GPI[4:3]_STS)—R/WC.

0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal

is not active. (The status bit cannot be cleared while the corresponding signal is still active).

1 = These bits are set any time the corresponding GPIO is set up as an input and the

corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set).

4:3

If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is

set, then:

- If the system is in an S1_S5 state, the event will also wake the system.

- If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will

be generated, depending on the GPI_ROUT bits for the corresponding GPI.

Reserved

GPI[1:0] Status (GPI[1:0]_STS)—R/WC.

0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal

is not active. (The status bit cannot be cleared while the corresponding signal is still active).

1 = These bits are set any time the corresponding GPIO is set up as an input and the

corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set).

1:0

If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is

set, then:

- If the system is in an S1_S5 state, the event will also wake the system.

- If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will be

generated, depending on the GPI_ROUT bits for the corresponding GPI.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-71

LPC Interface Bridge Registers (D31:F0)

9.8.3.12

GPE1_EN—General Purpose Event 1 Enable Register

I/O Address:

PMBASE + 2Eh

(ACPI GPE1_BLK + 2)

0000h

Attribute:

Size:

Usage:

R/W

16-bit

ACPI

Default Value:

Lockable:

Power Well:

Resume

Note: This register is symmetrical to the General Purpose Event 1 Status Register. GPIOs that are not

implemented will not have the corresponding bits implemented in this register. All of the bits in

this register will be cleared by RSMRST#.

Note: Bits 5 and 2 are not implemented since GPIO5 and GPIO2 are not implemented.

Bit

Description

GPI[15:6] Enable (GPI[15:6]_EN)—R/W.

1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event.

15:6

0 = Disable.

Reserved

GPI[4:3] Enable (GPI[4:3]_EN)—R/W.

1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event.

4:3

0 = Disable.

Reserved

GPI[1:0] Enable (GPI[1:0]_EN)—R/W.

1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event.

1:0

0 = Disable.

9.8.3.13

SMI_EN—SMI Control and Enable Register

I/O Address:

Default Value:

Lockable:

PMBASE + 30h

0000h

Attribute:

Size:

Usage:

R/W

32 bit

ACPI or Legacy

Power Well:

Core

Bit

Description

31:15

Reserved

Periodic SMI# Enable (PERIODIC_EN)—R/W.

0 = Disable.

1 = Enables the ICH2 to generate an SMI# when the PERIODIC_STS bit is set in the SMI_STS

TCO Enable (TCO_EN)—R/W.

0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are

caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0,

NMIs will still be routed to cause SMIs.

1 = Enables the TCO logic to generate SMI#.

Reserved

Microcontroller SMI# Enable (MCSMI_EN)—R/W.

0 = Disable.

1 = Enables ICH2 to trap accesses to the microcontroller range (62h or 66h) and generate an

SMI#. Note that ’trapped’ cycles will be claimed by the ICH2 on PCI, but not forwarded to LPC.

10:8

Reserved

9-72

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

BIOS Release (BIOS_RLS)—WO.

0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.

1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit

position by BIOS software.

Software SMI# Timer Enable (SWSMI_TMR_EN)—R/W.

0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the

SMI# will not be generated.

1 = Starts Software SMI# Timer. When the SWSMI timer expires (the time-out period depends

upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated.

SWSMI_TMR_EN stays set until cleared by software.

APMC Enable (APMC_EN)—R/W.

0 = Disable. Writes to the APM_CNT register will not cause an SMI#.

1 = Enables writes to the APM_CNT register to cause an SMI#.

SLP SMI Enable (SLP_SMI_EN)—R/W.

0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software

attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit.

1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the

system will not transition to the sleep state based on that write to the SLP_EN bit.

Legacy USB Enable (LEGACY_USB_EN)—R/W.

0 = Disable.

1 = Enables legacy USB circuit to cause SMI#.

BIOS Enable (BIOS_EN)—R/W.

0 = Disable.

1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit.

End of SMI (EOS)—R/W (special). This bit controls the arbitration of the SMI signal to the

processor. This bit must be set for the ICH2 to assert SMI# low to the processor.

1 = When this bit is set, SMI# signal will be deasserted for 4 PCI clocks before its assertion. In the

SMI handler, the processor should clear all pending SMIs (by servicing them and then clearing

their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-

assert SMI upon detection of an SMI event and the setting of a SMI status bit.

0 = Once the ICH2 asserts SMI# low, the EOS bit is automatically cleared.

Global SMI Enable (GBL_SMI_EN)—R/W.

0 = No SMI# will be generated by ICH2. This bit is reset by a PCI reset event.

1 = Enables the generation of SMI# in the system upon any enabled SMI event.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-73

LPC Interface Bridge Registers (D31:F0)

9.8.3.14

SMI_STS—SMI Status Register

I/O Address:

Default Value:

Lockable:

PMBASE + 34h

0000h

Core

Attribute:

Size:

Usage:

R/W

32-bit

ACPI or Legacy

Power Well:

Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH2 will cause an SMI# (except

bits 8:10 and 12, which do not need enable bits since they are logic ORs of other registers that have

enable bits).

Bit

Description

31:17 Reserved

SMBus SMI Status (SMBUS_SMI_STS)—R/WC.

1 = Indicates that the SMI# was caused by either the SMBus Slave receiving a message, or the

SMBALERT# signal going active. This bit will be set on SMBALERT# assertion only if the

SMBus Host Controller is programmed to generate SMIs (not interrupts).

0 = This bit is cleared by writing a 1 to its bit position.

SERR IRQ SMI Status (SERIRQ_SMI_STS)—RO.

1 = Indicates that the SMI# was caused by the SERIRQ decoder.

0 = SMI# was not caused by SERIRQ decoder. This is not a sticky bit.

Periodic Status (PERIODIC_STS)—R/WC.

1 = This bit will be set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit is

also set, the ICH2 will generate an SMI#.

0 = This bit is cleared by writing a 1 to its bit position.

TCO Status (TCO_STS)—RO.

0 = SMI# not caused by TCO logic.

1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event.

Device Monitor Status (DEVMON_STS)—RO.

1 = Set under any of the following conditions:

- Any of the DEV[7:4]_TRAP_STS bits are set and the corresponding DEV[7:4]_TRAP_EN bits

are also set.

- Any of the DEVTRAP_STS bits are set and the corresponding DEVTRAP_EN bits are also set.

0 = SMI# not caused by Device Monitor.

Microcontroller SMI# Status (MCSMI_STS)—R/WC.

0 = Indicates that there has been no access to the power management microcontroller range (62h or

66h). This bit is cleared by software writing a 1 to the bit position.

1 = Set if there has been an access to the power management microcontroller range (62h or 66h). If

this bit is set, and the MCSMI_EN bit is also set, the ICH2 will generate an SMI#.

GPE1 Status (GPE1_STS)—RO. This bit is a logical OR of the bits in the GPE1_STS register that

are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the

corresponding bit set in the GPE1_EN register. Bits that are not routed to cause an SMI# will have no

effect on the GPE1_STS bit.

0 = SMI# was not generated by a GPI assertion.

1 = SMI# was generated by a GPI assertion.

GPE0 Status (GPE0_STS)—RO. This bit is a logical OR of the bits in the GPE0_STS register that

also have the corresponding bit set in the GPE0_EN register.

0 = SMI# was not generated by a GPE0 event.

1 = SMI# was generated by a GPE0 event.

PM1 Status Register (PM1_STS_REG)—RO. This is an OR of the bits in the ACPI PM1 Status

0 = SMI# was not generated by a PM1_STS event.

1 = SMI# was generated by a PM1_STS event.

Reserved.

9-74

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

Software SMI Timer Status (SWSMI_TMR_STS)—R/WC.

1 = Set by the hardware when the Software SMI# Timer expires.

0 = Software clears this bit by writing a 1 to the bit location.

APM Status (APM_STS)—R/WC.

1 = SMI# was generated by a write access to the APM control register with the APMC_EN bit set.

0 = Software clears this bit by writing a 1 to the bit location.

SLP SMI Status (SLP_SMI_STS)—R/WC.

1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.

0 = Software clears this bit by writing a 1 to the bit location.

Legacy USB Status (LEGACY_USB_STS)—RO. This bit is a logical OR of each of the SMI status

bits in the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable

bits. This bit will not be active if the enable bits are not set.

0 = SMI# was not generated by USB Legacy event.

1 = SMI# was generated by USB Legacy event.

BIOS Status (BIOS_STS)—R/WC.

1 = SMI# was generated due to ACPI software requesting attention (writing a 1 to the GBL_RLS bit

with the BIOS_EN bit set).

0 = This bit cleared by software writing a 1 to its bit position.

Reserved.

1:0

9.8.3.15

MON_SMI—Device Monitor SMI Status and Enable Register

I/O Address:

Default Value:

Lockable:

PMBASE +40h

0000h

Attribute:

Size:

Usage:

R/W, R/WC

16-bit

Legacy Only

Power Well:

Core

Bit

Description

Device 7:4 Trap Status (DEV[7:4]_TRAP_STS)—R/WC. Bit 12 corresponds to Monitor 4, bit 13

corresponds to Monitor 5 etc.

1 = SMI# was caused by an access to the corresponding device monitor’s I/O range.

15:12

0 = SMI# was not caused by the associated device monitor.

Device 7:4 Trap Enable (DEV[7:4]_TRAP_EN)—R/W. Bit 8 corresponds to Monitor 4, bit 9

corresponds to Monitor 5 etc.

1 = Enables SMI# due to an access to the corresponding device monitor’s I/O range.

11:8

7:0

0 = Disable.

Reserved

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-75

LPC Interface Bridge Registers (D31:F0)

9.8.3.16

DEVACT_STS—Device Activity Status Register

I/O Address:

Default Value:

Lockable:

PMBASE +44h

0000h

Attribute:

Size:

Usage:

R/WC

16-bit

Legacy Only

Power Well:

Core

This register is used in conjunction with the Periodic SMI# timer to detect any system activity for

legacy power management.

Bit

Description

15:14

Reserved

ADLIB Activity Status (ADLIB_ACT_STS)—R/WC.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

Keyboard Controller Activity Status (KBC_ACT_STS)—R/WC. KBC (60/64h).

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

MIDI Activity Status (MIDI_ACT_STS)—R/WC.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

Audio Activity Status (AUDIO_ACT_STS)—R/WC. Audio (Sound Blaster “ORed” with MSS).

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

PIRQ[D or H] Activity Status (PIRQDH_ACT_STS)—R/WC.

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to

the bit location.

PIRQ[C or G] Activity Status (PIRQCG_ACT_STS)—R/WC.

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to

the bit location.

PIRQ[B or F] Activity Status (PIRQBF_ACT_STS)—R/WC.

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to

the bit location.

PIRQ[A or E] Activity Status (PIRQAE_ACT_STS)—R/WC.

0 = The corresponding PCI interrupts have not been active.

1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to

the bit location.

Legacy Activity Status (LEG_ACT_STS)—R/WC. Parallel Port, Serial Port 1, Serial Port 2, Floppy

Disk Controller.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

Reserved.

IDE Secondary Drive 1 Activity Status (IDES1_ACT_STS)—R/WC.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

IDE Secondary Drive 0 Activity Status (IDES0_ACT_STS)—R/WC.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

IDE Primary Drive 1 Activity Status (IDEP1_ACT_STS)—R/WC.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

IDE Primary Drive 0 Activity Status (IDEP0_ACT_STS)—R/WC.

0 = Indicates that there has been no access to this device’s I/O range.

1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location.

9.8.3.17

DEVTRAP_EN—Device Trap Enable Register

I/O Address:

Default Value

Lockable:

PMBASE +48h

0000h

Attribute:

Size:

Usage:

R/W

16-bit

Legacy Only

Power Well:

Core

This register enables the individual trap ranges to generate an SMI# when the corresponding status

bit in the DEVACT_STS register is set. When a range is enabled, I/O cycles associated with that

range will not be forwarded to LPC or IDE.

Bit

Description

15:14

Reserved

ADLIB Trap Enable (ADLIB_TRP_EN)—R/W.

0 = Disable.

1 = Enable.

KBC Trap Enable (KBC_TRP_EN)—R/W. KBC (60/64h).

0 = Disable.

1 = Enable.

MIDI Trap Enable (MIDI_TRP_EN)—R/W.

0 = Disable.

1 = Enable.

Audio Trap Enable (AUDIO_TRP_EN)—R/W. Audio (Sound Blaster “ORed” with MSS).

9:6

0 = Disable.

1 = Enable.

Reserved

LEG_IO_TRP_EN—R/W. Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk Controller.

0 = Disable.

1 = Enable.

Reserved.

IDE Secondary Drive 1 Trap Enable (IDES1_TRP_EN)—R/W.

0 = Disable.

1 = Enable.

IDE Secondary Drive 0 Trap Enable (IDES0_TRP_EN)—R/W.

0 = Disable.

1 = Enable.

IDE Primary Drive 1 Trap Enable (IDEP1_TRP_EN)—R/W.

0 = Disable.

1 = Enable.

IDE Primary Drive 0 Trap Enable (IDEP0_TRP_EN)—R/W.

0 = Disable.

1 = Enable.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-77

LPC Interface Bridge Registers (D31:F0)

9.8.3.18

BUS_ADDR_TRACK—Bus Address Tracker Register

I/O Address:

Lockable:

Power Well:

PMBASE +4Ch

Core

Attribute:

Size:

Usage:

16-bit

Legacy Only

This register could be used by the SMI# handler to assist in determining what was the last cycle

from the processor.

Bit

Description

Corresponds to the low 16 bits of the last I/O cycle, as would be defined by the PCI AD[15:0] signals

on the PCI bus (even though it may not be a real PCI cycle). The value is latched based on SMI#

active. This functionality is useful for figuring out which I/O was last being accessed.

15:0

9.8.3.19

BUS_CYC_TRACK—Bus Cycle Tracker Register

I/O Address:

Lockable:

Power Well:

PMBASE +4Eh

Core

Attribute:

Size:

Usage:

8-bit

Legacy Only

This register could be used by the SMM handler to assist in determining what was the last cycle

from the processor.

Bit

Description

Corresponds to the byte enables, as would be defined by the PCI C/BE# signals on the PCI bus

(even though it may not be a real PCI cycle). The value is latched based on SMI# going active.

7:4

Corresponds to the cycle type, as would be defined by the PCI C/BE# signals on the PCI bus (even

though it may not be a real PCI cycle). The value is latched based on SMI# going active.

3:0

™

9.8.3.20

SS_CNT— SpeedStep Control Register (82801BAM ICH2-M)

I/O Address:

Default Value

Lockable:

PMBASE +50h

01h

Core

Attribute:

Size:

Usage:

R/W (special)

8-bit

ACPI/Legacy

Power Well:

Writes to this register initiates an Intel^®SpeedStep^™transition, which involves a temporary

transition to a C3-like state in which the STPCLK# signal will go active. An Intel^®SpeedStep^™

transition always occur on writes to the SS_CNT register, even if the value written to SS_STATE

is the same as the previous value (after this “transition” the system would still be in the same

Intel^®SpeedStep^™state).

Bit

Description

7:1

Reserved

SpeedStep State (SS_STATE)— R/W (Special). When this bit is read, it will return the current

SpeedStep state. Writes to this register will cause a change to the SpeedStep state indicated

by the value written to this bit.

™

0 = High-power state.

1 = Low-power state.

9-78

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.9

System Management TCO Registers (D31:F0)

The TCO logic is accessed via registers mapped to the PCI configuration space

(Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers, see LPC

Device 31:Function 0 PCI Configuration registers.

9.9.1

TCO Register I/O Map

The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which is,

ACPIBASE + 60h in the PCI configuration space. The following table shows the mapping of the

registers within that 32-byte range. Each register is described in the sections below.

Table 9-11. TCO I/O Register Map

Offset

00h

Mnemonic

TCO_RLD

Type

TCO Timer Reload and Current Value

TCO Timer Initial Value

TCO Data In

R/W

01h

02h

TCO_TMR

TCO_DAT_IN

TCO_DAT_OUT

TCO1_STS

TCO2_STS

TCO1_CNT

TCO2_CNT

03h

TCO Data Out

04h–05h

06h–07h

08h–09h

0Ah–0Bh

TCO Status

TCO Control

TCO_MESSAGE1,

TCO_MESSAGE2

0Ch–0Dh

Used by BIOS to indicate POST/Boot progress

R/W

0Eh

0Fh

TCO_WDSTATUS

Watchdog Status Register

Reserved

R/W

10h

SW_IRQ_GEN

Software IRQ Generation Register

Reserved

R/W

11h–1Fh

9.9.2

TCO1_RLD—TCO Timer Reload and Current Value Register

I/O Address:

Default Value:

Lockable:

TCOBASE +00h

0000h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

TCO Timer Value. Reading this register will return the current count of the TCO timer. Writing any

value to this register will reload the timer to prevent the time-out. Bits 7:6 will always be 0.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-79

LPC Interface Bridge Registers (D31:F0)

9.9.3

TCO1_TMR—TCO Timer Initial Value Register

I/O Address:

Default Value:

Lockable:

TCOBASE +01h

0004h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

7:6

5:0

Reserved

TCO Timer Initial Value. Value that is loaded into the timer each time the TCO_RLD register is

written. Values of 0h–3h will be ignored and should not be attempted. The timer is clocked at

approximately 0.6 seconds, and this allows time-outs ranging from 2.4 seconds to 38 seconds.

9.9.4

9.9.5

TCO1_DAT_IN—TCO Data In Register

I/O Address:

Default Value:

Lockable:

TCOBASE +02h

0000h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

TCO Data In Value. Data Register for passing commands from the OS to the SMI handler. Writes

to this register will cause an SMI and set the OS_TCO_SMI bit in the TCO_STS register.

7:0

TCO1_DAT_OUT—TCO Data Out Register

I/O Address:

Default Value:

Lockable:

TCOBASE +03h

0000h

Attribute:

Size:

Power Well:

R/W

8-bit

Core

Bit

Description

TCO Data Out Value. Data Register for passing commands from the SMI handler to the OS.

Writes to this register will set the TCO_INT_STS bit in the TCO_STS register. It will also cause an

interrupt, as selected by the TCO_INT_SEL bits.

7:0

9.9.6

TCO1_STS—TCO1 Status Register

I/O Address:

Default Value:

Lockable:

TCOBASE +04h

0000h

Attribute:

Size:

Power Well:

R/WC RO

16-bit

Core

(Except bit 7, in RTC)

Bit

Description

15:13

Reserved

Hub Interface SERR Status (HUBSERR_STS)—R/WC.

1 = ICH2 received an SERR# message via the hub interface. The software must read the memory

controller hub (or its equivalent) to determine the reason for the SERR#.

0 = Software clears this bit by writing a 1 to the bit position.

Hub Interface NMI Status (HUBNMI_STS)—R/WC.

1 = ICH2 received an NMI message via the hub interface. The software must read the memory

controller hub (or its equivalent) to determine the reason for the NMI.

0 = Software clears this bit by writing a 1 to the bit position.

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

Bit

Description

Hub Interface SMI Status (HUBSMI_STS)—R/WC.

1 = ICH2 received an SMI message via the hub interface. The software must read the memory

controller hub (or its equivalent) to determine the reason for the SMI#.

0 = Software clears this bit by writing a 1 to the bit position.

Hub Interface SCI Status (HUBSCI_STS)—R/WC.

1 = ICH2 received an SCI message via the hub interface. The software must read the memory

controller hub (or its equivalent) to determine the reason for the SCI.

0 = Software clears this bit by writing a 1 to the bit position.

BIOS Write Status (BIOSWR_STS)—R/WC.

1 = ICH2 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS.

This occurs when either:

a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or

b) any write is attempted to the BIOS and the BIOSWP bit is also set.

0 = Software clears this bit by writing a 1 to the bit position.

Note:On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS will

not be set.

New Century Status (NEWCENTURY_STS)—R/WC. This bit is in the RTC well.

1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.

Setting this bit will cause an SMI# (but not a wake event).

0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.

Note that the NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when

RTC power has not been maintained). Software can determine if RTC power has not been

maintained by checking the RTC_PWR_STS bit or by other means (e.g., a checksum on RTC

RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a

legal value and then clear the NEWCENTURY_STS bit.

The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a “1” is

written to the bit to clear it. After writing a “1” to this bit, software should not exit the SMI handler

until verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.

6:4

Reserved

Time Out Status (TIMEOUT)—R/WC.

1 = Set by ICH2 to indicate that the SMI was caused by the TCO timer reaching 0.

0 = Software clears this bit by writing a 1 to the bit position.

TCO Interrupt Status (TCO_INT_STS)—R/WC.

1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register.

0 = Software clears this bit by writing a 1 to the bit position.

Software TCO SMI Status (SW_TCO_SMI)—R/WC.

1 = Software caused an SMI# by writing to the TCO_DAT_IN register.

0 = Software clears this bit by writing a 1 to the bit position.

NMI to SMI Status (NMI2SMI_STS)—RO.

1 = Set by the ICH2 when an SMI# occurs because an event occurred that would otherwise have

caused an NMI (because NMI2SMI_EN is set).

0 = Cleared by clearing the associated NMI status bit.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-81

LPC Interface Bridge Registers (D31:F0)

9.9.7

TCO2_STS—TCO2 Status Register

I/O Address:

Default Value:

Lockable:

TCOBASE +06h

0000h

Attribute:

Size:

Power Well:

R/WC, RO

16-bit

Resume

(Except Bit 0, in RTC)

Bit

Description

15:3

Reserved

Boot Status (BOOT_STS):

1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the

first instruction.

0 = Cleared by ICH2 based on RSMRST# or by software writing a 1 to this bit. Note that software

should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit.

If rebooting due to a second TCO timer time-out and if the BOOT_STS bit is set, the ICH2 will reboot

using the ‘safe’ multiplier (1111). This allows the system to recover from a processor frequency

multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set and

the frequency multiplier is 1111, then the BIOS knows that the processor has been programmed to an

illegal multiplier.

Second TCO Time-out Status (SECOND_TO_STS)—R/WC.

1 = The ICH2 sets this bit to a 1 to indicate that the TCO timer timed out a second time (probably due

to system lock). If this bit is set the ICH2 will reboot the system after the second time-out. The

reboot is done by asserting PCIRST#.

0 = This bit is cleared by writing a 1 to the bit position or by a RSMRST#.

Intruder Detect (INTRD_DET)—R/WC.

1 = Set by ICH2 to indicate that an intrusion was detected. This bit is set even if the system is in G3

state.

0 = This bit is only cleared by writing a 1 to the bit position, or by RTCRST# assertion.

9-82

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.9.8

TCO1_CNT—TCO1 Control Register

I/O Address:

Default Value:

Lockable:

TCOBASE +08h

0000h

Attribute:

Size:

Power Well:

R/W, R/WC

16-bit

Core

Bit

Description

15:12

Reserved

TCO Timer Halt (TCO_TMR_HLT)—R/W.

0 = The TCO Timer is enabled to count.

1 = The TCO Timer will halt. It will not count and, thus, cannot reach a value that will cause an

SMI# or set the SECOND_TO_STS bit. When set, this bit prevents rebooting and prevents

Alert On LAN event messages from being transmitted on the SMLINK (but not Alert On LAN

heartbeat messages).

Send Now (SENDNOW)—R/W (special).

1 = Writing a 1 to this bit will cause the ICH to send an Alert On LAN Event message over the

SMLINK interface, with the Software Event bit set.

0 = The ICH will clear this bit when it has completed sending the message. Software must not set

this bit to 1 again until the ICH has set it back to 0.

Setting the SENDNOW bit causes the ICH2 integrated LAN Controller to reset, which can have

unpredictable side-effects. Unless software protects against these side effects, software should not

attempt to set this bit.

NMI to SMI Enable (NMI2SMI_EN)—R/W.

0 = Normal NMI functionality.

1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the

settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table:

NMI_EN GBL_SMI_EN

Description

No SMI# at all because GBL_SMI_EN = 0

SMI# will be caused due to NMI events

No SMI# at all because GBL_SMI_EN = 0

No SMI# due to NMI because NMI_EN = 1

NMI Now (NMI_NOW)—R/WC.

1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to

the NMI handler.

0 = This bit is cleared by writing a 1 to the bit position. The NMI handler is expected to clear this bit.

Another NMI will not be generated until the bit is cleared.

7:0

Reserved

9.9.9

TCO2_CNT—TCO2 Control Register

I/O Address:

Default Value:

Lockable:

TCOBASE +0Ah

0000h

Attribute:

Size:

Power Well:

R/W

16-bit

Resume

Bit

Description

15:3 Reserved.

INTRUDER# Signal Select (INTRD_SEL)—R/W. Selects the action to take if the INTRUDER# signal

goes active.

00 = No interrupt or SMI#

01 = Interrupt (as selected by TCO_INT_SEL).

10 = SMI

2:1

11 = Reserved

Reserved.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-83

LPC Interface Bridge Registers (D31:F0)

9.9.10

9.9.11

9.9.12

TCO_MESSAGE1 and TCO_MESSAGE2 Registers

I/O Address:

TCOBASE +0Ch (Message 1) Attribute:

TCOBASE +0Dh (Message 2)

R/W

Default Value:

Lockable:

00h

Size:

Power Well:

8-bit

Resume

Bit

Description

TCO Message (TCO_MESSAGE[n])—R/W.The value written into this register will be sent out via

the SMLINK interface in the MESSAGE field of the Alert On LAN message. BIOS can write to this

7:0

TCO_WDSTATUS—TCO2 Control Register

Offset Address:

Default Value:

Power Well:

TCOBASE + 0Eh

00h

Resume

Attribute:

Size:

R/W

8 bits

Bit

Description

Watchdog Status (WDSTATUS)—R/W. The value written to this register will be sent in the Alert On

LAN message on the SMLINK interface. It can be used by the BIOS or system management

software to indicate more details on the boot progress. This register will be reset to the default of

00h based on RSMRST# (but not PCI reset).

7:0

SW_IRQ_GEN—Software IRQ Generation Register

Offset Address:

Default Value:

Power Well:

TCOBASE + 10h

03h

Resume

Attribute:

Size:

R/W

8 bits

Bit

Description

7:2

Reserved.

IRQ12 Cause (IRQ12_CAUSE)—R/W. The state of this bit is logically ANDed with the IRQ12 signal

as received by the ICH2’s SERIRQ logic. This bit must be a “1” (default) if the ICH2 is expected to

receive IRQ12 assertions from a SERIRQ device.

IRQ1 Cause (IRQ1_CAUSE)—R/W. The state of this bit is logically ANDed with the IRQ1 signal as

received by the ICH2’s SERIRQ logic. This bit must be a “1” (default) if the ICH2 is expected to

receive IRQ1 assertions from a SERIRQ device.

9-84

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.10

General Purpose I/O Registers (D31:F0)

The control for the general purpose I/O signals is handled through a separate 64-byte I/O space.

The base offset for this space is selected by the GPIO_BAR register. Table 9-12 summarizes the

ICH2 GPIO implementation.

Table 9-12. Summary of GPIO Implementation

Alternate

Function

(Note 1)

Power

Well

GPIO

Type

Notes

GPIO_USE_SEL bit 0 enables REQ/GNT[A]# pair.

Input active status read from GPE1_STS register bit 0.

Input active high/low set through GPI_INV register bit 0.

Input

Only

GPIO[0]

REQ[A]#

Core

GPIO_USE_SEL bit 1 enables REQ/GNT[B]# pair

(See note 4).

Input active status read from GPE1_STS register bit 1.

Input active high/low set through GPI_INV register bit 1.

Input

Only

REQ[B]# or

REQ[5]#

GPIO[1]

GPIO[2]

GPIO[3:4]

GPIO[5]

N/A

PIRQ[E:H]#

N/A

Core

N/A

Not implemented

GPIO_USE_SEL bits [3:4] enable PIRQ[F:G]#.

Input active status read from GPE1_STS reg. bits [3:4].

Input active high/low set through GPI_INV reg. bit [3:4].

Input

Only

N/A

Not implemented

ICH2 (82801BA):

Input active status read from GPE1_STS register bit 6.

Input active high/low set through GPI_INV register bit 6.

Input

Only

GPIO[6]

Unmuxed

Core

ICH2-M (82801BAM):

Not implemented.

Input

Only

Input active status read from GPE1_STS register bit 7.

Input active high/low set through GPI_INV register bit 7

GPIO[7]

Unmuxed

Core

Input

Only

Input active status read from GPE1_STS register bit 8.

Input active high/low set through GPI_INV register bit 8.

GPIO[8]

Unmuxed

N/A

Resume

N/A

GPIO[9:10]

N/A

Not implemented

GPIO_USE_SEL bit 11 enables SMBALERT#

SMBALERT# Resume Input active status read from GPE1_STS register bit 11.

Input active high/low set through GPI_INV register bit 11.

Input

Only

GPIO[11]

GPIO[12]

Input

Only

Input active status read from GPE1_STS register bit 12.

Input active high/low set through GPI_INV register bit 12.

Unmuxed

Resume

Input

Only

Input active status read from GPE1_STS register bit 13.

Input active high/low set through GPI_INV register bit 13.

GPIO[13]

GPIO[14:15]

GPIO[16]

Unmuxed

N/A

Resume

N/A

Not Implemented

Output

Only

Output controlled via GP_LVL register bit 16.

TTL driver output

GNT[A]#

Core

Output

Only

GNT[B]# or

GNT[5]#

Output controlled via GP_LVL register bit 17.

TTL driver output

GPIO[17]

Core

ICH2 (82801BA):

Output controlled via GP_LVL register bits [18:19].

TTL driver output

Output

Only

GPIO[18:19]

Unmuxed

Core

ICH2-M (82801BAM):

Not implemented.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-85

LPC Interface Bridge Registers (D31:F0)

Table 9-12. Summary of GPIO Implementation (Continued)

Alternate

Power

GPIO

Type

Function

(Note 1)

Notes

Well

ICH2 (82801BA):

Output controlled via GP_LVL register bit 20.

TTL driver output

Output

Only

GPIO[20]

Unmuxed

Core

ICH2-M (82801BAM):

Not implemented.

ICH2 (82801BA):

Unmuxed for

ICH2

82801BA

This GPO defaults high.

Output controlled via GP_LVL register bit 21.

TTL driver output

Output

Only

GPIO[21]

Core

CS_STAT#

for ICH2-M

82801BAM

ICH2-M (82801BAM):

Output controlled via GP_LVL register bit 21.

TTL driver output

ICH2 (82801BA):

Output controlled via GP_LVL register bit [22].

Open-drain output

Output

Only

GPIO[22]

GPIO[23]

Unmuxed

Core

ICH2-M (82801BAM):

Not implemented.

ICH2 (82801BA):

Output controlled via GP_LVL register bit [23].

TTL driver output

Output

Only

ICH2-M (82801BAM):

Not implemented.

ICH2 (82801BA):

Input active status read from GP_LVL register bit 24.

Output controlled via GP_LVL register bit 24.

TTL driver output

Input /

Output

GPIO[24]

GPIO[25]

Unmuxed

Resume

ICH2-M (82801BAM):

Not implemented.

Blink enabled via GPO_BLINK register bit 25.

Input active status read from GP_LVL register bit 25

Output controlled via GP_LVL register bit 25.

TTL driver output

Input /

Output

Resume

N/A

GPIO[26]

N/A

Unmuxed

N/A

Not implemented

Input active status read from GP_LVL register bits [27:28]

Resume Output controlled via GP_LVL register bits [27:28]

TTL driver output

Input /

Output

GPIO[27:28]

GPIO[29:31]

N/A

Not implemented

NOTES:

1. All GPIOs default to their alternate function

2. All inputs are sticky. The status bit will remain set as long as the input was asserted for 2 clocks. GPIs are

sampled on PCI clocks in S0/S1...

3. GPIs are sampled on RTC clocks in S3/S4/S5 for the 82801BA ICH2 and in S1/S3/S4/S5 for the 82801BAM

ICH2-M.

4. GPIO[7:6,4:3,1:0] (GPIO[7,4:3,1:0] for the ICH2-M) are 5V tolerant, and all GPIs can be routed to cause an

SCI or SMI#

5. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT[5]# is enabled. See

Section 9.1.22.

9-86

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.10.1

GPIO Register I/O Address Map

Table 9-13. Registers to Control GPIO

Offset

Mnemonic

General Registers

GPIO_USE_SEL GPIO Use Select

Default

Access

00–03h

04–07h

08–0Bh

0C–0Fh

10–13h

1A00 3180h

0000 FFFFh

00h

R/W

GP_IO_SEL

GPIO Input/Output Select

Reserved

—

GP_LVL

—

GPIO Level for Input or Output

Reserved

1F1F 0000h

00h

R/W

Output Control Registers

14–17h

18–1Bh

1C–1Fh

GPO_TTL

GPO_BLINK

—

GPIO TTL Select

GPIO Blink Enable

Reserved

06630000h

00000000h

R/W

Input Control Registers

20–2Bh

2C–2Fh

—

Reserved

00000000h

GPI_INV

GPIO Signal Invert

R/W

9.10.2

GPIO_USE_SEL—GPIO Use Select Register

Offset Address:

Default Value:

Lockable:

GPIOBASE + 00h

1A003180h

Yes

Attribute:

Size:

Power Well:

R/W

32-bit

Resume

Bit

Description

GPIO Use Select (GPIO_USE_SEL)—R/W. Each bit in this register enables the corresponding

GPIO (if it exists) to be used as a GPIO, rather than for the native function.

0 = Signal used as native function.

1 = Signal used as a GPIO.

Note: ICH2 82801BA: Bits 31:29, 26, 15:14, 10:9 and 7 are not implemented because there is no

corresponding GPIO.

21,11,

5:0

ICH2-M 82801BAM: Bits 31:29, 26, 24:22, 20:18, 15:14, 10:9, and 7:6 are not implemented

because there is no corresponding GPIO.

Note: ICH2 82801BA: Bits 28:27, 25:22, 20:18,13:12, 8 and 6 are not implemented because the

corresponding GPIOs are not multiplexed.

ICH2-M 82801BAM: Bits 28:27, 25, 13:12 and 8 are not implemented because the

corresponding GPIOs are not mutiplexed.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-87

LPC Interface Bridge Registers (D31:F0)

9.10.3

GP_IO_SEL—GPIO Input/Output Select Register

Offset Address:

Default Value:

Lockable:

GPIOBASE +04h

0000FFFFh

Attribute:

Size:

Power Well:

R/W

32-bit

Resume

Bit

Description

31:29, 26 15:14,

10:9, 5, 2

Reserved.

GPIO[n] Select (GPIO[n]_SEL)—R/W.

28:27,25:24 (ICH2)

28:27,25 (ICH2-M)

0 = Output. The corresponding GPIO signal is an output.

1 = Input. The corresponding GPIO signal is an input.

24:22, 20:18, 6

(ICH2-M)

Reserved

23:16 (ICH2)

Always 0. The GPIOs are fixed as outputs.

21:16 (ICH2-M)

13:11, 8:6, 4:3, 1:0

(ICH2)

Always 1. These GPIOs are fixed as inputs.

13:11, 8:7, 4:3, 1:0

(ICH2-M)

NOTES:

1. There will be some delay on GPIO[24:28] going to their default state based on the rising edge of

RSMRST#. This is the case since these signals are in the resume well and resume well outputs

are not valid until after RSMRST# goes high. ICH2 only guarantees that these GPIOs will be

stable prior to SLP_S3# going active.

9-88

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.10.4

GP_LVL—GPIO Level for Input or Output Register

Offset Address:

Default Value:

Lockable:

GPIOBASE +0Ch

1B3F 0000h

Attribute:

Size:

Power Well:

R/W, RO

32-bit

See bit descriptions

Bit

Description

31:29, 26, 15:14,

10:9, 5, 2

(ICH2)

Reserved.

31:29, 26, 24:22,

20:18, 15:14, 10:9 6,

5, 2

(ICH2-M)

GPIO Level (GP_LVL[n])—R/W. If GPIO[n] is programmed to be an output (via the

corresponding bit in the GP_IO_SEL register), then the bit can be updated by software

to drive a high or low value on the output pin. If GPIO[n] is programmed as an input,

then software can read the bit to determine the level on the corresponding input pin.

These bits correspond to GPIO that are in the Resume well, and will be reset to their

default values by RSMRST# but not by PCIRST#.

28:27, 25:24

(ICH2)

28:27, 25

(ICH2-M)

0 = Low

1 = High

GPIO Level (GP_LVL[n])—R/W. These bits can be updated by software to drive a

high or low value on the output pin. These bits correspond to GPIO that are in the

Core well, and will be reset to their default values by PCIRST#.

23:16

(ICH2)

21, 17:16

(ICH2-M)

0 = Low

1 = High

ICH2 82801BA:

For GPI[13:11] and [8:6,4:3,1:0], the active status of a GPI is read from the

corresponding bit in GPE1_STS register.

13:11, 8:6, 4:3, 1:0

(ICH2)

ICH2-M 82801BAM:

13:11, 8:7, 4:3, 1:0

(ICH2-M)

For GPI[13:11] and [8:7,4:3,1:0], the active status of a GPI is read from the

corresponding bit in GPE1_STS register.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-89

LPC Interface Bridge Registers (D31:F0)

9.10.5

GPO_BLINK—GPO Blink Enable Register

Offset Address:

Default Value:

Lockable:

GPIOBASE +18h

0004 0000h

Attribute:

Size:

Power Well:

R/W

32-bit

See bit description

Bit

Description

31:29, 26, 24:20,

17:0

(ICH2)

Reserved

31:29, 26, 24:20,

18:0

(ICH2-M)

GPIO Blink (GP_BLINK[n])—R/W. The setting of these bits will have no effect if the

corresponding GPIO is programmed as an input. These bits correspond to GPIO that

are in the Resume well and will be reset to their default values by RSMRST# but not by

PCIRST#.

28:27, 25

0 = The corresponding GPIO will function normally.

1 = If the corresponding GPIO is programmed as an output, the output signal will blink

at a rate of approximately once per second. The high and low times have

approximately 50% duty cycle. The GP_LVL bit is not altered when this bit is set.

GPIO Blink (GP_BLINK[n])—R/W. The setting of these bits will have no effect if the

corresponding GPIO is programmed as an input. These bits correspond to GPIO that

are in the Core well, and will be reset to their default values by PCIRST#.

19:18 (ICH2)

19 (ICH2-M)

0 = The corresponding GPIO will function normally.

1 = If the corresponding GPIO is programmed as an output, the output signal will blink

at a rate of approximately once per second. The high and low times have

approximately 50% duty cycle. The GP_LVL bit is not altered when this bit is set.

NOTES:.

1. ICH2 82801BA: GPIO[18] blinks, by default, immediately after reset. This signal could be

connected to an LED to indicate a failed boot (by programming BIOS to clear GP_BLINK[18]

after successful POST).

9-90

82801BA ICH2 and 82801BAM ICH2-M Datasheet

LPC Interface Bridge Registers (D31:F0)

9.10.6

GPI_INV—GPIO Signal Invert Register

Offset Address:

Default Value:

Lockable:

GPIOBASE +2Ch

00000000h

Attribute:

Size:

Power Well:

R/W

32-bit

See bit description

Bit

Description

31:14, 10:9,

5, 2

(ICH2)

Reserved

31:14, 10:9, 6,

5, 2

(ICH2-M)

GPIO Signal High/Low Select (GP_INV[n])—R/W. These bits are used to allow both active-

low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input

signal must be active for at least 2 PCI clocks to ensure detection by the ICH2. In the S3, S4

or S5 states the input signal must be active for at least 2 RTC clocks to ensure detection. The

setting of these bits will have no effect if the corresponding GPIO is programmed as an

output. These bits correspond to GPIO that are in the Resume well, and will be reset to their

default values by RSMRST# but not by PCIRST#.

13:11, 8

0 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input

pin to be high.

1 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input

pin to be low.

GPIO Signal High/Low Select (GP_INV[n])—R/W. These bits are used to allow both active-

low and active-high inputs to cause SMI# or SCI. Note that in the S0 or S1 state, the input

signal must be active for at least 2 PCI clocks to ensure detection by the ICH2. The setting of

these bits will have no effect if the corresponding GPIO is programmed as an output. These

bits correspond to GPIO that are in the Core well, and will be reset to their default values by

PCIRST#.

7:6, 4:3, 1:0

(ICH2)

7, 4:3, 1:0

(ICH2-M)

0 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input

pin to be high.

1 = The corresponding GPI_STS bit will be set when the ICH2 detects the state of the input

pin to be low.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

9-91

LPC Interface Bridge Registers (D31:F0)

This page is intentionally left blank

9-92

82801BA ICH2 and 82801BAM ICH2-M Datasheet

IDE Controller Registers (D31:F1)

IDE Controller Registers (D31:F1) 10

10.1

PCI Configuration Registers (IDE—D31:F1)

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

All of the IDE registers are in the Core well. None can be locked.

Table 10-1. PCI Configuration Map (IDE—D31:F1)

Offset

Mnemonic

Vendor ID

Default

Type

00h–01h

VID

8086h

244Bh (ICH2)

02h–03h

DID

Device ID

244Ah (ICH2-M)

04h–05h

06h–07h

08h

CMD

STS

RID

Command Register

Device Status

00h

0280h

See Note 1

80h

R/W

Revision ID

09h

Programming Interface

Sub Class Code

Base Class Code

Master Latency Timer

Header Type

0Ah

SCC

BCC

MLT

HTYPE

BAR

01h

0Bh

01h

0Dh

0Eh

00h

20h–23h

Base Address Register

00000001h

R/W

R/Write-

Once

2C–2Dh

2E–2Fh

SVID

SID

Subsystem Vendor ID

Subsystem ID

R/Write-

Once

40h–41h

42–43h

44h

IDE_TIMP

ID_TIMS

Primary IDE Timing

0000h

00h

R/W

Secondary IDE Timing

SIDETIM

Slave IDE Timing

48h

SDMAC

Synchronous DMA Control Register

Synchronous DMA Timing Register

IDE I/O Configuration Register

00h

4Ah–4Bh

54h

SDMATIM

IDE_CONFIG

0000h

00h

NOTES:

1. Refer to the Specification Update for the value of the Revision ID Register

2. The ICH2 IDE controller is not arbitrated as a PCI device; therefore, it doe s not need a master latency timer.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

10-1

IDE Controller Registers (D31:F1)

10.1.1

10.1.2

VID—Vendor ID Register (IDE—D31:F1)

Offset Address:

Default Value:

Lockable:

00–01h

8086h

Attribute:

Size:

Power Well:

16-bit

Core

Bit

Description

15:0

Vendor ID Value. This is a 16 bit value assigned to Intel. Intel VID = 8086h

DID—Device ID Register (IDE—D31:F1)

Offset Address:

Lockable:

02–03h

Attribute:

Size:

Power Well:

16-bit

Core

Default Value:

244Bh (82801BA ICH2)

244Ah (82801BAM ICH2-M)

Bit

Description

15:0

Device ID Value. This is a 16 bit value assigned to the ICH2 IDE controller.

10.1.3

CMD—Command Register (IDE—D31:F1)

Address Offset:

Default Value:

04h–05h

00h

Attribute:

Size:

RO, R/W

16 bits

Bit

Description

15:10

Reserved.

Fast Back to Back Enable (FBE)—RO. Reserved as 0.

SERR# Enable—RO. Reserved as 0.

Wait Cycle Control—RO. Reserved as 0.

Parity Error Response—RO. Reserved as 0.

VGA Palette Snoop—RO. Reserved as 0.

Postable Memory Write Enable (PMWE)—RO. Reserved as 0.

Special Cycle Enable (SCE)—RO. Reserved as 0.

Bus Master Enable (BME)—R/W. Controls the ICH2’s ability to act as a PCI master for IDE Bus

Master transfers.

Memory Space Enable (MSE)—RO. Reserved as 0.

I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers.

0 = Disables access to the Legacy IDE ports (both Primary and Secondary) as well as the Bus

Master IO registers.

1 = Enable. Note that the Base Address register for the Bus Master registers should be

programmed before this bit is set.

Note: Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently

disable the Primary or Secondary I/O spaces.

10-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

IDE Controller Registers (D31:F1)

10.1.4

STS—Device Status Register (IDE—D31:F1)

Address Offset:

Default Value:

06–07h

0280h

Attribute:

Size:

R/WC, RO

16 bits

Bit

Description

Detected Parity Error (DPE)—RO. Reserved as 0.

Signaled System Error (SSE)—RO. Reserved as 0.

Received Master-Abort Status (RMA)—R/WC.

1 = Bus Master IDE interface function, as a master, generated a master abort.

0 = Cleared by writing a 1 to it.

Reserved as 0—RO.

Signaled Target-Abort Status (STA)—R/WC.

1 = ICH2 IDE interface function is targeted with a transaction that the ICH2 terminates with a target

abort.

0 = Cleared by writing a 1 to it.

DEVSEL# Timing Status (DEVT)—RO.

10:9

01 = Hardwired; however, the ICH2 does not have a real DEVSEL# signal associated with the IDE

unit, so these bits have no effect.

Data Parity Error Detected—RO. Reserved as 0.

Fast Back-to-Back Capable—RO. Reserved as 1.

User Definable Features (UDF)—RO. Reserved as 0.

66 MHz Capable—RO. Reserved as 0.

Reserved

4:0

10.1.5

10.1.6

RID—Revision ID Register (HUB-PCI—D30:F0)

Offset Address:

Default Value:

08h

Attribute:

Size:

8 bits

See bit description

Bit

Description

Revision Identification Number—RO. This 8-bit value indicates the revision number for the ICH2

IDE controller. Refer to the Specification Update for the value of the Revision ID Register.

7:0

PI—Programming Interface (IDE—D31:F1)

Address Offset:

Default Value:

09h

80h

Attribute:

Size:

8 bits

Bit

Description

Programming Interface Value—RO.

80h = The 1b in bit 7 indicates that this IDE controller is capable of bus master operation.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

10-3

IDE Controller Registers (D31:F1)

10.1.7

10.1.8

10.1.9

SCC—Sub Class Code (IDE—D31:F1)

Address Offset:

Default Value:

0Ah

01h

Attribute:

Size:

8 bits

Bit

Description

Sub Class Code—RO.

01h = IDE device, in the context of a mass storage device.

7:0

BCC—Base Class Code (IDE—D31:F1)

Address Offset:

Default Value:

0Bh

01h

Attribute:

Size:

8 bits

Bit

Description

Base Class Code—RO.

7:0

01 = Mass storage device

MLT—Master Latency Timer (IDE—D31:F1)

Address Offset:

Default Value:

0Dh

00h

Attribute:

Size:

8 bits

Bit

Description

Bus Master Latency—RO. The IDE controller is implemented internally, and is not arbitrated as a

PCI device, so it does not need a Master Latency Timer.

7:0

Hardwired to 00h.

10.1.10 BM_BASE—Bus Master Base Address Register

(IDE—D31:F1)

Address Offset:

Default Value:

20h–23h

00000001h

Attribute:

Size:

R/W

32 bits

The Bus Master IDE interface function uses Base Address register 5 to request a 16 byte IO space

to provide a software interface to the Bus Master functions. Only 12 bytes are actually used

(6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address.

Bit

Description

31:16

15:4

3:1

Reserved.

Base Address—R/W. Base address of the I/O space (16 consecutive I/O locations).

Reserved.

Resource Type Indicator (RTE)—RO. Hardwired to 1, indicating a request for IO space.

10-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

IDE Controller Registers (D31:F1)

10.1.11 IDE_SVID—Subsystem Vendor ID (IDE—D31:F1)

Address Offset:

Default Value:

Lockable:

2Ch–2Dh

00h

Attribute:

Size:

Power Well:

R/Write-Once

16 bits

Core

Bit

Description

Subsystem Vendor ID (SVID)—R/Write-Once. The SVID register, in combination with the

Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from

each other. Software (BIOS) sets the value in this register. After that, the value can be read, but

subsequent writes to this register have no effect. The value written to this register will also be

readable via the corresponding SVID registers for the USB#1, USB#2 and SMBus functions.

15:0

10.1.12 IDE_SID—Subsystem ID (IDE—D31:F1)

Address Offset:

Default Value:

Lockable:

2Eh–2Fh

00h

Attribute:

Size:

Power Well:

R/Write-Once

16 bits

Core

Bit

Description

Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register,

enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS)

sets the value in this register. After that, the value can be read, but subsequent writes to this register

have no effect. The value written to this register will also be readable via the corresponding SID

registers for the USB#1, USB#2 and SMBus functions.

15:0

10.1.13 IDE_TIM—IDE Timing Register (IDE—D31:F1)

Address Offset:

Default Value:

Primary:

Secondary: 42–43h

0000h

40–41h

Attribute:

Size:

R/W

16 bits

This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It

also controls operation of the buffer for PIO transfers.

Bit

Description

IDE Decode Enable (IDE)—R/W. Individually enable/disable the Primary or Secondary decode.

The IDE I/O Space Enable bit in the Command register must be set in order for this bit to have any

effect. Additionally, separate configuration bits are provided (in the IDE I/O Configuration register)

to individually disable the primary or secondary IDE interface signals, even if the IDE Decode

Enable bit is set.

0 = Disable.

1 = Enables the ICH2 to decode the associated Command Blocks (1F0h–1F7h for primary,

170h–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).

Drive 1 Timing Register Enable (SITRE)—R/W.

0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.

1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1

IORDY Sample Point (ISP). The setting of these bits determine the number of PCI clocks between

IDE IOR#/IOW# assertion and the first IORDY sample point.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

13:12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

10-5

IDE Controller Registers (D31:F1)

Bit

Description

11:10

Reserved.

Recovery Time (RCT)—R/W. The setting of these bits determines the minimum number of PCI

clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clock

9:8

Drive 1 DMA Timing Enable (DTE1)—R/W.

0 = Disable.

1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data

port will run in compatible timing.

Drive 1 Prefetch/Posting Enable (PPE1)—R/W.

0 = Disable.

1 = Enable Prefetch and posting to the IDE data port for this drive.

Drive 1 IORDY Sample Point Enable (IE1)—R/W.

0 = Disable IORDY sampling for this drive.

1 = Enable IORDY sampling for this drive.

Drive 1 Fast Timing Bank (TIME1)—R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = When this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the IORDY

sample point, and bits 9:8 for the recovery time. When this bit = 1 and bit 14 = 1, accesses to

the data port will use the IORDY sample point and recover time specified in the slave IDE

timing register.

Drive 0 DMA Timing Enable (DTE0)—R/W.

0 = Disable.

1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data

port will run in compatible timing.

Drive 0 Prefetch/Posting Enable (PPE0)—R/W.

0 = Disable prefetch and posting to the IDE data port for this drive.

1 = Enable prefetch and posting to the IDE data port for this drive.

Drive 0 IORDY Sample Point Enable (IE0)—R/W.

0 = Disable IORDY sampling is disabled for this drive.

1 = Enable IORDY sampling for this drive.

Drive 0 Fast Timing Bank (TIME0)—R/W.

0 = Accesses to the data port will use compatible timings for this drive.

1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the

recovery time

10-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

IDE Controller Registers (D31:F1)

10.1.14 SLV_IDETIM—Slave (Drive 1) IDE Timing Register

(IDE—D31:F1)

Address Offset:

Default Value:

44h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Secondary Drive 1 IORDY Sample Point (SISP1)—R/W. Determines the number of PCI clocks

between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data

port and bit 14 of the IDE timing register for secondary is set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

7:6

5:4

3:2

1:0

Secondary Drive 1 Recovery Time (SRCT1)—R/W. Determines the minimum number of PCI clocks

between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to

drive 1 data port and bit 14 of the IDE timing register for secondary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

Primary Drive 1 IORDY Sample Point (PISP1)—R/W. Determines the number of PCI clocks

between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port

and bit 14 of the IDE timing register for primary is set.

00 = 5 clocks

01 = 4 clocks

10 = 3 clocks

11 = Reserved

Primary Drive 1 Recovery Time (PRCT1)—R/W. Determines the minimum number of PCI clocks

between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to

drive 1 data port and bit 14 of the IDE timing register for primary is set.

00 = 4 clocks

01 = 3 clocks

10 = 2 clocks

11 = 1 clocks

82801BA ICH2 and 82801BAM ICH2-M Datasheet

10-7

IDE Controller Registers (D31:F1)

10.1.15 SDMA_CNT—Synchronous DMA Control Register

(IDE—D31:F1)

Address Offset:

Default Value:

48h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

7:4

Reserved.

Secondary Drive 1 Synchronous DMA Mode Enable (SSDE1)—R/W.

0 = Disable (default).

1 = Enable Synchronous DMA mode for secondary channel drive 1

Secondary Drive 0 Synchronous DMA Mode Enable (SSDE0)—R/W.

0 = Disable (default).

1 = Enable Synchronous DMA mode for secondary drive 0.

Primary Drive 1 Synchronous DMA Mode Enable (PSDE1)—R/W.

0 = Disable (default).

1 = Enable Synchronous DMA mode for primary channel drive 1

Primary Drive 0 Synchronous DMA Mode Enable (PSDE0)—R/W.

0 = Disable (default).

1 = Enable Synchronous DMA mode for primary channel drive 0

10.1.16 SDMA_TIM—Synchronous DMA Timing Register

(IDE—D31:F1)

Address Offset:

Default Value:

4A–4Bh

0000h

Attribute:

Size:

R/W

16 bits

Bit

Description

15:14

13:12

11:10

9:8

Reserved.

Secondary Drive 1 Cycle Time (SCT1)—R/W. For Ultra ATA mode, the setting of these bits

determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also

determined by the setting of these bits.

SCB1 = 0 (33 MHz clk)

00 = CT 4 clocks, RP 6 clocks

01 = CT 3 clocks, RP 5 clocks

10 = CT 2 clocks, RP 4 clocks

11 = Reserved

SCB1 = 1 (66 MHz clk)

FAST_SCB1 = 1 (133 MHz clk)

00 = Reserved

01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks

10 = CT 2 clocks, RP 8 clocks 10 = Reserved

11 = Reserved

Reserved.

Secondary Drive 0 Cycle Time (SCT0)—R/W. For Ultra ATA mode, the setting of these bits

determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also

determined by the setting of these bits.

SCB1 = 0 (33 MHz clk)

00 = CT 4 clocks, RP 6 clocks

01 = CT 3 clocks, RP 5 clocks

10 = CT 2 clocks, RP 4 clocks

11 = Reserved

SCB1 = 1 (66 MHz clk)

FAST_SCB1 = 1 (133 MHz clk)

00 = Reserved

01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks

10 = CT 2 clocks, RP 8 clocks 10 = Reserved

11 = Reserved

7:6

Reserved.

10-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

IDE Controller Registers (D31:F1)

Bit

Description

Primary Drive 1 Cycle Time (PCT1)—R/W. For Ultra ATA mode, the setting of these bits

determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also

determined by the setting of these bits.

PCB1 = 0 (33 MHz clk)

PCB1 = 1 (66 MHz clk)

FAST_PCB1 = 1 (133 MHz clk)

5:4

3:2

1:0

00 = CT 4 clocks, RP 6 clocks 00 = Reserved

00 = Reserved

01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks

10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved

11 = Reserved

Reserved.

11 = Reserved

Primary Drive 0 Cycle Time (PCT0)—R/W. For Ultra ATA mode, the setting of these bits

determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also

determined by the setting of these bits.

PCB1 = 0 (33 MHz clk)

PCB1 = 1 (66 MHz clk)

FAST_PCB1 = 1 (133 MHz clk)

00 = CT 4 clocks, RP 6 clocks 00 = Reserved

00 = Reserved

01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks

10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved

11 = Reserved

10.1.17 IDE_CONFIG—IDE I/O Configuration Register

Address Offset:

Default Value:

54h

00h

Attribute:

Size:

R/W

32 bits

Bit

Description

31:20

19:18

Reserved.

Secondary IDE Signal Mode (SEC_SIG_MODE)—R/W.

00 = Normal (Enabled).

01 = Tri-state (Disabled).

10 = Drive low (Disabled).

11 = Reserved.

ICH2 (82801BA):

These bits are used to control mode of the Secondary IDE signal pins. These bits should always be

set to 00b for desktop implementations.

ICH2-M (82801BAM):

These bits are used to control mode of the Secondary IDE signal pins for mobile swap bay support.

Primary IDE Signal Mode (PRIM_SIG_MODE)—R/W.

00 = Normal (Enabled).

01 = Tri-state (Disabled).

10 = Drive low (Disabled).

11 = Reserved.

17:16

ICH2 (82801BA):

These bits are used to control mode of the Primary IDE signal pins. These bits should always be

set to 00b for desktop implementations.

ICH2-M (82801BAM):

These bits are used to control mode of the Secondary IDE signal pins for mobile swap bay support.

Fast Secondary Drive 1 Base Clock (FAST_SCB1)—R/W. This bit is used in conjuction with the

SCT1 bits to enable/disable Ultra ATA/100 timings for the Secondary Slave drive.

0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.

1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this register).

82801BA ICH2 and 82801BAM ICH2-M Datasheet

10-9

IDE Controller Registers (D31:F1)

Bit

Description

Fast Secondary Drive 0 Base Clock (FAST_SCB0)—R/W. This bit is used in conjuction with the

SCT0 bits to enable/disable Ultra ATA/100 timings for the Secondary Master drive.

0 = Disable Ultra ATA/100 timing for the Secondary Master drive.

1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this register).

Fast Primary Drive 1 Base Clock (FAST_PCB1)—R/W. This bit is used in conjuction with the

PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive.

0 = Disable Ultra ATA/100 timing for the Primary Slave drive.

1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).

Fast Primary Drive 0 Base Clock (FAST_PCB0)—R/W. This bit is used in conjuction with the

PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive.

0 = Disable Ultra ATA/100 timing for the Primary Master drive.

1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).

Reserved.

Write Buffer PingPong Enable (WR_PingPong_EN)—R/W.

0 = Disabled. The buffer will behave similar to PIIX4.

1 = Enables the write buffer to be used in a split (ping/pong) manner.

9:8

Reserved.

Secondary Slave Channel Cable Reporting—R/W. BIOS should program this bit to tell the IDE

driver which cable is plugged into the channel.

0 = 40 conductor cable is present.

1 = 80 conductor cable is present.

Secondary Master Channel Cable Reporting—R/W. Same description as bit 7

Primary Slave Channel Cable Reporting—R/W. Same description as bit 7

Primary Master Channel Cable Reporting—R/W. Same description as bit 7

Secondary Drive 1 Base Clock (SCB1)—R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

Secondary Drive 0 Base Clock (SCBO)—R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

Primary Drive 1 Base Clock (PCB1)—R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

Primary Drive 0 Base Clock (PCB0)—R/W.

0 = 33 MHz base clock for Ultra ATA timings.

1 = 66 MHz base clock for Ultra ATA timings

10-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

IDE Controller Registers (D31:F1)

10.2

Bus Master IDE I/O Registers (D31:F1)

The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located

in Device 31:Function 1 Configuration space (offset 20h). All bus master IDE I/O space registers

can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an

indeterminate, inconsistent value; writes to reserved bits have no affect (but should not be

attempted). The description of the I/O registers is shown in Table 10-2.

Table 10-2. Bus Master IDE I/O Registers

Offset

Mnemonic

Command Register Primary

Default

Type

00h

01h

BMICP

00h

R/W

Reserved

02h

BMISP

Status Register Primary

Reserved

00h

R/WC

03h

00h

04h–07h

08h

BMIDP

BMICS

Descriptor Table Pointer Primary

Command Register Secondary

Reserved

xxxxxxxxh

00h

R/W

09h

00h

0Ah

BMISS

BMIDS

Status Register Secondary

Reserved

00h

R/WC

0Bh

00h

0Ch–0Fh

Descriptor Table Pointer Secondary

xxxxxxxxh

R/W

10.2.1

BMIC[P,S]—Bus Master IDE Command Register

Address Offset:

Default Value:

Primary: 00h

Secondary: 08h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

7:4

Reserved. Returns 0s.

Read / Write Control (RWC)—R/W. This bit sets the direction of the bus master transfer: This bit

must NOT be changed when the bus master function is active.

0 = Memory reads.

1 = Memory writes

2:1

Reserved. Returns 0s.

Start/Stop Bus Master (START)—R/W.

1 = Enables bus master operation of the controller. Bus master operation begins when this bit is

detected changing from a zero to a one. The controller will transfer data between the IDE device

and memory only when this bit is set. Master operation can be halted by writing a '0' to this bit.

0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped

and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus Master

IDE Active bit of the Bus Master IDE Status register for that IDE channel is set) and the drive has

not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for that

IDE channel is not set), the bus master command is said to be aborted and data transferred from

the drive may be discarded instead of being written to system memory.

This bit is intended to be reset after the data transfer is completed, as indicated by either the Bus

Master IDE Active bit or the Interrupt bit of the Bus Master IDE Status register for that IDE

channel being set, or both.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

10-11

IDE Controller Registers (D31:F1)

10.2.2

BMIS[P,S]—Bus Master IDE Status Register

Address Offset:

Default Value:

Primary: 02h

Secondary: 0Ah

00h

Attribute:

Size:

R/WC

8 bits

Bit

Description

Reserved. Returns 0.

Drive 1 DMA Capable—R/W.

0 = Not Capable.

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this

channel is capable of DMA transfers, and that the controller has been initialized for optimum

performance. The ICH2 does not use this bit. It is intended for systems that do not attach BMIDE

to the PCI bus.

Drive 0 DMA Capable—R/W.

0 = Not Capable.

1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this

channel is capable of DMA transfers and that the controller has been initialized for optimum

performance. The ICH2 does not use this bit. It is intended for systems that do not attach BMIDE

to the PCI bus.

4:3

Reserved. Returns 0s.

Interrupt—R/WC. Software can use this bit to determine if an IDE device has asserted its interrupt

line (IRQ14 for the Primary channel and IRQ15 for Secondary).

1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is

masked in the 8259 or the internal I/O APIC. When this bit is read as a one, all data transferred

from the drive is visible in system memory.

0 = This bit is cleared by software writing a '1' to the bit position. If this bit is cleared while the

interrupt is still active, this bit will remain clear until another assertion edge is detected on the

interrupt line.

Error—R/WC.

1 = This bit is set when the controller encounters a target abort or master abort when transferring

data on PCI.

0 = This bit is cleared by software writing a '1' to the bit position.

Bus Master IDE Active (ACT)—RO.

1 = Set by the ICH2 when the Start bit is written to the Command register.

0 = This bit is cleared by the ICH2 when the last transfer for a region is performed, where EOT for

that region is set in the region descriptor. It is also cleared by the ICH2 when the Start bit is

cleared in the Command register. When this bit is read as a zero, all data transferred from the

drive during the previous bus master command is visible in system memory, unless the bus

master command was aborted.

10.2.3

BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Address Offset:

Default Value:

Primary: 04h

Secondary: 0Ch

All bits undefined

Attribute:

Size:

R/W

32 bits

Bit

Description

Base address of Descriptor table (BADDR)—R/W. Corresponds to A[31:2]. The Descriptor Table

must be DWord aligned. The Descriptor Table must not cross a 64 KB boundary in memory.

31:2

1:0

Reserved.

10-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

11.1

PCI Configuration Registers (D31:F2/F4)

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

Table 11-1. PCI Configuration Map (USB—D31:F2/F4)

Function 2

Default

Function 4

Default

Offset

Mnemonic

Type

00–01h

02–03h

04–05h

06–07h

08h

VID

DID

Vendor ID

8086h

2442h

0000h

0280h

See Note

00h

8086h

2444h

0000h

0280h

See Note

00h

R/W

Device ID

CMD

STA

Command Register

Device Status

RID

Revision ID

09h

Programming Interface

Sub Class Code

Base Class Code

Header Type

0Ah

SCC

03h

0Bh

BCC

0Ch

0Eh

HTYPE

Base

SVID

SID

00h

20–23h

2C–2Dh

2E–2Fh

3Ch

Base Address Register

Subsystem Vendor ID

Subsystem ID

00000001h

INTR_LN

INTR_PN

Interrupt Line

00h

3Dh

Interrupt Pin

03h

60h

SB_RELNUM Serial Bus Release Number

10h

USB Legacy Keyboard/

Mouse Control

C0–C1h USB_LEGKEY

2000h

00h

2000h

00h

R/W

C4h

USB_RES

USB Resume Enable

NOTE: Refer to the Specification Update for the value of the Revision ID Register.

11.1.1

VID—Vendor Identification Register (USB—D31:F2/F4)

Address Offset:

Default Value:

00–01h

8086h

Attribute:

Size:

16 bits

Bit

Description

Vendor ID Value—RO. This is a 16-bit value assigned to Intel.

15:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-1

USB Controller Registers

11.1.2

11.1.3

DID—Device Identification Register (USB—D31:F2/F4)

Address Offset:

Default Value:

02–03h

Function 2: 2442h

Function 4: 2444h

Attribute:

Size:

16 bits

Bit

Description

Device ID Value—RO. This is a 16-bit value assigned to the ICH2 USB Host Controllers

15:0

CMD—Command Register (USB—D31:F2/F4)

Address Offset:

Default Value:

04–05h

0000h

Attribute:

Size:

R/W

16 bits

Bit

Description

15:10

Reserved.

Fast Back to Back Enable (FBE)—RO. Reserved as 0.

SERR# Enable—RO. Reserved as 0.

Wait Cycle Control—RO. Reserved as 0.

Parity Error Response—RO. Reserved as 0.

VGA Palette Snoop—RO. Reserved as 0.

Postable Memory Write Enable (PMWE)—RO. Reserved as 0.

Special Cycle Enable (SCE)—RO. Reserved as 0.

Bus Master Enable (BME)—R/W. When set, the ICH2 can act as a master on the PCI bus for USB

transfers.

Memory Space Enable (MSE)—RO. Reserved as 0.

I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers.

1 = Enable accesses to the USB I/O registers. The Base Address register for USB should be

programmed before this bit is set.

0 = Disable

11-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

11.1.4

STA—Device Status Register (USB—D31:F2/F4)

Address Offset:

Default Value:

06–07h

0280h

Attribute:

Size:

R/WC

16 bits

Bit

Description

15:14 Reserved as ‘00b’. Read Only.

Received Master-Abort Status (RMA)—R/WC.

1 = USB, as a master, generated a master-abort.

0 = Software clears this bit by writing a 1 to the bit location.

Reserved. Always read as 0.

Signaled Target-Abort Status (STA)—R/WC.

1 = USB function is targeted with a transaction that the ICH2 terminates with a target abort.

0 = Software clears this bit by writing a 1 to the bit location.

DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL# assertion.

10:9 These read only bits indicate the ICH2's DEVSEL# timing when performing a positive decode. ICH2

generates DEVSEL# with medium timing for USB.

Data Parity Error Detected: Reserved as 0. Read Only.

Fast Back-to-Back Capable: Reserved as 1. Read Only.

User Definable Features (UDF): Reserved as 0. Read Only.

66 MHz Capable: Reserved as 0. Read Only.

Reserved.

4:0

11.1.5

11.1.6

RID—Revision Identification Register (USB—D31:F2/F4)

Address Offset:

Default Value:

08h

Attribute:

Size:

8 bits

See bit description

Bit

Description

Revision Identification. These bits contain device stepping information and are hardwired to the

default value. Refer to the Specification Update for the value of the Revision ID Register.

7:0

PI—Programming Interface (USB—D31:F2/F4)

Address Offset:

Default Value:

09h

00h

Attribute:

Size:

8 bits

Bit

Description

Programming Interface—RO.

00h = No specific register level programming interface defined.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-3

USB Controller Registers

11.1.7

11.1.8

11.1.9

SCC—Sub Class Code Register (USB—D31:F2/F4)

Address Offset:

Default Value:

0Ah

03h

Attribute:

Size:

8 bits

Bit

Description

Sub Class Code—RO.

7:0

03h = Universal Serial Bus Host Controller.

BCC—Base Class Code Register (USB—D31:F2/F4)

Address Offset:

Default Value:

0Bh

0Ch

Attribute:

Size:

8 bits

Bit

Description

Base Class Code—RO.

7:0

0Ch = Serial Bus controller.

BASE—Base Address Register (USB—D31:F2/F4)

Address Offset:

Default Value:

20–23h

00000001h

Attribute:

Size:

R/W

32 bits

Bit

Description

31:16

15:5

4:1

Reserved.

Base Address—R/W. Bits [15:5] correspond to I/O address signals AD [15:5], respectively. This

gives 32 bytes of relocatable I/O space.

Reserved.

Resource Type Indicator (RTE)—RO. This bit is hardwired to 1 indicating that the base address

field in this register maps to I/O space

11.1.10 SVID—Subsystem Vendor ID (USB—D31:F2/F4)

Address Offset:

Default Value:

Lockable:

2Ch–2Dh

00h

Attribute:

Size:

Power Well:

16 bits

Core

Bit

Description

Subsystem Vendor ID (SVID)—RO. The SVID register, in combination with the Subsystem ID

(SID) register, enables the operating system (OS) to distinguish subsystems from each other. The

value returned by reads to this register is the same as that which was written by BIOS into the

IDE_SVID register.

15:0

11-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

11.1.11 SID—Subsystem ID (USB—D31:F2/F4)

Address Offset:

Default Value:

Lockable:

2Eh–2Fh

00h

Attribute:

Size:

Power Well:

16 bits

Core

Bit

Description

Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register,

enables the operating system (OS) to distinguish subsystems from each other. The value returned

by reads to this register is the same as that which was written by BIOS into the IDE_SID register.

15:0

11.1.12 INTR_LN—Interrupt Line Register (USB—D31:F2/F4)

Address Offset:

Default Value:

3Ch

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Interrupt Line—R/W. This data is not used by the ICH2. It is to communicate to software the interrupt

line that the interrupt pin is connected to.

7:0

11.1.13 INTR_PN—Interrupt Pin Register (USB—D31:F2/F4)

Address Offset:

Default Value:

3Dh

Attribute:

Size:

Function 2: 03h(82801BA ICH2)

8 bits

04h (82801B AM ICH2-M)

Function 4: 03h (both ICH2 and ICH2-M)

Bit

Description

7:3

Reserved.

Interrupt Pin—RO. The value of 03h in Function 2 indicates that the ICH2 will drive PIRQD# as its

interrupt line for USB Controller 0 (ports 0 and 1).

2:0

The value of 03h in Function 4 indicates that the ICH2 will drive PIRQC# as its interrupt line for USB

Controller 1 (ports 2 and 3). However, in the ICH2 implementation, when the USB Controller 1

interrupt is generated PIRQ[H]# will go active, not PIRQ[C]#.

11.1.14 SB_RELNUM—Serial Bus Release Number Register

(USB—D31:F2/F4)

Address Offset:

Default Value:

60h

10h

Attribute:

Size:

8 bits

Bit

Description

Serial Bus Release Number—RO.

10h = Indicates that the USB controller is compliant with the USB specification release 1.0.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-5

USB Controller Registers

11.1.15 USB_LEGKEY—USB Legacy Keyboard/Mouse Control

Address Offset:

Default Value:

C0–C1

2000h

Attribute:

Size:

R/W, R/WC, RO

16 bits

Bit

Description

SMI Caused by End of Pass-through (SMIBYENDPS)—R/WC. Indicates if the event occurred.

Note that even if the corresponding enable bit is not set in bit 0, this bit will still be active. It is up to the

SMM code to use the enable bit to determine the exact cause of the SMI#.

1 = Event Occurred

0 = Software clears this bit by writing a 1 to the bit location.

Reserved.

PCI Interrupt Enable (USBPIRQEN)—R/W. Used to prevent the USB controller from generating an

interrupt due to transactions on its ports. Note that it will probably be configured to generate an SMI

using bit 4 of this register. Default to 1 for compatibility with older USB software.

1 = Enable

0 = Disable

SMI Caused by USB Interrupt (SMIBYUSB)—RO. Indicates if the event occurred. Note that even if

the corresponding enable bit is not set in the bit 4, this bit will still be active. It is up to the SMM code

to use the enable bit to determine the exact cause of the SMI#.

1 = Event Occurred

0 = Software should clear the IRQ via the USB controller. Writing a 1 to this bit will have no effect.

SMI Caused by Port 64 Write (TRAPBY64W)—R/WC. Indicates if the event occurred. Note that

even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM

code to use the enable bit to determine the exact cause of the SMI#.

1 = Event Occurred

0 = Software clears this bit by writing a 1 to the bit location.

SMI Caused by Port 64 Read (TRAPBY64R)—R/WC. Indicates if the event occurred. Note that

even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM

code to use the enable bit to determine the exact cause of the SMI#.

1 = Event Occurred

0 = Software clears this bit by writing a 1 to the bit location.

SMI Caused by Port 60 Write (TRAPBY60W)—R/WC. Indicates if the event occurred. Note that

even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM

code to use the enable bit to determine the exact cause of the SMI#.

1 = Event Occurred

0 = Software clears this bit by writing a 1 to the bit location.

SMI Caused by Port 60 Read (TRAPBY60R)—R/WC. Indicates if the event occurred. Note that

even if the corresponding enable bit is not set in bit 0, this bit will still be active. It is up to the SMM

code to use the enable bit to determine the exact cause of the SMI#.

1 = Event Occurred

0 = Software clears this bit by writing a 1 to the bit location.

SMI at End of Pass-through Enable (SMIATENDPS)—R/W. May need to cause SMI at the end of a

pass-through. Can occur if an SMI is generated in the middle of a pass through, and needs to be

serviced later.

1 = Enable

0 = Disable

Pass Through State (PSTATE)—RO.

1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.

0 = If software needs to reset this bit, it should set bit 5 to 0.

A20Gate Pass-Through Enable (A20PASSEN)—R/W.

1 = Allows A20GATE sequence Pass-Through function. SMI# will not be generated, even if the

various enable bits are set.

0 = Disable

11-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

Bit

Description

SMI on USB IRQ Enable (USBSMIEN)—R/W.

1 = USB interrupt will cause an SMI event.

0 = Disable

SMI on Port 64 Writes Enable (64WEN)—R/W.

1 = A write to port 64h will cause an SMI event.

0 = Disable

SMI on Port 64 Reads Enable (64REN)—R/W.

1 = A read to port 64h will cause an SMI event.

0 = Disable

SMI on Port 60 Writes Enable (60WEN)—R/W.

1 = A write to port 60h will cause an SMI event.

0 = Disable

SMI on Port 60 Reads Enable (60REN)—R/W.

1 = A read to port 60h will cause an SMI event.

0 = Disable

11.1.16 USB_RES—USB Resume Enable Register

(USB—D31:F2/F4)

Address Offset:

Default Value:

C4h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

7:2

Reserved.

PORT1EN—R/W. Enable the USB controller to respond to wakeup events on this port. For Function

2 this applies to port 1; for Function 4, this applies to port 3.

1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.

0 = The USB controller will not look at this port for a wakeup event.

PORT0EN—R/W. Enable the USB controller to respond to wakeup events on this port. For Function

2 this applies to port 0; for Function 4, this applies to port 2.

1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.

0 = The USB controller will not look at this port for a wakeup event.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-7

USB Controller Registers

11.2

USB I/O Registers

Some of the read/write register bits that deal with changing the state of the USB hub ports function

such that on read back they reflect the current state of the port, and not necessarily the state of the

last write to the register. This allows the software to poll the state of the port and wait until it is in

the proper state before proceeding. A Host Controller Reset, Global Reset, or Port Reset will

immediately terminate a transfer on the affected ports and disable the port. This affects the

USBCMD register, bit [4] and the PORTSC registers, bits [12,6,2]. See individual bit descriptions

for more detail.

Table 11-2. USB I/O Registers

Offset

Mnemonic

Default

Type

00–01h

02–03h

04–05h

06–07h

08–0Bh

0Ch

USBCMD

USBSTS

USBINTR

FRNUM

USB Command Register

USB Status Register

USB Interrupt Enable

USB Frame Number

0000h

0020h

0000h

Undefined

40h

R/W*

R/WC

R/W

R/W (see Note 1)

FRBASEADD USB Frame List Base Address

R/W

SOFMOD

—

USB Start of Frame Modify

Reserved

R/W

0D–0Fh

10–11h

12–13h

14–17h

18h

R/WC (see Note 1)

PORTSC0

PORTSC1

—

Port 0 Status/Control

Port 1 Status/Control

Reserved

0080h

LOOPDATA

Loop Back Test Data

00h

NOTES:

1. These registers are Word writable only. Byte writes to these registers have unpredictable effects.

11.2.1

USBCMD—USB Command Register

I/O Offset:

Default Value:

Base + (00–01h)

0000h

Attribute:

Size:

R/W

16 bits

The Command Register indicates the command to be executed by the serial bus host controller.

Writing to the register causes a command to be executed. The table following the bit description

provides additional information on the operation of the Run/Stop and Debug bits.

Bit

Description

15:7

Reserved.

Loop Back Test Mode—R/W.

1 = ICH2 is in loop back test mode. When both ports are connected together, a write to one port will

be seen on the other port and the data will be stored in I/O offset 18h.

0 = Disable loop back test mode.

Max Packet (MAXP)—R/W. This bit selects the maximum packet size that can be used for full

speed bandwidth reclamation at the end of a frame. This value is used by the Host Controller to

determine whether it should initiate another transaction based on the time remaining in the SOF

counter. Use of reclamation packets larger than the programmed size will cause a Babble error if

executed during the critical window at frame end. The Babble error results in the offending endpoint

being stalled. Software is responsible for ensuring that any packet which could be executed under

bandwidth reclamation be within this size limit.

1 = 64 bytes

0 = 32 bytes

11-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

Bit

Description

Configure Flag (CF)—R/W. This bit has no effect on the hardware. It is provided only as a

semaphore service for software.

1 = HCD software sets this bit as the last action in its process of configuring the Host Controller.

0 = Indicates that software has not completed host controller configuration.

Software Debug (SWDBG)—R/W. The SWDBG bit must only be manipulated when the controller is

in the stopped state. This can be determined by checking the HCHalted bit in the USBSTS register.

1 = Debug mode. In SW Debug mode, the Host Controller clears the Run/Stop bit after the

completion of each USB transaction. The next transaction is executed when software sets the

Run/Stop bit back to 1.

0 = Normal Mode.

Force Global Resume (FGR)—R/W.

1 = Host Controller sends the Global Resume signal on the USB, and sets this bit to 1 when a

resume event (connect, disconnect, or K-state) is detected while in global suspend mode.

0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global Resume signal.

At that time all USB devices should be ready for bus activity. The 1 to 0 transition causes the

port to send a low speed EOP signal. This bit will remain a 1 until the EOP has completed.

Enter Global Suspend Mode (EGSM)—R/W.

1 = Host Controller enters the Global Suspend mode. No USB transactions occur during this time.

The Host Controller is able to receive resume signals from USB and interrupt the system.

Software must ensure that the Run/Stop bit (bit 0) is cleared prior to setting this bit.

0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes this bit to 0 at

the same time that Force Global Resume (bit 4) is written to 0 or after writing bit 4 to 0.

Global Reset (GRESET)—R/W.

1 = Global Reset. The Host Controller sends the global reset signal on the USB and then resets all

its logic, including the internal hub registers. The hub registers are reset to their power on state.

Chip Hardware Reset has the same effect as Global Reset (bit 2), except that the Host

Controller does not send the Global Reset on USB.

0 = This bit is reset by the software after a minimum of 10 ms has elapsed as specified in Chapter 7

of the USB Specification.

Host Controller Reset (HCRESET)—R/W. The effects of HCRESET on Hub registers are slightly

different from Chip Hardware Reset and Global USB Reset. The HCRESET affects bits [8,3:0] of the

Port Status and Control Register (PORTSC) of each port. HCRESET resets the state machines of

the Host Controller including the Connect/Disconnect state machine (one for each port). When the

Connect/Disconnect state machine is reset, the output that signals connect/disconnect are negated

to 0, effectively signaling a disconnect, even if a device is attached to the port. This virtual

disconnect causes the port to be disabled. This disconnect and disabling of the port causes bit 1

(connect status change) and bit 3 (port enable/disable change) of the PORTSC to get set. The

disconnect also causes bit 8 of PORTSC to reset. About 64 bit times after HCRESET goes to 0, the

connect and low-speed detect will take place, and bits 0 and 8 of the PORTSC will change

accordingly.

1 = Reset. When this bit is set, the Host Controller module resets its internal timers, counters, state

machines, etc. to their initial value. Any transaction currently in progress on USB is immediately

terminated.

0 = Reset by the Host Controller when the reset process is complete.

Run/Stop (RS)—R/W. When set to 1, the ICH2 proceeds with execution of the schedule. The ICH2

continues execution as long as this bit is set. When this bit is cleared, the ICH2 completes the

current transaction on the USB and then halts. The HC Halted bit in the status register indicates

when the Host Controller has finished the transaction and has entered the stopped state. The Host

Controller clears this bit when the following fatal errors occur: consistency check failure, PCI Bus

errors.

1 = Run

0 = Stop

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-9

USB Controller Registers

Table 11-3. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation

SWDBG Run/Stop

Description

(Bit 5)

(Bit 0)

If executing a command, the Host Controller completes the command and then

stops. The 1.0 ms frame counter is reset and command list execution resumes from

start of frame using the frame list pointer selected by the current value in the FRNUM

Execution of the command list resumes from Start Of Frame using the frame list

pointer selected by the current value in the FRNUM register. The Host Controller

remains running until the Run/Stop bit is cleared (by software or hardware).

If executing a command, the Host Controller completes the command and then stops

and the 1.0 ms frame counter is frozen at its current value. All status are preserved.

The Host Controller begins execution of the command list from where it left off when

the Run/Stop bit is set.

Execution of the command list resumes from where the previous execution stopped.

The Run/Stop bit is set to 0 by the Host Controller when a TD is being fetched. This

causes the Host Controller to stop again after the execution of the TD (single step).

When the Host Controller has completed execution, the HC Halted bit in the Status

When the USB Host Controller is in Software Debug Mode (USBCMD Register bit 5=1), the

single stepping software debug operation is as follows:

To Enter Software Debug Mode:

1. HCD puts Host Controller in Stop state by setting the Run/Stop bit to 0.

2. HCD puts Host Controller in Debug Mode by setting the SWDBG bit to 1.

3. HCD sets up the correct command list and Start Of Frame value for starting point in the Frame

List Single Step Loop.

4. HCD sets Run/Stop bit to 1.

5. Host Controller executes next active TD, sets Run/Stop bit to 0, and stops.

6. HCD reads the USBCMD register to check if the single step execution is completed

(HCHalted=1).

7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to end

Software Debug mode.

8. HCD ends Software Debug mode by setting SWDBG bit to 0.

9. HCD sets up normal command list and Frame List table.

10. HCD sets Run/Stop bit to 1 to resume normal schedule execution.

In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts. When a valid TD

is found, the Run/Stop bit is reset. When the TD is finished, the HCHalted bit in the USBSTS

The SW Debug mode skips over inactive TDs and only halts after an active TD has been executed.

When the last active TD in a frame has been executed, the Host Controller waits until the next SOF

is sent and then fetches the first TD of the next frame before halting.

This HCHalted bit can also be used outside of Software Debug mode to indicate when the Host

Controller has detected the Run/Stop bit and has completed the current transaction. Outside of the

Software Debug mode, setting the Run/Stop bit to 0 always resets the SOF counter so that when the

Run/Stop bit is set the Host Controller starts over again from the frame list location pointed to by

the Frame List Index (see FRNUM Register description) rather than continuing where it stopped.

11-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

11.2.2

USBSTA—USB Status Register

I/O Offset:

Default Value:

Base + (02–03h)

0020h

Attribute:

Size:

R/WC

16 bits

This register indicates pending interrupts and various states of the Host Controller. The status

resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0

in this register by writing a 1 to it.

Bit

Description

15:6

Reserved.

HCHalted—R/WC.

1 = The Host Controller has stopped executing as a result of the Run/Stop bit being set to 0, either

by software or by the Host Controller hardware (debug mode or an internal error). Default.

0 = Software resets this bit to 0 by writing a 1 to the bit position.

Host Controller Process Error—R/WC.

1 = The Host Controller has detected a fatal error. This indicates that the Host Controller suffered

a consistency check failure while processing a Transfer Descriptor. An example of a

consistency check failure would be finding an illegal PID field while processing the packet

header portion of the TD. When this error occurs, the Host Controller clears the Run/Stop bit

in the Command register to prevent further schedule execution. A hardware interrupt is

generated to the system.

0 = Software resets this bit to 0 by writing a 1 to the bit position.

Host System Error—R/WC.

1 = A serious error occurred during a host system access involving the Host Controller module. In

a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and

PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the

Command register to prevent further execution of the scheduled TDs. A hardware interrupt is

generated to the system.

0 = Software resets this bit to 0 by writing a 1 to the bit position.

Resume Detect (RSM_DET)—R/WC.

1 = The Host Controller received a “RESUME” signal from a USB device. This is only valid if the

Host Controller is in a global suspend state (bit 3 of Command register = 1).

0 = Software resets this bit to 0 by writing a 1 to the bit position.

USB Error Interrupt—R/WC.

1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow).

If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0

are set.

0 = Software resets this bit to 0 by writing a 1 to the bit position.

USB Interrupt (USBINT)—R/WC.

1 = The Host Controller sets this bit when the cause of an interrupt is a completion of a USB

transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is

detected (actual length field in TD is less than maximum length field in TD), and short packet

detection is enabled in that TD.

0 = Software resets this bit to 0 by writing a 1 to the bit position.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-11

USB Controller Registers

11.2.3

USBINTR—Interrupt Enable Register

I/O Offset:

Default Value:

Base + (04–05h)

0000h

Attribute:

Size:

R/W

16 bits

This register enables and disables reporting of the corresponding interrupt to the software. When a

bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors

(Host Controller Processor Error-bit 4, USBSTS Register) cannot be disabled by the host

controller. Interrupt sources that are disabled in this register still appear in the Status Register to

allow the software to poll for events.

Bit

Description

15:4

Reserved.

Short Packet Interrupt Enable—R/W.

1 = Enabled.

0 = Disabled.

Interrupt On Complete (IOC) Enable—R/W.

1 = Enabled.

0 = Disabled.

Resume Interrupt Enable—R/W.

1 = Enabled.

0 = Disabled.

Time-out/CRC Interrupt Enable—R/W.

1 = Enabled.

0 = Disabled.

11.2.4

FRNUM—Frame Number Register

I/O Offset:

Default Value:

Base + (06–07h)

0000h

Attribute:

Size:

R/W (Writes must be Word Writes)

16 bits

Bits [10:0] of this register contain the current frame number which is included in the frame SOF

packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are

used to select a particular entry in the Frame List during scheduled execution. This register is

updated at the end of each frame time.

This register must be written as a word. Byte writes are not supported. This register cannot be

written unless the Host Controller is in the STOPPED state as indicated by the HCHalted bit

(USBSTS register). A write to this register while the Run/Stop bit is set (USBCMD register) is

ignored.

Bit

Description

15:11

Reserved.

Frame List Current Index/Frame Number—R/W. Provides the frame number in the SOF Frame.

The value in this register increments at the end of each time frame (approximately every 1 ms). In

addition, bits [9:0] are used for the Frame List current index and correspond to memory address

signals [11:2].

10:0

11-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

11.2.5

FRBASEADD—Frame List Base Address

I/O Offset:

Default Value:

Base + (08–0Bh)

Undefined

Attribute:

Size:

R/W

32 bits

This 32-bit register contains the beginning address of the Frame List in the system memory. HCD

loads this register prior to starting the schedule execution by the Host Controller. When written,

only the upper 20 bits are used. The lower 12 bits are written as zero (4-KB alignment). The

contents of this register are combined with the frame number counter to enable the Host Controller

to step through the Frame List in sequence. The two least significant bits are always 00. This

requires DWord alignment for all list entries. This configuration supports 1024 Frame List entries.

Bit

Description

31:12

11:0

Base Address—R/W. These bits correspond to memory address signals [31:12], respectively.

Reserved.

11.2.6

SOFMOD—Start of Frame Modify Register

I/O Offset:

Default Value:

Base + (0Ch)

40h

Attribute:

Size:

R/W

8 bits

This 1-byte register is used to modify the value used in the generation of SOF timing on the USB.

Only the 7 least significant bits are used. When a new value is written into these 7 bits, the SOF

timing of the next frame will be adjusted. This feature can be used to adjust out any offset from the

clock source that generates the clock that drives the SOF counter. This register can also be used to

maintain real time synchronization with the rest of the system so that all devices have the same

sense of real time. Using this register, the frame length can be adjusted across the full range

required by the USB specification. Its initial programmed value is system dependent based on the

accuracy of hardware USB clock and is initialized by system BIOS. It may be reprogrammed by

USB system software at any time. Its value will take effect from the beginning of the next frame.

This register is reset upon a Host Controller Reset or Global Reset. Software must maintain a copy

of its value for reprogramming if necessary.

Bit

Description

Reserved.

SOF Timing Value—R/W. Guidelines for the modification of frame time are contained in Chapter 7 of

the USB Specification. The SOF cycle time (number of SOF counter clock periods to generate a SOF

frame length) is equal to 11936 + value in this field. The default value is decimal 64 which gives a SOF

cycle time of 12000. For a 12 MHz SOF counter clock input, this produces a 1 ms Frame period. The

following table indicates what SOF Timing Value to program into this field for a certain frame period.

Frame Length

(# 12 MHz Clocks)

(decimal)

SOF Reg. Value

(decimal)

11936

11937

6:0

11999

12000

12001

12062

12063

126

127

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-13

USB Controller Registers

11.2.7

PORTSC[0,1]—Port Status and Control Register

I/O Offset:

Port 0/2: Base + (10–11h)

Port 1/3: Base + (12–13h)

0080h

Attribute:

Size:

R/W (Word writes only)

16 bits

Default Value:

Note: For Function 2, this applies to ICH2 USB ports 0 and 1. For Function 4, this applies to ICH2 USB

ports 2 and 3.

After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a port are: no

device connected, Port disabled, and the bus line status is 00 (single-ended zero).

Bit

Description

15:13

Reserved—RO.

Suspend—R/W.±This bit should not be written to a 1 if global suspend is active (bit 3=1 in the

USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows:

Bits [12,2]

Hub State

Disable

Enable

Suspend

When in suspend state, downstream propagation of data is blocked on this port, except for single-

ended 0 resets (global reset and port reset). The blocking occurs at the end of the current

transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the

port is sensitive to resume detection. Note that the bit status does not change until the port is

suspended and that there may be a delay in suspending a port if there is a transaction currently in

progress on the USB.

1 = Port in suspend state.

0 = Port not in suspend state.

Note: Normally, if a transaction is in progress when this bit is set, the port will be suspended when

the current transaction completes. However, in the case of a specific error condition (out transaction

with babble), the ICH2 may issue a start-of-frame, and then suspend the port.

Overcurrent Indicator—R/WC. Set by hardware

1 = Overcurrent pin has gone from inactive to active on this port.

0 = Software clears this bit by writing a 1 to the bit position.

Overcurrent Active—RO. This bit is set and cleared by hardware.

1 = Indicates that the overcurrent pin is active (low).

0 = Indicates that the overcurrent pin is inactive (high).

Port Reset—RO.±

1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling.

0 = Port is not in Reset.

Low Speed Device Attached (LS)—RO. Writes have no effect.±

1 = Low speed device is attached to this port.

0 = Full speed device is attached.

Reserved—RO. Always read as 1.

Resume Detect (RSM_DET)—R/W. Software sets this bit to a 1 to drive resume signaling. The

Host Controller sets this bit to a 1 if a J-to-K transition is detected for at least 32 microseconds while

the port is in the Suspend state. The ICH2 then reflects the K-state back onto the bus as long as the

bit remains a 1 and the port is still in the suspend state (bit 12,2 are 11). Writing a 0 (from 1) causes

the port to send a low speed EOP. This bit will remain a 1 until the EOP has completed.

1 = Resume detected/driven on port.

0 = No resume (K-state) detected/driven on port.

Line Status—RO.±These bits reflect the D+ (bit 4) and D- (bit 5) signals lines’ logical levels. These

bits are used for fault detect and recovery as well as for USB diagnostics. This field is updated at

EOF2 time (See Chapter 11 of the USB Specification).

5:4

11-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

USB Controller Registers

Bit

Description

Port Enable/Disable Change—R/WC.±For the root hub, this bit gets set only when a port is

disabled due to disconnect on that port or due to the appropriate conditions existing at the EOF2

point (See Chapter 11 of the USB Specification).

1 = Port enabled/disabled status has changed.

0 = No change. Software clears this bit by writing a 1 to the bit location.

Port Enabled/Disabled (PORT_EN)—R/W.±Ports can be enabled by host software only. Ports can

be disabled by either a fault condition (disconnect event or other fault condition) or by host software.

Note that the bit status does not change until the port state actually changes and that there may be

a delay in disabling or enabling a port if there is a transaction currently in progress on the USB.

1 = Enable.

0 = Disable.

Connect Status Change—R/WC.±Indicates that a change has occurred in the port’s Current

Connect Status (see bit 0). The hub device sets this bit for any changes to the port device connect

status, even if system software has not cleared a connect status change. If, for example, the

insertion status changes twice before system software has cleared the changed condition, hub

hardware will be setting” an already-set bit (i.e., the bit will remain set). However, the hub transfers

the change bit only once when the Host Controller requests a data transfer to the Status Change

endpoint. System software is responsible for determining state change history in such a case.

1 = Change in Current Connect Status.

0 = No change. Software clears this bit by writing a 1 to the bit location.

Current Connect Status—RO.±This value reflects the current state of the port, and may not

correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.

1 = Device is present on port.

0 = No device is present.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

11-15

USB Controller Registers

This page is intentionally left blank.

11-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

SMBus Controller Registers (D31:F3)

SMBus Controller Registers (D31:F3) 12

12.1

PCI Configuration Registers (SMBUS—D31:F3)

Table 12-1. PCI Configuration Registers (SMBUS—D31:F3)

Offset

Mnemonic

Attribute

00–01h

02–03h

04–05h

06–07h

08h

VID

DID

CMD

STA

RID

Vendor ID

Device ID

Command Register

Device Status

RO, R/W

RO, R/WC

Revision ID

09h

Programming Interface

Sub Class Code

Base Class Code

0Ah

SCC

BCC

0Bh

20–23h

2C–2Dh

2E–2Fh

3Ch

SMB_BASE SMBus Base Address Register

R/W

SVID

SID

Subsystem Vendor ID

Subsystem ID

INTR_LN

INTR_PN

HOSTC

Interrupt Line

R/W

3Dh

Interrupt Pin

40h

Host Configuration

R/W

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

12.1.1

VID—Vendor Identification Register (SMBUS—D31:F3)

Address:

Default Value:

00–01h

8086h

Attributes:

Size:

16 bits

Bit

Description

15:0

Vendor ID Value—RO. This is a 16 bit value assigned to Intel

12.1.2

DID—Device Identification Register (SMBUS—D31:F3)

Address:

Default Value:

02–03h

2443h

Attributes:

Size:

16 bits

Bit

Description

15:0

Device ID value—RO.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

12-1

SMBus Controller Registers (D31:F3)

12.1.3

CMD—Command Register (SMBUS—D31:F3)

Address:

Default Value:

04–05h

0000h

Attributes:

Size:

RO, R/W

16 bits

Bit

Description

15:10

Reserved.

Fast Back to Back Enable (FBE)—RO. Reserved as 0.

SERR# Enable (SERREN)—RO. Reserved as 0.

Wait Cycle Control (WCC)—RO. Reserved as 0.

Parity Error Response (PER)—RO. Reserved as 0.

VGA Palette Snoop (VPS)—RO. Reserved as 0.

Postable Memory Write Enable (PMWE)—RO. Reserved as 0.

Special Cycle Enable (SCE)—RO. Reserved as 0.

Bus Master Enable (BME)—RO. Reserved as 0.

Memory Space Enable (MSE)—RO. Reserved as 0.

I/O Space Enable (IOSE)—R/W.

0 = Disable.

1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.

12.1.4

STA—Device Status Register (SMBUS—D31:F3)

Address:

Default Value:

06–07h

0280h

Attributes:

Size:

RO, R/WC

16 bits

Bit

Description

Detected Parity Error (DPE)—RO. Reserved as 0.

Signaled System Error (SSE)—RO. Reserved as 0.

Received Master Abort (RMA)—RO. Reserved as 0.

Received Target Abort (RTA)—RO. Reserved as 0.

Signaled Target-Abort Status (STA)—R/WC.

1 = Function is targeted with a transaction that the ICH2 terminates with a target abort.

0 = Software resets STA to 0 by writing a 1 to this bit location.

DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL# assertion

for positive decode.

10:9

01 = Medium timing.

Data Parity Error Detected—RO. Reserved as 0.

Fast Back-to-Back Capable—RO. Reserved as 1.

User Definable Features (UDF)—RO. Reserved as 0.

66 MHz Capable—RO. Reserved as 0.

Reserved.

4:0

12-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

SMBus Controller Registers (D31:F3)

12.1.5

12.1.6

RID—Revision ID Register (SMBUS—D31:F3)

Offset Address:

Default Value:

08h

Attribute:

Size:

8 bits

See bit description

Bit

Description

Revision Identification Number. 8-bit value that indicates the revision number for the SMBus

Controller. Refer to the Specification Update for the value of the Revision ID Register

7:0

PI—Programming Interface (SMBUS—D31:F3)

Address Offset:

Default Value:

09h

80h

Attribute:

Size:

8 bits

Bit

Description

Programming Interface Value—RO.

80h = The 1b in bit 7 indicates that this IDE controller is capable of bus master operation.

7:0

12.1.7

12.1.8

SCC—Sub Class Code Register (SMBUS—D31:F3)

Address Offset:

Default Value:

0Ah

05h

Attributes:

Size:

8 bits

Bit

Description

Sub Class Code—RO.

7:0

05h = SM Bus serial controller

BCC—Base Class Code Register (SMBUS—D31:F3)

Address Offset:

Default Value:

0Bh

0Ch

Attributes:

Size:

8 bits

Bit

Description

Base Class Code—RO.

7:0

0Ch = Serial controller.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

12-3

SMBus Controller Registers (D31:F3)

12.1.9

SMB_BASE—SMBus Base Address Register

(SMBUS—D31:F3)

Address Offset:

Default Value:

20–23h

00000001h

Attribute:

Size:

R/W

32-bits

Bit

Description

31:16

15:4

3:1

Reserved.

Base Address—R/W. Provides the 16-bit system I/O base address for the ICH2 SMB logic.

Reserved.

IO Space Indicator—RO. This read-only bit is always 1, indicating that the SMB logic is I/O

mapped.

12.1.10 SVID—Subsystem Vendor ID (SMBUS—D31:F2/F4)

Address Offset:

Default Value:

Lockable:

2Ch–2Dh

00h

Attribute:

Size:

Power Well:

16 bits

Core

Bit

Description

Subsystem Vendor ID (SVID)—RO. The SVID register, in combination with the Subsystem ID

(SID) register, enables the operating system (OS) to distinguish subsystems from each other. The

value returned by reads to this register is the same as that which was written by BIOS into the

IDE_SVID register.

15:0

12.1.11 SID—Subsystem ID (SMBUS—D31:F2/F4)

Address Offset:

Default Value:

Lockable:

2Eh–2Fh

00h

Attribute:

Size:

Power Well:

16 bits

Core

Bit

Description

Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register,

enables the operating system (OS) to distinguish subsystems from each other. The value returned

by reads to this register is the same as that which was written by BIOS into the IDE_SID register.

15:0

12.1.12 INTR_LN—Interrupt Line Register (SMBUS—D31:F3)

Address Offset:

Default Value:

3Ch

00h

Attributes:

Size:

R/W

8 bits

Bit

Description

Interrupt line—R/W. This data is not used by the ICH2. It is to communicate to software the interrupt

line that the interrupt pin is connected to PIRQB#.

7:0

12-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

SMBus Controller Registers (D31:F3)

12.1.13 INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)

Address Offset:

Default Value:

3Dh

02h

Attributes:

Size:

8 bits

Bit

Description

Interrupt PIN—RO.

02h = Indicates that the ICH2 SMBus Controller will drive PIRQB# as its interrupt line.

7:0

12.1.14 HOSTC—Host Configuration Register (SMBUS—D31:F3)

Address Offset:

Default Value:

40h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

7:3

Reserved.

I C Enable (I2C_EN)—R/W.

0 = SMBus behavior.

1 = The ICH2 is enabled to communicate with I C devices. This will change the formatting of some

commands.

SMBus to SMI Enable (SMB_SMI_EN)—R/W.

0 = SMBus interrupts will not generate an SMI#.

1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. This bit will only

take effect if the INTREN bit is set in I/O space.This bit needs to be set for SMBALERT# to be

enabled.

SMBus Host Enable (HST_EN)—R/W.

0 = Disable the SMBus Host Controller.

1 = Enable. The SMB Host Controller interface is enabled to execute commands. The INTREN bit

needs to be enabled for the SMB Host Controller to interrupt or SMI#. Note that the SMB Host

Controller will not respond to any new requests until all interrupt requests have been serviced.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

12-5

SMBus Controller Registers (D31:F3)

12.2

SMBus I/O Registers

Table 12-2. SMB I/O Registers

Offset

Mnemonic

Host Status

Default

Access

00h

02h

HST_STS

HST_CNT

HST_CMD

XMIT_SLVA

HST_D0

HST_D1

BLOCK_DB

—

00h

44h

0000h

00h

R/W

Host Control

03h

Host Command

Transmit Slave Address

Host Data 0

04h

05h

06h

Host Data 1

07h

Block Data Byte

Reserved

08h

09h

RCV_SLVA

SLV_DATA

—

Receive Slave Address

Slave Data

R/W

0Ah

0Bh–0Dh

Reserved

See

0Eh

0Fh

SMLINK_PIN_CTL

SMBUS_PIN_CTL

SMLINK Pin Control

SMbus Pin Control

Description

R/W

See

Description

12-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

SMBus Controller Registers (D31:F3)

12.2.1

HST_STS—Host Status Register

Default Value:

00h

Attribute:

Size:

R/WC

8-bits

All status bits are set by hardware and cleared by the software writing a one to the particular bit

position. Writing a zero to any bit position has no effect.

Bit

Description

Byte Done Status (BYTE_DONE_STA)—R/WC.

1 = The ICH2 has received a byte (for Block Read commands) or if it has completed transmission

of a byte (for Block Write commands). This bit will be set even on the last byte of the transfer. It

will not be set when transmission is due to the Alert On LAN* heartbeat.

0 = Cleared by writing a 1 to the bit position.

In Use Status (INUSE_STA)—R/WC (special). This bit is used as semaphore among various

independent software threads that may need to use the ICH2’s SMBus logic and has no other effect

on Hardware.

0 = After a full PCI reset, a read to this bit returns a 0.

1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next

read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0,

and will then own the usage of the host controller.

SMBus Alert Status (SMBALERT_STA)—R/WC.

0 = Interrupt or SMI# was not generated by SMBALERT#.

1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by

software writing a 1 to the bit position or by RSMRST# going low.

If the signal is programmed as a GPIO, then this bit will never be set.

Interrupt/SMI# was Failed Bus Transaction (FAILED)—R/WC.

1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to

the KILL bit being set to terminate the host transaction.

0 = Cleared by writing a 1 to the bit position.

Bus Error (BUS_ERR)—R/WC.

1 = The source of the interrupt of SMI# was a transaction collision.

0 = Cleared by writing a 1 to the bit position.

Device Error (DEV_ERR)—R/WC.

1 = The source of the interrupt or SMI# was due to one of the following:

•

Illegal Command Field,

Unclaimed Cycle (host initiated),

Host Device Time-out Error.]

0 = Software resets this bit by writing a 1 to this location. The ICH2 will then deassert the interrupt

or SMI#.

Interrupt/SMI# was Successful Completion (INTR)—R/WC (special). This bit can only be set by

termination of a command. INTR is not dependent on the INTREN bit of the Host Controller Register

(offset 02h); it is only dependent on the termination of the command. If the INTREN bit is not set, the

INTR bit will be set, although the interrupt will not be generated. Software can poll the INTR bit in

this non-interrupt case.

1 = The source of the interrupt or SMI# was the successful completion of its last command.

0 = Software resets this bit by writing 1 to this location. The ICH2 then deasserts the interrupt or

SMI#.

Host Busy (HOST_BUSY)—RO.

1 = Indicates that the ICH2 is running a command from the host interface. No SMB registers should

be accessed while this bit is set, except the Block Data Byte Register. The Block Data Byte

to check the BYTE_DONE_STS bit.

0 = Cleared by the ICH2 when the current transaction is completed.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

12-7

SMBus Controller Registers (D31:F3)

12.2.2

HST_CNT—Host Control Register

Default Value:

02h

00h

Attribute:

Size:

R/W

8-bits

Bit

Description

Reserved.

START—WO.

1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All registers

should be setup prior to writing a 1 to this bit position.

0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status register (offset

00h) can be used to identify when the ICH2 has finished the command.

LAST BYTE—WO. This bit is used for Block Read commands.

1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the

block. This causes the ICH2 to send a NACK (instead of an ACK) after receiving the last byte.

SMBus Command (SMB_CMD)—R/W. The bit encoding below indicates which command the ICH2

is to perform. If enabled, the ICH2 generates an interrupt or SMI# when the command has

completed. If the value is for a non-supported or reserved command, the ICH2 sets the device error

(DEV_ERR) status bit and generates an interrupt when the START bit is set. The ICH2 performs no

command and does not operate until DEV_ERR is cleared.

000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit slave address

001 = Byte: This command uses the transmit slave address and command registers. Bit 0 of the

slave address register determines if this is a read or write command.

010 = Byte Data: This command uses the transmit slave address, command, and DATA0 registers.

Bit 0 of the slave address register determines if this is a read or write command. If it is a read,

the DATA0 register will contain the read data.

011 = Word Data: This command uses the transmit slave address, command, DATA0 and DATA1

registers. Bit 0 of the slave address register determines if this is a read or write command. If it

is a read, after the command completes, the DATA0 and DATA1 registers will contain the read

data.

4:2

100 = Process Call: This command uses the transmit slave address, command, DATA0 and DATA1

registers. Bit 0 of the slave address register determines if this is a read or write command.

After the command completes, the DATA0 and DATA1 registers will contain the read data.

101 = Block: This command uses the transmit slave address, command, DATA0 registers, and the

Block Data Byte register. For block write, the count is stored in the DATA0 register and

indicates how many bytes of data will be transferred. For block reads, the count is received

and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or

write command. For writes, data is retrieved from the first n (where n is equal to the specified

count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte

110 = I C Read: This command uses the transmit slave address, command, DATA0, DATA1

registers, and the Block Data Byte register. The read data is stored in the Block Data Byte

111 = Reserved

KILL—R/W.

1 = When set, kills the current host transaction taking place, sets the FAILED status bit, and

asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the

SMBus Host Controller to function normally.

0 = Normal SMBus Host Controller functionality.

INTREN—R/W.

1 = Enable the generation of an interrupt or SMI# upon the completion of the command.

0 = Disable.

12-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

SMBus Controller Registers (D31:F3)

12.2.3

12.2.4

HST_CMD—Host Command Register

Default Value:

03h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Host Command—R/W. This eight bit field is transmitted by the host controller in the command field

of the SMBus protocol during the execution of any command.

7:0

XMIT_SLVA—Transmit Slave Address Register

Default Value:

04h

00h

Attribute:

Size:

R/W

8 bits

This register is transmitted by the host controller in the slave address field of the SMBus protocol.

Bit

Description

7:1

ADDRESS—R/W. 7-bit address of the targeted slave.

Read/Write Select—R/W. Direction of the host transfer.

0 = Write

1 = Read

12.2.5

12.2.6

HST_D0—Data 0 Register

Default Value:

05h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

DATA0/COUNT—R/W. This field contains the eight bit data sent in the DATA0 field of the SMBus

protocol. For block write commands, this register reflects the number of bytes to transfer. This register

should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32

will result in unpredictable behavior. The host controller does not check or log illegal block counts.

7:0

HST_D1—Data 1 Register

Default Value:

06h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

DATA1—R/W. This eight bit register is transmitted in the DATA1 field of the SMBus protocol during

the execution of any command.

7:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

12-9

SMBus Controller Registers (D31:F3)

12.2.7

BLOCK_DB—Block Data Byte Register

Default Value:

07h

00h

Attribute:

Size:

R/W

8 bits

Bit

Description

Block Data Byte—R/W. For Block Writes, software writes the first byte to this register as part of the

setup for this command. After the ICH2 has sent the Address, Command, and Byte Count fields, it will

send the byte in the Block Data Byte register. After the byte has been sent, the ICH2 sets the

BYTE_DONE_STS bit in the Host Status register. If there are more bytes to send, the software then

writes in the next byte to the Block Data Byte register and software also clears the BYTE_DONE_STS

bit. The ICH2 then sends the next byte. During the time from when a byte has been transmitted to

7:0

when the next byte has been loaded, the ICH2 inserts wait-states on the SMBus/I C.

A similar process will be used for Block Reads. After receiving the byte count (which goes in the DATA

0 register), the first “data byte” goes in the Block Data Byte register and the ICH2 generates an SMI#

or interrupt (depending on configuration). The interrupt or SMI# handler then reads the byte and

clears the BYTE_DONE_STS bit. This frees room for the next byte. During the time from when a byte

is read to when the BYTE_DONE_STS bit is cleared, the ICH2 inserts wait-states on the SMBus/I C.

12.2.8

RCV_SLVA—Receive Slave Address Register

Default Value:

Lockable:

09h

44h

Attribute:

Size:

Power Well:

R/W

8 bits

Resume

Bit

Description

Reserved

SLAVE_ADDR—R/W. This field is the slave address that the ICH2 decodes for read and write cycles.

The default is not 0 so the SMBus Slave Interface can respond even before the processor comes up

(or if the processor is dead). This register is cleared by RSMRST#, but not by PCIRST#.

6:0

12.2.9

SLV_DATA—Receive Slave Data Register

Default Value:

Lockable:

0Ah

00h

Attribute:

Size:

Power Well:

16 bits

Resume

This register contains the 16-bit data value written by the external SMBus master. The CPU can

then read the value from this register. This register is reset by RSMRST#, but not PCIRST#.

Bit

Description

15:8

7:0

DATA_MSG1: Data Message Byte 1—RO. See Section 5.17.5 for a discussion of this field.

DATA_MSG0: Data Message Byte 0—RO. See Section 5.17.5 for a discussion of this field.

12-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

SMBus Controller Registers (D31:F3)

12.2.10 SMLINK_PIN_CTL—SMLINK Pin Control Register

Default Value:

0Eh

See Below

Attribute:

Size:

Read/Write

8 bits

Note: This register is in the resume well and is reset by RSMRST#.

Bit

Description

7:3

Reserved

SMLINK Clock Pin Control (SMLINK_CLK_CTL)—R/W.

1 = No functional impact on the SMLINK[0] pin. (default)

0 = ICH2 will drive the SMLINK[0] pin low, independent of the what the other SMLINK logic would

otherwise indicate for the SMLINK[0] pin.

SMLINK[1] Pin Current Status (SMLINK[1]_CUR_STA)—RO. This read-only bit has a default

value that is dependent on an external signal level. This pin returns the value on the SMLINK[1]

pin. This allows software to read the current state of the pin.

1 = SMLINK[1] pin is high

0 = SMLINK[1] pin is low

SMLINK[0] Pin Current Status (SMLINK[0]_CUR_STA)—RO. This read-only bit has a default

value that is dependent on an external signal level. This pin returns the value on the SMLINK[0]

pin. This allows software to read the current state of the pin.

1 = SMLINK[0] pin is high

0 = SMLINK[0] pin is low

12.2.11 SMBUS_PIN_CTL—SMBus Pin Control Register

Default Value:

0Fh

See Below

Attribute:

Size:

Read/Write

8 bits

Note: This register is in the resume well and is reset by RSMRST#.

Bit

Description

7:3

Reserved

SMBCLK Pin Control (SMBCLK_CTL)—R/W.

1 = No functional impact on the SMBCLK pin. (default)

0 = ICH2 drives the SMBCLK pin low, independent of the what the other SMB logic would

otherwise indicate for the SMBCLK pin.

SMBDATA Pin Current Status (SMBDATA_CUR_STA)—RO. This read-only bit has a

default value that is dependent on an external signal level. This pin returns the value on

the SMBDATA pin. This allows software to read the current state of the pin.

1 = SMBDATA pin is high

0 = SMBDATA pin is low

SMBCLK Pin Current Status (SMBCLK_CUR_STA)—RO. This read-only bit has a

default value that is dependent on an external signal level. This pin returns the value on

the SMBCLK pin. This allows software to read the current state of the pin.

1 = SMBCLK pin is high

0 = SMBCLK pin is low

82801BA ICH2 and 82801BAM ICH2-M Datasheet

12-11

SMBus Controller Registers (D31:F3)

This page is intentionally left blank.

12-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

AC’97 Audio Controller Registers

(D31:F5)

13.1

AC’97 Audio PCI Configuration Space (D31:F5)

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

Table 13-1. PCI Configuration Map (Audio—D31:F5)

Offset

Mnemonic

Vendor Identification

Default

Access

00h–01h

02h–03h

04h–05h

06h–07h

08h

VID

DID

8086h

2445h

0000

0280h

See Note

Device Identification

PCI Command

PCICMD

PCISTS

RID

R/W

R/WC

PCI Device Status

Revision Identification

Programming Interface

Sub Class Code

09h

0Ah

SCC

01h

0Bh

BCC

Base Class Code

04h

0Eh

HEDT

NAMBAR

Header Type

10h–13h

14h–17h

18h–2Bh

2Ch–2Dh

2Eh–2Fh

30h–3Bh

3Ch

Native Audio Mixer Base Address

00000001h

00h

R/W

NABMBAR Native Audio Bus Mastering Base Address

—

SVID

SID

Reserved

Subsystem Vendor ID

Subsystem ID

Reserved

0000h

—

Write-Once

—

INTR_LN

INTR_PN

—

Interrupt Line

Interrupt Pin

Reserved

00h

R/W

3Dh

02h

3Eh–FFh

—

NOTE: Refer to the Specification Update for the value of the Revision ID Register

13.1.1

VID—Vendor Identification Register (Audio—D31:F5)

Offset:

Default Value:

Lockable:

01h-00h

8086h

Attribute:

Size:

Power Well:

16 Bits

Core

Bit

Description

Vendor ID Value. This is a 16 bit value assigned to Intel

15:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-1

AC’97 Audio Controller Registers (D31:F5)

13.1.2

13.1.3

DID—Device Identification Register (Audio—D31:F5)

Offset:

Default Value:

Lockable:

03h–02h

2445h

Attribute:

Size:

Power Well:

16 Bits

Core

Bit

Description

15:0

Device ID Value.

PCICMD—PCI Command Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

05h–04h

0000h

Attribute:

Size:

Power Well:

R/W

16 bits

Core

PCICMD is a 16-bit control register. Refer to the PCI 2.1 specification for complete details on each

bit.

Bit

Description

15:10

Reserved. Read as 0s.

Fast Back to Back Enable (FBE). Not implemented. Hardwired to 0.

SERR# Enable (SEN). Not implemented. Hardwired to 0.

Wait Cycle Control (WCC). Not implemented. Hardwired to 0.

Parity Error Response (PER). Not implemented. Hardwired to 0.

VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.

Memory Write and Invalidate Enable (MWI). Not implemented. Hardwired to 0.

Special Cycle Enable (SCE). Not implemented. Hardwired to 0.

Bus Master Enable (BME)—R/W. Controls standard PCI bus mastering capabilities.

0 = Disable.

1 = Enable

Memory Space (MS). Hardwired to 0, AC '97 does not respond to memory accesses

IOS (I/O Space)—R/W. This bit controls access to the AC’97 Audio Controller I/O space registers.

0 = Disable (Default).

1 = Enable access to I/O space. The Native PCI Mode Base Address register should be

programmed prior to setting this bit.

13-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

13.1.4

PCISTS—PCI Device Status Register (Audio—D31:F5)

Offset:

Default Value

Lockable:

07h–06h

0280h

Attribute:

Size:

Power Well:

R/WC

16 bits

Core

PCISTA is a 16-bit status register. Refer to the PCI 2.1 specification for complete details on each

bit.

Bit

Description

Detected Parity Error (DPE). Not implemented. Hardwired to 0.

SERR# Status (SERRS). Not implemented. Hardwired to 0.

Master-Abort Status (MAS)—R/WC.

1 = Bus Master AC '97 2.1 interface function, as a master, generates a master abort.

0 = Software clears this bit by writing a 1 to the bit position.

Reserved. Will always read as 0.

Signaled Target-Abort Status (STA). Not implemented. Hardwired to 0.

DEVSEL# Timing Status (DEVT)—RO. This 2-bit field reflects the ICH2's DEVSEL# timing when

performing a positive decode.

10:9

01b = Medium timing.

Data Parity Detected (DPD). Not implemented. Hardwired to 0.

Fast Back to back Capable (FBC). Hardwired to 1. This bit indicates that the ICH2 as a target is

capable of fast back-to-back transactions.

UDF Supported. Not implemented. Hardwired to 0.

66 MHz Capable. Hardwired to 0.

Reserved. Read as 0's.

4:0

13.1.5

13.1.6

RID—Revision Identification Register (Audio—D31:F5)

Offset:

Default Value:

08h

Attribute:

Size:

8 Bits

See bit description

Lockable:

Power Well:

Core

Bit

Description

Revision ID Value—RO. Refer to the ICH2 / ICH2-M Specification Update for the value of the

Revision ID Register

7:0

PI—Programming Interface Register (Audio—D31:F5)

Offset:

Default Value:

Lockable:

09h

00h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

7:0

Programming Interface—RO.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-3

AC’97 Audio Controller Registers (D31:F5)

13.1.7

13.1.8

13.1.9

SCC—Sub Class Code Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

0Ah

01h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

Sub Class Code—RO.

7:0

01h = Audio Device

BCC—Base Class Code Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

0Bh

04h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

Base Class Code—RO.

7:0

04h = Multimedia device

HEDT—Header Type Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

0Eh

00h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

7:0

Header Type Value. Hardwired to 00h.

13-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

13.1.10 NAMBAR—Native Audio Mixer Base Address Register

(Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

10h–13h

00000001h

Attribute:

Size:

Power Well:

R/W

32 bits

Core

The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous

block of I/O space that is to be used for the Native Audio Mixer software interface. The mixer

requires 256 bytes of I/O space. Native Audio Mixer and Modem codec I/O registers are located

from 00h to 7Fh and reside in the codec. Access to these registers will be decoded by the AC '97

controller and forwarded over the AC-link to the codec. The codec will then respond with the

In the case of the split codec implementation, accesses to the different codecs are differentiated by

the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh

for the secondary codec.

For a description of these I/O registers, refer to the AC‘97 specification.

Bit

Description

31:16 Hardwired to 0s

Base Address—R/W. These bits are used in the I/O space decode of the Native Audio Mixer

interface registers. The number of upper bits that a device actually implements depends on how

much of the address space the device will respond to. For the AC ‘97 mixer, the upper 16 bits are

hardwired to 0, while bits 15:8 are programmable. This configuration yields a maximum I/O block

size of 256 bytes for this base address.

15:8

Note: This address must align to a 256-byte boundary.

Reserved. Read as 0s.

7:1

Resource Type Indicator (RTE)—RO. Hardwired to 1 indicating a request for I/O space.

13.1.11 NABMBAR—Native Audio Bus Mastering Base Address

Address Offset:

Default Value:

Lockable:

14h–17h

00000001h

Attribute:

Size:

Power Well:

R/W

32 bits

Core

The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous

block of I/O space that is to be used for the Native Mode Audio software interface.

Bit

Description

31:16

Hardwired to 0s

Base Address—R/W. These bits are used in the I/O space decode of the Native Audio Bus

Mastering interface registers. The number of upper bits that a device actually implements depends

on how much of the address space the device will respond to. For AC '97 bus mastering, the upper

16 bits are hardwired to 0, while bits 15:6 are programmable. This configuration yields a maximum

I/O block size of 64 bytes for this base address.

15:6

Note: This address must align to a 64-byte boundary.

Reserved. Read as 0s.

5:1

Resource Type Indicator (RTE)—RO. This bit is set to 1 indicating a request for I/O space.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-5

AC’97 Audio Controller Registers (D31:F5)

13.1.12 SVID—Subsystem Vendor ID Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

2Dh–2Ch

0000h

Attribute:

Size:

Power Well:

Read/Write-Once

16 bits

Core

The SVID register, in combination with the Subsystem ID register, enable the operating

environment to distinguish one audio subsystem from the other(s). This register is implemented as

write-once register. Once a value is written to it, the value can be read back. Any subsequent writes

will have no effect.

Bit

Description

15:0 Subsystem Vendor ID Value—R/Write-Once.

13.1.13 SID—Subsystem ID Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

2Fh–2Eh

0000h

Attribute:

Size:

Power Well:

Read/Write-Once

16 bits

Core

The SID register, in combination with the Subsystem Vendor ID register make it possible for the

operating environment to distinguish one audio subsystem from the other(s). This register is

implemented as write-once register. Once a value is written to it, the value can be read back. Any

subsequent writes will have no effect.

Bit

Description

15:0 Subsystem ID Value—R/Write-Once.

13.1.14 INTR_LN—Interrupt Line Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

3Ch

00h

Attribute:

Size:

Power Well:

R/W

8 bits

Core

This register indicates which PCI interrupt line is used for the AC’97 module interrupt.

Bit

Description

Interrupt Line—R/W. This data is not used by the ICH2. It is used to communicate to software the

interrupt line that the interrupt pin is connected to.

7:0

13-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

13.1.15 INTR_PN—Interrupt Pin Register (Audio—D31:F5)

Address Offset:

Default Value:

Lockable:

3Dh

02h

Attribute:

Size:

Power Well:

8 bits

Core

This register indicates which PCI interrupt pin is used for the AC '97 module interrupt. The AC '97

interrupt is internally OR’ed to the interrupt controller with the PIRQB# signal.

Bit

Description

7:3

2:0

Reserved.

AC '97 Interrupt Routing—RO. Hardwired to 010b to select PIRQB#.

13.2

AC’97 Audio I/O Space (D31:F5)

The AC’97 I/O space includes Native Audio Bus Master Registers and Native Mixer Registers.

Table 13-2 shows the register addresses for the audio mixer registers.

Table 13-2. ICH2 Audio Mixer Register Configuration

Primary

offset

Secondary

Offset

NAMBAR Exposed Registers (D31:F5)

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

80h

82h

84h

86h

88h

8Ah

8Ch

8Eh

90h

92h

94h

96h

98h

9Ah

9Ch

9Eh

A0h

A2h

A4h

A6h

A8h

AAh

Reset

Master Volume Mute

Headphone Volume Mute

Master Volume Mono Mute

Master Tone (R & L)

PC_BEEP Volume Mute

Phone Volume Mute

Mic Volume Mute

Line In Volume Mute

CD Volume Mute

Video Volume Mute

Aux Volume Mute

PCM Out Volume Mute

Record Select

Record Gain Mute

Record Gain Mic Mute

General Purpose

3D Control

AC’97 RESERVED

Powerdown Ctrl/Stat

Extended Audio

Extended Audio Ctrl/Stat

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-7

AC’97 Audio Controller Registers (D31:F5)

Table 13-2. ICH2 Audio Mixer Register Configuration (Continued)

Primary

offset

Secondary

Offset

NAMBAR Exposed Registers (D31:F5)

2Ch

2Eh

ACh

AEh

PCM Front DAC Rate

PCM Surround DAC Rate

PCM LFE DAC Rate

PCM LR ADC Rate

MIC ADC Rate

30h

B0h

32h

B2h

34h

B4h

36h

B6h

6Ch Vol: C, LFE Mute

6Ch Vol: L, R Surround Mute

Intel RESERVED

38h

B8h

3Ah:56h

BAh–F6h

58h

Vendor Reserved

Vendor ID1

7Ah

7Ch

7Eh

Vendor ID2

NOTE:

1. Registers in bold are multiplexed between audio and modem functions

2. Software should not try to access reserved registers

The Bus Master registers are located from offset + 00h to offset + 51h and reside in the AC ‘97

controller. Accesses to these registers do NOT cause the cycle to be forwarded over the AC-link to

the codec.

In the case of the split codec implementation accesses to the different codecs are differentiated by

the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh

for the secondary codec.

The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the

same global registers in the audio and modem I/O space. Therefore a read/write to these registers in

either audio or modem I/O space affects the same physical register.

Bus Mastering registers exist in I/O space and reside in the AC ‘97 controller. The three channels

(PCM in, PCM out, and Mic in) each have their own set of Bus Mastering registers. The following

“x_” in front of the register to indicate that the register applies to all three channels. The naming

prefix convention used in Table 13-3 and in the register description I/O address is as follows:

• PI = PCM in channel

• PO = PCM out channel

• MC = Mic in channel.

13-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

Table 13-3. Native Audio Bus Master Control Registers

Offset

Mnemonic

Name

Default

Access

00h

04h

05h

06h

08h

0Ah

0Bh

10h

14h

15h

16h

18h

1Ah

1Bh

20h

24h

25h

26h

28h

2Ah

2Bh

2Ch

30h

34h

PI_BDBAR

PI_CIV

PCM In Buffer Descriptor list Base Address Register

PCM In Current Index Value

00000000h

00h

R/W

PI_LVI

PCM In Last Valid Index

00h

R/W

PI_SR

PCM In Status Register

0001h

0000h

00h

PI_PICB

PI_PIV

PCM In Position In Current Buffer

PCM In Prefetched Index Value

PCM In Control Register

PI_CR

00h

R/W

PO_BDBAR

PO_CIV

PO_LVI

PO_SR

PO_PICB

PO_PIV

PO_CR

PCM Out Buffer Descriptor list Base Address Register

PCM Out Current Index Value

PCM Out Last Valid Index

00000000h

00h

R/W

PCM Out Status Register

0001h

0000h

00h

PCM Out Position In Current Buffer

PCM Out Prefetched Index Value

PCM Out Control Register

00h

R/W

MC_BDBAR Mic. In Buffer Descriptor list Base Address Register

00000000h

00h

PM_CIV

MC_LVI

Mic. In Current Index Value

Mic. In Last Valid Index

Mic. In Status Register

Mic In Position In Current Buffer

Mic. In Prefetched Index Value

Mic. In Control Register

Global Control

00h

R/W

MC_SR

0001h

0000h

00h

MC_PICB

MC_PIV

MC_CR

00h

R/W

GLOB_CNT

GLOB_STA

ACC_SEMA

00000000h

00h

Global Status

Codec Write Semaphore Register

R/W

13.2.1

x_BDBAR—Buffer Descriptor Base Address Register

I/O Address:

NABMBAR + 00h (PIBDBAR), Attribute:

NABMBAR + 10h (POBDBAR),

R/W (DWord access only)

NABMBAR + 20h (MCBDBAR)

Default Value:

Lockable:

00000000h

Size:

Power Well:

32 bits

Core

This register can be accessed only as a DWord (32 bits).

Bit

Description

Buffer Descriptor Base Address[31:3]—R/W. These bits represent address bits 31:3. The data

should be aligned on 8 byte boundaries. Each buffer descriptor is 8 bytes long and the list can

contain a maximum of 32 entries.

31:3

2:0

Hardwired to 0.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-9

AC’97 Audio Controller Registers (D31:F5)

13.2.2

x_CIV—Current Index Value Register

I/O Address:

NABMBAR + 04h (PICIV),

Attribute:

NABMBAR + 14h (POCIV),

NABMBAR + 24h (MCCIV)

00h

Default Value:

Lockable:

Size:

Power Well:

8 bits

Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single

32 bit read from address offset 04h. Software can also read this register individually by doing a

single 8 bit read to offset 04h.

Bit

Description

7:5

Hardwired to 0

Current Index Value[4:0]—RO. These bits represent which buffer descriptor within the list of 32

descriptors is currently being processed. As each descriptor is processed, this value is

incremented. The value rolls over after it reaches 31.

4:0

13.2.3

x_LVI—Last Valid Index Register

I/O Address:

NABMBAR + 05h (PILVI),

NABMBAR + 15h (POLVI),

Attribute:

R/W

NABMBAR + 25h (MCLVI)

Default Value:

Lockable:

00h

Size:

Power Well:

8 bits

Core

Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single

32 bit read from address offset 04h. Software can also read this register individually by doing a

single 8 bit read to offset 05h.

Bit

Description

7:5

Hardwired to 0.

Last Valid Index[4:0]—R/W. This value represents the last valid descriptor in the list. This value is

updated by the software each time it prepares a new buffer and adds it to the list.

4:0

13-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

13.2.4

x_SR—Status Register

I/O Address:

NABMBAR + 06h (PISR),

Attribute:

R/WC, RO (Word Access only)

NABMBAR + 16h (POSR),

NABMBAR + 26h (MCSR)

0001h

Default Value:

Lockable:

Size:

Power Well:

16 bits

Core

This register can be accessed only as a Word (16 bits).

Bit

Description

15:5

Reserved.

FIFO error (FIFOE)—R/WC.

1 = FIFO error occurs.

0 = Cleared by writing a 1 to this bit position.

PISR Register: FIFO error indicates a FIFO overrun. The FIFO pointers do not increment, the

incoming data is not written into the FIFO, thus is lost.

POSR Register: FIFO error indicates a FIFO underrun. The sample transmitted in this case should

be the last valid sample.

The ICH2 will set the FIFOE bit if the under-run or overrun occurs when there are more valid buffers

to process.

Buffer Completion Interrupt Status (BCIS)—R/WC.

1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt

on Completion (IOC) bit is set in the command byte of the buffer descriptor. It remains active

until cleared by software.

0 = Cleared by writing a 1 to this bit position.

Last Valid Buffer Completion Interrupt (LVBCI)—R/WC.

1 = Last valid buffer has been processed. It remains active until cleared by software. This bit

indicates the occurrence of the event signified by the last valid buffer being processed. Thus,

this is an event status bit that can be cleared by software once this event has been

recognized. This event will cause an interrupt if the enable bit in the Control Register is set.

The interrupt is cleared when the software clears this bit.

In the case of Transmits (PCM out, Modem out) this bit is set, after the last valid buffer has

been fetched (not after transmitting it). While in the case of Receives, this bit is set after the

data for the last buffer has been written to memory.

0 = Cleared by writing a 1 to this bit position.

Current Equals Last Valid (CELV)—RO.

1 = Current Index is equal to the value in the Last Valid Index Register, and the buffer pointed to by

the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is

very similar to bit 2, except this bit reflects the state rather than the event. This bit reflects the

state of the controller, and remains set until the controller exits this state.

0 = Cleared by hardware when controller exists state (i.e., until a new value is written to the LVI

DMA Controller Halted (DCH)—RO.

1 = Halted. This could happen because of the Start/Stop bit being cleared, or it could happen once

the controller has processed the last valid buffer (in which case it will set bit 1 and halt).

Software can read the above 3 registers simultaneously by scheduling a single 32 bit read from

address offset 04h. Software can also read this individual register by performing a 16 bit read from

06h.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-11

AC’97 Audio Controller Registers (D31:F5)

13.2.5

x_PICB—Position In Current Buffer Register

I/O Address:

NABMBAR + 08h (PIPICB),

NABMBAR + 18h (POPICB),

NABMBAR + 28h (MCPICB)

0000h

Attribute:

RO (Word access only)

Default Value:

Lockable:

Size:

Power Well:

16 bits

Core

This register can be accessed only as a Word (16 bits).

Bit

Description

Position In Current Buffer[15:0]—RO. These bits represent the number of DWords remaining to

be processed in the current buffer; the number of samples not yet read from memory (in the case of

reads from memory) or not yet written to memory (in the case of writes to memory), irrespective of

the number of samples that have been transmitted/received across AC-link.

15:0

13.2.6

x_PIV—Prefetched Index Value Register

I/O Address:

NABMBAR + 0Ah (PIPIV),

Attribute:

NABMBAR + 1Ah (POPIV),

NABMBAR + 2Ah (MCPIV)

00h

Default Value:

Lockable:

Size:

Power Well:

8 bits

Core

Bit

Description

7:5

4:0

Hardwired to 0.

Prefetched Index Value[4:0]—RO. These bits represent which buffer descriptor in the list has

been prefetched. The bits in this register are also modulo 32 and roll over after they reach 31.

13-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

13.2.7

x_CR—Control Register

I/O Address:

NABMBAR + 0Bh (PICR),

Attribute:

R/W

NABMBAR + 1Bh (POCR),

NABMBAR + 2Bh (MCCR)

00h

Default Value:

Lockable:

Size:

Power Well:

8 bits

Core

Bit

Description

7:5

Reserved.

Interrupt On Completion Enable (IOCE)—R/W. This bit controls whether or not an interrupt

occurs when a buffer completes with the IOC bit set in its descriptor.

0 = Disable. Interrupt will not occur.

1 = Enable.

FIFO Error Interrupt Enable (FEIE)—R/W. This bit controls whether the occurrence of a FIFO

error will cause an interrupt or not.

0 = Disable. Bit 4 in the Status Register will be set; however, the interrupt will not occur.

1 = Enable. Interrupt will occur.

Last Valid Buffer Interrupt Enable (LVBIE)—R/W. This bit controls whether the completion of the

last valid buffer will cause an interrupt or not.

0 = Disable. Bit 2 in the Status register will still be set; however, the interrupt will not occur.

1 = Enable.

Reset Registers (RR)—R/W (special).

1 = Contents of all Bus master related registers to be reset, except the interrupt enable bits (bit

4,3,2 of this register). Software needs to set this bit but need not clear it since the bit is self

clearing. This bit must be set only when the Run/Pause bit is cleared. Setting it when the Run

bit is set will cause undefined consequences.

0 = Removes reset condition.

Run/Pause Bus master (RPBM)—R/W.

0 = Pause bus master operation. This results in all state information being retained (i.e., master

mode operation can be stopped and then resumed).

1 = Run. Bus master operation starts.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-13

AC’97 Audio Controller Registers (D31:F5)

13.2.8

GLOB_CNT—Global Control Register

I/O Address:

Default Value:

Lockable:

NABMBAR + 2Ch

00000000h

Attribute:

Size:

Power Well:

R/W (DWord access only)

32 bits

Core

This register can be accessed only as a DWord (32 bits).

Bit

Description

31:22

Reserved.

PCM 4/6 Enable—R/W. Configures PCM Output for 2, 4 or 6 channel mode.

00 = 2-channel mode (default)

01 = 4-channel mode

10 = 6-channel mode

11 = Reserved

21:20

19:6

Reserved.

Secondary Resume Interrupt Enable—R/W.

0 = Disable.

1 = Enable an interrupt to occur when the secondary codec causes a resume event on the

AC-link.

Primary Resume Interrupt Enable—R/W.

0 = Disable.

1 = Enable an interrupt to occur when the primary codec causes a resume event on the AC-link.

ACLINK Shut Off—R/W.

0 = Normal operation.

1 = Drive all AC’97 outputs low and turn off all AC’97 input buffer enables

AC’97 Warm Reset—R/W (special).

0 = Normal operation.

1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken

a suspended codec without clearing its internal registers. If software attempts to perform a

warm reset while bit_clk is running, the write will be ignored and the bit will not change. This bit

is self-clearing (it remains set until the reset completes and bit_clk is seen on the ACLink, after

which it clears itself).

AC ‘97 Cold Reset#—R/W.

0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry. All data in

the controller and the codec will be lost. Software needs to clear this bit no sooner than the

minimum number of ms have elapsed.

1 = This bit defaults to 0; thus, after reset, the driver needs to set this bit to a 1. The value of this

bit is retained after suspends; thus, if this bit is set to a 1 prior to suspending, a cold reset is not

generated automatically upon resuming.

Note: This bit is in the Resume well, not in the Core well.

GPI Interrupt Enable (GIE)—R/W. This bit controls whether the change in status of any GPI

causes an interrupt.

0 = Bit 0 of the Global Status Register is set, but no interrupt is generated.

1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.

13-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Audio Controller Registers (D31:F5)

13.2.9

GLOB_STA—Global Status Register

I/O Address:

Default Value:

Lockable:

NABMBAR + 30h

00300000h

Attribute:

Size:

Power Well: Core

RO, R/W, R/WC (DWord access only)

32 bits

This register can be accessed only as a DWord (32 bits).

Bit

Description

31:22 Reserved.

6 Channel Capability (6CH_CAP)—RO. Hardwired to 1.

0 = The AC ‘97 Controller does not support 6-channel PCM Audio output.

1 = The AC ‘97 Controller supports 6-channel PCM Audio output.

4 Channel Capability (4CH_CAP)—RO. Hardwired to 1.

0 = The AC ‘97 Controller does not support 4-channel PCM Audio output.

1 = The AC ‘97 Controller supports 4-channel PCM Audio output.

19:18 Reserved.

MD3—R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains

context across power states (except G3). The bit has no hardware function. It is used by software in

conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state.

AD3—R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains

context across power states (except G3). The bit has no hardware function. It is used by software in

conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state.

Read Completion Status (RCS)—R/WC. This bit indicates the status of codec read completions.

0 = A codec read completes normally.

1 = A codec read results in a time-out. The bit remains set until being cleared by software writing a

1 to the bit location.

Bit 3 of slot 12—RO. Display bit 3 of the most recent slot 12.

Bit 2 of slot 12—RO. Display bit 2 of the most recent slot 12.

Bit 1 of slot 12—RO. Display bit 1 of the most recent slot 12.

Secondary Resume Interrupt (SRI)—R/WC. This bit indicates that a resume event occurred on

AC_SDIN[1].

1 = Resume event occurred

0 = Cleared by writing a 1 to this bit position.

Primary Resume Interrupt (PRI)—R/WC. This bit indicates that a resume event occurred on

AC_SDIN[0].

1 = Resume event occurred

0 = Cleared by writing a 1 to this bit position.

Secondary Codec Ready (SCR)—RO. Reflects the state of the codec ready bit in AC_SDIN[1].

Bus masters ignore the condition of the codec ready bits, so software must check this bit before

starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.

0 = Not Ready.

1 = Ready.

Primary Codec Ready (PCR)—RO. Reflects the state of the codec ready bit in AC_SDIN [0]. Bus

masters ignore the condition of the codec ready bits, so software must check this bit before starting

the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.

0 = Not Ready.

1 = Ready.

Mic In Interrupt (MINT)—RO. This bit indicates that one of the Mic in channel interrupts occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

13-15

AC’97 Audio Controller Registers (D31:F5)

Bit

Description

PCM Out Interrupt (POINT)—RO. This bit indicates that one of the PCM out channel interrupts

occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

PCM In Interrupt (PIINT)—RO. This bit indicates that one of the PCM in channel interrupts

occurred.

1 = Interrupt occurred.

4:3

0 = 0 = When the specific interrupt is cleared, this bit will be cleared.

Reserved

Modem Out Interrupt (MOINT)—RO. This bit indicates that one of the modem out channel

interrupts occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

Modem In Interrupt (MIINT)—RO. This bit indicates that one of the modem in channel interrupts

occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

GPI Status Change Interrupt (GSCI)—RWC. This bit reflects the state of bit 0 in slot 12, and is set

whenever bit 0 of slot 12 is set. This happens when the value of any of the GPIOs currently defined

as inputs changes.

1 = Input changed.

0 = Cleared by writing a 1 to this bit position.

13.2.10 CAS—Codec Access Semaphore Register

I/O Address:

Default Value:

Lockable:

NABMBAR + 34h

00h

Attribute:

Size:

Power Well:

R/W

8 bits

Core

Bit

Description

7:1

Reserved.

Codec Access Semaphore (CAS)—R/W (special). This bit is read by software to check whether a

codec access is currently in progress.

0 = No access in progress.

1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform

an I/O access. Once the access is completed, hardware automatically clears this bit.

13-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Modem Controller Registers (D31:F6)

AC’97 Modem Controller Registers

(D31:F6)

14.1

AC’97 Modem PCI Configuration Space (D31:F6)

Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).

Table 14-1. PCI Configuration Map (Modem—D31:F6)

Offset

Mnemonic

Vendor Identification

Default

Access

00h–01h

02h–03h

04h–05h

06h–07h

08h

VID

DID

8086

2446h

0000

Device Identification

PCI Command

PCI Device Status

Revision Identification

Programming Interface

Sub Class Code

Base Class Code

Header Type

PCICMD

PCISTA

RID

R/W

R/WC

0280h

See Note

09h

0Ah

SCC

BCC

HEDT

—

03h

0Bh

07h

0Eh

0Fh

Reserved

—

10h–13h

14h–17h

18h–1Bh

1Ch–2Bh

2Ch–2Dh

2Eh–2Fh

30h–3Bh

3Ch

MMBAR

MBAR

—

Modem Mixer Base Address

Modem Base Address

Reserved

00000001h

—

R/W

—

Reserved

—

SVID

SID

Subsystem Vendor ID

Subsystem ID

0000h

—

Write-Once

—

Reserved

INTR_LN

INT_PN

—

Interrupt Line

00h

3Dh

Interrupt Pin

02h

3Eh–FFh

Reserved

—

NOTE: Refer to the Specification Update for the value of the Revision ID Register

14.1.1

VID—Vendor Identification Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

01h–00h

8086

Attribute:

Size:

Power Well:

16 Bits

Core

Bit

Description

15:0

Vendor ID Value.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

14-1

AC’97 Modem Controller Registers (D31:F6)

14.1.2

14.1.3

DID—Device Identification Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

03h–02h

2446h

Attribute:

Size:

Power Well:

16 Bits

Core

Bit

Description

15:0

Device ID Value.

PCICMD—PCI Command Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

05h–04h

0000h

Attribute:

Size:

Power Well:

R/W

16 bits

Core

PCICMD is a 16-bit control register. Refer to the PCI 2.1 specification for complete details on each

bit.

Bit

Description

15:10

Reserved. Read 0.

Fast Back to Back Enable (FBE). Not implemented. Hardwired to 0.

SERR# Enable (SEN). Not implemented. Hardwired to 0.

Wait Cycle Control (WCC). Not implemented. Hardwired to 0.

Parity Error Response (PER). Not implemented. Hardwired to 0.

VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.

Memory Write and Invalidate Enable (MWI). Not implemented. Hardwired to 0.

Special Cycle Enable (SCE). Not implemented. Hardwired to 0.

Bus Master Enable (BME)—R/W. Controls standard PCI bus mastering capabilities.

0 = Disable.

1 = Enable

Memory Space (MS). Hardwired to 0, AC ‘97 does not respond to memory accesses.

I/O Space (IOS)—R/W. This bit controls access to the I/O space registers.

0 = Disable access. (default = 0).

1 = Enable access to I/O space. The Native PCI Mode Base Address register should be

programmed prior to setting this bit.

14-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Modem Controller Registers (D31:F6)

14.1.4

PCISTA—Device Status Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

07h–06h

0280h

Attribute:

Size:

Power Well:

R/WC

16 bits

Core

PCISTA is a 16-bit status register. Refer to the PCI 2.1 specification for complete details on each

bit.

Bit

Description

Detected Parity Error (DPE)—RO. Not implemented. Hardwired to 0.

SERR# Status (SERRS)—RO. Not implemented. Hardwired to 0.

Master-Abort Status (MAS)—R/WC.

1 = Bus Master AC ‘97 interface function, as a master, generates a master abort.

0 = Software clears this bit by writing a 1 to the bit position.

Reserved. Read as “0”.

Signaled Target-Abort Status (STA)—RO. Not implemented. Hardwired to 0.

DEVSEL# Timing Status (DEVT)—RO. This 2-bit field reflects the ICH2's DEVSEL# timing

parameter. These read only bits indicate the ICH2's DEVSEL# timing when performing a positive

decode.

10:9

Data Parity Detected (DPD)—RO. Not implemented. Hardwired to 0.

Fast Back to back Capable (FBC)—RO. Hardwired to 1. This bit indicates that the ICH2 as a target is

capable of fast back-to-back transactions.

UDF Supported—RO. Not implemented. Hardwired to 0.

66 MHz Capable—RO. Hardwired to 0.

Reserved. Read as 0s.

4:0

14.1.5

14.1.6

RID—Revision Identification Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

08h

Attribute:

Size:

Power Well:

8 Bits

Core

See bit description

Bit

Description

Revision ID Value—RO. Refer to the Specification Update for the value of the Revision ID

7:0

PI—Programming Interface Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

09h

00h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

7:0

Programming Interface Value—RO.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

14-3

AC’97 Modem Controller Registers (D31:F6)

14.1.7

14.1.8

14.1.9

SCC—Sub Class Code Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

0Ah

03h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

Sub Class Code Value—RO.

7:0

03h = Generic Modem.

BCC—Base Class Code Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

0Bh

07h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

Base Class Code Value—RO.

7:0

07h = Simple Communications Controller.

HEDT—Header Type Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

0Eh

00h

Attribute:

Size:

Power Well:

8 bits

Core

Bit

Description

7:0

Header Value—RO.

14.1.10 MMBAR—Modem Mixer Base Address Register

(Modem—D31:F6)

Address Offset:

Default Value:

10h–13h

00000001h

Attribute:

Size:

R/W

32 bits

The Native PCI Mode Modem uses PCI Base Address register #1 to request a contiguous block of

I/O space that is to be used for the Modem Mixer software interface. The mixer requires 256 bytes

of I/O space. All accesses to the mixer registers are forwarded over the AC-link to the codec where

the registers reside.

In the case of the split codec implementation accesses to the different codecs are differentiated by

the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh

for the secondary codec.

14-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Modem Controller Registers (D31:F6)

Bit

Description

31:16 Hardwired to 0s

Base Address—R/W. These bits are used in the I/O space decode of the Modem interface

registers. The number of upper bits that a device actually implements depends on how much of the

address space the device will respond to. For the AC ‘97 Modem, the upper 16 bits are hardwired to

0, while bits 15:8 are programmable. This configuration yields a maximum I/O block size of

256 bytes for this base address.

15:8

Note: This address must align to a 256-byte boundary.

Reserved. Read as 0

7:1

Resource Type Indicator (RTE)—RO. This bit is set to one, indicating a request for I/O space.

14.1.11 MBAR—Modem Base Address Register (Modem—D31:F6)

Address Offset:

Default Value:

14h–17h

00000001h

Attribute:

Size:

R/W

32 bits

The Modem function uses PCI Base Address register #1 to request a contiguous block of I/O space

that is to be used for the Modem software interface. The Modem Bus Mastering register space

requires 128 bytes of I/O space. All Modem registers reside in the controller, therefore cycles are

NOT forwarded over the AC-link to the codec.

Bit

Description

31:16 Hardwired to 0s

Base Address—R/W. These bits are used in the I/O space decode of the Modem interface

registers. The number of upper bits that a device actually implements depends on how much of the

address space the device will respond to. For the AC ‘97 Modem, the upper 16 bits are hardwired to

0, while bits 15:7 are programmable. This configuration yields a maximum I/O block size of

128 bytes for this base address.

15:7

Note: This address must align to a 128-byte boundary.

Reserved. Read as 0

6:1

Resource Type Indicator (RTE)—RO. This bit is set to one, indicating a request for I/O space.

14.1.12 SVID—Subsystem Vendor ID (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

2Dh–2Ch

0000h

Attribute:

Size:

Power Well:

Write-Once

16 bits

Core

The SVID register, in combination with the Subsystem ID register, enable the operating

environment to distinguish one audio subsystem from the other(s). This register is implemented as

write-once register. Once a value is written to the register, the value can be read back. Any

subsequent writes will have no effect.

Bit

Description

Subsystem Vendor ID Value—Read/Write-Once.

15:0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

14-5

AC’97 Modem Controller Registers (D31:F6)

14.1.13 SID—Subsystem ID (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

2Fh–2Eh

0000h

Attribute:

Size:

Power Well:

Write-Once

16 bits

Core

The SID register, in combination with the Subsystem Vendor ID register, makes it possible for the

operating environment to distinguish one audio subsystem from another. This register is

implemented as a write-once register. Once a value is written to the register, the value can be read

back. Any subsequent writes will have no effect.

Bit

Description

15:0

Subsystem ID Value—Read/Write-Once.

14.1.14 INTR_LN—Interrupt Line Register (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

3Ch

00h

Attribute:

Size:

Power Well:

R/W

8 bits

Core

This register indicates which PCI interrupt line is used for the AC’97 module interrupt.

Bit

Description

Interrupt Line—R/W. This data is not used by the ICH2. It is used to communicate to software the

interrupt line that the interrupt pin is connected to.

7:0

14.1.15 INT_PIN—Interrupt Pin (Modem—D31:F6)

Address Offset:

Default Value:

Lockable:

3Dh

02h

Attribute:

Size:

Power Well:

8 bits

Core

This register indicates which PCI interrupt pin is used for the AC ‘97 modem interrupt. The AC ‘97

interrupt is internally ORed to the interrupt controller with the PIRQB# signal.

Bit

Description

7:3

2:0

Reserved.

AC ‘97 Interrupt Routing—RO. Hardwired to 010b to select PIRQB#.

14-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Modem Controller Registers (D31:F6)

14.2

AC’97 Modem I/O Space (D31:F6)

In the case of the split codec implementation accesses to the modem mixer registers in different

codecs are differentiated by the controller by using address offsets 00h–7Fh for the primary codec

and address offsets 80h–FEh for the secondary codec. Table 14-2 shows the register addresses for

the modem mixer registers.

Table 14-2. ICH2 Modem Mixer Register Configuration

MMBAR Exposed Registers (D31:F6)

Name

Primary

Secondary

00h:38h

3Ch

3Eh

40h

80h:B8h

BCh

BEh

C0h

C2h

C4h

C6h

C8h

CAh

CCh

CEh

D0h

D2h

D4h

D6h

D8h

FAh

Intel RESERVED

Extended Modem ID

Extended Modem Status/Control

Line 1 DAC/ADC Rate

42h

Line 2 DAC/ADC Rate

44h

Handset DAC/ADC Rate

46h

Line 1 DAC/ADC Level Mute

48h

Line 2 DAC/ADC Level Mute

4Ah

4Ch

4Eh

50h

Handset DAC/ADC Level Mute

GPIO Pin Configuration

GPIO Polarity/Type

GPIO Pin Sticky

52h

GPIO Pin Wake Up

GPIO Pin Status

54h

56h

Misc. Modem AFE Stat/Ctrl

Vendor Reserved

Vendor ID1

58h

7Ah

7Ch

FCh

FEh

7Eh

Vendor ID2

NOTE:

1. Registers in bold are multiplexed between audio and modem functions

2. Registers in italics are for functions not supported by the ICH2

3. Software should not try to access reserved registers

4. The ICH2 supports a modem codec as either primary or secondary, but does not support two modem codecs.

The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the

same global registers in the audio and modem I/O space. Therefore a read/write to these registers in

either audio or modem I/O space affects the same physical register.

These registers exist in I/O space and reside in the AC ‘97 controller. The two channels, Modem in

and Modem out, each have their own set of Bus Mastering registers. The following register

descriptions apply to both channels. The naming prefix convention used is as follows:

• MI = Modem in channel

• MO = Modem out channel

82801BA ICH2 and 82801BAM ICH2-M Datasheet

14-7

AC’97 Modem Controller Registers (D31:F6)

Table 14-3. Modem Registers

Offset

Mnemonic

Name

Default

Access

Modem In Buffer Descriptor List Base Address

00h

MI_BDBAR

00000000h

R/W

04h

05h

06h

08h

0Ah

0Bh

MI_CIV

MI_LVI

MI_SR

Modem In Current Index Value Register

Modem In Last Valid Index Register

Modem In Status Register

00h

R/W

0001h

00h

MI_PICB

MI_PIV

MI_CR

Modem In Position In Current Buffer Register

Modem In Prefetch Index Value Register

Modem In Control Register

00h

R/W

00h

Modem Out Buffer Descriptor List Base Address

10h

MO_BDBAR

00000000h

R/W

14h

15h

16h

18h

1Ah

1Bh

3Ch

40h

44h

MO_CIV

MO_LVI

Modem Out Current Index Value Register

Modem Out Last Valid Register

Modem Out Status Register

Modem In Position In Current Buffer Register

Modem Out Prefetched Index Register

Modem Out Control Register

Global Control

00h

R/W

MO_SR

0001h

00h

MI_PICB

MO_PIV

00h

MO_CR

00h

R/W

GLOB_CNT

GLOB_STA

ACC_SEMA

00000000h

00h

Global Status

Codec Write Semaphore Register

R/W

NOTE:

1. MI = Modem in channel; MO = Modem out channel

14.2.1

x_BDBAR—Buffer Descriptor List Base Address Register

I/O Address:

MBAR + 00h (MIBDBAR),

MBAR + 10h (MOBDBAR)

00000000h

Attribute:

R/W (DWord access only)

Default Value:

Lockable:

Size:

Power Well:

32bits

Core

This register can be accessed only as a DWord (32 bits).

Bit

Description

Buffer Descriptor List Base Address[31:3]—R/W. These bits represent address bits 31:3. The

entries should be aligned on 8 byte boundaries.

31:3

2:0

Hardwired to 0.

14-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Modem Controller Registers (D31:F6)

14.2.2

x_CIV—Current Index Value Register

I/O Address:

MBAR + 04h (MICIV),

Attribute:

MBAR + 14h (MOCIV),

00h

Default Value:

Lockable:

Size:

Power Well:

8bits

Core

Bit

Description

7:5

4:0

Hardwired to 0.

Current Index Value [4:0]—RO. These bits represent which buffer descriptor within the list of 16

descriptors is being processed currently. As each descriptor is processed, this value is

incremented.

14.2.3

x_LVI—Last Valid Index Register

I/O Address:

MBAR + 05h (MILVI),

MBAR + 15h (MOLVI)

00h

Attribute:

R/W

Default Value:

Power Well:

Core

Bit

Description

7:5

4:0

Hardwired to 0

Last Valid Index [4:0]—R/W. These bits indicate the last valid descriptor in the list. This value is

updated by software as it prepares new buffers and adds to the list.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

14-9

AC’97 Modem Controller Registers (D31:F6)

14.2.4

x_SR—Status Register

I/O Address:

MBAR + 06h (MISR),

Attribute:

R/WC (Word access only)

MBAR + 16h (MOSR)

0001h

Default Value:

Lockable:

Size:

Power Well:

16 bits

Core

This register can be accessed only as a Word (16 bits).

Bit

Description

15:5

Reserved.

FIFO error (FIFOE)—R/WC.

1 = FIFO error occurs.

0 = Cleared by writing a 1 to this bit position.

Modem in: FIFO error indicates a FIFO overrun. The FIFO pointers do not increment, the incoming

data is not written into the FIFO, thereby being lost.

Modem out: FIFO error indicates a FIFO underrun. The sample transmitted in this case should be

the last valid sample.

The ICH2 sets the FIFOE bit if the under-run or overrun occurs when there are more valid buffers to

process.

Buffer Completion Interrupt Status (BCIS)—R/WC.

1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt

on Completion (IOC) bit is set in the command byte of the buffer descriptor. Remains active

until software clears bit.

0 = Cleared by writing a 1 to this bit position.

Last Valid Buffer Completion Interrupt (LVBCI)—R/WC.

1 = Set by hardware when last valid buffer has been processed. It remains active until cleared by

software. This bit indicates the occurrence of the event signified by the last valid buffer being

processed. Thus, this is an event status bit that can be cleared by software once this event

has been recognized. This event will cause an interrupt if the enable bit in the Control Register

is set. The interrupt is cleared when the software clears this bit.

In the case of transmits (PCM out, Modem out) this bit is set, after the last valid buffer has

been fetched (not after transmitting it) While in the case of Receives, this bit is set after the

data for the last buffer has been written to memory.

0 = Cleared by writing a 1 to this bit position

Current Equals Last Valid (CELV)—RO.

1 = Current Index is equal to the value in the Last Valid Index Register, AND the buffer pointed to

by the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is

very similar to bit 2, except, this bit reflects the state rather than the event. This bit reflects the

state of the controller, and remains set until the controller exits this state.

0 = Hardware clears when controller exists state (i.e., until a new value is written to the LVI

DMA Controller Halted (DCH)—RO.

1 = DMA controller is halted. This could happen because of the Start/Stop bit being cleared, or it

could happen once the controller has processed the last valid buffer (in which case it will set

bit 1 and halt).

14-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Modem Controller Registers (D31:F6)

14.2.5

x_PICB—Position In Current Buffer Register

I/O Address:

MBAR + 08h (MIPICB),

Attribute:

RO (Word access only)

MBAR + 18h (MOPICB),

0000h

Default Value:

Lockable:

Size:

Power Well:

16 bits

Core

This register can be accessed only as a Word (16 bits).

Bit

Description

Position In Current Buffer[15:0]—RO. These bits represent the number of DWords left to be

processed in the current buffer.

15:0

14.2.6

x_PIV—Prefetch Index Value Register

I/O Address:

MBAR + 0Ah (MIPIV),

MBAR + 1Ah (MOPIV)

Attribute:

Default Value:

Lockable:

00h

Size:

Power Well:

8 bits

Core

Bit

Description

7:5

4:0

Hardwired to 0

Prefetched Index value [4:0]—RO. These bits represent which buffer descriptor in the list has

been prefetched.

14.2.7

x_CR—Control Register

I/O Address:

MBAR + 0Bh (MICR),

Attribute:

R/W

MBAR + 1Bh (MOCR)

00h

Default Value:

Lockable:

Size:

Power Well:

8 bits

Core

Bit

Description

7:5

Reserved.

Interrupt On Completion Enable (IOCE)—R/W. This bit controls whether or not an interrupt

occurs when a buffer completes with the IOC bit set in its descriptor.

0 = Disable.

1 = Enable.

FIFO Error Interrupt Enable (FEIE)—R/W. This bit controls whether the occurrence of a FIFO

error will cause an interrupt or not.

0 = Disable. Bit 4 in the Status Register will be set, but the interrupt will not occur.

1 = Enable. Interrupt will occur

Last Valid Buffer Interrupt Enable (LVBIE)—R/W. This bit controls whether the completion of the

last valid buffer will cause an interrupt or not.

0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur.

1 = Enable.

Reset Registers (RR)—R/W (special).

1 = Contents of all registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register).

Software needs to set this bit. It must be set only when the Run/Pause bit is cleared. Setting it

when the Run bit is set will cause undefined consequences. This bit is self-clearing (software

does not need to clear it).

0 = Removes reset condition.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

14-11

AC’97 Modem Controller Registers (D31:F6)

Bit

Description

Run/Pause Bus master (RPBM)—R/W.

0 = Pause bus master operation. This results in all state information being retained (i.e., master

mode operation can be stopped and then resumed).

1 = Run. Bus master operation starts.

14.2.8

GLOB_CNT—Global Control Register

I/O Address:

Default Value:

Lockable:

MBAR + 3Ch

00000000h

Attribute:

Size:

Power Well:

R/W (DWord access only)

32 bits

Core

This register can be accessed only as a DWord (32 bits).

Bit

Description

31:6

Reserved.

Secondary Resume Interrupt Enable—R/W.

0 = Disable.

1 = Enable an interrupt to occur when the secondary codec causes a resume event on the

AC-link.

Primary Resume Interrupt Enable—R/W.

0 = Disable.

1 = Enable an interrupt to occur when the primary codec causes a resume event on the AC-link.

ACLINK Shut Off—R/W.

0 = Normal operation.

1 = Disable the AC-link signals (drive all AC’97 outputs low and turn off all AC’97 input buffer

enables)

AC’97 Warm Reset—R/W (special).

1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken

a suspended codec without clearing its internal registers. If software attempts to perform a

warm reset while BIT_CLK is running, the write will be ignored and the bit will not be changed.

A warm reset can only occur in the absence of BIT_CLK.

0 = This bit is self-clearing (it clears itself after the reset has occurred and BIT_CLK has started).

AC‘97 Cold Reset#—R/W (special).

0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC‘97 circuitry. All data in the

codec will be lost. Software needs to clear this bit no sooner than after 1usec has elapsed.

This bit reflects the state of the AC_RST# pin. The ICH2 clears this bit to “0” upon entering

S3/S4/S5 sleep states and PCIRST#.

GPI Interrupt Enable (GIE)—R/W. This bit controls whether the change in status of any GPI

causes an interrupt.

0 = Bit 0 of the Global Status Register is set, but an interrupt is not generated.

1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.

14-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

AC’97 Modem Controller Registers (D31:F6)

14.2.9

GLOB_STA—Global Status Register

I/O Address:

Default Value:

Lockable:

MBAR + 40h

00300000h

Attribute:

Size:

Power Well:

RO, R/W, R/WC (DWord access only)

32 bits

Core

This register can be accessed only as a DWord (32 bits).

Bit

Description

31:22 Reserved.

6 Channel Capability (6CH_CAP)—RO. Hardwired to 1.

0 = The AC ‘97 Controller does not support 6-channel PCM Audio output.

1 = The AC ‘97 Controller supports 6-channel PCM Audio output.

4 Channel Capability (4CH_CAP)—RO. Hardwired to 1.

0 = The AC ‘97 Controller does not support 4-channel PCM Audio output.

1 = The AC ‘97 Controller supports 4-channel PCM Audio output.

19:18 Reserved.

MD3—R/W. Power down semaphore for modem. This bit exists in the suspend well and maintains

context across power states (except G3). The bit has no hardware function. It is used by software in

conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state.

AD3—R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains

context across power states (except G3). The bit has no hardware function. It is used by software in

conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state.

Read Completion Status (RCS)—R/W. This bit indicates the status of codec read completions.

0 = A codec read completes normally.

1 = A codec read results in a time-out. The bit remains set until being cleared by software.

Bit 3 of slot 12—RO. Display bit 3 of the most recent slot 12

Bit 2 of slot 12—RO. Display bit 2 of the most recent slot 12

Bit 1 of slot 12—RO. Display bit 1 of the most recent slot 12

Secondary Resume Interrupt (SRI)—R/WC. This bit indicates that a resume event occurred on

AC_SDIN[1].

1 = Resume event occurred

0 = Cleared by writing a 1 to this bit position.

Primary Resume Interrupt (PRI)—R/WC. This bit indicates that a resume event occurred on

AC_SDIN[0].

1 = Resume event occurred

0 = Cleared by writing a 1 to this bit position.

Secondary Codec Ready (SCR)—RO. Reflects the state of the codec ready bit in AC_SDIN[1].

Bus masters ignore the condition of the codec ready bits, so software must check this bit before

starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.

0 = Not Ready.

1 = Ready.

Primary Codec Ready (PCR)—RO. Reflects the state of the codec ready bit in AC_SDIN [0]. Bus

masters ignore the condition of the codec ready bits, so software must check this bit before starting

the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.

0 = Not Ready.

1 = Ready.

Mic In Interrupt (MINT)—RO. This bit indicates that one of the Mic in channel interrupts occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

14-13

AC’97 Modem Controller Registers (D31:F6)

Bit

Description

PCM Out Interrupt (POINT)—RO. This bit indicates that one of the PCM out channel interrupts

occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

PCM In Interrupt (PIINT)—RO. This bit indicates that one of the PCM in channel interrupts

occurred.

1 = Interrupt occurred.

4:3

0 = 0 = When the specific interrupt is cleared, this bit will be cleared.

Reserved

Modem Out Interrupt (MOINT)—RO. This bit indicates that one of the modem out channel

interrupts occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

Modem In Interrupt (MIINT)—RO. This bit indicates that one of the modem in channel interrupts

occurred.

1 = Interrupt occurred.

0 = When the specific interrupt is cleared, this bit will be cleared.

GPI Status Change Interrupt (GSCI)—RWC. This bit reflects the state of bit 0 in slot 12, and is set

when bit 0 of slot 12 is set. This happens when the value of any of the GPIOs currently defined as

inputs changes.

1 = Input changed.

0 = Cleared by writing a 1 to this bit position.

Note: On reads from a codec, the controller will give the codec a maximum of 4 frames to respond, after

which if no response is received, it will return a dummy read completion to the processor (with all

pHs on the data) and also set the Read Completion Status bit in the Global Status Register.

14.2.10 CAS—Codec Access Semaphore Register

I/O Address:

Default Value:

Lockable:

NABMBAR + 44h

00h

Attribute:

Size:

Power Well:

R/W

8 bits

Core

Bit

Description

7:1

Reserved.

Codec Access Semaphore (CAS)—R/W (special). This bit is read by software to check whether a

codec access is currently in progress.

0 = No access in progress.

1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform

an I/O access. Once the access is completed, hardware automatically clears this bit.

14-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Pinout and Package Information 15

15.1

Pinout

This section contains the ICH2 82801BA and ICH2-M 82801BAM ballout information.

Figure 15-1 and Figure 15-2 provide a graphical illustration of how the ballout maps to the 360

EBGA package for both the ICH2 82801BA and 82801BAM ICH2-M. Table 15-1 provides the

ballout for the ICH2 82801BA, listed alphabetically by signal name. Table 15-2 provides the

ballout for the ICH2-M 82801BAM, listed alphabetically by signal name.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-1

Pinout and Package Information

Figure 15-1. ICH2 82801BA and ICH2-M 82801BAM Ballout (Top view — Left side)

HLCOMP

VSS

HL_STB

HL3

HL_STB#

HL4

VSS

#N/A

VSS

HL0

HL2

HL5

HL6

HL8

VSS

HL7

VSS

IGNNE#

NMI

VSS

HUBREF

VSS

HL1

VSS

HL11

VSS

HL9

HL10

VSS

STPCLK#

VCC1_8

INTR

VCC1_8

#N/A

VSS

CLK66

#N/A

VSS

A20M#

#N/A

VCC1_8

VSS

VCCSUS3_3

(ICH2)

LAN_TXD2

LAN_RXD1

LAN_RXD2

#N/A

LAN_TXD1

LAN_RXD0

LAN_TXD0

LAN_CLK

#N/A

VCCLAN3_3

(ICH2-M)

VCCSUS3_3

(ICH2)

VCCLAN3_3

(ICH2-M)

VCCSUS1_8

(ICH2)

LAN_RSTSYNC

VCCLAN1_8

(ICH2-M)

VCCSUS1_8

(ICH2)

#N/A

EE_SHCLK

EE_DIN

EE_DOUT

EE_CS

VSS

VCCLAN1_8

(ICH2-M)

VSS

V5REF1

GPIO21 (ICH2)

REQB# /

REQ5# /

GPIO1

GNTB# /

GNT5# /

GPIO17

C3_STAT# /

GPIO21

(ICH2-M)

GNTA# /GPIO16

REQA# /

GPIO0

GNT1#

GNT0#

PIRQH#

PIRQD#

VSS

PIRQG# /

GPIO4

PIRQF#/ GPIO3

PIRQE#

VSS

PIRQA#

GNT4#

REQ2#

AD26

PIRQB#

REQ0#

GNT3#

AD24

PIRQC#

REQ1#

AD30

REQ4#

GNT2#

AD28

VCC1_8

VCC3_3

AD3

AD22

AD20

AD18

AD16

FRAME#

AD11

TRDY#

AD4

VCC3_3

AD10

VCC3_3

SERR#

VCC3_3

IRDY#

VCC1_8

AD21

STOP#

PAR

AD27

AD29

PCICLK

GPIO6 (ICH2)

AD15

AD13

AD9

AD2

AD5

AD12

PERR#

C/BE2#

AD23

AGPBUSY#

(ICH2-M)

VSS

C/BE0#

AD6

AD0

AD1

AD7

AD8

AD14

C/BE1#

PLOCK#

DEVSEL#

AD17

AD19

C/BE3#

AD25

AD31

REQ3#

GPIO7

LFRAME# /

FWH4

15-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Figure 15-2. ICH2 82801BA and ICH2-M 82801BAM Ballout (Top view — Right side)

GPIO23 (ICH2) GPIO18 (ICH2)

CPUSLP#

CPUPWRGD

SDA0

SIORDY

SDD15

SDD13

SDD3

VSS

GMUXSEL#

(ICH2-M)

STP_PCI#

(ICH2-M)

VRMPWRGD

(ICH2)

SMI#

RCIN#

SDA2

SDDACK#

SDDREQ

SDD1

SDD11

VSS

GPIO22 (ICH2)

VGATE /

VRMPWRGD

(ICH2-M)

CPUPERF#

(ICH2-M)

GPIO20 (ICH2)

INIT#

A20GATE

SDCS1#

SDCS3#

VCC3_3

IRQ15

SDA1

SDIOW#

SDIOR#

VCC3_3

SDD14

SDD0

SDD12

SDD2

SDD4

SDD5

SDD8

SDD9

SDD6

STP_CPU#

(ICH2-M)

GPIO19 (ICH2)

V_CPU_IO

SDD10

SLP_S1#

(ICH2-M)

VCC3_3

PDCS3#

PDA1

SDD7

PDA0

PDCS1#

IRQ14

PDA2

PDDACK#

PDDREQ

PDD1

PDIOR#

PDD0

PIORDY

PDD15

PDD13

PDD11

PDD5

PDIOW#

PDD14

VSS

PDD2

PDD12

PDD3

VCC1_8

CLK14

PDD4

PDD10

PDD8

PDD9

V5REF2

APICCLK

CLK48

PDD6

PDD7

APICD1

AC_SYNC

AC_BITCLK

INTRUDER#

SMLINK0

SERIRQ

AC_SDOUT

RSMRST#

VBIAS

SPKR

VCC3_3

APICD0

FERR#

RTCX2

RTCX1

PWROK

VCCSUS3_3

RTCRST#

TP0(ICH2)

VCCRTC

BATLOW#

(ICH2-M)

GPIO24 (ICH2)

VCCSUS1_8

SLP_S3#

VCCSUS3_3

V5REF_SUS

SMLINK1

AC_RST#

CLKRUN#

(ICH2-M)

LAD1 / FWH1

LAD0 / FWH0

LDRQ1#

LDRQ0#

GPIO12

GPIO8

GPIO25

PME#

USBP0P

USBP2P

USBP0N

OC0#

OC3#

OC1#

PWRBTN#

OC2#

AC_SDIN1

AC_SDIN0

RSM_PWROK

(ICH2)

SUSSTAT#

USBP2N

LAN_PWROK#

(ICH2-M)

FS0

THRM#

GPIO28

GPIO27

PCIRST#

GPIO13

SMBDATA

SMBCLK

RI#

SUSCLK

SLP_S5#

USBP1N

USBP1P

USBP3N

USBP3P

VSS

LAD3 / FWH3

LAD2 / FWH2

SMBALERT# /

GPIO11

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-3

Pinout and Package Information

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Signal Name

Ball Number

Signal Name

Ball Number

AD28

AD29

Y10

SDD03

A20GATE

A20M#

AC_BITCLK

AC_RST#

AC_SDIN0

AC_SDIN1

AC_SDOUT

AC_SYNC

AD0

A20

C13

D11

R19

V22

Y22

W22

P21

P19

AA4

AB4

AD30

AD31

AA10

N20

P22

N19

AA3

AB6

APICCLK

APICD0

APICD1

C/BE0#

C/BE1#

C/BE2#

C/BE3#

AA9

M19

P20

AD1

CLK14

AD2

CLK48

AD3

CLK66

AD4

CPUPWRGD

CPUSLP#

DEVSEL#

EE_CS

A13

A12

AB7

AD5

AD6

AB3

AA5

AB5

AD7

AD8

EE_DIN

EE_DOUT

EE_SHCLK

FERR#

AD9

AD10

AD11

R22

AD12

FRAME#

FS0

AD13

AA12

AD14

AA6

GNT0#

AD15

GNT1#

AD16

GNT2#

AD17

AA8

GNT3#

AD18

GNT4#

AD19

AB8

GNTA# / GPIO16

GNTB# / GNT5# / GPIO17

GPIO6

AD20

AD21

Y11

AA11

Y14

W14

AB15

A15

D14

AD22

GPIO7

AD23

GPIO8

AD24

GPIO12

GPIO13

GPIO18

GPIO19

AD25

AB9

AD26

AD27

W10

15-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Signal Name

Ball Number

Signal Name

Ball Number

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO27

GPIO28

HL_STB

HL_STB#

HL0

C14

LAN_RXD1

LAN_RXD2

LAN_TXD0

LAN_TXD1

LAN_TXD2

LDRQ0#

LDRQ1#

LFRAME# / FWH4

NMI

B14

A14

V21

W15

AB14

AA14

Y13

W13

AB11

B11

W19

Y20

Y21

W20

OC0#

OC1#

HL1

OC2#

HL2

OC3#

HL3

PAR

HL4

PCICLK

PCIRST#

PDA0

W11

AA15

F20

F19

E22

E21

E19

H19

H22

J19

J22

K21

L20

M21

M22

L22

L21

K22

K20

J21

J20

H21

H20

F22

HL5

HL6

HL7

PDA1

HL8

PDA2

HL9

PDCS1#

PDCS3#

PDD0

HL10

HL11

HLCOMP

HUBREF

IGNNE#

INIT#

PDD1

PDD2

A11

C12

C11

T19

F21

C16

Y12

W12

AB13

AB12

PDD3

PDD4

INTR

PDD5

INTRUDER#

IRDY#

PDD6

PDD7

IRQ14

PDD8

IRQ15

PDD9

LAD0 / FWH0

LAD1 / FWH1

LAD2 / FWH2

LAD3 / FWH3

LAN_CLK

LAN_RSTSYNC

LAN_RXD0

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

PDDACK#

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-5

Pinout and Package Information

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Signal Name

Ball Number

Signal Name

Ball Number

PDDREQ

PDIOR#

G22

G19

G21

SDD2

SDD4

D19

C20

C21

D22

E20

D21

C22

D20

B20

C19

A19

C18

A18

B17

B18

D17

C17

N21

PDIOW#

PERR#

SDD5

SDD6

PIORDY

PIRQA#

G20

SDD7

SDD8

PIRQB#

SDD9

PIRQC#

SDD10

PIRQD#

SDD11

PIRQE#

SDD12

PIRQF# / GPIO3

PIRQG# / GPIO4

PIRQH#

SDD13

SDD14

SDD15

PLOCK#

PME#

AA7

Y15

W21

R20

B13

SDDACK#

SDDREQ

SDIOR#

SDIOW#

SERIRQ

SERR#

PWRBTN#

PWROK

RCIN#

REQ0#

REQ1#

SIORDY

SLP_S3#

SLP_S5#

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SMI#

A17

W16

AB18

AB17

AB16

AA16

B12

U19

V20

N22

REQ2#

REQ3#

AB10

REQ4#

REQA# / GPIO0

REQB# / REQ5#/ GPIO1

RI#

AA17

Y16

R21

T20

U22

T22

A16

D16

B16

C15

D15

D18

B19

RSM_PWROK

RSMRST#

RTCRST#

RTCX1

SMLINK0

SMLINK1

SPKR

STOP#

RTCX2

STPCLK#

SUSCLK

SUSSTAT#

THRM#

TP0

C10

AA18

Y17

AA13

U20

SDA0

SDA1

SDA2

SDCS1#

SDCS3#

SDD0

TRDY#

USBP0N

USBP0P

Y18

W17

SDD1

15-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Signal Name

Ball Number

Signal Name

Ball Number

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

V_CPU_IO

V5REF_SUS

V5REF1

V5REF2

VBIAS

AA19

AB19

Y19

W18

AA20

AB20

D12

D13

V19

VCCSUS1_8

VCCSUS3_3

VRMPWRGD

VSS

V14

V15

V16

T18

U18

V17

V18

B15

M20

T21

D10

VCC1_8

VCC3_3

VCCRTC

VSS

K19

L19

VSS

E14

E15

E16

E17

E18

F18

G18

H18

J18

P18

R18

VSS

J10

J11

J12

J13

J14

VSS

K10

K11

K12

K13

K14

VSS

L10

L11

VSS

A10

VSS

U21

VSS

A21

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-7

Pinout and Package Information

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Table 15-1. ICH2 82801BA Alphabetical

Ball List by Signal Name

Signal Name

Ball Number

Signal Name

Ball Number

VSS

A22

AA1

AA2

AA21

AA22

AB1

AB2

AB21

AB22

VSS

L12

L13

L14

M10

M11

M12

M13

M14

B10

N10

N11

N12

N13

N14

B21

B22

P10

P11

P12

P13

P14

15-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Table 15-2. ICH2-M 82801BAM

Alphabetical Ball List by

Signal Name

Alphabetical Ball List by

Signal Name

Ball Number

Signal Name

Ball Number

AD29

AD30

Y10

A20GATE

A20M#

AC_BITCLK

AC_RST#

AC_SDIN0

AC_SDIN1

AC_SDOUT

AC_SYNC

AD0

C13

D11

R19

V22

Y22

W22

P21

P19

AA4

AB4

AD31

AA10

Y11

N20

P22

N19

U20

AA3

AB6

AGPBUSY#

APICCLK

APICD0

APICD1

BATLOW#

C/BE0#

C/BE1#

AD1

C/BE2#

AD2

C/BE3#

AA9

AD3

C3_STAT# / GPIO21

CLK14

AD4

M19

P20

AD5

CLK48

AD6

AB3

AA5

AB5

CLK66

AD7

CLKRUN#

CPUPERF#

CPUPWRGD

CPUSLP#

DEVSEL#

EE_CS

V21

B14

A13

A12

AB7

AD8

AD9

AD10

AD11

AD12

AD13

EE_DIN

AD14

AA6

EE_DOUT

EE_SHCLK

FERR#

AD15

AD16

R22

AD17

AA8

FRAME#

FS0

AD18

AA12

A14

AD19

AB8

GMUXSEL#

GNT0#

AD20

AD21

GNT1#

AD22

GNT2#

AD23

GNT3#

AD24

GNT4#

AD25

AB9

GNTA# / GPIO16

GNTB# / GNT5# / GPIO17

GPIO7

AD26

AD27

W10

AA11

AD28

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-9

Pinout and Package Information

Table 15-2. ICH2-M 82801BAM

Alphabetical Ball List by

Signal Name

Alphabetical Ball List by

Signal Name

Ball Number

Signal Name

Ball Number

GPIO8

GPIO12

GPIO13

GPIO25

GPIO27

GPIO28

HL_STB

HL_STB#

HL0

Y14

W14

AB15

W15

AB14

AA14

LAN_RXD1

LAN_RXD2

LAN_TXD0

LAN_TXD1

LAN_TXD2

LDRQ0#

LDRQ1#

LFRAME# / FWH4

NMI

Y13

W13

AB11

B11

W19

Y20

Y21

W20

HL1

OC0#

HL2

OC1#

HL3

OC2#

HL4

OC3#

HL5

PAR

HL6

PCICLK

PCIRST#

PDA0

W11

AA15

F20

F19

E22

E21

E19

H19

H22

J19

J22

K21

L20

M21

M22

L22

L21

K22

K20

J21

J20

H21

H20

HL7

HL8

HL9

PDA1

HL10

PDA2

HL11

PDCS1#

PDCS3#

PDD0

HLCOMP

HUBREF

IGNNE#

INIT#

A11

C12

C11

T19

F21

C16

Y12

W12

AB13

AB12

PDD1

PDD2

INTR

PDD3

INTRUDER#

IRDY#

PDD4

PDD5

IRQ14

PDD6

IRQ15

PDD7

LAD0 / FWH0

LAD1 / FWH1

LAD2 / FWH2

LAD3 / FWH3

LAN_CLK

LAN_PWROK

LAN_RSTSYNC

LAN_RXD0

PDD8

PDD9

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

Y16

15-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Table 15-2. ICH2-M 82801BAM

Alphabetical Ball List by

Signal Name

Table 15-2. ICH2-M 82801BAM

Alphabetical Ball List by

Signal Name

Ball Number

Signal Name

Ball Number

PDDACK#

PDDREQ

PDIOR#

F22

G22

G19

G21

SDD1

SDD2

B19

D19

A20

C20

C21

D22

E20

D21

C22

D20

B20

C19

A19

C18

A18

B17

B18

D17

C17

N21

SDD3

PDIOW#

PERR#

SDD4

SDD5

PIORDY

PIRQA#

G20

SDD6

SDD7

PIRQB#

SDD8

PIRQC#

SDD9

PIRQD#

SDD10

PIRQE#

SDD11

PIRQF# / GPIO3

PIRQG# / GPIO4

PIRQH#

SDD12

SDD13

SDD14

PLOCK#

PME#

AA7

Y15

W21

R20

B13

SDD15

SDDACK#

SDDREQ

SDIOR#

SDIOW#

SERIRQ

SERR#

PWRBTN#

PWROK

RCIN#

REQ0#

REQ1#

REQ2#

SIORDY

SLP_S1#

SLP_S3#

SLP_S5#

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SMI#

A17

D14

W16

AB18

AB17

AB16

AA16

B12

U19

V20

N22

REQ3#

AB10

REQ4#

REQA# / GPIO0

REQB# / REQ5#/ GPIO1

RI#

AA17

R21

T20

U22

T22

A16

D16

B16

C15

D15

D18

RSMRST#

RTCRST#

RTCX1

SMLINK0

SMLINK1

SPKR

RTCX2

SDA0

SDA1

STOP#

SDA2

STP_CPU#

STP_PCI#

STPCLK#

SUSCLK

C14

A15

C10

AA18

SDCS1#

SDCS3#

SDD0

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-11

Pinout and Package Information

Table 15-2. ICH2-M 82801BAM

Alphabetical Ball List by

Signal Name

Alphabetical Ball List by

Signal Name

Ball Number

Signal Name

Ball Number

SUSSTAT#

THRM#

Y17

AA13

VCC3_3

VCCLAN1_8

VCCLAN3_3

VCCRTC

VCCSUS1_8

VCCSUS3_3

VGATE / VRMPWRGD

VSS

TRDY#

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

V_CPU_IO

V5REF_SUS

V5REF1

V5REF2

VBIAS

Y18

W17

AA19

AB19

Y19

W18

AA20

AB20

D12

D13

V19

U21

V14

V15

V16

T18

U18

V17

V18

B15

M20

T21

D10

VCC1_8

VCC3_3

K19

L19

VSS

E14

E15

E16

E17

E18

F18

G18

H18

J18

P18

R18

VSS

J10

J11

J12

J13

J14

VSS

K10

K11

K12

K13

K14

VSS

15-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Table 15-2. ICH2-M 82801BAM

Alphabetical Ball List by

Signal Name

Table 15-2. ICH2-M 82801BAM

Alphabetical Ball List by

Signal Name

Ball Number

Signal Name

Ball Number

VSS

L10

L11

VSS

A10

L12

L13

L14

A21

A22

AA1

AA2

AA21

AA22

AB1

AB2

AB21

AB22

M10

M11

M12

M13

M14

N10

N11

N12

N13

N14

B10

B21

B22

P10

P11

P12

P13

P14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-13

Pinout and Package Information

15.2

Package Information

Figure 15-3 and Figure 15-4 illustrate the ICH2 and ICH2-M 360 EBGA package.

Figure 15-3. ICH2 / ICH2-M Package (Top and Side Views)

Top View

0.127

-A-

23.00 ±0.10

19.50 ±0.20

Pin 1 corner

Pin 1 I.D.

-B-

Detail A

23.00 ±0.10

14.70 REF

19.50 ±0.20

45° Chamfer

(4 places)

0.127

14.70 REF

Detail A (Not to scale)

Au Gate

Pin #1 Corner

No Radius

Pin #1 SHINY

1.0 Dia x 0.15 Depth

6.75 ±0.50 x 6.75 ±0.50 From Center Line

90°

Side View

1.17 ±0.05

2.23 ±0.19

30°

0.15

-C-

0.56 ±0.04

0.50 ±0.10

Seating Plane (see Note 3)

Notes:

1. All dimensions are in millimeters.

2. All dimensions and tolerances conform to ANSI Y14.5M - 1982.

3. Primary Datum (-C-) and seating plane are defined by the sperical crowns of the solder balls.

15-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Pinout and Package Information

Figure 15-4. ICH2 / ICH2-M Package (Bottom View)

Bottom View

Pin A1 corner

0.70

0.50

Note 3

0.30

1.00

1.00 REF

1.00

1.00 REF

1.0

3 places

Notes:

1. All dim ensions are in m illimeters.

2. All dim ensions and tolerances conform to ANSI Y14.5M - 1982.

3. Dimension is measured at the maximum solder ball diameter. Parallel to Datum (-C-) on Side View illustration.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

15-15

Pinout and Package Information

This page is intentionally left blank.

15-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Note: The data provided in this chapter regarding the Electrical Characteristics of the ICH2 component

are preliminary and subject to change.

16.1

Absolute Maximum Ratings

^{Case Temperature under Bias ..................................................................................... 0}°^{C to +109}°^C

^{Storage Temperature ............................................................................................... -55}°^{C to +150}°^C

Voltage on Any 3.3V Pin with Respect to Ground...............................................-0.5 to Vcc + 0.3 V

Voltage on Any 5V Tolerant Pin with Respect to Ground (VREF=5V)...............-0.5 to VREF + 0.3 V

1.8V Supply Voltage with Respect to Vss .....................................................................-0.5 to +2.7V

3.3V Supply Voltage with Respect to Vss ....................................................................-0.5 to +4.6 V

5.0V Supply Voltage (Vref) with Respect to Vss .........................................................-0.5 to +5.5 V

Maximum Power Dissipation ....................................................................................................2.0 W

Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage.

These are stress ratings only. See Section 16.2 for the Functional Operating Range of the ICH2.

16.2

Functional Operating Range

All of the AC and DC Characteristics specified in this document assume that the ICH2 component

is operating within the Functional Operating Range given in this section. Operation outside of the

Functional Operating Range is not recommended, and extended exposure outside of the Functional

Operating Range may affect component reliability.

^{Case Temperature under Bias .................................................................................... 0}°^{C to +109}°^C

1.8V Supply Voltage (VCC1_8) with respect to Vss......................................................1.7V to 1.9V

1.8V Supply Voltage (VccSus1_8) with respect to Vss..................................................1.6Vto1.9V

ICH2-M: 1.8V Supply Voltage (VCCLAN1_8) with respect to Vss...........................1.6V to 1.9V

3.3V Supply Voltage (VCC3_3, VccSus3_3) with respect to Vss .........................3.102Vto3.498V

ICH2-M: 3.3V Supply Voltage (VCCLAN3_3) with respect to Vss...................3.102V to 3.498V

5V Supply Voltage (V5REF, V5REF_Sus) with respect to Vss................................ 4.75V to 5.25V

V_CPU_IO Voltage with respect to Vss......................................................................................TBD

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-1

Electrical Characteristics

16.3

D.C. Characteristics

Table 16-1. ICH2-M Power Consumption Measurements

Power Plane

Maximum Sustain Supply Current Icc(max)

(ICH2-M)

1.8V Core

300 mA

410 mA

30 mA

100 mA

5 mA

3.3V I/O

1.8V LAN

3.3V LAN

23 mA

6 mA

180 mA; 50 mA when LAN Connect Componenplaced

186 mA

180 mA

(LAN + LAN Connect

Component)

in reduced power mode (50 MHz clk!5 MHz)

2 mA

(ICH2)

1.8V Sus

5 mA

1.8 mA

1.4 mA

1.8 mA

1.4 mA

1.8 mA

1.4 mA

1.8 mA

(ICH2-M)

3.3V Sus

VccRTC

15 mA

1.4 mA

4 uA

NOTES:

1. 1.8V and 3.3V LAN Icc(max) in S0 was measured running Full Duplex LAN test.

2. 1.8V SUS Icc(max) in S0 state was measured while running a test that continuously accessed PM registers.

3. 3.3V SUS Icc(max) in S0 state was measured running a concurrency test, in which all 4 USB ports were

exercised.

4. 1.8V Core and 3.3V I/O Icc(max) in S0 state was measured running a test that generated a constant stream

of CPU->PCI writes, with an inverting pattern, causing data lines to switch on every clock.

Table 16-2. DC Characteristic Input Signal Association

Symbol

Associated Signals

PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, TRDY#, STOP#,

PAR, PERR#, PLOCK#, SERR#, REQ[4:0]#

PC/PCI Signals: REQ[A]#/GPIO[0], REQB[#]/REQ[5]#/GPIO[1]

IDE Signals: PDD[15:0], SDD[15:0], PDDREQ, PIORDY, SDDREQ, SIORDY

Interrupt Signals: IRQ[15:14], SERIRQ, PIRQ[D:A]#, PIRQ[H]#,

PIRQ[G:F]#/GPIO[4:3], PIRQ[E]#

Legacy Signals: RCIN#, A20GATE

USB Signals: OC[3:0]#.

ICH2 (82801BA):

IH1 IL1

(5V Tolerant)

GPIO Signals: GPIO[7,6,4,3,1,0]

ICH2-M (82801BAM):

GPIO Signals: GPIO[7,4,3,1,0]

Power Management Signals: AGPBUSY#

Clock Signals: CLK66, CLK48, CLK14, LAN_CLK, PCICLK

IH2 IL2

16-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Table 16-2. DC Characteristic Input Signal Association (Continued)

Symbol

Associated Signals

LPC/FWH Signals: LDRQ[1:0]#, LAD[3:0]/FWH[3:0].

System Management Signals: SMBALERT#/GPIO[11]

EEPROM Signals: EE_DIN

AC’97 Signals: AC_BITCLK, AC_SDIN[1:0], AC_SYNC

ICH2 (82801BA):

Power Management Signals: PME#, PWRBTN#, RI#, RSM_PWROK, RTCRST#,

THRM#, VRMPWRGD

IH3 IL3

GPIO Signals: GPIO[25:24, 13:12, 8]

ICH2-M (82801BAM):

Power Management Signals: BATLOW#, CLKRUN#, PME#, PWRBTN#, RI#,

LAN_PWROK, RTCRST#, THRM#, VRMPWRGD/VGATE

GPIO Signals: GPIO[25, 13:12, 8]

Clock Signals: APICCLK

IH4 IL4

SMBus Signals: SMBCLK, SMBDATA

System Management Signals: INTRUDER#, SMLINK[1:0]

Power Management Signals: RSMRST#, PWROK,

GPIO Signals: GPIO[28:27]

IH5 IL5

LAN Signals: LAN_RXD[2:0]

Processor Signals: FERR#, APICD[1:0]

Hub Interface Signals: HL[11:0], HL_STB#, HL_STB

USB Signals: USBP[1:0][P,N]

RTCX1

IL6 IH6

IL7 IH7

IL8 IH8

/ V / V

CM SE

IL9 IH9

Table 16-3. DC Input Characteristics

Symbol

Parameter

Min.

Max

Unit

Notes

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

-0.5

2.0

0.8

V5REF + 0.5

0.8

IL1

IH1

-0.5

IL2

2.0

Vcc3_3 + 0.5

0.3Vcc3_3

Vcc3_3 + 0.5

0.7

IH2

-0.5

IL3

0.5Vcc3_3

-0.5

IH3

IL4

1.7

2.625

IH4

-0.5

0.6

IL5

2.1

VccSus3_3 + 0.5

0.3Vcc3_3

Vcc3_3 + 0.5

0.6

IH5

-0.5

IL6

0.6Vcc3_3

-0.5

IH6

IL7

1.2

Vcc3_3 + 0.5

HUBREF - 0.15

HUBREF - 0.20

IH7

Normal Mode

Input Low Voltage

-0.5

IL8

Enhanced Mode

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-3

Electrical Characteristics

Table 16-3. DC Input Characteristics

Symbol

Parameter

Min.

Max

Unit

Notes

HUBREF + 0.15

HUBREF + 0.20

Normal Mode

Input High Voltage

Vcc1_8 + 0.5

IH8

Enhanced Mode

Differential Input

Sensitivity

0.2

0.8

Note 1

Note 2

DifferentialCommon

Mode Range

2.5

2.0

Single-Ended

Receiver Threshold

Input Low Voltage

Input High Voltage

-0.5

0.10

2.0

IL9

0.40

IH10

NOTES:

1. V = | USBPx[P] - USBPx[N] |

2. Includes V range.

Table 16-4. DC Characteristic Output Signal Association

Symbol

Associated Signals

IDE Signals: PDD[15:0], SDD[15:0], PDIOW#/PDSTOP, SDIOW#/SDSTOP, PDIOR#/

PDWSTB/PRDMARDY, SDIOR#/STWSTB/SRDMARDY, PDDACK#, SDDACK#,

PDA[2:0], SDA[2:0], PDCS[3,1]#, SDCS[3,1]#

OH1 OL1

Processor Signals: A20M#, CPUPWRGD, CPUSLP#, IGNNE#, INIT#, INTR, NMI,

SMI#, STPCLK#

OH2 OL2

PCI Signals: AD[31:0], C/BE[3:0]#, PCIRST#, GNT[4:0]#, PAR, DEVSEL#, PERR#,

PLOCK#, STOP#, TRDY#, IRDY#, FRAME#, SERR#

OH3 OL3

Interrupt Signals: SERIRQ, PIRQ[D:A]#, PIRQ[H]#, PIRQ[G:F]#/GPIO[4:3], PIRQ[E]#

PCI Signals: GNT5#/GNTB#/GPIO17, GNTA#/GPIO16

LPC/FWH Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4]

AC’97 Signals: AC_RST#, AC_SDOUT, AC_SYNC

LAN Signals: LAN_RSTSYNC, LAN_TXD[2:0]

ICH2 (82801BA):

OH4 OL4

Power Management Signals: PME#

GPIO Signals: GPIO[21]

ICH2-M (82801BAM):

Power Management Signals: PME#, C3_STAT#

SMBus Signals: SMBCLK, SMBDATA

System Management Signals: SMLINK[1:0]

Interrupt Signals: APICD[1:0]

OL5 OH5

EEPROM Signals: EE_CS, EE_DOUT, EE_SHCLK

Other Signals: SPKR]

ICH2 (82801BA):

Power Management Signals: SLP_S3#, SLP_S5#, SUS_STAT#, SUSCLK

GPIO Signals: GPIO[25:22, 20:18]

ICH2-M (82801BAM):

OL6 OH6

GPIO Signals: GPIO[25]

USB Signals: USBPO[P:N], USBP1[P:N]

Hub Signals: HL[11:0], HL_STB#, HL_STB

OL7 OH7

OL8 OH8

16-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Table 16-5. DC Output Characteristics

Symbol

Parameter

Min.

Max

Unit

Notes

OL / OH

Output Low Voltage

Output High Voltage

Output Low Voltage

0.5

4 mA

OL1

2.4

-0.4 mA

4.0 mA

OH1

0.4

0.55

0.1Vcc

0.4

OL2

Output High Voltage V_CPU_IO - 0.13V

Output Low Voltage

-0.5 mA Note 1

6 mA

OH2

OL3

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

2.4

-2 mA

Note 1

OH3

1.5 mA

OL4

0.9Vcc

-0.5 mA Note 1

3.0 mA

OH4

OL5

N/A

Note 1

OH5

0.4

4.0 mA

OL6

Vcc3_3 - 0.5

Vcc - 0.5

-2.0 mA Note 1

5 mA

OH6

0.4

OL7

-2 mA

OH7

0.1(Vcc1_8)

0.8

1 mA

Normal Mode

Output Low Voltage

Output High Voltage

OL8

20 mA

Enhanced Mode

0.9(Vcc1_8)

1.6

-1 mA

Normal Mode

OH8

-1.5 mA Enhanced Mode

NOTES:

1. The CPUPWRGD, SERR#, PIRQ[A:H], PME#, GPIO22/CPUPERF, APIC[1:0], SMBDATA, SMBCLK and

SMLINK[1:0] signals have an open drain driver, and the VOH specification does not apply. These signals

must have external pull-up resistors.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-5

Electrical Characteristics

Table 16-6. Other DC Characteristics

Symbol

Parameter

Min.

Max

Unit

Notes

VBIAS

Voltage BIAS

0.32

4.75

3.102

1.7

0.44

5.25

3.498

1.9

ICH2 Core Well Reference Voltage

I/O Buffer Voltage

V5REF

VCC3_3

VCC1_8

Internal Logic Voltage

0.48(Vcc1.8) 0.52(Vcc1.8)

0.64(Vcc1.8) 0.70(Vcc1.8)

Normal Mode

HUBREF

Hub Interface Reference Voltage

Enhanced Mode

Suspend Well Reference Voltage

Suspend Well I/O Buffer Voltage

Suspend Well Logic Voltage

4.75

3.102

1.6

5.25

3.498

1.9

V5REF_Sus

VccSus3_3

VccSus1_8

VccLAN3_3

(ICH2-M)

LAN Controller I/O Buffer Voltage

LAN Controller Logic Voltage

3.102

1.7

3.498

VccLAN1_8

(ICH2-M)

1.9

3.6

Vcc(RTC)

Battery Voltage

2.0

1.9

Applied to

USBP[3:0][P:N]

IT+

Hysteresis Input Rising Threshold

Applied to

USBP[3:0]P:N]

Hysteresis Input Falling Threshold

1.3

IT-

Differential Input Sensitivity

Differential Common Mode Range

Output Signal Crossover Voltage

Single Ended Rcvr Threshold

Input Leakage Current

0.2

0.8

1.3

0.8

-1.0

-10

|(USBPx+,USBPx-)|

2.5

2.0

Includes V

CRS

2.0

LI1

LI2

+1.0

+10

Hi-Z State Data Line Leakage

uA (0 V< V < 3.3V)

Input Leakage Current - Clock

signals

-100

+100

uA See Note

LI3

Input Capacitance - Hub interface

Input Capacitance - All Other

= 1 MHz

Output Capacitance

I/O Capacitance

= 1 MHz

OUT

I/O

Crystal Load Capacitance

7.5

NOTE: Includes APICCLK, CLK14, CLK48, CLK66, LAN_CLK and PCICLK

16-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

16.4

A.C. Characteristics

Table 16-7. Clock Timings

Sym

Parameter

Min

Max

Unit

Notes

Figure

PCI Clock (PCICLK)

Period

33.3

16-2

High Time

Low Time

Rise Time

Fall Time

Oscillator Clock (OSC)

USB Clock (USBCLK)

Period

16-2

High Time

Low time

Operating Frequency

Frequency Tolerance

High Time

MHz

ppm

clk48

2500

t10

t11

t12

t13

16-2

Low time

Rise Time

1.2

Fall Time

Suspend Clock (SUSCLK)

Operating Frequency

High time

KHz

susclk

t14

16-2

t15

Low Time

SMBus Clock (SMBCLK)

Operating Frequency

High time

4.0

4.7

KHz

smb

t18

16-17

t19

t20

t21

Low time

Rise time

1000

300

Fall time

I/O APIC Clock (APICCLK)

Operating Frequency

High time

14.32 33.33

MHz

ioap

t22

16-2

t23

t24

t25

Low time

Rise time

1.0

5.0

Fall time

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-7

Electrical Characteristics

Table 16-7. Clock Timings (Continued)

Sym

Parameter

AC’97 Clock (BITCLK)

Operating Frequency

Min

Max

Unit

Notes

Figure

12.288

750

ac97

t26

Output Jitter

High time

Low time

Rise time

Fall time

t27

t28

t29

t30

32.56 48.84

16-2

2.0

6.0

Hub Interface Clock

Operating Frequency

High time

t31

t32

t33

t34

t35

6.0

16-2

Low time

Rise time

0.25

1.0

1.2

4.5

Fall time

CLK66 leads PCICLK

NOTES:

1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle.

2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle

conditions.

3. This specification includes pin-to-pin skew from the clock generator as well as board skew.

4. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.

5. SUSCLK duty cycle can range from 30% minimum to 70% maximum.

16-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Table 16-8. PCI Interface Timing

Sym

Parameter

AD[31:0] Valid Delay

Min

Max Units

Notes

Figure

Min: 0pF

Max: 50pF

t40

16-3

t41

t42

AD[31:0] Setup Time to PCICLK Rising

AD[31:0] Hold Time from PCICLK Rising

16-4

C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PAR, PERR#, PLOCK#, DEVSEL# Valid Delay

from PCICLK Rising

Min: 0pF

Max: 50pF

t43

t44

16-3

16-7

C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output

Enable Delay from PCICLK Rising

C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float

Delay from PCICLK Rising

t45

t46

t47

16-5

16-4

C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

SERR#, PERR#, DEVSEL#, Setup Time to

PCICLK Rising

C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,

SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold

Time from PCLKIN Rising

16-4

16-6

t48

t49

PCIRST# Low Pulse Width

GNT[A:B}#, GNT[5:0]# Valid Delay from PCICLK

Rising

REQ[A:B]#, REQ[5:0]# Setup Timer to PCICLK

Rising

t50

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-9

Electrical Characteristics

Table 16-9. IDE PIO & Multiword DMA Mode Timing

Sym

Parameter

Min

Max

Units

Notes

Figure

PDIOR#/PDIOW#/SDIOR#/SDIOW# Active From

CLK66 Rising

t60

16-8, 16-9

PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From

CLK66 Rising

t61

t62

t63

16-8, 16-9

16-8

PDA[2:0]/SDA[2:0] Valid Delay From CLK66 Rising

PDCS1#/SDCS1#, PDCS3#/SDCS3# Active From

CLK66 Rising

16-8

PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From

CLK66 Rising

t64

16-8

16-9

t65

t66

t67

t68

PDDACK#/SDDACK# Active From CLK66 Rising

PDDACK#/SDDACK# Inactive From CLK66 Rising

PDDREQ/SDDREQ Setup Time to CLK66 Rising

PDDREQ/SDDREQ Hold From CLK66 Rising

16-9

PDD[15:0]/SDD[15:0] Valid Delay From CLK66

Rising

t69

16-8, 16-9

t70

t71

t72

t73

t74

PDD[15:0]/SDD[15:0] Setup Time to CLK66 Rising

PDD[15:0]/SDD[15:0] Hold From CLK66 Rising

PIORDY/SIORDY Setup Time to CLK66 Rising

PIORDY/SIORDY Hold From CLK66 Rising

PIORDY/SIORDY Inactive Pulse Width

16-8, 16-9

16-8

PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width

Low

t75

t76

2,3

3,4

16-8, 16-9

PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width

High

NOTES:

1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock.

2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI

clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register

3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width

cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE

timing register.

4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or greater.

Refer to the RCT field in the IDE Timing Register.

16-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Table 16-10. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)

Mode 0 (ns)

(1)

Mode 1 (ns)

Mode 2 (ns)

Figure

Sym

Parameter

Min

Max

Min

Max

Min

Max

t80

t81

t82

t83

t84

t85

t86

t87

t88

t89

t90

Sustained Cycle Time (T2cyctyp)

Cycle Time (Tcyc)

240

160

120

112

230

154

115

16-11

16-13

16-10

16-12

Two Cycle Time (T2cyc)

Data Setup Time (Tds)

Data Hold Time (Tdh)

Data Valid Setup Time (Tdvs)

Data Valid Hold Time (Tdvh)

Limited Interlock Time (Tli)

Interlock Time w/ Minimum (Tmli)

Envelope Time (Tenv)

150

160

125

100

Ready to Pause Time (Trp)

16-10,

16-13

t91

DMACK setup/hold Time (Tack)

NOTE:

1. The specification symbols in parentheses correspond to the Ultra ATA specification name.

Table 16-11. Ultra ATA Timing (Mode 3, Mode 4, Mode 5)

Mode 3 (ns)

Mode 4 (ns)

Mode 5 (ns)

(1)

Sym

Parameter

Figure

Min

Max

Min

Max

Min

Max

t80

t81

t82

t83

t84

t85

t86

t87

t88

t89

t90

Sustained Cycle Time (T2cyctyp)

(2)

Cycle Time (Tcyc)

16.8

16-11

16-13

16-10

16-12

Two Cycle Time (T2cyc)

Data Setup Time (Tds)

4.0

4.6

3.3

Data Hold Time (Tdh)

Data Valid Setup Time (Tdvs)

Data Valid Hold Time (Tdvh)

Limited Interlock Time (Tli)

Interlock Time w/ Minimum (Tmli)

Envelope Time (Tenv)

100

Ready to Pause Time (Trp)

16-10,

16-13

t91

DMACK setup/hold Time (Tack)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-11

Electrical Characteristics

Table 16-12. Universal Serial Bus Timing

Sym

Parameter

Min

Max

Units

Notes

Fig

Full Speed Source (Note 7)

t100

t101

USBPx+, USBPx- Driver Rise Time

USBPx+, USBPx- Driver Fall Time

1, C = 50 pF 16-14

Source Differential Driver Jitter

To Next Transition

t102

-2

-1

2, 3

16-15

16-16

For Paired Transitions

t103

t104

Source EOP Width

160

-2

175

Differential to SE0 Transition Skew

Receiver Data Jitter Tolerance

To Next Transition

t105

-20

-10

16-15

16-16

For Paired Transitions

EOP Width: Must reject as EOP

EOP Width: Must accept as EOP

t106

t107

Differential to SE0 Transition Skew

-2

Low Speed Source (Note 8)

1, 6

t108

t109

USBPx+, USBPx- Driver Rise Time

= 50 pF

= 350 pF

16-14

300

1,6

USBPx+, USBPx- Driver Fall Time

= 50 pF

= 350 pF

Source Differential Driver Jitter

To Next Transition

t110

-2

-1

2, 3

16-15

16-16

For Paired Transitions

t111

t112

Source EOP Width

160

-2

175

Differential to SE0 Transition Skew

Receiver Data Jitter Tolerance

To Next Transition

For Paired Transitions

t113

-20

-10

16-15

16-16

EOP Width: Must reject as EOP

EOP Width: Must accept as EOP

t114

t115

Differential to SE0 Transition Skew

-2

NOTES:

1. Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at

maximum

2. Timing difference between the differential data signals

3. Measured at crossover point of differential data signals

4. Measured at 50% swing point of data signals

5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP

6. Measured from 10% to 90% of the data signal

7. Full Speed Data Rate has minimum of 11.97 Mbps and maximum of 12.03 Mbps

8. Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps

16-12

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Table 16-13. IOAPIC Bus Timing

Sym

Parameter

Min

Max

Units

Notes

Fig

t120

t121

t122

APICCD[1:0]# Valid Delay from APICCLK Rising

APICCD[1:0]# Setup Time to APICCLK Rising

APICCD[1:0]# Hold Time from APICCLK Rising

3.0

8.5

3.0

12.0

16-3

16-4

Table 16-14. SMBus Timing

Sym

Parameter

Min

Max

Units Notes

Fig

t130

t131

Bus Tree Time Between Stop and Start Condition

4.7

16-17

Hold Time after (repeated) Start Condition. After this

period, the first clock is generated.

4.0

16-17

t132

t133

t134

t135

t136

t137

t138

Repeated Start Condition Setup Time

Stop Condition Setup Time

4.7

4.0

300

250

16-17

Data Hold Time

Data Setup Time

Device Time Out

Cumulative Clock Low Extend Time (slave device)

Cumulative Clock Low Extend Time (master device)

16-18

NOTES:

1. A device will time out when any clock low exceeds this value.

2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the

initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines

and reset itself.

3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a

message as defined from start-to-ack, ack-to-ack or ack-to-stop.

Table 16-15. AC’97 Timing

Sym

Parameter

Min

Max

Units

Notes

Fig

t140

t141

ACSDIN[0:1] Setup to Falling Edge of BITCLK

ACSDIN[0:1] Hold from Falling Edge of BITCLK

ACSYNC, ACSDOUT valid delay from rising edge of

BITCLK

t142

16-3

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-13

Electrical Characteristics

Table 16-16. LPC Timing

Sym

Parameter

Min

Max

Units

Notes

Fig

t150

t151

t152

t153

t154

t155

t156

t157

LAD[3:0] Valid Delay from PCICLK Rising

LAD[3:0] Output Enable Delay from PCICLK Rising

LAD[3:0] Float Delay from PCICLK Rising

LAD[3:0] Setup Time to PCICLK Rising

LAD[3:0] Hold Time from PCICLK Rising

LDRQ[1:0]# Setup Time to PCICLK Rising

LDRQ[1:0]# Hold Time from PCICLK Rising

LFRAME# Valid Delay from PCICLK Rising

16-3

16-7

16-5

16-4

16-3

Table 16-17. Miscellaneous Timings

Sym

Parameter

Min

Max

Units

Notes

Fig

t160

t161

t162

t163

t164

t165

SERIRQ Setup Time to PCICLK Rising

SERIRQ Hold Time from PCICLK Rising

RI#, EXTSMI#, GPI, USB Resume Pulse Width

SPKR Valid Delay from OSC Rising

SERR# Active to NMI Active

16-4

16-6

16-3

RTCCLK

200

230

IGNNE# Inactive from FERR# Inactive

Table 16-18. Power Sequencing and Reset Signal Timings

Sym

Parameter

Min

Max

Units

Notes

Fig

16-18,

16-19

t170

VccRTC active to RTCRST# inactive

V5RefSus active to VccSus3_3, VccSus1_8

active

16-18,

16-19

t171

t172

1, 2

VccRTC supply active to VccSus supplies

active

16-18,

16-19

t173

(ICH2)

VccSus supplies active to RSM_PWROK

active, RSMRST# inactive

16-18,

16-21

t173

(ICH2-M)

16-19

16-22

VccSus supplies active to RSMRST# inactive

V5Ref active to Vcc3_3, Vcc1_8 active

16-18,

16-19

t174

1, 2

t175

(ICH2)

VccSus supplies active to Vcc supplies active

VccSus supplies active to VccLAN supplies

16-18

16-19

t175a

(ICH2-M) active

t175b

VccLAN supplies active to LAN_PWROK

(ICH2-M) active

16-19

16-20

t175c

(ICH2-M)

VccLAN supplies active to Vcc supplies active

16-19

16-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Table 16-18. Power Sequencing and Reset Signal Timings (Continued)

Sym

Parameter

Min

Max

Units

Notes

Fig

16-18,

16-21,

16-25

t176

(ICH2)

Vcc supplies active to PWROK, VRMPWRGD

active

16-19

16-20

16-22

t176

(ICH2-M)

Vcc supplies active to PWROK, VGATE active

16-18,

16-21

16-25

PWROK, VRMPWRGD active to SUS_STAT#

inactive

t177

RTCCLK

16-18

16-20

16-22

PWROK, VGATE active to SUS_STAT#

inactive

16-18,

16-19

16-21,

16-22

16-25,

16-26

t178

SUS_STAT# inactive to PCIRST# inactive

RTCCLK

t179

t180

AC_RST# active low pulse width

AC_RST# inactive to BIT_CLK startup delay

162.8

NOTES:

1. The V5Ref supply must power up before or simultaneous with its associated 3.3V supply, and must power

down simultaneous with or after the 3.3V supply. See Section 2.20.4 for details.

2. The associated 3.3V and 1.8V supplies are assumed to power up or down together. The difference between

the levels of the 3.3V and 1.8V supplies must never be greater than 2.0V.

3. 82801BA ICH2: The VccSus supplies must never be active while the VccRTC supply is inactive. Likewise,

the Vcc supplies must never be active while the VccSus supplies are inactive.

4. 82801BAM ICH2-M: The VccSus supplies must never be active while the VccRTC supply is inactive.

Likewise, the Vcc or VccLAN supplies must never be active while the VccSus supplies are inactive, and the

Vcc supplies must never be active while the VccLAN supplies are inactive.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-15

Electrical Characteristics

Table 16-19. Power Management Timings

Sym

Parameter

Min

Max

Units

Notes

Fig

VccSus active to SLP_S3#, SLP_S5#,

SUS_STAT# and PCIRST# active

16-21,

16-22

t181

t182

t183

RSMRST# inactive to SUSCLK running,

SLP_S3#, SLP_S5# inactive

16-21,

16-22

110

t184

(ICH2)

Vcc active to STPCLK#, CPUSLP#, inactive,

and processor Frequency Strap signals high

16-21,

16-25

Vcc active to STPCLK#, CPUSLP#,

STP_CPU#, STP_PCI#, SLP_S1, C3_STAT#

inactive, and CPU Frequency Strap signals high

t184

(ICH2-M)

16-20

16-22

PWROK and VRMPWRGD active to

SUS_STAT# inactive and processor Frequency

Straps latched to Strap Values

16-21,

16-22

t185

t186

RTCCLK

CLK66

Processor Reset Complete to Frequency Strap

signals unlatched from Strap Values

16-21,

16-22

16-23,

16-24

16-25,

16-26

t187

STPCLK# active to Stop Grant cycle

N/A

t188

(ICH2)

16-25,

16-25

Stop Grant cycle to CPUSLP# active

Stop Grant cycle to C3_STAT# active

PCICLK

16-23,

16-26,

16-28

t188a

(ICH2-M)

16-23,

16-26,

16-28

t188b

(ICH2-M)

C3_STAT# active to CPUSLP# active

2.8

t189

(ICH2)

S1 Wake Event to CPUSLP# inactive

CPUSLP# inactive to STPCLK# inactive

CPUSLP# active to SUS_STAT# active

204

237

PCICLK

16-23

16-23,

16-25

t190

t192

(ICH2)

RTCCLK

16-25

16-23,

16-26,

16-28

t192a

(ICH2-M)

CPUSLP# active to STP_CPU# active

PCICLK

t192b

(ICH2-M)

16-23,

16-26,

STP_CPU# active to SUS_STAT# active

SUS_STAT# active to PCIRST# active

SUS_STAT# active to STP_PCI# active

STP_PCI# active to SLP_S1# active

RTCCLK

t193

(ICH2)

16-25

t193a

(ICH2-M)

16-23,

16-26,

t193b

(ICH2-M)

16-23,

16-26,

SLP_S1# active to PCIRST# active, STP_PCI#

inactive, SLP_S1# inactive, and STP_CPU#

inactive

t193c

(ICH2-M)

16-23,

16-26,

RTCCLK

16-25,

16-26

t194

PCIRST# active to SLP_S3# active

16-16

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Table 16-19. Power Management Timings

Sym

Parameter

Min

Max

Units

Notes

Fig

16-25,

16-26

t195

SLP_S3# active to SLP_S5# active

RTCCLK 1, 6

SLP_S3# active to VRMPWRGD (VRMPWRGD

/ VGATE for ICh2-M) inactive

16-25,

16-26

t196

t196a

t197

100

16-25,

16-26

SLP_S3# active to PWROK

PWROK, VRMPWRGD inactive to Vcc supplies

inactive

16-25,

16-26

16-25,

16-26

t198

Wake Event to SLP_S3#, SLP_S5# inactive

RTCCLK

t198a

(ICH2-M)

Wake Event to SLP_S1# inactive

16-23,

t199

SLP_S1# inactive to STP_CPU#, STP_PCI#

(ICH2-M) inactive

t200

STP_CPU#, STP_PCI# inactive to SUS_STAT#

(ICH2-M) inactive

t201

(ICH2-M)

SUS_STAT# inactive to CPU_SLP# inactive

PCICLK

t203

(ICH2-M)

16-23,

16-28

STPCLK# inactive to C3_STAT# inactive

Processor I/F signals latched prior to STPCLK#

active

t204

t205

t206

CLK66

16-27

Break Event to STPCLK# inactive

3120

1880

STPCLK# inactive to processor I/F signals

unlatched

240

t207

(ICH2-M)

Break Event to STP_CPU# inactive

PCICLK

16-28

t208

(ICH2-M)

STP_CPU# inactive to CPU_SLP# inactive

NOTES:

1. These transitions are clocked off the internal RTC. One RTC clock is approximately 32 us.

2. This transition is clocked off the 66 MHz CLK66. One CLK66 is approximately 15 ns.

3. The ICH2 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing

for this cycle getting to the ICH2 is dependant on the processor and the memory controller.

4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.

5. The ICH2 has no maximum timing requirement for this transition. It is up to the system designer to determine

if the SLP_S3# and SLP_S5# signals are used to control the power planes.

6. If the transition to S5 is due to Power Button Override, SLP_S3# and SLP_S5# are asserted together

following timing t194 (PCIRST# active to SLP_S3# and SLP_S5# active).

7. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay

from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-17

Electrical Characteristics

16.5

Timing Diagrams

Figure 16-1. Clock Timing

Period

High Time

2.0V

0.8V

Low Time

Fall Time

Figure 16-2. Valid Delay From Rising Clock Edge

Rise Time

Clock

1.5V

Valid Delay

Output

Figure 16-3. Setup And Hold Times

Clock

1.5V

Setup Time

Hold Time

Input

Figure 16-4. Float Delay

Input

Float

Delay

Output

16-18

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Figure 16-5. Pulse Width

Pulse Width

Figure 16-6. Output Enable Delay

Clock

1.5V

Output

Enable

Delay

Output

Figure 16-7. IDE PIO Mode

CLK66

t61

t60

t76

t75

DIOx#

t69

write data

DD[15:0] Write

t71

t70

read data

DD[15:0] Read

t73

t72

t74

IORDY

sample point

t64

t62,t63

DA[2:0], CS1#, CS3#

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-19

Electrical Characteristics

Figure 16-8. IDE Multiword DMA

CLK66

t68

t67

DDREQ[1:0]

t65

DDACK[1:0]

t60

t61

t75

t76

DIOx#

t70 t71

Read Data

Write Data

DD[15:0] Read

DD[15:0] Write

Read Data

t69

Write Data

t69

Figure 16-9. Ultra ATA Mode (Drive Initiating a Burst Read)

DMARQ (drive)

t91

DMACK# (host)

t89

STOP (host)

t89

DMARDY# (host)

STROBE (drive)

DD[15:0]

DA[2:0], CS[1:0]

16-20

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Figure 16-10. Ultra ATA Mode (Sustained Burst)

t82

t81

t85

STROBE @ sender

t86

Data @ sender

t83

STROBE @ receiver

t84

Data @ receiver

Figure 16-11. Ultra ATA Mode (Pausing a DMA Burst)

t90

STOP (host)

DMARDY#

STROBE

DATA

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-21

Electrical Characteristics

Figure 16-12. Ultra ATA Mode (Terminating a DMA Burst)

DMARQ (drive)

t88

t91

DMACK# (host)

STOP (host)

DMARDY# (drive)

t87

Strobe (host)

DATA (host)

CRC

Figure 16-13. USB Rise and Fall Times

Rise Time

90%

Fall Time

90%

Differential

Data Lines

10%

Low Speed: 75 ns at=C50 pF, 300 ns at=C350 pF

Full Speed: 4 to 20 ns at=C50 pF

Figure 16-14. USB Jitter

Tperiod

Crossover

Points

Differential

Data Lines

Consecutive

Transitions

Paired

Transitions

16-22

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Figure 16-15. USB EOP Width

Tperiod

Data

Crossover

Level

Differential

Data Lines

EOP

Width

Figure 16-16. SMBus Transaction

t19

t20

t21

SMBCLK

t135

t133

t131

t18

t134

t132

SMBDATA

t130

Figure 16-17. SMBus Time-out

Start

Stop

t137

CLK

ack

t138

SMBCLK

SMBDATA

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-23

Electrical Characteristics

Figure 16-18. Power Sequencing and Reset Signal Timings (82801BA ICH2 only)

PWROK,

VRMPWRGD

T176

Vcc3_3, Vcc1_8,

V_CPU_IO

T175

T174

V5Ref

RSMRST#,

RSM_PWROK

T173

T171

VccSus3_3,

VccSus1_8

T172

V5RefSus

RTCRST#

T170

VccRTC

ich2_powerup_reset_DT.vsd

Figure 16-19. Power Sequencing and Reset Signal Timings (82801BAM ICH2-M only)

PWROK,

VGATE

T176

Vcc3_3, Vcc1_8,

V_CPU_IO

T175c

T174

V5Ref

T175b

LAN_PWROK

VccLAN3_3,

VccLAN1_8

T175a

T173

RSMRST#

VccSus3_3,

VccSus1_8

T172

T171

V5RefSus

RTCRST#

T170

VccRTC

ICH2_Powerup_Reset_MO.vst

16-24

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Figure 16-20. 1.8V/3.3V Power Sequencing

3.3

1.8

Voltage

V < 2.0V

Time

Figure 16-21. G3 (Mechanical Off) to S0 Timings (82801BA ICH2 only)

System

State

S0 state

Hub interface "CPU

Reset Complete"

message

STPCLK#,

CPUSLP#

T186

T184

Frequency

Straps

Normal Operation

Strap Values

T185

T177

PCIRST#

T178

T181

SUS_STAT#

PWROK,

VRMPWRGD

T176

Vcc

SLP_S3#

SLP_S5#

T181

T183

T182

Running

SUSCLK

RSMRST#,

RSM_PWROK

T173

VccSus

ICH2_G3_S0_timing_DT1.vst

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-25

Electrical Characteristics

Figure 16-22. G3 (Mechanical Off) to S0 Timings (82801BAM ICH2-M only)

System

State Removed (G3)

Main Battery

S0 state

Hub interface "CPU

Reset Complete"

message

STPCLK#, CPUSLP#,

STP_CPU#, STP_PCI#,

SLP_S1#, C3_STAT#

T186

T184

Frequency

Straps

Normal Operation

Strap Values

T185

T177

PCIRST#

T178

T181

SUS_STAT#

PWROK, VGATE,

LAN_PWROK

T175b / T176

Vcc,

VccLAN

SLP_S3#

SLP_S5#

T181

T183

T182

SUSCLK

RSMRST#

VccSus

Running

T173

ICH2 G3 S0 timing MO vsd

Figure 16-23. S0 to S1 to S0 Timings (82801BA ICH2 only)

STATE

STPCLK#

T190

PCI Stop Grant

Cycle

T187

CPUSLP#

T188

T189

Wake Event

ich2_S0_S1D_timing.vsd

16-26

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Figure 16-24. S0 to S1 to S0 Timings (82801BAM ICH2-M only)

STATE

STPCLK#

T190

PCI Stop Grant

Cycle

T187

T203

C3_STAT#

T188a

CPUSLP#

T188b

T201

STP_CPU#

T192a

T199

SUS_STAT#

STP_PCI#

T192b

T200

T193a

SLP_S1#

T193b

T198a

Wake Event

Figure 16-25. S0 to S5 to S0 Timings (82801BA ICH2 only)

S4/S5

S3/S4/S5

STPCLK#

Stop Grant

Cycle

T184

T187

CPUSLP#

SUS_STAT#

PCIRST#

T188

T192

T177

T193

T178

SLP_S3#

T194

T198

SLP_S5#

T195

W ake Event

VRMPW RGD

T196

T176

PW ROK

Vcc

T196a

T197

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-27

Electrical Characteristics

Figure 16-26. S0 to S5 to S0 Timings (82801BAM ICH2-M only)

S4/S5

S3/S4/S5

STPCLK#

Stop Grant

Cycle

T184

T187

C3_STAT#

CPUSLP#

T188a

T188b

STP_CPU#

T192a

T177

SUS_STAT#

T192b

SLP_S1#

T193a

STP_PCI#

T193b

T178

PCIRST#

SLP_S3#

T193c

T194

T198

SLP_S5#

T195

W ake Event

VGATE

T196

T176

PW ROK

T196a

Vcc

T197

Figure 16-27. C0 to C2 to C0 Timings

CPU I/F

Signals

Unlatched

Latched

Unlatched

STPCLK#

T204

T205

T206

Break

Event

16-28

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Electrical Characteristics

Figure 16-28. C0 to C3 to C0 Timings (82801BAM ICH2-M only)

CPU I/F

Signals

Unlatched

Latched

STPCLK#

T206

T190

T204

PCI Stop

Grant Cycle

C3_STAT#

CPU_SLP#

STP_CPU#

T203

T188a

T188b

T208

Break

Event

T192a

ICH2_C0_C3_Timing.vsd

T207

82801BA ICH2 and 82801BAM ICH2-M Datasheet

16-29

Electrical Characteristics

This page is intentionally left blank.

16-30

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Testability

17.1

Test Mode Description

The ICH2 supports two types of test modes, a tri-state test mode and a XOR Chain test mode.

Driving RTCRST# low for a specific number of PCI clocks while PWROK is high activates a

particular test mode as described in Table 17-1.

Note: RTCRST# can be driven low any time after PCIRST# is inactive.

Table 17-1. Test Mode Selection

Number of PCI Clocks RTCRST# driven low after

Test Mode

PWROK active

No Test Mode Selected

XOR Chain 1

XOR Chain 2

XOR Chain 3

XOR Chain 4

All “Z”

9 - 24

>24

Reserved. DO NOT ATTEMPT

No Test Mode Selected

Figure 17-1 illustrates the entry into a test mode. A particular test mode is entered upon the rising

edge of the RTCRST# after being asserted for a specific number of PCI clocks while PWROK is

active. To change test modes, the same sequence should be followed again. To restore the ICH2 to

normal operation, execute the sequence with RTCRST# being asserted so that no test mode is

selected as specified in Table 17-1.

Figure 17-1. Test Mode Entry (XOR Chain Example)

RSMRST#

PWROK

RTCRST#

N Number of PCI Clocks

Test Mode Entered

Other Signal

Outputs

All Output Signals Tri-Stated

XOR Chain Output Enabled

82801BA ICH2 and 82801BAM ICH2-M Datasheet

17-1

Testability

17.2

Tri-state Mode

When in the tri-state mode, all outputs and bi-directional pin are tri-stated, including the XOR

Chain outputs.

17.3

XOR Chain Mode

In the ICH2, provisions for Automated Test Equipment (ATE) board level testing are implemented

with XOR Chains. The ICH2 signals are grouped into four independent XOR chains which are

enabled individually. When an XOR chain is enabled, all output and bi-directional buffers within

that chain are tri-stated, except for the XOR chain output. Every signal in the enabled XOR chain

(except for the XOR chain’s output) functions as an input. All output and bi-directional buffers for

pins not in the selected XOR chain are tri-stated. Figure 17-2 is a schematic example of XOR chain

circuitry.

Table 17-3 - Table 17-6 list each XOR chain pin ordering, with the first value being the first input

and the last value being the XOR chain output. Table 17-7 lists the signal pins not included in any

XOR chain.

Figure 17-2. Example XOR Chain Circuitry

Vcc

XOR

Chain

Output

Input

Pin 1

Input

Pin 3

Input

Pin 2

Input

Pin 4

Input

Pin 5

Input

Pin 6

17.3.1

XOR Chain Testability Algorithm Example

XOR chain testing allows motherboard manufacturers to check component connectivity (e.g.,

opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 17-2.

Table 17-2. XOR Test Pattern Example

Input

Pin 1

Input

Pin 2

Input

Pin 3

Input

Pin 4

Input

Pin 5

Input

Pin 6

XOR

Output

Vector

17-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Testability

In this example, Vector 1 applies all "0s" to the chain inputs. The outputs being non-inverting, will

consistently produce a "1" at the XOR output on a good board. One short to Vcc (or open floating

to Vcc) will result in a "0" at the chain output, signaling a defect.

Likewise, applying Vector 7 (all "1s") to the chain inputs (given that there are an even number of

input signals in the chain), will consistently produce a "1" at the XOR chain output on a good

board. One short to Vss (or open floating to Vss) will result in a "0" at the chain output, signaling a

defect. It is important to note that the number of inputs pulled to "1" will affect the expected chain

output value. If the number of chain inputs pulled to "1" is even, then expect "1" at the output. If

the number of chain inputs pulled to "1" is odd, expect "0" at the output.

Continuing with the example in Table 17-2, as the input pins are driven to "1" across the chain in

sequence, the XOR Output will toggle between "0" and "1." Any break in the toggling sequence

(e.g., "1011") will identify the location of the short or open.

17.3.1.1

Test Pattern Consideration for XOR Chain 4

When the ICH2 is operated with the Hub Interface in "Normal" mode (See Section 2.20.1), the

HL_STB and HL_STB# signals must always be driven to complementary logic levels. For

example, if a "1" is driven on HL_STB, then a "0" must be driven on HL_STB# and vice versa.

This will need to be considered in applying test patterns to this chain.

When the ICH2 is operated with the Hub Interface in "Enhanced" mode there are no restrictions on

the values that may be driven onto the HL_STB and HL_STB# signals.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

17-3

Testability

Table 17-3. XOR Chain #1 (RTCRST# Asserted for 4 PCI Clocks while PWROK Active)

Pin Name

LAN_TXD0

Ball #

Notes

Pin Name

REQ2#

Ball #

Notes

Top of XOR Chain

2nd signal in XOR

LAN_TXD1

LAN_TXD2

LAN_RXD0

LAN_RXD1

LAN_RXD2

EE_DOUT

EE_SHCLK

EE_CS

GNT2#

GNT3#

AD26

AD30

AD28

AD18

AD22

AD16

STOP#

EE_DIN

GPIO21 (ICH2)

C3_STAT#/

GPIO21

PAR

(ICH2-M)

GPIO16 / GNTA#

FRAME#

AD20

GPIO1 / REQB# /

REQ5#

GPIO17 / GNTB# /

GNT5#

AD15

GNT1#

TRDY#

AD11

AD13

AD4

GNT0#

GPIO0 / REQA#

PIRQH#

GPIO4 / PIRQG#

GPIO3 / PIRQF#

PIRQE#

AD9

C/BE0#

AD2

AA3

PIRQD#

AD6

AB3

AA4

PIRQA#

AD3

PIRQB#

AD0

PIRQC#

AD5

REQ4#

AD10

AD7

AA5

GNT4#

Last in XOR Chain

XOR Chain #1

OUTPUT

REQ0#

REQ1#

AC_SDIN1

W22

17-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Testability

Table 17-4. XOR Chain #2 (RTCRST# Asserted for 5 PCI clocks while PWROK Active)

Pin Name

Ball #

Notes

Pin Name

LDRQ1#

Ball #

Notes

AD1

AB4

Top of XOR Chain

2nd signal in XOR

W13

AB14

AA14

Y14

AD12

GPIO27

GPIO28

GPIO8

AD8

AB5

AA6

SERR#

AD14

GPIO12

GPIO13

PCIRST#

PME#

W14

AB15

AA15

Y15

PERR#

C/BE1#

DEVSEL#

PLOCK#

C/BE2#

IRDY#

AB6

AB7

AA7

GPIO25

SMBCLK

SMBDATA

W15

AB16

AA16

SMBALERT# /

GPIO11

AD17

AA8

AB17

AD19

AB8

RI#

AA17

AB18

Y17

AD23

SLP_S5#

SUSSTAT#

SLP_S3#

SUSCLK

USBP0P

USBP0N

USBP1P

USBP1N

AD21

C/BE3#

AD25

AA9

AB9

W10

Y10

AA10

AB10

W16

AA18

W17

Y18

AD27

AD29

AD31

AB19

AA19

REQ3#

GPIO6 (ICH2)

Y11

USBP2P

W18

AGPBUSY#

(ICH2-M)

GPIO7

AA11

AB11

AB12

AA12

Y12

USBP2N

USBP3P

USBP3N

OC0#

Y19

AB20

AA20

W19

Y20

LFRAME# / FWH4

LAD3 / FWH3

FS0

LAD0 / FWH0

LAD1 / FWH1

LAD2 / FWH2

THRM#

OC1#

W12

OC2#

Y21

AB13

AA13

OC3#

W20

XOR Chain #2

OUTPUT

TP0 (ICH2)

LDRQ0#

Y13

U20

BATLOW#

(ICH2-M)

82801BA ICH2 and 82801BAM ICH2-M Datasheet

17-5

Testability

Table 17-5. XOR Chain #3 (RTCRST# Asserted for 6 PCI Clocks while PWROK Active)

Pin Name

AC_SDIN0

Ball #

Notes

Pin name

PDD14

Ball #

Notes

Y22

W21

U19

V20

W22

Top of XOR Chain

2nd signal in XOR

H21

H19

G22

G21

H20

PWRBTN#

SMLINK0

SMLINK1

AC_SDIN1

TP0 (ICH2)

PDD0

PDDREQ

PDIOW#

PDD15

U20

V22

V21

PDDACK#

PDA2

F22

E22

F21

BATLOW#

(ICH2-M)

AC_RST#

GPIO24 (ICH2)

IRQ14

CLKRUN#

(ICH2-M)

AC_SDOUT

AC_SYNC

FERR#

APICD0

APICD1

SERIRQ

SPKR

P21

P19

R22

P22

N19

N21

N22

M21

M22

L22

L21

L20

K22

K21

K20

J20

J22

J21

H22

J19

SDD6

D22

G20

E21

G19

F20

D21

C22

F19

E20

C21

D20

C20

E19

B20

D19

C19

A20

PIORDY

PDCS1#

PDIOR#

PDA0

SDD8

SDD9

PDD6

PDA1

PDD7

SDD7

PDD8

SDD5

PDD9

SDD10

SDD4

PDD5

PDD10

PDD4

PDCS3#

SDD11

SDD2

PDD11

PDD13

PDD3

SDD12

SDD3

Last in XOR Chain

XOR Chain #3

OUTPUT

PDD12

PDD1

RI#

AA17

PDD2

17-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Testability

Table 17-6. XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks while PWROK Active)

Pin Name

SDD13

Ball #

Notes

Pin Name

INIT#

Ball #

Notes

A19

B19

C18

D18

D17

B18

C17

A18

D16

B17

C16

A17

B16

Top of XOR Chain

2nd signal in XOR

C12

B12

A12

A11

B11

C11

D11

C10

SDD1

SMI#

SDD14

SDD0

CPUSLP#

IGNNE#

NMI

SDIOR#

SDDREQ

SDIOW#

SDD15

SDA1

INTR

A20M#

STPCLK#

HL7

SDDACK#

IRQ15

HL5

HL6

SIORDY

SDA2

HL4

HL8

See

SDCS3#

D15

HL10

Section 17.3.1.1

See

SDA0

A16

C15

HL_STB#

HL_STB

Section 17.3.1.1

SDCS1#

VRMPWRGD

(ICH2)

B15

HL9

VRMPWRGD /

VGATE (ICH2-M)

GPIO18 (ICH2)

A15

D14

C14

B14

A14

HL2

STP_PCI#

(ICH2-M)

GPIO19 (ICH2)

HL1

SLP_S1#

(ICH2-M)

GPIO20 (ICH2)

HL0

STP_CPU#

(ICH2-M)

GPIO22 (ICH2)

HL11

HLCOMP

CPUPERF#

(ICH2-M)

GPIO23 (ICH2)

Last in XOR Chain

SSMUXSEL#

(ICH2-M)

A20GATE

RCIN#

C13

B13

XOR Chain #4

OUTPUT

OC0#

W19

CPUPWRGD

A13

82801BA ICH2 and 82801BAM ICH2-M Datasheet

17-7

Testability

Table 17-7. Signals Not in XOR Chain

Pin Name

RSMRST#

Ball #

Notes

Pin Name

CLK14

Ball #

Notes

R21

R20

U22

T22

T21

T20

M19

P20

PWROK

RTCX1

RTCX2

VBIAS

CLK48

CLK66

APICCLK

PCICLK

INTRUDER#

N20

W11

T19

RTCRST#

RSM_PWROK

(ICH2)

LAN_CLK

Y16

LAN_PWROK

(ICH2-M)

AC_BITCLK

R19

17-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

I/O Register Index

Table A-1. ICH2 Fixed I/O Registers

Port

EDS Section and Location

Channel 0 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

00h

Channel 0 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

01h

02h

03h

04h

05h

06h

07h

Channel 1 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

Channel 1 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

Channel 2 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

Channel 2 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

Channel 3 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

Channel 3 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

Section 9.2.4, “DMACMD—DMA Command Register”

on page 9-26

Channel 0–3 DMA Command

08h

Section 9.2.5, “DMASTS—DMA Status Register” on

page 9-26

Channel 0–3 DMA Status Register

Channel 0–3 DMA Write Single

Mask Register

Section 9.2.6, “DMA_WRSMSK—DMA Write Single

Mask Register” on page 9-27

0Ah

0Bh

0Ch

0Dh

0Eh

Channel 0–3 DMA Channel Mode

Section 9.2.7, “DMACH_MODE—DMA Channel Mode

Channel 0–3 DMA Clear Byte

Pointer Register

Section 9.2.8, “DMA Clear Byte Pointer Register” on

page 9-28

Channel 0–3 DMA Master Clear

Section 9.2.9, “DMA Master Clear Register” on

page 9-28

Channel 0–3 DMA Clear Mask

Section 9.2.10, “DMA_CLMSK—DMA Clear Mask

Channel 0–3 DMA Write All Mask

Section 9.2.11, “DMA_WRMSK—DMA Write All Mask

0Fh

Aliased at 00h–0Fh

10h–1Fh

Master PIC ICW1 Init. Cmd Word 1

Section 9.4.2, “ICW1—Initialization Command Word 1

Master PIC OCW2 Op Ctrl Word 2

Section 9.4.8, “OCW2—Operational Control Word 2

20h

Master PIC OCW3 Op Ctrl Word 3

Section 9.4.9, “OCW3—Operational Control Word 3

82801BA ICH2 and 82801BAM ICH2-M Datasheet

A-1

I/O Register Index

Table A-1. ICH2 Fixed I/O Registers (Continued)

Port

EDS Section and Location

Master PIC ICW2 Init. Cmd Word 2

Section 9.4.3, “ICW2—Initialization Command Word 2

Master PIC ICW3 Init. Cmd Word 3

Section 9.4.4, “ICW3—Master Controller Initialization

Command Word 3 Register” on page 9-35

21h

Master PIC ICW4 Init. Cmd Word 4

Section 9.4.6, “ICW4—Initialization Command Word 4

Master PIC OCW1 Op Ctrl Word 1

Section 9.4.7, “OCW1—Operational Control Word 1

(Interrupt Mask) Register” on page 9-36

Aliased at 20h–21h

24h–25h

28h–29h

24h–25h

2Ch–2Dh

30h–31h

34h–35h

38h–39h

3Ch–3Dh

Counter 0 Interval Time Status Byte

Format

Section 9.3.2, “SBYTE_FMT—Interval Timer Status

Byte Format Register” on page 9-32

40h

41h

42h

Counter 0 Counter Access Port

Section 9.3.3, “Counter Access Ports Register” on

page 9-32

Counter 1 Interval Time Status Byte

Format

Section 9.3.2, “SBYTE_FMT—Interval Timer Status

Byte Format Register” on page 9-32

Counter 1 Counter Access Port

Section 9.3.3, “Counter Access Ports Register” on

page 9-32

Counter 2 Interval Time Status Byte

Format

Section 9.3.2, “SBYTE_FMT—Interval Timer Status

Byte Format Register” on page 9-32

Counter 2 Counter Access Port

Section 9.3.3, “Counter Access Ports Register” on

page 9-32

Section 9.3.1, “TCW—Timer Control Word Register” on

page 9-30

Timer Control Word Register

Section 9.3.1.1, “RDBK_CMD—Read Back Command”

on page 9-31

Timer Control Word Register Read

Back

43h

Section 9.3.1.2, “LTCH_CMD—Counter Latch

Command” on page 9-31

Counter Latch Command

Aliased at 40h–43h

50h–53h

61h

Section 9.7.1, “NMI_SC—NMI Status and Control

NMI Status and Control Register

Section 9.7.2, “NMI_EN—NMI Enable (and Real Time

Clock Index)” on page 9-52

NMI Enable Register

70h

71h

Table 9-7 “RTC (Standard) RAM Bank” on page 9-47

Real-Time Clock (Standard RAM)

Index Register

Section 9.7.2, “NMI_EN—NMI Enable (and Real Time

Clock Index)” on page 9-52

Real-Time Clock (Standard RAM)

Target Register

Table 9-7 “RTC (Standard) RAM Bank” on page 9-47

Extended RAM Index Register

Extended RAM Target Register

72h

73h

A-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

I/O Register Index

Table A-1. ICH2 Fixed I/O Registers (Continued)

Port

EDS Section and Location

Aliased if U128E bit in RTC Configuration Register is

enabled

Aliased at 70h–71h

74h–75h

Section 9.1.24, “RTC_CONF—RTC Configuration

Aliased to 70h–71h if U128E bit in RTC Configuration

Aliased at 72h–73h or 70h–71h

76h–77h

Section 9.1.24, “RTC_CONF—RTC Configuration

Channel 2 DMA Memory Low Page

Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page

Registers” on page 9-25

81h

82h

Channel 3 DMA Memory Low Page

Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page

Registers” on page 9-25

Channel 1 DMA Memory Low Page

Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page

Registers” on page 9-25

83h

84h–86h

87h

Reserved Page Registers

Channel 0 DMA Memory Low Page

Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page

Registers” on page 9-25

Reserved Page Register

88h

Channel 6 DMA Memory Low Page

Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page

Registers” on page 9-25

89h

Channel 7 DMA Memory Low Page

Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page

Registers” on page 9-25

8Ah

8Bh

Channel 5 DMA Memory Low Page

Section 9.2.3, “DMAMEM_LP—DMA Memory Low Page

Registers” on page 9-25

Reserved Page Registers

Refresh Low Page Register

8Ch–8Eh

8Fh

91h–9Fh

(except 92h)

Aliased at 81h–8Fh

Section 9.7.3, “PORT92—Fast A20 and Init Register” on

page 9-52

Fast A20 and INIT Register

92h

A0h

Slave PIC ICW1 Init. Cmd Word 1

Section 9.4.2, “ICW1—Initialization Command Word 1

Slave PIC OCW2 Op Ctrl Word 2

Section 9.4.8, “OCW2—Operational Control Word 2

Slave PIC OCW3 Op Ctrl Word 3

Section 9.4.9, “OCW3—Operational Control Word 3

Slave PIC ICW2 Init. Cmd Word 2

Section 9.4.3, “ICW2—Initialization Command Word 2

Slave PIC ICW3 Init. Cmd Word 3

Section 9.4.4, “ICW3—Master Controller Initialization

Command Word 3 Register” on page 9-35

Slave PIC ICW4 Init. Cmd Word 4

Section 9.4.6, “ICW4—Initialization Command Word 4

Slave PIC OCW1 Op Ctrl Word 1

Section 9.4.7, “OCW1—Operational Control Word 1

(Interrupt Mask) Register” on page 9-36

Aliased at A0h–A1h

A4h–A5h

A8h–A9h

ACh–ADh

B0h–B1h

82801BA ICH2 and 82801BAM ICH2-M Datasheet

A-3

I/O Register Index

Table A-1. ICH2 Fixed I/O Registers (Continued)

Port

EDS Section and Location

Advanced Power Management

Control Port Register

Section 9.8.2.1, “APM_CNT—Advanced Power

Management Control Port Register” on page 9-60

B2h

Advanced Power Management

Status Port Register

Section 9.8.2.2, “APM_STS—Advanced Power

Management Status Port Register” on page 9-60

B3h

Aliased at A0h–A1h

B4h–B5h

B8h–B9h

BCh–BDh

Channel 4 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

C0h

C1h

C2h

C3h

C4h

C5h

C6h

C7h

C8h

C9h

CAh

CBh

CCh

CDh

CEh

CFh

Aliased at C0h

Channel 4 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

Aliased at C2h

Channel 5 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

Aliased at C4h

Channel 5 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

Aliased at C6h

Channel 6 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

Aliased at C8h

Channel 6 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

Aliased at CAh

Channel 7 DMA Base & Current

Address Register

Section 9.2.1, “DMABASE_CA—DMA Base and Current

Address Registers” on page 9-24

Aliased at CCh

Channel 7 DMA Base & Current

Count Register

Section 9.2.2, “DMABASE_CC—DMA Base and Current

Count Registers” on page 9-25

Aliased at CEh

Section 9.2.4, “DMACMD—DMA Command Register”

on page 9-26

Channel 4–7 DMA Command

D0h

Section 9.2.5, “DMASTS—DMA Status Register” on

page 9-26

Channel 4–7 DMA Status Register

Aliased at D0h

D1h

D4h

D5h

D6h

D7h

D8h

D9h

Channel 4–7 DMA Write Single

Mask Register

Section 9.2.6, “DMA_WRSMSK—DMA Write Single

Mask Register” on page 9-27

Aliased at D4h

Channel 4–7 DMA Channel Mode

Section 9.2.7, “DMACH_MODE—DMA Channel Mode

Aliased at D6h

Channel 4–7 DMA Clear Byte

Pointer Register

Section 9.2.8, “DMA Clear Byte Pointer Register” on

page 9-28

Aliased at D8h

A-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

I/O Register Index

Table A-1. ICH2 Fixed I/O Registers (Continued)

Port

EDS Section and Location

Channel 4–7 DMA Master Clear

Section 9.2.9, “DMA Master Clear Register” on

page 9-28

DAh

DBh

DCh

DEh

DFh

F0h

Aliased at DAh

Channel 4–7 DMA Clear Mask

Section 9.2.10, “DMA_CLMSK—DMA Clear Mask

Aliased at DCh

Channel 4–7 DMA Write All Mask

Section 9.2.11, “DMA_WRMSK—DMA Write All Mask

Aliased at DEh

Section 9.7.4, “COPROC_ERR—Coprocessor Error

Coprocessor Error Reigster

PIO Mode Command Block Offset

for Secondary Drive

170h–177h See ATA Specification for detailed register description

1F0h–1F7h See ATA Specification for detailed register description

PIO Mode Command Block Offset

for Primary Drive

PIO Mode Control Block Offset for

Secondary Drive

376h

3F6h

4D0h

4D1h

CF9h

See ATA Specification for detailed register description

PIO Mode Control Block Offset for

Primary Drive

Master PIC Edge/Level Triggered

Section 9.4.10, “ELCR1—Master Controller Edge/Level

Triggered Register” on page 9-39

Slave PIC Edge/Level Triggered

Section 9.4.11, “ELCR2—Slave Controller Edge/Level

Triggered Register” on page 9-40

Section 9.7.5, “RST_CNT—Reset Control Register” on

page 9-53

Reset Control Register

NOTE: When the POS_DEC_EN bit is set, additional I/O ports get positively decoded by the ICH2. Refer to

through for a listing of these ranges.

82801BA ICH2 and 82801BAM ICH2-M Datasheet

A-5

I/O Register Index

Table A-2. ICH2 Variable I/O Registers

Offset

EDS Section and Location

LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space.

LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in

Section 7.1.11, “CSR_MEM_BASE CSR—Memory-Mapped Base Address Register (LAN Controller—

B1:D8:F0)” on page 7-5 CSR_IO_BASE set in Section 7.1.12, “CSR_IO_BASE—CSR I/O-Mapped Base

Address Register (LAN Controller—B1:D8:F0)” on page 7-5

Section 7.2.1, “System Control Block Status Word

SCB Status Word

01h–00h

03h–02h

Section 7.2.2, “System Control Block Command Word

SCB Command Word

Section 7.2.3, “System Control Block General Pointer

SCB General Pointer

PORT

07h–04h

OBh–08h

0Fh–0Eh

Section 7.2.4, “PORT Register” on page 7-14

Section 7.2.5, “EEPROM Control Register” on

page 7-15

EEPROM Control Register

Section 7.2.6, “Management Data Interface (MDI)

Control Register” on page 7-16

MDI Control Register

13h–10h

17h–14h

Section 7.2.7, “Receive DMA Byte Count Register” on

page 7-16

Receive DMA Byte Count

Section 7.2.8, “Early Receive Interrupt Register” on

page 7-17

Early Receive Interrupt

Flow Control Register

PMDR

18h

1Ah–19h

1Bh

Section 7.2.9, “Flow Control Register” on page 7-18

Section 7.2.10, “Power Management Driver (PMDR)

Section 7.2.11, “General Control Register” on

page 7-19

General Control

General Status

1Ch

1Dh

Section 7.2.12, “General Status Register” on

page 7-20

Power Management I/O Registers at PMBASE+Offset

PMBASE set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-6

Section 9.8.3.1, “PM1_STS—Power Management 1

Status Register” on page 9-62

PM1 Status

00–01h

02–03h

04–07h

08–0Bh

10h–13h

14h

Section 9.8.3.2, “PM1_EN—Power Management 1

Enable Register” on page 9-64

PM1 Enable

Section 9.8.3.3, “PM1_CNT—Power Management 1

Control Register” on page 9-65

PM1 Control

Section 9.8.3.4, “PM1_TMR—Power Management 1

Timer Register” on page 9-66

PM1 Timer

Section 9.8.3.5, “PROC_CNT—Processor Control

Processor Control

Section 9.8.3.6, “LV2—Level 2 Register” on

page 9-67

Level 2 Register

Section 9.8.3.9, “GPE0_STS—General Purpose

Event 0 Status Register” on page 9-68

General Purpose Event 0 Status

General Purpose Event 0 Enables

General Purpose Event 1 Status

General Purpose Event 1 Enables

28–29h

2A–2Bh

2C–2D

2E–2F

Section 9.8.3.10, “GPE0_EN—General Purpose

Event 0 Enables Register” on page 9-70

Section 9.8.3.11, “GPE1_STS—General Purpose

Event 1 Status Register” on page 9-71

Section 9.8.3.12, “GPE1_EN—General Purpose

Event 1 Enable Register” on page 9-72

A-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

I/O Register Index

Table A-2. ICH2 Variable I/O Registers (Continued)

Offset

EDS Section and Location

Section 9.8.3.13, “SMI_EN—SMI Control and Enable

SMI# Control and Enable

30–31h

Section 9.8.3.14, “SMI_STS—SMI Status Register”

on page 9-74

SMI Status Register

Monitor SMI Status

Device Activity Status

Device Trap Enable

Bus Address Tracker

Bus Cycle Tracker

34–35h

40h

Section 9.8.3.15, “MON_SMI—Device Monitor SMI

Status and Enable Register” on page 9-75

Section 9.8.3.16, “DEVACT_STS—Device Activity

Status Register” on page 9-76

44h

Section 9.8.3.17, “DEVTRAP_EN—Device Trap

Enable Register” on page 9-77

48h

Section 9.8.3.18, “BUS_ADDR_TRACK—Bus

Address Tracker Register” on page 9-78

4Ch

4Eh

Section 9.8.3.19, “BUS_CYC_TRACK—Bus Cycle

Tracker Register” on page 9-78

TCO I/O Registers at TCOBASE + Offset

TCOBASE = PMBASE + 40h

PMBASE is set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-6

TCO_RLD: TCO Timer Reload and

Current Value

Section 9.9.2, “TCO1_RLD—TCO Timer Reload and

Current Value Register” on page 9-79

00h

01h

Section 9.9.3, “TCO1_TMR—TCO Timer Initial Value

TCO_TMR: TCO Timer Initial Value

TCO_DAT_IN: TCO Data In

TCO_DAT_OUT: TCO Data Out

TCO1_STS: TCO Status

Section 9.9.4, “TCO1_DAT_IN—TCO Data In

02h

Section 9.9.5, “TCO1_DAT_OUT—TCO Data Out

03h

Section 9.9.6, “TCO1_STS—TCO1 Status Register”

on page 9-80

04h–05h

06h–07h

08h–09h

0Ah–0Bh

Section 9.9.7, “TCO2_STS—TCO2 Status Register”

on page 9-82

TCO2_STS: TCO Status

Section 9.9.8, “TCO1_CNT—TCO1 Control Register”

on page 9-83

TCO1_CNT: TCO Control

TCO2_CNT: TCO Control

Section 9.9.9, “TCO2_CNT—TCO2 Control Register”

on page 9-83

GPIO I/O Registers at GPIOBASE + Offset

GPIOBASE is set in Section 9.1.14, “GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)” on page 9-8

Section 9.10.2, “GPIO_USE_SEL—GPIO Use Select

GPIO Use Select

00–03h

04–07h

0C–0Fh

18–1Bh

2C–2Fh

Section 9.10.3, “GP_IO_SEL—GPIO Input/Output

Select Register” on page 9-88

GPIO Input/Output Select

GPIO Level for Input or Output

GPIO Blink Enable

Section 9.10.4, “GP_LVL—GPIO Level for Input or

Output Register” on page 9-89

Section 9.10.5, “GPO_BLINK—GPO Blink Enable

Section 9.10.6, “GPI_INV—GPIO Signal Invert

GPIO Signal Invert

82801BA ICH2 and 82801BAM ICH2-M Datasheet

A-7

I/O Register Index

Table A-2. ICH2 Variable I/O Registers (Continued)

Offset

EDS Section and Location

BMIDE I/O Registers at BM_BASE + Offset

BM_BASE is set at Section 10.1.10, “BM_BASE—Bus Master Base Address Register (IDE—D31:F1)” on

page 10-4

Section 10.2.1, “BMIC[P,S]—Bus Master IDE

Command Register” on page 10-11

Command Register Primary

Status Register Primary

00h

02h

Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status

Section 10.2.3, “BMID[P,S]—Bus Master IDE

Descriptor Table Pointer Register” on page 10-12

Descriptor Table Pointer Primary

Command Register Secondary

Status Register Secondary

04h–07h

08h

Section 10.2.1, “BMIC[P,S]—Bus Master IDE

Command Register” on page 10-11

Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status

0Ah

Section 10.2.3, “BMID[P,S]—Bus Master IDE

Descriptor Table Pointer Register” on page 10-12

Descriptor Table Pointer Secondary

0Ch–0Fh

USB I/O Registers at Base Address + Offset

USB Base Address is set at Section 11.1.9, “BASE—Base Address Register (USB—D31:F2/F4)” on

page 11-4

Section 11.2.1, “USBCMD—USB Command Register”

on page 11-8

USB Command Register

USB Status Register

00h–01h

02h–03h

04h–05h

06h–07h

08h–0Bh

0Ch

Section 11.2.2, “USBSTA—USB Status Register” on

page 11-11

Section 11.2.3, “USBINTR—Interrupt Enable

USB Interrupt Enable

Section 11.2.4, “FRNUM—Frame Number Register”

on page 11-12

USB Frame Number

Section 11.2.5, “FRBASEADD—Frame List Base

Address” on page 11-13

USB Frame List Base Address

USB Start of Frame Modify

Port 0, 2 Status/Control

Section 11.2.6, “SOFMOD—Start of Frame Modify

Section 11.2.7, “PORTSC[0,1]—Port Status and

Control Register” on page 11-14

10h–11h

Section 11.2.7, “PORTSC[0,1]—Port Status and

Control Register” on page 11-14

Port 1, 3 Status/Control

Loop Back Test Data

12h–13h

18h

SMBus I/O Registers at SMB_BASE + Offset

SMB_BASE is set at Section 12.1.9, “SMB_BASE—SMBus Base Address Register (SMBUS—D31:F3)” on

page 12-4

Section 12.2.1, “HST_STS—Host Status Register” on

page 12-7

Host Status

00h

02h

03h

04h

05h

06h

Section 12.2.2, “HST_CNT—Host Control Register”

on page 12-8

Host Control

Section 12.2.3, “HST_CMD—Host Command

Host Command

Transmit Slave Address

Host Data 0

Section 12.2.4, “XMIT_SLVA—Transmit Slave

Address Register” on page 12-9

Section 12.2.5, “HST_D0—Data 0 Register” on

page 12-9

Section 12.2.6, “HST_D1—Data 1 Register” on

page 12-9

Host Data 1

A-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

I/O Register Index

Table A-2. ICH2 Variable I/O Registers (Continued)

Offset

EDS Section and Location

Section 12.2.7, “BLOCK_DB—Block Data Byte

Block Data Byte

07h

Section 12.2.8, “RCV_SLVA—Receive Slave Address

Receive Slave Address

Receive Slave Data

09h

0Ah

Section 12.2.9, “SLV_DATA—Receive Slave Data

AC’97 Audio I/O Registers at NAMBAR + Offset

NAMBAR is set at Section 13.1.11, “NABMBAR—Native Audio Bus Mastering Base Address Register

(Audio—D31:F5)” on page 13-5

PCM In Buffer Descriptor list Base

Address Register

Section 13.2.1, “x_BDBAR—Buffer Descriptor Base

Address Register” on page 13-9

00h

04h

05h

06h

08h

0Ah

0Bh

10h

14h

15h

16h

18h

1Ah

1Bh

20h

24h

25h

26h

28h

2Ah

2Bh

Section 13.2.2, “x_CIV—Current Index Value

PCM In Current Index Value

PCM In Last Valid Index

Section 13.2.3, “x_LVI—Last Valid Index Register” on

page 13-10

Section 13.2.4, “x_SR—Status Register” on

page 13-11

PCM In Status Register

Section 13.2.5, “x_PICB—Position In Current Buffer

PCM In Position In Current Buffer

PCM In Prefetched Index Value

PCM In Control Register

Section 13.2.6, “x_PIV—Prefetched Index Value

Section 13.2.7, “x_CR—Control Register” on

page 13-13

PCM Out Buffer Descriptor list Base

Address Register

Section 13.2.1, “x_BDBAR—Buffer Descriptor Base

Address Register” on page 13-9

Section 13.2.2, “x_CIV—Current Index Value

PCM Out Current Index Value

PCM Out Last Valid Index

Section 13.2.3, “x_LVI—Last Valid Index Register” on

page 13-10

Section 13.2.4, “x_SR—Status Register” on

page 13-11

PCM Out Status Register

Section 13.2.5, “x_PICB—Position In Current Buffer

PCM Out Position In Current Buffer

PCM Out Prefetched Index Value

PCM Out Control Register

Section 13.2.6, “x_PIV—Prefetched Index Value

Section 13.2.7, “x_CR—Control Register” on

page 13-13

Mic. In Buffer Descriptor list Base

Address Register

Section 13.2.1, “x_BDBAR—Buffer Descriptor Base

Address Register” on page 13-9

Section 13.2.2, “x_CIV—Current Index Value

Mic. In Current Index Value

Mic. In Last Valid Index

Section 13.2.3, “x_LVI—Last Valid Index Register” on

page 13-10

Section 13.2.4, “x_SR—Status Register” on

page 13-11

Mic. In Status Register

Section 13.2.5, “x_PICB—Position In Current Buffer

Mic In Position In Current Buffer

Mic. In Prefetched Index Value

Mic. In Control Register

Section 13.2.6, “x_PIV—Prefetched Index Value

Section 13.2.7, “x_CR—Control Register” on

page 13-13

82801BA ICH2 and 82801BAM ICH2-M Datasheet

A-9

I/O Register Index

Table A-2. ICH2 Variable I/O Registers (Continued)

Offset

EDS Section and Location

Section 13.2.8, “GLOB_CNT—Global Control

Global Control

2Ch

Section 13.2.9, “GLOB_STA—Global Status Register”

on page 13-15

Global Status

30h

34h

Section 13.2.10, “CAS—Codec Access Semaphore

Codec Access Semaphore Register

AC’97 Modem I/O Registers at MBAR + Offset

MBAR is set in Section 14.1.11, “MBAR—Modem Base Address Register (Modem—D31:F6)” on

page 14-5

Modem In Buffer Descriptor List Base

Address Register

Section 14.2.1, “x_BDBAR—Buffer Descriptor List

Base Address Register” on page 14-8

00h

04h

05h

06h

08h

0Ah

0Bh

10h

14h

15h

16h

18h

1Ah

1Bh

3Ch

40h

44h

Modem In Current Index Value

Section 14.2.2, “x_CIV—Current Index Value

Section 14.2.3, “x_LVI—Last Valid Index Register” on

page 14-9

Modem In Last Valid Index Register

Modem In Status Register

Section 14.2.4, “x_SR—Status Register” on

page 14-10

Modem In Position In Current Buffer

Section 14.2.5, “x_PICB—Position In Current Buffer

Modem In Prefetch Index Value

Section 14.2.6, “x_PIV—Prefetch Index Value

Section 14.2.7, “x_CR—Control Register” on

page 14-11

Modem In Control Register

Modem Out Buffer Descriptor List

Base Address Register

Section 14.2.1, “x_BDBAR—Buffer Descriptor List

Base Address Register” on page 14-8

Modem Out Current Index Value

Section 14.2.2, “x_CIV—Current Index Value

Section 14.2.3, “x_LVI—Last Valid Index Register” on

page 14-9

Modem Out Last Valid Register

Modem Out Status Register

Section 14.2.4, “x_SR—Status Register” on

page 14-10

Modem In Position In Current Buffer

Section 14.2.5, “x_PICB—Position In Current Buffer

Modem Out Prefetched Index

Section 14.2.6, “x_PIV—Prefetch Index Value

Section 14.2.7, “x_CR—Control Register” on

page 14-11

Modem Out Control Register

Global Control

Section 14.2.8, “GLOB_CNT—Global Control

Section 14.2.9, “GLOB_STA—Global Status Register”

on page 14-13

Global Status

Section 14.2.10, “CAS—Codec Access Semaphore

Codec Access Semaphore Register

A-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Numerics

4 Channel Capability 13-15, 14-13

6 Channel Capability 13-15, 14-13

A20Gate Pass-Through Enable

(A20PASSEN) 11-6

AC ‘97 Cold Reset# 13-14

AC ‘97 Interrupt Routing 14-6

AC ’97 Interrupt Routing 13-7

AC‘97 Cold Reset# 14-12

AC’97 Warm Reset 13-14, 14-12

AC97_EN 9-66

Base Address 7-5, 9-6, 9-8, 10-4, 11-4, 11-13,

12-3, 13-5, 14-5

Base address of Descriptor table (BADDR)

10-12

Base and Current Address 9-24

Base and Current Count 9-25

Base Class Code 7-4, 8-5, 9-5, 10-4, 11-4,

12-3, 13-4

Base Class Code Value 14-4

Binary/BCD Countdown Select 9-30

BIOS_EN 9-69

AC97_STS 9-65

ACLINK Shut Off 13-14, 14-12

ACPI_EN 9-6

BIOS_RLS BIOS Release 9-69

BIOS_STS 9-71

BIOSWE BIOS Write Enable 9-7

BIOSWR_STS 9-77

AD3 13-15, 14-13

ADDRESS 12-8

Bit 1 of slot 12 13-15, 14-13

Bit 2 of slot 12 13-15, 14-13

Bit 3 of slot 12 13-15, 14-13

BLE BIOS Lock Enable 9-7

Block Data Byte 12-9

Address Increment/Decrement Select 9-27

ADLIB_ACT_STS 9-72

ADLIB_LPC_EN 9-18

ADLIB_TRP_EN 9-73

AF Alarm Flag 9-50

BOOT_STS 9-78

AFTERG3_EN 9-55

Buffer Completion Interrupt Status (BCIS)

13-11, 14-10

AIE Alarm Interrupt Enable 9-49

ALT_A20_GATE 9-52

ALTACC_EN Alternate Access Mode Enable

9-12

APIC Data 9-42

APIC ID 9-43

Buffer Descriptor Base Address 13-9

Buffer Descriptor List Base Address 14-8

Buffered Mode (BUF) 9-36

Bus Master Enable (BME) 7-2, 8-3, 10-2,

11-2, 13-2, 14-2

APIC Index 9-41

APIC_EN 9-12

Bus Master IDE Active (ACT) 10-12

BUS_ERR 12-6

APM_STS 9-71

APMC_EN 9-69

BYTE_DONE_STS 12-6

AUDIO_ACT_STS 9-72

AUDIO_TRP_EN 9-73

Autoinitialize Enable 9-27

Automatic End of Interrupt (AEOI) 9-36

Auxiliary Current 7-8

CAP_ID Capability ID 7-8

CAP_LIST Capabilities List 7-3

CAP_PTR Capabilities Pointer 7-6

Cascaded Interrupt Controller IRQ

Connection 9-35

Channel 0 Select 9-11

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Index-1

Channel 1 Select 9-11

Channel 2 Select. 9-11

Current Equals Last Valid (CELV) 13-11,

14-10

Channel 3 Select 9-11

Channel 5 Select 9-11

Channel 6 Select 9-11

Channel 7 Select 9-11

Current Index Value 13-10, 14-9

CUS Command Unit Status 7-11

CX Command Unit (CU) Executed 7-11

CX Mask 7-12

Channel Mask Bits 9-29

Channel Mask Select 9-27

Channel Request Status 9-26

Channel Terminal Count Status 9-26

Clear Byte Pointer 9-28

Clear Mask Register 9-28

CLS Cache Line Size 7-4

CNA CU Not Active 7-11

CNA Mask 7-12

D1 Support 7-8

D2 Support 7-8

Data 7-16

Data Parity Error Detected (DPD) 7-3, 8-4, 8-8

Data Scale 7-9

Data Select 7-9

DATA_MSG0 Data Message Byte 0 12-9

DATA_MSG1 Data Message Byte 1 12-9

DATA0/COUNT 12-8

CNF1_LPC_EN 9-17

CNF2_LPC_EN 9-17

DATA1 12-8

Codec Write In Progress (CWIP) 13-16

COMA Decode Range 9-14

COMA_LPC_EN 9-18

Date Alarm 9-50

DCB_EN DMA Collection Buffer Enable

9-12

COMB Decode Range 9-14

COMB_LPC_EN 9-18

Deep Power-Down on Link Down Enable

7-19

Configure Flag (CF) 11-9

Connect Status Change 11-15

COPR_ERR_EN Coprocessor Error Enable

9-11

Delivery Mode 9-46

Delivery Status 9-45

Destination 9-45

Destination Mode 9-45

COPROC_ERR 9-52

Detected Parity Error (DPE) 7-3, 8-4, 8-8

DEV_ERR 12-6

DEV_STS DEVSEL# Timing Status 9-4

DEV_TRAP_EN 9-71

Count Register Status 9-32

Countdown Type Status 9-32

Counter 0 Select 9-31

Counter 1 Select 9-31

DEV_TRAP_STS 9-71

Counter 2 Select 9-31

Device ID Value 9-2, 11-2, 13-2, 14-2

Device ID value 12-1

Counter Latch Command 9-31

Counter Mode Selection 9-30

Counter OUT Pin State 9-32

Counter Port 9-32

Counter Select 9-30

Counter Selection 9-31

Device Identification Number 7-2, 8-2

Device Specific Initialization (DSI) 7-8

DEVMON_STS Device Monitor Status 9-70

DEVSEL# Timing Status (DEVT) 10-3, 11-3,

12-2, 13-3

CPU_BIST_EN 9-13

DM Data Mode 9-49

CPUPWR_FLR CPU Power Failure 9-55

CPUSLP_EN 9-54

CUC Command Unit Command 7-13

Current Connect Status 11-15

DMA Channel Group Enable 9-26

DMA Channel Select 9-27

DMA Controller Halted (DCH) 13-11, 14-10

DMA Group Arbitration Priority 9-26

DMA Low Page 9-25

Index-2

82801BA ICH2 and 82801BAM ICH2-M Datasheet

DMA Transfer Mode 9-27

FAST_PCB0 Fast Primary Drive 0 Base

DMA Transfer Type 9-27

Clock 10-10

DPE Detected Parity Error 9-4

DPED Data Parity Error Detected 9-4

Drive 0 DMA Capable 10-12

Drive 0 DMA Timing Enable (DTE0) 10-6

Drive 0 Fast Timing Bank (TIME0) 10-7

Drive 0 IORDY Sample Point Enable (IE0)

10-7

FAST_PCB1 Fast Primary Drive 1 Base

Clock 10-9

FAST_SCB0 Fast Secondary Drive 0 Base

Clock 10-9

FAST_SCB1 Fast Secondary Drive 1 Base

Clock 10-9

FC Full 7-18

Drive 0 Prefetch/Posting Enable (PPE0) 10-7

Drive 1 DMA Capable 10-12

FC Paused 7-18

FC Paused Low 7-18

Drive 1 DMA Timing Enable (DTE1) 10-6

Drive 1 Fast Timing Bank (TIME1) 10-6

Drive 1 IORDY Sample Point Enable (IE1)

10-6

FCP Flow control Pause 7-11

FCP Mask 7-12

FDD Decode Range 9-15

FDD_LPC_EN 9-18

Drive 1 Prefetch/Posting Enable (PPE1) 10-6

FIFO error (FIFOE) 13-11, 14-10

Drive 1 Timing Register Enable (SITRE) 10-6 FIFO Error Interrupt Enable (FEIE) 13-13,

DSE Daylight Savings Enable 9-49

DT Delivery Type 9-44

DTE Delayed Transaction Enable 9-12

Duplex Mode 7-20

14-11

Flow Control Threshold 7-18

Force Global Resume (FGR) 11-9

FORCE_THTL 9-63

DV Division Chain Select 9-48

Dynamic Data 7-9

FR Frame Received 7-11

FR Mask 7-12

Frame List Current Index/Frame Number

11-12

FREQ_STRAP 9-13

Early Receive Count 7-17

Edge/Level Bank Select (LTIM) 9-34

EECS EEPROM Chip Select 7-15

EEDI EEPROM Serial Data In 7-15

EEDO EEPROM Serial Data Out 7-15

EESK EEPROM Serial Clock 7-15

Enable Special Mask Mode (ESMM) 9-38

Enter Global Suspend Mode (EGSM) 11-9

EOS End of SMI 9-69

ER Early Receive 7-11

ER Mask 7-12

FULL_RST 9-53

FWH_C0_EN 9-16, 9-21

FWH_C0_IDSEL 9-19

FWH_C8_EN 9-16, 9-21

FWH_C8_IDSEL 9-19

FWH_D0_EN 9-16, 9-21

FWH_D0_IDSEL 9-19

FWH_D8_EN 9-16, 9-21

FWH_D8_IDSEL 9-19, 9-20

FWH_E0_EN 9-16

Error 10-12

FWH_E0_IDSEL 9-19, 9-20

FWH_E8_EN 9-16

F1_Disable 9-22

F2_Disable 9-22

F3_Disable 9-22

FWH_E8_IDSEL 9-19, 9-20

FWH_F0_EN 9-16

F4_Disable 9-22

F5_Disable 9-22

FWH_F0_IDSEL 9-19, 9-20

FWH_F8_EN 9-16

F6_Disable 9-22

FWH_F8_IDSEL 9-19

FAILED 12-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Index-3

HUBSMI_STS 9-77

GAMEH_LPC_EN 9-17

GAMEL_LPC_EN 9-17

GBL _STS 9-61

GBL_EN 9-61

GBL_RLS Global Release 9-62

GBL_SMI_EN 9-69

I/O Address Base bits 8-7

I/O Address Limit bits 8-7

I/O Addressing Capability 8-7

I/O APIC Identification 9-44

I/O Space (IOS) 14-2

GEN1_BASE Generic I/O Decode Range 1

Base 9-17

GEN1_EN Generic Decode Range 1 Enable

9-17

I/O Space Enable (IOE) 7-2, 8-3

I/O Space Enable (IOSE) 11-2, 12-2

I2C_EN 12-4

iA64_EN

GEN2_BASE Generic I/O Decode Range 2

Base 9-20

iA64 Processor Mode Enable 9-54

ICW/OCW select 9-34

GEN2_EN Generic I/O Decode Range 2 En-

able 9-20

Global Reset (GRESET) 11-9

GPE0_STS 9-70

ICW4 Write Required (IC4) 9-34

IDE Decode Enable (IDE) 10-6

IDEP0_ACT_STS 9-73

IDEP0_TRP_EN 9-73

GPE1_STS 9-70

GPI Interrupt Enable (GIE) 13-14, 14-12

GPI Route 9-56

GPI Status Change Interrupt (GSCI) 13-16,

14-14

GPI_EN 9-68

IDEP1_ACT_STS 9-73

IDEP1_TRP_EN 9-73

IDES0_ACT_STS 9-72

IDES0_TRP_EN 9-73

IDES1_ACT_STS 9-72

IDES1_TRP_EN 9-73

GPI_STS 9-67

INIT_NOW 9-52

GPIO_EN 9-8

GPIO_SEL 9-84

GPIO_USE_SEL 9-83

HCHalted 11-11

Header Type 7-5, 9-5

Header Type Value 13-4

Header Value 14-4

INT_LN Interrupt Line 7-7

INT_PN Interrupt Pin 7-7

Interesting Packet 7-19

Internal LAN Master Request Status

(LAN_MREQ_STS) 8-13

Internal PCI Master Request Status

(INT_MREQ_STS) 8-13

Interrupt 10-12

HIDE_ISA Hide ISA Bridge 9-11

Hole Enable (15MB-16MB). 8-12

Host Controller Process Error 11-11

Host Controller Reset (HCRESET) 11-9

Host System Error 11-11

HOST_BUSY 12-6

Interrupt Enable 7-16

Interrupt Input Pin Polarity 9-45

Interrupt Level Select (L2, L1, L0) 9-37

Interrupt Line 11-5, 13-6, 14-6

Interrupt line 12-4

Interrupt On Complete (IOC) Enable 11-12

Interrupt On Completion Enable (IOCE)

13-13, 14-11

HOURFORM Hour Format 9-49

HP_PCI_EN 8-12

HST_EN SMBus Host Enable 12-4

HUBNMI_STS 9-76

Interrupt PIN 12-4

Interrupt pin 11-5

HUBSCI_STS 9-77

HUBSERR_STS 9-76

Interrupt Request Level 9-35

Interrupt Request Mask 9-36

Index-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Interrupt Vector Base Address 9-35

INTR 12-6

Last Valid Buffer Interrupt Enable (LVBIE)

13-13, 14-11

INTRD_DET Intruder Detect 9-78

INTRD_SEL 9-80

INTREN 12-7

Last Valid Index 13-10, 14-9

Latch Count of Selected Counters 9-31

Latch Status of Selected Counters 9-31

LEG_ACT_STS 9-72

INUSE_STS 12-6

IO Space Indicator 12-3

IOCHK_NMI_EN 9-51

IOCHK_NMI_STS IOCHK# NMI Source

Status 9-51

LEG_IO_TRP_EN 9-73

LEGACY_USB_EN 9-69

LEGACY_USB_STS 9-71

Line Status 11-14

IORDY Sample Point (ISP) 10-6

IOS (I/O Space) 13-2

IOSE I/O Space Enable (IOSE) 10-2

IRQ Number 9-42

IRQ Routing 9-8, 9-9

IRQ10 ECL 9-40

Link Status Change Indication 7-19

Link Status Indication 7-20

Loop Back Test Mode 11-8

Low Speed Device Attached (LS) 11-14

LPT Decode Range 9-15

LPT_LPC_EN 9-18

IRQ11 ECL 9-40

IRQ12 ECL 9-40

M Interrupt Mask 7-12

IRQ12LEN Mouse IRQ12 Latch Enable 9-12

IRQ14 ECL 9-40

IRQ15 ECL 9-40

Magic Packet 7-19

MAS (Master-Abort Status) 14-3

Mask 9-45

IRQ1LEN Keyboard IRQ1 Latch Enable 9-11 Master Abort Mode 8-11

IRQ3 ECL 9-39

Master Clear 9-28

IRQ4 ECL 9-39

IRQ5 ECL 9-39

IRQ6 ECL 9-39

IRQ7 ECL 9-39

Master Latency Count 8-6

Master/Slave in Buffered Mode 9-36

Master-Abort Status (MAS) 13-3

Max Packet (MAXP) 11-9

Maximum Redirection Entries 9-44

MC_LPC_EN 9-17

IRQ9 ECL 9-40

IRQEN Interrupt Routing Enable 9-8, 9-9

IRQF Interrupt Request Flag 9-50

ISA Enable 8-11

MCSMI_EN Microcontroller SMI Enable

9-68

MCSMI_STS Microcontroller SMI# Status

9-70

MD3 13-15, 14-13

KBC_ACT_STS 9-72

KBC_LPC_EN 9-17

KBC_TRP_EN 9-73

KILL 12-7

MDI Management Data Interrupt 7-11

Memory Address Base 8-9

Memory Address Limit 8-9

Memory Space Enable (MSE) 7-2, 8-3

Mic In Interrupt (MINT) 13-15, 14-13

Microprocessor Mode 9-36

MIDI Decode Range 9-15

MIDI_ACT_STS 9-72

L128LOCK Lower 128-byte Lock 9-14

LAN Connect Address 7-16

LAN Connect Register Address 7-16

LAN Connect Software Reset 7-19

Last Valid Buffer Completion Interrupt

(LVBCI) 13-11, 14-10

MIDI_LPC_EN 9-18

MIDI_TRP_EN 9-73

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Index-5

MLTC Master Latency Timer Count 7-4

Mode Selection Status 9-32

Modem In Interrupt (MIINT) 13-16, 14-14

Modem Out Interrupt (MOINT) 13-16, 14-14

MON_TRAP_BASE 9-57

MON4_FWD_EN 9-56

MON4_MASK 9-57

PCM 4/6 Enable 13-14

PCM In Interrupt (PIINT) 13-16, 14-14

PCM Out Interrupt (POINT) 13-16, 14-13

PER Parity Error Response 7-2, 9-3

PER_SMI_SEL 9-54

PERIODIC_EN 9-68

PERIODIC_STS 9-70

MON5_FWD_EN 9-56

MON5_MASK 9-57

MON6_FWD_EN 9-56

MON6_MASK 9-57

MON7_FWD_EN 9-56

MON7_MASK 9-57

MSS Decode Range 9-15

MSS_LPC_EN 9-18

PF Periodic Interrupt Flag 9-50

PIE Periodic Interrupt Enable 9-49

PIRQAE_ACT_STS 9-72

PIRQBF_ACT_STS 9-72

PIRQCG_ACT_STS 9-72

PIRQDH_ACT_STS 9-72

PM1_STS_REG 9-70

PME Clock 7-8

Multi-function Device 9-5

Multi-function Device. 7-5

Multi-Transaction Timer Count Value 8-12

MWIE Memory Write and Invalidate

Enable 7-2

PME Enable 7-9

PME Status 7-9, 7-19

PME Support 7-8

PME_EN 9-66

PME_STS 9-64

Pointer Field 7-14

NEWCENTURY_STS 9-77

NMI_EN 9-52

NMI_NOW 9-79

NMI2SMI_EN 9-77, 9-79

NO_REBOOT 9-13

Poll Mode Command 9-38

Port Enable/Disable Change 11-15

Port Enabled/Disabled (PORT_EN) 11-15

PORT Function Selection 7-14

Port Reset 11-14

NXT_PTR Next Item Pointer 7-8

PORT0EN 11-7

PORT1EN 11-7

OCW2 Select 9-37

OCW3 Select 9-38

Opcode 7-16

POS_DEC_EN Positive Decode Enable 9-12

Position In Current Buffer 13-12, 14-11

Power State 7-9

Overcurrent Active 11-14

Overcurrent Indicator 11-14

Parity Error Response 8-3

Parity Error Response Enable 8-11

Pass Through State (PSTATE) 11-6

PCB0 10-10

PRBTNOR_STS Power Button Override

Status 9-60

Prefetchable Memory Address Base 8-9

Prefetchable Memory Address Limit 8-10

Prefetched Index Value 13-12

Prefetched Index value 14-11

PRIM_SIG_MODE 10-9

Primany Resume Interrupt Enable 13-14,

14-12

Primary Bus Number 8-6

Primary Codec Ready (PCR) 13-15, 14-13

Primary Drive 0 Cycle Time (PCT0) 10-9

PCB1 10-10

PCI Interrupt Enable (USBPIRQEN) 11-6

PCI Master Request Status

(PCI_MREQ_STS) 8-13

PCI_DAC_EN 8-11

PCI_SERR_EN 9-51

Index-6

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Primary Drive 0 Synchronous DMA Mode

Enable (PSDE0) 10-8

Resume Interrupt Enable 11-12

Revision ID Value 13-3, 14-3

Primary Drive 1 Cycle Time (PCT1) 10-9

Primary Drive 1 IORDY Sample Point

(PISP1) 10-7

Revision Identification Number 8-4, 9-4

Revision Identification Number. 7-3

RI_EN 9-66

Primary Drive 1 Recovery Time (PRCT1)

10-7

Primary Drive 1 Synchronous DMA Mode

Enable (PSDE1) 10-8

Primary Master Channel Cable Reporting

10-10

RI_STS 9-64

RMA Master Abort Status 7-3, 9-4

RNR Mask 7-12

RNR Receive Not Ready 7-11

Rotate and EOI Codes (R, SL, EOI) 9-37

RS Rate Select 9-48

Primary Resume Interrupt 13-15, 14-13

RST_CPU 9-53

Primary Slave Channel Cable Reporting 10-10 RTA Received Target Abort 9-4

Programming Interface Value 10-3, 14-3

PRQ 9-44

PWR_FLR Power Failure 9-55

PWRBTN__STS 9-60

RTC_EN RTC Event Enable 9-61

RTC_INDX Real Time Clock Index Address

9-52

RTC_PWR_STS 9-55

PWRBTN_EN 9-61

RTC_STS 9-60

PWRBTN_LVL 9-54

PWROK_FLR PWROK Failure 9-55

RUC Receive Unit Command 7-13

Run/Pause Bus master (RPBM) 13-13, 14-11

Run/Stop (RS) 11-10

Read / Write Control (RWC) 10-11

Read Back Command 9-31

Read Completion Status 13-15

Read/Write Select 9-30

RUS Receive Unit Status 7-11

RW 12-8

SAFE_MODE 9-13

Read/Write Selection Status 9-32

Ready 7-16

SB16 Decode Range 9-15

SB16_LPC_EN 9-18

Receive DMA Byte Count 7-16

Received Master Abort (RMA) 8-4, 8-8

Received Master-Abort Status (RMA) 10-3,

11-3

SCB General Pointer 7-14

SCB1 10-10

SCBO 10-10

SCI_EN 9-62

Received System Error (SSE) 8-4, 8-8

Received Target Abort (RTA) 7-3, 8-4, 8-8

Recovery Time (RCT) 10-6

Redirection Entry Clear 9-43

REF_TOGGLE Refresh Cycle Toggle 9-51

Remote IRR 9-45

Reset Registers(RR) 14-11

Reset Registers(RR). 13-13

Resource Indicator 9-6, 9-8

Resource Type Indicator (RTE) 10-4, 11-4,

13-5, 14-5

SCI_IRQ_SEL 9-6

SEC_SIG_MODE 10-9

SECOND_TO_STS 9-78

Secondary Bus Number 8-6

Secondary Codec Ready (SCR) 13-15, 14-13

Secondary Drive 0 Cycle Time (SCT0) 10-8

Secondary Drive 0 Synchronous DMA Mode

Enable (SSDE0) 10-8

Secondary Drive 1 Cycle Time (SCT1) 10-8

Secondary Drive 1 IORDY Sample Point

(SISP1) 10-7

Secondary Drive 1 Recovery Time (SRCT1)

10-7

Resume Detect (RSM_DET) 11-11, 11-14

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Index-7

Secondary Drive 1 Synchronous DMA Mode

Enable (SSDE1) 10-8

Secondary Master Channel Cable Reporting

10-10

SIRQMD Serial IRQ Mode Select 9-9

SIRQSZ Serial IRQ Frame Size 9-9

Slave Identification Code 9-36

SLAVE_ADDR 12-9

Secondary Resume Interrupt 13-15, 14-13

Secondary Resume Interrupt Enable 13-14,

14-12

SLP_EN 9-62

SLP_SMI_EN 9-69

SLP_SMI_STS 9-71

Secondary Slave Channel Cable Reporting

10-10

SLP_TYP 9-62

SMB_CMD 12-7

SENDNOW 9-79

SMB_FOR_BIOS 9-22

Serial Bus Release Number 11-5

SERIRQ_SMI_STS 9-70

SERR# Due to Delayed Transaction Timeout

(SERR_DTT). 8-14

SMB_SMI_EN 12-4

SMB_WAK_STS SMBus Wake Status 9-64

SMBALERT_STS 12-6

SMBUS_SMI_STS 9-70

SERR# Due to Received Target Abort

(SERR_RTA). 8-14

SMI at End of Pass-through Enable

(SMIATENDPS) 11-6

SERR# Enable 8-11

SMI Caused by End of Pass-through

(SMIBYENDPS) 11-6

SMI Caused by Port 60 Read (TRAPBY60R)

11-6

SMI Caused by Port 60 Write (TRAPBY60W)

11-6

SERR# Enable (SERR_EN) 7-2, 8-3

SERR# enable on Delayed Transaction

Timeout (SERR_DTT_EN) 8-13

SERR# enable on receiving target abort

(SERR_RTA_EN) 8-13

SERR#_NMI_STS SERR# NMI Source

Status 9-51

SMI Caused by Port 64 Read (TRAPBY64R)

11-6

SERR_DTT SERR# Due to Delayed

Transaction Timeout 9-10

SMI Caused by Port 64 Write (TRAPBY64W)

11-6

SERR_DTT_EN SERR# on Delayed Transac-

tion Timeout Enable 9-10

SMI Caused by USB Interrupt (SMIBYUSB)

11-6

SERR_EN 9-3

SERR_RTA SERR# Due to Received Target

Abort 9-10

SERR_RTA_EN SERR# on Received Target

Abort Enable 9-10

SET Update Cycle Inhibit 9-49

SFPW Start Frame Pulse Width 9-9

Short Packet Interrupt Enable 11-12

SI Software Generated Interrupt 7-12

Signaled System Error (SSE) 7-3

Signaled Target Abort (STA) 8-4

Signaled Target-Abort Status 12-2

Signaled Target-Abort Status (STA) 10-3,

11-3

SMI on Port 60 Reads Enable (60REN) 11-7

SMI on Port 60 Writes Enable (60WEN) 11-7

SMI on Port 64 Reads Enable (64REN) 11-7

SMI on Port 64 Writes Enable (64WEN) 11-7

SMI on USB IRQ (USBSMIEN) 11-7

SOF Timing Value 11-13

Software Debug (SWDBG) 11-9

Special Fully Nested Mode (SFNM) 9-36

Special Mask Mode (SMM) 9-38

Speed 7-20

SPKR_DAT_EN 9-51

SQWE Square Wave Enable 9-49

SSE Signaled System Error 9-4

STA Signaled Target Abort 9-4

START 12-7

Single or Cascade (SNGL) 9-34

SIRQEN Serial IRQ Enable 9-9

Start/Stop Bus Master (START) 10-11

Index-8

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Sub Class Code 10-3, 11-4, 12-3, 13-4

Sub Class Code Value 14-4

Sub-Class Code 7-4, 8-5, 9-5

Subordinate Bus Number 8-6

Subsystem ID Value 13-6, 14-6

Subsystem Vendor ID Value 13-6, 14-5

Suspend 11-14

Timeout/CRC Interrupt Enable 11-12

TMR_VAL 9-62

TMR2_OUT_STS Timer Counter 2 OUT

Status 9-51

TMROF_EN Timer Overflow Interrupt

Enable 9-61

TMROF_STS Timer Overflow Status 9-61

TOP_SWAP 9-13

SW_TCO_SMI 9-77

SWI Software Interrupt 7-11

SWSMI_RATE_SEL 9-54

SWSMI_TMR_EN Software SMI# Timer

Enable 9-69

SWSMI_TMR_STS 9-71

SYS_RST 9-53

Trigger Mode 9-45

U128E Upper 128-byte Enable 9-14

U128LOCK Upper 128-byte Lock 9-14

UF Update-ended Flag 9-50

UIE Update-ended Interrupt Enable 9-49

UIP Update In Progress 9-48

USB Error Interrupt 11-11

USB Interrupt (USBINT) 11-11

USB1_EN 9-66

TCO_EN 9-68

TCO_INT_EN TCO Interrupt Enable 9-7

TCO_INT_SEL TCO Interrupt Select 9-7

TCO_INT_STS 9-77

USB1_STS 9-65

TCO_MESSAGE 9-80

USB2_EN 9-66

TCO_STS 9-70

USB2_STS 9-65

TCO_TMR_HLT TCO Timer Halt 9-79

TCOSCI_EN 9-66

TCOSCI_STS 9-64

Vendor ID Value 9-2, 11-1, 12-1, 13-1, 14-1

Vendor Identification Number 8-2

Version 7-8

THRM#_POL 9-66

THRM_DTY 9-63

VGA Enable 8-11

THRM_EN 9-66

VRT Valid RAM and Time Bit 9-50

WAK_STS 9-60

WDSTATUS Watchdog Status 9-80

WR_PingPong_EN 10-10

THRM_STS Thermal Interrupt Status 9-65

THRMOR_STS Thermal Interrupt Override

Status 9-65

THT_EN 9-63

THTL_DTY 9-63

THTL_STS Throttle Status 9-63

Xoff 7-18

TIM_CNT2_EN Timer Counter 2 Enable 9-51 Xon 7-18

TIMEOUT 9-77

82801BA ICH2 and 82801BAM ICH2-M Datasheet

Index-9

Intel around the world

United States and Canada

Intel Corporation

Robert Noyce Building

2200 Mission College Boulevard

P.O. Box 58119

Santa Clara, CA 95052-8119

USA

Phone: (800) 628-8686

Europe

Intel Corporation (UK) Ltd.

Pipers Way

Swindon

Wiltshire SN3 1RJ

Phone:

England

Germany

France

Italy

(44) 1793 403 000

(49) 89 99143 0

(33) 1 4571 7171

(39) 2 575 441

Israel

(972) 2 589 7111

Netherlands (31) 10 286 6111

Sweden

(46) 8 705 5600

Asia-Pacific

Intel Semiconductor Ltd.

32/F Two Pacific Place

88 Queensway, Central

Hong Kong, SAR

Phone: (852) 2844 4555

Japan

Intel Kabushiki Kaisha

P.O. Box 115 Tsukuba-gakuen

5-6 Tokodai, Tsukuba-shi

Ibaraki-ken 305

Japan

Phone: (81) 298 47 8522

South America

Intel Semicondutores do Brazil

Rue Florida, 1703-2 and CJ22

CEP 04565-001 Sao Paulo-SP

Brazil

Phone: (55) 11 5505 2296

For more information

To learn more about Intel Corporation, visit our site

on the World Wide Web at www.intel.com

82801BA [INTEL]

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