82910GL [INTEL]
Express Chipset; Express芯片组
| 型号： | 82910GL |
| 厂家： | 
INTEL |
| 描述： | Express Chipset |
| 文件： | 总426页 (文件大小：3241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Intel® 915G/915GV/915GL/915P/
915PL/910GL Express Chipset
Datasheet
For the Intel® 82915G/82915GV/82915GL/82910GL Graphics and
Memory Controller Hub (GMCH) and the Intel® 82915P/82915PL
Memory Controller Hub (MCH)
February 2005
Document Number: 301467-005
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 82915G,82915GV,82915GL,82910GL GMCH and 82915P/82915PL MCH may contain design defects or errors known as errata, which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading
Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See
http://www.intel.com/products/ht/hyperthreading_more.htm for more information including details on which processors support HT Technology.
Intel, Pentium, Celeron and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
Copyright© 2004–2005, Intel Corporation. All rights reserved
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Datasheet
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Contents
1
Introduction .......................................................................................................................17
1.1
1.2
1.3
Terminology..........................................................................................................24
Reference Documents..........................................................................................26
GMCH (MCH) Overview.......................................................................................26
1.3.1
1.3.2
1.3.3
1.3.4
Host Interface........................................................................................26
System Memory Interface.....................................................................27
Direct Media Interface (DMI).................................................................28
PCI Express* Graphics Interface (Intel® 82915G/82915P/
and 82915PL Only)...............................................................................28
Integrated Graphics (Intel® 82915G/82915GV/82910GL/82915GL
GMCH Only) .........................................................................................29
Analog and Intel® SDVO Displays (Intel®
1.3.5
1.3.6
82915G/82915GV/82910GL/82915GL GMCH Only) ...........................31
System Interrupts..................................................................................31
(G)MCH Clocking..................................................................................31
Power Management..............................................................................32
1.3.7
1.3.8
1.3.9
2
Signal Description .............................................................................................................33
2.1
2.2
2.3
2.4
2.5
Host Interface Signals ..........................................................................................35
DDR/DDR2 DRAM Channel A Interface ..............................................................38
DDR/DDR2 DRAM Channel B Interface ..............................................................39
DDR/DDR2 DRAM Reference and Compensation..............................................40
PCI Express* x16 Graphics Port Signals (Intel® 82915G, 82915P,
82915PL Only)......................................................................................................41
2.6
Analog Display Signals (Intel® 82915G/82915GV/82915GL/82910GL
GMCH Only).........................................................................................................42
2.7
2.8
2.9
Clocks, Reset, and Miscellaneous .......................................................................43
Direct Media Interface (DMI) ................................................................................43
Intel® Serial DVO (SDVO) Interface (82915G/82915GV/82915GL/82910GL
GMCH Only).........................................................................................................44
2.10
2.11
Power and Ground ...............................................................................................45
Reset States and Pull-up/Pull-downs...................................................................46
3
Register Description..........................................................................................................53
3.1
3.2
3.3
Register Terminology ...........................................................................................53
Platform Configuration..........................................................................................55
General Routing Configuration Accesses............................................................58
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Standard PCI Bus Configuration Mechanism.......................................58
Logical PCI Bus 0 Configuration Mechanism.......................................58
Primary PCI and Downstream Configuration Mechanism....................59
PCI Express* Enhanced Configuration Mechanism.............................60
Intel® 915x GMCH Configuration Cycle Flowchart ...............................62
3.4
I/O Mapped Registers ..........................................................................................63
3.4.1
CONFIG_ADDRESS—Configuration Address Register ......................63
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3.4.2
CONFIG_DATA—Configuration Data Register....................................64
4
Host Bridge/DRAM Controller Registers (D0:F0) .............................................................65
4.1 Host Bridge/DRAM Controller PCI Register Details (D0:F0) ...............................68
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
VID—Vendor Identification (D0:F0)......................................................68
DID—Device Identification (D0:F0) ......................................................68
PCICMD—PCI Command (D0:F0).......................................................69
PCISTS—PCI Status (D0:F0)...............................................................70
RID—Revision Identification (D0:F0)....................................................71
CC—Class Code (D0:F0) .....................................................................71
MLT—Master Latency Timer (D0:F0)...................................................72
HDR—Header Type (D0:F0) ................................................................72
SVID—Subsystem Vendor Identification (D0:F0).................................72
4.1.10 SID—Subsystem Identification (D0:F0)................................................73
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ...............................................73
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ......................................74
4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address
(D0:F0)..................................................................................................75
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0)
(Intel® 82915G/82915P/82915PL Only)................................................76
4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ......77
4.1.16 GGC—GMCH Graphics Control Register (D0:F0)
(82915G/82915GV/82915GL/82910GL GMCH only)...........................78
4.1.17 DEVEN—Device Enable (D0:F0) .........................................................79
4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0)..................................81
4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0)..................................82
4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0)..................................83
4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0)..................................84
4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0)..................................85
4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0)..................................86
4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0)..................................87
4.1.25 LAC—Legacy Access Control (D0:F0).................................................88
4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0).......................................89
4.1.27 SMRAM—System Management RAM Control (D0:F0)........................90
4.1.28 ESMRAMC—Extended System Management RAM Control (D0:F0) ..91
4.1.29 ERRSTS—Error Status (D0:F0) ...........................................................92
4.1.30 ERRCMD—Error Command (D0:F0) ...................................................93
4.1.31 SKPD—Scratchpad Data (D0:F0) ........................................................94
4.1.32 CAPID0—Capability Identifier (D0:F0) .................................................94
5
MCHBAR Registers ..........................................................................................................95
5.1 MCHBAR Register Details ...................................................................................96
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
C0DRB0—Channel A DRAM Rank Boundary Address 0 ....................96
C0DRB1—Channel A DRAM Rank Boundary Address 1 ....................98
C0DRB2—Channel A DRAM Rank Boundary Address 2 ....................98
C0DRB3—Channel A DRAM Rank Boundary Address 3 ....................98
C0DRA0—Channel A DRAM Rank 0,1 Attribute .................................99
C0DRA2—Channel A DRAM Rank 2,3 Attribute .................................99
C0DCLKDIS—Channel A DRAM Clock Disable ................................100
C0BNKARC—Channel A DRAM Bank Architecture ..........................101
C0DRT1—Channel A DRAM Timing Register ...................................102
5.1.10 C0DRC0—Channel A DRAM Controller Mode 0 ...............................104
5.1.11 C1DRB0—Channel B DRAM Rank Boundary Address 0 ..................106
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5.1.12 C1DRB1—Channel B DRAM Rank Boundary Address 1 ..................106
5.1.13 C1DRB2—Channel B DRAM Rank Boundary Address 2 ..................106
5.1.14 C1DRB3—Channel B DRAM Rank Boundary Address 3 ..................106
5.1.15 C1DRA0—Channel B DRAM Rank 0,1 Attribute ...............................106
5.1.16 C1DRA2—Channel B DRAM Rank 2,3 Attribute ...............................107
5.1.17 C1DCLKDIS—Channel B DRAM Clock Disable ................................107
5.1.18 C1BNKARC—Channel B Bank Architecture ......................................107
5.1.19 C1DRT1—Channel B DRAM Timing Register 1 ................................107
5.1.20 C1DRC0—Channel B DRAM Controller Mode 0 ...............................107
5.1.21 PMCFG—Power Management Configuration ....................................108
5.1.22 PMSTS—Power Management Status ................................................108
6
7
EPBAR Registers—Egress Port Register Summary......................................................109
6.1
EP RCRB Configuration Register Details ..........................................................109
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
EPESD—EP Element Self Description...............................................110
EPLE1D—EP Link Entry 1 Description ..............................................111
EPLE1A—EP Link Entry 1 Address....................................................111
EPLE2D—EP Link Entry 2 Description ..............................................112
EPLE2A—EP Link Entry 2 Address....................................................113
DMIBAR Registers—Direct Media Interface (DMI) RCRB .............................................115
7.1 Direct Media Interface (DMI) RCRB Register Details ........................................116
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
DMIVCECH—DMI Virtual Channel Enhanced Capability Header .....116
DMIPVCCAP1—DMI Port VC Capability Register 1..........................116
DMIPVCCAP2—DMI Port VC Capability Register 2..........................117
DMIPVCCTL—DMI Port VC Control ..................................................117
DMIVC0RCAP—DMI VC0 Resource Capability ................................118
DMIVC0RCTL0—DMI VC0 Resource Control ...................................119
DMIVC0RSTS—DMI VC0 Resource Status.......................................120
DMIVC1RCAP—DMI VC1 Resource Capability ................................120
DMIVC1RCTL1—DMI VC1 Resource Control ...................................121
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status.......................................121
7.1.11 DMILCAP—DMI Link Capabilities ......................................................122
7.1.12 DMILCTL—DMI Link Control..............................................................122
7.1.13 DMILSTS—DMI Link Status ...............................................................123
8
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) 125
8.1 Host-PCI Express* Bridge PCI Register Details (D1:F0)...................................128
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
VID1—Vendor Identification (D1:F0)..................................................128
DID1—Device Identification (D1:F0) ..................................................128
PCICMD1—PCI Command (D1:F0)...................................................129
PCISTS1—PCI Status (D1:F0)...........................................................130
RID1—Revision Identification (D1:F0)................................................132
CC1—Class Code (D1:F0) .................................................................132
CL1—Cache Line Size (D1:F0)..........................................................133
HDR1—Header Type (D1:F0) ............................................................133
PBUSN1—Primary Bus Number (D1:F0)...........................................133
8.1.10 SBUSN1—Secondary Bus Number (D1:F0) ......................................134
8.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) .................................134
8.1.12 IOBASE1—I/O Base Address (D1:F0) ...............................................135
8.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................135
8.1.14 SSTS1—Secondary Status (D1:F0)...................................................136
8.1.15 MBASE1—Memory Base Address (D1:F0)........................................137
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8.1.16 MLIMIT1—Memory Limit Address (D1:F0).........................................138
8.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0)................139
8.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0).................140
8.1.19 CAPPTR1—Capabilities Pointer (D1:F0) ...........................................140
8.1.20 INTRLINE1—Interrupt Line (D1:F0) ...................................................141
8.1.21 INTRPIN1—Interrupt Pin (D1:F0).......................................................141
8.1.22 BCTRL1—Bridge Control (D1:F0)......................................................142
8.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) ..................144
8.1.24 PM_CS1—Power Management Control/Status (D1:F0) ....................145
8.1.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ......146
8.1.26 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) ....................146
8.1.27 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0)....147
8.1.28 MC—Message Control (D1:F0)..........................................................148
8.1.29 MA—Message Address (D1:F0).........................................................149
8.1.30 MD—Message Data (D1:F0) ..............................................................149
8.1.31 PEG_CAPL—PCI Express* Capability List (D1:F0)...........................150
8.1.32 PEG_CAP—PCI Express*-G Capabilities (D1:F0).............................150
8.1.33 DCAP—Device Capabilities (D1:F0) ..................................................151
8.1.34 DCTL—Device Control (D1:F0)..........................................................152
8.1.35 DSTS—Device Status (D1:F0) ...........................................................153
8.1.36 LCAP—Link Capabilities (D1:F0) .......................................................154
8.1.37 LCTL—Link Control (D1:F0)...............................................................155
8.1.38 LSTS—Link Status (D1:F0) ................................................................156
8.1.39 SLOTCAP—Slot Capabilities (D1:F0) ................................................157
8.1.40 SLOTCTL—Slot Control (D1:F0)........................................................158
8.1.41 SLOTSTS—Slot Status (D1:F0) .........................................................159
8.1.42 RCTL—Root Control (D1:F0) .............................................................160
8.1.43 RSTS—Root Status (D1:F0)...............................................................161
8.1.44 PEGLC—PCI Express*-G Legacy Control .........................................162
8.1.45 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) ......163
8.1.46 PVCCAP1—Port VC Capability Register 1 (D1:F0)...........................163
8.1.47 PVCCAP2—Port VC Capability Register 2 (D1:F0)...........................164
8.1.48 PVCCTL—Port VC Control (D1:F0) ...................................................164
8.1.49 VC0RCAP—VC0 Resource Capability (D1:F0) .................................165
8.1.50 VC0RCTL—VC0 Resource Control (D1:F0) ......................................165
8.1.51 VC0RSTS—VC0 Resource Status (D1:F0)........................................166
8.1.52 VC1RCAP—VC1 Resource Capability (D1:F0) .................................166
8.1.53 VC1RCTL—VC1 Resource Control (D1:F0) ......................................167
8.1.54 VC1RSTS—VC1 Resource Status (D1:F0)........................................168
8.1.55 RCLDECH—Root Complex Link Declaration Enhanced Capability
Header (D1:F0)...................................................................................168
8.1.56 ESD—Element Self Description (D1:F0)............................................169
8.1.57 LE1D—Link Entry 1 Description (D1:F0)............................................170
8.1.58 LE1A—Link Entry 1 Address (D1:F0).................................................171
8.1.59 PEGSSTS—PCI Express*-G Sequence Status (D1:F0)....................171
9
Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/
82910GL GMCH Only)....................................................................................................173
9.1
Integrated Graphics Device PCI Register Details (D2:F0).................................175
9.1.1
9.1.2
9.1.3
9.1.4
VID2—Vendor Identification (D2:F0)..................................................175
DID2—Device Identification (D2:F0) ..................................................175
PCICMD2—PCI Command (D2:F0)...................................................176
PCISTS2—PCI Status (D2:F0)...........................................................177
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9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
RID2—Revision Identification (D2:F0)................................................178
CC—Class Code (D2:F0) ...................................................................178
CLS—Cache Line Size (D2:F0)..........................................................179
MLT2—Master Latency Timer (D2:F0)...............................................179
HDR2—Header Type (D2:F0) ............................................................180
9.1.10 MMADR—Memory Mapped Range Address (D2:F0) ........................180
9.1.11 IOBAR—I/O Base Address (D2:F0) ...................................................181
9.1.12 GMADR—Graphics Memory Range Address (D2:F0).......................182
9.1.13 GTTADR—Graphics Translation Table Range Address (D2:F0).......183
9.1.14 SVID2—Subsystem Vendor Identification (D2:F0).............................183
9.1.15 SID2—Subsystem Identification (D2:F0)............................................184
9.1.16 ROMADR—Video BIOS ROM Base Address (D2:F0).......................184
9.1.17 CAPPOINT—Capabilities Pointer (D2:F0) .........................................185
9.1.18 INTRLINE—Interrupt Line (D2:F0) .....................................................185
9.1.19 INTRPIN—Interrupt Pin (D2:F0).........................................................185
9.1.20 MINGNT—Minimum Grant (D2:F0)....................................................186
9.1.21 MAXLAT—Maximum Latency (D2:F0) ...............................................186
9.1.22 MCAPPTR—Mirror of Dev0 Capability Pointer (D2:F0)
(Mirrored_D0_34) ...............................................................................186
9.1.23 MCAPID—Mirror of Dev0 Capability Identification (D2:F0)
(Mirrored_D0_E0)...............................................................................186
9.1.24 MGGC—Mirror of Dev0 GMCH Graphics Control (D2:F0)
(Mirrored_D0_52) ...............................................................................187
9.1.25 MDEVENdev0f0—Mirror of Dev0 Device Enable (D2:F0)
(Mirrored_D0_54) ...............................................................................187
9.1.26 BSM—Base of Stolen Memory (D2:F0)..............................................187
9.1.27 MSAC—Multi Size Aperture Control (D2:F0) .....................................188
9.1.28 PMCAPID—Power Management Capabilities ID (D2:F0)..................188
9.1.29 PMCAP—Power Management Capabilities (D2:F0)..........................189
9.1.30 PMCS—Power Management Control/Status (D2:F0) ........................190
9.1.31 SWSMI—Software SMI (D2:F0) .........................................................191
9.1.32 ASLE—System Display Event Register (D2:F0) ................................191
9.1.33 ASLS—ASL Storage (D2:F0) .............................................................192
10
Device 2 Function 1 (D2:F1) Configuration Registers (Intel®
82915G/82915GV/82915GL/ 82910GL Only).................................................................193
10.1
Device 2 Function 1 Configuration Register Details (D2:F1).............................194
10.1.1 VID2—Vendor Identification (D2:F1)..................................................194
10.1.2 DID2—Device Identification (D2:F1) ..................................................194
10.1.3 PCICMD2—PCI Command (D2:F1)...................................................195
10.1.4 PCISTS2—PCI Status (D2:F1)...........................................................196
10.1.5 RID2—Revision Identification (D2:F1)................................................197
10.1.6 CC—Class Code Register (D2:F1).....................................................197
10.1.7 CLS—Cache Line Size (D2:F1)..........................................................197
10.1.8 MLT2—Master Latency Timer (D2:F1)...............................................198
10.1.9 HDR2—Header Type Register (D2:F1)..............................................198
10.1.10 MMADR—Memory Mapped Range Address (D2:F1) ........................198
10.1.11 SVID2—Subsystem Vendor Identification (D2:F1).............................199
10.1.12 SID2—Subsystem Identification (D2:F1)............................................199
10.1.13 ROMADR—Video BIOS ROM Base Address (D2:F1).......................199
10.1.14 CAPPOINT—Capabilities Pointer (D2:F1) .........................................199
10.1.15 MINGNT—Minimum Grant Register (D2:F1)......................................200
10.1.16 MAXLAT—Maximum Latency (D2:F1) ...............................................200
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10.1.17 MCAPPTR—Mirror of Dev0 Capability Pointer (D2:F1)
(Mirrored_D0_34) ...............................................................................200
10.1.18 MCAPID—Mirror of Dev0 Capability Identification (D2:F1)
(Mirrored_D0_E0)...............................................................................200
10.1.19 MGGC—Mirror of Dev0 GMCH Graphics Control (D2:F1)
(Mirrored_D0_52) ...............................................................................200
10.1.20 MDEVENdev0f0—Mirror of Dev0 Device Enable (D2:F1)
(Mirrored_D0_54) ...............................................................................201
10.1.21 BSM—Base of Stolen Memory Register (D2:F1) ...............................201
10.1.22 PMCAPID—Power Management Capabilities ID (D2:F1)..................201
10.1.23 PMCAP—Power Management Capabilities (D2:F1)..........................201
10.1.24 PMCS—Power Management Control/Status (D2:F1) ........................202
10.1.25 SWSMI—Software SMI (D2:F1) .........................................................202
10.1.26 ASLS—ASL Storage (D2:F1) .............................................................203
Device 2 – PCI I/O Registers .............................................................................204
10.2.1 MMIO_INDEX—MMIO Address Register...........................................204
10.2.2 MMIO_DATA—MMIO Data Register..................................................204
10.2
11
System Address Map......................................................................................................205
11.1
Legacy Address Range......................................................................................207
11.1.1 DOS Range (0h – 9_FFFFh) ..............................................................208
11.1.2 Legacy Video Area (A_0000h–B_FFFFh) ..........................................208
11.1.3 Expansion Area (C_0000h–D_FFFFh)...............................................209
11.1.4 Extended System BIOS Area (E_0000h–E_FFFFh)..........................210
11.1.5 System BIOS Area (F_0000h–F_FFFFh)...........................................210
11.1.6 Programmable Attribute Map (PAM) Memory Area Details................210
Main Memory Address Range (1 MB to TOLUD) ..............................................211
11.2.1 ISA Hole (15 MB–16 MB) ...................................................................211
11.2.2 TSEG ..................................................................................................212
11.2.3 Pre-allocated Memory.........................................................................212
PCI Memory Address Range (TOLUD – 4 GB) .................................................212
11.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh) .................214
11.3.2 HSEG (FEDA_0000h–FEDB_FFFFh)................................................214
11.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................214
11.3.4 High BIOS Area ..................................................................................214
11.3.5 PCI Express* Configuration Address Space (Intel® 82915G/82915P
Only) ...................................................................................................215
11.2
11.3
11.3.6 PCI Express* Graphics Attach (Intel® 82915G/82915P Only)............215
11.3.7 AGP DRAM Graphics Aperture ..........................................................215
11.3.8 Graphics Memory Address Ranges (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only) .........................216
11.4
System Management Mode (SMM) ...................................................................216
11.4.1 SMM Space Definition ........................................................................217
11.4.2 SMM Space Restrictions ....................................................................217
11.4.3 SMM Space Combinations .................................................................218
11.4.4 SMM Control Combinations................................................................218
11.4.5 SMM Space Decode and Transaction Handling ................................219
11.4.6 Processor WB Transaction to an Enabled SMM Address Space ......219
11.4.7 SMM Access through GTT TLB (Intel® 82915G/82915GV/82910GL
GMCH Only) .......................................................................................219
11.4.8 Memory Shadowing............................................................................219
11.4.9 I/O Address Space..............................................................................220
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11.4.10 PCI Express* I/O Address Mapping (Intel® 82915G/82915P/82915PL
Only) ...................................................................................................220
11.4.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping ............220
11.4.12 Legacy VGA and I/O Range Decode Rules .......................................221
12
Functional Description ....................................................................................................223
12.1
Host Interface .....................................................................................................223
12.1.1 FSB GTL+ Termination.......................................................................223
12.1.2 FSB Dynamic Bus Inversion...............................................................223
12.1.3 APIC Cluster Mode Support ...............................................................224
System Memory Controller.................................................................................224
12.2.1 Memory Organization Modes..............................................................224
System Memory Configuration Registers Overview ..........................................226
12.3.1 DRAM Technologies and Organization ..............................................227
12.3.1.1 Rules for Populating DIMM Slots ......................................227
12.3.1.2 System Memory Supported Configurations ......................228
12.3.1.3 Main Memory DRAM Address Translation and Decoding 228
12.3.2 DRAM Clock Generation ....................................................................231
12.3.3 Suspend-to-RAM and Resume...........................................................231
12.3.4 DDR2 On-Die Termination..................................................................231
12.3.5 DDR2 Off-Chip Driver Impedance Calibration....................................231
PCI Express* (Intel® 82915G/82915P82915PL Only)........................................232
12.4.1 Transaction Layer...............................................................................232
12.4.2 Data Link Layer...................................................................................232
12.4.3 Physical Layer.....................................................................................232
Intel® Serial Digital Video Output (SDVO) (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only).........................................233
12.5.1 Intel® SDVO Capabilities.....................................................................233
12.5.2 Intel® SDVO Modes ............................................................................234
Integrated Graphics Device (Intel® 82915G/82915GV/82915GL/82910GL
GMCH Only).......................................................................................................235
12.6.1 3D Engine ...........................................................................................236
12.6.2 Setup Engine ......................................................................................236
12.6.2.1 3D Primitives and Data Formats Support..........................236
12.6.2.2 Pixel Accurate “Fast” Scissoring and Clipping Operation .237
12.6.2.3 Depth Bias.........................................................................237
12.6.2.4 Backface Culling................................................................237
12.6.2.5 Scan Converter..................................................................237
12.6.2.6 Pixel Rasterization Rules ..................................................237
12.6.2.7 2D Functionality.................................................................237
12.6.3 Texture Engine....................................................................................238
12.6.3.1 Perspective Correct Texture Support................................238
12.6.3.2 Texture Formats and Storage ...........................................238
12.6.3.3 Texture Decompression ....................................................238
12.6.3.4 Texture ChromaKey ..........................................................238
12.6.3.5 Anti-Aliasing.......................................................................238
12.6.3.6 Texture Map Filtering ........................................................238
12.6.3.7 Multiple Texture Composition............................................239
12.6.3.8 Bi-Cubic Filter (4x4 Programmable Texture Filter) ...........239
12.6.3.9 Cubic Environment Mapping .............................................240
12.6.4 Raster Engine .....................................................................................240
12.6.4.1 Texture Map Blending .......................................................240
12.2
12.3
12.4
12.5
12.6
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12.6.4.2 Combining Intrinsic and Specular Color Components ......240
12.6.4.3 Color Shading Modes........................................................240
12.6.4.4 Color Dithering...................................................................241
12.6.4.5 Vertex and Per Pixel Fogging............................................241
12.6.4.6 Alpha Blending (Frame Buffer)..........................................241
12.6.4.7 Microsoft DirectX* API and SGI OpenGL* API Logic Ops 242
12.6.4.8 Color Buffer Formats: 8-, 16-, or 32-bits per Pixel
(Destination Alpha)............................................................242
12.6.4.9 Depth Buffer ......................................................................242
12.6.4.10 Stencil Buffer .....................................................................243
12.6.4.11 Projective Textures............................................................243
12.6.5 2D Engine ...........................................................................................243
12.6.5.1 GMCH VGA Registers.......................................................243
12.6.5.2 Logical 128-bit Fixed BLT and 256 Fill Engine..................243
12.6.6 Video Engine.......................................................................................244
12.6.6.1 Hardware Motion Compensation.......................................244
12.6.6.2 Sub-Picture Support..........................................................244
12.6.7 Planes.................................................................................................245
12.6.7.1 Cursor Plane......................................................................245
12.6.7.2 Overlay Plane....................................................................245
12.6.7.3 Advanced Deinterlacing and Dynamic Bob and Weave ...246
12.6.8 Pipes...................................................................................................246
12.6.8.1 Clock Generator Units (DPLL) ..........................................246
Display Interfaces (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)247
12.7.1 Analog Display Port Characteristics ...................................................249
12.7.1.1 Integrated RAMDAC..........................................................249
12.7.1.2 Sync Signals......................................................................249
12.7.1.3 VESA/VGA Mode ..............................................................249
12.7.1.4 DDC (Display Data Channel) ............................................250
12.7.2 Digital Display Interface......................................................................250
12.7.2.1 Digital Display Channels – SDVOB and SDVOC..............250
12.7.2.2 ADD2 Card ........................................................................250
12.7.3 Multiple Display Configurations ..........................................................252
Power Management ...........................................................................................253
12.7
12.8
12.9
Clocking..............................................................................................................253
13
Electrical Characteristics.................................................................................................255
13.1
13.2
13.3
13.4
Absolute Maximum Ratings................................................................................255
Power Characteristics ........................................................................................257
Signal Groups.....................................................................................................259
DC Characteristics .............................................................................................262
13.4.1 General DC Characteristics................................................................262
13.4.2 RGB/CRT DAC Display DC Characteristics (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only) .........................265
14
Ballout and Package Information....................................................................................267
14.1
14.2
14.3
DDR2 Ballout......................................................................................................267
DDR Ballout........................................................................................................329
Package Information ..........................................................................................395
15
10
Testability........................................................................................................................399
15.1
Complimentary Pins ...........................................................................................399
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15.2
15.3
15.4
15.5
15.6
15.7
XOR Test Mode Initialization for DDR................................................................400
XOR Test Mode Initialization for DDR2..............................................................400
XOR Chain Definition .........................................................................................401
DDR XOR Chains...............................................................................................401
DDR2 XOR Chains.............................................................................................414
PADs Excluded from XOR Mode(s)...................................................................426
Figures
Figure 1-1. Intel® 915G Express Chipset System Block Diagram Example.....................18
Figure 1-2. Intel® 915P Express Chipset System Block Diagram Example .....................19
Figure 1-3. Intel® 915GV Express Chipset System Block Diagram Example...................20
Figure 1-4. Intel® 910GL Express Chipset System Block Diagram Example...................21
Figure 1-5. Intel® 915PL Express Chipset System Block Diagram Example ...................22
Figure 1-6. Intel® 915GL Express Chipset System Block Diagram Example...................23
Figure 2-1. Intel® (G)MCH Signal Interface Diagram........................................................34
Figure 3-1. Conceptual Chipset PCI Configuration Diagram............................................55
Figure 3-2. Register Organization (Representative of the Intel® 82915G GMCH) ...........57
Figure 3-3. DMI Type 0 Configuration Address Translation .............................................59
Figure 3-4. DMI Type 1 Configuration Address Translation .............................................59
Figure 3-5. Memory Map to PCI Express* Device Configuration Space..........................60
Figure 3-6. Intel® 915x GMCH Configuration Cycle Flowchart.........................................62
Figure 6-1. Link Declaration Topology............................................................................109
Figure 11-1. System Address Ranges............................................................................207
Figure 11-2. Microsoft MS-DOS* Legacy Address Range .............................................208
Figure 11-3. Main Memory Address Range....................................................................211
Figure 11-4. PCI Memory Address Range......................................................................213
Figure 12-1. System Memory Styles...............................................................................225
Figure 12-2. Integrated Graphics Device Block Diagram ...............................................235
Figure 12-3. System Clocking Example..........................................................................254
Figure 14-1. Intel® 82915G GMCH Ballout for DDR2 (Top View: Columns 1–12).........268
Figure 14-2. Intel® 82915G GMCH Ballout for DDR2 (Top View: Columns 13–24).......269
Figure 14-3. Intel® 82915G GMCH Ballout for DDR2 (Top View: Columns 25–35).......270
Figure 14-4. Intel® 82915G GMCH Ballout for DDR (Top View: Columns 1–12 )..........330
Figure 14-5. Intel® 82915G GMCH Ballout for DDR (Top View: Columns 13–24 )........331
Figure 14-6. Intel® 82915G GMCH Ballout for DDR (Top View: Columns 25–35 )........332
Figure 14-7. (G)MCH Package Dimensions ...................................................................396
Figure 14-8. (G)MCH Component Keep-Out Restrictions..............................................397
Figure 15-1. XOR Test Mode Initialization Cycles..........................................................400
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Tables
Table 2-1. Host Interface Reset and S3 States ................................................................46
Table 2-2. System Memory (DDR2) Reset and S3 States ...............................................47
Table 2-3. System Memory (DDR) Reset and S3 States .................................................49
Table 2-4. PCI Express* Graphics x16 Port Reset and S3 States ...................................50
Table 2-5. DMI Reset and S3 States ................................................................................50
Table 2-6. Clocking Reset and S3 States.........................................................................51
Table 2-7. MISC Reset and S3 States..............................................................................51
Table 2-8. DAC Reset and S3 States (Intel® 82915G/82915GV/82915GL/82910GL
GMCH only) ...............................................................................................................51
Table 3-1. Device Number Assignment for Internal (G)MCH Devices .............................57
Table 4-1. Device 0 Function 0 Register Address Map Summary....................................65
Table 6-1. Egress Port Register Address Map ...............................................................109
Table 7-1. DMI Register Address Map Summary...........................................................115
Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0) ...........125
Table 9-1. Integrated Graphics Device Register Address Map (D2:F0).........................173
Table 10-1. Device 2 Function 1 Register Address Map Summary ...............................193
Table 11-1. Expansion Area Memory Segments............................................................209
Table 11-2. Extended System BIOS Area Memory Segments.......................................210
Table 11-3. System BIOS Area Memory Segments .......................................................210
Table 11-4. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB
TSEG .......................................................................................................................212
Table 11-5. SMM Space Table .......................................................................................218
Table 11-6. SMM Control Table......................................................................................218
Table 12-1. Sample System Memory Organization with Interleaved Channels .............225
Table 12-2. Sample System Memory Organization with Asymmetric Channels ............225
Table 12-3. DDR / DDR2 DIMM Supported Configurations ...........................................228
Table 12-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode) ......229
Table 12-5. DRAM Address Translation (Dual Channel Symmetric Mode) ...................230
Table 12-6. Display Port Characteristics ........................................................................248
Table 12-7. Analog Port Characteristics.........................................................................249
Table 13-1. Absolute Maximum Ratings.........................................................................255
Table 13-2. Non-Memory Power Characteristics............................................................257
Table 13-3. DDR Power Characteristics.........................................................................258
Table 13-4. DDR2 Power Characteristics.......................................................................258
Table 13-5. Signal Groups..............................................................................................259
Table 13-6. DC Characteristics3 .....................................................................................262
Table 13-7. RGB/CRT DAC Display DC Characteristics (Functional Operating Range:
VCCA_DAC = 2.5 V ±5%) .......................................................................................265
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)..............271
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name).............300
Table 14-3. GMCH/MCH Ballout for DDR Systems (Sorted by Ball Number)................333
Table 14-4. GMCH/MCH Ballout for DDR Systems (Sorted by Signal Name)...............365
Table 15-1. Complimentary Pins to Drive.......................................................................399
Table 15-2. XOR Chain Outputs for both DDR and DDR2.............................................401
Table 15-3. DDR XOR Chain #0.....................................................................................402
Table 15-4. DDR XOR Chain #1.....................................................................................404
Table 15-5. DDR XOR Chain #2.....................................................................................406
Table 15-6. DDR XOR Chain #3.....................................................................................407
Table 15-7. DDR XOR Chain #4.....................................................................................408
Table 15-8. DDR XOR Chain #5.....................................................................................409
Table 15-9. DDR XOR Chain #6.....................................................................................410
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Table 15-10. DDR XOR Chain #7...................................................................................411
Table 15-11. DDR XOR Chain #8...................................................................................412
Table 15-12. DDR XOR Chain #9...................................................................................413
Table 15-13. DDR2 XOR Chain #0.................................................................................414
Table 15-14. DDR2 XOR Chain #1.................................................................................416
Table 15-15. DDR2 XOR Chain #2.................................................................................418
Table 15-16. DDR2 XOR Chain #3.................................................................................419
Table 15-17. DDR2 XOR Chain #4.................................................................................420
Table 15-18. DDR2 XOR Chain #5.................................................................................421
Table 15-19. DDR2 XOR Chain #6.................................................................................422
Table 15-20. DDR2 XOR Chain #7.................................................................................423
Table 15-21. DDR2 XOR Chain #8.................................................................................424
Table 15-22. DDR2 XOR Chain #9.................................................................................425
Table 15-23. XOR Pad Exclusion List.............................................................................426
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Revision History
Rev
-001
-002
Description
Date
• Initial Release
June 2004
September 2004
• Added Intel® 82915GV GMCH
• Minor edits throughout for clarity
• Added Intel® 82910GL GMCH
-003
-004
September 2004
January 2005
• Added Intel® 82915GL GMCH
• Added Intel® 82915PL GMCH
• Minor edits throughout for clarity
-005
February 2005
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Intel® 82915G/82915GV/82915GL/
82910GL/82915P/82915PL (G)MCH Features
Processor Interface
Integrated Graphics Device
⎯ One Intel® Pentium® 4 processor or Intel® Celeron®
D processor including 775-Land package.
⎯ Supports Pentium 4 processor FSB interrupt
delivery
(82915G/82915GV/82915GL/82910GL only)
⎯ Core frequency of 333 MHz
⎯ High-Quality 3D Setup and Render Engine
⎯ High-Quality Texture Engine
⎯ Video DVD/PC-VCR
⎯ 3D Graphics Rendering Enhancements
⎯ 2D Graphics
⎯ Video Overlay
⎯ Multiple Overlay Functionality
Analog Display Support
(82915G/82915GV/82915GL/82910GL only)
⎯ 400 MHz Integrated 24-bit RAMDAC
⎯ Up to 2048x1536@ 85 Hz refresh
⎯ Hardware Color Cursor Support
⎯ DDC2B Compliant Interface
Digital Display Support
(82915G/82915GV/82915GL/82910GL only)
⎯ Two SDVO ports multiplexed with PCI Express
Graphics Interface (82915G only)
⎯ 200 MHz dot clock on each 12-bit interface
⎯ Can combine two channels to form one larger
interface (82915G only)
⎯ 533 MT/s (133 MHz) FSB (82915G/82915GV/
82915GL/82910GL/82915P/82915PL) and 800
MT/s (200 MHz) FSB (82915G/82915GV/
82915GL/82915P/82915PL only)
⎯ FSB Dynamic Bus Inversion (DBI)
⎯ 32-bit host bus addressing for access to 4 GB of
memory space
⎯ 12-deep In-Order Queue
⎯ 1-deep Defer Queue
⎯ GTL+ bus driver with integrated GTL termination
resistors
⎯ Supports a Cache Line Size of 64 bytes
System Memory
⎯ One or two 64-bit wide DDR/DDR2 SDRAM data
channels (82915PL and 82910GL supports DDR
400 or DDR 333, 1 DIMM, 2 Channels only)
(82915PL supports DDR only)
⎯ Bandwidth up to 8.5 GB/s (DDR/DDR2 533) in
dual-channel interleaved mode.
⎯ Flat panels up to 2048x1536@ 85Hz or digital
CRT/HDTV at 1920x1080@ 85Hz
⎯ Non-ECC memory only.
⎯ Dual Independent Display options with digital
display. (82915G only)
⎯ 256-Mb, 512-Mb and 1-Gb DDR/DDR2
technologies
⎯ Multiplexed Digital Display Channels (Supported
with ADD2 Card). (82915G only)
⎯ Supports TMDS transmitters or TV-Out encoders
⎯ ADD2 card uses PCI Express Graphics x16
connector (82915G only)
⎯ Only x8, x16, DDR/DDR2 devices with four banks
and also supports eight bank, 1-Gbit DDR2 devices.
⎯ Opportunistic refresh
⎯ Up to 64 simultaneously open pages (four ranks of
eight bank devices* 2 channels)
⎯ SPD (Serial Presence Detect) scheme for DIMM
detection support
⎯ Suspend-to-RAM support using CKE
⎯ Supports configurations defined in the JEDEC
DDR/DDR2 DIMM specification only
PCI Express* Graphics Interface
(82915G/82915P/82915PL only)
⎯ One x16 PCI Express port
DMI Interface
⎯ A chip-to-chip connection interface to Intel® ICH6
⎯ 2 GB/s point-to-point DMI to ICH6 (1 GB/s each
direction)
⎯ 100 MHz reference clock (shared with PCI Express
Graphics Attach).
⎯ 32-bit downstream addressing
⎯ Messaging and Error Handling
⎯ Compatible with the PCI Express Base
Package
Specification revision 1.0a
⎯ 37.5 mm × 37.5 mm., 1210 balls, variable ball pitch
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1 Introduction
The Intel® 91x Express chipset family is designed for use with the Intel® Pentium® 4 processor /
Intel® Celeron® D processor (Intel® 915G/915GV/915GL/915P/915PL chipsets) or Intel®
Celeron® processor (Intel® 910GL chipset) in desktop platforms. Each chipset in the family
contains two components: GMCH (or MCH) for the host bridge and I/O Controller Hub 6 (ICH6)
for the I/O subsystem. The 82915G GMCH is part of the 915G Express chipset, the 82915GV is
part of the 915GV Express chipset, the 82915GL is part of the 915GL Express Chipset, the
82910GL is part of the 910GL Express chipset, the 82915P MCH is part of the 915P Express
chipset, and the 82915PL is part of the 915PL Express chipset. The ICH6 is the sixth generation
I/O Controller Hub and provides a multitude of I/O related functions. Figure 1-1 shows an
example system block diagram for the 915G Express chipset, Figure 1-2 shows an example
system block diagram for the 915P Express chipsets, Figure 1-3 shows an example system block
diagram for the 915GV Express chipset, Figure 1-4 shows an example system block diagram for
the 910GL Express chipsets, Figure 1-5 shows an example system block diagram for the 915PL
Express chipsets, and Figure 1-6 shows an example system block diagram for the 915GL Express
chipsets.
This document is the datasheet for the Intel® 82915G Graphics and Memory Controller Hub
(GMCH), Intel® 82915GV Graphics and Memory Controller Hub (GMCH), Intel® 82915GL
Graphics and Memory Controller Hub (GMCH), Intel® 82910GL Graphics and Memory
Controller Hub (GMCH), Intel® 82915P Memory Controller Hub (MCH), and the Intel® 82915PL
Memory Controller Hub (MCH). Topics covered include; signal description, system memory
map, PCI register description, a description of the (G)MCH interfaces and major functional units,
electrical characteristics, ballout definitions, and package characteristics.
The difference between the 82915G GMCH and 82915P MCH is that the 82915G GMCH
contains an integrated graphics port (and associated SDVO and analog display ports) and the
82915P MCH does not contain these items. Both devices support PCI Express graphics. The
82915GV GMCH contains an integrated graphics port (and associated SDVO and analog display
ports), but does not support PCI Express graphics. The 82915GL GMCH has the same features as
the 82915GV GMCH, but only supports DDR memory. The 82915PL GMCH has the same
features as the 82915P GMCH, but only supports 2 channels of DDR DIMM memory to a
maximum of 1-DIMM per channel. The 82910GL GMCH supports only 533 MHz FSB, contains
an integrated graphics port (and associated SDVO and analog display ports), does not support PCI
Express graphics, and supports only 2 channels of DDR DIMM memory to a maximum of 1-
DIMM per channel.
Note: Unless otherwise specified, the information in this document applies to the 82915G Graphics and
Memory Controller Hub (GMCH), 82915GV Graphics and Memory Controller Hub (GMCH),
82915GV Graphics and Memory Controller Hub (GMCH), 82910GL Graphics and Memory
Controller Hub (GMCH), 82915PL Memory Controller Hub (MCH), and the 82915P Memory
Controller Hub (MCH).
Note: References in this document to PCI Express are for the 82915G, 82915P, and the 82915PL only.
Note: References in this document to the Integrated Graphics Device (IGD) are for the 82915G,
82915GV, 82915GL, and 82910GL only.
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Note: References in this document to DDR2 memory are for the 82915G, 82915GV, and 82915P only.
Note: Unless otherwise specified, ICH6 refers to the Intel® 82801FB ICH6, 82801FR ICHR, 82801FW
ICH6W, and 82801FRW ICH6RW I/O Controller Hub 6 components.
Figure 1-1. Intel® 915G Express Chipset System Block Diagram Example
Intel® Pentium®
4
Processor or Intel®
Celeron® D Processor
533/800 MHz FSB
Analog
Intel® 915G Express Chipset
Display
VGA
System Memory
DDR or DDR2
Add2
Card
Display
Display
Channel A
Channel B
Intel® 82915G GMCH
DDR or DDR2
SDVO
OR
DDR or DDR2
DDR or DDR2
PCI Express
x16 Graphics
Graphics
Display
Card
DMI Interface
USB 2.0
8 ports, 480 Mb/s
Power Management
Clock Generation
LAN Connect/ASF
GPIO
Intel® ICH6
4 Serial ATA Ports
150 MB/s
System
Management (TCO)
SMBus 2.0/I2C
2 ATA 100 Ports
Seven PCI Masters
AC '97
3 CODEC support
PCI Bus
Flash
BIOS
SIO
LPC
Interface
Sys_Blk_G
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Figure 1-2. Intel® 915P Express Chipset System Block Diagram Example
Intel® Pentium®
4
Processor or Intel®
Celeron® D Processor
533/800 MHz FSB
Intel® 915P Express Chipset
System Memory
DDR or DDR2
DDR or DDR2
Channel A
Channel B
PCI Express
x16 Graphics
Intel® 82915P MCH
Graphics
Card
Display
DDR or DDR2
DDR or DDR2
DMI Interface
USB 2.0
8 ports, 480 Mb/s
Power Management
IDE
Clock Generation
LAN Connect/ASF
4 SATA Ports
150 MB/s
Intel® ICH6x
AC '97/Intel® High
Definition Audio
CODECs
System
Management (TCO)
SMBus 2.0/I2C
PCI Express* x1
Intel® PCI Express
Gigabit Ethernet
Seven PCI Masters
PCI Bus
GPIO
Flash
BIOS
SIO
LPC
Interface
Sys_Blk_P
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Figure 1-3. Intel® 915GV Express Chipset System Block Diagram Example
Intel® Pentium®
4
Processor or Intel®
Celeron® D Processor
533/800 MHz
System Bus
Intel® 915GV Express Chipset
Analog
Display
VGA
System Memory
DDR or DDR2
Add2
Card
Display
Display
Channel A
Channel B
Intel® 82915GV GMCH
DDR or DDR2
SDVO
DDR or DDR2
DDR or DDR2
DMI Interface
USB 2.0
8 ports, 480 Mb/s
Power Management
Clock Generation
LAN Connect/ASF
GPIO
Intel® ICH6
4 Serial ATA Ports
150 MB/s
System
Management (TCO)
SMBus 2.0/I2C
2 ATA 100 Ports
Seven PCI Masters
AC '97
3 CODEC support
PCI Bus
Flash
BIOS
SIO
LPC
Interface
Sys_Blk_GV
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Figure 1-4. Intel® 910GL Express Chipset System Block Diagram Example
Intel® Celeron®
Processor
D
533 MHz
System Bus
Intel® 910GL Express Chipset
Analog
Display
System Memory
VGA
Channel A
DDR
DDR
Add2
Card
Display
Display
Intel® 82910GL GMCH
SDVO
Channel B
DMI Interface
USB 2.0
8 ports, 480 Mb/s
Power Management
Clock Generation
LAN Connect/ASF
GPIO
Intel® ICH6
4 Serial ATA Ports
150 MB/s
System
Management (TCO)
SMBus 2.0/I2C
2 ATA 100 Ports
Seven PCI Masters
AC '97
3 CODEC support
PCI Bus
Flash
BIOS
SIO
LPC
Interface
Sys_Blk_GL
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Figure 1-5. Intel® 915PL Express Chipset System Block Diagram Example
Intel® Pentium®
4
Processor or Intel®
Celeron® D Processor
533/800 MHz FSB
Intel® 915PL Express Chipset
System Memory
DDR
Channel A
Channel B
PCI Express*
x16 Graphics
Intel®
82915PL
MCH
Graphics
Card
Display
DDR
DMI Interface
USB 2.0
8 ports, 480 Mb/s
Power Management
IDE
Clock Generation
LAN Connect/ASF
4 SATA Ports
150 MB/s
Intel® ICH6x
AC '97/Intel® High
Definition Audio
CODECs
System
Management (TCO)
SMBus 2.0/I2C
PCI Express* x1
GPIO
Intel® PCI Express
Gigabit Ethernet
Seven PCI Masters
PCI Bus
Flash
BIOS
SIO
LPC
Interface
Sys_Blk_P
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Figure 1-6. Intel® 915GL Express Chipset System Block Diagram Example
Intel® Pentium®
4
Processor or Intel®
Celeron® D Processor
533/800 MHz
System Bus
Intel® 915GL Express Chipset
Analog
Display
VGA
System Memory
DDR
DDR
Add2
Card
Display
Display
Channel A
Channel B
Intel® 82915GL GMCH
SDVO
DDR
DDR
DMI Interface
USB 2.0
8 ports, 480 Mb/s
Power Management
Clock Generation
LAN Connect/ASF
GPIO
Intel® ICH6
4 Serial ATA Ports
150 MB/s
System
Management (TCO)
SMBus 2.0/I2C
2 ATA 100 Ports
Seven PCI Masters
AC '97
3 CODEC support
PCI Bus
Flash
BIOS
SIO
LPC
Interface
Sys_Blk_GV
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1.1
Terminology
Term
Description
Advanced Digital Display Card – 2nd Generation. Provides digital display options for an
Intel graphics controller that supports ADD2 cards. This card plugs into a x16 PCI
Express connector but uses the multiplexed SDVO interface. Will not work with an Intel
graphics controller that supports DVO and ADD cards.
ADD2 Card
Core refers to the internal base logic in the (G)MCH.
Cathode Ray Tube.
Core
CRT
DBI
Dynamic Bus Inversion.
Double Data Rate SDRAM memory technology.
A second generation Double Data Rate SDRAM memory technology.
The Direct Media Interface is the connection between the (G)MCH and the Intel® ICH6.
DDR
DDR2
DMI
Digital Video Interface. This is the specification that defines the connector and interface
for digital displays.
DVI
Front Side Bus. The FSB is synonymous with Host or processor bus
FSB
Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN# and
PWROK are asserted.
Full Reset
Graphics Memory Controller Hub component that contains the processor interface,
DRAM controller, and integrated graphics device. It may also contain an x16 PCI
Express port (typically the external graphics interface). It communicates with the I/O
controller hub (ICH6*) over the DMI interconnect. Throughout this document GMCH
refers to the Intel® 82915G GMCH, 82915GV GMCH, 82915GL, and 82910GL, unless
otherwise specified. Note that term (G)MCH is used when referring to both GMCH and
MCH components.
GMCH
High Definition Multimedia Interface. HDMI supports standard, enhanced, or high-
definition video, plus multi-channel digital audio on a single cable. It transmits all ATSC
HDTV standards and supports 8-channel digital audio, with bandwidth to spare for
future requirements and enhancements (additional details are available through
www.HDMI.org)
HDMI
This term is used synonymously with processor.
Host
An interrupt request signal where X stands for interrupts A,B,C, and D.
INTx
Intel® ICH6
Sixth generation I/O Controller Hub component that contains additional functionality
compared to previous ICH6s. The Intel® I/O Controller Hub component contains the
primary PCI interface, LPC interface, USB2, ATA-100, and other I/O functions. It
communicates with the GMCH over a proprietary interconnect called DMI.
Internal Graphics Device.
Liquid Crystal Display.
IGD
LCD
LVDS
Low Voltage Differential Signaling. A high speed, low power data transmission standard
used for display connections to LCD panels.
24
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Term
Description
The Memory Controller Hub (MCH) component contains the processor interface and
DRAM controller; however, it does not contain an internal graphics device like the
GMCH. It may also contain an x16 PCI Express port (typically the external graphics
interface). It communicates with the I/O controller hub (ICH6*) and other I/O controller
hubs over the DMI interconnect. Throughout this document the term MCH refers to the
82915P and 82915PL MCH. Note: (G)MCH is used when referring to both GMCH and
MCH components.
MCH
Message Signaled Interrupt. A transaction initiated outside the host, conveying interrupt
information to the receiving agent through the same path that normally carries read and
write commands.
MSI
Third Generation Input Output (PCI Express) Graphics Attach called PCI Express
Graphics. A high-speed serial interface whose configuration is software compatible with
the existing PCI specifications. The specific PCI Express implementation intended for
connecting the GMCH to an external graphics controller is a x16 link and replaces AGP.
PCI Express*
Primary PCI
The physical PCI bus that is driven directly by the ICH6 component. Communication
between Primary PCI and the GMCH occurs over DMI. Note that the Primary PCI bus is
not PCI Bus 0 from a configuration standpoint.
System Control Interrupt. SCI is used in ACPI protocol.
SCI
Serial Digital Video Out (SDVO). Digital display channel that serially transmits digital
display data to an external SDVO device. The SDVO device accepts this serialized
format and then translates the data into the appropriate display format (i.e., TMDS,
LVDS, TV-Out). This interface is not electrically compatible with the previous digital
display channel - DVO. For the Intel® 82915G GMCH, The SDVO interface is
multiplexed on a portion of the x16 graphics PCI Express interface.
SDVO
Third party codec that uses SDVO as an input. An SDVO device may have a variety of
output formats including: DVI, LVDS, HDMI, TV-Out, etc.
SDVO Device
An indication that an unrecoverable error has occurred on an I/O bus.
SERR
SMI
System Management Interrupt. SMI is used to indicate any of several system conditions
(such as thermal sensor events, throttling activated, access to System Management
RAM, chassis open, or other system state related activity).
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16
SDRAM devices in parallel, ignoring ECC. These devices are usually, but not always,
mounted on a single side of a DIMM.
Rank
Transition Minimized Differential Signaling. Signaling interface from Silicon Image that
is used in DVI and HDMI.
TMDS
TOLM
Top Of Low Memory. The highest address below 4 GB for which a processor-initiated
memory read or write transaction will create a corresponding cycle to DRAM on the
memory interface.
Voltage Controlled Oscillator.
VCO
UMA
Unified Memory Architecture. UMA describes an IGD using system memory for its
frame buffers.
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1.2
Reference Documents
Document Title
Document
Number/Location
Intel® 915G/915GV/910GL Express Chipset Thermal Design Guide
Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
http://intel.com/design/chip
sets/designex/301469.htm
http://developer.intel.com/d
esign/chipsets/datashts/30
1473.htm
Advanced Configuration and Power Interface Specification, Version 2.0
Advanced Configuration and Power Interface Specification, Version 1.0b
The PCI Local Bus Specification, Version 2.3
http://www.acpi.info/
http://www.acpi.info/
http://www.pcisig.com/spe
cifications
PCI Express* Specification, Version 1.0a
http://www.pcisig.com/spe
cifications
1.3
GMCH (MCH) Overview
The (G)MCH connects to the processor as shown in Figure 1-1, Figure 1-2, Figure 1-3, Figure
1-4, Figure 1-5, and Figure 1-6. A major role of the (G)MCH in a system is to manage the flow of
information between its interfaces: the processor interface (FSB), the System Memory interface
(DRAM controller), the Integrated Graphics interface (82915G/82915GV/82915GL/82910GL
GMCH only), the External Graphics interface via PCI Express (82915G/82915P/82915PL MCH
only), and the I/O Controller Hub through the DMI interface. This includes arbitrating between
the interfaces when each initiates transactions.
The (G)MCH supports one or two channels of DDR
(82915G/82915GV/82915GL/82915P/82915PL/82910GL) or DDR2 (82915G/82915GV/82915P)
SDRAM. The (G)MCH also supports the new PCI Express based external graphics attach. Thus,
the 915G/915GV/915GL/910GL/915P and 915PL Express chipsets are NOT compatible with
AGP (1X, 2X, 4X, or 8X).
To increase system performance, the (G)MCH incorporates several queues and a write cache. The
(G)MCH also contains advanced desktop power management logic.
1.3.1
Host Interface
The (G)MCH is optimized for both the Pentium 4 processors in the LGA775 socket and the
Celeron D processor in the FC-mPGA4 socket. The (G)MCH can use a single LGA 775 socket
processor. The (G)MCH supports FSB frequency of 533/800 MT/s (133/200 MHz HCLK) using
a scalable FSB Vcc_CPU (82910GL only supports 533 MT/s, 133 MHz HCLK). The (G)MCH
supports the Pentium 4 processor subset of the Extended Mode Scaleable Bus Protocol. The
primary enhancements over the Compatible Mode P6 bus protocol are: Source synchronous
double-pumped (2) Address and Source synchronous quad-pumped (4x) Data.
The (G)MCH supports 32-bit host addressing, decoding up to 4 GB of the processor’s memory
address space. Host-initiated I/O cycles are decoded to PCI Express, DMI, or the (G)MCH
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configuration space. Host-initiated memory cycles are decoded to PCI Express, DMI, or system
memory. PCI Express device accesses to non-cacheable system memory are not snooped on the
host bus. Memory accesses initiated from PCI Express using PCI semantics and from DMI to
system memory will be snooped on the host bus.
1.3.2
System Memory Interface
The (G)MCH integrates a system memory DDR/DDR2 controller with two, 64-bit wide interfaces
(82910GL, 82915PL, and 82915GL supports DDR only). Only Double Data Rate (DDR/DDR2)
memory is supported; consequently, the buffers support only SSTL_2/1.8 V signal interfaces. The
memory controller interface is fully configurable through a set of control registers. Features of the
(G)MCH memory controller include:
• The (G)MCH System Memory Controller directly supports one or two channels of memory
(each channel consisting of 64 data lines).
• Supports two memory addressing organization options:
⎯ The memory channels are asymmetric: "Stacked" channels are assigned addresses
serially. Channel B addresses are assigned after all Channel A addresses.
⎯ The memory channels are interleaved: Addresses are ping-ponged between the channels
after each cache line (64-B boundary).
• Available bandwidth up to:
⎯ 3.2 GB/s (DDR/DDR2 400) for single-channel mode
⎯ 6.4 GB/s in dual-channel interleaved mode assuming DDR or DDR2 400 MHz.
⎯ 8.5 GB/s in dual-channel interleaved mode assuming DDR2 533 MHz.
• Supports DDR memory DIMM frequencies of 333 MHz and 400 MHz or DDR2 memory
DIMM frequencies of 400 MHz and 533 MHz. All DIMMs in a system must be of the same
type (e.g., all DDR or all DDR2, not mixed). The speed used in all channels is the speed of
the slowest DIMM in the system.
• 82910GL supports DDR memory only, DIMM frequencies of 333 MHz and 400 MHz, dual
channel mode, 1-DIMM maximum per channel.
• I/O Voltage of 2.6 V for DDR, and 1.8 V for DDR2.
• Supports non-ECC memory only.
• Supports 256-Mb, 512-Mb and 1-Gb DDR/DDR2 technologies
• Supports only x8, x16, DDR/DDR2 devices with four banks and also supports eight bank,
1-Gbit DDR2 devices.
• Supports opportunistic refresh
• In dual channel mode the (G)MCH supports 64 simultaneously open pages (four ranks of
eight bank devices* 2 channels)
• Supports Partial Writes to memory using Data Mask (DM) signals.
• Supports page sizes of 4 KB, 8 KB and 16 KB.
• Supports a burst length of 8 for single-channel and dual-channel interleaved and asymmetric
operating modes.
• Supports unbuffered DIMMs.
• SPD (Serial Presence Detect) scheme for DIMM detection support
• Suspend-to-RAM support using CKE
• Supports configurations defined in the JEDEC DDR/DDR2 DIMM specification only
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By using 256-Mb technology, the smallest memory capacity possible is 128 MB, assuming single-
channel mode. (16M rows * 16b/(row*device) * 4 devices/DIMM-side * 1 DIMM-side/channel *
1 channel *1B/8b = 128 MB). By using 1-Gb technology in dual-channel interleaved mode, the
largest memory capacity possible is 8 GB. (128M rows * 8b/(row*device) * 8 devices/DIMM-
side * 4 DIMM-sides/channel * 2 channels * 1B/8b * 1G/1024M = 8 GB). This exceeds a 32-bit
address limit of 4 GB. In a 32-bit system, only the first 4 GB of memory will be accessible.
The (G)MCH supports a memory thermal management scheme to selectively manage reads and/or
writes. Memory thermal management can be triggered either by on-die thermal sensor, or by
preset limits. Management limits are determined by weighted sum of various commands that are
scheduled on the memory interface.
1.3.3
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the (G)MCH and ICH6.
This high-speed interface integrates advanced priority-based servicing allowing for concurrent
traffic and true isochronous transfer capabilities. Base functionality is completely software
transparent permitting current and legacy software to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions,
the ICH6 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a
fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of
traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both
ends of the DMI link (i.e., the ICH6 and (G)MCH). Features of the DMI include:
• A chip-to-chip connection interface to ICH6
• 2 GB/s point-to-point DMI to ICH6 (1 GB/s each direction)
• 100 MHz reference clock (shared with PCI Express Graphics Attach).
• 32-bit downstream addressing
• APIC and MSI interrupt messaging support. Will send Intel-defined “End Of Interrupt”
broadcast message when initiated by the processor.
• Message Signaled Interrupt (MSI) messages
• SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
1.3.4
PCI Express* Graphics Interface (Intel® 82915G/82915P/
and 82915PL Only)
The (G)MCH (82915G, 82915P, and 82915PL only) contains a 16-lane (x16) PCI Express port
intended for an external PCI Express graphics card. The PCI Express port is compatible with the
PCI Express Base Specification revision 1.0a. The x16 port operates at a frequency of 2.5 Gb/s on
each lane while employing 8b/10b encoding, and supports a maximum theoretical bandwidth of
4 Gb/s each direction. The 82915G GMCH multiplexes the PCI Express interface with two Intel®
SDVO ports.
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Features of the PCI Express Interface include:
• One x16 PCI Express port intended for graphics attach, compatible with the PCI Express
Base Specification revision 1.0a.
• Theoretical PCI Express transfer rate of 2.5 Gb/s.
• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a theoretical bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface
• Maximum theoretical realized bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when (1)x16.
• PCI Express Graphics Extended Configuration Space. The first 256 bytes of configuration
space alias directly to the PCI Compatibility configuration space. The remaining portion of
the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as
extended configuration space.
• PCI Express Enhanced Addressing Mechanism. Accessing the device configuration space in
a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Supports traditional AGP style traffic (asynchronous non-snooped, PCI Express-relaxed
ordering)
• Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e., normal
PCI 2.3 Configuration space as a PCI-to-PCI bridge)
• Supports “static” lane numbering reversal. This method of lane reversal is controlled by a
Hardware Reset strap, and reverses both the receivers and transmitters for all lanes (e.g.,
TX15->TX0, RX15->RX0). This method is transparent to all external devices and is different
than lane reversal as defined in the PCI Express Specification. In particular, link initialization
is not affected by static lane reversal.
1.3.5
Integrated Graphics (Intel®
82915G/82915GV/82910GL/82915GL GMCH Only)
The 82915G/82915GV/82910GL/915GL GMCH provides an integrated graphics device (IGD)
delivering cost competitive 3D, 2D and video capabilities. The GMCH contains an extensive set
of instructions for 3D operations, BLT and Stretch BLT operations, motion compensation,
overlay, and display control. The GMCH’s video engines support video conferencing and other
video applications. The GMCH does not support a dedicated local graphics memory interface, it
may only be used in a UMA configuration. The GMCH also has the capability to support external
graphics accelerators via the PCI Express Graphics port but cannot work concurrently with the
integrated graphics devce. High bandwidth access to data is provided through the system memory
port. The GMCH also provides 3D hardware acceleration for block level transfers of data (BLTs).
2D BLTs are considered a special case of 3D transfers and use the 3D acceleration. The BLT
engine provides the ability to copy a source block of data to a destination and perform raster
operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination.
Performing these common tasks in hardware reduces processor load, and thus improves
performance.
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GMCH graphics support includes:
• Core Frequency of 333 MHz
• 3D Graphics Rendering Enhancements
⎯1.3 Dual Texture GigaPixel/Sec Fill Rate
⎯Flat and Gouraud Shading
• High Quality 3D Setup and Render Engine
⎯Setup matching processor geometry delivery
⎯Color Alpha Blending for Transparency
rates
⎯Vertex and Programmable Pixel Fog and
⎯Triangle lists, strips and fans
⎯Indexed vertex and flexible vertex formats
⎯Vertex cache
Atmospheric Effects
⎯Color Specular Lighting
⎯Z Bias Support
⎯Pixel accurate fast scissoring and clipping
⎯Dithering
operation
⎯Anti-Aliased Lines
⎯Backface culling
⎯16- and 24-bit Z Buffering
⎯8-bit Stencil Buffering
⎯Double and Triple Render Buffer Support
⎯16- and 32-bit Color
⎯Destination Alpha
⎯Supports D3D and OpenGL pixelization rules
⎯Anti-aliased lines
⎯Sprite points
⎯Zone Rendering Technology 3
⎯Shadow maps
⎯Maximum 3D Resolution Supported:
⎯Double-sided stencil
1600x1200x32@85Hz
• High-Quality Texture Engine
⎯Fast Clear Support
⎯533 MegaTexel/Sec Performance –
266 Mpixel/Sec fill rate up to 2 bilinear
textures
• 2D Graphics
⎯Optimized 256-bit BLT Engine
⎯Alpha Stretch Blitter
⎯Hardware Pixel Shader 2.0
⎯Per-pixel perspective corrected texture
⎯Anti-aliased Lines
mapping
⎯32-bit Alpha Blended Cursor
⎯Color Space Conversion
⎯Programmable 3-Color Transparent Cursor
⎯8-, 16- and 32-bit Color
⎯ROP Support
⎯2/10/10/10 texture format
⎯Bi-cubic filtering
⎯Single-pass quad texture compositing
⎯Enhanced texture blending functions
⎯12 levels of detail mip map sizes from 1x1 to
• Video Overlay
2Kx2K
⎯Advanced Deinterlacing
⎯All texture formats including 32-bit RGBA and
8-bit palettes
⎯Process Amplifier Color Control
⎯Single High Quality Scalable Overlay
⎯Alpha and luminance maps
⎯Texture color-keying/chromakeying
• Multiple Overlay Functionality provided via Stretch
⎯Bilinear, trilinear and anisotropic mip-mapped
Blitter (PIP, Video Conferencing, etc.)
filtering
⎯5-tap Horizontal, 2-tap Vertical Filtered Scaling
⎯Independent Gamma Correction
⎯Independent Brightness/Contrast/Saturation
⎯Independent Tint/Hue Support
⎯Cubic environment reflection mapping
⎯Embossed and DOT3 bump-mapping
⎯DXTn and FXT1 texture decompression
⎯Non-power of 2 texture
⎯Destination Color-keying
⎯Render to texture
⎯Source Chroma-keying
• Video DVD/PC-VCR
⎯Maximum Source Resolution: 720x480x32
⎯H/W Motion Compensation for MPEG2
⎯Maximum Overlay Display Resolution:
2048x1536x32
⎯Dynamic Bob and Weave Support for Video
Streams
⎯Video Mixer Render (VMR)
⎯Source Resolution up to 1920x1080 with
2 vertical taps
⎯Software DVD At 30 fps, Full Screen
⎯Supports 720x480 DVD Quality Encoding at
low processor Utilization for PC-VCR or home
⎯movie recording and editing
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1.3.6
Analog and Intel® SDVO Displays (Intel®
82915G/82915GV/82910GL/82915GL GMCH Only)
The GMCH provides interfaces to a progressive scan analog monitor and two SDVO ports
(multiplexed with PCI Express x16 Graphics Port signals) capable of driving an ADD2 card. The
digital display channels are capable of driving a variety of SDVO devices (e.g., TMDS, TV-Out).
Note that SDVO only works with the Integrated Graphics Device (IGD). The GMCH provides
two SDVO ports that are capable of driving up to a 200 MHz pixel clock each.
The GMCH SDVO ports can each support a single-channel SDVO device. If both ports are active
in single-channel mode, they can have different display timing and data. Alternatively, the SDVO
ports can combine to support dual channel devices, supporting higher resolutions and refresh
rates. The GMCH is compliant with DVI Specification 1.0. When combined with a DVI
compliant external device and connector, the GMCH has a high-speed interface to a digital
display (e.g., flat panel or digital CRT).
The GMCH Supports Hot-Plug and Display for PCI Express* x16 Graphics. This is not supported
for ADD2 cards.
1.3.7
1.3.8
System Interrupts
The (G)MCH interrupt support includes:
• Supports both 8259 and Pentium 4 processor FSB interrupt delivery mechanisms.
• Supports interrupts signaled as upstream Memory Writes from PCI Express and DMI
⎯ MSIs routed directly to FSB
⎯ From I/OxAPICs
(G)MCH Clocking
The differential FSB clock (HCLKP/HCLKN) can be set to either 133 MHz or 200 MHz
(82915G/82915GV/82915GL/82915P/82915PL only). This supports FSB transfer rates of 533
MT/s and 800 MT/s (82915G/82915GV/82915GL/82915P/82915PL only). The Host PLL
generates 2X, 4X, and 8X versions of the host clock for internal optimizations. The (G)MCH core
clock is synchronized to the host clock.
The internal and external memory clocks of 133 MHz and 200 MHz are generated from one of
two (G)MCH PLLs that use the host clock as a reference. This includes 2X and 4X for internal
optimizations.
For the 82915G/82915P/82915PL (G)MCH, the PCI Express core clock of 250 MHz is generated
from a separate PCI Express PLL. This clock uses the fixed 100 MHz Serial Reference Clock
(GCLKP/GCLKN) for reference.
For the 82915G/82915GV/82915GL/82910GL GMCH, display timings are generated from
display PLLs that use a 96 MHz differential non-spread spectrum clock as a reference. Display
PLLs can also use the SDVO_TVCLKIN[+/-] from an SDVO device as a reference.
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All of the above mentioned clocks are capable of tolerating Spread Spectrum clocking as defined
in the Clock Generator specification. Host, Memory, and PCI Express* x16 Graphics PLLs, and
all associated internal clocks are disabled until PWROK is asserted.
1.3.9
Power Management
(G)MCH Power Management support includes:
• PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)
• SMRAM space remapping to A0000h (128 KB)
• Supports extended SMRAM space above 256 MB, additional 1-MB TSEG from the Base of
graphics stolen memory (BSM) when enabled, and cacheable (cacheability controlled by
processor)
• ACPI Rev 1.0 compatible power management
• Supports processor states: C0, C1, C2, C3, and C4
• Supports System states: S0, S1, S3, S4, and S5
• Supports processor Thermal Management 2 (TM2)
• Microsoft Windows NT* Hardware Design Guide v1.0 compliant
§
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2 Signal Description
This chapter provides a detailed description of (G)MCH signals. The signals are arranged in
functional groups according to their associated interface. The states of all of the signals during
reset are provided in Section 2.11.
The following notations are used to describe the signal type:
GTL+
PCIE
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for
complete details. The (G)MCH integrates GTL+ termination resistors, and
supports VTT of from 0.83 V to 1.65 V (including guardbanding).
PCI-Express interface signals. These signals are compatible with PCI Express
1.0 Signaling Environment AC Specifications and are AC coupled. The buffers
are not 3.3 V tolerant. Differential voltage specification = (|D+ - D-|) * 2
= 1.2 V maximum. Single-ended maximum = 1.5 V.
Single-ended minimum = 0 V.
DMI
Direct Media Interface signals. These signals are compatible with PCI Express
1.0 Signaling Environment AC Specifications, but are DC coupled. The buffers
are not 3.3 V tolerant. Differential voltage specification
= (|D+ - D-|) * 2 = 1.2 V maximum. Single-ended maximum = 1.5 V.
Single-ended minimum = 0 V.
CMOS
COD
CMOS buffers. 1.5 V tolerant.
CMOS Open Drain buffers. 2.5 V tolerant.
High Voltage CMOS buffers. 2.5 V tolerant.
High Voltage CMOS input-only buffers. 3.3 V tolerant.
HVCMOS
HVIN
SSTL-2
Stub Series Termination Logic. These are 2.6 V output capable buffers. 2.6 V
tolerant.
SSTL-1.8
A
Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
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Figure 2-1. Intel® (G)MCH Signal Interface Diagram
HA[31:3]#
HD[63:0]
HADS#
HSYNC
VSYNC
Intel®
RED, RED#
GREEN, GREEN#
BLUE, BLUE#
REFSET
DDC_CLK
DDC_DATA
82915G/
82915GV/
82910GL
Only
HBNR#
Analog
Display
HBPRI#
HDBSY#
HDEFER#
HDRDY#
HEDRDY#
HHIT#
SDVOB_GREEN-, SDVOB_GREEN+
SDVOB_BLUE-, SDVOB_BLUE+
SDVOC_RED- / SDVOB_ALPHA-,
SDVOC_RED+ / SDVOB_ALPHA+
SDVOC_GREEN-, SDVOC_GREEN+
SDVOC_BLUE-, SDVOC_BLUE+
SDVOC_CLK-, SDVOC_CLK+
SDVO_TVCLKIN-, SDVO_TVCLKIN,
SDVOB_INT-, SDVOB_INT+
SDVOC_INT-, SDVOC_INT+
SDVO_STALL-, SDVO_STALL+
SDVO_CTRLCLK
HHITM#
Processor
HLOCK#
System
HREQ[4:0]#
Bus
HPCREQ#
Interface
HTRDY#
HRS[2:0]#
HCPURST#
HBREQ0#
HDINV[3:0]#
Intel®
SDVO
Device
Interface1
Intel®
82915G/
82915GV/
82910GL
Only
HADSTB[1:0]#
HDSTBP[3:0]#, HDSTBN[3:0]#
BSEL[2:0]
SDVO_CTRLDATA
HRCOMP
HSCOMP
HSWING
HVREF
PCI
Express
x16
Graphics
Port
EXP_RXN[15:0], EXP_RXP[15:0]
EXP_TXN[15:0], EXP_TXP[15:0]
EXP_COMPO
EXP_COMPI
EXP_SLR
Intel®
82915G/
82915P
Only
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
SRAS_A#
SCAS_A#
SWE_A#
SDQ_A[63:0]
System
Memory2
HCLKP, HCLKN
GCLKP, GCLKN
DREFCLKN, DREFCLKP
RSTIN#
PWROK
EXTTS#
BSEL[2:0]
MTYPE
ICH_SYNC#
DDR/
DDR2
Channel
A
Clocks,
Reset, and
Misc.
SDM_A[7:0]
SDQS_A[7:0], SDQS_A[7:0]#
SCKE_A[3:0]
SCLK_A[5:0], SCLK_A[5:0]#
SODT_A[3:0]
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
SRAS_B#
SCAS_B#
SWE_B#
Direct
Media
Interface
System
DMI_RXP[3:0], DMI_RXN[3:0]
DMI_TXP[3:0], DMI_TXN[3:0]
Memory2
DDR/
DDR2
Channel
B
SDQ_B[63:0]
SDM_B[7:0]
SDQS_B[7:0], SDQS_B[7:0]#
SCKE_B[3:0]
SCLK_B[5:0], SCLK_B[5:0]#
SODT_B[3:0]
VCC
VTT
VCC_EXP
VCCSM
VCC2
Voltage
Reference,
and Power
VCCA_EXPPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_SMPLL
SRCOMP[1:0]
SOCOMP[1:0]
SM_SLEWIN[1:0]
SM_SLEWOUT[1:0]
SMVREF[1:0]
System
Memory2
VSS
Intel®
DDR/DDR2
Ref./ Comp.
82915G/
82915GV/
82910GL
Only
VCCA_DAC
VSSA_DAC
Note:
1. SDVO signals on the 82915G GMCH are multiplexed with the PCI Express x16 Graphics Port signals.
2. The 82910GL GMCH only supports DDR (not DDR2).
Signal_Info
34
Datasheet
Signal Description
R
2.1
Host Interface Signals
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
voltage of the Host Bus (VTT).
Signal Name
Type
Description
HADS#
I/O
Address Strobe: The processor bus owner asserts HADS# to indicate the
first of two cycles of a request phase. The (G)MCH can assert this signal for
snoop cycles and interrupt messages.
GTL+
HBNR#
HBPRI#
I/O
Block Next Request: This signal is used to block the current request bus
owner from issuing new requests. This signal is used to dynamically control
the processor bus pipeline depth.
GTL+
O
Priority Agent Bus Request: The (G)MCH is the only Priority Agent on the
processor bus. It asserts this signal to obtain the ownership of the address
bus. This signal has priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
GTL+
HBREQ0#
I/O
Bus Request 0: The (G)MCH pulls the processor’s bus HBREQ0# signal
low during HCPURST#. The processor samples this signal on the active-to-
inactive transition of HCPURST#. The minimum setup time for this signal is
4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is
20 HCLKs. HBREQ0# should be tristated after the hold time requirement
has been satisfied.
GTL+
HCPURST#
O
CPU Reset: The HCPURST# pin is an output from the (G)MCH. The
(G)MCH asserts HCPURST# while RSTIN# is asserted and for
approximately 1 ms after RSTIN# is de-asserted. The HCPURST# allows
the processors to begin execution in a known state.
GTL+
Note that the Intel® ICH6 must provide processor frequency select strap set-
up and hold times around HCPURST#. This requires strict synchronization
between (G)MCH HCPURST# de-assertion and the Intel® ICH6 driving the
straps.
HDBSY#
I/O
GTL+
O
Data Bus Busy: This signal is used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
HDEFER#
Defer: Signals that the (G)MCH will terminate the transaction currently
being snooped with either a deferred response or with a retry response.
GTL+
HDINV[3:0]#
I/O
Dynamic Bus Inversion: Driven along with the HD[63:0] signals. Indicates
if the associated signals are inverted or not. HDINV[3:0]# are asserted such
that the number of data bits driven electrically low (low voltage) within the
corresponding 16 bit group never exceeds 8.
GTL+
HDINVx#
Data Bits
HDINV3#
HDINV2#
HDINV1#
HDINV0#
HD[63:48]
HD[47:32]
HD[31:16]
HD[15:0]
Datasheet
35
Signal Description
R
Signal Name
Type
Description
HDRDY#
HEDRDY#
HA[31:3]#
I/O
GTL+
O
Data Ready: This signal is asserted for each cycle that data is transferred.
Early Data Ready: This signal indicates that the data phase of a read
transaction will start on the bus exactly one common clock after assertion.
GTL+
I/O
Host Address Bus: HA[31:3]# connect to the processor address bus.
During processor cycles, the HA[31:3]# are inputs. The (G)MCH drives
HA[31:3]# during snoop cycles on behalf of DMI and PCI Express Graphics
initiators. HA[31:3]# are transferred at 2x rate.
GTL+
HADSTB[1:0]#
HD[63:0]
I/O
GTL+
I/O
Host Address Strobe: The source synchronous strobes used to transfer
HA[31:3]# and HREQ[4:0] at the 2x transfer rate.
Host Data: These signals are connected to the processor data bus. Data on
HD[63:0] is transferred at 4x rate. Note that the data signals may be
inverted on the processor bus, depending on the HDINV[3:0]# signals.
GTL+
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
Differential Host Data Strobes: The differential source synchronous
strobes are used to transfer HD[63:0] and HDINV[3:0]# at 4x transfer rate.
GTL+
These signals are named this way because they are not level sensitive.
Data is captured on the falling edge of both strobes. Hence, they are
pseudo-differential, and not true differential.
Strobes
Data
Bits
HDSTBP3#, HDSTBN3#
HDSTBP2#, HDSTBN2#
HDSTBP1#, HDSTBN1#
HDSTBP0#, HDSTBN0#
HD[63:48]
HD[47:32]
HD[31:16]
HD[15:0]
HDINV3#
HDINV2#
HDINV1#
HDINV0#
HHIT#
I/O
Hit: This signal indicates that a caching agent holds an unmodified version
of the requested line. Also, driven in conjunction with HHITM# by the target
to extend the snoop window.
GTL+
HHITM#
I/O
Hit Modified: This signal indicates that a caching agent holds a modified
version of the requested line and that this agent assumes responsibility for
providing the line. This signal is also driven in conjunction with HHIT# to
extend the snoop window.
GTL+
HLOCK#
I/O
Host Lock: All processor bus cycles sampled with the assertion of HLOCK#
and HADS#, until the negation of HLOCK# must be atomic (i.e., no DMI or
PCI Express Graphics accesses to DRAM are allowed when HLOCK# is
asserted by the processor).
GTL+
HPCREQ#
I
Precharge Request: The processor provides a “hint” to the (G)MCH that it
is OK to close the DRAM page of the memory read request with which the
hint is associated. The (G)MCH uses this information to schedule the read
request to memory using the special “AutoPrecharge” attribute. This causes
the DRAM to immediately close (Precharge) the page after the read data
has been returned. This allows subsequent processor requests to more
quickly access information on other DRAM pages, since it will no longer be
necessary to close an open page prior to opening the proper page.
Asserted by the requesting agent during both halves of Request Phase. The
same information is provided in both halves of the request phase.
GTL+
2x
36
Datasheet
Signal Description
R
Signal Name
Type
Description
HREQ[4:0]#
I/O
GTL+
2x
Host Request Command: These signals define the attributes of the
request. HREQ[4:0]# are transferred at 2x rate. They are asserted by the
requesting agent during both halves of Request Phase. In the first half the
signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second half the signals carry additional
information to define the complete transaction type.
The transactions supported by the (G)MCH Host Bridge are defined in the
Host Interface section of this document.
HTRDY#
O
Host Target Ready: This signal indicates that the target of the processor
transaction is able to enter the data transfer phase.
GTL+
O
HRS[2:0]#
Response Signals: These signals indicate the type of response as shown
below:
GTL+
000 = Response type
001 = Idle state
010 = Retry response
011 = Deferred response
100 = Reserved (not driven by (G)MCH)
101 = Hard Failure (not driven by (G)MCH)
110 = No data response
111 = Implicit Writeback
111 = Normal data response
BSEL[2:0]
HRCOMP
HSCOMP
HSWING
I
CMOS
I/O
Bus Speed Select: At the de-assertion of RSTIN#, the value sampled on
these pins determines the expected frequency of the bus.
Host RCOMP: Used to calibrate the Host GTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (VTT).
Slew Rate Compensation: Compensation for the Host Interface.
CMOS
I/O
CMOS
I
Host Voltage Swing: This signal provides the reference voltage used by
FSB RCOMP circuits. HSWING is used for the signals handled by
HRCOMP.
A
HVREF
I
Host Reference Voltage Reference: Voltage input for the data, address,
and common clock signals of the Host GTL interface.
A
Datasheet
37
Signal Description
R
2.2
DDR/DDR2 DRAM Channel A Interface
Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM.
Signal Name
Type
Description
SCLK_A[5:0]
O
SSTL-
2/1.8
SDRAM Differential Clock: (3 per DIMM). SCLK_Ax and its
complement SCLK_Ax# signal make a differential clock pair output. The
crossing of the positive edge of SCLK_Ax and the negative edge of its
complement SCLK_Ax# are used to sample the command and control
signals on the SDRAM.
SCLK_A[5:0]#
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
O
SSTL-
2/1.8
SDRAM Complementary Differential Clock: (3 per DIMM) These are
the complementary differential DDR/DDR2 clock signals.
O
SSTL-
2/1.8
Chip Select: (1 per Rank) These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank.
O
SSTL-
2/1.8
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM
O
Bank Select: These signals define which banks are selected within each
SSTL-
2/1.8
SDRAM rank
DDR2: 1-Gb technology is 8 banks.
DDR: 1-Gb technology is 4 banks. SBS_A[2] is not used.
SRAS_A#
SCAS_A#
SWE_A#
O
SSTL-
2/1.8
Row Address Strobe: This signal is used with SCAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
O
SSTL-
2/1.8
Column Address Strobe: This signal is used with SRAS_A# and
SWE_A# (along with SCS_A#) to define the SDRAM commands.
O
Write Enable: This signal is used with SCAS_A# and SRAS_A# (along
SSTL-
2/1.8
with SCS_A#) to define the SDRAM commands.
SDQ_A[63:0]
I/O
SSTL-
2/1.8
2x
Data Lines: SDQ_A signals interface to the SDRAM data bus.
SDM_A[7:0]
O
Data Mask: When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one SDM_Ax signal for
every data byte lane.
SSTL-
2/1.8
2X
SDQS_A[7:0]
I/O
SSTL-
2/1.8
2x
Data Strobes: For DDR, the rising and falling edges of SDQS_Ax are
used for capturing data during read and write transactions. For DDR2,
SDQS_Ax and its complement SDQS_Ax# signal make up a differential
strobe pair. The data is captured at the crossing point of SDQS_Ax and
its complement SDQS_Ax# during read and write transactions.
SDQS_A[7:0]#
I/O
SSTL-1.8
2x
Data Strobe Complements (DDR2 only): These signals are the
complementary DDR2 strobe signals.
38
Datasheet
Signal Description
R
Signal Name
Type
Description
SCKE_A[3:0]
O
SSTL-
2/1.8
Clock Enable: (1 per Rank) SACKE is used to initialize the SDRAMs
during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
SODT_A[3:0]
O
On Die Termination (DDR2 only): Active On-die Termination Control
SSTL-1.8
signals for DDR2 devices.
2.3
DDR/DDR2 DRAM Channel B Interface
Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM.
Signal Name
Type
Description
SCLK_B[5:0]
O
SSTL-
2/1.8
SDRAM Differential Clock: (3 per DIMM) SCLK_Bx and its complement
SCLK_Bx# signal make a differential clock pair output. The crossing of
the positive edge of SCLK_Bx and the negative edge of its complement
SCLK_Bx# are used to sample the command and control signals on the
SDRAM.
SCLK_B[5:0]#
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
O
SSTL-
2/1.8
SDRAM Complementary Differential Clock: (3 per DIMM) These are
the complementary differential DDR/DDR2 clock signals.
O
SSTL-
2/1.8
Chip Select: (1 per Rank) These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank
O
SSTL-
2/1.8
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM
O
Bank Select: These signals define which banks are selected within
SSTL-
2/1.8
each SDRAM rank
DDR2: 1-Gb technology is 8 banks.
DDR: 1-Gb technology is 4 banks. SBS_B[2] is not used
SRAS_B#
SCAS_B#
SWE_B#
O
SSTL-
2/1.8
Row Address Strobe: This signal is used with SCAS_B# and SWE_B#
(along with SCS_B#) to define the SDRAM commands
O
SSTL-
2/1.8
Column Address Strobe: This signal is used with SRAS_B# and
SWE_B# (along with SCS_B#) to define the SDRAM commands.
O
Write Enable: This signal is used with SCAS_B# and SRAS_B# (along
SSTL-
2/1.8
with SCS_B#) to define the SDRAM commands.
SDQ_B[63:0]
I/O
SSTL-
2/1.8
2x
Data Lines: SDQ_Bx signals interface to the SDRAM data bus
SDM_B[7:0]
O
SSTL-
2/1.8
2x
Data Mask: When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one SDM_Bx signal for
every data byte lane.
Datasheet
39
Signal Description
R
Signal Name
Type
Description
SDQS_B[7:0]
I/O
SSTL-
2/1.8
2x
Data Strobes: For DDR the rising and falling edges of SDQS_Bx are
used for capturing data during read and write transactions. For DDR2,
SDQS_Bx and its complement SDQS_Bx# make up a differential strobe
pair. The data is captured at the crossing point of SDQS_Bx and its
complement SDQS_Bx# during read and write transactions.
SDQS_B[7:0]#
SCKE_B[3:0]
SODT_B[3:0]
I/O
SSTL-1.8
2x
Data Strobe Complements (DDR2 only): These signals are the
complementary DDR2 Strobe signals.
O
SSTL-
2/1.8
Clock Enable: (1 per Rank) SCKE_B is used to initialize the SDRAMs
during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
O
On Die Termination (DDR2 only): Active On-die Termination Control
signals for DDR2 devices.
SSTL-1.8
2.4
DDR/DDR2 DRAM Reference and Compensation
Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM.
Signal Name
Type
Description
SRCOMP[1:0]
SOCOMP[1:0]
I/O
System Memory RCOMP
I/O
A
DDR2 On-Die DRAM Over Current Detection (OCD) driver
compensation (DDR2 only)
SM_SLEWIN[1:0]
I
Buffer Slew Rate Input: Slew Rate characterization buffer input for X
and Y orientation.
A
SM_SLEWOUT[1:0]
SMVREF[1:0]
O
A
Buffer Slew Rate Output: Slew Rate characterization buffer output for X
and Y orientation
I
SDRAM Reference Voltage: Reference voltage inputs for each DQ,
A
DM, DQS, and DQS# input signals.
40
Datasheet
Signal Description
R
2.5
PCI Express* x16 Graphics Port Signals (Intel®
82915G, 82915P, 82915PL Only)
Unless otherwise specified, PCI Express Graphics signals are AC coupled, so the only voltage
specified is a maximum 1.2 V differential swing.
Signal Name
Type
Description
EXP_RXN[15:0]
EXP_RXP[15:0]
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_COMPO
I/O
PCIE
PCI Express Graphics Receive Differential Pair
O
PCIE
PCI Express Graphics Transmit Differential Pair
I
A
PCI Express Graphics Output Current Compensation
Note: EXP_COMP0 is used for DMI current compensation.
PCI Express Graphics Input Current Compensation
Note: EXP_COMPI is used for DMI current compensation.
EXP_COMPI
EXP_SLR
I
A
I
PCI Express* Static Lane Reversal: The (G)MCH’s PCI Express lane
numbers are reversed. For example, the (G)MCH PCI Express interface
signals can be configured as follows:
CMOS
Normal
Lane
Ball
C10
A9
Operation
EXP_TXP0
EXP_TXP1
…
Reversed
EXP_TXP15
EXP_TXP14
…
…
N3
P1
EXP_TXP14…
EXP_TXP15
EXP_TXP1…
EXP_TXP0
0 = (G)MCH’s PCI Express lane numbers are reversed
1 = Normal operation
Datasheet
41
Signal Description
R
2.6
Analog Display Signals (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only)
Signal Name
RED
Type
Description
O
A
RED Analog Video Output: This signal is a CRT Analog video output
from the internal color palette DAC. The DAC is designed for a 37.5 Ω
routing impedance; however, the terminating resistor to ground will be
75 Ω (e.g., 75 Ω resistor on the board, in parallel with a 75 Ω CRT load).
RED#
O
A
O
A
REDB Analog Output: This signal is an analog video output from the
internal color palette DAC. It should be shorted to the ground plane.
GREEN
GREEN Analog Video Output: This signal is a CRT Analog video
output from the internal color palette DAC. The DAC is designed for a
37.5 Ω routing impedance; however, the terminating resistor to ground
will be 75 Ω (e.g., 75 Ω resistor on the board, in parallel with a 75 Ω CRT
load).
GREEN#
BLUE
O
A
O
A
GREENB Analog Output: This signal is an analog video output from the
internal color palette DAC. It should be shorted to the ground plane.
BLUE Analog Video Output: This signal is a CRT Analog video output
from the internal color palette DAC. The DAC is designed for a 37.5 Ω
routing impedance; however, the terminating resistor to ground will be
75 Ω (e.g., 75 Ω resistor on the board, in parallel with a 75 Ω CRT load).
BLUE#
O
A
O
A
BLUEB Analog Output: This signal is an analog video output from the
internal color palette DAC. It should be shorted to the ground plane.
REFSET
Resistor Set: Set point resistor for the internal color palette DAC.
A 255 Ω 1% resistor is required between REFSET and motherboard
ground.
HSYNC
O
CRT Horizontal Synchronization: This signal is used as the horizontal
2.5 V
CMOS
sync (polarity is programmable) or “sync interval”. 2.5 V output
VSYNC
O
CRT Vertical Synchronization: This signal is used as the vertical sync
2.5 V
CMOS
(polarity is programmable). 2.5 V output.
DDC_CLK
DDC_DATA
I/O
2.5 V
CMOS
Monitor Control Clock. This signal may be used as the DDC_CLK for a
secondary multiplexed digital display connector.
I/O
Monitor Control Data. This signal may be used as the DDC_Data for a
2.5 V
CMOS
secondary multiplexed digital display connector.
42
Datasheet
Signal Description
R
2.7
Clocks, Reset, and Miscellaneous
Signal Name
Type
Description
HCLKP
HCLKN
I
Differential Host Clock In: These pins receive a differential host clock
from the external clock synthesizer. This clock is used by all of the
(G)MCH logic that is in the Host clock domain.
CMOS
GCLKP
GCLKN
I
Differential PCI Express Graphics Clock In: These pins receive a
differential 100 MHz serial reference clock from the external clock
synthesizer. This clock is used to generate the clocks necessary for the
support of PCI Express.
CMOS
DREFCLKN
DREFCLKP
RSTIN#
I
Display PLL Differential Clock In
CMOS
I
Reset In: When asserted, this signal will asynchronously reset the
(G)MCH logic. This signal is connected to the PLTRST# output of the
Intel® ICH6. All PCI Express Graphics Attach output signals will also tri-
state compatible with PCI Express* Specification Rev 1.0a.
HVIN
This input should have a Schmitt trigger to avoid spurious resets.
This signal is required to be 3.3 V tolerant.
PWROK
EXTTS#
I
HVIN
I
Power OK: When asserted, PWROK is an indication to the (G)MCH that
core power has been stable for at least 10 us.
External Thermal Sensor Input: This signal may connect to a precision
thermal sensor located on or near the DIMMs. If the system temperature
reaches a dangerously high value, then this signal can be used to trigger
the start of system thermal management. This signal is activated when
an increase in temperature causes a voltage to cross some threshold in
the sensor.
HVCMOS
MTYPE
I
Memory Type Select Strap. This signal is a strapping option that
indicates the type of system memory. For the 82910GL GMCH, this
signal must be tied to ground.
CMOS
0 = DDR2
1 = DDR
ICH_SYNC#
O
ICH Sync: This signal is connected to the MCH_SYNCH# signal on the
ICH6.
HVCMOS
2.8
Direct Media Interface (DMI)
Signal Name
Type
Description
DMI_RXP[3:0]
DMI_RXN[3:0]
I/O
DMI
Direct Media Interface: These signals are the receive differential
pair (Rx).
DMI_TXP[3:0]
DMI_TXN[3:0]
O
DMI
Direct Media Interface: These signals are the transmit differential
pair (Tx).
Datasheet
43
Signal Description
R
2.9
Intel® Serial DVO (SDVO) Interface
(82915G/82915GV/82915GL/82910GL GMCH Only)
For the 82915G/82915GV/82915GL/82910GL GMCH, all but two of the pins in this section are
multiplexed with the lower 8 lanes of the PCI Express interface.
Note: The SDVO interface does not support static lane reversal (e.g., SDVOB_CLK# will originate
from the same ball whether the PCI Express interface is lane-reversed mode or not.
Signal Name
Type
Description
SDVOB_GREEN-
O
Serial Digital Video Channel B Green Complement. This signal is
PCIE
multiplexed with EXP_TXN1.
SDVOB_GREEN+
SDVOB_BLUE-
SDVOB_BLUE+
O
PCIE
Serial Digital Video Channel B Green. This signal is multiplexed
with EXP_TXP1.
O
PCIE
Serial Digital Video Channel B Blue Complement. This signal is
multiplexed with EXP_TXN2.
O
Serial Digital Video Channel B Blue. This signal is multiplexed with
PCIE
EXP_TXP2.
SDVOC_RED- /
SDVOB_ALPHA-
O
PCIE
Serial Digital Video Channel C Red Complement Channel B
Alpha Complement. This signal is multiplexed with EXP_TXN4.
SDVOC_RED+ /
SDVOB_ALPHA+
O
PCIE
Serial Digital Video Channel C Red Channel B Alpha. This signal
is multiplexed with EXP_TXP4.
SDVOC_GREEN-
SDVOC_GREEN+
SDVOC_BLUE-
SDVOC_BLUE+
SDVOC_CLK-
O
PCIE
Serial Digital Video Channel C Green Complement. This signal is
multiplexed with EXP_TXN5.
O
PCIE
Serial Digital Video Channel C Green. This signal is multiplexed
with EXP_TXP5.
O
PCIE
Serial Digital Video Channel C Blue Complement. This signal is
multiplexed with EXP_TXN6.
O
PCIE
Serial Digital Video Channel C Blue. This signal is multiplexed with
EXP_TXP6.
O
Serial Digital Video Channel C Clock Complement. This signal is
PCIE
multiplexed with EXP_TXN7.
SDVOC_CLK+
SDVO_TVCLKIN-
SDVO_TVCLKIN+
SDVOB_INT-
O
PCIE
Serial Digital Video Channel C Clock. This signal is multiplexed
with EXP_TXP7.
I
Serial Digital Video TVOUT Synchronization Clock Complement.
This signal is multiplexed with EXP_RXN0.
PCIE
I
Serial Digital Video TVOUT Synchronization Clock. This signal is
multiplexed with EXP_RXP0.
PCIE
I
Serial Digital Video Input Interrupt Complement. This signal is
PCIE
multiplexed with EXP_RXN1.
SDVOB_INT+
I
Serial Digital Video Input Interrupt. This signal is multiplexed with
PCIE
EXP_RXP1.
SDVOC_INT+
I
Serial Digital Video Input Interrupt. This signal is multiplexed with
PCIE
EXP_RXP5.
SDVOC_INT-
I
Serial Digital Video Input Interrupt Complement. This signal is
PCIE
multiplexed with EXP_RXN5.
44
Datasheet
Signal Description
R
Signal Name
Type
Description
SDVO_STALL-
I
Serial Digital Video Field Stall Complement. This signal is
PCIE
multiplexed with EXP_RXN2.
SDVO_STALL+
I
Serial Digital Video Field Stall.. This signal is multiplexed with
PCIE
EXP_RXP2.
SDVO_CTRLCLK
SDVO_CTRLDATA
I/O
COD
Serial Digital Video Device Control Clock.
I/O
Serial Digital Video Device Control Data.
COD
This signal also provides a strapping option. Device 1 (Host-PCI
Express Bridge) is disabled on Reset when the SDVO Presence
strap (SDVO_CTLRDATA) is sampled high, and is enabled when
this signal is sampled low.
2.10
Power and Ground
Name
Voltage
Description
VCC
VTT
1.5 V
1.2 V
Core Power.
Processor System Bus Power.
PCI Express* and DMI Power.
System Memory Power.
VCC_EXP
VCCSM
1.5 V
1.8 V / 2.6 V
DDR2: VCCSM = 1.8 V
DDR: VCCSM = 2.6 V
VCC2
2.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
2.5 V
2.5 V CMOS Power.
VCCA_EXPPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_SMPLL
VCCA_DAC
PCI Express PLL Analog Power.
Display PLL A Analog Power.
Display PLL B Analog Power.
Host PLL Analog Power.
System Memory PLL Analog Power.
Display DAC Analog Power. This signal is on the
82915G/82915GV/82915GL/82910GL GMCH only.
VSS
0 V
0 V
Ground.
VSSA_DAC
Ground. This signal is on the 82915G/82915GV/82915GL/82910GL
GMCH only.
Datasheet
45
Signal Description
R
2.11
Reset States and Pull-up/Pull-downs
This section describes the expected states of the (G)MCH I/O buffers during and immediately
after the assertion of RSTIN#. This table only refers to the contributions on the interface from the
(G)MCH and does not reflect any external influence (such as external pull-up/pull-down resistors
or external drivers).
Legend:
CMCT:
Common Mode Center Tapped. Differential signals are weakly driven to the common
mode central voltage.
DRIVE: Strong drive (to normal value supplied by core logic if not otherwise stated)
TERM:
LV:
Normal termination devices are turned on
Low voltage
HV:
IN:
High voltage
Input buffer enabled
ISO:
TRI:
PU:
Isolate input buffer so that it doesn’t oscillate if input left floating
Tri-state
Weak internal pull-up
Weak internal pull-down
PD:
STRAP: Strap input sampled during assertion or on the de-asserting edge of RSTIN#
Table 2-1. Host Interface Reset and S3 States
State During
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
Assertion
Host I/F
HCPURST#
O
DRIVE LV
TERM HV after
TRI (No VTT)
approximately 1ms
HADSTB[1:0]#
HA[31:3]#
HD[63:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
HDSTBP[3:0]#
HDSTBN[3:0]#
HDINV[3:0]#
HADS#
HBNR#
HBPRI#
HDBSY#
I/O
O
HDEFER#
HDRDY#
I/O
O
HEDRDY#
46
Datasheet
Signal Description
R
State During
RSTIN#
Assertion
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Interface
Signal Name
I/O
Host I/F
HHIT#
I/O
I/O
I/O
I/O
O
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
IN
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
TERM HV
IN
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI (No VTT)
TRI
HHITM#
HLOCK#
HREQ[4:0]#
HTRDY#
HRS[2:0]#
HBREQ0#
HPCREQ#
HVREF
O
I/O
I
I
HRCOMP
I/O
TRI
TRI after RCOMP
TRI
20 Ω resistor
for board with
target
impedance of
60 Ω
HSWING
HSCOMP
I
IN
IN
I/O
TRI
TRI
TRI
Table 2-2. System Memory (DDR2) Reset and S3 States
State During
RSTIN#
Assertion
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Interface
Signal Name
I/O
System
Memory
(DDR2)
Channel A
SCLK_A[5:0]
SCLK_A[5:0]#
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
SRAS_A#
O
O
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
O
O
O
O
SCAS_A#
O
SWE_A#
O
SDQ_A[63:0]
SDM_A[7:0]
SDQS_A[7:0]
SDQS_A[7:0]#
SCKE_A[3:0]
SODT_A[3:0]
I/O
O
I/O
I/O
O
O
LV
LV
LV
Datasheet
47
Signal Description
R
State During
RSTIN#
Assertion
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Interface
Signal Name
I/O
System
Memory
(DDR2)
Channel B
SCLK_B[5:0]
SCLK_B[5:0]#
SCS_B[3:0]#
SMA_B[13]
O
O
O
O
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
O
LV
LV
LV
SMA_B[12:11]
SMA_B[10:8]
SMA_B[7]
O
O
TRI
LV
TRI
LV
TRI
LV
O
TRI
TRI
TRI
SMA_B[6:0]
SBS_B[2]
O
O
LV
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
LV
LV
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
LV
SBS_B[1:0]
TRI
SRAS_B#
O
TRI
SCAS_B#
O
TRI
SWE_B#
O
TRI
SDQ_B[63:0]
SDM_B[7:0]
SDQS_B[7:0]
SDQS_B[7:0]#
SCKE_B[3:0]
SODT_B[3:0]
SRCOMP0
I/O
O
TRI
TRI
I/O
I/O
O
TRI
TRI
LV
O
LV
LV
LV
I/O
I/O
I
TRI
TRI
IN
TRI (after RCOMP)
TRI
TRI
IN
SRCOMP1
TRI (after RCOMP)
SM_SLEWIN[1:0]
SM_SLEWOU{1:0]
SMVREF[1:0]
SOCOMP[1:0]
IN
O
TRI
IN
TRI (after RCOMP)
TRI
IN
I
IN
I/O
TRI
TRI
TRI
DDR2: 40 Ω
resistor to
ground
48
Datasheet
Signal Description
R
Table 2-3. System Memory (DDR) Reset and S3 States
State During
State After RSTIN#
De-assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
S3
Assertion
System
Memory
(DDR)
Channel A
SCLK_A[5:0]
SCLK_A[5:0]#
SMA_A[13:9]
SMA_A[8]
O
O
TRI
TRI
TRI
LV
TRI
TRI
TRI
LV
TRI
TRI
TRI
LV
O
O
SMA_A[7:6]
SMA_A[5]
O
TRI
LV
TRI
LV
TRI
LV
O
SMA_A[4:0]
SBS_A[2:0]
SCS_A[3]#
SCS_A[2:1]#
SCS_A[0]#
SRAS_A#
O
TRI
TRI
TRI
LV
TRI
TRI
TRI
LV
TRI
TRI
TRI
LV
O
O
O
O
TRI
TRI
LV
TRI
TRI
LV
TRI
TRI
LV
O
SCAS_A#
O
SWE_A#
O
TRI
TRI
TRI
TRI
TRI
LV
TRI
TRI
TRI
TRI
TRI
LV
TRI
TRI
TRI
TRI
TRI
LV
SDQ_A[63:0]
SDM_A[7:0]
SDQS_A[7:0]
SDQS_A[7:0]#
SCKE_A[3:0]
Channel B
SCLK_B[5:0]
SCLK_B[5:0]#
SMA_B[13:0]
SMA_B[0]
I/O
O
I/O
I/O
O
System
Memory
(DDR)
O
O
O
O
O
O
O
O
O
O
O
TRI
TRI
TRI
LV
TRI
TRI
TRI
LV
TRI
TRI
TRI
LV
SBS_B[2]
TRI
LV
TRI
LV
TRI
LV
SBS_B[1]
SBS_B[0]
TRI
LV
TRI
LV
TRI
LV
SCS_B[3]#
SCS_B[2:0]#
SRAS_B#
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
SCAS_B#
Datasheet
49
Signal Description
R
State During
RSTIN#
Assertion
State After RSTIN#
De-assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
S3
System
Memory
(DDR)
SWE_B#
SDQ_B[63:0]
O
I/O
O
TRI
TRI
TRI
TRI
TRI
LV
TRI
TRI
TRI
TRI
TRI
TRI
LV
TRI
SDM_B[7:0]
TRI
SDQS_B[7:0]
SDQS_B[7:0]#
SCKE_B[3:0]
SRCOMP0
I/O
I/O
O
TRI
TRI
LV
I/O
I/O
I
TRI
TRI
IN
TRI (after RCOMP)
TRI
TRI
IN
SRCOMP1
TRI (after RCOMP)
SM_SLEWIN[1:0]
SM_SLEWOU[1:0]
SMVREF[1:0]
SOCOMP[1:0]
IN
O
TRI
IN
TRI (after RCOMP)
TRI
IN
I
IN
I/O
TRI
TRI
TRI
DDR2: 40 Ω
resistor to
ground
Table 2-4. PCI Express* Graphics x16 Port Reset and S3 States
State During
S3
State After RSTIN#
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
De-assertion
Assertion
PCI
Express*-
Graphics
EXP_RXN[15:0]
EXP_RXP[15:0]
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_COMPO
EXP_COMPI
I/O
I/O
O
O
I
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
TRI
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
TRI
CMCT 1.0 V
TRI (after RCOMP)
TRI (after RCOMP)
I
TRI
TRI
Table 2-5. DMI Reset and S3 States
State During
RSTIN#
Assertion
S3
State After RSTIN#
De-assertion
Pull-up/ Pull-
down
Interface
Signal Name
I/O
DMI
DMI_RXN[3:0]
DMI_RXP[3:0]
DMI_TXN[3:0]
DMI_TXP[3:0]
I/O
I/O
O
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
O
50
Datasheet
Signal Description
R
Table 2-6. Clocking Reset and S3 States
State During
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
Assertion
HCLKN
I
I
I
I
I
I
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Clocks
HCLKP
GCLKN
GCLKP
DREFCLKN
DREFCLKP
Table 2-7. MISC Reset and S3 States
State During
RSTIN#
Assertion
S3
State After RSTIN#
De-assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
I
I
IN
HV
IN
HV
IN
HV
Misc.
PWROK
EXTTS#
I
PU
PU
PU
BSEL[2:0]
I
TRI
TRI
TRI
MTYPE
I
TERM HV
TERM HV
PU
TERM HV
TERM HV
PU
TERM HV
TERM HV
PU
EXP_SLR
I
ICH_SYNC#
SDVO_CTRLCLK
SDVO_CTRLDATA
O
O
I/O
TRI
TRI
TRI
TERM PD
TRI
TERM PD
Table 2-8. DAC Reset and S3 States (Intel® 82915G/82915GV/82915GL/82910GL GMCH only)
State During
RSTIN#
Assertion
S3
State After RSTIN#
Deassertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
HSYNC
O
O
O
O
O
O
O
O
O
LV
LV
LV
LV
DAC
VSYNC
RED
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
RED#
TRI
GREEN
GREEN#
BLUE
TRI
TRI
TRI
BLUE#
REFSET
TRI
0.5* VCCA_DAC
255 Ω 1%
Resistor to
Ground
DDC_CLK
I/O
I/O
IN
IN
IN
IN
IN
IN
DDC_DATA
§
Datasheet
51
Signal Description
R
52
Datasheet
Register Description
R
3 Register Description
The (G)MCH contains two sets of software accessible registers, accessed via the processor I/O
address space: Control registers and internal configuration registers.
• Control registers are I/O mapped into the processor I/O space that control access to PCI and
PCI Express configuration space (see Section 3.4).
• Internal configuration registers residing within the (G)MCH are partitioned into three logical
device register sets (“logical” since they reside within a single physical device). The first
register set is dedicated to Host Bridge functionality (i.e. DRAM configuration, other chipset
operating parameters and optional features). The second register block is dedicated to the
82915G/82915P/82915PL (G)MCH Host-PCI Express Bridge functions (controls PCI
Express interface configurations and operating parameters). The third register block is for the
82915G/82915GV/82915GL/82910GL GMCH internal graphics functions.
The (G)MCH internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the processor. The registers that reside within the lower
256 bytes of each device can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities,
with the exception of CONFIG_ADDRESS that can only be accessed as a DWord. All multi-byte
numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts
of the field). Registers that reside in bytes 256 through 4095 of each device may only be accessed
using memory mapped transactions in DWord (32-bit) quantities.
3.1
Register Terminology
The following table shows the register-related terminology that is used.
Item
Description
RO
Read Only bit(s). Writes to these bits have no effect.
RS/WC
Read Set / Write Clear bit(s). These bits are set to ‘1’ when read and then will continue
to remain set until written. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a
write of ‘0’ has no effect.
R/W
Read / Write bit(s). These bits can be read and written.
R/WC
Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A
write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect.
R/WC/S
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this
bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no
effect. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset
(for PCI Express* related bits a cold reset is “Power Good Reset” as defined in the PCI
Express* Specification).
R/W/L
R/W/S
Read / Write / Lockable bit(s). These bits can be read and written. Additionally there is a
bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field
from being writeable (bit field becomes Read Only).
Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a
cold reset is “Power Good Reset” as defined in the PCI Express* Specification).
Datasheet
53
Register Description
R
Item
R/WSC
Description
Read / Write Self Clear bit(s). These bits can be read and written. When the bit is ‘1’,
hardware may clear the bit to ‘0’ based upon internal events, possibly sooner than any
subsequent read could retrieve a ‘1’.
R/WSC/L
Read / Write Self Clear / Lockable bit(s). These bits can be read and written. When the
bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly sooner
than any subsequent read could retrieve a ‘1’. Additionally there is a bit (which may or
may not be a bit marked R/W/L) that, when set, prohibits this bit field from being
writeable (bit field becomes Read Only).
R/WC
Read Write Clear bit(s). These bits can be read and written. However, a write of ‘1’
clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect.
R/WO
Write Once bit(s). Once written, bits with this attribute become Read Only. These bits
can only be cleared by a Reset.
W
Write Only. Whose bits may be written, but will always-return zeros when read. They are
used for write side effects. Any data written to these registers cannot be retrieved.
Reserved Bits
Some of the (G)MCH registers described in this section contain reserved bits. These
bits are labeled "Reserved”. Software must deal correctly with fields that are reserved.
On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and then
written back. Note the software does not need to perform read, merge, and write
operation for the configuration address register.
Reserved
Registers
In addition to reserved bits within a register, the (G)MCH contains address locations in
the configuration space of the Host Bridge entity that are marked either "Reserved" or
“Intel Reserved”. The (G)MCH responds to accesses to “Reserved” address locations
by completing the host cycle. When a “Reserved” register location is read, a zero value
is returned. (“Reserved” registers can be 8-, 16-, or 32-bits in size). Writes to
“Reserved” registers have no effect on the (G)MCH. Registers that are marked as “Intel
Reserved” must not be modified by system software. Writes to “Intel Reserved”
registers may cause system failure. Reads from “Intel Reserved” registers may return a
non-zero value.
Default Value
Upon a Full Reset, the (G)MCH sets its entire set of internal configuration registers to
predetermined default states. Some register values at reset are determined by external
strapping options. The default state represents the minimum functionality feature set
required to successfully bringing up the system. Hence, it does not represent the
optimal system configuration. It is the responsibility of the system initialization software
(usually BIOS) to properly determine the DRAM configurations, operating parameters
and optional system features that are applicable, and to program the (G)MCH registers
accordingly.
54
Datasheet
Register Description
R
3.2
Platform Configuration
In platforms that support DMI (e.g. this (G)MCH) the configuration structure is significantly
different from previous Hub architectures. The DMI physically connects the (G)MCH and the
Intel ICH6; so, from a configuration standpoint, the DMI is logically PCI bus 0. As a result, all
devices internal to the (G)MCH and the Intel ICH6 appear to be on PCI bus 0.
The ICH6 internal LAN controller does not appear on bus 0; it appears on the external PCI bus
(whose number is configurable).
The system’s primary PCI expansion bus is physically attached to the Intel ICH6 and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and
therefore has a programmable PCI Bus number. The PCI Express Graphics Attach appears to
system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI
bus 0.
Note: A physical PCI bus 0 does not exist and that DMI and the internal devices in the (G)MCH and
Intel ICH6 logically constitute PCI Bus 0 to configuration software. This is shown in Figure 3-1.
Figure 3-1. Conceptual Chipset PCI Configuration Diagram
Processor
Intel ® 82915G/ 82915GV/ 82915GL/
82915P/82915PL/82919GL (G)MCH
PCI Configuration in I/O
DRAM Interface Bus 0,
Device 0
Device 1 (82915G/82915P/
82915PL GMCH only
Internal Graphics Bus 0,
(82915G/82915GV/82915G
L82910GL
Device
DMI
PCI_Config_Dia
Datasheet
55
Register Description
R
The (G)MCH contains the following PCI devices within a single physical component. The
configuration registers for the devices are mapped as devices residing on PCI bus 0.
• Device 0 – Host Bridge/DRAM Controller: Logically this appears as a PCI device residing
on PCI bus 0. Device 0 contains the standard PCI header registers, PCI Express base address
register, DRAM control (including thermal/throttling control), and configuration for the DMI
and other (G)MCH specific registers.
• Device 1– Host-PCI Express Bridge (82915G/82915P/82915PL (G)MCH only). Logically
this appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI
Express* Specification Revision 1.0a. Device 1 contains the standard PCI-to-PCI bridge
registers and the standard PCI Express/PCI configuration registers (including the PCI
Express memory address mapping). It also contains Isochronous and Virtual Channel
controls in the PCI Express extended configuration space.
• Device 2 – Internal Graphics Control (82915G/82915GV/82915GL/82910GL GMCH
only). Logically, this appears as a PCI device residing on PCI bus 0. Physically, device 2
contains the configuration registers for 3D, 2D, and display functions.
56
Datasheet
Register Description
R
Figure 3-2. Register Organization (Representative of the Intel® 82915G GMCH)
PCI Express* Egress Port
(RCRB)
FFFh
Device 2 Configuration
Registers: Internal Graphics
VC1 (Isochronous) Port
Arbitration Controls
FFFh
0FFh
Unused
000h
DMI Root Complex Register
Block (RCRB)
FFFh
Mirror of bits needed by
graphics driver graphics
thermal controls
(G)MCH-ICH6 Serial Interface
(DMI) Controls:
Analog Controls Error
Reporting Controls VC Control
(Incl. VCp)
000h
FFFh
Device 1 Configuration
Registers: PCI Express X16
000h
PCI Express x16 Controls:
Analog Controls
Error Reporting Controls
VC Controls
PCI Express Address Range
0FFF FFFFh
Accessed only by PCI
Express enhanced access
mechanism. 4KB block
allocated for each potential
device in root hierarchy.
Hot Plug/Slot Controls
0FFh
Device Level Controls
000h
FFFh
Device 2 Range
Device 1 Range
Device 0 Range
Device 0 Configuration
Registers
0000 0000h
3FFFh
Device 0 MMIO Registers:
(G)MCH Control
Thermal Sensor PSB Analog
Controls (Rcomp+)
0FFh
000h
CH 0/1 Analog Controls
CH 0/1 Timing Controls
Ch 0/1 Throttling
Ch 0/1 Oranization Arviter
Controls
Device Level Controls, PAM
EPBAR
DMI BAR
PCIEXBAR
0000h
MCHBAR
Reg_Org_82915G
Note: Diagram not to scale
NOTES:
1. Very high level representation. Many details omitted.
2. Inter graphics memory mapped registers are not shown.
3. Only Device 1 use PCI Express extended configuration space.
4. Device 0 and Device 2 use only standard PCI configuration space.
5. Hex numbers represent address range size and not actual locations.
Table 3-1. Device Number Assignment for Internal (G)MCH Devices
(G)MCH Function
Device#
Host Bridge / DRAM Controller
Device 0
Device 1
Host-to-PCI Express* Bridge (virtual P2P) (Intel® 82915G/82915P/82915PL
(G)MCH only)
Internal Graphics Control (82915G/82915GV/82915GL/82910GL GMCH
only)
Device 2
Datasheet
57
Register Description
R
3.3
General Routing Configuration Accesses
The (G)MCH supports two PCI related interfaces: DMI and PCI Express. PCI and PCI Express
configuration cycles are selectively routed to one of these interfaces. The (G)MCH is responsible
for routing configuration cycles to the proper interface. Configuration cycles to the Intel ICH6
internal devices and Primary PCI (including downstream devices) are routed to the Intel ICH6 via
DMI. Configuration cycles to both the PCI Express Graphics PCI compatibility configuration
space and the PCI Express Graphics extended configuration space are routed to the PCI Express
Graphics port.
A detailed description of the mechanism for translating processor I/O bus cycles to configuration
cycles is described below.
3.3.1
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8
functions with each function containing up to 256 8-bit configuration registers. The PCI
specification defines two bus cycles to access the PCI configuration space: Configuration Read
and Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the (G)MCH.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O
address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though
0CFFh). To reference a configuration register a DW I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the
device, and a specific configuration register of the device function being accessed.
CONFIG_ADDRESS [31] must be 1 to enable a configuration cycle. CONFIG_DATA then
becomes a window into the four bytes of configuration space specified by the contents of
CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the (G)MCH
translating the CONFIG_ADDRESS into the appropriate configuration cycle.
The (G)MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal (G)MCH configuration registers,
DMI or PCI Express.
3.3.2
Logical PCI Bus 0 Configuration Mechanism
The (G)MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus 0 device. The Host-DMI Bridge entity within the
(G)MCH is hardwired as Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity within the
(G)MCH is hardwired as Device 1 on PCI Bus 0. The 82915G/82915GV/82915GL/82910GL
GMCH’s Device 2 contains the control registers for the Integrated Graphics Controller. The Intel
ICH6 decodes the Type 0 access and generates a configuration access to the selected internal
device.
58
Datasheet
Register Description
R
3.3.3
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and falls outside the range claimed
by the Host-PCI Express bridge (not between upper bound in device’s Subordinate Bus Number
register and lower bound in device’s Secondary Bus Number register), the (G)MCH would
generate a Type 1 DMI Configuration Cycle. This DMI configuration cycle will be sent over the
DMI.
If the cycle is forwarded to the Intel ICH6 via the DMI, the Intel ICH6 compares the non-zero
Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI-
to-PCI bridges to determine if the configuration cycle is meant for ICH6 PCI Express ports one of
the Intel ICH6’s devices, the DMI, or a downstream PCI bus.
Figure 3-3. DMI Type 0 Configuration Address Translation
Configuration Address
11
31
30
24 23
16 15
10
Function
8
7
2
1
0
Double
Word
Device
Number
Bus Number
1
Reserved
XX
DMI Type 0 Configuration Address Extension
OCF8h
OCFBh
OCFAh
OCF9h
11
31
30
24 23
16 15
10
Function
8
7
2
1
0
Double
Word
Device
Number
Bus Number
1
Reserved
00
DMI_Typ0_Config
Figure 3-4. DMI Type 1 Configuration Address Translation
Configuration Address
16 15
11
31
30
24 23
10
Function
8
7
2
1
0
Double
Word
Device
Number
Bus Number
1
Reserved
XX
DMI Type 1 Configuration Address Extension
OCFAh
OCF9h
OCF8h
OCFBh
11
0
31
30
24 23
16 15
10
Function
8
7
2 1
Double
Word
Device
Number
Bus Number
1
Reserved
00
DMI_Typ1_Config
Datasheet
59
Register Description
R
3.3.4
PCI Express* Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as compared to
256 bytes allowed by PCI Specification, Revision 2.3. PCI Express configuration space is divided
into a PCI 2.3 compatible region that consists of the first 256B of a logical device’s configuration
space and a PCI Express extended region that consists of the remaining configuration space.
The PCI compatible region can be accessed using either the mechanism defined in the previous
section or using the enhanced PCI Express configuration access mechanism described in this
section. The extended configuration registers may only be accessed using the enhanced PCI
Express configuration access mechanism. To maintain compatibility with PCI configuration
addressing mechanisms, system software must access the extended configuration space using
32-bit operations (32-bit aligned) only. These 32-bit operations include byte enables allowing
only appropriate bytes within the DWord to be accessed. Locked transactions to the PCI Express
memory mapped configuration address space are not supported. All changes made using either
access mechanism are equivalent. The enhanced PCI Express configuration access mechanism
uses a flat memory-mapped address space to access device configuration registers. This address
space is reported by the system firmware to the operating system. The PCIEXBAR register
defines the base address for the 256-MB block of addresses below top of addressable memory
(currently 4 GB) for the configuration space associated with all devices and functions that are
potentially a part of the PCI Express root complex hierarchy. The PCI Express Configuration
Transaction Header includes an additional 4 bits (Extended Register Address[3:0]) between the
Function Number and Register Address fields to provide indexing into the 4 KB of configuration
space allocated to each potential device. For PCI Compatible Configuration Requests, the
Extended Register Address field must be all zeros.
Figure 3-5. Memory Map to PCI Express* Device Configuration Space
0xFFFFFFFh
0xFFFFFh
0xFFFh
0xFFFFFh
Bus 255
Device 31
Function 7
PCI Express
Extended
Configuration
Space
0xFFFFh
0x7FFFh
0xFFFFh
0x7FFFh
0xFFh
0x3Fh
0x1FFFFFh
PCI
Compatible
Config Space
Bus 1
Bus 0
Function 1
Function 0
Device 1
Device 0
0xFFFFFh
0h
PCI
Compatible
Config Header
Located By PCI
Express Base
Address
MemMap_PCIExpress
Just the same as with PCI devices, each device is selected based on decoded address information
that is provided as a part of the address portion of Configuration Request packets. A PCI Express
device will decode all address information fields (bus, device, function, and extended address
numbers) to provide access to the correct register.
60
Datasheet
Register Description
R
To access this space (steps 1, 2, 3 are performed only once by BIOS)
1. Use the PCI compatible configuration mechanism to enable the PCI Express enhanced
configuration mechanism by writing 1 to bit 31 of the DEVEN register.
2. Use the PCI compatible configuration mechanism to write an appropriate PCI Express base
address into the PCIEXBAR register.
3. Calculate the host address of the register you wish to set using (PCI Express base + (bus
number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) + (1 B * offset
within the function) = host address).
4. Use a memory write or memory read cycle to the calculated host address to write to or read
from that register.
2
31
28 27
Base
20 19
15 14
12 11
8
7
1
0
Register
Number
Device
Function
Bus
Extended
X
X
Config_Write
PCI Express Configuration Writes
Internally the host interface unit translates writes to PCI Express extended configuration space to
configurations on the backbone. Writes to extended space are posted on the FSB, but non-posted
on the PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes).
See the PCI Express Specification for more information on both the PCI 2.3 compatible and PCI
Express enhanced configuration mechanism and transaction rules.
Datasheet
61
Register Description
R
3.3.5
Intel® 915x GMCH Configuration Cycle Flowchart
Figure 3-6. Intel® 915x GMCH Configuration Cycle Flowchart
DW I/O Write to
CONFIG_ADDRES
S with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Yes
Bus# = 0
No
GMCH Generates
Type 1 Access to
PCI Express
Bus# > Sec Bus
Bus# ≤ Sub Bus
in GMCH Dev 1
GMCH Claims if
Function# = 0
Yes
Yes
Device# = 0
No
No
Bus# =
Yes
Secondary Bus in
GMCH Dev 1
Yes
Yes
Yes
Device# = 1 &
Dev # 1 Enabled
GMCH Claims if
Function# = 0
No
No
GMCH Generates MISI
Type 1Configuration
Cycle
Device# = 2 &
Dev# 2
Enabled
GMCH Claims if
Function# = 0
No
GMCH Generates
Type 0 Accessto
PCI Express
Device# = 7&
Dev# 7 Enabled
Yes
Device# = 0
GMCH Claims if
Function# = 0
No
No
MCH allows cycle to
go to DMI resulting in
Master Abort
GMCH Generates DMI
Type 0 Configuration
Cycle
Config_Cyc_Flow_915
62
Datasheet
Register Description
R
3.4
I/O Mapped Registers
The (G)MCH contains two registers that reside in the processor I/O address space − the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible through the
Configuration Data window.
3.4.1
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Default Value:
Access:
0CF8h Accessed as a DWord
00000000h
R/W
Size:
32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or Word
reference will "pass through" the Configuration Address Register and DMI onto the Primary PCI
bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent configuration access is
intended.
Bit
Access
&
Default
Description
31
R/W
0b
Configuration Enable (CFGE):
1 = Enable
0 = Disable
30:24
23:16
Reserved
R/W
00h
Bus Number: If the Bus Number is programmed to 00h the target of the
Configuration Cycle is a PCI Bus #0 agent. If this is the case and the (G)MCH is
not the target (i.e., the device number is ≥ 3 and not equal to 7), then a DMI Type
0 Configuration Cycle is generated.
If the Bus Number is non-zero, and does not fall within the ranges enumerated by
device 1’s Secondary Bus Number or Subordinate Bus Number Register, then a
DMI Type 1 Configuration Cycle is generated.
If the Bus Number is non-zero and matches the value programmed into the
Secondary Bus Number Register of device 1, a Type 0 PCI configuration cycle will
be generated on PCI Express Graphics.
If the Bus Number is non-zero, greater than the value in the Secondary Bus
Number register of device 1 and less than or equal to the value programmed into
the Subordinate Bus Number Register of device 1 a Type 1 PCI configuration
cycle will be generated on PCI Express Graphics.
This field is mapped to byte 8 [7:0] of the request header format during PCI
Express Configuration cycles and A[23:16] during the DMI Type 1 configuration
cycles.
Datasheet
63
Register Description
R
Bit
Access
&
Default
Description
15:11
R/W
00h
Device Number: This field selects one agent on the PCI bus selected by the Bus
Number. When the Bus Number field is “00”, the (G)MCH decodes the Device
Number field. The (G)MCH is always Device Number 0 for the Host bridge entity,
Device Number 1 for the Host-PCI Express entity. Therefore, when the
Bus Number =0 and the Device Number equals 0, 1, or 2 the internal (G)MCH
devices are selected.
This field is mapped to byte 6 [7:3] of the request header format during PCI
Express Configuration cycles and A [15:11] during the DMI configuration cycles.
10:8
R/W
000b
Function Number: This field allows the configuration registers of a particular
function in a multi-function device to be accessed. The (G)MCH ignores
configuration cycles to its internal devices if the function number is not equal to 0
or 1.
This field is mapped to byte 6 [2:0] of the request header format during PCI
Express Configuration cycles and A[10:8] during the DMI configuration cycles.
7:2
1:0
R/W
00h
Register Number: This field selects one register within a particular Bus, Device,
and Function as specified by the other fields in the Configuration Address
Register.
This field is mapped to byte 7 [7:2] of the request header format during PCI
Express Configuration cycles and A[7:2] during the DMI Configuration cycles.
Reserved
3.4.2
CONFIG_DATA—Configuration Data Register
I/O Address:
Default Value:
Access:
0CFCh
00000000h
R/W
Size:
32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents of
CONFIG_ADDRESS.
Bit
Access &
Default
Description
31:0
R/W
0000 0000h
Configuration Data Window (CDW): If bit 31 of CONFIG_ADDRESS is 1, any
I/O access to the CONFIG_DATA register will produce a configuration
transaction using the contents of CONFIG_ADDRESS to determine the bus,
device, function, and offset of the register to be accessed.
§
64
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4 Host Bridge/DRAM Controller
Registers (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Warning: Address locations that are not listed are considered Reserved registers locations. Reads to
Reserved registers may return non-zero values. Writes to reserved locations may cause system
failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in
this component are not included in this document. The reserved/unimplemented space in the PCI
configuration header space is not documented as such in this summary.
Table 4-1. Device 0 Function 0 Register Address Map Summary
Address
Offset
Register
Symbol
Default
Value
Register Name
Vendor Identification
Access
00–01h
02–03h
04–05h
06–07h
VID
DID
8086h
2580h
0006h
0090h
RO
RO
Device Identification
PCI Command
PCI Status
PCICMD
PCISTS
RO, R/W
RO,
R/W/C
08h
RID
Revision Identification
See register
description
RO
09–0Bh
0Ch
CC
—
Class Code
060000h
—
RO
—
Reserved
0Dh
MLT
Master Latency Timer
Header Type
00h
RO
0Eh
HDR
—
00h
RO
0F–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
Reserved
—
—
SVID
SID
Subsystem Vendor Identification
Subsystem Identification
Reserved
0000h
0000h
—
R/W/O
R/W/O
—
—
CAPPTR
—
Capabilities Pointer
Reserved
EOh
RO
35–3Fh
40–43h
44–47h
—
—
EPBAR
MCHBAR
Egress Port Base Address
00000000h
00000000h
RO
GMCH Memory Mapped Register Range
Base Address
R/W
48–4Bh
4C–4Fh
PCIEXBAR
DMIBAR
PCI Express* Register Range Base Address
E0000000h
00000000h
R/W
R/W
Root Complex Register Range Base
Address
Datasheet
65
Host Bridge/DRAM Controller Registers (D0:F0)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
52–53h
GGC
GMCH Graphics Control Register (82915G
GMCH only)
0030h
R/W/L
54–57h
58–8Fh
90h
DEVEN
—
Device Enable
00000019h
—
R/W
—
Reserved
PAM0
PAM1
PAM2
PAM3
PAM4
PAM5
PAM6
LAC
Programmable Attribute Map 0
Programmable Attribute Map 1
Programmable Attribute Map 2
Programmable Attribute Map 3
Programmable Attribute Map 4
Programmable Attribute Map 5
Programmable Attribute Map 6
Legacy Access Control
00h
00h
00h
00h
00h
00h
00h
00h
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
91h
92h
93h
94h
95h
96h
97h
98–9Bh
9Ch
—
Reserved
TOLUD
SMRAM
Top of Low Usable DRAM
System Management RAM Control
08h
00h
R/W
9Dh
RO,
R/W/L
9Eh
ESMRAMC
Extended System Management RAM Control
00h
RO,
R/W/L
9F–C7h
C8–C9h
—
Reserved
—
—
ERRSTS
Error Status
0000h
RO,
R/W/L
CA–CBh
CC–DBh
DC–DFh
E0–E8h
ERRCMD
—
Error Command
Reserved
0000h
—
R/W
—
SKPD
CAPID0
Scratchpad Data
Capability Identifier
00000000h
R/W
RO
0000000000
01090009h
E9–FFh
100h
—
C0DRB0
C0DRB1
C0DRB2
C0DRB3
—
Reserved
—
00h
00h
00h
00h
—
—
Channel A DRAM Rank Boundary Address 0
Channel A DRAM Rank Boundary Address 1
Channel A DRAM Rank Boundary Address 2
Channel A DRAM Rank Boundary Address 3
Reserved
R/W
R/W
R/W
R/W
—
101h
102h
103h
104–107h
108h
C0DRA0
C0DRA2
—
Channel A DRAM Rank 0,1 Attribute
Channel A DRAM Rank 2,3 Attribute
Reserved
00h
00h
—
R/W
R/W
—
109h
10A–10Bh
10Ch
C0DCLKDIS
—
Channel A DRAM Clock Disable
Reserved
00h
—
R/W
—
10Dh
66
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
10E–10F
110–113h
114–117h
118–11Fh
120–123h
124–17Fh
180h
C0BNKARC
—
Channel A DRAM Bank Architecture
Reserved
0000h
R/W
—
—
900122h
—
C0DRT1
—
Channel A DRAM Timing Register
Reserved
R/W
—
C0DRC0
—
Channel A DRAM Controller Mode 0
Reserved
00000000h
—
R/W, RO
—
C1DRB0
C1DRB1
C1DRB2
C1DRB3
—
Channel B DRAM Rank Boundary Address 0
Channel B DRAM Rank Boundary Address 1
Channel B DRAM Rank Boundary Address 2
Channel B DRAM Rank Boundary Address 3
Reserved
00h
R/W
R/W
R/W
R/W
—
181h
00h
182h
00h
183h
00h
184–187h
188h
—
C1DRA0
C1DRA2
—
Channel B DRAM Rank 0,1 Attribute
Channel B DRAM Rank 2,3 Attribute
Reserved
00h
R/W
R/W
—
189h
00h
18A–18Bh
18Ch
—
C1DCLKDIS
—
Channel B DRAM Clock Disable
Reserved
00h
R/W
—
18Dh
—
18E–18Fh
190–193h
194h
C1BNKARC
—
Channel B Bank Architecture
Reserved
0000h
—
R/W
—
C1DRT1
—
Channel B DRAM Timing Register 1
Reserved
900122h
—
R/W, RO
—
195–19Fh
1A0–1A3h
1A4–F0Fh
F10–F13h
F14h
C1DRC0
—
Channel B DRAM Controller Mode 0
Reserved
00000000h
—
R/W, RO
—
PMCFG
PMSTS
Power Management Configuration
Power Management Status
00000000h
00000000h
R/W
R/W/C/S
Datasheet
67
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1
Host Bridge/DRAM Controller PCI Register Details
(D0:F0)
4.1.1
VID—Vendor Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
00h
8086h
RO
Size:
16 bits
This register combined with the Device Identification register uniquely identifies any PCI device.
Bit
Access &
Default
Description
15:0
RO
Vendor Identification Number (VID): PCI standard identification for Intel.
8086h
4.1.2
DID—Device Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
02h
2580h
RO
Size:
16 bits
This register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit
Access &
Default
Description
15:0
RO
Device Identification Number (DID): This field is an identifier assigned to
2580h
the (G)MCH core/primary PCI device.
68
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.3
PCICMD—PCI Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
04h
0006h
RO, R/W
16 bits
Size:
Since (G)MCH Device 0 does not physically reside on Primary PCI bus, many of the bits are not
implemented.
Bit
Access &
Default
Description
15:10
9
Reserved
RO
0b
Fast Back-to-Back Enable (FB2B). This bit controls whether or not the master
can do fast back-to-back write. Since device 0 is strictly a target this bit is not
implemented and is hardwired to 0.
8
R/W
0b
SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR
messaging. The (G)MCH does not have a SERR signal. The (G)MCH
communicates the SERR condition by sending an SERR message over DMI to
the ICH6.
1 = Enable. The (G)MCH is enabled to generate SERR messages over DMI for
specific Device 0 error conditions that are individually enabled in the
ERRCMD register. The error status is reported in the ERRSTS, and PCISTS
registers. If SERRE is clear, then the SERR message is not generated by the
(G)MCH for Device 0.
0 = Disable
Note: That this bit only controls SERR messaging for the Device 0. Device 1 has
its own SERRE bits to control error reporting for error conditions occurring in that
device. The control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
7
6
5
4
3
2
1
0
RO
0b
Address/Data Stepping Enable (ADSTEP). Hardwired to 0.
RO
0b
Parity Error Enable (PERRE). PERR# is not implemented by the (G)MCH and
this bit is hardwired to 0.
RO
0b
VGA Palette Snoop Enable (VGASNOOP). Hardwired to a 0.
RO
0b
Memory Write and Invalidate Enable (MWIE). The (G)MCH will never issue
memory write and invalidate commands. This bit is therefore hardwired to 0.
RO
0b
Reserved
RO
1b
Bus Master Enable (BME). The (G)MCH is always enabled as a master. This bit
is hardwired to a "1".
RO
1b
Memory Access Enable (MAE). The (G)MCH always allows access to main
memory. This bit is not implemented and is hardwired to 1.
RO
0b
I/O Access Enable (IOAE). Hardwired to a 0.
Datasheet
69
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.4
PCISTS—PCI Status (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
06h
0090h
RO, R/W/C
16 bits
Size:
This status register reports the occurrence of error events on Device 0’s PCI interface. Since the
(G)MCH Device 0 does not physically reside on Primary PCI, many of the bits are not
implemented.
Bit
15
14
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Hardwired to a 0.
R/W/C
0b
Signaled System Error (SSE): Software clears this bit by writing a 1 to it.
1 = The (G)MCH Device 0 generated an SERR message over DMI for any
enabled Device 0 error condition. Device 0 error conditions are enabled in the
PCICMD, and ERRCMD registers. Device 0 error flags are read/reset from
the PCISTS, or ERRSTS registers.
13
12
R/WC
0b
Received Master Abort Status (RMAS): Software clears this bit by writing a 1 to
it.
1 = (G)MCH generated a DMI request that receives an Unsupported Request
completion packet.
R/WC
0b
Received Target Abort Status (RTAS): Software clears this bit by writing a 1 to
it.
1 = (G)MCH generated a DMI request that receives a Completer Abort
completion packet.
11
RO
0b
Signaled Target Abort Status (STAS): The (G)MCH will not generate a Target
Abort DMI completion packet or Special Cycle. This bit is not implemented in the
(G)MCH and is hardwired to a 0.
10:9
RO
00b
DEVSEL Timing (DEVT): These bits are hardwired to "00". Device 0 does not
physically connect to Primary PCI. These bits are set to "00" (fast decode) so
that optimum DEVSEL timing for Primary PCI is not limited by the (G)MCH.
8
7
RO
0b
Master Data Parity Error Detected (DPD): PERR signaling and messaging are
not implemented by the (G)MCH; therefore, this bit is hardwired to 0.
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. Device 0 does not physically
connect to Primary PCI. This bit is set to 1 (indicating fast back-to-back
capability) so that the optimum setting for Primary PCI is not limited by the
(G)MCH.
6
5
Reserved
RO
0b
66 MHz Capable: Does not apply to PCI Express*. Hardwired to 0.
4
RO
1b
Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration
software that this device/function implements a list of new capabilities. A list of
new capabilities is accessed via register CAPPTR at configuration address offset
34h. Register CAPPTR contains an offset pointing to the start address within
configuration space of this device where the Capability standard register resides.
3:0
Reserved
70
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.5
RID—Revision Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
08h
See bit description
RO
Size:
8 bits
This register contains the revision number of the (G)MCH Device 0.
Bit
Access &
Default
Description
7:0
RO
00h
Revision Identification Number (RID): This field indicates the number of times
that this device in this component has been “stepped” through the manufacturing
process. Refer to the Intel® 82915G/82915P/82915GV/82910GL Express Chipset
Specification Update for the value of the Revision ID Register.
4.1.6
CC—Class Code (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
09h
060000h
RO
Size:
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a register-
specific programming interface.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC): This is an 8-bit value that indicates the base class
06h
code for the (G)MCH.
06h = Bridge device.
15:8
7:0
RO
00h
Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of
Bridge into which the (G)MCH falls.
00h = Host Bridge.
RO
00h
Programming Interface (PI): This is an 8-bit value that indicates the
programming interface of this device. This value does not specify a particular
register set layout and provides no practical use for this device.
Datasheet
71
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.7
MLT—Master Latency Timer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
0Dh
00h
RO
8 bits
Size:
Device 0 in the (G)MCH is not a PCI master. Therefore, this register is not implemented.
Bit
Access &
Default
Description
7:0
Reserved
4.1.8
HDR—Header Type (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
0Eh
00h
RO
8 bits
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Access &
Default
Description
7:0
RO
PCI Header (HDR): This field always returns 0 to indicate that the (G)MCH is a
00h
single function device with standard header layout.
4.1.9
SVID—Subsystem Vendor Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
2Ch
0000h
R/WO
16 bits
Size:
This value is used to identify the vendor of the subsystem.
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-
up to indicate the vendor of the system board. After it has been written once, it
becomes read only.
72
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.10
SID—Subsystem Identification (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
2Eh
0000h
R/W/O
16 bits
Size:
This value is used to identify a particular subsystem.
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem ID (SUBID): This field should be programmed during BIOS
initialization. After it has been written once, it becomes read only.
4.1.11
CAPPTR—Capabilities Pointer (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
34h
E0h
RO
8 bits
Size:
The CAPPTR provides the offset that is the pointer to the location of the first device capability in
the capability list.
Bit
Access &
Default
Description
7:0
RO
Pointer to the offset of the first capability ID register block: In this case the
E0h
first capability is the product-specific Capability Identifier (CAPID0).
Datasheet
73
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.12
EPBAR—Egress Port Base Address (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
40h
00000000h
RO
Size:
32 bits
This is the base address for the Egress Port MMIO configuration space. There is no physical
memory within this 4-KB window that can be addressed. The 4 KB reserved by this register does
not alias to any PCI 2.3 compliant memory-mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to EPBAREN[Dev 0, offset
54h, bit 27]
Bit
Access &
Default
Description
31:12
R/W
Egress Port MMIO Base Address: This field corresponds to bits 31 to 12 of the
00000h
base address Egress Port MMIO configuration space.
BIOS will program this register resulting in a base address for a 4-KB block of
contiguous memory address space. This register ensures that a naturally aligned
4-KB space is allocated within total addressable memory space of 4 GB.
System software uses this base address to program the (G)MCH MMIO register
set.
11:0
Reserved
74
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.13
MCHBAR—(G)MCH Memory Mapped Register Range Base
Address (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
44h
00000000h
R/W
Size:
32 bits
This is the base address for the (G)MCH memory-mapped configuration space. There is no
physical memory within this 16-KB window that can be addressed. The 16 KB reserved by this
register does not alias to any PCI 2.3 compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0,
offset 54h, bit 28]
Bit
Access &
Default
Description
31:14
R/W
(G)MCH Memory Mapped Base Address: This field corresponds to bits 31:14 of
00000h
the base address (G)MCH memory-mapped configuration space.
BIOS will program this register resulting in a base address for a 16-KB block of
contiguous memory address space. This register ensures that a naturally aligned
16-KB space is allocated within total addressable memory space of 4 GB.
System software uses this base address to program the (G)MCH Memory-
mapped register set.
13:0
Reserved
Datasheet
75
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.14
PCIEXBAR—PCI Express* Register Range Base Address
(D0:F0) (Intel® 82915G/82915P/82915PL Only)
PCI Device:
Address Offset:
Default Value:
Access:
0
48h
E0000000h
R/W
Size:
32 bits
This is the base address for the PCI Express configuration space. This window of addresses
contains the 4 KB of configuration space for each PCI Express device that can potentially be part
of the PCI Express hierarchy associated with the (G)MCH. There is not actual physical memory
within this 256-MB window that can be addressed. Each PCI Express hierarchies require a PCI
Express BASE register. The (G)MCH supports one PCI Express hierarchy.
The 256 MB reserved by this register does not alias to any PCI 2.3 compliant memory-mapped
space. For example, MCHBAR reserves a 16-KB space and reserves a 4-KB space both outside of
PCIEXBAR space. They cannot be overlaid on the space reserved by PCIEXBAR for devices 0.
On reset, this register is disabled and must be enabled by writing a 1 to PCIEXBAREN [Dev 0,
offset 54h, bit 31]
If the PCI Express Base Address [bits 31:28] were set to Fh, an overlap with the High BIOS area,
APIC ranges would result. Software must guarantee that these ranges do not overlap. The PCI
Express Base Address cannot be less than the maximum address written to the Top of physical
memory register (TOLUD). If a system is populated with more than 3.5 GB, either the PCI
Express Enhanced Access mechanism must be disabled or the value in TOLUD must be reduced
to report that only 3.5 GB are present in the system to allow a value of Eh for the PCI Express
Base Address (assuming that all PCI 2.3 compatible configuration space fits above 3.75 GB).
Bit
Access &
Default
Description
31:28
R/W
Eh
PCI Express* Base Address: This field corresponds to bits 31 to 28 of the
base address for PCI Express enhanced configuration space.
BIOS will program this register resulting in a base address for a 256-MB block
of contiguous memory address space. Having control of those particular 4 bits
insures that this base address will be on a 256-MB boundary, above the lowest
256 MB and still within total addressable memory space, currently 4 GB.
The address used to access the PCI Express configuration space for a specific
device can be determined as follows:
PCI Express Base Address + Bus Number * 1 MB + Device Number * 32 KB +
Function Number * 4 KB
The address used to access the PCI Express configuration space for Device 1
in this component would be PCI Express Base Address + 0 * 1 MB + 1 * 32 KB
+ 0 * 4 KB = PCI Express Base Address + 32 KB. Remember that this
address is the beginning of the 4-KB space that contains both the PCI
compatible configuration space and the PCI Express extended configuration
space.
27:0
Reserved
76
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.15
DMIBAR—Root Complex Register Range Base Address
(D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
4Ch
00000000h
R/W
Size:
32 bits
This is the base address for the Root Complex configuration space. This window of addresses
contains the Root Complex Register set for the PCI Express hierarchy associated with the
(G)MCH. There is no physical memory within this 4-KB window that can be addressed. The
4 KB that is reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space.
On reset, this register is disabled and must be enabled by writing a 1 to the DMIBAREN [Dev 0,
offset 54h, bit 29].
|
Bit
Access &
Default
Description
31:12
R/W
DMI Base Address: This field corresponds to bits 31 to 12 of the base address
0000 0h
DMI configuration space.
BIOS will program this register resulting in a base address for a 4-KB block of
contiguous memory address space. This register ensures that a naturally
aligned 4-KB space is allocated within total addressable memory space of
4 GB.
System software uses this base address to program the DMI register set.
Reserved
11:0
Datasheet
77
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.16
GGC—GMCH Graphics Control Register (D0:F0)
(82915G/82915GV/82915GL/82910GL GMCH only)
PCI Device:
Address Offset:
Default Value:
Access:
0
52h
0030h
R/W/L
16 bits
Size:
Bit
Access &
Default
Descriptions
15:7
6:4
Reserved
R/W/L
011b
Graphics Mode Select (GMS): This field is used to select the amount of main
memory that is pre-allocated to support the Internal Graphics device in VGA
(non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-
allocated only when Internal graphics is enabled. Device 2 (IGD) does not claim
VGA cycles (memory and I/O), and the Sub-Class Code field within Device 2,
Function 0 Class Code register is 80h.
000 = No memory pre-allocated
001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer.
010 = Reserved.
011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer.
100–111 = Reserved.
NOTES:
1. This register is locked and becomes Read Only when the D_LCK bit in the
SMRAM register is set.
2. If IGD is disabled, this field should be set to 000.
3:2
1
Reserved
R/W
0b
IGD VGA Disable (IVD):
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the Sub-Class
Code within Device 2 Class Code register is 00h.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and
the Sub-Class Code field within Device 2, Function 0 Class Code register is
80h.
0
Reserved
78
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.17
DEVEN—Device Enable (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
54h
00000019h
R/W
Size:
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within the
(G)MCH.
Bit
Access &
Default
Description
31
R/W
0b
82915G/82915P/82915PL (G)MCH:
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and write transactions
proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:28 are
R/W with no functionality behind them.
1 = The PCIEXBAR register is enabled. Memory read and write transactions
whose address bits 31:28 match PCIEXBAR 31:28 will be translated to
configuration reads and writes within the (G)MCH. These translated cycles
are routed as shown in the table above.
82915GV/82915GL/82910GL GMCH:
Reserved.
30
29
Reserved
R/W
0b
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory.
1 = DMIBAR memory mapped accesses are claimed and decoded appropriately.
MCHBAR Enable (MCHBAREN):
28
R/W
0b
0 = MCHBAR is disabled and does not claim any memory.
1 = MCHBAR memory mapped accesses are claimed and decoded
appropriately.
27
R/W
0b
EPBAR Enable (EPBAREN):
0 = EPBAR is disabled and does not claim any memory.
1 = EPBAR memory mapped accesses are claimed and decoded appropriately.
Reserved
26:5
Datasheet
79
Host Bridge/DRAM Controller Registers (D0:F0)
R
Bit
Access &
Default
Description
4
R/W
1b
82915G/82915GV/82915GL/82910GL GMCH:
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0 Device 2 Function 1 is disabled and hidden
1 = Bus 0 Device 2 Function 1 is enabled and visible
Note: Setting this bit to enabled when bit 3 is 0 has no meaning.
82915P/82915PL MCH:
Reserved.
3
R/W
1b
82915G/82915GV/82915GL/82910GL GMCH:
Internal Graphics Engine Function 0 (D2F0EN):
0 = Bus 0 Device 2 Function 0 is disabled and hidden
1 = Bus 0 Device 2 Function 0 is enabled and visible
82915P/82915PL MCH:
Reserved.
2
1
Reserved
R/W
1b
82915G/82915P/82915PL (G)MCH:
PCI Express* Port (D1EN):
Strap
dependent
0 = Bus 0 Device 1 Function 0 is disabled and hidden. This also gates PCI
Express internal clock (lgclk) and asserts PCI Express internal reset (lgrstb).
1 = Bus 0 Device 1 Function 0 is enabled and visible.
The SDVO Presence hardware strap determines default value. Device 1 is
disabled on Reset when the SDVO Presence strap (SDVO_CTLRDATA signal) is
sampled high, and is enabled otherwise.
82915GV/82915GL/82910GL GMCH:
Reserved.
0
RO
1b
Host Bridge: Bus 0 Device 0 Function 0 can not be disabled and is therefore
hardwired to 1.
80
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.18
PAM0—Programmable Attribute Map 0 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
90h
00h
R/W
Size:
8 bits
This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h–
0FFFFFh
The (G)MCH allows programmable memory attributes on 13 Legacy memory segments of
various sizes in the 768-KB to 1-MB address range. Seven Programmable Attribute Map (PAM)
Registers are used to support these features. Cache ability of these areas is controlled via the
MTRR registers in the processor. Two bits are used to specify memory attributes for each
memory segment. These bits apply to both host accesses and PCI initiator accesses to the PAM
areas. These attributes are:
• RE (Read Enable). When RE = 1, the processor read accesses to the corresponding memory
segment are claimed by the (G)MCH and directed to main memory. Conversely, when
RE = 0, the host read accesses are directed to Primary PCI.
• WE (Write Enable). When WE = 1, the host write accesses to the corresponding memory
segment are claimed by the (G)MCH and directed to main memory. Conversely, when
WE = 0, the host write accesses are directed to Primary PCI.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write,
or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read
Only.
Each PAM Register controls two regions, typically 16 KB in size.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0F0000-0FFFFF Attribute (HIENABLE): This field controls the steering of read and
write cycles that addresses the BIOS area from 0F0000h to 0FFFFFh.
00 = DRAM Disabled: All accesses are directed to the DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to the DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:0
Reserved
Warning: The (G)MCH may hang if a PCI Express graphics attach or DMI originated access to Read
Disabled or Write Disabled PAM segments occurs (due to a possible IWB to non-DRAM). For
these reasons the following critical restriction is placed on the programming of the PAM regions:
At the time that a DMI or PCI Express graphics attach accesses to the PAM region may occur, the
targeted PAM segment must be programmed to be both readable and writeable.
Datasheet
81
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.19
PAM1—Programmable Attribute Map 1 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
91h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h–
0C7FFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0C4000-0C7FFF Attribute (HIENABLE): This field controls the steering of read and
write cycles that address the BIOS area from 0C4000h to 0C7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0C0000-0C3FFF Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0C0000h to 0C3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
82
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.20
PAM2—Programmable Attribute Map 2 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
92h
00h
R/W
Size:
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h–
0CFFFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0CC000h–0CFFFFh Attribute (HIENABLE):
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0C8000h–0CBFFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0C8000h to 0CBFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Datasheet
83
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.21
PAM3—Programmable Attribute Map 3 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
93h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h–
0D7FFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0D0000h–0D3FFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
84
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.22
PAM4—Programmable Attribute Map 4 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
94h
00h
R/W
Size:
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h-
0DFFFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0DC000h to 0DFFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0D8000h to 0DBFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Datasheet
85
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.23
PAM5—Programmable Attribute Map 5 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
95h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h-
0E7FFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0E4000h–0E7FFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0E0000h–0E3FFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
86
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.24
PAM6—Programmable Attribute Map 6 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
96h
00h
R/W
Size:
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h–
0EFFFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Datasheet
87
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.25
LAC—Legacy Access Control (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
97h
00h
R/W
8 bits
Size:
This 8-bit register controls a fixed DRAM hole from 15–16 MB.
Bit
Access &
Default
Description
7
R/W
0b
Hole Enable (HEN): This field enables a memory hole in DRAM space. The DRAM
that lies "behind" this space is not remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
Reserved
6:1
0
R/W
0b
MDA Present (MDAP): This bit works with the VGA Enable bits in the BCTRL
register of Device 1 to control the routing of processor initiated transactions targeting
MDA compatible I/O and memory address ranges. This bit should not be set if
device 1's VGA Enable bit is not set.
If device 1's VGA enable bit is not set, then accesses to I/O address range x3BCh–
x3BFh are forwarded to the DMI.
If the VGA enable bit is set and MDA is not present, then accesses to I/O address
range x3BCh–x3BFh are forwarded to PCI Express* if the address is within the
corresponding IOBASE and IOLIMIT, otherwise they are forwarded to the DMI.
MDA resources are defined as the following:
Memory:
I/O:
0B0000h – 0B7FFFh
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(Including ISA address aliases, A [15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be
forwarded to the DMI even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN
MDAP
Description
0
0
All References to MDA and VGA space are routed to
the DMI
0
1
1
0
Illegal combination
All VGA and MDA references are routed to PCI
Express Graphics Attach.
1
1
All VGA references are routed to PCI Express
Graphics Attach. MDA references are routed to the
DMI
88
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.26
TOLUD—Top of Low Usable DRAM (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
9Ch
08h
R/W
Size:
8 bits
This 8-bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen Memory
(82915G only) are within the DRAM space defined. From the top, the (G)MCH optionally claims
1 to 32 MB of DRAM for internal graphics if enabled (82915G/82915GV/82915GL/82910GL
GMCH only), and 1, 2, or 8 MB of DRAM for TSEG if enabled. These bits are LT Lockable.
Bit
Access &
Default
Description
7:3
R/W
01h
Top of Low Usable DRAM (TOLUD): This register contains bits 31:27 of an
address one byte above the maximum DRAM memory that is usable by the
operating system. Address bits 31:27 programmed to 01h implies a minimum
memory size of 128 MBs.
Configuration software must set this value to the smaller of the following 2 choices:
• Maximum amount memory in the system plus one byte or the minimum address
allocated for PCI memory.
Address bits 26:0 are assumed to be 000_0000h for the purposes of address
comparison. The host interface positively decodes an address towards DRAM if the
incoming address is less than the value programmed in this register.
If this register is set to 0000 0b, it implies 128 MBs of system memory.
Note: The Top of Low Usable DRAM is the lowest address above both Graphics
Stolen memory (82915G/82915GV/82915GL/82910GL only) and TSEG. The host
interface determines the base of Graphics Stolen Memory by subtracting the
Graphics Stolen Memory Size from TOLUD and further decrements by 1 MB to
determine base of TSEG.
2:0
Reserved
Programming Example (82915G/82915GV/82915GL/82910GL GMCH only):
• C1DRB7 is set to 4 GB
• TSEG is enabled and TSEG size is set to 1 MB
• Internal Graphics is enabled and Graphics Mode Select is set to 32 MB
• BIOS knows the OS requires 1G of PCI space.
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This
20-MB range at the very top of addressable memory space is lost to APIC.
According to the above equation, TOLUD is originally calculated to: 4 GB = 1_0000_0000h
The system memory requirements are:
4 GB (max addressable space) – 1 GB (PCI space) – 20 MB (lost memory) =
3 GB – 128 MB (minimum granularity) = B800_0000h
Since B800_0000h (PCI and other system requirements) is less than 1_0000_0000h, TOLUD
should be programmed to B8h.
Datasheet
89
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.27
SMRAM—System Management RAM Control (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
9Dh
00h
R/W/L, RO
8 bits
Size:
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are
treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also,
the OPEN bit must be reset before the LOCK bit is set.
Bit
Access &
Default
Description
7
6
Reserved
R/W/L
0b
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM
space DRAM is made visible even when SMM decode is not active. This is
intended to help BIOS initialize SMM space. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time.
5
4
R/W/L
0b
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not
accessible to data references, even if SMM decode is active. Code references
may still access SMM space DRAM. This will allow SMM software to reference
through SMM space to update the display even when SMM is mapped over the
VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set
at the same time. Note that the D_CLS bit only applies to Compatible SMM
space.
R/W/L
0b
SMM Space Locked (D_LCK): When D_LCK is set to 1, D_OPEN is reset to 0
and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and
TSEG_EN become read only. D_LCK can be set to 1 via a normal configuration
space write but can only be cleared by a full Reset. The combination of D_LCK
and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to "lock down"
SMM space in the future so that no application software (or BIOS itself) can
violate the integrity of SMM space, even if the program has knowledge of the
D_OPEN function.
3
R/W/L
0b
Global SMRAM Enable (G_SMRAME): If set to a 1, Compatible SMRAM
functions are enabled, providing 128 KB of DRAM accessible at the A0000h
address while in SMM (ADSB with SMM decode). To enable Extended SMRAM
function this bit has be set to 1. Refer to the section on SMM for more details.
Once D_LCK is set, this bit becomes read only.
2:0
RO
010b
Compatible SMM Space Base Segment (C_BASE_SEG): This field indicates
the location of SMM space. SMM DRAM is not remapped. It is simply made
visible if the conditions are right to access SMM space, otherwise the access is
forwarded to DMI. Since the (G)MCH supports only the SMM space between
A0000h and BFFFFh, this field is hardwired to 010.
90
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.28
ESMRAMC—Extended System Management RAM Control
(D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
9Eh
00h
R/W/L, RO
8 bits
Size:
The Extended SMRAM register controls the configuration of Extended SMRAM space. The
Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory
space that is above 1 MB.
Bit
Access &
Default
Description
7
R/W/L
0b
Enable High SMRAM (H_SMRAME): This bit controls the SMM memory space
location (i.e., above 1 MB or below 1 MB). When G_SMRAME is 1 and H_SMRAME
is 1, the high SMRAM memory space is enabled. SMRAM accesses within the range
0FEDA0000h to 0FEDBFFFFh are remapped to DRAM addresses within the range
000A0000h to 000BFFFFh. Once D_LCK has been set, this bit becomes read only.
6
R/W/C
0b
Invalid SMRAM Access (E_SMERR): This bit is set when the processor has
accessed the defined memory ranges in Extended SMRAM (High Memory and T-
segment) while not in SMM space and with the D-OPEN bit = 0. It is software’s
responsibility to clear this bit. The software must write a 1 to this bit to clear it.
5
4
RO
1b
SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the (G)MCH .
L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the (G)MCH.
L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the (G)MCH.
RO
1b
3
RO
1b
2:1
R/W/L
00b
TSEG Size (TSEG_SZ): This field selects the size of the TSEG memory block if
enabled. Memory from the top of DRAM space is partitioned away so that it may
only be accessed by the processor interface and only then when the SMM bit is set
in the request packet. Non-SMM accesses to this memory region are sent to the
DMI when the TSEG memory block is enabled.
00 = 1-MB Tseg. (TOLUD – Graphics Stolen Memory Size – 1M) to (TOLUD –
Graphics Stolen Memory Size).
01 = 2-MB Tseg (TOLUD – Graphics Stolen Memory Size – 2M) to (TOLUD –
Graphics Stolen Memory Size).
10 = 8-MB Tseg (TOLUD – Graphics Stolen Memory Size – 8M) to (TOLUD –
Graphics Stolen Memory Size).
11 = Reserved.
Once D_LCK has been set, these bits become read only.
NOTE: References to Graphics Stolen Memory only apply to the
82915G/82915GV/82915GL/82910GL GMCH only.
0
R/W/L
0b
TSEG Enable (T_EN): This bit Enables SMRAM memory for Extended SMRAM
space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to
appear in the appropriate physical address space. Note that once D_LCK is set, this
bit becomes read only.
Datasheet
91
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.29
ERRSTS—Error Status (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
C8h
0000h
R/WC/S, RO
16 bits
Size:
This register is used to report various error conditions via the SERR DMI messaging mechanism.
A SERR DMI message is generated on a zero to one transition of any of these flags (if enabled by
the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR
is enabled and generated. After the error processing is complete, the error logging mechanism can
be unlocked by clearing the appropriate status bit by software writing a 1 to it.
0Bit
Access &
Default
Description
15:13
12
Reserved
R/WC/S
0b
(G)MCH Software Generated Event for SMI:
1 = This bit indicates the source of the SMI was a Device 2 Software Event.
11
R/WC/S
0b
(G)MCH Thermal Sensor Event for SMI/SCI/SERR: This bit indicates that a
(G)MCH Thermal Sensor trip has occurred and an SMI, SCI, or SERR has been
generated. The status bit is set only if a message is sent based on Thermal
event enables in Error command, SMI command, and SCI command registers. A
trip point can generate one of SMI, SCI, or SERR interrupts (two or more per
event is illegal). Multiple trip points can generate the same interrupt, if software
chooses this mode, subsequent trips may be lost. If this bit is already set, an
interrupt message will not be sent on a new thermal sensor event.
10
9
Reserved
R/WC/S
0b
LOCK to non-DRAM Memory Flag (LCKF):
1 = (G)MCH detected a lock operation to memory space that did not map into
DRAM.
8
R/WC/S
0b
Received Refresh Timeout Flag(RRTOF):
1 = 1024 memory core refreshes are enqueued.
Reserved
7:0
92
Datasheet
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.30
ERRCMD—Error Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
CAh
0000h
R/W
Size:
16 bits
This register controls the (G)MCH responses to various system errors. Since the (G)MCH does
not have an SERR# signal, SERR messages are passed from the (G)MCH to the Intel ICH6 over
DMI. When a bit in this register is set, a SERR message will be generated on DMI when the
corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is
globally enabled for Device 0 via the PCI Command register.
Bit
Access &
Default
Description
15:12
11
Reserved
R/W
0b
SERR on (G)MCH Thermal Sensor Event (TSESERR)
1 = The (G)MCH generates a DMI SERR special cycle when bit 11 of the
ERRSTS is set. The SERR must not be enabled at the same time as the SMI
for the same thermal sensor event.
0 = Reporting of this condition via SERR messaging is disabled.
Reserved
10
9
R/W
0b
SERR on LOCK to non-DRAM Memory (LCKERR)
1 = The (G)MCH will generate a DMI SERR special cycle whenever a processor
lock cycle is detected that does not hit DRAM.
0 = Reporting of this condition via SERR messaging is disabled.
8
R/W
0b
SERR on DRAM Refresh Timeout (DRTOERR)
1 = The (G)MCH generates a DMI SERR special cycle when a DRAM Refresh
timeout occurs.
0 = Reporting of this condition via SERR messaging is disabled.
Reserved
7:0
Datasheet
93
Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.31
SKPD—Scratchpad Data (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
DCh
00000000h
R/W
Size:
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the convenience of
BIOS and graphics drivers.
Bit
Access &
Default
Description
31:0
R/W
Scratchpad Data: 1 DWord of data storage.
00000000 h
4.1.32
CAPID0—Capability Identifier (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
E0h
000000000001090009h
RO
Size:
72 bits
Bit
Access &
Default
Description
71:28
27:24
Reserved
RO
1h
CAPID Version: This field has the value 0001b to identify the first revision of the
CAPID register definition.
23:16
15:8
7:0
RO
09h
CAPID Length: This field has the value 09h to indicate the structure length
(9 bytes).
RO
00h
Next Capability Pointer: This field is hardwired to 00h indicating the end of the
capabilities linked list.
RO
CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the
09h
PCI SIG for vendor dependent capability pointers.
§
94
Datasheet
MCHBAR Registers
R
5 MCHBAR Registers
These registers are offset from the MCHBAR base address.
Address
Offset
Register
Symbol
Default
Access
Value
Register Name
100h
101h
C0DRB0
C0DRB1
C0DRB2
C0DRB3
—
Channel A DRAM Rank Boundary Address 0
Channel A DRAM Rank Boundary Address 1
Channel A DRAM Rank Boundary Address 2
Channel A DRAM Rank Boundary Address 3
Reserved
00h
00h
R/W
R/W
R/W
R/W
—
102h
00h
103h
00h
104–107h
108h
—
C0DRA0
C0DRA2
—
Channel A DRAM Rank 0,1 Attribute
Channel A DRAM Rank 2,3 Attribute
Reserved
00h
R/W
R/W
—
109h
00h
10A–10Bh
10Ch
—
C0DCLKDIS
—
Channel A DRAM Clock Disable
Reserved
00h
R/W
—
10Dh
—
10E–10F
110–113h
114–117h
118–11Fh
120–123h
124–17Fh
180h
C0BNKARC
—
Channel A DRAM Bank Architecture
Reserved
0000h
—
R/W
—
C0DRT1
—
Channel A DRAM Timing Register
Reserved
900122h
—
R/W
—
C0DRC0
—
Channel A DRAM Controller Mode 0
Reserved
00000000h
—
R/W, RO
—
C1DRB0
C1DRB1
C1DRB2
C1DRB3
—
Channel B DRAM Rank Boundary Address 0
Channel B DRAM Rank Boundary Address 1
Channel B DRAM Rank Boundary Address 2
Channel B DRAM Rank Boundary Address 3
Reserved
00h
R/W
R/W
R/W
R/W
—
181h
00h
182h
00h
183h
00h
184–187h
188h
—
C1DRA0
C1DRA2
—
Channel B DRAM Rank 0,1 Attribute
Channel B DRAM Rank 2,3 Attribute
Reserved
00h
R/W
R/W
—
189h
00h
18A–18Bh
18Ch
—
C1DCLKDIS
—
Channel B DRAM Clock Disable
Reserved
00h
R/W
—
18Dh
—
18E–18Fh
190–193h
194h
C1BNKARC
—
Channel B Bank Architecture
Reserved
0000h
—
R/W
—
C1DRT1
Channel B DRAM Timing Register 1
900122h
R/W, RO
Datasheet
95
MCHBAR Registers
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
195–19Fh
1A0–1A3h
1A4–F0Fh
F10–F13h
F14h
—
Reserved
—
—
R/W, RO
—
C1DRC0
—
Channel B DRAM Controller Mode 0
Reserved
00000000h
—
PMCFG
PMSTS
Power Management Configuration
Power Management Status
00000000h
00000000h
R/W
R/W/C/S
5.1
MCHBAR Register Details
5.1.1
C0DRB0—Channel A DRAM Rank Boundary Address 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
100h
00h
R/W
Size:
8 bits
The DRAM Rank Boundary Register defines the upper boundary address of each DRAM rank
with a granularity of 32 MB. Each rank has its own single-byte DRB register. These registers are
used to determine which chip select will be active for a given address.
Channel and Rank Map:
Channel A Rank 0: 100h
Channel A Rank 1: 101h
Channel A Rank 2: 102h
Channel A Rank 3: 103h
Channel B Rank 0: 180h
Channel B Rank 1: 181h
Channel B Rank 2: 182h
Channel B Rank 3: 183h
Single Channel or Asymmetric Channels Example
If the channels are independent, addresses in Channel B should begin where addresses in Channel
A left off, and the address of the first rank of Channel A can be calculated from the technology
(256 Mbit, 512 Mbit, or 1 Gbit) and the x8 or x16 configuration. With independent channels, a
value of 01h in C0DRB0 indicates that 32 MB of DRAM has been populated in the first rank, and
the top address in that rank is 32 MB.
96
Datasheet
MCHBAR Registers
R
Programming guide
If Channel A is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in chA rank0 (in 32-MB increments)
C0DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments)
______
C1DRB0 = Total memory in chA rank0 + chA rank1 + chA rank2 + chA rank3 + chB rank0
(in 32-MB increments)
If Channel B is empty, all of the C1DRBs are programmed with the same value as C0DRB3.
Interleaved Channels Example
If channels are interleaved, corresponding ranks in opposing channels will contain the same value,
and the value programmed takes into account the fact that twice as many addresses are spanned
by this rank compared to the single channel case. With interleaved channels, a value of 01h in
C0DRB0 and a value of 01h in C1DRB0 indicate that 32 MB of DRAM has been populated in
the first rank of each channel and the top address in that rank of either channel is 64 MB.
Programming guide:
C0DRB0 = C1DRB0 = Total memory in chA rank0 (in 32-MB increments)
C0DRB1 = C1DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments)
______
C0DRB3 = C1DRB3 = Total memory in chA rank0 + chA rank1+ chA rank2 + chA rank3
(in 32-MB increments)
Note: Channel A DRB3 and Channel B DRB3 must be equal for this mode, but the other DRBs may be
different.
In all modes, if a DIMM is single sided, it appears as a populated rank and an empty rank. A DRB
must be programmed appropriately for each.
Each Rank is represented by a byte. Each byte has the following format.
Bit
Access &
Default
Description
7:0
R/W
00h
Channel A DRAM Rank Boundary Address: This 8 bit value defines the upper
and lower addresses for each DRAM rank. Bits 6:2 are compared against
Address 31:27 to determine the upper address limit of a particular rank. Bits 1:0
must be 0s. Bit 7 may be programmed to a 1 in the highest DRB (DRB3) if 4 GBs
of memory is present.
Datasheet
97
MCHBAR Registers
R
5.1.2
5.1.3
5.1.4
C0DRB1—Channel A DRAM Rank Boundary Address 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
101h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
C0DRB2—Channel A DRAM Rank Boundary Address 2
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
102h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
C0DRB3—Channel A DRAM Rank Boundary Address 3
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
103h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
98
Datasheet
MCHBAR Registers
R
5.1.5
C0DRA0—Channel A DRAM Rank 0,1 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
108h
00h
R/W
Size:
8 bits
The DRAM Rank Attribute Registers define the page sizes to be used when accessing different
ranks. These registers should be left with their default value (all zeros) for any rank that is
unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in
the CxDRA registers describes the page size of a pair of ranks.
Channel and Rank Map:
Channel A Rank 0, 1:
Channel A Rank 2, 3:
Channel B Rank 0, 1:
Channel B Rank 2, 3:
108h
109h
188h
189h
Bit
Access &
Default
Description
7
Reserved
6:4
R/W
Channel A DRAM odd Rank Attribute: This 3 bit field defines the page size of
000b
the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
3
Reserved
2:0
R/W
Channel A DRAM even Rank Attribute: This 3 bit field defines the page size of
000b
the corresponding rank.
000 = Unpopulated
001 = Reserved
010 = 4 KB
011 = 8 KB
100 = 16 KB
Others = Reserved
5.1.6
C0DRA2—Channel A DRAM Rank 2,3 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
109h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRA0.
Datasheet
99
MCHBAR Registers
R
5.1.7
C0DCLKDIS—Channel A DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
10Ch
00h
R/W
Size:
8 bits
This register can be used to disable the system memory clock signals to each DIMM slot. This can
significantly reduce EMI and Power concerns for clocks that go to unpopulated DIMMs. Clocks
should be enabled based on whether a slot is populated, and what kind of DIMM is present.
Bit
Access &
Default
Description
7:6
5
Reserved
R/W
0b
DIMM Clock Gate Enable Pair 5
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
4
3
2
1
0
R/W
0b
DIMM Clock Gate Enable Pair 4
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 3
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 2
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 1
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
R/W
0b
DIMM Clock Gate Enable Pair 0
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
Note: Since there are multiple clock signals assigned to each Rank of a DIMM, it is important to clarify
exactly which Rank width field affects which clock signal:
Channel
Rank
Clocks Affected
0
0
1
1
0 or 1
2 or 3
0 or 1
2 or 3
SCLK_A[2:0]/ SCLK_A[2:0]#
SCLK_A[5:3]/ SCLK_A[5:3]#
SCLK_B[2:0]/ SCLK_B[2:0]#
SCLK_B[5:3]/ SCLK_B[5:3]#
100
Datasheet
MCHBAR Registers
R
5.1.8
C0BNKARC—Channel A DRAM Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
10Eh
0000h
R/W
Size:
16 bits
This register is used to program the bank architecture for each Rank.
Bit
Access &
Default
Description
15:8
7:6
Reserved
R/W
00b
Rank 3 Bank Architecture
00 = 4 Bank.
01 = 8 Bank.
1X = Reserved
Rank 2 Bank Architecture
00 = 4 Bank.
5:4
3:2
1:0
R/W
00b
01 = 8 Bank.
1X = Reserved
Rank 1 Bank Architecture
00 = 4 Bank.
R/W
00b
01 = 8 Bank.
1X = Reserved
Rank 0 Bank Architecture
00 = 4 Bank.
R/W
00b
01 = 8 Bank.
1X = Reserved
Datasheet
101
MCHBAR Registers
R
5.1.9
C0DRT1—Channel A DRAM Timing Register
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
114h
900122hh
R/W, RO
32 bits
Size:
Bit
Access &
Default
Description
31:24
23:20
Reserved
R/W
9h
Activate to Precharge delay (tRAS). This bit controls the number of DRAM clocks
for tRAS. Minimum recommendations are beside their corresponding encodings.
0h – 3h = Reserved
4h – Fh = Four to Fifteen Clocks respectively.
19
RO
0b
Reserved for Activate to Precharge Delay (tRAS) MAX: It is required that the
Panic Refresh timer be set to a value less than the tRAS maximum. Based on this
setting, a Panic Refresh occurs before TRAS maximum expiration and closes all
the banks.
This bit controls the maximum number of clocks that a DRAM bank can remain
open. After this time period, the DRAM controller will guarantee to pre-charge the
bank. This time period may or may not be set to overlap with time period that
requires a refresh to happen.
The DRAM controller includes a separate tRAS-MAX counter for every supported
bank. With a maximum of four ranks, and four banks per rank, there are 16
counters per channel.
0 = 120 microseconds
1 = Reserved
Note: This register will become Read Only with a value of 0 if the design does
not implement these counters.
t
RAS-MAX is not required because a panic refresh will close all banks in a rank
before tRAS-MAX expires.
18:10
9:8
Reserved
R/W
01b
CASB Latency (tCL). This value is programmable on DDR2 DIMMs. The value
programmed here must match the CAS Latency of every DDR2 DIMM in the
system.
Encoding DDR CL
DDR2 CL
00
01
3
5
2.5
4
10
2
3
11
Reserved
Reserved
7
Reserved
102
Datasheet
MCHBAR Registers
R
Bit
Access &
Default
Description
6:4
R/W
DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted
010b
between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
Reserved
3
2:0
R/W
010b
DRAM RAS Precharge (tRP). This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
Datasheet
103
MCHBAR Registers
R
5.1.10
C0DRC0—Channel A DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
120h
00000000h
R/W
Size:
32 bits
Access &
Default
Bit
Description
31:30
29
Reserved
R/W
0b
Initialization Complete (IC): This bit is used for communication of software state
between the memory controller and the BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete.
28:11
10:8
Reserved
R/W
Refresh Mode Select (RMS): This field determines whether refresh is enabled
000b
and, if so, at what rate refreshes will be executed.
000 = Refresh disabled
001 = Refresh enabled. Refresh interval 15.6 µsec
010 = Refresh enabled. Refresh interval 7.8 µsec
011 = Refresh enabled. Refresh interval 3.9 µsec
100 = Refresh enabled. Refresh interval 1.95 µsec
111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other = Reserved
7
RO
0b
Reserved
104
Datasheet
MCHBAR Registers
R
Access &
Default
Bit
Description
6:4
R/W
Mode Select (SMS). These bits select the special operational mode of the DRAM
interface. The special modes are intended for initialization at power up.
000 b
000 = Post Reset state – When the (G)MCH exits reset (power-up or otherwise),
the mode select field is cleared to “000”.
During any reset sequence, while power is applied and reset is active, the
(G)MCH de-asserts all CKE signals. After internal reset is de-asserted,
CKE signals remain de-asserted until this field is written to a value
different than “000”. On this event, all CKE signals are asserted.
During suspend, (G)MCH internal signal triggers DRAM controller to flush
pending commands and enter all ranks into Self-Refresh mode. As part of
resume sequence, (G)MCH will be reset – which will clear this bit field to
“000” and maintain CKE signals de-asserted. After internal reset is de-
asserted, CKE signals remain de-asserted until this field is written to a
value different than “000”. On this event, all CKE signals are asserted.
During entry to other low power states (C3, S1), (G)MCH internal signal
triggers DRAM controller to flush pending commands and enter all ranks
into Self-Refresh mode. During exit to normal mode, (G)MCH signal
triggers DRAM controller to exit Self-Refresh and resume normal
operation without S/W involvement.
001 = NOP Command Enable – All processor cycles to DRAM result in a NOP
command on the DRAM interface.
010 = All Banks Pre-charge Enable – All processor cycles to DRAM result in an
“all banks precharge” command on the DRAM interface.
011 = Mode Register Set Enable – All processor cycles to DRAM result in a
“mode register” set command on the DRAM interface. Host address lines
are mapped to DRAM address lines in order to specify the command sent.
Host address lines [12:3] are mapped to MA[9:0], and HA[13] is mapped
to MA[11].
101 = Reserved
110 = CBR Refresh Enable – In this mode all processor cycles to DRAM result in
a CBR cycle on the DRAM interface
111 = Normal operation
Reserved
3:2
1:0
RO
DRAM Type (DT). This field is used to select between supported SDRAM types.
This bit is controlled by the MTYPE strap signal.
00 = Reserved
01 = Dual Data Rate (DDR) SDRAM
10 = Second Revision Dual Data Rate (DDR2) SDRAM
11 = Reserved
Datasheet
105
MCHBAR Registers
R
5.1.11
5.1.12
5.1.13
5.1.14
5.1.15
C1DRB0—Channel B DRAM Rank Boundary Address 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
180h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
C1DRB1—Channel B DRAM Rank Boundary Address 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
181h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
C1DRB2—Channel B DRAM Rank Boundary Address 2
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
182h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
C1DRB3—Channel B DRAM Rank Boundary Address 3
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
183h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
C1DRA0—Channel B DRAM Rank 0,1 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
188h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRA0.
106
Datasheet
MCHBAR Registers
R
5.1.16
5.1.17
5.1.18
5.1.19
5.1.20
C1DRA2—Channel B DRAM Rank 2,3 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
189h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRA0.
C1DCLKDIS—Channel B DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
18Ch
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DCLKDIS.
C1BNKARC—Channel B Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
18Eh
0000h
R/W
Size:
16 bits
The operation of this register is detailed in the description for register C0BNKARC.
C1DRT1—Channel B DRAM Timing Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
194h
900122h
R/W
Size:
32 bits
The operation of this register is detailed in the description for register C0DRT1.
C1DRC0—Channel B DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
1A0h
00000000h
R/W
Size:
32 bits
The operation of this register is detailed in the description for register C0DRC0.
Datasheet
107
MCHBAR Registers
R
5.1.21
PMCFG—Power Management Configuration
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
F10h
00000000h
R/W
Size:
32 bits
Bit
Access &
Default
Description
31:5
4
Reserved
R/W
0b
Enhanced Power Management Features Enable
0 = Legacy power management mode
1 = Reserved.
3:0
Reserved
5.1.22
PMSTS—Power Management Status
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
F14h
00000000h
R/W
Size:
32 bits
This register is Reset by PWROK only.
Bit
Access &
Default
Description
31:2
1
Reserved
R/WC/S
0b
Channel B in self-refresh. This bit is set by power management hardware after
Channel B is placed in self refresh as a result of a Power State or a Reset Warn
sequence. It is cleared by power management hardware before starting Channel
B self refresh exit sequence initiated by a power management exit. It is cleared
by BIOS in a warm reset (Reset# asserted while pwrok is asserted) exit
sequence.
0 = Channel B not guaranteed to be in self-refresh.
1 = Channel B in Self-Refresh.
0
R/WC/S
0b
Channel A in Self-refresh. Set by power management hardware after Channel
A is placed in self refresh as a result of a Power State or a Reset Warn
sequence. It is cleared by power management hardware before starting Channel
A self refresh exit sequence initiated by a power management exit. It is cleared
by the BIOS in a warm reset (Reset# asserted while PWOK is asserted) exit
sequence.
0 = Channel A not guaranteed to be in self-refresh.
1 = Channel A in Self-Refresh.
§
108
Datasheet
EPBAR Registers—Egress Port Register Summary
R
6 EPBAR Registers—Egress Port
Register Summary
These registers are offset from the EPBAR base address.
Table 6-1. Egress Port Register Address Map
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
044h–047h
050h–053h
EPESD
EPLE1D
EPLE1A
EP Element Self Description
EP Link Entry 1 Description
EP Link Entry 1 Address
0000h
0100h
R/WO, RO
R/WO, RO
R/WO, RO
058h–
05Fh
000000000
0000000h
060h–063h
EPLE2D
EPLE2A
EP Link Entry 2 Description
EP Link Entry 2 Address
02000002h
R/WO, RO
RO
068h–
06Fh
000000000
0008000h
6.1
EP RCRB Configuration Register Details
Figure 6-1. Link Declaration Topology
(G)MCH
X16
PEG
(Port #2)
Link #2
(Type 1)
Link #1
(Type 0)
Egress Port
(Port #0)
Main Memory
Subsystem
Link #2
(Type 0)
Link #1
(Type 0)
DMI
(Port #1)
Link #1
(Type 0)
X4
Intel® ICH6
Egress Port
(Port #0)
Egress_LinkDeclar_Topo
Datasheet
109
EPBAR Registers—Egress Port Register Summary
R
6.1.1
EPESD—EP Element Self Description
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
044h
00000201h
R/WO, RO
32 bits
Size:
This register provides information about the root complex element containing this Link
Declaration capability.
Bit
Access
& Default
Description
31:24
RO
00h
Port Number: This field specifies the port number associated with this element with
respect to the component that contains this element. A value of 00h indicates to
configuration software that this is the default egress port.
23:16
15:8
R/WO
00h
Component ID: This field identifies the physical component that contains this Root
Complex Element. Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
RO
02h
Number of Link Entries: This field indicates the number of link entries following
the Element Self Description. This field reports 2 (one each for PCI Express* x16
interface and DMI).
7:4
3:0
Reserved
RO
1h
Element Type: This field Indicates the type of the Root Complex Element.
1h = Port to system memory
110
Datasheet
EPBAR Registers—Egress Port Register Summary
R
6.1.2
EPLE1D—EP Link Entry 1 Description
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
050h
0100h
R/WO, RO
32 bits
Size:
This register provides the First part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access
& Default
Description
31:24
RO
01h
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (DMI). The target port number is with respect to
the component that contains this element as specified by the target component ID.
23:16
R/WO
00h
Target Component ID: This field identifies the physical or logical component that is
targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:2
1
Reserved
RO
0b
Link Type: This bit indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the target RCRB.
0
R/WO
0b
Link Valid
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
6.1.3
EPLE1A—EP Link Entry 1 Address
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
058h
0000000000000000h
R/WO
Size:
64 bits
This register provides the second part of a Link Entry, which declares an internal link to another
Root Complex Element.
Bit
Access &
Default
Description
63:32
31:12
Reserved
R/WO
Link Address: This field provides the memory-mapped base address of the
0 0000h
RCRB that is the target element (DMI) for this link entry.
11:0
Reserved
Datasheet
111
EPBAR Registers—Egress Port Register Summary
R
6.1.4
EPLE2D—EP Link Entry 2 Description
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
060h
02000002h
R/WO, RO
32 bits
Size:
This register provides the First part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access &
Default
Description
31:24
RO
02h
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (PCI Express* x16 interface). The target port
number is with respect to the component that contains this element as specified
by the target component ID.
23:16
R/WO
00h
Target Component ID: This field identifies the physical or logical component that
is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:2
1
Reserved
RO
1b
Link Type:
1 = Link points to configuration space of the integrated device that controls the
x16 root port. The link address specifies the configuration address (segment,
bus, device, function) of the target root port.
0
R/WO
0b
Link Valid
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
112
Datasheet
EPBAR Registers—Egress Port Register Summary
R
6.1.5
EPLE2A—EP Link Entry 2 Address
MMIO Range:
Address Offset:
Default Value:
Access:
EPBAR
068h
0000000000008000h
RO
Size:
64 bits
This register provides the second part of a Link Entry that declares an internal link to another
Root Complex Element.
Bit
Access &
Default
Description
63:28
27:20
Reserved
RO
Bus Number
00h
19:15
14:12
11:0
RO
0 0001b
Device Number: Target for this link is PCI Express* x16 port (Device 1).
RO
000b
Function Number
Reserved
§
Datasheet
113
EPBAR Registers—Egress Port Register Summary
R
114
Datasheet
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7 DMIBAR Registers—Direct Media
Interface (DMI) RCRB
This Root Complex Register Block (RCRB) controls the (G)MCH-Intel ICH6 serial interconnect.
The base address of this space is programmed in DMIBAR in device 0 configuration space. These
registers are offset from the DMIBAR base address
Table 7-1. DMI Register Address Map Summary
Address
offset
Register
Symbol
Register Name
PCI Dev #
000–003h
004–007h
008–00Bh
00C–00Dh
00E–00Fh
010–013h
014–017h
018–019h
01A–01Bh
01C–01Fh
020–023h
024–025h
026–027h
028–083h
084–087h
088–089h
08A–08Bh
08C–FFFh
DMIVCECH
DMIPVCCAP1
DMIPVCCAP2
DMIPVCCTL
—
DMI Virtual Channel Enhanced Capability Header
DMI Port VC Capability Register 1
DMI Port VC Capability Register 2
DMI Port VC Control
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
DMIBAR
Reserved
DMIVC0RCAP
DMIVC0RCTL
—
DMI VC0 Resource Capability
DMI VC0 Resource Control
Reserved
DMIVC0RSTS
DMIVC1RCAP
DMIVC1RCTL
—
DMI VC0 Resource Status
DMI VC1 Resource Capability
DMI VC1 Resource Control
Reserved
DMIVC1RSTS
—
DMI VC1 Resource Status
Reserved
DMILCAP
DMILCTL
DMILSTS
—
DMI Link Capabilities
DMI Link Control
DMI Link Status
Reserved
Datasheet
115
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1
Direct Media Interface (DMI) RCRB Register Details
7.1.1
DMIVCECH—DMI Virtual Channel Enhanced Capability
Header
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
000h
04010002h
RO
Size:
32 bits
This register indicates DMI Virtual Channel capabilities.
Bit
Access &
Default
Description
31:20
19:16
15:0
RO
040h
Pointer to Next Capability: This field indicates the next item in the list.
RO
1h
Capability Version: This field indicates support as a version 1 capability
structure.
RO
Capability ID: This field indicates this is the Virtual Channel capability item.
0002h
7.1.2
DMIPVCCAP1—DMI Port VC Capability Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
004h
00000001h
R/WO, RO
32 bits
Size:
This register describes the configuration of Virtual Channels associated with this port.
Bit
Access &
Default
Description
31:12
11:10
Reserved
RO
Port Arbitration Table Entry Size (PATS): This field indicates the size of the
00b
port arbitration table is 4 bits (to allow up to 8 ports).
Reference Clock (RC)
9:8
RO
00b
Fixed at 10 ns.
7
Reserved
6:4
RO
Low Priority Extended VC Count (LPEVC): This field indicates that there are
000b
no additional VCs of low priority with extended capabilities.
3
Reserved
2:0
R/WO
001b
Extended VC Count: This field indicates that there is one additional VC (VC1)
that exists with extended capabilities.
116
Datasheet
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.3
DMIPVCCAP2—DMI Port VC Capability Register 2
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
008h
00000001h
RO
Size:
32 bits
This register describes the configuration of Virtual Channels associated with this port.
Bit
Access &
Default
Description
31:24
RO
VC Arbitration Table Offset (ATO): This field indicates that no table is present
00h
for VC arbitration since it is fixed.
23:8
7:0
Reserved
RO
VC Arbitration Capability: This field indicates that the VC arbitration is fixed in
01h
the root complex. VC1 is highest priority and VC0 is lowest priority.
7.1.4
DMIPVCCTL—DMI Port VC Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
00Ch
00000000h
R/W, RO
16 bits
Size:
Bit
Access &
Default
Description
15:4
3:1
Reserved
R/W
000b
VC Arbitration Select: This field indicates which VC should be programmed in
the VC arbitration table. The root complex takes no action on the setting of this
field since there is no arbitration table.
0
RO
0b
Load VC Arbitration Table (LAT): This field indicates that the table programmed
should be loaded into the VC arbitration table. This bit is defined as read/write with
always returning 0 on reads.
Datasheet
117
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.5
DMIVC0RCAP—DMI VC0 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
010h
00000001h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:24
RO
Port Arbitration Table Offset (AT): This VC implements no port arbitration table
00h
since the arbitration is fixed.
23
Reserved
22:16
RO
Maximum Time Slots (MTS): This VC implements fixed arbitration, and therefore
00h
this field is not used.
15
14
RO
0b
Reject Snoop Transactions (RTS): This VC must be able to take snoopable
transactions.
RO
0b
Advanced Packet Switching (APS): This VC is capable of all transactions, not
just advanced packet switching transactions.
13:8
7:0
Reserved
RO
Port Arbitration Capability (PAC): This field indicates that this VC uses fixed
01h
port arbitration.
118
Datasheet
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.6
DMIVC0RCTL0—DMI VC0 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
014h
8000007Fh
R/W, RO
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
Virtual Channel Enable (EN): Enables the VC when set. Disables the VC when
cleared.
30:27
26:24
Reserved
RO
Virtual Channel Identifier (ID): Indicates the ID to use for this virtual channel.
000b
23:20
19:17
Reserved
R/W
0h
Port Arbitration Select (PAS): Indicates which port table is being programmed.
The root complex takes no action on this setting since the arbitration is fixed and
there is no arbitration table.
16
RO
0b
Load Port Arbitration Table (LAT): The root complex does not implement an
arbitration table for this virtual channel.
15:8
7:1
Reserved
R/W
7Fh
Transaction Class / Virtual Channel Map (TVM): This field indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
0
Reserved
Datasheet
119
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.7
DMIVC0RSTS—DMI VC0 Resource Status
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
01Ah
00000002h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
RO
1b
VC Negotiation Pending (NP):
0 = Virtual channel is Not being negotiated with ingress ports.
1 = Virtual channel is still being negotiated with ingress ports.
0
RO
0b
Port Arbitration Tables Status (ATS): There is no port arbitration table for this
VC, so this bit is reserved at 0.
7.1.8
DMIVC1RCAP—DMI VC1 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
01Ch
00008001h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:24
RO
00h
Port Arbitration Table Offset (AT): This field indicates the location of the port
arbitration table in the root complex. A value of 3h indicates the table is at offset
30h.
23
Reserved
22:16
RO
Maximum Time Slots (MTS): This value is updated by platform BIOS based upon
00h
the determination of the number of time slots available in the platform.
15
14
RO
1b
Reject Snoop Transactions (RTS): All snoopable transactions on VC1 are
rejected. This VC is for isochronous transfers only.
RO
0b
Advanced Packet Switching (APS): This VC is capable of all transactions, not
just advanced packet switching transactions.
13:8
7:0
Reserved
RO
Port Arbitration Capability (PAC): This field indicates the port arbitration
01h
capability is time-based WRR of 128 phases.
120
Datasheet
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.9
DMIVC1RCTL1—DMI VC1 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
020h
00100000h
R/W, RO
32 bits
Size:
This register controls the resources associated with Virtual Channel 1.
Bit
Access &
Default
Description
Virtual Channel Enable (EN):
0 = Disable.
31
R/W
0b
1 = Enable.
30:27
26:24
RO
0h
Reserved
R/W
Virtual Channel Identifier (ID): This field indicates the ID to use for this virtual
001b
channel.
23:20
19:17
Reserved
R/W
0h
Port Arbitration Select (PAS): This field indicates which port table is being
programmed. The only permissible value of this field is 4h for the time-based
WRR entries.
16:8
7:1
Reserved
R/W
00h
Transaction Class / Virtual Channel Map (TVM): This field indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
0
Reserved
7.1.10
DMIVC1RSTS—DMI VC1 Resource Status
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
026h
0000h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
RO
0b
VC Negotiation Pending (NP):
0 = Virtual channel is Not being negotiated with ingress ports.
1 = Virtual channel is still being negotiated with ingress ports.
Reserved
0
Datasheet
121
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.11
DMILCAP—DMI Link Capabilities
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
084h
00012C41h
R/WO, RO
32 bits
Size:
This register indicates DMI specific capabilities.
Bit
Access &
Default
Description
31:18
17:15
Reserved
R/WO
010b
L1 Exit Latency (EL1). L1 not supported on DMI.
14:12
11:10
9:4
R/WO
010b
L0s Exit Latency (EL0): This field indicates that exit latency is 128 ns to less
than 256 ns.
RO
11b
Active State Link PM Support (APMS): This field indicates that L0s is supported
on DMI.
RO
4h
Maximum Link Width (MLW): This field indicates the maximum link width is
4 ports.
3:0
RO
1h
Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s.
7.1.12
DMILCTL—DMI Link Control
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
088h
0000h
R/W
Size:
16 bits
This register allows control of DMI.
Bit
Access &
Default
Description
15:8
7
Reserved
Extended Synch (ES):
R/W
0h
1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to
entering L0 and extra TS1 sequences at exit from L1 prior to entering L0.
6:2
1:0
Reserved
Active State Link PM Control (APMC): Indicates whether DMI should enter L0s.
R/W
00b
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
122
Datasheet
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
7.1.13
DMILSTS—DMI Link Status
MMIO Range:
Address Offset:
Default Value:
Access:
DMIBAR
08Ah
0001h
RO
Size:
16 bits
This register indicates DMI status.
Bit
Access &
Default
Description
15:10
9:4
Reserved
RO
Negotiated Link Width (NLW): This field is valid only when the link is in the L0,
00h
L0s, or L1 states (after link width negotiation is successfully completed).
Negotiated link width is x4 (000100b).
All other encodings are reserved.
Link Speed (LS)
3:0
RO
1h
Link is 2.5 Gb/s.
§
Datasheet
123
DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
124
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8 Host-PCI Express* Bridge
Registers (D1:F0)
(Intel® 82915G/82915P/82915PL
Only)
Device 1contains the controls associated with the PCI Express x16 root port that is the intended to
attach as the point for external graphics. It is typically referred to as PCI Express* x16 Graphics
Interface port. In addition, it also functions as the virtual PCI-to-PCI bridge.
Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a valid value
unless the register value is stable.
The PCI Express* Specification defines two types of reserved bits: Reserved and Preserved:
• Reserved for future R/W implementations; software must preserve value read for writes to
bits.
• Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for
writes to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are part of the
Reserved and Preserved type that have historically been the typical definition for Reserved.
It is important to note that most (if not all) control bits in this device cannot be modified unless
the link is down. Software is required to first Disable the link, then program the registers, and
then re-enable the link (which will cause a full-retrain with the new settings).
Table 8-1. Host-PCI Express* Graphics Bridge Register Address Map (D1:F0)
Address
Offset
Register
Symbol
Default
Value
Register Name
Vendor Identification
Access
00–01h
02–03h
04–05h
06–07h
08h
VID1
DID1
8086h
2581h
0000h
0000h
RO
RO
Device Identification
PCI Command
PCICMD1
PCISTS1
RID1
RO, R/W
RO, R/W
RO
PCI Status
Revision Identification
See
register
description
09–0Bh
0Ch
CC1
CL1
—
Class Code
Cache Line Size
Reserved
060400h
00h
RO
R/W
—
0Dh
—
0Eh
HDR1
Header Type
01h
RO
Datasheet
125
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
0F–17h
18h
—
PBUSN1
SBUSN1
SUBUSN1
—
Reserved
—
00h
—
RO
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Reserved
19h
00h
RO
1Ah
00h
R/W
—
1Bh
—
1Ch
IOBASE1
IOLIMIT1
SSTS1
I/O Base Address
F0h
00h
RO
1Dh
I/O Limit Address
R/W
RO, R/W/C
R/W
R/W
RO, R/W
RO, R/W
—
1Eh–1Fh
20–21h
22–23h
24–25h
26–27h
28–33h
34h
Secondary Status
00h
MBASE1
MLIMIT1
PMBASE1
PMLIMIT1
—
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
Reserved
FFF0h
0000h
FFF0h
0000h
—
CAPPTR1
—
Capabilities Pointer
Reserved
88h
RO
35–3Bh
3Ch
—
—
INTRLINE1
INTRPIN1
BCTRL1
—
Interrupt Line
00h
R/W
RO
3Dh
Interrupt Pin
00h
3E–3Fh
40–7Fh
80–83h
Bridge Control
0000h
—
RO, R/W
—
Reserved
PM_CAPID1
Power Management Capabilities
19029001h
or
RO
1902A001h
84–87h
88–8Bh
PM_CS1
Power Management Control/Status
00000000h
RO, R/W/S
RO
SS_CAPID
Subsystem ID and Vendor ID Capabilities
0000800D
h
8C–8Fh
90–91h
92–93h
94–97h
98–99h
9A–9Fh
A0–A1h
A2–A3h
A4–A7h
A8–A9h
AA–ABh
AC–AFh
B0–B1h
SS
MSI_CAPID
MC
Subsystem ID and Subsystem Vendor ID
Message Signaled Interrupts Capability ID
Message Control
00008086h
A005h
RO
RO
0000h
RO, R/W
RO, R/W
R/W
MA
Message Address
00000000h
0000h
MD
Message Data
—
Reserved
—
—
PEG_CAPL
PEG_CAP
DCAP
DCTL
PCI Express* Capability List
PCI Express Capabilities
Device Capabilities
Device Control
0010h
RO
0141h
RO
00000000h
0000h
RO
R/W
DSTS
LCAP
Device Status
0000h
RO
Link Capabilities
02012E01h
0000h
R/WO
RO, R/W
LCTL
Link Control
126
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
B2–B3h
B4–B7h
B8–B9h
BA–BBh
BC–BDh
BE–BFh
C0–C3h
C4–EBh
EC–EFh
F0–FFh
100–103h
LSTS
SLOTCAP
SLOTCTL
SLOTSTS
RCTL
Link Status
1001h
00000000h
01C0h
0X00h
RO
R/WO
R/W
Slot Capabilities
Slot Control
Slot Status
RO, R/W/C
R/W
Root Control
0000h
—
Reserved
—
—
RSTS
Root Status
00000000h
—
RO, R/W/C
—
—
Reserved
PEGLC
—
PCI Express*-Graphics Legacy Control
Reserved
00000000h
—
R/W, RO
—
VCECH
Virtual Channel Enhanced Capability
Header
14010002h
RO
104–107h
108–10Bh
10C–10Dh
10E–10Fh
110–113h
114–117h
118–119h
11A–11Bh
11C–11Fh
120–123h
124–125h
126–127h
128–13Fh
140–143h
PVCCAP1
PVCCAP2
PVCCTL
—
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
00000001h
00000001h
0000h
RO, R/WO
RO
R/W
—
Reserved
—
VC0RCAP
VC0RCTL
—
VC0 Resource Capability
VC0 Resource Control
Reserved
00000000h
8000007Fh
—
RO
RO, R/W
—
VC0RSTS
VC1RCAP
VC1RCTL
—
VC0 Resource Status
VC1 Resource Capability
VC1 Resource Control
Reserved
0000h
RO
00008000h
01000000h
—
RO
RO, R/W
—
VC1RSTS
—
VC1 Resource Status
Reserved
0000h
RO
—
—
RCLDECH
Root Complex Link Declaration Enhanced
Capability Header
00010005h
RO
144–147h
148–14Fh
150–153h
154–157h
158–15Fh
ESD
—
Element Self Description
Reserved
02000100h
RO, R/WO
—
—
00000000h
—
LE1D
—
Link Entry 1 Description
Reserved
RO, R/WO
—
LE1A
Link Entry 1 Address
000000000
0000000h
R/WO
160–217h
218–21Fh
—
Reserved
—
—
PEGSSTS
PCI Express*-Graphics Sequence Status
000000000
0000FFFh
RO
220–FFFh
—
Reserved
—
—
Datasheet
127
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1
Host-PCI Express* Bridge PCI Register Details
(D1:F0)
8.1.1
VID1—Vendor Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
00h
8086h
RO
Size:
16 bits
This register combined with the Device Identification register uniquely identifies any PCI device.
Bit
Access &
Default
Description
15:0
RO
Vendor Identification (VID1): PCI standard identification for Intel.
8086h
8.1.2
DID1—Device Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
02h
2581h
RO
Size:
16 bits
This register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit
Access &
Default
Description
15:0
RO
Device Identification Number (DID1): This field is an identifier assigned to the
2581h
(G)MCH device 1 (virtual PCI-to-PCI bridge, PCI Express* Graphics port).
128
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.3
PCICMD1—PCI Command (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
04h
0000h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15:11
10
Reserved
INTA Assertion Disable:
R/W
0b
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages.
Any INTA emulation interrupts already asserted must be de-asserted when this
bit is set.
Only affects interrupts generated by the device (PCI INTA from a PME or Hot
Plug event) controlled by this command register. It does not affect upstream
MSIs, upstream PCI INTA-INTD asserts and de-assert messages.
9
8
RO
0b
Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented. Hardwired
to 0.
R/W
0b
SERR Message Enable (SERRE1): This bit is an enable bit for Device 1 SERR
messaging. The (G)MCH communicates the SERR# condition by sending a
SERR message to the Intel® ICH6. This bit, when set, enables reporting of non-
fatal and fatal errors to the Root Complex. Note that errors are reported if
enabled either through this bit or through the PCI Express* specific bits in the
Device Control Register
0 = The SERR message is generated by the (G)MCH for Device 1 only under
conditions enabled individually through the Device Control Register.
1 = The (G)MCH is enabled to generate SERR messages which will be sent to
the ICH6 for specific Device 1 error conditions that are individually enabled in
the BCTRL1 register and for all non-fatal and fatal errors generated on the
primary side of the virtual PCI to PCI Express bridge (not those received by
the secondary side). The error status is reported in the PCISTS1 register.
7
6
Reserved
R/WO
0b
Parity Error Enable (PERRE): This bit controls whether or not the Master Data
Parity Error bit in the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register cannot be set.
1 = Master Data Parity Error bit in PCI Status register can be set.
VGA Palette Snoop: Hardwired to 0.
5
4
3
RO
0b
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0.
Special Cycle Enable (SCE): Hardwired to 0.
RO
0b
Datasheet
129
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Bit
Access &
Default
Description
2
R/W
0b
Bus Master Enable (BME): This bit does not affect forwarding of completions
from the primary interface to the secondary interface.
0 = This device is prevented from making memory or I/O requests to its primary
bus. Note that according to the PCI specification, as MSI interrupt messages
are in-band memory writes, disabling the bus master enable bit prevents this
device from generating MSI interrupt messages or passing them from its
secondary bus to its primary bus. Upstream memory writes/reads, I/O
writes/reads, peer writes/reads, and MSIs will all be treated as illegal cycles.
Writes are forwarded to memory address 0h with byte enables de-asserted.
Reads will be forwarded to memory address 0h and will return Unsupported
Request status (or Master abort) in its completion packet.
1 = This device is allowed to issue requests to its primary bus. Completions for
previously issued memory read requests on the primary bus will be issued
when the data is available.
1
0
R/W
0b
Memory Access Enable (MAE)
0 = All of device 1’s memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges defined in the
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
R/W
0b
IO Access Enable (IOAE)
0 = All of device 1’s I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1 and IOLIMIT1
registers.
8.1.4
PCISTS1—PCI Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
06h
0000h
RO, R/W/C
16 bits
Size:
This register reports the occurrence of error conditions associated with primary side of the
“virtual” Host-PCI Express bridge in the (G)MCH.
Bit
15
14
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Hardwired to 0. Parity (generating poisoned TLPs)
is not supported on the primary side of this device.
R/WC
0b
Signaled System Error (SSE):
1 = This bit is set when this Device sends an SERR due to detecting an
ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the
Command register is ‘1’. Both received (if enabled by BCTRL1[1]) and
internally detected error messages do not affect this field.
13
RO
0b
Received Master Abort Status (RMAS): Not Applicable or Implemented.
Hardwired to 0. The concept of a master abort does not exist on primary side of
this device.
130
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Bit
12
Access &
Default
Description
RO
0b
Received Target Abort Status (RTAS): Hardwired to 0. The concept of a target
abort does not exist on primary side of this device.
11
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The concept of a target
abort does not exist on primary side of this device.
10:9
RO
00b
DEVSELB Timing (DEVT): This device is not the subtractive decoded device on
bus 0. This bit field is therefore hardwired to 00b to indicate that the device uses
the fastest possible decode.
8
RO
0b
Master Data Parity Error (PMDPE): Because the primary side of the PCI
Express* x16 Graphics Interface’s virtual PCI-to-PCI bridge is integrated with the
(G)MCH functionality, there is no scenario where this bit will get set. Because
hardware will never set this bit, it is impossible for software to have an
opportunity to clear this bit or otherwise test that it is implemented. The PCI
specification defines it as a R/WC; however, for this implementation, an RO
definition behaves the same way and will meet all Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
7
RO
0b
Fast Back-to-Back (FB2B): Hardwired to 0.
6
5
Reserved
RO
0b
66/60MHz capability (CAP66): Hardwired to 0.
4
3
RO
1b
Capabilities List: This bit indicates that a capabilities list is present. Hardwired
to 1.
RO
0b
INTA Status: This field indicates that an interrupt message is pending internally
to the device. Only PME and Hot Plug sources feed into this status bit (not PCI
INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit,
PCICMD1[10], has no effect on this bit.
2:0
Reserved
Datasheet
131
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.5
RID1—Revision Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
08h
See bit description
RO
Size:
8 bits
This register contains the revision number of the (G)MCH device 1.
Bit
Access &
Default
Description
7:0
RO
00h
Revision Identification Number (RID1): This field indicates the number of times
that this device in this component has been “stepped” through the manufacturing
process. Refer to the Intel®
82915G/82915P/82915PL/82915GV/82915GL/82910GL Express Chipset
Specification Update for the value of the Revision ID Register.
8.1.6
CC1—Class Code (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
09h
060400h
RO
Size:
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a register-
specific programming interface.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC): This field indicates the base class code for this
06h
device.
06h = Bridge device.
15:8
7:0
RO
04h
Sub-Class Code (SUBCC): This field indicates the sub-class code for this
device.
04h = PCI-to-PCI Bridge.
RO
00h
Programming Interface (PI): This field indicates the programming interface of
this device. This value does not specify a particular register set layout and
provides no practical use for this device.
132
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.7
CL1—Cache Line Size (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
0Ch
00h
R/W
8 bits
Size:
Bit
Access &
Default
Description
7:0
R/W
00h
Cache Line Size (Scratch pad): This field is implemented by PCI Express*
devices as a read/write field for legacy compatibility purposes but has no impact
on any PCI Express device functionality.
8.1.8
HDR1—Header Type (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
0Eh
01h
RO
8 bits
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Access &
Default
Description
7:0
RO
Header Type Register (HDR): This field returns 01h to indicate that this is a
01h
single function device with bridge header layout.
8.1.9
PBUSN1—Primary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
18h
00h
RO
8 bits
Size:
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI bus 0.
Bit
Access &
Default
Description
7:0
RO
00h
Primary Bus Number (BUSN): Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since device 1
is an internal device and its primary bus is always 0, these bits are read only and
are hardwired to 0.
Datasheet
133
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.10
SBUSN1—Secondary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
19h
00h
RO
8 bits
Size:
This register identifies the bus number assigned to the second bus side of the “virtual” bridge i.e.
to PCI Express Graphics. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express Graphics.
Bit
Access &
Default
Description
7:0
R/W
00h
Secondary Bus Number (BUSN): This field is programmed by configuration
software with the bus number assigned to PCI Express*-G.
8.1.11
SUBUSN1—Subordinate Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Ah
00h
R/W
8 bits
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI Express
Graphics. This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to PCI Express Graphics.
Bit
Access &
Default
Description
7:0
R/W
00h
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus that lies
behind the device 1 bridge. When only a single PCI device resides on the PCI
Express*-G segment, this register will contain the same value as the SBUSN1
register.
134
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.12
IOBASE1—I/O Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Ch
F0h
RO
8 bits
Size:
This register controls the processor-to-PCI Express Graphics I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]
are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KB
boundary.
Bit
Access &
Default
Description
7:4
R/W
Fh
I/O Address Base (IOBASE): This field corresponds to A[15:12] of the I/O
addresses passed by bridge 1 to PCI Express*-G. BIOS must not set this register
to 00h; otherwise, 0CF8h/0CFCh accesses will be forwarded to the PCI Express
hierarchy associated with this device.
3:0
Reserved
8.1.13
IOLIMIT1—I/O Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Dh
00h
R/W
8 bits
Size:
This register controls the processor-to-PCI Express Graphics I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purposes of address decode, address bits A[11:0]
are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-
KB aligned address block.
Bit
Access &
Default
Description
7:4
R/W
0h
I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of the I/O
address limit of device 1. Devices between this upper limit and IOBASE1 will be
passed to the PCI Express* hierarchy associated with this device.
3:0
Reserved
Datasheet
135
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.14
SSTS1—Secondary Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Eh
00h
RO, R/W/C
16 bits
Size:
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
secondary side (i.e., PCI Express Graphics side) of the “virtual” PCI-PCI Bridge in the (G)MCH.
Bit
Access &
Default
Description
15
R/WC
0b
Detected Parity Error (DPE):
1 = The MCH received across the link (upstream) a Posted Write Data Poisoned
TLP (EP=1).
14
13
12
11
R/WC
0b
Received System Error (RSE):
1 = Secondary side sends an ERR_FATAL or ERR_NONFATAL message due to
an error detected by the secondary side, and the SERR Enable bit in the
Bridge Control register is 1.
R/WC
0b
Received Master Abort (RMA):
1 = Secondary Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a completion with
Unsupported Request Completion Status.
R/WC
0b
Received Target Abort (RTA):
1 = Secondary Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a completion with
Completer Abort Completion Status.
RO
0b
Signaled Target Abort (STA): Hardwired to 0. The (G)MCH does not generate
Target Aborts (the (G)MCH will never complete a request using the Completer
Abort Completion status).
10:9
8
RO
00b
DEVSELB Timing (DEVT): Hardwired to 0.
R/WC
0b
Master Data Parity Error (SMDPE).
1 = The MCH received across the link (upstream) a Read Data Completion
Poisoned TLP (EP=1).
Note: This bit can only be set when the Parity Error Enable bit in the Bridge
Control register is set.
7
RO
0b
Fast Back-to-Back (FB2B): Hardwired to 0.
6
5
Reserved
RO
0b
66/60 MHz capability (CAP66): Hardwired to 0.
4:0
Reserved
136
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.15
MBASE1—Memory Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
20h
FFF0h
R/W
16 bits
Size:
This register controls the processor to PCI Express Graphics non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. The configuration software must initialize this register. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
Bit
15:4
3:0
Access &
Default
Description
R/W
FFFh
Memory Address Base (MBASE): This field corresponds to A[31:20] of the
lower limit of the memory range that will be passed to PCI Express*.
Reserved
Datasheet
137
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.16
MLIMIT1—Memory Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
22h
0000h
R/W
16 bits
Size:
This register controls the processor-to-PCI Express Graphics non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. Configuration software must initialize this register. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address
range will be at the top of a 1-MB aligned memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable PCI
Express Graphics address ranges (typically, where control/status memory-mapped I/O data
structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map
prefetchable address ranges (typically, graphics local memory). This segregation allows
application of USWC space attribute to be performed in a true plug-and-play manner to the
prefetchable address range for improved processor-PCI Express memory access performance.
Note: Configuration software is responsible for programming all address range registers (prefetchable,
non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with
each other and/or with the ranges covered with the main memory). There is no provision in the
(G)MCH hardware to enforce prevention of overlap and operations of the system in the case of
overlap are not guaranteed.
Bit
15:4
3:0
Access &
Default
Description
R/W
000h
Memory Address Limit (MLIMIT): This field corresponds to A[31:20] of the
upper limit of the address range passed to PCI Express*.
Reserved
138
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.17
PMBASE1—Prefetchable Memory Base Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
24h
FFF0h
RO, R/W
16 bits
Size:
This register, in conjunction with the corresponding Upper Base Address register, controls the
processor-to-PCI Express Graphics prefetchable memory access routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-
bit address. The lower 8 bits of the Upper Base Address register are read/write and correspond to
address bits A[39:32] of the 40-bit address. The configuration software must initialize this
register. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the
bottom of the defined memory address range will be aligned to a 1-MB boundary.
Bit
Access &
Default
Description
15:4
R/W
FFFh
Prefetchable Memory Base Address (MBASE): This field corresponds to
A[31:20] of the lower limit of the memory range that will be passed to PCI
Express*.
3:0
RO
0h
64-bit Address Support: This field indicates that the bridge supports only 32 bit
addresses.
Datasheet
139
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.18
PMLIMIT1—Prefetchable Memory Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
26h
0000h
RO, R/W
16 bits
Size:
This register, in conjunction with the corresponding Upper Limit Address register, controls the
processor-to-PCI Express Graphics prefetchable memory access routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-
bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to
address bits A[39:32] of the 40-bit address. The configuration software must initialize this
register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh.
Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory
block. Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Bit
15:4
3:0
Access &
Default
Description
R/W
000h
Prefetchable Memory Address Limit (PMLIMIT): This field corresponds to
A[31:20] of the upper limit of the address range passed to PCI Express*.
RO
0h
64-bit Address Support: This field indicates the bridge supports only 32 bit
addresses.
8.1.19
CAPPTR1—Capabilities Pointer (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
34h
88h
RO
8 bits
Size:
The capabilities pointer provides the address offset to the location of the first entry in this
device’s linked list of capabilities.
Bit
Access &
Default
Description
7:0
RO
First Capability (CAPPTR1): The first capability in the list is the Subsystem ID
88h
and Subsystem Vendor ID Capability.
140
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.20
INTRLINE1—Interrupt Line (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
3Ch
00h
R/W
8 bits
Size:
This register contains interrupt line routing information. The device itself does not use this value;
rather device drivers and operating systems use it to determine priority and vector information.
Bit
Access &
Default
Description
7:0
R/W
00h
Interrupt Connection: This field is used to communicate interrupt line routing
information. POST software writes the routing information into this register as it
initializes and configures the system. The value in this register indicates which
input of the system interrupt controller this device’s interrupt pin is connected to.
8.1.21
INTRPIN1—Interrupt Pin (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
3Dh
00h
RO
8 bits
Size:
This register specifies which interrupt pin this device uses.
Bit
Access &
Default
Description
7:0
RO
Interrupt Pin: As a single function device, the PCI Express* device specifies
01h
INTA as its interrupt pin.
01h = INTA
Datasheet
141
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.22
BCTRL1—Bridge Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
3Eh
0000h
RO, R/W
16 bits
Size:
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges.
The BCTRL provides additional control for the secondary interface (i.e., PCI Express) as well as
some bits that affect the overall behavior of the “virtual” Host-PCI Express bridge embedded
within (G)MCH (e.g., VGA compatible address ranges mapping).
Bit
Access &
Default
Description
15:12
11
Reserved
RO
0b
Discard Timer SERR Enable: Hardwired to 0.
10
9
RO
0b
Discard Timer Status: Hardwired to 0.
RO
0b
Secondary Discard Timer: Hardwired to 0.
Primary Discard Timer: Hardwired to 0.
8
RO
0b
7
RO
0b
Fast Back-to-Back Enable (FB2BEN): Hardwired to 0.
6
R/W
0b
Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on the
corresponding PCI Express* Port.
5
RO
0b
Master Abort Mode (MAMODE): When acting as a master, unclaimed reads
that experience a master abort returns all 1s and any writes that experience a
master abort completes normally and the data is thrown away. Hardwired to 0.
4
3
R/W
0b
VGA 16-bit Decode: This bit enables the PCI-to-PCI bridge to provide 16-bit
decoding of VGA I/O address precluding the decoding of alias addresses every 1
KB. This bit only has meaning if bit 3 (VGA Enable) of this register is also set to
1, enabling VGA I/O decoding and forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
R/W
0b
VGA Enable (VGAEN): This bit controls the routing of processor-initiated
transactions targeting VGA compatible I/O and memory address ranges. See the
VGAEN/MDAP table in Device 0, offset 97h[0].
142
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Bit
Access &
Default
Description
2
R/W
0b
ISA Enable (ISAEN): This bit is needed to exclude legacy resource decode to
route ISA resources to legacy decode path. This bit modifies the response by the
(G)MCH to an I/O access issued by the processor that target ISA I/O addresses.
This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT
registers.
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express Graphics.
1 = (G)MCH will not forward to PCI Express Graphics any I/O transactions
addressing the last 768 bytes in each 1-KB block, even if the addresses are
within the range defined by the IOBASE and IOLIMIT registers. Instead of
going to PCI Express Graphics, these cycles are forwarded to DMI where
they can be subtractively or positively claimed by the ISA bridge.
1
0
R/W
0b
SERR Enable (SERREN)
0 = No forwarding of error messages from secondary side to primary side that
could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
RO
0b
Parity Error Response Enable (PEREN): This bit controls whether or not the
Master Data Parity Error bit in the Secondary Status register is set when the
MCH receives across the link (upstream) a Read Data Completion Poisoned
TLP.
0 = Master Data Parity Error bit in Secondary Status register cannot be set.
1 = Master Data Parity Error bit in Secondary Status register can be set..
Datasheet
143
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.23
PM_CAPID1—Power Management Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
80h
1902 9001h or 1902 A001h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:27
RO
19h
PME Support: This field indicates the power states in which this device may
indicate PME wake via PCI Express messaging. D0, D3hot, and D3cold. This
device is not required to do anything to support D3hot and D3cold; it simply must
report that those states are supported. Refer to the PCI Power Management 1.1
specification for encoding explanation and other power management details.
26
25
RO
0b
D2: Hardwired to 0 to indicate that the D2 power management state is NOT
supported.
RO
0b
D1: Hardwired to 0 to indicate that the D1 power management state is NOT
supported.
24:22
21
RO
000b
Auxiliary Current: Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary
current requirements.
RO
0 b
Device Specific Initialization (DSI): Hardwired to 0 to indicate that special
initialization of this device is NOT required before generic class device driver is to
use it.
20
19
RO
0b
Auxiliary Power Source (APS): Hardwired to 0.
RO
0b
PME Clock: Hardwired to 0 to indicate this device does NOT support PME#
generation.
18:16
RO
010b
PCI PM CAP Version: Hardwired to 02h to indicate there are 4 bytes of power
management registers implemented and that this device complies with revision
1.1 of the PCI Power Management Interface Specification.
15:8
7:0
RO
90h
or
Pointer to Next Capability: This field contains a pointer to the next item in the
capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI) capability at 90h. If
MSICH (CAPL[0] @ 7Fh) is 1, then the next item in the capabilities list is the PCI
Express* capability at A0h.
A0h
RO
Capability ID: Value of 01h identifies this linked list item (capability structure) as
01h
being for PCI Power Management registers.
144
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.24
PM_CS1—Power Management Control/Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
84h
00000000h
RO, R/W/S
32 bits
Size:
Bit
Access &
Default
Description
31:16
15
Reserved
PME Status: This bit indicates that this device does not support PME#
RO
0b
generation from D3
.
cold
14:13
12:9
8
RO
00b
Data Scale: This field indicates that this device does not support the power
management data register.
RO
0h
Data Select: This field indicates that this device does not support the power
management data register.
R/W/S
0b
PME Enable: This bit indicates that this device does not generate PMEB
assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:2
1:0
Reserved
R/W
00b
Power State: This field indicates the current power state of this device and can
be used to set the device into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The device
must return to the D0 state to be fully functional.
There is no hardware functionality required to support these power states.
Datasheet
145
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.25
SS_CAPID—Subsystem ID and Vendor ID Capabilities
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
88h
0000800Dh
RO
Size:
32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides. Because
this device is an integrated part of the system and not an add-in device, it is anticipated that this
capability will never be used. However, it is necessary because Microsoft will test for its
presence.
Bit
Access &
Default
Description
31:16
15:8
Reserved
RO
Pointer to Next Capability: This field contains a pointer to the next item in the
80h
capabilities list which is the PCI Power Management capability.
7:0
RO
Capability ID: A value of 0Dh identifies this linked list item (capability structure)
0D h
as being for SSID/SSVID registers in a PCI-to-PCI Bridge.
8.1.26
SS—Subsystem ID and Subsystem Vendor ID (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
8Ch
00008086h
RO
Size:
32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These values
must be preserved through power management transitions and hardware reset.
Bit
Access &
Default
Description
31:16
15:0
R/WO
0000h
Subsystem ID (SSID): This field identifies the particular subsystem and is
assigned by the vendor.
R/WO
8086h
Subsystem Vendor ID (SSVID): This field identifies the manufacturer of the
subsystem and is the same as the vendor ID that is assigned by the PCI Special
Interest Group.
146
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.27
MSI_CAPID—Message Signaled Interrupts Capability ID
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
90h
A005h
RO
Size:
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by writing a
predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH (CAPL [0] at
7Fh). In that case walking this linked list will skip this capability and, instead, go directly from
the PCI PM capability to the PCI Express capability.
Bit
15:8
7:0
Access &
Default
Description
RO
A0h
Pointer to Next Capability: This field contains a pointer to the next item in the
capabilities list that is the PCI Express* capability.
RO
Capability ID:
05h
05h = Identifies this linked list item (capability structure) as being for MSI
registers.
Datasheet
147
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.28
MC—Message Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
92h
0000h
RO, R/W
16 bits
Size:
System software can modify bits in this register, but the device is prohibited from doing so.
If the device writes the same message multiple times, only one of those messages is guaranteed to
be serviced. If all of them must be serviced, the device must not generate the same message again
until the driver services the earlier one.
Bit
Access &
Default
Description
15:8
7
Reserved
RO
0b
64-bit Address Capable: Hardwired to 0 to indicate that the function does not
implement the upper 32 bits of the Message Address register and is incapable of
generating a 64-bit memory address.
6:4
R/W
000b
Multiple Message Enable (MME): System software programs this field to
indicate the actual number of messages allocated to this device. This number will
be equal to or less than the number actually requested.
000 = 1 message allocated
001–111 = Reserved
3:1
RO
Multiple Message Capable (MMC): System software reads this field to
000b
determine the number of messages being requested by this device.
000 = 1 message requested
001–111 = Reserved
0
R/W
0b
MSI Enable (MSIEN) Controls the ability of this device to generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME or HotPlug messages. INTA will
not be generated and INTA Status (PCISTS1[3]) will not be set.
148
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.29
MA—Message Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
94h
00000000h
RO, R/W
32 bits
Size:
Bit
Access &
Default
Description
31:2
R/W
Message Address: This field is used by system software to assign an MSI
00000000 h
address to the device.
The device handles an MSI by writing the padded contents of the MD register to
this address.
1:0
RO
Force DWord Align: Hardwired to 0 so that addresses assigned by system
00b
software are always aligned on a DWord address boundary.
8.1.30
MD—Message Data (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
98h
0000h
R/W
16 bits
Size:
Bit
Access &
Default
Description
15:0
R/W
Message Data: This field provides a base message data pattern assigned by
0000h
system software and used to handle an MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit value to
the memory address specified in the MA register. The upper 16 bits are always
set to 0. This register supplies the lower 16 bits.
Datasheet
149
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.31
PEG_CAPL—PCI Express* Capability List (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A0h
0010h
RO
Size:
16 bits
This register enumerates the PCI Express capability structure.
Bit
Access &
Default
Description
15:8
RO
00h
Pointer to Next Capability: This value terminates the capabilities list. The Virtual
Channel capability and any other PCI Express* specific capabilities that are
reported via this mechanism are in a separate capabilities list located entirely
within PCI Express extended configuration space.
7:0
RO
Capability ID: This field identifies this linked list item (capability structure) as
10h
being for PCI Express registers.
8.1.32
PEG_CAP—PCI Express*-G Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A2h
0141h
RO
Size:
16 bits
Indicates PCI Express device capabilities.
Bit
Access &
Default
Description
15:14
13:9
Reserved
RO
Interrupt Message Number: Hardwired to 0.
00h
8
R/WO
1b
Slot Implemented
0 = The PCI Express* Link associated with this port is connected to an integrated
component or is disabled.
1 = The PCI Express Link associated with this port is connected to a slot.
BIOS must initialize this field appropriately if a slot connection is not implemented.
7:4
3:0
RO
4h
Device/Port Type: Hardwired to 0100 to indicate root port of PCI Express Root
Complex.
RO
1h
PCI Express Capability Version: Hardwired to 1 as it is the first version.
150
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.33
DCAP—Device Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A4h
00000000h
RO
Size:
32 bits
This register indicates PCI Express link capabilities.
Bit
Access &
Default
Description
31:6
5
Reserved
RO
0b
Extended Tag Field Supported: Hardwired to indicate support for 5-bit Tags as a
Requestor.
4:3
2:0
RO
00b
Phantom Functions Supported: Hardwired to 0.
RO
Max Payload Size: Hardwired to indicate 128B maximum supported payload for
000b
Transaction Layer Packets (TLP).
Datasheet
151
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.34
DCTL—Device Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A8h
0000h
R/W
16 bits
Size:
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not error
messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port
Command Register.
Bit
Access &
Default
Description
15:8
7:5
Reserved
R/W
Max Payload Size
000b
000 = 128B maximum supported payload for Transaction Layer Packets (TLP).
As a receiver, the device must handle TLPs as large as the set value; as
transmitter, the device must not generate TLPs exceeding the set value.
Note: All other encodings are reserved.
Reserved
4
3
R/W
0b
Unsupported Request Reporting Enable:
0 = Disable.
1 = Enable. Unsupported Requests will be reported.
Note that reporting of error messages received by Root Port is controlled
exclusively by Root Control register.
2
1
R/W
0b
Fatal Error Reporting Enable:
0 = Disable.
1 = Enable. Fatal errors will be reported. For a Root Port, the reporting of fatal
errors is internal to the root. No external ERR_FATAL message is
generated.
R/W
0b
Non-Fatal Error Reporting Enable:
0 = Disable.
1 = Enable. Non-fatal errors will be reported. For a Root Port, the reporting of
non-fatal errors is internal to the root. No external ERR_NONFATAL
message is generated. Uncorrectable errors can result in degraded
performance.
0
R/W
0b
Correctable Error Reporting Enable:
0 = Disable.
1 = Enable. Correctable errors will be reported. For a Root Port, the reporting of
correctable errors is internal to the root. No external ERR_CORR message
is generated.
152
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.35
DSTS—Device Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
AAh
0000h
RO
Size:
16 bits
This register reflects status corresponding to controls in the Device Control register.
Note: The error reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
Bit
Access &
Default
Description
15:6
5
Reserved
RO
0b
Transactions Pending
0 = All pending transactions (including completions for any outstanding non-
posted requests on any used virtual channel) have been completed.
1 = Device has transaction(s) pending (including completions for any outstanding
non-posted requests for all used Traffic Classes).
4
3
Reserved
R/WC
0b
Unsupported Request Detected:
1 = Device received an Unsupported Request. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
Register.
2
1
0
R/WC
0b
Fatal Error Detected:
1 = Fatal error(s) were detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device Control register.
R/WC
0b
Non-Fatal Error Detected:
1 = Non-fatal error(s) were detected. Errors are logged in this register regardless
of whether error reporting is enabled or not in the Device Control register.
R/WC
0b
Correctable Error Detected:
1 = Correctable error(s) were detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
Note: The (G)MCH may report a false 8B/10B Receiver Error when exiting L0s.
This is reported thru the Correctable Error Detected bit CESTS device 1, offset
1D0h, Bit [0]. This will reduce the value of Receiver Error detection when L0s is
enabled. Disable L0s for accurate Receiver Error reporting.
Datasheet
153
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.36
LCAP—Link Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
ACh
02012E01h
R/WO
16 bits
Size:
This register indicates PCI Express device specific capabilities.
Bit
Access &
Default
Description
31:24
RO
Port Number: This field indicates the PCI Express* port number for the given PCI
02h
Express link. This field matches the value in Element Self Description [31:24].
23:18
17:15
Reserved
R/WO
010b
L1 Exit Latency: This field indicates the length of time this Port requires to
complete the transition from L1 to L0. The value 010 b indicates the range of 2 µs
to less than 4 µs. If this field is required to be any value other than the default,
BIOS must initialize it accordingly.
Both bytes of this register that contain a portion of this field must be written
simultaneously in order to prevent an intermediate (and undesired) value from
ever existing.
14:12
R/WO
010b
L0s Exit Latency: This field indicates the length of time this Port requires to
complete the transition from L0s to L0. The value 010 b indicates the range of 128
ns to less than 256 ns. If this field is required to be any value other than the
default, BIOS must initialize it accordingly.
Note: When PCI Express* is operating with separate reference clocks, L0s exit
latency may be greater than the setting in the L0s Exit Latency Register.
Expect longer exit latency then setting in L0s Exit Latency Register. The
link may enter Recovery state before reaching L0. System BIOS can
program the appropriate Exit Latency and advertised N_FTS value if it
detects that the downstream device is not using the common reference
clock (indicated in the Slot Clock Configuration bit 12 of the device’s Link
Status Register)
11:10
9:4
R/WO
11b
Active State Link PM Support: L0s & L1 entry supported.
RO
Max Link Width: Hardwired to indicate X16.
10h
When Force X1 mode is enabled on this PCI Express* x16 Graphics Interface
device, this field reflects X1 (01h).
3:0
RO
1h
Max Link Speed: Hardwired to indicate 2.5 Gb/s.
154
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.37
LCTL—Link Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B0h
0000h
RO, R/W
16 bits
Size:
This register allows control of PCI Express link.
Bit
Access &
Default
Description
15:8
7
Reserved
R/W
0h
Reserved. Must be 0 when writing this register.
6
R/W
0b
Common Clock Configuration
0 = This component and the component at the opposite end of this Link are
operating with asynchronous reference clock.
1 = This component and the component at the opposite end of this Link are
operating with a distributed common reference clock.
Components use this common clock configuration information to report the correct
L0s and L1 Exit Latencies.
5
R/W
0b
Retrain Link
0 = Normal operation
1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from L0,
L0s, or L1 states to the Recovery state.
This bit always returns 0 when read. This bit is cleared automatically (no need to
write a 0).
4
R/W
0b
Link Disable
0 = Normal operation
1 = Link is disabled. Forces the LTSSM to transition to the Disabled state (via
Recovery) from L0, L0s, or L1 states.
Link retraining happens automatically on 0 to 0 transition, just like when coming
out of reset. Writes to this bit are immediately reflected in the value read from the
bit, regardless of actual Link state.
3
RO
0b
Read Completion Boundary (RCB): Hardwired to 0 to indicate 64 byte.
2
Reserved
1:0
R/W
00b
Active State PM: This field controls the level of active state power management
supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
Datasheet
155
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.38
LSTS—Link Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B2h
1001h
RO
Size:
16 bits
This register indicates PCI Express link status.
Bit
Access &
Default
Description
15:13
12
Reserved
RO
1b
Slot Clock Configuration
0 = The device uses an independent clock irrespective of the presence of a
reference on the connector.
1 = The device uses the same physical reference clock that the platform provides
on the connector.
11
10
RO
0b
Link Training:
1 = Link training is in progress. Hardware clears this bit once Link training is
complete.
RO
0b
Training Error:
1 = This bit is set by hardware upon detection of unsuccessful training of the Link
to the L0 Link state.
9:4
RO
00h
Negotiated Width: This field indicates negotiated link width. This field is valid
only when the link is in the L0, L0s, or L1 states (after link width negotiation is
successfully completed).
00h = Reserved
01h = X1
04h = Reserved
08h = Reserved
10h = X16
All other encodings are reserved.
Negotiated Speed: This field indicates negotiated link speed.
1h = 2.5 Gb/s
3:0
RO
1h
All other encodings are reserved.
156
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.39
SLOTCAP—Slot Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B4h
00000000h
R/WO
Size:
32 bits
PCI Express slot-related registers allow for the support of Hot-Plug.
Bit
Access &
Default
Description
31:19
R/WO
0000h
Physical Slot Number: This field indicates the physical slot number attached to
this Port.
This field must be initialized by BIOS to a value that assigns a slot number that
is globally unique within the chassis.
18:17
16:15
Reserved
R/WO
00b
Slot Power Limit Scale: This field specifies the scale used for the Slot Power
Limit Value.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
If this field is written, the link sends a Set_Slot_Power_Limit message.
14:7
R/WO
00h
Slot Power Limit Value: In combination with the Slot Power Limit Scale value,
this field specifies the upper limit on power supplied by slot. Power limit (in
Watts) is calculated by multiplying the value in this field by the value in the Slot
Power Limit Scale field.
If this field is written, the link sends a Set_Slot_Power_Limit message.
6
5
4
3
R/WO
0b
Hot-plug Capable: This field indicates that this slot is capable of supporting
Hot-plug operations.
R/WO
0b
Hot-plug Surprise: This field indicates that a device present in this slot might
be removed from the system without any prior notification.
R/WO
0b
Power Indicator Present: This field indicates that a Power Indicator is
implemented on the chassis for this slot.
R/WO
0b
Attention Indicator Present: This field indicates that an Attention Indicator is
implemented on the chassis for this slot.
2:1
0
Reserved
R/WO
0b
Attention Button Present: This field indicates that an Attention Button is
implemented on the chassis for this slot. The Attention Button allows the user to
request hot-plug operations.
Datasheet
157
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.40
SLOTCTL—Slot Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
B8h
01C0h
R/W
16 bits
Size:
PCI Express slot related registers allow for the support of Hot-Plug.
Bit
Access &
Default
Description
15:10
9:8
Reserved
R/W
01b
Power Indicator Control: Reads to this register return the current state of the
Power Indicator.
Writes to this register set the Power Indicator and cause the Port to send the
appropriate POWER_INDICATOR_* messages.
00 = Reserved
01 = On
10 = Blink
11 = Off
7:6
R/W
11b
Attention Indicator Control: Reads to this register return the current state of
the Attention Indicator.
Writes to this register set the Attention Indicator and cause the Port to send the
appropriate ATTENTION_INDICATOR_* messages.
00 = Reserved
01 = On
10 = Blink
11 = Off
5
4
R/W
0b
Hot plug Interrupt Enable:
0 = Disable.
1 = Enables generation of hot plug interrupt on enabled hot plug events.
R/W
0b
Command Completed Interrupt Enable:
0 = Disable.
1 = Enables the generation of hot plug interrupt when the Hot plug controller
completes a command.
3
R/W
0b
Presence Detect Changed Enable:
0 = Disable.
1 = Enables the generation of hot plug interrupt or wake message on a
presence detect changed event.
2:1
0
Reserved
R/W
0b
Attention Button Pressed Enable:
0 = Disable.
1 = Enables the generation of hot plug interrupt or wake message on an
attention button pressed event.
158
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.41
SLOTSTS—Slot Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
BAh
0X00h
RO, R/W/C
16 bits
Size:
PCI Express slot-related registers allow for the support of Hot-Plug.
Bit
Access &
Default
Description
15:7
6
Reserved
RO
Xb
Presence Detect State: This bit indicates the presence of a card in the slot.
0 = Slot Empty
1 = Card Present in slot.
5
4
Reserved
R/WC
0b
Command Completed:
1 = Hot plug controller completed an issued command.
Presence Detect Changed:
3
R/WC
0b
1 = Presence Detect change is detected. This corresponds to an edge on the
signal that corresponds to bit 6 of this register (Presence Detect State).
2:1
0
Reserved
R/WC
0b
Attention Button Pressed:
1 = Attention Button is pressed.
Datasheet
159
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.42
RCTL—Root Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
BCh
0000h
R/W
16 bits
Size:
This register allows control of PCI Express Root Complex specific parameters. The system error
control bits in this register determine if corresponding SERRs are generated when our device
detects an error (reported in this device’s Device Status register) or when an error message is
received across the link. Reporting of SERR as controlled by these bits takes precedence over the
SERR Enable in the PCI Command Register.
Bit
Access &
Default
Description
15:4
3
Reserved
R/W
0b
PME Interrupt Enable
0 = No interrupts are generated as a result of receiving PME messages.
1 = Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit of the Root Status Register. A PME interrupt is also
generated if the PME Status bit of the Root Status Register is set when this bit
is set from a cleared state.
2
1
0
R/W
0b
System Error on Fatal Error Enable: This bit controls the Root Complex’s
response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = Indicates that an SERR should be generated if a fatal error is reported by any
of the devices in the hierarchy associated with this Root Port, or by the Root
Port itself.
R/W
0b
System Error on Non-Fatal Uncorrectable Error Enable: This bit controls the
Root Complex’s response to non-fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that an SERR should be generated if a non-fatal error is reported by
any of the devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
R/W
0b
System Error on Correctable Error Enable: This bit controls the Root Complex’s
response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that an SERR should be generated if a correctable error is reported
by any of the devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
160
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.43
RSTS—Root Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
C0h
00000000h
RO, R/W/C
32 bits
Size:
This register provides information about PCI Express Root Complex specific parameters.
Bit
Access &
Default
Description
31:18
17
Reserved
RO
0b
PME Pending: This bit indicates that another PME is pending when the PME
Status bit is set. When the PME Status bit is cleared by software; the PME is
delivered by hardware by setting the PME Status bit again and updating the
Requestor ID appropriately. The PME pending bit is cleared by hardware if no
more PMEs are pending.
16
R/W/C
0b
PME Status: This bit indicates that the requestor ID indicated in the PME
Requestor ID field asserted PME. Subsequent PMEs are kept pending until the
status register is cleared by writing a 1 to this field.
15:0
RO
PME Requestor ID: This field indicates the PCI requestor ID of the last PME
0000h
requestor.
Datasheet
161
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.44
PEGLC—PCI Express*-G Legacy Control
PCI Device:
Address Offset:
Default Value:
Access:
1
ECh
00000000h
RO, R/W
32 bits
Size:
This register controls functionality that is needed by Legacy (non-PCI Express aware) OS’s
during run time.
Bit
Access &
Default
Description
31:3
RO
Reserved
0000
0000h
2
1
0
R/W
0b
PME GPE Enable (PMEGPE):
0 = Do not generate GPE PME message when PME is received.
1 = Enable. Generate a GPE PME message when PME is received
(Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This enables
the (G)MCH to support PMEs on the PCI Express* x16 Graphics Interface
port under legacy OSs.
R/W
0b
Hot-Plug GPE Enable (HPGPE)
0 = Do not generate GPE Hot-Plug message when Hot-Plug event is received.
1 = Enable. Generate a GPE Hot-Plug message when Hot-Plug Event is received
(Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables the
(G)MCH to support Hot-Plug on the PCI Express* x16 Graphics Interface port
under legacy OSs.
R/W
0b
General Message GPE Enable (GENGPE)
0 = Do not forward received GPE assert/deassert messages.
1 = Enable. Forward received GPE assert/deassert messages. These general
GPE message can be received via the PCI Express* x16 Graphics Interface
port from an external Intel device and will be subsequently forwarded to the
Intel® ICH6 (via Assert_GPE and Deassert_GPE messages on DMI).
162
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.45
VCECH—Virtual Channel Enhanced Capability Header
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
100h
14010002h
RO
Size:
32 bits
This register indicates PCI Express device Virtual Channel capabilities.
Note: Extended capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability structures.
Bit
Access &
Default
Description
31:20
19:16
15:0
RO
140h
Pointer to Next Capability: The Link Declaration Capability is the next in the PCI
Express* extended capabilities list.
RO
1h
PCI Express Virtual Channel Capability Version: Hardwired to 1 to indicate
compliances with the 1.0a version of the PCI Express specification.
RO
Extended Capability ID: Value of 0002 h identifies this linked list item (capability
0002h
structure) as being for PCI Express Virtual Channel registers.
8.1.46
PVCCAP1—Port VC Capability Register 1 (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
104h
00000001h
RO, R/WO
32 bits
Size:
This register describes the configuration of PCI Express Virtual Channels associated with this
port.
Bit
Access &
Default
Description
31:7
6:4
Reserved
RO
000b
Low Priority Extended VC Count: This field indicates the number of (extended)
Virtual Channels in addition to the default VC belonging to the low-priority VC
(LPVC) group that has the lowest priority with respect to other VC resources in a
strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
Reserved
3
2:0
R/WO
001b
Extended VC Count: This field indicates the number of (extended) Virtual
Channels in addition to the default VC supported by the device.
Datasheet
163
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.47
PVCCAP2—Port VC Capability Register 2 (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
108h
00000001h
RO
Size:
32 bits
This register describes the configuration of PCI Express Virtual Channels associated with this
port.
Bit
Access &
Default
Description
31:24
RO
00h
VC Arbitration Table Offset: This field indicates the location of the VC Arbitration
Table. This field contains the zero-based offset of the table in DQWORDS (16
bytes) from the base address of the Virtual Channel Capability Structure. A value
of 0 indicates that the table is not present (due to fixed VC priority).
23:8
7:0
Reserved
RO
VC Arbitration Capability: This field indicates that the only possible VC
01h
arbitration scheme is hardware fixed (in the root complex).
VC1 is the highest priority, VC0 is the lowest priority.
8.1.48
PVCCTL—Port VC Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
10Ch
0000h
R/W
16 bits
Size:
Bit
Access &
Default
Description
15:4
3:1
Reserved
R/W
000b
VC Arbitration Select: This field will be programmed by software to the only
possible value as indicated in the VC Arbitration Capability field. The value 001b
when written to this field will indicate the VC arbitration scheme is hardware fixed
(in the root complex).
This field can not be modified when more than one VC in the LPVC group is
enabled.
0
Reserved
164
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.49
VC0RCAP—VC0 Resource Capability (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
110h
00000000h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:16
15
Reserved
Reject Snoop Transactions
RO
0b
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
14:0
Reserved
8.1.50
VC0RCTL—VC0 Resource Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
114h
8000007Fh
RO, R/W
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
VC0 Enable: For VC0, this is hardwired to 1 and read only as VC0 can never be
disabled.
30:27
26:24
Reserved
RO
VC0 ID: This field assigns a VC ID to the VC resource. For VC0 this is hardwired
000b
to 0 and read only.
23:8
7:1
Reserved
R/W
7Fh
TC/VC0 Map: This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource. In order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding transactions with
the TC labels are targeted at the given Link.
0
RO
1b
TC0/VC0 Map: Traffic Class 0 is always routed to VC0.
Datasheet
165
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.51
VC0RSTS—VC0 Resource Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
11Ah
0000h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
RO
1b
VC0 Negotiation Pending
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is set by
default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state. It is cleared when the link
successfully exits the FC_INIT2 state
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
0
Reserved
8.1.52
VC1RCAP—VC1 Resource Capability (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
11Ch
00008000h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:16
15
Reserved
Reject Snoop Transactions
RO
1b
0 = Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
14:0
Reserved
166
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.53
VC1RCTL—VC1 Resource Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
120h
01000000h
RO, R/W
32 bits
Size:
Controls the resources associated with PCI Express Virtual Channel 1.
Bit
Access &
Default
Description
31
R/W
0b
VC1 Enable
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled. See exceptions in note below.
Software must use the VC Negotiation Pending bit to check whether the VC
negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read
from this VC Enable bit indicates that the VC is enabled (Flow Control
Initialization is completed for the PCI Express* port); a 0 read from this bit
indicates that the Virtual Channel is currently disabled.
Notes:
• To enable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be set in both Components on a Link.
• To disable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be cleared in both Components on a Link.
• Software must ensure that no traffic is using a Virtual Channel at the time it is
disabled.
• Software must fully disable a Virtual Channel in both Components on a Link
before re-enabling the Virtual Channel.
30:27
26:24
Reserved
R/W
001b
VC1 ID: Assigns a VC ID to the VC resource. Assigned value must be non-zero.
This field cannot be modified when the VC is already enabled.
Reserved
23:8
7:1
R/W
00h
TC/VC1 Map: This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to
the VC resource. In order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding transactions with
the TC labels are targeted at the given Link.
0
RO
0b
TC0/VC1 Map: Traffic Class 0 is always routed to VC0.
Datasheet
167
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.54
VC1RSTS—VC1 Resource Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
126h
0000h
RO
Size:
16 bits
This register reports the Virtual Channel specific status.
Bit
Access &
Default
Description
15:2
1
Reserved
RO
1b
VC1 Negotiation Pending
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is set by
default on Reset, as well as when the corresponding Virtual Channel is Disabled
or the Link is in the DL_Down state. It is cleared when the link successfully exits
the FC_INIT2 state
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
0
Reserved
8.1.55
RCLDECH—Root Complex Link Declaration Enhanced
Capability Header (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
140h
00010005h
RO
Size:
32 bits
This capability declares links from this element (PCI Express* x16 Graphics Interface) to other
elements of the root complex component to which it belongs. See the PCI Express specification
for link/topology declaration requirements.
Bit
Access &
Default
Description
31:20
RO
Pointer to Next Capability: This is the last capability in the PCI Express*
extended capabilities list.
000h
19:16
15:0
RO
1h
Link Declaration Capability Version: Hardwired to 1 to indicate compliances
with the 1.0a version of the PCI Express specification.
RO
Extended Capability ID: Value of 0005h identifies this linked list item (capability
0005h
structure) as being for PCI Express Link Declaration Capability.
Note: See corresponding Egress Port Link Declaration Capability registers for diagram of Link
Declaration Topology.
168
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.56
ESD—Element Self Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
144h
02000100h
RO, R/WO
32 bits
Size:
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
Access &
Default
Description
31:24
RO
02h
Port Number: This field specifies the port number associated with this element
with respect to the component that contains this element. The egress port of the
component to provide arbitration to this Root Complex Element uses this port
number value.
23:16
15:8
R/WO
00h
Component ID: This field indicates the physical component that contains this
Root Complex Element. Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
RO
01h
Number of Link Entries: This field indicates the number of link entries following
the Element Self Description. This field reports 1 (to Egress port only as peer-to-
peer capabilities in this topology are not reported).
7:4
3:0
Reserved
RO
0h
Element Type: This field indicates the type of the Root Complex Element.
0h = root port.
Datasheet
169
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.57
LE1D—Link Entry 1 Description (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
150h
00000000h
RO, R/WO
32 bits
Size:
This register provides the First part of a Link Entry that declares an internal link to another Root
Complex Element.
Bit
Access &
Default
Description
31:24
RO
00h
Target Port Number: This field specifies the port number associated with the
element targeted by this link entry (Egress Port). The target port number is with
respect to the component that contains this element as specified by the target
component ID.
23:16
R/WO
00h
Target Component ID: This field indicates the physical or logical component that
is targeted by this link entry. A value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:2
1
Reserved
RO
0b
Link Type: This field indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the target RCRB.
0
R/WO
0b
Link Valid:
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
170
Datasheet
Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.58
LE1A—Link Entry 1 Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
158h
0000000000000000h
R/WO
Size:
64 bits
This register provides the second part of a Link Entry that declares an internal link to another
Root Complex Element.
Bit
Access &
Default
Description
63:32
31:12
Reserved
R/WO
Link Address: This field indicates memory-mapped base address of the RCRB
0 0000h
that is the target element (Egress Port) for this link entry.
11:0
Reserved
8.1.59
PEGSSTS—PCI Express*-G Sequence Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
218h
0000000000000FFFh
RO
Size:
64 bits
This register provides PCI Express status reporting that is required by the PCI Express
specification.
Bit
Access &
Default
Description
63:60
59:48
Reserved
RO
000h
Next Transmit Sequence Number: Value of the NXT_TRANS_SEQ counter.
This counter represents the transmit Sequence number to be applied to the next
TLP to be transmitted onto the Link for the first time.
47:44
43:32
Reserved
RO
Next Packet Sequence Number: Packet sequence number to be applied to the
000h
next TLP to be transmitted or re-transmitted onto the Link.
31:28
27:16
Reserved
RO
Next Receive Sequence Number: This is the sequence number associated with
000h
the TLP that is expected to be received next.
15:12
11:0
Reserved
RO
Last Acknowledged Sequence Number: This is the sequence number
FFFh
associated with the last acknowledged TLP.
§
Datasheet
171
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9 Integrated Graphics Device
Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/
82910GL GMCH Only)
Device 2 contains registers for the internal graphics functions. Table 9-1 lists the PCI
configuration registers in order of ascending offset address. Function 0 can be VGA compatible
or not, this is selected through bit 1 of GGC register (Device 0, offset 52h). The following
sections describe Device 2 PCI configuration registers only.
Table 9-1. Integrated Graphics Device Register Address Map (D2:F0)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
00–01h
02–03h
04–05h
06–07h
08h
VID2
DID2
Vendor Identification
8086h
2582h
0000h
0090h
RO
RO
Device Identification
PCI Command
PCICMD2
PCISTS2
RID2
RO, R/W
RO
PCI Status
Revision Identification
See register
description
RO
09–0Bh
0Ch
CC
CLS
Class Code
030000h
00h
RO
RO
Cache Line Size
0Dh
MLT2
Master Latency Timer
Header Type
00h
RO
0Eh
HDR2
—
80h
RO
0Fh
Reserved
—
—
10–13h
14–17h
18–1Bh
1C–1Fh
20–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
MMADR
IOBAR
GMADR
GTTADR
—
Memory Mapped Range Address
I/O Base Address
00000000h
00000001h
00000008h
00000000h
—
RO, R/W
RO, R/W
RO, R/W/L
RO, R/W
—
Graphics Memory Range Address
Graphics Translation Table Range Address
Reserved
SVID2
SID2
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
Capabilities Pointer
0000h
0000h
00000000h
D0h
R/WO
R/WO
RO
ROMADR
CAPPOINT
—
RO
35–3Bh
Reserved
—
—
Datasheet
173
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
3Ch
3Dh
INTRLINE
INTRPIN
MINGNT
MAXLAT
—
Interrupt Line
Interrupt Pin
00h
01h
00h
00h
—
R/W
RO
RO
RO
—
3Eh
Minimum Grant
3Fh
Maximum Latency
40–43h
44h
Reserved
MCAPPTR
—
Mirror of Dev0 Capability Pointer
Reserved
D0h
—
RO
—
45–47h
48–50h
MCAPID
Mirror of Dev0 Capability Identification
0000000000
01090009h
RO
51h
—
Reserved
—
—
52–53h
54–57h
MGGC
Mirror of Dev0 GMCH Graphics Control
Mirror of Dev0 Device Enable
0030h
RO
RO
MDEVENde
v0F0
00000019h
58–5Bh
5C–5Fh
60–61h
62h
—
BSM
—
Reserved
—
07800000h
—
—
RO
Base of Stolen Memory
Reserved
—
MSAC
—
Multi size Aperture Control
Reserved
00h
R/W
—
63–CFh
D0–D1h
D2–D3h
D4–D5h
D6–D7h
E0–E1h
E2–E3h
E4–E7
—
PMCAPID
PMCAP
PMCS
—
Power Management Capabilities ID
Power Management Capabilities
Power Management Control/Status
Reserved
0001h
0022h
0000h
—
RO
RO
RO, R/W
—
SWSMI
—
Software SMI
0000h
—
R/W
—
Reserved
ASLE
—
System Display Event
Reserved
00000000h
—
R/W
—
E8h–FBh
FC–FFh
ASLS
ASL Storage
00000000h
R/W
174
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1
Integrated Graphics Device PCI Register Details
(D2:F0)
9.1.1
VID2—Vendor Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
00h
8086h
RO
Size:
16 bits
This register, combined with the Device Identification register, uniquely identifies any PCI
device.
Bit
Access &
Default
Description
15:0
RO
Vendor Identification Number (VID): PCI standard identification for Intel.
8086h
9.1.2
DID2—Device Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
02h
2582h
RO
Size:
16 bits
This register, combined with the Vendor Identification register, uniquely identifies any PCI
device.
Bit
Access &
Default
Description
15:0
RO
Device Identification Number (DID): This is a 16 bit value assigned to the GMCH
2582h
Graphic device
Datasheet
175
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.3
PCICMD2—PCI Command (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
04h
0000h
RO, R/W
16 bits
Size:
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
Access &
Default
Description
15:11
10
Reserved
R/W
0b
Interrupt Disable: This bit disables the device from asserting INTx#.
0 = Enable the assertion of this device’s INTx# signal.
1 = Disable the assertion of this device’s INTx# signal. DO_INTx messages will
not be sent to the DMI.
9
8
7
6
RO
0b
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
RO
0b
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
RO
0b
Address/Data Stepping Enable (ADSTEP): Not Implemented. Hardwired to 0.
RO
0b
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0. Since the IGD
belongs to the category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error that it detects
and continues with normal operation.
5
4
3
2
RO
0b
Video Palette Snooping (VPS): This bit is hardwired to 0 to disable snooping.
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does
not support memory write and invalidate commands.
RO
0b
Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD ignores Special
cycles.
R/W
0b
Bus Master Enable (BME):
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1
0
R/W
0b
Memory Access Enable (MAE): This bit controls the IGD’s response to memory
space accesses.
0 = Disable.
1 = Enable.
R/W
0 b
I/O Access Enable (IOAE): This bit controls the IGD’s response to I/O space
accesses.
0 = Disable.
1 = Enable.
176
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.4
PCISTS2—PCI Status (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
06h
0090h
RO
Size:
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and
PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the
IGD.
Bit
15
14
13
12
11
10:9
8
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Since the IGD does not detect parity; this bit is
always hardwired to 0.
RO
0b
Signaled System Error (SSE): The IGD never asserts SERR#, therefore this bit
is hardwired to 0.
RO
0b
Received Master Abort Status (RMAS): The IGD never gets a Master Abort,
therefore, this bit is hardwired to 0.
RO
0b
Received Target Abort Status (RTAS): The IGD never gets a Target Abort,
therefore this bit is hardwired to 0.
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use
target abort semantics.
RO
00b
DEVSEL Timing (DEVT): N/A. These bits are hardwired to 00.
RO
0b
Master Data Parity Error Detected (DPD): Since Parity Error Response is
hardwired to disabled (and the IGD does not do any parity detection), this bit is
hardwired to 0.
7
6
5
4
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back
when the transactions are not to the same agent.
RO
0b
User Defined Format (UDF). Hardwired to 0.
66 MHz PCI Capable (66C). N/A; Hardwired to 0.
RO
0b
RO
1b
Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h
provides an offset into the function’s PCI Configuration Space containing a
pointer to the location of the first item in the list.
3
RO
0b
Interrupt Status: This bit reflects the state of the interrupt in the device. Only
when the Interrupt Disable bit in the command register is a 0 and this Interrupt
Status bit is a 1, will the devices INTx# signal be asserted. Setting the Interrupt
Disable bit to a 1 has no effect on the state of this bit.
2:0
Reserved
Datasheet
177
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.5
RID2—Revision Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
08h
See bit description
RO
Size:
8 bits
This register contains the revision number for Device 2 Functions 0 and 1
Bit
Access &
Default
Description
7:0
RO
00h
Revision Identification Number (RID): This field indicates the number of times
that this device in this component has been “stepped” through the manufacturing
process. Refer to the Intel® 82915G/82915P/82915GV/82910GL Express
Chipset Specification Update for the value of the Revision ID Register.
9.1.6
CC—Class Code (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
09h
030000h
RO
Size:
24 bits
This register contains the device programming interface information related to the Sub-Class
Code and Base Class Code definition for the IGD. This register also contains the Base Class Code
and the function sub-class in relation to the Base Class Code.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC). This is an 8-bit value that indicates the base class
03h
code for the GMCH.
03h = Display Controller.
15:8
7:0
RO
00h
Sub-Class Code (SUBCC): Value will be determined based on Device 0 GGC
register, bit 1.
00h = VGA compatible
80h = Non VGA
RO
Programming Interface (PI)
00h = Hardwired as a Display controller.
00 h
178
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.7
CLS—Cache Line Size (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Ch
00h
RO
8 bits
Size:
The IGD does not support this register as a PCI slave.
Bit
Access &
Default
Description
7:0
RO
00h
Cache Line Size (CLS): This field is hardwired to 0s. The IGD, as a PCI
compliant master, does not use the Memory Write and Invalidate command and,
in general, does not perform operations based on cache line size.
9.1.8
MLT2—Master Latency Timer (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Dh
00h
RO
8 bits
Size:
The IGD does not support the programmability of the master latency timer because it does not
perform bursts.
Bit
Access &
Default
Description
7:0
RO
Master Latency Timer Count Value: Hardwired to 0s.
00h
Datasheet
179
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.9
HDR2—Header Type (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Eh
80h
RO
8 bits
Size:
This register contains the Header Type of the IGD.
Bit
Access &
Default
Description
7
RO
1b
Multi Function Status (MFunc): This bit indicates if the device is a Multi-
Function Device. The Value of this register is determined by Device 0, offset 54h,
DEVEN[4]. If Device 0 DEVEN[4] is set, the Mfunc bit is also set.
6:0
RO
Header Code (H): This is a 7-bit value that indicates the Header Code for the
00h
IGD. This code has the value 00h, indicating a type 0 configuration space format.
9.1.10
MMADR—Memory Mapped Range Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
10h
00000000h
RO, R/W
32 bits
Size:
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits [31:19].
Bit
31:19
18:4
3
Access &
Default
Description
R/W
0000h
Memory Base Address: Set by the OS, these bits correspond to address
signals [31:19].
RO
0000h
Address Mask: Hardwired to 0s to indicate 512 KB address range.
Prefetchable Memory: Hardwired to 0 to prevent prefetching.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / IO Space: Hardwired to 0 to indicate memory space.
RO
0b
2:1
0
RO
00b
RO
0b
180
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.11
IOBAR—I/O Base Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
14h
00000001h
RO, R/W
32 bits
Size:
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O Base to be located anywhere in 16 bit I/O address space. Bits 2:1
are fixed and return 0s; bit 0 is hardwired to a 1 indicating that 8 bytes of I/O space are decoded.
Access to the 8Bs of I/O space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set.
Access is disallowed in PM states D1–D3 or if IO Enable is clear or if Device 2 is turned off.
Note that access to this I/O BAR is independent of VGA functionality within Device 2. Also note
that this mechanism in available only through function 0 of Device 2 and is not duplicated in
Function 1.
If accesses to this I/O bar are allowed, the GMCH claims all 8, 16, or 32 bit I/O cycles from the
processor that falls within the 8B claimed.
Bit
Access &
Default
Description
31:16
15:3
Reserved
R/W
IO Base Address: Set by the OS, these bits correspond to address signals
0000h
[15:3].
2:1
0
RO
00b
Memory Type: Hardwired to 0s to indicate 32-bit address.
RO
1b
Memory / I/O Space: Hardwired to 1 to indicate I/O space.
Datasheet
181
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.12
GMADR—Graphics Memory Range Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
18h
00000008h
RO, R/W/L
16 bits
Size:
IGD graphics memory base address is specified in this register.
Bit
31:28
27
Access &
Default
Description
R/W
0h
Memory Base Address: Set by the OS, these bits correspond to address
signals [31:28].
R/W/L
0b
256-MB Address Mask: This bit is either part of the Memory Base Address
(R/W) or part of the Address Mask (RO), depending on the value of MSAC[1].
See MSAC (Dev 2, Func 0, offset 62) for details.
26:4
3
RO
000000h
Address Mask: Hardwired to 0s to indicate at least 128-MB address range
Prefetchable Memory: Hardwired to 1 to enable prefetching
Memory Type: Hardwired to 0 to indicate 32-bit address.
RO
1b
2:1
0
RO
00b
RO
0b
Memory/IO Space: Hardwired to 0 to indicate memory space.
182
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.13
GTTADR—Graphics Translation Table Range Address
(D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
1Ch
00000000h
RO, R/W
32 bits
Size:
This register requests allocation for Graphics Translation Table Range. The allocation is for
256 KB and the base address is defined by bits [31:18].
Bit
31:18
17:4
3
Access &
Default
Description
R/W
0000h
Memory Base Address: Set by the OS, these bits correspond to address
signals [31:18].
RO
0000h
Address Mask: Hardwired to 0s to indicate 256-KB address range.
Prefetchable Memory: Hardwired to 0 to prevent prefetching.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory/IO Space: Hardwired to 0 to indicate memory space.
RO
0b
2:1
0
RO
00b
RO
0b
9.1.14
SVID2—Subsystem Vendor Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Ch
0000h
R/WO
16 bits
Size:
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem Vendor ID. This value is used to identify the vendor of the
subsystem. This register should be programmed by BIOS during boot-up. Once
written, this register becomes Read-Only. This register can only be cleared by a
Reset.
Datasheet
183
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.15
SID2—Subsystem Identification (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Eh
0000h
R/WO
16 bits
Size:
Bit
Access &
Default
Description
15:0
R/WO
0000h
Subsystem Identification: This value is used to identify a particular subsystem.
This field should be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This register can only be cleared by a Reset.
9.1.16
ROMADR—Video BIOS ROM Base Address (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
30h
00000000h
RO
Size:
32 bits
The IGD does not use a separate BIOS ROM; therefore, this register is hardwired to 0s.
Bit
Access &
Default
Description
31:18
17:11
RO
0000h
ROM Base Address: Hardwired to 0s.
RO
Address Mask: Hardwired to 0s to indicate 256-KB address range.
00h
10:1
0
Reserved
RO
0b
ROM BIOS Enable: 0 = ROM not accessible.
184
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.17
CAPPOINT—Capabilities Pointer (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
34h
D0h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
D0h
Capabilities Pointer Value: This field contains an offset into the function’s PCI
configuration space for the first item in the New Capabilities Linked List; the
Power Management Capabilities ID registers at address D0h.
9.1.18
INTRLINE—Interrupt Line (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Ch
00h
R/W
8 bits
Size:
Bit
Access &
Default
Description
7:0
R/W
00h
Interrupt Connection: This field is used to communicate interrupt line routing
information. POST software writes the routing information into this register as it
initializes and configures the system. The value in this register indicates which
input of the system interrupt controller that the device’s interrupt pin is connected
to.
9.1.19
INTRPIN—Interrupt Pin (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Dh
01h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Interrupt Pin: As a device that only has interrupts associated with a single
01h
function, the IGD specifies INTA# as its interrupt pin.
01h = INTA#.
Datasheet
185
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.20
MINGNT—Minimum Grant (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Eh
00h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Minimum Grant Value: The IGD does not burst as a PCI compliant master.
00h
9.1.21
MAXLAT—Maximum Latency (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Fh
00h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Maximum Latency Value: The IGD has no specific requirements for how often it
00h
needs to access the PCI bus.
9.1.22
9.1.23
MCAPPTR—Mirror of Dev0 Capability Pointer (D2:F0)
(Mirrored_D0_34)
PCI Device:
Function:
2
0
Address Offset:
Size:
44h
8 bits
This register is a Read-Only copy of Device 0, Offset 34h register.
MCAPID—Mirror of Dev0 Capability Identification (D2:F0)
(Mirrored_D0_E0)
PCI Device:
Function:
2
0
Address Offset:
Size:
48h
72 bits
This register is a Read-Only copy of Device 0, Offset E0h register.
186
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.24
9.1.25
9.1.26
MGGC—Mirror of Dev0 GMCH Graphics Control (D2:F0)
(Mirrored_D0_52)
PCI Device:
Function:
2
0
Address Offset:
Size:
52h
16 bits
This register is a Read-Only copy of Device 0, Offset 52h register.
MDEVENdev0f0—Mirror of Dev0 Device Enable (D2:F0)
(Mirrored_D0_54)
PCI Device:
Function:
2
0
Address Offset:
Size:
54h
32 bits
This register is a Read-Only copy of Device 0, Offset 54h register.
BSM—Base of Stolen Memory (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
5Ch
07800000h
RO
Size:
32 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the
top of low used DRAM, GMCH claims 1 to 64 MBs of DRAM for internal graphics, if enabled.
Bit
Access &
Default
Description
31:20
RO
078h
Base of Stolen Memory (BSM): This register contains bits 31:20 of the base
address of stolen DRAM memory. The host interface determines the base of
Graphics Stolen memory by subtracting the graphics stolen memory size from
TOLUD. See Device 0 TOLUD for more explanation.
19:0
Reserved
Datasheet
187
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.27
MSAC—Multi Size Aperture Control (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
62h
00h
R/W
8 bits
Size:
This register determines the size of the graphics memory aperture in function 0 and in the trusted
space. By default, the aperture size is 256 MB (bit 27 read only). If bit 1 is set to a 1, then the
aperture size is limited to 128 MB. Only the system BIOS will write this register based on pre-
boot address allocation efforts, but the graphics may read this register to determine the correct
aperture size. System BIOS needs to save this value on boot so that it can reset it correctly during
S3 resume.
Bit
Access &
Default
Description
7:4
R/W
0h
Scratch Bits Only. These bits have no physical effect on hardware.
3:2
1
Reserved
R/W
0b
256-MB Aperture Disable
0 = Bit 27 of GMADR and the equivalent trusted memory aperture is read-only,
allowing 256 MB of address space to be mapped.
1 = Bit 27 of GMADR and the equivalent trusted memory aperture is read-write,
limiting the address space to 128 MB.
0
Reserved
9.1.28
PMCAPID—Power Management Capabilities ID (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
D0h
0001h
RO
Size:
16 bits
Bit
15:8
7:0
Access &
Description
Default
RO
00h
NEXT_PTR: This field contains a pointer to next item in capabilities list. This is
the final capability in the list and must be set to 00h.
RO
CAP_ID: SIG defines this ID is 01h for power management.
01h
188
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.29
PMCAP—Power Management Capabilities (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
D2h
0022h
RO
Size:
16 bits
Bit
15:11
10
Access &
Description
Default
RO
00h
PME Support: This field indicates the power states in which the IGD may assert
PME#. Hardwired to 0 to indicate that the IGD does not assert the PME# signal.
RO
0b
D2: The D2 power management state is not supported. This bit is hardwired to 0.
9
RO
0b
D1: Hardwired to 0 to indicate that the D1 power management state is not
supported.
8:6
5
Reserved
RO
1b
Device Specific Initialization (DSI): Hardwired to 1 to indicate that special
initialization of the IGD is required before generic class device driver is to use it.
4
3
RO
0b
Auxiliary Power Source: Hardwired to 0.
RO
0b
PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation.
2:0
RO
010b
Version: Hardwired to 010b to indicate that there are 4 bytes of power
management registers implemented and that this device complies with revision
1.1 of the PCI Power Management Interface Specification
Datasheet
189
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.30
PMCS—Power Management Control/Status (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
D4h
0000h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15
RO
0b
PME_Status: This bit is 0 to indicate that IGD does not support PME# generation
from D3 (cold).
14:9
8
Reserved
RO
0b
PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
7:2
1:0
Reserved
R/W
00b
Power State: This field indicates the current power state of the IGD and can be
used to set the IGD into a new power state. If software attempts to write an
unsupported state to this field, the write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values. Behavior of the graphics controller in supported states is detailed in the
power management section.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
190
Datasheet
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.31
SWSMI—Software SMI (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
E0h
0000h
R/W
16 bits
Size:
As long as there is the potential that DVO port legacy drivers exist that expect this register at this
address, Dev2, F0, address E0h–E1h must be reserved for this register.
Bit
15:8
7:1
0
Access &
Default
Description
R/W
00h
SW scratch bits
R/W
00h
Software Flag: This field is used to indicate caller and SMI function desired, as
well as return result.
R/W
0b
GMCH Software SMI Event: When Set, this bit will trigger an SMI. Software
must write a 0 to clear this bit
9.1.32
ASLE—System Display Event Register (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
E4h
00000000h
R/W
Size:
32 bits
Byte, Word, or Double Word PCI configuration cycles can access this register.
Bit
Access &
Default
Description
31:8
R/W
00h
ASLE Scratch Trigger 3: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
23:16
15:8
7:0
R/W
00h
ASLE Scratch Trigger 2: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
R/W
00h
ASLE Scratch Trigger 1: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
R/W
00h
ASLE Scratch Trigger 0: When written, this scratch byte triggers an interrupt
when IER bit 0 is enabled and IMR bit 0 is unmasked. If written as part of a 16-
bit or 32-bit write, only one interrupt is generated in common.
Datasheet
191
Integrated Graphics Device Registers (D2:F0)
(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)
R
9.1.33
ASLS—ASL Storage (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
2
FCh
00000000h
R/W
Size:
32 bits
This SW scratch register only needs to be read/write accessible. The exact bit register usage must
be worked out in common between System BIOS and driver software, but storage for
switching/indicating up to 6 devices is possible with this amount. For each device, the ASL
control method requires two bits for _DOD (BIOS detectable yes or no, VGA/Non VGA); one bit
for _DGS (enable/disable requested) and two bits for _DCS (enabled now/disabled now,
connected or not).
Bit
Access &
Default
Description
31:0
R/W
RW according to a software controlled usage to support device switching
00000000 h
192
Datasheet
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10 Device 2 Function 1 (D2:F1)
Configuration Registers
(Intel® 82915G/82915GV/82915GL/
82910GL Only)
Table 10-1. Device 2 Function 1 Register Address Map Summary
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
00–01h
02–03h
04–05h
06–07h
08h
VID2
DID2
Vendor Identification
8086h
2780h
0000h
0090h
RO
RO
Device Identification
PCI Command
PCICMD2
PCISTS2
RID2
RO, R/W
RO
PCI Status
Revision Identification
See register
description
RO
09–0Bh
0Ch
CC
CLS
Class Code Register
Cache Line Size
03800h
00h
RO
RO
0Dh
MLT2
HDR2
—
Master Latency Timer
Header Type Register
Reserved
00h
RO
0Eh
80h
RO
0Fh
—
—
10–13h
14–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
MMADR
—
Memory Mapped Range Address
Reserved
00000000h
—
RO, R/W
—
SVID2
SID2
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
Capabilities Pointer
Reserved
0000h
0000h
00000000h
D0h
R/WO
R/WO
RO
ROMADR
CAPPOINT
—
RO
35–3Dh
3Eh
—
—
MINGNT
MAXLAT
—
Minimum Grant Register
Maximum Latency
00h
RO
3Fh
00h
RO
40–43h
44h
Reserved
—
—
MCAPPTR
—
Mirror of Dev0 Capability Pointer
Reserved
45–47h
—
—
Datasheet
193
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
48–50h
51h
MCAPID
Mirror of Dev0 Capability Identification
Reserved
—
MGGC
MDEVENdev0f0
—
—
—
52–53h
54–57h
58–5Bh
5C–5Fh
60–CFh
D0–D1h
D2–D3h
D4–D5h
D6–DFh
E0–E1h
E2–FBh
FC–FFh
Mirror of Dev0 GMCH Graphics Control
Mirror of Dev0 Device Enable
Reserved
—
07800000h
0000h
0001h
0022h
0000h
—
—
RO
BSM
Base of Stolen Memory Register
Reserved
—
—
PMCAPID
PMCAP
PMCS
—
Power Management Capabilities ID
Power Management Capabilities
Power Management Control/Status
Reserved
RO
RO
RO, R/W
—
SWSMI
—
Software SMI
0000h
—
R/W
—
Reserved
ASLS
ASL Storage
00000000h
R/W
10.1
Device 2 Function 1 Configuration Register Details
(D2:F1)
10.1.1
VID2—Vendor Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
00h
8086h
RO
Size:
16 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.2
DID2—Device Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
02h
2782h
RO
Size:
16 bits
This register is unique in Device 2, Function 1 (the Device 2, Function 0 DID is separate). This
difference in Device ID is necessary for allowing distinct Plug and Play enumeration of function 1
when both function 0 and function 1 have the same class code.
194
Datasheet
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.3
PCICMD2—PCI Command (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
04h
0000h
RO, R/W
16 bits
Size:
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
Access &
Default
Description
15:10
9
Reserved
RO
0b
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
8
7
6
RO
0b
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
RO
0b
Address/Data Stepping Enable (ADSTEP): Not Implemented. Hardwired to 0.
RO
0b
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0. Since the IGD
belongs to the category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error that it detects
and continues with normal operation.
5
4
3
2
RO
0b
VGA Palette Snoop Enable (VGASNOOP): This bit is hardwired to 0 to disable
snooping.
RO
0b
Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does
not support memory write and invalidate commands.
RO
0b
Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD ignores Special
cycles.
R/W
0b
Bus Master Enable (BME):
0 = Disable
1 = Enable the IGD to function as a PCI compliant master.
1
0
R/W
0b
Memory Access Enable (MAE): This bit controls the IGD’s response to memory
space accesses.
0 = Disable.
1 = Enable.
R/W
0b
I/O Access Enable (IOAE): This bit controls the IGD’s response to I/O space
accesses.
0 = Disable.
1 = Enable.
Datasheet
195
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.4
PCISTS2—PCI Status (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
06h
0090h
RO
Size:
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and
PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the
IGD.
Bit
15
14
13
12
11
10:9
8
Access &
Default
Description
RO
0b
Detected Parity Error (DPE): Since the IGD does not detect parity; this bit is
always hardwired to 0.
RO
0b
Signaled System Error (SSE): The IGD never asserts SERR#; therefore, this
bit is hardwired to 0.
RO
0b
Received Master Abort Status (RMAS): The IGD never gets a Master Abort,
therefore this bit is hardwired to 0.
RO
0b
Received Target Abort Status (RTAS): The IGD never gets a Target Abort,
therefore this bit is hardwired to 0.
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use
target abort semantics.
RO
00b
DEVSEL Timing (DEVT): These bits are hardwired to 00.
RO
0b
Master Data Parity Error Detected (DPD): Since Parity Error Response is
hardwired to disabled (and the IGD does not do any parity detection), this bit is
hardwired to 0.
7
6
5
4
RO
1b
Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back
when the transactions are not to the same agent.
RO
0b
User Defined Format (UDF). Hardwired to 0.
66 MHz PCI Capable (66C). Hardwired to 0.
RO
0b
RO
1b
Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h
provides an offset into the function’s PCI Configuration Space containing a
pointer to the location of the first item in the list.
3
RO
0b
Interrupt Status: Hardwired to 0.
2:0
Reserved
196
Datasheet
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.5
10.1.6
RID2—Revision Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
08h
See description below
RO
Size:
8 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
CC—Class Code Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
09h
038000h
RO
Size:
24 bits
This register contains the device programming interface information related to the Sub-Class
Code and Base Class Code definition for the IGD. This register also contains the Base Class Code
and the function sub-class in relation to the Base Class Code.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC): This is an 8-bit value that indicates the base class
03h
code for the GMCH.
03h = Display Controller.
15:8
7:0
RO
80h
Sub-Class Code (SUBCC)
80h = Non VGA
RO
00h
Programming Interface (PI)
00h = Hardwired as a Display controller.
10.1.7
CLS—Cache Line Size (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Ch
00h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
Datasheet
197
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.8
10.1.9
MLT2—Master Latency Timer (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Dh
00h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
HDR2—Header Type Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
0Eh
80h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.10 MMADR—Memory Mapped Range Address (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
10h
00000000h
RO, R/W
32 bits
Size:
This register requests allocation for the IGD registers and instruction ports. The allocation is for
512 KB and the base address is defined by bits [31:19].
Bit
31:19
18:4
3
Access &
Default
Description
R/W
0000h
Memory Base Address: Set by the OS, these bits correspond to address
signals [31:19].
RO
0000h
Address Mask: Hardwired to 0s to indicate 512-KB address range.
Prefetchable Memory: Hardwired to 0 to prevent prefetching.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / IO Space: Hardwired to 0 to indicate memory space.
RO
0b
2:1
0
RO
00b
RO
0b
198
Datasheet
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
R
10.1.11 SVID2—Subsystem Vendor Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Ch
0000h
R/WO
16 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.12 SID2—Subsystem Identification (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
2Eh
0000h
R/WO
16 bits
Size:
This register is a Read Only copy of Device 2, Function 0.
10.1.13 ROMADR—Video BIOS ROM Base Address (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
30h
00000000h
RO
Size:
32 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.14 CAPPOINT—Capabilities Pointer (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
34h
D0h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
Datasheet
199
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
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10.1.15 MINGNT—Minimum Grant Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Eh
00h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.16 MAXLAT—Maximum Latency (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
3Fh
00h
RO
8 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.17 MCAPPTR—Mirror of Dev0 Capability Pointer (D2:F1)
(Mirrored_D0_34)
PCI Device:
Function:
2
1
Address Offset:
Size:
44h
8 bits
This register is a Read Only copy of Device 0, Offset 34h register.
10.1.18 MCAPID—Mirror of Dev0 Capability Identification (D2:F1)
(Mirrored_D0_E0)
PCI Device:
Function:
2
1
Address Offset:
Size:
48h
72 bits
This register is a Read-Only copy of Device 0, Offset E0h register.
10.1.19 MGGC—Mirror of Dev0 GMCH Graphics Control (D2:F1)
(Mirrored_D0_52)
PCI Device:
Address Offset:
Size:
2
52h
16 bits
This register is a Read Only copy of Device 0, Offset 52h register.
200
Datasheet
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
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10.1.20 MDEVENdev0f0—Mirror of Dev0 Device Enable (D2:F1)
(Mirrored_D0_54)
PCI Device:
Function:
2
1
Address Offset:
Size:
54h
32 bits
This register is a Read Only copy of Device 0, Offset 54h register.
10.1.21 BSM—Base of Stolen Memory Register (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
5Ch
07800000h
RO
Size:
32 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.22 PMCAPID—Power Management Capabilities ID (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
D0h
0001h
RO
Size:
16 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
10.1.23 PMCAP—Power Management Capabilities (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
D2h
0022h
RO
Size:
16 bits
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
Datasheet
201
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
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10.1.24 PMCS—Power Management Control/Status (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
D4h
0000h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15
RO
0 b
PME_Status: This bit is 0 to indicate that IGD does not support PME# generation
from D3 (cold).
14:9
8
Reserved
RO
0 b
PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
7:2
1:0
Reserved
R/W
00 b
Power State: This field indicates the current power state of the IGD and can be
used to set the IGD into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values. Behavior of the graphics controller in supported states is detailed in the
power management section.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
10.1.25 SWSMI—Software SMI (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
E0h
0000h
R/W
16 bits
Size:
This register is a copy of Device 2, Function 0. It has the same Read, Write attributes as D2:F0. It
is implemented as common hardware with two access addresses.
202
Datasheet
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
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10.1.26 ASLS—ASL Storage (D2:F1)
PCI Device:
Address Offset:
Default Value:
Access:
2
FCh
00000000h
R/W
Size:
32 bits
This software scratch register only needs to be read/write accessible. The exact bit register usage
must be worked out in common between System BIOS and driver software, but storage for
switching/indicating up to 6 devices is possible with this amount. For each device, the ASL
control method with require two bits for _DOD (BIOS detectable yes or no, VGA/NonVGA), one
bit for _DGS (enable/disable requested), and two bits for _DCS (enabled now/disabled now,
connected or not).
Bit
Access &
Default
Description
31:0
R/W
R/W according to a software controlled usage to support device switching
00000000 h
Datasheet
203
Device 2 Function 1 (D2:F1) Configuration Registers
(Intel® 82915G/82915GV/82915GL/ 82910GL Only)
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10.2
Device 2 – PCI I/O Registers
The following are not PCI configurations registers; they are I/O registers.
10.2.1
MMIO_INDEX—MMIO Address Register
I/O Address:
Size:
IOBAR + 0h
32 bits
MMIO_INDEX: A 32 bit I/O write to this port loads the offset of the memory-mapped I/O
(MMIO) register that needs to be accessed. An I/O Read returns the current value of this register.
An 8/16-bit I/O write to this register is completed by the GMCH but does not update this register.
This mechanism to access internal graphics MMIO registers must not be used to access VGA I/O
registers that are mapped through the MMIO space. VGA registers must be accessed directly
through the dedicated VGA IO ports.
Bit
31:2
1:0
Access &
Default
Description
R/W
00000000 h
Register Offset: This field selects any one of the DWord registers within the
MMIO register space of Device 2.
Reserved
10.2.2
MMIO_DATA—MMIO Data Register
I/O Address:
Size:
IOBAR + 4h
32 bits
MMIO_DATA: A 32 bit I/O write to this port is re-directed to the MMIO register pointed to by
the MMIO-index register. A 32 bit I/O read to this port is re-directed to the MMIO register
pointed to by the MMIO-index register. 8 or 16 bit I/O writes are completed by the GMCH and
may have un-intended side effects; hence, they must not be used to access the data port. 8 or 16
bit I/O reads are completed normally.
Bit
Access &
Default
Description
31:0
R/W
MMIO Data Window
00000000 h
§
204
Datasheet
System Address Map
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11 System Address Map
The (G)MCH supports 4 GB of addressable memory space (see Figure 11-1) and 64 KB+3 bytes
of addressable I/O space. A programmable memory address space under the 1-MB region is
divided into regions that can be individually controlled with programmable attributes such as
disable, read/write, write only, or read only. This section focuses on how the memory space is
partitioned and what the separate memory regions are used for. I/O address space has simpler
mapping and is explained near the end of this section.
Note: Address mapping information for the Integrated Graphics Device applies to the
82915G/82915GV/82915GL/82910GL GMCH only. The 82915P/82915PL MCH does not have
an IGD.
Note: Address mapping information for the PCI Express Device applies to the
82915G/82915P/82915PL (G)MCH only. The 82915GV/82915GL/82910GL GMCH does not
support PCI Express.
Addressing of memory ranges larger than 4 GB is not supported. The HREQ[4:3] FSB pins are
decoded to determine whether the access is above or below 4 GB.
The (G)MCH does not support the PCI Dual Address Cycle (DAC) Mechanism, PCI Express
64-bit prefetchable memory transactions, or any other addressing mechanism that allows
addressing of greater than 4 GB on either the DMI or PCI Express interface. The (G)MCH does
not limit system memory space in hardware. There is no hardware lock to stop someone from
inserting more memory than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the
DMI. The exception to this rule is VGA ranges that may be mapped to PCI Express, DMI, or to
the internal graphics device (IGD). In the absence of more specific references, cycle descriptions
referencing PCI should be interpreted as the DMI/PCI, while cycle descriptions referencing PCI
Express or IGD are related to the PCI Express bus or the internal graphics device respectively.
The (G)MCH does not remap APIC or any other memory spaces above TOLUD (Top of Low
Usable DRAM). The TOLUD register is set to the appropriate value by BIOS.
The Address Map includes a number of programmable ranges:
• Device 0
⎯ EPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous channel
using time based weighted round robin arbitration. (4-KB window)
⎯ MCHBAR – Memory mapped range for internal (G)MCH registers. For example,
memory buffer register controls. (16-KB window)
⎯ PCIEXBAR – Flat memory-mapped address space to access device configuration
registers. This mechanism can be used to access PCI configuration space (0h–FFh) and
Extended configuration space (100h–FFFh) for PCI Express devices. This enhanced
configuration access mechanism is defined in the PCI Express specification. (256-MB
window)
⎯ DMIBAR –This window is used to access registers associated with the (G)MCH/ICH6
(DMI) register memory range. (4-KB window)
Datasheet
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⎯ IFPBAR – Any write to this window will trigger a flush of the (G)MCH’s Global Write
Buffer to let software guarantee coherency between writes from an isochronous agent
and writes from the processor (4-KB window).
⎯ GGC – 82915G/82915GV/82910GL GMCH graphics control register. Used to select the
amount of main memory that is pre-allocated to support the internal graphics device in
VGA (non-linear) and Native (linear) modes (0–64-MB options).
• Device 1: Function 0:
⎯ MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
⎯ PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
⎯ IOBASE1/IOLIMIT1 – PCI Express port I/O access window.
• Device 2: Function 0 (82915G/82915GV/82915GL/82910GL GMCH only)
⎯ MMADR – IGD registers and internal graphics instruction port. (512-KB window)
⎯ IOBAR – I/O access window for the GMCH internal graphics. Through this window
address/data register pair, using I/O semantics, the IGD and internal graphics instruction
port registers can be accessed. Note, this allows accessing the same registers as
MMADR. In addition, the IOBAR can be used to issue writes to the GTTADR table.
⎯ GMADR – Internal graphics translation window. (256-MB window)
⎯ GTTADR – Internal graphics translation table location. (256-KB window). Note that the
PGTBL_CTL register (MMIO 2020) indicates the physical address base which is 4 KB
aligned.
• Device 2: Function 1 (82915G/82915GV/82915GL/82910GL GMCH only)
⎯ MMADR – Function 1 IGD registers and internal graphics instruction port. (512-KB
window)
The rules for the above programmable ranges are:
• ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or system
designer’s responsibility to limit memory population so that adequate PCI, PCI Express, High
BIOS, PCI Express Memory Mapped space, and APIC memory space can be allocated.
• In the case of overlapping ranges with memory, the memory decode will be given priority.
• There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges.
• Accesses to overlapped ranges may produce indeterminate results.
• The only peer-to-peer cycles allowed below the top of memory (register TOLUD) are DMI to
PCI Express VGA range writes. Note that peer to peer cycles to the Internal Graphics VGA
range are not supported.
Figure 11-1 shows the system memory address map in a simplified form.
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Figure 11-1. System Address Ranges
4 GB
Device 0
Bars
(EPBAR,
MCHBAR,
PCIEXBAR,
DMIBAR)
Device 1
Bars
(MBASE1/
MLIMIT1,
PMBASE1/
PMLIMIT1)
Device 21
Bars
(MMADR,
GMADR,
GTTADR)
PCI Memory
Address Range
(Subtractively
decoded to DMI)
TOLUD
Device 0
GGC
(Graphics
Stolen
Independently Programmable
Non-Overlapping Windows
Main Memory
Address Range
Memory)
1 MB
Legacy Address
Range
0
NOTES:
1. Device 2 is not on the 82915P/82915PL MCH.
2. Device 1 is not on the 82915GV/82910GL/82915GL GMCH.
11.1
Legacy Address Range
This area is divided into the following address regions:
• 0 – 640 KB: DOS Area
• 640 – 768 KB: Legacy Video Buffer Area
• 768 – 896 KB in 16-KB sections (total of 8 sections): Expansion Area
• 896 – 960 KB in 16-KB sections (total of 4 sections): Extended System BIOS Area
• 960-KB – 1-MB Memory: System BIOS Area
Datasheet
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System Address Map
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Figure 11-2. Microsoft MS-DOS* Legacy Address Range
1MB
000F_FFFFh
000F_0000h
000E_FFFFh
000E_0000h
000D_FFFFh
System BIOS (Upper)
64KB
960KB
896KB
Extended System BIOS (Lower)
64KB (16KBx4)
Expansion Area
128KB (16KBx8)
000C_0000h
000B_FFFFh
768KB
640KB
Legacy Video Area
(SMM Memory)
128KB
000A_0000h
0009_FFFFh
DOS Area
0000_0000h
11.1.1
11.1.2
DOS Range (0h – 9_FFFFh)
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main
memory controlled by the (G)MCH.
Legacy Video Area (A_0000h–B_FFFFh)
The legacy 128-KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh) can be
mapped to IGD, to PCI Express, and/or to the DMI. The appropriate mapping is programmable.
Based on the programming, priority for VGA mapping is constant. The (G)MCH always decodes
internally mapped devices first. Internal to the 82915G/82915GV/82915GL/82910GL GMCH,
decode precedence is always given to the IGD. The (G)MCH always positively decodes internally
mapped devices, namely the IGD (82915G/82915GV/82915GL/82910GL only) and PCI Express.
Subsequent decoding of regions mapped to PCI Express or the DMI depends on the
programming. This region is also the default for SMM space.
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Compatible SMRAM Address Range (A_0000h–B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range are routed
to physical system DRAM at 000A 0000h–000B FFFFh. Non-SMM-mode processor accesses to
this range are considered to be to the Video Buffer Area as described above. PCI Express and
DMI originated cycles to enabled SMM space are not allowed and are considered to be to the
Video Buffer Area if IGD (82915G/82915GV/82915GL/82910GL GMCH only) is not enabled as
the VGA device. PCI Express and DMI initiated cycles are attempted as peer cycles, and will
master abort on PCI if no external VGA device claims them.
Monochrome Adapter (MDA) Range (B_0000h–B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the
system. Accesses in the standard VGA range are forwarded to IGD, PCI Express, or the DMI
(depending on the programming of the on-chip registers). Since the monochrome adapter may be
mapped to any one of these devices, the (G)MCH must decode cycles in the MDA range
(000B_0000h – 000B_7FFFh) and forward either to IGD, PCI Express, or the DMI. In addition to
the memory range B0000h to B7FFFh, the (G)MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h,
3B9h, 3BAh and 3BFh and forwards them to the either IGD, PCI Express, and/or the DMI.
11.1.3
Expansion Area (C_0000h–D_FFFFh)
This 128-KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight, 16-KB
segments. Each segment can be assigned one of four read/write states: read only, write only,
read/write, or disabled. Typically, these blocks are mapped through the (G)MCH and are
subtractively decoded to ISA space. Memory that is disabled is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 11-1. Expansion Area Memory Segments
Memory Segments
Attributes
Comments
0C0000h–0C3FFFh
0C4000h–0C7FFFh
0C8000h–0CBFFFh
0CC000h –0CFFFFh
0D0000h–0D3FFFh
0D4000h–0D7FFFh
0D8000h–0DBFFFh
0DC000h–0DFFFFh
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Datasheet
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11.1.4
Extended System BIOS Area (E_0000h–E_FFFFh)
This 64-KB area (000E_0000h – 000E_FFFFh) is divided into four, 16-KB segments. Each
segment can be assigned independent read and write attributes so it can be mapped either to main
DRAM or to the DMI. Typically, this area is used for RAM or ROM. Memory segments that are
disabled are not remapped elsewhere.
Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 11-2. Extended System BIOS Area Memory Segments
Memory Segments
Attributes
Comments
0E0000h–0E3FFFh
0E4000h–0E7FFFh
0E8000h–0EBFFFh
0EC000h–0EFFFFh
W/R
W/R
W/R
W/R
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Extension
11.1.5
System BIOS Area (F_0000h–F_FFFFh)
This area is a single, 64-KB segment (000F_0000h – 000F_FFFFh). This segment can be
assigned read and write attributes. It is by default (after reset) read/write disabled and cycles are
forwarded to the DMI. By programming the read/write attributes, the (G)MCH can “shadow”
BIOS into main memory. When disabled, this segment is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to main memory.
Table 11-3. System BIOS Area Memory Segments
Memory Segments
Attributes
WE RE
Comments
0F0000h–0FFFFFh
BIOS Area
11.1.6
Programmable Attribute Map (PAM) Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM memory area.
The (G)MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be IWB cycles
targeting DMI.
However, DMI becomes the default target for processor and DMI originated accesses to disabled
segments of the PAM region. If the MTRRs covering the PAM regions are set to WB or RC, it is
possible to get IWB cycles targeting DMI. This may occur for DMI-originated cycles to disabled
PAM regions.
Warning: For example, assume that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read targeting the
PAM region. A snoop is generated on the FSB and the result is an IWB. Since the PAM region is
“Read Disabled”, the default target for the Memory Read becomes DMI. The IWB associated
with this cycle will cause the (G)MCH to hang.
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11.2
Main Memory Address Range (1 MB to TOLUD)
This address range extends from 1 MB to the top of physical memory that is permitted to be
accessible by the (G)MCH (as programmed by in the TOLUD register). All accesses to addresses
within this range will be forwarded by the (G)MCH to the main memory unless they fall into the
optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory.
The (G)MCH provides a maximum main memory address decode space of 4 GB. The (G)MCH
does not remap APIC or PCI Express memory space. This means that as the amount of physical
memory populated in the system reaches 4 GB, there will be physical memory that exists, yet non-
addressable; therefore, this memory is unusable by the system.
The (G)MCH does not limit main memory address space in hardware.
Figure 11-3. Main Memory Address Range
4 GB Maximum
FFFF_FFFFh
Flash
APIC
Contains
programmable
windows, ICH6/PCI
ranges.
PCI Memory Range
TOLUD
IGD (1–32 MB, optional)
TSEG (1 MB / 2 MB /
8 MB, optional)
Main Memory
0100_000h
00F0_000h
16 MB
15 MB
ISA Hole (optional)
Main Memory
0010_000h
0h
1 MB
DOS Compatibility
Memory
0 MB
Main_Mem_Addr_G-P_Only
11.2.1
ISA Hole (15 MB–16 MB)
BIOS can create a hole at 15 MB–16 MB. Accesses within this hole are forwarded to the DMI.
The range of physical main memory disabled by opening the hole is not remapped to the top of
the memory; that physical main memory space is not accessible. This 15 MB–16 MB hole is an
optionally enabled ISA hole.
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11.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory, which is
at the top of physical memory. SMM-mode processor accesses to enabled TSEG access the
physical DRAM at the same address. Non-processor originated accesses are not allowed to SMM
space. PCI Express, DMI, and Internal Graphics originated cycles to enabled SMM space are
handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for
writes. When the extended SMRAM space is enabled, processor accesses to the TSEG range
without SMM attribute or without WB attribute are also forwarded to memory as invalid accesses.
Non-SMM-mode write-back cycles that target TSEG space are completed to main memory for
cache coherency. When SMM is enabled, the maximum amount of memory available to the
system is equal to the amount of physical main memory minus the value in the TSEG register
which is fixed at 1 MB, 2 MB or 8 MB.
11.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within
system memory address range (< TOLUD) are created for SMM-mode and legacy VGA graphics
compatibility. It is the responsibility of BIOS to properly initialize these regions. Table 11-4
details the location and attributes of the regions.
Table 11-4. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB TSEG
Memory Segments
Attributes
Comments
0000_0000h – 03DF_FFFFh
03E0_0000h – 03EF_FFFFh
R/W
Available system memory 62 MB
SMM Mode Only -
processor reads
TSEG Address Range and Pre-allocated
memory
03F0_0000h – 03FF_FFFFh
R/W
Pre-allocated Graphics VGA memory.
1 MB (or 4/8/16/32/64 MB) when IGD is enabled.
11.3
PCI Memory Address Range (TOLUD – 4 GB)
This address range, from the top of physical memory to 4 GB (top of addressable memory space
supported by the (G)MCH) is normally mapped via the DMI to PCI. Exceptions to this mapping
include BAR memory mapped regions that include:
• EPBAR, MCHBAR, DMIBAR.
• The second exception to the mapping rule deals with the PCI Express port:
⎯
Addresses decoded to the PCI Express Memory Window defined by the MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1 registers are mapped to PCI Express.
⎯ Addresses decoded to PCI Express configuration space are mapped based on Bus,
Device, and Function number. (PCIEXBAR range).
• The third exception to the mapping rule occurs in an internal graphics configuration (82915G
GMCH only):
⎯ Addresses decoded to the Graphics Memory Range. (GMADR range)
⎯ Addresses decoded to the Graphics Translation Table range (GTTADR range).
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⎯ Addresses decoded to the Memory Mapped Range of the Internal Graphics Device
(MMADR range). There is a MMADR range for device 2 function 0 and a MMADR
range for device 2 function 1. Both ranges are forwarded to the Internal Graphics
Device.
The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap
with APCI Configuration, FSB Interrupt Space and High BIOS Address Range.
Figure 11-4. PCI Memory Address Range
FFFF_FFFFh
4 GB
High BIOS
FFE0_0000h
4 GB – 2 MB
DMI Interface
(subtractively decode)
FEF0_0000h
FEE0_0000h
4 GB – 17 MB
4 GB – 18 MB
FSB Interrupts
Optional HSEG
FEDA_0000h to
FEDB_FFFFh
DMI Interface
(subtractively decode)
FED0_0000h
4 GB – 19 MB
Local (processor)
APIC
FEC8_0000h
FEC0_0000h
I/O APIC
4 GB – 20 MB
DMI Interface
(subtractively decode)
F000_0000h
E000_0000h
4 GB – 256 MB
PCI Express
Configuration Space
Possible address range
(Not guaranteed)
4 GB – 512 MB
Programmable windows,
graphics ranges,
PCI Express* Port
could be here
DMI Interface
(subtractively decode)
TOLUD
PCI_Address_Ranges_G-P-only
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11.3.1
11.3.2
APIC Configuration Space (FEC0_0000h-FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the ICH6
portion of the chipset, but may also exist as stand-alone components.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be
populated in the system. Since it is difficult to relocate an interrupt controller using plug-and-play
software, fixed address decode regions have been allocated for them. Processor accesses to the
default IOAPIC region (FEC0_0000h to FEC7_FFFFh) are always forwarded to DMI.
HSEG (FEDA_0000h–FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to
SMM memory. It is sometimes called the High SMM memory space. SMM-mode processor
accesses to the optionally enabled HSEG are remapped to 000A_0000h – 000B_FFFFh. Non-
SMM-mode processor accesses to enabled HSEG are considered invalid and are terminated
immediately on the FSB. The exceptions to this rule are Non-SMM-mode write-back cycles that
are remapped to SMM space to maintain cache coherency. PCI Express and DMI originated
cycles to enabled SMM space are not allowed. Physical main memory behind the HSEG
transaction address is not remapped and is not accessible. All cacheline writes with WB attribute
or Implicit write backs to the HSEG range are completed to DRAM like an SMM cycle.
11.3.3
11.3.4
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any device on PCI
Express or DMI may issue a memory write to 0FEEx_xxxxh. The (G)MCH will forward this
memory write along with the data to the FSB as an Interrupt Message Transaction. The (G)MCH
terminates the FSB transaction by providing the response and asserting HTRDY#. This memory
write cycle does not go to DRAM.
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI memory address range is reserved for
system BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system
BIOS. The processor begins execution from the High BIOS after reset. This region is mapped to
the DMI so that the upper subset of this region aliases to the 16-MB–256-KB range. The actual
address space required for the BIOS is less than 2 MB, but the minimum processor MTRR range
for this region is 2 MB; thus, that full 2 MB must be considered.
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11.3.5
11.3.6
PCI Express* Configuration Address Space (Intel®
82915G/82915P Only)
A configuration register defines the base address for the 256-MB block of addresses below top of
addressable memory (4 GB) for the configuration space associated with all devices and functions
that are potentially a part of the PCI Express root complex hierarchy. This range will be aligned to
a 256-MB boundary. BIOS must assign this address range such that it will not conflict with any
other address ranges.
PCI Express* Graphics Attach (Intel® 82915G/82915P Only)
The (G)MCH can be programmed to direct memory accesses to the PCI Express interface when
addresses are within either of two programmed ranges specified via registers in the (G)MCH’s
Device 1 configuration space.
• The first range is controlled via the Memory Base Register (MBASE) and Memory Limit
Register (MLIMIT) registers.
• The second range is controlled via the Prefetchable Memory Base (PMBASE) and
Prefetchable Memory Limit (PMLIMIT) registers.
The (G)MCH positively decodes memory accesses to PCI Express memory address space as
defined by the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤
Prefetchable_Memory_Limit_Address
It is essential to support a separate Prefetchable range to apply USWC attribute (from the
processor point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note: The programmable ranges are used to allocate memory address space for any PCI Express devices
sitting on PCI Express that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In other
words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the
memory base/limit and prefetchable base/limit windows.
11.3.7
AGP DRAM Graphics Aperture
Unlike AGP4x, PCI Express has no concept of aperture for PCI Express devices. As a result,
there is no need to translate addresses from PCI Express. Therefore, the (G)MCH has no
APBASE and APSIZE registers.
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11.3.8
Graphics Memory Address Ranges (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only)
The GMCH can be programmed to direct memory accesses to IGD when addresses are within any
of three programmable ranges.
• The Memory Map Base Register (MMADR) is used to access graphics control registers.
• The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory
allocated via the graphics translation table.
• The Graphics Translation Table Base Register (GTTADR) is used to access the translation
table.
Normally these ranges will reside above the Top-of-Main-DRAM and below High BIOS and
APIC address ranges. They normally reside above the top of memory (TOLUD) so that physical
DRAM memory space is not allocate to them.
The memory allocated via the graphics translation table is a Prefetchable range to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used by the
processor for write combining.
11.4
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM RAM). The
(G)MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of
Memory Segment (TSEG). System Management RAM space provides a memory area that is
available for the SMI handlers and code and data storage. This memory resource is normally
hidden from the system OS so that the processor has immediate access to this memory space upon
entry to SMM. (G)MCH provides three SMRAM options:
• Below 1-MB option that supports compatible SMI handlers.
• Above 1-MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. For the
82915G/82915GV/82915GL/82910GL GMCH, the TSEG area lies below IGD stolen
memory.
The above 1-MB solutions require changes to compatible SMRAM handler’s code to properly
execute above 1 MB.
Note: DMI and PCI Express masters are not allowed to access the SMM space.
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11.4.1
11.4.2
Datasheet
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed
SMM space is defined as the range of bus addresses used by the processor to access SMM space.
DRAM SMM space is defined as the range of physical DRAM memory locations containing the
SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible,
High, and TSEG. The Compatible and TSEG SMM space is not remapped; therefore, the
addressed and DRAM SMM space is the same address range. Since the High SMM space is
remapped, the addressed and DRAM SMM space are different address ranges. Note that the High
DRAM space is the same as the Compatible Transaction Address space. The following table
describes three unique address ranges:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
SMM Space Enabled
Transaction Address Space
DRAM Space (DRAM)
Compatible (C)
High (H)
000A_0000h to 000B_FFFFh
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
TSEG (T)
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and
may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to
system main memory, or to any “PCI” devices (including DMI, PCI Express, and graphics
devices). This is a BIOS responsibility.
• Both D_OPEN and D_CLOSE capability must not be enabled at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as
available main memory. This is a BIOS responsibility.
• Any address translated through the internal graphics device’s TLB must not target main
memory from A_0000-F_FFFF.
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11.4.3
SMM Space Combinations
When High SMM is enabled, the Compatible SMM space is effectively disabled. Processor
originated accesses to the Compatible SMM space are forwarded to PCI Express if this VGA
capability is enabled; otherwise, they are forwarded to the DMI. PCI Express and DMI originated
accesses are never allowed to access SMM space.
Table 11-5. SMM Space Table
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Disable
Enable
Disable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Disable
Enable
Enable
Disabled
Disabled
11.4.4
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows
software to write to the SMM ranges without being in SMM mode. BIOS software can use this bit
to initialize SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM
mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI
Express. The SMM software can use this bit to write to video memory while running SMM code
out of DRAM.
Table 11-6. SMM Control Table
G_SMRAME
D_LCK
D_CLS
D_OPEN
Processor in
SMM Mode
SMM Code
Access
SMM Data
Access
0
x
X
X
0
0
1
1
X
0
1
x
0
0
1
0
1
x
x
x
x
0
1
x
1
x
0
1
1
Disable
Disable
Enable
Enable
Enable
Invalid
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Disable
Invalid
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
Disable
Enable
Disable
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11.4.5
11.4.6
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to SMM space.
Processor WB Transaction to an Enabled SMM Address
Space
Processor write-back transactions (HREQ1# = 0) to enabled SMM address space must be written
to the associated SMM DRAM, even though the space is not open and the transaction is not
performed in SMM mode. This ensures SMM space cache coherency when cacheable extended
SMM space is used.
11.4.7
SMM Access through GTT TLB (Intel®
82915G/82915GV/82910GL GMCH Only)
Accesses through GTT TLB address translation to enabled SMM DRAM space are not allowed.
Writes will be routed to memory address 0h with byte enables de-asserted and reads will be
routed to memory address 0h. If a GTT TLB translated address hits enabled SMM DRAM space,
an Invalid Translation Table Entry Flag is reported to BIOS.
PCI Express and DMI originated accesses are never allowed to access SMM space directly or
through the GTT TLB address translation. If a GTT TLB translated address hits enabled SMM
DRAM space, an Invalid Translation Table Entry Flag is reported to BIOS.
PCI Express and DMI write accesses through graphics memory range set up by BIOS will be
snooped. If, when translated, the resulting physical address is to enabled SMM DRAM space, the
request will be remapped to address 0h with de-asserted byte enables.
PCI Express and DMI read accesses to the graphics memory range set up by BIOS are not
supported; therefore, users/systems will have no address translation concerns. PCI Express and
DMI reads to the graphics memory range will be remapped to address 0h. The read will complete
with UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure they are not in SMM (actually, anything
above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to address 0h. This is
not specific to PCI Express or DMI; it applies to the processor or internal graphics engines. Also,
since the graphics memory range snoop would not be directly to SMM space, there would not be
a writeback to SMM. In fact, the writeback would also be invalid (because it uses the same
translation) and goes to address 0h.
11.4.8
Memory Shadowing
Any block of memory that can be designated as “read only” or “write only” can be “shadowed”
into (G)MCH main memory. Typically, this is done to allow ROM code to execute more rapidly
out of main DRAM memory. ROM is used as read-only during the copy process while DRAM at
the same time is designated write-only. After copying, the DRAM is designated read-only so that
ROM is shadowed. Processor bus transactions are routed accordingly.
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11.4.9
I/O Address Space
The (G)MCH does not support the existence of any other I/O devices beside itself on the
processor bus. The (G)MCH generates either DMI or PCI Express bus cycles for all processor I/O
accesses that it does not claim. Within the host bridge, the (G)MCH contains two internal
registers in the processor I/O space. These locations are used to implement a configuration space
access mechanism.
The processor allows 64 KB+3 bytes to be addressed within the I/O space. The (G)MCH
propagates the processor I/O address without any translation on to the destination bus; therefore,
providing addressability for 64 KB+3 byte locations. Note that the upper 3 locations can be
accessed only during I/O address wrap-around when processor bus HA16# address signal is
asserted. HA16# is asserted on the processor bus when an I/O access is made to 4 bytes from
address 0FFFDh, 0FFFEh, or 0FFFFh. HA16# is also asserted when an I/O access is made to
2 bytes from address 0FFFFh.
For the 828915G GMCH, a set of I/O accesses (other than ones used for configuration space
access) are consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics I/O decode and the associated control are explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
the DMI bus unless they fall within the PCI Express I/O address range as defined by the
mechanisms explained below. I/O writes are not posted. Memory writes to the ICH6 or PCI
Express are posted.
The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status. Upstream
I/O cycles and configuration cycles should never occur. If one does occur, the request will route
as a read to memory address 0h so a completion is naturally generated (whether the original
request was a read or write). The transaction will complete with a UR completion status.
11.4.10 PCI Express* I/O Address Mapping (Intel®
82915G/82915P/82915PL Only)
The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus
interface when processor-initiated I/O cycle addresses are within the PCI Express I/O address
range.
11.4.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping
The following are (G)MCH decode rules and cross-bridge address mapping used in this chipset:
• VGAA = 000A_0000h – 000A_FFFFh
• MDA = 000B_0000h – 000B_7FFFh
• VGAB = 000B_8000h – 000B_FFFFh
• MAINMEM = 0100_0000 to TOLUD
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11.4.12 Legacy VGA and I/O Range Decode Rules
The legacy 128-KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to IGD
(82915G/82915GV/82915GL/82910GL GMCH only), to PCI Express (Device #1), and/or to the
DMI depending on BIOS programming. Priority for VGA mapping is constant in that the
(G)MCH always decodes internally mapped devices first. Internal to the GMCH, decode
precedence is always given to IGD. The (G)MCH always positively decodes internally mapped
devices, namely the IGD and PCI Express.
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12 Functional Description
This chapter describes the (G)MCH interfaces and major functional units.
12.1
Host Interface
The (G)MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. The
cache line size is 64 bytes. Source synchronous transfer is used for the address and data signals.
The address signals are double pumped, and a new address can be generated every other bus
clock. At 133/200 MHz bus clock, the address signals run at 266/400 MT/s for a maximum
address queue rate of 66/100 million addresses/sec. The data is quad pumped and an entire
64 byte cache line can be transferred in two bus clocks. At 133/200 MHz bus clock the data
signals run at 533/800 MT/s for a maximum bandwidth of 4.2 GB/s or 6.4 GB/s.
Note: The host interface on the 82910GL GMCH runs at 133 MHz only.
The FSB interface supports up to 12 simultaneous outstanding transactions. The (G)MCH
supports only one outstanding deferred transaction on the FSB.
12.1.1
12.1.2
FSB GTL+ Termination
The (G)MCH integrates GTL+ termination resistors on die. Also, approximately
2.8 pf (fast) – 3.3 pf (slow) per pad of on die capacitance will be implemented to provide better
FSB electrical performance.
FSB Dynamic Bus Inversion
The (G)MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from
the processor. DBI limits the number of data signals that are driven to a low voltage on each quad
pumped data phase. This decreases the worst-case power consumption of the (G)MCH.
HDINV[3:0]# indicate if the corresponding 16 bits of data are inverted on the bus for each quad
pumped data phase:
HDINV[3:0]#
Data Bits
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HD[15:0]
HD[31:16]
HD[47:32]
HD[63:48]
When the processor or the (G)MCH drives data, each 16-bit segment is analyzed. If more than 8
of the 16 signals would normally be driven low on the bus, the corresponding HDINVx# signal
will be asserted and the data will be inverted prior to being driven on the bus. When the processor
or the (G)MCH receives data, it monitors HDINV[3:0]# to determine if the corresponding data
segment should be inverted.
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12.1.3
APIC Cluster Mode Support
This is required for backwards compatibility with existing software, including various operating
systems. As one example, beginning with Microsoft Windows 2000 there is a mode (boot.ini) that
allows an end user to enable the use of cluster addressing support of the APIC.
The (G)MCH supports three types of interrupt re-direction:
• Physical
• Flat-Logical
• Clustered-Logical
12.2
System Memory Controller
This section describes the (G)MCH system memory interface for both DDR memory and DDR2
memory. The (G)MCH supports both DDR and DDR2 memory and either one or two DIMMs per
channel.
Note: The 82915G/82915GV GMCH and 82915P MCH support both DDR memory and DDR2
memory, and either one or two DIMMs per channel. The 82910GL only supports DDR memory
and a maximum of one DIMM per channel. The 82915PL and 82915GL support only DDR and
either one or two DIMMs per channel.
12.2.1
Memory Organization Modes
The system memory controller supports two styles of memory organization (Interleaved and
Asymmetric) and two modes of operation (DDR and DDR2). Rules for populating DIMM slots
are included in this chapter.
Interleaved Mode
This mode provides maximum performance on real applications. Addresses are ping-ponged
between the channels, and the switch happens after each cache line (64 byte boundary). If two
consecutive cache lines are requested, both may be retrieved simultaneously, since they are
guaranteed to be on opposite channels. The drawbacks of Interleaved Mode are that the system
designer must populate both channels of memory such that they have equal capacity, but the
technology and device width may vary from one channel to the other. Refer to Figure 12-1 for
further clarification.
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode, addresses
start in channel A and stay there until the end of the highest rank in channel A; then, addresses
continue from the bottom of channel B to the top. Real world applications are unlikely to make
requests that alternate between addresses that sit on opposite channels with this memory
organization, so in most cases, bandwidth will be limited to that of a single channel. The system
designer is free to populate or not to populate any rank on either channel, including either
degenerate single channel case. Refer to Figure 12-1 for further clarification.
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Figure 12-1. System Memory Styles
Dual Channel Interleaved
(channels do not have to
match)
Dual Channel Asymmetric
(channels do not have to
match)
Single Channel
CL
CL
CL
CH B
TOM
TOM
CH B
CH A
TOM
CH B
CH B0
CH A
TOM
CH A or CH B
CH B
CH A
CH B
CH A
CH A
CH A0
0
0
Scheme
XOR Bit 6 => CL
Sys_Mem_Styles
Table 12-1. Sample System Memory Organization with Interleaved Channels
Rank
Channel A
population
Cumulative
top address in
Channel A
Channel B
population
Cumulative
top address in
Channel B
3
2
1
0
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
256 MB
512 MB
512 MB
256 MB
512 MB
512 MB
Table 12-2. Sample System Memory Organization with Asymmetric Channels
Rank
Channel A
population
Cumulative
top address in
Channel A
Channel B
population
Cumulative
top address in
Channel B
3
2
1
0
0 MB
1280 MB
1280 MB
1024 MB
512 MB
0 MB
2560 MB
2560 MB
2304 MB
1792 MB
256 MB
512 MB
512 MB
256 MB
512 MB
512 MB
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12.3
System Memory Configuration Registers Overview
The configuration registers located in the PCI configuration space of the (G)MCH control the
system memory operation. Following is a brief description of configuration registers.
• DRAM Rank Boundary (CxDRBy): The x represents a channel, either A (where x = 0) or
B (where x = 1). The y represents a rank, 0 through 3. DRB registers define the upper
addresses for a rank of DRAM devices in a channel. When the (G)MCH is configured in
asymmetric mode, each register represents a single rank. When the (G)MCH is configured in
a dual interleaved mode, each register represents a pair of corresponding ranks in opposing
channels. There are 4 DRB registers for each channel.
• DRAM Rank Architecture (CxDRAy): The x represents a channel, either A (where x = 0)
or B (where x = 1). The y represents a rank, 0 through 3. DRA registers specify the
architecture features of each rank of devices in a channel. The only architecture feature
specified is page size. When the (G)MCH is configured in asymmetric mode, each DRA
represents a single rank in a single channel. When the (G)MCH is configured in a dual-
channel lock-step or interleaved mode, each DRA represents a pair of corresponding ranks in
opposing channels. There are 4 DRA registers per channel. Each requires only 3 bits, so there
are two DRAs packed into a byte.
• Clock Configuration (CLKCFG): Specifies DRAM frequency. The same clock frequency
will be driven to all DIMMs.
• DRAM Timing (CxDRTy): The x represents a channel, A (where x = 0) or B
(where x = 1). A second register for a channel is differentiated by y, A or B. The DRT
registers define the timing parameters for all devices in a channel. The BIOS programs this
register with “least common denominator” values after reading the SPD registers of each
DIMM in the channel.
• DRAM Control (CxDRCy): The x represents a channel, A (where x = 0) or B
(where x = 1). A second register for a channel is differentiated by y, A or B. DRAM refresh
mode, rate, and other controls are selected here.
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12.3.1
DRAM Technologies and Organization
All standard 256-Mb, 512-Mb, and 1-Gb technologies and addressing are supported for x16 and
x8 devices.
• All supported DDR devices have 4 banks; all supported DDR2 devices have 4 or 8 banks.
• The (G)MCH supports various page sizes. Page size is individually selected for every rank.
• 4 KB, 8 KB, and 16 KB for asymmetric, interleaved, or single-channel modes.
• The DRAM sub-system supports single or dual channels, 64-b wide per channel.
• There can be a maximum of four ranks populated (two double-sided DIMMs) per channel.
• Mixed mode double-sided DIMMs (x8 and x16 on the same DIMM) are not supported
• By using 1-Gb technology, the largest memory capacity is 8 GB
32M rows/bank * 4 banks/device * 8 columns * 8 devices/rank * 4 ranks/channel *
2 channel * 1b/(row*column) * 1G/1024M * 1B/8b = 8 GB.
Though it is possible to put 8 GB in system by stuffing both channels this way, the (G)MCH
is still limited to 4 GB of addressable space due to the number of address pins on the FSB.
• By using 256-Mb technology, the smallest memory capacity is 128 MB
(4M rows/bank * 4banks/device * 16 columns * 4 devices/rank * 1 rank * 1B/8b =128 MB)
12.3.1.1
Rules for Populating DIMM Slots
• In all modes, the frequency of system memory will be the lowest frequency of all DIMMs in
the system, as determined through the SPD registers on the DIMMs.
• In the Single Channel mode, any DIMM slot within the channel may be populated in any
order. Either channel may be used. To save power, do not populate the unused channel.
• In Dual-Channel Asymmetric mode, any DIMM slot may be populated in any order.
• In Dual-Channel Interleaved mode, any DIMM slot may be populated in any order, but the
total memory in each channel must be the same.
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12.3.1.2
System Memory Supported Configurations
The (G)MCH supports the 256-Mbit, 512-Mbit and 1-Gbit technology based DIMMs from
Table 12-3.
Table 12-3. DDR / DDR2 DIMM Supported Configurations
Technology
Configuration
# of
Row
Address
Bits
# of Column
Address Bits
# of Bank
Address
Bits
Page
Size
Rank
Size
256Mbit
256Mbit
512Mbit
512Mbit
512Mbit
1Gbit
16M X 16
32M X 8
32M X 16
64M X 8
64M X 8
64M X 16
128M X 8
64M X 16
128M X 8
13
13
13
13
14
14
14
13
14
9
2
2
2
2
2
2
2
3
3
4K
8K
128 MB
256 MB
256 MB
512 MB
512 MB
512 MB
1 GB
10
10
11
10
10
11
10
10
8K
16K
8K
8K
1Gbit
16K
8K
1Gbit
512 MB
1 GB
1Gbit
8K
12.3.1.3
Main Memory DRAM Address Translation and Decoding
Table 12-4 and Table 12-5 specify the host interface to memory interface address multiplex for
the (G)MCH. Refer to the details of the various DIMM configurations as described in Table 12-3.
The address lines specified in the column header refer to the host (processor) address lines.
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Table 12-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
256 Mb x16 4i
256 Mb x8 4i
512 Mb x16 4i
512 Mb x8 4i
512 Mb x16 4i
4 KB
8 KB
8 KB
16 KB
8 KB
8 KB
8 KB
16 KB
8 KB
8 KB
128 MB
256 MB
256 MB
512 MB
256 MB
512 MB
512 MB
1 GB
r10 r9
r12 r10 r9
r8
r8
r8
r8
r8
r8
r8
r8
r8
r8
r7
r7
r7
r7
r7
r7
r7
r7
r7
r7
r6
r6
r6
r6
r6
r6
r6
r6
r6
r6
r5
r5
r5
r5
r5
r5
r5
r5
r5
r5
r4
r4
r4
r4
r4
r4
r4
r4
r4
r4
r3
r3
r3
r3
r3
r3
r3
r3
r3
r3
r2
r2
r2
r2
r2
r2
r2
r2
r2
r2
r1
r1
r1
r1
r1
r1
r1
r1
r1
r1
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r11 r12 b0 b1 c8 c7 c6 c5 c4 c3 c2 c1 c0
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
b0 b1 c11 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
b0 b1 b2 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
b0 b1 b2 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0
r12 r10 r9
r11 r12 r10 r9
r12 r10 r9
512 Mb x8
1 Gb x16
1 Gb x8
4i
4i
4i
8i
8i
r13 r12 r10 r9
r13 r12 r10 r9
r13 r11 r12 r10 r9
r11 r12 r10 r9
r13 r11 r12 r10 r9
1 Gb x16
1 Gb x8
512 MB
1 GB
NOTES:
1. b – ‘bank’ select bit
2. c – ‘column’ address bit
3. r – ‘row’ address bit
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Table 12-5. DRAM Address Translation (Dual Channel Symmetric Mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
256 Mb x16 4i
256 Mb x8 4i
512 Mb x16 4i
512 Mb x8 4i
512 Mb x16 4i
4 KB
8 KB
8 KB
16 KB
4 KB
8 KB
8 KB
16 KB
4 KB
8 KB
128 MB
256 MB
256 MB
512 MB
256 MB
512 MB
512 MB
1 GB
r10 r9
r12 r10 r9
r8
r8
r8
r8
r8
r8
r8
r8
r8
r8
r7
r7
r7
r7
r7
r7
r7
r7
r7
r7
r6
r6
r6
r6
r6
r6
r6
r6
r6
r6
r5
r5
r5
r5
r5
r5
r5
r5
r5
r5
r4
r4
r4
r4
r4
r4
r4
r4
r4
r4
r3
r3
r3
r3
r3
r3
r3
r3
r3
r3
r2
r2
r2
r2
r2
r2
r2
r2
r2
r2
r1
r1
r1
r1
r1
r1
r1
r1
r1
r1
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r11 r12 b0 b1 c8 c7 c6 c5 c4 c3
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3
b0 b1 c11 c9 c8 c7 c6 c5 c4 c3
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3
r11 b1 b0 c9 c8 c7 c6 c5 c4 c3
b0 b1 c11 c9 c8 c7 c6 c5 c4 c3
b0 b1 b2 c9 c8 c7 c6 c5 c4 c3
b0 b1 b2 c9 c8 c7 c6 c5 c4 c3
h
h
h
h
h
h
h
h
h
h
c2 c1 c0
c2 c1 c0
c2 c1 c0
c2 c1 c0
c2 c1 c0
c2 c1 c0
c2 c1 c0
c2 c1 c0
c2 c1 c0
c2 c1 c0
r12 r10 r9
r11 r12 r10 r9
r12 r10 r9
512 Mb x8
1 Gb x16
1 Gb x8
4i
4i
4i
8i
8i
r13 r12 r10 r9
r13 r12 r10 r9
r13 r11 r12 r10 r9
r11 r12 r10 r9
r13 r11 r12 r10 r9
1 Gb x16
1 Gb x8
512 MB
1 GB
NOTES:
1. b – ‘bank’ select bit
2. c – ‘column’ address bit
3. h – channel select bit
4. r – ‘row’ address bit
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12.3.2
12.3.3
12.3.4
DRAM Clock Generation
The (G)MCH generates three differential clock pairs for every supported DIMM. There are a total
of 6 clock pairs driven directly by the (G)MCH to 2 DIMMs per channel
(82915G/82915GV/82915GL and 82915P) and to 1 DIMM per channel (82910GL/82915PL).
Suspend-to-RAM and Resume
When entering the Suspend-to-RAM (STR) state, the SDRAM controller will flush pending
cycles and then enter all SDRAM rows into self refresh. In STR, the CKE signals remain LOW so
the SDRAM devices will perform self-refresh.n
DDR2 On-Die Termination
On-die termination (ODT) is a feature that allows a DRAM to turn on/off internal termination
resistance for each DQ, DM, DQS, and DQS# signal for x8 and x16 configurations via the ODT
control signals. The ODT feature is designed to improve signal integrity of the memory channel
by allowing the termination resistance for the DQ, DM, DQS, and DQS# signals to be located
inside the DRAM devices themselves, instead of on the motherboard. The (G)MCH drives out the
required ODT signals, based on memory configuration and which rank is being written to or read
from, to the DRAM devices on a targeted DIMM rank to enable or disable their termination
resistance.
12.3.5
DDR2 Off-Chip Driver Impedance Calibration
The OCD impedance adjustment mode allows the (G)MCH to measure and adjust the pull-up and
pull-down strength of the DRAM devices. It uses a series of EMRS commands to guide the
DRAM through measurement and calibration cycles. This feature is described in more detail in
the JEDEC DDR2 device specification.
The algorithm and sequence of the adjustment cycles is handled by software. The (G)MCH
adjusts the DRAM driver impedance by issuing OCD commands to the DIMM and looking at the
analog voltage on the DQ lines.
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12.4
PCI Express* (Intel® 82915G/82915P82915PL Only)
Refer to Chapter 0 a for list of PCI Express features, and the PCI Express specification for further
details. The (G)MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy.
The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model
(a load-store architecture with a flat address space) is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express configuration uses standard
mechanisms as defined in the PCI Plug-and-Play specification. The initial speed of 1.25 GHz
(250 MHz internally) results in 2.5 Gb/s/direction that provides a 250 MB/s communications
channel in each direction (500 MB/s total) per lane that is close to twice the data rate of classic
PCI.
Note: The PCI Express graphics port will operate in x1 mode if a non-graphics card is plugged in.
12.4.1
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer’s
primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).
TLPs are used to communicate transactions (such as read and write as well as certain types of
events). The Transaction Layer also manages flow control of TLPs.
Note: If the (G)MCH receives two back-to-back malformed packets, the second malformed packet is not
trapped or logged. The (G)MCH will not log or identify the second malformed packet. However,
the 1st malformed TLP is logged, and is considered a Fatal Error. Link behavior is not guaranteed
at that point whether a 2nd malformed TLP is detected or not.
12.4.2
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage
between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer
include link management, error detection, and error correction.
12.4.3
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input
buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching
circuitry.
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12.5
Intel® Serial Digital Video Output (SDVO) (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only)
The 82915G/82915GV/82915GL/82910GL GMCH SDVO ports are multiplexed with the PCI
Express x16 interface. PCI Express and SDVO simultaneous operation is NOT supported, even
though SDVO does not require all of the PCI Express lanes.
The Intel® SDVO port is the second generation of digital video output from compliant GMCH.
The electrical interface is based on the PCI Express interface, although the protocol and timings
are completely unique. Where PCI Express runs at a fixed frequency, the frequency of the SDVO
interface is dependant upon the active display resolution and timing. The port can be dynamically
configured in several modes to support display configurations.
Essentially, an SDVO port will transmit display data in a high speed, serial format across
differential AC coupled signals. An SDVO port consists of a sideband differential clock pair and
a number of differential data pairs.
12.5.1
Intel® SDVO Capabilities
SDVO ports can support a variety of display types including LVDS, DVI, Analog CRT, TV-Out
and external CE type devices. The GMCH uses an external SDVO device to translate from SDVO
protocol and timings to the desired display format and timings.
The Internal Graphics Device on the 82915G/82915GV/82915GL/82910GL GMCH can have one
or two SDVO ports multiplexed on the x16 PCI Express interface. When an external x16 PCI
Express graphics accelerator is not in use, an ADD2 card may be plugged into the x16 connector
or if a x16 slot is not present, the SDVO(s) may be located ‘down’ on the motherboard to access
the multiplexed SDVO ports and provide a variety of digital display options.
The ADD2 card is designed to fit in a x16 PCI Express connector. The ADD2 card can support
one or two devices. If a single channel SDVO device is used, it should be attached to the channel
B SDVO pins. The ADD2 card can support two separate SDVO devices when the interface is in
Dual Independent (82915G only) or Dual Simultaneous Standard modes.
The SDVO port defines a two-wire point-to-point communication path between the SDVO device
and GMCH. The SDVO control clock and data provide similar functionality to I2C. However,
unlike I2C, this interface is intended to be point-to-point (from the GMCH to the SDVO device)
and will require the SDVO device to act as a switch and direct traffic from the SDVO control bus
to the appropriate receiver. Additionally, this control bus will be able to run at faster speeds (up to
1 MHz) than a traditional I2C interface would.
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12.5.2
Intel® SDVO Modes
The port can be dynamically configured in several modes:
• Standard. This mode provides baseline SDVO functionality. Supports Pixel Rates between
25 and 200 MP/s. Utilizes three data pairs to transfer RGB data.
• Extended. This mode adds Alpha support to data stream. Extended mode supports Pixel rates
between 25 MP/s and 200 MP/s. The mode uses four data channels and is only supported on
SDVOB. Leverages channel C (SDVOC) Red pair as the Alpha pair for channel B (SDVOB).
Note: Operating in extended SDVO mode is mutually exclusive to the use of a second display
on SDVO.
• Dual Standard. This mode uses Standard data streams across both SDVOB and SDVOC.
Both channels can only run in Standard mode (3 data pairs) and each channel supports Pixel
Rates between 25 and 200 MP/s.
⎯ Dual Independent Standard (82915G only). In Dual Independent Standard mode, each
SDVO channel will see a different pixel stream. The data stream across SDVOB will not
be the same as the data stream across SDVOC.
⎯ Dual Simultaneous Standard. In Dual Simultaneous Standard mode, both SDVO
channels will see the same pixel stream. The data stream across SDVOB will be the same
as the data stream across SDVOC. The display timings will be identical, but the transfer
timings may not be (i.e., SDVOB clocks and data may not be perfectly aligned with
SDVOC clock and data as seen at the SDVO device(s)). Since this mode uses just a
single data stream, it uses a single pixel pipeline within the GMCH.
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12.6
Integrated Graphics Device (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only)
The GMCH provides a highly integrated graphics accelerator and chipset while allowing a
flexible integrated system graphics solution. Figure 12-2 shows a simplified block diagram of the
IGD in the GMCH.
Figure 12-2. Integrated Graphics Device Block Diagram
Video Engine
DAC (Analog)
SDVOB (Digital)
SDVOC (Digital)
M
e
m
o
r
Port
Mux
Control
Display
Engine
2D Engine
3D Engine
y
Gfx_Blk_Dia
High bandwidth access to data is provided through the graphics and system memory ports. The GMCH
can access graphics data located in system memory at 4.2 GB/s – 8.5 GB/s (depending on memory
configuration). The GMCH uses Intel’s Direct Memory Execution model to fetch textures from system
memory. The GMCH includes a cache controller to avoid frequent memory fetches of recently used
texture data.
The GMCH is able to drive an integrated DAC, and/or two SDVO ports (multiplexed with PCI
Express) capable of driving an ADD2 card. External SDVO devices are capable of driving a
standard progressive scan analog monitor with resolutions up to 2048x1536 @ 75 Hz. The SDVO
ports are capable of driving a variety of TV-Out, TMDS, and LVDS transmitters.
The GMCH’s Internal Graphics Device (IGD) contains several types of components. The major
components in the IGD are the engines, planes, pipes and ports. The GMCH has a 3D/2D
Instruction Processing unit to control the 3D and 2D engines. The IGD’s 3D and 2D engines are
fed with data through the memory controller. The outputs of the engines are surfaces sent to
memory, which are then retrieved and processed by the GMCH planes.
The GMCH contains a variety of planes (such as display, overlay, cursor and VGA). A plane
consists of rectangular shaped image that has characteristics such as source, size, position,
method, and format. These planes get attached to source surfaces that are rectangular memory
surfaces with a similar set of characteristics. They are also associated with a particular destination
pipe.
A pipe consists of a set of combined planes and a timing generator. The GMCH has two
independent display pipes, allowing for support of two independent display streams. A port is the
destination for the result of the pipe. The GMCH contains three display ports, 1 analog (DAC)
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and two digital (SDVO ports B and C). The ports will be explained in more detail later in the
chapter.
The entire IGD is fed with data from its memory controller. The GMCH’s graphics performance
is directly related to the amount of bandwidth available. If the engines are not receiving data fast
enough from the memory controller (e.g., single-channel DDR333), the rest of the IGD will also
be affected.
The rest of this chapter will focus on explaining the IGD components, their limitations and
dependencies.
12.6.1
3D Engine
The 3D engine of GMCH has been designed with a deep pipelined architecture, where
performance is maximized by allowing each stage of the pipeline to simultaneously operate on
different primitives or portions of the same primitive. GMCH supports Perspective-Correct
Texture Mapping, Multitextures, Bump-Mapping, Cubic Environment Maps, Bilinear, Trilinear
and Anisotropic MIP mapped filtering, Gouraud shading, Alpha-blending, Vertex and Per Pixel
Fog and Z/W Buffering.
The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the
pipline are the Setup Engine, Scan Converter, Texture Pipeline, and Raster Pipeline. A typical
programming sequence would be to send instructions to set the state of the pipeline followed by
rending instructions containing 3D primitive vertex data.
The engine’s performance is dependent on the memory bandwidth available. Systems that have
more bandwidth available will outperform systems with less bandwidth. The engine’s
performance is also dependent on the core clock frequency. The higher the frequency, the more
data is processed.
12.6.2
Setup Engine
The setup stage of the pipeline takes the input data associated with each vertex of a 3D primitive
and computes the various parameters required for scan conversion. In formatting this data, the
GMCH maintains sub-pixel accuracy.
12.6.2.1
3D Primitives and Data Formats Support
The 3D primitives rendered by GMCH are points, lines, discrete triangles, line strips, triangle
strips, triangle fans and polygons. In addition to this, GMCH supports the Microsoft DirectX*
Flexible Vertex Format (FVF), which enables the application to specify a variable length of
parameter list obviating the need for sending unused information to the hardware. Strips, Fans and
Indexed Vertices as well as FVF, improve the vertex rate delivered to the setup engine
significantly.
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12.6.2.2
Pixel Accurate “Fast” Scissoring and Clipping Operation
The GMCH supports 2D clipping to a scissor rectangle within the drawing window. Objects are
clipped to the scissor rectangle, avoiding processing pixels that fall outside the rectangle. The
GMCH’s clipping and scissoring in hardware reduce the need for software to clip objects, and
thus improve performance. During the setup stage, GMCH clips objects to the scissor window.
A scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger
region than the hardware renders to. The scissor rectangle needs to be pixel accurate, and
independent of line and point width. The GMCH will support a single scissor box rectangle that
can be enabled or disabled. The rectangle is defined as an Inclusive box. Inclusive is defined as
“draw the pixel if it is inside the scissor rectangle”.
12.6.2.3
12.6.2.4
Depth Bias
The GMCH supports source Depth Biasing in the Setup Engine. The Depth Bias value is
specified in the vertex command packet on a per primitive basis. The value ranges from -1 to 1.
The Depth Bias value is added to the z or w value of the vertices. This is used for coplanar
polygon priority. If two polygons are to be rendered that are coplanar, due to the inherent
precision differences induced by unique x, y and z values, there is no guarantee which polygon
will be closer or farther. By using Depth Bias, it is possible to offset the destination z value
(compare value) before comparing with the new z value.
Backface Culling
As part of the setup, the GMCH discards polygons from further processing, if they are facing
away from or towards the user’s viewpoint. This operation, referred to as “Back Face Culling” is
accomplished based on the “clockwise” or “counter-clockwise” orientation of the vertices on a
primitive. This can be enabled or disabled by the driver.
12.6.2.5
12.6.2.6
Scan Converter
Working on a per-polygon basis, the Scan Converter uses the vertex and edge information is used
to identify all pixels affected by features being rendered.
Pixel Rasterization Rules
The GMCH supports both OpenGL and D3D pixel rasterization rules to determine whether a
pixel is filled by the triangle or line. For both D3D and OpenGL modes, a top-left filling
convention for filling geometry will be used. Pixel rasterization rule on rectangle primitive is also
supported using the top-left fill convention.
12.6.2.7
2D Functionality
The stretch BLT function can stretch source data in the X and Y directions to a destination larger
or smaller than the source. Stretch BLT functionality expands a region of memory into a larger or
smaller region using replication and interpolation. The stretch BLT function also provides format
conversion and data alignment.
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12.6.3
Texture Engine
The GMCH allows an image, pattern, or video to be placed on the surface of a 3D polygon.
The texture processor receives the texture coordinate information from the setup engine and the
texture blend information from the scan converter. The texture processor performs texture color
or ChromaKey matching, texture filtering (anisotropic, trilinear, and bilinear interpolation), and
YUV to RGB conversions.
12.6.3.1
Perspective Correct Texture Support
A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon.
A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in
perspective, it is important that texture be mapped in perspective as well. Without perspective
correction, texture is distorted when an object recedes into the distance.
12.6.3.2
12.6.3.3
Texture Formats and Storage
The GMCH supports up to 32 bits of color for textures.
Texture Decompression
DirectX supports Texture Compression to reduce the bandwidth required to deliver textures. As
the textures’ average size gets larger with higher color depth and multiple textures become the
norm, it becomes increasingly important to provide a mechanism for compressing textures.
Texture decompression formats supported include DXT1, DXT2, DXT3, DXT4, DXT5 and
FXT1.
12.6.3.4
12.6.3.5
12.6.3.6
Texture ChromaKey
ChromaKey describes a method of removing a specific color or range of colors from a texture
map before it is applied to an object. For “nearest” texture filter modes, removing a color simply
makes those portions of the object transparent (the previous contents of the back buffer show
through). For “linear“ texture filtering modes, the texture filter is modified if only the non-nearest
neighbor texels match the key (range).
Anti-Aliasing
Aliasing is one of the artifacts that degrade image quality. In its simplest manifestation, aliasing
causes the jagged staircase effects on sloped lines and polygon edges. Another artifact is the
moiré patterns that occur as a result of a very small number of pixels available on screen to
contain the data of a high resolution texture map. More subtle effects are observed in animation,
where very small primitives blink in and out of view.
Texture Map Filtering
The GMCH supports many texture mapping modes. Perspective correct mapping is always
performed. As the map is fitted across the polygon, the map can be tiled, mirrored in either the U
or V directions, or mapped up to the end of the texture and no longer placed on the object (this is
known as clamp mode). The way a texture is combined with other object attributes is also
definable.
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The GMCH supports up to 12 Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1x1
texels. Textures need not be square. Included in the texture processor is a texture cache, which
provides efficient MIP-mapping.
The GMCH supports 7 types of texture filtering:
• Nearest (aka Point Filtering): Texel with coordinates nearest to the desired pixel is used.
(This is used if only one LOD is present).
• Linear (aka Bilinear Filtering): A weighted average of a 2x2 area of texels surrounding the
desired pixel is used. (This is used if only one LOD is present).
• Nearest MIP Nearest (aka Point Filtering): This is used if many LODs are present. The
nearest LOD is chosen and the texel with coordinates nearest to the desired pixel is used.
• Linear MIP Nearest (Bilinear MIP Mapping): This is used if many LODs are present. The
nearest LOD is chosen and a weighted average of a 2x2 area of texels surrounding the
desired pixel is used (four texels). This is also referred to as Bilinear MIP Mapping.
• Nearest MIP Linear (Point MIP Mapping): This is used if many LODs are present. Two
appropriate LODs are selected and within each LOD the texel with coordinates nearest to the
desired pixel is selected. The Final texture value is generated by linear interpolation between
the two texels selected from each of the MIP Maps.
• Linear MIP Linear (Trilinear MIP Mapping): This is used if many LODs are present. Two
appropriate LODs are selected and a weighted average of a 2x2 area of texels surrounding the
desired pixel in each MIP Map is generated (four texels per MIP Map). The Final texture
value is generated by linear interpolation between the two texels generated for each of the
MIP Maps. Trilinear MIP Mapping is used minimize the visibility of LOD transitions across
the polygon.
• Anisotropic MIP Nearest (Anisotropic Filtering): This is used if many LODs are present. The
nearest LOD-1 level will be determined for each of four sub-samples for the desired pixel.
These four sub-samples are then bilinear filtered and averaged together.
Both D3D (DirectX 6.0 and later) and OpenGL (Revision 1.1) allow support for all these filtering
modes.
12.6.3.7
12.6.3.8
Multiple Texture Composition
The GMCH also performs multiple texture composition. This allows the combination of two or
greater MIP Maps to produce a new one with new LODs and texture attributes in a single or
iterated pass. Flexible vertex format support allows multitexturing because it makes it possible to
pass more than one texture in the vertex structure.
Bi-Cubic Filter (4x4 Programmable Texture Filter)
A bi-cubic texture filter can be selected instead of the bilinear filter. The implementation is of a
4x4 separable filter with loadable coefficients. A 4x4 filter can be used for providing high-quality
up/ down scaling of 2D or 3D rendered images.
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12.6.3.9
Cubic Environment Mapping
Environment maps allow applications to render scenes with complex lighting and reflections
while significantly decreasing processor load. There are several methods to generate environment
maps (such as, spherical, circular and cubic). The GMCH supports cubic reflection mapping over
spherical and circular since it is the best choice to provide real-time environment mapping for
complex lighting and reflections.
Cubic Mapping requires a texture map for each of the 6 cube faces. These can be generated by
pointing a camera with a 90-degree field-of-view in the appropriate direction. Per-vertex vectors
(normal, reflection or refraction) are interpolated across the polygon and the intersection of these
vectors with the cube texture faces is calculated. Texel values are then read from the intersection
point on the appropriate face and filtered accordingly.
12.6.4
Raster Engine
The Raster Engine is where the color data (such as fogging, specular RGB, texture map blending,
etc.) is processed. The final color of the pixel is calculated and the RGBA value combined with
the corresponding components resulting from the Texture Engine. These textured pixels are
modified by the specular and fog parameters. These specular highlighted, fogged, textured pixels
are color blended with the existing values in the frame buffer. In parallel, stencil, alpha and depth
buffer tests are conducted which will determine whether the Frame and Depth Buffers will be
updated with the new pixel values.
12.6.4.1
12.6.4.2
Texture Map Blending
Multiple Textures can be blended together in an iterative process and applied to a primitive. The
GMCH allows up to four texture coordinates and texture maps to be specified onto the same
polygon. Also, the GMCH supports using a texture coordinate set to access multiple texture maps.
State variables in multiple texture are bound to texture coordinates, texture map or texture
blending.
Combining Intrinsic and Specular Color Components
The GMCH allows an independently specified and interpolated “specular RGB” attribute to be
added to the post-texture blended pixel color. This feature provides a full RGB specular highlight
to be applied to a textured surface, permitting a high-quality reflective colored lighting effect not
available in devices which apply texture after the lighting components have been combined. If
specular-add state variable is disabled, only the resultant colors from the map blending are used.
If this state variable is enabled, RGB values from the output of the map blending are added to
values for RS, GS, BS on a component by component basis.
12.6.4.3
Color Shading Modes
The Raster Engine supports the flat and Gouraud shading modes. These shading modes are
programmed by the appropriate state variables issued through the command stream.
Flat shading is performed by smoothly interpolating the vertex intrinsic color components (Red,
Green, Blue), Specular Highlights(R,G,B), Fog, and Alpha to the pixel, where each vertex color
has the same value. The setup engine substitutes one of the vertex’s attribute values for the other
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two vertices attribute values thereby creating the correct flat shading terms. This condition is set
up by the appropriate state variables issued prior to rendering the primitive.
OpenGL and D3D use a different vertex to select the flat shaded color. This vertex is defined as
the “provoking vertex”. In the case of strips/fans, after the first triangle, attributes on every vertex
that define a primitive are used to select the flat color of the primitive. A state variable is used to
select the “flat color” prior to rendering the primitive.
Gouraud shading is performed by smoothly interpolating the vertex intrinsic color components
(Red, Green, Blue). Specular Highlights (R,G,B), Fog, and Alpha to the pixel, where each vertex
color has a different value.
All the attributes can be selected independently from one of the shading modes by setting the
appropriate value state variables.
12.6.4.4
12.6.4.5
Color Dithering
Color Dithering helps to hide color quantization errors. Color Dithering takes advantage of the
human eye’s propensity to “average” the colors in a small area. Input color, alpha, and fog
components are converted from 8-bit components to 5- or 6- bit component by dithering.
Dithering is performed on blended textured pixels. In 32-bit mode, dithering is not performed on
the components
Vertex and Per Pixel Fogging
Fogging is used to create atmospheric effects (such as low visibility conditions in flight simulator-
type games). It adds another level of realism to computer-generated scenes. Fog can be used for
depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer
details (fewer polygons), thereby improving the rendering speed or frame rate. Fog is simulated
by attenuating the color of an object with the fog color as a function of distance. Higher fog
density produces lower visibility for distant objects. There are two ways to implement the fogging
technique: per-vertex (linear) fogging and per-pixel (non-linear) fogging. The per-vertex method
interpolates the fog value at the vertices of a polygon to determine the fog factor at each pixel
within the polygon. This method provides realistic fogging as long as the polygons are small.
With large polygons (such as a ground plane depicting an airport runway), the per-vertex
technique results in unnatural fogging.
The GMCH supports both types of fog operations, vertex and per pixel or table fog. If fog is
disabled, the incoming color intensities are passed unchanged to the destination blend unit.
12.6.4.6
Alpha Blending (Frame Buffer)
Alpha Blending adds the material property of transparency or opacity to an object. Alpha
blending combines a source pixel color (RSGSBS) and alpha (AS) component with a destination
pixel color (RDGDBD) and alpha (AD) component. For example, this is so that a glass surface on
top (source) of a red surface (destination) would allow much of the red base color to show
through.
Blending allows the source and destination color values to be multiplied by programmable factors
and then combined via a programmable blend function. The combined and independent selection
of factors and blend functions for color and alpha are supported.
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12.6.4.7
12.6.4.8
Microsoft DirectX* API and SGI OpenGL* API Logic Ops
Both APIs provide a mode to use bitwise ops in place of alpha blending. This is used for rubber-
banding (i.e., draw a rubber band outline over the scene using an XOR operation). Drawing it
again restores the original image without having to do a potentially expensive redraw.
Color Buffer Formats: 8-, 16-, or 32-bits per Pixel (Destination Alpha)
The Raster Engine supports 8-bit, 16-bit, and 32-bit Color Buffer Formats. The 8-bit format is
used to support planar YUV420 format, which used only in Motion Compensation and Arithmetic
Stretch format. The bit format of Color and Z will be allowed to mix.
The GMCH supports both double and triple buffering, where one buffer is the primary buffer
used for display and one or two are the back buffer(s) used for rendering.
The frame buffer of the GMCH contains at least two hardware buffers: the Front Buffer (display
buffer) and the Back Buffer (rendering buffer). While the back buffer may actually coincide with
(or be part of) the visible display surface, a separate (screen or window-sized) back buffer is used
to permit double-buffered drawing. That is, the image being drawn is not visible until the scene is
complete and the back buffer made visible (via an instruction) or copied to the front buffer (via a
2D BLT operation). Rendering to one and displaying from the other remove the possibility of
image tearing. This also speeds up the display process over a single buffer. Additionally, triple
back buffering is also supported. The instruction set of the GMCH provides a variety of controls
for the buffers (e.g., initializing, flip, clear, etc.).
12.6.4.9
Depth Buffer
The Raster Engine can read and write from this buffer and use the data in per fragment operations
that determine whether resultant color and depth value of the pixel for the fragment are to be
updated or not.
Typical applications for entertainment or visual simulations with exterior scenes require far/near
ratios of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth. This can
cause hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. A
24-bit Z-buffer provides 16 million Z-values, as opposed to only 64 K with a 16-bit Z buffer.
With lower Z-resolution, two distant overlapping objects may be assigned the same Z-value. As a
result, the rendering hardware may have a problem resolving the order of the objects, and the
object in the back may appear through the object in the front.
By contrast, when W (or eye-relative Z) is used, the buffer bits can be more evenly allocated
between the near and far clip planes in world space. The key benefit is that the ratio of far and
near is no longer an issue, allowing applications to support a maximum range of miles, yet still get
reasonably accurate depth buffering within inches of the eye point.
The GMCH supports a flexible format for the floating-point W buffer, wherein the number of
exponent bits is programmable. This allows the driver to determine variable precision as a
function of the dynamic range of the W (screen-space Z) parameter.
The selection of depth buffer size is relatively independent of the color buffer. A 16-bit Z/W or
24-bit Z/W buffer can be selected with a 16-bit color buffer. Z buffer is not supported in 8-bit
mode.
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12.6.4.10 Stencil Buffer
The Raster Engine provides 8-bit stencil buffer storage in 32-bit mode and the ability to perform
stencil testing. Stencil testing controls 3D drawing on a per pixel basis, conditionally eliminating
a pixel on the outcome of a comparison between a stencil reference value and the value in the
stencil buffer at the location of the source pixel being processed. They are typically used in
multipass algorithms to achieve special effects, such as decals, outlining, shadows and
constructive solid geometry rendering.
12.6.4.11 Projective Textures
The GMCH supports two simultaneous projective textures at full rate processing, and four
textures at half rate. These textures require three floating point texture coordinates to be included
in the Flexible Vertex Format (FVF). Projective textures enable special effects (such as projecting
spot light textures obliquely onto walls, etc.).
12.6.5
2D Engine
The GMCH contains BLT functionality, and an extensive set of 2D instructions. To take
advantage of the 3D drawing engine’s functionality, some BLT functions (such as Alpha BLTs,
arithmetic (bilinear) stretch BLTs, rotations, transposing pixel maps, limited color space
conversion, and DIBs) make use of the 3D renderer.
12.6.5.1
12.6.5.2
GMCH VGA Registers
The 2D registers are a combination of registers defined by IBM when the Video Graphics Array
(VGA) was first introduced and others that Intel has added to support graphics modes that have
color depths, resolutions, and hardware acceleration features that go beyond the original VGA
standard.
Logical 128-bit Fixed BLT and 256 Fill Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows*
operating systems. The 128-bit GMCH BLT Engine provides hardware acceleration of block
transfers of pixel data for many common Windows operations. The term BLT refers to a block
transfer of pixel data between memory locations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data Alignment
• Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between memory locations. The
allowable memory transfers are between: cacheable system memory and frame buffer memory,
frame buffer memory and frame buffer memory, and within system memory. Data to be
transferred can consist of regions of memory, patterns, or solid color fills. A pattern will always
be 8x8 pixels wide and may be 8, 16, or 32 bits per pixel.
The GMCH BLT engine has the ability to expand monochrome data into a color depth of 8, 16, or
32 bits. BLTs can be either opaque or transparent. Opaque transfers move the data specified to the
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destination. Transparent transfers compare destination color to source color and write according
to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the BLT
overlaps with the source memory location, the GMCH can specify which area in memory to begin
the BLT transfer. Hardware is included for all 256 raster operations (Source, Pattern, and
Destination) defined by Microsoft, including transparent BLT.
The GMCH has instructions to invoke BLT and stretch BLT operations, permitting software to set
up instruction buffers and use batch processing. The GMCH can perform hardware clipping
during BLTs.
12.6.6
Video Engine
12.6.6.1
Hardware Motion Compensation
The Motion Compensation (MC) process consists of reconstructing a new picture by predicting
(either forward, backward, or bi-directionally) the resulting pixel colors from one or more
reference pictures. The GMCH receives the video stream and implements Motion Compensation
and subsequent steps in hardware. Performing Motion Compensation in hardware reduces the
processor demand of software-based MPEG-2 decoding, and thus improves system performance.
The Motion Compensation functionality is overloaded onto the texture cache and texture filter.
The texture cache is used to typically access the data in the reconstruction of the frames and the
filter is used in the actual motion compensation process. To support this overloaded functionality
the texture cache additionally support the YUV420 planar input formats.
12.6.6.2
Sub-Picture Support
Sub-picture is used for two purposes; one is Subtitles for movie captions, etc. (that are
superimposed on a main picture), and the other is Menus used to provide some visual operation
environments the user of a content player.
DVD allows movie subtitles to be recorded as Sub-pictures. On a DVD disc, it is called "Subtitle"
because it has been prepared for storing captions. Since the disc can have a maximum of 32 tracks
for Subtitles, they can be used for various applications, for example, as Subtitles in different
languages or other information to be displayed.
There are two kinds of Menus; the System Menus and other In-Title Menus. First, the System
Menus are displayed and operated at startup of or during the playback of the disc or from the stop
state. Second, In-Title menus can be programmed as a combination of Sub-picture and Highlight
commands to be displayed during playback of the disc.
The GMCH supports sub-picture for DVD and DBS by mixing the two video streams via alpha
blending. Unlike color keying, alpha blending provides a softer effect and each pixel that is
displayed is a composite between the two video stream pixels. The GMCH can use four methods
when dealing with sub-pictures. The flexibility enables the GMCH to work with all sub- picture
formats.
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12.6.7
Planes
A plane consists of rectangular shaped image that has characteristics such as source, size,
position, method, and format. These planes get attached to source surfaces, which are rectangular
memory surfaces with a similar set of characteristics. They are also associated with a particular
destination pipe.
12.6.7.1
12.6.7.2
Cursor Plane
The cursor planes are one of the simplest display planes. With a few exceptions, the cursor plane
has a fixed size of 64x64 and a fixed Z-order (top). In legacy modes, cursor can cause the display
data below it to be inverted.
Overlay Plane
The overlay engine provides a method of merging either video capture data (from an external
Video Capture device) or data delivered by the processor, with the graphics data on the screen.
The source data can be mirrored horizontally or vertically or both.
Source/Destination Color Keying/ChromaKeying
Overlay source/destination ChromaKeying enables blending of the overlay with the underlying
graphics background. Destination color keying/ChromaKeying can be used to handle occluded
portions of the overlay window on a pixel by pixel basis that is actually an underlay. Destination
ChromaKeying would only be used for YUV passthrough to TV. Destination color keying
supports a specific color (8- or 15-bit) mode as well as 32-bit alpha blending.
Source color keying/ChromaKeying is used to handle transparency based on the overlay window
on a pixel by pixel basis. This is used when “blue screening” an image to overlay the image on a
new background later.
Gamma Correction
To compensate for overlay color intensity loss due to the non-linear response between display
devices, the overlay engine supports independent gamma correction. This allows the overlay data
to be converted to linear data or corrected for the display device when not blending.
YUV to RGB Conversion
The format conversion can be bypassed in the case of RGB source data. The format conversion
assumes that the YUV data is input in the 4:4:4 format and uses the full range scale.
Maximum Resolution and Frequency
The maximum frequency supported by the overlay logic is 180 MHz. The maximum resolution is
dependent on a number of variables (e.g., memory speed, memory latency, port selected, pipe
selected, mode definition).
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Deinterlacing Support
For display on a progressive computer monitor, interlaced data that has been formatted for display
on interlaced monitors (TV) needs to be de-interlaced. The simple approaches to de-interlacing
create unwanted display artifacts. More advanced de-interlacing techniques have a large cost
associated with them. The compromise solution is to provide a low cost but effective solution and
enable both hardware and software based external solutions. Software based solutions are enabled
through a high bandwidth transfer to system memory and back.
12.6.7.3
Advanced Deinterlacing and Dynamic Bob and Weave
Interlaced data that originates from a video camera creates two fields that are temporally offset by
1/60 of a second. There are several schemes to deinterlace the video stream: line replication,
vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the
previous field and inserts them into the current field to construct the frame; this is known as
Weaving. This is the best solution for images with little motion however, showing a frame that
consists of the two fields will have serration or feathering of moving edges when there is motion
in the scene. Vertical filtering or “Bob” interpolates adjacent lines rather than replicating the
nearest neighbor. This is the best solution for images with motion; however, it will have reduced
spatial resolution in areas that have no motion and introduces aliasing. In the absence of any other
deinterlacing, these form the baseline and are supported by the GMCH.
Scaling Filter and Control
The scaling filter has three vertical taps and five horizontal taps. Arbitrary scaling (per pixel
granularity) for any video source (YUV422 or YUV420) format is supported.
The overlay logic can scale an input image up to 1600X1200with no major degradation in the
filter used as long as the maximum frequency limitation is met. Display resolution and refresh rate
combinations where the dot clock is greater than the maximum frequency require the overlay to
use pixel replication.
12.6.8
Pipes
The display consists of two pipes. The Pipes can operate in a single-wide or “double-wide” mode
at 2x graphics core clock though they are effectively limited by the respective display port. The
display planes and the cursor plane will provide a “double wide” mode to feed the pipe.
12.6.8.1
Clock Generator Units (DPLL)
The clock generator units provide a stable frequency for driving display devices. It operates by
converting an input reference frequency into an output frequency. The timing generators take
their input from internal DPLL devices that are programmable to generate pixel clocks in the
range of 25–400 MHz. Accuracy for VESA timing modes is required to be within ± 0.5%.
The DPLL can take a reference frequency from the external reference input (DREFCLKINN/P),
the TV clock input (TVCLKIN).
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12.7
Display Interfaces (Intel®
82915G/82915GV/82915GL/ 82910GL GMCH Only)
The GMCH has three display ports; one analog and two digital. Each port can transmit data
according to one or more protocols. The digital ports are connected to an external device that
converts one protocol to another. Examples of this are TV encoders, external DACs, LVDS
transmitters, and TMDS transmitters. Each display port has control signals that may be used to
control, configure and/or determine the capabilities of an external device.
The analog port is a dedicated port (not multiplexed) on the 82915GV/82915GL/82910GL
GMCH. For the 82915G GMCH, the SDVO ports B and C are multiplexed with the PCI Express
graphics interface and are not available if an external PCI Express graphics device is in use. When
a 915G Express chipset system uses a PCI Express graphics connector, SDVO ports B and C can
be used via an ADD2 (Advanced Digital Display 2) card. Ports B and C can also operate in dual-
channel mode, where the data bus is connected to both display ports, allowing a single device to
take data at twice the pixel rate.
• The GMCH’s analog port uses an integrated 400 MHz RAMDAC that can directly drive a
standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit
color at 85 Hz.
• The GMCH’s SDVO ports are each capable of driving a 200-MP pixel rate. Each port is
capable of driving a digital display up to 1600x1200 @ 60Hz. When in dual-channel mode,
the GMCH can drive a flat panel up to 2048x1536 @ 85 Hz or dCRT/HDTV up to
1920x1080 @ 85 Hz.
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant
external device and connector, the GMCH has a high speed interface to a digital display
(e.g., flat panel or digital CRT).
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Table 12-6. Display Port Characteristics
Interface Protocol
Analog
Digital Port B
DVO 1.0
Digital Port C
DVO 1.0
RGB DAC
HSYNC
VSYNC
Yes Enable/Polarity
Yes Enable/Polarity
BLANK
No
No
No
No
Yes1
Yes
Yes
Yes1
Yes
Yes
No1
STALL
Field
Display_Enable
Image Aspect Ratio
Pixel Aspect Ratio
Voltage
Programmable and typically 1.33:1 or 1.78:1
Square
RGB 0.7 V p-p
NA
PCI Express*
PCI Express*
Clock
Differential
Max Rate
400 Mpixel
Analog RGB
DDC1/DDC2B
No
200/400 Mpixel
RGB 8:8:8 YUV 4:4:4
Format
Control Bus
External Device
Connector
DDC2B
TMDS/LVDS Transmitter /TV Encoder
DVI/CVBS/S-Video/Component/SCART
VGA/DVI-I
NOTES:
1. Single signal software selectable between display enable and Blank#.
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12.7.1
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal.
There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the
analog port. The intended target device is for a CRT based monitor with a VGA connector.
Display devices (such as LCD panels) with analog inputs may work satisfactory but no
functionality has been added to the signals to enhance that capability.
Table 12-7. Analog Port Characteristics
Signal
Port Characteristic
Support
Voltage Range
Monitor Sense
Analog Copy Protection
Sync on Green
Voltage
0.7 V p-p only
Analog Compare
RGB
No
No
2.5 V
Enable/Disable
Polarity adjust
Composite Sync Support
Special Flat Panel Sync
Stereo Sync
Port control
HSYNC
VSYNC
VGA or port control
No
No
No
Voltage
Externally buffered to 5V
Through GPIO interface
DDC
Control
12.7.1.1
12.7.1.2
Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that
transforms the digital data from the graphics and video subsystems to analog data for the CRT
monitor. The GMCH’s integrated 400 MHz RAMDAC supports resolutions up to 2048 x 1536 @
85Hz. Three 8-bit DACs provide the RED, GREEN, and BLUE signals to the monitor.
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since
these levels cannot be generated internal to the device, external level shifting buffers are required.
These signals can be polarity adjusted and individually disabled in one of the two possible states.
The sync signals power up disabled in the high state. No composite sync or special flat panel sync
support is included.
12.7.1.3
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display mode
using the VGA CRTC registers. Timings are generated based on the VGA register values and the
timing generator registers are not used.
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12.7.1.4
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the host
system and display. Both configuration and control information can be exchanged allowing plug-
and-play systems to be realized. Support for DDC 1 and 2 is implemented. The GMCH uses the
DDC_CLK and DDC_DATA signals to communicate with the analog monitor. The GMCH
generates these signals at 2.5 V. External pull-up resistors and level shifting circuitry should be
implemented on the board.
The GMCH implements a hardware GMBus controller that can be used to control these signals
allowing for transactions speeds up to 400 kHz.
12.7.2
Digital Display Interface
The GMCH has several options for driving digital displays. The GMCH contains two SDVO
ports that are multiplexed on the PCI Express* x16 Graphics Interface. When an external PCI
Express* x16 Graphics Interface graphics accelerator is not present, the GMCH can use the
multiplexed SDVO ports to provide extra digital display options. These additional digital display
capabilities may be provided through an ADD2 card that is designed to plug in to a PCI Express
connector.
12.7.2.1
Digital Display Channels – SDVOB and SDVOC
The GMCH has the capability to support digital display devices through two SDVO ports. When
an external graphics accelerator is used via the PCI Express* x16 Graphics Interface port, these
SDVO ports are not available.
The shared SDVO ports each support a pixel clock up to 200 MHz and can support a variety of
transmission devices. When using a dual-channel external transmitter, it will be possible to pair
the two SDVO ports in dual-channel mode to support a single digital display with higher
resolutions and refresh rates. In this mode, GMCH is capable of driving pixel clock up to
400 MHz.
SDVO_CTRLDATA is an open-drain signal that will act as a strap during reset to tell the GMCH
whether the interface is a PCI Express interface or an SDVO interface. When implementing
SDVO, either via ADD2 cards or with a down device, a pull-up is placed on this line to signal to
the GMCH to run in SDVO mode and for proper GMBus operation.
12.7.2.2
ADD2 Card
When a 915G Express chipset platform uses a PCI Express* x16 Graphics Interface connector,
the multiplexed SDVO ports may be used via an ADD2 card. The ADD2 card will be designed to
fit a standard PCI Express (x16) connector.
12.7.2.2.1 TMDS Capabilities
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant
external device and connector, the GMCH has a high speed interface to a digital display
(e.g., flat panel or digital CRT). When combining the two multiplexed SDVO ports, the GMCH
can drive a flat panel up to 2048x1536 or a dCRT/HDTV up to 1920x1080. Flat Panel is a fixed
resolution display. The GMCH supports panel fitting in the transmitter, receiver or an external
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device, but has no native panel fitting capabilities. The GMCH will, however, provide unscaled
mode where the display is centered on the panel.
12.7.2.2.2 LVDS Capabilities
The GMCH may use the multiplexed SDVO ports to drive a LVDS transmitter. Flat Panel is a
fixed resolution display. The GMCH supports panel fitting in the transmitter, receiver or an
external device, but has no native panel fitting capabilities. The GMCH will, however, provide
unscaled mode where the display is centered on the panel. The GMCH supports scaling in the
LVDS transmitter through the SDVO stall input pair.
12.7.2.2.3 TV-Out Capabilities
Although traditional TVs are not digital displays, the GMCH uses a digital display channel to
communicate with a TV-Out transmitter. For that reason, the GMCH considers a TV-Output to be
a digital display. GMCH supports NTSC and PAL standard definition formats. The GMCH
generates the proper timing for the external encoder. The external encoder is responsible for
generation of the proper format signal. Since the multiplexed SDVO interface is a
NTSC/PAL/SECAM display on the TV-Out port , it can be configured to be the boot device. It is
necessary to ensure that appropriate BIOS support is provided. If EasyLink is supported in the
GMCH, then this mechanism could be used to interrogate the display device.
The TV-Out interface on the GMCH is addressable as a master device. This allows an external
TV encoder device to drive a pixel clock signal on SDVO_TVClk[+/-] that the GMCH uses as a
reference frequency. The frequency of this clock is dependent on the output resolution required.
Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV encoder chip.
Care must be taken to allow for support of TV sets with high performance de-interlacers and
progressive scan displays connected to by way of a non-interlaced signal. Timing will be
generated with pixel granularity to allow more overscan ratios to be supported.
Direct YUV from Overlay
When source material is in the YUV format and is destined for a device that can take YUV format
data in, it is desired to send the data without converting it to RGB. This avoids the truncation
errors associated with multiple color conversion steps. The common situation will be that the
overlay source data is in the YUV format and will bypass the conversion to RBG as it is sent to
the TV port directly.
Sync Lock Support
Sync lock to the TV will be done using the external encoders PLL combined with the display
phase detector mechanism. The availability of this feature will be used to determine which
external encoder is in use.
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Analog Content Protection
Analog content protection is provided through the external encoder using Macrovision 7.01. DVD
software must verify the presence of a Macrovision TV encoder before playback continues.
Simple attempts to disable the Macrovision operation must be detected.
Connectors
Target TV connectors support includes the CVBS, S-Video, Component, and SCART connectors.
The external TV encoder in use will determine the method of support.
12.7.2.2.4 Control Bus
Communication to SDVO registers and if utilized, ADD2 PROMs and monitor DDCs, are
accomplished by using the SDVO_CTRLDATA and SDVO_CTRLCLK signals through the
SDVO device. These signals run up to 1 MHz and connect directly to the SDVO device. The
SDVO device is then responsible for routing the DDC and PROM data streams to the appropriate
location. Consult SDVO device datasheets for level shifting requirements of these signals.
Intel® SDVO Modes
The port can be dynamically configured in several modes:
• Standard – This mode provides baseline SDVO functionality. The mode supports pixel rates
between 25 and 200 MP/s. It uses three data pairs to transfer RGB data.
• Extended (82915G only) – This mode adds Alpha support to data stream. Extended mode
supports pixel rates between 25 MHz and 200 MP/s. The mode uses four data channels and is
only supported on SDVOB. It leverages channel C (SDVOC) Red pair as the Alpha pair for
channel B (SDVOB).
• Dual Standard – This mode uses standard data streams across both SDVOB and SDVOC.
Both channels can only run in Standard mode (3 data pairs) and each channel supports Pixel
Rates between 25 and 200 MP/s.
⎯ Dual Independent Standard (82915G only) - In Dual Independent Standard mode, each
SDVO channel will see a different pixel stream. The data stream across SDVOB will not
be the same as the data stream across SDVOC. This mode is only supported on the
82915G/82915GV/82915GL/82910GL GMCH.
⎯ Dual Simultaneous Standard - In Dual Simultaneous Standard mode, both SDVO
channels will see the same pixel stream. The data stream across SDVOB will be the same
as the data stream across SDVOC. The display timings will be identical, but the transfer
timings may not be (i.e., SDVOB clocks and data may not be perfectly aligned with
SDVOC clock and data as seen at the SDVO device(s)). Since this uses just a single data
stream, it uses a single pixel pipeline within the GMCH.
12.7.3
Multiple Display Configurations
Microsoft Windows* 2000 and Windows* XP operating systems have enabled support for multi-
monitor display. Since the GMCH has several display ports available for its two pipes, it can
support up to two different images on different display devices. Timings and resolutions for these
two images may be different. The GMCH supports Intel Dual Display Clone, Intel Dual Display
Twin, and Extended Desktop.
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Intel Dual Display Clone uses both display pipes to drive the same content, at the same resolution
and color depth to two different displays. This configuration allows for different refresh rates on
each display.
Intel Dual Display Twin uses one of the display pipes to drive the same content, at the same
resolution, color depth, and refresh rates to two different displays.
Extended Desktop (82915G only) uses both display pipes to drive different content, at potentially
different resolutions, refresh rates, and color depths to two different displays. This configuration
allows for a larger Windows Desktop by using both displays as a work surface.
Note: The GMCH graphics engine is also incapable of operating in parallel with an external PCI
Express graphics device. The GMCH graphics engine can, however, work in conjunction with a
PCI graphics adapter.
12.8
Power Management
Power Management capabilities of the (G)MCH include the following:
• ACPI 1.0b support
• ACPI S0, S3, S4, S5, C0, C1, C2, C3, C4
• Enhanced power management state transitions for increasing time the processor spends in
low power states
• Internal Graphics Display Device Control D0, D1, D2, D3
(82915G/82915GV/82915GL/82910GL GMCH only)
• Graphics Adapter States: D0, D3.
• PCI Express Link States: L0, L0s, L1, L2/L3 Ready, L3
• Conditional memory Self-Refresh during C2, C3, and C4 states
12.9
Clocking
The (G)MCH has a total of 5 PLLs providing the internal clocks. The PLLs are:
• Host PLL – This PLL generates the main core clocks in the host clock domain. The host PLL
is used to generate memory and internal graphics core clocks. It uses the Host clock
(H_CLKIN) as a reference.
• PCI Express PLL (82915G/92915P/82915PL (G)MCH Only) – This PLL generates all PCI
Express related clocks, including the Direct Media Interface that connects to the ICH6. This
PLL uses the 100 MHz (G_CLKIN) as a reference.
• Display PLL A PLL (82915G/92915GV/82915GL/82910GL GMCH Only) – This PLL
generates the internal clocks for Display A. It uses D_REFCLKIN as a reference.
• Display PLL B (82915G/92915GV/82915GL/82910GL GMCH Only) – This PLL generates
the internal clocks for Display B. It uses D_REFCLKIN as a reference.
Figure 12-3 illustrates the various clocks in the platform.
Datasheet
253
Functional Description
R
Figure 12-3. System Clocking Example
DiffPair
ITP
Processor
CK410
56PinSSOP
Memory
Processor Diff Pair
Processor Diff Pair
Processor Diff Pair
MainPLL
SSC
PCIExpress GFX
HPLL
MPLL
x16PCIExp
PCI Express Diff Pair
PCI Express Diff Pair
PCIExpressDif f Pair
PCIExpressDif f Pair
PCIExpressDif f Pair
PCIExpressDif f Pair
PCIExpressDif f Pair
SATADiffPair
DPLL
PCI
Express
PLL
PCIExpressDev
DMI
DPLL
PCIExpressDev
PCIExpressDev
PCIExpressDev
SATA
PLL
SSC
(G)MCH
66MHz
DiffPair
25MHz
DiffPair
PCI
Express
PLL
4 x1PCI Exp
SATA
PLL
96 MHzDOT DiffPair
CK410
48PinSSOP
48 MHzUSB
REF 14MHz
USB PLL
REF 14MHz
SIO LPC
LAN
LCI Bit Clock
25MHz
48/14MHz
PLL
Intel® ICH6
HighDef Audio
BitClock
REF 14MHz
PCI 33MHz
AC97
TPMLPC
PCI 33MHz
PCI 33MHz
OSC
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
PCI 33MHz
FWHLPC
GlueChip
Port80PCI
24MHzBit
Clock
32.768KHz
66/33
Buffer
High DefAudio
66MHz
66MHz
66MHz
25MHz
Oscillator
14.000MHz
§
254
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13 Electrical Characteristics
This chapter contains the (G)MCH absolute maximum electrical ratings, power dissipation values,
and DC characteristics.
13.1
Absolute Maximum Ratings
Table 13-1 lists the (G)MCH’s maximum environmental stress ratings. Functional operation at the
absolute maximum and minimum is neither implied nor guaranteed. Functional operating
parameters are listed in the DC characteristics tables.
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operating beyond the “operating conditions” is not recommended
and extended exposure beyond “operating conditions” may affect reliability.
Table 13-1. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Uni
t
Notes
Tstorage
Storage Temperature
-55
150
°C
1
(G)MCH Core
VCC
1.5 V Core Supply Voltage with respect to VSS
-0.3
1.65
V
Host Interface (533 MHz/800 MHz)
VTT
1.2 V System Bus Input Voltage with respect
to VSS
-0.3
-0.3
1.65
1.65
V
V
VCCA_HPLL
1.5 V Host PLL Analog Supply Voltage with
respect to VSS
DDR Interface (333 MHz/400 MHz)
VCCSM (DDR)
2.6 V DDR System Memory Supply Voltage
with respect to VSS
-0.3
-0.3
4.0
V
V
VCCA_SMPLL
(DDR)
1.5 V System Memory PLL Analog Supply
Voltage with respect to VSS
1.65
DDR2 Interface (400 MHz/533 MHz)
VCCSM (DDR2)
1.8 V DDR2 System Memory Supply Voltage
with Respect to VSS
-0.3
-0.3
4.0
V
V
VCCA_SMPLL
(DDR2)
1.5 V System Memory PLL Analog Supply
Voltage with respect to VSS
1.65
Datasheet
255
Electrical Characteristics
R
Symbol
Parameter
Min
Max
Uni
t
Notes
PCI Express*/Intel® SDVO/DMI Interface
VCC_EXP
1.5 V PCI Express and DMI Supply Voltage
with respect to VSS
-0.3
-0.3
1.65
1.65
V
V
VCCA_EXPPLL
1.5 V PCI Express PLL Analog Supply Voltage
with respect to VSS
RGB/CRT DAC Display Interface (8 bit) (Intel® 82915G/82915GV/82910GL GMCH only)
VCCA_DAC
2.5 V Display DAC Analog Supply Voltage with
respect to VSS
-0.3
-0.3
-0.3
2.65
1.65
1.65
V
V
V
VCCA_DPLLA
VCCA_DPLLB
1.5 V Display PLL A Analog Supply Voltage
with respect to VSS
1.5 V Display PLL B Analog Supply Voltage
with respect to VSS
CMOS Interface
VCC2
2.5 V CMOS Supply Voltage with respect to
VSS
-0.3
2.65
V
NOTES:
1. Possible damage to the (G)MCH may occur if the (G)MCH temperature exceeds 150 °C. Intel does not
guarantee functionality for parts that have exceeded temperatures above 150 °C due to specification
violation.
256
Datasheet
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13.2
Power Characteristics
Table 13-2. Non-Memory Power Characteristics
Symbol
Parameter
Signal Names
Min
Typ
Max
Unit
Notes
IVTT
1.2 V System Bus Supply Bus Current
1.5 V Core Supply Current (Integrated)
1.5 V Core Supply Current (Discrete)
VTT
—
—
—
—
—
—
—
—
1.0
9.7
7.7
A
A
A
1, 4
2,3,4
2,3,4
IVCC
VCC
IVCC
VCC
IVCC_EXP
1.5 V PCI Express and DMI Supply
Current
VCC_EXP
1.4
70
A
IVCCA_DAC
2.5 V Display DAC Analog Supply
Current
VCCA_DAC
—
—
mA
IVCC2
2.5 V CMOS Supply Current
VCC2
—
—
—
—
2
mA
mA
IVCCA_EXPPLL
1.5 V PCI Express and DMI PLL
Analog Supply Current
VCCA_EXPPL
L
45
IVCCA_HPLL
IVCCA_DPLLA
IVCCA_DPLLB
1.5 V Host PLL Supply Current
VCCA_HPLL
—
—
—
—
45
55
mA
mA
1.5 V Display PLL A and PLL B Supply
Current
VCCA_DPLLA
VCCA_DPLLB
NOTES:
1. Estimate is only for max current coming through Chipset’s supply balls
2. Rail includes PLL current
3. Includes Worst case Leakage
4. Calculated for highest frequencies
Datasheet
257
Electrical Characteristics
R
Table 13-3. DDR Power Characteristics
Symbol
Parameter
Min
Max
Unit
Notes
IVCCSM
DDR System Memory Interface (2.6 V) Supply
Current
—
4.1
A
(DDR)
ISUS_VCCSM
(DDR)
DDR System Memory Interface (2.6 V) Standby
Supply Current
—
—
25
10
mA
µA
ISMVREF
DDR System Memory Interface Reference Voltage
(1.3 V) Supply Current
(DDR)
ISUS_SMVREF
DDR System Memory Interface Reference Voltage
(1.3 V) Standby Supply Current
—
—
10
42
µA
ITTRC
DDR System Memory Interface Resistor
mA
Compensation Voltage (2.6 V) Supply Current
(DDR)
ISUS_TTRC
(DDR)
DDR System Memory Interface Resistor
Compensation Voltage (2.6 V) Standby Supply
Current
—
—
0
µA
IVCCA_SMPLL
(DDR)
System Memory PLL Analog (1.5 V) Supply
Current
60
mA
Table 13-4. DDR2 Power Characteristics
Symbol
IVCCSM
Parameter
Min
Max
Unit
Notes
DDR2 System Memory Interface (1.8 V) Supply
Current
—
4.7
A
(DDR2)
ISUS_VCCSM
(DDR2)
ISMVREF
DDR2 System Memory Interface (1.8 V) Standby
Supply Current
—
—
—
—
—
25
10
10
32
0
mA
µA
µA
mA
µA
DDR2 System Memory Interface Reference
Voltage (0.90 V) Supply Current
(DDR2)
ISUS_SMVREF
(DDR2)
ITTRC
DDR2 System Memory Interface Reference
Voltage (0.90 V) Standby Supply Current
DDR2 System Memory Interface Resister
Compensation Voltage (1.8 V) Supply Current
(DDR2)
ISUS_TTRC
(DDR2)
DDR2 System Memory Interface Resister
Compensation Voltage (1.8 V) Standby Supply
Current
IVCCA_SMPLL
(DDR2)
System Memory PLL Analog (1.5 V) Supply
Current
—
60
mA
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Datasheet
Electrical Characteristics
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13.3
Signal Groups
The signal description includes the type of buffer used for the particular signal:
GTL+
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification
for complete details. The (G)MCH integrates most GTL+ termination
resistors.
DDR
DDR System memory (2.6 V CMOS buffers)
DDR2 System memory (1.8 V CMOS buffers)
DDR2
PCI Express/SDVO PCI Express interface signals. These signals are compatible with PCI
Express 1.0a signaling environment AC Specifications. The buffers are
not 3.3 V tolerant.
Analog
Ref
Analog signal interface
Voltage reference signal
HVCMOS
SSTL-2
SSTL-1.8
2.5 V Tolerant High Voltage CMOS buffers
2.6 V Tolerant Stub Series Termination Logic
1.8 V Tolerant Stub Series Termination Logic
Table 13-5. Signal Groups
Signal
Group
Signal Type
Signals
Notes
Host Interface Signal Groups
(a)
GTL+
Input/Outputs
HADS#, HBNR#, HBREQ0#, HDBSY#, HDRDY#,
HDINV[3:0]#, HA[31:3]#, HADSTB[1:0]#, HD[63:0],
HDSTBP[3:0]#, HDSTBN[3:0]#, HHIT#, HHITM#,
HREQ[4:0]#, HLOCK#
(b)
(c)
(d)
GTL+
Common Clock
Outputs
HBPRI#, HCPURST#, HDEFER#, HTRDY#, HRS[2:0]#,
HDPWR#, HEDRDY#
GTL+
Asynchronous
Input
BSEL[2:0], HPCREQ#
Analog Host I/F
Ref & Comp.
Signals
HVREF, HSWING HRCOMP, HSCOMP
PCI-Express Graphics and SDVO Interface Signal Groups
(e)
PCI
PCI Express Interface (82915G/82915P/82915PL
Express/SDVO
Input
(G)MCH only): EXP_RXN[15:0], EXP_RXP[15:0],
SDVO Interface (82915G/82915GV/82915GL/82910GL
GMCH only): SDVO_TVCLKIN#, SDVO_TVCLKIN,
SDVOB_INT#, SDVOB_INT, SDVO_STALL#,
SDVO_STALL, SDVOC_INT#, SDVOC_INT
Datasheet
259
Electrical Characteristics
R
Signal
Group
Signal Type
Signals
Notes
(f)
PCI
PCI Express Interface (82915G/82915P/82915PL
Express/SDVO
Output
(G)MCH only): EXP_TXN(15:0), EXP_TXP(15:0)
SDVO Interface (82915G/82915GV/82915GL/82910GL
GMCH only): SDVOB_RED#, SDVOB_RED,
SDVOB_GREEN#, SDVOB_GREEN, SDVOB_BLUE#,
SDVOB_BLUE, SDVOB_CLK, SDVOB_CLK#,
SDVOC_RED#/SDVOB_ALPHA#,
SDVOC_RED/SDVOB_ALPHA, SDVOC_GREEN#,
SDVOC_GREEN SDVOC_BLUE#, SDVOC_BLUE,
SDVOC_CLK, SDVOC_CLK#
(g)
Analog
EXP_COMP0
EXP_COMPI
PCI Express /
SDVO Interface
Compensation
Signals
DDR Interface Signal Groups
(h)
SSTL- 2
SDQ_A[63:0], SDQ_B[63:0], SDQS_A[7:0],
SDQS_B[7:0]
DDR CMOS I/O
SSTL – 2
(i)
SDM_A[7:0], SDM_B[7:0], SMA_A[13:0], SMA_B[13:0],
SBS_A[1:0], SBS_B[1:0], SRAS_A#, SRAS_B#,
SCAS_A#, SCAS_B#, SWE_A#, SWE_B# SCKE_A[3:0],
SCKE_B[3:0], SCS_A[3:0]#, SCS_B[3:0]#, SCLK_A[5:0],
SCLK_A[5:0]#, SCLK_B[5:0], SCLK_B[5:0]#
DDR CMOS
Output
(j)
DDR Reference
Voltage
SMVREF[1:0] (DDR)
DDR2 Interface Signal Groups (Intel® 82915G/82915GV GMCH and 82915P MCH only)
(k)
SSTL – 1.8
SDQ_A[63:0]#, SDQ_B[63:0]#, SDQS_A[7:0],
SDQS_A[7:0]#, SDQS_B[7:0]#, SDQS_B[7:0]#
DDR2 CMOS
I/O
(l)
SSTL – 1.8
SDM_A[7:0], SDM_B[7:0], SMA[13:0], SMA_B[13:0],
SBS_A[2:0], SBS_B[2:0], SRAS_A#, SRAS_B#,
SCAS_A#, SCAS_B#, SWE_A#, SWE_B#,
DDR2 CMOS
Output
SODT_A[3:0], SODT_B[3:0], SCKE_A[3:0],
SCKE_B[3:0], SCS_A[3:0]#, SCS_B[3:0]#, SCLK_A[5:0],
SCLK_A[5:0]#, SCLK_B[5:0], SCLK_B[5:0]#
(m)
DDR2
SMVREF[1:0] (DDR2)
Reference
Voltage
260
Datasheet
Electrical Characteristics
R
Signal
Group
Signal Type
Signals
Notes
RGB/CRT DAC Display Signal Groups (Intel® 82915G/82915GV/82915GL/82910GL GMCH only)
Analog Current
Outputs
RED, RED#, GREEN, GREEN#, BLUE, BLUE#
REFSET
Analog/Ref
DAC
Current Mode
Reference pin.
DC Spec. not
required
Miscellaneous
CMOS Type
HSYNC, VSYNC
Clocks, Reset, and Miscellaneous Signal Groups
(n)
HVCMOS Input
EXTTS#
(n1)
Miscellaneous
Inputs
RSTIN#, PWROK
(0)
(p)
Low Voltage
Diff. Clock Input
HCLKN, HCLKP, DREFCLKP, DREFCLKN, GCLKP,
GCLKN
HVCMOS I/O
SDVO_CRTLCLK, SDVO_CTRLDATA, DDC_CLK,
DDC_DATA
I/O Buffer Supply Voltages
(q)
1.2 V System
Bus Input
VTT
Supply Voltage
(r)
1.5 V SDVO,
PCI Express
VCC_EXP
Supply Voltages
(s)
(t)
2.6 V DDR
Supply Voltage
VCCSM (DDR)
VCCSM (DDR2)
1.8 V DDR2
Supply Voltage
(u)
(v)
(w)
1.5 V DDR PLL
Analog Supply
Voltage
VCCA_SMPLL (DDR)
VCCA_SMPLL (DDR2)
VCC
1.5 V DDR2
PLL Analog
Supply Voltage
1.5 V (G)MCH
Core Supply
Voltage
2.5 V CMOS
Supply Voltage
(x)
(y)
VCC2
2.5 V RGB/CRT
DAC Display
Analog Supply
Voltage
VCCA_DAC
(z)
PLL Analog
Supply Voltages
VCCA_HPLL, VCCA_EXPPLL, VCCA_DPLLA,
VCCA_DPLLB
Datasheet
261
Electrical Characteristics
R
13.4
DC Characteristics
13.4.1
General DC Characteristics
Table 13-6. DC Characteristics3
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
I/O Buffer Supply Voltage (AC Noise not included)
VCCSM (DDR)
VCCSM (DDR2)
(s)
(t)
DDR I/O Supply Voltage
DDR2 I/O Supply Voltage
2.5
1.7
2.6
1.8
1.5
2.7
1.9
V
V
V
VCCA_SMPLL
(DDR)
(u)
DDR I/O PLL Analog Supply
Voltage
1.425
1.575
VCCA_SMPLL
(DDR2)
(v)
(r)
DDR2 I/O PLL Analog
Supply Voltage
1.425
1.425
1.09
1.5
1.5
1.2
1.5
1.575
1.575
1.26
V
V
V
V
VCC_EXP
SDVO, PCI-Express Supply
Voltage
VTT
(q) System Bus Input Supply
Voltage
VCC
(w) (G)MCH Core Supply
Voltage
1.425
1.575
VCC2
(x)
(y)
CMOS Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
V
V
VCCA_DAC
CRT Display DAC Supply
Voltage
VCCA_HPLL,
VCCA_EXPPLL,
VCCA_DPLLA,
VCCA_DPLLB
(z)
Various PLL’S Analog
Supply Voltages
1.425
1.5
1.575
V
Reference Voltages
HVREF
(d)
Host Address, Data, and
Common Clock Signal
Reference Voltage
2/3 x VTT1– 2% 2/3 x VTT 2/3 x VTT + 2%
V
HSWING
(d)
(j)
Host Compensation
Reference Voltage
1/4 x VTT – 2% 1/4 x VTT
1/4 x VTT
2%
+
V
V
SMVREF (DDR)
DDR Reference Voltage
0.50 x
VCCSM(DDR)
– 0.05
0.50 x
VCCSM
(DDR)
0.50 x
VCCSM(DDR)
+ 0.05
SMVREF
(DDR2)
(m) DDR2 Reference Voltage
0.49 x VCCSM
(DDR2)
0.50 x
VCCSM
(DDR2)
0.51 x VCCSM
(DDR2)
V
Host Interface
VIL_H
(a, c) Host GTL+ Input Low
Voltage
-0.10
0
(2/3 x VTT) –
0.1
V
V
VIH_H
(a, c) Host GTL+ Input High
Voltage
(2/3 x VTT) +
0.1
VTT
VTT + 0.1
262
Datasheet
Electrical Characteristics
R
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
VOL_H
VOH_H
IOL_H
ILEAK_H
CPAD
(a, b) Host GTL+ Output Low
Voltage
—
VTT – 0.1
—
—
—
—
—
—
—
(0.25 x
V
V
V
TT)+0.1
(a, b) Host GTL+ Output High
Voltage
VTT
(a, b) Host GTL+ Output Low
Current
VTTmax
/
mA Rttmin = 54Ω
(1-0.25)Rttmin
(a, c) Host GTL+ Input Leakage
Current
—
20
µA VOL<Vpad<Vtt
(a, c) Host GTL+ Input
Capacitance
2
3.5
2.5
pF
pF
CPCKG
(a, c) Host GTL+ Input
0.90
Capacitance (common clock)
DDR Interface
VIL(DC) (DDR)
(h)
(h)
(h)
(h)
DDR Input Low Voltage
DDR Input High Voltage
DDR Input Low Voltage
DDR Input High Voltage
—
—
—
—
—
SMVREF
(DDR) – 0.15
V
V
V
V
VIH(DC) (DDR)
VIL(AC) (DDR)
VIH(AC) (DDR)
SMVREF
(DDR) + 0.15
—
—
SMVREF
(DDR) – 0.31
SMVREF
—
(DDR) + 0.31
VOL (DDR)
VOH (DDR)
ILeak (DDR)
CI/O (DDR)
(h, i) DDR Output Low Voltage
(h, i) DDR Output High Voltage
—
2.1
—
—
—
—
—
0.4
V
V
1
1
(h)
Input Leakage Current
±10
µA
pF
(h, i) DDR Input/Output Pin
Capacitance
3.0
6.0
DDR2 Interface (Intel® 82915G/82915GV GMCH and 82915P MCH only)
VIL(DC) (DDR2)
VIH(DC) (DDR2)
VIL(AC) (DDR2)
VIH(AC) (DDR2)
(k)
(k)
(k)
(k)
DDR2 Input Low Voltage
DDR2 Input High Voltage
DDR2 Input Low Voltage
DDR2 Input High Voltage
—
—
—
—
—
SMVREF
(DDR2) –
0.125
V
V
V
V
SMVREF
(DDR2) +
0.125
—
—
SMVREF
(DDR2) –
0.250
SMVREF
(DDR2) +
0.250
—
VOL (DDR2)
VOH (DDR2)
ILeak (DDR2)
CI/O (DDR2)
(k, l) DDR2 Output Low Voltage
(k, l) DDR2 Output High Voltage
—
1.5
—
—
—
—
—
0.3
V
V
1
1
(k)
Input Leakage Current
±10
uA
pF
(k, l) DDR2 Input/Output Pin
Capacitance
3.0
6.0
Datasheet
263
Electrical Characteristics
R
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
1.5 V PCI Express Interface 1.0a (includes PCI Express and SDVO)
VTX-DIFF P-P
VTX_CM-ACp
ZTX-DIFF-DC
VRX-DIFF p-p
VRX_CM-ACp
(f)
(f)
Differential Peak to Peak
Output Voltage
0.400
—
—
—
0.600
20
V
mV
Ohms
V
2
AC Peak Common Mode
Output Voltage
(f)
DC Differential TX
Impedance
80
100
—
120
(e)
(e)
Differential Peak to Peak
Input Voltage
0.175
—
0.600
150
3
AC peak Common Mode
Input Voltage
—
mV
Clocks, Reset, and Miscellaneous Signals
VIL
(n)
(n)
(n)
(n)
(o)
(o)
(o)
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
Input Low Voltage
Input High Voltage
Crossing Voltage
—
2.0
—
—
—
0.8
—
V
V
VIH
ILEAK
CIN
—
±10
6.0
µA
pF
V
3.0
—
—
VIL
0
—
VIH
0.660
0.710
0.850
V
VCROSS
0.45 x (VIH
VIL)
–
0.5 x
(VIH – VIL)
0.55 x (VIH
VIL)
–
V
VOL
VOH
IOL
(p)
Output Low Voltage (CMOS
Outputs)
—
2.1
—
—
—
—
—
0.4
—
1
V
V
(p) Output High Voltage (CMOS
Outputs)
(p) Output Low Current (CMOS
Outputs)
mA @VOL_HI max
mA @VOH_HI min
IOH
(p) Output High Current (CMOS
Outputs)
-1
—
VIL
(p) Input Low Voltage
(p) Input High Voltage
(p) Crossing Voltage
(p) Input Capacitance
(n1) Input Low Voltage
(n1) Input High Voltage
(n1) Crossing Voltage
(n1) Input Capacitance
—
1.4
—
—
—
—
—
—
—
—
—
1.1
—
V
V
VIH
ILEAK
CIN
VIL
±10
6.0
µA
pF
V
3.0
—
0.8
VIH
2.0
—
—
V
ILEAK
CIN
±100
5.370
µA
0<Vin<VCC3_3
4.690
pF
NOTES:
1. Determined with 2x (G)MCH DDR/DDR2 Buffer Strength Settings into a 50 Ω to 0.5xVCCSM
(DDR/DDR2) test load.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
Transmitter compliance eye diagram of PCI-E specification and measured over any 250 consecutive TX
Uls.
3. Specified at the measurement point and measured over any 250 consecutive Uls. The test load shown
in Receiver compliance eye diagram of PCI-E specification should be used as the RX device when
taking measurements.
264
Datasheet
Electrical Characteristics
R
13.4.2
RGB/CRT DAC Display DC Characteristics (Intel®
82915G/82915GV/82915GL/82910GL GMCH Only)
Table 13-7. RGB/CRT DAC Display DC Characteristics (Functional Operating Range:
VCCA_DAC = 2.5 V ±5%)
Parameter
Min
Typical
Max
Units
Notes
DAC Resolution
—
8
—
Bits
1
Max Luminance (full-scale)
Min Luminance
0.665
—
0.700
0.000
73.2
—
0.770
—
V
V
1, 2, 4; white video level voltage
1, 3, 4; black video level voltage
LSB Current
—
—
µA
4, 5
1, 6
1, 6
Integral Linearity (INL)
Differential Linearity (DNL)
-1.0
-1.0
+1.0
+1.0
LSB
LSB
—
Video channel-channel
voltage amplitude mismatch
—
—
6
%
7
Monotonicity
Guaranteed
—
NOTES:
1. Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of Analog
Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Max steady-state amplitude
3. Min steady-state amplitude
4. Defined for a double 75-Ohm termination.
5. Set by external reference resistor value.
6. INL and DNL measured and calculated according to VESA Video Signal Standards.
7. Max full-scale voltage difference among R, G, B outputs (percentage of steady-state full-scale voltage).
§
Datasheet
265
Electrical Characteristics
R
266
Datasheet
Ballout and Package Information
R
14 Ballout and Package Information
The (G)MCH ballout supports platforms using DDR2 and DDR system memory. The (G)MCH’s
system memory interface ballout differs between DDR2 and DDR modes.
Note: The DDR and DDR2 signals are multiplexed so that they are supported on the same package.
14.1
DDR2 Ballout
Figure 14-1, Figure 14-2, and Figure 14-3 show the 82915G GMCH ballout for platforms using
DDR2 system memory, as viewed from the top side of the package. Figure 14-1 shows columns
1–12; Figure 14-2 shows columns 13–24; Figure 14-3 shows columns 25–35.
The complete DDR2 ballout for the 82915G/82915GV/82910GL GMCH and 82915P MCH are
listed in Table 14-1 and Table 14-2. Table 14-1 is sorted by ball number. Table 14-2 is sorted
alphabetically by signal name based on the signal names of the 82915G GMCH. Note that the
first table has more entries than the second table. The second table does not include unpopulated
balls whereas the first table does.
Note: Balls that are listed as RSV are Reserved. Board traces should Not be routed to these balls.
Note: Balls that are listed as NC are No Connects. Board traces to these balls are permitted as specified.
Datasheet
267
Ballout and Package Information
R
Figure 14-1. Intel® 82915G GMCH Ballout for DDR2 (Top View: Columns 1–12)
1
2
3
4
5
6
7
8
9
10
11
12
VCCA_
DPLLA
A
NC
VSS
VSS
EXP_TXN3
EXP_TXP3
EXP_TXN1
EXP_TXP1
VSS
GCLKP
B
C
D
E
F
NC
VSS
EXP_TXP5
EXP_TXN5
VSS
EXP_RXP4
VSS
EXP_RXN4
VSS
VSS
VSS
EXP_TXP4
VSS
VSS
VSS
EXP_TXP2
VSS
VSS
EXP_TXN0
VSS
VSS
EXP_TXP0
VSS
GCLKN
VSS
VSS
VSS
EXP_TXN4
EXP_RXP5
EXP_RXN5
VSS
EXP_TXN2
VSS
VSS
VSS
VSS
VSYNC
HSYNC
NC
VSS
EXP_TXP6
EXP_TXN6
EXP_TXP8
EXP_TXN8
VSS
VSS
EXP_RXN3
EXP_RXP3
VSS
VSS
EXP_RXN2
EXP_RXP2
VSS
VSS
EXP_RXP0
EXP_RXN0
VSS
EXP_TXP7
EXP_TXN7
EXP_TXP9
VSS
VSS
VSS
VSS
VSS
G
H
VSS
VSS
EXP_RXN6
VSS
EXP_RXP6
VSS
VSS
VSS
NC
VSS
VSS
EXP_RXN7
EXP_RXP7
VSS
VSS
EXP_RXN1
NC
EXP_
J
K
L
EXP_TXN9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
EXP_RXN8
VSS
EXP_RXP8
VSS
VSS
EXP_RXN9
VSS
VSS
EXP_RXP9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
EXP_RXP1
VSS
NC
NC
NC
TXP10
EXP_
EXP_
TXP11
TXN10
EXP_
EXP_
EXP_
EXP_
VSS
TXN11
TXP12
RXN10
RXP10
EXP_
EXP_TXN1
2
EXP_
EXP_
M
N
P
R
VSS
VSS
VSS
DREFCLKN
TXP13
RXN12
RXP12
EXP_
EXP_
EXP_
EXP_
VSS
VSS
VSS
NC
NC
NC
TXN13
TXP14
RXN13
RXP13
EXP_
EXP_
EXP_
EXP_
EXP_
VSS
VSS
VSS
TXP15
TXN14
RXP14
RXN14
RXP11
EXP_
EXP_
EXP_
EXP_
DMI_TXP0
VSS
VSS
VSS
TXN15
RXN15
RXP15
RXN11
T
U
V
DMI_TXP1
DMI_TXN1
VSS
VSS
VSS
VSS
DMI_TXN0
DMI_TXP2
DMI_TXN2
VSS
VSS
VSS
VSS
VSS
DMI_RXN0
VSS
VSS
VSS
DMI_RXN1
VSS
DMI_RXP1
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
DMI_RXP0
DMI_TXP3
DMI_RXN3
DMI_RXP3
DMI_RXP2
DMI_RXN2
VSS
EXP_
W
Y
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VSS
VSS
NC
NC
COMPI
EXP_
COMPO
AA
AB
AC
AD
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
NC
NC
RSV
SDQ_B20
SM_SLEW
OUT1
AE
AF
SDQ_A5
VSS
SDQ_A4
SDM_A0
SDQ_A0
SDQ_A1
VSS
VSS
SOCOMP1
SOCOMP0
VSS
VSS
SMVREF0
RSTIN#
SMVREF1
VSS
VSS
SDQ_B11
SDQ_B10
VSS
VSS
SM_
VSS
SLEWIN1
AG
AH
SDQS_A0
VSS
SDQS_A0#
SDQ_A7
SDQ_A6
SDQ_A2
SRCOMP0
SDQ_B0
VSS
VSS
NC
PWROK
SDQ_B5
SRCOMP1
VSS
SDQ_B4
SDM_B1
SDQ_B14
SDQ_B15
VSS
VSS
VSS
SDQS_B1#
SDQ_B17
SM_
AJ
SDQ_A12
SDQ_A3
SDQ_A8
SDQ_A13
SDQ_A9
VSS
VSS
SDM_B0
SDQ_B1
VSS
SDQ_B12
VSS
SDQ_B8
VSS
VSS
VSS
SCLK_B4
VSS
SLEWIN0
SM_SLEW
OUT0
AK
VSS
SDQS_B0
SCLK_B1
SDQS_B1
AL
AM
AN
AP
AR
SDM_A1
SDQS_A1#
SCLK_A1
SCLK_A4#
SDQ_A14
NC
SDQS_A1
SCLK_A1#
SCLK_A4
SDQ_A15
VSS
SDQS_B0#
VSS
SDQ_B6
SDQ_B7
SDQ_A20
SDQ_A21
SDQ_A16
5
SDQ_B2
VSS
SDQ_B13
VSS
SDQ_B9
VSS
SCLK_B1#
SCKE_B3
SDQ_A19
SDQ_A18
SCKE_B2
9
VSS
VCCSM
SCKE_B1
SCKE_B0
VCCSM
10
SCLK_B4#
VCCSM
SBS_B2
SMA_B11
SMA_B12
11
SMA_B7
SMA_B5
VSS
NC
NC
1
SDQ_A10
SDQ_A11
SDQ_B3
SDQ_A17
VSS
SDM_A2
SDQS_A2
SDQS_A2#
7
SDQ_A22
VSS
VCCSM
SMA_B9
12
SDQ_A23
8
2
3
4
6
268
Datasheet
Ballout and Package Information
R
Figure 14-2. Intel® 82915G GMCH Ballout for DDR2 (Top View: Columns 13–24)
13
14
15
16
17
18
19
20
21
22
23
24
VCCA_
VCCA_
HPLL
A
B
VCC2
REFSET
EXP_SLR
VSS
VTT
VTT
VTT
VTT
HSWING
HVREF
EXPPLL
VCCA_
DPLLB
VCCA_
SMPLL
VSS
RSV
VSS
VSS
VTT
VTT
VTT
VTT
HRCOMP
VSS
C
D
E
F
VSS
VCCA_DAC
VCCA_DAC
VSSA_DAC
VSS
RSV
GREEN
GREEN#
RED
MTYPE
VSS
NC
VSS
NC
VSS
BSEL2
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VSS
HD40
VTT
VTT
VTT
VTT
VTT
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
HD37
HSCOMP
HD62
BSEL1
RSV
VSS
VTT
VSS
RSV
BSEL0
HD47
VSS
VSS
HDSTBN2#
VSS
NC
G
H
RED#
VSS
HD45
HD46
HCPURST#
VSS
VSS
BLUE
NC
NC
HD41
SDVO_
J
BLUE#
VSS
VSS
RSV
VSS
VSS
VSS
HDSTBP2#
HDINV2#
VSS
VSS
HD35
HD39
HD32
HD34
VSS
HD33
VSS
CTRLCLK
SDVO_
K
EXTTS#
HD44
HD43
HD31
CTRLDATA
L
M
VSS
DREFCLKP
VCC
DDC_DATA
ICH_SYNC#
VCC
VSS
DDC_CLK
VCC
VSS
RSV
VSS
VSS
VSS
HD42
VCC
NC
HD38
VSS
VSS
VSS
VSS
HD36
VCC
VSS
HCLKN
NC
HD30
HCLKP
NC
VSS
VSS
N
VCC
VSS
VCC
NC
P
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
NC
NC
R
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
NC
T
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
U
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
V
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
W
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Y
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
NC
NC
VSS
SDQ_B18
VSS
SDQ_B19
VSS
VSS
SDQ_A30
VSS
SDQ_B28
VSS
VSS
SDQS_B3
VSS
SDQ_B27
VSS
VSS
SDQ_B37
VSS
SDM_B6
VSS
SDQ_B21
SDQ_B16
VSS
RSV_TP0
SDQ_A29
VSS
SDQ_A31
SDQ_A26
VSS
SDQ_B30
SDQ_B31
VSS
SDQ_B23
SDQ_B22
VSS
VSS
SDQS_A3
SDQS_A3#
VSS
VSS
SDQS_B3#
SDM_B3
VSS
VSS
SDQ_B36
SCLK_B0#
VSS
SDQ_B32
SDM_B4
NC
VSS
VSS
VSS
SDM_B2
VSS
RSV_TP1
VSS
SDM_A3
VSS
SDQ_A27
RSV
SDQ_B25
VSS
SDQ_B26
RSV
SCLK_B0
VSS
NC
SDQ_A25
VSS
RSV
RSV
RSV
SDQS_B2
VSS
VSS
RSV_TP3
SMA_B3
SMA_B0
SMA_B2
SMA_B10
SDQ_A28
VSS
RSV
SDQ_B24
VSS
VSS
RSV
SCLK_B3#
VSS
VSS
RSV
SDQS_B2#
VCCSM
RSV_TP2
SMA_B4
SDQ_A24
VCCSM
SRAS_B#
SWE_B#
SDQ_B29
SCKE_A1
SCKE_A2
SCAS_B#
RSV
RSV
SCLK_B3
VCCSM
SMA_A6
SMA_A3
SMA_A2
SCLK_A3#
VCCSM
SMA_B8
SMA_B6
VCCSM
SBS_B1
VCCSM
VCCSM
NC
VCCSM
SBS_A2
VCCSM
SMA_A11
SMA_A9
SMA_A7
VCCSM
SMA_A8
SMA_A5
SCKE_A0
VCCSM
VSS
VCCSM
SMA_B1
SBS_B0
VSS
VCCSM
SCKE_A3
SMA_A12
VSS
VCCSM
SMA_A4
SMA_A1
13
14
15
16
17
18
19
20
21
22
23
24
Datasheet
269
Ballout and Package Information
R
Figure 14-3. Intel® 82915G GMCH Ballout for DDR2 (Top View: Columns 25–35)
25
HD48
HD63
HD58
VSS
26
27
28
29
30
31
32
33
34
NC
35
NC
VSS
HD61
HD57
HD55
VSS
HD53
VSS
A
B
HDINV3#
HD59
HD54
VSS
HDSTBP3#
HDSTBN3#
HD18
HD51
HD17
VSS
HD52
HD15
HD14
VSS
HD13
HD11
NC
HD49
HD56
HD50
HD9
HD12
VSS
C
VSS
HD60
VSS
VSS
HD10
HD8
D
HD25
VSS
VSS
HD24
HD16
VSS
HBPRI#
VSS
HPCREQ#
HREQ4#
HREQ3#
HREQ2#
HADSTB0#
VSS
HREQ1#
VSS
HDSTBP0#
HREQ0#
HD7
HDINV0#
HD6
HDSTBN0#
VSS
E
HDSTBN1#
VSS
HD23
HD22
VSS
F
HD26
VSS
VSS
VSS
HD20
HA6#
VSS
HA7#
VSS
HD5
HD3
G
HDSTBP1#
HDINV1#
VSS
VSS
HD19
HA3#
HD1
VSS
HD4
H
HD27
HD28
HD29
VSS
HD21
HA13#
VSS
HA5#
VSS
HRS2#
VSS
HD0
HD2
HDEFER#
VSS
J
HA14#
VSS
HA4#
HA8#
VSS
HA15#
HLOCK#
HRS0#
HHIT#
K
HA18#
HA20#
HA19#
HA22#
VSS
HA12#
HA16#
VSS
HA9#
HA11#
HADS#
HA21#
VSS
VSS
HDBSY#
HBNR#
HHITM#
VSS
L
VSS
VSS
HA10#
VSS
HDRDY#
VSS
VSS
M
VSS
HADSTB1#
VSS
HA23#
VSS
HA26#
HEDRDY#
HBREQ0#
SDQ_A62
SDM_A7
SDQ_A57
SDQ_A61
SDQ_A50
SDM_A6
RSV
HTRDY#
HRS1#
SDQ_A59
VSS
N
VSS
HA24#
HA25#
VSS
NC
VSS
P
VSS
VSS
HA17#
HA31#
VSS
RSV
RSV
SDQ_A58
VSS
RSV
R
VSS
HA30#
SDQ_B63
VSS
HA27#
VSS
VSS
HA28#
VSS
SDQ_A63
SDQS_A7#
VSS
T
VSS
HA29#
SDQ_B58
VSS
RSV
VSS
SDQS_A7
SDQ_A56
SDQ_A51
VSS
U
VSS
VSS
SDQ_B59
SDQ_B57
VSS
RSV
RSV
RSV
V
VSS
SDQ_B62
SDQ_B60
VSS
SDQS_B7
VSS
VSS
SDM_B7
VSS
VSS
SDQ_A60
SDQ_A55
SDQS_A6#
VSS
W
Y
VSS
SDQS_B7#
SDQ_B56
VSS
RSV
VSS
VSS
VSS
SDQ_B61
RSV
RSV
RSV
SDQ_A54
VSS
SDQS_A6
SCLK_A5#
SCLK_A2
VSS
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
VSS
SDQ_B51
SDQ_B50
VSS
SDQ_B55
VSS
VSS
SDQS_B6
VSS
VSS
SDQ_B54
SCLK_B5
VSS
VSS
SDQS_B6#
NC
VSS
SCLK_A5
SCLK_A2#
SDQ_A49
SDQ_A52
VSS
VSS
VSS
SCLK_B5#
SDQ_B53
VSS
SDQ_A48
SDQ_B52
VSS
RSV
SCLK_B2#
SDQ_B33
VSS
SCLK_B2
VSS
SDQ_B49
SDQ_B48
SDQ_B47
SDQ_A36
VSS
VSS
VSS
SDQ_A43
SDQ_A42
SDQS_A5#
SDQ_A40
SDQ_A44
SDQ_B45
SMA_B13
SODT_B0
SCS_B0#
SODT_A3
VCCSM
SDQ_A53
SDQ_A47
SDM_A5
VSS
SDQ_B43
VSS
VSS
VSS
SDQS_B4#
VSS
VSS
SDQ_B46
SDQS_B5#
VSS
SDQ_B42
SDM_B5
SDQ_B41
SDQ_A35
SDQ_A34
VSS
SDQ_A46
VSS
SDQS_A5
SDQ_A41
VSS
SDQS_B4
SDQ_B39
VSS
SDQS_B5
SDQ_A33
VSS
VSS
SDQ_B35
VSS
SDQ_B44
SDM_A4
SDQS_A4#
VSS
VSS
SDQ_A45
SODT_B3
SODT_B1
SCS_B1#
SCS_B3#
SCS_B2#
NC
SDQ_A32
SDQ_A37
SMA_A10
SBS_A1
SRAS_A#
SBS_A0
27
VSS
SDQ_B40
VSS
VCCSM
SODT_B2
SDQ_B38
VCCSM
SCLK_A3
SCLK_A0#
VSS
SDQ_B34
VCCSM
SCLK_A0
SMA_A0
VCCSM
26
NC
SDQ_A39
SDQS_A4
SDQ_A38
SODT_A0
VSS
VCCSM
SWE_A#
VCCSM
SCS_A2#
28
VCCSM
SODT_A1
SCS_A1#
SCAS_A#
SODT_A2
SCS_A0#
29
SCS_A3#
SMA_A13
VCCSM
31
VCCSM
NC
NC
25
30
32
33
34
35
270
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
A1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
—
—
—
NC
A2
NC
NC
A3
VSS
VSS
VSS
A4
—
—
—
A5
VSS
VSS
VSS
A6
EXP_TXN3
EXP_TXP3
EXP_TXN1
EXP_TXP1
VSS
EXP_TXN3
EXP_TXP3
EXP_TXN1
EXP_TXP1
VSS
SDVOB_CLK-
SDVOB_CLK+
SDVOB_GREEN-
SDVOB_GREEN+
VSS
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
B1
GCLKP
VCCA_DPLLA
VCC2
GCLKP
VCCA_DPLLA
VCC2
GCLKP
VCCA_DPLLA
VCC2
VCCA_EXPPLL
RSV
VCCA_EXPPLL
REFSET
EXP_SLR
VCCA_HPLL
VSS
VCCA_EXPPLL
REFSET
RSV
EXP_SLR
VCCA_HPLL
VSS
VCCA_HPLL
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
HSWING
HVREF
HD48
HSWING
HVREF
HD48
HSWING
HVREF
HD48
VSS
VSS
VSS
HD61
HD61
HD61
HD57
HD57
HD57
HD55
HD55
HD55
VSS
VSS
VSS
HD53
HD53
HD53
—
—
—
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
B2
VSS
VSS
VSS
B3
EXP_RXP4
EXP_RXN4
VSS
EXP_RXP4
EXP_RXN4
VSS
RSV
B4
RSV
B5
VSS
B6
VSS
VSS
VSS
B7
VSS
VSS
VSS
B8
VSS
VSS
VSS
Datasheet
271
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
B9
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
VSS
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
C1
VSS
VSS
GCLKN
VSS
GCLKN
VSS
GCLKN
VSS
VCCA_DPLLB
VSS
VCCA_DPLLB
VSS
VCCA_DPLLB
VSS
RSV
RSV
RSV
VSS
VSS
VSS
VCCA_SMPLL
VSS
VCCA_SMPLL
VSS
VCCA_SMPLL
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
HRCOMP
VSS
HRCOMP
VSS
HRCOMP
VSS
HD63
HD63
HD63
HDINV3#
HD54
HDINV3#
HD54
HDINV3#
HD54
VSS
VSS
VSS
HDSTBP3#
HD51
HDSTBP3#
HD51
HDSTBP3#
HD51
HD52
HD52
HD52
HD15
HD15
HD15
HD13
HD13
HD13
HD11
HD11
HD11
NC
NC
NC
VSS
VSS
VSS
C2
EXP_TXP5
VSS
EXP_TXP5
VSS
SDVOC_GREEN+
VSS
C3
C4
VSS
VSS
VSS
SDVOC_RED-/
SDVOB_ALPHA-
C5
C6
EXP_TXN4
EXP_TXP4
EXP_TXN4
EXP_TXP4
SDVOC_RED+/
SDVOB_ALPHA+
C7
C8
EXP_TXN2
EXP_TXP2
EXP_TXN0
EXP_TXP0
VSS
EXP_TXN2
EXP_TXP2
EXP_TXN0
EXP_TXP0
VSS
SDVOB_BLUE-
SDVOB_BLUE+
SDVOB_RED-
SDVOB_RED+
VSS
C9
C10
C11
C12
C13
C14
—
—
—
VSS
VSS
VSS
RSV
RSV
RSV
272
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
D1
Intel® 82915P MCH1
MTYPE
NC
Intel® 82915G GMCH2
MTYPE
NC
Intel® 82915GV GMCH3
MTYPE
NC
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
—
—
—
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD12
VSS
HD12
VSS
HD12
VSS
—
—
—
D2
EXP_TXN5
VSS
EXP_TXN5
VSS
SDVOC_GREEN-
VSS
D3
D4
VSS
VSS
VSS
D5
EXP_RXP5
VSS
EXP_RXP5
VSS
SDVOC_INT+
VSS
D6
D7
VSS
VSS
VSS
D8
VSS
VSS
VSS
D9
VSS
VSS
VSS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
VSS
VSS
VSS
VSS
VSS
VSS
RSV
VSYNC
VCCA_DAC
GREEN
VSS
VSYNC
VCCA_DAC
GREEN
VSS
RSV
RSV
VSS
VSS
VSS
VSS
BSEL2
VSS
BSEL2
VSS
BSEL2
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
Datasheet
273
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
E1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
HSCOMP
VSS
HSCOMP
VSS
HSCOMP
VSS
VSS
VSS
VSS
HD60
VSS
HD60
HD60
VSS
VSS
HD18
VSS
HD18
HD18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HD10
HD8
HD10
HD10
HD8
HD8
—
—
—
VSS
VSS
VSS
E2
VSS
VSS
VSS
E3
EXP_TXP6
VSS
EXP_TXP6
VSS
SDVOC_BLUE+
VSS
E4
E5
EXP_RXN5
VSS
EXP_RXN5
VSS
SDVOC_INT-
VSS
E6
E7
EXP_RXN3
VSS
EXP_RXN3
VSS
RSV
E8
VSS
E9
EXP_RXN2
VSS
EXP_RXN2
VSS
SDVOC_STALL-
VSS
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
EXP_RXP0
RSV
EXP_RXP0
HSYNC
VCCA_DAC
GREEN#
BSEL1
NC
SDVOC_TVCLKIN+
HSYNC
VCCA_DAC
GREEN#
BSEL1
NC
RSV
RSV
BSEL1
NC
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
HD62
HD25
VSS
HD62
HD62
HD25
HD25
VSS
VSS
HD24
HD16
VSS
HD24
HD24
HD16
HD16
VSS
VSS
HBPRI#
HBPRI#
HBPRI#
274
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
E31
E32
E33
E34
E35
F1
Intel® 82915P MCH1
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
Intel® 82915G GMCH2
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
Intel® 82915GV GMCH3
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
SDVOC_CLK+
VSS
F2
F3
EXP_TXN6
VSS
EXP_TXN6
VSS
SDVOC_BLUE-
VSS
F4
F5
VSS
VSS
VSS
F6
VSS
VSS
VSS
F7
EXP_RXP3
VSS
EXP_RXP3
VSS
RSV
F8
VSS
F9
EXP_RXP2
VSS
EXP_RXP2
VSS
SDVOC_STALL+
VSS
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
G1
EXP_RXN0
NC
EXP_RXN0
NC
SDVOC_TVCLKIN-
NC
RSV
VSSA_DAC
RED
VSSA_DAC
RED
RSV
RSV
RSV
RSV
VSS
VSS
VSS
HD47
HD47
HD47
VSS
VSS
VSS
HDSTBN2#
VTT
HDSTBN2#
VTT
HDSTBN2#
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
NC
NC
NC
VSS
VSS
VSS
HDSTBN1#
HD23
HDSTBN1#
HD23
HDSTBN1#
HD23
HD22
HD22
HD22
VSS
VSS
VSS
VSS
VSS
VSS
HREQ4#
VSS
HREQ4#
VSS
HREQ4#
VSS
HREQ0#
HD6
HREQ0#
HD6
HREQ0#
HD6
VSS
VSS
VSS
EXP_TXN7
VSS
EXP_TXN7
VSS
SDVOC_CLK-
VSS
G2
G3
EXP_TXP8
EXP_TXP8
RSV
Datasheet
275
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
G4
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
G5
EXP_RXN6
EXP_RXP6
VSS
EXP_RXN6
EXP_RXP6
VSS
RSV
G6
RSV
G7
VSS
G8
VSS
VSS
VSS
G9
VSS
VSS
VSS
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
H1
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VSS
VSS
VSS
RSV
RED#
VSS
RED#
VSS
VSS
RSV
RSV
RSV
VSS
VSS
VSS
HD45
HD45
HD45
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
HCPURST#
HD26
HCPURST#
HD26
HCPURST#
HD26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HD20
HD20
HD20
HA6#
HREQ3#
HA7#
HD7
HA6#
HA6#
HREQ3#
HA7#
HREQ3#
HA7#
HD7
HD7
HD5
HD5
HD5
HD3
HD3
HD3
EXP_TXP9
VSS
EXP_TXP9
VSS
RSV
H2
VSS
H3
EXP_TXN8
VSS
EXP_TXN8
VSS
RSV
H4
VSS
H5
VSS
VSS
VSS
H6
VSS
VSS
VSS
H7
EXP_RXN7
EXP_RXP7
VSS
EXP_RXN7
EXP_RXP7
VSS
RSV
H8
RSV
H9
VSS
H10
H11
VSS
VSS
VSS
EXP_RXN1
EXP_RXN1
SDVOB_INT-
276
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
J1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
NC
NC
NC
VSS
VSS
VSS
RSV
BLUE
BLUE
NC
NC
NC
BSEL0
NC
BSEL0
NC
BSEL0
NC
HD46
HD41
HD40
VSS
HD46
HD46
HD41
HD40
VSS
HD41
HD40
VSS
VTT
VTT
VTT
HD37
VSS
HD37
HD37
VSS
VSS
VSS
VSS
VSS
HDSTBP1#
VSS
HDSTBP1#
VSS
HDSTBP1#
VSS
HD19
HA3#
HD19
HD19
HA3#
VSS
HA3#
VSS
VSS
HREQ2#
VSS
HREQ2#
VSS
HREQ2#
VSS
HD1
HD1
HD1
VSS
VSS
VSS
HD4
HD4
HD4
EXP_TXN9
VSS
EXP_TXN9
VSS
RSV
J2
VSS
J3
EXP_TXP10
VSS
EXP_TXP10
VSS
RSV
J4
VSS
J5
EXP_RXN8
EXP_RXP8
VSS
EXP_RXN8
EXP_RXP8
VSS
RSV
J6
RSV
J7
VSS
J8
VSS
VSS
VSS
J9
VSS
VSS
VSS
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
VSS
VSS
VSS
EXP_RXP1
NC
EXP_RXP1
NC
SDVOB_INT+
NC
RSV
SDVO_CTRLCLK
BLUE#
VSS
SDVO_CTRLCLK
BLUE#
VSS
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HDSTBP2#
HDSTBP2#
HDSTBP2#
Datasheet
277
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
K1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
HD35
HD35
HD35
HD32
HD32
HD32
VSS
VSS
VSS
HD33
HD33
HD33
HD27
HD27
HD27
HDINV1#
HD21
HDINV1#
HD21
HDINV1#
HD21
HA13#
HA5#
HA13#
HA5#
HA13#
HA5#
VSS
VSS
VSS
HADSTB0#
HRS2#
HD0
HADSTB0#
HRS2#
HD0
HADSTB0#
HRS2#
HD0
HD2
HD2
HD2
HDEFER#
EXP_TXP11
VSS
HDEFER#
EXP_TXP11
VSS
HDEFER#
RSV
K2
VSS
K3
EXP_TXN10
VSS
EXP_TXN10
VSS
RSV
K4
VSS
K5
VSS
VSS
VSS
K6
VSS
VSS
VSS
K7
EXP_RXN9
EXP_RXP9
VSS
EXP_RXN9
EXP_RXP9
VSS
RSV
K8
RSV
K9
VSS
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
RSV
SDVO_CTRLDATA
VSS
SDVO_CTRLDATA
VSS
VSS
RSV
RSV
RSV
EXTTS#
HD44
EXTTS#
HD44
EXTTS#
HD44
HD43
HD43
HD43
HDINV2#
VSS
HDINV2#
VSS
HDINV2#
VSS
HD39
HD39
HD39
HD34
HD34
HD34
HD31
HD31
HD31
VSS
VSS
VSS
HD28
HD28
HD28
VSS
VSS
VSS
HA14#
HA14#
HA14#
278
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
K28
K29
K30
K31
K32
K33
K34
K35
L1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
HA4#
HA4#
HA4#
HA8#
VSS
HA8#
HA8#
VSS
VSS
VSS
VSS
VSS
HA15#
HRS0#
VSS
HA15#
HRS0#
VSS
HA15#
HRS0#
VSS
EXP_TXN11
VSS
EXP_TXN11
VSS
RSV
L2
VSS
L3
EXP_TXP12
VSS
EXP_TXP12
VSS
RSV
L4
VSS
L5
EXP_RXN10
EXP_RXP10
VSS
EXP_RXN10
EXP_RXP10
VSS
RSV
L6
RSV
L7
VSS
L8
VSS
VSS
VSS
L9
VSS
VSS
VSS
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
VCC
VCC
VCC
VSS
VSS
VSS
NC
NC
NC
VSS
VSS
VSS
RSV
DDC_DATA
VSS
DDC_DATA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HD30
VSS
HD30
HD30
VSS
VSS
HD29
HA18#
VSS
HD29
HD29
HA18#
VSS
HA18#
VSS
HA12#
HA9#
HA12#
HA9#
HA12#
HA9#
VSS
VSS
VSS
HA11#
VSS
HA11#
VSS
HA11#
VSS
HLOCK#
HHIT#
HDBSY#
HLOCK#
HHIT#
HDBSY#
HLOCK#
HHIT#
HDBSY#
Datasheet
279
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
M1
Intel® 82915P MCH1
EXP_TXP13
VSS
Intel® 82915G GMCH2
EXP_TXP13
VSS
Intel® 82915GV GMCH3
RSV
M2
VSS
M3
EXP_TXN12
VSS
EXP_TXN12
VSS
RSV
M4
VSS
M5
VSS
VSS
VSS
M6
VSS
VSS
VSS
M7
EXP_RXN12
EXP_RXP12
VSS
EXP_RXN12
EXP_RXP12
VSS
RSV
M8
RSV
M9
VSS
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
M35
N1
VSS
VSS
VSS
VSS
VSS
VSS
DREFCLKN
DREFCLKP
ICH_SYNC#
RSV
DREFCLKN
DREFCLKP
ICH_SYNC#
DDC_CLK
RSV
DREFCLKN
DREFCLKP
ICH_SYNC#
DDC_CLK
RSV
RSV
VSS
VSS
VSS
HD42
HD42
HD42
HD38
VSS
HD38
HD38
VSS
VSS
HD36
HD36
HD36
HCLKN
HCLKP
VSS
HCLKN
HCLKP
VSS
HCLKN
HCLKP
VSS
VSS
VSS
VSS
HA20#
VSS
HA20#
HA20#
VSS
VSS
HA16#
VSS
HA16#
HA16#
VSS
VSS
HA10#
HADS#
HDRDY#
—
HA10#
HA10#
HADS#
HDRDY#
—
HADS#
HDRDY#
—
VSS
VSS
VSS
HBNR#
EXP_TXN13
VSS
HBNR#
EXP_TXN13
VSS
HBNR#
RSV
N2
VSS
N3
EXP_TXP14
VSS
EXP_TXP14
VSS
RSV
N4
VSS
N5
EXP_RXN13
EXP_RXP13
VSS
EXP_RXN13
EXP_RXP13
VSS
RSV
N6
RSV
N7
VSS
N8
VSS
VSS
VSS
280
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
N9
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
N31
N32
N33
N34
N35
P1
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
HA19#
HADSTB1#
VSS
HA19#
HADSTB1#
VSS
HA19#
HADSTB1#
VSS
HA23#
VSS
HA23#
VSS
HA23#
VSS
HA21#
VSS
HA21#
VSS
HA21#
VSS
HA26#
HTRDY#
HHITM#
EXP_TXP15
VSS
HA26#
HTRDY#
HHITM#
EXP_TXP15
VSS
HA26#
HTRDY#
HHITM#
RSV
P2
VSS
P3
EXP_TXN14
VSS
EXP_TXN14
VSS
RSV
P4
VSS
P5
VSS
VSS
VSS
P6
VSS
VSS
VSS
P7
EXP_RXP14
EXP_RXN14
VSS
EXP_RXP14
EXP_RXN14
VSS
RSV
P8
RSV
P9
VSS
P10
P11
P12
P13
P14
P15
P16
EXP_RXP11
VSS
EXP_RXP11
VSS
RSV
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
Datasheet
281
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
R1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
HA22#
VSS
HA22#
VSS
HA22#
VSS
HA24#
VSS
HA24#
VSS
HA24#
VSS
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
HEDRDY#
HRS1#
VSS
HEDRDY#
HRS1#
VSS
HEDRDY#
HRS1#
VSS
EXP_TXN15
VSS
EXP_TXN15
VSS
RSV
R2
VSS
R3
DMI_TXP0
VSS
DMI_TXP0
VSS
DMI_TXP0
VSS
R4
R5
EXP_RXN15
EXP_RXP15
VSS
EXP_RXN15
EXP_RXP15
VSS
RSV
R6
RSV
R7
VSS
R8
VSS
VSS
VSS
R9
VSS
VSS
VSS
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
EXP_RXN11
VSS
EXP_RXN11
VSS
RSV
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
282
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
T1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HA25#
HA17#
RSV
HA25#
HA17#
RSV
HA25#
HA17#
RSV
RSV
RSV
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
DMI_TXP1
VSS
DMI_TXP1
VSS
DMI_TXP1
VSS
T2
T3
DMI_TXN0
VSS
DMI_TXN0
VSS
DMI_TXN0
VSS
T4
T5
VSS
VSS
VSS
T6
VSS
VSS
VSS
T7
VSS
VSS
VSS
T8
DMI_RXN1
DMI_RXP1
VSS
DMI_RXN1
DMI_RXP1
VSS
DMI_RXN1
DMI_RXP1
VSS
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
VSS
VSS
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
HA30#
HA27#
VSS
HA30#
HA27#
VSS
HA30#
HA27#
VSS
HA31#
VSS
HA31#
VSS
HA31#
VSS
HA28#
VSS
HA28#
VSS
HA28#
VSS
Datasheet
283
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
T33
T34
T35
U1
Intel® 82915P MCH1
SDQ_A62
VSS
Intel® 82915G GMCH2
SDQ_A62
VSS
Intel® 82915GV GMCH3
SDQ_A62
VSS
SDQ_A63
DMI_TXN1
VSS
SDQ_A63
DMI_TXN1
VSS
SDQ_A63
DMI_TXN1
VSS
U2
U3
DMI_TXP2
VSS
DMI_TXP2
VSS
DMI_TXP2
VSS
U4
U5
DMI_RXP0
DMI_RXN0
VSS
DMI_RXP0
DMI_RXN0
VSS
DMI_RXP0
DMI_RXN0
VSS
U6
U7
U8
VSS
VSS
VSS
U9
VSS
VSS
VSS
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
V1
DMI_RXN3
VSS
DMI_RXN3
VSS
DMI_RXN3
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
SDQ_B63
VSS
SDQ_B63
VSS
SDQ_B63
VSS
HA29#
VSS
HA29#
VSS
HA29#
VSS
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
SDM_A7
SDQS_A7
SDQS_A7#
VSS
SDM_A7
SDQS_A7
SDQS_A7#
VSS
SDM_A7
SDQS_A7
SDQS_A7#
VSS
V2
VSS
VSS
VSS
V3
DMI_TXN2
VSS
DMI_TXN2
VSS
DMI_TXN2
VSS
V4
V5
DMI_TXP3
DMI_TXP3
DMI_TXP3
284
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
V6
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
V7
DMI_RXP2
DMI_RXN2
VSS
DMI_RXP2
DMI_RXN2
VSS
DMI_RXP2
DMI_RXN2
VSS
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
W1
DMI_RXP3
VSS
DMI_RXP3
VSS
DMI_RXP3
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B58
SDQ_B59
RSV
SDQ_B58
SDQ_B59
RSV
SDQ_B58
SDQ_B59
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_A57
SDQ_A56
VSS
SDQ_A57
SDQ_A56
VSS
SDQ_A57
SDQ_A56
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
RSV
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
VSS
NC
NC
NC
VCC
VCC
VCC
Datasheet
285
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
Y1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B57
VSS
SDQ_B57
VSS
SDQ_B57
VSS
SDM_B7
VSS
SDM_B7
VSS
SDM_B7
VSS
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPO
VSS
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPO
VSS
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
RSV
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
286
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
Y22
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
Y23
VCC
VCC
VCC
Y24
VCC
VCC
VCC
Y25
VSS
VSS
VSS
Y26
SDQ_B60
VSS
SDQ_B60
VSS
SDQ_B60
VSS
Y27
Y28
SDQS_B7#
VSS
SDQS_B7#
VSS
SDQS_B7#
VSS
Y29
Y30
RSV
RSV
RSV
Y31
VSS
VSS
VSS
Y32
VSS
VSS
VSS
Y33
SDQ_A50
VSS
SDQ_A50
VSS
SDQ_A50
VSS
Y34
Y35
SDQ_A55
VSS
SDQ_A55
VSS
SDQ_A55
VSS
AA1
AA2
VSS
VSS
VSS
AA3
VSS
VSS
VSS
AA4
VSS
VSS
VSS
AA5
VSS
VSS
VSS
AA6
VSS
VSS
VSS
AA7
VSS
VSS
VSS
AA8
VSS
VSS
VSS
AA9
VSS
VSS
VSS
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B56
SDQ_B61
SDQ_B56
SDQ_B61
SDQ_B56
SDQ_B61
Datasheet
287
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AA30
AA31
AA32
AA33
AA34
AA35
AB1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_A54
SDM_A6
SDQS_A6
SDQS_A6#
VCC
SDQ_A54
SDM_A6
SDQS_A6
SDQS_A6#
VCC
SDQ_A54
SDM_A6
SDQS_A6
SDQS_A6#
VCC
AB2
VCC
VCC
VCC
AB3
VCC
VCC
VCC
AB4
VCC
VCC
VCC
AB5
VCC
VCC
VCC
AB6
VCC
VCC
VCC
AB7
VCC
VCC
VCC
AB8
VCC
VCC
VCC
AB9
VCC
VCC
VCC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AC1
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
SDQ_B51
SDQ_B55
VSS
SDQ_B51
SDQ_B55
VSS
SDQ_B51
SDQ_B55
VSS
RSV
RSV
RSV
VSS
VSS
VSS
SDQS_B6
VSS
SDQS_B6
VSS
SDQS_B6
VSS
RSV
RSV
RSV
SCLK_A5#
VSS
SCLK_A5#
VSS
SCLK_A5#
VSS
VCC
VCC
VCC
AC2
VCC
VCC
VCC
288
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AC3
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VCC
VCC
VCC
AC4
VCC
VCC
VCC
AC5
VCC
VCC
VCC
AC6
VCC
VCC
VCC
AC7
VCC
VCC
VCC
AC8
VCC
VCC
VCC
AC9
VCC
VCC
VCC
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AD1
VCC
VCC
VCC
VCC
VCC
VCC
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
SDQ_B50
VSS
SDQ_B50
VSS
SDQ_B50
VSS
SDQ_B54
VSS
SDQ_B54
VSS
SDQ_B54
VSS
SDQS_B6#
VSS
SDQS_B6#
VSS
SDQS_B6#
VSS
VSS
VSS
VSS
SCLK_A5
SCLK_A2
SCLK_A2#
VCC
SCLK_A5
SCLK_A2
SCLK_A2#
VCC
SCLK_A5
SCLK_A2
SCLK_A2#
VCC
AD2
VCC
VCC
VCC
AD3
VCC
VCC
VCC
AD4
VCC
VCC
VCC
AD5
VCC
VCC
VCC
AD6
VCC
VCC
VCC
AD7
VCC
VCC
VCC
AD8
VCC
VCC
VCC
AD9
VCC
VCC
VCC
AD10
VCC
VCC
VCC
Datasheet
289
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AE1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
SDQ_B20
VSS
SDQ_B20
VSS
SDQ_B20
VSS
SDQ_B18
SDQ_B19
VSS
SDQ_B18
SDQ_B19
VSS
SDQ_B18
SDQ_B19
VSS
SDQ_A30
SDQ_B28
VSS
SDQ_A30
SDQ_B28
VSS
SDQ_A30
SDQ_B28
VSS
SDQS_B3
SDQ_B27
VSS
SDQS_B3
SDQ_B27
VSS
SDQS_B3
SDQ_B27
VSS
SDQ_B37
SDM_B6
VSS
SDQ_B37
SDM_B6
VSS
SDQ_B37
SDM_B6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCLK_B5
SCLK_B5#
NC
SCLK_B5
SCLK_B5#
NC
SCLK_B5
SCLK_B5#
NC
SDQ_A48
RSV
SDQ_A48
RSV
SDQ_A48
RSV
—
—
—
VSS
VSS
VSS
SDQ_A49
SDQ_A5
SDQ_A4
SDQ_A0
VSS
SDQ_A49
SDQ_A5
SDQ_A4
SDQ_A0
VSS
SDQ_A49
SDQ_A5
SDQ_A4
SDQ_A0
VSS
AE2
AE3
AE4
AE5
SOCOMP1
VSS
SOCOMP1
VSS
SOCOMP1
VSS
AE6
AE7
SVREF0
SVREF1
VSS
SVREF0
SVREF1
VSS
SVREF0
SVREF1
VSS
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
SM_SLEWOUT1
SDQ_B11
VSS
SM_SLEWOUT1
SDQ_B11
VSS
SM_SLEWOUT1
SDQ_B11
VSS
SDQ_B21
VSS
SDQ_B21
VSS
SDQ_B21
VSS
VSS
VSS
VSS
RSV_TP0
VSS
RSV_TP0
VSS
RSV_TP0
VSS
VSS
VSS
VSS
290
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AF1
Intel® 82915P MCH1
SDQ_A31
VSS
Intel® 82915G GMCH2
SDQ_A31
VSS
Intel® 82915GV GMCH3
SDQ_A31
VSS
VSS
VSS
VSS
SDQ_B30
VSS
SDQ_B30
VSS
SDQ_B30
VSS
VSS
VSS
VSS
SCLK_B2#
SCLK_B2
SDQ_B49
VSS
SCLK_B2#
SCLK_B2
SDQ_B49
VSS
SCLK_B2#
SCLK_B2
SDQ_B49
VSS
SDQ_B53
VSS
SDQ_B53
VSS
SDQ_B53
VSS
SDQ_B52
VSS
SDQ_B52
VSS
SDQ_B52
VSS
SDQ_A43
SDQ_A53
SDQ_A52
VSS
SDQ_A43
SDQ_A53
SDQ_A52
VSS
SDQ_A43
SDQ_A53
SDQ_A52
VSS
AF2
SDM_A0
SDQ_A1
VSS
SDM_A0
SDQ_A1
VSS
SDM_A0
SDQ_A1
VSS
AF3
AF4
AF5
SOCOMP0
VSS
SOCOMP0
VSS
SOCOMP0
VSS
AF6
AF7
RSTIN#
VSS
RSTIN#
VSS
RSTIN#
VSS
AF8
AF9
SM_SLEWIN1
VSS
SM_SLEWIN1
VSS
SM_SLEWIN1
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
SDQ_B10
VSS
SDQ_B10
VSS
SDQ_B10
VSS
SDQ_B16
SDQ_B23
VSS
SDQ_B16
SDQ_B23
VSS
SDQ_B16
SDQ_B23
VSS
SDQ_A29
SDQS_A3
VSS
SDQ_A29
SDQS_A3
VSS
SDQ_A29
SDQS_A3
VSS
SDQ_A26
SDQS_B3#
VSS
SDQ_A26
SDQS_B3#
VSS
SDQ_A26
SDQS_B3#
VSS
SDQ_B31
SDQ_B36
SDQ_B32
SDQ_B33
VSS
SDQ_B31
SDQ_B36
SDQ_B32
SDQ_B33
VSS
SDQ_B31
SDQ_B36
SDQ_B32
SDQ_B33
VSS
Datasheet
291
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG1
Intel® 82915P MCH1
SDQ_B48
SDQ_B43
VSS
Intel® 82915G GMCH2
SDQ_B48
SDQ_B43
VSS
Intel® 82915GV GMCH3
SDQ_B48
SDQ_B43
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A42
SDQ_A47
VSS
SDQ_A42
SDQ_A47
VSS
SDQ_A42
SDQ_A47
VSS
SDQS_A0
SDQS_A0#
SDQ_A6
SRCOMP0
VSS
SDQS_A0
SDQS_A0#
SDQ_A6
SRCOMP0
VSS
SDQS_A0
SDQS_A0#
SDQ_A6
SRCOMP0
VSS
AG2
AG3
AG4
AG5
AG6
NC
NC
NC
AG7
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
VSS
VSS
VSS
SDQ_B22
VSS
SDQ_B22
VSS
SDQ_B22
VSS
VSS
VSS
VSS
SDQS_A3#
VSS
SDQS_A3#
VSS
SDQS_A3#
VSS
VSS
VSS
VSS
SDM_B3
VSS
SDM_B3
VSS
SDM_B3
VSS
VSS
VSS
VSS
SCLK_B0#
SDM_B4
VSS
SCLK_B0#
SDM_B4
VSS
SCLK_B0#
SDM_B4
VSS
SDQS_B4#
SDQ_B47
VSS
SDQS_B4#
SDQ_B47
VSS
SDQS_B4#
SDQ_B47
VSS
VSS
VSS
VSS
SDQ_B46
SDQ_B42
SDQ_A46
SDQS_A5#
SDM_A5
SDQ_B46
SDQ_B42
SDQ_A46
SDQS_A5#
SDM_A5
SDQ_B46
SDQ_B42
SDQ_A46
SDQS_A5#
SDM_A5
292
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AG35
AH1
Intel® 82915P MCH1
SDQS_A5
VSS
Intel® 82915G GMCH2
SDQS_A5
VSS
Intel® 82915GV GMCH3
SDQS_A5
VSS
AH2
SDQ_A7
SDQ_A2
SDQ_B0
VSS
SDQ_A7
SDQ_A2
SDQ_B0
VSS
SDQ_A7
SDQ_A2
SDQ_B0
VSS
AH3
AH4
AH5
AH6
VSS
VSS
VSS
AH7
SDQ_B5
VSS
SDQ_B5
VSS
SDQ_B5
VSS
AH8
AH9
SDM_B1
SDQS_B1#
VSS
SDM_B1
SDQS_B1#
VSS
SDM_B1
SDQS_B1#
VSS
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
AH35
AJ1
SDQ_B17
SDM_B2
VSS
SDQ_B17
SDM_B2
VSS
SDQ_B17
SDM_B2
VSS
RSV_TP1
SDM_A3
VSS
RSV_TP1
SDM_A3
VSS
RSV_TP1
SDM_A3
VSS
SDQ_A27
SDQ_B25
VSS
SDQ_A27
SDQ_B25
VSS
SDQ_A27
SDQ_B25
VSS
SDQ_B26
SCLK_B0
VSS
SDQ_B26
SCLK_B0
VSS
SDQ_B26
SCLK_B0
VSS
NC
NC
NC
SDQS_B4
VSS
SDQS_B4
VSS
SDQS_B4
VSS
SDQ_A36
SDQS_B5
VSS
SDQ_A36
SDQS_B5
VSS
SDQ_A36
SDQS_B5
VSS
SDQS_B5#
SDM_B5
VSS
SDQS_B5#
SDM_B5
VSS
SDQS_B5#
SDM_B5
VSS
SDQ_A40
VSS
SDQ_A40
VSS
SDQ_A40
VSS
SDQ_A41
SDQ_A12
SDQ_A3
SDQ_A13
VSS
SDQ_A41
SDQ_A12
SDQ_A3
SDQ_A13
VSS
SDQ_A41
SDQ_A12
SDQ_A3
SDQ_A13
VSS
AJ2
AJ3
AJ4
AJ5
SDM_B0
SDQ_B1
SDQ_B12
SDM_B0
SDQ_B1
SDQ_B12
SDM_B0
SDQ_B1
SDQ_B12
AJ6
AJ7
Datasheet
293
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AJ8
Intel® 82915P MCH1
SDQ_B8
VSS
Intel® 82915G GMCH2
SDQ_B8
VSS
Intel® 82915GV GMCH3
SDQ_B8
VSS
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AK1
VSS
VSS
VSS
SCLK_B4
SM_SLEWIN0
VSS
SCLK_B4
SM_SLEWIN0
VSS
SCLK_B4
SM_SLEWIN0
VSS
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A25
RSV
SDQ_A25
RSV
SDQ_A25
RSV
VSS
VSS
VSS
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_B39
SDQ_B35
VSS
SDQ_B39
SDQ_B35
VSS
SDQ_B39
SDQ_B35
VSS
SDQ_A33
SDQ_B44
VSS
SDQ_A33
SDQ_B44
VSS
SDQ_A33
SDQ_B44
VSS
SDQ_B41
VSS
SDQ_B41
VSS
SDQ_B41
VSS
SDQ_A44
SDQ_A45
VSS
SDQ_A44
SDQ_A45
VSS
SDQ_A44
SDQ_A45
VSS
VSS
VSS
VSS
AK2
SDQ_A8
SDQ_A9
VSS
SDQ_A8
SDQ_A9
VSS
SDQ_A8
SDQ_A9
VSS
AK3
AK4
AK5
SDQS_B0
VSS
SDQS_B0
VSS
SDQS_B0
VSS
AK6
AK7
VSS
VSS
VSS
AK8
VSS
VSS
VSS
AK9
SCLK_B1
SDQS_B1
VSS
SCLK_B1
SDQS_B1
VSS
SCLK_B1
SDQS_B1
VSS
AK10
AK11
AK12
AK13
AK14
AK15
SM_SLEWOUT0
SDQS_B2
VSS
SM_SLEWOUT0
SDQS_B2
VSS
SM_SLEWOUT0
SDQS_B2
VSS
RSV_TP3
RSV_TP3
RSV_TP3
294
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AK35
AL1
Intel® 82915P MCH1
SDQ_A28
VSS
Intel® 82915G GMCH2
SDQ_A28
VSS
Intel® 82915GV GMCH3
SDQ_A28
VSS
RSV
RSV
RSV
SDQ_B24
VSS
SDQ_B24
VSS
SDQ_B24
VSS
RSV
RSV
RSV
SCLK_B3#
VSS
SCLK_B3#
VSS
SCLK_B3#
VSS
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A32
VSS
SDQ_A32
VSS
SDQ_A32
VSS
SDM_A4
VSS
SDM_A4
VSS
SDM_A4
VSS
SDQ_A35
SDQ_B40
SDQ_B45
SODT_B3
VCCSM
SDM_A1
SDQS_A1#
SDQS_A1
SDQS_B0#
SDQ_B6
SDQ_B2
SDQ_B13
SDQ_B9
SCLK_B1#
VSS
SDQ_A35
SDQ_B40
SDQ_B45
SODT_B3
VCCSM
SDM_A1
SDQS_A1#
SDQS_A1
SDQS_B0#
SDQ_B6
SDQ_B2
SDQ_B13
SDQ_B9
SCLK_B1#
VSS
SDQ_A35
SDQ_B40
SDQ_B45
SODT_B3
VCCSM
SDM_A1
SDQS_A1#
SDQS_A1
SDQS_B0#
SDQ_B6
SDQ_B2
SDQ_B13
SDQ_B9
SCLK_B1#
VSS
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
SCLK_B4#
SMA_B7
VSS
SCLK_B4#
SMA_B7
VSS
SCLK_B4#
SMA_B7
VSS
SDQS_B2#
SMA_B3
VSS
SDQS_B2#
SMA_B3
VSS
SDQS_B2#
SMA_B3
VSS
SDQ_A24
SDQ_B29
VSS
SDQ_A24
SDQ_B29
VSS
SDQ_A24
SDQ_B29
VSS
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
SCLK_B3
SCLK_B3
SCLK_B3
Datasheet
295
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AM1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
SMA_A2
SMA_A2
SMA_A2
SDQ_B38
SDQ_B34
SDQ_A37
NC
SDQ_B38
SDQ_B34
SDQ_A37
NC
SDQ_B38
SDQ_B34
SDQ_A37
NC
SDQS_A4#
SDQ_A39
SDQ_A34
VSS
SDQS_A4#
SDQ_A39
SDQ_A34
VSS
SDQS_A4#
SDQ_A39
SDQ_A34
VSS
SMA_B13
SODT_B1
SODT_B2
SMA_B13
SODT_B1
SODT_B2
SMA_B13
SODT_B1
SODT_B2
AM2
SCLK_A1
SCLK_A1#
VSS
SCLK_A1
SCLK_A1#
VSS
SCLK_A1
SCLK_A1#
VSS
AM3
AM4
AM5
SDQ_B7
VSS
SDQ_B7
VSS
SDQ_B7
VSS
AM6
AM7
VSS
VSS
VSS
AM8
VSS
VSS
VSS
AM9
SCKE_B3
VCCSM
VCCSM
SMA_B5
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SCKE_A1
VCCSM
VCCSM
SMA_A11
VCCSM
VCCSM
SCLK_A3#
VCCSM
VCCSM
SMA_A10
VCCSM
VSS
SCKE_B3
VCCSM
VCCSM
SMA_B5
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SCKE_A1
VCCSM
VCCSM
SMA_A11
VCCSM
VCCSM
SCLK_A3#
VCCSM
VCCSM
SMA_A10
VCCSM
VSS
SCKE_B3
VCCSM
VCCSM
SMA_B5
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SCKE_A1
VCCSM
VCCSM
SMA_A11
VCCSM
VCCSM
SCLK_A3#
VCCSM
VCCSM
SMA_A10
VCCSM
VSS
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
SDQS_A4
VSS
SDQS_A4
VSS
SDQS_A4
VSS
296
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AM32
AM33
AM34
AM35
AN1
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VCCSM
VCCSM
VCCSM
SODT_B0
SCS_B1#
—
SODT_B0
SCS_B1#
—
SODT_B0
SCS_B1#
—
VSS
VSS
VSS
AN2
SCLK_A4#
SCLK_A4
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A22
SDQ_A19
SCKE_B1
SBS_B2
SCLK_A4#
SCLK_A4
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A22
SDQ_A19
SCKE_B1
SBS_B2
SCLK_A4#
SCLK_A4
SDQ_A10
SDQ_A20
SDQ_B3
AN3
AN4
AN5
AN6
AN7
SDM_A2
SDQ_A22
SDQ_A19
SCKE_B1
SBS_B2
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AP1
SMA_B8
RSV_TP2
SMA_B2
SBS_B1
SRAS_B#
SCKE_A2
NC
SMA_B8
RSV_TP2
SMA_B2
SBS_B1
SRAS_B#
SCKE_A2
NC
SMA_B8
RSV_TP2
SMA_B2
SBS_B1
SRAS_B#
SCKE_A2
NC
SBS_A2
SMA_A9
SMA_A8
SMA_A6
—
SBS_A2
SMA_A9
SMA_A8
SMA_A6
—
SBS_A2
SMA_A9
SMA_A8
SMA_A6
—
SCLK_A3
SCLK_A0
SBS_A1
SWE_A#
SCAS_A#
SDQ_A38
SCS_A3#
SODT_A1
SCS_B0#
SCS_B3#
VCCSM
NC
SCLK_A3
SCLK_A0
SBS_A1
SWE_A#
SCAS_A#
SDQ_A38
SCS_A3#
SODT_A1
SCS_B0#
SCS_B3#
VCCSM
NC
SCLK_A3
SCLK_A0
SBS_A1
SWE_A#
SCAS_A#
SDQ_A38
SCS_A3#
SODT_A1
SCS_B0#
SCS_B3#
VCCSM
NC
AP2
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A14
SDQ_A15
SDQ_A11
AP3
AP4
Datasheet
297
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AP5
Intel® 82915P MCH1
SDQ_A21
SDQ_A17
SDQS_A2
VSS
Intel® 82915G GMCH2
SDQ_A21
SDQ_A17
SDQS_A2
VSS
Intel® 82915GV GMCH3
SDQ_A21
SDQ_A17
SDQS_A2
VSS
AP6
AP7
AP8
AP9
SDQ_A18
SCKE_B0
SMA_B11
VCCSM
SDQ_A18
SCKE_B0
SMA_B11
VCCSM
SDQ_A18
SCKE_B0
SMA_B11
VCCSM
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AR1
SMA_B6
SMA_B4
SMA_B10
VCCSM
SMA_B6
SMA_B4
SMA_B10
VCCSM
SMA_B6
SMA_B4
SMA_B10
VCCSM
SWE_B#
SCAS_B#
SCKE_A0
VCCSM
SWE_B#
SCAS_B#
SCKE_A0
VCCSM
SWE_B#
SCAS_B#
SCKE_A0
VCCSM
SMA_A7
SMA_A5
SMA_A3
VCCSM
SMA_A7
SMA_A5
SMA_A3
VCCSM
SMA_A7
SMA_A5
SMA_A3
VCCSM
SCLK_A0#
SMA_A0
SRAS_A#
VCCSM
SCLK_A0#
SMA_A0
SRAS_A#
VCCSM
SCLK_A0#
SMA_A0
SRAS_A#
VCCSM
SODT_A2
SODT_A0
SMA_A13
SCS_A1#
SODT_A3
SCS_B2#
NC
SODT_A2
SODT_A0
SMA_A13
SCS_A1#
SODT_A3
SCS_B2#
NC
SODT_A2
SODT_A0
SMA_A13
SCS_A1#
SODT_A3
SCS_B2#
NC
NC
NC
NC
AR2
NC
NC
NC
AR3
VSS
VSS
VSS
AR4
AR5
SDQ_A16
VSS
SDQ_A16
VSS
SDQ_A16
VSS
AR6
AR7
SDQS_A2#
SDQ_A23
SCKE_B2
VCCSM
SDQS_A2#
SDQ_A23
SCKE_B2
VCCSM
SDQS_A2#
SDQ_A23
SCKE_B2
VCCSM
AR8
AR9
AR10
AR11
AR12
SMA_B12
SMA_B9
SMA_B12
SMA_B9
SMA_B12
SMA_B9
298
Datasheet
Ballout and Package Information
R
Table 14-1. GMCH/MCH Ballout for DDR2 Systems (Sorted by Ball Number)
Ball #
AR13
AR14
AR15
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
Intel® 82915P MCH1
Intel® 82915G GMCH2
Intel® 82915GV GMCH3
VSS
VSS
VSS
VCCSM
SMA_B1
SBS_B0
VSS
VCCSM
SMA_B1
SBS_B0
VSS
VCCSM
SMA_B1
SBS_B0
VSS
VCCSM
SCKE_A3
SMA_A12
VSS
VCCSM
SCKE_A3
SMA_A12
VSS
VCCSM
SCKE_A3
SMA_A12
VSS
VCCSM
SMA_A4
SMA_A1
VSS
VCCSM
SMA_A4
SMA_A1
VSS
VCCSM
SMA_A4
SMA_A1
VSS
VCCSM
SBS_A0
SCS_A2#
SCS_A0#
VSS
VCCSM
SBS_A0
SCS_A2#
SCS_A0#
VSS
VCCSM
SBS_A0
SCS_A2#
SCS_A0#
VSS
VCCSM
—
VCCSM
—
VCCSM
—
VCCSM
NC
VCCSM
NC
VCCSM
NC
NC
NC
NC
NOTES:
1. DDR2, PCI Express* x16 Graphics Interface, No DAC, No Intel® SDVO
2. DDR2, PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
3. DDR2, No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
Datasheet
299
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
H14
J14
H16
E15
D17
M15
L14
U6
RSV
BLUE
BLUE
RSV
BLUE#
BLUE#
BSEL0
BSEL0
BSEL0
BSEL1
BSEL1
BSEL1
BSEL2
BSEL2
BSEL2
RSV
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
EXP_RXN0
EXP_RXN1
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
SDVOC_TVCLKIN-
SDVOB_INT-
RSV
RSV
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
EXP_RXN0
EXP_RXN1
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
T8
V8
U10
U5
T9
V7
V10
T3
U1
V3
W5
R3
T1
U3
V5
M12
M13
W10
Y10
F11
H11
L5
RSV
R10
M7
N5
RSV
RSV
RSV
P8
RSV
R5
SDVOC_STALL-
RSV
E9
E7
RSV
B4
SDVOC_INT-
RSV
E5
G5
RSV
H7
RSV
J5
RSV
K7
300
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
EXP_RXP0
EXP_RXP1
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_SLR
Intel® 82915G GMCH 2
EXP_RXP0
EXP_RXP1
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_SLR
Intel® 82915GV GMCH 3
Ball #
E11
J11
L6
SDVOC_TVCLKIN+
SDVOB_INT+
RSV
RSV
P10
M8
N6
P7
RSV
RSV
RSV
RSV
R6
F9
SDVOC_STALL+
RSV
F7
RSV
B3
SDVOC_INT+
RSV
D5
G6
H8
J6
RSV
RSV
RSV
K8
RSV
A16
C9
A8
EXP_TXN0
EXP_TXN1
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXN2
EXP_TXN3
EXP_TXN0
EXP_TXN1
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXN2
EXP_TXN3
SDVOB_RED-
SDVOB_GREEN-
RSV
K3
RSV
L1
RSV
M3
N1
P3
RSV
RSV
RSV
R1
C7
A6
SDVOB_BLUE-
SDVOB_CLK-
SDVOC_RED-/
SDVOB_ALPHA-
EXP_TXN4
EXP_TXN4
C5
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXP0
EXP_TXP1
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
EXP_TXP2
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXP0
EXP_TXP1
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
EXP_TXP2
SDVOC_GREEN-
SDVOC_BLUE-
SDVOC_CLK-
RSV
D2
F3
G1
H3
J1
RSV
SDVOB_RED+
SDVOB_GREEN+
RSV
C10
A9
J3
RSV
K1
L3
RSV
RSV
M1
N3
P1
C8
RSV
RSV
SDVOB_BLUE+
Datasheet
301
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
EXP_TXP3
EXP_TXP3
SDVOB_CLK+
A7
SDVOC_RED+/
SDVOB_ALPHA+
EXP_TXP4
EXP_TXP4
C6
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXTTS#
GCLKN
GCLKP
RSV
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXTTS#
GCLKN
GCLKP
GREEN
GREEN#
HA3#
SDVOC_GREEN+
SDVOC_BLUE+
SDVOC_CLK+
RSV
C2
E3
F1
G3
RSV
H1
EXTTS#
GCLKN
GCLKP
GREEN
GREEN#
HA3#
K16
B11
A11
D14
E14
H29
K29
J29
G30
G32
K30
L29
M30
L31
L28
J28
K27
K33
M28
R29
L26
N26
M26
N31
P26
N29
P28
R28
N33
T27
T31
U28
T26
T29
M31
RSV
HA3#
HA4#
HA4#
HA4#
HA5#
HA5#
HA5#
HA6#
HA6#
HA6#
HA7#
HA7#
HA7#
HA8#
HA8#
HA8#
HA9#
HA9#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
302
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
Intel® 82915G GMCH 2
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
Intel® 82915GV GMCH 3
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
Ball #
J31
N27
M35
E30
R33
M22
M23
G24
J33
HD1
HD1
HD1
H33
J34
HD2
HD2
HD2
HD3
HD3
HD3
G35
H35
G34
F34
G33
D34
C33
D33
B34
C34
B33
C32
B32
E28
C30
D29
H28
G29
J27
HD4
HD4
HD4
HD5
HD5
HD5
HD6
HD6
HD6
HD7
HD7
HD7
HD8
HD8
HD8
HD9
HD9
HD9
HD10
HD10
HD10
HD11
HD11
HD11
HD12
HD12
HD12
HD13
HD13
HD13
HD14
HD14
HD14
HD15
HD15
HD15
HD16
HD16
HD16
HD17
HD17
HD17
HD18
HD18
HD18
HD19
HD19
HD19
HD20
HD20
HD20
HD21
HD21
HD21
HD22
HD22
HD22
F28
F27
E27
E25
G25
J25
HD23
HD23
HD23
HD24
HD24
HD24
HD25
HD25
HD25
HD26
HD26
HD26
HD27
HD27
HD27
HD28
HD28
HD28
K25
L25
L23
K23
J22
HD29
HD29
HD29
HD30
HD30
HD30
HD31
HD31
HD31
HD32
HD32
HD32
HD33
HD33
HD33
J24
HD34
HD34
HD34
K22
Datasheet
303
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
J21
HD35
HD35
HD35
HD36
HD36
HD36
M21
H23
M19
K21
H20
H19
M18
K18
K17
G18
H18
F17
A25
C27
C31
B30
B31
A31
B27
A29
C28
A28
C25
C26
D27
A27
E24
B25
L35
J35
HD37
HD37
HD37
HD38
HD38
HD38
HD39
HD39
HD39
HD40
HD40
HD40
HD41
HD41
HD41
HD42
HD42
HD42
HD43
HD43
HD43
HD44
HD44
HD44
HD45
HD45
HD45
HD46
HD46
HD46
HD47
HD47
HD47
HD48
HD48
HD48
HD49
HD49
HD49
HD50
HD50
HD50
HD51
HD51
HD51
HD52
HD52
HD52
HD53
HD53
HD53
HD54
HD54
HD54
HD55
HD55
HD55
HD56
HD56
HD56
HD57
HD57
HD57
HD58
HD58
HD58
HD59
HD59
HD59
HD60
HD60
HD60
HD61
HD61
HD61
HD62
HD62
HD62
HD63
HD63
HD63
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
E34
J26
K19
B26
M32
E35
F26
F19
C29
E33
H26
J19
304
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
HDSTBP3#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HSCOMP
HSWING
RSV
Intel® 82915G GMCH 2
HDSTBP3#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HSCOMP
HSWING
HSYNC
HTRDY#
HVREF
ICH_SYNC#
MTYPE
NC
Intel® 82915GV GMCH 3
HDSTBP3#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HSCOMP
HSWING
HSYNC
HTRDY#
HVREF
ICH_SYNC#
MTYPE
NC
Ball #
B29
P33
L34
N35
L33
E31
B23
F33
E32
H31
G31
F31
K34
P34
J32
D24
A23
E12
HTRDY#
HVREF
ICH_SYNC#
MTYPE
NC
N34
A24
M14
C15
A2
NC
NC
NC
A34
NC
NC
NC
A35
NC
NC
NC
AA12
AB12
AC23
AC24
AD30
AG6
AH24
AJ14
AL28
AN19
AP1
AP35
AR1
AR2
AR34
AR35
B1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B35
Datasheet
305
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
C16
E16
NC
NC
NC
NC
NC
NC
NC
NC
NC
F12
NC
NC
NC
F24
NC
NC
NC
G12
H12
H15
H17
J12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K12
NC
NC
NC
L12
NC
NC
NC
L19
NC
NC
NC
N12
N22
N23
N24
P12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P23
NC
NC
NC
P24
NC
NC
NC
P30
NC
NC
NC
R12
R24
T12
NC
NC
NC
NC
NC
NC
NC
NC
NC
U12
V12
NC
NC
NC
NC
NC
NC
W12
Y12
NC
NC
NC
PWROK
RSV
RSV
RSV
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
AG7
F14
G14
A15
AF7
AA30
AA31
AB29
AB33
AC12
AC13
AC14
AC15
AC16
AC17
AC18
306
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
AC19
AC20
AC21
AC22
AD32
AJ18
AJ20
AJ21
AJ23
AJ24
AK18
AK21
AK24
AL20
AL21
B15
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
C14
RSV
RSV
RSV
F15
RSV
RSV
RSV
G16
RSV
RSV
RSV
K15
RSV
RSV
RSV
M16
RSV
RSV
RSV
R30
RSV
RSV
RSV
R31
RSV
RSV
RSV
R35
RSV
RSV
RSV
U30
RSV
RSV
RSV
V30
RSV
RSV
RSV
V31
RSV
RSV
RSV
V32
RSV
RSV
RSV
Y30
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
SBS_A1
SBS_A2
SBS_B0
SBS_B1
SBS_B2
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
SBS_A1
SBS_A2
SBS_B0
SBS_B1
SBS_B2
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
SBS_A1
SBS_A2
SBS_B0
SBS_B1
SBS_B2
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
AE16
AH15
AN14
AK15
AR27
AN27
AN20
AR16
AN16
AN11
AN29
AP18
AP19
AM18
Datasheet
307
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
Intel® 82915G GMCH 2
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
Intel® 82915GV GMCH 3
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
Ball #
AN18
AR19
AP10
AN10
AR9
AM9
AN26
AP25
AM2
AM3
AC34
AC35
AN25
AM24
AN3
AN2
AC33
AB34
AH22
AG23
AK9
AL9
AE26
AE25
AL23
AK22
AJ11
AL11
AD28
AD29
AR29
AP32
AR28
AN31
AN33
AM34
AP34
AN34
AF2
SDM_A1
SDM_A1
SDM_A1
AL1
SDM_A2
SDM_A2
SDM_A2
AN7
SDM_A3
SDM_A3
SDM_A3
AH16
AK29
SDM_A4
SDM_A4
SDM_A4
308
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
Intel® 82915G GMCH 2
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
Intel® 82915GV GMCH 3
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
Ball #
AG34
AA33
U33
AJ5
AH9
AH13
AG20
AG24
AH31
AD24
W31
AE3
SDQ_A1
SDQ_A1
SDQ_A1
AF3
SDQ_A2
SDQ_A2
SDQ_A2
AH3
AJ2
SDQ_A3
SDQ_A3
SDQ_A3
SDQ_A4
SDQ_A4
SDQ_A4
AE2
SDQ_A5
SDQ_A5
SDQ_A5
AE1
SDQ_A6
SDQ_A6
SDQ_A6
AG3
AH2
AK2
SDQ_A7
SDQ_A7
SDQ_A7
SDQ_A8
SDQ_A8
SDQ_A8
SDQ_A9
SDQ_A9
SDQ_A9
AK3
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
AN4
AP4
AJ1
AJ3
AP2
AP3
AR5
AP6
AP9
AN9
AN5
AP5
AN8
AR8
AL17
AJ17
AF19
AH18
AK16
AF16
AD17
AE19
Datasheet
309
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
Intel® 82915G GMCH 2
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
Intel® 82915GV GMCH 3
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
Ball #
AK27
AJ28
AL31
AK31
AH27
AL27
AN30
AL30
AH33
AH35
AF33
AE33
AJ33
AJ34
AG32
AF34
AD31
AD35
Y33
W34
AE35
AE34
AA32
Y35
V34
V33
R32
R34
W35
W33
T33
T35
AH4
SDQ_B1
SDQ_B1
SDQ_B1
AJ6
SDQ_B2
SDQ_B2
SDQ_B2
AL6
SDQ_B3
SDQ_B3
SDQ_B3
AN6
SDQ_B4
SDQ_B4
SDQ_B4
AG9
AH7
SDQ_B5
SDQ_B5
SDQ_B5
SDQ_B6
SDQ_B6
SDQ_B6
AL5
SDQ_B7
SDQ_B7
SDQ_B7
AM5
AJ8
SDQ_B8
SDQ_B8
SDQ_B8
SDQ_B9
SDQ_B9
SDQ_B9
AL8
SDQ_B10
SDQ_B10
SDQ_B10
AF11
310
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
Intel® 82915G GMCH 2
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
Intel® 82915GV GMCH 3
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
Ball #
AE11
AJ7
AL7
AG10
AG11
AF13
AH12
AD14
AD15
AD12
AE13
AG14
AF14
AK19
AH19
AH21
AD21
AD18
AL18
AE22
AF22
AF24
AF25
AL26
AJ26
AF23
AD23
AL25
AJ25
AK32
AJ31
AG31
AF28
AJ29
AK33
AG30
AG27
AF27
AE27
AC26
AB26
AE31
AE29
Datasheet
311
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
RSV
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
AC28
AB27
AA28
W29
V28
SDQ_B54
SDQ_B54
SDQ_B55
SDQ_B55
SDQ_B56
SDQ_B56
SDQ_B57
SDQ_B57
SDQ_B58
SDQ_B58
SDQ_B59
SDQ_B59
V29
SDQ_B60
SDQ_B60
Y26
SDQ_B61
SDQ_B61
AA29
W26
U26
SDQ_B62
SDQ_B62
SDQ_B63
SDQ_B63
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SDVO_CTRLCLK
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SDVO_CTRLCLK
AG1
AG2
AL3
AL2
AP7
AR7
AF17
AG17
AM30
AL29
AG35
AG33
AA34
AA35
U34
U35
AK5
AL4
AK10
AH10
AK13
AL14
AD20
AF20
AH25
AG26
AH28
AH30
AB31
AC30
W27
Y28
J13
312
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
SDVO_CTRLDATA
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWOUT0
SM_SLEWOUT1
SMA_A0
Intel® 82915GV GMCH 3
SDVO_CTRLDATA
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWOUT0
SM_SLEWOUT1
SMA_A0
Ball #
K13
RSV
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWOUT0
SM_SLEWOUT1
SMA_A0
AJ12
AF9
AK12
AE10
AP26
AR24
AL24
AP23
AR23
AP22
AN23
AP21
AN22
AN21
AM27
AM21
AR20
AP31
AM15
AR15
AN15
AL15
AP14
AM12
AP13
AL12
AN13
AR12
AP15
AP11
AR11
AL33
AF5
SMA_A1
SMA_A1
SMA_A1
SMA_A2
SMA_A2
SMA_A2
SMA_A3
SMA_A3
SMA_A3
SMA_A4
SMA_A4
SMA_A4
SMA_A5
SMA_A5
SMA_A5
SMA_A6
SMA_A6
SMA_A6
SMA_A7
SMA_A7
SMA_A7
SMA_A8
SMA_A8
SMA_A8
SMA_A9
SMA_A9
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B1
SMA_B1
SMA_B2
SMA_B2
SMA_B2
SMA_B3
SMA_B3
SMA_B3
SMA_B4
SMA_B4
SMA_B4
SMA_B5
SMA_B5
SMA_B5
SMA_B6
SMA_B6
SMA_B6
SMA_B7
SMA_B7
SMA_B7
SMA_B8
SMA_B8
SMA_B8
SMA_B9
SMA_B9
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SOCOMP0
SOCOMP1
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SOCOMP0
SOCOMP1
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SOCOMP0
SOCOMP1
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SODT_B0
SODT_B1
SODT_B2
SODT_B3
AE5
AP30
AN32
AP29
AP33
AM33
AL34
AL35
AK34
Datasheet
313
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
Intel® 82915G GMCH 2
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
Intel® 82915GV GMCH 3
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
Ball #
AP27
AN17
AG4
AG8
AE7
AE8
AN28
AP17
AA13
AA14
AA16
AA18
AA20
AA21
AA22
AA23
AA24
AB1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB10
AB11
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB20
AB21
AB22
AB23
AB24
AB3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB4
VCC
VCC
VCC
AB5
VCC
VCC
VCC
AB6
VCC
VCC
VCC
AB7
VCC
VCC
VCC
AB8
VCC
VCC
VCC
AB9
VCC
VCC
VCC
AC1
VCC
VCC
VCC
AC10
AC11
VCC
VCC
VCC
314
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Intel® 82915G GMCH 2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Intel® 82915GV GMCH 3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Ball #
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AD1
AD10
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
L10
N13
N14
N15
N16
N18
N20
N21
P13
P14
P15
P17
P19
P21
P22
R13
R14
R15
R16
R18
R20
R22
R23
T13
T14
Datasheet
315
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
T15
T16
T17
T19
T20
T21
T23
T24
U13
U14
U16
U18
U20
U22
U24
V13
V14
V15
V17
V19
V21
V23
V24
W13
W14
W16
W18
W20
W22
W24
Y13
Y14
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
W1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
W2
W3
316
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
Intel® 82915G GMCH 2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
Intel® 82915GV GMCH 3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
Ball #
W4
W6
W7
W8
W9
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
A13
RSV
VCCA_DAC
VCCA_DAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_EXPPLL
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCA_DAC
VCCA_DAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_EXPPLL
VCCA_HPLL
VCCA_SMPLL
VCCSM
D13
RSV
E13
VCCA_DPLLA
VCCA_DPLLB
VCCA_EXPPLL
VCCA_HPLL
VCCA_SMPLL
VCCSM
A12
B13
A14
A17
B17
AK35
AM10
AM11
AM13
AM14
AM16
AM17
AM19
AM20
AM22
AM23
AM25
AM26
AM28
AM32
AN35
AP12
AP16
AP20
AP24
AP28
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
Datasheet
317
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
Intel® 82915G GMCH 2
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
Intel® 82915GV GMCH 3
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
Ball #
AR10
AR14
AR18
AR22
AR26
AR31
AR33
A10
VSS
VSS
VSS
A18
VSS
VSS
VSS
A26
VSS
VSS
VSS
A3
VSS
VSS
VSS
A30
VSS
VSS
VSS
A33
VSS
VSS
VSS
A5
VSS
VSS
VSS
AA1
VSS
VSS
VSS
AA10
AA11
AA15
AA17
AA19
AA2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA25
AA26
AA27
AA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA4
VSS
VSS
VSS
AA5
VSS
VSS
VSS
AA6
VSS
VSS
VSS
AA7
VSS
VSS
VSS
AA8
VSS
VSS
VSS
AA9
VSS
VSS
VSS
AB25
AB28
AB30
AB32
AB35
AC25
AC27
AC29
AC31
AC32
AD11
AD13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
318
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
AD16
AD19
AD22
AD25
AD26
AD27
AD34
AE12
AE14
AE15
AE17
AE18
AE20
AE21
AE23
AE24
AE28
AE30
AE32
AE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE6
VSS
AE9
VSS
AF1
VSS
AF10
AF12
AF15
AF18
AF21
AF26
AF29
AF30
AF31
AF32
AF35
AF4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF6
VSS
AF8
VSS
AG12
AG13
AG15
AG16
AG18
AG19
VSS
VSS
VSS
VSS
VSS
Datasheet
319
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
AG21
AG22
AG25
AG28
AG29
AG5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH1
VSS
AH11
AH14
AH17
AH20
AH23
AH26
AH29
AH32
AH34
AH5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH6
VSS
AH8
VSS
AJ10
AJ13
AJ15
AJ16
AJ19
AJ22
AJ27
AJ30
AJ32
AJ35
AJ4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ9
VSS
AK1
VSS
AK11
AK14
AK17
AK20
AK23
AK25
AK26
AK28
AK30
AK4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK6
320
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
AK7
AK8
AL10
AL13
AL16
AL19
AL22
AL32
AM29
AM31
AM4
AM6
AM7
AM8
AN1
AP8
AR13
AR17
AR21
AR25
AR3
AR30
AR6
B10
B12
B14
B16
B18
B2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B24
B28
B5
VSS
VSS
VSS
B6
VSS
B7
VSS
B8
VSS
B9
VSS
C1
VSS
C11
C13
C17
C18
C23
C3
VSS
VSS
VSS
VSS
VSS
Datasheet
321
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
C35
C4
VSS
VSS
VSS
D10
D11
D15
D16
D18
D23
D25
D26
D28
D3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D30
D31
D32
D4
VSS
VSS
VSS
VSS
D6
VSS
D7
VSS
D8
VSS
D9
VSS
E1
VSS
E10
E17
E18
E2
VSS
VSS
VSS
VSS
E23
E26
E29
E4
VSS
VSS
VSS
VSS
E6
VSS
E8
VSS
F10
F16
F18
F2
VSS
VSS
VSS
VSS
F23
F25
F29
F30
F32
F35
F4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F5
322
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
F6
VSS
VSS
F8
VSS
G10
G11
G13
G15
G17
G19
G2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G20
G23
G26
G27
G28
G4
VSS
VSS
VSS
VSS
VSS
VSS
G7
VSS
G8
VSS
G9
VSS
H10
H13
H2
VSS
VSS
VSS
H21
H24
H25
H27
H30
H32
H34
H4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H5
VSS
H6
VSS
H9
VSS
J10
J15
J16
J17
J18
J2
VSS
VSS
VSS
VSS
VSS
VSS
J20
J23
J30
J4
VSS
VSS
VSS
VSS
J7
Datasheet
323
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
J8
VSS
VSS
J9
VSS
K10
K11
K14
K2
VSS
VSS
VSS
VSS
K20
K24
K26
K28
K31
K32
K35
K4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K5
VSS
K6
VSS
K9
VSS
L11
L13
L15
L16
L17
L18
L2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L20
L21
L22
L24
L27
L30
L32
L4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L7
VSS
L8
VSS
L9
VSS
M10
M11
M17
M2
VSS
VSS
VSS
VSS
M20
M24
M25
M27
VSS
VSS
VSS
324
Datasheet
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
M29
M34
M4
VSS
VSS
VSS
VSS
M5
VSS
M6
VSS
M9
VSS
N10
N11
N17
N19
N2
VSS
VSS
VSS
VSS
VSS
N25
N28
N30
N32
N4
VSS
VSS
VSS
VSS
VSS
N7
VSS
N8
VSS
N9
VSS
P11
P16
P18
P2
VSS
VSS
VSS
VSS
P20
P25
P27
P29
P31
P32
P35
P4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P5
VSS
P6
VSS
P9
VSS
R11
R17
R19
R2
VSS
VSS
VSS
VSS
R21
R25
R26
R27
R4
VSS
VSS
VSS
VSS
Datasheet
325
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915G GMCH 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Intel® 82915GV GMCH 3
Ball #
R7
VSS
VSS
R8
VSS
R9
VSS
T10
T11
T18
T2
VSS
VSS
VSS
VSS
T22
T25
T28
T30
T32
T34
T4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T5
VSS
T6
VSS
T7
VSS
U11
U15
U17
U19
U2
VSS
VSS
VSS
VSS
VSS
U21
U23
U25
U27
U29
U31
U32
U4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U7
VSS
U8
VSS
U9
VSS
V1
VSS
V11
V16
V18
V2
VSS
VSS
VSS
VSS
V20
V22
V25
V26
V27
VSS
VSS
VSS
VSS
326
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R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSV
RSV
VTT
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
V35
V4
VSS
VSS
VSS
VSS
VSS
VSS
V6
VSS
VSS
V9
VSS
VSS
W11
W15
W17
W19
W21
W23
W25
W28
W30
W32
Y11
Y18
Y22
Y25
Y27
Y29
Y31
Y32
Y34
F13
D12
A19
A20
A21
A22
B19
B20
B21
B22
C19
C20
C21
C22
D19
D20
D21
D22
E19
E20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
VSYNC
VTT
VSSA_DAC
VSYNC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
Datasheet
327
Ballout and Package Information
R
Table 14-2. GMCH/MCH Ballout for DDR2 Systems (Sorted by Signal Name)
Intel® 82915P MCH 1
Intel® 82915G GMCH 2
Intel® 82915GV GMCH 3
Ball #
E21
E22
F20
F21
F22
G21
G22
H22
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
NOTES:
1. DDR2, PCI Express* x16 Graphics Interface, No DAC, No Intel® SDVO
2. DDR2, PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
3. DDR2, No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
328
Datasheet
Ballout and Package Information
R
14.2
DDR Ballout
Figure 14-4, Figure 14-5, and Figure 14-6 show the 82915G GMCH ballout for platforms using
DDR system memory, as viewed from the top side of the package. Figure 14-4 shows columns
1–12; Figure 14-5 shows columns 13–24; Figure 14-6 shows columns 25–35.
The complete DDR ballout for both the 82915G/82915GV/82915GL GMCH and
82915P/82915PL MCH are listed in Table 2-1and Table 14-4
is sorted by ball number. Table 14-4 is sorted alphabetically by signal name based on the signal
names of the 82915G GMCH. Note that the first table has more entries than the second table. The
second table does not include unpopulated balls whereas the first table does.
Note: Balls that are listed as RSV are Reserved. Board traces should Not be routed to these balls.
Note: Balls that are listed as NC are No Connects. Board traces to these balls are permitted as specified.
Datasheet
329
Ballout and Package Information
R
Figure 14-4. Intel® 82915G GMCH Ballout for DDR (Top View: Columns 1–12 )
1
2
3
4
5
6
7
8
9
10
11
12
VCCA_
DPLLA
A
NC
VSS
VSS
EXP_TXN3
EXP_TXP3
EXP_TXN1
EXP_TXP1
VSS
GCLKP
B
C
D
E
F
NC
VSS
EXP_TXP5
EXP_TXN5
VSS
EXP_RXP4
VSS
EXP_RXN4
VSS
VSS
VSS
EXP_TXP4
VSS
VSS
VSS
EXP_TXP2
VSS
VSS
EXP_TXN0
VSS
VSS
EXP_TXP0
VSS
GCLKN
VSS
VSS
VSS
EXP_TXN4
EXP_RXP5
EXP_RXN5
VSS
EXP_TXN2
VSS
VSS
VSS
VSS
VSYNC
HSYNC
NC
VSS
EXP_TXP6
EXP_TXN6
EXP_TXP8
EXP_TXN8
VSS
VSS
EXP_RXN3
EXP_RXP3
VSS
VSS
EXP_RXN2
EXP_RXP2
VSS
VSS
EXP_RXP0
EXP_RXN0
VSS
EXP_TXP7
EXP_TXN7
EXP_TXP9
VSS
VSS
VSS
VSS
VSS
G
H
VSS
VSS
EXP_RXN6
VSS
EXP_RXP6
VSS
VSS
VSS
NC
VSS
VSS
EXP_RXN7
EXP_RXP7
VSS
VSS
EXP_RXN1
NC
EXP_
TXN9
EXP_
J
K
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
EXP_RXN8
VSS
EXP_RXP8
VSS
VSS
EXP_RXN9
VSS
VSS
EXP_RXP9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
EXP_RXP1
VSS
NC
NC
NC
TXP10
EXP_
EXP_
TXP11
TXN10
EXP_
EXP_
EXP_
EXP_
VSS
TXN11
TXP12
RXN10
RXP10
EXP_
EXP_
EXP_
EXP_
DREF
CLKN
M
N
P
R
VSS
VSS
VSS
TXP13
TXN12
RXN12
RXP12
EXP_
EXP_
EXP_
EXP_
VSS
VSS
VSS
NC
NC
NC
TXN13
TXP14
RXN13
RXP13
EXP_
EXP_
EXP_
EXP_
EXP_
VSS
VSS
VSS
TXP15
TXN14
RXP14
RXN14
RXP11
EXP_
EXP_RXN1
5
EXP_
EXP_
DMI_TXP0
VSS
VSS
VSS
TXN15
RXP15
RXN11
T
U
V
DMI_TXP1
DMI_TXN1
VSS
VSS
VSS
VSS
DMI_TXN0
DMI_TXP2
DMI_TXN2
VSS
VSS
VSS
VSS
VSS
DMI_RXN0
VSS
VSS
VSS
DMI_RXN1
VSS
DMI_RXP1
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
DMI_RXP0
DMI_TXP3
DMI_RXN3
DMI_RXP3
DMI_RXP2
DMI_RXN2
VSS
EXP_
W
Y
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VSS
VSS
NC
NC
COMPI
EXP_
COMPO
AA
AB
AC
AD
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
NC
NC
RSV
SDQ_B20
SM_SLEW
OUT1
AE
AF
SDQ_A5
VSS
SDQ_A4
SDM_A0
SDQ_A0
SDQ_A1
VSS
VSS
RSV
RSV
VSS
VSS
SMVREF0
RSTIN#
SMVREF1
VSS
VSS
SDQ_B11
SDQ_B10
VSS
VSS
SM_SLEWI
N1
VSS
AG
AH
SDQS_A0
VSS
RSV
SDQ_A6
SDQ_A7
SRCOMP0
SDQ_B5
VSS
VSS
NC
PWROK
SDQ_B0
SRCOMP1
VSS
SDQ_B4
SDM_B1
SDQ_B14
RSV
SDQ_B15
VSS
VSS
SDQ_A2
VSS
SDQ_B21
SM_
AJ
SDQ_A8
SDQ_A3
SDQ_A9
SDQ_A12
SDQ_A13
VSS
VSS
SDM_B0
SDQ_B1
VSS
SDQ_B8
VSS
SDQ_B12
VSS
VSS
VSS
SCLK_B1#
VSS
SLEWIN0
SM_SLE
WOUT0
AK
VSS
SDQS_B0
SCLK_B4
SDQS_B1
AL
AM
AN
AP
AR
SDM_A1
RSV
SCLK_A4
SCLK_A1
SDQ_A14
NC
SDQS_A1
SCLK_A4#
SCLK_A1#
SDQ_A15
VSS
RSV
VSS
SDQ_B2
SDQ_B6
SDQ_A20
SDQ_A16
SDQ_A17
5
SDQ_B7
VSS
SDQ_B9
VSS
SDQ_B13
VSS
SCLK_B4#
SCKE_B1
SDQ_A23
SDQ_A19
SCKE_B3
9
VSS
VCCSM
SCKE_B0
SCKE_B2
VCCSM
10
SCLK_B1
VCCSM
SCKE_A1
SCKE_A2
SCKE_A3
11
SCKE_A0
SMA_B12
VSS
NC
NC
1
SDQ_A10
SDQ_A11
SDQ_B3
SDQ_A21
VSS
SDM_A2
SDQS_A2
RSV
SDQ_A18
VSS
VCCSM
SMA_B11
12
SDQ_A22
8
2
3
4
6
7
330
Datasheet
Ballout and Package Information
R
Figure 14-5. Intel® 82915G GMCH Ballout for DDR (Top View: Columns 13–24 )
13
14
15
16
17
18
19
20
21
22
23
24
VCCA_
VCCA_
HPLL
A
VCC2
REFSET
EXP_SLR
VSS
VTT
VTT
VTT
VTT
HSWING
HVREF
EXPPLL
VCCA_
DPLLB
VCCA_
SMPLL
B
C
D
VSS
RSV
RSV
MTYPE
VSS
VSS
NC
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
HRCOMP
VSS
VSS
VSS
VSS
VCCA_
DAC
GREEN
VSS
BSEL2
VSS
HSCOMP
E
F
VCCA_DAC
VSSA_DAC
GREEN#
RED
BSEL1
RSV
NC
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
HD62
NC
VSS
HD47
HDSTBN2#
HCPURST
#
G
H
J
VSS
VSS
RED#
BLUE
VSS
NC
RSV
BSEL0
VSS
VSS
NC
HD45
HD46
VSS
VSS
HD41
VSS
HD40
VSS
VTT
VSS
VTT
VTT
VSS
HD37
VSS
VSS
SDVO_CTR
LCLK
BLUE#
VSS
VSS
HDSTBP2#
HD35
HD32
HD33
SDVO_
K
VSS
RSV
EXTTS#
HD44
HD43
HDINV2#
VSS
HD39
HD34
HD31
VSS
CTRLDATA
L
M
VSS
DREFCLKP
VCC
DDC_DATA
ICH_SYNC#
VCC
VSS
DDC_CLK
VCC
VSS
RSV
VSS
VSS
VSS
HD42
VCC
NC
HD38
VSS
VSS
VSS
VSS
HD36
VCC
VSS
HCLKN
NC
HD30
HCLKP
NC
VSS
VSS
N
VCC
VSS
VCC
NC
P
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
NC
NC
R
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
NC
T
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
U
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
V
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
W
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Y
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
NC
NC
VSS
SDQ_B19
VSS
SDQ_B23
VSS
VSS
SDQ_A26
VSS
SDQ_B24
VSS
VSS
SDQS_B3
VSS
SDQ_B31
VSS
VSS
SDQ_B36
VSS
SDM_B6
VSS
SDQ_B16
SDQ_B17
VSS
RSV_TP0
SDQ_A28
VSS
SDQ_A30
SDQ_A27
VSS
SDQ_B26
SDQ_B30
VSS
SDQ_B22
SDQ_B18
VSS
VSS
SDQS_A3
RSV
VSS
RSV
VSS
SDQ_B32
SCLK_B0#
VSS
SDQ_B37
SDM_B4
NC
VSS
VSS
SDM_B3
VSS
VSS
SDM_B2
VSS
RSV_TP1
VSS
SDM_A3
VSS
VSS
SDQ_A31
RSV
SDQ_B29
VSS
SDQ_B27
RSV
SCLK_B0
VSS
NC
SDQ_A29
VSS
RSV
RSV
RSV
SDQS_B2
VSS
VSS
RSV_TP3
SMA_B7
SMA_A9
SMA_B5
SMA_A11
SDQ_A24
VSS
RSV
SDQ_B25
VSS
VSS
RSV
SCLK_B3#
VSS
VSS
RSV
RSV
SDQ_A25
VCCSM
SMA_B2
SMA_B6
SDQ_B28
SMA_B0
SMA_A8
SMA_B1
RSV
RSV
SCLK_B3
VCCSM
SMA_A10
RSV
RSV
VCCSM
SMA_B9
SMA_A12
VCCSM
RSV_TP2
SMA_B8
VCCSM
SMA_A7
VCCSM
VCCSM
NC
VCCSM
SMA_B10
VCCSM
SMA_A4
SMA_A2
SMA_A3
VCCSM
SMA_A0
SMA_A1
SCLK_A0
SMA_A5
VCCSM
RSV
24
AR
VSS
VCCSM
SMA_B4
SMA_B3
VSS
VCCSM
SBS_B1
SMA_A6
VSS
VCCSM
RSV
13
14
15
16
17
18
19
20
21
22
23
Datasheet
331
Ballout and Package Information
R
Figure 14-6. Intel® 82915G GMCH Ballout for DDR (Top View: Columns 25–35 )
25
HD48
HD63
HD58
VSS
26
27
28
29
30
31
32
33
34
35
NC
VSS
HD61
HD57
HD55
VSS
HD53
VSS
NC
A
B
HDINV3#
HD59
HD54
VSS
HDSTBP3#
HDSTBN3#
HD18
HD51
HD17
VSS
HD52
HD15
HD14
VSS
HD13
HD11
NC
HD49
HD56
HD50
HD9
HD12
VSS
C
VSS
HD60
VSS
VSS
HD10
HD8
D
HD25
VSS
VSS
HD24
HD16
VSS
HBPRI#
VSS
HPCREQ#
HREQ4#
HREQ3#
HREQ2#
HADSTB0#
VSS
HREQ1#
VSS
HDSTBP0#
HREQ0#
HD7
HDINV0#
HD6
HDSTBN0#
VSS
E
HDSTBN1#
VSS
HD23
HD22
VSS
F
HD26
VSS
VSS
VSS
HD20
HA6#
VSS
HA7#
VSS
HD5
HD3
G
HDSTBP1#
HDINV1#
VSS
VSS
HD19
HA3#
HD1
VSS
HD4
H
HD27
HD28
HD29
VSS
HD21
HA13#
VSS
HA5#
VSS
HRS2#
VSS
HD0
HD2
HDEFER#
VSS
J
HA14#
VSS
HA4#
HA8#
VSS
HA15#
HLOCK#
HRS0#
HHIT#
K
HA18#
HA20#
HA19#
HA22#
VSS
HA12#
HA16#
VSS
HA9#
HA11#
HADS#
HA21#
VSS
VSS
HDBSY#
HBNR#
HHITM#
VSS
L
VSS
VSS
HA10#
VSS
HDRDY#
VSS
VSS
M
VSS
HADSTB1#
VSS
HA23#
VSS
HA26#
HTRDY#
HRS1#
SDQ_A59
VSS
N
VSS
HA24#
HA25#
VSS
NC
VSS
HEDRDY#
HBREQ0#
SDQ_A62
SDM_A7
P
VSS
VSS
HA17#
HA31#
VSS
RSV
RSV
SDQ_A58
VSS
RSV
R
VSS
HA30#
SDQ_B58
VSS
HA27#
VSS
VSS
HA28#
VSS
SDQ_A63
RSV
T
VSS
HA29#
SDQ_B63
VSS
RSV
VSS
SDQS_A7
SDQ_A56
SDQ_A51
VSS
U
VSS
VSS
SDQ_B59
SDQ_B57
VSS
RSV
RSV
RSV
SDQ_A57
SDQ_A61
SDQ_A50
SDM_A6
VSS
V
VSS
SDQ_B62
SDQ_B60
VSS
SDQS_B7
VSS
VSS
SDM_B7
VSS
VSS
SDQ_A60
SDQ_A55
RSV
W
Y
VSS
RSV
RSV
VSS
VSS
VSS
SDQ_B61
VSS
SDQ_B56
RSV
RSV
RSV
SDQ_A54
VSS
SDQS_A6
SCLK_A2
SCLK_A5#
VSS
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
VSS
SDQ_B51
SDQ_B55
VSS
SDQ_B50
VSS
VSS
SDQS_B6
VSS
SMA_A13
SCLK_A2#
VSS
VSS
SDQ_B54
SCLK_B5#
VSS
VSS
RSV
VSS
SCLK_A5
SDQ_A53
SDQ_A48
VSS
VSS
VSS
SCLK_B5
SDQ_B52
VSS
NC
SDQ_A52
SDQ_B48
VSS
SMA_B13
VSS
SCLK_B2#
SDQ_B33
VSS
SCLK_B2
VSS
SDQ_B53
SDQ_B49
SDQ_B46
SDQ_A32
VSS
VSS
SDQ_A47
SDQ_A46
RSV
SDQ_A49
SDQ_A43
SDM_A5
VSS
SDQ_B47
VSS
VSS
VSS
RSV
VSS
SDQ_B42
RSV
SDQ_B43
SDM_B5
SDQ_B41
SDQ_A35
SDQ_A39
VSS
SDQ_A42
VSS
SDQS_A5
SDQ_A41
VSS
SDQS_B4
SDQ_B38
VSS
VSS
SDQS_B5
SDQ_A37
VSS
VSS
SDQ_A45
SDQ_A44
SDQ_B44
SCS_A3#
SCS_B3#
SCS_B2#
RSV
SDQ_B35
VSS
SDQ_B40
SDM_A4
RSV
VSS
VSS
SDQ_A40
SCS_A2#
SCAS_A#
SCS_A0#
SCS_B1#
SCS_B0#
NC
SDQ_A33
SDQ_A36
SBS_B0
SCAS_B#
SRAS_B#
SWE_B#
27
VSS
SDQ_B45
VSS
VCCSM
SCS_A1#
SDQ_B34
VCCSM
SCLK_A0#
SCLK_A3
VSS
SDQ_B39
VCCSM
SCLK_A3#
SBS_A1
VCCSM
26
NC
SDQ_A38
SDQS_A4
SDQ_A34
RSV
VCCSM
SBS_A0
VCCSM
RSV
VSS
VCCSM
RSV
SRAS_A#
RSV
RSV
VCCSM
NC
SWE_A#
VCCSM
31
RSV
RSV
VSS
VCCSM
33
NC
25
28
29
30
32
34
35
332
Datasheet
Ballout and Package Information
R
Table 14-3. GMCH/MCH Ballout for DDR Systems (Sorted by Ball Number)
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
A1
A2
A3
A4
A5
—
NC
—
NC
—
NC
—
NC
—
NC
—
NC
VSS
—
VSS
—
VSS
—
VSS
—
VSS
—
VSS
—
VSS
VSS
VSS
VSS
VSS
VSS
SDVOB_CLK
-
A6
A7
A8
A9
EXP_TXN3
EXP_TXP3
EXP_TXN1
EXP_TXP1
EXP_TXN3
EXP_TXP3
EXP_TXN1
EXP_TXP1
EXP_TXN3
EXP_TXP3
EXP_TXN1
EXP_TXP1
SDVOB_CLK-
SDVOB_CLK+
SDVOB_CLK-
SDVOB_CLK+
SDVOB_CLK
+
SDVOB_GRE
EN-
SDVOB_GREE
N-
SDVOB_GREEN-
SDVOB_GREEN+
SDVOB_GRE
EN+
SDVOB_GREE
N+
A10
A11
VSS
VSS
VSS
VSS
VSS
VSS
GCLKP
GCLKP
GCLKP
GCLKP
GCLKP
GCLKP
VCCA_DPLL
A
A12
A13
A14
VCCA_DPLLA
VCC2
VCCA_DPLLA
VCC2
VCCA_DPLLA
VCC2
VCCA_DPLLA
VCC2
VCCA_DPLLA
VCC2
VCC2
VCCA_EXPP
LL
VCCA_EXPPL
L
VCCA_EXPPLL
VCCA_EXPPLL
VCCA_EXPPLL
VCCA_EXPPLL
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
REFSET
RSV
RSV
EXP_SLR
VCCA_HPLL
VSS
RSV
EXP_SLR
VCCA_HPLL
VSS
REFSET
EXP_SLR
VCCA_HPLL
VSS
REFSET
RSV
REFSET
RSV
VCCA_HPLL
VSS
VCCA_HPLL
VSS
VCCA_HPLL
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
HSWING
HVREF
HD48
VSS
HSWING
HVREF
HD48
VSS
HSWING
HVREF
HD48
VSS
HSWING
HVREF
HD48
VSS
HSWING
HVREF
HD48
VSS
HSWING
HVREF
HD48
VSS
HD61
HD57
HD55
VSS
HD61
HD57
HD55
VSS
HD61
HD57
HD55
VSS
HD61
HD57
HD55
VSS
HD61
HD57
HD55
VSS
HD61
HD57
HD55
VSS
HD53
—
HD53
—
HD53
—
HD53
—
HD53
—
HD53
—
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
Datasheet
333
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
A35
B1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B2
VSS
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
GCLKN
VSS
VSS
VSS
VSS
VSS
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
GCLKN
VSS
VSS
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
GCLKN
VSS
B3
EXP_RXP4
EXP_RXN4
VSS
EXP_RXP4
EXP_RXN4
VSS
EXP_RXP4
EXP_RXN4
VSS
B4
B5
B6
VSS
VSS
VSS
B7
VSS
VSS
VSS
B8
VSS
VSS
VSS
B9
VSS
VSS
VSS
B10
B11
B12
VSS
VSS
VSS
GCLKN
VSS
GCLKN
VSS
GCLKN
VSS
VCCA_DPLL
B
B13
VCCA_DPLLB
VCCA_DPLLB
VCCA_DPLLB
VCCA_DPLLB
VCCA_DPLLB
B14
B15
B16
VSS
RSV
VSS
VSS
RSV
VSS
VSS
RSV
VSS
VSS
RSV
VSS
VSS
RSV
VSS
VSS
RSV
VSS
VCCA_SMPL
L
B17
VCCA_SMPLL
VCCA_SMPLL
VCCA_SMPLL
VCCA_SMPLL
VCCA_SMPLL
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
C1
VSS
VTT
VSS
VTT
VSS
VTT
VSS
VTT
VSS
VTT
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
HRCOMP
VSS
HRCOMP
VSS
HRCOMP
VSS
HRCOMP
VSS
HRCOMP
VSS
HRCOMP
VSS
HD63
HDINV3#
HD54
VSS
HD63
HDINV3#
HD54
VSS
HD63
HDINV3#
HD54
VSS
HD63
HDINV3#
HD54
VSS
HD63
HDINV3#
HD54
VSS
HD63
HDINV3#
HD54
VSS
HDSTBP3#
HD51
HD52
HD15
HD13
HD11
NC
HDSTBP3#
HD51
HD52
HD15
HD13
HD11
NC
HDSTBP3#
HD51
HD52
HD15
HD13
HD11
NC
HDSTBP3#
HD51
HD52
HD15
HD13
HD11
NC
HDSTBP3#
HD51
HD52
HD15
HD13
HD11
NC
HDSTBP3#
HD51
HD52
HD15
HD13
HD11
NC
VSS
VSS
VSS
VSS
VSS
VSS
334
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
SDVOC_GRE
EN+
SDVOC_GREE
N+
C2
EXP_TXP5
EXP_TXP5
EXP_TXP5
SDVOC_GREEN+
C3
C4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDVOC_RED
SDVOC_RED-/
SDVOB_ALPHA
-
-/
SDVOC_RED-/
SDVOB_ALPHA-
C5
C6
EXP_TXN4
EXP_TXP4
EXP_TXN4
EXP_TXP4
EXP_TXN4
EXP_TXP4
SDVOB_ALP
HA-
SDVOC_RED
+/
SDVOB_ALP
HA+
SDVOC_RED+/
SDVOB_ALPHA
+
SDVOC_RED+/
SDVOB_ALPHA+
SDVOB_BLU
E-
C7
C8
EXP_TXN2
EXP_TXP2
EXP_TXN0
EXP_TXP0
EXP_TXN2
EXP_TXP2
EXP_TXN0
EXP_TXP0
EXP_TXN2
EXP_TXP2
EXP_TXN0
EXP_TXP0
SDVOB_BLUE-
SDVOB_BLUE+
SDVOB_RED-
SDVOB_RED+
SDVOB_BLUE-
SDVOB_BLUE+
SDVOB_RED-
SDVOB_RED+
SDVOB_BLU
E+
SDVOB_RED
-
C9
SDVOB_RED
+
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
VSS
—
VSS
—
VSS
—
VSS
—
VSS
—
VSS
—
VSS
VSS
VSS
VSS
VSS
VSS
RSV
RSV
RSV
RSV
RSV
RSV
MTYPE
NC
MTYPE
NC
MTYPE
NC
MTYPE
NC
MTYPE
NC
MTYPE
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
HD58
HD59
HD49
HD56
HDSTBN3#
HD17
HD50
HD14
HD9
Datasheet
335
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
C34
C35
D1
HD12
VSS
—
HD12
VSS
—
HD12
VSS
—
HD12
VSS
—
HD12
VSS
—
HD12
VSS
—
SDVOC_GRE
EN-
SDVOC_GREE
N-
D2
EXP_TXN5
EXP_TXN5
EXP_TXN5
SDVOC_GREEN-
D3
D4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDVOC_INT
+
D5
EXP_RXP5
EXP_RXP5
EXP_RXP5
SDVOC_INT+
SDVOC_INT+
D6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSV
RSV
RSV
VSS
VSS
BSEL2
VSS
VTT
VSS
VSS
VSS
VSS
VSS
VSS
RSV
RSV
RSV
VSS
VSS
BSEL2
VSS
VTT
VSS
VSS
VSS
VSS
VSS
VSS
D7
D8
VSS
VSS
VSS
VSS
D9
VSS
VSS
VSS
VSS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
E1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSYNC
VCCA_DAC
GREEN
VSS
VSYNC
VCCA_DAC
GREEN
VSS
VSYNC
VCCA_DAC
GREEN
VSS
VSYNC
VCCA_DAC
GREEN
VSS
VSS
VSS
VSS
VSS
BSEL2
VSS
BSEL2
VSS
BSEL2
VSS
BSEL2
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
HSCOMP
VSS
VSS
HD60
VSS
HD18
VSS
VSS
VSS
HD10
HD8
—
VSS
HSCOMP
VSS
VSS
HD60
VSS
HD18
VSS
VSS
VSS
HD10
HD8
—
VSS
VSS
VSS
HSCOMP
VSS
HSCOMP
VSS
HSCOMP
VSS
HSCOMP
VSS
VSS
VSS
VSS
VSS
HD60
VSS
HD60
VSS
HD60
VSS
HD60
VSS
HD18
VSS
HD18
VSS
HD18
VSS
HD18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HD10
HD8
HD10
HD8
HD10
HD8
HD10
HD8
—
—
—
—
VSS
VSS
VSS
VSS
VSS
VSS
336
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
E2
E3
VSS
VSS
VSS
VSS
VSS
VSS
SDVOC_BLU
E+
EXP_TXP6
EXP_TXP6
EXP_TXP6
SDVOC_BLUE+
SDVOC_BLUE+
E4
E5
E6
E7
E8
VSS
SDVOC_INT-
VSS
VSS
EXP_RXN5
VSS
VSS
EXP_RXN5
VSS
VSS
EXP_RXN5
VSS
VSS
SDVOC_INT-
VSS
VSS
SDVOC_INT-
VSS
RSV
EXP_RXN3
VSS
EXP_RXN3
VSS
EXP_RXN3
VSS
RSV
RSV
VSS
VSS
VSS
SDVOC_STA
LL-
SDVOC_STALL
-
E9
EXP_RXN2
VSS
EXP_RXN2
VSS
EXP_RXN2
VSS
SDVOC_STALL-
VSS
E10
E11
VSS
VSS
SDVOC_TVC
LKIN+
SDVOC_TVCLK
IN+
EXP_RXP0
EXP_RXP0
EXP_RXP0
SDVOC_TVCLKIN+
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
F1
HSYNC
VCCA_DAC
GREEN#
BSEL1
NC
RSV
RSV
RSV
RSV
HSYNC
VCCA_DAC
GREEN#
BSEL1
NC
HSYNC
VCCA_DAC
GREEN#
BSEL1
NC
HSYNC
VCCA_DAC
GREEN#
BSEL1
NC
RSV
RSV
BSEL1
NC
BSEL1
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
HD62
HD62
HD62
HD62
HD62
HD62
HD25
HD25
HD25
HD25
HD25
HD25
VSS
VSS
VSS
VSS
VSS
VSS
HD24
HD24
HD24
HD24
HD24
HD24
HD16
HD16
HD16
HD16
HD16
HD16
VSS
VSS
VSS
VSS
VSS
VSS
HBPRI#
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
HBPRI#
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
HBPRI#
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
HBPRI#
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
HBPRI#
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
HBPRI#
HPCREQ#
HREQ1#
HDSTBP0#
HDINV0#
HDSTBN0#
EXP_TXP7
VSS
F2
SDVOC_BLU
E-
F3
EXP_TXN6
EXP_TXN6
EXP_TXN6
SDVOC_BLUE-
SDVOC_BLUE-
Datasheet
337
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
F4
F5
F6
F7
F8
VSS
VSS
VSS
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSV
VSS
VSS
VSS
VSS
RSV
VSS
VSS
VSS
VSS
EXP_RXP3
VSS
EXP_RXP3
VSS
EXP_RXP3
VSS
SDVOC_STA
LL+
SDVOC_STALL
+
F9
EXP_RXP2
VSS
EXP_RXP2
VSS
EXP_RXP2
VSS
SDVOC_STALL+
VSS
F10
F11
VSS
VSS
SDVOC_TVC
LKIN-
SDVOC_TVCLK
IN-
EXP_RXN0
EXP_RXN0
EXP_RXN0
SDVOC_TVCLKIN-
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
NC
VSSA_DAC
RED
NC
RSV
NC
RSV
NC
VSSA_DAC
RED
NC
VSSA_DAC
RED
NC
VSSA_DAC
RED
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
HD47
VSS
HD47
VSS
HD47
VSS
HD47
VSS
HD47
VSS
HD47
VSS
HDSTBN2#
VTT
HDSTBN2#
VTT
HDSTBN2#
VTT
HDSTBN2#
VTT
HDSTBN2#
VTT
HDSTBN2#
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
HDSTBN1#
HD23
HD22
VSS
HDSTBN1#
HD23
HD22
VSS
HDSTBN1#
HD23
HD22
VSS
HDSTBN1#
HD23
HD22
VSS
HDSTBN1#
HD23
HD22
VSS
HDSTBN1#
HD23
HD22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HREQ4#
VSS
HREQ4#
VSS
HREQ4#
VSS
HREQ4#
VSS
HREQ4#
VSS
HREQ4#
VSS
HREQ0#
HD6
HREQ0#
HD6
HREQ0#
HD6
HREQ0#
HD6
HREQ0#
HD6
HREQ0#
HD6
VSS
VSS
VSS
VSS
VSS
VSS
SDVOC_CLK
-
G1
EXP_TXN7
EXP_TXN7
EXP_TXN7
SDVOC_CLK-
SDVOC_CLK-
G2
G3
G4
G5
VSS
RSV
VSS
RSV
VSS
EXP_TXP8
VSS
VSS
VSS
VSS
RSV
VSS
RSV
VSS
RSV
VSS
RSV
EXP_TXP8
VSS
EXP_TXP8
VSS
EXP_RXN6
EXP_RXN6
EXP_RXN6
338
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
G6
G7
RSV
VSS
EXP_RXP6
VSS
EXP_RXP6
VSS
EXP_RXP6
VSS
RSV
VSS
RSV
VSS
G8
VSS
VSS
VSS
VSS
VSS
VSS
G9
VSS
VSS
VSS
VSS
VSS
VSS
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
H1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
RED#
VSS
RSV
RSV
RED#
VSS
RED#
VSS
RED#
VSS
VSS
VSS
RSV
VSS
RSV
RSV
RSV
RSV
VSS
RSV
VSS
VSS
VSS
VSS
HD45
VSS
HD45
VSS
HD45
VSS
HD45
VSS
HD45
VSS
HD45
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
HCPURST#
HD26
VSS
HCPURST#
HD26
VSS
HCPURST#
HD26
VSS
HCPURST#
HD26
VSS
HCPURST#
HD26
VSS
HCPURST#
HD26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HD20
HA6#
HREQ3#
HA7#
HD7
HD20
HA6#
HREQ3#
HA7#
HD7
HD20
HA6#
HREQ3#
HA7#
HD7
HD20
HA6#
HREQ3#
HA7#
HD7
HD20
HA6#
HREQ3#
HA7#
HD7
HD20
HA6#
HREQ3#
HA7#
HD7
HD5
HD5
HD5
HD5
HD5
HD5
HD3
HD3
HD3
HD3
HD3
HD3
RSV
VSS
EXP_TXP9
VSS
EXP_TXP9
VSS
EXP_TXP9
VSS
RSV
VSS
RSV
VSS
H2
H3
RSV
VSS
EXP_TXN8
VSS
EXP_TXN8
VSS
EXP_TXN8
VSS
RSV
VSS
RSV
VSS
H4
H5
VSS
VSS
VSS
VSS
VSS
VSS
H6
VSS
VSS
VSS
VSS
VSS
VSS
H7
RSV
RSV
VSS
EXP_RXN7
EXP_RXP7
VSS
EXP_RXN7
EXP_RXP7
VSS
EXP_RXN7
EXP_RXP7
VSS
RSV
RSV
VSS
RSV
RSV
VSS
H8
H9
H10
VSS
VSS
VSS
VSS
VSS
VSS
Datasheet
339
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
J1
SDVOB_INT-
NC
EXP_RXN1
NC
EXP_RXN1
NC
EXP_RXN1
NC
SDVOB_INT-
NC
SDVOB_INT-
NC
VSS
VSS
VSS
VSS
VSS
VSS
BLUE
NC
RSV
RSV
BLUE
NC
BLUE
NC
BLUE
NC
NC
NC
BSEL0
NC
BSEL0
NC
BSEL0
NC
BSEL0
NC
BSEL0
NC
BSEL0
NC
HD46
HD41
HD40
VSS
HD46
HD41
HD40
VSS
HD46
HD41
HD40
VSS
HD46
HD41
HD40
VSS
HD46
HD41
HD40
VSS
HD46
HD41
HD40
VSS
VTT
VTT
VTT
VTT
VTT
VTT
HD37
VSS
HD37
VSS
HD37
VSS
HD37
VSS
HD37
VSS
HD37
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HDSTBP1#
VSS
HDSTBP1#
VSS
HDSTBP1#
VSS
HDSTBP1#
VSS
HDSTBP1#
VSS
HDSTBP1#
VSS
HD19
HA3#
VSS
HD19
HA3#
VSS
HD19
HA3#
VSS
HD19
HA3#
VSS
HD19
HA3#
VSS
HD19
HA3#
VSS
HREQ2#
VSS
HREQ2#
VSS
HREQ2#
VSS
HREQ2#
VSS
HREQ2#
VSS
HREQ2#
VSS
HD1
HD1
HD1
HD1
HD1
HD1
VSS
VSS
VSS
VSS
VSS
VSS
HD4
HD4
HD4
HD4
HD4
HD4
RSV
EXP_TXN9
VSS
EXP_TXN9
VSS
EXP_TXN9
VSS
RSV
RSV
J2
VSS
VSS
VSS
J3
RSV
EXP_TXP10
VSS
EXP_TXP10
VSS
EXP_TXP10
VSS
RSV
RSV
J4
VSS
VSS
VSS
J5
RSV
EXP_RXN8
EXP_RXP8
VSS
EXP_RXN8
EXP_RXP8
VSS
EXP_RXN8
EXP_RXP8
VSS
RSV
RSV
J6
RSV
RSV
RSV
J7
VSS
VSS
VSS
J8
VSS
VSS
VSS
VSS
VSS
VSS
J9
VSS
VSS
VSS
VSS
VSS
VSS
J10
J11
J12
VSS
VSS
VSS
VSS
VSS
VSS
SDVOB_INT+
NC
EXP_RXP1
NC
EXP_RXP1
NC
EXP_RXP1
NC
SDVOB_INT+
NC
SDVOB_INT+
NC
SDVO_CTRL
CLK
SDVO_CTRLCL
K
J13
J14
RSV
RSV
RSV
RSV
SDVO_CTRLCLK
BLUE#
SDVO_CTRLCLK
BLUE#
BLUE#
BLUE#
340
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
K1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HDSTBP2#
VSS
HDSTBP2#
VSS
HDSTBP2#
VSS
HDSTBP2#
VSS
HDSTBP2#
VSS
HDSTBP2#
VSS
HD35
HD32
VSS
HD35
HD35
HD35
HD35
HD32
VSS
HD35
HD32
VSS
HD32
HD32
HD32
VSS
VSS
VSS
HD33
HD27
HDINV1#
HD21
HA13#
HA5#
VSS
HD33
HD33
HD33
HD33
HD27
HDINV1#
HD21
HA13#
HA5#
VSS
HD33
HD27
HDINV1#
HD21
HA13#
HA5#
VSS
HD27
HD27
HD27
HDINV1#
HD21
HDINV1#
HD21
HDINV1#
HD21
HA13#
HA5#
HA13#
HA5#
HA13#
HA5#
VSS
VSS
VSS
HADSTB0#
HRS2#
HD0
HADSTB0#
HRS2#
HD0
HADSTB0#
HRS2#
HD0
HADSTB0#
HRS2#
HD0
HADSTB0#
HRS2#
HD0
HADSTB0#
HRS2#
HD0
HD2
HD2
HD2
HD2
HD2
HD2
HDEFER#
RSV
HDEFER#
EXP_TXP11
VSS
HDEFER#
EXP_TXP11
VSS
HDEFER#
EXP_TXP11
VSS
HDEFER#
RSV
HDEFER#
RSV
K2
VSS
VSS
VSS
K3
RSV
EXP_TXN10
VSS
EXP_TXN10
VSS
EXP_TXN10
VSS
RSV
RSV
K4
VSS
VSS
VSS
K5
VSS
VSS
VSS
VSS
VSS
VSS
K6
VSS
VSS
VSS
VSS
VSS
VSS
K7
RSV
EXP_RXN9
EXP_RXP9
VSS
EXP_RXN9
EXP_RXP9
VSS
EXP_RXN9
EXP_RXP9
VSS
RSV
RSV
K8
RSV
RSV
RSV
K9
VSS
VSS
VSS
K10
K11
K12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
SDVO_CTRL
DATA
SDVO_CTRLDA
TA
K13
RSV
RSV
SDVO_CTRLDATA
SDVO_CTRLDATA
K14
K15
K16
K17
K18
VSS
RSV
VSS
RSV
VSS
RSV
VSS
RSV
VSS
RSV
VSS
RSV
EXTTS#
HD44
HD43
EXTTS#
HD44
HD43
EXTTS#
HD44
HD43
EXTTS#
HD44
HD43
EXTTS#
HD44
HD43
EXTTS#
HD44
HD43
Datasheet
341
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
L1
HDINV2#
VSS
HDINV2#
VSS
HDINV2#
VSS
HDINV2#
VSS
HDINV2#
VSS
HDINV2#
VSS
HD39
HD34
HD31
VSS
HD39
HD34
HD31
VSS
HD39
HD34
HD31
VSS
HD39
HD34
HD31
VSS
HD39
HD34
HD31
VSS
HD39
HD34
HD31
VSS
HD28
VSS
HD28
VSS
HD28
VSS
HD28
VSS
HD28
VSS
HD28
VSS
HA14#
VSS
HA14#
VSS
HA14#
VSS
HA14#
VSS
HA14#
VSS
HA14#
VSS
HA4#
HA8#
VSS
HA4#
HA8#
VSS
HA4#
HA8#
VSS
HA4#
HA8#
VSS
HA4#
HA8#
VSS
HA4#
HA8#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HA15#
HRS0#
VSS
HA15#
HRS0#
VSS
HA15#
HRS0#
VSS
HA15#
HRS0#
VSS
HA15#
HRS0#
VSS
HA15#
HRS0#
VSS
RSV
EXP_TXN11
VSS
EXP_TXN11
VSS
EXP_TXN11
VSS
RSV
RSV
L2
VSS
VSS
VSS
L3
RSV
EXP_TXP12
VSS
EXP_TXP12
VSS
EXP_TXP12
VSS
RSV
RSV
L4
VSS
VSS
VSS
L5
RSV
EXP_RXN10
EXP_RXP10
VSS
EXP_RXN10
EXP_RXP10
VSS
EXP_RXN10
EXP_RXP10
VSS
RSV
RSV
L6
RSV
RSV
RSV
L7
VSS
VSS
VSS
L8
VSS
VSS
VSS
VSS
VSS
VSS
L9
VSS
VSS
VSS
VSS
VSS
VSS
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DDC_DATA
VSS
RSV
RSV
DDC_DATA
VSS
DDC_DATA
VSS
DDC_DATA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HD30
HD30
HD30
HD30
HD30
HD30
342
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
M1
VSS
HD29
HA18#
VSS
VSS
HD29
VSS
HD29
VSS
HD29
VSS
HD29
HA18#
VSS
VSS
HD29
HA18#
VSS
HA18#
VSS
HA18#
VSS
HA18#
VSS
HA12#
HA9#
HA12#
HA9#
HA12#
HA9#
HA12#
HA9#
HA12#
HA9#
HA12#
HA9#
VSS
VSS
VSS
VSS
VSS
VSS
HA11#
VSS
HA11#
VSS
HA11#
VSS
HA11#
VSS
HA11#
VSS
HA11#
VSS
HLOCK#
HHIT#
HDBSY#
RSV
HLOCK#
HHIT#
HDBSY#
EXP_TXP13
VSS
HLOCK#
HHIT#
HDBSY#
EXP_TXP13
VSS
HLOCK#
HHIT#
HDBSY#
EXP_TXP13
VSS
HLOCK#
HHIT#
HDBSY#
RSV
HLOCK#
HHIT#
HDBSY#
RSV
M2
VSS
VSS
VSS
M3
RSV
EXP_TXN12
VSS
EXP_TXN12
VSS
EXP_TXN12
VSS
RSV
RSV
M4
VSS
VSS
VSS
M5
VSS
VSS
VSS
VSS
VSS
VSS
M6
VSS
VSS
VSS
VSS
VSS
VSS
M7
RSV
EXP_RXN12
EXP_RXP12
VSS
EXP_RXN12
EXP_RXP12
VSS
EXP_RXN12
EXP_RXP12
VSS
RSV
RSV
M8
RSV
RSV
RSV
M9
VSS
VSS
VSS
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DREFCLKN
DREFCLKP
ICH_SYNC#
DDC_CLK
RSV
DREFCLKN
DREFCLKP
ICH_SYNC#
RSV
DREFCLKN
DREFCLKP
ICH_SYNC#
RSV
DREFCLKN
DREFCLKP
ICH_SYNC#
DDC_CLK
RSV
DREFCLKN
DREFCLKP
ICH_SYNC#
DDC_CLK
RSV
DREFCLKN
DREFCLKP
ICH_SYNC#
DDC_CLK
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
HD42
HD38
VSS
HD42
HD42
HD42
HD42
HD38
VSS
HD42
HD38
VSS
HD38
HD38
HD38
VSS
VSS
VSS
HD36
HCLKN
HCLKP
VSS
HD36
HD36
HD36
HD36
HCLKN
HCLKP
VSS
HD36
HCLKN
HCLKP
VSS
HCLKN
HCLKP
VSS
HCLKN
HCLKP
VSS
HCLKN
HCLKP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HA20#
VSS
HA20#
VSS
HA20#
VSS
HA20#
VSS
HA20#
VSS
HA20#
VSS
HA16#
HA16#
HA16#
HA16#
HA16#
HA16#
Datasheet
343
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
M29
M30
M31
M32
M33
M34
M35
N1
VSS
HA10#
HADS#
HDRDY#
—
VSS
HA10#
HADS#
HDRDY#
—
VSS
HA10#
HADS#
HDRDY#
—
VSS
HA10#
HADS#
HDRDY#
—
VSS
HA10#
HADS#
HDRDY#
—
VSS
HA10#
HADS#
HDRDY#
—
VSS
VSS
VSS
VSS
VSS
VSS
HBNR#
RSV
HBNR#
EXP_TXN13
VSS
HBNR#
EXP_TXN13
VSS
HBNR#
EXP_TXN13
VSS
HBNR#
RSV
HBNR#
RSV
N2
VSS
VSS
VSS
N3
RSV
EXP_TXP14
VSS
EXP_TXP14
VSS
EXP_TXP14
VSS
RSV
RSV
N4
VSS
VSS
VSS
N5
RSV
EXP_RXN13
EXP_RXP13
VSS
EXP_RXN13
EXP_RXP13
VSS
EXP_RXN13
EXP_RXP13
VSS
RSV
RSV
N6
RSV
RSV
RSV
N7
VSS
VSS
VSS
N8
VSS
VSS
VSS
VSS
VSS
VSS
N9
VSS
VSS
VSS
VSS
VSS
VSS
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
N31
N32
N33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VCC
VCC
NC
VCC
VCC
VCC
VCC
VCC
NC
VCC
VCC
NC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
HA19#
HADSTB1#
VSS
HA19#
HADSTB1#
VSS
HA19#
HADSTB1#
VSS
HA19#
HADSTB1#
VSS
HA19#
HADSTB1#
VSS
HA19#
HADSTB1#
VSS
HA23#
VSS
HA23#
VSS
HA23#
VSS
HA23#
VSS
HA23#
VSS
HA23#
VSS
HA21#
VSS
HA21#
VSS
HA21#
VSS
HA21#
VSS
HA21#
VSS
HA21#
VSS
HA26#
HA26#
HA26#
HA26#
HA26#
HA26#
344
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
N34
N35
P1
HTRDY#
HHITM#
RSV
HTRDY#
HHITM#
EXP_TXP15
VSS
HTRDY#
HHITM#
EXP_TXP15
VSS
HTRDY#
HHITM#
EXP_TXP15
VSS
HTRDY#
HHITM#
RSV
HTRDY#
HHITM#
RSV
P2
VSS
VSS
VSS
P3
RSV
EXP_TXN14
VSS
EXP_TXN14
VSS
EXP_TXN14
VSS
RSV
RSV
P4
VSS
VSS
VSS
P5
VSS
VSS
VSS
VSS
VSS
VSS
P6
VSS
VSS
VSS
VSS
VSS
VSS
P7
RSV
EXP_RXP14
EXP_RXN14
VSS
EXP_RXP14
EXP_RXN14
VSS
EXP_RXP14
EXP_RXN14
VSS
RSV
RSV
P8
RSV
RSV
RSV
P9
VSS
VSS
VSS
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
R1
RSV
EXP_RXP11
VSS
EXP_RXP11
VSS
EXP_RXP11
VSS
RSV
RSV
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VCC
VCC
NC
VCC
VCC
VCC
VCC
VCC
NC
VCC
VCC
NC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
HA22#
VSS
HA22#
VSS
HA22#
VSS
HA22#
VSS
HA22#
VSS
HA22#
VSS
HA24#
VSS
HA24#
VSS
HA24#
VSS
HA24#
VSS
HA24#
VSS
HA24#
VSS
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HEDRDY#
HRS1#
VSS
HEDRDY#
HRS1#
VSS
HEDRDY#
HRS1#
VSS
HEDRDY#
HRS1#
VSS
HEDRDY#
HRS1#
VSS
HEDRDY#
HRS1#
VSS
RSV
EXP_TXN15
VSS
EXP_TXN15
VSS
EXP_TXN15
VSS
RSV
RSV
R2
VSS
VSS
VSS
R3
DMI_TXP0
DMI_TXP0
DMI_TXP0
DMI_TXP0
DMI_TXP0
DMI_TXP0
Datasheet
345
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
R4
R5
VSS
RSV
VSS
EXP_RXN15
EXP_RXP15
VSS
VSS
EXP_RXN15
EXP_RXP15
VSS
VSS
EXP_RXN15
EXP_RXP15
VSS
VSS
RSV
VSS
RSV
R6
RSV
RSV
RSV
R7
VSS
VSS
VSS
R8
VSS
VSS
VSS
VSS
VSS
VSS
R9
VSS
VSS
VSS
VSS
VSS
VSS
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
T1
RSV
EXP_RXN11
VSS
EXP_RXN11
VSS
EXP_RXN11
VSS
RSV
RSV
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HA25#
HA17#
RSV
HA25#
HA17#
RSV
HA25#
HA17#
RSV
HA25#
HA17#
RSV
HA25#
HA17#
RSV
HA25#
HA17#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
SDQ_A58
HBREQ0#
SDQ_A59
RSV
DMI_TXP1
VSS
DMI_TXP1
VSS
DMI_TXP1
VSS
DMI_TXP1
VSS
DMI_TXP1
VSS
DMI_TXP1
VSS
T2
T3
DMI_TXN0
VSS
DMI_TXN0
VSS
DMI_TXN0
VSS
DMI_TXN0
VSS
DMI_TXN0
VSS
DMI_TXN0
VSS
T4
T5
VSS
VSS
VSS
VSS
VSS
VSS
T6
VSS
VSS
VSS
VSS
VSS
VSS
T7
VSS
VSS
VSS
VSS
VSS
VSS
T8
DMI_RXN1
DMI_RXN1
DMI_RXN1
DMI_RXN1
DMI_RXN1
DMI_RXN1
346
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
U1
DMI_RXP1
VSS
DMI_RXP1
VSS
DMI_RXP1
VSS
DMI_RXP1
VSS
DMI_RXP1
VSS
DMI_RXP1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
HA30#
HA27#
VSS
HA30#
HA27#
VSS
HA30#
HA27#
VSS
HA30#
HA27#
VSS
HA30#
HA27#
VSS
HA30#
HA27#
VSS
HA31#
VSS
HA31#
VSS
HA31#
VSS
HA31#
VSS
HA31#
VSS
HA31#
VSS
HA28#
VSS
HA28#
VSS
HA28#
VSS
HA28#
VSS
HA28#
VSS
HA28#
VSS
SDQ_A62
VSS
SDQ_A62
VSS
SDQ_A62
VSS
SDQ_A62
VSS
SDQ_A62
VSS
SDQ_A62
VSS
SDQ_A63
DMI_TXN1
VSS
SDQ_A63
DMI_TXN1
VSS
SDQ_A63
DMI_TXN1
VSS
SDQ_A63
DMI_TXN1
VSS
SDQ_A63
DMI_TXN1
VSS
SDQ_A63
DMI_TXN1
VSS
U2
U3
DMI_TXP2
VSS
DMI_TXP2
VSS
DMI_TXP2
VSS
DMI_TXP2
VSS
DMI_TXP2
VSS
DMI_TXP2
VSS
U4
U5
DMI_RXP0
DMI_RXN0
VSS
DMI_RXP0
DMI_RXN0
VSS
DMI_RXP0
DMI_RXN0
VSS
DMI_RXP0
DMI_RXN0
VSS
DMI_RXP0
DMI_RXN0
VSS
DMI_RXP0
DMI_RXN0
VSS
U6
U7
U8
VSS
VSS
VSS
VSS
VSS
VSS
U9
VSS
VSS
VSS
VSS
VSS
VSS
U10
U11
U12
U13
DMI_RXN3
VSS
DMI_RXN3
VSS
DMI_RXN3
VSS
DMI_RXN3
VSS
DMI_RXN3
VSS
DMI_RXN3
VSS
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
Datasheet
347
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
V1
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B58
VSS
SDQ_B58
VSS
SDQ_B58
VSS
SDQ_B58
VSS
SDQ_B58
VSS
SDQ_B58
VSS
HA29#
VSS
HA29#
VSS
HA29#
VSS
HA29#
VSS
HA29#
VSS
HA29#
VSS
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDM_A7
SDQS_A7
RSV
SDM_A7
SDQS_A7
RSV
SDM_A7
SDQS_A7
RSV
SDM_A7
SDQS_A7
RSV
SDM_A7
SDQS_A7
RSV
SDM_A7
SDQS_A7
RSV
VSS
VSS
VSS
VSS
VSS
VSS
V2
VSS
VSS
VSS
VSS
VSS
VSS
V3
DMI_TXN2
VSS
DMI_TXN2
VSS
DMI_TXN2
VSS
DMI_TXN2
VSS
DMI_TXN2
VSS
DMI_TXN2
VSS
V4
V5
DMI_TXP3
VSS
DMI_TXP3
VSS
DMI_TXP3
VSS
DMI_TXP3
VSS
DMI_TXP3
VSS
DMI_TXP3
VSS
V6
V7
DMI_RXP2
DMI_RXN2
VSS
DMI_RXP2
DMI_RXN2
VSS
DMI_RXP2
DMI_RXN2
VSS
DMI_RXP2
DMI_RXN2
VSS
DMI_RXP2
DMI_RXN2
VSS
DMI_RXP2
DMI_RXN2
VSS
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
DMI_RXP3
VSS
DMI_RXP3
VSS
DMI_RXP3
VSS
DMI_RXP3
VSS
DMI_RXP3
VSS
DMI_RXP3
VSS
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
348
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
W1
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B63
SDQ_B59
RSV
SDQ_B63
SDQ_B59
RSV
SDQ_B63
SDQ_B59
RSV
SDQ_B63
SDQ_B59
RSV
SDQ_B63
SDQ_B59
RSV
SDQ_B63
SDQ_B59
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_A57
SDQ_A56
VSS
SDQ_A57
SDQ_A56
VSS
SDQ_A57
SDQ_A56
VSS
SDQ_A57
SDQ_A56
VSS
SDQ_A57
SDQ_A56
VSS
SDQ_A57
SDQ_A56
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
DMI_TXN3
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXP_COMPI
VSS
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
Datasheet
349
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
Y1
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B62
SDQS_B7
VSS
SDQ_B57
VSS
SDQ_B57
VSS
SDQ_B57
VSS
SDQ_B57
VSS
SDQ_B57
VSS
SDQ_B57
VSS
SDM_B7
VSS
SDM_B7
VSS
SDM_B7
VSS
SDM_B7
VSS
SDM_B7
VSS
SDM_B7
VSS
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
SDQ_A61
SDQ_A51
SDQ_A60
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
EXP_COMP
O
Y10
EXP_COMPO
EXP_COMPO
EXP_COMPO
EXP_COMPO
EXP_COMPO
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
SDQ_B60
VSS
SDQ_B60
VSS
SDQ_B60
VSS
SDQ_B60
VSS
SDQ_B60
VSS
SDQ_B60
VSS
350
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
Y28
Y29
RSV
VSS
RSV
VSS
RSV
VSS
RSV
VSS
RSV
VSS
RSV
VSS
Y30
RSV
RSV
RSV
RSV
RSV
RSV
Y31
VSS
VSS
VSS
VSS
VSS
VSS
Y32
VSS
VSS
VSS
VSS
VSS
VSS
Y33
SDQ_A50
VSS
SDQ_A50
VSS
SDQ_A50
VSS
SDQ_A50
VSS
SDQ_A50
VSS
SDQ_A50
VSS
Y34
Y35
SDQ_A55
VSS
SDQ_A55
VSS
SDQ_A55
VSS
SDQ_A55
VSS
SDQ_A55
VSS
SDQ_A55
VSS
AA1
AA2
VSS
VSS
VSS
VSS
VSS
VSS
AA3
VSS
VSS
VSS
VSS
VSS
VSS
AA4
VSS
VSS
VSS
VSS
VSS
VSS
AA5
VSS
VSS
VSS
VSS
VSS
VSS
AA6
VSS
VSS
VSS
VSS
VSS
VSS
AA7
VSS
VSS
VSS
VSS
VSS
VSS
AA8
VSS
VSS
VSS
VSS
VSS
VSS
AA9
VSS
VSS
VSS
VSS
VSS
VSS
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B61
SDQ_B56
RSV
SDQ_B61
SDQ_B56
RSV
SDQ_B61
SDQ_B56
RSV
SDQ_B61
SDQ_B56
RSV
SDQ_B61
SDQ_B56
RSV
SDQ_B61
SDQ_B56
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_A54
SDQ_A54
SDQ_A54
SDQ_A54
SDQ_A54
SDQ_A54
Datasheet
351
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
AA33
AA34
AA35
AB1
SDM_A6
SDQS_A6
RSV
SDM_A6
SDQS_A6
RSV
SDM_A6
SDQS_A6
RSV
SDM_A6
SDQS_A6
RSV
SDM_A6
SDQS_A6
RSV
SDM_A6
SDQS_A6
RSV
VCC
VCC
VCC
VCC
VCC
VCC
AB2
VCC
VCC
VCC
VCC
VCC
VCC
AB3
VCC
VCC
VCC
VCC
VCC
VCC
AB4
VCC
VCC
VCC
VCC
VCC
VCC
AB5
VCC
VCC
VCC
VCC
VCC
VCC
AB6
VCC
VCC
VCC
VCC
VCC
VCC
AB7
VCC
VCC
VCC
VCC
VCC
VCC
AB8
VCC
VCC
VCC
VCC
VCC
VCC
AB9
VCC
VCC
VCC
VCC
VCC
VCC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AC1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B51
SDQ_B50
VSS
SDQ_B51
SDQ_B50
VSS
SDQ_B51
SDQ_B50
VSS
SDQ_B51
SDQ_B50
VSS
SDQ_B51
SDQ_B50
VSS
SDQ_B51
SDQ_B50
VSS
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
SDQS_B6
VSS
SDQS_B6
VSS
SDQS_B6
VSS
SDQS_B6
VSS
SDQS_B6
VSS
SDQS_B6
VSS
SMA_A13
SCLK_A2
VSS
SMA_A13
SCLK_A2
VSS
SMA_A13
SCLK_A2
VSS
SMA_A13
SCLK_A2
VSS
SMA_A13
SCLK_A2
VSS
SMA_A13
SCLK_A2
VSS
VCC
VCC
VCC
VCC
VCC
VCC
AC2
VCC
VCC
VCC
VCC
VCC
VCC
352
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
AC3
AC4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSV
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSV
AC5
VCC
VCC
VCC
VCC
AC6
VCC
VCC
VCC
VCC
AC7
VCC
VCC
VCC
VCC
AC8
VCC
VCC
VCC
VCC
AC9
VCC
VCC
VCC
VCC
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AD1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B55
VSS
SDQ_B55
VSS
SDQ_B55
VSS
SDQ_B55
VSS
SDQ_B55
VSS
SDQ_B55
VSS
SDQ_B54
VSS
SDQ_B54
VSS
SDQ_B54
VSS
SDQ_B54
VSS
SDQ_B54
VSS
SDQ_B54
VSS
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCLK_A2#
SCLK_A5#
SCLK_A5
VCC
SCLK_A2#
RSV
SCLK_A2#
SCLK_A5#
SCLK_A5
VCC
SCLK_A2#
SCLK_A5#
SCLK_A5
VCC
SCLK_A2#
SCLK_A5#
SCLK_A5
VCC
SCLK_A2#
RSV
RSV
RSV
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AD2
VCC
VCC
VCC
VCC
AD3
VCC
VCC
VCC
VCC
AD4
VCC
VCC
VCC
VCC
AD5
VCC
VCC
VCC
VCC
AD6
VCC
VCC
VCC
VCC
AD7
VCC
VCC
VCC
VCC
Datasheet
353
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
AD8
AD9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AE1
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B20
VSS
SDQ_B20
VSS
SDQ_B20
VSS
SDQ_B20
VSS
SDQ_B20
VSS
SDQ_B20
VSS
SDQ_B19
SDQ_B23
VSS
SDQ_B19
SDQ_B23
VSS
SDQ_B19
SDQ_B23
VSS
SDQ_B19
SDQ_B23
VSS
SDQ_B19
SDQ_B23
VSS
SDQ_B19
SDQ_B23
VSS
SDQ_A26
SDQ_B24
VSS
SDQ_A26
SDQ_B24
VSS
SDQ_A26
SDQ_B24
VSS
SDQ_A26
SDQ_B24
VSS
SDQ_A26
SDQ_B24
VSS
SDQ_A26
SDQ_B24
VSS
SDQS_B3
SDQ_B31
VSS
SDQS_B3
SDQ_B31
VSS
SDQS_B3
SDQ_B31
VSS
SDQS_B3
SDQ_B31
VSS
SDQS_B3
SDQ_B31
VSS
SDQS_B3
SDQ_B31
VSS
SDQ_B36
SDM_B6
VSS
SDQ_B36
SDM_B6
VSS
SDQ_B36
SDM_B6
VSS
SDQ_B36
SDM_B6
VSS
SDQ_B36
SDM_B6
VSS
SDQ_B36
SDM_B6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCLK_B5#
SCLK_B5
NC
RSV
SCLK_B5#
SCLK_B5
NC
SCLK_B5#
SCLK_B5
NC
SCLK_B5#
SCLK_B5
NC
RSV
RSV
RSV
NC
NC
SDQ_A52
SMA_B13
—
SDQ_A52
SMA_B13
—
SDQ_A52
SMA_B13
—
SDQ_A52
SMA_B13
—
SDQ_A52
SMA_B13
—
SDQ_A52
SMA_B13
—
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A53
SDQ_A5
SDQ_A4
SDQ_A0
VSS
SDQ_A53
SDQ_A5
SDQ_A4
SDQ_A0
VSS
SDQ_A53
SDQ_A5
SDQ_A4
SDQ_A0
VSS
SDQ_A53
SDQ_A5
SDQ_A4
SDQ_A0
VSS
SDQ_A53
SDQ_A5
SDQ_A4
SDQ_A0
VSS
SDQ_A53
SDQ_A5
SDQ_A4
SDQ_A0
VSS
AE2
AE3
AE4
AE5
RSV
RSV
RSV
RSV
RSV
RSV
AE6
VSS
VSS
VSS
VSS
VSS
VSS
AE7
SVREF0
SVREF1
VSS
SVREF0
SVREF1
VSS
SVREF0
SVREF1
VSS
SVREF0
SVREF1
VSS
SVREF0
SVREF1
VSS
SVREF0
SVREF1
VSS
AE8
AE9
SM_SLEWO
UT1
SM_SLEWOU
T1
SM_SLEWOUT
1
AE10
AE11
SM_SLEWOUT1
SDQ_B11
SM_SLEWOUT1
SDQ_B11
SM_SLEWOUT1
SDQ_B11
SDQ_B11
SDQ_B11
SDQ_B11
354
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AF1
VSS
SDQ_B16
VSS
VSS
SDQ_B16
VSS
VSS
SDQ_B16
VSS
VSS
SDQ_B16
VSS
VSS
SDQ_B16
VSS
VSS
SDQ_B16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSV_TP0
VSS
RSV_TP0
VSS
RSV_TP0
VSS
RSV_TP0
VSS
RSV_TP0
VSS
RSV_TP0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A30
VSS
SDQ_A30
VSS
SDQ_A30
VSS
SDQ_A30
VSS
SDQ_A30
VSS
SDQ_A30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B26
VSS
SDQ_B26
VSS
SDQ_B26
VSS
SDQ_B26
VSS
SDQ_B26
VSS
SDQ_B26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCLK_B2#
SCLK_B2
SDQ_B53
VSS
SCLK_B2#
SCLK_B2
SDQ_B53
VSS
SCLK_B2#
SCLK_B2
SDQ_B53
VSS
SCLK_B2#
SCLK_B2
SDQ_B53
VSS
SCLK_B2#
SCLK_B2
SDQ_B53
VSS
SCLK_B2#
SCLK_B2
SDQ_B53
VSS
SDQ_B52
VSS
SDQ_B52
VSS
SDQ_B52
VSS
SDQ_B52
VSS
SDQ_B52
VSS
SDQ_B52
VSS
SDQ_B48
VSS
SDQ_B48
VSS
SDQ_B48
VSS
SDQ_B48
VSS
SDQ_B48
VSS
SDQ_B48
VSS
SDQ_A47
SDQ_A49
SDQ_A48
VSS
SDQ_A47
SDQ_A49
SDQ_A48
VSS
SDQ_A47
SDQ_A49
SDQ_A48
VSS
SDQ_A47
SDQ_A49
SDQ_A48
VSS
SDQ_A47
SDQ_A49
SDQ_A48
VSS
SDQ_A47
SDQ_A49
SDQ_A48
VSS
AF2
SDM_A0
SDQ_A1
VSS
SDM_A0
SDQ_A1
VSS
SDM_A0
SDQ_A1
VSS
SDM_A0
SDQ_A1
VSS
SDM_A0
SDQ_A1
VSS
SDM_A0
SDQ_A1
VSS
AF3
AF4
AF5
RSV
RSV
RSV
RSV
RSV
RSV
AF6
VSS
VSS
VSS
VSS
VSS
VSS
AF7
RSTIN#
VSS
RSTIN#
VSS
RSTIN#
VSS
RSTIN#
VSS
RSTIN#
VSS
RSTIN#
VSS
AF8
SM_SLEWIN
1
AF9
SM_SLEWIN1
SM_SLEWIN1
SM_SLEWIN1
SM_SLEWIN1
SM_SLEWIN1
AF10
AF11
AF12
AF13
AF14
AF15
VSS
SDQ_B10
VSS
VSS
SDQ_B10
VSS
VSS
SDQ_B10
VSS
VSS
SDQ_B10
VSS
VSS
SDQ_B10
VSS
VSS
SDQ_B10
VSS
SDQ_B17
SDQ_B22
VSS
SDQ_B17
SDQ_B22
VSS
SDQ_B17
SDQ_B22
VSS
SDQ_B17
SDQ_B22
VSS
SDQ_B17
SDQ_B22
VSS
SDQ_B17
SDQ_B22
VSS
Datasheet
355
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG1
SDQ_A28
SDQS_A3
VSS
SDQ_A28
SDQS_A3
VSS
SDQ_A28
SDQS_A3
VSS
SDQ_A28
SDQS_A3
VSS
SDQ_A28
SDQS_A3
VSS
SDQ_A28
SDQS_A3
VSS
SDQ_A27
RSV
SDQ_A27
RSV
SDQ_A27
RSV
SDQ_A27
RSV
SDQ_A27
RSV
SDQ_A27
RSV
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B30
SDQ_B32
SDQ_B37
SDQ_B33
VSS
SDQ_B30
SDQ_B32
SDQ_B37
SDQ_B33
VSS
SDQ_B30
SDQ_B32
SDQ_B37
SDQ_B33
VSS
SDQ_B30
SDQ_B32
SDQ_B37
SDQ_B33
VSS
SDQ_B30
SDQ_B32
SDQ_B37
SDQ_B33
VSS
SDQ_B30
SDQ_B32
SDQ_B37
SDQ_B33
VSS
SDQ_B49
SDQ_B47
VSS
SDQ_B49
SDQ_B47
VSS
SDQ_B49
SDQ_B47
VSS
SDQ_B49
SDQ_B47
VSS
SDQ_B49
SDQ_B47
VSS
SDQ_B49
SDQ_B47
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A46
SDQ_A43
VSS
SDQ_A46
SDQ_A43
VSS
SDQ_A46
SDQ_A43
VSS
SDQ_A46
SDQ_A43
VSS
SDQ_A46
SDQ_A43
VSS
SDQ_A46
SDQ_A43
VSS
SDQS_A0
RSV
SDQS_A0
RSV
SDQS_A0
RSV
SDQS_A0
RSV
SDQS_A0
RSV
SDQS_A0
RSV
AG2
AG3
SDQ_A6
SRCOMP0
VSS
SDQ_A6
SRCOMP0
VSS
SDQ_A6
SRCOMP0
VSS
SDQ_A6
SRCOMP0
VSS
SDQ_A6
SRCOMP0
VSS
SDQ_A6
SRCOMP0
VSS
AG4
AG5
AG6
NC
NC
NC
NC
NC
NC
AG7
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
PWROK
SRCOMP1
SDQ_B4
SDQ_B14
SDQ_B15
VSS
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B18
VSS
SDQ_B18
VSS
SDQ_B18
VSS
SDQ_B18
VSS
SDQ_B18
VSS
SDQ_B18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDM_B3
SDM_B3
SDM_B3
SDM_B3
SDM_B3
SDM_B3
356
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AG35
AH1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCLK_B0#
SDM_B4
VSS
SCLK_B0#
SDM_B4
VSS
SCLK_B0#
SDM_B4
VSS
SCLK_B0#
SDM_B4
VSS
SCLK_B0#
SDM_B4
VSS
SCLK_B0#
SDM_B4
VSS
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_B46
VSS
SDQ_B46
VSS
SDQ_B46
VSS
SDQ_B46
VSS
SDQ_B46
VSS
SDQ_B46
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B42
SDQ_B43
SDQ_A42
RSV
SDQ_B42
SDQ_B43
SDQ_A42
RSV
SDQ_B42
SDQ_B43
SDQ_A42
RSV
SDQ_B42
SDQ_B43
SDQ_A42
RSV
SDQ_B42
SDQ_B43
SDQ_A42
RSV
SDQ_B42
SDQ_B43
SDQ_A42
RSV
SDM_A5
SDQS_A5
VSS
SDM_A5
SDQS_A5
VSS
SDM_A5
SDQS_A5
VSS
SDM_A5
SDQS_A5
VSS
SDM_A5
SDQS_A5
VSS
SDM_A5
SDQS_A5
VSS
AH2
SDQ_A2
SDQ_A7
SDQ_B5
VSS
SDQ_A2
SDQ_A7
SDQ_B5
VSS
SDQ_A2
SDQ_A7
SDQ_B5
VSS
SDQ_A2
SDQ_A7
SDQ_B5
VSS
SDQ_A2
SDQ_A7
SDQ_B5
VSS
SDQ_A2
SDQ_A7
SDQ_B5
VSS
AH3
AH4
AH5
AH6
VSS
VSS
VSS
VSS
VSS
VSS
AH7
SDQ_B0
VSS
SDQ_B0
VSS
SDQ_B0
VSS
SDQ_B0
VSS
SDQ_B0
VSS
SDQ_B0
VSS
AH8
AH9
SDM_B1
RSV
SDM_B1
RSV
SDM_B1
RSV
SDM_B1
RSV
SDM_B1
RSV
SDM_B1
RSV
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_B21
SDM_B2
VSS
SDQ_B21
SDM_B2
VSS
SDQ_B21
SDM_B2
VSS
SDQ_B21
SDM_B2
VSS
SDQ_B21
SDM_B2
VSS
SDQ_B21
SDM_B2
VSS
RSV_TP1
SDM_A3
VSS
RSV_TP1
SDM_A3
VSS
RSV_TP1
SDM_A3
VSS
RSV_TP1
SDM_A3
VSS
RSV_TP1
SDM_A3
VSS
RSV_TP1
SDM_A3
VSS
SDQ_A31
SDQ_B29
VSS
SDQ_A31
SDQ_B29
VSS
SDQ_A31
SDQ_B29
VSS
SDQ_A31
SDQ_B29
VSS
SDQ_A31
SDQ_B29
VSS
SDQ_A31
SDQ_B29
VSS
SDQ_B27
SCLK_B0
VSS
SDQ_B27
SCLK_B0
VSS
SDQ_B27
SCLK_B0
VSS
SDQ_B27
SCLK_B0
VSS
SDQ_B27
SCLK_B0
VSS
SDQ_B27
SCLK_B0
VSS
NC
NC
NC
NC
NC
NC
SDQS_B4
SDQS_B4
SDQS_B4
SDQS_B4
SDQS_B4
SDQS_B4
Datasheet
357
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
AH35
AJ1
VSS
SDQ_A32
SDQS_B5
VSS
VSS
SDQ_A32
SDQS_B5
VSS
VSS
SDQ_A32
SDQS_B5
VSS
VSS
SDQ_A32
SDQS_B5
VSS
VSS
SDQ_A32
SDQS_B5
VSS
VSS
SDQ_A32
SDQS_B5
VSS
RSV
RSV
RSV
RSV
RSV
RSV
SDM_B5
VSS
SDM_B5
VSS
SDM_B5
VSS
SDM_B5
VSS
SDM_B5
VSS
SDM_B5
VSS
SDQ_A45
VSS
SDQ_A45
VSS
SDQ_A45
VSS
SDQ_A45
VSS
SDQ_A45
VSS
SDQ_A45
VSS
SDQ_A41
SDQ_A8
SDQ_A3
SDQ_A12
VSS
SDQ_A41
SDQ_A8
SDQ_A3
SDQ_A12
VSS
SDQ_A41
SDQ_A8
SDQ_A3
SDQ_A12
VSS
SDQ_A41
SDQ_A8
SDQ_A3
SDQ_A12
VSS
SDQ_A41
SDQ_A8
SDQ_A3
SDQ_A12
VSS
SDQ_A41
SDQ_A8
SDQ_A3
SDQ_A12
VSS
AJ2
AJ3
AJ4
AJ5
SDM_B0
SDQ_B1
SDQ_B8
SDQ_B12
VSS
SDM_B0
SDQ_B1
SDQ_B8
SDQ_B12
VSS
SDM_B0
SDQ_B1
SDQ_B8
SDQ_B12
VSS
SDM_B0
SDQ_B1
SDQ_B8
SDQ_B12
VSS
SDM_B0
SDQ_B1
SDQ_B8
SDQ_B12
VSS
SDM_B0
SDQ_B1
SDQ_B8
SDQ_B12
VSS
AJ6
AJ7
AJ8
AJ9
AJ10
AJ11
VSS
VSS
VSS
VSS
VSS
VSS
SCLK_B1#
SCLK_B1#
SCLK_B1#
SCLK_B1#
SCLK_B1#
SCLK_B1#
SM_SLEWIN
0
AJ12
SM_SLEWIN0
SM_SLEWIN0
SM_SLEWIN0
SM_SLEWIN0
SM_SLEWIN0
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A29
RSV
SDQ_A29
RSV
SDQ_A29
RSV
SDQ_A29
RSV
SDQ_A29
RSV
SDQ_A29
RSV
VSS
VSS
VSS
VSS
VSS
VSS
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_B38
SDQ_B35
VSS
SDQ_B38
SDQ_B35
VSS
SDQ_B38
SDQ_B35
VSS
SDQ_B38
SDQ_B35
VSS
SDQ_B38
SDQ_B35
VSS
SDQ_B38
SDQ_B35
VSS
SDQ_A37
SDQ_B40
SDQ_A37
SDQ_B40
SDQ_A37
SDQ_B40
SDQ_A37
SDQ_B40
SDQ_A37
SDQ_B40
SDQ_A37
SDQ_B40
358
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AK1
VSS
SDQ_B41
VSS
VSS
SDQ_B41
VSS
VSS
SDQ_B41
VSS
VSS
SDQ_B41
VSS
VSS
SDQ_B41
VSS
VSS
SDQ_B41
VSS
SDQ_A44
SDQ_A40
VSS
SDQ_A44
SDQ_A40
VSS
SDQ_A44
SDQ_A40
VSS
SDQ_A44
SDQ_A40
VSS
SDQ_A44
SDQ_A40
VSS
SDQ_A44
SDQ_A40
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK2
SDQ_A9
SDQ_A13
VSS
SDQ_A9
SDQ_A13
VSS
SDQ_A9
SDQ_A13
VSS
SDQ_A9
SDQ_A13
VSS
SDQ_A9
SDQ_A13
VSS
SDQ_A9
SDQ_A13
VSS
AK3
AK4
AK5
SDQS_B0
VSS
SDQS_B0
VSS
SDQS_B0
VSS
SDQS_B0
VSS
SDQS_B0
VSS
SDQS_B0
VSS
AK6
AK7
VSS
VSS
VSS
VSS
VSS
VSS
AK8
VSS
VSS
VSS
VSS
VSS
VSS
AK9
SCLK_B4
SDQS_B1
VSS
SCLK_B4
SDQS_B1
VSS
SCLK_B4
SDQS_B1
VSS
SCLK_B4
SDQS_B1
VSS
SCLK_B4
SDQS_B1
VSS
RSV
AK10
AK11
SDQS_B1
VSS
SM_SLEWO
UT0
SM_SLEWOU
T0
SM_SLEWOUT
0
AK12
SM_SLEWOUT0
SM_SLEWOUT0
SM_SLEWOUT0
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
SDQS_B2
VSS
SDQS_B2
VSS
SDQS_B2
VSS
SDQS_B2
VSS
SDQS_B2
VSS
SDQS_B2
VSS
RSV_TP3
SDQ_A24
VSS
RSV_TP3
SDQ_A24
VSS
RSV_TP3
SDQ_A24
VSS
RSV_TP3
SDQ_A24
VSS
RSV_TP3
SDQ_A24
VSS
RSV_TP3
SDQ_A24
VSS
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_B25
VSS
SDQ_B25
VSS
SDQ_B25
VSS
SDQ_B25
VSS
SDQ_B25
VSS
SDQ_B25
VSS
RSV
RSV
RSV
RSV
RSV
RSV
SCLK_B3#
VSS
RSV
SCLK_B3#
VSS
SCLK_B3#
VSS
SCLK_B3#
VSS
RSV
RSV
VSS
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDQ_A33
VSS
SDQ_A33
VSS
SDQ_A33
VSS
SDQ_A33
VSS
SDQ_A33
VSS
SDQ_A33
VSS
SDM_A4
VSS
SDM_A4
VSS
SDM_A4
VSS
SDM_A4
VSS
SDM_A4
VSS
SDM_A4
VSS
SDQ_A35
SDQ_B45
SDQ_B44
SDQ_A35
SDQ_B45
SDQ_B44
SDQ_A35
SDQ_B45
SDQ_B44
SDQ_A35
SDQ_B45
SDQ_B44
SDQ_A35
SDQ_B45
SDQ_B44
SDQ_A35
SDQ_B45
SDQ_B44
Datasheet
359
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
AK34
AK35
AL1
SCS_A2#
VCCSM
SDM_A1
RSV
SCS_A2#
VCCSM
SDM_A1
RSV
SCS_A2#
VCCSM
SDM_A1
RSV
SCS_A2#
VCCSM
SDM_A1
RSV
SCS_A2#
VCCSM
SDM_A1
RSV
RSV
VCCSM
SDM_A1
RSV
AL2
AL3
SDQS_A1
RSV
SDQS_A1
RSV
SDQS_A1
RSV
SDQS_A1
RSV
SDQS_A1
RSV
SDQS_A1
RSV
AL4
AL5
SDQ_B2
SDQ_B7
SDQ_B9
SDQ_B13
SCLK_B4#
VSS
SDQ_B2
SDQ_B7
SDQ_B9
SDQ_B13
RSV
SDQ_B2
SDQ_B7
SDQ_B9
SDQ_B13
SCLK_B4#
VSS
SDQ_B2
SDQ_B7
SDQ_B9
SDQ_B13
SCLK_B4#
VSS
SDQ_B2
SDQ_B7
SDQ_B9
SDQ_B13
SCLK_B4#
VSS
SDQ_B2
SDQ_B7
SDQ_B9
SDQ_B13
RSV
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AM1
AM2
AM3
VSS
VSS
SCLK_B1
SCKE_A0
VSS
SCLK_B1
SCKE_A0
VSS
SCLK_B1
SCKE_A0
VSS
SCLK_B1
SCKE_A0
VSS
SCLK_B1
SCKE_A0
VSS
SCLK_B1
SCKE_A0
VSS
RSV
RSV
RSV
RSV
RSV
RSV
SMA_B7
VSS
SMA_B7
VSS
SMA_B7
VSS
SMA_B7
VSS
SMA_B7
VSS
SMA_B7
VSS
SDQ_A25
SDQ_B28
VSS
SDQ_A25
SDQ_B28
VSS
SDQ_A25
SDQ_B28
VSS
SDQ_A25
SDQ_B28
VSS
SDQ_A25
SDQ_B28
VSS
SDQ_A25
SDQ_B28
VSS
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
SCLK_B3
RSV
RSV
SCLK_B3
RSV
SCLK_B3
RSV
SCLK_B3
RSV
RSV
RSV
RSV
SDQ_B34
SDQ_B39
SDQ_A36
NC
SDQ_B34
SDQ_B39
SDQ_A36
NC
SDQ_B34
SDQ_B39
SDQ_A36
NC
SDQ_B34
SDQ_B39
SDQ_A36
NC
SDQ_B34
SDQ_B39
SDQ_A36
NC
SDQ_B34
SDQ_B39
SDQ_A36
NC
RSV
RSV
RSV
RSV
RSV
RSV
SDQ_A38
SDQ_A39
VSS
SDQ_A38
SDQ_A39
VSS
SDQ_A38
SDQ_A39
VSS
SDQ_A38
SDQ_A39
VSS
SDQ_A38
SDQ_A39
VSS
SDQ_A38
SDQ_A39
VSS
SCS_A3#
SCAS_A#
SCS_A1#
—
RSV
SCS_A3#
SCAS_A#
SCS_A1#
—
SCS_A3#
SCAS_A#
SCS_A1#
—
SCS_A3#
SCAS_A#
SCS_A1#
—
RSV
SCAS_A#
SCS_A1#
—
SCAS_A#
SCS_A1#
—
SCLK_A4
SCLK_A4#
RSV
SCLK_A4
SCLK_A4#
SCLK_A4
SCLK_A4#
SCLK_A4
SCLK_A4#
RSV
RSV
RSV
360
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
AM4
AM5
VSS
SDQ_B6
VSS
VSS
SDQ_B6
VSS
VSS
SDQ_B6
VSS
VSS
SDQ_B6
VSS
VSS
SDQ_B6
VSS
VSS
SDQ_B6
VSS
AM6
AM7
VSS
VSS
VSS
VSS
VSS
VSS
AM8
VSS
VSS
VSS
VSS
VSS
VSS
AM9
SCKE_B1
VCCSM
VCCSM
SMA_B12
VCCSM
VCCSM
SMA_A9
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SMA_A4
VCCSM
VCCSM
SCLK_A0
VCCSM
VCCSM
SBS_B0
VCCSM
VSS
SCKE_B1
VCCSM
VCCSM
SMA_B12
VCCSM
VCCSM
SMA_A9
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SMA_A4
VCCSM
VCCSM
SCLK_A0
VCCSM
VCCSM
SBS_B0
VCCSM
VSS
SCKE_B1
VCCSM
VCCSM
SMA_B12
VCCSM
VCCSM
SMA_A9
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SMA_A4
VCCSM
VCCSM
SCLK_A0
VCCSM
VCCSM
SBS_B0
VCCSM
VSS
SCKE_B1
VCCSM
VCCSM
SMA_B12
VCCSM
VCCSM
SMA_A9
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SMA_A4
VCCSM
VCCSM
SCLK_A0
VCCSM
VCCSM
SBS_B0
VCCSM
VSS
SCKE_B1
VCCSM
VCCSM
SMA_B12
VCCSM
VCCSM
SMA_A9
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SMA_A4
VCCSM
VCCSM
SCLK_A0
VCCSM
VCCSM
SBS_B0
VCCSM
VSS
SCKE_B1
VCCSM
VCCSM
SMA_B12
VCCSM
VCCSM
SMA_A9
VCCSM
VCCSM
SMA_B0
VCCSM
VCCSM
SMA_A4
VCCSM
VCCSM
SCLK_A0
VCCSM
VCCSM
SBS_B0
VCCSM
VSS
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AN1
SDQS_A4
VSS
SDQS_A4
VSS
SDQS_A4
VSS
SDQS_A4
VSS
SDQS_A4
VSS
SDQS_A4
VSS
VCCSM
SCS_B3#
SCS_A0#
—
VCCSM
RSV
VCCSM
SCS_B3#
SCS_A0#
—
VCCSM
SCS_B3#
SCS_A0#
—
VCCSM
SCS_B3#
SCS_A0#
—
VCCSM
RSV
SCS_A0#
—
SCS_A0#
—
VSS
VSS
VSS
VSS
VSS
VSS
AN2
SCLK_A1
SCLK_A1#
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A18
SCLK_A1
SCLK_A1#
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A18
SCLK_A1
SCLK_A1#
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A18
SCLK_A1
SCLK_A1#
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A18
SCLK_A1
SCLK_A1#
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A18
SCLK_A1
SCLK_A1#
SDQ_A10
SDQ_A20
SDQ_B3
SDM_A2
SDQ_A18
AN3
AN4
AN5
AN6
AN7
AN8
Datasheet
361
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AP1
SDQ_A23
SCKE_B0
SCKE_A1
—
SDQ_A23
SCKE_B0
SCKE_A1
—
SDQ_A23
SCKE_B0
SCKE_A1
—
SDQ_A23
SCKE_B0
SCKE_A1
—
SDQ_A23
SCKE_B0
SCKE_A1
—
SDQ_A23
SCKE_B0
SCKE_A1
—
SMA_B9
RSV_TP2
SMA_B5
SMA_A7
SMA_B2
SMA_A8
NC
SMA_B9
RSV_TP2
SMA_B5
SMA_A7
SMA_B2
SMA_A8
NC
SMA_B9
RSV_TP2
SMA_B5
SMA_A7
SMA_B2
SMA_A8
NC
SMA_B9
RSV_TP2
SMA_B5
SMA_A7
SMA_B2
SMA_A8
NC
SMA_B9
RSV_TP2
SMA_B5
SMA_A7
SMA_B2
SMA_A8
NC
SMA_B9
RSV_TP2
SMA_B5
SMA_A7
SMA_B2
SMA_A8
NC
SMA_B10
SMA_A2
SMA_A0
SMA_A10
—
SMA_B10
SMA_A2
SMA_A0
SMA_A10
—
SMA_B10
SMA_A2
SMA_A0
SMA_A10
—
SMA_B10
SMA_A2
SMA_A0
SMA_A10
—
SMA_B10
SMA_A2
SMA_A0
SMA_A10
—
SMA_B10
SMA_A2
SMA_A0
SMA_A10
—
SCLK_A0#
SCLK_A3#
SCAS_B#
SBS_A0
SRAS_A#
SDQ_A34
RSV
SCLK_A0#
SCLK_A3#
SCAS_B#
SBS_A0
SRAS_A#
SDQ_A34
RSV
SCLK_A0#
SCLK_A3#
SCAS_B#
SBS_A0
SRAS_A#
SDQ_A34
RSV
SCLK_A0#
SCLK_A3#
SCAS_B#
SBS_A0
SRAS_A#
SDQ_A34
RSV
SCLK_A0#
SCLK_A3#
SCAS_B#
SBS_A0
SRAS_A#
SDQ_A34
RSV
SCLK_A0#
RSV
SCAS_B#
SBS_A0
SRAS_A#
SDQ_A34
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SCS_B2#
SCS_B1#
VCCSM
NC
RSV
SCS_B2#
SCS_B1#
VCCSM
NC
SCS_B2#
SCS_B1#
VCCSM
NC
SCS_B2#
SCS_B1#
VCCSM
NC
RSV
SCS_B1#
VCCSM
NC
SCS_B1#
VCCSM
NC
AP2
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A16
SDQ_A21
SDQS_A2
VSS
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A16
SDQ_A21
SDQS_A2
VSS
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A16
SDQ_A21
SDQS_A2
VSS
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A16
SDQ_A21
SDQS_A2
VSS
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A16
SDQ_A21
SDQS_A2
VSS
SDQ_A14
SDQ_A15
SDQ_A11
SDQ_A16
SDQ_A21
SDQS_A2
VSS
AP3
AP4
AP5
AP6
AP7
AP8
AP9
SDQ_A19
SCKE_B2
SCKE_A2
VCCSM
SMA_A12
SDQ_A19
RSV
SDQ_A19
SCKE_B2
SCKE_A2
VCCSM
SMA_A12
SDQ_A19
SCKE_B2
SCKE_A2
VCCSM
SMA_A12
SDQ_A19
SCKE_B2
SCKE_A2
VCCSM
SMA_A12
SDQ_A19
RSV
AP10
AP11
AP12
AP13
RSV
RSV
VCCSM
SMA_A12
VCCSM
SMA_A12
362
Datasheet
Ballout and Package Information
R
Intel®
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
82915GL
GMCH6
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AR1
SMA_B8
SMA_A11
VCCSM
SMA_B6
SMA_B1
SMA_A5
VCCSM
SMA_A3
SMA_A1
RSV
SMA_B8
SMA_A11
VCCSM
SMA_B6
SMA_B1
SMA_A5
VCCSM
SMA_A3
SMA_A1
RSV
SMA_B8
SMA_A11
VCCSM
SMA_B6
SMA_B1
SMA_A5
VCCSM
SMA_A3
SMA_A1
RSV
SMA_B8
SMA_A11
VCCSM
SMA_B6
SMA_B1
SMA_A5
VCCSM
SMA_A3
SMA_A1
RSV
SMA_B8
SMA_A11
VCCSM
SMA_B6
SMA_B1
SMA_A5
VCCSM
SMA_A3
SMA_A1
RSV
SMA_B8
SMA_A11
VCCSM
SMA_B6
SMA_B1
SMA_A5
VCCSM
SMA_A3
SMA_A1
RSV
VCCSM
SCLK_A3
SBS_A1
SRAS_B#
VCCSM
RSV
VCCSM
RSV
VCCSM
SCLK_A3
SBS_A1
SRAS_B#
VCCSM
RSV
VCCSM
SCLK_A3
SBS_A1
SRAS_B#
VCCSM
RSV
VCCSM
SCLK_A3
SBS_A1
SRAS_B#
VCCSM
RSV
VCCSM
RSV
SBS_A1
SRAS_B#
VCCSM
RSV
SBS_A1
SRAS_B#
VCCSM
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SWE_A#
RSV
SWE_A#
RSV
SWE_A#
RSV
SWE_A#
RSV
SWE_A#
RSV
SWE_A#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SCS_B0#
NC
SCS_B0#
NC
SCS_B0#
NC
SCS_B0#
NC
SCS_B0#
NC
SCS_B0#
NC
NC
NC
NC
NC
NC
NC
AR2
NC
NC
NC
NC
NC
NC
AR3
VSS
VSS
VSS
VSS
VSS
VSS
AR4
—
—
—
—
—
—
AR5
SDQ_A17
VSS
SDQ_A17
VSS
SDQ_A17
VSS
SDQ_A17
VSS
SDQ_A17
VSS
SDQ_A17
VSS
AR6
AR7
RSV
RSV
RSV
RSV
RSV
RSV
AR8
SDQ_A22
SCKE_B3
VCCSM
SCKE_A3
SMA_B11
VSS
SDQ_A22
RSV
SDQ_A22
SCKE_B3
VCCSM
SCKE_A3
SMA_B11
VSS
SDQ_A22
SCKE_B3
VCCSM
SCKE_A3
SMA_B11
VSS
SDQ_A22
SCKE_B3
VCCSM
SCKE_A3
SMA_B11
VSS
SDQ_A22
RSV
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
VCCSM
RSV
VCCSM
RSV
SMA_B11
VSS
SMA_B11
VSS
VCCSM
SMA_B4
SMA_B3
VSS
VCCSM
SMA_B4
SMA_B3
VSS
VCCSM
SMA_B4
SMA_B3
VSS
VCCSM
SMA_B4
SMA_B3
VSS
VCCSM
SMA_B4
SMA_B3
VSS
VCCSM
SMA_B4
SMA_B3
VSS
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
Datasheet
363
Ballout and Package Information
R
Intel®
82915GL
GMCH6
Intel®
82915PL
MCH5
Ball
#
Intel® 82915P
MCH1
Intel® 82915G
GMCH 2
Intel® 82915GV
GMCH 3
Intel® 82910GL
GMCH 4
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
SBS_B1
SMA_A6
VSS
SBS_B1
SMA_A6
VSS
SBS_B1
SMA_A6
VSS
SBS_B1
SMA_A6
VSS
SBS_B1
SMA_A6
VSS
SBS_B1
SMA_A6
VSS
VCCSM
RSV
VCCSM
RSV
VCCSM
RSV
VCCSM
RSV
VCCSM
RSV
VCCSM
RSV
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VCCSM
SWE_B#
RSV
VCCSM
SWE_B#
RSV
VCCSM
SWE_B#
RSV
VCCSM
SWE_B#
RSV
VCCSM
SWE_B#
RSV
VCCSM
SWE_B#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
VSS
VSS
VSS
VSS
VSS
VSS
VCCSM
—
VCCSM
—
VCCSM
—
VCCSM
—
VCCSM
—
VCCSM
—
VCCSM
NC
VCCSM
NC
VCCSM
NC
VCCSM
NC
VCCSM
NC
VCCSM
NC
NC
NC
NC
NC
NC
NC
NOTES:
1. DDR, PCI Express* x16 Graphics Interface, No DAC, No Intel® SDVO
2. DDR, PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
3. DDR, No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
4. DDR (One DIMM per Channel), No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
5. DDR (One DIMM per Channel), PCI Express* x16 Graphics Interface, No DAC, No Intel® SDVO
6. DDR, No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
364
Datasheet
Ballout and Package Information
R
Table 14-4. GMCH/MCH Ballout for DDR Systems (Sorted by Signal Name)
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
H14
BLUE
RSV
RSV
RSV
RSV
BLUE
BLUE#
BLUE
BLUE
BLUE#
BLUE#
BLUE#
J14
H16
E15
D17
M15
L14
U6
BSEL0
BSEL0
BSEL0
BSEL0
BSEL0
BSEL0
BSEL1
BSEL1
BSEL1
BSEL1
BSEL1
BSEL1
BSEL2
BSEL2
BSEL2
BSEL2
BSEL2
BSEL2
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
RSV
RSV
RSV
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
RSV
DDC_CLK
DDC_DATA
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
RSV
RSV
RSV
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DREFCLKN
DREFCLKP
EXP_COMPI
EXP_COMPO
T8
V8
U10
U5
T9
V7
V10
T3
U1
V3
W5
R3
T1
U3
V5
M12
M13
W10
Y10
RSV
RSV
RSV
SDVOC_
TVCLKIN-
SDVOC_
TVCLKIN-
SDVOC_TVCLKIN-
EXP_RXN0
EXP_RXN0
EXP_RXN0
F11
SDVOB_INT-
SDVOC_STALL-
RSV
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
SDVOB_INT-
SDVOC_STALL-
RSV
SDVOB_INT-
SDVOC_STALL-
RSV
H11
E9
E7
B4
E5
G5
H7
J5
RSV
RSV
RSV
SDVOC_INT-
RSV
SDVOC_INT-
RSV
SDVOC_INT-
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
K7
Datasheet
365
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
RSV
RSV
RSV
RSV
RSV
RSV
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
L5
R10
M7
N5
P8
R5
SDVOC_
TVCLKIN+
SDVOC_
TVCLKIN+
SDVOC_TVCLKIN+
EXP_RXP0
EXP_RXP0
EXP_RXP0
E11
SDVOB_INT+
SDVOC_STALL+
RSV
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_SLR
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_SLR
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_SLR
SDVOB_INT+
SDVOC_STALL+
RSV
SDVOB_INT+
SDVOC_STALL+
RSV
J11
F9
F7
RSV
RSV
RSV
B3
D5
G6
H8
J6
SDVOC_INT+
RSV
SDVOC_INT+
RSV
SDVOC_INT+
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
K8
L6
RSV
RSV
RSV
RSV
RSV
RSV
P10
M8
N6
P7
R6
A16
C9
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
SDVOB_RED-
SDVOB_GREEN-
SDVOB_BLUE-
SDVOB_CLK-
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
SDVOB_RED-
SDVOB_RED-
SDVOB_GREEN- SDVOB_GREEN- A8
SDVOB_BLUE-
SDVOB_CLK-
SDVOB_BLUE-
SDVOB_CLK-
C7
A6
SDVOC_RED-/
SDVOB_ALPHA-
SDVOC_RED-/
SDVOB_ALPHA-
SDVOC_RED-/
SDVOB_ALPHA-
EXP_TXN4
EXP_TXN4
EXP_TXN4
C5
SDVOC_GREEN-
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
SDVOC_GREEN- SDVOC_GREEN- D2
SDVOC_BLUE-
SDVOC_CLK-
RSV
SDVOC_BLUE-
SDVOC_CLK-
RSV
SDVOC_BLUE-
SDVOC_CLK-
RSV
F3
G1
H3
J1
RSV
RSV
RSV
RSV
RSV
RSV
K3
L1
RSV
RSV
RSV
RSV
RSV
RSV
M3
N1
P3
R1
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
366
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
C10
GMCH3
SDVOB_RED+
EXP_TXP0
EXP_TXP1
EXP_TXP0
EXP_TXP1
EXP_TXP0
EXP_TXP1
SDVOB_RED+
SDVOB_RED+
SDVOB_
GREEN+
SDVOB_
GREEN+
SDVOB_GREEN+
A9
SDVOB_BLUE+
SDVOB_CLK+
EXP_TXP2
EXP_TXP3
EXP_TXP2
EXP_TXP3
EXP_TXP2
EXP_TXP3
SDVOB_BLUE+
SDVOB_CLK+
SDVOB_BLUE+
SDVOB_CLK+
C8
A7
SDVOC_RED+/
SDVOB_
SDVOC_RED+/
SDVOB_
SDVOC_RED+/
SDVOB_ALPHA+
EXP_TXP4
EXP_TXP5
EXP_TXP4
EXP_TXP5
EXP_TXP4
EXP_TXP5
C6
C2
ALPHA+
ALPHA+
SDVOC_GREEN
+
SDVOC_GREEN
+
SDVOC_GREEN+
SDVOC_BLUE+
SDVOC_CLK+
RSV
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
EXTTS#
GCLKN
GCLKP
RSV
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
EXTTS#
GCLKN
GCLKP
RSV
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
EXTTS#
GCLKN
SDVOC_BLUE+
SDVOC_CLK+
RSV
SDVOC_BLUE+
SDVOC_CLK+
RSV
E3
F1
G3
RSV
RSV
RSV
H1
RSV
RSV
RSV
J3
RSV
RSV
RSV
K1
RSV
RSV
RSV
L3
RSV
RSV
RSV
M1
RSV
RSV
RSV
N3
RSV
RSV
RSV
P1
EXTTS#
GCLKN
GCLKP
GREEN
GREEN#
HA3#
EXTTS#
GCLKN
GCLKP
GREEN
GREEN#
HA3#
EXTTS#
GCLKN
GCLKP
GREEN
GREEN#
HA3#
K16
B11
A11
D14
E14
H29
K29
J29
G30
G32
K30
L29
M30
L31
L28
J28
K27
K33
M28
R29
L26
GCLKP
GREEN
GREEN#
HA3#
RSV
RSV
HA3#
HA3#
HA4#
HA4#
HA4#
HA4#
HA4#
HA4#
HA5#
HA5#
HA5#
HA5#
HA5#
HA5#
HA6#
HA6#
HA6#
HA6#
HA6#
HA6#
HA7#
HA7#
HA7#
HA7#
HA7#
HA7#
HA8#
HA8#
HA8#
HA8#
HA8#
HA8#
HA9#
HA9#
HA9#
HA9#
HA9#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA10#
HA10#
HA10#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA11#
HA11#
HA11#
HA12#
HA12#
HA12#
HA13#
HA13#
HA13#
HA14#
HA14#
HA14#
HA15#
HA15#
HA15#
HA16#
HA16#
HA16#
HA17#
HA17#
HA17#
HA18#
HA18#
HA18#
Datasheet
367
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB0#
HADSTB1#
HBNR#
HBPRI#
HBREQ0#
HCLKN
HCLKP
HCPURST#
HD0
N26
M26
N31
P26
N29
P28
R28
N33
T27
T31
U28
T26
T29
M31
J31
N27
M35
E30
R33
M22
M23
G24
J33
HD1
HD1
HD1
HD1
HD1
HD1
H33
J34
HD2
HD2
HD2
HD2
HD2
HD2
HD3
HD3
HD3
HD3
HD3
HD3
G35
H35
G34
F34
G33
D34
C33
D33
B34
C34
B33
C32
B32
E28
C30
HD4
HD4
HD4
HD4
HD4
HD4
HD5
HD5
HD5
HD5
HD5
HD5
HD6
HD6
HD6
HD6
HD6
HD6
HD7
HD7
HD7
HD7
HD7
HD7
HD8
HD8
HD8
HD8
HD8
HD8
HD9
HD9
HD9
HD9
HD9
HD9
HD10
HD10
HD10
HD10
HD10
HD10
HD11
HD11
HD11
HD11
HD11
HD11
HD12
HD12
HD12
HD12
HD12
HD12
HD13
HD13
HD13
HD13
HD13
HD13
HD14
HD14
HD14
HD14
HD14
HD14
HD15
HD15
HD15
HD15
HD15
HD15
HD16
HD16
HD16
HD16
HD16
HD16
HD17
HD17
HD17
HD17
HD17
HD17
368
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
D29
GMCH3
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
H28
G29
J27
F28
F27
E27
E25
G25
J25
K25
L25
L23
K23
J22
J24
K22
J21
M21
H23
M19
K21
H20
H19
M18
K18
K17
G18
H18
F17
A25
C27
C31
B30
B31
A31
B27
A29
C28
A28
Datasheet
369
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
HD58
HD59
HD58
HD59
HD58
HD59
HD58
HD59
HD58
HD59
HD58
HD59
C25
C26
D27
A27
E24
B25
L35
J35
E34
J26
K19
B26
M32
E35
F26
F19
C29
E33
H26
J19
B29
P33
L34
N35
L33
E31
B23
F33
E32
H31
G31
F31
K34
P34
J32
D24
A23
E12
N34
A24
HD60
HD60
HD60
HD60
HD60
HD60
HD61
HD61
HD61
HD61
HD61
HD61
HD62
HD62
HD62
HD62
HD62
HD62
HD63
HD63
HD63
HD63
HD63
HD63
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HHITM#
HLOCK#
HPCREQ#
HRCOMP
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS1#
HRS1#
HRS1#
HRS1#
HRS1#
HRS2#
HRS2#
HRS2#
HRS2#
HRS2#
HRS2#
HSCOMP
HSWING
HSYNC
HSCOMP
HSWING
RSV
HSCOMP
HSWING
RSV
HSCOMP
HSWING
HSYNC
HSCOMP
HSWING
HSYNC
HSCOMP
HSWING
HSYNC
HTRDY#
HVREF
HTRDY#
HVREF
HTRDY#
HVREF
HTRDY#
HVREF
HTRDY#
HVREF
HTRDY#
HVREF
370
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
M14
GMCH3
ICH_SYNC#
MTYPE
NC
ICH_SYNC#
MTYPE
NC
ICH_SYNC#
MTYPE
NC
ICH_SYNC#
MTYPE
NC
ICH_SYNC#
MTYPE
NC
ICH_SYNC#
MTYPE
NC
C15
A2
NC
NC
NC
NC
NC
NC
A34
NC
NC
NC
NC
NC
NC
A35
NC
NC
NC
NC
NC
NC
AA12
AB12
AC23
AC24
AD30
AG6
AH24
AJ14
AL28
AN19
AP1
AP35
AR1
AR2
AR34
AR35
B1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B35
NC
NC
NC
NC
NC
NC
C16
E16
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
F12
NC
NC
NC
NC
NC
NC
F24
NC
NC
NC
NC
NC
NC
G12
H12
H15
H17
J12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K12
NC
NC
NC
NC
NC
NC
L12
NC
NC
NC
NC
NC
NC
L19
NC
NC
NC
NC
NC
NC
N12
N22
N23
N24
P12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Datasheet
371
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P23
P24
NC
NC
NC
NC
NC
NC
P30
NC
NC
NC
NC
NC
NC
R12
NC
NC
NC
NC
NC
NC
R24
NC
NC
NC
NC
NC
NC
T12
NC
NC
NC
NC
NC
NC
U12
NC
NC
NC
NC
NC
NC
V12
NC
NC
NC
NC
NC
NC
W12
Y12
NC
NC
NC
NC
NC
NC
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RSV
RSV
RSV
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RSV
RSV
RSV
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PWROK
RED
RED#
REFSET
RSTIN#
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
AG7
F14
G14
A15
AF7
AA30
AA31
AA35
AB29
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC30
AE5
AF20
AF5
AG17
AG2
AG26
AG33
AH10
AH30
372
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
GMCH3
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
AJ18
AJ20
AJ21
AJ23
AJ24
AK18
AK21
AK24
AL14
AL2
AL20
AL21
AL24
AL29
AL4
AN31
AN32
AP23
AP29
AP30
AP32
AP33
AR23
AR24
AR28
AR29
AR7
B15
C14
F15
G16
K15
M16
R30
R31
R35
U30
U35
V30
V31
Datasheet
373
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
V32
RSV
RSV
RSV
RSV
Y28
RSV
RSV
RSV
RSV
RSV
RSV
Y30
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
SBS_A1
SBS_B0
SBS_B1
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
RSV
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
RSV_TP0
RSV_TP1
RSV_TP2
RSV_TP3
SBS_A0
SBS_A1
SBS_B0
SBS_B1
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
RSV
AE16
AH15
AN14
AK15
AN28
AP26
AM27
AR19
AL34
AN27
AL12
AN11
AP11
AR11
AN10
AM9
SBS_A1
SBS_A1
SBS_A1
SBS_A1
SBS_B0
SBS_B0
SBS_B0
SBS_B0
SBS_B1
SBS_B1
SBS_B1
SBS_B1
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCAS_A#
SCAS_B#
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
RSV
RSV
SCKE_B0
SCKE_B1
RSV
SCKE_B0
SCKE_B1
RSV
AP10
AR9
RSV
RSV
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
RSV
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
RSV
AM24
AN25
AN2
AN3
AB34
AC33
AP25
AN26
AM2
RSV
RSV
RSV
RSV
RSV
RSV
AM3
RSV
RSV
AC35
AC34
AH22
AG23
AL11
AJ11
AE26
AE25
AL23
RSV
RSV
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
RSV
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
RSV
374
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
GMCH3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
RSV
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
RSV
AK22
AK9
RSV
RSV
RSV
RSV
AL9
RSV
RSV
AD29
AD28
AM34
AL35
AK34
AL33
AP34
AN34
AN33
AM33
AF2
RSV
RSV
SCS_A0#
SCS_A1#
RSV
SCS_A0#
SCS_A1#
RSV
RSV
RSV
SCS_B0#
SCS_B1#
RSV
SCS_B0#
SCS_B1#
RSV
RSV
RSV
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7
SDQ_A8
SDQ_A9
SDQ_A10
AL1
AN7
AH16
AK29
AG34
AA33
U33
AJ5
AH9
AH13
AG20
AG24
AH31
AD24
W31
AE3
AF3
AH2
AJ2
AE2
AE1
AG3
AH3
AJ1
AK2
AN4
Datasheet
375
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15
SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47
SDQ_A48
SDQ_A49
SDQ_A50
AP4
AJ3
AK3
AP2
AP3
AP5
AR5
AN8
AP9
AN5
AP6
AR8
AN9
AK16
AL17
AD17
AF19
AF16
AJ17
AE19
AH18
AH27
AK27
AN30
AK31
AL27
AJ28
AL30
AL31
AJ34
AH35
AG32
AF34
AJ33
AH33
AF33
AE33
AE35
AE34
Y33
376
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
W34
GMCH3
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55
SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B0
AD31
AD35
AA32
Y35
V34
V33
R32
R34
W35
W33
T33
T35
AH7
AJ6
SDQ_B1
SDQ_B1
SDQ_B1
SDQ_B1
SDQ_B1
SDQ_B1
SDQ_B2
SDQ_B2
SDQ_B2
SDQ_B2
SDQ_B2
SDQ_B2
AL5
SDQ_B3
SDQ_B3
SDQ_B3
SDQ_B3
SDQ_B3
SDQ_B3
AN6
AG9
AH4
AM5
AL6
SDQ_B4
SDQ_B4
SDQ_B4
SDQ_B4
SDQ_B4
SDQ_B4
SDQ_B5
SDQ_B5
SDQ_B5
SDQ_B5
SDQ_B5
SDQ_B5
SDQ_B6
SDQ_B6
SDQ_B6
SDQ_B6
SDQ_B6
SDQ_B6
SDQ_B7
SDQ_B7
SDQ_B7
SDQ_B7
SDQ_B7
SDQ_B7
SDQ_B8
SDQ_B8
SDQ_B8
SDQ_B8
SDQ_B8
SDQ_B8
AJ7
SDQ_B9
SDQ_B9
SDQ_B9
SDQ_B9
SDQ_B9
SDQ_B9
AL7
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23
SDQ_B24
SDQ_B25
SDQ_B26
AF11
AE11
AJ8
AL8
AG10
AG11
AE13
AF13
AG14
AD14
AD12
AH12
AF14
AD15
AD18
AK19
AE22
Datasheet
377
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A1
SDQS_A2
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A1
SDQS_A2
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A1
SDQS_A2
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A1
SDQS_A2
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A1
SDQS_A2
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55
SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63
SDQS_A0
SDQS_A1
SDQS_A2
AH21
AL18
AH19
AF22
AD21
AF23
AF25
AL25
AJ26
AD23
AF24
AJ25
AL26
AJ29
AJ31
AG30
AG31
AK33
AK32
AG27
AF28
AE31
AF27
AB27
AB26
AE29
AE27
AC28
AC26
AA29
W29
U26
V29
Y26
AA28
W26
V28
AG1
AL3
AP7
378
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
GMCH3
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
AF17
AM30
AG35
AA34
U34
AK5
AK10
AK13
AD20
AH25
AH28
AB31
W27
SDVO_CTRLC
LK
SDVO_CTRLCLK
SDVO_CTRLDATA
RSV
RSV
RSV
RSV
SDVO_CTRLCLK SDVO_CTRLCLK J13
SDVO_CTRLD SDVO_CTRLDAT SDVO_CTRLDAT
K13
ATA
A
A
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWIN0
SM_SLEWIN1
SM_SLEWIN0
SM_SLEWIN1
AJ12
AF9
SM_SLEWOU
T0
SM_SLEWOU
T0
SM_SLEWOU
T0
SM_SLEWOUT0
SM_SLEWOUT1
SM_SLEWOUT0
SM_SLEWOUT1
SM_SLEWOUT0
SM_SLEWOUT1
AK12
AE10
SM_SLEWOU
T1
SM_SLEWOU
T1
SM_SLEWOU
T1
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_B0
SMA_B1
SMA_B2
SMA_B3
AN22
AP22
AN21
AP21
AM21
AP19
AR20
AN16
AN18
AM15
AN23
AP15
AP13
AB33
AM18
AP18
AN17
AR16
Datasheet
379
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SRAS_A#
SRAS_B#
SRCOMP0
SRCOMP1
SVREF0
SVREF1
SWE_A#
SWE_B#
VCC
AR15
AN15
AP17
AL15
AP14
AN13
AN20
AR12
AM12
AD32
AN29
AP27
AG4
AG8
AE7
AE8
AP31
AR27
AA13
AA14
AA16
AA18
AA20
AA21
AA22
AA23
AA24
AB1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB10
AB11
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB20
AB21
VCC
VCC
VCC
VCC
VCC
VCC
380
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
GMCH3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB22
AB23
AB24
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AC1
AC10
AC11
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AD1
AD10
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
L10
N13
N14
N15
N16
N18
N20
N21
P13
Datasheet
381
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
P14
P15
P17
P19
P21
P22
R13
R14
R15
R16
R18
R20
R22
R23
T13
T14
T15
T16
T17
T19
T20
T21
T23
T24
U13
U14
U16
U18
U20
U22
U24
V13
V14
V15
V17
V19
V21
V23
V24
W13
382
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
W14
GMCH3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W16
W18
W20
W22
W24
Y13
Y14
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
W1
W2
W3
W4
W6
W7
W8
W9
Y1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC2
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
A13
D13
E13
A12
B13
VCCA_DAC
VCCA_DAC
VCCA_DPLLA
VCCA_DPLLB
RSV
RSV
VCCA_DAC
VCCA_DAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_DAC
VCCA_DAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_DAC
VCCA_DAC
VCCA_DPLLA
VCCA_DPLLB
RSV
RSV
VCCA_DPLLA
VCCA_DPLLB
VCCA_DPLLA
VCCA_DPLLB
VCCA_EXPPL
L
VCCA_EXPPL
L
VCCA_EXPPL
L
VCCA_EXPPLL
VCCA_EXPPLL
VCCA_EXPPLL
A14
Datasheet
383
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCA_HPLL
VCCA_SMPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
A17
B17
AK35
AM10
AM11
AM13
AM14
AM16
AM17
AM19
AM20
AM22
AM23
AM25
AM26
AM28
AM32
AN35
AP12
AP16
AP20
AP24
AP28
AR10
AR14
AR18
AR22
AR26
AR31
AR33
A10
VSS
VSS
VSS
VSS
VSS
VSS
A18
VSS
VSS
VSS
VSS
VSS
VSS
A26
VSS
VSS
VSS
VSS
VSS
VSS
A3
VSS
VSS
VSS
VSS
VSS
VSS
A30
VSS
VSS
VSS
VSS
VSS
VSS
A33
VSS
VSS
VSS
VSS
VSS
VSS
A5
VSS
VSS
VSS
VSS
VSS
VSS
AA1
VSS
VSS
VSS
VSS
VSS
VSS
AA10
AA11
VSS
VSS
VSS
VSS
VSS
VSS
384
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
GMCH3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA15
AA17
AA19
AA2
AA25
AA26
AA27
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AB25
AB28
AB30
AB32
AB35
AC25
AC27
AC29
AC31
AC32
AD11
AD13
AD16
AD19
AD22
AD25
AD26
AD27
AD34
AE12
AE14
AE15
AE17
AE18
AE20
AE21
Datasheet
385
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE23
AE24
AE28
AE30
AE32
AE4
AE6
AE9
AF1
AF10
AF12
AF15
AF18
AF21
AF26
AF29
AF30
AF31
AF32
AF35
AF4
AF6
AF8
AG12
AG13
AG15
AG16
AG18
AG19
AG21
AG22
AG25
AG28
AG29
AG5
AH1
AH11
AH14
AH17
AH20
386
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
GMCH3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH23
AH26
AH29
AH32
AH34
AH5
AH6
AH8
AJ10
AJ13
AJ15
AJ16
AJ19
AJ22
AJ27
AJ30
AJ32
AJ35
AJ4
AJ9
AK1
AK11
AK14
AK17
AK20
AK23
AK25
AK26
AK28
AK30
AK4
AK6
AK7
AK8
AL10
AL13
AL16
AL19
AL22
AL32
Datasheet
387
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM29
AM31
AM4
AM6
AM7
AM8
AN1
AP8
AR13
AR17
AR21
AR25
AR3
AR30
AR6
B10
B12
B14
B16
B18
B2
B24
B28
B5
B6
B7
B8
B9
C1
C11
C13
C17
C18
C23
C3
C35
C4
D10
D11
D15
388
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
D16
GMCH3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D18
D23
D25
D26
D28
D3
D30
D31
D32
D4
D6
D7
D8
D9
E1
E10
E17
E18
E2
E23
E26
E29
E4
E6
E8
F10
F16
F18
F2
F23
F25
F29
F30
F32
F35
F4
F5
F6
F8
Datasheet
389
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G10
G11
G13
G15
G17
G19
G2
G20
G23
G26
G27
G28
G4
G7
G8
G9
H10
H13
H2
H21
H24
H25
H27
H30
H32
H34
H4
H5
H6
H9
J10
J15
J16
J17
J18
J2
J20
J23
J30
J4
390
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
J7
GMCH3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
J9
K10
K11
K14
K2
K20
K24
K26
K28
K31
K32
K35
K4
K5
K6
K9
L11
L13
L15
L16
L17
L18
L2
L20
L21
L22
L24
L27
L30
L32
L4
L7
L8
L9
M10
M11
M17
M2
Datasheet
391
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M20
M24
M25
M27
M29
M34
M4
M5
M6
M9
N10
N11
N17
N19
N2
N25
N28
N30
N32
N4
N7
N8
N9
P11
P16
P18
P2
P20
P25
P27
P29
P31
P32
P35
P4
P5
P6
P9
R11
R17
392
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
R19
GMCH3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R2
R21
R25
R26
R27
R4
R7
R8
R9
T10
T11
T18
T2
T22
T25
T28
T30
T32
T34
T4
T5
T6
T7
U11
U15
U17
U19
U2
U21
U23
U25
U27
U29
U31
U32
U4
U7
U8
U9
Datasheet
393
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
GMCH3
Intel® 82910GL
GMCH4
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
VSYNC
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSV
VSYNC
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSV
VSYNC
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
VSYNC
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
VSYNC
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_DAC
VSYNC
VTT
V1
V11
V16
V18
V2
V20
V22
V25
V26
V27
V35
V4
V6
V9
W11
W15
W17
W19
W21
W23
W25
W28
W30
W32
Y11
Y18
Y22
Y25
Y27
Y29
Y31
Y32
Y34
F13
D12
A19
A20
A21
A22
B19
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
394
Datasheet
Ballout and Package Information
R
Intel® 82915GL
GMCH6
Intel® 82915PL
MCH5
Intel® 82915P
MCH1
Intel® 82915G
GMCH2
Intel® 82915GV
Intel® 82910GL
GMCH4
Ball #
B20
GMCH3
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
B21
B22
C19
C20
C21
C22
D19
D20
D21
D22
E19
E20
E21
E22
F20
F21
F22
G21
G22
H22
NOTES:
1. DDR, PCI Express* x16 Graphics Interface, No DAC, No Intel® SDVO
2. DDR, PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
3. DDR, No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
4. DDR (One DIMM per Channel), No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
5. DDR (One DIMM per Channel), PCI Express* x16 Graphics Interface, No DAC, No Intel® SDVO
6. DDR, No PCI Express* x16 Graphics Interface, DAC, Intel® SDVO
14.3
Package Information
The (G)MCH package measures 37.5 mm × 37.5 mm. The 1210 balls are located in a non-grid
pattern. For example, the ball pitch varies from 31.8 mils to 43.0 mils, depending upon the
X-axis or Y-axis direction. Figure 14-7 shows the physical dimensions of the package and
Figure 14-8 shows the (G)MCH keep-out regions.
Datasheet
395
Ballout and Package Information
R
Figure 14-7. (G)MCH Package Dimensions
(G)MCH
396
Datasheet
Ballout and Package Information
R
Figure 14-8. (G)MCH Component Keep-Out Restrictions
§
Datasheet
397
Ballout and Package Information
R
398
Datasheet
Testability
R
15 Testability
In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has been
implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin
connected to it.
15.1
Complimentary Pins
Table 15-1 contains pins which must remain complimentary while performing XOR testing. The
first and third columns contain the pin and its compliment. The second and fourth columns
specify which chain the associated pins are on.
Note: The SDQSx# pins are only used in DDR2 mode. In DDR it is not necessary to drive
SDQS_A[7:0]# or SDQS_B[7:0]#.
Table 15-1. Complimentary Pins to Drive
Complimentary Pin
XOR Chain
Complimentary Pin
XOR Chain
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SDQS_A8
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
SDQS_B8
FSB XOR 1
FSB XOR 0
FSB XOR 0
FSB XOR 0
SM XOR 6
SM XOR 6
SM XOR 6
SM XOR 4
SM XOR 4
SM XOR 2
SM XOR 2
SM XOR 2
SM XOR 2
SM XOR 7
SM XOR 7
SM XOR 7
SM XOR 7
SM XOR 7
SM XOR 3
SM XOR 3
SM XOR 3
SM XOR 7
H_DSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
SDQS_A0#
SDQS_A1#
SDQS_A2#
SDQS_A3#
SDQS_A4
FSB XOR 1
FSB XOR 0
FSB XOR 0
FSB XOR 0
SM XOR 4
SM XOR 4
SM XOR 4
SM XOR 6
SM XOR 2
SM XOR 4
SM XOR 4
SM XOR 4
SM XOR 4
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SM XOR 5
SDQS_A5#
SDQS_A6#
SDQS_A7#
SDQS_A8#
SDQS_B0#
SDQS_B1#
SDQS_B2#
SDQS_B3#
SDQS_B4#
SDQS_B5#
SDQS_B6#
SDQS_B7#
SDQS_B8#
Datasheet
399
Testability
R
15.2
XOR Test Mode Initialization for DDR
XOR test mode (DDR) can be entered by pulling the reserved ballout RSV (located at F15) low
through the de-assertion of external reset (RSTIN#). It was intended that no clocks should be
required to enter this test mode; however, it is recommended that customers used the following
sequence.
On power up, hold PWROK, PCIRST#, and reserved ballout RSV (located at F15) low and start
external clocks, refer to the timing diagram below. After a few clock cycles, pull PWROK high.
After ~3–4 clocks, de-assert PCIRST# (pull it high). Release reserved ballout RSV (located at
F15). No external drive. Allow the clocks to run for an additional 32 clocks. Begin testing the
XOR chains. Refer to timing diagram in below.
15.3
XOR Test Mode Initialization for DDR2
XOR test mode (DDR2) can be entered by pulling reserved ballout RSV(located at F15) and
MTYPE low through the de-assertion of external reset (RSTIN#). It was intended that no clocks
should be required to enter this test mode; however, it is recommended that customers use the
following sequence.
On power up, hold PWROK, PCIRST#, and reserved ballout RSV (located at F15) low and start
external clocks. After a few clock cycles, pull PWROK high. After ~3-4 clocks, de-assert
PCIRST# (pull it high). Release reserved ballout RSV (located at F15) and MTYPE. No external
drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains. Refer to
Figure 15-1.
Figure 15-1. XOR Test Mode Initialization Cycles
32 clocks
PWROK
~3-4 Clocks
RSV_F15
Don’t Care
MTYPE
1 if DDR1; 0 if DDR2
Don’t Care
RSTIN#
Start XOR testing
XOR_Chain_Tim
400
Datasheet
Testability
R
15.4
XOR Chain Definition
The 82915G/82915GV/82915GL/82910GL GMCH, and the 82915P/ 82915PL MCH each have
10 XOR chains. The XOR chain outputs are driven out on the following output pins. During full-
width testing, XOR chain outputs are visible on both pins. For example, xor_out0 is visible on
BSEL2.
Table 15-2. XOR Chain Outputs for both DDR and DDR2
XOR Chain
Output Pins
Coordinate Location
xor_out0
xor_out1
xor_out2
xor_out3
xor_out4
xor_out5
xor_out6
xor_out7
xor_out8
xor_out9
BSEL2
RSV
D17
M16
F15
C15
A16
B15
C14
K15
H16
E15
RSV
MTYPE
EXP_SLR
RSV
RSV
RSV
BSEL0
BSEL1
15.5
DDR XOR Chains
The tables in this section show the DDR XOR chains. The last section in this chapter has a pin
exclusion list. The chain files are golden, if there is a pin missing from the chain files and
exclusion list, it should be added to the exclusion list.
Note: The DDR XOR Chain information is based on the 82915G GMCH. Differences for the
82915GV/82915GL/82910GL GMCH and 82915P/82915PL MCH are indicated in the
“Comments” column.
Datasheet
401
Testability
R
Table 15-3. DDR XOR Chain #0
Comments
Pin Count
Ball #
DDR Signal Name
1
M15
M14
K16
L14
K13
J13
DDC_CLK
ICH_SYNC#
EXTTS#
DDC_DATA
SDVO_CTRLDATA
SDVO_CTRLCLK
RSV
RSV on the 82915P/82915PL MCH
2
3
4
RSV on the 82915P/82915PL MCH
RSV on the 82915P/82915PL MCH
RSV on the 82915P/82915PL MCH
5
6
7
G16
G24
K17
M18
K18
F17
M19
K21
K19
H18
J19
8
HCPURST#
HD44
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
HD42
HD43
HD47
HD38
HD39
HDINV2#
HD46
HDSTBP2#
HDSTBN2#
HD45
F19
G18
K22
M21
J21
HD34
HD36
HD35
H20
H19
J24
HD40
HD41
HD33
J22
HD32
H23
A25
A29
D27
B26
B29
C29
C25
B30
E27
C30
E25
H28
F27
F28
H26
HD37
HD48
HD55
HD60
HDINV3#
HDSTBP3#
HDSTBN3#
HD58
HD51
HD24
HD17
HD25
HD19
HD23
HD22
HDSTBP1#
402
Datasheet
Testability
R
Comments
Pin Count
Ball #
DDR Signal Name
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
F26
J27
J25
K25
K23
L23
J26
G25
L25
B32
G33
H33
H35
J34
G30
H29
J28
J29
K33
F31
K29
L31
K27
M30
F33
E30
J35
P33
HDSTBN1#
HD21
HD27
HD28
HD31
HD30
HDINV1#
HD26
HD29
HD15
HD7
HD1
HD4
HD2
HA6#
HA3#
HA13#
HA5#
HA15#
HREQ4#
HA4#
HA11#
HA14#
HA10#
HREQ0#
HBPRI#
HDEFER#
HEDRDY#
D17
BSEL2
XOR Chain #0 Output
Datasheet
403
Testability
R
Table 15-4. DDR XOR Chain #1
Comments
Pin Count
Ball #
DDR Signal Name
1
A28
A27
B27
B25
E24
C26
C27
C28
A31
C31
B31
D29
E28
G29
B34
B33
C32
C33
C34
D34
D33
E34
E33
E35
F34
G34
G35
J33
HD57
HD61
2
3
HD54
4
HD63
5
HD62
6
HD59
7
HD49
8
HD56
9
HD53
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
HD50
HD52
HD18
HD16
HD20
HD11
HD13
HD14
HD9
HD12
HD8
HD10
HDINV0#
HDSTBP0#
HDSTBN0#
HD6
HD5
HD3
HD0
G32
H31
K30
J31
HA7#
HREQ2#
HA8#
HADSTB0#
HREQ3#
HPCREQ#
HA9#
G31
E31
L29
L28
J32
HA12#
HRS2#
HRS0#
HLOCK#
HDRDY#
HADS#
HHIT#
HBNR#
HDBSY#
HHITM#
K34
L33
M32
M31
L34
M35
L35
N35
404
Datasheet
Testability
R
Comments
Pin Count
Ball #
DDR Signal Name
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
P34
N34
R33
N31
N33
T31
E32
T27
M26
N26
P28
U28
N27
L26
M28
T29
R28
N29
T26
P26
R29
HRS1#
HTRDY#
HBREQ0#
HA21#
HA26#
HA28#
HREQ1#
HA27#
HA20#
HA19#
HA24#
HA29#
HADSTB1#
HA18#
HA16#
HA31#
HA25#
HA23#
HA30#
HA22#
HA17#
M16
RSV
XOR Chain #1 Output
Datasheet
405
Testability
R
Table 15-5. DDR XOR Chain #2
Pin Count
Ball #
DDR Signal Name
Comments
1
R32
R34
SDQ_A58
SDQ_A59
SDQ_A63
SDQ_A60
SDQ_A62
SDQ_A56
SDQ_A57
SDM_A7
SDQ_A61
SDQS_A7
SDQS_A6
SDQ_A51
SDQ_A55
SDQ_A50
SDQ_A53
SDQ_A48
SDQ_A49
SDM_A6
SDQ_A54
SDQ_A52
SMA_A13
SCLK_A5
SCLK_A2
SCLK_A2#
SDQ_A43
SDQ_A41
SDQ_A40
SDM_A5
SDQ_A47
SDQ_A46
SDQ_A42
SDQ_A45
SDQ_A44
SDQS_A5
RSV
2
3
T35
4
W35
5
T33
6
V34
7
V33
8
U33
9
W33
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
U34
AA34
W34
Y35
Y33
AD35
AE35
AE34
AA33
AA32
AD31
AB33
AC35
AB34
AC33
AF34
AH35
AJ34
AG34
AE33
AF33
AG32
AH33
AJ33
AG35
AR29
AP33
AP29
AN32
AP30
AL29
RSV
RSV
RSV
RSV
RSV
F15
RSV
XOR Chain #2 Output
406
Datasheet
Testability
R
Table 15-6. DDR XOR Chain #3
Pin Count
Ball #
DDR Signal Name
Comments
1
W26
U26
SDQ_B62
SDQ_B58
SDQ_B63
SDQ_B59
SDQ_B57
SDM_B7
2
3
V28
4
V29
5
W29
6
W31
7
AA29
AA28
Y26
SDQ_B56
SDQ_B61
SDQ_B60
SDQS_B7
SMA_B13
SDQS_B6
SDQ_B50
SDQ_B48
SDQ_B55
SDQ_B53
SDQ_B52
SDQ_B49
SDQ_B51
SDQ_B54
SDM_B6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
W27
AD32
AB31
AB27
AE31
AC26
AE27
AE29
AF27
AB26
AC28
AD24
AP34
AD29
AE25
AE26
AN34
AN33
AM34
AK34
AL34
AL35
AM33
AF28
AK32
AH31
AK33
AJ31
AG27
AJ29
AG31
AH28
AL33
AJ25
AL25
AJ26
AL26
AF23
AF25
SCS_B0#
SCLK_B5
SCLK_B2#
SCLK_B2
SCS_B1#
SCS_B2#
SCS_A0#
SCS_A2#
SCAS_A#
SCS_A1#
SCS_B3#
SDQ_B47
SDQ_B45
SDM_B5
SDQ_B44
SDQ_B41
SDQ_B46
SDQ_B40
SDQ_B43
SDQS_B5
SCS_A3#
SDQ_B38
SDQ_B34
SDQ_B35
SDQ_B39
SDQ_B32
SDQ_B33
C15
MTYPE
XOR Chain #3 Output
Datasheet
407
Testability
R
Table 15-7. DDR XOR Chain #4
Pin Count
Ball #
DDR Signal Name
Comments
1
U35
AA35
AC34
AG33
AP32
AN31
AM30
AK31
AH27
AK29
AJ28
AL30
AL31
AN30
AL27
AK27
AN29
AN28
AR28
AN27
AP27
AR27
AP25
AN26
AN25
AM24
AL24
AM27
AP26
AP31
AR24
AR23
AP23
AN23
AN22
AF17
AH18
AF19
AJ17
AL17
AF16
AN18
AR7
RSV
RSV
2
3
SCLK_A5#
RSV
4
5
RSV
6
RSV
7
SDQS_A4
SDQ_A35
SDQ_A32
SDM_A4
SDQ_A37
SDQ_A38
SDQ_A39
SDQ_A34
SDQ_A36
SDQ_A33
SRAS_A#
SBS_A0
RSV
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SCAS_B#
SRAS_B#
SWE_B#
SCLK_A3
SCLK_A3#
SCLK_A0#
SCLK_A0
RSV
SBS_B0
SBS_A1
SWE_A#
RSV
RSV
RSV
SMA_A10
SMA_A0
SDQS_A3
SDQ_A31
SDQ_A27
SDQ_A29
SDQ_A25
SDQ_A28
SMA_A8
RSV
AM3
SCLK_A4#
RSV
AL2
AG2
RSV
A16
EXP_SLR
XOR Chain #4 Output
408
Datasheet
Testability
R
Table 15-8. DDR XOR Chain #5
Pin Count
Ball #
DDR Signal Name
Comments
1
Y28
RSV
2
AC30
AD28
AG30
AH30
AG24
AD23
AF24
AG26
AF20
AE22
AL18
AK19
AG20
AD21
AF22
AH21
AD18
AH19
AK22
AG23
AH22
AN17
AP18
AP17
AR16
AN16
AN15
AM15
AP15
AR15
AL15
AP14
AP10
AL14
AL9
RSV
3
SCLK_B5#
SDQ_B42
RSV
4
5
6
SDM_B4
SDQ_B36
SDQ_B37
RSV
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
RSV
SDQ_B26
SDQ_B28
SDQ_B25
SDM_B3
SDQ_B31
SDQ_B30
SDQ_B27
SDQ_B24
SDQ_B29
SCLK_B3#
SCLK_B0#
SCLK_B0
SMA_B2
SMA_B1
SMA_B6
SMA_B3
SMA_A7
SMA_B5
SMA_A9
SMA_A11
SMA_B4
SMA_B7
SMA_B8
SCKE_B2
RSV
SCLK_B4#
RSV
AH10
AL4
RSV
B15
RSV
XOR Chain #5 Output
Datasheet
409
Testability
R
Table 15-9. DDR XOR Chain #6
Pin Count
Ball #
DDR Signal Name
Comments
1
AG17
AH16
AE19
AD17
AK16
AM18
AM21
AN21
AP22
AN20
AP21
AR20
AP19
AR19
AP7
AP9
AN9
AR8
AN8
AN7
AP6
AR5
AP5
AN5
AN2
AN3
AM2
AP4
AP3
AP2
AN4
AK3
AK2
AJ3
RSV
2
SDM_A3
SDQ_A30
SDQ_A26
SDQ_A24
SMA_B0
SMA_A4
SMA_A2
SMA_A1
SMA_B10
SMA_A3
SMA_A6
SMA_A5
SBS_B1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SDQS_A2
SDQ_A19
SDQ_A23
SDQ_A22
SDQ_A18
SDM_A2
SDQ_A21
SDQ_A17
SDQ_A16
SDQ_A20
SCLK_A1
SCLK_A1#
SCLK_A4
SDQ_A11
SDQ_A15
SDQ_A14
SDQ_A10
SDQ_A13
SDQ_A9
SDQ_A12
SDQ_A8
SDM_A1
SDQS_A1
SDQS_A0
SDQ_A6
SDM_A0
SDQ_A2
SDQ_A7
SDQ_A3
SDQ_A1
SDQ_A0
SDQ_A4
SDQ_A5
AJ1
AL1
AL3
AG1
AG3
AF2
AH2
AH3
AJ2
AF3
AE3
AE2
AE1
C14
RSV
XOR Chain #6 Output
410
Datasheet
Testability
R
Table 15-10. DDR XOR Chain #7
Pin Count
Ball #
DDR Signal Name
Comments
1
AH25
AD20
AL23
AP13
AR12
AN13
AL12
AR11
AP11
AN11
AM12
AR9
SDQS_B4
SDQS_B3
SCLK_B3
SMA_A12
SMA_B11
SMA_B9
2
3
4
5
6
7
SCKE_A0
SCKE_A3
SCKE_A2
SCKE_A1
SMA_B12
SCKE_B3
SCKE_B0
SCKE_B1
SDQ_B23
SDQ_B19
SDQ_B18
SDM_B2
SDQ_B21
SDQ_B22
SDQ_B20
SDQ_B17
SDQ_B16
SDQS_B2
SCLK_B1
SCLK_B1#
SCLK_B4
SDQ_B13
SDQ_B9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
AN10
AM9
AD15
AD14
AG14
AH13
AH12
AF14
AD12
AF13
AE13
AK13
AL11
AJ11
AK9
AL8
AL7
AJ7
SDQ_B8
AJ8
SDQ_B12
SDQ_B10
SDQ_B15
SDQ_B14
SDM_B1
SDQ_B11
SDQS_B1
SDQS_B0
SDQ_B4
AF11
AG11
AG10
AH9
AE11
AK10
AK5
AG9
AH7
SDQ_B0
AJ6
SDQ_B1
AL6
SDQ_B7
AN6
SDQ_B3
AL5
SDQ_B2
AJ5
SDM_B0
SDQ_B5
AH4
AM5
SDQ_B6
K15
RSV
XOR Chain #7 Output
Datasheet
411
Testability
R
Table 15-11. DDR XOR Chain #8
Pin Count
Ball #
DDR Signal Name
Comments
1
F11
C9
H11
A8
E9
C7
E7
A6
B4
C5
E5
D2
G5
F3
EXP_RXN0
EXP_TXN0
EXP_RXN1
EXP_TXN1
EXP_RXN2
EXP_TXN2
EXP_RXN3
EXP_TXN3
EXP_RXN4
EXP_TXN4
EXP_RXN5
EXP_TXN5
EXP_RXN6
EXP_TXN6
EXP_RXN7
EXP_TXN7
EXP_RXN8
EXP_TXN8
EXP_RXN9
EXP_TXN9
EXP_RXN10
EXP_TXN10
EXP_RXN11
EXP_TXN11
EXP_RXN12
EXP_TXN12
EXP_RXN13
EXP_TXN13
EXP_RXN14
EXP_TXN14
EXP_RXN15
EXP_TXN15
EXP_RXP0
EXP_TXP0
EXP_RXP1
EXP_TXP1
EXP_RXP2
EXP_TXP2
EXP_RXP3
EXP_TXP3
EXP_RXP4
EXP_TXP4
EXP_RXP5
EXP_TXP5
EXP_RXP6
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
H7
G1
J5
H3
K7
J1
L5
K3
R10
L1
M7
M3
N5
N1
P8
P3
R5
R1
E11
C10
J11
A9
F9
C8
F7
A7
B3
C6
D5
C2
G6
412
Datasheet
Testability
R
Pin Count
Ball #
DDR Signal Name
Comments
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
E3
H8
F1
J6
EXP_TXP6
EXP_RXP7
EXP_TXP7
EXP_RXP8
EXP_TXP8
EXP_RXP9
EXP_TXP9
EXP_RXP10
EXP_TXP10
EXP_RXP11
EXP_TXP11
EXP_RXP12
EXP_TXP12
EXP_RXP13
EXP_TXP13
EXP_RXP14
EXP_TXP14
EXP_RXP15
EXP_TXP15
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
G3
K8
H1
L6
J3
P10
K1
M8
L3
N6
M1
P7
N3
R6
P1
H16
BSEL0
XOR Chain #8 Output
Table 15-12. DDR XOR Chain #9
Pin Count
Ball #
DDR Signal Name
Comments
1
2
U6
U5
T3
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
3
4
R3
T8
5
6
T9
7
U1
T1
8
9
V8
V7
V3
U3
U10
V10
W5
V5
10
11
12
13
14
15
16
E15
BSEL1
XOR Chain #9 Output
Datasheet
413
Testability
R
15.6
DDR2 XOR Chains
The tables in this section list all of the pads used in DDR2 XOR testing. Any pads not listed in the
table can be considered part of the exclude list.
Note: The DDR2 XOR Chain information is based on the 82915G GMCH. Differences for the
82915GV GMCH and 82915P MCH are indicated in the “Comments” column.
Table 15-13. DDR2 XOR Chain #0
Comments
Pin Count
Ball #
DDR2 Signal Name
1
M15
M14
K16
L14
K13
J13
DDC_CLK
ICH_SYNC#
EXTTS#
DDC_DATA
SDVO_CTRLDATA
SDVO_CTRLCLK
RSV
RSV on the 82915P
2
3
4
RSV on the 82915P
RSV on the 82915P
RSV on the 82915P
5
6
7
G16
G24
K17
M18
K18
F17
M19
K21
K19
H18
J19
8
HCPURST#
HD44
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
HD42
HD43
HD47
HD38
HD39
HDINV2#
HD46
HDSTBP2#
HDSTBN2#
HD45
F19
G18
K22
M21
J21
HD34
HD36
HD35
H20
H19
J24
HD40
HD41
HD33
J22
HD32
H23
A25
A29
D27
B26
B29
C29
C25
B30
E27
HD37
HD48
HD55
HD60
HDINV3#
HDSTBP3#
HDSTBN3#
HD58
HD51
HD24
414
Datasheet
Testability
R
Comments
Pin Count
Ball #
DDR2 Signal Name
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
C30
E25
H28
F27
F28
H26
F26
J27
J25
K25
K23
L23
J26
G25
L25
B32
G33
H33
H35
J34
G30
H29
J28
J29
K33
F31
K29
L31
K27
M30
F33
E30
J35
P33
HD17
HD25
HD19
HD23
HD22
HDSTBP1#
HDSTBN1#
HD21
HD27
HD28
HD31
HD30
HDINV1#
HD26
HD29
HD15
HD7
HD1
HD4
HD2
HA6#
HA3#
HA13#
HA5#
HA15#
HREQ4#
HA4#
HA11#
HA14#
HA10#
HREQ0#
HBPRI#
HDEFER#
HEDRDY#
D17
BSEL2
XOR Chain #0 Output
Datasheet
415
Testability
R
Table 15-14. DDR2 XOR Chain #1
Comments
Pin Count
Ball #
DDR2 Signal Name
1
A28
A27
B27
B25
E24
C26
C27
C28
A31
C31
B31
D29
E28
G29
B34
B33
C32
C33
C34
D34
D33
E34
E33
E35
F34
G34
G35
J33
HD57
HD61
2
3
HD54
4
HD63
5
HD62
6
HD59
7
HD49
8
HD56
9
HD53
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
HD50
HD52
HD18
HD16
HD20
HD11
HD13
HD14
HD9
HD12
HD8
HD10
HDINV0#
HDSTBP0#
HDSTBN0#
HD6
HD5
HD3
HD0
G32
H31
K30
J31
HA7#
HREQ2#
HA8#
HADSTB0#
HREQ3#
HPCREQ#
HA9#
G31
E31
L29
L28
J32
HA12#
HRS2#
HRS0#
HLOCK#
HDRDY#
HADS#
HHIT#
HBNR#
HDBSY#
HHITM#
K34
L33
M32
M31
L34
M35
L35
N35
416
Datasheet
Testability
R
Comments
Pin Count
Ball #
DDR2 Signal Name
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
P34
N34
R33
N31
N33
T31
E32
T27
M26
N26
P28
U28
N27
L26
M28
T29
R28
N29
T26
P26
R29
HRS1#
HTRDY#
HBREQ0#
HA21#
HA26#
HA28#
HREQ1#
HA27#
HA20#
HA19#
HA24#
HA29#
HADSTB1#
HA18#
HA16#
HA31#
HA25#
HA23#
HA30#
HA22#
HA17#
M16
RSV
XOR Chain #1 Output
Datasheet
417
Testability
R
Table 15-15. DDR2 XOR Chain #2
Pin Count
Ball #
DDR2 Signal Name
Comments
1
R32
R34
SDQ_A58
SDQ_A59
SDQ_A63
SDQ_A60
SDQ_A62
SDQ_A56
SDQ_A57
SDM_A7
2
3
T35
4
W35
5
T33
6
V34
7
V33
8
U33
9
W33
SDQ_A61
SDQS_A7
SDQS_A6
SDQ_A51
SDQ_A55
SDQ_A50
SDQ_A49
SDQ_A52
SDQ_A53
SDM_A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
U34
AA34
W34
Y35
Y33
AD35
AE35
AE34
AA33
AA32
AD31
AB33
AC35
AB34
AC33
AF34
AH35
AJ34
AG34
AE33
AF33
AG32
AH33
AJ33
AG35
AR29
AP33
AP29
AN32
AP30
AL29
SDQ_A54
SDQ_A48
RSV
SCLK_A2#
SCLK_A5#
SCLK_A5
SDQ_A47
SDQ_A41
SDQ_A45
SDM_A5
SDQ_A43
SDQ_A42
SDQ_A46
SDQ_A40
SDQ_A44
SDQS_A5
SCS_A0#
SODT_A3
SODT_A2
SODT_A1
SODT_A0
SDQS_A4#
F15
RSV
XOR Chain #2 Output
418
Datasheet
Testability
R
Table 15-16. DDR2 XOR Chain #3
Pin Count
Ball #
DDR2 Signal Name
Comments
1
W26
U26
SDQ_B62
SDQ_B63
SDQ_B58
SDQ_B59
SDQ_B57
SDM_B7
2
3
V28
4
V29
5
W29
6
W31
7
AA29
AA28
Y26
SDQ_B61
SDQ_B56
SDQ_B60
SDQS_B7
RSV
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
W27
AD32
AB31
AB27
AE31
AC26
AE27
AE29
AF27
AB26
AC28
AD24
AP34
AD29
AE25
AE26
AN34
AN33
AM34
AK34
AL34
AL35
AM33
AF28
AK32
AH31
AK33
AJ31
AG27
AJ29
AG31
AH28
AL33
AJ25
AL25
AJ26
AL26
AF23
AF25
SDQS_B6
SDQ_B55
SDQ_B52
SDQ_B50
SDQ_B49
SDQ_B53
SDQ_B48
SDQ_B51
SDQ_B54
SDM_B6
SCS_B2#
SCLK_B5#
SCLK_B2#
SCLK_B2
SCS_B3#
SCS_B0#
SCS_B1#
SODT_B3
SODT_B1
SODT_B2
SODT_B0
SDQ_B43
SDQ_B40
SDM_B5
SDQ_B45
SDQ_B41
SDQ_B47
SDQ_B44
SDQ_B42
SDQS_B5
SMA_B13
SDQ_B39
SDQ_B38
SDQ_B35
SDQ_B34
SDQ_B36
SDQ_B33
C15
MTYPE
XOR Chain #3 Output
Datasheet
419
Testability
R
Table 15-17. DDR2 XOR Chain #4
Pin Count
Ball #
DDR2 Signal Name
Comments
1
U35
AA35
AC34
AG33
AP32
AN31
AM30
AK31
AH27
AK29
AJ28
AL30
AL31
AN30
AL27
AK27
AN29
AN28
AR28
AN27
AP27
AR27
AP25
AN26
AN25
AM24
AL24
AM27
AP26
AP31
AR24
AR23
AP23
AN23
AN22
AF17
AH18
AF19
AJ17
AL17
AF16
AN18
AR7
SDQS_A7#
SDQS_A6#
SCLK_A2
SDQS_A5#
SCS_A1#
SCS_A3#
SDQS_A4
SDQ_A35
SDQ_A36
SDM_A4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SDQ_A33
SDQ_A39
SDQ_A34
SDQ_A38
SDQ_A37
SDQ_A32
SCAS_A#
SWE_A#
SCS_A2#
SBS_A1
SRAS_A#
SBS_A0
SCLK_A0#
SCLK_A0
SCLK_A3
SCLK_A3#
SMA_A2
SMA_A10
SMA_A0
SMA_A13
SMA_A1
SMA_A4
SMA_A3
SMA_A6
SMA_A8
SDQS_A3
SDQ_A27
SDQ_A26
SDQ_A25
SDQ_A24
SDQ_A29
SCKE_A2
SDQS_A2#
SCLK_A1#
SDQS_A1#
SDQS_A0#
AM3
AL2
AG2
A16
EXP_SLR
XOR Chain #4 Output
420
Datasheet
Testability
R
Table 15-18. DDR2 XOR Chain #5
Pin Count
Ball #
DDR2 Signal Name
Comments
1
Y28
SDQS_B7#
SDQS_B6#
SCLK_B5
SDQ_B46
SDQS_B5#
SDM_B4
2
AC30
AD28
AG30
AH30
AG24
AD23
AF24
AG26
AF20
AE22
AL18
AK19
AG20
AD21
AF22
AH21
AD18
AH19
AK22
AG23
AH22
AN17
AP18
AP17
AR16
AN16
AN15
AM15
AP15
AR15
AL15
AP14
AP10
AL14
AL9
3
4
5
6
7
SDQ_B37
SDQ_B32
SDQS_B4#
SDQS_B3#
SDQ_B30
SDQ_B29
SDQ_B24
SDM_B3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SDQ_B27
SDQ_B31
SDQ_B26
SDQ_B28
SDQ_B25
SCLK_B3#
SCLK_B0#
SCLK_B0
SRAS_B#
SCAS_B#
SWE_B#
SBS_B0
SBS_B1
SMA_B2
SMA_B0
SMA_B10
SMA_B1
SMA_B3
SMA_B4
SCKE_B0
SDQS_B2#
SCLK_B1#
SDQS_B1#
SDQS_B0#
AH10
AL4
B15
RSV
XOR Chain #5 Output
Datasheet
421
Testability
R
Table 15-19. DDR2 XOR Chain #6
Pin Count
Ball #
DDR2 Signal Name
Comments
1
AG17
AH16
AE19
AD17
AK16
AM18
AM21
AN21
AP22
AN20
AP21
AR20
AP19
AR19
AP7
AP9
AN9
AR8
AN8
AN7
AP6
AR5
AP5
AN5
AN2
AN3
AM2
AP4
AP3
AP2
AN4
AK3
AK2
AJ3
SDQS_A3#
SDM_A3
SDQ_A31
SDQ_A30
SDQ_A28
SCKE_A1
SMA_A11
SMA_A9
SMA_A5
SBS_A2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SMA_A7
SMA_A12
SCKE_A0
SCKE_A3
SDQS_A2
SDQ_A18
SDQ_A19
SDQ_A23
SDQ_A22
SDM_A2
SDQ_A17
SDQ_A16
SDQ_A21
SDQ_A20
SCLK_A4#
SCLK_A4
SCLK_A1
SDQ_A11
SDQ_A15
SDQ_A14
SDQ_A10
SDQ_A9
SDQ_A8
SDQ_A13
SDQ_A12
SDM_A1
SDQS_A1
SDQS_A0
SDQ_A6
SDM_A0
SDQ_A7
SDQ_A2
SDQ_A3
SDQ_A1
SDQ_A0
SDQ_A4
SDQ_A5
AJ1
AL1
AL3
AG1
AG3
AF2
AH2
AH3
AJ2
AF3
AE3
AE2
AE1
C14
RSV
XOR Chain #6 Output
422
Datasheet
Testability
R
Table 15-20. DDR2 XOR Chain #7
Pin Count
Ball #
DDR2 Signal Name
Comments
1
AH25
AD20
AL23
AP13
AR12
AN13
AL12
AR11
AP11
AN11
AM12
AR9
SDQS_B4
SDQS_B3
SCLK_B3
SMA_B6
SMA_B9
SMA_B8
SMA_B7
SMA_B12
SMA_B11
SBS_B2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SMA_B5
SCKE_B2
SCKE_B1
SCKE_B3
SDQ_B19
SDQ_B18
SDQ_B22
SDM_B2
SDQ_B17
SDQ_B23
SDQ_B20
SDQ_B16
SDQ_B21
SDQS_B2
SCLK_B4#
SCLK_B4
SCLK_B1
SDQ_B9
SDQ_B13
SDQ_B12
SDQ_B8
SDQ_B10
SDQ_B15
SDQ_B14
SDM_B1
SDQ_B11
SDQS_B1
SDQS_B0
SDQ_B4
SDQ_B5
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B6
SDM_B0
SDQ_B0
SDQ_B7
AN10
AM9
AD15
AD14
AG14
AH13
AH12
AF14
AD12
AF13
AE13
AK13
AL11
AJ11
AK9
AL8
AL7
AJ7
AJ8
AF11
AG11
AG10
AH9
AE11
AK10
AK5
AG9
AH7
AJ6
AL6
AN6
AL5
AJ5
AH4
AM5
K15
RSV
XOR Chain #7 Output
Datasheet
423
Testability
R
Table 15-21. DDR2 XOR Chain #8
Pin Count
Ball #
DDR2 Signal Name
Comments
1
F11
C9
H11
A8
E9
C7
E7
A6
B4
C5
E5
D2
G5
F3
EXP_RXN0
EXP_TXN0
EXP_RXN1
EXP_TXN1
EXP_RXN2
EXP_TXN2
EXP_RXN3
EXP_TXN3
EXP_RXN4
EXP_TXN4
EXP_RXN5
EXP_TXN5
EXP_RXN6
EXP_TXN6
EXP_RXN7
EXP_TXN7
EXP_RXN8
EXP_TXN8
EXP_RXN9
EXP_TXN9
EXP_RXN10
EXP_TXN10
EXP_RXN11
EXP_TXN11
EXP_RXN12
EXP_TXN12
EXP_RXN13
EXP_TXN13
EXP_RXN14
EXP_TXN14
EXP_RXN15
EXP_TXN15
EXP_RXP0
EXP_TXP0
EXP_RXP1
EXP_TXP1
EXP_RXP2
EXP_TXP2
EXP_RXP3
EXP_TXP3
EXP_RXP4
EXP_TXP4
EXP_RXP5
EXP_TXP5
EXP_RXP6
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
H7
G1
J5
H3
K7
J1
L5
K3
R10
L1
M7
M3
N5
N1
P8
P3
R5
R1
E11
C10
J11
A9
F9
C8
F7
A7
B3
C6
D5
C2
G6
424
Datasheet
Testability
R
Pin Count
Ball #
DDR2 Signal Name
Comments
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
E3
H8
F1
J6
EXP_TXP6
EXP_RXP7
EXP_TXP7
EXP_RXP8
EXP_TXP8
EXP_RXP9
EXP_TXP9
EXP_RXP10
EXP_TXP10
EXP_RXP11
EXP_TXP11
EXP_RXP12
EXP_TXP12
EXP_RXP13
EXP_TXP13
EXP_RXP14
EXP_TXP14
EXP_RXP15
EXP_TXP15
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
For SDVO interface signal name, see ballout table.
G3
K8
H1
L6
J3
P10
K1
M8
L3
N6
M1
P7
N3
R6
P1
H16
BSEL0
XOR Chain #8 Output
Table 15-22. DDR2 XOR Chain #9
Pin Count
Ball #
DDR2 Signal Name
Comments
1
2
U6
U5
T3
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
3
4
R3
T8
5
6
T9
7
U1
T1
8
9
V8
V7
V3
U3
U10
V10
W5
V5
10
11
12
13
14
15
16
E15
BSEL1
XOR Chain #9 Output
Datasheet
425
Testability
R
15.7
PADs Excluded from XOR Mode(s)
A large number of pads do not support XOR testing. The majority of the pads that fall into this
category are analog related pins (see Table 15-23).
Table 15-23. XOR Pad Exclusion List
PCI Express*
GCLKN
Host Interface
HCLKN
System Memory
Misc
SRCOMP1
SRCOMP0
DREFCLKN
DREFCLKP
BLUE
GCLKP
HCLKP
HRCOMP
HSCOMP
HVREF
EXP_COMPO
EXP_COMPI
SMVREF1
SMVREF0
BLUE#
SOCOMP1
GREEN
GREEN#
RED
HSWING
SOCOMP0
SM_SLEWOUT1
SM_SLEWOUT0
SM_SLEWIN1
SM_SLEWIN0
RED#
RSTIN#
HSYNC
VSYNC
REFSET
§
426
Datasheet
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