A80960JC-50 [INTEL]
RISC Microprocessor, 32-Bit, 50MHz, CMOS, CPGA132, PGA-132;
| 型号： | A80960JC-50 |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 32-Bit, 50MHz, CMOS, CPGA132, PGA-132 |
| 文件： | 总86页 (文件大小：1293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
80960JA/JF/JD/JS/JC/JT 3.3 V
Embedded 32-Bit Microprocessor
Datasheet
Product Features
■ Code Compatible with all 80960Jx
■ On-Chip Data RAM
Processors
—1 Kbyte Critical Variable Storage
—Single-Cycle Access
■ High-Performance Embedded Architecture
—One Instruction/Clock Execution
■ 3.3 V Supply Voltage
—Core Clock Rate is:
—5 V Tolerant Inputs
1x the Bus Clock for 80960JA/JF/JS
2x the Bus Clock for 80960JD/JC
3x the Bus Clock for 80960JT
—TTL Compatible Outputs
■ High Bandwidth Burst Bus
—32-Bit Multiplexed Address/Data
—Programmable Memory Configuration
—Selectable 8-, 16-, 32-Bit Bus Widths
—Supports Unaligned Accesses
—Big or Little Endian Byte Ordering
■ High-Speed Interrupt Controller
—31 Programmable Priorities
—Eight Maskable Pins plus NMI#
—Up to 240 Vectors in Expanded Mode
■ Two On-Chip Timers
—Load/Store Programming Model
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers (8 sets)
—Nine Addressing Modes
—User/Supervisor Protection Model
■ Two-Way Set Associative Instruction
Cache
—80960JA - 2 Kbyte
—80960JF/JD - 4 Kbyte
—80960JS/JC/JT - 16 Kbyte
—Programmable Cache-Locking
Mechanism
—Independent 32-Bit Counting
—Clock Prescaling by 1, 2, 4 or 8
—lnternal Interrupt Sources
■ Direct Mapped Data Cache
—80960JA - 1 Kbyte
■ Halt Mode for Low Power
■ IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
■ Packages
—80960JF/JD - 2 Kbyte
—80960JS/JC/JT - 4 Kbyte
—Write Through Operation
■ On-Chip Stack Frame Cache
—Seven Register Sets Can Be Saved
—Automatic Allocation on Call/Return
—132-Lead Pin Grid Array (PGA)
—132-Lead Plastic Quad Flat Pack
(PQFP)
—196-Ball Mini Plastic Ball Grid Array
(MPBGA)
—0-7 Frames Reserved for High-Priority
Interrupts
Order Number: 273159-003
June, 1999
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 80960JA/JF/JD/JS/JC/JT 3.3 V microprocessors may contain design defects or errors known as errata which may cause the products to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1999
*Third-party brands and names are the property of their respective owners.
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Contents
1.0
2.0
Introduction..................................................................................................................7
80960Jx Overview......................................................................................................8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
80960 Processor Core ........................................................................................10
Burst Bus.............................................................................................................10
Timer Unit............................................................................................................11
Priority Interrupt Controller ..................................................................................11
Instruction Set Summary.....................................................................................11
Faults and Debugging .........................................................................................12
Low Power Operation..........................................................................................12
Test Features ......................................................................................................12
Memory-Mapped Control Registers ....................................................................13
Data Types and Memory Addressing Modes ......................................................13
3.0
4.0
Packaging Information...........................................................................................15
3.1
Pin Descriptions ..................................................................................................17
3.1.1 Functional Pin Definitions.......................................................................17
3.1.2 80960Jx 132-Lead PGA Pinout..............................................................23
3.1.3 80960Jx 132-Lead PQFP Pinout............................................................27
3.1.4 80960Jx 196-Ball MPBGA Pinout ..........................................................30
Package Thermal Specifications.........................................................................35
Thermal Management Accessories.....................................................................40
3.3.1 Heatsinks................................................................................................40
3.2
3.3
Electrical Specifications........................................................................................41
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute Maximum Ratings.................................................................................41
Operating Conditions...........................................................................................41
Connection Recommendations ...........................................................................42
VCC5 Pin Requirements (VDIFF) .......................................................................42
VCCPLL Pin Requirements.................................................................................43
DC Specifications................................................................................................44
AC Specifications ................................................................................................48
4.7.1 AC Test Conditions and Derating Curves ..............................................51
4.7.1.1 Ouput Delay or Hold vs. Load Capacitance ..............................51
4.7.1.2 T vs. AD Bus Load Capacitance............................................53
LX
4.7.1.3 ICC Active vs. Frequency..........................................................55
4.7.2 AC Timing Waveforms ...........................................................................59
5.0
6.0
Bus Functional Waveforms..................................................................................65
5.1
5.2
Basic Bus States .................................................................................................75
Boundary-Scan Register .....................................................................................76
Device Identification ...............................................................................................82
6.1
6.2
6.3
80960JS/JC/JT Device Identification Register ....................................................83
80960JD Device Identification Register ..............................................................84
80960JA/JF Device Identification Register..........................................................85
7.0
Revision History.......................................................................................................86
Datasheet
3
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figures
1
80960Jx Microprocessor Package Options........................................................... 7
2
3
4
5
6
7
8
9
80960Jx Block Diagram ........................................................................................ 9
132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23
132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................24
132-Lead PQFP - Top View ................................................................................27
196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down .................30
196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up .................31
VCC5 Current-Limiting Resistor..........................................................................42
VCCPLL Lowpass Filter......................................................................................43
AC Test Load ......................................................................................................51
Output Delay or Hold vs. Load Capacitance –
10
11
80960JS/JC/JT (3.3 V Signals) ..........................................................................51
12
Output Delay or Hold vs. Load Capacitance –
80960JS/JC/JT (5 V Signals) .............................................................................52
Output Delay or Hold vs. Load Capacitance – 80960JA/JF/JD ..........................52
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
T
T
T
vs. AD Bus Load Capacitance – 80960JS/JC/JT (3.3 V Signals) ................53
vs. AD Bus Load Capacitance – 80960JS/JC/JT (5 V Signals) ...................53
vs. AD Bus Load Capacitance – 80960JA/JF/JD .........................................54
Active (Power Supply) vs. Frequency – 80960JA/JF....................................55
LX
LX
LX
I
CC
80960JA/JF I Active (Thermal) vs. Frequency................................................55
CC
80960JD I Active (Power Supply) vs. Frequency............................................56
CC
80960JD I Active (Thermal) vs. Frequency.....................................................56
CC
80960JC I Active (Power Supply) vs. Frequency............................................57
CC
80960JC I Active (Thermal) vs. Frequency.....................................................57
CC
80960JS I Active (Power Supply) vs. Frequency............................................58
CC
80960JS I Active (Thermal) vs. Frequency.....................................................58
CC
CLKIN Waveform ................................................................................................59
T
T
T
T
T
T
T
Output Delay Waveform.............................................................................59
Output Float Waveform................................................................................60
OV1
OF
IS1
IS2
IS3
IS4
and T
and T
and T
and T
Input Setup and Hold Waveform...................................................60
Input Setup and Hold Waveform...................................................60
Input Setup and Hold Waveform...................................................61
Input Setup and Hold Waveform...................................................61
IH1
IH2
IH3
IH4
, T
and T
Relative Timings Waveform.................................................62
LX LXL
LXA
DT/R# and DEN# Timings Waveform .................................................................62
TCK Waveform....................................................................................................63
T
T
T
T
and T
Input Setup and Hold Waveforms .........................................63
BSIS1
BSIH1
and T
and T
Output Delay and Output Float Waveform..........................63
Output Delay and Output Float Waveform..........................64
BSOV1
BSOF1
BSOV2
BSOF2
and T
Input Setup and Hold Waveform ...........................................64
BSIS2
BSIH2
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........65
Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................66
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................67
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................68
Burst Read and Write Transactions With 1, 0 Wait States and
Extra Tr State on Read, 16-Bit Bus.....................................................................69
44
45
Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian .................................................70
HOLD/HOLDA Waveform For Bus Arbitration ....................................................71
4
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
46
47
48
49
50
52
53
54
Cold Reset Waveform .........................................................................................72
Warm Reset Waveform.......................................................................................73
Entering the ONCE State ....................................................................................74
Bus States with Arbitration ..................................................................................76
Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................80
80960JS/JC/JT Device Identification Register Fields..........................................83
80960JD Device Identification Register Fields....................................................84
80960JA/JF Device Identification Register Fields...............................................85
Tables
1
2
3
4
5
6
7
8
80960Jx 3.3-V Microprocessor Family..................................................................7
80960Jx Instruction Set.......................................................................................14
80960Jx Processors Available in 132-Pin PGA Package ...................................15
80960Jx Processors Available in 132-Pin PQFP Package .................................15
80960Jx Processors Available in Extended Temperature PQFP Package.........16
80960Jx Processors Available in 196-Ball MPBGA Package .............................16
Pin Description Nomenclature.............................................................................17
Pin Description — External Bus Signals .............................................................18
Pin Description — Processor Control Signals, Test Signals and Power.............21
Pin Description — Interrupt Unit Signals.............................................................22
132-Lead PGA Pinout — In Signal Order............................................................25
132-Lead PGA Pinout — In Pin Order ................................................................26
132-Lead PQFP Pinout — In Signal Order .........................................................28
132-Lead PQFP Pinout — In Pin Order ..............................................................29
196-Ball MPBGA Pinout — In Signal Order ........................................................32
196-Ball MPBGA Pinout — In Pin Order.............................................................33
132-Lead PGA Package Thermal Characteristics...............................................36
80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics..................36
80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics..................37
132-Lead PQFP Package Thermal Characteristics ............................................37
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Maximum T at Various Airflows in °C (80960JT)...............................................38
A
Maximum T at Various Airflows in °C (80960JC) ..............................................38
A
Maximum T at Various Airflows in °C (80960JD) ..............................................39
A
Maximum T at Various Airflows in °C (80960JS)...............................................39
A
Maximum T at Various Airflows in °C (80960JA/JF)..........................................40
A
Absolute Maximum Ratings.................................................................................41
80960Jx Operating Conditions............................................................................41
VDIFF Parameters ..............................................................................................43
80960Jx DC Characteristics................................................................................44
80960Jx I Characteristics................................................................................44
CC
80960Jx AC Characteristics................................................................................48
Note Definitions for Table 31, 80960Jx AC Characteristics ................................50
Boundary-Scan Register Bit Order......................................................................77
Natural Boundaries for Load and Store Accesses ..............................................78
Summary of Byte Load and Store Accesses.......................................................78
Summary of Short Word Load and Store Accesses............................................78
Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)...........................79
80960Jx Device Type and Stepping Reference..................................................82
Datasheet
5
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
39
40
41
42
43
44
45
80960JS/JC/JT Device ID Register Field Definitions ..........................................83
80960JS/JC/JT Device ID Model Types .............................................................83
80960JD Device ID Field Definitions...................................................................84
80960JD Device ID Model Types........................................................................84
80960JA/JF Device ID Field Definitions..............................................................85
80960JA/JF Device ID Model Types...................................................................85
Data Sheet Revision History ...............................................................................86
6
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
1.0
Introduction
This document contains information for the 80960Jx microprocessors, including electrical
characteristics and package pinout information. Detailed functional descriptions — other than
parametric performance — are published in the i960® Jx Microprocessor Developer’s Manual
(272483) and can be viewed online at http://developer.intel.com/design/i960/Techinfo/80960JX/.
Figure 1. 80960Jx Microprocessor Package Options
A80960JX
®
GD80960JX
XXXXXXXXSS
XXXXXXXSS
i960
M
i
© 19xx
M
©
19xx
i
NG80960JX
XXXXXXXX SS
M
©
19xx
i
196-Ball MPBGA
132-Pin PQFP
132-Pin PGA
Throughout this datasheet, references to “80960Jx” indicate features that apply to the 3.3-V Jx
processors only:
Table 1. 80960Jx 3.3-V Microprocessor Family
Instruction
Cache
Data
Cache
Processor
Voltage
Core Clock
80960JA
80960JF
80960JD
80960JS
80960JC
80960JT
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
3.3 V (5 V Tolerant)
2 Kbyte
4 Kbyte
4 Kbyte
16 Kbyte
16 Kbyte
16 Kbyte
1 Kbyte
2 Kbyte
2 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
1x
1x
2x
1x
2x
3x
Datasheet
7
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
2.0
80960Jx Overview
The 80960Jx processor offers high performance to cost-sensitive 32-bit embedded applications.
The 80960Jx is object code compatible with the 80960 core architecture and is capable of sustained
execution at the rate of one instruction per clock. This processor’s features include generous
instruction cache, data cache, and data RAM. It also boasts a fast interrupt mechanism and dual-
programmable timer units.
The 80960Jx processor’s clock multiplication operates the processor core at two or three times the
bus clock rate to improve execution performance without increasing the complexity of board
designs.
Memory subsystems for cost-sensitive embedded applications often impose substantial wait state
penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU
execution from the external bus.
The 80960Jx rapidly allocates and deallocates local register sets during context switches. The
processor must flush a register set to the stack only when it saves more than seven sets to its local
register cache.
A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full
complement of control signals simplifies the connection of the 80960Jx to external components.
The user programs physical and logical memory attributes through memory-mapped control
registers (MMRs) — an extension not found on the i960® Kx, Sx or Cx processors. Physical and
logical configuration registers enable the processor to operate with all combinations of bus width
and data object alignment. The processor supports a homogeneous byte ordering model.
This processor integrates two important peripherals: a timer unit and an interrupt controller. These
and other hardware resources are programmed through memory-mapped control registers, an
extension to the familiar i960 processor architecture.
The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and
general-purpose system timing. These operate in either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.
The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The
ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt
latency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% compared
to the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% compared
to the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reduce
latency. Acting independently from the core, the ICU compares the priorities of posted interrupts
with the current process priority, off-loading this task from the core. The ICU also supports the
integrated timer interrupts.
8
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
The 80960Jx features a Halt mode designed to support applications where low power consumption
is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up
to 90 percent.
The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary
Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.
The Solutions960® program features a wide variety of development tools which support the i960
processor family. Many of these tools are developed by partner companies; some are developed by
Intel, such as profile-driven optimizing compilers. For more information on these products, contact
your local Intel representative.
Figure 2. 80960Jx Block Diagram
Control
21
Physical Region
Configuration
32-bit buses
address / data
CLKIN
PLL, Clocks,
Power Mgmt
Instruction Cache
80960JA - 2K
Bus
Control Unit
Address/
Data Bus
80960JF/JD - 4K
Bus Request
Queues
TAP
5
80960JS/JC/JT - 16K
Two-Way Set Associative
Boundary Scan
Controller
32
Two 32-Bit
Timers
Instruction Sequencer
Interrupt
Port
Constants
Control
Programmable
Interrupt Controller
9
8-Set
Local Register Cache
Execution
and
Memory
Interface
Unit
Memory-Mapped
Register Interface
Multiply
Divide
Unit
Address
Generation
128
Unit
32-bit Address
32-bit Data
1K Data RAM
Global / Local
Register File
effective
address
SRC1 SRC2 DEST
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JS/JC/JT - 4K
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Datasheet
9
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core’s performance include:
• Core operates at the bus speed with the 80960JA/JF/JS
• Core operates at two or three times the bus speed with the 80960JD/JC and 80960JT,
respectively
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline break latency
• Register and resource scoreboarding allow overlapped instruction execution
• 128-bit register bus speeds local register caching
• Two-way set associative, integrated instruction cache
• Direct-mapped, integrated data cache
• 1-Kbyte integrated data RAM delivers zero wait state program data
2.2
Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory
and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit
words per six clock cycles. The external address/data bus is multiplexed.
Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory
organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and
data caching are programmed through a group of logical memory templates and a defaults register.
The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16-, and 8-bit bus widths to simplify I/O interfaces
• External ready control for address-to-data, data-to-data and data-to-next-address wait state types
• Support for big or little endian byte ordering to facilitate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus from the core
Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
initialization boot record (IBR).
10
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
2.3
2.4
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed by use of the TU registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960Jx’s interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected. Clock prescaling is supported.
Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level-
triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channels
and a single Non-Maskable Interrupt (NMI#) pin. Interrupts are serviced according to their priority
levels relative to the current process priority.
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
• Interrupt vectors and interrupt handler routines can be reserved on-chip.
• Register frames for high-priority interrupt handlers can be cached on-chip.
• The interrupt stack can be placed in cacheable memory space.
• Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and
80960JT, respectively.
2.5
Instruction Set Summary
The 80960Jx adds several new instructions to the i960 processor core architecture. The new
instructions are:
• Conditional Move
• Conditional Add
• Conditional Subtract
• Byte Swap
• Halt
• Cache Control
• Interrupt Control
Table 2 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx Microprocessor
Developer’s Manual (272483) for a detailed description of each instruction.
Datasheet
11
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
2.6
Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to
detect as many as seven different trace event types. Alternatively, mark and fmark instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s
sub-micron topology provides the circuit density for optimal cache size and high operating speeds
while dissipating modest power. The processor also uses dynamic power management to turn off
clocks to unused circuits.
Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,
the processor core stops completely while the integrated peripherals continue to function, reducing
overall power requirements up to 90 percent. Processor execution resumes from internally or
externally generated interrupts.
2.8
Test Features
The 80960Jx incorporates numerous features that enhance the user’s ability to test both the
processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).
The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE
mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to
electrically “remove” itself from a circuit board. This allows for system-level testing in which a
remote tester — such as an in-circuit emulator — can exercise the processor system.
The provided test logic does not interfere with component or circuit board behavior and ensures
that components function correctly, connections between various components are correct, and
various components interact correctly on the printed circuit board.
The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing.
It can examine connections that might otherwise be inaccessible to a test system.
12
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
2.9
Memory-Mapped Control Registers
The 80960Jx, although compliant with the i960 processor core, has the added advantage of
memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These
registers give software the interface to easily read and modify internal control registers.
Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The processor ensures that these accesses do not
generate external bus cycles.
2.10
Data Types and Memory Addressing Modes
As with all i960 processors, the 80960Jx instruction set supports several data types and formats:
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
The 80960Jx provides a full set of addressing modes for C and assembly programming:
• Two Absolute modes
• Five Register Indirect modes
• Index with displacement
• IP with displacement
Datasheet
13
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 2. 80960Jx Instruction Set
Data Movement
Arithmetic
Logical
Bit, Bit Field and Byte
Add
Subtract
Multiply
And
Set Bit
Divide
Not And
And Not
Or
Clear Bit
Remainder
Modulo
Not Bit
Load
Alter Bit
Store
Shift
Exclusive Or
Not Or
Scan For Bit
Span Over Bit
Extract
Move
†Conditional Select
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
†Conditional Add
†Conditional Subtract
Rotate
Or Not
Load Address
Nor
Modify
Exclusive Nor
Not
Scan Byte for Equal
†Byte Swap
Nand
Comparison
Branch
Call/Return
Fault
Compare
Call
Conditional Compare
Compare and Increment
Compare and Decrement
Test Condition Code
Check Bit
Unconditional Branch
Conditional Branch
Compare and Branch
Call Extended
Call System
Return
Conditional Fault
Synchronize Faults
Branch and Link
Debug
Processor Management
Atomic
Flush Local Registers
Modify Arithmetic
Controls
Modify Trace Controls
Mark
Modify Process Controls
†Halt
Atomic Add
Atomic Modify
Force Mark
System Control
†Cache Control
†Interrupt Control
† denotes new 80960 instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB processors.
14
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
3.0
Packaging Information
The 80960Jx is offered in various speed grades and three package types.
The 132-pin Pin Grid Array (PGA) device is specified for operation at V = 3.3 V ± 0.15 V over
CC
a case temperature range of 0° to 100°C. The following processor versions are available in the
PGA package:
Table 3. 80960Jx Processors Available in 132-Pin PGA Package
Processor
A80960JT-100
Core Speed
Bus Speed
33 MHz
100 MHz
66 MHz
50 MHz
40 MHz
33 MHz
33 MHz
25 MHz
16 MHz
66 MHz
50 MHz
40 MHz
33 MHz
33 MHz
25 MHz
16 MHz
A80960JC-66
A80960JC-50
A80960JC-40
A80960JC-33
A80960JS-33
A80960JS-25
A80960JS-16
A80960JD-66
A80960JD-50
A80960JD-40
A80960JD-33
A80960JA/JF-33
A80960JA/JF-25
A80960JA/JF-16
33 MHz
25 MHz
20 MHz
16 MHz
33 MHz
25 MHz
16 MHz
33 MHz
25 MHz
20 MHz
16 MHz
33 MHz
25 MHz
16 MHz
The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at
= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C. The following processor
V
CC
versions are available in the PQFP package:
Table 4. 80960Jx Processors Available in 132-Pin PQFP Package (Sheet 1 of 2)
Processor
NG80960JT-100
Core Speed
Bus Speed
33 MHz
100 MHz
66 MHz
50 MHz
40 MHz
33 MHz
33 MHz
25 MHz
16 MHz
66 MHz
50 MHz
NG80960JC-66
NG80960JC-50
NG80960JC-40
NG80960JC-33
NG80960JS-33
NG80960JS-25
NG80960JS-16
NG80960JD-66
NG80960JD-50
33 MHz
25 MHz
20 MHz
16 MHz
33 MHz
25 MHz
16 MHz
33 MHz
25 MHz
Datasheet
15
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 4. 80960Jx Processors Available in 132-Pin PQFP Package (Sheet 2 of 2)
Processor
NG80960JD-40
Core Speed
Bus Speed
20 MHz
40 MHz
33 MHz
33 MHz
25 MHz
16 MHz
NG80960JD-33
16 MHz
33 MHz
25 MHz
16 MHz
NG80960JA/JF-33
NG80960JA/JF-25
NG80960JA/JF-16
An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation
at V = 3.3 V ± 0.15 V over a case temperature range of -40° to 100°C. The following processor
CC
version is available in the extended temperature PQFP package:
Table 5. 80960Jx Processors Available in Extended Temperature PQFP Package
Processor
TG80960JA-25
Core Speed
Bus Speed
25 MHz
25 MHz
The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at
= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C. The following processor
V
CC
versions are available in the MPBGA package:
Table 6. 80960Jx Processors Available in 196-Ball MPBGA Package
Processor
GD80960JT-100
Core Speed
Bus Speed
33 MHz
100 MHz
66 MHz
50 MHz
40 MHz
33 MHz
33 MHz
25 MHz
16 MHz
50 MHz
33 MHz
25 MHz
GD80960JC-66
GD80960JC-50
GD80960JC-40
GD80960JC-33
GD80960JS-33
GD80960JS-25
GD80960JS-16
GD80960JD-50
GD80960JA/JF-33
GD80960JA-25
33 MHz
25 MHz
20 MHz
16 MHz
33 MHz
25 MHz
16 MHz
25 MHz
33 MHz
25 MHz
For package specifications and information, refer to Intel’s Packaging Handbook (order number
240800).
16
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
3.1
Pin Descriptions
This section describes the pins for the 80960Jx processors. Section 3.1.1 describes pin function.
Refer to the following sections for pinout information for the three package types:
• Section 3.1.2, “80960Jx 132-Lead PGA Pinout” on page 23.
• Section 3.1.3, “80960Jx 132-Lead PQFP Pinout” on page 27.
• Section 3.1.4, “80960Jx 196-Ball MPBGA Pinout” on page 30.
3.1.1
Functional Pin Definitions
Table 7 presents the legend for interpreting the three pin description tables that follow. These tables
define the pins associated with the bus interface, basic control and test functions, and the Interrupt
Unit.
Table 7. Pin Description Nomenclature
Symbol
Description
I
O
Input pin only.
Output pin only.
I/O
–
Pin can be either an input or output.
Pin must be connected as described.
Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.
S
S(E) Edge sensitive input
S(L) Level sensitive input
Asynchronous. Inputs may be asynchronous relative to CLKIN.
A (...)
A(E) Edge sensitive input
A(L) Level sensitive input
While the processor’s RESET# pin is asserted, the pin:
R(1) is driven to VCC
R(0) is driven to VSS
R (...)
R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to VCC
While the processor is in the hold state, the pin:
H(1) is driven to VCC
H(0) is driven to VSS
H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats
H (...)
P (...)
While the processor is halted, the pin:
P(1) is driven to VCC
P(0) is driven to VSS
P(Q) Maintains previous state or continues to be a valid output
Datasheet
17
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 8. Pin Description — External Bus Signals (Sheet 1 of 4)
NAME
TYPE
DESCRIPTION
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (T ) cycle, bits 31:2 contain a physical word
a
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write
data is present on one or more contiguous bytes, comprising AD[31:24], AD[23:16],
AD[15:8] and AD[7:0]. During write operations, unused pins are driven to
determinate values.
SIZE, which comprises bits 0-1 of the AD lines during a T cycle, specifies the
a
number of data transfers during the bus transaction.
AD1
AD0
Bus Transfers
1 Transfer
I/O
S(L)
R(X)
H(Z)
P(Q)
0
0
1
1
0
1
0
1
AD[31:0]
2 Transfers
3 Transfers
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
•
•
write — AD[31:2] are driven with the last data value on the AD bus.
read — AD[31:4] are driven with the last address value on the AD bus; AD[3:2]
are driven with the value of A[3:2] from the last data cycle.
Typically, AD[1:0] reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
O
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
R(0)
H(Z)
P(0)
ALE
ALE#
ADS#
asserted during a T cycle and deasserted before the beginning of the Td state. It is
a
active HIGH and floats to a high impedance state during a hold cycle (Th).
O
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE# is
the inverted version of ALE. This signal gives the 80960Jx a high degree of
compatibility with existing 80960Kx systems.
R(1)
H(Z)
P(1)
O
ADDRESS STROBE indicates a valid address and the start of a new bus access.
R(1)
H(Z)
P(1)
The processor asserts ADS# for the entire T cycle. External bus control logic
a
typically samples ADS# at the end of the cycle.
ADDRESS[3:2] comprise a partial demultiplexed address bus.
32-bit memory accesses: the processor asserts address bits A[3:2] during T . The
partial word address increments with each assertion of RDYRCV# during a aburst.
O
R(X)
H(Z)
P(Q)
16-bit memory accesses: the processor asserts address bits A[3:1] during T with A1
driven on the BE1# pin. The partial short word address increments with each
assertion of RDYRCV# during a burst.
a
A[3:2]
8-bit memory accesses: the processor asserts address bits A[3:0] during T , with
a
A[1:0] driven on BE[1:0]#. The partial byte address increments with each assertion
of RDYRCV# during a burst.
18
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 8. Pin Description — External Bus Signals (Sheet 2 of 4)
NAME
TYPE
DESCRIPTION
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3# enables data on AD[31:24]
BE2# enables data on AD[23:16]
BE1# enables data on AD[15:8]
BE0# enables data on AD[7:0]
16-bit bus:
BE3# becomes Byte High Enable (enables data on AD[15:8])
O
BE2# is not used (state is high)
R(1)
H(Z)
P(1)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Byte Low Enable (enables data on AD[7:0])
BE[3:0]#
8-bit bus:
BE3# is not used (state is high)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Address Bit 0 (A0)
The processor asserts byte enables, byte high enable and byte low enable during T .
a
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last Td cycle.
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A[3:2] described above.
WIDTH/HALTED signals denote the physical memory attributes for a bus
transaction:
WIDTH/
HLTD1
WIDTH/
HLTD0
O
0
0
1
1
0
1
0
1
8 Bits Wide
WIDTH/
HLTD[1:0]
R(0)
H(Z)
P(1)
16 Bits Wide
32 Bits Wide
Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
DATA/CODE indicates that a bus access is a data access (1) or an instruction
access (0). D/C# has the same timing as W/R#.
O
R(X)
H(Z)
P(Q)
D/C#
W/R#
0 = instruction access
1 = data access
WRITE/READ specifies, during a T cycle, whether the operation is a write (1) or
read (0). It is latched on-chip and remains valid during Td cycles.
a
O
R(0)
H(Z)
P(Q)
0 = read
1 = write
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during T
and Tw/Td cycles for a write. DT/R# never changes state when DEN# is asserted. a
O
R(0)
H(Z)
P(Q)
DT/R#
0 = receive
1 = transmit
Datasheet
19
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 8. Pin Description — External Bus Signals (Sheet 3 of 4)
NAME
TYPE
DESCRIPTION
DATA ENABLE indicates data transfer cycles during a bus access. DEN# is
asserted at the start of the first data cycle in a bus access and deasserted at the end
of the last data cycle. DEN# is used with DT/R# to provide control for data
transceivers connected to the data bus.
O
R(1)
H(Z)
P(1)
DEN#
0 = data cycle
1 = not data cycle
BURST LAST indicates the last transfer in a bus access. BLAST# is asserted in the
last data transfer of burst and non-burst accesses. BLAST# remains active as long
as wait states are inserted via the RDYRCV# pin. BLAST# becomes inactive after
the final data transfer in a bus cycle.
O
R(1)
H(Z)
P(1)
BLAST#
0 = last data transfer
1 = not last data transfer
READY/RECOVER indicates that data on AD lines can be sampled or removed. If
RDYRCV# is not asserted during a Td cycle, the Td cycle is extended to the next
cycle by inserting a wait state (Tw).
0 = sample data
1 = don’t sample data
I
RDYRCV#
S(L)
The RDYRCV# pin has another function during the recovery (Tr) state. The
processor continues to insert additional recovery states until it samples the pin
HIGH. This function gives slow external devices more time to float their buffers
before the processor begins to drive address again.
0 = insert wait states
1 = recovery complete
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK# output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK#. This prevents external agents from accessing memory involved
in semaphore operations.
I/O
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
S(L)
R(H)
H(Z)
P(1)
LOCK#/
ONCE#
ONCE MODE: The processor samples the ONCE# input during reset. If it is
asserted LOW at the end of reset, the processor enters ONCE mode. In ONCE
mode, the processor stops all clocks and floats all output pins. The pin has a weak
internal pullup which is active during reset to ensure normal operation when the pin
is left unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the Th state. When
I
HOLD is deasserted, the processor deasserts HOLDA and enters either the Ti or T
a
HOLD
S(L)
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
20
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 8. Pin Description — External Bus Signals (Sheet 4 of 4)
NAME
TYPE
DESCRIPTION
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor can grant HOLD requests and enter
the Th state during reset and while halted as well as during regular operation.
O
R(Q)
H(1)
P(Q)
HOLDA
0 = hold not acknowledged
1 = hold acknowledged
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960® Jx Microprocessor User’s Guide (272483). Arbitration
logic can examine this signal to determine when an external bus master should
acquire/relinquish the bus.
O
R(0)
H(Q)
P(0)
BSTAT
0 = no potential stall
1 = potential stall
Table 9. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
CLOCK INPUT provides the processor’s fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
CLKIN
I
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
During reset, the input pins are ignored with the exception of LOCK#/ONCE#,
STEST and HOLD.
I
RESET#
A(L)
The RESET# pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET# must be asserted a minimum of 10,000
CLKIN cycles with VCC and CLKIN stable. On a warm reset, RESET# should be
asserted for a minimum of 15 cycles.
SELF TEST enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
I
STEST
S(L)
0 = self test disabled
1 = self test enabled
FAIL indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL# is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
O
•
When self-test passes, the processor deasserts FAIL# and begins operation
from user code.
R(0)
H(Q)
P(1)
FAIL#
•
When self-test fails, the processor asserts FAIL# and then stops executing.
0 = self test failed
1 = self test passed
TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TCK
TDI
I
I
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
S(L)
Datasheet
21
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 9. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 2 of 2)
NAME
TYPE
DESCRIPTION
O
TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
R(Q)
HQ)
P(Q)
TDO
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor between this pin and VSS. If TAP is not used,
this pin must be connected to VSS; however, no resistor is required. See Section 4.3,
“Connection Recommendations” on page 42.
I
TRST#
A(L)
I
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of
the test logic for IEEE 1149.1 Boundary Scan testing.
TMS
VCC
S(L)
–
–
POWER pins intended for external connection to a VCC board plane.
PLL POWER is a separate VCC supply pin for the phase lock loop clock generator. It
is intended for external connection to the VCC board plane. In noisy environments,
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects
on timing relationships.
VCCPLL
VCC5
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
buffers. This signal should be connected to +5 V for use with inputs which exceed
3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.
–
VSS
NC
–
–
GROUND pins intended for external connection to a VSS board plane.
NO CONNECT pins. Do not make any system connections to these pins.
Table 10. Pin Description — Interrupt Unit Signals
NAME
TYPE
DESCRIPTION
EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT[7:0]#
pins can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.
I
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
XINT[7:0]#
A(E/L)
Mixed Mode: The XINT[7:5]# pins act as dedicated sources and the XINT[4:0]# pins
act as the five most significant bits of a vectored source. The least significant bits of
the vectored source are set to 0102 internally.
Unused external interrupt pins should be connected to VCC
.
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI# is the highest priority interrupt source and is falling edge-triggered. If NMI# is
I
NMI#
A(E)
unused, it should be connected to VCC
.
22
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
3.1.2
80960Jx 132-Lead PGA Pinout
Figure 3. 132-Lead Pin Grid Array Top View - Pins Facing Down
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P
P
V
V
V
V
V
V
V
V
V
V
CC
AD6 AD11 AD13
AD18 AD19 AD22 AD25
AD20 AD24 AD26 AD27
CC
CC
CC
CC
CC
CC
SS
N
N
V
V
V
V
SS
AD3
AD0
AD7 AD10
SS
SS
SS
SS
SS
M
M
AD9
AD12
AD21 AD23
AD4 AD8
AD1 AD5
AD14 AD15 AD16
AD17
NC AD29 AD30
L
L
V
V
CC
CC
BE3# BE2#
AD28
AD31
K
J
K
J
V
V
AD2
V
V
V
SS
SS
SS
CC
CC
V
NC
VCCPLL
NC
BE1#
V
CC
SS
H
G
F
E
D
A80960Jx
H
G
F
E
D
CLKIN
V
V
BE0#
ALE
V
V
V
SS
SS
CC
CC
SS
M
© 19xx
V
V
V
V
SS
CC
i
BSTAT
V
V
V
V
V
V
RDYRCV#
SS
SS
SS
CC
CC
CC
XXXXXXXX SS
V
RESET#
TDI
DEN#
DT/R#
CC
SS
SS
V
V
V
CC
SS
CC
C
B
A
C
B
A
LOCK#/
ONCE#
NC STESTTRST#XINT0#XINT1# HOLD NC
VCC5
FAIL#
A2
A3 BLAST# HOLDA
NC
TCK
XINT4#
XINT3# XINT6#
V
V
V
V
SS
NC TDO WIDTH/ D/C# W/R#
HLTD0
SS
SS
SS
NC
NC
ALE#
TMS XINT2# XINT5#XINT7# NMI#
V
V
V
V
WIDTH/ ADS#
HLTD1
CC
CC
CC
CC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Datasheet
23
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 4. 132-Lead Pin Grid Array Bottom View - Pins Facing Up
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
P
AD25 AD22 AD19 AD18
AD27 AD26 AD24 AD20
V
V
V
V
V
V
V
V
V
CC
AD13 AD11
AD10 AD7
AD8 AD4
AD6
AD3
AD0
CC
CC
CC
CC
CC
SS
CC
N
N
V
V
V
V
V
SS
SS
SS
SS
SS
SS
M
M
AD23 AD21
AD12
AD9
AD17
AD16 AD15 AD14
AD30 AD29 NC
BE2# BE3# AD28
L
K
J
L
K
J
AD1
V
AD5
AD2
CC
V
V
V
V
V
AD31
BE1#
SS
CC
SS
CC
CC
NC
V
V
V
V
SS
CC
SS
SS
H
G
F
H
G
F
VCCPLL V
CLKIN
V
V
BE0#
ALE
SS
SS
CC
CC
V
NC
V
V
SS
CC
BSTAT
V
V
V
RDYRCV#V
RESET# V
V
CC
CC
SS
SS
SS
SS
SS
CC
E
D
E
D
V
V
DEN#
DT/R#
CC
V
V
TDI
V
V
CC
CC
SS
C
B
A
C
B
A
LOCK#/
ONCE#
HOLDA BLAST# A3
A2
FAIL#
VCC5
HOLD XINT1#XINT0#TRST#STEST NC
NC
XINT4# TCK
XINT3#
NC
W/R# D/C# WIDTH/ TDO NC
HLTD0
V
V
V
V
SS
XINT6#
SS
SS
CC
SS
CC
ALE#
NC
NC
ADS# WIDTH/
HLTD1
V
V
V
V
NMI# XINT7#XINT5# XINT2# TMS
CC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
24
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 11. 132-Lead PGA Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A2
C5
C4
AD31
ADS#
ALE
K3
A1
TDO
TMS
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPLL
VCC5
VSS
B4
A14
C12
A6
VSS
VSS
B9
D2
A3
AD0
M14
L13
K12
N14
M13
L12
P14
N13
M12
M11
N12
P13
M10
P12
M9
G3
A3
VSS
D13
E2
AD1
ALE#
BE0#
BE1#
BE2#
BE3#
BLAST#
BSTAT
CLKIN
D/C#
VSS
AD2
H3
A7
VSS
E13
F2
AD3
J3
A8
VSS
AD4
L1
A9
VSS
F13
G2
AD5
L2
D1
VSS
AD6
C3
D14
E1
VSS
G13
H2
AD7
F3
VSS
AD8
H14
B2
E14
F1
VSS
H13
J2
AD9
VSS
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
DEN#
DT/R#
FAIL#
HOLD
HOLDA
LOCK#/ONCE#
NC
E3
F14
G1
G14
H1
VSS
J13
K2
D3
VSS
C6
VSS
K13
N5
C9
VSS
C2
J1
VSS
N6
M8
C1
J14
K1
VSS
N7
M7
A4
VSS
N8
M6
NC
A5
K14
L14
P5
VSS
N9
P4
NC
B5
VSS
N10
N11
B1
P3
NC
B14
C8
VSS
N4
NC
P6
W/R#
WIDTH/HLTD0
WIDTH/HLTD1
XINT0#
XINT1#
XINT2#
XINT3#
XINT4#
XINT5#
XINT6#
XINT7#
M5
NC
C14
G12
J12
M3
A10
F12
E12
C13
B13
D12
P7
B3
P2
NC
P8
A2
M4
NC
P9
C11
C10
A13
B12
B11
A12
B10
A11
N3
NC
P10
P11
H12
C7
P1
NMI#
N2
RDYRCV#
RESET#
STEST
TCK
N1
L3
B6
M2
VSS
B7
M1
TDI
VSS
B8
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Datasheet
25
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 12. 132-Lead PGA Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A1
A2
ADS#
WIDTH/HLTD1
ALE#
C6
C7
FAIL#
VCC5
NC
H1
H2
VCC
VSS
M10
M11
M12
M13
M14
N1
AD12
AD9
AD8
AD4
AD0
AD27
AD26
AD24
AD20
VSS
A3
C8
H3
BE0#
VCCPLL
VSS
A4
NC
C9
HOLD
XINT1#
XINT0#
TRST#
STEST
NC
H12
H13
H14
J1
A5
NC
C10
C11
C12
C13
C14
D1
A6
VCC
CLKIN
VCC
A7
VCC
N2
A8
VCC
J2
VSS
N3
A9
VCC
J3
BE1#
NC
N4
A10
A11
A12
A13
A14
B1
NMI#
VCC
J12
J13
J14
K1
N5
XINT7#
XINT5#
XINT2#
TMS
D2
VSS
VSS
N6
VSS
D3
DT/R#
TDI
VCC
N7
VSS
D12
D13
D14
E1
VCC
N8
VSS
VSS
K2
VSS
N9
VSS
W/R#
VCC
K3
AD31
AD2
N10
N11
N12
N13
N14
P1
VSS
B2
D/C#
VCC
K12
K13
K14
L1
VSS
B3
WIDTH/HLTD0
TDO
E2
VSS
VSS
AD10
AD7
AD3
AD25
AD22
AD19
AD18
VCC
B4
E3
DEN#
RESET#
VSS
VCC
B5
NC
E12
E13
E14
F1
BE2#
BE3#
AD28
AD5
B6
VSS
L2
B7
VSS
VCC
L3
P2
B8
VSS
VCC
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
P3
B9
VSS
F2
VSS
AD1
P4
B10
B11
B12
B13
B14
C1
XINT6#
XINT4#
XINT3#
TCK
F3
BSTAT
RDYRCV#
VSS
VCC
P5
F12
F13
F14
G1
AD30
AD29
NC
P6
VCC
P7
VCC
VCC
P8
VCC
NC
VCC
AD23
AD21
AD17
AD16
AD15
AD14
P9
VCC
LOCK#/ONCE#
HOLDA
BLAST#
A3
G2
VSS
P10
P11
P12
P13
P14
VCC
C2
G3
ALE
VCC
C3
G12
G13
G14
NC
AD13
AD11
AD6
C4
VSS
C5
A2
VCC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
26
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
3.1.3
80960Jx 132-Lead PQFP Pinout
Figure 5. 132-Lead PQFP - Top View
AD9
99
1
TRST#
TCK
TMS
HOLD
XINT0#
XINT1#
XINT2#
98
97
96
95
94
93
V
V
(I/O)
(I/O)
2
3
4
5
6
7
CC
SS
AD10
AD11
V
V
V
(I/O)
(I/O)
(Core)
CC
SS
CC
XINT3#
(I/O)
CC
92
91
90
8
9
10
V
(Core)
V
V
SS
AD12
(I/O)
SS
89
88
87
86
85
84
83
82
81
80
79
78
11
12
13
14
15
16
17
18
19
20
21
22
AD13
AD14
AD15
XINT4#
XINT5#
XINT6#
V
(I/O)
XINT7#
NMI#
CC
V
(I/O)
SS
®
AD16
AD17
AD18
AD19
V
V
(Core)
(Core)
CC
SS
i960
NC
NC
V
V
(I/O)
(I/O)
VCC5
NC
NC
FAIL#
ALE#
TDO
CC
SS
AD20
AD21
AD22
AD23
NG80960Jx
77
76
75
74
73
72
71
23
24
25
26
27
28
29
XXXXXXXX SS
V
V
(Core)
(Core)
V
V
(I/O)
(I/O)
CC
SS
CC
M
© 19xx
SS
i
V
V
(I/O)
(I/O)
WIDTH/HLTD1
CC
SS
V
V
(Core)
(Core)
CC
AD24
70
69
68
67
30
31
32
33
SS
WIDTH/HLTD0
A2
AD25
AD26
NC
A3
Datasheet
27
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 13. 132-Lead PQFP Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
60
61
ALE#
ADS#
24
36
33
32
55
54
53
52
28
31
35
37
42
43
34
132
50
4
VCC (Core)
47
59
VSS (Core)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
VSS (I/O)
NC
124
10
27
40
48
56
64
71
79
85
93
97
106
112
131
18
19
21
22
67
121
122
126
127
14
13
12
11
VCC (Core)
VCC (Core)
VCC (Core)
VCC (Core)
VCC (Core)
VCC (Core)
62
A3
74
63
A2
92
66
BE3#
113
115
123
9
68
BE2#
69
BE1#
70
BE0#
V
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
CC (I/O)
75
WIDTH/HLTD1
WIDTH/HLTD0
D/C#
V
26
76
V
V
V
V
V
V
V
V
V
V
V
V
41
77
49
78
W/R#
57
81
DT/R#
65
82
DEN#
72
83
BLAST#
RDYRCV#
LOCK#/ONCE#
HOLD
80
84
86
87
94
NC
88
98
NC
89
HOLDA
BSTAT
CLKIN
RESET#
STEST
FAIL#
44
51
117
125
128
23
2
105
111
129
119
20
NC
90
NC
95
NC
96
VCCPLL
VCC5
NC
99
NC
AD8
100
101
102
103
104
107
108
109
110
45
V
SS (CLK)
SS (Core)
SS (Core)
SS (Core)
SS (Core)
SS (Core)
118
17
NC
AD7
TCK
V
V
V
V
V
XINT7#
XINT6#
XINT5#
XINT4#
XINT3#
XINT2#
XINT1#
XINT0#
NMI#
AD6
TDI
130
25
1
30
AD5
TDO
38
AD4
TRST#
TMS
46
AD3
3
58
8
AD2
V
CC (CLK)
120
16
29
39
VSS (Core)
VSS (Core)
VSS (Core)
VSS (Core)
73
7
AD1
V
V
V
CC (Core)
CC (Core)
CC (Core)
91
6
AD0
114
116
5
ALE
15
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
28
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 14. 132-Lead PQFP Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
TRST#
TCK
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
BLAST#
D/C#
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
NC
AD26
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
AD8
AD7
2
3
TMS
ADS#
W/R#
AD25
AD6
4
HOLD
XINT0#
XINT1#
XINT2#
XINT3#
AD24
AD5
5
VSS (Core)
VSS (I/O)
VCC (I/O)
VSS (Core)
VCC (Core)
AD23
AD4
6
VCC (Core)
VCC (I/O)
VSS (I/O)
AD3
7
V
SS (I/O)
8
VCC (I/O)
9
VCC (I/O)
DT/R#
DEN#
AD2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
V
SS (I/O)
AD22
AD1
XINT4#
XINT5#
XINT6#
XINT7#
NMI#
HOLDA
ALE
AD21
AD0
AD20
VCC (I/O)
VSS (Core)
VSS (I/O)
VCC (I/O)
AD19
VSS (I/O)
VCC (Core)
VSS (Core)
VCC (Core)
VSS (Core)
CLKIN
VCC (Core)
V
SS (I/O)
V
CC (Core)
VCC (I/O)
LOCK#/ONCE#
BSTAT
AD18
V
SS (Core)
AD17
NC
AD16
NC
BE0#
V
SS (I/O)
CC (I/O)
AD15
VSS (CLK)
VCCPLL
VCC (CLK)
NC
VCC5
NC
BE1#
V
BE2#
NC
BE3#
AD14
FAIL#
ALE#
TDO
V
SS (I/O)
CC (I/O)
AD13
NC
V
AD12
VCC (Core)
VSS (Core)
RESET#
NC
VSS (Core)
VSS (Core)
VCC (Core)
VSS (I/O)
VCC (I/O)
VCC (Core)
AD31
V
SS (I/O)
WIDTH/HLTD1
CC (Core)
SS (Core)
AD30
V
CC (I/O)
AD11
NC
V
AD29
STEST
V
AD28
AD10
VCC (I/O)
TDI
WIDTH/HLTD0
V
SS (I/O)
CC (I/O)
AD27
VSS (I/O)
VCC (I/O)
AD9
A2
A3
V
VSS (I/O)
RDYRCV#
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Datasheet
29
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
3.1.4
80960Jx 196-Ball MPBGA Pinout
Figure 6. 196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
A
B
C
AD28
V
NC
V
V
AD22
V
AD18
V
AD15 AD13
V
CC
NC
AD8
NC
CC
CC
CC
CC
CC
AD30 AD27 AD29
AD23 AD20 AD17 AD14 AD12 AD10 AD9 AD7
AD4
V
CC
AD26 AD25
V
V
CC
AD24 AD21 AD19 AD16
AD11 AD6
AD5 AD0
AD2
AD1
NC
NC
AD31
NC
NC
NC
CC
D
E
F
G
H
J
D
E
F
G
H
J
V
V
V
V
V
V
V
V
AD3
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
NC
NC
NC
NC
V
V
V
V
V
V
CC
CC
CC
SS
CC
CC
CC
VCCPLL
NC
NC
V
V
V
V
V
V
V
V
CC
CC
SS
SS
SS
SS
SS
SS
SS
SS
NC CLKIN
NC
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
NC
V
CC
SS
SS
BE1# BE2# BE3#
BSTAT
V
V
V
BE0#
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
TDI
NC
NC
NC RESET#
CC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
K
L
K
L
LOCK#/
ONCE#
ALE
V
STEST
V
V
V
V
V
V
SS
CC
CC
SS
SS
SS
SS
HOLDA DEN#
V
V
V
V
V
SS
NC RDYRCV#
CC
SS
SS
SS
M
N
M
N
DT/R#
V
NC
NC
NC
NC
A3
V
V
ALE# VCC5
V
XINT2# XINT0# TMS TRST# TCK
CC
CC
CC
CC
TDO
NC XINT4#
XINT6#
XINT3# HOLD
XINT1#
W/R# D/C#
A2
NC
P
P
BLAST#
V
WIDTH0
NC
ADS#
WIDTH1FAIL#
NC
NC
NMI# XINT7#XINT5#
V
NC
CC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
30
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 7. 196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
A
B
C
V
AD13 AD15
V
AD18
V
AD22
V
NC
V
AD28
NC
AD8
NC
CC
CC
CC
CC
CC
CC
AD4
AD7 AD9 AD10 AD12 AD14 AD17 AD20 AD23
V
AD29 AD27 AD30
V
CC
V
V
AD25 AD26
AD2
AD1
AD6 AD11
AD0 AD5
AD16 AD19 AD21 AD24
NC
NC
AD31
NC
NC
NC
CC
CC
D
E
F
G
H
J
D
E
F
G
H
J
AD3
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
NC
NC
CC
CC
CC
CC
CC
SS
CC
VCCPLL
V
V
V
V
V
V
V
V
V
V
V
NC
NC
NC
NC
SS
SS
SS
SS
SS
SS
SS
SS
CC
CC
CLKIN NC
NC
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
BE3# BE2# BE1#
V
NC
SS
SS
CC
V
V
BSTAT
V
V
V
V
V
V
V
V
V
V
V
V
V
BE0#
V
CC
SS
SS
RESET# NC
TDI
NC
NC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
K
L
K
L
ALE
V
LOCK#/
ONCE#
STEST
V
CC
V
V
V
V
V
SS
SS
SS
SS
SS
CC
RDYRCV# NC
V
V
V
V
DEN# HOLDA
V
CC
SS
SS
SS
SS
M
N
M
N
DT/R#
TCK TRST# TMS XINT0# XINT2#
V
VCC5 ALE#
V
V
A3
A2
NC
NC
NC
NC
V
CC
CC
CC
CC
HOLD XINT3# XINT1# XINT6# NC XINT4# NC
TDO
D/C# W/R#
P
P
WIDTH0 V
BLAST#
NC
V
XINT5# XINT7# NMI# NC
NC
FAIL# WIDTH1
ADS#
NC
CC
CC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Datasheet
31
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 15. 196-Ball MPBGA Pinout — In Signal Order (Sheet 1 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
A2
N5
M5
D13
D14
C14
D11
B14
D12
C13
B13
A13
B12
B11
C12
B10
A11
B9
BE0#
BE1#
BE2#
BE3#
BLAST#
BSTAT
CLKIN
DEN#
D/C#
DT/R#
FAIL#
HOLD
HOLDA
LOCK#/ONCE#
NC
J2
H1
NC
NC
M4
N3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCPLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1
K3
A3
AD0
H2
NC
N4
K13
L3
AD1
H3
NC
N8
AD2
P3
NC
N10
P1
M2
M6
M9
N6
P4
AD3
J3
NC
AD4
G13
L2
NC
P8
AD5
NC
P9
AD6
N2
NC
P14
P10
L14
J14
K14
M14
J12
N7
AD7
M1
P7
NMI#
RDYRCV#
RESET#
STEST
TCK
TDI
P13
F14
D4
D5
D6
D7
D8
D9
D10
E4
AD8
AD9
N14
L1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
ADS#
ALE
K2
A1
NC
A4
TDO
TMS
TRST#
VCC5
VCC
NC
A14
C1
M12
M13
M8
A3
A10
C9
NC
NC
C3
B8
NC
D1
E5
A8
NC
D2
VCC
A5
E6
C8
NC
D3
VCC
A7
E7
B7
NC
E1
VCC
A9
E8
C7
NC
E2
VCC
A12
B1
E9
A6
NC
F1
VCC
E10
E11
F4
B6
NC
F2
VCC
B5
C6
NC
G1
G2
G12
G14
H12
H14
J13
K12
L12
L13
M3
VCC
C10
C11
E3
C5
NC
VCC
F5
C4
NC
VCC
F6
B3
NC
VCC
E12
E13
E14
F3
F7
A2
NC
VCC
F8
B4
NC
VCC
F9
B2
NC
VCC
F10
F11
G4
G5
G6
C2
NC
VCC
F12
F13
G3
P2
NC
VCC
K1
NC
VCC
ALE#
M7
NC
VCC
H13
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
32
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 15. 196-Ball MPBGA Pinout — In Signal Order (Sheet 2 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G7
G8
G9
G10
G11
H4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H11
J4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K7
K8
K9
K10
K11
L5
VSS
L11
P5
WIDTH0
WIDTH1
W/R#
J5
P6
J6
N1
J7
XINT0#
XINT1#
XINT2#
XINT3#
XINT4#
XINT5#
XINT6#
XINT7#
M11
N12
M10
N13
N9
J8
H5
J9
L6
H6
J10
J11
K4
K5
K6
L7
H7
L8
H8
L9
P12
N11
P11
H9
L10
L4
H10
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Table 16. 196-Ball MPBGA Pinout — In Pin Order (Sheet 1 of 2)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A1
A2
NC
AD28
VCC
C11
C12
C13
C14
D1
VCC
AD11
AD6
AD2
NC
F7
F8
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCCPLL
NC
J3
J4
BSTAT
VSS
A3
F9
J5
VSS
A4
NC
F10
F11
F12
F13
F14
G1
J6
VSS
A5
VCC
J7
VSS
A6
AD22
VCC
D2
NC
J8
VSS
A7
D3
NC
J9
VSS
A8
AD18
VCC
D4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD3
AD5
AD0
AD1
NC
J10
J11
J12
J13
J14
K1
K2
K3
K4
K5
K6
K7
K8
VSS
A9
D5
VSS
A10
A11
A12
A13
A14
B1
AD15
AD13
VCC
D6
G2
NC
TDI
D7
G3
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
D8
G4
RESET#
ALE
AD8
NC
D9
G5
D10
D11
D12
D13
D14
E1
G6
LOCK#/ONCE#
VCC
VCC
G7
B2
AD30
AD27
AD29
VCC
G8
VSS
B3
G9
VSS
B4
G10
G11
G12
VSS
B5
VSS
B6
AD23
E2
NC
VSS
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Datasheet
33
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 16. 196-Ball MPBGA Pinout — In Pin Order (Sheet 2 of 2)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
B7
B8
AD20
AD17
AD14
AD12
AD10
AD9
E3
E4
VCC
VSS
G13
G14
H1
CLKIN
NC
K9
K10
K11
K12
K13
K14
L1
VSS
VSS
B9
E5
VSS
BE1#
BE2#
BE3#
VSS
VSS
B10
B11
B12
B13
B14
C1
E6
VSS
H2
NC
E7
VSS
H3
VCC
E8
VSS
H4
STEST
HOLDA
DEN#
VCC
AD7
E9
VSS
H5
VSS
AD4
E10
E11
E12
E13
E14
F1
VSS
H6
VSS
L2
NC
VSS
H7
VSS
L3
C2
AD31
NC
VCC
VCC
VCC
NC
H8
VSS
L4
VSS
C3
H9
VSS
L5
VSS
C4
AD26
AD25
AD24
AD21
AD19
AD16
VCC
H10
H11
H12
H13
H14
J1
VSS
L6
VSS
C5
VSS
L7
VSS
C6
F2
NC
NC
L8
VSS
C7
F3
VCC
VSS
VCC
L9
VSS
C8
F4
NC
L10
L11
L12
P4
VSS
C9
F5
VSS
VCC
VSS
C10
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
F6
VSS
J2
BE0#
TDO
NC
NC
NC
M10
M11
M12
M13
M14
N1
XINT2#
XINT0#
TMS
TRST#
TCK
W/R#
D/C#
NC
N7
VCC
RDYRCV#
DT/R#
VCC
N8
P5
WIDTH0
WIDTH1
FAIL#
NC
N9
XINT4#
NC#
P6
N10
N11
N12
N13
N14
P1
P7
NC
XINT6#
XINT1#
XINT3#
HOLD
NC
P8
NC
P9
NC
A3
N2
P10
P11
P12
P13
P14
NMI#
XINT7#
XINT5#
VCC
VCC
N3
ALE#
VCC5
VCC
N4
NC
N5
A2
P2
ADS#
BLAST#
N6
VCC
P3
NC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
34
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
3.2
Package Thermal Specifications
The 80960Jx is specified for operation when T (case temperature) is within the range of 0°C to
C
100°C for PGA, MPBGA and PQFP packages. An extended temperature device is also available in
a PQFP package with T = -40°C to 100°C. Case temperature may be measured in any
C
environment to determine whether the 80960Jx is within its specified operating range. The case
temperature should be measured at the center of the top surface, opposite the pins.
θ
is the thermal resistance from case to ambient. Use the following equation to calculate T , the
A
CA
maximum ambient temperature to conform to a particular case temperature:
T = T - P (θ
)
CA
A
C
Junction temperature (T ) is commonly used in reliability calculations. T can be calculated from
J
J
θ
(thermal resistance from junction to case) using the following equation:
JC
T = T + P (θ )
JC
J
C
Similarly, if T is known, the corresponding case temperature (T ) can be calculated as follows:
A
C
T = T + P (θ )
CA
C
A
Compute P by multiplying I from Table 30, “80960Jx I Characteristics” on page 44 and V .
CC
CC
CC
See the following tables for θ and θ values:
JC
CA
PGA package:
Table 17 on page 36
MPBGA package:
PQFP package:
Table 18 on page 36 and Table 19 on page 37
Table 20 on page 37
For high speed operation, the processor’s θ may be significantly reduced by adding a heatsink
JA
and/or by increasing airflow.
Refer to the following tables for the maximum ambient temperature (T ) permitted without
A
exceeding T for the PGA, MPBGA, and PQFP packages. The values are based on typical I and
C
CC
V
of +3.3 V, with a T of +100°C.
CC
C
80960JT processor:
80960JC processor:
80960JD processor:
80960JS processor:
80960JA/JF processor:
Table 21 on page 38
Table 22 on page 38
Table 23 on page 39
Table 24 on page 39
Table 25 on page 40
Datasheet
35
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 17. 132-Lead PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.08)
θJC (Junction-to-Case)
θCA (Case-to-Ambient) (No Heatsink)
0.7
25
15
16
0.7
19
9
0.7
14
6
0.7
12
5
0.7
11
4
0.7
10
4
θ
θ
CA (Case-to-Ambient) (Omnidirectional Heatsink)
CA (Case-to-Ambient) (Unidirectional Heatsink)
8
6
5
4
4
θJA
θCA
θJC
θJ-PIN
θJ-CAP
NOTES:
1. This table applies to a PGA device plugged into a socket or soldered directly into a board.
2. θ = θ + θ
JA
JC
CA
3. θ
4. θ
5. θ
6. θ
7. θ
8. θ
= 5.6°C/W (approximate) (no heatsink)
J-CAP
J-PIN
J-PIN
J-CAP
J-PIN
J-PIN
= 6.4°C/W (inner pins) (approximate) (no heatsink)
= 6.2°C/W (outer pins) (approximate) (no heatsink)
= 3°C/W (approximate) (with heatsink)
= 3.3°C/W (inner pins) (approximate) (with heatsink)
= 3.3°C/W (outer pins) (approximate) (with heatsink)
Table 18. 80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.08)
θJC (Junction-to-Case)
2
2
2
2
2
2
θCA (Case-to-Ambient) (No Heatsink)
30
22
20
19
18
18
θJA
θCA
θJC
NOTES:
1. This table applies to an MPBGA device soldered directly into a board with all VSS connections.
2. θ = θ + θ
JA JC
CA
36
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 19. 80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.08)
θJC (Junction-to-Case)
2
2
2
2
2
2
θCA (Case-to-Ambient) (No Heatsink)
34
25
23
22
21
20
θJA
θCA
θJC
NOTES:
1. This table applies to an MPBGA device soldered directly into a board with all VSS connections.
2. θ = θ + θ
JA JC
CA
Table 20. 132-Lead PQFP Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
50
100
200
400
600
800
(0)
(0.25)
(0.50)
(1.01)
(2.03)
(3.04)
(4.06)
θJC (Junction-to-Case)
4.1
23
4.3
19
4.3
18
4.3
16
4.3
14
4.7
11
4.9
9
θCA (Case-to-Ambient -No Heatsink)
θCA
θJA
θJC
θJB
θJL
NOTES:
1. This table applies to a PQFP device soldered directly into board.
2. θ = θ + θ
JA
JL
JC
CA
3. θ = 13°C/W (approx.)
4. θ = 13.5°C/W (approx.)
JB
Datasheet
37
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 21. Maximum T at Various Airflows in °C (80960JT)
A
Airflow-ft/min (m/sec)
fCLKIN
(MHz)
0
(0)
200
400
600
800
1000
(1.01) (2.03) (3.04) (4.06) (5.07)
TA without Heatsink
PQFP
Package
33
63
74
78
82
86
87
T
A without Heatsink
33
33
60
76
70
86
78
90
81
92
82
94
84
94
TA with Omnidirectional
PGA
Package
Heatsink1
T
A with Unidirectional
33
33
74
46
87
60
90
63
92
65
94
66
94
68
Heatsink2
MPBGA
Package
TA without Heatsink
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 22. Maximum T at Various Airflows in °C (80960JC)
A
Airflow-ft/min (m/sec)
0
fCLKIN (MHz)
(0)
200
400
600
800
1000
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
20
75
79
84
86
82
86
89
90
85
87
90
92
88
90
92
93
90
92
94
95
91
93
94
95
PQFP
Package
TA without Heatsink
16.67
33
25
20
73
78
83
85
79
83
87
89
85
87
90
92
87
89
92
93
88
90
92
93
89
91
93
94
TA without Heatsink
16.67
33
25
20
84
87
90
91
90
92
94
95
93
95
96
96
95
96
97
97
96
96
97
98
96
96
97
98
PGA
TA with Omnidirectional
Package Heatsink1
16.67
33
25
20
82
86
89
90
91
93
94
95
93
95
96
96
95
96
97
97
96
96
97
98
96
96
97
98
TA with Unidirectional
Heatsink2
16.67
33
25
20
63
69
76
80
73
78
83
85
75
79
84
86
76
80
85
87
77
81
85
87
78
82
86
88
MPBGA
Package
TA without Heatsink
16.67
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
38
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 23. Maximum T at Various Airflows in °C (80960JD)
A
Airflow-ft/min (m/sec)
0
(0)
200
400
600
800
1000
fCLKIN (MHz)
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
20
61
70
75
79
73
79
82
86
76
82
85
87
81
86
88
90
85
88
90
92
86
90
91
93
PQFP
Package
TA without Heatsink
16.67
33
25
20
58
68
73
78
68
75
79
83
76
82
85
87
80
84
87
89
81
86
88
90
83
87
89
91
TA without Heatsink
16.67
33
25
20
75
81
84
87
85
88
90
92
90
92
93
95
92
94
95
96
93
95
96
96
93
95
96
96
PGA
TA with Omnidirectional
Package Heatsink1
16.67
33
25
20
73
79
82
86
86
90
91
93
90
92
93
95
92
94
95
96
93
95
96
96
93
96
96
96
TA with Unidirectional
Heatsink2
16.67
MPBGA
Package
TA without Heatsink
25
61
72
74
76
77
77
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 24. Maximum T at Various Airflows in °C (80960JS)
A
Airflow-ft/min (m/sec)
0
(0)
200
400
600
800
1000
f
CLKIN (MHz)
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
16.67
84
86
91
89
90
94
90
92
94
92
93
96
94
95
96
94
95
97
PQFP
Package
TA without Heatsink
33
25
16.67
83
85
90
87
89
92
90
92
94
92
93
95
92
93
96
93
94
96
TA without Heatsink
33
25
16.67
90
91
94
94
95
96
96
96
98
97
97
98
97
98
98
97
98
98
PGA
TA with Omnidirectional
Package Heatsink1
33
25
16.67
89
90
94
94
95
97
96
96
98
97
97
98
97
98
98
97
98
98
TA with Unidirectional
Heatsink2
33
25
16.67
76
80
86
83
85
90
84
86
91
85
87
91
85
87
92
86
88
92
MPBGA
Package
TA without Heatsink
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Datasheet
39
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 25. Maximum T at Various Airflows in °C (80960JA/JF)
A
Airflow-ft/min (m/sec)
0
fCLKIN (MHz)
(0)
200
400
600
800
1000
(1.01) (2.03) (3.04) (4.06) (5.07)
33
25
16
79
84
89
86
89
92
87
90
93
90
92
95
92
94
96
93
94
96
For NG80960JA/JF
TA without Heatsink
PQFP
Package
For TG80960JA-25
TA without Heatsink
25
84
89
90
92
94
94
33
25
16
78
83
88
83
87
91
87
90
93
89
92
94
90
92
95
91
93
95
TA without Heatsink
33
25
16
87
90
93
92
94
96
95
96
97
96
97
98
96
97
98
96
97
98
PGA
TA with Omnidirectional
Package Heatsink1
33
25
16
86
89
92
93
94
96
95
96
97
96
97
98
96
97
98
96
97
98
TA with Unidirectional
Heatsink2
MPBGA
Package
33
25
73
79
80
84
82
86
83
87
84
87
84
87
TA without Heatsink
NOTES:
1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).
2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
3.3
Thermal Management Accessories
The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an
endorsement or a warranty of the performance of any of the listed products and/or companies.
3.3.1
Heatsinks
1. Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
(972) 243-4321
2. Wakefield Engineering
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900
3. Aavid Thermal Technologies, Inc.
One Kool Path
Laconia, NH 03247-0400
(603) 528-3400
40
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
This document contains information on products in the production phase of development. The
specifications within this datasheet are subject to change without prior notice. Verify with your
local Intel sales office or the world wide web to ensure that you have the latest datasheet and device
specification update before finalizing a design.
Warning: Stressing the device beyond the “Absolute Maximum Ratings” will cause permanent damage.
These are stress ratings only.
Table 26. Absolute Maximum Ratings
Parameter
Maximum Rating
Storage Temperature
–65oC to +150oC
–65oC to +110oC
–0.5 V to + 4.6 V
–0.5 V to + 6.5 V
Case Temperature Under Bias
Supply Voltage wrt. VSS
Voltage on VCC5 wrt. VSS
Voltage on Other Pins wrt. VSS
–0.5 V to VCC + 0.5 V
4.2
Operating Conditions
Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Table 27 indicates the operating conditions for the 80960Jx 3.3v processors.
Table 27. 80960Jx Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
V
Supply Voltage
3.15
3.15
3.45
5.5
V
V
CC
VCC5
Input Protection Bias
(1)
Input Clock Frequency
80960JT-100
80960JC-66
15
15
15
15
15
15
15
15
12
12
12
12
12
12
12
33.3
33.3
25
20
16.67
33
25
16.67
33.3
25
80960JC-50
80960JC-40
80960JC-33
80960JS-33
80960JS-25
80960JS-16
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
f
MHz
CLKIN
20
16.67
33.3
25
16
Operating Case Temperature
PGA, MPBGA, and PQFP
TC
0
-40
100
100
°C
Extended temp PQFP (TG80960JA-25)
1. See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 42.
Datasheet
41
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.3
Connection Recommendations
For clean on-chip power distribution, V and V pins separately feed the device’s functional units.
CC
SS
Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board,
every V pin should connect to a power plane and every V pin should connect to a ground plane. Place
CC
SS
liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges.
The 80960JS/JC/JT processors are produced on Intel’s advanced CMOS process. Proper bulk decoupling
must be used to prevent device damage during initial power up and during transitions from low power
mode to normal processor operation. Power supply behavior during these transitions can cause the power
supply to exceed the maximum V specification and may cause device damage.
CC
Pay special attention to the Test Reset (TRST#) pin. It is essential that the JTAG Boundary Scan Test
Access Port (TAP) controller initializes to a known state whether it will be used or not. If the JTAG
Boundary Scan function will be used, connect a pulldown resistor between the TRST# pin and V . If the
SS
JTAG Boundary Scan function will not be used (even for board-level testing), connect the TRST# pin to
V .
SS
Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used.
Note: Pins identified as NC must not be connected in the system.
4.4
VCC5 Pin Requirements (VDIFF)
In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V V plane.
CC
In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V
components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation, and
prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and its
3.3 V V pins must not exceed 2.25 V. If this requirement is not met, current flow through the pin
CC
may exceed the value at which the processor is damaged. Instances when the voltage can exceed
2.25 V is during power up or power down, where one source reaches its level faster than the other,
briefly causing an excess voltage differential. Another instance is during steady-state operation,
where the differential voltage of the regulator (provided a regulator is used) cannot be maintained
within 2.25 V. Two methods are possible to prevent this from happening:
• Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V.
or:
• As shown in Figure 8, place a 100 Ω resistor in series with the VCC5 pin to limit the current
through VCC5.
Figure 8. VCC5 Current-Limiting Resistor
+5 V (±0.25 V)
VCC5 Pin
100 Ω
(±5%, 0.5 W)
42
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and
reliable method for limiting current. The resistor can also prevent damage in the case of a power
failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.
Table 28. VDIFF Parameters
Symbol
Parameter
Min
Max
Units
Notes
VCC5 input should not exceed VCC by more than 2.25 V
during power-up and power-down, or during steady-
state operation.
VCC5-VCC
Difference
VDIFF
2.25
V
4.5
VCCPLL Pin Requirements
To reduce clock skew on the 80960Jx processor, the VCCPLL pin for the Phase Lock Loop (PLL)
circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise induced
clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor must be
low ESR solid tantalum; the 0.01 µF capacitor must be of the type X7R and the node connecting
VCCPLL must be as short as possible.
If the voltage on the VCCPLL power supply pin exceeds the V pin voltage by 0.5 V at any time,
CC
including the power up and power down sequences, excessive currents can permanently damage
on-chip electrostatic discharge (ESD) protection diodes. The damage can accumulate over multiple
episodes.
In actual applications, this problem occurs only when the VCCPLL and V pins are driven by
CC
separate power supplies or voltage regulators. Applications that use one power supply for
VCCPLL and V are not typically at risk. Verify that your application does not allow the
CC
VCCPLL voltage to exceed V by 0.5 V.
CC
The VCCPLL low-pass filter recommendation does not promote this problem.
Figure 9. VCCPLL Lowpass Filter
100
10
Ω (80960JA/JF/JD)
Ω (80960JS/JC/JT)
VCCPLL
(On 80960Jx)
+
VCC
(Board Plane)
4.7 µF
0.01 µF
F_CA078A
Datasheet
43
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.6
DC Specifications
Table 29. 80960Jx DC Characteristics
Symbol
VIL
Parameter
Min
Typ
Max
Units
Notes
Input Low Voltage
-0.3
2.0
0.8
VCC5 + 0.3
0.4
V
V
V
V
V
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
Output Ground Bounce
VOL
VOH
VOLP
IOL = 3 mA
IOH = -1 mA
(1,2)
2.4
<0.8
Input Capacitance
PGA
PQFP
15
15
15
f
f
f
= fMIN
(2)
CLKIN
CLKIN
CLKIN
CIN
pF
pF
pF
MPBGA
I/O or Output Capacitance
PGA
PQFP
MPBGA
15
15
15
= fMIN
(2)
COUT
CLKIN Capacitance
PGA
PQFP
15
15
15
= fMIN
(2)
CCLK
MPBGA
NOTES:
1. Typical is measured with VCC = 3.3 V and temperature = 25°C.
2. Not tested.
Table 30. 80960Jx I Characteristics (Sheet 1 of 4)
CC
Symbol
Parameter
Typ
Max
Units
Notes
Input Leakage Current for each pin
except TCK, TDI, TRST# and TMS
ILI1
± 1
µA
0 ≤ VIN ≤ VCC
Input Leakage Current for TCK, TDI,
TRST# and TMS
80960 JA/JF/JD
ILI2
-140
-250
-250
-300
µA
µA
kΩ
VIN = 0.45V (1)
80960 JS/JC/JT
ILO
Output Leakage Current
± 1
30
0.4 ≤ VOUT ≤ VCC
Internal Pull-UP Resistance for
ONCE#, TMS, TDI and TRST#
Rpu
20
44
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 30. 80960Jx I Characteristics (Sheet 2 of 4)
CC
Symbol
Parameter
80960JT-100
Typ
Max
Units
Notes
505
80960JC-66
80960JC-50
80960JC-40
80960JC-33
360
280
230
195
80960JS-33
80960JS-25
80960JS-16
240
185
120
ICC Active
(Power Supply)
mA
(2,3)
80960JD-66
80960JD-50
80960JD-40
80960JD-33
580
447
367
310
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
320
241
154
80960JT-100
480
80960JC-66
80960JC-50
80960JC-40
80960JC-33
345
270
221
185
80960JS-33
80960JS-25
80960JS-16
221
170
113
ICC Active
(Thermal)
mA
(2,4)
80960JD-66
80960JD-50
80960JD-40
80960JD-33
510
390
320
260
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
271
215
152
Datasheet
45
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 30. 80960Jx I Characteristics (Sheet 3 of 4)
CC
Symbol
Parameter
Typ
Max
Units
Notes
Reset mode
80960JT-100
380
80960JC-66
80960JC-50
80960JC-40
80960JC-33
275
210
170
140
80960JS-33
80960JS-25
80960JS-16
240
182
120
80960JD-66
80960JD-50
80960JD-40
80960JD-33
475
425
345
300
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
250
200
150
ICC Test
(Power modes)
Halt mode
mA
(5)
80960JT-100
52
80960JC-66
80960JC-50
80960JC-40
80960JC-33
45
34
27
23
80960JS-33
80960JS-25
80960JS-16
35
30
20
80960JD-66
80960JD-50
80960JD-40
80960JD-33
50
40
34
29
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
31
26
21
ONCE mode
10
46
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 30. 80960Jx I Characteristics (Sheet 4 of 4)
CC
Symbol
Parameter
80960JT-100
Typ
Max
Units
Notes
80960JC-66
80960JC-50
80960JC-40
80960JC-33
80960JS-33
80960JS-25
80960JS-16
ICC5 Current on the
VCC5 Pin
200
µA
(6)
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
NOTES:
1. These pins have internal pullup devices. Typical leakage current is not tested.
2. Measured with device operating and outputs loaded to the test condition in Figure 10, “AC Test Load” on
page 51.
3. ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested.
4. ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured with
VCC =3.3 V and temperature = 25°C. This parameter is characterized but not tested.
5. ICC Test (Power modes) refers to the ICC values that are tested when the 80960JD is in Reset mode, Halt
mode or ONCE mode with VCC = 3.45 V.
6. ICC5 is tested at VCC = 3.3 V, VCC5 = 5.25 V.
Datasheet
47
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.7
AC Specifications
The 80960Jx AC timings are based upon device characterization.
Table 31. 80960Jx AC Characteristics (Sheet 1 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
INPUT CLOCK TIMINGS
CLKIN Frequency
80960JT-100
15
33.3
80960JC-66
80960JC-50
80960JC-40
80960JC-33
15
15
15
15
33.3
25
20
16.67
80960JS-33
80960JS-25
80960JS-16
15
15
15
33.3
25
16.67
TF
MHz
80960JD-66
80960JD-50
80960JD-40
80960JD-33
12
12
12
12
33.3
25
20
16.67
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
12
12
12
33.3
25
16
CLKIN Period
80960JT-100
30
66.7
80960JC-66
80960JC-50
80960JC-40
80960JC-33
30
40
50
60
66.7
66.7
66.7
66.7
80960JS-33
80960JS-25
80960JS-16
30
40
60
66.7
66.7
66.7
TC
ns
80960JD-66
80960JD-50
80960JD-40
80960JD-33
30
40
50
60
83.3
83.3
83.3
83.3
80960JA/JF-33
80960JA/JF-25
80960JA/JF-16
30
40
62.5
83.3
83.3
83.3
TCS
TCH
CLKIN Period Stability
± 250
ps
ns
(1, 2)
Measured at 1.5 V
(1)
CLKIN High Time
8
8
Measured at 1.5 V
(1)
TCL
CLKIN Low Time
ns
TCR
TCF
CLKIN Rise Time
CLKIN Fall Time
4
4
ns
ns
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
NOTE: See Table 32 on page 50 for note definitions for this table.
48
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 31. 80960Jx AC Characteristics (Sheet 2 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
SYNCHRONOUS OUTPUT TIMINGS
Output Valid Delay, Except ALE/ALE#
Inactive and DT/R# for 3.3 V input signals
2.5
2.5
13.5
TOV1
ns
(2) (11)
Same as above, but for 5.5 V input signals
16.5
Output Valid Delay, DT/R#
80960JS/JC/JT
80960JD
0.5TC + 7 0.5TC + 9
0.5TC + 7 0.5TC + 9
0.5TC + 4 0.5TC + 18
TOV2
ns
ns
80960JA/JF
TOF
Output Float Delay
2.5
SYNCHRONOUS INPUT TIMINGS
Input Setup to CLKIN — AD[31:0], NMI#,
13.5
(4)
(5)
(5)
(6)
XINT[7:0]#
80960JS/JC/JT
TIS1
TIH1
TIS2
6
6
9
ns
ns
ns
80960JD
80960JA/JF
Input Hold from CLKIN — AD[31:0], NMI#,
XINT[7:0]#
80960JS/JC/JT
80960JD
2.0
1.5
1.0
80960JA/JF
Input Setup to CLKIN — RDYRCV# and
HOLD
80960JS/JC/JT
80960JD
6.5
6.5
80960JA/JF
10.0
Input Hold from CLKIN — RDYRCV# and
HOLD
TIH2
1
ns
ns
(6)
(7)
Input Setup to CLKIN — RESET#
80960JS/JC/JT
7
7
8
TIS3
80960JD
80960JA/JF
Input Hold from CLKIN — RESET#
80960JS/JC/JT
2
2
1
TIH3
ns
ns
(7)
(8)
80960JD
80960JA/JF
Input Setup to RESET# — ONCE#, STEST
80960JS/JC/JT
80960JD
80960JA/JF
7
7
8
TIS4
Input Hold from RESET# — ONCE#,
STEST
2
2
1
TIH4
80960JS/JC/JT
80960JD
80960JA/JF
ns
(8)
NOTE: See Table 32 on page 50 for note definitions for this table.
Datasheet
49
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 31. 80960Jx AC Characteristics (Sheet 3 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
RELATIVE OUTPUT TIMINGS
Address Valid to ALE/ALE# Inactive
For 3.3 V Data Input Signals
For 5.0 V Data Input Signals
TLX
0.5TC - 5
0.5TC - 8
ns
ns
(9)
TLXL
TLXA
TDXD
ALE/ALE# Width
Address Hold from ALE/ALE# Inactive
DT/R# Valid to DEN# Active
0.5TC - 7
Equal Loading (9)
BOUNDARY SCAN TEST SIGNAL TIMINGS
TBSF
TCK Frequency
TCK High Time
0.5TF
MHz
ns
Measured at 1.5 V
(1)
TBSCH
15
15
Measured at 1.5 V
(1)
TBSCL
TCK Low Time
ns
TBSCR
TBSCF
TBSIS1
TBSIH1
TCK Rise Time
TCK Fall Time
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
Input Setup to TCK — TDI, TMS
Input Hold from TCK — TDI, TMS
4
6
3
3
3
3
4
TBSOV1 TDO Valid Delay
30
30
30
30
(1,10)
(1,10)
(1,10)
(1,10)
TBSOF1 TDO Float Delay
TBSOV2 All Outputs (Non-Test) Valid Delay
TBSOF2 All Outputs (Non-Test) Float Delay
TBSIS2
Input Setup to TCK — All Inputs (Non-Test)
Input Hold from TCK — All Inputs (Non-
Test)
TBSIH2
6
ns
NOTE: See Table 32 on page 50 for note definitions for this table.
Table 32. Note Definitions for Table 31, 80960Jx AC Characteristics
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is
OL
designed to be no longer than the valid delay.
5. AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation.
NMI# and XINT[7:0]# may be synchronous or asynchronous. Meeting setup and hold time guarantees
recognition at a particular clock edge. For asynchronous operation, NMI# and XINT[7:0]# must be
asserted for a minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at
a particular clock edge.
8. ONCE# and STEST# must be stable at the rising edge of RESET# for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
11.Worst-case TOV condition occurs on I/O pins when pins transition from a floating high input to driving a
low output state. The Address/Data Bus pins encounter this condition between the last access of a read,
and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at
50 pF loads.
50
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.7.1
AC Test Conditions and Derating Curves
The AC Specifications in Section 4.7, “AC Specifications” are tested with the 50 pF load indicated
in Figure 10.
Figure 10. AC Test Load
Output Pin
CL = 50 pF for all signals
CL
Refer to the following sections for the specified derating curves:
• Section 4.7.1.1, “Ouput Delay or Hold vs. Load Capacitance” on page 51
• Section 4.7.1.2, “T vs. AD Bus Load Capacitance” on page 53
LX
4.7.1.1
Ouput Delay or Hold vs. Load Capacitance
Figure 11. Output Delay or Hold vs. Load Capacitance – 80960JS/JC/JT (3.3 V Signals)
AC Timings vs. Load Capacitance
(3.3 V Signals)
nom + 10
nom + 8
nom + 6
nom + 4
nom + 2
nom + 0
50
100
150
AD Bus Capacitive Load (pF)
Datasheet
51
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 12. Output Delay or Hold vs. Load Capacitance – 80960JS/JC/JT (5 V Signals)
AC Timings vs. Load Capacitance
(5 V Signals)
nom + 16
nom + 14
nom + 12
nom + 10
nom + 8
nom + 6
nom + 4
nom + 2
nom + 0
50
100
150
AD Bus Capacitive Load (pF)
Figure 13. Output Delay or Hold vs. Load Capacitance – 80960JA/JF/JD
AC Timings vs. Load Capacitance
nom+ 8
nom+ 7
nom+ 6
nom+ 5
nom+ 4
nom+ 3
nom+ 2
nom+ 1
nom+ 0
50
100
150
AD Bus Capacitive Load (pF)
Rise and Fall times are identical.
52
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.7.1.2
TLX vs. AD Bus Load Capacitance
Figure 14. T vs. AD Bus Load Capacitance – 80960JS/JC/JT (3.3 V Signals)
LX
AC Timings vs. Load Capacitance
(3.3 V Signals)
nom - 10
nom - 8
nom - 6
nom - 4
nom - 2
nom - 0
50
100
150
AD Bus Capacitive Load (pF)
Note: The T Derating curve applies only when an imbalance in the capacitive load occurs between the
LX
AD bus and ALE. The T derating is based on a 50 pF load on ALE. The derating applies to ALE
LX
and ALE#.
Figure 15. T vs. AD Bus Load Capacitance – 80960JS/JC/JT (5 V Signals)
LX
AC Timings vs. Load Capacitance
(5 V Signals)
nom - 20
nom - 15
nom - 10
nom - 5
nom - 0
50
100
150
AD Bus Capacitive Load (pF)
Note: The T Derating curve applies only when an imbalance in the capacitive load occurs between the
LX
AD bus and ALE. The T derating is based on a 50 pF load on ALE. The derating applies to ALE
LX
and ALE#.
Datasheet
53
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 16. T vs. AD Bus Load Capacitance – 80960JA/JF/JD
LX
AC Timings vs. Load Capacitance
nom- 8
nom- 7
nom- 6
nom- 5
nom- 4
nom- 3
nom- 2
nom- 1
nom- 0
50
100
150
AD Bus Capacitive Load (pF)
Rise and Fall times are identical.
Note: The T Derating curve applies only when an imbalance in the capacitive load occurs between the
LX
AD bus and ALE. The T derating is based on a 50 pF load on ALE. The derating applies to ALE
LX
and ALE#.
54
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.7.1.3
ICC Active vs. Frequency
Figure 17. I Active (Power Supply) vs. Frequency – 80960JA/JF
CC
Icc Active (Power Supply) vs Frequency
350
300
250
200
150
100
50
0
12
15
18
21
24
27
30
33
CLKIN Frequency MHz
Figure 18. 80960JA/JF I Active (Thermal) vs. Frequency
CC
Icc Active (Thermal) vs. Frequency
300
250
200
150
100
50
0
12
15
18
21
24
27
30
33
CLKIN Frequency MHz
Datasheet
55
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 19. 80960JD I Active (Power Supply) vs. Frequency
CC
Icc Active (Power Supply) vs. Frequency
600
500
400
300
200
100
0
12
15
18
21
24
27
30
33
CLKIN Frequency (MHz)
Figure 20. 80960JD I Active (Thermal) vs. Frequency
CC
Icc Active (Thermal) vs. Frequency
600
500
400
300
200
100
0
12
15
18
21
24
27
30
33
CLKIN Frequency (MHz)
56
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 21. 80960JC I Active (Power Supply) vs. Frequency
CC
Icc Active (Power Supply) vs Frequency
80960 JC
400
350
300
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKIN Frequency MHz
Figure 22. 80960JC I Active (Thermal) vs. Frequency
CC
Icc Active (Thermal) vs Frequency
80960 JC
400
350
300
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKIN Frequency MHz
Datasheet
57
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 23. 80960JS I Active (Power Supply) vs. Frequency
CC
Icc Active (Power Supply) vs Frequency
80960 JS
300
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKIN Frequency MHz
Figure 24. 80960JS I Active (Thermal) vs. Frequency
CC
Icc Active (Thermal) vs. Frequency
80960 JS
250
200
150
100
50
0
15
18
21
24
27
30
33
CLKIN Frequency MHz
58
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4.7.2
AC Timing Waveforms
Figure 25. CLKIN Waveform
T
T
CR
CF
2.0V
1.5V
0.8V
T
CH
T
CL
T
C
Figure 26. T
Output Delay Waveform
OV1
1.5V
1.5V
CLKIN
T
OV1
AD[31:0],
ALE (active),
ALE# (active),
ADS#, A[3:2],
1.5V
BE[3:0]#,
WIDTH/HLTD[1:0],
D/C#, W/R#, DEN#,
BLAST#, LOCK#,
HOLDA, BSTAT, FAIL#
Datasheet
59
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 27. T Output Float Waveform
OF
1.5V
OF
1.5V
CLKIN
T
AD[31:0],
ALE, ALE#
ADS#, A[3:2],
BE[3:0]#,
WIDTH/HLTD[1:0],
D/C#, W/R#, DT/R#,
DEN#, BLAST#, LOCK#
Figure 28. TIS1 and TIH1 Input Setup and Hold Waveform
1.5V
1.5V
1.5V
CLKIN
T
IH1
T
IS1
AD[31:0]
NMI#
Valid
1.5V
XINT[7:0]#
Figure 29. TIS2 and TIH2 Input Setup and Hold Waveform
1.5V
1.5V
1.5V
CLKIN
T
IH2
T
IS2
HOLD,
1.5V
Valid
1.5V
RDYRCV#
60
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 30. TIS3 and TIH3 Input Setup and Hold Waveform
1.5V
1.5V
CLKIN
T
T
IS3
IH3
RESET#
Figure 31. TIS4 and TIH4 Input Setup and Hold Waveform
RESET#
T
IH4
T
IS4
ONCE#,
Valid
STEST
Datasheet
61
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 32. TLX, TLXL and TLXA Relative Timings Waveform
Ta
Tw/Td
1.5V
1.5V
1.5V
CLKIN
TLXL
ALE
1.5V
Valid
1.5V
1.5V
ALE#
TLX
TLXA
1.5V
AD[31:0]
Valid
Figure 33. DT/R# and DEN# Timings Waveform
Ta
Tw/Td
CLKIN
1.5V
1.5V
1.5V
TOV2
Valid
DT/R#
TDXD
DEN#
TOV1
62
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 34. TCK Waveform
T
T
BSCR
BSCF
2.0V
1.5V
0.8V
T
BSCH
T
BSCL
Figure 35. TBSIS1 and TBSIH1 Input Setup and Hold Waveforms
1.5V
1.5V
1.5V
TCK
T
T
BSIH1
BSIS1
TMS
TDI
1.5V
Valid
1.5V
Figure 36. TBSOV1 and TBSOF1 Output Delay and Output Float Waveform
TCK
1.5V
1.5V
1.5V
T
T
BSOV1
BSOF1
Valid
1.5V
TDO
Datasheet
63
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 37. TBSOV2 and TBSOF2 Output Delay and Output Float Waveform
TCK
1.5V
1.5V
1.5V
T
T
BSOF2
BSOV2
Non-Test
Outputs
Valid
1.5V
Figure 38. TBSIS2 and TBSIH2 Input Setup and Hold Waveform
TCK
1.5V
1.5V
1.5V
TBSIS2 TBSIH2
Non-Test
Inputs
1.5V
Valid
1.5V
64
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
5.0
Bus Functional Waveforms
Figure 39 through Figure 44 illustrate typical 80960Jx bus transactions. Figure 45 depicts the bus
arbitration sequence. Figure 46 illustrates the processor reset sequence from the time power is
applied to the device. Figure 47 illustrates the processor reset sequence when the processor is in
operation. Figure 48 illustrates the processor ONCE# sequence from the time power is applied to
the device. Figure 50 and Figure 51 also show accesses on 32-bit buses. Table 35 through Table 37
summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to
data alignment.
Figure 39. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
Ta
Td
Tr
Ti
Ti
Ta
Td
Tr
Ti
Ti
CLKIN
D
ADDR
ADDR
Invalid
DATA Out
AD31:0
In
ALE
ADS#
A3:2
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF030A
Datasheet
65
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 40. Burst Read and Write Transactions Without Wait States, 32-Bit Bus
TA
TD
TD
TR
TA
TD
TD
TD TD
TR
CLKIN
DATA
Out
D
DATA
Out
D
In
DATA DATA
Out
ADDR
ADDR
AD31:0
In
Out
ALE
ADS#
00 or 10
01 or 11
00
01
10
11
A3:2
BE3:0#
1 0
1 0
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
66
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 41. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
TA
TW
TW
TD
TW
TD
TW
TD
TW
TD
TR
CLKIN
AD31:0
ALE
DATA
Out
DATA
Out
DATA
Out
DATA
Out
ADDR
ADS#
A3:2
0 0
0 1
1 0
1 1
BE3:0#
WIDTH1:0
D/C#
1 0
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF032A
Datasheet
67
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 42. Burst Read and Write Transactions Without Wait States, 8-Bit Bus
TA
TD
TD
TR
TA
TD
TD
TD
TD
TR
CLKIN
DATA
Out
D
In
DATA DATA
DATA
D
In
ADDR
ADDR
AD31:0
Out
Out Out
ALE
ADS#
A3:2
00,01,10 or 11
00,01,10 or 11
01 or
BE1#/A1
BE0#/A0
00
01
10
11
00 or 10
11
WIDTH1:0
D/C#
00
00
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
F_JF033A
68
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 43. Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on
Read, 16-Bit Bus
TW TD
TD
TR
TR
TA
TW
TD TD
TR
TA
CLKIN
AD31:0
ALE
D
D
DATA
DATA
Out
ADDR
ADDR
In
In
Out
ADS#
00,01,10, or 11
00,01,10, or 11
A3:2
0
0
1
BE1#/A1
1
BE3#/BHE
BE0#/BLE
01
01
WIDTH1:0
D/C#
W/R#
BLAST#
DT/R#
DEN#
F_JF034A
RDYRCV#
Datasheet
69
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 44. Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian
TA
TD
TR
TA
TD
TR
TA
TD
TR
TA
TD
TR
CLKIN
AD31:0
ALE
D
In
D
In
D
In
D
In
A
A
A
A
ADS#
A3:2
00
00
01
10
BE3:0#
WIDTH1:0
D/C#
0 0 0 0
1 1 1 0
0 0 1 1
1 1 0 1
1 0
Valid
W/R#
BLAST#
DT/R#
DEN#
RDYRCV#
70
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 45. HOLD/HOLDA Waveform For Bus Arbitration
TI or TR
TH
TH
TI or TA
CLKIN
Outputs:
AD31:0,
ALE, ALE#,
ADS#, A3:2,
BE3:0#,
Valid
Valid
WIDTH/HLTD1:0,
D/C#, W/R#,
DT/R#, DEN#,
BLAST#, LOCK#
HOLD
HOLDA
(Note)
NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the
same edge in which it recognizes HOLD if the last state was Ti or the last Tr of a bus transaction. Similarly,
the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
Datasheet
71
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 46. Cold Reset Waveform
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~ ~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
72
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 47. Warm Reset Waveform
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~
~
~
~
~
~
~
~
~
~
Datasheet
73
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 48. Entering the ONCE State
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~ ~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~ ~
~ ~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
74
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
5.1
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when
RESET# is asserted. When the processor needs to initiate a bus access, it enters the Ta state to
transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV# input signal indicates completion of each transfer. When data is
not ready, the processor can wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case
of a burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next
data word. The processor asserts the BLAST# signal during the last Tw/Td states of an access.
Once all data words transfer in a burst access (up to four), the bus enters the Tr state to allow
devices on the bus to recover.
The processor remains in the Tr state until RDYRCV# is deasserted. When the recovery state
completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the
bus enters the Ta state to transmit the new address.
Datasheet
75
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 49. Bus States with Arbitration
(READY AND BURST)
OR NOT READY
Tw/Td
RECOVERED AND
READY AND NO BURST
Ta
REQUEST
PENDING AND (NO
HOLD OR LOCKED)
REQUEST PENDING
AND (NO HOLD OR
LOCKED)
NOT
RECOVERED
Tr
RECOVERED AND
NO REQUEST AND
(NO HOLD OR
LOCKED)
REQUEST
PENDING AND
NO HOLD
NO REQUEST
AND (NO HOLD
OR LOCKED)
Ti
ONCE & RESET
DEASSERTION
RECOVERED AND
HOLD AND NOT
LOCKED
NO REQUEST
AND NO HOLD
Th
RESET
To
HOLD AND
NOT LOCKED
HOLD
READY — RDYRCV# ASSERTED
Ti — IDLE STATE
Ta — ADDRESS STATE
NOT READY — RDYRCV# NOT ASSERTED
BURST — BLAST# NOT ASSERTED
NO BURST — BLAST# ASSERTED
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
RECOVERED — RDYRCV# NOT ASSERTED
NOT RECOVERED — RDYRCV# ASSERTED
REQUEST PENDING — NEW TRANSACTION
NOREQUEST — NO NEW TRANSACTION
HOLD — HOLD REQUEST ASSERTED
To — ONCE STATE
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RESET — RESET# ASSERTED
ONCE — ONCE# ASSERTED
5.2
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and
HIGHZ pins.
Table 33 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
76
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 33. Boundary-Scan Register Bit Order
Input/
Output
Input/
Output
Input/
Output
Bit
Signal
Bit
Signal
Bit
Signal
RDYRCV#
(TDI)
0
I
24
DEN#
O
48
AD17
I/O
1
2
HOLD
I
I
25
26
HOLDA
ALE
O
O
49
50
AD16
AD15
I/O
I/O
XINT0#
LOCK#/
ONCE# cell
3
XINT1#
I
27
Enable cell1
51
AD14
I/O
LOCK#/
ONCE#
4
5
6
XINT2#
XINT3#
XINT4#
I
I
I
28
29
30
I/O
O
52
53
54
AD13
AD12
I/O
I/O
BSTAT
BE0#
Enable
cell1
O
AD cells
7
XINT5#
XINT6#
XINT7#
NMI#
I
31
32
33
34
35
36
37
38
39
40
41
42
43
44
BE1#
BE2#
BE3#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
O
55
56
57
58
59
60
61
62
63
64
65
66
67
68
AD11
AD10
AD9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
8
I
O
9
I
O
10
11
12
13
14
15
16
17
18
19
20
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD8
FAIL#
I
AD7
ALE#
O
AD6
WIDTH/HLTD1
WIDTH/HLTD0
A2
O
AD5
O
AD4
O
AD3
A3
O
AD2
CONTROL1
CONTROL2
BLAST#
D/C#
Enable cell1
AD1
Enable cell1
AD0
O
O
CLKIN
RESET#
I
STEST
(TDO)
21
ADS#
O
45
AD20
I/O
69
I
22
W/R#
O
O
46
47
AD19
AD18
I/O
I/O
23
DT/R#
NOTE:
1. Enable cells are active low.
Datasheet
77
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 34. Natural Boundaries for Load and Store Accesses
Data Width
Natural Boundary (Bytes)
Byte
1
2
Short Word
Word
4
Double Word
Triple Word
Quad Word
8
16
16
Table 35. Summary of Byte Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit
Bus (WIDTH1:0=01)
Accesses on 32 Bit
Bus (WIDTH1:0=10)
+0 (aligned)
•
byte access
•
byte access
•
byte access
Table 36. Summary of Short Word Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit
Bus (WIDTH1:0=01)
Accesses on 32 Bit
Bus (WIDTH1:0=10)
+0 (aligned)
+1
•
•
burst of 2 bytes
2 byte accesses
•
•
short-word access
2 byte accesses
•
•
short-word access
2 byte accesses
78
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Table 37. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
Address Offset
from Natural
Boundary in Bytes
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit Bus
(WIDTH1:0=01)
Accesses on 32 Bit
Bus (WIDTH1:0=10)
•
•
•
case n=1:
burst of 2 short words
case n=2:
burst of 4 short words
+0 (aligned)
(n =1, 2, 3, 4)
•
n burst(s) of 4 bytes
•
burst of n word(s)
case n=3:
burst of 4 short words
burst of 2 short words
•
case n=4:
2 bursts of 4 short words
•
•
•
byte access
•
•
•
byte access
•
•
•
•
byte access
+1 (n =1, 2, 3, 4)
+5 (n = 2, 3, 4)
+9 (n = 3, 4)
short-word access
short-word access
burst of 2 bytes
n-1 burst(s) of 4 bytes
byte access
n-1 burst(s) of 2 short
words
n-1 word
access(es)
+13 (n = 3, 4)
•
byte access
•
byte access
•
•
short-word access
•
•
short-word access
+2 (n =1, 2, 3, 4)
+6 (n = 2, 3, 4)
+10 (n = 3, 4)
+14 (n = 3, 4)
•
•
•
burst of 2 bytes
n-1 burst(s) of 2 short
words
n-1 word
access(es)
n-1 burst(s) of 4 bytes
burst of 2 bytes
•
short-word access
byte access
•
short-word access
byte access
•
•
•
•
•
•
•
•
byte access
+3 (n =1, 2, 3, 4)
+7 (n = 2, 3, 4)
+11 (n = 3, 4)
+15 (n = 3, 4)
n-1 burst(s) of 2 short
words
n-1 word
access(es)
n-1 burst(s) of 4 bytes
burst of 2 bytes
byte access
•
•
short-word access
byte access
•
•
short-word access
byte access
+4 (n = 2, 3, 4)
+8 (n = 3, 4)
•
n burst(s) of 4 bytes
•
n burst(s) of 2 short words
•
n word access(es)
+12 (n = 3, 4)
Datasheet
79
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 50. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
0
0
4
8
12
3
16
4
20
5
24
6
Byte Offset
Word Offset
1
2
Short Access (Aligned)
Byte, Byte Accesses
Short-Word
Load/Store
Short Access (Aligned)
Byte, Byte Accesses
Word Access (Aligned)
Byte, Short, Byte, Accesses
Short, Short Accesses
Word
Load/Store
Byte, Short, Byte Accesses
One Double-Word Burst (Aligned)
Byte, Short, Word, Byte Accesses
Short, Word, Short Accesses
Double-Word
Load/Store
Byte, Word, Short, Byte Accesses
Word, Word Accesses
One Double-Word
Burst (Aligned)
80
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Figure 51. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
0
4
8
12
16
20
24
Byte Offset
Word Offset
0
1
2
3
4
5
6
One Three-Word
Burst (Aligned)
Byte, Short, Word,
Word, Byte Accesses
Short, Word, Word,
Short Accesses
Triple-Word
Load/Store
Byte, Word, Word,
Short, Byte Accesses
Word, Word,
Word Accesses
Word, Word,
Word Accesses
Word,
Word,
Word
Accesses
One Four-Word
Burst (Aligned)
Byte, Short, Word, Word,
Word, Byte Accesses
Short, Word, Word, Word,
Short Accesses
Quad-Word
Load/Store
Byte, Word, Word, Word,
Short, Byte Accesses
Word, Word, Word,
Word Accesses
Word,
Word,
Word,
Word,
Accesses
Datasheet
81
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
6.0
Device Identification
80960Jx processors may be identified electrically, according to device type and stepping (see
Figure 52, and Table 39 through Table 44). Table 38 identifies the device type and stepping for all
5 V, 80960Jx processors. Figure 52, and Table 39 through Table 44 identify all 3.3V-5V-tolerant
80960Jx processors. The device ID was enhanced to differentiate between 3.3V and 5V supply
voltages, and between non-clock-doubled and clock-doubled cores when stepping from the A2
stepping to the C0 stepping. The 32-bit identifier is accessible in several ways:
• Upon reset, the identifier is placed into the g0 register.
• The identifier may be accessed from supervisor mode at any time by reading the DEVICEID
register at address FF008710H.
• The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the
IDCODE instruction.
• The device and stepping letter is also printed on the top side of the product package.
Table 38. 80960Jx Device Type and Stepping Reference
Device and
Stepping
Version
Number
Complete ID
(Hex)
Part Number
Manufacturer
X
80960JT A0, A1
80960JC A1
80960JS A1
80960JD C0
80960JF C0
80960JA C0
0000
0011
0011
0011
0011
0011
0000 1000 0010 1011
0000 1000 0011 0011
0000 1000 0010 0011
0000 1000 0011 0000
0000 1000 0010 0000
0000 1000 0010 0001
0000 0001 001
0000 0001 001
0000 0001 001
0000 0001 001
0000 0001 001
0000 0001 001
1
1
1
1
1
1
0082B013
30833013
30823013
30830013
30820013
30821013
82
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
6.1
80960JS/JC/JT Device Identification Register
Figure 52. 80960JS/JC/JT Device Identification Register Fields
Part Number
Product
VCC
Type
Version
Gen
Model
Manufacturer ID
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0 1
0
0
0
0
0
0
0
1
0
0
1
1
28
24
20
16
12
8
4
0
Table 39. 80960JS/JC/JT Device ID Register Field Definitions
Field
Version
Value
See Table 40
Definition
Indicates major stepping changes.
Indicates that a device is 3.3 V.
Designates type of product.
VCC
0 = 3.3 V device
Product Type
000 100
(Indicates i960 CPU)
Generation Type 0001 = J-series
Indicates the generation (or series) the product belongs
to.
Model
D DPCC
Indicates member within a series and specific model
information.
D = Clock Multiplier
(01) Clock-Tripled
(P) Product Derivative
(0) Jx
C = Cache Size
(11) 16K I-cache, 4K D-
cache
Manufacturer ID 000 0000 1001
(Indicates Intel)
Manufacturer ID assigned by IEEE.
Table 40. 80960JS/JC/JT Device ID Model Types
Device
Version VCC
Product
Gen.
Model
Manufacturer ID
‘1’
80960JT A0, A1
80960JC A1
80960JS A1
0000
0000
0000
0
0
0
000100
000100
000100
0001
0001
0001
01011
10011
00011
00000001001
00000001001
00000001001
1
1
1
Datasheet
83
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
6.2
80960JD Device Identification Register
Figure 53. 80960JD Device Identification Register Fields
Part Number
Product
Type
VCC
Version
Gen
Model
Manufacturer ID
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0 0 1
0
0
0
0
0
0
0
1
0
0
1
1
28
24
20
16
12
8
4
0
Table 41. 80960JD Device ID Field Definitions
Field
Version
Value
Definition
See Table 38
Indicates major stepping changes.
Indicates that a device is 3.3 V.
0 = 3.3 V device
1 = 5V device
VCC
00 0100
(Indicates i960 CPU)
Product Type
Designates type of product.
Generation Type 0001 = J-series
Indicates the generation (or series) the product belongs to.
D000C
D = Clock Doubled
(0) Not Clock-Doubled
(1) Clock Doubled
Model
C = Cache Size
(0) 4K I-cache, 2K D-
cache
Indicates member within a series and specific model information.
(1) 2K I-cache, 1K D-
cache
000 0000 1001
(Indicates Intel)
Manufacturer ID
Manufacturer ID assigned by IEEE.
Table 42. 80960JD Device ID Model Types
Device
Version VCC
0011
Product
Gen.
Model
Manufacturer ID
‘1’
80960JD C0
0
000100
0001
10000
00000001001
1
84
Datasheet
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
6.3
80960JA/JF Device Identification Register
Figure 54. 80960JA/JF Device Identification Register Fields
Part Number
Product
VCC
Type
Version
Gen
Model
Manufacturer ID
1
0
0
0
0
1
0
0
0
0
0 1
0
0
0
0
0
0
0
1
0
0
1
1
28
24
20
16
12
8
4
0
Table 43. 80960JA/JF Device ID Field Definitions
Field
Version
Value
Definition
See Table 44
Indicates major stepping changes.
Indicates that a device is 3.3 V.
VCC
0 = 3.3 V device
1 = 5V device
Product Type
00 0100
Designates type of product.
(Indicates i960 CPU)
Generation Type 0001 = J-series
Indicates the generation (or series) to which the
product belongs.
Model
0000C
C = Cache Size
Indicates member within a series and specific
model information.
0 = 4K I-cache, 2K D-cache
1 = 2K I-cache, 1K D-cache
Manufacturer ID 000 0000 1001
(Indicates Intel)
Manufacturer ID assigned by IEEE.
Table 44. 80960JA/JF Device ID Model Types
Device
Version VCC
Product
Gen.
Model
Manufacturer ID
‘1’
80960JA C0
80960JF C0
0011
0011
0
0
000100
000100
0001
0001
00001
00000
00000001001
00000001001
1
1
Datasheet
85
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
7.0
Revision History
Table 45. Datasheet Revision History
Revision
Date
Description
Merged the 80960JS/JC datasheet information into this datasheet (previously named
80960JA/JF/JD/JT 3.3 V Embedded 32-Bit Microprocessor datasheet).
Updated ICC values for the 80960JS/JC/JT processors.
Increased TIH1 specification for the 80960JS/JC/JT processors.
Updated MPBGA thermal specifications.
003
06/99
Corrected orientation of MPBGA package diagrams (Figures 6 and 7).
002
001
12/98
03/98
Added Figures 11, 12, 14, and 15 to distinguish 80960JT 3.3-V and 5-V signal
derating curves from the 80960JA/JF/JD derating curves.
This datasheet supersedes revisions to the following 80960Jx datasheets: #273109
(JT), #272971-002 (JD), and #276146-001 (JA/JF). In addition to combining the
documents into one, the following content was changed:
Figure 1, “80960Jx Microprocessor Package Options” on page 7: Added MPBGA
package to diagram.
Section 3.1.4, “80960Jx 196-Ball MPBGA Pinout” on page 30: Added new Figures 6
and 7, Tables 10, 11 and 13.
Figure 16, “TLX vs. AD Bus Load Capacitance – 80960JA/JF/JD” on page 54: Added
with the note that follows the figure.
86
Datasheet
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