A80960JD-66 [INTEL]

3.3 V EMBEDDED 32-BIT MICROPROCESSOR; 3.3 V嵌入式32位微处理器


型号：	A80960JD-66
厂家：	INTEL
描述：	3.3 V EMBEDDED 32-BIT MICROPROCESSOR 3.3 V嵌入式32位微处理器微处理器
文件：	总59页 (文件大小：736K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRODUCT PREVIEW

80960JD

3.3 V EMBEDDED 32-BIT MICROPROCESSOR

• 3.3 V, 5 V Tolerant, Version of the 80960JD Processor

■ Pin/Code Compatible with all 80960Jx

■ 3.3 V Supply Voltage

— 5 V Tolerant Inputs

Processors

— TTL Compatible Outputs

■ High-Performance Embedded Architecture

— One Instruction/Clock Execution

— Core Clock Rate is 2x the Bus Clock

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers (8 sets)

— Nine Addressing Modes

■ High Bandwidth Burst Bus

— 32-Bit Multiplexed Address/Data

— Programmable Memory Configuration

— Selectable 8-, 16-, 32-Bit Bus Widths

— Supports Unaligned Accesses

— Big or Little Endian Byte Ordering

— User/Supervisor Protection Model

■ High-Speed Interrupt Controller

— 31 Programmable Priorities

■ Two-Way Set Associative Instruction Cache

— 80960JD - 4 Kbyte

— Eight Maskable Pins plus NMI

— Up to 240 Vectors in Expanded Mode

— Programmable Cache Locking

Mechanism

■ Two On-Chip Timers

■ Direct Mapped Data Cache

— 80960JD - 2 Kbyte

— Independent 32-Bit Counting

— Clock Prescaling by 1, 2, 4 or 8

— lnternal Interrupt Sources

— Write Through Operation

■ Halt Mode for Low Power

■ On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority

Interrupts

■ IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

■ Packages

— 132-Lead Pin Grid Array (PGA)

— 132-Lead Plastic Quad Flat Pack (PQFP)

■ On-Chip Data RAM

— 1 Kbyte Critical Variable Storage

— Single-Cycle Access

132

PIN 1

A80960JD

XXXXXXXXC0

i960

19xx

NG80960JD

XXXXXXXXC0S

19xx

Figure 1. 80960JD Microprocessor

November 1996

Order Number: 272971-001

Information in this document is provided in connection with Intel products. No license, express or implied, by

estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in

Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel

disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or

warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright

or other intellectual property right. Intel products are not intended for use in medical, life saving, or life

sustaining applications.

Intel retains the right to make changes to specifications and product descriptions at any time, without notice.

*Third-party brands and names are the property of their respective owners.

Copies of documents which have an ordering number and are referenced in this document, or other Intel

literature, may be obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect IL 60056-764

or call 1-800-548-4725

©INTEL CORPORATION, 1996

Contents

80960JD

3.3 V EMBEDDED 32-BIT MICROPROCESSOR

1.0 PURPOSE .................................................................................................................................................. 1

2.0 80960JD OVERVIEW ................................................................................................................................ 1

2.1 80960 Processor Core ........................................................................................................................ 2

2.2 Burst Bus ............................................................................................................................................ 2

2.3 Timer Unit ........................................................................................................................................... 3

2.4 Priority Interrupt Controller ................................................................................................................. 3

2.5 Instruction Set Summary .................................................................................................................... 3

2.6 Faults and Debugging ........................................................................................................................ 3

2.7 Low Power Operation ......................................................................................................................... 3

2.8 Test Features ..................................................................................................................................... 4

2.9 Memory-Mapped Control Registers .................................................................................................... 4

2.10 Data Types and Memory Addressing Modes ................................................................................... 4

3.0 PACKAGE INFORMATION ....................................................................................................................... 6

3.1 Pin Descriptions .................................................................................................................................. 6

3.1.1 Functional Pin Definitions ........................................................................................................ 6

3.1.2 80960Jx 132-Lead PGA Pinout ............................................................................................. 12

3.1.3 80960Jx PQFP Pinout ........................................................................................................... 16

3.2 Package Thermal Specifications ...................................................................................................... 19

3.3 Thermal Management Accessories .................................................................................................. 21

4.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 22

4.1 Absolute Maximum Ratings .............................................................................................................. 22

4.2 Operating Conditions ........................................................................................................................ 22

4.3 Connection Recommendations ........................................................................................................ 22

4.4 V_CC5Pin Requirements (V_DIFF) ........................................................................................................ 23

4.5 VCCPLL Pin Requirements .............................................................................................................. 23

4.6 DC Specifications ............................................................................................................................. 24

4.7 AC Specifications ............................................................................................................................. 26

4.7.1 AC Test Conditions and Derating Curves .............................................................................. 29

4.7.2 AC Timing Waveforms ........................................................................................................... 30

5.0 BUS FUNCTIONAL WAVEFORMS ........................................................................................................ 37

6.0 DEVICE IDENTIFICATION ...................................................................................................................... 51

7.0 REVISION HISTORY ............................................................................................................................... 53

iii

Contents

FIGURES

Figure 1. 80960JD Microprocessor ................................................................................................................ i

Figure 2. 80960JD Block Diagram ................................................................................................................2

Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up .............................................................12

Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down ..............................................................13

Figure 5. 132-Lead PQFP - Top View .........................................................................................................16

Figure 6. VCC5 Current-Limiting Resistor ...................................................................................................23

Figure 7. VCCPLL Lowpass Filter ...............................................................................................................23

Figure 8. AC Test Load ...............................................................................................................................29

Figure 9. Output Delay or Hold vs. Load Capacitance ................................................................................29

Figure 10. CLKIN Waveform .........................................................................................................................30

Figure 11. Output Delay Waveform for T_OV1................................................................................................30

Figure 12. Output Float Waveform for T_OF...................................................................................................31

Figure 13. Input Setup and Hold Waveform for T_IS1and T_IH1......................................................................31

Figure 14. Input Setup and Hold Waveform for T_IS2and T_IH2......................................................................32

Figure 15. Input Setup and Hold Waveform for T_IS3and T_IH3......................................................................32

Figure 16. Input Setup and Hold Waveform for T_IS4and T_IH4......................................................................33

Figure 17. Relative Timings Waveform for T_LX, T_LXLand T_LXA....................................................................33

Figure 18. DT/R and DEN Timings Waveform ..............................................................................................34

Figure 19. TCK Waveform ............................................................................................................................34

Figure 20. Input Setup and Hold Waveforms for T_BSIS1and T_BSIH1.............................................................35

Figure 21. Output Delay and Output Float Waveform for T_BSOV1AND T_BSOF1............................................35

Figure 22. Output Delay and Output Float Waveform for T_BSOV2and T_BSOF2.............................................36

Figure 23. Input Setup and Hold Waveform for T_BSIS2and T_BSIH2...............................................................36

Figure 24. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ..................................37

Figure 25. Burst Read and Write Transactions Without Wait States, 32-Bit Bus ..........................................38

Figure 26. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ...................................................39

Figure 27. Burst Read and Write Transactions Without Wait States, 8-Bit Bus ............................................40

Figure 28. Burst Read and Write Transactions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus .......................................................................................41

Figure 29. Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ..............................42

Figure 30. HOLD/HOLDA Waveform For Bus Arbitration .............................................................................43

Figure 31. Cold Reset Waveform ..................................................................................................................44

Figure 32. Warm Reset Waveform ................................................................................................................45

Figure 33. Entering the ONCE State .............................................................................................................46

Figure 34. Summary of Aligned and Unaligned Accesses (32-Bit Bus) ........................................................49

Figure 35. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ....................................50

Figure 36. 80960JD Device Identification Register .......................................................................................51

Contents

TABLES

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

80960Jx Instruction Set ................................................................................................................. 5

Pin Description Nomenclature ....................................................................................................... 6

Pin Description — External Bus Signals ........................................................................................ 7

Pin Description — Processor Control Signals, Test Signals and Power ..................................... 10

Pin Description — Interrupt Unit Signals ..................................................................................... 11

132-Lead PGA Pinout — In Signal Order .................................................................................... 14

132-Lead PGA Pinout — In Pin Order ......................................................................................... 15

132-Lead PQFP Pinout — In Signal Order .................................................................................. 17

132-Lead PQFP Pinout — In Pin Order ....................................................................................... 18

Table 10. 132-Lead PGA Package Thermal Characteristics ....................................................................... 19

Table 11. 132-Lead PQFP Package Thermal Characteristics ..................................................................... 20

Table 12. Maximum T_Aat Various Airflows in °C ......................................................................................... 21

Table 13. 80960JD Operating Conditions .................................................................................................... 22

Table 14. 80960JD DC Characteristics ....................................................................................................... 24

Table 15. 80960JD ICC Characteristics ...................................................................................................... 25

Table 16. 80960JD AC Characteristics ........................................................................................................ 26

Table 17. Note Definitions for Table 16, 80960JD AC Characteristics (pg. 26) ........................................... 28

Table 18. Natural Boundaries for Load and Store Accesses ....................................................................... 47

Table 19. Summary of Byte Load and Store Accesses ............................................................................... 47

Table 20. Summary of Short Word Load and Store Accesses .................................................................... 47

Table 21. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ................................................... 48

Table 22. 80960JD66 Die and Stepping Reference .................................................................................... 51

Table 23. Fields of 80960JD Device ID ....................................................................................................... 52

Table 24. 80960JD Device ID Model Types ................................................................................................ 52

Table 25. Device ID Version Numbers for Different Steppings .................................................................... 52

80960JD

(MMRs) — an extension not found on the i960 Kx,

Sx or Cx processors. Physical and logical configu-

ration registers enable the processor to operate with

all combinations of bus width and data object

alignment. The processor supports a homogeneous

byte ordering model.

1.0 PURPOSE

This document contains preview information for the

80960JD microprocessor, including electrical

characteristics and package pinout information.

Detailed functional descriptions

— other than

parametric performance — are published in the

i960^®Jx Microprocessor User’s Guide (272483).

This processor integrates two important peripherals:

a timer unit and an interrupt controller. These and

other hardware resources are programmed through

memory-mapped control registers, an extension to

the familiar 80960 architecture.

Throughout this data sheet, references to “80960Jx”

indicate features which apply to all of the following:

• 80960JA — 5V, 2 Kbyte instruction cache, 1 Kbyte

data cache

The timer unit (TU) offers two independent 32-bit

timers for use as real-time system clocks and

general-purpose system timing. These operate in

either single-shot or auto-reload mode and can

generate interrupts.

• 80L960JA — 3.3 V version of the 80960JA

• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache and clock doubling

• 80960JD — 3.3V, 5V Tolerant version of the

80960JD

The interrupt controller unit (ICU) provides a flexible

means for requesting interrupts. The ICU provides

full programmability of up to 240 interrupt sources

into 31 priority levels. The ICU takes advantage of a

cached priority table and optional routine caching to

minimize interrupt latency. Clock doubling reduces

interrupt latency by 40% compared to the

80960JA/JF. Local registers may be dedicated to

high-priority interrupts to further reduce latency.

Acting independently from the core, the ICU

compares the priorities of posted interrupts with the

current process priority, off-loading this task from the

core. The ICU also supports the integrated timer

interrupts.

• 80960JF — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache

• 80L960JF — 3.3 V version of the 80960JF

2.0 80960JD OVERVIEW

The 80960JD offers high performance to cost-

sensitive 32-bit embedded applications. The

80960JD is object code compatible with the 80960

Core Architecture and is capable of sustained

execution at the rate of one instruction per clock.

This processor’s features include generous

instruction cache, data cache and data RAM. It also

boasts a fast interrupt mechanism, dual program-

mable timer units and new instructions.

The 80960JD features a Halt mode designed to

support applications where low power consumption

is critical. The halt instruction shuts down instruction

execution, resulting in a power savings of up to 90

percent.

The 80960JD’s clock doubler operates the processor

core at twice the bus clock rate to improve execution

performance without increasing the complexity of

board designs.

The 80960JD’s testability features, including ONCE

(On-Circuit Emulation) mode and Boundary Scan

(JTAG), provide a powerful environment for design

debug and fault diagnosis.

Memory subsystems for cost-sensitive embedded

applications often impose substantial wait state

penalties. The 80960JD integrates considerable

storage resources on-chip to decouple CPU

execution from the external bus.

The

Solutions960® program features a wide variety

of development tools which support the i960

processor family. Many of these tools are developed

by partner companies; some are developed by Intel,

such as profile-driven optimizing compilers. For

more information on these products, contact your

local Intel representative.

The 80960JD rapidly allocates and deallocates local

needs to flush a register set to the stack only when it

saves more than seven sets to its local register cache.

A 32-bit multiplexed burst bus provides a high-speed

interface to system memory and I/O.

A full

complement of control signals simplifies the

connection of the 80960JD to external components.

The user programs physical and logical memory

attributes through memory-mapped control registers

PRODUCT PREVIEW

80960JD

Control

Physical Region

Configuration

32-bit buses

address / data

CLKIN

PLL, Clocks,

Power Mgmt

Bus

4 KByte Instruction Cache

Two-Way Set Associative

Control Unit

Address/

Data Bus

Bus Request

Queues

TAP

Boundary Scan

Controller

Instruction Sequencer

Two 32-Bit

Timers

Constants

Control

Interrupt

Port

Programmable

Interrupt Controller

8-Set

Local Register Cache

Execution

and

Memory

Interface

Unit

Memory-Mapped

Multiply

Divide

Unit

Address

Generation

128

Unit

1 Kbyte

32-bit Address

32-bit Data

Global / Local

effective

address

Data RAM

SRC1 SRC2 DEST

2 Kbyte Direct

Mapped Data

Cache

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

Figure 2. 80960JD Block Diagram

• 2 Kbyte direct-mapped, integrated data cache

2.1 80960 Processor Core

• 1 Kbyte integrated data RAM delivers zero wait

state program data

The 80960Jx family is a scalar implementation of the

80960 Core Architecture. Intel designed this

processor core as a very high performance device

that is also cost-effective. Factors that contribute to

the core’s performance include:

2.2 Burst Bus

• Core operates at twice the bus speed (80960JD

only)

A 32-bit high-performance bus controller interfaces

the 80960JD to external memory and peripherals.

The BCU fetches instructions and transfers data at

the rate of up to four 32-bit words per six clock

cycles. The external address/data bus is multi-

plexed.

• Single-clock execution of most instructions

• Independent Multiply/Divide Unit

• Efficient instruction pipeline minimizes pipeline

break latency

Users may configure the 80960JD’s bus controller to

match an application’s fundamental memory organi-

zation. Physical bus width is register-programmed

for up to eight regions. Byte ordering and data

caching are programmed through a group of logical

memory templates and a defaults register.

• Register and resource scoreboarding allow

overlapped instruction execution

• 128-bit register bus speeds local register caching

• 4 Kbyte two-way set associative, integrated

instruction cache

PRODUCT PREVIEW

80960JD

The BCU’s features include:

• Interrupt vectors and interrupt handler routines can

be reserved on-chip

• Multiplexed external bus to minimize pin count

• Register frames for high-priority interrupt handlers

can be cached on-chip

• 32-, 16- and 8-bit bus widths to simplify I/O

interfaces

• The interrupt stack can be placed in cacheable

memory space

• External ready control for address-to-data, data-to-

data and data-to-next-address wait state types

• Interrupt microcode executes at twice the bus

frequency

• Support for big or little endian byte ordering to

facilitate the porting of existing program code

• Unaligned bus accesses performed transparently

• Three-deep load/store queue to decouple the bus

from the core

2.5 Instruction Set Summary

The 80960Jx adds several new instructions to the

i960 core architecture. The new instructions are:

Upon reset, the 80960JD conducts an internal self

test. Then, before executing its first instruction, it

performs an external bus confidence test by

performing a checksum on the first words of the

initialization boot record (IBR).

• Conditional Move

• Conditional Add

• Conditional Subtract

• Byte Swap

The user may examine the contents of the caches at

any time by executing special cache control instruc-

tions.

• Halt

• Cache Control

• Interrupt Control

2.3 Timer Unit

Table 1 identifies the instructions that the 80960Jx

supports. Refer to i960^®Jx Microprocessor User’s

Guide (272483) for a detailed description of each

instruction.

The timer unit (TU) contains two independent 32-bit

timers which are capable of counting at several clock

rates and generating interrupts. Each is programmed

by use of the TU registers. These memory-mapped

registers are addressable on 32-bit boundaries. The

timers have a single-shot mode and auto-reload

capabilities for continuous operation. Each timer has

an independent interrupt request to the 80960JD’s

interrupt controller. The TU can generate a fault

when unauthorized writes from user mode are

detected. Clock prescaling is supported.

2.6 Faults and Debugging

The 80960Jx employs a comprehensive fault model.

The processor responds to faults by making implicit

calls to a fault handling routine. Specific information

collected for each fault allows the fault handler to

diagnose exceptions and recover appropriately.

The processor also has built-in debug capabilities. In

software, the 80960Jx may be configured to detect

as many as seven different trace event types. Alter-

natively, mark and fmark instructions can generate

trace events explicitly in the instruction stream.

Hardware breakpoint registers are also available to

trap on execution and data addresses.

2.4 Priority Interrupt Controller

A programmable interrupt controller manages up to

240 external sources through an 8-bit external

interrupt port. Alternatively, the interrupt inputs may

be configured for individual edge- or level-triggered

inputs. The interrupt unit (IU) also accepts interrupts

from the two on-chip timer channels and a single

Non-Maskable Interrupt (NMI) pin. Interrupts are

serviced according to their priority levels relative to

the current process priority.

2.7 Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-

micron manufacturing process. The processor’s sub-

micron topology provides the circuit density for

optimal cache size and high operating speeds while

Low interrupt latency is critical to many embedded

applications. As part of its highly flexible interrupt

mechanism, the 80960JD exploits several

techniques to minimize latency:

PRODUCT PREVIEW

80960JD

dissipating modest power. The processor also uses

dynamic power management to turn off clocks to

unused circuits.

2.9 Memory-Mapped Control

Registers

The 80960JD, though compliant with i960 series

processor core, has the added advantage of

memory-mapped, internal control registers not found

on the i960 Kx, Sx or Cx processors. These give

software the interface to easily read and modify

internal control registers.

Users may program the 80960Jx to enter Halt mode

for maximum power savings. In Halt mode, the

processor core stops completely while the integrated

peripherals continue to function, reducing overall

power requirements up to 90 percent. Processor

execution resumes from internally or externally

generated interrupts.

Each of these registers is accessed as a memory-

mapped, 32-bit register. Access is accomplished

through regular memory-format instructions. The

processor ensures that these accesses do not

generate external bus cycles.

2.8 Test Features

The 80960Jx incorporates numerous features which

enhance the user’s ability to test both the processor

and the system to which it is attached. These

features include ONCE (On-Circuit Emulation) mode

and Boundary Scan (JTAG).

2.10 Data Types and Memory

Addressing Modes

As with all i960 family processors, the 80960Jx

instruction set supports several data types and

formats:

The 80960Jx provides testability features compatible

with IEEE Standard Test Access Port and Boundary

Scan Architecture (IEEE Std. 1149.1).

• Bit

One of the boundary scan instructions, HIGHZ,

forces the processor to float all its output pins

(ONCE mode). ONCE mode can also be initiated at

reset without using the boundary scan mechanism.

• Bit fields

• Integer (8-, 16-, 32-, 64-bit)

• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)

• Triple word (96 bits)

• Quad word (128 bits)

ONCE mode is useful for board-level testing. This

feature allows a mounted 80960JD to electrically

“remove” itself from a circuit board. This allows for

system-level testing where a remote tester — such

The 80960Jx provides a full set of addressing modes

for C and assembly programming:

as an in-circuit emulator

processor system.

— can exercise the

• Two Absolute modes

• Five Register Indirect modes

• Index with displacement

• IP with displacement

The provided test logic does not interfere with

component or circuit board behavior and ensures

that components function correctly, connections

between various components are correct, and

various components interact correctly on the printed

circuit board.

The JTAG Boundary Scan feature is an attractive

alternative to conventional “bed-of-nails” testing. It

can examine connections which might otherwise be

inaccessible to a test system.

PRODUCT PREVIEW

80960JD

Table 1. 80960Jx Instruction Set

Arithmetic Logical

Data Movement

Load

Bit, Bit Field and Byte

Add

And

Set Bit

Store

Subtract

Not And

And Not

Clear Bit

Move

Multiply

Not Bit

*Conditional Select

Load Address

Divide

Alter Bit

Remainder

Exclusive Or

Not Or

Scan For Bit

Span Over Bit

Extract

Modulo

Shift

Or Not

Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

*Conditional Add

*Conditional Subtract

Rotate

Nor

Modify

Exclusive Nor

Not

Scan Byte for Equal

*Byte Swap

Nand

Comparison

Branch

Call/Return

Fault

Compare

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Conditional Fault

Conditional Compare

Call Extended

Call System

Return

Synchronize Faults

Compare and

Increment

Compare and

Decrement

Branch and Link

Test Condition Code

Check Bit

Processor

Management

Debug

Atomic

Modify Trace Controls

Mark

Flush Local Registers

Atomic Add

Modify Arithmetic

Controls

Atomic Modify

Force Mark

Modify Process

Controls

*Halt

System Control

*Cache Control

*Interrupt Control

NOTES: Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB

implementations.

PRODUCT PREVIEW

80960JD

3.0 PACKAGE INFORMATION

Table 2. Pin Description Nomenclature

The 80960JD is offered with three speeds and two

package types. The 132-pin Pin Grid Array (PGA)

device is specified for operation at V_CC= 3.3 V ± 5%

over a case temperature range of 0° to 100°C:

Symbol

Description

Input pin only.

I/O

–

Output pin only.

• A80960JD-66 (66 MHz core, 33 MHz bus)

• A80960JD-50 (50 MHz core, 25 MHz bus)

• A80960JD-40 (40 MHz core, 20 MHz bus)

Pin can be either an input or output.

Pin must be connected as described.

Synchronous. Inputs must meet setup

and hold times relative to CLKIN for

proper operation.

The 132-pin Plastic Quad Flatpack (PQFP) devices

will be specified for operation at V_CC= 3.3 V ± 5%

over a case temperature range of 0° to 100°C:

S(E) Edge sensitive input

S(L) Level sensitive input

• NG80960JD-66 (66 MHz core, 33 MHz bus)

• NG80960JD-50 (50 MHz core, 25 MHz bus)

• NG80960JD-40 (40 MHz core, 20 MHz bus)

A (...)

R (...)

Asynchronous. Inputs may be

asynchronous relative to CLKIN.

A(E) Edge sensitive input

A(L) Level sensitive input

For complete package specifications and infor-

mation, refer to Intel’s Packaging Handbook

(240800).

While the processor’s RESET pin is

asserted, the pin:

3.1 Pin Descriptions

R(1) is driven to V_CC

R(0) is driven to V_SS

This section describes the pins for the 80960JD in

the 132-pin ceramic Pin Grid Array (PGA) package

and 132-lead Plastic Quad Flatpack Package

(PQFP).

R(Q) is a valid output

R(X) is driven to unknown state

R(H) is pulled up to V_CC

H (...)

While the processor is in the hold state,

the pin:

Section 3.1.1, Functional Pin Definitions

describes pin function; Section 3.1.2, 80960Jx 132-

Lead PGA Pinout and Section 3.1.3, 80960Jx

PQFP Pinout define the signal and pin locations for

the supported package types.

H(1) is driven to V_CC

H(0) is driven to V_SS

H(Q) Maintains previous state or

continues to be a valid output

H(Z) Floats

3.1.1 Functional Pin Definitions

P (...)

While the processor is halted, the pin:

P(1) is driven to V_CC

P(0) is driven to V_SS

P(Q) Maintains previous state or

continues to be a valid output

Table 2 presents the legend for interpreting the pin

descriptions which follow. Pins associated with the

bus interface are described in Table 3. Pins

associated with basic control and test functions are

described in Table 4. Pins associated with the

Interrupt Unit are described in Table 5.

PRODUCT PREVIEW

80960JD

Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)

NAME

TYPE

DESCRIPTION

AD31:0

I/O

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data

S(L)

R(X)

H(Z)

P(Q)

to and from memory. During an address (T ) cycle, bits 31:2 contain a physical word

address (bits 0-1 indicate SIZE; see below). During a data (T ) cycle, read or write

data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,

AD15:8 and AD7:0. During write operations, unused pins are driven to determinate

values.

SIZE, which comprises bits 0-1 of the AD lines during a T cycle, specifies the

number of data transfers during the bus transaction.

AD1

AD0

Bus Transfers

1 Transfer

2 Transfers

3 Transfers

4 Transfers

When the processor enters Halt mode, if the previous bus operation was a:

• write — AD31:2 are driven with the last data value on the AD bus.

• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are

driven with the value of A3:2 from the last data cycle.

Typically, AD1:0 reflect the SIZE information of the last bus transaction (either

instruction fetch or load/store) that was executed before entering Halt mode.

ALE

ADS

A3:2

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

asserted during a T cycle and deasserted before the beginning of the T state. It is

R(0)

H(Z)

P(0)

active HIGH and floats to a high impedance state during a hold cycle (T ).

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the

inverted version of ALE. This signal gives the 80960JD a high degree of compatibility

with existing 80960Kx systems.

R(1)

H(Z)

P(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

R(1)

H(Z)

P(1)

The processor asserts ADS for the entire T cycle. External bus control logic typically

samples ADS at the end of the cycle.

ADDRESS3:2 comprise a partial demultiplexed address bus.

R(X)

H(Z)

P(Q)

32-bit memory accesses: the processor asserts address bits A3:2 during T . The

partial word address increments with each assertion of RDYRCV during a burst.

16-bit memory accesses: the processor asserts address bits A3:1 during T with A1

driven on the BE1 pin. The partial short word address increments with each assertion

of RDYRCV during a burst.

8-bit memory accesses: the processor asserts address bits A3:0 during T , with A1:0

driven on BE1:0. The partial byte address increments with each assertion of

RDYRCV during a burst.

PRODUCT PREVIEW

80960JD

Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)

NAME

TYPE

DESCRIPTION

BE3:0

BYTE ENABLES select which of up to four data bytes on the bus participate in the

current bus access. Byte enable encoding is dependent on the bus width of the

memory region accessed:

R(1)

H(Z)

P(1)

32-bit bus:

BE3 enables data on AD31:24

BE2 enables data on AD23:16

BE1 enables data on AD15:8

BE0 enables data on AD7:0

16-bit bus:

BE3 becomes Byte High Enable (enables data on AD15:8)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Byte Low Enable (enables data on AD7:0)

8-bit bus:

BE3 is not used (state is high)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Address Bit 0 (A0)

The processor asserts byte enables, byte high enable and byte low enable during T .

Since unaligned bus requests are split into separate bus transactions, these signals

do not toggle during a burst. They remain active through the last T_dcycle.

For accesses to 8- and 16-bit memory, the processor asserts the address bits in

conjunction with A3:2 described above.

WIDTH/

WIDTH/HALTED signals denote the physical memory attributes for a bus trans-

HLTD1:0

R(0)

H(Z)

P(1)

action:

WIDTH/HLTD1

WIDTH/HLTD0

8 Bits Wide

16 Bits Wide

32 Bits Wide

Processor Halted

The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in

response to a HOLD request, regardless of prior operating state.

D/C

DATA/CODE indicates that a bus access is a data access (1) or an instruction

R(X)

H(Z)

P(Q)

access (0). D/C has the same timing as W/R.

0 = instruction access

1 = data access

W/R

DT/R

WRITE/READ specifies, during a T cycle, whether the operation is a write (1) or

R(0)

H(Z)

P(Q)

read (0). It is latched on-chip and remains valid during T cycles.

0 = read

1 = write

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the

R(0)

H(Z)

P(Q)

address/data bus. It is low during T_aand T /T cycles for a read; it is high during T

and T_w/T cycles for a write. DT/R never changes state when DEN is asserted.

0 = receive

1 = transmit

PRODUCT PREVIEW

80960JD

Table 3. Pin Description — External Bus Signals (Sheet 3 of 4)

NAME

DEN

TYPE

DESCRIPTION

DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted

at the start of the first data cycle in a bus access and deasserted at the end of the

last data cycle. DEN is used with DT/R to provide control for data transceivers

connected to the data bus.

R(1)

H(Z)

P(1)

0 = data cycle

1 = not data cycle

BLAST

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the

last data transfer of burst and non-burst accesses. BLAST remains active as long as

wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final

data transfer in a bus cycle.

R(1)

H(Z)

P(1)

0 = last data transfer

1 = not last data transfer

RDYRCV

READY/RECOVER indicates that data on AD lines can be sampled or removed. If

S(L)

RDYRCV is not asserted during a T cycle, the T_dcycle is extended to the next cycle

by inserting a wait state (T ).

0 = sample data

1 = don’t sample data

The RDYRCV pin has another function during the recovery (T_r) state. The processor

continues to insert additional recovery states until it samples the pin HIGH. This

function gives slow external devices more time to float their buffers before the

processor begins to drive address again.

0 = insert wait states

1 = recovery complete

LOCK/

ONCE

I/O

BUS LOCK indicates that an atomic read-modify-write operation is in progress. The

LOCK output is asserted in the first clock of an atomic operation and deasserted in

the last data transfer of the sequence. The processor does not grant HOLDA while it

is asserting LOCK. This prevents external agents from accessing memory involved

in semaphore operations.

S(L)

R(H)

H(Z)

P(1)

0 = Atomic read-modify-write in progress

1 = Atomic read-modify-write not in progress

ONCE MODE: The processor samples the ONCE input during reset. If it is asserted

LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the

processor stops all clocks and floats all output pins. The pin has a weak internal

pullup which is active during reset to ensure normal operation when the pin is left

unconnected.

0 = ONCE mode enabled

1 = ONCE mode not enabled

HOLD

HOLD: A request from an external bus master to acquire the bus. When the

S(L)

processor receives HOLD and grants bus control to another master, it asserts

HOLDA, floats the address/data and control lines and enters the T state. When

HOLD is deasserted, the processor deasserts HOLDA and enters either the T or T

state, resuming control of the address/data and control lines.

0 = no hold request

1 = hold request

PRODUCT PREVIEW

80960JD

Table 3. Pin Description — External Bus Signals (Sheet 4 of 4)

NAME

TYPE

DESCRIPTION

HOLDA

HOLD ACKNOWLEDGE indicates to an external bus master that the processor has

relinquished control of the bus. The processor can grant HOLD requests and enter

the T_hstate during reset and while halted as well as during regular operation.

R(Q)

H(1)

P(Q)

0 = hold not acknowledged

1 = hold acknowledged

BSTAT

BUS STATUS indicates that the processor may soon stall unless it has sufficient

access to the bus; see i960^®Jx Microprocessor User’s Guide (272483). Arbitration

logic can examine this signal to determine when an external bus master should

acquire/relinquish the bus.

R(0)

H(Q)

P(0)

0 = no potential stall

1 = potential stall

Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 1 of 2)

NAME

CLKIN

TYPE

DESCRIPTION

CLOCK INPUT provides the processor’s fundamental time base; both the processor

core and the external bus run at the CLKIN rate. All input and output timings are

specified relative to a rising CLKIN edge.

RESET

RESET initializes the processor and clears its internal logic. During reset, the

processor places the address/data bus and control output pins in their idle (inactive)

states.

A(L)

During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST

and HOLD.

The RESET pin has an internal synchronizer. To ensure predictable processor initial-

ization during power up, RESET must be asserted a minimum of 10,000 CLKIN

cycles with V_CCand CLKIN stable. On a warm reset, RESET should be asserted for

a minimum of 15 cycles.

STEST

FAIL

SELF TEST enables or disables the processor’s internal self-test feature at initial-

ization. STEST is examined at the end of reset. When STEST is asserted, the

processor performs its internal self-test and the external bus confidence test. When

STEST is deasserted, the processor performs only the external bus confidence test.

S(L)

0 = self test disabled

1 = self test enabled

FAIL indicates a failure of the processor’s built-in self-test performed during initial-

ization. FAIL is asserted immediately upon reset and toggles during self-test to

indicate the status of individual tests:

R(0)

H(Q)

P(1)

• When self-test passes, the processor deasserts FAIL and begins operation from

user code.

• When self-test fails, the processor asserts FAIL and then stops executing.

0 = self test failed

1 = self test passed

TCK

TDI

TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1

Boundary Scan Testing (JTAG). State information and data are clocked into the

processor on the rising edge; data is clocked out of the processor on the falling edge.

TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising

S(L)

edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.

PRODUCT PREVIEW

80960JD

Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 2 of 2)

NAME

TDO

TYPE

DESCRIPTION

TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling

edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At

other times, TDO floats. TDO does not float during ONCE mode.

R(Q)

HQ)

P(Q)

TRST

TEST RESET asynchronously resets the Test Access Port (TAP) controller function

of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan

feature, connect a pulldown resistor between this pin and V_SS. If TAP is not used,

this pin must be connected to V_SS; however, no resistor is required. See Section 4.3,

Connection Recommendations (pg. 22).

A(L)

TMS

TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of

S(L)

the test logic for IEEE 1149.1 Boundary Scan testing.

V_CC

–

POWER pins intended for external connection to a V_CCboard plane.

V_CCPLL

PLL POWER is a separate V_CCsupply pin for the phase lock loop clock generator. It

is intended for external connection to the V_CCboard plane. In noisy environments,

add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects

on timing relationships.

V_CC5

–

5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O

buffers. This signal should be connected to +5 V for use with inputs which exceed

3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.

V_SS

–

GROUND pins intended for external connection to a V_SSboard plane.

NO CONNECT pins. Do not make any system connections to these pins.

Table 5. Pin Description — Interrupt Unit Signals

NAME

TYPE

DESCRIPTION

XINT7:0

EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0

A(E/L) pins can be configured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs

can be programmed to be level (low) or edge (falling) sensitive.

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins

are level sensitive in this mode.

Mixed Mode:

The XINT7:5 pins act as dedicated sources and the XINT4:0 pins

act as the five most significant bits of a vectored source. The least

significant bits of the vectored source are set to 010₂internally.

Unused external interrupt pins should be connected to V_CC

NMI

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

A(E)

NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is

unused, it should be connected to V_CC

PRODUCT PREVIEW

80960JD

3.1.2 80960Jx 132-Lead PGA Pinout

AD22 AD19 AD18 V_CC

V_CC

V_CCAD13

AD11 AD6

AD25

V_SS

AD27 AD26 AD24 AD20

AD10 AD7

AD3

AD23 AD21

AD12

AD9

AD17

AD16 AD15 AD14

AD8

AD5

AD0

V_CC

AD4

AD1

AD30 AD29 NC

BE2

V_CC

BE3

V_SS

AD28

AD31

AD2 V_SS

V_CC

V_SS

V_CC

V_SS

BE1

BE0

V_CCPLLV_SSCLKIN

V_CC

V_SS

V_CC

V_SSALE

V_SS

V_CC

BSTAT

DEN

V_CC

V_SS

RDYRCV V_SS

RESET V_SS

V_CC

V_SS

V_CC

V_SSDT/R

V_SS

TDI

LOCK/

ONCE

HOLDA BLAST

FAIL

V_SS

V_CC

V_CC5

NC HOLD XINT1 XINT0 TRST STEST NC

W/R

D/C WIDTH/ TDO NC

HLTD0

V_SS

V_SSXINT6 XINT4 XINT3 TCK

ALE

ADS WIDTH/

HLTD1

V_CC

V_CCV_CC

NMI XINT7 XINT5 XINT2 TMS

Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up

PRODUCT PREVIEW

80960JD

TMS

CLKIN

V_SS

AD0

AD4

AD3

AD7

AD6

V_CC

V_SS

TDI

V_CC

V_SS

AD2

V_CC

AD1

XINT2 TCK STEST

AD11

V_SS

AD5

RESET

XINT5 XINT3 TRST

XINT7 XINT4 XINT0

RDYRCV NC

V_CCPLLNC

AD8

AD9

AD10 AD13

V_SS

V_CC

AD12 V_SS

V_CC

NMI

V_CC

XINT6 XINT1

V_SSHOLD

AD14

V_SS

V_CC

A80960JD

AD15 V_SS

V_CC

V_SS

AD16

V_SS

V_CC

V_SS

V_CC5

V_CC

V_SS

FAIL

AD17 V_SS

AD21 V_SS

XXXXXXXX C0

V_CC

TDO

AD23 AD20 AD18

AD19

BE1

V_SS

V_CC

BSTAT ALE

BE0

V_SS

V_CC

AD31 AD28

AD24

WIDTH/

HLTD0

BLAST

ALE

DT/R

V_SS

DEN

WIDTH/

HLTD1

D/C HOLDA

V_SS

BE3

BE2

AD29

AD22

AD26

ADS

V_CC

AD30 AD27 AD25

W/R LOCK/

ONCE

Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down

PRODUCT PREVIEW

80960JD

Table 6. 132-Lead PGA Pinout — In Signal Order

Signal

AD31

ADS

Signal

TDO

TMS

TRST

V_CC

V_CCPLL

V_CC5

V_SS

Signal

V_SS

A14

C12

V_SS

AD0

M14

L13

K12

N14

M13

L12

P14

N13

M12

M11

N12

P13

M10

P12

ALE

V_SS

D13

AD1

ALE

V_SS

AD2

BE0

V_SS

E13

AD3

BE1

V_SS

AD4

BE2

V_SS

F13

AD5

BE3

V_SS

AD6

BLAST

BSTAT

CLKIN

D/C

D14

V_SS

G13

AD7

V_SS

AD8

H14

E14

V_SS

H13

AD9

V_SS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

DEN

F14

G14

V_SS

J13

DT/R

FAIL

V_SS

K13

HOLD

HOLDA

LOCK/ONCE

V_SS

J14

V_SS

K14

L14

V_SS

N10

N11

B14

V_SS

W/R

C14

G12

J12

A10

F12

E12

C13

B13

D12

WIDTH/HLTD0

WIDTH/HLTD1

XINT0

XINT1

XINT2

XINT3

XINT4

XINT5

XINT6

XINT7

C11

C10

A13

B12

B11

A12

B10

A11

P10

P11

H12

NMI

RDYRCV

RESET

STEST

TCK

V_SS

TDI

V_SS

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

PRODUCT PREVIEW

80960JD

Table 7. 132-Lead PGA Pinout — In Pin Order

Signal

ADS

Signal

FAIL

V_CC5

Signal

V_CC

M10

M11

M12

M13

M14

Signal

AD12

AD9

AD8

AD4

AD0

AD27

AD26

AD24

AD20

V_SS

WIDTH/HLTD1

ALE

V_SS

BE0

HOLD

XINT1

XINT0

TRST

STEST

H12

H13

H14

V_CCPLL

V_SS

C10

C11

C12

C13

C14

V_CC

CLKIN

V_CC

V_SS

V_CC

BE1

A10

A11

A12

A13

A14

NMI

V_CC

J12

J13

J14

XINT7

XINT5

XINT2

TMS

V_SS

DT/R

TDI

V_CC

V_SS

D12

D13

D14

V_CC

V_SS

W/R

V_CC

AD31

AD2

N10

N11

N12

N13

N14

V_SS

D/C

V_CC

K12

K13

K14

V_SS

WIDTH/HLTD0

TDO

V_SS

AD10

AD7

AD3

AD25

AD22

AD19

AD18

V_CC

DEN

RESET

V_SS

V_CC

E12

E13

E14

BE2

V_SS

BE3

V_SS

V_CC

AD28

AD5

V_SS

V_CC

L12

L13

L14

V_SS

AD1

B10

B11

B12

B13

B14

XINT6

XINT4

XINT3

TCK

BSTAT

RDYRCV

V_SS

V_CC

F12

F13

F14

AD30

AD29

V_CC

AD23

AD21

AD17

AD16

AD15

AD14

V_CC

LOCK/ONCE

HOLDA

BLAST

V_SS

P10

P11

P12

P13

P14

V_CC

ALE

V_CC

G12

G13

G14

AD13

AD11

AD6

V_SS

V_CC

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

PRODUCT PREVIEW

80960JD

3.1.3 80960Jx PQFP Pinout

AD9

TRST

TCK

TMS

HOLD

XINT0

XINT1

XINT2

V_CC(I/O)

V_SS(I/O)

AD10

AD11

_CC(I/O)

_SS(I/O)

V_CC(Core)

XINT3

V_CC(I/O)

_SS(I/O)

XINT4

XINT5

XINT6

V_SS(Core)

AD12

AD13

AD14

AD15

V_CC(I/O)

XINT7

NMI

_SS(I/O)

AD16

AD17

AD18

AD19

V_CC(Core)

_SS(Core)

i960

V_CC(I/O)

V_CC5

FAIL

ALE

TDO

V_SS(I/O)

AD20

AD21

AD22

NG80960JX

XXXXXXXX C0

AD23

V_CC(Core)

_CC(I/O)

_SS(I/O)

WIDTH/HLTD1

_CC(Core)

_SS(Core)

V_SS(Core)

_CC(I/O)

_SS(I/O)

AD24

WIDTH/HLTD0

AD25

AD26

Figure 5. 132-Lead PQFP - Top View

PRODUCT PREVIEW

80960JD

Table 8. 132-Lead PQFP Pinout — In Signal Order

Signal

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

Signal

ALE

132

Signal

V_SS(Core)

V_SS(I/O)

124

106

112

131

121

122

126

127

V_CC(Core)

V_CC(I/O)

ADS

BE3

113

115

123

BE2

BE1

BE0

WIDTH/HLTD1

WIDTH/HLTD0

D/C

V_CC(I/O)

W/R

DT/R

DEN

BLAST

RDYRCV

LOCK/ONCE

HOLD

HOLDA

BSTAT

CLKIN

RESET

STEST

FAIL

_CC(I/O)

117

125

128

V_CC(I/O)

V_CCPLL

105

111

129

119

V_CC5

AD8

100

101

102

103

104

107

108

109

110

V_SS(CLK)

V_SS(Core)

118

AD7

TCK

XINT7

XINT6

XINT5

XINT4

XINT3

XINT2

XINT1

XINT0

NMI

AD6

TDI

130

AD5

TDO

_SS(Core)

AD4

TRST

V_SS(Core)

AD3

TMS

AD2

V_CC(CLK)

120

AD1

_CC(Core)

AD0

V_CC(Core)

114

116

ALE

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

PRODUCT PREVIEW

80960JD

Table 9. 132-Lead PQFP Pinout — In Pin Order

Signal

TRST

TCK

Signal

BLAST

D/C

Signal

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

Signal

AD8

AD26

AD7

TMS

ADS

AD25

AD6

HOLD

XINT0

XINT1

XINT2

XINT3

W/R

AD24

AD5

V_SS(Core)

V_CC(Core)

V_SS(I/O)

V_CC(I/O)

DT/R

V_SS(I/O)

V_CC(I/O)

V_SS(Core)

V_CC(Core)

AD23

AD4

V_CC(I/O)

V_SS(I/O)

AD3

_CC(I/O)

V_SS(I/O)

XINT4

AD2

DEN

AD22

AD1

HOLDA

ALE

AD21

AD0

XINT5

AD20

V_CC(I/O)

V_SS(I/O)

V_CC(Core)

V_SS(Core)

V_CC(Core)

V_SS(Core)

CLKIN

V_SS(CLK)

V_CCPLL

V_{CC (CLK)}

XINT6

V_SS(Core)

V_CC(Core)

V_SS(I/O)

V_CC(I/O)

LOCK/ONCE

BSTAT

BE0

V_SS(I/O)

V_CC(I/O)

AD19

XINT7

NMI

V_CC(Core)

V_SS(Core)

AD18

AD17

AD16

V_SS(I/O)

V_CC(I/O)

AD15

V_CC5

BE1

BE2

BE3

AD14

FAIL

V_SS(I/O)

V_CC(I/O)

V_SS(Core)

V_CC(Core)

AD31

AD13

ALE

AD12

V_CC(Core)

V_SS(Core)

RESET

TDO

V_SS(Core)

V_CC(Core)

V_SS(I/O)

V_CC(I/O)

AD11

V_CC(I/O)

V_SS(I/O)

WIDTH/HLTD1

V_CC(Core)

V_SS(Core)

WIDTH/HLTD0

AD30

AD29

STEST

V_CC(I/O)

TDI

AD28

AD10

_SS(I/O)

V_SS(I/O)

V_CC(I/O)

AD9

V_CC(I/O)

AD27

V_SS(I/O)

RDYRCV

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

PRODUCT PREVIEW

80960JD

Similarly, if T_Ais known, the corresponding case

temperature (T_C) can be calculated as follows:

3.2 Package Thermal Specifications

The 80960JD is specified for operation when T_C

(case temperature) is within the range of 0°C to

100°C for both PGA and PQFP packages. Case

temperature may be measured in any environment

to determine whether the 80960JD is within its

specified operating range. The case temperature

should be measured at the center of the top surface,

opposite the pins.

T_C= T_A+ P (θ_CA

Compute P by multiplying I_CCfrom Table 14 and

_CC. Values for θ_JCand θ_CAare given in Table 10

)

for the PGA package and Table 11 for the PQFP

package. For high speed operation, the processor’s

θ_JAmay be significantly reduced by adding

heatsink and/or by increasing airflow.

θ_CAis the thermal resistance from case to ambient.

Use the following equation to calculate T_A, the

maximum ambient temperature to conform to a

particular case temperature:

Table 12 shows the maximum ambient temperature

(T_A) permitted without exceeding T_Cfor both PGA

and PQFP packages. The values are based on

typical I_CCand V_CCof +3.3 V, with a T_CASEof

+100°C.

_A= T_C- P (θ_CA)

Junction temperature (T_J) is commonly used in

reliability calculations. T_Jcan be calculated from θ_JC

(thermal resistance from junction to case) using the

following equation:

T_J= T_C+ P (θ_JC

)

Table 10. 132-Lead PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

200 400 600 800

(1.01) (2.03) (3.04) (4.06) (5.08)

Parameter

1000

(0)

θ_JC(Junction-to-Case)

0.7

θ_CA(Case-to-Ambient) (No Heatsink)

θ_CA(Case-to-Ambient) (Omnidirectional Heatsink)

θ_CA(Case-to-Ambient) (Unidirectional Heatsink)

θ_JA

θ_CA

θ_JC

θ_J-PIN

θ_J-CAP

NOTES:

1. This table applies to a PGA device plugged into a socket or soldered directly into a board.

= θ + θ

= 5.6°C/W (approx.) (no heatsink)

J-CAP

J-PIN

J-CAP

J-PIN

= 6.4°C/W (inner pins) (approx.) (no heatsink)

= 6.2°C/W (outer pins) (approx.) (no heatsink)

= 3°C/W (approx.) (with heatsink)

= 3.3°C/W (inner pins) (approx.) (with heatsink)

= 3.3°C/W (outer pins) (approx.) (with heatsink)

PRODUCT PREVIEW

80960JD

Table 11. 132-Lead PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Airflow — ft./min (m/sec)

Parameter

100

200

400

600

800

1000

(0)

(0.25) (0.50) (1.01) (2.03) (3.04) (4.06) (5.08)

θ_JC(Junction-to-Case)

4.1

4.3

4.7

4.9

5.3

θ_CA(Case-to-Ambient -No Heatsink)

θ_CA

θ_JA

θ_JC

θ_JB

θ_JL

NOTES:

1. This table applies to a PQFP device soldered directly into board.

= θ

+ θ

JC CA

= 13°C/W (approx.)

= 13.5°C/W (approx.)

PRODUCT PREVIEW

80960JD

Table 12. Maximum T_Aat Various Airflows in °C

Airflow-ft/min (m/sec)

400 600

200

800

1000

f_CLKIN(MHz)

(0)

(1.01) (2.03) (3.04) (4.06) (5.07)

_Awithout Heatsink

PQFP

Package

T_Awith Omni Heatsink¹

PGA

Package

T_Awith Uni-directional

Heatsink²

1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41mil fin width, 124 mil center-to-center fin spacing)

2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing)

3.3 Thermal Management Accessories

The following is a list of suggested sources for 80960JD thermal solutions. This is neither an endorsement or a

warranty of the performance of any of the listed products and/or companies.

Heatsinks

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75234-8993

(214) 243-4321 FAX: (214) 241-4656

2. Wakefield Engineering

60 Audubon Road

Wakefield, MA 01880

(617) 245-5900

3. Aavid Thermal Technologies, Inc.

One Kool Path

Laconia, NH 03247-0400

(603) 528-3400

PRODUCT PREVIEW

80960JD

4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings

NOTICE: This document contains information on

products in the design phase of development. Do

not finalize a design with this information. Revised

information will be published when the product

becomes available. Verify with your local Intel

sales office that you have the latest datasheet

before finalizing a design.

Parameter

Maximum Rating

Storage Temperature

–65 C to +150 C

WARNING: Stressing the device beyond the

“Absolute Maximum Ratings” may cause perma-

nent damage. These are stress ratings only. Oper-

ation beyond the “Operating Conditions” is not

recommended and extended exposure beyond the

“Operating Conditions” may affect device reli-

ability.

Case Temperature Under Bias

Supply Voltage wrt. V_SS

Voltage on V_CC5wrt. V_SS

Voltage on Other Pins wrt. V_SS

–65 C to +110 C

–0.5 V to + 4.6 V

–0.5 V to + 6.5 V

–0.5 V to V + 0.5 V

4.2 Operating Conditions

Table 13. 80960JD Operating Conditions

Symbol

V_CC

Parameter

Supply Voltage

Min

3.15

Max

3.45

5.5

Units

Notes

V_CC5

Input Protection Bias

Input Clock Frequency

(1)

CLKIN

80960JD-66

80960JD-50

80960JD-40

33.3

MHz

T_C

Operating Case Temperature (PGA

and PQFP)

100

°C

NOTES:

1. See Section 4.4, V_CC5Pin Requirements (V_DIFF) (pg. 23)

Pay special attention to the Test Reset (TRST) pin. It

is essential that the JTAG Boundary Scan Test

Access Port (TAP) controller initializes to a known

state whether it will be used or not. If the JTAG

Boundary Scan function will be used, connect a

pulldown resistor between the TRST pin and V_SS. If

the JTAG Boundary Scan function will not be used

(even for board-level testing), connect the TRST pin

to V_SS. Also, do not connect the TDI, TDO, and TCK

pins if the TAP Controller will not be used.

4.3 Connection Recommendations

For clean on-chip power distribution, V_CCand V_SS

pins separately feed the device’s functional units.

Power and ground connections must be made to all

80960JD power and ground pins. On the circuit

board, every V_CCpin should connect to a power

plane and every V_SSpin should connect to a ground

plane. Place liberal decoupling capacitance near the

80960JD, since the processor can cause transient

power surges.

Pins identified as NC must not be connected in

the system.

PRODUCT PREVIEW

80960JD

As shown in Figure 6, place a 100Ω resistor in series

4.4 V_CC5Pin Requirements (V_DIFF

)

with the V_CC5pin to limit the current through V_CC5

In mixed voltage systems where the processor is

components, V_CC5must be connected to 5 volts.

This allows proper 5 volt tolerant buffer operation,

and prevents damage to the input pins. The voltage

differential between the 80960Jx V_CC5pin and its 3.3

volt V_CCpins must not exceed 2.25 volts. If this

requirement is not met, current flow through the pin

may exceed the value at which the processor is

damaged. Instances when the voltage can exceed

2.25 volts is during power up or power down, where

one source reaches its level faster than the other,

briefly causing an excess voltage differential.

Another instance is during steady-state operation,

where the differential voltage of the regulator

(provided a regulator is used) cannot be maintained

within 2.25 volts. Two methods are possible to

prevent this from happening:

_CC5Pin

+5 V (±0.25 V)

100 Ω

(±5%, 0.5 W)

Figure 6. V_CC5Current-Limiting Resistor

• If the regulator cannot prevent the 2.25 volt differ-

ential, the addition of the resistor is a simple and

reliable method for limiting current. The resistor

can also prevent damage in the case of a power

failure, where the 5 volt supply remains on and the

3.3 volt supply goes to zero.

• Use a regulator that is designed to prevent the

voltage differential from exceeding 2.25 volts, or,

In 3.3 volt only systems where the 80960Jx input

pins are driven from 3.3 volt logic, connect the V_CC5

pin directly to the 3.3 volt V_CCplane.

Symbol

Parameter

Min

Max

Units

Notes

V_DIFF

V_CC5-V_CC

Difference

2.25

V_CC5input should not exceed V_CCby more than 2.25 V

during power-up and power-down, or during steady-state

operation.

tantalum), the 0.01 µF capacitor must be of the type

X7R and the node connecting V_CCPLLmust be as

short as possible.

4.5 V_CCPLLPin Requirements

To reduce clock jitter on the i960 Jx processor, the

V_CCPLLpin for the Phase Lock Loop (PLL) circuit is

isolated on the pinout. The lowpass filter, as shown

in Figure 7, reduces noise induced clock jitter and its

effects on timing relationships in system designs.

The 4.7 µF capacitor must be (low ESR solid

100

Ω (±5%, 1/8 W)

V_CCPLL

(On i960 Jx processors)

V_CC

(Board Plane)

4.7µF

0.01µF

F_CA078A

Figure 7. V_CCPLLLowpass Filter

PRODUCT PREVIEW

80960JD

4.6 DC Specifications

Table 14. 80960JD DC Characteristics

Symbol

V_IL

Parameter

Input Low Voltage

Input High Voltage

Output Low Voltage

Min

-0.3

2.0

Typ

Max

0.8

Units

Notes

V_IH

V_CC5+ 0.3

0.4

V_OL

I_OL= 3 mA

_OL= 100 µA

I_OH= -1 mA

_OH= -200 µA

0.2

V_OH

Output High Voltage

2.4

_CC- 0.2

V_OLP

C_IN

Output Ground Bounce

TBD

(1,2)

Input Capacitance

PGA

PQFP

= f_MIN(2)

CLKIN

C_OUT

I/O or Output Capacitance

PGA

PQFP

CLKIN

C_CLK

CLKIN Capacitance

PGA

PQFP

= f_MIN(2)

CLKIN

NOTES:

1. Typical is measured with V_CC= 3.3 V and temperature = 25 °C.

2. Not tested.

PRODUCT PREVIEW

80960JD

Table 15. 80960JD I_CCCharacteristics

Symbol

Parameter

Typ

Max

Units

Notes

0 ≤ V_IN≤ V_CC

I_LI1

Input Leakage Current for

each pin except TCK, TDI,

TRST and TMS

± 1

µA

I_LI2

Input Leakage Current for

TCK, TDI, TRST and TMS

-140

-250

µA

V_IN= 0.45V (1)

I_LO

Output Leakage Current

± 1

µA

kΩ

0.4 ≤ V_OUT≤ V_CC

R_pu

Internal Pull-UP

Resistance for ONCE,

TMS, TDI and TRST

I_CCActive

(Power Supply)

80960JD-66

80960JD-50

80960JD-40

790

600

500

(2,3)

I_CCActive

(Thermal)

80960JD-66

80960JD-50

80960JD-40

720

540

435

(2,4)

I_CCTest

(Power modes)

Reset mode

80960JD-66

80960JD-50

80960JD-40

Halt mode

703

535

430

(5)

80960JD-66

80960JD-50

80960JD-40

ONCE mode

(5)

I_{CC 5}Current on the

80960JD-66

80960JD-50

80960JD-40

200

µA

(6)

_CC5Pin

PRODUCT PREVIEW

80960JD

4.7 AC Specifications

The 80960JD AC timings are based upon device characterization.

Table 16. 80960JD AC Characteristics (Sheet 1 of 2)

Symbol

T_F

Parameter

Min

Max

Units

Notes

INPUT CLOCK TIMINGS

CLKIN Frequency

80960JD-66

80960JD-50

80960JD-40

33.3

MHz

T_c

CLKIN Period

80960JD-66

80960JD-50

83.3

80960JD-40

83.3

T_CS

T_CH

T_CL

T_CR

T_CF

CLKIN Period Stability

CLKIN High Time

CLKIN Low Time

CLKIN Rise Time

CLKIN Fall Time

± 250

(1, 2)

Measured at 1.5 V (1)

0.8 V to 2.0 V (1)

2.0 V to 0.8 V (1)

SYNCHRONOUS OUTPUT TIMINGS

T_OV1

Output Valid Delay, Except ALE/ALE

Inactive and DT/R for 3.3V input sig-

nals.

2.5

13.5

(3)

Same as above, but for 5.5V input

signals.

2.5

16.5

T_OV2

T_OF

Output Valid Delay, DT/R

0.5T_C+ 7

0.5T_C

Output Float Delay

2.5

13.5

(4)

SYNCHRONOUS INPUT TIMINGS

T_IS1

T_IH1

T_IS2

T_IH2

Input Setup to CLKIN — AD31:0,

NMI, XINT7:0

(5)

(6)

Input Hold from CLKIN — AD31:0,

NMI, XINT7:0

1.5

6.5

Input Setup to CLKIN — RDYRCV

and HOLD

Input Hold from CLKIN — RDYRCV

and HOLD

T_IS3

T_IH3

T_IS4

Input Setup to CLKIN — RESET

Input Hold from CLKIN — RESET

(7)

(8)

Input Setup to RESET — ONCE,

STEST

T_IH4

Input Hold from RESET — ONCE,

STEST

(8)

NOTES: See Table 17 on page 28 for note definitions for this table.

PRODUCT PREVIEW

80960JD

Table 16. 80960JD AC Characteristics (Sheet 2 of 2)

Symbol

T_LX

Parameter

Min

Max

Units

Notes

RELATIVE OUTPUT TIMINGS

Address Valid to ALE/ALE Inactive

ALE/ALE Width

0.5T_C- 5

0.5T_C- 7

T_LXL

T_LXA

T_DXD

(9)

Address Hold from ALE/ALE Inactive

DT/R Valid to DEN Active

Equal Loading (9)

BOUNDARY SCAN TEST SIGNAL TIMINGS

T_BSF

TCK Frequency

TCK High Time

TCK Low Time

TCK Rise Time

TCK Fall Time

0.5T_F

MHz

T_BSCH

T_BSCL

T_BSCR

T_BSCF

T_BSIS1

T_BSIH1

T_BSOV1

T_BSOF1

T_BSOV2

T_BSOF2

T_BSIS2

Measured at 1.5 V (1)

0.8 V to 2.0 V (1)

2.0 V to 0.8 V (1)

Input Setup to TCK — TDI, TMS

Input Hold from TCK — TDI, TMS

TDO Valid Delay

(1,10)

TDO Float Delay

All Outputs (Non-Test) Valid Delay

All Outputs (Non-Test) Float Delay

Input Setup to TCK — All Inputs

(Non-Test)

T_BSIH2

Input Hold from TCK — All Inputs

(Non-Test)

NOTES: See Table 17 on page 28 for note definitions for this table.

PRODUCT PREVIEW

80960JD

NOTES:

Table 17. Note Definitions for Table 16, 80960JD AC Characteristics (pg. 26)

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN

frequency.

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than I . Float delay is not tested, but is

designed to be no longer than the valid delay.

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI

and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-

nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a

minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a

particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10. Relative to falling edge of TCK.

11. Worst-case T_OVcondition occurs on I/O pins when pins transition from a floating high input to driving a

low output state. The Address/Data Bus pins encounter this condition between the last access of a read,

and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at

50 pF loads.

PRODUCT PREVIEW

80960JD

4.7.1 AC Test Conditions and Derating Curves

The AC Specifications in Section 4.7, AC Specifi-

cations are tested with the 50 pF load indicated in

Figure 8. Figure 9 shows how timings vary with load

capacitance; Figure 11 shows how output rise and

fall times vary with load capacitance.

Output Pin

= 50 pF for all signals

Figure 8. AC Test Load

Capacitance

AC timings vs. load Cap

nom + 25

nom + 20

nom + 15

nom + 10

nom + 5

Rising

Falling

nom + 0

100

150

200

250

300

C_L(pF)

CL (pF)

Figure 9. Output Delay or Hold vs. Load Capacitance

PRODUCT PREVIEW

80960JD

4.7.2 AC Timing Waveforms

2.0V

1.5V

0.8V

Figure 10. CLKIN Waveform

1.5V

OV1

1.5V

CLKIN

AD31:0,

ALE (active),

1.5V

ADS, A3:2,

BE3:0,

WIDTH/HLTD1:0,

D/C, W/R, DEN,

BLAST, LOCK,

HOLDA, BSTAT, FAIL

Figure 11. Output Delay Waveform for T_OV1

PRODUCT PREVIEW

80960JD

1.5V

CLKIN

AD31:0,

ALE, ALE

ADS, A3:2,

BE3:0,

WIDTH/HLTD1:0,

D/C, W/R, DT/R,

DEN, BLAST, LOCK

Figure 12. Output Float Waveform for T_OF

1.5V

IH1

1.5V

CLKIN

IS1

AD31:0

NMI

Valid

1.5V

XINT7:0

Figure 13. Input Setup and Hold Waveform for T

and T

IH1

IS1

PRODUCT PREVIEW

80960JD

1.5V

CLKIN

IH2

IS2

HOLD,

1.5V

Valid

1.5V

RDYRCV

Figure 14. Input Setup and Hold Waveform for T

and T

IH2

IS2

1.5V

CLKIN

IS3

IH3

RESET

Figure 15. Input Setup and Hold Waveform for T

and T

IH3

IS3

PRODUCT PREVIEW

80960JD

RESET

IH4

IS4

ONCE,

STEST

Valid

Figure 16. Input Setup and Hold Waveform for T

and T

IH4

IS4

T /T

1.5V

CLKIN

LXL

ALE

1.5V

Valid

1.5V

LXA

1.5V

AD31:0

Valid

Figure 17. Relative Timings Waveform for T , T

LX LXL

and T

LXA

PRODUCT PREVIEW

80960JD

T /T

w d

CLKIN

1.5V

OV2

Valid

DT/R

DEN

DXD

OV1

Figure 18. DT/R and DEN Timings Waveform

BSCR

BSCF

2.0V

1.5V

0.8V

BSCH

BSCL

Figure 19. TCK Waveform

PRODUCT PREVIEW

80960JD

1.5V

TCK

BSIH1

BSIS1

TMS

TDI

1.5V

Valid

1.5V

Figure 20. Input Setup and Hold Waveforms for T

and T

BSIS1

BSIH1

TCK

1.5V

BSOV1

BSOF1

Valid

1.5V

TDO

Figure 21. Output Delay and Output Float Waveform for T

BSOV1

AND T

BSOF1

PRODUCT PREVIEW

80960JD

TCK

1.5V

BSOF2

BSOV2

Non-Test

Outputs

Valid

1.5V

Figure 22. Output Delay and Output Float Waveform for T

and T

BSOF2

BSOV2

TCK

1.5V

BSIH2

BSIS2

Non-Test

Inputs

1.5V

Valid

1.5V

Figure 23. Input Setup and Hold Waveform for T

and T

BSIS2

BSIH2

PRODUCT PREVIEW

80960JD

33 illustrates the processor ONCE sequence from

the time power is applied to the device. Figures 34

and 35 also show accesses on 32-bit buses. Tables

18 through 21 summarize all possible combinations

of bus accesses across 8-, 16-, and 32-bit buses

according to data alignment.

5.0 BUS FUNCTIONAL WAVEFORMS

Figures 24 through 29 illustrate typical 80960JD bus

transactions. Figure 30 depicts the bus arbitration

sequence. Figure 31 illustrates the processor reset

sequence from the time power is applied to the

device. Figure 32 illustrates the processor reset

sequence when the processor is in operation. Figure

CLKIN

ADDR

DATA Out

Invalid

AD31:0

ALE

ADS

A3:2

BE3:0

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

F_JF030A

Figure 24. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus

PRODUCT PREVIEW

80960JD

CLKIN

DATA

Out

DATA

Out

DATA

Out

DATA

Out

ADDR

AD31:0

ALE

ADS

00 or 10

01 or 11

A3:2

BE3:0

1 0

WIDTH1:0

D/C

1 0

W/R

BLAST

DT/R

DEN

RDYRCV

Figure 25. Burst Read and Write Transactions Without Wait States, 32-Bit Bus

PRODUCT PREVIEW

80960JD

CLKIN

AD31:0

ALE

DATA

Out

DATA

Out

DATA

Out

DATA

Out

ADDR

ADS

A3:2

0 0

0 1

1 0

1 1

BE3:0

WIDTH1:0

D/C

1 0

W/R

BLAST

DT/R

DEN

RDYRCV

F_JF032A

Figure 26. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus

PRODUCT PREVIEW

80960JD

CLKIN

DATA

Out

DATA

Out

DATA DATA

ADDR

AD31:0

Out

ALE

ADS

A3:2

00,01,10 or 11

01 or

BE1/A1

BE0/A0

00 or 10

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

F_JF033A

Figure 27. Burst Read and Write Transactions Without Wait States, 8-Bit Bus

PRODUCT PREVIEW

80960JD

CLKIN

AD31:0

ALE

DATA

Out

DATA

Out

ADDR

ADS

00,01,10, or 11

A3:2

BE1/A1

BE3/BHE

BE0/BLE

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

F_JF034A

RDYRCV

Figure 28. Burst Read and Write Transactions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus

PRODUCT PREVIEW

80960JD

CLKIN

AD31:0

ALE

ADS

A3:2

BE3:0

WIDTH1:0

D/C

0 0 0 0

1 1 1 0

0 0 1 1

1 1 0 1

1 0

Valid

W/R

BLAST

DT/R

DEN

RDYRCV

Figure 29. Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian

PRODUCT PREVIEW

80960JD

T or T

i a

CLKIN

Outputs:

AD31:0,

ALE, ALE,

ADS, A3:2,

BE3:0,

Valid

WIDTH/HLTD1:0,

D/C, W/R,

DT/R, DEN,

BLAST, LOCK

HOLD

HOLDA

(Note)

NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the

same edge in which it recognizes HOLD if the last state was T or the last T of a bus transaction. Similarly,

the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.

Figure 30. HOLD/HOLDA Waveform For Bus Arbitration

PRODUCT PREVIEW

80960JD

Figure 31. Cold Reset Waveform

PRODUCT PREVIEW

80960JD

Figure 32. Warm Reset Waveform

PRODUCT PREVIEW

80960JD

Figure 33. Entering the ONCE State

PRODUCT PREVIEW

80960JD

Table 18. Natural Boundaries for Load and Store Accesses

Data Width

Byte

Natural Boundary (Bytes)

Short Word

Word

Double Word

Triple Word

Quad Word

Table 19. Summary of Byte Load and Store Accesses

Address Offset from

Natural Boundary

(in Bytes)

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit

Bus (WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)

• byte access

Table 20. Summary of Short Word Load and Store Accesses

Address Offset from

Natural Boundary

(in Bytes)

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit

Bus (WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)

• burst of 2 bytes

• 2 byte accesses

• short-word access

• 2 byte accesses

• short-word access

• 2 byte accesses

PRODUCT PREVIEW

80960JD

Table 21. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)

Address Offset

from Natural

Boundary in Bytes

Accesses on 8-Bit Bus

(WIDTH1:0=00)

Accesses on 16 Bit Bus

(WIDTH1:0=01)

Accesses on 32 Bit

Bus (WIDTH1:0=10)

+0 (aligned)

• n burst(s) of 4 bytes

• case n=1:

• burst of n word(s)

(n =1, 2, 3, 4)

burst of 2 short words

• case n=2:

burst of 4 short words

• case n=3:

burst of 4 short words

burst of 2 short words

• case n=4:

2 bursts of 4 short words

+1 (n =1, 2, 3, 4)

+5 (n = 2, 3, 4)

+9 (n = 3, 4)

• byte access

• short-word access

• n-1 burst(s) of 2 short words • n-1 word access(es)

• byte access

• short-word access

• burst of 2 bytes

• n-1 burst(s) of 4 bytes

• byte access

+13 (n = 3, 4)

• byte access

+2 (n =1, 2, 3, 4)

+6 (n = 2, 3, 4)

+10 (n = 3, 4)

+14 (n = 3, 4)

• burst of 2 bytes

• n-1 burst(s) of 4 bytes

• burst of 2 bytes

• short-word access

• n-1 burst(s) of 2 short words • n-1 word access(es)

• short-word access

+3 (n =1, 2, 3, 4)

+7 (n = 2, 3, 4)

+11 (n = 3, 4)

+15 (n = 3, 4)

• byte access

• n-1 burst(s) of 2 short words • n-1 word access(es)

• short-word access

• byte access

• n-1 burst(s) of 4 bytes

• burst of 2 bytes

• byte access

• short-word access

• byte access

+4 (n = 2, 3, 4)

+8 (n = 3, 4)

• n burst(s) of 4 bytes

• n burst(s) of 2 short words

• n word access(es)

+12 (n = 3, 4)

PRODUCT PREVIEW

80960JD

Byte Offset

Word Offset

Short Access (Aligned)

Byte, Byte Accesses

Short-Word

Load/Store

Short Access (Aligned)

Byte, Byte Accesses

Word Access (Aligned)

Byte, Short, Byte, Accesses

Short, Short Accesses

Word

Load/Store

Byte, Short, Byte Accesses

One Double-Word Burst (Aligned)

Byte, Short, Word, Byte Accesses

Short, Word, Short Accesses

Double-Word

Load/Store

Byte, Word, Short, Byte Accesses

Word, Word Accesses

One Double-Word

Burst (Aligned)

Figure 34. Summary of Aligned and Unaligned Accesses (32-Bit Bus)

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80960JD

Byte Offset

Word Offset

One Three-Word

Burst (Aligned)

Byte, Short, Word,

Word, Byte Accesses

Short, Word, Word,

Short Accesses

Triple-Word

Load/Store

Byte, Word, Word,

Short, Byte Accesses

Word, Word,

Word Accesses

Word, Word,

Word Accesses

Word,

Word

Accesses

One Four-Word

Burst (Aligned)

Byte, Short, Word, Word,

Word, Byte Accesses

Short, Word, Word, Word,

Short Accesses

Quad-Word

Load/Store

Byte, Word, Word, Word,

Short, Byte Accesses

Word, Word, Word,

Word Accesses

Word,

Accesses

Figure 35. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)

PRODUCT PREVIEW

80960JD

• Upon reset, the identifier is placed into the g0

6.0 DEVICE IDENTIFICATION

80960JD processors may be identified electrically,

according to device type and stepping (see Figure

36, and Table 22 through Table 25). Table 22

identifies the device ID for all 3.3 V and 5 V,

80960JD processors. Figure 36, and Table 23

through Table 25 identify all 3.3 V, 5 V-tolerant,

80960JD processors. The device ID for the C0

stepping is enhanced to differentiate between 3.3 V

and 5 V supply voltages, and between non-clock-

doubled and clock-doubled cores when stepping

from the A2 stepping to the C0 stepping. The 32-bit

identifier is accessible in three ways:

• The identifier may be accessed from supervisor

mode at any time by reading the DEVICE ID

• The IEEE Standard 1149.1 Test Access Port may

select the DEVICE ID register through the

IDCODE instruction.

• The device and stepping letter is also printed on

the top side of the product package.

Table 22. 80960JD Die and Stepping Reference

Device and

Stepping

Version

Number

Complete ID

(Hex)

Part Number

Manufacturer

80960JD A, A2

80960JD C0

0000

0011

1000 1000 0010 0000

0000 1000 0011 0000

0000 0001 001

08820013

30830013

Part Number

Product

Type

V_CC

Version

Gen

Model

Manufacturer ID

0 1

Figure 36. 80960JD Device Identification Register

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80960JD

Table 23. Fields of 80960JD Device ID

Value

Field

Definition

Version

V_CC

See Table 25

Indicates major stepping changes.

0 = 3.3 V device

1 = 5V device

Indicates that a device is 3.3 V or 5.0 V.

Product Type

00 0100

Designates type of product.

(Indicates i960 CPU)

Generation Type 0001 = J-series

Indicates the generation (or series) of product.

Model

D000C

Indicates member within a series and specific model

information.

D = Clock Doubled

(0) Not Clock-Doubled

(1) Clock Doubled

C = Cache Size

(0) 4K I-cache, 2K D-cache

(1) 2K I-cache, 1K D-cache

Manufacturer ID 000 0000 1001

(Indicates Intel)

Manufacturer ID assigned by IEEE.

Table 24. 80960JD Device ID Model Types

Device

Version V_CC

Product

000100

Gen.

0001

Model

00000

10000

Manufacturer ID

00000001001

‘1’

80960JD A, A2

80960JD C0

See

Table 25

Table 25. Device ID Version Numbers for Different Steppings

Stepping

Version

0000

0011

NOTE: This data sheet applies to the 80960JD C0 stepping.

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80960JD

7.0 REVISION HISTORY

This is the first revision of the 3.3 V device.

PRODUCT PREVIEW

A80960JD-66 [INTEL]

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