AD80583QH046003_技术文档

Intel® Xeon® Processor 7400 Series

Datasheet

October 2008

Order Number: 320335, Revision: -003

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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

The Intel® Xeon® Processor 7400 Series may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

2

I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed

2

by Intel. Implementations of the I C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and

North American Philips Corporation.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be

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Intel 64 (Formerly called Intel EM64T) requires a computer system with a processor, chipset, BIOS, OS, device drivers and

applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS.

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2

Intel® Xeon® Processor 7400 Series Datasheet

Contents

1

Introduction..............................................................................................................9

1.1

1.2

1.3

Terminology ..................................................................................................... 11

State of Data.................................................................................................... 13

References ....................................................................................................... 13

2

Electrical Specifications........................................................................................... 15

2.1

2.2

Front Side Bus and GTLREF ................................................................................ 15

Decoupling Guidelines........................................................................................ 16

2.2.1 VCC Decoupling...................................................................................... 16

2.2.2 VTT Decoupling...................................................................................... 16

2.2.3 Front Side Bus AGTL+ Decoupling ............................................................ 16

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking....................................... 16

2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0]).................................. 17

2.3.2 PLL Power Supply................................................................................... 18

Voltage Identification (VID) ................................................................................ 18

Reserved, Unused, or Test Signals....................................................................... 20

Front Side Bus Signal Groups.............................................................................. 20

CMOS Asynchronous and Open Drain Asynchronous Signals.................................... 22

Test Access Port (TAP) Connection....................................................................... 22

Mixing Processors.............................................................................................. 23

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10 Absolute Maximum and Minimum Ratings ............................................................. 23

2.11 Processor DC Specifications ................................................................................ 24

2.11.1 Flexible Motherboard Guidelines (FMB)...................................................... 24

2.11.2 V_CCOvershoot Specification..................................................................... 33

2.11.3 Die Voltage Validation............................................................................. 33

2.11.4 Platform Environmental Control Interface (PECI) DC Specifications................ 34

2.11.4.1 DC Characteristics..................................................................... 34

2.11.4.2 Input Device Hysteresis............................................................. 35

2.12 AGTL+ FSB Specifications................................................................................... 35

2.13 Front Side Bus AC Specifications ......................................................................... 37

2.14 Processor AC Timing Waveforms ......................................................................... 41

3

Mechanical Specifications........................................................................................ 51

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Package Mechanical Drawing............................................................................... 51

Processor Component Keepout Zones................................................................... 54

Package Loading Specifications ........................................................................... 60

Package Handling Guidelines............................................................................... 61

Package Insertion Specifications.......................................................................... 61

Processor Mass Specifications ............................................................................. 61

Processor Materials............................................................................................ 61

Processor Markings............................................................................................ 62

Processor Pin-Out Coordinates ............................................................................ 63

4

Pin Listing ............................................................................................................... 65

4.1

Processor Pin Assignments ................................................................................. 65

4.1.1 Pin Listing by Pin Name........................................................................... 65

4.1.2 Pin Listing by Pin Number........................................................................ 73

5

6

Signal Definitions .................................................................................................... 81

5.1 Signal Definitions .............................................................................................. 81

Thermal Specifications ............................................................................................ 89

6.1

Package Thermal Specifications........................................................................... 89

6.1.1 Thermal Specifications ............................................................................ 89

6.1.2 Thermal Metrology ................................................................................. 97

Intel® Xeon® Processor 7400 Series Datasheet

3

6.2

6.3

Processor Thermal Features ................................................................................97

6.2.1 Intel® Thermal Monitor Features ..............................................................97

6.2.2 Intel Thermal Monitor..............................................................................97

6.2.3 Intel Thermal Monitor 2...........................................................................98

6.2.4 On-Demand Mode...................................................................................99

6.2.5 PROCHOT# Signal ................................................................................100

6.2.6 FORCEPR# Signal .................................................................................100

6.2.7 THERMTRIP# Signal..............................................................................100

Platform Environment Control Interface (PECI) ....................................................101

6.3.1 Introduction.........................................................................................101

6.3.1.1 TCONTROL and Tcc Activation on PECI-Based Systems.................102

6.3.1.2 Processor Thermal Data Sample Rate and Filtering.......................102

6.3.2 PECI Specifications ...............................................................................103

6.3.2.1 PECI Device Address................................................................103

6.3.2.2 PECI Command Support...........................................................103

6.3.2.3 PECI Fault Handling Requirements.............................................103

6.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support.................104

7

Features ................................................................................................................105

7.1

7.2

Power-On Configuration Options ........................................................................105

Clock Control and Low Power States...................................................................105

7.2.1 Normal State .......................................................................................106

7.2.2 HALT or Extended HALT State.................................................................106

7.2.2.1 HALT State.............................................................................106

7.2.2.2 Extended HALT State...............................................................106

7.2.3 Stop-Grant State ..................................................................................108

7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant

Snoop State.........................................................................................109

7.2.4.1 HALT Snoop State, Stop Grant Snoop State ................................109

7.2.4.2 Extended HALT Snoop State .....................................................109

Enhanced Intel SpeedStep® Technology.............................................................109

System Management Bus (SMBus) Interface .......................................................110

7.4.1 SMBus Device Addressing ......................................................................111

7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions.......................112

7.4.3 Processor Information ROM (PIROM) .......................................................113

7.4.3.1 Header ..................................................................................115

7.4.3.2 Processor Data........................................................................119

7.4.3.3 Processor Core Data ................................................................121

7.4.3.4 Cache Data ............................................................................124

7.4.3.5 Package Data .........................................................................126

7.4.3.6 Part Number Data ...................................................................127

7.4.3.7 Thermal Reference Data...........................................................129

7.4.3.8 Feature Data ..........................................................................130

7.4.3.9 OD: Other Data.......................................................................131

7.4.4 Checksums ..........................................................................................132

7.4.5 Scratch EEPROM...................................................................................132

7.3

7.4

8

9

Debug Tools Specifications ....................................................................................133

8.1

8.2

Debug Port System Requirements......................................................................133

Logic Analyzer Interface (LAI) ...........................................................................133

8.2.1 Mechanical Considerations .....................................................................133

8.2.2 Electrical Considerations........................................................................134

Boxed Processor Specifications..............................................................................135

9.1

9.2

Introduction....................................................................................................135

Thermal Specifications......................................................................................135

9.2.1 Boxed Processor Cooling Requirements....................................................135

4

Intel® Xeon® Processor 7400 Series Datasheet

Figures

2-1

Intel® Xeon® X7460 Processor Load Current versus Time...................................... 28

Intel® Xeon® Processor E7400 Series Load Current versus Time ............................ 28

Intel® Xeon® Processor L7400 Series Load Current versus Time............................. 29

VCC Static and Transient Tolerance Load Lines...................................................... 31

VCC Overshoot Example Waveform...................................................................... 33

Input Device Hysteresis ..................................................................................... 35

Electrical Test Circuit ......................................................................................... 41

TCK Clock Waveform ......................................................................................... 42

Differential Clock Waveform................................................................................ 42

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10 Differential Clock Crosspoint Specification............................................................. 42

2-11 BCLK Waveform at Processor Pad and Pin............................................................. 43

2-12 FSB Common Clock Valid Delay Timing Waveform ................................................. 43

2-13 FSB Source Synchronous 2X (Address) Timing Waveform ....................................... 44

2-14 FSB Source Synchronous 4X (Data) Timing Waveform............................................ 45

2-15 TAP Valid Delay Timing Waveform ....................................................................... 46

2-16 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform............... 46

2-17 THERMTRIP# Power Down Sequence ................................................................... 46

2-18 SMBus Timing Waveform.................................................................................... 47

2-19 SMBus Valid Delay Timing Waveform ................................................................... 47

2-20 Voltage Sequence Timing Requirements ............................................................... 48

2-21 FERR#/PBE# Valid Delay Timing ......................................................................... 48

2-22 VID Step Timings .............................................................................................. 49

2-23 VID Step Times and Vcc Waveforms .................................................................... 49

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

Processor Package Assembly Sketch .................................................................... 51

Intel® Xeon® Processor 7400 Series Package Drawing (Sheet 1 of 2)...................... 52

Intel® Xeon® Processor 7400 Series Package Drawing (Sheet 2 of 2)...................... 53

Top Side Board Keepout Zones (Part 1)................................................................ 55

Top Side Board Keepout Zones (Part 2)................................................................ 56

Bottom Side Board Keepout Zones....................................................................... 57

Board Mounting-Hole Keepout Zones ................................................................... 58

Volumetric Height Keep-Ins ................................................................................ 59

Processor Topside Markings ................................................................................ 62

3-10 Processor Bottom-Side Markings ......................................................................... 62

3-11 Processor Pin-Out Coordinates, Top View.............................................................. 63

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

7-1

7-2

Intel® Xeon® X7460 Processor Thermal Profile..................................................... 91

6-Core Intel® Xeon® Processor E7400 Series Thermal Profile................................. 93

4-Core Intel® Xeon® Processor E7400 Series Thermal Profile................................. 94

6-Core Intel® Xeon® Processor L7400 Series Thermal Profile ................................. 95

4-Core Intel® Xeon® Processor L7400 Series Thermal Profile ................................. 96

Case Temperature (TCASE) Measurement Location ................................................ 97

Intel Thermal Monitor 2 Frequency and Voltage Ordering........................................ 99

PECI Topology ................................................................................................ 101

Conceptual Fan Control Diagram For a PECI-Based Platform.................................. 102

Stop Clock State Machine ................................................................................. 108

Logical Schematic of SMBus Circuitry ................................................................. 111

Intel® Xeon® Processor 7400 Series Datasheet

5

Tables

1-1

Processor Features.............................................................................................10

Core Frequency to Multiplier Configuration ............................................................17

BSEL[2:0] Frequency Table.................................................................................17

Voltage Identification Definition ...........................................................................19

FSB Signal Groups .............................................................................................21

AGTL+ Signal Description Table...........................................................................22

Non AGTL+ Signal Description Table.....................................................................22

Signal Reference Voltages...................................................................................22

Processor Absolute Maximum Ratings...................................................................23

Voltage and Current Specifications.......................................................................24

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10 VCC Static and Transient Tolerance......................................................................30

2-11 AGTL+ Signal Group DC Specifications..................................................................31

2-12 CMOS Signal Input/Output Group DC Specifications................................................32

2-13 Open Drain Signal Group DC Specifications ...........................................................32

2-14 SMBus Signal Group DC Specifications..................................................................32

2-15 VCC Overshoot Specifications..............................................................................33

2-16 PECI DC Electrical Limits.....................................................................................34

2-17 AGTL+ Bus Voltage Definitions ............................................................................36

2-18 FSB Differential BCLK Specifications .....................................................................36

2-19 Front Side Bus Differential Clock AC Specifications .................................................37

2-20 Front Side Bus Common Clock AC Specifications ....................................................37

2-21 FSB Source Synchronous AC Specifications............................................................38

2-22 Miscellaneous GTL+ AC Specifications...................................................................39

2-23 Front Side Bus AC Specifications (Reset Conditions) ...............................................39

2-24 TAP Signal Group AC Specifications ......................................................................40

2-25 VID Signal Group AC Specifications ......................................................................40

2-26 SMBus Signal Group AC Specifications..................................................................40

3-1

3-2

3-3

4-1

4-2

5-1

6-1

6-2

6-3

6-4

6-5

6-6

6-7

7-1

7-2

7-3

7-4

7-5

7-6

7-7

Processor Loading Specifications..........................................................................60

Package Handling Guidelines...............................................................................61

Processor Materials ............................................................................................61

Pin Listing by Pin Name ......................................................................................65

Pin Listing by Pin Number ...................................................................................73

Signal Definitions...............................................................................................81

Processor Thermal Specifications .........................................................................91

Intel® Xeon® X7460 Processor Thermal Profile Table.............................................92

6-Core Intel® Xeon® Processor E7400 Series Thermal Profile Table.........................93

4-Core Intel® Xeon® Processor E7400 Series Thermal Profile Table.........................94

6-Core Intel® Xeon® Processor L7400 Series Thermal Profile Table .........................95

4-Core Intel® Xeon® Processor L7400 Series Thermal Profile Table .........................96

GetTemp0() and GetTemp1() Error Codes...........................................................104

Power-On Configuration Option Pins...................................................................105

Extended HALT Maximum Power........................................................................107

Memory Device SMBus Addressing .....................................................................112

Read Byte SMBus Packet ..................................................................................112

Write Byte SMBus Packet..................................................................................112

Processor Information ROM Data Sections...........................................................113

128 Byte ROM Checksum Values........................................................................132

6

Intel® Xeon® Processor 7400 Series Datasheet

Revision History

Document

Revision

Number

Description

Date

320335

001

002

003

Initial Release

September 2008

October 2008

Updated Power Information

Add Boxed Processor Information

§

Intel® Xeon® Processor 7400 Series Datasheet

7

8

Intel® Xeon® Processor 7400 Series Datasheet

Introduction

1 Introduction

ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE.

The Intel® Xeon® Processor 7400 Series is a four or six core product for multi-

processor servers. The processor is a single die based on Intel’s 45 nanometer process

technology combining high performance with the power efficiencies of a low-power

microarchitecture. The processor maintains the tradition of compatibility with IA-32

software. Some key features include on-die, 32 KB Level 1 instruction data cache per

core and 3 MB of shared Level 2 cache per two processor cores with Advanced Transfer

Cache Architecture. The Intel® Xeon® Processor 7400 Series will be available with

12 MB or 16 MB of on-die level 3 (L3) cache. The processor’s Data Prefetch Logic

speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting

in reduced bus cycle penalties and improved performance. The 1066 MTS Front Side

Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making

8.5 GBytes per second data transfer rates possible.

Enhanced thermal and power management capabilities are implemented including

Intel® Thermal Monitor (TM1), Intel® Thermal Monitor 2 (TM2) and Enhanced Intel

SpeedStep® Technology. TM1 and TM2 provide efficient and effective cooling in high

temperature situations. Enhanced Intel SpeedStep Technology allows trade-offs to be

made between performance and power consumption. This may lower average power

consumption (in conjunction with OS support).

Processor features include Advanced Dynamic Execution, enhanced floating point and

multi-media units, Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3

(SSE3) and Streaming SIMD Extensions 4 (SSE4). SSE4 extends the Intel^®64

instruction set to accelerate applications that involve graphics, video, 3D imaging, and

Web services. Advanced Dynamic Execution improves speculative execution and branch

prediction internal to the processor. The floating point and multi-media units include

128-bit wide registers and a separate register for data movement. SSE3 instructions

provide highly efficient double-precision floating point, SIMD integer, and memory

management operations.

The Intel® Xeon® Processor 7400 Series supports Intel^®64 as an enhancement to

Intel's IA-32 architecture. This enhancement allows the processor to execute operating

systems and applications written to take advantage of the 64-bit extension technology.

Further details on Intel 64 and its programming model can be found in the Intel^®64

and IA-32 Intel^®Architectures Software Developer's Manual.

In addition, the Intel® Xeon® Processor 7400 Series supports the Execute Disable Bit

functionality. When used in conjunction with a supporting operating system, Execute

Disable allows memory to be marked as executable or non-executable. This feature can

prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus

help improve the overall security of the system. Further details on Execute Disable can

be found at http://www.intel.com/cd/ids/developer/asmo-na/eng/149308.htm.

The Intel® Xeon® Processor 7400 Series supports Intel^®Virtualization Technology for

hardware-assisted virtualization within the processor. Intel Virtualization Technology is

a set of hardware enhancements that can improve virtualization solutions. Intel

Virtualization Technology is used in conjunction with Virtual Machine Monitor software

enabling multiple, independent software environments inside a single platform. Further

details on Intel Virtualization Technology can be found at

http://developer.intel.com/technology/vt.

Intel® Xeon® Processor 7400 Series Datasheet

9

Introduction

Intel® Xeon® Processor 7400 Series are intended for high performance multi-

processor server systems. The processors support a Multiple Independent Bus (MIB)

architecture with one processor on each bus. The MIB architecture provides improved

performance by allowing increased FSB speeds and bandwidth. All versions of the

Intel® Xeon® Processor 7400 Series will include manageability features. Components

of the manageability features include an OEM EEPROM and Processor Information ROM

which are accessed through an SMBus interface and contain information relevant to the

particular processor and system in which it is installed. The Intel® Xeon® Processor

7400 Series is packaged in a 604-pin Flip Chip Micro Pin Grid Array (FC-mPGA8)

package and utilizes a surface-mount Zero Insertion Force (ZIF) mPGA604 socket. The

Intel® Xeon® Processor 7400 Series supports 40-bit addressing.

Table 1-1.

Processor Features

# of Processor

Cores

L1 Cache per

Core

Total L2 Advanced Total L3 Shared

1

Front Side Bus

Transfer Rate

Package

Transfer Cache

Cache

4 or 6

32 KB

instruction

32 KB data

6M or 9M

Shared L2 Cache

12M or 16M

1066 MTS

FC-mPGA8

Notes:

1.

Total accessible size of the L3 cache may vary by up to thirty-two (32) cache lines (64 bytes per line),

depending on usage and operating environment.

2.

Total accessible size of L2 caches may vary by one cache line pair (128 bytes) per core, depending on

usage and operating environment

Intel® Xeon® Processor 7400 Series-based platforms implement independent core

voltage (V_CC) power planes for each processor. FSB termination voltage (V_TT) is shared

and must connect to all FSB agents. The processor core voltage utilizes power delivery

guidelines specified by VRM/EVRD 11.0 and its associated load line (see Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design

Guidelines for further details). VRM/EVRD 11.0 will support the power requirements of

all frequencies of the processors including Flexible Motherboard Guidelines (FMB) (see

Section 2.11.1). Refer to the appropriate platform design guidelines for implementation

details.

The Intel® Xeon® Processor 7400 Series supports 1066 MTS (Mega Transfers per

Second) Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply

protocol and Source-Synchronous Transfer (SST) of address and data to improve

performance. The processor transfers data four times per bus clock (4X data transfer

rate). Along with the 4X data bus, the address bus can deliver addresses two times per

bus clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the

Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X

address bus provide a data bus bandwidth of up to 8.5 GBytes per second. The FSB is

also used to deliver interrupts.

Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.

Section 2.1 contains the electrical specifications of the FSB while implementation

details are fully described in the appropriate platform design guidelines (refer to

Section 1.3).

The Intel® Xeon® Processor 7400 Series supports Intel^®Cache Safe Technology on

the L3 cache. This provides a threshold-based mechanism for cache error reporting.

Intel recommends that fault prediction handlers rely on this mechanism to assess

processor cache health. Please refer to the Intel^®64 and IA-32 Architectures Software

Developer’s Manual, Volume 3A for more detailed information.

10

Intel® Xeon® Processor 7400 Series Datasheet

Introduction

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in

the asserted state when driven to a low level. For example, when RESET# is low, a

reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has

occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as address or data), the ‘#’ symbol implies

that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and

D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Commonly used terms are explained here for clarification:

• Intel® Xeon® Processor 7400 Series – Intel 64-bit microprocessor intended for

multi processor servers. The Intel® Xeon® Processor 7400 Series is a single die

implementation based on Intel’s 45 nanometer process, in the FC-mPGA8 package

with four or six processor cores and L3 cache.

• Processor core – Processor core with integrated L1 cache. The L2 cache is shared

between two cores on the die and interfaces to other processor pairs and the L3

cache through a simplified direct interface. All AC timing and signal integrity

specifications are at the pads of the processor die.

• FC-mPGA8 — The Intel® Xeon® Processor 7400 Series is available in a Flip-Chip

Micro Pin Grid Array 8 package, consisting of a single processor die mounted on a

pinned substrate with an integrated heat spreader (IHS). This packaging

technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.

• mPGA604 — The Intel® Xeon® Processor 7400 Series processor mates with the

system board through this surface mount, 604-pin, zero insertion force (ZIF)

socket.

• FSB (Front Side Bus) – The electrical interface that connects the processor to the

chipset. Also referred to as the processor system bus or the system bus. All

memory and I/O transactions as well as interrupt messages pass between the

processor and chipset over the FSB.

• Multi Independent Bus (MIB) – A front side bus architecture with one processor

on each bus, rather than a FSB shared between multiple processor agents. The MIB

architecture provides improved performance by allowing increased FSB speeds and

bandwidth.

• MTS - Mega Transfers per Second.

• Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum

values the Intel® Xeon® Processor 7400 Series will have over certain time periods.

The values are only estimates and actual specifications for future processors may

differ.

• Functional Operation – Refers to the normal operating conditions in which all

processor specifications, including DC, AC, FSB, signal quality, mechanical and

thermal are satisfied.

• Storage Conditions – Refers to a non-operational state. The processor may be

installed in a platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor pins should not be connected

to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure

to “free air” (that is, unsealed packaging or a device removed from packaging

material) the processor must be handled in accordance with moisture sensitivity

labeling (MSL) as indicated on the packaging material.

• Priority Agent – The priority agent is the host bridge to the processor and is

typically known as the chipset.

Intel® Xeon® Processor 7400 Series Datasheet

11

Introduction

• Symmetric Agent – A symmetric agent is a processor which shares the same I/O

subsystem and memory array, and runs the same operating system as another

processor in a system. Systems using symmetric agents are known as Symmetric

Multiprocessing (SMP) systems.

• Integrated Heat Spreader (IHS) – A component of the processor package used

to enhance the thermal performance of the package. Component thermal solutions

interface with the processor at the IHS surface.

• Thermal Design Power – Processor thermal solutions should be designed to meet

this target. It is the highest expected sustainable power while running known

power intensive real applications. TDP is not the maximum power that the

processor can dissipate.

• Platform Environment Control Interface (PECI) – A proprietary one-wire bus

interface that provides a communication channel between Intel processor and

controller components to external thermal monitoring devices, for use in fan speed

control. PECI communicates readings from the processor’s Digital Thermal Sensors

(DTS). The DTS replaces the thermal diode available in previous processors.

• Enhanced Intel SpeedStep^®Technology — Enhanced Intel SpeedStep^®

Technology is the next generation implementation of the Geyserville technology

which extends power management capabilities of servers.

• Intel^®64 – An enhancement to Intel's IA-32 architecture that allows the

processor to execute operating systems and applications written to take advantage

of the 64-bit extension technology. Further details on can be found in the 64-bit

Extension Technology Software Developer's Guide at

http://developer.intel.com/technology/64bitextensions/.

• Intel^®Virtualization Technology – Processor virtualization which when used in

conjunction with Virtual Machine Monitor software enables multiple, robust

independent software environments inside a single platform.

• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that

interfaces with a card edge socket and supplies the correct voltage and current to

the processor based on the logic state of the processor VID bits.

• EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto

the system board that provides the correct voltage and current to the processor

based on the logic state of the processor VID bits.

• V_CC– The processor core power supply.

• V_CCPLL– The processor Phase Lock Loop (PLL) power supply.

• V_SS– The processor ground.

• V_TT– FSB termination voltage. (Note: In some Intel processor EMTS documents,

V_TTis instead called V_CCP.)

• Processor Information ROM (PIROM) — A memory device located on the

processor and accessible via the System Management Bus (SMBus) which contains

information regarding the processor’s features. This device is shared with the

Scratch EEPROM, is programmed during manufacturing, and is write-protected.

• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)

— A memory device located on the processor and addressable via the SMBus which

can be used by the OEM to store information useful for system management.

• SMBus — System Management Bus. A two-wire interface through which simple

system and power management related devices can communicate with the rest of

the system. It is based on the principals of the operation of the I²C* two-wire serial

bus from Phillips Semiconductor.

12

Intel® Xeon® Processor 7400 Series Datasheet

Introduction

Note:

I²C is a two-wire communications bus/protocol developed by Phillips. SMBus is a subset

of the I²C bus/protocol and was developed by Intel. Implementations of the I²C

bus/protocol or the SMBus bus/protocol may require licenses from various entities,

including Phillips Electronics N.V. and North American Phillips Corporation.

1.2

1.3

State of Data

The data contained within this document is subject to change.The specifications are

subject to change without notice. Verify with your local Intel sales office that you have

the latest datasheet before finalizing a design

References

Material and concepts available in the following documents may be beneficial when

reading this document:

Document

Notes

1

Number

®

AP-485, Intel Processor Identification and the CPUID Instruction

241618

1

®

Intel 64 and IA-32 Architectures Software Developer's Manual

253665

253666

253667

253668

253669

•

Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

®

Intel 64 and IA-32 Architectures Software Developer's Manual Documentation

Changes

1

252046

248966

®

Intel 64 and IA-32 Architectures Optimization Reference Manual

1

64-bit Extension Technology Software Developer's Guide

•

Volume 1

Volume 2

300834

300835

®

Intel Virtualization Technology for IA-32 Processors (VT-x) Preliminary

Specification

C97063

1

2

Intel® Xeon® Processor 7400 Series Specification Update

32033501

315889

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)

11.0 Design Guidelines

EPS12V Power Supply Design Guide: A Server system Infrastructure (SSI)

Specification for Entry Chassis Power Supplies

Intel® Xeon® Processor 7400 Series Thermal / Mechanical Design Guide

32033701

1

Notes:

1.

2.

Document is available publicly at http://developer.intel.com.

Document available on www.ssiforum.org.

§

Intel® Xeon® Processor 7400 Series Datasheet

13

Introduction

14

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

2 Electrical Specifications

2.1

Front Side Bus and GTLREF

Most Intel® Xeon® Processor 7400 Series FSB signals use Assisted Gunning

Transceiver Logic (AGTL+) signaling technology. This technology provides improved

noise margins and reduced ringing through low voltage swings and controlled edge

rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high

logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the

addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the

first clock of a low-to-high voltage transition. Platforms implement a termination

voltage level for AGTL+ signals defined as V_TT. Because platforms implement separate

power planes for each processor (and chipset), V_CCand V_TTare supplied separately to

the processor. This configuration allows for improved noise tolerance as processor

frequency increases. Speed enhancements to data and address buses have made

signal integrity considerations and platform design methods even more critical than

with previous processor families. Design guidelines for the processor FSB are detailed

in the appropriate platform design guidelines (refer to Section 1.3).

The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID and GTLREF_ADD_END) which are used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and

GTLREF_DATA_END are used for the 4X front side bus signaling group and

GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front

side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See

Table 2-17 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID and

GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines

for details. Termination resistors (R_TT) for AGTL+ signals are provided on the processor

silicon and are terminated to V_TT. The on-die termination resistors are always enabled

on the processor to control reflections on the transmission line. Intel chipsets also

provide on-die termination, thus eliminating the need to terminate the bus on the

baseboard for most AGTL+ signals.

Some FSB signals do not include on-die termination (R_TT) and must be terminated on

the baseboard. See Table 2-4, Table 2-5 and Table 2-6 for details regarding these

signals.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for

AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog

signal simulation of the FSB, including trace lengths, is highly recommended when

designing a system. Contact your Intel Field Representative to obtain the processor

signal integrity models, which includes buffer and package models.

Intel® Xeon® Processor 7400 Series Datasheet

15

Electrical Specifications

2.2

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large average current swings between low and full power states.

This may cause voltages on power planes to sag below their minimum values if bulk

decoupling is not adequate. Larger bulk storage (C_BULK), such as electrolytic capacitors,

supply current during longer lasting changes in current demand by the component,

such as coming out of an idle condition. Similarly, they act as a storage well for current

when entering an idle condition from a running condition. Care must be taken in the

baseboard design to ensure that the voltage provided to the processor remains within

the specifications listed in Table 2-9. Failure to do so can result in timing violations or

reduced lifetime of the component. For further information and guidelines, refer to the

appropriate platform design guidelines.

2.2.1

2.2.2

V Decoupling

CC

Vcc regulator solutions need to provide bulk capacitance with a low Effective Series

Resistance (ESR). Bulk decoupling must be provided on the baseboard to handle large

current swings. The power delivery solution must insure the voltage and current

specifications are met (as defined in Table 2-9). For further information regarding

power delivery, decoupling and layout guidelines, refer to the appropriate platform

design guidelines.

V_TTDecoupling

Bulk decoupling must be provided on the baseboard. Decoupling solutions must be

sized to meet the expected load. To insure optimal performance, various factors

associated with the power delivery solution must be considered including regulator

type, power plane and trace sizing, and component placement. A conservative

decoupling solution consists of a combination of low ESR bulk capacitors and high

frequency ceramic capacitors. For further information regarding power delivery,

decoupling and layout guidelines, refer to the appropriate platform design guidelines.

2.2.3

Front Side Bus AGTL+ Decoupling

The processor integrates signal termination on the die, as well as a portion of the

required high frequency decoupling capacitance on the processor package. However,

additional high frequency capacitance must be added to the baseboard to properly

decouple the return currents from the FSB. Bulk decoupling must also be provided by

the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in

the appropriate platform design guidelines.

2.3

Front Side Bus Clock (BCLK[1:0]) and Processor

Clocking

BCLK[1:0] inputs directly controls the FSB interface speed as well as the core

frequency of the processor. As in previous processor generations, the processor core

frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is

set during manufacturing. The default setting is for the maximum speed of the

processor. It is possible to override this setting using software. This permits operation

at lower frequencies than the processor’s tested frequency.

16

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

The processor core frequency is configured during reset by using values stored

internally during manufacturing. The stored value sets the highest bus fraction at which

the particular processor can operate. If lower speeds are desired, the appropriate ratio

can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details

of operation at core frequencies lower than the maximum rated processor speed.

Clock multiplying within the processor is provided by the internal phase locked loop

(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread

spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are

provided in Table 2-18 and Table 2-19, respectively. These specifications must be met

while also meeting signal integrity requirements as outlined in Table 2-18. The

processor utilizes differential clocks. Details regarding BCLK[1:0] driver specifications

are provided in the CK410B Clock Synthesizer/Driver Design Guidelines. Table 2-1

contains processor core frequency to FSB multipliers and their corresponding core

frequencies.

Table 2-1.

Core Frequency to Multiplier Configuration

Core Frequency to FSB

Multiplier

Core Frequency with

266 MHz FSB Clock

Notes

1/8

1/9

2.13 GHz

2.40 GHz

2.66 GHz

1, 2.

1/10

Notes:

1.

2.

Individual processors operate only at or below the frequency marked on the package.

For valid processor core frequencies, refer to the Intel® Xeon® Processor 7400 Series Specification

Update.

2.3.1

Front Side Bus Frequency Select Signals (BSEL[2:0])

Upon power up, the FSB frequency is set to the maximum supported by the individual

processor. BSEL[2:0] are CMOS outputs, and are used to select the FSB frequency.

Please refer to Table 2-12 for DC specifications. Table 2-2 defines the possible

combinations of the signals and the frequency associated with each combination. The

frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB

agents must operate at the same core and FSB frequency. See the appropriate platform

design guidelines for further details.

Table 2-2.

BSEL[2:0] Frequency Table

BSEL2

BSEL1

BSEL0

Bus Clock Frequency

0

1

0

1

0

1

0

1

0

1

0

1

0

1

266.666 MHz

Reserved

Intel® Xeon® Processor 7400 Series Datasheet

17

Electrical Specifications

2.3.2

PLL Power Supply

An on-die PLL filter solution is implemented on the processor. The V_CCPLLinput is used

to provide power to the on chip PLL of the processor. Please refer to Table 2-9 for DC

specifications. Refer to the appropriate platform design guidelines for decoupling and

routing guidelines.

2.4

Voltage Identification (VID)

The Voltage Identification (VID) specification for the processor is defined by the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design

Guidelines. The voltage set by the VID signals is the reference VR output voltage to be

delivered to the processor Vcc pins. VID signals are CMOS outputs. Please refer to

Table 2-11 for the DC specifications for these signals. A voltage range is provided in

Table 2-9 and changes with frequency. The specifications have been set such that one

voltage regulator can operate with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two

devices at the same core frequency may have different default VID settings. This is

reflected by the VID range values provided in Table 2-3.

The processor uses six voltage identification signals, VID[6:1], to support automatic

selection of power supply voltages. Table 2-3 specifies the voltage level corresponding

to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers

to a low voltage level. The definition provided in Table 2-3 is not related in any way to

previous Intel^®Xeon^®processors or voltage regulator designs. If the processor socket

is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the

voltage that is requested, the voltage regulator must disable itself. See the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design

Guidelines for further details.

Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down

(EVRD) 11.0 Design Guidelines defines VID [7:0], VID 7 and VID 0 are not used on the

Intel® Xeon® Processor 7400 Series.

The Intel® Xeon® Processor 7400 Series provides the ability to operate while

transitioning to an adjacent VID and its associated processor core voltage (V_CC). This

will represent a DC shift in the load line. It should be noted that a low-to-high or high-

to-low voltage state change may result in as many VID transitions as necessary to

reach the target core voltage. Transitions above the specified VID are not permitted.

Table 2-9 includes VID step sizes and DC shift ranges. Minimum and maximum voltages

must be maintained as shown in Table 2-10 and Table 2-2.

The VRM or EVRD utilized must be capable of regulating its output to the value defined

by the new VID. DC specifications for dynamic VID transitions are included in Table 2-9

and Table 2-10, while AC specifications are included in Table 2-25. Refer to the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design

Guidelines for further details.

Power source characteristics must be guaranteed to be stable whenever the supply to

the voltage regulator is stable.

18

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Table 2-3.

Voltage Identification Definition

VID6 VID5 VID4 VID3 VID2 VID1

HEX

V_{CC_MAX}

HEX

V_{CC_MAX}

400

mV

200

mV

100

mV

50

25

12.5

mV

400

mV

200

mV

100

mV

50

25

12.5

mV

7A

78

76

74

72

70

6E

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

3C

3A

38

36

34

32

30

2E

2C

2A

28

26

24

22

20

1E

1C

1A

18

16

14

12

10

0E

0C

0A

08

06

04

02

00

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

6C

6A

68

66

64

62

60

5E

5C

5A

58

56

54

52

50

4E

4C

4A

48

46

44

42

40

3E

1

OFF

Notes:

1.

2.

3.

When this VID pattern is observed, the voltage regulator output should be disabled.

Shading denotes the expected VID range of the Intel® Xeon® Processor 7400 Series.

The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see

®

Section 6.2.3), Extended HALT state transitions (see Section 7.2.2), or Enhanced Intel SpeedStep Technology transitions

(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications.

Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is

received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until

power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design

Guidelines.

4.

Intel® Xeon® Processor 7400 Series Datasheet

19

Electrical Specifications

2.5

Reserved, Unused, or Test Signals

All Reserved signals must remain unconnected. Connection of these signals to V_CC, V_TT,

V_SS, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Section 4 for a pin listing of the processor

and the location of all Reserved signals.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active high inputs, should be connected through a

resistor to ground (V_SS). Unused outputs can be left unconnected; however, this may

interfere with some TAP functions, complicate debug probing, and prevent boundary

scan testing. A resistor must be used when tying bidirectional signals to power or

ground. When tying any signal to power or ground, a resistor will also allow for system

testability. Resistor values should be within ± 20% of the impedance of the baseboard

trace for FSB signals, unless otherwise noticed in the appropriate platform design

guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same

value as the on-die termination resistors (R_TT). For details see Table 2-20.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

termination. Inputs and utilized outputs must be terminated on the baseboard. Unused

outputs may be terminated on the baseboard or left unconnected. Note that leaving

unused outputs unterminated may interfere with some TAP functions, complicate debug

probing, and prevent boundary scan testing. Signal termination for these signal types

is discussed in the appropriate platform design guidelines.

For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then

terminate the net with a 51 Ω resistor to V_TT.

The TESTHI signals may use individual pull-up resistors or be grouped together as

detailed below.

• TESTHI[1:0] - can be grouped together with a single pull-up to V_TT

2.6

Front Side Bus Signal Groups

The FSB signals have been combined into groups by buffer type. AGTL+ input signals

have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the

term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group

when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as

the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active

anytime and include an active PMOS pull-up transistor to assist during the first clock of

a low-to-high voltage transition.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals whose timings are

specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the

second set is for the source synchronous signals which are relative to their respective

strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals

are still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 2-4 identifies which signals are common clock, source synchronous

and asynchronous.

20

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Table 2-4.

FSB Signal Groups

1

Signal Group

Type

Signals

AGTL+ Common Clock Input

Synchronous to BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,

TRDY#;

AGTL+ Common Clock Output

AGTL+ Common Clock I/O

Synchronous to BCLK[1:0]

BPM4#, BPM[2:1]#, BPMb[2:1]#

2

ADS#, AP[1:0]#, BINIT# , BNR# , BPM5#,

BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#,

2

DBSY#, DP[3:0]#, DRDY#, HIT# , HITM# ,

2

LOCK#, MCERR#

AGTL+ Source Synchronous I/O Synchronous to assoc.

strobe

Signals

Associated Strobe

REQ[4:0]#

A[37:36,16:3]#

ADSTB0#

A[39:38, 35:17]#

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

ADSTB1#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

AGTL+ Strobes I/O

Open Drain Output

Synchronous to BCLK[1:0]

Asynchronous

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

FERR#/PBE#, IERR#, PROCHOT#,

THERMTRIP#, TDO

CMOS Asynchronous Input

Asynchronous

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/

INTR, LINT1/NMI, PWRGOOD, SMI#, STPCLK#,

TCK, TDI, TMS TRST#

CMOS Asynchronous Output

FSB Clock

Asynchronous

Clock

BSEL[2:0], VID[6:1]

BCLK[1:0]

SMBus

Synchronous to SM_CLK

Power/Other

SM_CLK, SM_DAT, SM_EP_A[2:0], SM_WP

Power/Other

COMP[3:0], GTLREF_ADD_MID,

GTLREF_ADD_END, GTLREF_DATA_MID,

GTLREF_DATA_END, LL_ID[1:0],

PROC_ID[1:0], PECI, RESERVED,

SKTOCC#,SM_VCC, TESTHI[1:0], TESTIN1,

TESTIN2, VCC, VCC_SENSE, VCC_SENSE2,

VCCPLL, VID[0], VSS_SENSE, VSS_SENSE2,

VSS, VTT, VTT_SEL

Notes:

1.

2.

Refer to Section 4 for signal descriptions.

These signals may be driven simultaneously by multiple agents (Wired-OR).

Intel® Xeon® Processor 7400 Series Datasheet

21

Electrical Specifications

Table 2-6 outlines AGTL+ signals which include on-die termination (RTT) and those that

require external termination. Table 2-6 outlines non AGTL+ signals including open drain

signals. Table 2-7 provides signal reference voltages.

Table 2-5.

AGTL+ Signal Description Table

AGTL+ signals with R

AGTL+ signals with no R

TT

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]#

BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,

DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

Note:

1.

Signals that have RTT in the package with 50 Ω pullup to V .

TT

Table 2-6.

Non AGTL+ Signal Description Table

Signals with R

Signals with no R

TT

A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0], FERR#/

PBE#, FORCEPR#, GTLREF_ADD_MID,

GTLREF_ADD_END, GTLREF_DATA_MID,

GTLREF_DATA_END, IERR#, IGNNE#, INIT#, LINT0/

INTR, LINT1/NMI, LL_ID[1:0], PROC_ID[1:0], PECI,

PROCHOT#, PWRGOOD, SKTOCC#, SMI#, STPCLK#,

TCK, TDI, TDO, TESTHI[1:0], TESTIN1, TESTIN2,

THERMTRIP#, TMS, TRST#, VCC_SENSE, VCC_SENSE2,

VID[6:1], VSS_SENSE, VSS_SENSE2, VTT_SEL

Table 2-7.

Signal Reference Voltages

GTLREF

CMOS

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, A20M#, FORCEPR#, LINT0/INTR, LINT1/NMI, IGNNE#,

BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#, BR[1:0]#, INIT#, PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, TRST#

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,

HITM#, LOCK#, MCERR#, RESET#, REQ[4:0]#,

RS[2:0]#, RSP#, TRDY#

2.7

CMOS Asynchronous and Open Drain

Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize

CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,

THERMTRIP#, and TDO utilize open drain output buffers. All of the CMOS and Open

Drain signals are required to be asserted/deasserted for at least eight BCLKs in order

for the processor to recognize the proper signal state. See Section 2.11 and

Section 2.13 for the DC and AC specifications. See Section 7.2 for additional timing

requirements for entering and leaving the low power states.

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, it is recommended that the processor(s) be first in the TAP chain and followed by

any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of

accepting an input of the appropriate voltage. Similar considerations must be made for

TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a

different voltage level.

22

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

2.9

Mixing Processors

Intel supports and validates multi-processor configurations only in which all processors

operate with the same FSB frequency, core frequency, number of cores, and have the

same internal cache sizes. Mixing components operating at different internal clock

frequencies or number of cores is not supported and will not be validated by Intel.

Note:

Processors within a system must operate at the same frequency per bits [12:8] of the

CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated

due to thermal events, Extended HALT, Enhanced Intel SpeedStep^®technology

transitions, or assertion of the FORCEPR# signal (See Section 6).

Mixing processors of different steppings but the same model (as per CPUID instruction)

is supported. Details regarding the CPUID instruction are provided in the AP-485 Intel^®

Processor Identification and the CPUID Instruction application note.

2.10

Absolute Maximum and Minimum Ratings

Table 2-8 specifies absolute maximum and minimum ratings only, which lie outside the

functional limits of the processor. Only within specified operation limits, can

functionality and long-term reliability be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

.

Table 2-8.

Processor Absolute Maximum Ratings

1, 2

Symbol

Parameter

Min

Max

Unit

Notes

V

Core voltage with respect to VSS

-0.30

1.45

V

CC

FSB termination voltage with respect to

TT

V

SS

T

Processor case temperature

Storage temperature

See

°C

CASE

Section 6

T

-40

85

3, 4, 5

STORAGE

Notes:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must

be satisfied.

2.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not

receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect

the long-term reliability of the device. For functional operation, please refer to the processor case

temperature specifications.

3.

4.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long-term reliability of the processor.

Intel® Xeon® Processor 7400 Series Datasheet

23

Electrical Specifications

2.11

Processor DC Specifications

The following notes apply:

• The processor DC specifications in this section are defined at the processor die and

not at the package pins unless noted otherwise.

• The notes associated with each parameter are part of the specification for that

parameter.

• Unless otherwise noted, all specifications in the tables apply to all frequencies and

cache sizes.

See Section 5 for the pin signal definitions. Most of the signals on the processor FSB

are in the AGTL+ signal group. The DC specifications for these signals are listed in

Table 2-11.

Table 2-9 through Table 2-17 list the DC specifications and are valid only while meeting

specifications for case temperature (Tcase as specified in Section 6), clock frequency,

and input voltages.

2.11.1

Flexible Motherboard Guidelines (FMB)

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the

Intel® Xeon® Processor 7400 Series will have over certain time periods. The values

are only estimates and actual specifications for future processors may differ. Processors

may or may not have specifications equal to the FMB value in the foreseeable future.

System designers should meet the FMB values to ensure their systems will be

compatible with future processors.

Table 2-9.

Voltage and Current Specifications (Sheet 1 of 3)

1

Symbol

VID

Parameter

Min

Typ

Max

Unit

Notes

VID range

for All processors

0.9000

1.4500

V

10

V

See Table 2-10 and Figure 2-4

2, 3, 5, 8

CC

Launch - FMB

Default V Voltage for initial

CC

power up

1.1

V

mV

V

CC_BOOT

VID_STEP

VID_SHIFT

TT

VID step size during a

transition

12.5

450

Total allowable DC load line

shift from VID steps

9

FSB termination voltage

(DC + AC specification)

1.045

1.425

3.135

1.100

1.50

1.155

1.605

7, 12

PLL supply voltage (DC + AC

specification)

V

CCPLL

SM_V

SMBus supply voltage

3.300

3.465

150

V

A

CC

I

for a 6-Core Intel®

CC

Xeon® X7460 Processor

Launch - FMB

3, 4, 5, 8

CC

I

for a Intel® Xeon®

Processor E7400 Series

Launch - FMB

130

A

CC

I

for a 4-Core Intel®

CC

Xeon® Processor E7400

Series

Launch - FMB

24

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Table 2-9.

Voltage and Current Specifications (Sheet 2 of 3)

1

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I

for an 6-Core Intel®

CC

85

A

3, 4, 5, 8

CC

Xeon® Processor L7400

Series

Launch - FMB

I

for an 4-Core Intel®

CC

65

A

3, 4, 5, 8

CC

Xeon® Processor L7400

Series

Launch - FMB

I

for a Intel®

CC_RESET

150

130

A

15

CC_RESET

Xeon® X7460 Processor

Launch - FMB

I

for a Intel®

CC_RESET

Xeon® Processor E7400

Series

Launch - FMB

I

for a 6-Core

CC_RESET

85

65

A

15

CC_RESET

CC_TDC

Intel® Xeon® Processor

L7400 Series

Launch - FMB

I

for a 4-Core

CC_RESET

Intel® Xeon® Processor

L7400 Series

Launch - FMB

Thermal Design Current

(TDC) for a Intel® Xeon®

X7460 Processor

125

95

5,13

Launch - FMB

Thermal Design Current

(TDC) for a 6-core Intel®

Xeon® Processor E7400

Series

CC_TDC

Launch - FMB

I

Thermal Design Current

(TDC) for a 4-core Intel®

Xeon® Processor E7400

Series

95

70

55

A

5,13

CC_TDC

Launch - FMB

Thermal Design Current

(TDC) for a 6-Core Intel®

Xeon® Processor L7400

Series

Launch - FMB

Thermal Design Current

(TDC) for a 4-Core Intel®

Xeon® Processor L7400

Series

Launch - FMB

I

Icc for SMBus supply

100

122.5

8.0

mA

A

SM_VCC

TT

I

for V supply before V

CC

14

6

CC

TT

stable

for V supply after V

CC

I

7.0

CC

TT

stable

I

for

200

µA

CC_GTLREF

CC_VCCPLL

CC

GTLREF_DATA_MID,

GTLREF_DATA_END,

GTLREF_ADD_MID, and

GTLREF_ADD_END

I

for PLL supply

520

mA

11

CC

Intel® Xeon® Processor 7400 Series Datasheet

25

Electrical Specifications

Table 2-9.

Voltage and Current Specifications (Sheet 2 of 3)

1

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I

for an 6-Core Intel®

CC

85

A

3, 4, 5, 8

CC

Xeon® Processor L7400

Series

Launch - FMB

I

for an 4-Core Intel®

CC

65

A

3, 4, 5, 8

CC

Xeon® Processor L7400

Series

Launch - FMB

I

for a Intel®

CC_RESET

150

130

A

15

CC_RESET

Xeon® X7460 Processor

Launch - FMB

I

for a Intel®

CC_RESET

Xeon® Processor E7400

Series

Launch - FMB

I

for a 6-Core

CC_RESET

85

65

A

15

CC_RESET

CC_TDC

Intel® Xeon® Processor

L7400 Series

Launch - FMB

I

for a 4-Core

CC_RESET

Intel® Xeon® Processor

L7400 Series

Launch - FMB

Thermal Design Current

(TDC) for a Intel® Xeon®

X7460 Processor

125

95

5,13

Launch - FMB

Thermal Design Current

(TDC) for a 6-core Intel®

Xeon® Processor E7400

Series

CC_TDC

Launch - FMB

I

Thermal Design Current

(TDC) for a 4-core Intel®

Xeon® Processor E7400

Series

95

70

55

A

5,13

CC_TDC

Launch - FMB

Thermal Design Current

(TDC) for a 6-Core Intel®

Xeon® Processor L7400

Series

Launch - FMB

Thermal Design Current

(TDC) for a 4-Core Intel®

Xeon® Processor L7400

Series

Launch - FMB

I

Icc for SMBus supply

100

122.5

8.0

mA

A

SM_VCC

TT

I

for V supply before V

CC

14

6

CC

TT

stable

for V supply after V

CC

I

7.0

CC

TT

stable

I

for

200

µA

CC_GTLREF

CC_VCCPLL

CC

GTLREF_DATA_MID,

GTLREF_DATA_END,

GTLREF_ADD_MID, and

GTLREF_ADD_END

I

for PLL supply

520

mA

11

CC

26

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Table 2-9.

Voltage and Current Specifications (Sheet 3 of 3)

1

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I

for a Intel® Xeon®

CC

150

A

TCC

X7460 Processor during

active thermal control circuit

(TCC)

I

for a Intel® Xeon®

CC

130

85

A

TCC

Processor E7400 Series

during active thermal control

circuit (TCC)

I

for an 6-core Intel®

CC

Xeon® Processor L7400

Series during active thermal

control circuit (TCC)

I

for an 4-core Intel®

65

CC

Xeon® Processor L7400

Series during active thermal

control circuit (TCC)

Notes:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processors.

The voltage specification requirements are measured across the VCC_SENSE and VSS_SENSE pins and

with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum

impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external

noise from the system is not coupled in the scope probe.

3.

4.

The processor must not be subjected to any static V level that exceeds the V

associated with any

CC

CC_MAX

particular current. Failure to adhere to this specification can shorten processor lifetime.

specification is based on maximum V loadline Refer to Figure 2-4 for details. The processor is

I

CC_MAX

CC

capable of drawing I

for up to 10 ms. Refer to Figure 2-1, Figure 2-2 or Figure 2-3for further details

CC_MAX

on the average processor current draw over various time durations.

FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See

Section 2.11.1 for further details on FMB guidelines.

This specification represents the total current for GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END.

5.

6.

7.

8.

9.

V

must be provided via a separate voltage source and must not be connected to V . This specification is

TT

CC

measured at the pin.

Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE)

shown in Figure 6-1.

This specification refers to the total reduction of the load line due to VID transitions below the specified

VID.

10. Individual processor VID values may be calibrated during manufacturing such that two devices at the same

frequency may have different VID settings.

11. This specification applies to the VCCPLL pin.

12. Baseboard bandwidth is limited to 20 MHz.

13.

I

is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and

CC_TDC

should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for

monitoring its temperature and asserting the necessary signal to inform the processor of a thermal

excursion. Please see the applicable design guidelines for further details. The processor is capable of

drawing I

indefinitely. Refer to Figure 2-6 for further details on the average processor current draw

CC_TDC

over various time durations. This parameter is based on design characterization and is not tested.

14. This is the maximum total current drawn from the V plane by the processor with R enabled. This

TT

specification does not include the current coming from on-board termination (R ), through the signal line.

TT

Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine

the total I drawn by the system. This parameter is based on design characterization and is not tested.

TT

15.

I

is specified while PWRGOOD and RESET# are asserted. Refer to Table 2-22 for the PWRGOOD to

CC_RESET

RESET# de-assertion time specification and Table 2-23 for the RESET# Pulse Width specification.

Intel® Xeon® Processor 7400 Series Datasheet

27

Electrical Specifications

Figure 2-1. Intel® Xeon® X7460 Processor Load Current versus Time

15 5

15 0

14 5

14 0

13 5

13 0

12 5

12 0

0.01

0.1

1

10

100

1000

Time Duration (s)

Notes:

1.

Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

Figure 2-2. Intel® Xeon® Processor E7400 Series Load Current versus Time

135

130

125

120

115

110

105

100

95

90

0.01

0.1

1

10

100

1000

Time Duration (s)

Notes:

1.

Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

28

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Figure 2-3. Intel® Xeon® Processor L7400 Series Load Current versus Time

10 0

95

90

85

80

75

70

65

60

0.01

0.1

1

10

100

1000

Time Duration (s)

Notes:

1.

Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

Intel® Xeon® Processor 7400 Series Datasheet

29

Electrical Specifications

Table 2-10. V_CCStatic and Transient Tolerance

I

(A)

V

(V)

V

(V)

V (V)

CC_Min

Notes

CC

CC_Max

CC_Typ

0

VID - 0.000

VID - 0.006

VID - 0.013

VID - 0.019

VID - 0.025

VID - 0.031

VID - 0.038

VID - 0.044

VID - 0.050

VID - 0.056

VID - 0.063

VID - 0.069

VID - 0.075

VID - 0.081

VID - 0.088

VID - 0.094

VID - 0.100

VID - 0.106

VID - 0.113

VID - 0.119

VID - 0.125

VID - 0.131

VID - 0.138

VID - 0.144

VID - 0.150

VID - 0.156

VID - 0.163

VID - 0.169

VID - 0.175

VID - 0.181

VID - 0.188

VID - 0.015

VID - 0.021

VID - 0.028

VID - 0.034

VID - 0.040

VID - 0.046

VID - 0.053

VID - 0.059

VID - 0.065

VID - 0.071

VID - 0.078

VID - 0.084

VID - 0.090

VID - 0.096

VID - 0.103

VID - 0.109

VID - 0.115

VID - 0.121

VID - 0.128

VID - 0.134

VID - 0.140

VID - 0.146

VID - 0.153

VID - 0.159

VID - 0.165

VID - 0.171

VID - 0.178

VID - 0.184

VID - 0.190

VID - 0.201

VID - 0.208

VID - 0.030

VID - 0.036

VID - 0.043

VID - 0.049

VID - 0.055

VID - 0.061

VID - 0.068

VID - 0.074

VID - 0.080

VID - 0.086

VID - 0.093

VID - 0.099

VID - 0.105

VID - 0.111

VID - 0.118

VID - 0.124

VID - 0.130

VID - 0.136

VID - 0.143

VID - 0.149

VID - 0.155

VID - 0.161

VID - 0.168

VID - 0.174

VID - 0.180

VID - 0.186

VID - 0.193

VID - 0.199

VID - 0.205

VID - 0.221

VID - 0.228

1, 2, 3

5

10

1, 2, 3

15

1, 2, 3

20

1, 2, 3

25

1, 2, 3

30

1, 2, 3

35

1, 2, 3

40

1, 2, 3

45

1, 2, 3

50

1, 2, 3

55

1, 2, 3

60

1, 2, 3

65

1, 2, 3

70

1, 2, 3

75

1, 2, 3

80

1, 2, 3

85

1, 2, 3

90

1, 2, 3

95

1, 2, 3

100

105

110

115

120

125

130

135

140

145

150

1, 2, 3, 4

1, 2, 3, 4, 5

Notes:

1.

2.

3.

The V

and V

loadlines represent static and transient limits. Please see Section 2.11.2 for

CC_MAX

CC_MIN

V

overshoot specifications.

CC

This table is intended to aid in reading discrete points on Figure 2-4 for Intel® Xeon® Processor 7400

Series.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and

across the VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator circuits

must also be taken from the processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for

socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide

for details on VR implementation.

4.

5.

Icc values greater than 95 A are not applicable for the Ultra Dense Intel® Xeon® Processor 7400 Series.

Icc values greater than 130 A are not applicable for the Rack Optimized Intel® Xeon® Processor 7400

Series.

30

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Figure 2-4. V_CCStatic and Transient Tolerance Load Lines

Icc [A]

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150

VID - 0.000

VID - 0.050

VID - 0.100

VID - 0.150

VID - 0.200

VID - 0.250

V_{C C}

M axim um

V_{C C}

Typical

V_{C C}

M inim um

Notes:

1.

The V

and V

loadlines represent static and transient limits. Please see Section 2.11.2 for VCC

CC_MAX

CC_MIN

overshoot specifications.

2.

3.

4.

Refer to Table 2-9 for processor VID information.

Refer to Table 2-10 for V Static and Transient Tolerance.

CC

The load lines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and the

VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator circuits must also

be taken from the processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the Voltage Regulator Module

(VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line

guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR

implementation.

5.

6.

Icc values greater than 95 A are not applicable for the Ultra Dense Intel® Xeon® Processor 7400 Series.

Icc values greater than 130 A are not applicable for the Rack Optimized Intel® Xeon® Processor 7400

Series.

Table 2-11. AGTL+ Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Input Low Voltage

Input High Voltage

Output High Voltage

Buffer On Resistance

Input Leakage Current

-0.10

0

GTLREF-0.10

V

2, 4, 6

3, 6

4, 6

5

IL

V

GTLREF+0.10

V

V +0.10

TT

IH

TT

V

R

V

- 0.10

7

N/A

9

V

TT

V

OH

ON

TT

11

+/-100

Ω

I

N/A

μA

7, 8

LI

Notes:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

V

IL

value.

is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

3.

4.

V

IH

value.

This is the pull down driver resistance. Measured at 0.33*V . Refer to processor I/O Buffer Models for I/V

TT

characteristics

5.

GTLREF should be generated from V with a 1% tolerance resistor divider. The V referred to in these

T

specifications is the instantaneous V .

TT

6.

7.

Specified when on-die R and R

are turned off. V between 0 and V .

TT

ON IN TT

This is the measurement at the pin.

Intel® Xeon® Processor 7400 Series Datasheet

31

Electrical Specifications

Table 2-12. CMOS Signal Input/Output Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

0.3*V

Units

Notes

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Current

Output High Current

Input Leakage Current

-0.10

0.00

V

2

IL

TT

V

0.7*V

V

V +0.1

TT

IH

TT

V

-0.10

0.9*V

0

0.1*V

V

2

OL

OH

OL

OH

TT

V

+0.1

TT

V

2

TT

I

1.70

N/A

4.70

mA

μA

3

I

4

I

± 100

5, 6

LI

Notes:

1.

2.

3.

4.

5.

6.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V .

TT

Measured at 0.1*V .

TT

Measured at 0.9*V .

For Vin between 0 V and V . Measured when the driver is tristated.

TT

This is the measurement at the pin.

Table 2-13. Open Drain Signal Group DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

Output Low Voltage

Output High Voltage

Output Low Current

Leakage Current

N/A

0.20

V

OL

OH

OL

LO

V

-5%

V

V +5%

TT

3

2

TT

I

16

N/A

50

mA

μA

N/A

± 200

4, 5

Notes:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at 0.2*V .

OH

TT

V

is determined by value of the external pullup resistor to V . Please refer to platform design guide for

TT

details.

For V between 0 V and V

4.

5.

.

OH

IN

This is the measurement at the pin.

Table 2-14. SMBus Signal Group DC Specifications

1, 2

Symbol

Parameter

Min

Max

Unit

Notes

V

Input Low Voltage

-0.30

0.30 * SM_VCC

3.465

0.400

3.0

V

IL

IH

OL

LI

Input High Voltage

0.70 * SM_VCC

Output Low Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

SMBus Pin Capacitance

0

V

I

N/A

mA

µA

pF

±10

± 10

LO

C

15.0

3

SMB

Notes:

1. These parameters are based on design characterization and are not tested.

2. All DC specifications for the SMBus signal group are measured at the processor pins.

3. Platform designers may need this value to calculate the maximum loading of the SMBus and

to determine maximum rise and fall times for SMBus signals.

32

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

2.11.2

V

Overshoot Specification

CC

Processors can tolerate short transient overshoot events where V_CCexceeds the VID

voltage when transitioning from a high-to-low current load condition. This overshoot

cannot exceed VID + V_{OS_MAX}(V_{OS_MAX}is the maximum allowable overshoot above

VID). These specifications apply to the processor die voltage as measured across the

VCC_SENSE and VSS_SENSE pins and across the VCC_SENSE2 and VSS_SENSE2 pins.

Table 2-15. V_CCOvershoot Specifications

Symbol

Parameter

Magnitude of V overshoot above VID

Min

Max

Units

Figure

Notes

V

50

25

mV

µs

2-5

OS_MAX

CC

T

Time duration of V overshoot above VID

CC

OS_MAX

Figure 2-5. V_CCOvershoot Example Waveform

Example Overshoot Waveform

V_OS

VID + 0.050

VID - 0.000

T_OS

0

5

10

15

20

25

Time [us]

T_OS: Overshoot time above VID

_OS: Overshoot above VID

V

Notes:

1.

2.

VOS is the measured overshoot voltage.

TOS is the measured time duration above VID.

2.11.3

Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in

Table 2-15 when measured across the VCC_SENSE and VSS_SENSE pins and across

the VCC_SENSE2 and VSS_SENSE2 pins. Overshoot events that are < 10 ns in duration

may be ignored. These measurements of processor die level overshoot should be taken

with a 100 MHz bandwidth limited oscilloscope.

Intel® Xeon® Processor 7400 Series Datasheet

33

Electrical Specifications

2.11.4

Platform Environmental Control Interface (PECI) DC

Specifications

PECI is an Intel proprietary one-wire bus interface that provides a communication

channel between Intel processor and external thermal monitoring devices. The Intel®

Xeon® Processor 7400 Series contains Digital Thermal Sensors (DTS) distributed

throughout the die. These sensors are implemented as analog-to-digital converters

calibrated at the factory for reasonable accuracy to provide a digital representation of

relative processor temperature. PECI provides an interface to relay the highest DTS

temperature within a die to external management devices for thermal/fan speed

control. More detailed information may be found in Section 6.3, “Platform Environment

Control Interface (PECI)” and the RS - Platform Environment Control Interface (PECI)

Specification.

2.11.4.1

DC Characteristics

A PECI device interface operates at a nominal voltage set by V_TT. The set of DC

electrical specifications shown in Table 2-16 is used with devices normally operating

from a V_TTinterface supply. V_TTnominal levels will vary between processor families. All

PECI devices will operate at the V_TTlevel determined by the processor installed in the

system. For specific nominal V_TTlevels, refer to Table 2-11.

Table 2-16. PECI DC Electrical Limits

Definition and

Conditions

1

Symbol

Min

Max

Units

Notes

V_in

Input Voltage Range

Hysteresis

-0.150

V_TT

V

V_hysteresis

0.1 * V_TT

N/A

Negative-edge

V_n

V_p

0.275 * V_TT

0.550 * V_TT

0.500 * V_TT

0.725 * V_TT

V

threshold voltage

Positive-edgethreshold

voltage

High level output

source

I_source

-6.0

0.5

N/A

1.0

50

mA

µA

(V_OH= 0.75 * V_TT)

Low level output sink

(V_OL= 0.25 * V_TT)

I_sink

High impedance state

leakage to V_TT

I_leak+

N/A

2

(V_leak= V_OL

)

High impedance

leakage to GND

I_leak-

N/A

10

µA

2

3

(V_leak= V_OH

)

C_bus

Bus capacitance

N/A

10

pF

Signal noise immunity

above 300 MHz

V_noise

0.1 * V_TT

N/A

V_p-p

Note:

1.

2.

3.

V

supplies the PECI interface. PECI behavior does not affect V min/max specifications.

TT TT

The leakage specification applies to powered devices on the PECI bus.

One node is counted for each client and one node for the system host. Extended trace lengths might appear

as additional nodes.

34

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

2.11.4.2

Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input

design for improved noise immunity. Use Figure 2-6 as a guide for input buffer design.

Figure 2-6. Input Device Hysteresis

V_TT

Maximum V_P

PECI High Range

Minimum V_P

Maximum V_N

Minimum

Hysteresis Signal Range

Valid Input

Minimum V_N

PECI Ground

PECI Low Range

2.12

AGTL+ FSB Specifications

Routing topologies are dependent on the processors supported and the chipset used in

the design. Please refer to the appropriate platform design guidelines for specific

implementation details. In most cases, termination resistors are not required as these

are integrated into the processor silicon. See Table 2-6 for details on which signals do

not include on-die termination. Please refer to Table 2-17 for R_TTvalues.

Valid high and low levels are determined by the input buffers via comparing with a

reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID,

and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END are the reference

voltage for the FSB 4X data signals, GTLREF_ADD_MID and GTLREF_ADD_END are the

reference voltage for the FSB 2X address signals and common clock signals. Table 2-17

lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and

GTLREF_ADD_END specifications.

The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard

using high precision voltage divider circuits. Refer to the appropriate platform design

guidelines for implementation details.

Intel® Xeon® Processor 7400 Series Datasheet

35

Electrical Specifications

Table 2-17. AGTL+ Bus Voltage Definitions

1

Symbol

Parameter

Min

Typ

Max

Units

Notes

GTLREF_DATA_MID

GTLREF_DATA_END

Data Bus Reference

Voltage

0.98 * 0.67 * V

0.67 * V

1.02 * 0.67 * V

V

2, 3

TT

GTLREF_ADD_MID

GTLREF_ADD_END

Address Bus

Reference Voltage

0.98 * 0.67 * V

0.67 * V

1.02 * 0.67 * V

V

2, 3

TT

R

Termination

Resistance (pull up)

45

50

55

4

5

TT

Ω

COMP

COMP Resistance

49.4

49.9

50.4

Notes:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values

across the range of V .

TT

3.

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V on the baseboard

TT

by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor tolerance. Refer to

the appropriate platform design guidelines for implementation details. The V referred to in these specifications is the

TT

instantaneous V

TT

4.

5.

R

is the on-die termination resistance measured at V of the AGTL+ output driver. Measured at 0.33*V . R is connected

TT OL TT TT

to V on die.

TT

COMP resistance must be provided on the system board with +/- 1% resistors. See the applicable platform design guide for

implementation details

Table 2-18. FSB Differential BCLK Specifications

1

Symbol

Parameter

Min

Typ

Max

Unit

Figure

Notes

V

Input Low Voltage

Input High Voltage

-0.150

0.660

0.250

0.0

.15

V

2-9

L

0.710

0.350

0.850

0.550

H

Absolute Crossing

Point

2-9, 2-10

2,8

CROSS(abs)

V

Relative Crossing

Point

0.250 +

Havg

N/A

0.550 +

Havg

V

2-9, 2-10

3,8,9,11

CROSS(rel)

0.5 * (V

- 0.700)

0.5 * (V

- 0.700)

Δ V

Range of Crossing

Points

N/A

0.140

CROSS

V

I

Overshoot

N/A

V

+ 0.300

N/A

V

2-9

4

5

OS

H

Undershoot

-0.300

0.200

US

Ringback Margin

Threshold Region

N/A

V

6

RBM

TR

V

- 0.100

V

+ 0.100

V

7

CROSS

Input Leakage

Current

N/A

+/- 100

μA

10

LI

Notes:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of

BCLK1.

3.

4.

5.

6.

V

is the statistical average of the V measured by the oscilloscope.

Havg H

Overshoot is defined as the absolute value of the maximum voltage.

Undershoot is defined as the absolute value of the minimum voltage.

Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum

Falling Edge Ringback.

Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches.

It includes input threshold hysteresis.

The crossing point must meet the absolute and relative crossing point specifications simultaneously.

V

7.

8.

9.

can be measured directly using “Vtop” on Agilent* and “High” on Tektronix* oscilloscopes.

Havg

10. For VIN between 0 V and VH,

11. VCROSS is defined as the total variation of all crossing voltages as defined in note 3.

36

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

2.13

Front Side Bus AC Specifications

The processor FSB timings specified in this section are defined at the

processor core (pads). Therefore, proper simulation of the FSB is the only

means to verify proper timing and signal quality.

See Table 4-1 for the pin listing and Table 5-1 for signal definitions. Table 2-19 through

Table 2-24 list the AC specifications associated with the processor FSB.

All AGTL+ timings are referenced to GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END for both ‘0’ and ‘1’ logic levels unless

otherwise specified.

The timings specified in this section should be used in conjunction with the processor

signal integrity models provided by Intel. AGTL+ layout guidelines are also available in

the appropriate platform design guidelines.

Note:

Care should be taken to read all notes associated with a particular timing parameter.

Table 2-19. Front Side Bus Differential Clock AC Specifications

1

T# Parameter

FSB Clock Frequency

Min

Typ

Max

Unit

Figure

Notes

265.247

3.7489

266.666

3.7500

266.745

3.7700

150

MHz

ns

2

3

T1: BCLK[1:0] Period

2-9

T2: BCLK[1:0] Period Stability

T3: BCLK[1:0] Rise Time

T4: BCLK[1:0] Fall Time

ps

4, 5

6

700

ps

700

ps

6

Differential Rising and Falling Edge

Rates

0.6

4

V/ns

7

Notes:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The processor core clock frequency is derived from BCLK. The bus clock to processor core clock ratio is

determined during initialization as described in Section 2.3. Table 2-1 includes core frequency to FSB

multipliers.

The period specified here is the average period. A given period may vary from this specification as

governed by the period stability specification (T2).

For the clock jitter specification, refer to the CK410B Clock Synthesize/Driver Design Guidelines.

3.

4.

5.

In this context, period stability is defined as the worst case timing difference between successive crossover

voltages. In other words, the largest absolute difference between adjacent clock periods must be less than

the period stability.

6.

7.

Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing.

Measured from -200 mV to +200 mV. The signal must be monotonic through the measurement region for

rise and fall time. The 400 mV measurement window is centered on the differential zero. See Figure 2-11.

.

Table 2-20. Front Side Bus Common Clock AC Specifications

1, 2, 3

T# Parameter

Min

Max

Unit

Figure

Notes

T10: Common Clock Output Valid Delay

T11: Common Clock Input Setup Time

T12: Common Clock Input Hold Time

T13: RESET# Pulse Width

0.22

0.650

0.150

1

1.10

N/A

10

ns

2-12

2-20

4

5

ns

ms

6, 7, 8

Notes:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Not 100% tested. Specified by design characterization.

All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V

) of the

CROSS

BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at nominal

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor

(pads).

Intel® Xeon® Processor 7400 Series Datasheet

37

Electrical Specifications

4.

5.

Valid delay timings for these signals are specified into the test circuit described in Figure 2-7 and with

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V .

TT

Specification is for a minimum swing is specified into the test circuit described in Figure 2-7 and defined

between AGTL+ V

to V

. This assumes an edge rate of 2.0 V/ns to 3.0 V/ns.

IL_MAX

IH_MIN

6.

7.

8.

RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.

This should be measured after V and BCLK[1:0] become stable.

TT

Maximum specification applies only while PWRGOOD is asserted.

Table 2-21. FSB Source Synchronous AC Specifications

1, 2, 3, 4

T# Parameter

Min

Max

Unit

Figure Notes

T20: Source Sync. Output Valid Delay

(first data/address only)

0.00

1.10

ns

2-13,

2-14

5

T21: T

Before Data Strobe

Source Sync. Data Output Valid

0.27

ns

2-14

2-13

5,8

5,9

VBD

T22: T Source Sync. Data Output Valid

After Data Strobe

0.27

VAD

T23: T Source Sync. Address Output

Valid Before Address Strobe

0.66

5,8

VBA

T24: T Source Sync. Address Output

Valid After Address Strobe

0.66

5,9

VAA

T25: T

T26: T

Data Input Setup Time

0.19

2-13,

2-14

6

SUSS

Address Input Setup Time

0.3

0.19

2-13,

2-14

6

Data Input Hold Time

2-13,

2-14

6

HSS

Address Input Hold Time

0.300

2-13,

2-14

6

12, 14, 15,10

11, 14

T27: Source Synchronous Address Strobe

Setup Time to BCLK[1:0]

3.5 - (1.875 * n)

4.15 - (0.9375 * n)

3.28

2-13,

2-14

T28: Source Synchronous Data Strobe

Setup Time to BCLK[1:0]

2-14

2-13

T30: Data Strobe ‘n’ (DSTBN#) Output

Valid Delay

4.38

3.91

13

T31: Address Strobe Output Valid Delay

2.81

Notes:

1.

2.

3.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Not 100% tested. Specified by design characterization.

All source synchronous AC timings are referenced to their associated strobe at nominal GTLREF_DATA_MID,

GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source synchronous data signals are

referenced to the falling edge of their associated data strobe. Source synchronous address signals are

referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+

signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and

GTLREF_ADD_END at the processor pads.

4.

5.

Unless otherwise noted, these specifications apply to both data and address timings.

Valid delay timings for these signals are specified into the test circuit described in Figure 2-7 and with

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V .

TT

6.

7.

8.

Specification is for a minimum swing into the test circuit described in Figure 2-7 and defined between

AGTL+ V

to V

. This assumes an edge rate of 3.0 V/ns to 5.5 V/ns.

IL_MAX

IH_MIN

All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to

each respective strobe.

This specification represents the minimum time the data or address will be valid before its strobe. Refer to

the appropriate platform design guidelines for more information on the definitions and use of these

specifications.

9.

This specification represents the minimum time the data or address will be valid after its strobe. Refer to

the appropriate platform design guidelines for more information on the definitions and use of these

specifications.

10. The rising edge of ADSTB# must come approximately 1/2 BCLK period after the falling edge of ADSTB#.

11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.

12. The address strobe setup time is measured with respect to T2. Calculation of the setup time is as follows:

a.

If T27 > BCLK period, then the setup time calculated is positive. The value calculated indicates

setup time before T1.

b.

If T27 < BCLK period, then the setup time calculated is positive. The value calculated indicates

setup time after T1.

38

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.

14. This specification reflects a typical value, not a minimum or maximum.

15. For this timing parameter, n = 0 to 1.

Table 2-22. Miscellaneous GTL+ AC Specifications

Notes

1, 2, 3, 4

T# Parameter

Min

Max

Unit

Figure

T35: Asynchronous GTL+ input pulse width

T36: PWRGOOD assertion to RESET# de-assertion

T37: BCLK stable to PWRGOOD assertion

T38: PROCHOT# pulse width

8

1

BCLKs

ms

5

10

2-20

2-16

2-17

2-21

2-20

10

500

BCLKs

µs

6,12

7

8

T39: THERMTRIP# assertion until V removed

CC

500

5

ms

T40: FERR# valid delay from STPCLK# deassertion

0

BCLKs

ms

T41: V stable to PWRGOOD assertion

CC

0.05

500

20

10

11

T42: PWRGOOD rise time

ns

T43: V

stable to VID / BSEL valid

10

100

10

1

µs

2-20

9,10

10

CC_BOOT

T44: VID / BSEL valid to V stable

µs

CC

T48: V stable to VID / BSEL valid

µs

10

TT

T49: V

stable to PWRGOOD assertion

ms

10

CCPLL

Notes:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing

Voltage (V

). PWRGOOD is referenced to BCLK0 rising edge at 0.5 * V .

CROSS

TT

3.

4.

5.

6.

7.

These signals may be driven asynchronously.

Refer to Section 7.2 for additional timing requirements for entering and leaving low power states.

A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system.

Refer to the PWRGOOD signal definition in Section 5 for more details information on behavior of the signal.

Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion

and before the deassertion of PROCHOT# for the processor to enable or disable the TCC.

8.

9.

Intel recommends the V power supply also be removed upon assertion of THERMTRIP#.

TT

This specification requires that the VID and BSEL signals be sampled no earlier than 10 μs after V (at

CC

V

voltage) and V are stable.

CC_BOOT

TT

10. Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply

is in regulation as defined by the minimum and maximum DC/AC specifications for all components being

powered by it.

11. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor.

Measured between (0.3* V ) and (0.7*V ).

TT

12. See Table 2-19 for BCLK specifications.

Table 2-23. Front Side Bus AC Specifications (Reset Conditions)

T# Parameter

Min

Max

Unit

Figure

Notes

T45: Reset Configuration Signals

(A[39:3]#, BR[1:0]#, INIT#, SMI#) Setup Time

480

µs

2-20

1

T46: Reset Configuration Signals

(A[39:3]#, INIT#, SMI#) Hold Time

2

20

2

BCLKs

2-20

2

T47: Reset Configuration Signals

BR[1:0]# Hold Time

Notes:

1.

2.

Before the clock that de-asserts RESET#.

After the clock that de-asserts RESET#.

Intel® Xeon® Processor 7400 Series Datasheet

39

Electrical Specifications

Table 2-24. TAP Signal Group AC Specifications

Notes

Figure

T# Parameter

Min

Max

Unit

1, 2, 8

T55: TCK Period

30

7.5

0

ns

2-8

3

4,7

5

T56: TDI, TMS Setup Time

T57: TDI, TMS Hold Time

T58: TDO Clock to Output Delay

T59: TRST# Assert Time

2-15

2-16

7.5

2

T

6

TCK

Notes:

1.

2.

3.

4.

5.

6.

7.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Not 100% tested. Specified by design characterization.

This specification is based on the capabilities of the ITP debug port, not on processor silicon.

Referenced to the rising edge of TCK.

Referenced to the falling edge of TCK.

TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.

Specification for a minimum swing defined between TAP V to V . This assumes a minimum edge rate of

t-

t+

0.5 V/ns.

It is recommended that TMS be asserted while TRST# is being deasserted.

8.

.

Table 2-25. VID Signal Group AC Specifications

1, 2

T # Parameter

Min

Max

Unit

Figure

Notes

T80: VID Step Time

T81: VID Dwell Time

5

µs

2-23

50

2-23

T82: VID Down Transition to Valid V (min)

0

50

0

2-22,2-23

CC

T83: VID Up Transition to Valid V (min)

CC

T84: VID Down Transition to Valid V (max)

CC

T85: VID Up Transition to Valid V (max)

CC

Notes:

1.

See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design

Guidelines for addition information.

2.

Platform support for VID transitions is required for the processor to operate within specifications.

Table 2-26. SMBus Signal Group AC Specifications

1, 2

T# Parameter

Min

Max

Unit

Figure

Notes

T90: SM_CLK Frequency

10

100

N/A

1.0

KHz

µs

ns

µs

T91: SM_CLK Period

T92: SM_CLK High Time

4.0

4.7

0.02

0.1

250

300

4.7

4.0

4.7

4.0

2-18

2-19

2-18

T93: SM_CLK Low Time

3

T94: SMBus Rise Time

T95: SMBus Fall Time

0.3

T96: SMBus Output Valid Delay

T97: SMBus Input Setup Time

T98: SMBus Input Hold Time

T99: Bus Free Time

4.5

N/A

4,

5

T100: Hold Time after Repeated Start Condition

T101: Repeated Start Condition Setup Time

T102: Stop Condition Setup Time

Notes:

1.

2.

These parameters are based on design characterization and are not tested.

All AC timings for the SMBus signals are referenced at V

pins. Refer to Figure 2-19.

or V

and measured at the processor

IL_MAX

IL_MIN

40

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

3.

Rise time is measured from (V

- 0.15V) to (V

+ 0.15V). Fall time is measured from

IL_MAX

IH_MIN

(0.9 * SM_VCC) to (V

- 0.15V). DC parameters are specified in Table 2-26.

IL_MAX

4.

5.

Minimum time allowed between request cycles.

Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next

transaction.

2.14

Processor AC Timing Waveforms

The following figures are used in conjunction with the AC timing tables, Table 2-19

through Table 2-25.

Note:

For Figure 2-8 through Figure 2-21, the following apply:

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing

Voltage (V_CROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock

AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID,

GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor

pads.

2. All source synchronous AC timings for AGTL+ signals are referenced to their

associated strobe (address or data) at nominal GTLREF_DATA_MID,

GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source

synchronous data signals are referenced to the falling edge of their associated data

strobe. Source synchronous address signals are referenced to the rising and falling

edge of their associated address strobe. All source synchronous AGTL+ signal

timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END at the processor pads.

3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V_CROSS. All

AGTL+ strobe signal timings are referenced at nominal GTLREF_DATA_MID,

GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor

pads.

4. All AC timings for the TAP signals are referenced to the TCK at 0.5 * V_TTat the

processor pins. All TAP signal timings (TMS, TDI, etc...) are referenced at 0.5 * V_TT

at the processor pads.

5. All CMOS signal timings are referenced at 0.5 * V_TTat the processor pins.

6. All AC timings for the SMBus signals are referenced to the SM_CLK at 0.5 *

SM_VCC at the processor pins. All SMBus signal timings (SM_DAT, SM_CLK, etc.)

are referenced at

The circuit used to test the AC specification is shown in Figure 2-7.

Figure 2-7. Electrical Test Circuit

V_TT

R_LOAD

Buffer

48 ohms, 169 ps/in, 1200 mils

L = 1.475 nH

C = 0.85 pF

AC Timings specified at this

point

Intel® Xeon® Processor 7400 Series Datasheet

41

Electrical Specifications

Figure 2-8. TCK Clock Waveform

V2

TCK

V3

V1

T

p

T_p= T55: Period

V1, V2: For rise and fall times, TCK is measured between 20% and 80% points on the waveform.

V3: TCK is referenced to 0.5 * V_TT

Figure 2-9. Differential Clock Waveform

Overshoot

VH

BCLK1

Rising Edge

Ringback

Crossing

Voltage

Crossing

Voltage

Ringback

Margin

Threshold

Region

Falling Edge

Ringback,

BCLK0

VL

Undershoot

Tp

Tp = T1: BCLK[1:0] period

Figure 2-10. Differential Clock Crosspoint Specification

650

600

550

500

550 mV

550 + 0.5 (VHavg - 700)

450

400

250 + 0.5 (VHavg - 700)

350

300

250

200

250 mV

660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850

VHavg (mV)

42

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Figure 2-11. BCLK Waveform at Processor Pad and Pin

SKT

PAD

Notes:

1.

2.

3.

4.

Waveform at pin is non-monotonic. Waveform at pad is monotonic.

Differential Edge Rate (DER) measured zero +/- 200mv.

g indicates V/ns units and meg indicates mv/ns units.

Waveform at pad has faster edge rate than at pin.

Figure 2-12. FSB Common Clock Valid Delay Timing Waveform

T0

T1

T2

BCLK1

BCLK0

T_P

Common Clock

Signal (@ driver)

valid

T_Q

T_R

Common Clock

Signal (@ receiver)

valid

T_P= T10: Common Clock Output Valid Delay

T_Q= T11: Common Clock Input Setup

T_R= T12: Common Clock Input Hold Time

Intel® Xeon® Processor 7400 Series Datasheet

43

Electrical Specifications

Figure 2-13. FSB Source Synchronous 2X (Address) Timing Waveform

T0

T1

T2

T_p/4

T_p/2

3T_p/4

BCLK1

BCLK0

T_R

ADSTB# (@ driver)

A# (@ driver)

T_J

T_H

T_J

T_H

valid

T_K

T_S

ADSTB# (@ receiver)

A# (@

valid

T_M

receiver)

valid

T_N

T

_P= T1: BCLK[1:0] Period

T_H= T23: Source Sync. Address Output Valid Before Address Strobe

T_J= T24: Source Sync. Address Output Valid After Address Strobe

_K= T27: Source Sync. Address Strobe Setup Time to BCLK

_M= T25: Source Sync. Input Setup Time

T

T_N= T26: Source Sync. Input Hold Time

T_S= T20: Source Sync. Output Valid Delay

T_R= T31: Address Strobe Output Valid Delay

44

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Figure 2-14. FSB Source Synchronous 4X (Data) Timing Waveform

T0

T_p/4

T1

T2

T_p/2

3T_p/4

BCLK1

BCLK0

T_D

DSTBp# (@ driver)

DSTBn# (@ driver)

T_A

T_B

T_A

D# (@ driver)

T_C

T_J

DSTBp# (@ receiver)

DSTBn# (@ receiver)

D# (@ receiver)

T_G

T_E

T_G

T_E

T_P= T1: BCLK[1:0] Period

T_A= T21: Source Sync. Data Output Valid Delay Before Data Strobe

T_B= T22: Source Sync. Data Output Valid Delay After Data Strobe

T_C= T28: Source Sync. Data Strobe Setup Time to BCLK

T_D= T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay

T_E= T25: Source Sync. Input Setup Time

T_G= T26: Source Sync. Input Hold Time

T_J= T20: Source Sync. Data Output Valid Delay

Intel® Xeon® Processor 7400 Series Datasheet

45

Electrical Specifications

Figure 2-15. TAP Valid Delay Timing Waveform

V

TCK

Tx Ts

Th

V

Valid

Signal

Tx = T58: TDO Clock to Output Delay

Ts = T56: TDI, TMS Setup Time

Th = T57: TDI, TMS Hold Time

V = 0.5 * V_TT

Note: Please refer to Table 2-12 for TAP Signal Group DC specifications and Table 2-24 for TAP Signal Group

AC specifications.

Figure 2-16. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform

V

T

q

T59 (TRST# Pulse Width), V = 0.5 * V_TT

T38 (PROCHOT# Pulse Width), V = GTLREF

T

=

q

Figure 2-17. THERMTRIP# Power Down Sequence

T_A

THERMTRIP#

Vcc

V_TT

T_A= T39 (THERMTRIP# to removal of power)

46

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Figure 2-18. SMBus Timing Waveform

t

F

t

HD;STA

R

t

LOW

Clk

t

SU;STO

t

HIGH

t

HD;STA

SU;STA

HD;DAT

SU;DAT

Data

t

BUF

S

P

STOP

START

STOP

t

=

T100

T98

T99

T97

=

T93

T92

T94

T95

=

T101

LOW

HD;STA

HD;DAT

BUF

SU;STA

SU;STD

t

= T102

HIGH =

R

F

=

SU;DAT

Figure 2-19. SMBus Valid Delay Timing Waveform

SM_CLK

TAA

DATA VALID

SM_DAT

DATA OUTPUT

TAA = T96

Intel® Xeon® Processor 7400 Series Datasheet

47

Electrical Specifications

Figure 2-20. Voltage Sequence Timing Requirements

VID[6:1] / BSEL[2:0]

Tc

V_TT

Tg

V_CCPLL

V_{CC_BOOT}

Ta

Vcc

Tb

Te

PWRGOOD

BCLK

Tf

Td

Th

Ti

Reset Configuration

Signals(A[35:3]#,

INIT#, SMI#)

Tj

Reset Configuration

Signals BR[1:0]#

RESET#

Ta= T43 (V_{CC_BOOT}stable to VID[6:1] / BSEL[2:0] valid)

Tb= T44 (VID[6:1] / BSEL[2:0] valid to Vcc stable)

Tc= T48 (V_TTstable to VID[6:1] / BSEL[2:0] valid)

Td= T36 (PWRGOOD assertion to RESET# de-assertion)

Te= T41 (V_CCstable to PWRGOOD assertion)

Tf = T37 (BCLK stable to PWRGOOD assertion)

Tg = T49 (V_CCPLLstable to PWRGOOD assertion)

Th = T45 Reset Configuration Signals (A[35:3]#, BR[1:0]#, INIT#, SMI#) Setup Time

Ti= T46 Reset Configuration Signals (A[35:3]#, INIT#, SMI#) Hold Time

Tj= T47 Reset Configuration Signals (BR[1:0]#) Hold Time

Figure 2-21. FERR#/PBE# Valid Delay Timing

BCLK

System bus

STPCLK#

SG

Ack

Ta

undefined

FERR#

undefined

PBE#

FERR#

FERR#/PBE#

48

Intel® Xeon® Processor 7400 Series Datasheet

Electrical Specifications

Notes:

1.

2.

Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion).

FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the

FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined

regions, the PBE# signal is driven. FERR# is driven at all other times.

Figure 2-22. VID Step Timings

n

n-1

m

m+1

VID

...

Tc

V_CC(max)

Ta

Tb

Td

V_CC(min)

Ta = T84: VID Down to Valid V_CC(max)

Tb = T82: VID Down to Valid V_CC(min)

Tc = T85: VID Up to Valid V_CC(max)

Td = T83: VID Up to Valid V_CC(min)

Figure 2-23. VID Step Times and Vcc Waveforms

Ta

Tb

n

n-6 = VID_TM2

n

VID

V

_CC(max)

V_CC(max,n-3)

Te

Tc

Td

V_CC(max,n-4)

V_CC(min)

V_CC(min,n-3)

Tf

V_CC(min,n-4)

Ta

Tb

Tc

Td

Te

Tf

= T80: VID Step Time

=

T81: Thermal Monitor 2 Dwell Time

T84: VID Down to Valid V_CC(max)

T82: VID Down to Valid V_CC(min)

T85: VID Up to Valid V_CC(max)

T83: VID Up to Valid V_CC(min)

Note: This waveform illustrates an example of an Intel Thermal

Monitor 2 transition or an Intel Enhanced SpeedStep

Technology transition that is six VID steps down from the

current state and six steps back up. Any arbitrary up or down

transition can be generalized from this waveform.

§

Intel® Xeon® Processor 7400 Series Datasheet

49

Electrical Specifications

50

Intel® Xeon® Processor 7400 Series Datasheet

Mechanical Specifications

3 Mechanical Specifications

The Intel® Xeon® Processor 7400 Series is packaged in a lead free FC-mPGA8 package

that interfaces with the motherboard via a mPGA604 socket. The package consists of

the processor die mounted on a substrate pin-carrier. An IHS is attached to the

package substrate and die and serves as the mating surface for processor component

thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor

package components and how they are assembled together.

The package components shown in Figure 3-1 include the following:

1. IHS

2. Processor die

3. FC-mPGA8 package

4. Pin-side capacitors

5. Package pin

Figure 3-1. Processor Package Assembly Sketch

Note:

Figure 3-1 is not to scale and is for reference only. The mPGA604 socket is not shown.

3.1

Package Mechanical Drawing

The drawings include dimensions necessary to design a thermal solution for the

processor. These dimensions include:

1. Package reference with tolerances (total height, length, width, etc.)

2. IHS parallelism and tilt

3. Pin dimensions

4. Top-side and back-side component keepout dimensions

5. Reference datums

All drawing dimensions are in mm [in].

Intel® Xeon® Processor 7400 Series Datasheet

51

Mechanical Specifications

Figure 3-2. Intel® Xeon® Processor 7400 Series Package Drawing (Sheet 1 of 2)

52

Intel® Xeon® Processor 7400 Series Datasheet

Mechanical Specifications

Figure 3-3. Intel® Xeon® Processor 7400 Series Package Drawing (Sheet 2 of 2)

Intel® Xeon® Processor 7400 Series Datasheet

53

Mechanical Specifications

3.2

Processor Component Keepout Zones

The processor may contain components on the substrate that define component

keepout zone requirements. A thermal and mechanical solution design must not intrude

into the required keepout zones. Decoupling capacitors are typically mounted to either

the topside or pin-side of the package substrate. All drawing dimension are in mm [in].

54

Intel® Xeon® Processor 7400 Series Datasheet

Mechanical Specifications

Figure 3-4. Top Side Board Keepout Zones (Part 1)

Intel® Xeon® Processor 7400 Series Datasheet

55

Mechanical Specifications

Figure 3-5. Top Side Board Keepout Zones (Part 2)

56

Intel® Xeon® Processor 7400 Series Datasheet

Mechanical Specifications

Figure 3-6. Bottom Side Board Keepout Zones

Intel® Xeon® Processor 7400 Series Datasheet

57

Mechanical Specifications

Figure 3-7. Board Mounting-Hole Keepout Zones

58

Intel® Xeon® Processor 7400 Series Datasheet

Mechanical Specifications

Figure 3-8. Volumetric Height Keep-Ins

Intel® Xeon® Processor 7400 Series Datasheet

59

Mechanical Specifications

3.3

Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package.

These mechanical load limits should not be exceeded during heatsink assembly,

shipping conditions, or standard use condition. Also, any mechanical system or

component testing should not exceed the maximum limits. The processor package

substrate should not be used as a mechanical reference or load-bearing surface for

thermal and mechanical solutions. The minimum loading specification must be

maintained by any thermal and mechanical solution.

Table 3-1.

Processor Loading Specifications

Parameter

Minimum

Maximum

Unit

Notes

1, 2, 3,

4

Static Compressive

Load

44

10

222

50

N

lbf

1, 2, 3, 5

1, 3, 4, 6, 7

1, 3, 5, 6, 7

1, 3, 8

44

10

288

65

N

lbf

Dynamic

Compressive Load

222 N + 0.45 kg * 100 G

50 lbf (static) + 1 lbm * 100 G

N

lbf

288 N + 0.45 kg * 100 G

65 lbf (static) + 1 lbm * 100 G

N

lbf

Transient

445

100

N

lbf

Notes:

1. These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface.

2. This is the minimum and maximum static force that can be applied by the heatsink and retention solution to

maintain the heatsink and processor interface.

3. These parameters are based on limited testing for design characterization. Loading limits are for the package

only and do not include the limits of the processor socket.

4. This specification applies for thermal retention solutions that allow baseboard deflection.

5. This specification applies either for thermal retention solutions that prevent baseboard deflection or for the

Intel enabled reference solution (CEK).

6. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.

7. Experimentally validated test condition used a heatsink mass of 1 lbm (~0.45 kg) with 100 G acceleration

measured at heatsink mass. The dynamic portion of this specification in the product application can have

flexibility in specific values, but the ultimate product of mass times acceleration should not exceed this

validated dynamic load (1 lbm x 100 G = 100 lb).

8. Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement,

representative of loads experienced by the package during heatsink installation.

60

Intel® Xeon® Processor 7400 Series Datasheet

Mechanical Specifications

3.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended

maximum loading on the processor IHS relative to a fixed substrate. These package

handling loads may be experienced during heatsink removal.

Table 3-2.

Package Handling Guidelines

Parameter

Maximum Recommended

Notes

1,

3,

4,

2

Shear

Tensile

Torque

356 N [80 lbf]

156 N [35 lbf]

8 N-m [70 lbf-in]

Notes:

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

2. These guidelines are based on limited testing for design characterization.

3. A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface.

4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top

surface.

3.5

3.6

Package Insertion Specifications

The Intel® Xeon® Processor 7400 Series can be inserted into and removed from a

mPGA604 socket 15 times. The socket should meet the mPGA604 requirements

detailed in the mPGA604 Socket Design Guidelines.

Processor Mass Specifications

The typical mass of the Intel® Xeon® Processor 7400 Series is 37.6 g (1.5oz). This

mass [weight] includes all the components that are included in the package.

3.7

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3.

Processor Materials

Component

Material

Integrated Heat Spreader (IHS)

Substrate

Nickel Plated Copper

Fiber-Reinforced Resin

Gold Plated Copper

Substrate Pins

Intel® Xeon® Processor 7400 Series Datasheet

61

Mechanical Specifications

3.8

Processor Markings

Figure 3-9 shows the topside markings and Figure 3-10 shows the bottom-side

markings on the processor. These diagrams are to aid in the identification of the Intel®

Xeon® Processor 7400 Series. Please note that the figures in this section are not to

scale.

Figure 3-9. Processor Topside Markings

22DD MMaattrriixx

IInncclluuddeessAATTPPOOaannddSSeerriaial l

NNuummbbeerr ((ffrroonntteennddmmaarkr)k)

Processor Name

i(m) ©’053

Pin 1 Indicator

Notes:

1.

2.

Character size for laser markings is: 17 Point, height 1.27 mm (50 mils), width 0.81 mm (32 mils)

All characters will be in upper case.

Figure 3-10. Processor Bottom-Side Markings

Pin 1 Indicator

2D Matrix

Includes ATPO and Serial

Number (front end mark)

Pin Field

Processor/Speed/Cache/Bus

Number

Cavity

with

Components

7xxx 2933/16M/1066

SL9HA COSTA RICA

C0096109-0021

S-Spec

Country of Assy

Text Line1

Text Line2

Text Line3

FPO – Serial #

(13 Characters)

62

Intel® Xeon® Processor 7400 Series Datasheet

Mechanical Specifications

3.9

Processor Pin-Out Coordinates

Figure 3-11 shows the top view of the processor pin coordinates. The coordinates are

referred to throughout the document to identify processor pins.

Figure 3-11. Processor Pin-Out Coordinates, Top View

COMMON

ADDRESS

COMMON

CLOCK

Async/

JTAG

CLOCK

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

A

B

A

B

C

D

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

Processor

Top View

R

T

U

V

U

V

W

Y

W

Y

AA

AB

AC

AD

AB

AC

AD

AE

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

CLOCKS

DATA

= Signal

= VCC

= Ground

= VTT

= Reserved/ No Connect

§

Intel® Xeon® Processor 7400 Series Datasheet

63

Mechanical Specifications

64

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

4 Pin Listing

4.1

Processor Pin Assignments

Section 2.6 contains the front side bus signal groups for the Intel® Xeon® Processor

7400 Series (see Table 2-4). This section provides a sorted pin list in Table 4-1 and

Table 4-2. Table 4-1 is a listing of all processor pins ordered alphabetically by pin name.

Table 4-2 is a listing of all processor pins ordered by pin number.

4.1.1

Pin Listing by Pin Name

Table 4-1. Pin Listing by Pin Name

(Sheet 2 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 1 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

A32#

A33#

A34#

A35#

A36#

A37#

A38#

A39#

A6

A7

C9

C8

Source Sync

Input/Output

Input

A3#

A22 Source Sync

A20 Source Sync

B18 Source Sync

C18 Source Sync

A19 Source Sync

C17 Source Sync

D17 Source Sync

A13 Source Sync

B16 Source Sync

B14 Source Sync

B13 Source Sync

A12 Source Sync

C15 Source Sync

C14 Source Sync

D16 Source Sync

D15 Source Sync

F15 Source Sync

A10 Source Sync

B10 Source Sync

B11 Source Sync

C12 Source Sync

E14 Source Sync

D13 Source Sync

Input/Output

A4#

A5#

A6#

F16 Source Sync

F22 Source Sync

A7#

A8#

B6

Source Sync

A9#

C16 Source Sync

F27 Async GTL+

D19 Common Clk

F17 Source Sync

F14 Source Sync

E10 Common Clk

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A20M#

ADS#

Input/Output

Input

ADSTB0#

ADSTB1#

AP0#

AP1#

D9

Y4

Common Clk

FSB Clk

BCLK0

BCLK1

W5

FSB Clk

Input

BINIT#

BNR#

F11 Common Clk

F20 Common Clk

Input/Output

Output

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

BPMb0#

BPMb1#

BPMb2#

BPMb3#

BPRI#

F6

F8

E7

F5

E8

E4

Common Clk

Output

Input/Output

Output

Input/Output

Output

A9

B8

Source Sync

AA4 Common Clk

AC1 Common Clk

AE2 Common Clk

AE3 Common Clk

D23 Common Clk

E13 Source Sync

D12 Source Sync

C11 Source Sync

Output

Input/Output

Input

B7

Source Sync

Intel® Xeon® Processor 7400 Series Datasheet

65

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 3 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 4 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

BR0#

BR1#

D20 Common Clk

F12 Common Clk

AA3 Power/Other

AB3 Power/Other

Y31 Power/Other

D25 Power/Other

E16 Power/Other

AE15 Power/Other

AE16 Power/Other

Y26 Source Sync

AA27 Source Sync

Y24 Source Sync

AA25 Source Sync

AD27 Source Sync

Y23 Source Sync

AA24 Source Sync

AB26 Source Sync

AB25 Source Sync

AB23 Source Sync

AA22 Source Sync

AA21 Source Sync

AB20 Source Sync

AB22 Source Sync

AB19 Source Sync

AA19 Source Sync

AE26 Source Sync

AC26 Source Sync

AD25 Source Sync

AE25 Source Sync

AC24 Source Sync

AD24 Source Sync

AE23 Source Sync

AC23 Source Sync

AA18 Source Sync

AC20 Source Sync

AC21 Source Sync

AE22 Source Sync

AE20 Source Sync

AD21 Source Sync

AD19 Source Sync

Input/Output

Output

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

AB17 Source Sync

AB16 Source Sync

AA16 Source Sync

AC17 Source Sync

AE13 Source Sync

AD18 Source Sync

AB15 Source Sync

AD13 Source Sync

AD14 Source Sync

AD11 Source Sync

AC12 Source Sync

AE10 Source Sync

AC11 Source Sync

AE9 Source Sync

AD10 Source Sync

AD8 Source Sync

AC9 Source Sync

AA13 Source Sync

AA14 Source Sync

AC14 Source Sync

AB12 Source Sync

AB13 Source Sync

AA11 Source Sync

AA10 Source Sync

AB10 Source Sync

AC8 Source Sync

AD7 Source Sync

AE7 Source Sync

AC6 Source Sync

AC5 Source Sync

AA8 Source Sync

Input/Output

Input

BSEL0

BSEL1

BSEL2

COMP0

COMP1

COMP2

COMP3

D0#

Output

Input

Input/Output

D1#

D2#

D3#

D4#

D5#

D6#

D7#

D8#

D9#

D10#

D11#

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

D28#

D29#

D30#

Y9

Source Sync

AB6 Source Sync

AC27 Source Sync

AD22 Source Sync

AE12 Source Sync

AB9 Source Sync

F18 Common Clk

C23 Common Clk

AC18 Common Clk

DBI0#

DBI1#

DBI2#

DBI3#

DBSY#

DEFER#

DP0#

Input/Output

66

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 5 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 6 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

DP1#

DP2#

DP3#

AE19 Common Clk

AC15 Common Clk

AE17 Common Clk

E18 Common Clk

Y21 Source Sync

Y18 Source Sync

Y15 Source Sync

Y12 Source Sync

Y20 Source Sync

Y17 Source Sync

Y14 Source Sync

Y11 Source Sync

E27 Async GTL+

A15 Async GTL+

Input/Output

Output

Reserved

A31

B1

Reserved

RESET#

RS0#

B4

DRDY#

B30

C31

D27

D29

E2

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FERR#/PBE#

FORCEPR#

GTLREF_ADD_END

GTLREF_ADD_MID

GTLREF_DATA_END

GTLREF_DATA_MID

HIT#

Y27

Y28

Y29

AA5

AA28

AB4

AC30

AD4

AD6

AD16

AD28

AD30

AD31

AE8

AE30

Y8

Input

F9

F23 Power/Other

W9 Power/Other

Power/Other

Input

W23 Power/Other

E22 Common Clk

A23 Common Clk

Input

Input/Output

Output

HITM#

IERR#

E5

C26 Async GTL+

D6 Async GTL+

Async GTL+

IGNNE#

Input

INIT#

Input

LINT0

B24 Async GTL+

G23 Async GTL+

B31 Power/Other

B28 Power/Other

A17 Common Clk

Input

Common Clk

Input

LINT1

Input

E21 Common Clk

D22 Common Clk

F21 Common Clk

Input

LL_IDO

Output

RS1#

Input

LL_ID1

Output

RS2#

Input

LOCK#

Input/Output

Output

RSP#

C6

A3

Common Clk

Power/Other

Input

MCERR#

PECI

D7

Common Clk

SKTOCC#

SM_CLK

SM_DAT

SM_EP_A0

SM_EP_A1

SM_EP_A2

SM_VCC

SM_WP

Output

Input

C28 Power/Other

AC28 SMBus

PROC_ID0

PROC_ID1

PROCHOT#

PWRGOOD

REQ0#

A30

B29

Power/Other

AC29 SMBus

Input/Output

Input

Output

AA29 SMBus

B25 Async GTL+

AB7 Async GTL+

B19 Source Sync

B21 Source Sync

C21 Source Sync

C20 Source Sync

B22 Source Sync

A28

Output

AB29 SMBus

Input

AB28 SMBus

Input

Input/Output

AE28 Power/Other

AE29 Power/Other

AD29 SMBus

REQ1#

REQ2#

Input

REQ3#

SMI#

C27 Async GTL+

REQ4#

STPCLK#

TCK

D4

Async GTL+

Reserved

E24 TAP

Intel® Xeon® Processor 7400 Series Datasheet

67

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 7 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 8 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

TDI

C24 TAP

Input

V

H1

H3

H5

H7

H9

Power/Other

CC

TDO

E25 TAP

Output

Input

Output

Input

TESTHI0

TESTHI1

TESTIN1

TESTIN2

THERMTRIP#

TMS

A16 Power/Other

W3

D1

C2

Power/Other

H23 Power/Other

H25 Power/Other

H27 Power/Other

H29 Power/Other

H31 Power/Other

F26 Async GTL+

A25 TAP

TRDY#

E19 Common Clk

F24 TAP

TRST#

V

A8

Power/Other

J2

J4

Power/Other

CC

A14 Power/Other

A18 Power/Other

A24 Power/Other

B20 Power/Other

J6

J8

J24

J26

J28

J30

K1

K3

K5

K7

K9

C4

Power/Other

C22 Power/Other

C30 Power/Other

D8

Power/Other

D14 Power/Other

D18 Power/Other

D24 Power/Other

D31 Power/Other

E6

Power/Other

K23 Power/Other

K25 Power/Other

K27 Power/Other

K29 Power/Other

K31 Power/Other

E20 Power/Other

E26 Power/Other

E28 Power/Other

E30 Power/Other

F1

F4

Power/Other

L2

L4

L6

L8

Power/Other

F29 Power/Other

F31 Power/Other

G2

G4

G6

G8

Power/Other

L24 Power/Other

L26 Power/Other

L28 Power/Other

L30 Power/Other

G24 Power/Other

G26 Power/Other

G28 Power/Other

G30 Power/Other

M1

M3

M5

M7

Power/Other

68

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 9 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 10 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

V

M9

Power/Other

V

T28 Power/Other

T30 Power/Other

CC

M23 Power/Other

M25 Power/Other

M27 Power/Other

M29 Power/Other

M31 Power/Other

U1

U3

U5

U7

U9

Power/Other

N1

N3

N5

N7

N9

Power/Other

U23 Power/Other

U25 Power/Other

U27 Power/Other

U29 Power/Other

U31 Power/Other

N23 Power/Other

N25 Power/Other

N27 Power/Other

N29 Power/Other

N31 Power/Other

V2

V4

V6

V8

Power/Other

P2

P4

P6

P8

Power/Other

V24 Power/Other

V26 Power/Other

V28 Power/Other

V30 Power/Other

P24 Power/Other

P26 Power/Other

P28 Power/Other

P30 Power/Other

W1

Power/Other

W25 Power/Other

W27 Power/Other

W29 Power/Other

W31 Power/Other

R1

R3

R5

R7

R9

Power/Other

Y2

Power/Other

Y16 Power/Other

Y22 Power/Other

Y30 Power/Other

AA1 Power/Other

AA6 Power/Other

AA20 Power/Other

AA26 Power/Other

AA31 Power/Other

AB2 Power/Other

AB8 Power/Other

AB14 Power/Other

AB18 Power/Other

AB24 Power/Other

AB30 Power/Other

R23 Power/Other

R25 Power/Other

R27 Power/Other

R29 Power/Other

R31 Power/Other

T2

T4

T6

T8

Power/Other

T24 Power/Other

T26 Power/Other

Intel® Xeon® Processor 7400 Series Datasheet

69

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 11 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 12 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

V

AC3 Power/Other

AC16 Power/Other

AC22 Power/Other

AC31 Power/Other

V

E1

E9

Power/Other

CC

SS

E15 Power/Other

E17 Power/Other

E23 Power/Other

E29 Power/Other

E31 Power/Other

AD2

Power/Other

AD20 Power/Other

AD26 Power/Other

AE14 Power/Other

AE18 Power/Other

AE24 Power/Other

AD1 Power/Other

B27 Power/Other

A26 Power/Other

CC

F2

F3

F7

Power/Other

F13 Power/Other

F19 Power/Other

F25 Power/Other

F28 Power/Other

F30 Power/Other

Input

CCPLL

Output

CC_SENSE

CC_SENSE2

VID1

VID2

VID3

VID4

VID5

VID6

E3

D3

C3

B3

A1

C1

A5

Power/Other

G1

G3

G5

G7

G9

Power/Other

V

SS

G25 Power/Other

G27 Power/Other

G29 Power/Other

G31 Power/Other

V

A11 Power/Other

A21 Power/Other

A27 Power/Other

A29 Power/Other

SS

V

SS

V

SS

V

SS

H2

H4

H6

H8

Power/Other

V

B2

B9

Power/Other

SS

V

SS

V

B15 Power/Other

B17 Power/Other

B23 Power/Other

SS

V

SS

H24 Power/Other

H26 Power/Other

H28 Power/Other

H30 Power/Other

V

SS

V

C7

Power/Other

SS

V

C13 Power/Other

C19 Power/Other

C25 Power/Other

C29 Power/Other

SS

V

SS

J1

J3

Power/Other

V

SS

V

SS

J5

V

D2

D5

Power/Other

SS

J7

V

SS

J9

V

D11 Power/Other

D21 Power/Other

D28 Power/Other

D30 Power/Other

SS

J23

J25

J27

V

SS

V

SS

V

SS

70

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 13 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 14 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

V

J29

J31

K2

Power/Other

V

P9

Power/Other

SS

P23 Power/Other

P25 Power/Other

P27 Power/Other

P29 Power/Other

P31 Power/Other

K4

K6

K8

K24 Power/Other

K26 Power/Other

K28 Power/Other

K30 Power/Other

R2

R4

R6

R8

Power/Other

L1

L3

L5

L7

L9

Power/Other

R24 Power/Other

R26 Power/Other

R28 Power/Other

R30 Power/Other

T1

T3

T5

T7

T9

Power/Other

L23 Power/Other

L25 Power/Other

L27 Power/Other

L29 Power/Other

L31 Power/Other

T23 Power/Other

T25 Power/Other

T27 Power/Other

T29 Power/Other

T31 Power/Other

M2

M4

M6

M8

Power/Other

M24 Power/Other

M26 Power/Other

M28 Power/Other

M30 Power/Other

U2

U4

U6

U8

Power/Other

N2

N4

N6

N8

Power/Other

U24 Power/Other

U26 Power/Other

U28 Power/Other

U30 Power/Other

N24 Power/Other

N26 Power/Other

N28 Power/Other

N30 Power/Other

V1

V3

V5

V7

V9

Power/Other

P1

P3

P5

P7

Power/Other

V23 Power/Other

V25 Power/Other

V27 Power/Other

Intel® Xeon® Processor 7400 Series Datasheet

71

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 15 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 16 of 16)

No.

Signal Buffer

Type

No.

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

V

V29 Power/Other

V31 Power/Other

V

AD3 Power/Other

AD9 Power/Other

AD15 Power/Other

AD17 Power/Other

AD23 Power/Other

AE6 Power/Other

AE11 Power/Other

AE21 Power/Other

AE27 Power/Other

D26 Power/Other

B26 Power/Other

SS

ss

W2

W4

Power/Other

W24 Power/Other

W26 Power/Other

W28 Power/Other

W30 Power/Other

SS

Y1

Y3

Y5

Y7

Power/Other

Output

SS_SENSE

SS_SENSE2

A4

B5

Power/Other

TT

Y13 Power/Other

Y19 Power/Other

Y25 Power/Other

B12 Power/Other

C5 Power/Other

AA2

Power/Other

C10 Power/Other

D10 Power/Other

E11 Power/Other

E12 Power/Other

F10 Power/Other

AA9 Power/Other

AA15 Power/Other

AA17 Power/Other

AA23 Power/Other

AA30 Power/Other

SS

W6

W7

W8

Y6

Power/Other

AB1

Power/Other

AB5 Power/Other

AB11 Power/Other

AB21 Power/Other

AB27 Power/Other

AB31 Power/Other

AC2 Power/Other

AC7 Power/Other

AC13 Power/Other

AC19 Power/Other

AC25 Power/Other

Y10 Power/Other

AA7 Power/Other

AA12 Power/Other

AC4 Power/Other

AC10 Power/Other

AD5 Power/Other

AD12 Power/Other

AE4 Power/Other

AE5 Power/Other

VTT_SEL

A2

Power/Other

Output

72

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

4.1.2

Pin Listing by Pin Number

Table 4-2.

Pin Listing by Pin Number

(Sheet 2 of 14)

Table 4-2.

Pin Listing by Pin Number

(Sheet 1 of 14)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

C1

V

Power/Other

TT

A1

A2

VID5

VTT_SEL

SKTOCC#

Power/Other Output

Power/Other

A13#

A12#

Source Sync Input/Output

Power/Other

A3

V

SS

A4

V

TT

A11#

Source Sync Input/Output

Power/Other

A5

V

Power/Other

SS

V

SS

A6

A32#

A33#

Source Sync Input/Output

Power/Other

A5#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

A7

REQ0#

A8

V

CC

V

CC

A9

A26#

A20#

Source Sync Input/Output

Power/Other

REQ1#

REQ4#

Common Clk Input/Output

Power/Other

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

B1

V

SS

V

SS

A14#

A10#

Source Sync Input/Output

Power/Other

LINT0

Async GTL+

Input

PROCHOT#

Output

V

CC

V

Power/Other Output

SS_SENSE2

CC_SENSE

FORCEPR#

TESTHI0

LOCK#

Async GTL+

Input

Power/Other Input

Common Clk Input/Output

Power/Other

LL_ID1

PROC_ID1

Reserved

LL_ID0

VID6

V

CC

A7#

A4#

Source Sync Input/Output

Power/Other

Power/Other Output

Power/Other Input

Power/Other Output

Power/Other

V

SS

C2

TESTIN2

VID3

A3#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

C3

HITM#

C4

V

CC

TT

V

CC

C5

Power/Other

TMS

TAP

Input

C6

RSP#

Common Clk Input

Power/Other

V

Power/Other Output

Power/Other

CC_SENSE2

SS

C7

V

SS

C8

A35#

A34#

Source Sync Input/Output

Power/Other

Reserved

C9

V

Power/Other

SS

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

V

TT

PROC_ID0

Reserved

Power/Other Output

A30#

A23#

Source Sync Input/Output

Power/Other

V

SS

B2

V

Power/Other

SS

A16#

A15#

A39#

A8#

Source Sync Input/Output

Power/Other

B3

VID4

Power/Other Output

B4

Reserved

B5

V

Power/Other

TT

B6

A38#

A31#

A27#

Source Sync Input/Output

Power/Other

A6#

B7

V

SS

B8

REQ3#

REQ2#

Common Clk Input/Output

Power/Other

B9

V

SS

B10

B11

A21#

A22#

Source Sync Input/Output

V

CC

Intel® Xeon® Processor 7400 Series Datasheet

73

Pin Listing

Table 4-2.

Pin Listing by Pin Number

(Sheet 3 of 14)

Table 4-2.

Pin Listing by Pin Number

(Sheet 4 of 14)

Signal

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

Output

Buffer Type

C23

C24

C25

C26

C27

C28

C29

C30

C31

D1

DEFER#

TDI

Common Clk Input

E5

E6

IERR#

Async GTL+

Power/Other

TAP

Input

V

CC

V

Power/Other Input

E7

BPM2#

BPM4#

Common Clk Input/Output

Power/Other

SS

IGNNE#

SMI#

Async GTL+

Input

E8

E9

V

SS

PECI

Power/Other Input/Output

Power/Other

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

F1

AP0#

Common Clk Input/Output

Power/Other

V

SS

CC

TT

Power/Other

Reserved

TESTIN1

A28#

A24#

Source Sync Input/Output

Power/Other

Power/Other Input

Power/Other

D2

V

SS

D3

VID2

Power/Other Output

COMP1

Power/Other Input

Power/Other

D4

STPCLK#

Async GTL+

Power/Other

Async GTL+

Input

V

SS

D5

V

DRDY#

TRDY#

Common Clk Input/Output

Common Clk Input

Power/Other

SS

D6

INIT#

Input

D7

MCERR#

Common Clk Input/Output

Power/Other

V

CC

D8

V

RS0#

HIT#

Common Clk Input

Common Clk Input/Output

Power/Other

CC

D9

AP1#

Common Clk Input/Output

Power/Other

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

E1

V

SS

TT

Power/Other

TCK

TDO

TAP

Input

SS

A29#

A25#

Source Sync Input/Output

Power/Other

TAP

Output

V

Power/Other

Async GTL+

Power/Other

CC

V

FERR#/PBE#

Output

CC

A18#

A17#

A9#

Source Sync Input/Output

Power/Other

V

CC

SS

CC

SS

CC

SS

CC

V

CC

ADS#

BR0#

Common Clk Input/Output

Power/Other

F2

V

F3

SS

RS1#

Common Clk Input

Power/Other

F4

BPRI#

F5

BPM3#

BPM0#

Common Clk Input/Output

Power/Other

V

F6

CC

COMP0

Power/Other Input

Power/Other Output

F7

V

SS

V

F8

BPM1#

Common Clk Input/Output

SS_SENSE

Reserved

F9

GTLREF_ADD_END Power/Other Input

V

Power/Other

F10

F11

F12

F13

F14

F15

F16

F17

V

Power/Other

SS

TT

Reserved

BINIT#

BR1#

Common Clk Input/Output

Power/Other

V

Power/Other

SS

CC

SS

V

SS

ADSTB1#

A19#

Source Sync Input/Output

E2

Reserved

VID1

E3

Power/Other Output

A36#

E4

BPM5#

Common Clk Input/Output

ADSTB0#

74

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

Table 4-2.

Pin Listing by Pin Number

(Sheet 5 of 14)

Table 4-2.

Pin Listing by Pin Number

(Sheet 6 of 14)

Signal

Pin No.

Pin Name

DBSY#

Direction

Pin No.

Pin Name

Direction

Buffer Type

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

G1

Common Clk Input/Output

Power/Other

H26

H27

H28

H29

H30

H31

J1

V

Power/Other

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

V

SS

BNR#

RS2#

A37#

Common Clk Input/Output

Common Clk Input

Source Sync Input/Output

GTLREF_ADD_MID Power/Other Input

TRST#

TAP

Input

V

Power/Other

Async GTL+

Power/Other

Async GTL+

Power/Other

J2

SS

THERMTRIP#

A20M#

Output

Input

J3

J4

V

J5

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

J6

J7

J8

J9

G2

J23

J24

J25

J26

J27

J28

J29

J30

J31

K1

G3

G4

G5

G6

G7

G8

G9

G23

G24

G25

G26

G27

G28

G29

G30

G31

H1

LINT1

Input

V

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

K2

K3

K4

K5

K6

K7

K8

K9

H2

K23

K24

K25

K26

K27

K28

K29

K30

K31

L1

H3

H4

H5

H6

H7

H8

H9

H23

H24

H25

L2

Intel® Xeon® Processor 7400 Series Datasheet

75

Pin Listing

Table 4-2.

Pin Listing by Pin Number

(Sheet 7 of 14)

Table 4-2.

Pin Listing by Pin Number

(Sheet 8 of 14)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

L3

L4

V

Power/Other

N24

N25

N26

N27

N28

N29

N30

N31

P1

V

Power/Other

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

L5

L6

L7

L8

L9

L23

L24

L25

L26

L27

L28

L29

L30

L31

M1

P2

P3

P4

P5

P6

P7

P8

P9

M2

P23

P24

P25

P26

P27

P28

P29

P30

P31

R1

M3

M4

M5

M6

M7

M8

M9

M23

M24

M25

M26

M27

M28

M29

M30

M31

N1

R2

R3

R4

R5

R6

R7

R8

R9

N2

R23

R24

R25

R26

R27

R28

R29

R30

R31

N3

N4

N5

N6

N7

N8

N9

N23

76

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

Table 4-2.

Pin Listing by Pin Number

(Sheet 9 of 14)

Table 4-2.

Pin Listing by Pin Number

(Sheet 10 of 14)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

T1

T2

V

Power/Other

V9

V23

V24

V25

V26

V27

V28

V29

V30

V31

W1

V

Power/Other

Power/Other Input

Power/Other

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

T3

T4

T5

T6

T7

T8

T9

T23

T24

T25

T26

T27

T28

T29

T30

T31

U1

W2

W3

TESTHI1

W4

V

SS

W5

BCLK1

FSB Clk

Input

W6

V

Power/Other

TT

W7

W8

W9

GTLREF_DATA_END Power/Other Input

GTLREF_DATA_MID Power/Other Input

U2

W23

W24

W25

W26

W27

W28

W29

W30

W31

Y1

U3

V

Power/Other

FSB Clk

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

U4

U5

U6

U7

U8

U9

U23

U24

U25

U26

U27

U28

U29

U30

U31

V1

Y2

Y3

Y4

BCLK0

Input

Y5

V

Power/Other

SS

TT

SS

Y6

Y7

Y8

RESET#

D62#

Common Clk Input

Source Sync Input/Output

Power/Other

Y9

V2

Y10

Y11

Y12

Y13

Y14

Y15

Y16

V

TT

V3

DSTBP3#

DSTBN3#

Source Sync Input/Output

Power/Other

V4

V5

V

SS

V6

DSTBP2#

DSTBN2#

Source Sync Input/Output

Power/Other

V7

V8

V

CC

Intel® Xeon® Processor 7400 Series Datasheet

77

Pin Listing

Table 4-2.

Pin Listing by Pin Number

(Sheet 11 of 14)

Table 4-2.

Pin Listing by Pin Number

(Sheet 12 of 14)

Signal

Buffer Type

Signal

Pin Name

Pin No.

Pin Name

Direction

Pin No.

Direction

Buffer Type

Y17

Y18

DSTBP1#

DSTBN1#

Source Sync Input/Output

Power/Other

AA30

AA31

AB1

V

Power/Other

SS

CC

SS

CC

Y19

V

SS

Y20

DSTBP0#

DSTBN0#

Source Sync Input/Output

Power/Other

AB2

Y21

AB3

BSEL1

Power/Other Output

Y22

V

AB4

Reserved

CC

Y23

D5#

D2#

Source Sync Input/Output

Power/Other

AB5

V

Power/Other

SS

Y24

AB6

D63#

Source Sync Input/Output

Y25

V

AB7

PWRGOOD

Async GTL+

Power/Other

Input

SS

Y26

D0#

Source Sync Input/Output

AB8

V

CC

Y27

Reserved

AB9

DBI3#

D55#

Source Sync Input/Output

Power/Other

Y28

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AB31

AC1

Y29

V

SS

Y30

V

Power/Other

D51#

D52#

Source Sync Input/Output

Power/Other

CC

Y31

BSEL2

Power/Other Output

Power/Other

AA1

V

CC

SS

AA2

Power/Other

D37#

D32#

D31#

Source Sync Input/Output

Power/Other

AA3

BSEL0

Power/Other Output

Common Clk Input/Output

AA4

BPMb0#

Reserved

AA5

V

CC

AA6

V

Power/Other

D14#

D12#

Source Sync Input/Output

Power/Other

CC

TT

AA7

Power/Other

AA8

D61#

Source Sync Input/Output

Power/Other

V

SS

AA9

V

D13#

D9#

Source Sync Input/Output

Power/Other

SS

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AA27

AA28

AA29

D54#

D53#

Source Sync Input/Output

Power/Other

V

CC

V

D8#

D7#

Source Sync Input/Output

Power/Other

TT

D48#

D49#

Source Sync Input/Output

Power/Other

V

SS

V

SM_EP_A2

SM_EP_A1

SMBus

Input

SS

D33#

Source Sync Input/Output

Power/Other

SMBus

V

Power/Other

SS

CC

SS

D24#

D15#

Source Sync Input/Output

Power/Other

BPMb1#

Common Clk Output

Power/Other

V

AC2

V

CC

SS

CC

TT

D11#

D10#

Source Sync Input/Output

Power/Other

AC3

Power/Other

AC4

Power/Other

V

AC5

D60#

D59#

Source Sync Input/Output

Power/Other

SS

D6#

D3#

Source Sync Input/Output

Power/Other

AC6

AC7

V

SS

V

AC8

D56#

D47#

Source Sync Input/Output

Power/Other

CC

D1#

Source Sync Input/Output

AC9

Reserved

SM_EP_A0

AC10

AC11

V

TT

SMBus

Input

D43#

Source Sync Input/Output

78

Intel® Xeon® Processor 7400 Series Datasheet

Pin Listing

Table 4-2.

Pin Listing by Pin Number

(Sheet 13 of 14)

Table 4-2.

Pin Listing by Pin Number

(Sheet 14 of 14)

Signal

Pin No.

Pin Name

D41#

Direction

Pin No.

Pin Name

Direction

Buffer Type

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AC31

AD1

Source Sync Input/Output

Power/Other

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

AE2

DBI1#

Source Sync Input/Output

Power/Other

V

SS

D50#

DP2#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

D21#

D18#

Source Sync Input/Output

Power/Other

V

CC

D34#

DP0#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

D4#

Source Sync Input/Output

Reserved

SM_WP

Reserved

BPMb2#

BPMb3#

V

SMBus

Input

SS

D25#

D26#

Source Sync Input/Output

Power/Other

V

Common Clk Output

Common Clk Input/Output

Power/Other

CC

D23#

D20#

Source Sync Input/Output

Power/Other

AE3

AE4

V

TT

SS

V

AE5

Power/Other

SS

D17#

Source Sync Input/Output

AE6

Power/Other Input

Source Sync Input/Output

DBI0#

AE7

D58#

SM_CLK

SM_DAT

Reserved

SMBus

Input

AE8

Reserved

D44#

Output

AE9

Source Sync Input/Output

Power/Other

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AE30

D42#

V

Power/Other

V

SS

CC

Power/Other Input

Power/Other

DBI2#

D35#

Source Sync Input/Output

Power/Other

CCPLL

CC

AD2

AD3

Power/Other

V

CC

SS

AD4

Reserved

COMP2

COMP3

DP3#

Power/Other Input

Common Clk Input/Output

Power/Other

AD5

V

Power/Other

TT

AD6

Reserved

D57#

AD7

Source Sync Input/Output

Power/Other

V

CC

AD8

D46#

DP1#

D28#

Common Clk Input/Output

Source Sync Input/Output

Power/Other

AD9

V

SS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

D45#

D40#

Source Sync Input/Output

Power/Other

V

SS

D27#

D22#

Source Sync Input/Output

Power/Other

V

TT

D38#

D39#

Source Sync Input/Output

Power/Other

V

CC

D19#

D16#

Source Sync Input/Output

Power/Other

V

SS

Reserved

V

SS

V

Power/Other

SM_VCC

Reserved

Power/Other

SS

D36#

D30#

Source Sync Input/Output

Power/Other

V

CC

D29#

Source Sync Input/Output

§

Intel® Xeon® Processor 7400 Series Datasheet

79

Pin Listing

80

Intel® Xeon® Processor 7400 Series Datasheet

Signal Definitions

5 Signal Definitions

5.1

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 1 of 8)

Name

A[39:3]#

Type

Description

Notes

40

I/O

A[39:3]# (Address) define a 2 -byte physical memory address space. In sub-

phase 1 of the address phase, these pins transmit the address of a transaction. In

sub-phase 2, these pins transmit transaction type information. These signals must

connect the appropriate pins of all agents on the processor FSB. A[39:3]# are

protected by parity signals AP[1:0]#. A[39:3]# are source synchronous signals

and are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset of

the A[39:3]# pins to determine their power-on configuration. See Section 7.1.

A20M#

I

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit

20 (A20#) before looking up a line in any internal cache and before driving a read/

write transaction on the bus. Asserting A20M# emulates the 8086 processor's

address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported

in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion

of the corresponding I/O write bus transaction.

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[39:3]# pins. All bus agents observe the ADS# activation to begin

parity checking, protocol checking, address decode, internal snoop, or deferred

reply ID match operations associated with the new transaction. This signal must be

connected to the appropriate pins on all Intel® Xeon® Processor 7400 Series FSB

agents.

ADSTB[1:0]#

Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and

falling edge. Strobes are associated with signals as shown below.

Signals

Associated Strobes

REQ[4:0],

ADSTB0#

A[37:36,16:3]#

A[39:38, 35:17]#

ADSTB1#

AP[1:0]#

I/O

AP[1:0]# (Address Parity) are driven by the requestor one common clock after

ADS#, A[39:3]#, REQ[4:0]# are driven. A correct parity signal is electrically high

if an even number of covered signals are electrically low and electrically low if an

odd number of covered signals are electrically low. This allows parity to be

electrically high when all the covered signals are electrically high. AP[1:0]# should

connect the appropriate pins of all processor FSB agents. The following table

defines the coverage for these signals.

Request Signals

Subphase 1

Subphase 2

A[39:24]#

A[23:3]#

AP0#

AP1#

AP0#

REQ[4:0]#

BCLK[1:0]

I

The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB

frequency. All processor FSB agents must receive these signals to drive their

outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing V

.

CROSS

Intel® Xeon® Processor 7400 Series Datasheet

81

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 2 of 8)

Name

Type

Description

Notes

BINIT#

I/O

BINIT# (Bus Initialization) may be observed and driven by all processor FSB

agents and if used, must connect the appropriate pins of all such agents. If the

BINIT# driver is enabled during power on configuration, BINIT# is asserted to

signal any bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration (see Section 7.1)

and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity

and bus request arbitration state machines. The bus agents do not reset their I/O

Queue (IOQ) and transaction tracking state machines upon observation of BINIT#

assertion. Once the BINIT# assertion has been observed, the bus agents will re-

arbitrate for the FSB and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is disabled during power-on configuration, a priority agent

may handle an assertion of BINIT# as appropriate to the error handling

architecture of the system.

BNR#

I/O

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is

unable to accept new bus transactions. During a bus stall, the current bus owner

cannot issue any new transactions.

Since multiple agents might need to request a bus stall at the same time, BNR# is

a wired-OR signal which must connect the appropriate pins of all processor FSB

agents. In order to avoid wired-OR glitches associated with simultaneous edge

transitions driven by multiple drivers, BNR# is activated on specific clock edges

and sampled on specific clock edges.

BPM5#

BPM4#

BPM3#

BPM[2:1]#

BPM0#

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.

They are outputs from the processor which indicate the status of breakpoints and

programmable counters used for monitoring processor performance. BPM[5:0]#

should connect the appropriate pins of all FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a

processor output used by debug tools to determine processor debug readiness.

I/O

O

I/O

O

I/O

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is

used by debug tools to request debug operation of the processors.

BPM[5:4]# must be bussed to all bus agents. Please refer to the appropriate

platform design guidelines for more detailed information.

BPMb3#

BPMb[2:1]#

BPMb0#

I/O

O

I/O

BPMb[3:0]# (Breakpoint Monitor) are a second set of breakpoint and performance

monitor signals. They are additional outputs from the processor which indicate the

status of breakpoints and programmable counters used for monitoring processor

performance. BPMb[3:0]# should connect the appropriate pins of all FSB agents.

BPRI#

I

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

FSB. It must connect the appropriate pins of all processor FSB agents. Observing

BPRI# active (as asserted by the priority agent) causes all other agents to stop

issuing new requests, unless such requests are part of an ongoing locked

operation. The priority agent keeps BPRI# asserted until all of its requests are

completed, then releases the bus by deasserting BPRI#.

BR[1:0]#

BSEL[2:0]

I/O

O

The BR[1:0]# signals are sampled on the active-to-inactive transition of RESET#.

The signal which the agent samples asserted determines its agent ID. BR0# drives

the BREQ0# signal in the system and is used by the processor to request the bus.

These signals do not have on-die termination and must be terminated.

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor

input clock frequency. Table 2-2 defines the possible combinations of the signals

and the frequency associated with each combination. The required frequency is

determined by the processors, chipset, and clock synthesizer. All FSB agents must

operate at the same frequency. For more information about these signals,

including termination recommendations, refer to the appropriate platform design

guideline.

COMP[3:0]

I

COMP[3:0] must be terminated to VSS on the baseboard using precision resistors.

These inputs configure the AGTL+ drivers of the processor. Refer to the

appropriate platform design guidelines for implementation details.

82

Intel® Xeon® Processor 7400 Series Datasheet

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 3 of 8)

Name

D[63:0]#

Type

Description

Notes

I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor FSB agents, and must connect the appropriate pins on all

such agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals, and will thus be driven four times

in a common clock period. D[63:0]# are latched off the falling edge of

both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals

correspond to a pair of one DSTBP# and one DSTBN#. The following

table shows the grouping of data signals to strobes and DBI#.

DSTBN#/

DSTBP#

Data Group

DBI#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DBI# signals determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DBI# signal.

When the DBI# signal is active, the corresponding data group is

inverted and therefore sampled active high.

DBI[3:0]#

I/O

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity

of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the

data bus is inverted. If more than half the data bits, within, within a 16-bit group,

would have been asserted electronically low, the bus agent may invert the data

bus signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment to Data Bus

Bus Signal

Data Bus Signals

DBI0#

DBI1#

DBI2#

DBI3#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

DBSY#

I/O

I

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on

the processor FSB to indicate that the data bus is in use. The data bus is released

after DBSY# is deasserted. This signal must connect the appropriate pins on all

processor FSB agents.

DEFER#

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility

of the addressed memory or I/O agent. This signal must connect the appropriate

pins of all processor FSB agents.

DP[3:0]#

DRDY#

I/O

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They

are driven by the agent responsible for driving D[63:0]#, and must connect the

appropriate pins of all processor FSB agents.

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

indicating valid data on the data bus. In a multi-common clock data transfer,

DRDY# may be deasserted to insert idle clocks. This signal must connect the

appropriate pins of all processor FSB agents.

Intel® Xeon® Processor 7400 Series Datasheet

83

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 4 of 8)

Name

DSTBN[3:0]#

Type

Description

Notes

I/O

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobes

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobes

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FERR#/PBE#

O

FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal

and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/

PBE# indicates a floating-point error and will be asserted when the processor

detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/

PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included

for compatibility with systems using MS-DOS*-type floating-point error reporting.

When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the

processor has a pending break event waiting for service. The assertion of FERR#/

PBE# indicates that the processor should be returned to the Normal state. For

additional information on the pending break event functionality, including the

identification of support of the feature and enable/disable information, refer to Vol.

®

3 of the Intel 64 and IA-32 Architectures Software Developer’s Manual and the

®

AP-485 Intel Processor Identification and the CPUID Instruction application note.

FORCEPR#

I

The FORCEPR# (force power reduction) input can be used by the platform to cause

the Intel® Xeon® Processor 7400 Series to activate the Thermal Control Circuit

(TCC).

GTLREF_ADD_MID

GTLREF_ADD_END

GTLREF_ADD determines the signal reference level for AGTL+ address and

common clock input pins. GTLREF_ADD is used by the AGTL+ receivers to

determine if a signal is a logical 0 or a logical 1. Please refer to Table 2-17 and the

appropriate platform design guidelines for additional details.

GTLREF_DATA_MID

GTLREF_DATA_END

I

GTLREF_DATA determines the signal reference level for AGTL+ data input pins.

GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0

or a logical 1. Please refer to Table 2-17 and the appropriate platform design

guidelines for additional details.

HIT#

HITM#

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any FSB agent may assert both HIT# and HITM# together to indicate that

it requires a snoop stall, which can be continued by reasserting HIT# and HITM#

together.

IERR#

O

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

processor FSB. This transaction may optionally be converted to an external error

signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted

until the assertion of RESET#.

This signal does not have on-die termination.

84

Intel® Xeon® Processor 7400 Series Datasheet

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 5 of 8)

Name

Type

Description

Notes

IGNNE#

I

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is deasserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion

of the corresponding I/O write bus transaction.

INIT#

I

INIT# (Initialization), when asserted, resets integer registers inside all processors

without affecting their internal caches or floating-point registers. Each processor

then begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal and must connect the appropriate pins

of all processor FSB agents.

LINT[1:0]

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all FSB

agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes

INTR, a maskable interrupt request signal, and LINT1/NMI becomes NMI, a

nonmaskable interrupt. INTR and NMI are backward compatible with the signals of

®

those names on the Pentium processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of the APIC

register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is

enabled by default after Reset, operation of these pins as LINT[1:0] is the default

configuration.

LL_ID[1:0]

O

The LL_ID[1:0] signals are used to select the correct loadline slope for the

processor. These signals are not connected to the processor die. A logic 0 is pulled

to ground and a logic 1 is a no-connect on the Intel® Xeon® Processor 7400

Series package.

00: Reserved

01: 1.25 mΩ Load Line

10: Reserved

11: Reserved

LOCK#

I/O

LOCK# indicates to the system that a transaction must occur atomically. This

signal must connect the appropriate pins of all processor FSB agents. For a locked

sequence of transactions, LOCK# is asserted from the beginning of the first

transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the processor

FSB, it will wait until it observes LOCK# deasserted. This enables symmetric

agents to retain ownership of the processor FSB throughout the bus locked

operation and ensure the atomicity of lock.

MCERR#

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable

error without a bus protocol violation. It may be driven by all processor

FSB agents.

MCERR# assertion conditions are configurable at a system level.

Assertion options are defined by the following options:

•

Enabled or disabled.

Asserted, if configured, for internal errors along with IERR#.

Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

•

Asserted by any bus agent when it observes an error in a bus transaction.

®

For more details regarding machine check architecture, refer to the Intel 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3: System Programming

Guide.

PECI

I/O

O

PECI is a proprietary one-wire bus interface that provides a communication

channel between Intel processor and chipset components to external thermal

monitoring devices. See Section 6.3, “Platform Environment Control Interface

(PECI)” for more on the PECI interface.

PROC_ID[1:0]

PROC_ID signals are used to identify which processor is installed.

00: Intel® Xeon® Processor 7400 Series

01: Intel® Xeon® Processor 7300 and 7200 Series

10: Reserved

11: Reserved

Intel® Xeon® Processor 7400 Series Datasheet

85

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 6 of 8)

Name

Type

Description

Notes

PROCHOT#

O

PROCHOT# (Processor Hot) will go active when the processor’s temperature

monitoring sensor detects that the processor has reached its maximum safe

operating temperature. This indicates that the Thermal Control Circuit (TCC) has

been activated, if enabled. The TCC will remain active until shortly after the

processor deasserts PROCHOT#. See Section 6.2.5 for more details.

PWRGOOD

I

PWRGOOD (Power Good) is an input. The processor requires this signal to be a

clean indication that all processor clocks and power supplies are stable and within

their specifications. “Clean” implies that the signal will remain low (capable of

sinking leakage current), without glitches, from the time that the power supplies

are turned on until they come within specification. The signal must then transition

monotonically to a high state. Figure 2-20 illustrates the relationship of PWRGOOD

to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks

and power must again be stable before a subsequent rising edge of PWRGOOD. It

must also meet the minimum pulse width specification in Table 2-15, and be

followed by a 1-10 ms RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

REQ[4:0]#

RESET#

I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor

FSB agents. They are asserted by the current bus owner to define the currently

active transaction type. These signals are source synchronous to ADSTB[1:0]#.

Refer to the AP[1:0]# signal description for details on parity checking of these

signals.

I

Asserting the RESET# signal resets all processors to known states and invalidates

their internal caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least 1 ms after VCC and BCLK have reached

their proper specifications. On observing active RESET#, all FSB agents will

deassert their outputs within two clocks. RESET# must not be kept asserted for

more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET#

for power-on configuration. These configuration options are described in the

Section 7.1.

This signal does not have on-die termination and must be terminated on the

system board.

RS[2:0]#

RSP#

I

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of all processor FSB agents.

RSP# (Response Parity) is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#, the signals for

which RSP# provides parity protection. It must connect to the appropriate pins of

all processor FSB agents.

A correct parity signal is high if an even number of covered signals are low and low

if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also

high, since this indicates it is not being driven by any agent guaranteeing correct

parity.

SKTOCC#

SM_CLK

O

SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate

that the processor is present. There is no connection to the processor silicon for

this signal.

I/O

The SM_CLK (SMBus Clock) signal is an input clock to the system management

logic which is required for operation of the system management features of the

processor. This clock is driven by the SMBus controller and is asynchronous to

other clocks in the processor. The processor includes a 10 kΩ pull-up resistor to

SM_VCC for this signal.

SM_DAT

I/O

I

The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal

provides the single-bit mechanism for transferring data between SMBus devices.

The processor includes a 10 kΩ pull-up resistor to SM_VCC for this signal.

SM_EP_A[2:0]

The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in

conjunction with the upper address bits in order to maintain unique addresses on

the SMBus in a system with multiple processors. To set an SM_EP_A line high, a

pull-up resistor should be used that is no larger than 1 kΩ. The processor includes

a 10 kΩ pull-down resistor to V for each of these signals.

SS

SM_VCC

I

SM_VCC provides power to the SMBus components on the processor package.

86

Intel® Xeon® Processor 7400 Series Datasheet

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 7 of 8)

Name

Type

Description

Notes

SM_WP

SMI#

I

WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch

EEPROM is write-protected when this input is pulled high to SM_VCC. The

processor includes a 10 kΩ pull-down resistor to V for this signal.

SS

I

SMI# (System Management Interrupt) is asserted asynchronously by system logic.

On accepting a System Management Interrupt, processors save the current state

and enter System Management Mode (SMM). An SMI Acknowledge transaction is

issued, and the processor begins program execution from the SMM handler.

If SMI# is asserted during the deassertion of RESET# the processor will tri-state

its outputs. See Section 7.1.

STPCLK#

STPCLK# (Stop Clock), when asserted, causes processors to enter a low power

Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and

stops providing internal clock signals to all processor core units except the FSB and

APIC units. The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor

restarts its internal clock to all units and resumes execution. The assertion of

STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK

I

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as

the Test Access Port).

TDI

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO

O

I

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides

the serial output needed for JTAG specification support.

TESTHI[1:0]

TESTHI[1:0] must be connected to a V_TTpower source through a resistor for

proper processor operation. Refer to Section 2.5 for TESTHI grouping restrictions.

TESTIN1

TESTIN2

I

TESTIN1 must be connected to a VTT power source through a resistor as well as to

the TESTIN2 pin of the same socket for proper processor operation.

TESTIN2 must be connected to a VTT power source through a resistor as well as to

the TESTIN1 pin of the same socket for proper processor operation.

Refer to Section 2.5 for TESTIN restrictions.

THERMTRIP#

O

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a temperature beyond which permanent silicon damage

may occur. Measurement of the temperature is accomplished through an internal

thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its

internal clocks (thus halting program execution) in an attempt to reduce the

processor junction temperature. To protect the processor, its core voltage (V

)

CC

must be removed following the assertion of THERMTRIP#. See Figure 2-17 and

Table 2-22 for the appropriate power down sequence and timing requirements.

Intel is currently evaluating whether V must also be removed.

TT

Driving of the THERMTRIP# signals is enabled within 10 ms of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-

assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s

junction temperature remains at or above the trip level, THERMTRIP# will again be

asserted within 10 ms of the assertion of PWRGOOD.

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY#

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of all FSB agents.

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven

low during power on Reset.

V

The Intel® Xeon® Processor 7400 Series implement an on-die PLL filter solution.

CCPLL

The V

input is used as a PLL supply voltage.

CCPLL

VCC_SENSE

VCC_SENSE2

O

VCC_SENSE and VCC_SENSE2 provides an isolated, low impedance connection to

the processor core power and ground. This signal should be connected to the

voltage regulator feedback signal, which insures the output voltage (that is,

processor voltage) remains within specification. Please see the applicable platform

design guide for implementation details.

Intel® Xeon® Processor 7400 Series Datasheet

87

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 8 of 8)

Name

Type

Description

Notes

VID[6:1]

O

VID[6:1] (Voltage ID) pins are used to support automatic selection of power

supply voltages (V ). These are CMOS signals that are driven by the processor

CC

and must be pulled up through a resistor. Conversely, the voltage regulator output

must be disabled prior to the voltage supply for these pins becomes invalid. The

VID pins are needed to support processor voltage specification variations. See

Table 2-3 for definitions of these pins. The VR must supply the voltage that is

requested by these pins, or disable itself.

VSS_SENSE

VSS_SENSE2

O

VSS_SENSE and VSS_SENSE2 provides an isolated, low impedance connection to

the processor core power and ground. This signal should be connected to the

voltage regulator feedback signal, which insures the output voltage (that is,

processor voltage) remains within specification. Please see the applicable platform

design guide for implementation details.

VTT

P

The FSB termination voltage input pins. Refer to Table 2-9 for further details.

VTT_SEL

O

The VTT_SEL signal is used to select the correct V_TTvoltage level for the processor.

VTT_SEL is connected to ground on the Intel® Xeon® Processor 7400 Series

package.

§

88

Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

6 Thermal Specifications

6.1

Package Thermal Specifications

The Intel® Xeon® Processor 7400 Series require a thermal solution to maintain

temperatures within its operating limits. Any attempt to operate the processor outside

these operating limits may result in permanent damage to the processor and

potentially other components within the system. As processor technology changes,

thermal management becomes increasingly crucial when building computer systems.

Maintaining the proper thermal environment is key to reliable, long-term system

operation.

A complete solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks

attached to the processor integrated heat spreader (IHS). Typical system level thermal

solutions may consist of system fans combined with ducting and venting.

This section provides data necessary for developing a complete thermal solution. For

more information on designing a component level thermal solution, refer to the Intel®

Xeon® Processor 7400 Series Thermal Mechanical Design Guide.

6.1.1

Thermal Specifications

To allow the optimal operation and long-term reliability of Intel processor-based

systems, the processor must remain within the minimum and maximum case

temperature (T_CASE) specifications as defined by the applicable thermal profile (see

Table 6-2 and Figure 6-1 for the Intel® Xeon® X7460 Processor, Table 6-3 and

Figure 6-2 for the 6-core Intel® Xeon® Processor E7400 Series, Figure 6-3 and

Table 6-4 for the 4-core Intel® Xeon® Processor E7400 Series, and Table 6-5 and

Figure 6-4 for the 6-core Intel® Xeon® Processor L7400 Series and Table 6-6 and

Figure 6-5 for the 4-core Intel® Xeon® Processor L7400 Series). Thermal solutions not

designed to provide this level of thermal capability may affect the long-term reliability

of the processor and system. For more details on thermal solution design, please refer

to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide.

The Intel® Xeon® Processor 7400 Series implement a methodology for managing

processor temperatures which is intended to support acoustic noise reduction through

fan speed control and to assure processor reliability. Selection of the appropriate fan

speed is based on the relative temperature data reported by the processor’s Platform

Environment Control Interface (PECI) bus as described in Section 6.3. If the value

reported via PECI is less than TCONTROL, then the case temperature is permitted to

exceed the Thermal Profile. If the value reported via PECI is greater than or equal to

TCONTROL, then the processor case temperature must remain at or below the

temperature as specified by the thermal profile. The temperature reported over PECI is

always a negative value and represents a delta below the onset of thermal control

circuit (TCC) activation, as indicated by PROCHOT# (see Section 6.2, Processor

Thermal Features). Systems that implement fan speed control must be designed to use

this data. Systems that do not alter the fan speed only need to guarantee the case

temperature meets the thermal profile specifications.

Intel has developed a thermal profile of which can be implemented with the Intel®

Xeon® X7460 Processor to ensure adherence to Intel reliability requirements. The

Intel® Xeon® X7460 Processor Thermal Profile (see Figure 6-1; Table 6-2) is

representative of a volumetrically unconstrained thermal solution (that is, industry

Intel® Xeon® Processor 7400 Series Datasheet

89

Thermal Specifications

enabled 2U heatsink). In this scenario, it is expected that the Thermal Control Circuit

(TCC) would only be activated for very brief periods of time when running the most

power intensive applications. Intel has developed the thermal profile to allow

customers to choose the thermal solution and environmental parameters that best suit

their platform implementation. Refer to the Intel® Xeon® Processor 7400 Series

Thermal Mechanical Design Guide for details on system thermal solution design,

thermal profiles and environmental considerations.

The Intel® Xeon® Processor E7400 Series (see Figure 6-2; Table 6-3) and Intel®

Xeon® Processor L7400 Series (see Figure 6-4; Table 6-5) supports a single Thermal

Profile. The Thermal Profiles are indicative of a constrained thermal environment

(Ex: 1U form factor). Because of the reduced cooling capability represented by this

solution, the probability of TCC activation and performance loss is increased.

Additionally, utilization of a thermal solution that does not meet the Thermal Profile will

violate the thermal specifications and may result in permanent damage to the

processor. Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical

Design Guide for details on system thermal solution design, thermal profiles and

environmental considerations.

The upper point of the thermal profile consists of the Thermal Design Power (TDP) and

the associated T_CASEvalue. It should be noted that the upper point associated with

Intel® Xeon® X7460 Processor Thermal Profile (x = TDP and y = T_{CASE_MAX}P @ TDP)

represents a thermal solution design point. In actuality the processor case temperature

will not reach this value due to TCC activation (see Figure 6-1 for the Intel® Xeon®

X7460 Processor).

Analysis indicates that real applications are unlikely to cause the processor to consume

maximum power dissipation for sustained time periods. Intel recommends that

complete thermal solution designs target the Thermal Design Power (TDP) instead of

the maximum processor power consumption. The Intel Thermal Monitor feature is

intended to help protect the processor in the event that an application exceeds the TDP

recommendation for a sustained time period. For more details on this feature, refer to

Section 6.2. To ensure maximum flexibility for future requirements, systems should be

designed to the Flexible Motherboard (FMB) guidelines, even if a processor with lower

power dissipation is currently planned. Intel Thermal Monitor or Intel Thermal

Monitor 2 feature must be enabled for the processor to remain within its

specifications.

90

Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

Table 6-1.

Processor Thermal Specifications

Thermal Design

Power

Core

Frequency

Minimum

TCASE (°C)

Maximum

TCASE (°C)

Notes

(W)

Intel® Xeon® X7460

130

90

5

See Figure 6-1,Figure 6-3;

Table 6-2,Table 6-4;

1, 2, 3, 4, 5

Processor Launch to FMB

Intel® Xeon® Processor

E7400 Series Launch to

FMB

See Figure 6-2; Table 6-3;

See Figure 6-4; Table 6-5;

See Figure 6-5; Table 6-6

6-core Intel® Xeon®

Processor L7400 Series

Launch to FMB

65

50

5

1, 2, 3, 4, 5

4-core Intel® Xeon®

Processor L7400 Series

Launch to FMB

Notes:

1.

These values are specified at V

for all processor frequencies. Systems must be designed to ensure

CC_MAX

the processor is not to be subjected to any static V and I combination wherein V exceeds V at

specified I . Please refer to the loadline specifications in Section 2.11.

CC

CC_MAX

CC

2.

3.

4.

5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum T

These specifications are based pre-silicon estimates and simulations. These specifications will be updated

with characterized data from silicon measurements in a future release of this document.

Power specifications are defined at all VIDs found in Table 2-3. The Intel® Xeon® Processor 7400 Series

may be shipped under multiple VIDs for each frequency.

.

CASE

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

Figure 6-1. Intel® Xeon® X7460 Processor Thermal Profile

70

65

60

55

50

T

CASE

=0.146 x Power +45 ^oC

45

40

35

30

0

10

20

30

40

50

60

70

80

90

100

110

120

130

Power (W)

Notes:

1.

Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 6-2 for

discrete points that constitute the thermal profile.

Intel® Xeon® Processor 7400 Series Datasheet

91

Thermal Specifications

2.

3.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

Table 6-2.

Intel® Xeon® X7460 Processor Thermal Profile Table

Power (W)

T

(°C)

CASE_MAX

45

0

10

46.5

47.9

49.4

50.8

52.3

53.8

55.2

56.7

58.2

59.6

61.1

62.5

64

20

30

40

50

60

70

80

90

100

110

120

130

Notes:

1.

2.

Thermal Profile is representative of a volumetrically unconstrained platform.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

3.

92

Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

Figure 6-2. 6-Core Intel® Xeon® Processor E7400 Series Thermal Profile

75.0

70.0

65.0

60.0

55.0

50.0

T

_CASE=0.256 x Power +45 ^oC

45.0

40.0

35.0

30.0

0

10

20

30

40

50

60

70

80

90

Power (W)

Notes:

1.

Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-3 for

discrete points that constitute the thermal profile.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

2.

3.

Table 6-3.

6-Core Intel® Xeon® Processor E7400 Series Thermal Profile Table

Power (W)

T

(°C)

CASE_MAX

0

45.0

10

20

30

40

50

60

70

80

90

47.6

50.1

52.7

55.2

57.8

60.3

62.9

65.4

68.0

Notes:

1.

2.

Thermal Profile is representative of a volumetrically unconstrained platform.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

3.

Intel® Xeon® Processor 7400 Series Datasheet

93

Thermal Specifications

Figure 6-3. 4-Core Intel® Xeon® Processor E7400 Series Thermal Profile

70.0

65.0

60.0

55.0

50.0

T

_CASE= 0.222 x Power + 45 ^oC

45.0

40.0

35.0

30.0

0

10

20

30

40

50

60

70

80

90

Power (W)

Notes:

1.

Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-4 for

discrete points that constitute the thermal profile.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

2.

3.

Table 6-4.

4-Core Intel® Xeon® Processor E7400 Series Thermal Profile Table

Power (W)

T

(°C)

CASE_MAX

45.0

0

10

20

30

40

50

60

70

80

90

47.2

49.4

51.7

53.9

56.1

58.3

60.6

62.8

65.0

Notes:

1.

2.

Thermal Profile is representative of a volumetrically constrained platform.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

3.

94

Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

Figure 6-4. 6-Core Intel® Xeon® Processor L7400 Series Thermal Profile

60.0

55.0

50.0

T

_CASE= 0.431 x Power + 45 ^oC

45.0

40.0

35.0

0

10

20

30

40

50

60

Power (W)

Notes:

1.

Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-5 for

discrete points that constitute the thermal profile.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

2.

3.

Table 6-5.

6-Core Intel® Xeon® Processor L7400 Series Thermal Profile Table

Power (W)

T

(°C)

CASE_MAX

0

45

10

20

30

40

50

60

65

49.3

53.6

57.9

62.2

66.5

70.8

73

Notes:

1.

2.

Thermal Profile is representative of a volumetrically unconstrained platform.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

3.

Intel® Xeon® Processor 7400 Series Datasheet

95

Thermal Specifications

Figure 6-5. 4-Core Intel® Xeon® Processor L7400 Series Thermal Profile

70.0

65.0

60.0

55.0

50.0

45.0

40.0

35.0

T_CASE= 0.400 x Power + 45 ^oC

0

10

20

30

40

50

Power (W)

Notes:

1.

Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-6 for

discrete points that constitute the thermal profile.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

2.

3.

Table 6-6.

4-Core Intel® Xeon® Processor L7400 Series Thermal Profile Table

Power (W)

T

(°C)

CASE_MAX

0

45

49

53

57

61

65

10

20

30

40

50

Notes:

1.

2.

Thermal Profile is representative of a volumetrically unconstrained platform.

Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of

thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC

activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and

environmental implementation details.

3.

96

Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

6.1.2

Thermal Metrology

The minimum and maximum case temperatures (T_CASE) are specified in Table 6-2

through Table 6-5, and are measured at the geometric top center of the processor

integrated heat spreader (IHS). Figure 6-6 illustrates the location where T_CASE

temperature measurements should be made. For detailed guidelines on temperature

measurement methodology, refer to the Intel® Xeon® Processor 7400 Series Thermal

Mechanical Design Guide.

Figure 6-6. Case Temperature (T_CASE) Measurement Location

Measure from edge of IHS

19.25 mm [0.76 in]

Measure T

at this point

(geometric^Cc^Ae^Sn^Eter of IHS)

19.25 mm [0.76 in]

53.34 mm FC-mPGA8 Package

Thermal grease should cover

entire area of IHS

Note: Figure is not to scale and is for reference only.

6.2

Processor Thermal Features

6.2.1

Intel® Thermal Monitor Features

Intel® Xeon® Processor 7400 Series provide two thermal monitor features, Intel®

Thermal Monitor (TM1) and Enhanced Thermal Monitor (TM2). The TM1 and TM2 must

both be enabled in BIOS for the processor to be operating within specifications. When

both are enabled, TM2 will be activated first and TM1 will be added if TM2 is not

effective.

6.2.2

Intel Thermal Monitor

The Intel Thermal Monitor (TM1) feature helps control the processor temperature by

activating the Thermal Control Circuit (TCC) when the processor silicon reaches its

maximum operating temperature. The TCC reduces processor power consumption as

needed by modulating (starting and stopping) the internal processor core clocks. The

Intel Thermal Monitor or Enhanced Thermal Monitor (Thermal Monitor 2) must be

enabled for the processor to be operating within specifications. The temperature at

which Thermal Monitor activates the thermal control circuit is not user configurable and

Intel® Xeon® Processor 7400 Series Datasheet

97

Thermal Specifications

is not software visible. Bus traffic is snooped in the normal manner, and interrupt

requests are latched (and serviced during the time that the clocks are on) while the

TCC is active.

When the Intel Thermal Monitor is enabled, and a high temperature situation exists

(that is, TCC is active), the clocks will be modulated by alternately turning the clocks

off and on at a duty cycle specific to the processor (typically 30 - 50%). Cycle times are

processor speed dependent and will decrease as processor core frequencies increase. A

small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the TCC goes inactive and clock

modulation ceases.

With a thermal solution designed to meet the Intel® Xeon® Processor 7400 Series

Thermal Profiles, it is anticipated that the TCC would only be activated for very short

periods of time when running the most power intensive applications. The processor

performance impact due to these brief periods of TCC activation is expected to be so

minor that it would be immeasurable. In addition, a thermal solution that is

significantly under designed may not be capable of cooling the processor even when

the TCC is active continuously. Refer to the Intel® Xeon® Processor 7400 Series

Thermal Mechanical Design Guide or information on designing a thermal solution.

The duty cycle for the TCC, when activated by the Intel Thermal Monitor, is factory

configured and cannot be modified. The Thermal Monitor does not require any

additional hardware, software drivers, or interrupt handling routines.

6.2.3

Intel Thermal Monitor 2

The Intel® Xeon® Processor 7400 Series adds supports for an Enhanced Thermal

Monitor capability known as Intel Thermal Monitor 2 (TM2). This mechanism provides

an efficient means for limiting the processor temperature by reducing the power

consumption within the processor. The Intel Thermal Monitor or Enhanced Thermal

Monitor must be enabled for the processor to be operating within specifications. TM2

requires support for dynamic VID transitions in the platform.

Note:

Not all Intel® Xeon® Processor 7400 Series are capable of supporting TM2. More detail

on which processor frequencies will support TM2 will be provided in future releases of

the Intel® Xeon® Processor 7400 Series Specification Update when available.

When Intel Thermal Monitor 2 is enabled, and a high temperature situation is detected,

the Thermal Control Circuit (TCC) will be activated for all processor cores. The TCC

causes the processor to adjust its operating frequency (via the bus multiplier) and

input voltage (via the VID signals). This combination of reduced frequency and VID

results in a reduction to the processor power consumption.

A processor enabled for Intel Thermal Monitor 2 includes two operating points, each

consisting of a specific operating frequency and voltage, which is identical for both

processor dies. The first operating point represents the normal operating condition for

the processor. Under this condition, the core-frequency-to-system-bus multiplier

utilized by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID

that is specified in Table 2-3.

The second operating point consists of both a lower operating frequency and voltage.

The lowest operating frequency is determined by the lowest supported bus ratio (1/8

for the Intel® Xeon® Processor 7400 Series). When the TCC is activated, the processor

automatically transitions to the new frequency. This transition occurs rapidly, on the

98

Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

order of 5 µs. During the frequency transition, the processor is unable to service any

bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will

be latched and kept pending until the processor resumes operation at the new

frequency.

Once the new operating frequency is engaged, the processor will transition to the new

core operating voltage by issuing a new VID code to the voltage regulator. The voltage

regulator must support dynamic VID steps in order to support Intel Thermal Monitor 2.

During the voltage change, it will be necessary to transition through multiple VID codes

to reach the target operating voltage. Each step will be one VID table entry (see

Table 2-3). The processor continues to execute instructions during the voltage

transition. Operation at the lower voltage reduces the power consumption of the

processor.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the operating frequency and

voltage transition back to the normal system operating point. Transition of the VID code

will occur first, in order to ensure proper operation once the processor reaches its

normal operating frequency. Refer to Figure 6-7 for an illustration of this ordering.

Figure 6-7. Intel Thermal Monitor 2 Frequency and Voltage Ordering

T_TM2

Temperature

f_MAX

f_TM2

Frequency

V_NOM

V_TM2

Vcc

Time

T(hysterisis)

The PROCHOT# signal is asserted when a high temperature situation is detected,

regardless of whether Intel Thermal Monitor or Intel Thermal Monitor 2 is enabled.

6.2.4

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force

the processor to reduce its power consumption. This mechanism is referred to as

“On-Demand” mode and is distinct from the Intel Thermal Monitor and Intel Thermal

Monitor 2 features. On-Demand mode is intended as a means to reduce system level

power consumption. Systems utilizing the Intel® Xeon® Processor 7400 Series must

not rely on software usage of this mechanism to limit the processor temperature. If bit

4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately

reduce its power consumption via modulation (starting and stopping) of the internal

core clock, independent of the processor temperature. When using On-Demand mode,

the duty cycle of the clock modulation is programmable via bits 3:1 of the same

Intel® Xeon® Processor 7400 Series Datasheet

99

Thermal Specifications

IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be

programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments.

On-Demand mode may be used in conjunction with the Intel Thermal Monitor;

however, if the system tries to enable On-Demand mode at the same time the TCC is

engaged, the factory configured duty cycle of the TCC will override the duty cycle

selected by the On-Demand mode.

6.2.5

PROCHOT# Signal

An external signal, PROCHOT# (processor hot) is asserted when the temperature of

either processor die has reached its factory configured trip point. If the Intel Thermal

Monitor is enabled (note that the Intel Thermal Monitor must be enabled for the

processor to be operating within specification), the TCC will be active when PROCHOT#

is asserted. The processor can be configured to generate an interrupt upon the

assertion or de-assertion of PROCHOT#. Refer to the Intel^®64 and IA-32 Architectures

Software Developer’s Manual.

PROCHOT# is designed to assert at or a few degrees higher than maximum T_CASE(as

specified by Thermal Profile) when dissipating TDP power, and cannot be interpreted as

an indication of processor case temperature. This temperature delta accounts for

processor package, lifetime and manufacturing variations and attempts to ensure the

Thermal Control Circuit is not activated below maximum T_CASEwhen dissipating TDP

power. There is no defined or fixed correlation between the PROCHOT# trip

temperature, or the case temperature. Thermal solutions must be designed to the

processor specifications and cannot be adjusted based on experimental measurements

of T_CASE, or PROCHOT#.

6.2.6

FORCEPR# Signal

The FORCEPR# (force power reduction) input can be used by the platform to cause the

Intel® Xeon® Processor 7400 Series to activate the TCC. If the Intel Thermal Monitor

is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal.

Assertion of the FORCEPR# signal will activate TCC for all processor cores. The TCC will

remain active until the system deasserts FORCEPR#. FORCEPR# is an asynchronous

input. FORCEPR# can be used to thermally protect other system components. To use

the VR as an example, when FORCEPR# is asserted, the TCC circuit in the processor

will activate, reducing the current consumption of the processor and the corresponding

temperature of the VR.

It should be noted that assertion of FORCEPR# does not automatically assert

PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high

temperature situation is detected. A minimum pulse width of 500 µs is recommended

when FORCEPR# is asserted by the system. Sustained activation of the FORCEPR#

signal may cause noticeable platform performance degradation.

Refer to the Caneland Platform Design Guide for details on implementing the

FORCEPR# signal feature.

6.2.7

THERMTRIP# Signal

Regardless of whether or not the Intel Thermal Monitor or Intel Thermal Monitor 2 is

enabled, in the event of a catastrophic cooling failure, the processor will automatically

shut down when either die has reached an elevated temperature (refer to the

THERMTRIP# definition in Table 5-1). At this point, the FSB signal THERMTRIP# will go

active and stay active as described in Table 5-1. THERMTRIP# activation is independent

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Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted,

processor core voltage (V_CC) must be removed within the time frame defined in

Table 2-22 and Figure 2-17. Intel also recommends the removal of V_TT.

6.3

Platform Environment Control Interface (PECI)

6.3.1

Introduction

PECI offers an interface for thermal monitoring of Intel processor and chipset

components. It uses a single wire, thus alleviating routing congestion issues.

Figure 6-8 shows an example of the PECI topology in a system with Intel® Xeon®

Processor 7400 Series. PECI uses CRC checking on the host side to ensure reliable

transfers between the host and client devices. Also, data transfer speeds across the

PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI

interface on Intel® Xeon® Processor 7400 Series is disabled by default and must be

enabled through BIOS.

Figure 6-8. PECI Topology

0

x

3

0

Domain0

Domain1

C28

Socket

Cluster ID[1:0] = 0

0

x

3

0

x

3

2

Domain0

Domain1

C28

Socket

Cluster ID[1:0] = 1

1

0

x

3

2

PECI Host

Controller

0

x

3

1

Domain0

Domain1

C28

Socket

Cluster ID[1:0] = 2

2

0

x

3

1

0

x

3

Domain0

Domain1

C28

Socket

Cluster ID[1:0] = 3

3

0

x

3

Note:

1.

Note: The power-on configuration (POC) settings of third party chipsets may produce different PECI

addresses than those shown in Figure 6-8. Thermal designers should consult their third party chipset

designers for the configured PECI addresses.

Intel® Xeon® Processor 7400 Series Datasheet

101

Thermal Specifications

6.3.1.1

T

and Tcc Activation on PECI-Based Systems

CONTROL

Fan speed control solutions based on PECI utilize a T_CONTROL(Temperature Control

Offset) value stored in the processor IA32_TEMPERATURE_TARGET MSR. This MSR uses

the same offset temperature format as PECI, though it contains no sign bit. Thermal

management devices should infer the T_CONTROLvalue as negative. Thermal

management algorithms should utilize the relative temperature value delivered over

PECI in conjunction with the MSR value to control or optimize fan speeds. Figure 7-8

shows a conceptual fan control diagram using PECI temperatures.

Figure 6-9. Conceptual Fan Control Diagram For a PECI-Based Platform

T_CONTROL

Setting

TCC Activation

Temperature

Max

PECI = 0

Fan Speed

(RPM)

PECI = -10

Min

PECI = -20

Temperature

(not intended to depict actual implementation)

6.3.1.2

Processor Thermal Data Sample Rate and Filtering

The DTS (Digital Thermal Sensors) provide an improved capability to monitor device

hot spots, which inherently leads to more varying temperature readings over short time

intervals. The DTS sample interval range can be modified, and a data filtering algorithm

can be activated to help moderate this. The DTS sample interval range is 82 us

(default) to 20 ms (max). This value can be set in BIOS.

To reduce the sample rate requirements on PECI and improve thermal data stability vs.

time the processor DTS also implements an averaging algorithm that filters the

incoming data. This is an alpha-beta filter with coefficients of 0.5, and is expressed

mathematically as: Current_filtered_temp = (Previous_filtered_temp / 2) +

(new_sensor_temp / 2). This filtering algorithm is fixed and cannot be changed. It is on

by default and can be turned off in BIOS.

Host controllers should utilize the min/max sample times to determine the appropriate

sample rate based on the controller's fan control algorithm and targeted response rate.

The key items to take into account when settling on a fan control algorithm are the DTS

sample rate, whether the temperature filter is enabled, how often the PECI host will

poll the processor for temperature data, and the rate at which fan speed is changed.

Depending on the designer’s specific requirements the DTS sample rate and alpha-beta

filter may have no effect on the fan control algorithm.

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Intel® Xeon® Processor 7400 Series Datasheet

Thermal Specifications

6.3.2

PECI Specifications

6.3.2.1

PECI Device Address

The Intel® Xeon® Processor 7400 Series obtains its PECI address based on the

processors APIC ID[4:3] at power on. APIC ID[4:3] is also known as the Cluster

ID[1:0]. The Cluster ID[1:0] is set, by the chipset, by asserting the power-on

configuration (POC) signals A[12:11]# at the deassertion of RESET#.

The PECI address for the Intel® Xeon® Processor 7400 Series = 0x30 + Cluster

ID[0:1] ^1.

.

The initial Cluster ID assigned to each socket must be unique to ensure a unique PECI

address is assigned to each socket. The Cluster ID may be changed via the XAPIC ID

register.

The default PECI device address for the Intel® 7300 chipset FSB0 is 0x30.

The default PECI device address for the Intel 7300 chipset FSB1 is 0x32.

The default PECI device address for the Intel 7300 chipset FSB2 is 0x31.

The default PECI device address for the Intel 7300 chipset FSB3 is 0x33.

The power-on-configuration (POC) settings of third-party chipsets may produce

different PECI addresses than those shown above. Thermal designers should consult

their third party chipset designers for the default configured PECI addresses or power-

on configuration method.

Please note that each address also supports two domains (Domain 0 and Domain 1).

For more information on PECI domains, please refer to the Platform Environment

Control Interface Specification.

Note:

1.

The Cluster ID bit order is reversed [0:1] for the PECI address calculation.

6.3.2.2

6.3.2.3

PECI Command Support

PECI command support is covered in detail in RS - Platform Environment Control

Interface (PECI) Specification. Please refer to this document for details on supported

PECI command function and codes

PECI Fault Handling Requirements

PECI is largely a fault tolerant interface, including noise immunity and error checking

improvements over other comparable industry standard interfaces. The PECI client is

as reliable as the device that it is embedded in, and thus given operating conditions

that fall under the specification, the PECI will always respond to requests and the

protocol itself can be relied upon to detect any transmission failures. There are,

however, certain scenarios where the PECI is known to be unresponsive.

Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to

provide reliable thermal data. System designs should implement a default power-on

condition that ensures proper processor operation during the time frame when reliable

data is not available via PECI.

To protect platforms from potential operational or safety issues due to an abnormal

condition on PECI, the Host controller should take action to protect the system from

possible damaging states. If the Host controller cannot complete a valid PECI

transactions of GetTemp0() with a given PECI device over 3 consecutive failed

transactions or a one second max specified interval, then it should take appropriate

Intel® Xeon® Processor 7400 Series Datasheet

103

Thermal Specifications

actions to protect the corresponding device and/or other system components from

overheating. The host controller may also implement an alert to software in the event

of a critical or continuous fault condition.

6.3.2.4

PECI GetTemp0() and GetTemp1() Error Code Support

The error codes supported for the processor GetTemp0() and GetTemp1() commands

are listed inTable 6-7 below:

Table 6-7.

GetTemp0() and GetTemp1() Error Codes

Error Code

0x8000

0x8002

Description

General sensor error

Sensor is operational, but has detected a temperature below its operational range

(underflow), currently 30 C absolute temperature.

o

§

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Intel® Xeon® Processor 7400 Series Datasheet

Features

7 Features

7.1

Power-On Configuration Options

Several configuration options can be configured by hardware. The Intel® Xeon®

Processor 7400 Series samples its hardware configuration at reset, on the active-to-

inactive transition of RESET#. For specifics on these options, please refer to Table 7-1.

The sampled information configures the processor for subsequent operation. These

configuration options cannot be changed except by another reset. All resets reconfigure

the processor, for reset purposes, the processor does not distinguish between a “warm”

reset (PWRGOOD signal remains asserted) and a “power-on” reset.

Table 7-1.

Power-On Configuration Option Pins

Configuration Option

Output tri state

Pin Name

Notes

SMI#

A3#

1,2,3

1,2

Execute BIST (Built-In Self Test)

Disable MCERR# observation

Disable BINIT# observation

Cluster ID

A9#

1,2

A10#

1,2

A[12:11]#

A15#

1,2

Disable bus parking

1,2

Notes:

1.

2.

3.

Asserting this signal during RESET# will select the corresponding option.

Address pins not identified in this table as configuration options should not be asserted during RESET#.

Requires de-assertion of PWRGOOD.

Disabling of any of the cores within the Intel® Xeon® Processor 7400 Series must be

handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will

allow for the disabling of a single core per core pair within the Intel® Xeon® Processor

7400 Series package.

7.2

Clock Control and Low Power States

The Intel® Xeon® Processor 7400 Series supports the Extended HALT state (also

referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce power

consumption by stopping the clock to internal sections of the processor, depending on

each particular state. See Figure 7-1 for a visual representation of the processor low

power states. The Extended HALT state is a lower power state than the HALT state or

Stop Grant state.

The Extended HALT state must be enabled via the BIOS for the processor to

remain within its specifications. For processors that are already running at the

lowest bus to core frequency ratio for its nominal operating point, the processor will

transition to the HALT state instead of the Extended HALT state.

The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In

a multiprocessor system, all the STPCLK# signals are bussed together, thus all

processors are affected in unison. When the STPCLK# signal is asserted, the processor

enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each

processor. The chipset needs to account for a variable number of processors asserting

the Stop Grant SBC on the bus before allowing the processor to be transitioned into one

of the lower processor power states. Refer to the applicable chipset specification.

Intel® Xeon® Processor 7400 Series Datasheet

105

Features

7.2.1

7.2.2

Normal State

This is the normal operating state for the processor.

HALT or Extended HALT State

The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state

must be enabled for the processor to remain within its specifications. The

Extended HALT state requires support for dynamic VID transitions in the platform.

7.2.2.1

HALT State

HALT is a low power state entered when the processor has executed the HALT or

MWAIT instruction. When one of the processor cores executes the HALT or MWAIT

instruction, that processor core is halted; however, the other processor cores continue

normal operation. The processor will transition to the Normal state upon the occurrence

of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the

front side bus. RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either

Normal Mode or the HALT state. See the Intel^®64 and IA-32 Architectures Software

Developer's Manual, Volume III: System Programming Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT state. When the

system deasserts STPCLK#, the processor will return execution to the HALT state.

While in HALT state, the processor will process front side bus snoops and interrupts.

7.2.2.2

Extended HALT State

Extended HALT state is a low power state entered when all processor cores have

executed the HALT or MWAIT instructions and Extended HALT state has been enabled

via the BIOS. When one of the processor cores executes the HALT instruction, that

processor core is halted; however, the other processor cores continue normal

operation. The Extended HALT state is a lower power state than the HALT state or Stop

Grant state. The Extended HALT state must be enabled for the processor to remain

within its specifications.

The processor will automatically transition to a lower core frequency and voltage

operating point before entering the Extended HALT state. Note that the processor FSB

frequency is not altered; only the internal core frequency is changed. When entering

the low power state, the processor will first switch to the lower bus to core frequency

ratio and then transition to the lower voltage (VID).

While in the Extended HALT state, the processor will process bus snoops.

106

Intel® Xeon® Processor 7400 Series Datasheet

Features

E

Table 7-2.

Extended HALT Maximum Power

Symbol

Parameter

Min

Max

Unit

Notes

P

Extended HALT State Power

42

W

1, 2

EXTENDED_HALT

Intel® Xeon®

X7460 Processor

P

Extended HALT State Power

C1 Idle Power

32

36

42

20

W

1, 2

EXTENDED_HALT

6-Core Intel®

Xeon® Processor

E7400 Series

P

1, 2, 3

EXTENDED_HALT

4-Core Intel®

Xeon® Processor

E7400 Series

P

_HALT

4-core Intel®

Xeon® E7420,

E7430 Processor

P

C1 Idle Power

_HALT

6-Core Intel®

Xeon® Processor

L7455 Series

P

C1 Idle Power

15

W

1, 2, 3

_HALT

4-Core Intel®

Xeon® Processor

L7445 Series

Notes:

1.

The specification is at T

= 50°C and nominal V . The VID setting represents the maximum expected

CASE CC

VID while running in HALT state.

2.

3.

This specification is characterized by design.

Processors running in the lowest bus ratio will enter the HALT state when the processor has executed the

HALT and MWAIT instruction since the processor is already in the lowest core frequency and voltage

operating point.

The processor exits the Extended HALT state when a break event occurs. When the

processor exits the Extended HALT state, it will first transition the VID to the original

value and then change the bus to core frequency ratio back to the original value.

Intel® Xeon® Processor 7400 Series Datasheet

107

Features

Figure 7-1. Stop Clock State Machine

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

Extended HALT or HALT State

Normal State

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB interrupts

BCLK running

Snoops and interrupts allowed

Normal execution

Snoop

Event

Occurs Serviced

Snoop

Event

STPCLK#

Asserted

STPCLK#

De-asserted

Extended HALT Snoop or HALT

Snoop State

BCLK running

Service snoops to caches

Snoop Event Occurs

Snoop Event Serviced

Stop Grant State

Stop Grant Snoop State

BCLK running

Snoops and interrupts allowed

Service snoops to caches

7.2.3

Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20

bus clocks after the response phase of the processor issued Stop Grant Acknowledge

special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted

once the processor is in the Stop Grant state. All processor cores will enter the Stop-

Grant state once the STPCLK# pin is asserted. Additionally, all processor cores must be

in the Stop Grant state before the deassertion of STPCLK#.

Since the AGTL+ signal pins receive power from the front side bus, these pins should

not be driven (allowing the level to return to V^TT) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the front side bus

should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be

latched and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will

stay in Stop-Grant state. A transition back to the Normal state will occur with the de-

assertion of the STPCLK# signal.

A transition to the Grant Snoop state will occur when the processor detects a snoop on

the front side bus (see Section 7.2.4.1).

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Intel® Xeon® Processor 7400 Series Datasheet

Features

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by

the processor, and only serviced when the processor returns to the Normal state. Only

one occurrence of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process snoops on the front side bus and it

will latch interrupts delivered on the front side bus.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be

asserted if there is any pending interrupt latched within the processor. Pending

interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of

PBE#. Assertion of PBE# indicates to system logic that it should return the processor to

the Normal state.

7.2.4

Extended HALT Snoop or HALT Snoop State, Stop Grant

Snoop State

The Extended HALT Snoop state is used in conjunction with the Extended HALT state. If

the Extended HALT state is not enabled in the BIOS, the default Snoop state entered

will be the HALT Snoop state. Refer to the sections below for details on HALT Snoop

state, Stop Grant Snoop state and Extended HALT Snoop state.

7.2.4.1

HALT Snoop State, Stop Grant Snoop State

The processor will respond to snoop or interrupt transactions on the front side bus

while in Stop-Grant state or in HALT state. During a snoop or interrupt transaction, the

processor enters the HALT/Grant Snoop state. The processor will stay in this state until

the snoop on the front side bus has been serviced (whether by the processor or another

agent on the front side bus) or the interrupt has been latched. After the snoop is

serviced or the interrupt is latched, the processor will return to the Stop-Grant state or

HALT state, as appropriate.

7.2.4.2

Extended HALT Snoop State

The Extended HALT Snoop state is the default Snoop state when the Extended HALT

state is enabled via the BIOS. The processor will remain in the lower bus to core

frequency ratio and VID operating point of the Extended HALT state.

While in the Extended HALT Snoop state, snoops and interrupt transactions are handled

the same way as in the HALT Snoop state. After the snoop is serviced or the interrupt is

latched, the processor will return to the Extended HALT state.

7.3

Enhanced Intel SpeedStep^®Technology

Intel® Xeon® Processor 7400 Series support Enhanced Intel SpeedStep^®Technology.

This technology enables the processor to switch between multiple frequency and

voltage points, which results in platform power savings. Enhanced Intel SpeedStep

Technology requires support for dynamic VID transitions in the platform. Switching

between voltage/frequency states is software controlled.

Note:

Not all Intel® Xeon® Processor 7400 Series may be capable of supporting Enhanced

Intel SpeedStep Technology. More details on which processor frequencies will support

this feature will be provided in future releases of the Intel® Xeon® Processor 7400

Series Specification Update when available.

Intel® Xeon® Processor 7400 Series Datasheet

109

Features

Enhanced Intel SpeedStep Technology creates processor performance states (P-states)

or voltage/frequency operating points. P-states are lower power capability states within

the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep Technology

enables real-time dynamic switching between frequency and voltage points. It alters

the performance of the processor by changing the bus to core frequency ratio and

voltage. This allows the processor to run at different core frequencies and voltages to

best serve the performance and power requirements of the processor and system. The

Intel® Xeon® Processor 7400 Series have hardware logic that coordinates the

requested voltage (VID) between the processor cores. The highest voltage requested

from the four processor cores is selected for that processor package. Note that the

front side bus is not altered; only the internal core frequency is changed. In order to

run at reduced power consumption, the voltage is altered in step with the bus ratio.

The following are key features of Enhanced Intel SpeedStep Technology:

• Multiple voltage/frequency operating points provide optimal performance at

reduced power consumption.

• Voltage/frequency selection is software controlled by writing to processor MSR’s

(Model Specific Registers), thus eliminating chipset dependency.

— If the target frequency is higher than the current frequency, V_CCis incremented

in steps (+12.5 mV) by placing a new value on the VID signals and the

processor shifts to the new frequency. Note that the top frequency for the

processor can not be exceeded.

— If the target frequency is lower than the current frequency, the processor shifts

to the new frequency and V_CCis then decremented in steps (-12.5 mV) by

changing the target VID through the VID signals.

7.4

System Management Bus (SMBus) Interface

The Intel® Xeon® Processor 7400 Series package includes an SMBus interface which

allows access to a memory component with two sections (referred to as the Processor

Information ROM and the Scratch EEPROM). These devices and their features are

described below.

Note:

The SMBus on-package thermal sensor has been removed and is no longer used. Refer

to Section 6.3 for details about the new digital thermometer and PECI interface.

The processor SMBus implementation uses the clock and data signals of the System

Management Bus (SMBus) Specification. It does not implement the SMBSUS# signal.

Layout and routing guidelines are available in the Caneland Platform Design Guide

document.

For platforms which do not implement any of the SMBus features found on the

processor, all of the SMBus connections, except SM_VCC, to the socket pins may be left

unconnected (SM_CLK, SM_DAT, SM_EP_A[2:0], SM_WP).

110

Intel® Xeon® Processor 7400 Series Datasheet

Features

Figure 7-2. Logical Schematic of SMBus Circuitry

SM_VCC

VCC

SM_EP_A0

SM_EP_A1

SM_EP_A2

SM_WP

DATA

CLK

Processor

Information

ROM

and Scratch

EEPROM

(1Kbit each)

VSS

SM_CLK

SM_DAT

Note: Actual implementation may vary. This figure is provided to offer a general understanding of the

architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.

7.4.1

SMBus Device Addressing

Of the addresses broadcast across the SMBus, the memory component claims those of

the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors

on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the

processor substrate to ensure that the memory components are in a known state in

systems which do not support the SMBus (or only support a partial implementation).

The “Z” bit is the read/write bit for the serial bus transaction.

Note that addresses of the form “0000XXXXb” are Reserved and should not be

generated by an SMBus master. The system designer must also ensure that their

particular implementation does not add excessive capacitance to the address inputs.

Excess capacitance at the address inputs may cause address recognition problems.

Refer to the appropriate platform design guide document.

Figure 7-2 shows a logical diagram of the pin connections. Table 7-3 describe the

address pin connections and how they affect the addressing of the devices.

Intel® Xeon® Processor 7400 Series Datasheet

111

Features

Table 7-3.

Memory Device SMBus Addressing

Address

(Hex)

Upper

Address

Device Select

R/W

1

SM_EP_A2

bit 3

SM_EP_A1

bit 2

SM_EP_A0

bit 1

bits 7-4

bit 0

A0h/A1h

A2h/A3h

A4h/A5h

A6h/A7h

A8h/A9h

AAh/ABh

ACh/ADh

AEh/AFh

1010

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Note:

1. This addressing scheme will support up to 8 processors on a single SMBus.

7.4.2

PIROM and Scratch EEPROM Supported SMBus

Transactions

The Processor Information ROM (PIROM) responds to two SMBus packet types: Read

Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge a

Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte

and Write Byte commands. Table 7-4 diagrams the Read Byte command. Table 7-5

diagrams the Write Byte command. Following a write cycle to the scratch ROM,

software must allow a minimum of 10 ms before accessing either ROM of the processor.

In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents

a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’

represents a negative acknowledge (NACK). The shaded bits are transmitted by the

Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are

transmitted by the SMBus host controller. In the tables, the data addresses indicate 8

bits. The SMBus host controller should transmit 8 bits with the most significant bit

indicating which section of the EEPROM is to be addressed: the Processor Information

ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).

Table 7-4.

Table 7-5.

Read Byte SMBus Packet

Slave

Addres

s

Comman

d Code

Slave

Address

S

Write

A

S

Read

A

Data

///

P

1

7-bits

1

8-bits

1

7-bits

1

8-bits

1

Write Byte SMBus Packet

S

Slave Address

Write

A

Command Code

A

Data

A

P

1

7-bits

1

8-bits

1

8-bits

1

112

Intel® Xeon® Processor 7400 Series Datasheet

Features

7.4.3

Processor Information ROM (PIROM)

The lower half (128 bytes) of the SMBus memory component is an electrically

programmed read-only memory with information about the processor. This information

is permanently write-protected. Table 7-6 shows the data fields and Section 7.4.3

provides the formats of the data fields included in the Processor Information ROM

(PIROM).

The PIROM consists of the following sections:

• Header

• Processor Data

• Processor Core Data

• Cache Data

• Package Data

• Part Number Data

• Thermal Reference Data

• Feature Data

• Other Data

Table 7-6.

Processor Information ROM Data Sections (Sheet 1 of 3)

# of

Bits

Offset/Section

Function

Notes

Header:

00h

01 - 02h

03h

8

16

8

Data Format Revision

PIROM Size

Two 4-bit hex digits

Size in bytes (MSB first)

Processor Data Address

Byte pointer, 00h if not present

04h

8

Processor Core Data

Address

05h

06h

07h

08h

8

L3 Cache Data Address

Package Data Address

Byte pointer, 00h if not present

Part Number Data Address

Thermal Reference Data

Address

09h

0Ah

8

Feature Data Address

Other Data Address

Reserved

Byte pointer, 00h if not present

Reserved

0B - 0Ch

0Dh

16

8

Checksum

1 byte checksum

Processor Data:

0E - 13h

14h

48

S-spec Number

Six 8-bit ASCII characters

6

2

Reserved

Sample/Production

Reserved (most significant bits)

00b = Sample, 01b = Production

15h

8

Checksum

1 byte checksum

Processor Core

Data:

16 - 19h

2

8

4

Reserved

Reserved for future use

From CPUID

Extended Family

Extended Model

From CPUID

Intel® Xeon® Processor 7400 Series Datasheet

113

Features

Table 7-6.

Processor Information ROM Data Sections (Sheet 2 of 3)

# of

Bits

Offset/Section

Function

Notes

2

Reserved

Reserved for future use

From CPUID

Processor Core Type

Processor Core Family

Processor Core Model

Processor Core Stepping

Reserved

4

From CPUID

4

From CPUID

4

From CPUID

2

Reserved for future use

1A - 1Bh

16

Front Side Bus Speed

16-bit binary number (in MTS)

1Ch

2

6

Multiprocessor Support

Reserved

00b = UP,01b = DP,10b = RSVD,11b = MP

Reserved

1D - 1Eh

1F - 20h

16

Maximum Core Frequency

Maximum Core VID

16-bit binary number (in MHz)

Maximum V requested by VID outputs in

CC

mV

21 - 22h

23h

16

8

Minimum Core Voltage

Minimum processor DC V in mV

CC

T

Maximum

Maximum case temperature spec in °C

1 byte checksum

CASE

24h

8

Checksum

Cache Data:

25 - 26h

27 - 28h

29 - 2Ah

2B - 2Ch

16

Reserved

Reserved for future use

16-bit binary number (in KB)

L2 Cache Size

L3 Cache Size

Maximum Cache CVID

Maximum V

requested by CVID

CACHE

outputs in mV

2D - 2Eh

2F - 30h

16

8

Minimum Cache Voltage

Reserved

Minimum processor DC V

in mV

CACHE

Reserved

31h

Checksum

1 byte checksum

Package Data:

32 - 35h

32

8

Package Revision

Reserved

Four 8-bit ASCII characters

Reserved for future use

1 byte checksum

36h

37h

8

Checksum

Part Number Data:

38 - 3Eh

56

112

64

Processor Part Number

Reserved

Seven 8-bit ASCII characters

Reserved

3F - 4Ch

4D - 54h

Processor Electronic

Signature

64-bit identification number

55 - 6Eh

6Fh

208

8

Reserved

Checksum

1 byte checksum

114

Intel® Xeon® Processor 7400 Series Datasheet

Features

Table 7-6.

Processor Information ROM Data Sections (Sheet 3 of 3)

# of

Bits

Offset/Section

Function

Notes

Thermal Ref. Data:

70h

8

16

8

Reserved

Checksum

Reserved

71 - 72h

73h

1 byte checksum

Feature Data:

74 - 77h

32

8

Processor Core Feature

Flags

From CPUID function 1, EDX contents

78h

Processor Feature Flags

[7] = Multi-Core

[6] = Serial Signature

[5] = Electronic Signature Present

[4] = Thermal Sense Device Present

[3] = Reserved

[2] = OEM EEPROM Present

[1] = Core VID Present

[0] = L3 Cache Present

79h

7Ah

8

Processor Thread and Core

Information

[7:2] = Number of cores

[1:0] = Number of threads per core

Additional Processor Feature [7] = Reserved

®

Flags

[6] = Intel Cache Safe Technology

[5] = Extended Halt State (C1E)

®

[4] = Intel Virtualization Technology

[3] = Execute Disable

®

[2] = Intel 64

[1] = Thermal Monitor TM2

[0] = Enhanced Intel SpeedStep

Technology

®

7B-7Ch

16

Thermal Adjustment Factors [15:8] = Measurement Correction Factor

(Pending)

Reserved

Checksum

[7:0] = Temperature Target

7D-7Eh

7Fh

16

8

Reserved

1 byte checksum

Details on each of these sections are described below.

Note:

Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not

rely on this model.

7.4.3.1

Header

To maintain backward compatibility, the Header defines the starting address for each

subsequent section of the PIROM. Software should check for the offset before reading

data from a particular section of the ROM.

Example: Code looking for the cache data of a processor would read offset 05h to find

a value of 25h. 25h is the first address within the 'Cache Data' section of the PIROM.

Intel® Xeon® Processor 7400 Series Datasheet

115

Features

7.4.3.1.1

DFR: Data Format Revision

This location identifies the data format revision of the PIROM data structure. Writes to

this register have no effect.

Offset:

00h

Bit

Description

7:0

Data Format Revision

The data format revision is used whenever fields within the PIROM are

redefined. The initial definition will begin at a value of 1. If a field, or bit

assignment within a field, is changed such that software needs to discern

between the old and new definition, then the data format revision field will be

incremented.

00h: Reserved

01h: Initial definition

02h: Second revision

03h: Third revision

04h: Fourth revision (Defined by this EMTS)

05h-FFh: Reserved

Example: The Intel® Xeon® Processor 7400 Series will use 04h at offset 00h.

Note:

Changes from Third Revision:

1. The Number of cores field in PTCI: Processor Thread and Core Information at offset

79h was extended to six bits. It now defined as Number of Core = Bits [7:2]. It

previously was defined as Bits [3:2]

7.4.3.1.2

PISIZE: PIROM Size

This location identifies the PIROM size. Writes to this register have no effect.

Offset:

01h-02h

Bit

Description

15:0

PIROM Size

The PIROM size provides the size of the device in hex bytes. The MSB is at

location 01h, the LSB is at location 02h.

0000h - 007Fh: Reserved

0080h: 128 byte PIROM size

0081- FFFFh: Reserved

7.4.3.1.3

PDA: Processor Data Address

This location provides the offset to the Processor Data Section. Writes to this register

have no effect.

Offset:

03h

Bit

Description

7:0

Processor Data Address

Byte pointer to the Processor Data section

00h: Processor Data section not present

01h - 0Dh: Reserved

0Eh: Processor Data section pointer value

0Fh-FFh: Reserved

116

Intel® Xeon® Processor 7400 Series Datasheet

Features

7.4.3.1.4

PCDA: Processor Core Data Address

This location provides the offset to the Processor Core Data Section. Writes to this

register have no effect.

Offset:

04h

Bit

Description

7:0

Processor Core Data Address

Byte pointer to the Processor Data section

00h: Processor Core Data section not present

01h - 15h: Reserved

16h: Processor Core Data section pointer value

17h-FFh: Reserved

7.4.3.1.5

L3CDA: L3 Cache Data Address

This location provides the offset to the L3 Cache Data Section. Writes to this register

have no effect.

Offset:

05h

Bit

Description

7:0

L3 Cache Data Address

Byte pointer to the L3 Cache Data section

00h: L3 Cache Data section not present

01h - 24h: Reserved

25h: L3 Cache Data section pointer value

26h-FFh: Reserved

7.4.3.1.6

PDA: Package Data Address

This location provides the offset to the Package Data Section. Writes to this register

have no effect.

Offset:

06h

Bit

Description

7:0

Package Data Address

Byte pointer to the Package Data section

00h: Package Data section not present

01h - 31h: Reserved

32h: Package Data section pointer value

33h-FFh: Reserved

Intel® Xeon® Processor 7400 Series Datasheet

117

Features

7.4.3.1.7

7.4.3.1.8

7.4.3.1.9

PNDA: Part Number Data Address

This location provides the offset to the Part Number Data Section. Writes to this

register have no effect.

Offset:

07h

Bit

Description

7:0

Part Number Data Address

Byte pointer to the Part Number Data section

00h: Part Number Data section not present

01h - 37h: Reserved

38h: Part Number Data section pointer value

39h-FFh: Reserved

TRDA: Thermal Reference Data Address

This location provides the offset to the Thermal Reference Data Section. Writes to this

register have no effect.

Offset:

08h

Bit

Description

7:0

Thermal Reference Data Address

Byte pointer to the Thermal Reference Data section

00h: Thermal Reference Data section not present

01h - 6Fh: Reserved

70h: Thermal Reference Data section pointer value

71h-FFh: Reserved

FDA: Feature Data Address

This location provides the offset to the Feature Data Section. Writes to this register

have no effect.

Offset:

09h

Bit

Description

7:0

Feature Data Address

Byte pointer to the Feature Data section

00h: Feature Data section not present

01h - 73h: Reserved

74h: Feature Data section pointer value

75h-FFh: Reserved

118

Intel® Xeon® Processor 7400 Series Datasheet

Features

7.4.3.1.10

ODA: Other Data Address

This location provides the offset to the Other Data Section. Writes to this register have

no effect.

Offset:

0Ah

Bit

Description

7:0

Other Data Address

Byte pointer to the Other Data section

00h: Other Data section not present

01h - 7Dh: Reserved

7Eh: Other Data section pointer value

7Fh- FFh: Reserved

7.4.3.1.11

RES1: Reserved 1

This locations are reserved. Writes to this register have no effect.

Offset:

0Bh-0Ch

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.4.3.1.12

HCKS: Header Checksum

This location provides the checksum of the Header Section. Writes to this register have

no effect.

Offset:

0Dh

Bit

Description

7:0

Header Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.2

Processor Data

This section contains two pieces of data:

• The S-spec of the part in ASCII format

• (1) 2-bit field to declare if the part is a pre-production sample or a production unit

7.4.3.2.1

SQNUM: S-Spec Number

This location provides the S-SPec number of the processor. The S-spec field is six ASCII

characters wide and is programmed with the same S-spec value as marked on the

processor. If the value is less than six characters in length, leading spaces (20h) are

programmed in this field. Writes to this register have no effect.

Example: A processor with a S-Spec mark of SLA67 contains the following in field 0E-

13h: 20h, 53h, 4Ch, 41h, 36h, 37h. This data consists of one blank at 0Eh followed by

the ASCII codes for SLA67 in locations 10 - 13h.

Intel® Xeon® Processor 7400 Series Datasheet

119

Features

Offset:

0Eh-13h

Bit

Description

47:40

Character 6

S-SPEC character or 20h

00h-0FFh: ASCII character

39:32

31:24

23:16

15:8

Character 5

S-SPEC character or 20h

00h-0FFh: ASCII character

Character 4

S-SPEC character

00h-0FFh: ASCII character

Character 3

S-SPEC character

00h-0FFh: ASCII character

Character 2

S-SPEC character

00h-0FFh: ASCII character

7:0

Character 1

S-SPEC character

00h-0FFh: ASCII character

7.4.3.2.2

SAMPROD: Sample/Production

This location contains the sample/production field, which is a two-bit field and is LSB

aligned. All Q-spec material will use a value of 00b. All S-spec material will use a value

of 01b. All other values are reserved. Writes to this register have no effect.

Example: A processor with a Qxxx mark (engineering sample) will have offset 14h set

to 00h. A processor with an Sxxxx mark (production unit) will use 01h at offset 14h.

Offset:

14h

Bit

Description

7:2

RESERVED

000000b-111111b: Reserved

1:0

Sample/Production

Sample or Production indictor

00b: Sample

01b: Production

10b-11b: Reserved

120

Intel® Xeon® Processor 7400 Series Datasheet

Features

7.4.3.2.3

PDCKS: Processor Data Checksum

This location provides the checksum of the Processor Data Section. Writes to this

register have no effect.

Offset:

15h

Bit

Description

7:0

Processor Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.3

Processor Core Data

This section contains core silicon-related data.

7.4.3.3.1

CPUID: Processor CPUID Signature

This location contains the CPUID, Processor Type, Family, Model and Stepping. The

CPUID field is a copy of the results in EAX[27:0] from Function 1 of the CPUID

instruction. The MSB is at location 16h, the LSB is at location 19h. Writes to this

register have no effect.

Example: If the CPUID of a processor is 000106D0h (A-0 stepping), then the value

programmed into offset 16 - 19h of the PIROM is 00041980h.

Note:

The field is not aligned on a byte boundary since the first two bits of the offset are

reserved. Thus, the data must be shifted right by two in order to obtain the same

results as the CPUID instruction.

Offset:

16h-19h

Bit

Description

31:30

Reserved

00b-11b: Reserved

29:21

21:18

Extended Family

00h-0Fh: Extended Family

Extended Model

0h-Fh: Extended Model

17:16

15:14

Reserved

00b-11b: Reserved

Processor Type

00b-11b: Processor Type

13:10

9:6

Processor Family

0h-Fh: Processor Family

Processor Model

0h-Fh: Processor Model

5:2

Processor Stepping

0h-Fh: Processor Stepping

1:0

Reserved

00b-11b: Reserved

Intel® Xeon® Processor 7400 Series Datasheet

121

Features

7.4.3.3.2

FSB: Front Side Bus Speed

This location contains the front side bus transaction rate information. Systems may

need to read this offset to decide if all installed processors support the same front side

bus speed. Because FSB is described as a 4X data bus, the transaction rate given in this

field is currently 1066 MTS. The data provided is the speed, rounded to a whole

number, and reflected in hex. Writes to this register have no effect.

Example: The Intel® Xeon® Processor 7400 Series supports a 1066 MTS front side

bus. Therefore, offset 1A - 1Bh has a value of 042Ah.

Offset:

1Ah-1Bh

Bit

Description

15:0

Front Side Bus Speed

0000h-FFFFh: MTS

7.4.3.3.3

MPSUP: Multiprocessor Support

This location contains 2 bits for representing the supported number of physical

processors on the bus. These two bits are MSB aligned where 00b equates to single-

processor operation, 01b is a dual-processor operation, and 11b represents multi-

processor operation. The Intel® Xeon® Processor 7400 Series is an MP processor. The

remaining six bits in this field are reserved for the future use. Writes to this register

have no effect.

Example: The Intel® Xeon® Processor 7400 Series will use C0h at offset 1Ch.

Offset:

1Ch

Bit

Description

7:6

Multiprocessor Support

UP, DP or MP indictor

00b: UP

01b: DP

10b: Reserved

11b: MP

5:0

RESERVED

000000b-111111b: Reserved

7.4.3.3.4

MCF: Maximum Core Frequency

This location contains the maximum core frequency for the processor. The frequency

should equate to the markings on the processor and/or the S-spec speed even if the

parts are not limited or locked to the intended speed. Format of this field is in MHz,

rounded to a whole number, and encoded in hex format. Writes to this register have no

effect.

Example: A 2.93 GHz processor will have a value of 0675h, which equates to 2933

decimal. Therefore, offset 1D - 1Eh has a value of 0765h.

122

Intel® Xeon® Processor 7400 Series Datasheet

Features

Offset:

1Dh-1Eh

Bit

Description

15:0

Maximum Core Frequency

0000h-FFFFh: MHz

7.4.3.3.5

MAXVID: Maximum Core VID

This location contains the maximum Core VID (Voltage Identification) voltage that may

be requested via the VID pins. This field, rounded to the next thousandth, is in mV and

is reflected in hex. Writes to this register have no effect.

Example: From Table 2-9the maximum VID is 1.450 V maximum voltage. Offset 1F -

20h would contain 05AAh (1450 decimal).

Offset:

1Fh-20h

Bit

Description

15:0

Maximum Core VID

0000h-FFFFh: mV

7.4.3.3.6

MINV: Minimum Core Voltage

This location contains the minimum Processor Core voltage. This field, rounded to the

next thousandth, is in mV and is reflected in hex. The minimum V_CCreflected in this

field is the minimum allowable voltage assuming the FMB maximum current draw.

Writes to this register have no effect.

Note:

The minimum core voltage value in offset 21 - 22h is a single value that assumes the

FMB maximum current draw. Refer to Table 2-9and Table 2-10 for the minimum core

voltage specifications based on actual real-time current draw.

Example: For an Intel® Xeon® Processor 7400 Series the minimum voltage is 0.695 V

= 0.900 V (Min VID) - 0.205 V (Voltage Offset at maximum current). Offset 21 - 22h

would contain 0267Fh (0695 decimal).

Offset:

21h-22h

Bit

Description

15:0

Minimum Core Voltage

0000h-FFFFh: mV

7.4.3.3.7

TCASE: T_CASEMaximum

This location provides the maximum T_CASEfor the processor. The field reflects

temperature in degrees Celsius in hex format. This data can be found in the Table 6-1.

The thermal specifications are specified at the case Integrated Heat Spreader

(IHS).Writes to this register have no effect.

Intel® Xeon® Processor 7400 Series Datasheet

123

Features

Offset:

23h

Bit

Description

7:0

T

Maximum

CASE

00h-FFh: Degrees Celsius

7.4.3.3.8

PCDCKS: Processor Core Data Checksum

This location provides the checksum of the Processor Core Data Section. Writes to this

register have no effect.

Offset:

24h

Bit

Description

7:0

Processor Core Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.4

Cache Data

This section contains cache-related data.

7.4.3.4.1

RES3: Reserved 3

These locations are reserved. Writes to this register have no effect.

Offset:

25h-26h

Bit

Description

15:0

RESERVED 3

0000h-FFFFh: Reserved

7.4.3.4.2

L2SIZE: L2 Cache Size

This location contains the size of the level two cache in kilobytes. Writes to this register

have no effect.

Example: The Intel® Xeon® Processor 7400 Series processor has a 6 MB (6144 KB)

or a 9 MB (9216 KB) L2 cache total (3 MB L2 cache per two processor cores). Thus,

offset 27 - 28h will contain 1800h (for 6 MB) or 2400h (for 9 MB).

Offset:

27h-28h

Bit

Description

15:0

L2 Cache Size

0000h-FFFFh: KB

124

Intel® Xeon® Processor 7400 Series Datasheet

Features

7.4.3.4.3

L3SIZE: L3 Cache Size

This location contains the size of the level three cache in kilobytes. Writes to this

register have no effect.

Example: The Intel® Xeon® Processor 7400 Series has either a 12 MB (12288 KB) ,

16 MB (16384 KB) or 8 MB ((8192 KB))L3 cache. Thus, offset 29 - 2Ah will contain

3000h (for 12 MB) ,4000h (for 16 MB) or 2000h(for 8 MB).

Offset:

29h-2Ah

Bit

Description

15:0

L3 Cache Size

0000h-FFFFh: KB

7.4.3.4.4

MAXCVID: Maximum Cache VID

This location contains the maximum Cache VID (Voltage Identification) voltage that

may be requested via the CVID pins. This field, rounded to the next thousandth, is in

mV and is reflected in hex. Writes to this register have no effect.

Example: The Intel® Xeon® Processor 7400 Series does not utilize a Cache VID.

Offset 2B - 2Ch will contain 0000h (0 decimal).

Offset:

2Bh-2Ch

Bit

Description

15:0

Maximum Cache VID

0000h-FFFFh: mV

7.4.3.4.5

MINCV: Minimum Cache Voltage

This location contains the minimum Cache voltage. This field, rounded to the next

thousandth, is in mV and is reflected in hex. The minimum V_CACHEreflected in this field

is the minimum allowable voltage assuming the FMB maximum current draw for two

processors. Writes to this register have no effect.

Example: The Intel® Xeon® Processor 7400 Series does not utilize a Cache VID.

Offset 2D - 2Eh will contain 0000h (0 decimal).

Offset:

2Dh-2Eh

Bit

Description

15:0

Minimum Cache Voltage

0000h-FFFFh: mV

Intel® Xeon® Processor 7400 Series Datasheet

125

Features

7.4.3.4.6

RES4: Reserved 4

These locations are reserved. Writes to this register have no effect.

Offset:

2Fh-30h

Bit

Description

15:0

RESERVED 4

0000h-FFFFh: Reserved

7.4.3.4.7

CDCKS: Cache Data Checksum

This location provides the checksum of the Cache Data Section. Writes to this register

have no effect.

Offset:

31h

Bit

Description

7:0

Cache Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.5

Package Data

This section provides package revision information.

7.4.3.5.1

PREV: Package Revision

This location tracks the highest level package revision. It is provided in ASCII format of

four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,

2.0, etc. If this only consumes three ASCII characters, a leading space is provided in

the data field.

Example: The Intel® Xeon® Processor 7400 Series utilizes the first revision of the FC-

mPGA8 package. Thus, at offset 32-35h, the data is a space followed by 1.0. In hex,

this would be 20h, 31h, 2Eh, 30h.

Offset:

32h-35h

Bit

Description

31:24

Character 4

ASCII character or 20h

00h-0FFh: ASCII character

23:16

15:8

7:0

Character 3

ASCII character

00h-0FFh: ASCII character

Character 2

ASCII character

00h-0FFh: ASCII character

Character 1

ASCII character

00h-0FFh: ASCII character

126

Intel® Xeon® Processor 7400 Series Datasheet

Features

7.4.3.5.2

RES5: Reserved 5

This location is reserved. Writes to this register have no effect.

Offset:

36h

Bit

Description

7:0

RESERVED 5

00h-FFh: Reserved

7.4.3.5.3

PDCKS: Package Data Checksum

This location provides the checksum of the Package Data Section. Writes to this register

have no effect.

Offset:

37h

Bit

Description

7:0

Package Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.6

Part Number Data

This section provides traceability. There are 208 available bytes in this section for

future use.

7.4.3.6.1

PPN: Processor Part Number

This location contains seven ASCII characters reflecting the Intel part number for the

processor. This information is typically marked on the outside of the processor. If the

part number is less than 7 characters, a leading space is inserted into the value. The

part number should match the information found in the marking specification found in

Section 3. Writes to this register have no effect.

Example: A processor with a part number of 80546KF will have data found at offset

38 - 3Eh is 38h, 30h, 35h, 34h, 36h, 4Bh, 46h.

Offset:

38h-3Eh

Bit

Description

4F:48

Character 7

ASCII character or 20h

00h-0FFh: ASCII character

47:40

39:32

31:24

Character 6

ASCII character or 20h

00h-0FFh: ASCII character

Character 5

ASCII character or 20h

00h-0FFh: ASCII character

Character 4

ASCII character

00h-0FFh: ASCII character

Intel® Xeon® Processor 7400 Series Datasheet

127

Features

Offset:

38h-3Eh

Bit

Description

23:16

Character 3

ASCII character

00h-0FFh: ASCII character

15:8

7:0

Character 2

ASCII character

00h-0FFh: ASCII character

Character 1

ASCII character

00h-0FFh: ASCII character

7.4.3.6.2

RES6: Reserved 6

This location is reserved. Writes to this register have no effect.

Offset:

3Fh-4Ch

Bit

Description

111:0

RESERVED 6

7.4.3.6.3

PS/ESIG: Processor Serial/Electronic Signature

This location contains a 64-bit identification number. The value in this field is either a

serial signature or an electronic signature. Bits 5 & 6 of the Processor Feature Flags

(Offset 78h) indicates which signature is present. Intel does not guarantee that each

processor will have a unique value in this field. Writes to this register have no effect.

Offset:

4Dh=54h

Bit

Description

63:0

Processor Serial/Electronic Signature

00000000h-FFFFFFFFh: Electronic Signature

7.4.3.6.4

RES7: Reserved 7

This location is reserved. Writes to this register have no effect.

Offset:

55h-6Eh

Bit

Description

207:0

RESERVED 7

128

Intel® Xeon® Processor 7400 Series Datasheet

Features

7.4.3.6.5

PNDCKS: Part Number Data Checksum

This location provides the checksum of the Part Number Data Section. Writes to this

register have no effect.

Offset:

6F

Bit

Description

7:0

Part Number Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.7

Thermal Reference Data

This section is reserved for future use.

7.4.3.7.1

RES8: Reserved 8

This location is reserved. Writes to this register have no effect.

Offset:

70h

Bit

Description

7:0

RESERVED 8

7.4.3.7.2

RES9: Reserved 9

This location is reserved. Writes to this register have no effect.

Offset:

71h-72h

Bit

Description

15:0

RESERVED 9

7.4.3.7.3

TRDCKS: Thermal Reference Data Checksum

This location provides the checksum of the Thermal Reference Data Section. Writes to

this register have no effect.

Offset:

73h

Bit

Description

7:0

Thermal Reference Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

Intel® Xeon® Processor 7400 Series Datasheet

129

Features

7.4.3.8

Feature Data

This section provides information on key features that the platform may need to

understand without powering on the processor.

7.4.3.8.1

PCFF: Processor Core Feature Flags

This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID

instruction. These details provide instruction and feature support by product family. A

decode of these bits is found in the AP-485 Intel^®Processor Identification and CPUID

Instruction application note. Writes to this register have no effect.

Offset:

74h-77h

Bit

Description

31:0

Processor Core Feature Flags

0000h-FFFFF: Feature Flags

7.4.3.8.2

PFF: Processor Feature Flags

This location contains additional feature information from the processor. Writes to this

register have no effect.

Note:

Bit 5 and Bit 6 are mutually exclusive (only one bit will be set).

Offset:

Bit

78h

Description

7

6

5

4

3

2

1

0

Multi-Core (set if the processor is a multi core processor)

Serial signature (set if there is a serial signature at offset 4D - 54h)

Electronic signature present (set if there is a electronic signature at 4D - 54h)

Thermal Sense Device present (set if an SMBus thermal sensor on package)

Reserved

OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh)

Core VID present (set if there is a VID provided by the processor)

L3 Cache present (set if there is a level 3 cache on the processor)

Bits are set when a feature is present, and cleared when they are not.

Example: The Intel® Xeon® Processor 7400 Series does not support a SMBus

Thermal Sense Device, supports either a Serial Signature or Electronic signature,

supports an OEM EEPROM, supports Core VID and supports an L3 Cache. Offset 78h

will contain A7h or C7h (167 or 199 decimal).

7.4.3.8.3

PTCI: Processor Thread and Core Information

This location contains information regarding the number of cores and threads on the

processor. Writes to this register have no effect.

Example: The Intel® Xeon® Processor 7400 Series has two, four or six cores and one

thread per core. Therefore, this register will have a value of 9h, 11h or 19h.

130

Intel® Xeon® Processor 7400 Series Datasheet

Features

Offset:

Bit

79h

Description

7:2

1:0

Number of cores

Number of threads per cores

7.4.3.8.4

AFF: Additional Processor Feature Flags

This location contains additional feature information for the processor. This field is

defined as follows: Writes to this register have no effect.

Offset:

Bit

7Ah

Description

7

6

5

4

3

2

1

0

Reserved

®

Intel Cache Safe Technology

Extended Halt State (C1E)

®

Intel Virtualization Technology

Execute Disable

®

Intel 64

Thermal Monitor 2

®

Enhanced Intel SpeedStep Technology

Bits are set when a feature is present, and cleared when they are not.

Example: The Intel® Xeon® Processor 7400 Series may or may not have Enhanced

Intel SpeedStep^®Technology present and supports all the other available features.

Offset 7Ah will contain 7Eh or 7Fh (126 or 127 decimal).

7.4.3.8.5

TAF: Thermal Adjustment Factors

This location contains information on thermal adjustment factors for the processor. This

field and it’s details are pending and will be updated in a future revision. Writes to this

register have no effect.

Offset:

Bit

7Bh-7Ch

Description

15:8

7:0

Measurement Correction Factor

Temperature Target

7.4.3.9

OD: Other Data

These locations are reserved. Writes to this register have no effect.

Offset:

7Dh-7Eh

Bit

Description

15:0

RESERVED

Intel® Xeon® Processor 7400 Series Datasheet

131

Features

7.4.3.9.1

FDCKS: Feature Data Checksum

This location provides the checksum of the Feature Data Section. Writes to this register

have no effect.

Offset:

7Fh

Bit

Description

7:0

Feature Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.4

Checksums

The PIROM includes multiple checksums. Table 7-7 includes the checksum values for

each section defined in the 128 byte ROM.

Table 7-7.

128 Byte ROM Checksum Values

Section

Checksum Address

Header

0Dh

15h

24h

31h

37h

6Fh

73h

7Fh

Processor Data

Processor Core Data

Cache Data

Package Data

Part Number Data

Thermal Ref. Data

Feature Data

Checksums are automatically calculated and programmed by Intel. The first step in

calculating the checksum is to add each byte from the field to the next subsequent

byte. This result is then negated to provide the checksum.

Example: For a byte string of AA445Ch, the resulting checksum will be B6h.

AA = 10101010

44 = 01000100

5C = 0101100

AA + 44 + 5C = 01001010

Negate the sum: 10110101 +1 = 101101 (B6h)

7.4.5

Scratch EEPROM

Also available in the memory component on the processor SMBus is an EEPROM which

may be used for other data at the system or processor vendor’s discretion. The data in

this EEPROM, once programmed, can be write-protected by asserting the active-high

SM_WP signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be

programmed in systems with no implementation of this signal. The Scratch EEPROM

resides in the upper half of the memory component (addresses 80 - FFh). The lower

half comprises the Processor Information ROM (addresses 00 - 7Fh), which is

permanently write-protected by Intel.

§

132

Intel® Xeon® Processor 7400 Series Datasheet

Debug Tools Specifications

8 Debug Tools Specifications

Please refer to the appropriate platform design guidelines for information regarding

debug tool specifications. Section 1.3 provides collateral details.

8.1

Debug Port System Requirements

The Intel® Xeon® Processor 7400 Series debug port is the command and control

interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of

the processors for system debug. The debug port, which is connected to the FSB, is a

combination of the system JTAG and execution signals. There are several mechanical,

electrical and functional constraints on the debug port that must be followed. The

mechanical constraint requires the debug port connector to be installed in the system

with adequate physical clearance. Electrical constraints exist due to the mixed high and

low speed signals of the debug port for the processor. While the JTAG signals operate at

a maximum of 75 MHz, the execution signals operate at the common clock FSB

frequency. The functional constraint requires the debug port to use the JTAG system via

a handshake and multiplexing scheme.

In general, the information in this chapter may be used as a basis for including all run-

control tools in Intel® Xeon® Processor 7400 Series-based systems designs including

tools from vendors other than Intel.

Note:

The debug port and JTAG signal chain must be designed into the processor board to

utilize the XDP for debug purposes except for interposer solutions.

8.2

Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces

(LAIs) for use in debugging Intel® Xeon® Processor 7400 Series systems. Tektronix

and Agilent should be contacted to obtain specific information about their logic analyzer

interfaces. The following information is general in nature. Specific information must be

obtained from the logic analyzer vendor.

Due to the complexity of Intel® Xeon® Processor 7400 Series-based multiprocessor

systems, the LAI is critical in providing the ability to probe and capture FSB signals.

There are two sets of considerations to keep in mind when designing a Intel® Xeon®

Processor 7400 Series-based system that can make use of an LAI: mechanical and

electrical.

8.2.1

Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI plugs into

the socket, while the processor plugs into a socket on the LAI. Cabling that is part of

the LAI egresses the system to allow an electrical connection between the processor

and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout

volume, as well as the cable egress restrictions, should be obtained from the logic

analyzer vendor. System designers must make sure that the keepout volume remains

unobstructed inside the system. In some cases, it is known that some of the electrolytic

capacitors fall inside of the keepout volume for the LAI. In this case, it is necessary to

move these capacitors to the backside of the board before using the LAI. Additionally,

note that it is possible that the keepout volume reserved for the LAI may include

Intel® Xeon® Processor 7400 Series Datasheet

133

Debug Tools Specifications

different requirements from the space normally occupied by the heatsink. If this is the

case, the logic analyzer vendor will provide either a cooling solution as part of the LAI

or additional hardware to mount the existing cooling solution.

8.2.2

Electrical Considerations

The LAI will also affect the electrical performance of the FSB, therefore it is critical to

obtain electrical load models from each of the logic analyzer vendors to be able to run

system level simulations to prove that their tool will work in the system. Contact the

logic analyzer vendor for electrical specifications and load models for the LAI solution

they provide.

§

134

Intel® Xeon® Processor 7400 Series Datasheet

Boxed Processor Specifications

9 Boxed Processor Specifications

9.1

Introduction

The Intel® Xeon® Processor 7400 Series is also offered as an Intel boxed processor.

Intel boxed processors are intended for system integrators who build systems from

baseboards and standard components. The boxed processor will not be supplied with a

cooling solution. Future revisions may have solutions that differ from those discussed

here.

9.2

Thermal Specifications

Please see Chapter 6 for the the cooling requirements of the boxed processor.

9.2.1

Boxed Processor Cooling Requirements

A suitable heatsink is required to properly cool the boxed processor. However, meeting

the processor’s temperature specifications is also a function of the thermal design of

the entire system, and ultimately the responsibility of the system integrator. The

processor temperature specification is found in Section 6.2.1 of this document.

§

Intel® Xeon® Processor 7400 Series Datasheet

135

Boxed Processor Specifications

136

Intel® Xeon® Processor 7400 Series Datasheet


型号：	AD80583QH046003
厂家：	INTEL
描述：	RISC Microprocessor, 64-Bit, 2130MHz, CMOS, PPGA604 外围集成电路
文件：	总136页 (文件大小：2839K)
中文：	中文翻译
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