AV80576LH0256M/SLGHC

Intel® Core™2 Duo Mobile

Processor, Intel® Core™2 Solo

Mobile Processor and Intel® Core™2

Extreme Mobile Processor on 45-nm

Process

Datasheet

For platforms based on Mobile Intel® 4 Series Express Chipset Family

March 2009

Document Number: 320120-004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE

FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics

of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for

conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with

this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Φ 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications

enabled for IntelÆ 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for

more information.

Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http://

processorfinder.intel.com or contact your Intel representative for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check

with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Φ

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some

uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations

and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

Intel, Pentium, Centrino, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction..............................................................................................................7

1.1

1.2

Terminology .......................................................................................................8

References .........................................................................................................9

2

Low Power Features................................................................................................ 11

2.1

Clock Control and Low-Power States .................................................................... 11

2.1.1 Core Low-Power State Descriptions........................................................... 13

2.1.1.1 Core C0 State........................................................................... 13

2.1.1.2 Core C1/AutoHALT Powerdown State........................................... 13

2.1.1.3 Core C1/MWAIT Powerdown State............................................... 14

2.1.1.4 Core C2 State........................................................................... 14

2.1.1.5 Core C3 State........................................................................... 14

2.1.1.6 Core C4 State........................................................................... 14

2.1.1.7 Core Deep Power Down Technology (Code Name C6) State ............ 15

2.1.2 Package Low-power State Descriptions...................................................... 15

2.1.2.1 Normal State............................................................................ 15

2.1.2.2 Stop-Grant State ...................................................................... 15

2.1.2.3 Stop-Grant Snoop State............................................................. 16

2.1.2.4 Sleep State.............................................................................. 16

2.1.2.5 Deep Sleep State...................................................................... 16

2.1.2.6 Deeper Sleep State................................................................... 17

Enhanced Intel SpeedStep® Technology .............................................................. 19

Extended Low-Power States................................................................................ 20

FSB Low Power Enhancements............................................................................ 21

2.4.1 Dynamic FSB Frequency Switching ........................................................... 21

2.4.2 Enhanced Intel® Dynamic Acceleration Technology .................................... 22

VID-x .............................................................................................................. 23

Processor Power Status Indicator (PSI-2) Signal.................................................... 23

2.2

2.3

2.4

2.5

2.6

3

Electrical Specifications........................................................................................... 25

3.1

3.2

Power and Ground Pins ...................................................................................... 25

Decoupling Guidelines........................................................................................ 25

3.2.1 VCC Decoupling...................................................................................... 25

3.2.2 FSB AGTL+ Decoupling ........................................................................... 25

3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 25

Voltage Identification and Power Sequencing ........................................................ 26

Catastrophic Thermal Protection.......................................................................... 29

Reserved and Unused Pins.................................................................................. 29

FSB Frequency Select Signals (BSEL[2:0])............................................................ 29

FSB Signal Groups............................................................................................. 30

CMOS Signals ................................................................................................... 31

Maximum Ratings.............................................................................................. 31

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10 Processor DC Specifications ................................................................................ 32

4

5

Package Mechanical Specifications and Pin Information.......................................... 51

4.1

4.2

4.3

Package Mechanical Specifications....................................................................... 51

Processor Pinout and Pin List .............................................................................. 59

Alphabetical Signals Reference............................................................................ 93

Thermal Specifications and Design Considerations ................................................ 101

5.1

Monitoring Die Temperature ............................................................................. 108

5.1.1 Thermal Diode ..................................................................................... 108

5.1.2 Intel® Thermal Monitor......................................................................... 109

Datasheet

3

5.1.3 Digital Thermal Sensor ..........................................................................111

Out of Specification Detection............................................................................112

PROCHOT# Signal Pin ......................................................................................112

5.2

5.3

Figures

1

2

3

4

Core Low-Power States .............................................................................................12

Package Low-Power States ........................................................................................13

Dynamic FSB Frequency Switching Protocol..................................................................22

Active VCC and ICC Loadline for Standard Voltage, Low-Power SV (25 W) and Dual-Core,

Extreme Edition Processors........................................................................................43

Deeper Sleep VCC and ICC Loadline for Standard-Voltage, Low-Power SV (25 W) and Dual-

Core Extreme Edition Processors ................................................................................44

Deeper Sleep VCC and ICC Loadline for Low-Power Standard-Voltage Processors ..............45

Active VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized

Performance Processor..............................................................................................46

Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized

Performance Processor..............................................................................................47

6-MB and 3-MB on 6-MB Die Micro-FCPGA Package Drawing (Sheet 1 of 2) ......................52

5

6

7

8

9

10 3-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ...................................53

11 3-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)...................................54

12 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ..................................55

13 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ..................................56

14 Intel Core 2 Duo Mobile Processor (POP and LV) Die Micro-FCBGA Processor Package

Drawing..................................................................................................................57

15 Intel Core 2 Duo Mobile Processor (ULV SC and ULV DC) Die Micro-FCBGA Processor Package

Drawing..................................................................................................................58

16 Processor Pinout (Top Package View, Left Side) ............................................................59

17 Processor Pinout (Top Package View, Right Side) ..........................................................60

18 Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side.....................80

19 Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side...................81

20 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Left Side.....................82

21 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side...................83

Tables

1

Coordination of Core Low-Power States at the Package Level..........................................13

2

3

4

5

6

7

8

Voltage Identification Definition..................................................................................26

BSEL[2:0] Encoding for BCLK Frequency......................................................................29

FSB Pin Groups ........................................................................................................30

Processor Absolute Maximum Ratings..........................................................................31

Voltage and Current Specifications for the Dual-Core, Extreme Edition Processors .............32

Voltage and Current Specifications for the Dual-Core, Standard-Voltage Processors...........34

Voltage and Current Specifications for the Dual-Core, Low-Power Standard-Voltage Processors

(25 W) in Standard Package ......................................................................................35

Voltage and Current Specifications for the Dual-Core, Power Optimized Performance (25 W)

SFF Processors.........................................................................................................37

9

10 Voltage and Current Specifications for the Dual-Core, Low-Voltage SFF Processor .............38

11 Voltage and Current Specifications for the Dual-Core, Ultra-Low-Voltage SFF Processor .....40

12 Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core

(5.5 W) SFF Processor...............................................................................................41

13 AGTL+ Signal Group DC Specifications ........................................................................48

14 CMOS Signal Group DC Specifications..........................................................................49

15 Open Drain Signal Group DC Specifications ..................................................................49

4

Datasheet

16 Pin Name Listing...................................................................................................... 61

17 Pin # Listing............................................................................................................ 72

18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name........................... 84

19 Signal Description .................................................................................................... 93

20 Power Specifications for the Dual-Core Extreme Edition Processor................................. 101

21 Power Specifications for the Dual-Core Standard Voltage Processor............................... 102

22 Power Specifications for the Dual-Core Low Power Standard Voltage Processors (25 W) in

Standard Package .................................................................................................. 103

23 Power Specifications for the Dual-Core Power Optimized Performance (25 W) SFF

Processors ............................................................................................................ 104

24 Power Specifications fro the Dual-Core Low Voltage (LV) SFF Processors ....................... 105

25 Power Specifications for the Dual-Core Ultra-Low-Voltage (ULV) Processors ................... 106

26 Power Specifications for the Single-Core Ultra-Low-Voltage (5.5 W) SFF Processors ........ 107

27 Thermal Diode Interface ......................................................................................... 108

28 Thermal Diode Parameters Using Transistor Model...................................................... 109

Datasheet

5

Revision History

Document Revision

Description

Date

Number

320120

-001

Initial Release

July 2008

• Chapter Update

— Chapter 1: Added introduction to the Intel Core 2 Duo

Processor in SFF Package

— Section 4.1: Added the package coplanarity information for

the processors in SFF Package

• Figure Update

— Added Figure 7

— Added Figure 8

— Added Figure 14

— Added Figure 15

— Added Figure 18 through Figure 21

• Table Update

320120

-002

August 2008

— Added Table 9

— Added Table 10

— Added Table 11

— Added Table 12

— Updated Table 16: Added Intel Core 2 Duo SFF Package

Processor Ball listing by Pin name

— Added Table 18

— Added Table 23

— Added Table 24

— Added Table 25

• Added information for Intel Core 2 Duo T9800, T9550, P9600,

P8700

320120

-003

-004

January 2009

March 2009

• Added information for Intel Core 2 Duo processor skus below:

— Updated Table 7 and 21 with T9900

— Updated Table 9 and 23 with SP9600

— Updated Table 10 and 24 with SL9600

— Updataed Table 11 and 25 with SU9600

— Updated Table 12 and 26 with SU3500

§

6

Datasheet

Introduction

1

Introduction

The Intel® Core^™2 Duo mobile processor, Intel® Core^™2 Duo mobile processor low-

voltage (LV), ultra low-voltage (ULV) in small form factor (SFF) package and Intel®

Core^™2 Extreme mobile are high-performance, low-power mobile processor based on

the Intel Core microarchitecture for Intel® Centrino® 2 processor technology.

This document contains electrical, mechanical and thermal specifications for the

following processors:

• The Intel Core 2 Duo processors and Intel Core 2 Extreme processors support the

Mobile Intel® 4 Series Express Chipset and Intel® ICH9M I/O controller.

— Dual-core extreme edition (DC-XE)

— Standard voltage (SV)

— 25-W processor in standard package (Power Optimized Performance-POP)

• The Intel Core 2 Duo processor in SFF package supports the Mobile Intel® GS45

Express Chipset and Intel® ICH9M SFF I/O controller.

This document contains electrical, mechanical and thermal specifications for:

— Power Optimized Performance (POP) in SFF package

— Low-voltage (LV) Processor in SFF package

— Ultra-low voltage (ULV) dual-core (DC) and single-core (SC) Processors in SFF

package

Notes:

In this document

1. Intel Core 2 Duo processor, and the Intel Core 2 Extreme processor are referred to

as the processor

2. Intel Core 2 Duo LV/ULV/POP processors are referred to as SFF processor

3. Mobile Intel 4 Series Express Chipset is referred as the GMCH.

Key features include:

• Dual-core processor for mobile with enhanced performance

• Supports Intel architecture with Intel® Wide Dynamic Execution

• Supports L1 cache-to-cache (C2C) transfer

• On-die, primary 32-KB instruction cache and 32-KB, write-back data cache in each

core

• The processor in DC-XE, standard voltage (SV) and LV have an on-die, up to 6-MB

second-level, shared cache with Advanced Transfer Cache architecture

• The processor in ULV single-core and dual-core have an on-die, up to 3-MB

second-level, shared cache with Advanced Transfer Cache architecture

• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3),

supplemental streaming SIMD extensions 3 (SSSE3) and SSE4.1 instruction sets

• The processor in DC-XE, SV and LV are offered at 1066-MHz, source-synchronous

front side bus (FSB)

• The processor in ULV are offered at 800-MHz, source-synchronous FSB

• Advanced power management features including Enhanced Intel SpeedStep®

Technology and dynamic FSB frequency switching

Datasheet

7

Introduction

• Digital thermal sensor (DTS)

• Intel® 64 architecture

• Supports enhanced Intel® Virtualization Technology

• Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded

Thermal Management (EMTTM)

• Supports PSI2 functionality

• SV processor offered in Micro-FCPGA and Micro-FCBGA packaging technologies

• Processor in POP, LV and ULV are offered in Micro-FCBGA packaging technologies

only

• Execute Disable Bit support for enhanced security

• Intel® Deep Power Down low-power state with P_LVL6 I/O support

• Support for Intel® Trusted Execution Technology

• Half ratio support (N/2) for core to bus ratio

1.1

Terminology

Term

Definition

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

#

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

AGTL+

Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor landings should not

be connected to any supply voltages, have any I/Os biased or receive any

clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device

removed from packaging material) the processor must be handled in

accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

Storage

Conditions

Enhanced Intel

SpeedStep®

Technology

Technology that provides power management capabilities to laptops.

Processor core die with integrated L1 and L2 cache. All AC timing and signal

integrity specifications are at the pads of the processor core.

Processor Core

8

Datasheet

Introduction

Term

Definition

The Execute Disable bit allows memory to be marked as executable or non-

executable, when combined with a supporting operating system. If code

attempts to run in non-executable memory the processor raises an error to

the operating system. This feature can prevent some classes of viruses or

worms that exploit buffer overrun vulnerabilities and can thus help improve

the overall security of the system. See the Intel® 64 and IA-32

Execute Disable

Bit

Architectures Software Developer's Manuals for more detailed information.

Intel® 64

Technology

64-bit memory extensions to the IA-32 architecture.

Intel®

Virtualization

Technology

Processor virtualization that, when used in conjunction with Virtual Machine

Monitor software, enables multiple, robust independent software

environments inside a single platform.

Half ratio support

(N/2) for Core to

Bus ratio

Intel Core 2 Duo processors and Intel Core 2 Extreme processors support

the N/2 feature that allows having fractional core-to-bus ratios. This feature

provides the flexibility of having more frequency options and being able to

have products with smaller frequency steps.

TDP

V_CC

V_SS

Thermal Design Power.

The processor core power supply.

The processor ground.

Low-voltage

LV

ULV

DC-XE

Ultra-Low-Voltage

Dual-core Extreme Edition

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document.

Document

Number

Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile

Processor, Intel® Core™2 Extreme Processor on 45-nm Technology

320121

Specification Update

Mobile Intel® 4 Series Express Chipset Family Datasheet

320122

320123

Mobile Intel® 4 Series Express Chipset Family Specification Update

Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)

Datasheet

316972

316973

Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)

Specification Update

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture

253665

253666

Volume 2A: Instruction Set Reference, A-M

Datasheet

9

Introduction

Document

Number

Document

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

253667

253668

253669

NOTE: Contact your Intel representative for the latest revision of this document.

§

10

Datasheet

Low Power Features

2

Low Power Features

2.1

Clock Control and Low-Power States

The processor supports low-power states both at the individual core level and the

package level for optimal power management.

A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel®

Enhanced Deeper Sleep and Intel® Deep Power Down Technology low-power states.

When both cores coincide in a common core low-power state, the central power

management logic ensures the entire processor enters the respective package low-

power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, P_LVL5,P_LVL6) I/O read

to the GMCH.

The processor implements two software interfaces for requesting low-power states:

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK

register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are

converted to equivalent MWAIT C-state requests inside the processor and do not

directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does

not need to be set up before using the P_LVLx I/O read interface. The sub-state hints

used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model

specific register (MSR).

If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the

PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system

logic that individual cores should return to the C0 state and the processor should return

to the Normal state.

Figure 1 shows the core low-power states and Figure 2 shows the package low-power

states for the processor. Table 1 maps the core low-power states to package low-power

states.

Datasheet

11

Low Power Features

Figure 1.

Core Low-Power States

Stop

Grant

STPCLK#

asserted

STPCLK#

deasserted

STPCLK#

deasserted

STPCLK#

asserted

STPCLK#

deasserted

STPCLK#

asserted

C1/Auto

Halt

C1/MWAIT

Core state

break

HLT instruction

MWAIT(C1)

Halt break

C0

P_LVL2 or

MWAIT(C2)

Core State

break

Core state

break

P_LVL3 or

C2^†

P_LVL4 or

P_LVL5/P_LVL6^ø

MWAIT(C4/C6)

Core

state

MWAIT(C3)

C4^{† ‡}/C6

break

C3^†

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.

‡ — Core C4 state supports the package level Deep C4 sub-state.

Ø — P_LVL5/P_LVL6 read is issued once the L2 cache is reduced to zero.

12

Datasheet

Low Power Features

Figure 2.

Package Low-Power States

SLP# asserted

DPSLP# asserted

DPRSTP# asserted

STPCLK# asserted

Stop

Grant

Deep

Sleep

Deeper

Sleep^†

Normal

Sleep

STPCLK# deasserted

SLP# deasserted

DPSLP# deasserted

DPRSTP# deasserted

Snoop Snoop

serviced occurs

Stop Grant

Snoop

† — Deeper Sleep includes the Deeper Sleep state, Deep C4 sub-state, and C6

Table 1.

Coordination of Core Low-Power States at the Package Level

Package State

Core1 State

C4/Deep Power Down

Technology State

Core0 State

C0

C1¹

C2

C3

(Code Named C6 State)

C0

C1¹

C2

Normal

Normal Stop-Grant Stop-Grant

Normal Stop-Grant Deep Sleep

Stop-Grant

Deep Sleep

C3

Deeper Sleep /Intel®

Enhanced Deeper Sleep/

Intel® Deep Power Down

C4/Deep Power

Down Technology

Normal

Normal Stop-Grant Deep Sleep

NOTE:

1.

AutoHALT or MWAIT/C1.

2.1.1

Core Low-Power State Descriptions

2.1.1.1

Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2

Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when a core executes the HALT instruction.

The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,

LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to

immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures

Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more

information.

Datasheet

13

Low Power Features

The system can generate a STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

While in AutoHALT Powerdown state, the dual-core processor will process bus snoops

and snoops from the other core. The processor core will enter a snoopable sub-state

(not shown in Figure 1) to process the snoop and then return to the AutoHALT

Powerdown state.

2.1.1.3

2.1.1.4

Core C1/MWAIT Powerdown State

C1/MWAIT is a low-power state entered when the processor core executes the

MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the

AutoHALT state except that Monitor events can cause the processor core to return to

the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,

Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference,

N-Z, for more information.

Core C2 State

Individual cores of the dual-core processor can enter the C2 state by initiating a P_LVL2

I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a

Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

While in the C2 state, the dual-core processor will process bus snoops and snoops from

the other core. The processor core will enter a snoopable sub-state (not shown in

Figure 1) to process the snoop and then return to the C2 state.

2.1.1.5

Core C3 State

Individual cores of the dual-core processor can enter the C3 state by initiating a P_LVL3

I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor

core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the

caches, the processor core maintains all its architectural states in the C3 state. The

Monitor remains armed if it is configured. All of the clocks in the processor core are

stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state

when the processor detects a snoop on the FSB or when the other core of the dual-core

processor accesses cacheable memory. The processor core will transition to the C0

state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB

interrupt message. RESET# will cause the processor core to immediately initialize itself.

2.1.1.6

Core C4 State

Individual cores of the dual-core processor can enter the C4 state by initiating a P_LVL4

or P_LVL5 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core

behavior in the C4 state is nearly identical to the behavior in the C3 state. The only

difference is that if both processor cores are in C4, the central power management logic

will request that the entire processor enter the Deeper Sleep package low-power state

(see Section 2.1.2.6).

To enable the package-level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing

and Intel Enhanced Deeper Sleep state fields must be configured in the

PMG_CST_CONFIG_CONTROL MSR. Refer to Section 2.1.2.6 for further details on Intel

Enhanced Deeper Sleep state.

14

Datasheet

Low Power Features

2.1.1.7

Core Deep Power Down Technology (Code Name C6) State

Deep Power Down Technology state is a new, power-saving state which is being

implemented on the processor. In Deep Power Down Technology the processor saves its

entire architectural state onto an on-die SRAM hence allowing it to lower its main core

voltage to any value, even as low as 0-V.

When the core enters Deep Power Down Technology state, it saves the processor state

that is relevant to the processor context in an on-die SRAM that resides on a separate

power plane V_CCP(I/O power supply). This allows the main core Vcc to be lowered to

any arbitrary voltage including 0-V. The on-die storage for saving the processor state is

implemented as a per-core SRAM.

2.1.2

Package Low-power State Descriptions

2.1.2.1

Normal State

This is the normal operating state for the processor. The processor remains in the

Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT

state.

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted, each core of the dual-core processor enters the

Stop-Grant state within 20 bus clocks after the response phase of the processor-issued

Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2,

C3, or C4 state remain in their current low-power state. When the STPCLK# pin is

deasserted, each core returns to its previous core low-power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to V_CCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should be

driven to the inactive state.

RESET# causes the processor to immediately initialize itself, but the processor will stay

in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#,

DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC

Specification T45. When re-entering the Stop-Grant state from the Sleep state,

STPCLK# should be deasserted after the deassertion of SLP# as per AC Specification

T75.

While in Stop-Grant state, the processor will service snoops and latch interrupts

delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts

and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be

asserted if there is any pending interrupt or Monitor event latched within the processor.

Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause

assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor

should return to the Normal state.

A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop

on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)

occurs with the assertion of the SLP# signal.

Datasheet

15

Low Power Features

2.1.2.3

2.1.2.4

Stop-Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor will stay in this

state until the snoop on the FSB has been serviced (whether by the processor or

another agent on the FSB) or the interrupt has been latched. The processor returns to

the Stop-Grant state once the snoop has been serviced or the interrupt has been

latched.

Sleep State

The Sleep state is a low-power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#

pin should only be asserted when the processor is in the Stop-Grant state. SLP#

assertions while the processor is not in the Stop-Grant state is out of specification and

may result in unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep

state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state will cause unpredictable behavior. Any transition on an input signal before

the processor has returned to the Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor will reset itself, ignoring

the transition through the Stop-Grant state. If RESET# is driven active while the

processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted

immediately after RESET# is asserted to ensure the processor correctly executes the

Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While

the processor is in the Sleep state, the SLP# pin must be deasserted if another

asynchronous FSB event needs to occur.

2.1.2.5

Deep Sleep State

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep

state. BCLK may be stopped during the Deep Sleep state for additional platform-level

power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with

the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs

of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to

allow for PLL stabilization) must occur before the processor can be considered to be in

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop

transactions or latching interrupt signals. No transitions of signals are allowed on the

FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep

16

Datasheet

Low Power Features

state, it will not respond to interrupts or snoop transactions. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable

behavior.

2.1.2.6

Deeper Sleep State

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core

voltage levels. One of the potential lower core voltage levels is achieved by entering the

base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the

DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is

achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of

Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of

the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely

shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.3 for further details on

reducing the L2 cache and entering Intel Enhanced Deeper Sleep state.

In response to entering Deeper Sleep, the processor drives the VID code corresponding

to the Deeper Sleep core voltage on the VID[6:0] pins.

Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP#

deassertion when either core requests a core state other than C4 or either core

requests a processor performance state other than the lowest operating point.

2.1.2.6.1

Intel® Enhanced Deeper Sleep State

Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power-

saving capabilities by allowing the processor to further reduce core voltage once the L2

cache has been reduced to zero ways and completely shut down. The following events

occur when the processor enters Intel Enhanced Deeper Sleep state:

• The last core entering C4 issues a P_LVL4 or P_LVL5 I/O read or an MWAIT(C4)

instruction and then progressively reduces the L2 cache to zero

• Once the L2 cache has been reduced to zero, the processor triggers a special

chipset sequence to notify the chipset to redirect all FSB traffic, except APIC

messages, to memory. The snoops are replied as misses by the chipset and are

directed to main memory instead of the L2 cache. This allows for higher residency

of the processor’s Intel Enhanced Deeper Sleep state.

• The processor drives the VID code corresponding to the Intel Enhanced Deeper

Sleep state core voltage on the VID[6:0] pins.

2.1.2.6.2

Deep Power Down State Technology (Code Named C6) State

When both cores have entered the CC6 state and the L2 cache has been shrunk down

to zero ways, the processor will enter the Deep Power Down Technology state. To do so

both cores save their architectural states in the on-die SRAM that resides in the V_CCP

domain. At this point, the core V_CCwill be dropped to the lowest core voltage closer to

0-V. The processor is now in an extremely low-power state.

In Intel Deep Power Down Technology state, the processor does not need to be

snooped as all the caches are flushed before entering this state.

Datasheet

17

Low Power Features

2.1.2.6.3

Dynamic Cache Sizing

Dynamic Cache Sizing allows the processor to flush and disable a programmable

number of L2 cache ways upon each Deeper Sleep entry under the following

conditions:

• The second core is already in C4 and Intel Enhanced Deeper Sleep state or Deep

Power Down Technology state (C6) is enabled (as specified in Section 2.1.1.6).

• The C0 timer that tracks continuous residency in the Normal package state has not

expired. This timer is cleared during the first entry into Deeper Sleep to allow

consecutive Deeper Sleep entries to shrink the L2 cache as needed.

• The FSB speed to processor core speed ratio is below the predefined L2 shrink

threshold.

The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in

the BBL_CR_CTL3 MSR. The C0 timer is referenced through the

CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2

cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the

FSB speed to processor core speed ratio is above the predefined L2 shrink threshold,

then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be

taken into account for Dynamic Cache Sizing decisions.

Upon STPCLK# deassertion, the first core exiting Intel Enhanced Deeper Sleep state or

Deep Power Down Technology state will expand the L2 cache to two ways and

invalidate previously disabled cache ways. If the L2 cache reduction conditions stated

above still exist when the last core returns to C4 and the package enters Intel

Enhanced Deeper Sleep state or Deep Power Down Technology state (C6), then the L2

will be shrunk to zero again. If a core requests a processor performance state resulting

in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the

second core (not the one currently entering the interrupt routine) requests the C1, C2,

or C3 states, then the whole L2 will be expanded upon the next interrupt event.

In addition, the processor supports Full Shrink on L2 cache. When the MWAIT Deep

Power Down Technology state instruction is executed with a hint=0x2 in ECX[3:0], the

micro code will shrink all the active ways of the L2 cache in one step. This ensures that

the package enters Deep Power Down Technology immediately when both cores are in

CC6 instead of iterating till the cache is reduced to zero. The operating system (OS) is

expected to use this hint when it wants to enter the lowest power state and can

tolerate the longer entry latency.

L2 cache shrink prevention may be enabled as needed on occasion through an

MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not

enter Intel Enhanced Deeper Sleep state or Intel Deep Power Down state since the L2

cache remains valid and in full size.

18

Datasheet

Low Power Features

2.2

Enhanced Intel SpeedStep® Technology

The processor features Enhanced Intel SpeedStep Technology. Following are the key

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the

lowest power.

• Voltage and frequency selection is software-controlled by writing to processor

MSRs:

— If the target frequency is higher than the current frequency, V_CCis ramped up

in steps by placing new values on the VID pins, and the PLL then locks to the

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the V_CCis changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch-free

transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 μs during the

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high

the processor can automatically perform a transition to a lower frequency and

voltage specified in a software-programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to

acceptable levels, an up-transition to the previous frequency and voltage point

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions

enabling better system-level thermal management.

• Enhanced thermal management features:

— Digital Thermal Sensor and Out of Specification detection.

— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in

case of unsuccessful TM2 transition.

— Dual-core thermal management synchronization.

Each core in the dual-core processor implements an independent MSR for controlling

Enhanced Intel SpeedStep Technology, but both cores must operate at the same

frequency and voltage. The processor has performance state coordination logic to

resolve frequency and voltage requests from the two cores into a single frequency and

voltage request for the package as a whole. If both cores request the same frequency

and voltage, then the processor will transition to the requested common frequency and

voltage. If the two cores have different frequency and voltage requests, then the

processor will take the highest of the two frequencies and voltages as the resolved

request and transition to that frequency and voltage.

The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic

Acceleration Technology mode on select SKUs. The operating system can take

advantage of these features and request a lower operating point called SuperLFM (due

to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic

Acceleration Technology mode.

Datasheet

19

Low Power Features

2.3

Extended Low-Power States

Extended low-power states (CXE) optimize for power by forcibly reducing the

performance state of the processor when it enters a package low-power state. Instead

of directly transitioning into the package low-power state, the enhanced package low-

power state first reduces the performance state of the processor by performing an

Enhanced Intel SpeedStep Technology transition down to the lowest operating point.

Upon receiving a break event from the package low-power state, control will be

returned to software while an Enhanced Intel SpeedStep Technology transition up to

the initial operating point occurs. The advantage of this feature is that it significantly

reduces leakage while in the Stop-Grant and Deeper Sleep states.

Deep Power Down Technology is always enabled in the extended low power state as

described above.

Note:

Long-term reliability cannot be assured unless all the Extended Low Power States are

enabled.

The processor implements two software interfaces for requesting enhanced package

low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by

configuring IA32_MISC_ENABLES MSR bits to automatically promote package low-

power states to enhanced package low-power states.

Caution:

Extended Stop-Grant and Enhanced Deeper Sleep must be enabled via the

BIOS for the processor to remain within specification. As processor technology

changes, enabling the extended low power states becomes increasingly crucial when

building computer systems. Maintaining the proper BIOS configuration is key to

reliable, long-term system operation. Not complying to this guideline may affect the

long-term reliability of the processor.

Enhanced Intel SpeedStep Technology transitions are multistep processes

that require clocked control. These transitions cannot occur when the processor is in

the Sleep or Deep Sleep package low-power states since processor clocks are not

active in these states. Extended Deeper Sleep is an exception to this rule when the

Hard C4E configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended

Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while

in Deeper Sleep and, upon exit, will automatically transition to the lowest operating

voltage and frequency to reduce snoop service latency. The transition to the lowest

operating point or back to the original software-requested point may not be

instantaneous. Furthermore, upon very frequent transitions between active and idle

states, the transitions may lag behind the idle state entry resulting in the processor

either executing for a longer time at the lowest operating point or running idle at a high

operating point. Observations and analyses show this behavior should not significantly

impact total power savings or performance score while providing power benefits in

most other cases.

20

Datasheet

Low Power Features

2.4

FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On-Die Termination disabling

• Low V_CCP(I/O termination voltage)

• Dynamic FSB frequency switching

The processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates

them only when data bus activity occurs, resulting in significant power savings with no

performance impact. BPRI# control also allows the processor address and control input

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows

a reciprocal power reduction in GMCH address and control input buffers when the

processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers

is disabled when the signals are driven low, resulting in additional power savings. The

low I/O termination voltage is on a dedicated voltage plane independent of the core

voltage, enabling low I/O switching power at all times.

2.4.1

Dynamic FSB Frequency Switching

Dynamic FSB frequency switching effectively reduces the internal bus clock frequency

in half to further decrease the minimum processor operating frequency from the

Enhanced Intel SpeedStep Technology performance states and achieve the Super Low

Frequency Mode (Super LFM). This feature is supported at FSB frequencies of

1066 MHz, 800 MHz and 667 MHz and does not entail a change in the external bus

signal (BCLK) frequency. Instead, both the processor and GMCH internally lower their

BCLK reference frequency to 50% of the externally visible frequency. Both the

processor and GMCH maintain a virtual BCLK signal (VBCLK) that is aligned to the

external BCLK but at half the frequency. After a downward shift, it would appear

externally as if the bus is running with a 133-MHz base clock in all aspects, except that

the actual external BCLK remains at 266 MHz. See Figure 3 for details. The transition

into Super LFM, a “down-shift,” is done following a handshake between the processor

and GMCH. A similar handshake is used to indicate an “up-shift,” a change back to

normal operating mode. Please ensure this feature is enabled and supported in the

BIOS.

Datasheet

21

Low Power Features

Figure 3.

Dynamic FSB Frequency Switching Protocol

NOTES:

1.

2.

All common clock signals will be active for two BCLKs instead of one (e.g., ADS#, HIT#).

The double-pumped signal strobes will have only one transition per BCLK when active,

instead of two.

3.

The quad-pumped signal strobes will have only two transitions per BCLK when active,

instead of four.

4.

5.

6.

7.

Same setup and hold times apply, but relative to every second rising BCLK.

Following a RESET#, the bus will be in the legacy full-frequency mode.

There will not be a down-shift right after RESET# deassertion.

There is no backing out of a transition into or out of half-frequency mode. Once the

sequence starts it must be completed.

2.4.2

Enhanced Intel® Dynamic Acceleration Technology

The processor supports Intel Dynamic Acceleration Technology mode. The Intel

Dynamic Acceleration Technology feature allows one core of the processor to operate at

a higher frequency point when the other core is inactive and the operating system

requests increased performance. This higher frequency is called the opportunistic

frequency and the maximum rated operating frequency is the ensured frequency.

The processor includes a hysteresis mechanism that improves overall Intel Dynamic

Acceleration Technology performance by decreasing unnecessary transitions of the

cores in and out of Intel Dynamic Acceleration Technology mode. Normally, the

processor would exit Intel Dynamic Acceleration Technology as soon as two cores are

active. This can become an issue if the idle core is frequently awakened for a short

periods (i.e., high timer tick rates). The hysteresis mechanism allows two cores to be

active for a limited time before it transitions out of Intel Dynamic Acceleration

Technology mode.

Intel Dynamic Acceleration Technology mode enabling requires:

• Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state

• Enhanced Multi-Threaded Thermal Management (EMTTM)

• Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via

BIOS.

22

Datasheet

Low Power Features

When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be

active under certain internal conditions. In such a scenario the processor may draw a

Instantaneous current (I_{CC_CORE_INST)}for a short duration of t_INST; however, the

average I_CCcurrent will be lesser than or equal to I_CCDEScurrent specification. Please

refer to the Processor DC Specifications section for more details.

2.5

VID-x

The processor implements the VID-x feature for improved control of core voltage levels

when the processor enters a reduced power consumption state. VID-x applies only

when the processor is in the Intel Dynamic Acceleration Technology performance state

and one or more cores are in low-power state (i.e., CC3/CC4/CC6). VID-x provides the

ability for the processor to request core voltage level reductions greater than one VID

tick. The amount of VID tick reduction is fixed and only occurs while the processor is in

Intel Dynamic Acceleration Technology mode. This improved voltage regulator

efficiency during periods of reduced power consumption allows for leakage current

reduction which results in platform power savings and extended battery life.

When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be

active under certain internal conditions. In such a scenario the processor may draw a

Instantaneous current (I_{CC_CORE_INST)}for a short duration of t_INST; however, the

average I_CCcurrent will be lesser than or equal to I_CCDEScurrent specification. Please

refer to the Processor DC Specifications section for more details.

2.6

Processor Power Status Indicator (PSI-2) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a

reduced power consumption state. PSI# can be used to improve intermediate and light

load efficiency of the voltage regulator, resulting in platform power savings and

extended battery life. The algorithm that the processor uses for determining when to

assert PSI# is different from the algorithm used in previous mobile processors. PSI-2

functionality is expanded further to support three processor states:

• Both cores are in idle state

• Only one core active state

• Both cores are in active state

PSI-2 functionality improves overall voltage regulator efficiency over a wide power

range based on the C-state and P-state of the two cores. The combined C-state and P-

state of both cores are used to dynamically predict processor power.

The real-time power prediction is compared against a set of predefined and configured

values of CHH and CHL. CHH is indicative of the active C-state of both the cores and

CHL is indicative that only one core is in active C-state and the other core is in low

power core state. PSI-2# output is asserted upon crossing these thresholds indicating

that the processor requires lower power. The voltage regulator will adapt its power

output accordingly. Additionally the voltage regulator may switch to a single phase and/

or asynchronous mode when the processor is idle and fused leakage limit is less than or

equal to the BIOS threshold value.

§

Datasheet

23

Low Power Features

24

Datasheet

Electrical Specifications

3

Electrical Specifications

3.1

Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of V_CC

(power) and V_SS(ground) inputs. All power pins must be connected to V_CCpower

planes while all V_SSpins must be connected to system ground planes. Use of multiple

power and ground planes is recommended to reduce I*R drop. The processor V_CCpins

must be supplied the voltage determined by the VID (Voltage ID) pins.

3.2

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large average current swings between low and full power states.

This may cause voltages on power planes to sag below their minimum values if bulk

decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply

current during longer lasting changes in current demand by the component, such as

coming out of an idle condition. Similarly, they act as a storage well for current when

entering an idle condition from a running condition. Care must be taken in the board

design to ensure that the voltage provided to the processor remains within the

specifications listed in the tables in Section 3.10. Failure to do so can result in timing

violations or reduced lifetime of the component.

3.2.1

V Decoupling

CC

V_CCregulator solutions need to provide bulk capacitance with a low Effective Series

Resistance (ESR) and keep a low interconnect resistance from the regulator to the

socket. Bulk decoupling for the large current swings when the part is powering on, or

entering/exiting low-power states, should be provided by the voltage regulator solution

depending on the specific system design.

3.2.2

3.2.3

FSB AGTL+ Decoupling

The processors integrate signal termination on the die as well as incorporate high

frequency decoupling capacitance on the processor package. Decoupling must also be

provided by the system motherboard for proper AGTL+ bus operation.

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous-generation processors, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio at manufacturing. The processor uses a differential clocking

implementation.

Datasheet

25

Electrical Specifications

3.3

Voltage Identification and Power Sequencing

The processor uses seven voltage identification pins,VID[6:0], to support automatic

selection of power supply voltages. The VID pins for the processor are CMOS outputs

driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding

to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to

a low-voltage level.

Table 2.

Voltage Identification Definition (Sheet 1 of 3)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

26

Datasheet

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 2 of 3)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

Datasheet

27

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 3 of 3)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

0.0000

28

Datasheet

Electrical Specifications

3.4

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An

external thermal sensor should also be used to protect the processor and the system

against excessive temperatures. Even with the activation of THERMTRIP#, which halts

all processor internal clocks and activity, leakage current can be high enough that the

processor cannot be protected in all conditions without the removal of power to the

processor. If the external thermal sensor detects a catastrophic processor temperature

of approximately 125°C (maximum), or if the THERMTRIP# signal is asserted, the V_CC

supply to the processor must be turned off within 500 ms to prevent permanent silicon

damage due to thermal runaway of the processor. THERMTRIP# functionality is not

ensured if the PWRGOOD signal is not asserted, and during Deep Power Down

Technology State (C6).

3.5

Reserved and Unused Pins

All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V_CC,

V_SS, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Section 4.2 for a pin listing of the

processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no-connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected. The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6,TEST7 pins are used for

test purposes internally and can be left as “No Connects”.

3.6

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.

Table 3.

BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1] BSEL[0]

BCLK Frequency

L

H

L

266 MHz

RESERVED

200 MHz

L

H

L

H

L

RESERVED

H

L

Datasheet

29

Electrical Specifications

3.7

FSB Signal Groups

The FSB signals have been combined into groups by buffer type in the following

sections. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as

well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the

AGTL+ output group as well as the AGTL+ I/O group when driving.

With the implementation of a source-synchronous data bus, two sets of timing

parameters are specified. One set is for common clock signals, which are dependent

upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second set is for

the source-synchronous signals which are relative to their respective strobe lines (data

and address) as well as the rising edge of BCLK0. Asychronous signals are still present

(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.

Table 4 identifies which signals are common clock, source synchronous, and

asynchronous.

Table 4.

FSB Pin Groups

Signal Group

Type

Signals¹

AGTL+ Common Synchronous to

Clock Input BCLK[1:0]

BPRI#, DEFER#, PREQ#⁵, RESET#, RS[2:0]#, TRDY#

AGTL+ Common Synchronous to

ADS#, BNR#, BPM[3:0]#³, BR0#, DBSY#, DRDY#,

HIT#, HITM#, LOCK#, PRDY#³, DPWR#

Clock I/O

BCLK[1:0]

Signals

Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]#

A[35:17]#

ADSTB[1]#

AGTL+ Source

Synchronous

I/O

Synchronous to

assoc. strobe

D[15:0]#, DINV0#

D[31:16]#, DINV1#

D[47:32]#, DINV2#

D[63:48]#, DINV3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

Synchronous to

BCLK[1:0]

AGTL+ Strobes

CMOS Input

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/

INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Asynchronous

Open Drain

Output

FERR#, IERR#, THERMTRIP#

Open Drain I/O

CMOS Output

CMOS Input

Asynchronous

PROCHOT#⁴

PSI#, VID[6:0], BSEL[2:0]

Synchronous to TCK TCK, TDI, TMS, TRST#

Synchronous to TCK TDO

Open Drain

Output

FSB Clock

Clock

BCLK[1:0]

COMP[3:0], DBR#², GTLREF, RSVD, TEST2, TEST1,

Power/Other

THERMDA, THERMDC, V_CC, V_CCA, V_CCP, V_{CC_SENSE}

_SS, V_{SS_SENSE}

,

V

NOTES:See next page

30

Datasheet

Electrical Specifications

1.

2.

Refer to Chapter 4 for signal descriptions and termination requirements.

In processor systems where there is no debug port implemented on the system board,

these signals are used to support a debug port interposer. In systems with the debug port

implemented on the system board, these signals are no connects.

BPM[2:1]# and PRDY# are AGTL+ output-only signals.

PROCHOT# signal type is open drain output and CMOS input.

On-die termination differs from other AGTL+ signals.

3.

4.

5.

3.8

3.9

CMOS Signals

CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,

all of the CMOS signals are required to be asserted for more than four BCLKs for the

processor to recognize them. See Section 3.10 for the DC specifications for the CMOS

signal groups.

Maximum Ratings

Table 5 specifies absolute maximum and minimum ratings only, which lie outside the

functional limits of the processor. Only within specified operation limits, can

functionality and long-term reliability be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function, or its reliability will be

severely degraded.

Caution:

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Table 5.

Processor Absolute Maximum Ratings

Symbol

T_STORAGE

Parameter

Min

Max

Unit

Notes^1,2

Processor Storage Temperature

-40

-25

85

°C

3,4,5

6

Any Processor Supply Voltage with

Respect to V_SS

V_CC

-0.3

-0.1

1.45

V

AGTL+ Buffer DC Input Voltage with

Respect to V_SS

V_inAGTL+

CMOS Buffer DC Input Voltage with

Respect to V_SS

V_{inAsynch_CMOS}

NOTES:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal

specifications must be satisfied.

Datasheet

31

Electrical Specifications

2.

3.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to

the processor.

Storage temperature is applicable to storage conditions only. In this scenario, the

processor must not receive a clock, and no lands can be connected to a voltage bias.

Storage within these limits will not affect the long-term reliability of the device. For

functional operation, please refer to the processor case temperature specifications.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long-term reliability of the processor.

For Intel® Core™2 Duo mobile processors in 22x22 mm package.

4.

5.

6.

3.10

Processor DC Specifications

The processor DC specifications in this section are defined at the processor

core (pads) unless noted otherwise.

The tables list the DC specifications for the processor and are valid only while meeting

specifications for junction temperature, clock frequency, and input voltages. The

Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest

and lowest core operating frequencies supported on the processor. Active mode load

line specifications apply in all states except in the Deep Sleep and Deeper Sleep states.

V

_CC,BOOTis the default voltage driven by the voltage regulator at power up in order to

set the VID values. Unless specified otherwise, all specifications for the processor are at

T_J= 105 °C. Read all notes associated with each parameter.

Table 6.

Voltage and Current Specifications for the Dual-Core, Extreme Edition

Processors (Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Notes

V_CCin Enhanced Intel® Dynamic Acceleration

Technology Mode

V_CCDAM

1.0

1.325

V

1, 2

V_CCHFM

V_CCLFM

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

1.0

—

1.275

1.1

V

1, 2

0.85

V_CCat Super Low Frequency Mode

(Super LFM)

V_CCSLFM

0.8

—

1.0

V

1, 2

2, 6

V_CC,BOOT

V_CCP

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

PLL Supply Voltage

—

1.20

1.05

1.5

—

V

1.00

1.425

0.65

0.6

1.10

1.575

0.85

V_CCA

V_CCDPRSLP

V_DC4

V_CCat Deeper Sleep

1, 2

V_CCat Intel® Enhanced Deeper Sleep State

—

0.85

V_CCat Deep Power Down Technology State

(C6)

V_CCDPPWDN

I_CCDES

0.35

—

0.7

V

A

I_CCfor Processors Recommended Design

Target

—

60

—

12

I_CCfor Processors

Processor

Core Frequency/Voltage

Number

I_CC

X9100

3.06 GHz & V_CCHFM

1.6 GHz & V_CCLFM

0.8 GHz & V_CCSLFM

59

34

24

—

A

3, 4, 10

32

Datasheet

Electrical Specifications

Table 6.

Symbol

Voltage and Current Specifications for the Dual-Core, Extreme Edition

Processors (Sheet 2 of 2)

Parameter

Min

Typ

Max

Unit

Notes

I_CCAuto-Halt & Stop-Grant

HFM

SuperLFM

I_AH,

I_SGNT

—

29.7

16.7

A

3, 4, 10

I_CCSleep

HFM

SuperLFM

I_SLP

—

28.8

16.5

A

3, 4, 10

I_CCDeep Sleep

HFM

SuperLFM

I_DSLP

26.8

16.0

I_DPRSLP

I_DC4

I_CCDeeper Sleep (C4)

—

12.2

11.7

11.0

A

3, 4

I_CCIntel Enhanced Deeper Sleep State

I_CCDeep Power Down Technology State (C6)

I_PPWDN

V_CCPower Supply Current Slew Rate at

Processor Package Pin

dI_CC/DT

I_CCA

—

600

130

mA/µs

mA

5, 7

I_CCfor V_CCASupply

8

9

I_CCfor V_CCPSupply before V_CCStable

4.5

2.5

A

I_CCP

I

_CCfor V_CCPSupply after V_CCStable

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (Intel Thermal

Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

6.

7.

Specified at 105 °C T_J.

Specified at the nominal V_CC

Measured at the bulk capacitors on the motherboard.

_CC,BOOTtolerance shown in Figure 4 and Figure 5.

.

V

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

8.

9.

10.

This is a power-up peak current specification, which is applicable when V_CCPis high and V_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification, which is applicable when both V_CCPand V_{CC_CORE}are high.

The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or

equal to 300 mV.

11.

The I_CCDES(max) specification of 60 A is for Intel® Core^™2 Extreme processors only.

Datasheet

33

Electrical Specifications

Table 7.

Voltage and Current Specifications for the Dual-Core, Standard-Voltage

Processors

Symbol

Parameter

Min

Typ

Max

Unit

Notes

V_CCin Enhanced Intel® Dynamic Acceleration

Technology Mode

V_CCDAM

1.0

1.3

V

1, 2

V_CCHFM

V_CCLFM

V_CCSLFM

V_CC,BOOT

V_CCP

V_CCat Highest Frequency Mode (HFM)

V_CCat Lowest Frequency Mode (LFM)

V_CCat Super Low Frequency Mode (Super LFM)

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.0

0.85

0.75

—

1.25

1.1

V

A

1, 2

2, 6

—

0.95

—

1.2

1.05

1.5

—

1.0

1.1

V_CCA

PLL Supply Voltage

1.425

0.65

0.6

1.575

0.85

0.7

V_CCDPRSLP

V_DC4

V_CCat Deeper Sleep

1, 2

12

V_CCat Intel® Enhanced Deeper Sleep State

—

V_CCDPPWDNV_CCat Deep Power Down Technology State (C6)

0.35

—

I_CCDES

I_CCfor Processors Recommended Design Target

I_CCfor Processors

—

47

—

Processor

Core Frequency/Voltage

Number

—

T9900

T9800

T9600

T9550

T9400

3.06 GHz & V_CCHFM

2.93 GHz & V_CCHFM

2.80 GHz & V_CCHFM

2.66 GHz & V_CCHFM

2.53 GHz & V_CCHFM

1.6 GHz & V_CCLFM

0.8 GHz & V_CCSLFM

47

I_CC

—

A

3, 4, 10

31.4

22.4

I_CCAuto-Halt & Stop-Grant

HFM

SuperLFM

I_AH,

I_SGNT

—

25.4

13.7

A

3, 4, 10

I_CCSleep

HFM

SuperLFM

I_SLP

24.7

13.5

I_CCDeep Sleep

HFM

SuperLFM

I_DSLP

22.9

13.0

I_DPRSLP

I_DC4

I_CCDeeper Sleep (C4)

—

11.7

10.5

5.7

A

3, 4

I_CCIntel Enhanced Deeper Sleep

I_CCDeep Power Down Technology State (C6)

I_PPWDN

V_CCPower Supply Current Slew Rate at Processor

Package Pin

dI_CC/DT

I_CCA

—

600

130

mA/µs

mA

5, 7

I_CCfor V_CCASupply

8

9

I_CCCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

I_CCP

NOTES:See next page.