AV80585VG0091MPSLGAN

Intel® Celeron® Processor 900

Series and Ultra Low Voltage 700

Series

Datasheet

For platforms based on Mobile Intel® 4 Series Chipset family

February 2010

Document Number: 320389-003

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FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics

of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for

conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with

this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Φ 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications

enabled for Intel 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for

more information.

45nm product is manufactured on a lead-free process. Lead is below 1000 PPM per EU RoHS directive (2002/95/EC, Annex A). Some EU RoHS

exemptions for lead may apply to other components used in the product package.

Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http://

processorfinder.intel.com or contact your Intel representative for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check

with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Φ

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some

uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations

and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

Intel, Celeron, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction..............................................................................................................6

1.1

1.2

Terminology .......................................................................................................7

References .........................................................................................................8

2

Low Power Features..................................................................................................9

2.1

Clock Control and Low-Power States ......................................................................9

2.1.1 Core Low-Power State Descriptions........................................................... 11

2.1.1.1 Core C0 State........................................................................... 11

2.1.1.2 Core C1/AutoHALT Powerdown State........................................... 11

2.1.1.3 Core C1/MWAIT Powerdown State............................................... 12

2.1.1.4 Core C2 State........................................................................... 12

2.1.1.5 Core C3 State........................................................................... 12

2.1.2 Package Low-Power State Descriptions...................................................... 12

2.1.2.1 Normal State............................................................................ 12

2.1.2.2 Stop-Grant State ...................................................................... 12

2.1.2.3 Stop-Grant Snoop State............................................................. 13

2.1.2.4 Sleep State.............................................................................. 13

FSB Low-Power Enhancements............................................................................ 14

Processor Power Status Indicator (PSI-2) Signal.................................................... 14

2.2

2.3

3

Electrical Specifications........................................................................................... 15

3.1

Power and Ground Pins ...................................................................................... 15

3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 15

Voltage Identification and Power Sequencing ........................................................ 15

Catastrophic Thermal Protection.......................................................................... 18

Reserved and Unused Pins.................................................................................. 19

FSB Frequency Select Signals (BSEL[2:0])............................................................ 19

FSB Signal Groups............................................................................................. 19

CMOS Signals ................................................................................................... 21

Maximum Ratings.............................................................................................. 21

Processor DC Specifications ................................................................................ 22

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4

5

Package Mechanical Specifications and Pin Information.......................................... 28

4.1

4.2

4.3

Package Mechanical Specifications....................................................................... 28

Processor Pinout and Pin List .............................................................................. 30

Alphabetical Signals Reference............................................................................ 47

Thermal Specifications and Design Considerations .................................................. 56

5.1

Monitoring Die Temperature ............................................................................... 57

5.1.1 Thermal Diode ....................................................................................... 57

5.1.2 Intel® Thermal Monitor........................................................................... 58

5.1.3 Digital Thermal Sensor............................................................................ 60

Out of Specification Detection ............................................................................. 61

PROCHOT# Signal Pin........................................................................................ 61

5.2

5.3

Datasheet

3

Figures

1

2

3

4

5

6

7

8

Core Low-Power States .............................................................................................10

Package Low-Power States ........................................................................................11

Active VCC and ICC Loadline......................................................................................25

Processor (ULV SC) Die Micro-FCBGA Processor Package Drawing ...................................29

Processor Top View Upper Left Side ............................................................................30

Procssor Top View Upper Right Side............................................................................31

Processor Top View Lower Left Side ............................................................................32

Processor Top View Lower Right Side ..........................................................................33

Tables

1

2

3

4

5

6

Coordination of Core Low-Power States at the Package Level..........................................11

Voltage Identification Definition..................................................................................16

BSEL[2:0] Encoding for BCLK Frequency......................................................................19

FSB Pin Groups ........................................................................................................20

Processor Absolute Maximum Ratings..........................................................................22

Voltage and Current Specifications for the Single-Core, Ultra Low Voltage (ULV, 10 W)

Processor ................................................................................................................23

Voltage and Current Specifications for the Single-Core Ultra Low Voltage (ULV, 5.5 W)

Processors...............................................................................................................24

FSB Differential BCLK Specifications............................................................................25

AGTL+ Signal Group DC Specifications ........................................................................26

7

8

9

10 CMOS Signal Group DC Specifications..........................................................................27

11 Open Drain Signal Group DC Specifications ..................................................................27

12 Signal Listing by Ball Number.....................................................................................34

13 Signal Description.....................................................................................................47

14 Power Specifications for the Single-Core Ultra Low Voltage Processors (ULV, 10 W)...........56

15 Power Specifications for the Single-Core Ultra Low Voltage (ULV, 5.5 W) Processors..........57

16 Thermal Diode Interface............................................................................................58

17 Thermal Diode Parameters Using Transistor Model ........................................................58

4

Datasheet

Revision History

Document Revision

Description

Date

Number

320389

001

Initial Release

August 2008

Table 6: Added specs for 743

Table 14: Added specs for 743

September

2009

320389

002

003

Added 900 series specifications

February 2010

Datasheet

5

Introduction

1 Introduction

The Intel® Celeron® processor on 45-nanometer process technology in the Intel®

Centrino® 2 process technology is the next generation high-performance, low-power

mobile processor based on the Intel Core microarchitecture.

In the Centrino 2 process technology platform, the Celeron processor supports the

Mobile Intel® 4 Series Express Chipset family and Intel® ICH9M I/O controller. This

document contains electrical, mechanical and thermal specifications for:

• Dual-Core and Single-Core Standard Voltage (35W TDP)

In the Montevina SFF platform, the Celeron processor supports the Mobile SFF Intel 4

Series Express Chipset family and Intel® ICH9M SFF I/O controller. This document also

contains electrical, mechanical and thermal specifications for:

• Single-Core SFF Ultra-Low Voltage (10W TDP)

• Single-Core SFF Ultra-Low Voltage (5.5W TDP)

In this document, Intel® Celeron® processor on 45-nm process will be referred to as

the processor and Mobile Intel® 4 Series Express Chipset family will be referred to as

the (G)MCH.

The following list provides some of the key features on this processor:

• Dual-core and single core processors for mobile with enhanced performance

• Supports Intel® architecture with Intel® Wide Dynamic Execution

• Supports L1 cache-to-cache (C2C) transfer

• On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each

core

• 1-MB second-level shared cache with Advanced Transfer Cache architecture

• 800-MHz source-synchronous front side bus (FSB)

• Digital thermal sensor (DTS)

• Intel® 64 architecture

• Supports PSI2 functionality

• The processor in SV is offered in 478-pin Micro-FCPGA and 479-ball Micro-FCBGA¹

packaging technologies

• The SFF processor in LV and ULV are offered in 956-ball Micro-FCBGA packaging

technologies only

• Execute Disable Bit support for enhanced security

•

1. Micro-FCBGA in standard package available for Embedded only.

6

Datasheet

Introduction

1.1

Terminology

Term

Definition

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

#

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+

signaling technology on some Intel processors.

AGTL+

Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor landings should not

be connected to any supply voltages, have any I/Os biased or receive any

clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device

removed from packaging material) the processor must be handled in

accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

Storage

Conditions

Processor core die with integrated L1 and L2 cache. All AC timing and signal

integrity specifications are at the pads of the processor core.

Processor Core

Intel® 64

Technology

64-bit memory extensions to the IA-32 architecture.

TDP

V_CC

V_SS

Thermal Design Power

The processor core power supply

The processor ground

Datasheet

7

Introduction

1.2

References

The following documents may be beneficial when reading this document.

Document

Number¹

Document

Intel® Core™2 Duo Mobile Processor and Intel® Core 2 Extreme Mobile

Processor Specification Update

377039

Mobile Intel® 4 Series Express Chipset Family Datasheet

320122

320123

605214

Mobile Intel® 4 Series Express Chipset Family Graphics Memory

Controller Hub Specification Update

Intel® I/O Controller Hub 9 Family Specification Update

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

8

Datasheet

Low Power Features

2 Low Power Features

2.1

Clock Control and Low-Power States

The processor supports low-power states both at the individual core level and the

package level for optimal power management.

A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3. When both cores

coincide in a common core low-power state, the central power management logic

ensures the entire processor enters the respective package low-power state by

initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the (G)MCH.

The processor implements two software interfaces for requesting low-power states:

MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK

register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are

converted to equivalent MWAIT C-state requests inside the processor and do not

directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does

not need to be set up before using the P_LVLx I/O read interface. The sub-state hints

used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model

specific register (MSR).

If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the

PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system

logic that individual cores should return to the C0 state and the processor should return

to the Normal state.

Figure 1 shows the core low-power states and Figure 2 shows the package low-power

states for the processor. Table 1 maps the core low-power states to package low-power

states.

Datasheet

9

Low Power Features

Figure 1.

Core Low-Power States

Stop

Grant

STPCLK#

asserted

STPCLK#

deasserted

STPCLK#

deasserted

STPCLK#

asserted

STPCLK#

deasserted

STPCLK#

asserted

C1/Auto

Halt

C1/MWAIT

Core state

break

HLT instruction

MWAIT(C1)

Halt break

C0

P_LVL2 or

MWAIT(C2)

Core

state

break

Core state

break

C2^†

P_LVL3 or

MWAIT(C3)

C3^†

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3.

10

Datasheet

Low Power Features

Figure 2.

Package Low-Power States

SLP# asserted

DPSLP# asserted

STPCLK# asserted

Stop

Grant

Deep

Sleep

Normal

Sleep

STPCLK# deasserted

SLP# deasserted

DPSLP# deasserted

Snoop Snoop

serviced occurs

Stop Grant

Snoop

Table 1.

Coordination of Core Low-Power States at the Package Level

Package State

Core0 State

Core1 State

C0

C1¹

C2

C3

C0

C1¹

C2

Normal

Stop-Grant

Deep Sleep

C3

NOTE:

1.

AutoHALT or MWAIT/C1.

2.1.1

Core Low-Power State Descriptions

2.1.1.1

Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2

Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when a core executes the HALT instruction.

The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,

LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to

immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal

state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures

Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more

information.

The system can generate a STPCLK# while the processor is in the AutoHALT

Powerdown state. When the system deasserts the STPCLK# interrupt, the processor

will return execution to the HALT state.

Datasheet

11

Low Power Features

While in AutoHALT Powerdown state, the dual-core processor will process bus snoops

and snoops from the other core. The processor core will enter a snoopable sub-state

(not shown in Figure 1) to process the snoop and then return to the AutoHALT

Powerdown state.

2.1.1.3

2.1.1.4

Core C1/MWAIT Powerdown State

C1/MWAIT is a low-power state entered when the processor core executes the

MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the

AutoHALT state except that Monitor events can cause the processor core to return to

the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,

Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference,

N-Z, for more information.

Core C2 State

Individual cores of the dual-core processor can enter the C2 state by initiating a P_LVL2

I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a

Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

While in the C2 state, the dual-core processor will process bus snoops and snoops from

the other core. The processor core will enter a snoopable sub-state (not shown in

Figure 1) to process the snoop and then return to the C2 state.

2.1.1.5

Core C3 State

Individual cores of the dual-core processor can enter the C3 state by initiating a P_LVL3

I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor

core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the

caches, the processor core maintains all its architectural states in the C3 state. The

Monitor remains armed if it is configured. All of the clocks in the processor core are

stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state

when the processor detects a snoop on the FSB or when the other core of the dual-core

processor accesses cacheable memory. The processor core will transition to the C0

state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB

interrupt message. RESET# will cause the processor core to immediately initialize itself.

2.1.2

Package Low-Power State Descriptions

2.1.2.1

Normal State

This is the normal operating state for the processor. The processor remains in the

Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT

state.

2.1.2.2

Stop-Grant State

When the STPCLK# pin is asserted, each core of the dual-core processor enters the

Stop-Grant state within 20 bus clocks after the response phase of the processor-issued

Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2,

C3 state remain in their current low-power state. When the STPCLK# pin is deasserted,

each core returns to its previous core low-power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be

driven (allowing the level to return to V_CCP) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the FSB should be

driven to the inactive state.

12

Datasheet

Low Power Features

RESET# causes the processor to immediately initialize itself, but the processor will stay

in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#,

DPSLP# pins must be deasserted prior to RESET# deassertion as per AC Specification

T45. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be

deasserted after the deassertion of SLP# as per AC Specification T75.

While in Stop-Grant state, the processor will service snoops and latch interrupts

delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts

and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be

asserted if there is any pending interrupt or Monitor event latched within the processor.

Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause

assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor

should return to the Normal state.

A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop

on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)

occurs with the assertion of the SLP# signal.

2.1.2.3

2.1.2.4

Stop-Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor will stay in this

state until the snoop on the FSB has been serviced (whether by the processor or

another agent on the FSB) or the interrupt has been latched. The processor returns to

the Stop-Grant state once the snoop has been serviced or the interrupt has been

latched.

Sleep State

The Sleep state is a low-power state in which the processor maintains its context,

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#

pin should only be asserted when the processor is in the Stop-Grant state. SLP#

assertions while the processor is not in the Stop-Grant state is out of specification and

may result in unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep

state. Snoop events that occur while in Sleep state or during a transition into or out of

Sleep state will cause unpredictable behavior. Any transition on an input signal before

the processor has returned to the Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as

specified in the RESET# pin specification, then the processor will reset itself, ignoring

the transition through the Stop-Grant state. If RESET# is driven active while the

processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted

immediately after RESET# is asserted to ensure the processor correctly executes the

Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power

state, the Deep Sleep state, by asserting the DPSLP# pin. While the processor is in the

Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event

needs to occur.

Datasheet

13

Low Power Features

2.2

FSB Low-Power Enhancements

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On-Die Termination disabling

• Low V_CCP(I/O termination voltage)

The processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates

them only when data bus activity occurs, resulting in significant power savings with no

performance impact. BPRI# control also allows the processor address and control input

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows

a reciprocal power reduction in GMCH address and control input buffers when the

processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers

is disabled when the signals are driven low, resulting in additional power savings. The

low I/O termination voltage is on a dedicated voltage plane independent of the core

voltage, enabling low I/O switching power at all times.

2.3

Processor Power Status Indicator (PSI-2) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a

reduced power consumption state. PSI# can be used to improve intermediate and light

load efficiency of the voltage regulator, resulting in platform power savings and

extended battery life. Since the processor is single core, the PSI-2 functionality will be

limited to the single core operational state.Additionally the voltage regulator may

switch to a single phase and/or asynchronous mode when the processor is idle and

fused leakage limit is less than or equal to the BIOS threshold value.

§

14

Datasheet

Electrical Specifications

3 Electrical Specifications

3.1

Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of V_CC

(power) and V_SS(ground) inputs. All power pins must be connected to V_CCpower

planes while all V_SSpins must be connected to system ground planes. Use of multiple

power and ground planes is recommended to reduce I*R drop. Refer to the platform

design guides for more details. The processor V_CCpins must be supplied the voltage

determined by the VID (Voltage ID) pins.

3.1.1

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous-generation processors, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor uses a differential clocking

implementation.

3.2

Voltage Identification and Power Sequencing

The processor uses seven voltage identification pins,VID[6:0], to support automatic

selection of power supply voltages. The VID pins for the processor are CMOS outputs

driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding

to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to

a low-voltage level.

Datasheet

15

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 1 of 3)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

16

Datasheet

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 2 of 3)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

Datasheet

17

Electrical Specifications

Table 2.

Voltage Identification Definition (Sheet 3 of 3)

VID6

VID5

VID4

VID3

VID2

VID1

VID0

V_CC(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

0.0000

3.3

Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An

external thermal sensor should also be used to protect the processor and the system

against excessive temperatures. Even with the activation of THERMTRIP#, which halts

all processor internal clocks and activity, leakage current can be high enough that the

processor cannot be protected in all conditions without the removal of power to the

processor. If the external thermal sensor detects a catastrophic processor temperature

of 125 °C (maximum), or if the THERMTRIP# signal is asserted, the V_CCsupply to the

processor must be turned off within 500 ms to prevent permanent silicon damage due

to thermal runaway of the processor. THERMTRIP# functionality is not ensured if the

PWRGOOD signal is not asserted.

18

Datasheet

Electrical Specifications

3.4

Reserved and Unused Pins

All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V_CC,

V_SS, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Section 4.2 for a pin listing of the

processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. Unused active low AGTL+ inputs may be left as no-connects if

AGTL+ termination is provided on the processor silicon. Unused active high inputs

should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected.

The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6 pins are used for test purposes internally

and can be left as “No Connects”.

Note:

There is no TEST7 pin on the processor.

3.5

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate

chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.

Table 3.

BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]

BSEL[1] BSEL[0] BCLK Frequency

L

H

L

RESERVED

200 MHz

L

H

L

H

L

RESERVED

H

L

3.6

FSB Signal Groups

The FSB signals have been combined into groups by buffer type in the following

sections. AGTL+ input signals have differential input buffers that use GTLREF as a

reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input

group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers

to the AGTL+ output group as well as the AGTL+ I/O group when driving.

Datasheet

19

Electrical Specifications

With the implementation of a source-synchronous data bus, two sets of timing

parameters need to be specified. One set is for common clock signals, which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second

set is for the source-synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 4 identifies which signals are common clock, source synchronous,

and asynchronous.

Table 4.

FSB Pin Groups

Signal Group

Type

Signals¹

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, PREQ#⁵, RESET#, RS[2:0]#,

TRDY#

AGTL+ Common Clock Input

AGTL+ Common Clock I/O

Synchronous to

BCLK[1:0]

ADS#, BNR#, BPM[3:0]#³, BR0#, DBSY#,

DRDY#, HIT#, HITM#, LOCK#, PRDY#³, DPWR#

Signals

Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]#

A[35:17]#

ADSTB[1]#

AGTL+ Source Synchronous

I/O

Synchronous to assoc.

strobe

D[15:0]#, DINV0#

D[31:16]#, DINV1#

D[47:32]#, DINV2#

D[63:48]#, DINV3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

Synchronous to

BCLK[1:0]

AGTL+ Strobes

CMOS Input

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#,

STPCLK#

Asynchronous

Open Drain Output

Open Drain I/O

CMOS Output

CMOS Input

Asynchronous

Synchronous to TCK

Clock

FERR#, IERR#, THERMTRIP#

PROCHOT#⁴

PSI#, VID[6:0], BSEL[2:0]

TCK, TDI, TMS, TRST#

TDO

Open Drain Output

FSB Clock

BCLK[1:0]

COMP[3:0], DBR#², GTLREF, RSVD, TEST2, TEST1,

Power/Other

THERMDA, THERMDC, V_CC, V_CCA, V_CCP, V_{CC_SENSE}

,

V

_SS, V_{SS_SENSE}

NOTES:

1.

2.

Refer to Chapter 4 for signal descriptions and termination requirements.

In processor systems where there is no debug port implemented on the system board, these signals are

used to support a debug port interposer. In systems with the debug port implemented on the system

board, these signals are no connects.

3.

4.

5.

BPM[2:1]# and PRDY# are AGTL+ output-only signals.

PROCHOT# signal type is open drain output and CMOS input.

On-die termination differs from other AGTL+ signals.

20

Datasheet

Electrical Specifications

3.7

3.8

CMOS Signals

CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non-

AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These

signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,

all of the CMOS signals are required to be asserted for more than four BCLKs for the

processor to recognize them. See Section 3.9 for the DC and AC specifications for the

CMOS signal groups.

Maximum Ratings

Table 5 specifies absolute maximum and minimum ratings only and these lie outside

the functional limits of the processor. Within functional operation limits, functionality

and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions outside these limits but within the

absolute maximum and minimum ratings, the device may be functional but with its

lifetime degraded, depending on exposure to conditions exceeding the functional

operation condition limits.

At conditions exceeding the absolute maximum and minimum ratings, neither

functionality nor long-term reliability can be expected. If a device is subjected to these

conditions for any length of time, the device may not function or may not be reliable

when returned to conditions within the functional operating condition limits.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Datasheet

21

Electrical Specifications

Table 5.

Processor Absolute Maximum Ratings

Parameter

Symbol

T_STORAGE

V_CC

Min

Max

Unit

Notes^1,5

Processor Storage Temperature

-40

-0.3

-0.1

85

°C

V

2,3,4,6

Any Processor Supply Voltage with Respect to V_SS

AGTL+ Buffer DC Input Voltage with Respect to V_SS

1.45

V_inAGTL+

V

V_{inAsynch_CMOS}CMOS Buffer DC Input Voltage with Respect to V_SS

V

NOTES:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must

be satisfied.

2.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not

receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect

the long-term reliability of the device. For functional operation, please refer to the processor case

temperature specifications.

3.

4.

5.

6.

This rating applies to the processor and does not include any tray or packaging.

Failure to adhere to this specification can affect the long-term reliability of the processor.

Overshoot and undershoot guidelines for input, output, and I/O signals are in Chapter 4.

The min T_STORAGEtemperature is -25 °C.

3.9

Processor DC Specifications

The processor DC specifications in this section are defined at the processor

core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and

signal pin assignments.

The tables in this section list the DC specifications for the processor and are valid only

while meeting specifications for junction temperature, clock frequency, and input

voltages. Active mode load line specifications apply in all states except in the Deep

Sleep states. V_CC,BOOTis the default voltage driven by the voltage regulator at power

up in order to set the VID values. Maximum Junction Temperature (T_J,max)values for

the processor are documented in Table 16 and Table 17. Read all notes associated with

each parameter.

22

Datasheet

Electrical Specifications

Table 6.

Symbol

Voltage and Current Specifications for the Single-Core Standard Voltage (SV)

Processors

Parameter

Min

Typ

Max

Unit

Notes

V_CC

0.8

—

1.25

—

V

A

1, 2

V_CC,BOOT

V_CCP

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.2

1.05

1.5

—

2, 6, 8

1.0

1.425

—

1.1

1.575

47

V_CCA

PLL Supply Voltage

I_CCDES

I_CCfor Processors Recommended Design Target

I_CCfor Processors

5, 12

—

Processor

I_CC

Core Frequency/Voltage

Number

—

47

900

2.2 GHz

A

3, 4

I_AH,

I_SGNT

I_CCAuto-Halt & Stop-Grant

25.4

I_SLP

I_CCSleep

—

24.7

22.9

A

3, 4

I_DPSLP

I_CCDeep Sleep

V_CCPower Supply Current Slew Rate at Processor

Package Pin

dI_CC/DT

I_CCA

—

600

130

mA/µs

mA

7, 9

I_CCfor V_CCASupply

10

11

I_CCCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

I_CCP

NOTES:.

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (e.g.

Enhanced Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

Specified at 105 °C T_J.

Specified at the nominal V_CC

Refer to the RS – Intel® Mobile Voltage Positioning (Intel® MVP) - 6 Mobile Processor and Mobile Chipset

Voltage Regulation Specification for design target capability.

.

6.

7.

8.

9.

Refer to Figure 14 for a waveform illustration of this parameter.

Measured at the bulk capacitors on the motherboard.

V

_CC,BOOTtolerance shown in Figure 3.

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

10.

11.

12.

This is a power-up peak current specification that is applicable when V_CCPis high and V_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification that is applicable when both V_CCPand V_{CC_CORE}are high.

Average current will be less than maximum specified I_CCDES. VR OCP threshold should be high enough to

support current levels described herein.

Datasheet

23

Electrical Specifications

Table 7.

Symbol

Voltage and Current Specifications for the Single-Core, Ultra Low Voltage

(ULV, 10 W) Processor

Parameter

Min

Typ

Max

Unit

Notes

V_CC

0.775

—

1.20

1.05

1.5

—

1.1

—

V

A

1, 2

2, 5

V_CC,BOOT

V_CCP

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.00

1.425

—

1.10

1.575

18

V_CCA

PLL Supply Voltage

I_CCDES

I_CCfor Processors Recommended Design Target

10

Processor

Core Frequency/Voltage

Number

—

I_CC

723

743

1.2 GHz

1.3 GHz

17.6

A

3, 4

I_AH,

I_SGNT

I_CCAuto-Halt & Stop-Grant

—

6.3

A

3, 4

I_SLP

I_CCSleep

—

5.9

5.0

A

3, 4

I_DPSLP

I_CCDeep Sleep

V_CCPower Supply Current Slew Rate at Processor

Package Pin

dI_CC/DT

I_CCA

—

600

130

mA/µs

mA

5, 7

I_CCfor V_CCASupply

8

9

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

I_CCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (e.g.,

Enhanced Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

6.

7.

Specified at 100 °C T_J.

Specified at the nominal V_CC

Measured at the bulk capacitors on the motherboard.

_CC,BOOTtolerance shown in Figure 3.

.

V

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

8.

9.

10.

This is a power-up peak current specification that is applicable when V_CCPis high and V_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification that is applicable when both V_CCPand V_{CC_CORE}are high.

Average current will be less than maximum specified I_CCDES. VR OCP threshold should be high enough to

support current levels.

24

Datasheet

Electrical Specifications

Table 8.

Symbol

Voltage and Current Specifications for the Single-Core Ultra Low Voltage (ULV,

5.5 W) Processors

Parameter

Min

Typ

Max

Unit

Notes

V_CC

0.775

—

1.20

1.05

1.5

—

1.1

—

V

A

1, 2

2, 5

V_CC,BOOT

V_CCP

Default V_CCVoltage for Initial Power Up

AGTL+ Termination Voltage

1.00

1.425

—

1.10

1.575

9

V_CCA

PLL Supply Voltage

I_CCDES

I_CCfor Processors Recommended Design Target

10

Processor

Core Frequency/Voltage

Number

—

9

I_CC

722

1.2 GHz

A

3, 4

I_AH,

I_SGNT

I_CCAuto-Halt & Stop-Grant

4.4

I_SLP

I_CCSleep

—

4.1

3.3

A

3, 4

I_DPSLP

I_CCDeep Sleep

V_CCPower Supply Current Slew Rate at Processor

Package Pin

dI_CC/DT

I_CCA

—

600

130

mA/µs

mA

5, 7

I_CCfor V_CCASupply

8

9

I_CCfor V_CCPSupply before V_CCStable

I_CCfor V_CCPSupply after V_CCStable

4.5

2.5

A

I_CCP

NOTES:

1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. Note

that this differs from the VID employed by the processor during a power management event (e.g.

Enhanced Halt State).

2.

The voltage specifications are assumed to be measured across V_{CC_SENSE}and V_{SS_SENSE}pins at socket with

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from

the system is not coupled in the scope probe.

3.

4.

5.

6.

7.

Specified at 100 °C T_J.

Specified at the nominal V_CC

Measured at the bulk capacitors on the motherboard.

_CC,BOOTtolerance shown in Figure 3.

.

V

Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

8.

9.

10.

This is a power-up peak current specification that is applicable when V_CCPis high and V_{CC_CORE}is low.

This is a steady-state I_CCcurrent specification that is applicable when both V_CCPand V_{CC_CORE}are high.

Average current will be less than maximum specified I_CCDES. VR OCP threshold should be high enough to

support current levels.

Datasheet

25

Electrical Specifications

Figure 3.

Active V_CCand I_CCLoadline

V_CC-CORE[V]

Slope = -4.0 mV/A at package

VccSense, VssSense pins.

Differential Remote Sense required.

V

_CC-COREmax

_{CC-CORE, DC}ma

V_CC-COREnom

V

10mV= RIPPLE

V_{CC-CORE, DC}min

V_CC-COREmin

+/-V_CC-CORETolerance

= VR St. Pt. Error 1/

I_CC-CORE

[A]

0

I_CC-COREmax

Note 1/ V_CC-CORESet Point Error Tolerance is per below:

Tolerance V_CC-COREVID Voltage Range

--------------- --------------------------------------------------------

+/-1.5%

+/-11.5mV

+/-25mV

V_CC-CORE> 0.7500V

0.5000V </= V_CC-CORE</= 0.7500V

0.3000V </= V_CC-CORE< 0.5000V

NOTES:

1.

Applies to low-voltage, ultra low-voltage and low-power standard voltage 22-mm (dual-

core) processors for Intel® Centrino® processor technology.

Active mode tolerance depends on VID value.

2.

Table 9.

Symbol

FSB Differential BCLK Specifications

Parameter

Crossing Voltage

Min

Typ

Max

Unit

Notes¹

V_CROSS

ΔV_CROSS

V_SWING

I_LI

0.3

—

0.55

140

—

V

2, 7, 8

Range of Crossing Points

Differential Output Swing

Input Leakage Current

Pad Capacitance

mV

µA

pF

2, 7, 5

300

-5

—

6

3

4

—

+5

Cpad

0.95

1.2

1.45

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of

BCLK1.

3.

4.

5.

6.

7.

8.

For Vin between 0 V and V_IH.

Cpad includes die capacitance only. No package parasitics are included.

ΔV_CROSSis defined as the total variation of all crossing voltages as defined in note 2.

Measurement taken from differential waveform.

Measurement taken from single-ended waveform.

Only applies to the differential rising edge (Clock rising and Clock# falling).

26

Datasheet

Electrical Specifications

Table 10.

Symbol

AGTL+ Signal Group DC Specifications

Parameter

I/O Voltage

Min

Typ

Max

Unit

Notes¹

V_CCP

1.00

0.65

27.23

49

1.05

0.70

27.5

55

1.10

0.72

27.78

63

V

GTLREF

R_COMP

R_ODT/A

R_ODT/D

R_ODT/Cntrl

V_IH

Reference Voltage

6

10

Compensation Resistor

Termination Resistor Address

Termination Resistor Data

Termination Resistor Control

Input High Voltage

Ω

V

11, 12

11, 13

11, 14

3,6

49

55

63

49

55

63

0.82

-0.10

0.90

50

1.05

0

1.20

0.55

1.10

61

V_IL

Input Low Voltage

V

2,4

V_OH

Output High Voltage

V_CCP

55

V

6

R_TT/A

Termination Resistance Address

Termination Resistance Data

Termination Resistance Control

Buffer on Resistance Address

Buffer on Resistance Data

Buffer on Resistance Control

Input Leakage Current

Pad Capacitance

Ω

µA

pF

7, 12

7, 13

7, 14

5, 12

5, 13

5, 14

8

R_TT/D

R_TT/Cntrl

R_ON/A

R_ON/D

R_ON/Cntrl

I_LI

50

55

61

50

55

61

23

25

29

23

25

29

23

25

29

—

±100

2.75

Cpad

1.80

2.30

9

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

_ILis defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

value.

_IHis defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

_IHand V_OHmay experience excursions above V_CCP. However, input signal drivers must comply with the

signal quality specifications.

This is the pulldown driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.

Measured at 0.31*V_CCP. R_ON(min) = 0.418*R_TT, R_ON(typ) = 0.455*R_TT,

V

3.

4.

5.

V

R

_ON(max) = 0.527*R_TT. R_TTtypical value of 55 Ω is used for R_ONtyp/min/max calculations.

GTLREF should be generated from V_CCPwith a 1% tolerance resistor divider. The V_CCPreferred to in these

specifications is the instantaneous V_CCP

_TTis the on-die termination resistance measured at V_OLof the AGTL+ output driver. Measured at

0.31*V_CCP. R_TTis connected to V_CCPon die. Refer to processor I/O buffer models for I/V characteristics.

Specified with on-die R_TTand R_ONturned off. Vin between 0 and V_CCP

6.

7.

.

R

8.

.

9.

Cpad includes die capacitance only. No package parasitics are included.

This is the external resistor on the comp pins.

10.

11.

12.

13.

14.

On-die termination resistance, measured at 0.33*V_CCP

.

Applies to Signals A[35:3].

Applies to Signals D[63:0].

Applies to Signals BPRI#, DEFER#, PREQ#, PREST#, RS[2:0]#, TRDY#, ADS#, BNR#, BPM[3:0], BR0#,

DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#, DSTB[1:0]#, DSTBP[3:0] and DSTBN[3:0]#.

Datasheet

27

Electrical Specifications

Table 11.

Symbol

CMOS Signal Group DC Specifications

Parameter

Min

Typ

Max

Unit

Notes¹

V_CCP

V_IL

I/O Voltage

1.00

-0.10

0.7*V_CCP

-0.10

0.9*V_CCP

1.5

1.05

0.00

V_CCP

0

1.10

0.3*V_CCP

V_CCP+0.1

0.1*V_CCP

V_CCP+0.1

4.1

V

Input Low Voltage CMOS

Input High Voltage

2, 3

2

V_IH

V

V_OL

Output Low Voltage

V

2

V_OH

I_OL

Output High Voltage

Output Low Current

Output High Current

Input Leakage Current

Pad Capacitance

V_CCP

—

V

2

mA

µA

pF

4

I_OH

1.5

—

4.1

5

I_LI

—

±100

6

Cpad1

Cpad2

1.80

2.30

1.2

2.75

7

Pad Capacitance for CMOS Input

0.95

1.45

8

NOTES:

1.

2.

3.

4.

5.

6.

7.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V_CCPreferred to in these specifications refers to instantaneous V_CCP

Refer to the processor I/O Buffer Models for I/V characteristics.

Measured at 0.1 *V_CCP

Measured at 0.9 *V_CCP

For Vin between 0 V and V_CCP. Measured when the driver is tristated.

.

Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are

included.

8.

Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.

Table 12.

Symbol

Open Drain Signal Group DC Specifications

Parameter

Output High Voltage

Min

Typ

Max

Unit

Notes¹

V_OH

V_OL

I_OL

V_CCP–5%

V_CCP

—

V_CCP+5%

0.20

V

3

Output Low Voltage

Output Low Current

Output Leakage Current

Pad Capacitance

0

16

—

50

mA

µA

pF

2

4

5

I_LO

—

±200

2.75

Cpad

1.80

2.30

NOTES:

1.

2.

3.

4.

5.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at 0.2 V.

V

_OHis determined by value of the external pull-up resistor to V_CCP

.

For Vin between 0 V and V_OH

.

Cpad includes die capacitance only. No package parasitics are included.

§

28

Datasheet

Package Mechanical Specifications and Pin Information

4 Package Mechanical

Specifications and Pin

Information

4.1

Package Mechanical Specifications

The SV processor is available in 478-pin Micro-FCPGA packages as well as 479-ball

Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 4

through Figure 8.

The ULV processor is available 956-ball Micro-FCBGA packages. The package

mechanical dimensions are shown in Figure 8.

The mechanical package pressure specifications are in a direction normal to the surface

of the processor. This requirement is to protect the processor die from fracture risk due

to uneven die pressure distribution under tilt, stack-up tolerances and other similar

conditions. These specifications assume that a mechanical attach is designed

specifically to load one type of processor.

Intel also specifies that 15-lbf load limit should not be exceeded on any of Intel’s BGA

packages so as to not impact solder joint reliability after reflow. This load limit ensures

that impact to the package solder joints due to transient bend, shock, or tensile loading

is minimized. The 15-lbf metric should be used in parallel with the 689-kPa (100 psi)

pressure limit as long as neither limits are exceeded. In some cases, designing to 15 lbf

will exceed the pressure specification of 689 kPa (100 psi) and therefore should be

reduced to ensure both limits are maintained.

Moreover, the processor package substrate should not be used as a mechanical

reference or load-bearing surface for the thermal or mechanical solution.

Caution:

The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors

are electrically conductive so care should be taken to avoid contacting the capacitors

with other electrically conductive materials on the motherboard. Doing so may short

the capacitors and possibly damage the device or render it inactive.

Datasheet

29

Package Mechanical Specifications and Pin Information

Figure 4.

1-MB on 6-MB Die (SV) Micro-FCPGA Package Drawing (Sheet 1 of 2)

h

30

Datasheet

Package Mechanical Specifications and Pin Information

Figure 5.

1-MB on 6-MB Die (SV) Micro-FCPGA Package Drawing (Sheet 2 of 2)

Datasheet

31

Package Mechanical Specifications and Pin Information

Figure 6.

1-MB on 6-MB Die (SV) Micro-FCBGA Package Drawing (Sheet 1 of 2)

32

Datasheet

Package Mechanical Specifications and Pin Information

Figure 7.

1-MB on 6-MB Die (SV) Micro-FCBGA Package Drawing (Sheet 2 of 2)

33

Datasheet

Package Mechanical Specifications and Pin Information

Figure 8.

Processor (ULV SC) Die Micro-FCBGA Processor Package Drawing

34

Datasheet

Package Mechanical Specifications and Pin Information

4.2

Processor Pinout and Pin List

Figure 9 and Figure 10 show the

processor (SV) pinout as viewed from the

top of the package. Table 14 provides the

pin list, arranged numerically by pin

number.

Figure 11 through Figure 14 show the top

view of the (ULV) processor package.

Table 13 lists the processor ballout

alphabetically by signal name. For signal

descriptions, refer to Section 4.3.

Figure 9.

Penryn Processor Pinout (Top Package View, Left Side)

1

2

3

4

5

6

7

8

9

10

11

12

13

1

A

VSS

RSVD

SMI#

INIT#

VSS

FERR#

DPSLP#

A20M#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

A

B

2

B

LINT1

IGNNE

#

THERM

TRIP#

C

D

E

RESET#

VSS

TEST7

RSVD

VSS

LINT0

VSS

VCC

VSS

VCC

VSS

C

D

E

STPCLK

#

PWRGO

OD

RSVD

BNR#

VSS

SLP#

DPRSTP

#

DBSY#

HITM#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

F

BR0#

VSS

RS[0]#

RS[2]#

RS[1]#

VSS

RSVD

HIT#

F

G

TRDY#

BPRI#

G

REQ[1]

#

H

J

ADS#

A[9]#

VSS

LOCK#

A[3]#

DEFER#

VSS

H

J

REQ[3]

#

VSS

VCCP

REQ[2]

#

REQ[0]

#

K

L

VSS

A[6]#

A[4]#

VSS

VCCP

VSS

K

L

REQ[4]#

A[13]#

VSS

A[5]#

RSVD

ADSTB[0]

#

M

A[7]#

VCCP

M

N

P

R

T

VSS

A[8]#

A[12]#

VSS

A[10]#

VSS

RSVD

A[11]#

VSS

VCCP

VSS

N

P

R

T

A[15]#

A[16]#

VSS

A[14]#

A[24]#

VSS

A[19]#

A[26]#

VSS

VCCP

VSS

RSVD

A[25]#

A[18]#

U

A[23]#

A[30]#

A[21]#

U

ADSTB[1]

#

V

VSS

RSVD

A[31]#

VSS

VCCP

V

W

Y

VSS

A[27]#

A[17]#

A[32]#

VSS

A[28]#

A[22]#

A[20]#

VSS

W

Y

COMP[3]

A[29]#

A

AA

AB

AC

AD

AE

AF

COMP[2]

VSS

A[34]#

PRDY#

VSS

A[35]#

TDO

A[33]#

VSS

TMS

TDI

TRST#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

A

B

BPM[3]

#

A

C

PREQ#

BPM[2]#

VSS

TCK

BPM[1]

#

BPM[0]

#

A

D

VSS

VID[0]

PSI#

VSS

SENSE

A

E

VID[6]

VID[4]

VSS

VID[2]

VCC

SENSE

A

F

TEST5

VSS

VID[5]

VID[3]

VID[1]

VSS

VCC

VSS

VCC

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

1. Keying option for uFCPGA, A1 and B1 are de-populated.

2. Keying option for uFCBGA, A1 is de-populated and B1 is VSS.

35

Datasheet

Package Mechanical Specifications and Pin Information

Figure 10.

Processor Pinout (Top Package View, Right Side)

14

15

16

17

18

19

20

21

22

23

24

THRMDA

VSS

25

VSS

26

A

B

C

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BCLK[1]

VSS

BCLK[0]

BSEL[0]

VSS

TEST6

VCCA

A

B

C

VCC

BSEL[1]

TEST1

THRMDC

VSS

DBR#

BSEL[2]

TEST3

PROCHOT

#

D

VCC

VSS

VCC

VSS

IERR#

RSVD

VSS

DPWR#

TEST2

VSS

D

E

F

VSS

VCC

VSS

VCC

VSS

VCC

VSS

DRDY#

VCCP

D[0]#

VSS

D[7]#

D[4]#

VSS

D[6]#

VSS

D[2]#

D[13]#

VSS

E

F

D[1]#

D[9]#

G

D[3]#

D[5]#

G

DSTBP[

0]#

H

VSS

D[12]#

D[15]#

VSS

DINV[0]#

H

DSTBN[

0]#

J

K

L

VCCP

VSS

D[11]#

VSS

D[10]#

D[8]#

VSS

J

K

L

D[14]#

D[22]#

D[17]#

D[29]#

VSS

DSTBN[

1]#

D[20]#

DSTBP[

1]#

M

VCCP

VSS

D[23]#

D[21]#

VSS

M

N

P

VCCP

VSS

D[16]#

D[26]#

VSS

DINV[1]#

VSS

D[31]#

D[24]#

VSS

N

P

D[25]#

D[18]#

COMP[0

]

R

T

VCCP

VSS

D[19]#

VSS

D[28]#

D[27]#

VSS

R

T

D[37]#

DINV[2]#

D[30]#

D[38]#

VSS

COMP[1

]

U

D[39]#

U

V

VCCP

VSS

D[36]#

VSS

D[34]#

D[43]#

VSS

D[35]#

VSS

V

W

D[41]#

D[44]#

W

DSTBN[

2]#

Y

VSS

D[32]#

VSS

D[42]#

D[45]#

VSS

D[40]#

VSS

Y

DSTBP[

2]#

A

AA

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

D[50]#

D[46]#

A

B

AB

AC

D[52]#

VSS

D[51]#

D[60]#

VSS

D[63]#

D[61]#

VSS

D[33]#

VSS

D[47]#

D[57]#

VSS

D[53]#

GTLREF

VSS

DINV[3

]#

A

C

A

D

A

D

D[54]#

VCC

D[59]#

D[58]#

D[49]#

D[48]#

DSTBN[3]

#

A

E

AE

AF

D[55]#

DSTBP[3]

#

A

F

VCC

VSS

VCC

VSS

VCC

VSS

D[62]#

D[56]#

VSS

TEST4

14

15

16

17

18

19

20

21

22

23

24

25

26

Datasheet

36

Package Mechanical Specifications and Pin Information

Figure 11.

Processor Top View Upper Left Side

BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC

COMP[

2]

VSS

TMS

TDI

TDO

A[35]#

A[17]#

A[31]#

A[30]#

A[19]#

A[16]#

1

BPM[3]

#

COMP[

3]

VSS

VID[5]

VSS

PREQ#

TCK

A[22]#

A[20]#

VSS

A[34]#

A[28]#

VSS

A[32]#

A[27]#

VSS

A[21]#

A[18]#

VSS

A[23]#

A[26]#

VSS

A[11]#

A[12]#

VSS

2

VSS

VID[4]

VID[1]

VSS

3

VSS

VID[6]

VSS

A[24]#

VSS

4

BPM[2]

#

ADSTB

[1]#

RSVD0

4

RSVD0

3

A[33]#

VSS

A[29]#

VCCP

VSS

A[25]#

VCCP

VSS

A[14]#

VCCP

VSS

A[10]#

VCCP

VSS

5

VSS

6

BPM[1]

#

VCCP

VSS

VCCP

VSS

VCCP

VSS

7

BPM[0]

#

VID[0]

PSI#

VID[3]

VID[2]

VSS

TRST#

PRDY#

VSS

8

VSS

9

TEST5

VSS

VCCP

VCC

VSS

VCCP

VCC

VSS

VCCP

VCC

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

VSS

VCCP

VSS

VCCS

ENSE

VSS

VSSSE

NSE

VCC

VCCP

VCC

VCCP

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

37

Datasheet

Package Mechanical Specifications and Pin Information

Figure 12.

Processor Top View Upper Right Side

AB AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

REQ[2]

#

REQ[0]

#

A[7]#

A[5]#

LOCK#

TRDY#

DBSY#

VSS

1

RSVD0

2

RSVD0

1

A[15]#

VSS

A[9]#

A[3]#

BR0#

RS[0]#

HIT#

HITM#

VSS

2

VSS

BPRI#

VCCP

VSS

BNR#

DBR#

VSS

LINT1

A20M#

LINT0

VSS

3

ADSTB

[0]#

REQ[3]

#

RSVD0

6

A[8]#

A[13]#

VSS

A[4]#

VSS

A[6]#

VSS

VCCP

VCC

ADS#

VSS

VCCP

VCC

RS[2]#

VSS

RS[1]#

VSS

FERR#

VSS

4

REQ[4]

#

REQ[1]

#

DEFER

#

RESET

#

SMI#

VSS

VCCP

VSS

5

VSS

VCCP

VCC

VSS

6

DPRST

P#

PWRG

OOD

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

7

RSVD0

7

STPCL

K#

DPSLP

#

VSS

INIT#

SLP#

VCCP

VCC

8

RSVD0

5

VCCP

VSS

VCCP

VSS

VCCP

VSS

9

THER

MTRIP

#

IGNNE

#

VCCP

VCC

VCCP

VCC

VCCP

VCC

VSS

VCCP

VCC

10

11

12

13

14

15

16

17

18

19

20

21

22

VCCP

VSS

VCCP

VCC

VCCP

VCC

VCCP

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Datasheet

38

Package Mechanical Specifications and Pin Information

Figure 13.

Processor Top View Lower Left Side

BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC

VSS

D[58]#

VSS

D[52]#

VSS

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

D[26]#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VCCP

VSS

VCC

VCCP

VSS

VCC

THRM

DC

THRM

DA

VSS

D[62]#

D[54]#

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

D[55]#

D[61]#

VSS

D[56]#

VSS

VCCP

D[45]#

VSS

VCCP

D[43]#

VSS

VCCP

D[35]#

VSS

DINV[3

]#

VSS

DSTBP

[3]#

D[48]#

D[50]#

VSS

D[59]#

VSS

DSTBN

[3]#

D[57]#

VSS

D[42]#

VSS

D[34]#

VSS

DINV[2

]#

D[60]#

VSS

D[51]#

D[63]#

D[53]#

D[33]#

D[46]#

D[41]#

D[47]#

D[37]#

D[44]#

TEST4

D[27]#

TEST6

VSS

GTLRE

F

DSTBP

[2]#

COMP[

0]

D[36]#

DSTBN

[2]#

COMP[

1]

VSS

D[49]#

D[32]#

D[40]#

D[39]#

D[38]#

39

Datasheet

Package Mechanical Specifications and Pin Information

Figure 14.

Processor Top View Lower Right Side

AB AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

VSS

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VCCP

VCCA

VSS

VCCP

VCCA

VSS

VCC

VCCP

VSS

VCC

VCCP

VSS

VCCP

TEST1

VSS

VCCP

VSS

VCCP

DRDY#

D[0]#

VSS

BCLK[

1]

BCLK[

0]

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

VSS

VCCP

D[17]#

VSS

VCCP

VSS

VCCP

VSS

BSEL[1

]

BSEL[0

]

PROC

HOT#

BSEL[2

]

VSS

D[6]#

D[13]#

D[1]#

VSS

DINV[0

]#

DSTBN

[0]#

D[25]#

D[24]#

VSS

D[29]#

VSS

D[11]#

VSS

D[12]#

VSS

D[4]#

VSS

TEST2

VSS

IERR#

VSS

DSTBP

[0]#

DPWR

#

D[21]#

D[23]#

D[20]#

D[10]#

D[22]#

D[8]#

D[15]#

D[7]#

D[2]#

VSS

DSTBP

[1]#

DSTBN

[1]#

DINV[1

]#

D[28]#

D[19]#

D[3]#

TEST3

D[30]#

D[18]#

D[31]#

D[16]#

D[14]#

D[9]#

D[5]#

VSS

Datasheet

40

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

BCLK[0]

A35

C35

J5

A[3]#

P2

V4

BCLK[1]

BNR#

A[4]#

A[5]#

W1

BPM[0]#

BPM[1]#

BPM[2]#

BPM[3]#

BPRI#

AY8

BA7

BA5

AY2

L5

A[6]#

T4

A[7]#

AA1

AB4

T2

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

A[33]#

A[34]#

A[35]#

A20M#

ADS#

AC5

AD2

AD4

AA5

AE5

AB2

AC1

AN1

AK4

AG1

AT4

AK2

AT2

AH2

AF4

AJ5

AH4

AM4

AP4

AR5

AJ1

AL1

AM2

AU5

AP2

AR1

C7

BR0#

M2

BSEL[0]

BSEL[1]

BSEL[2]

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

A37

C37

B38

AE43

AD44

AE1

AF2

F40

G43

E43

J43

D[1]#

D[2]#

D[3]#

D[4]#

H40

H44

G39

E41

L41

K44

N41

T40

M40

G41

M44

L43

P44

V40

V44

AB44

R41

D[5]#

D[6]#

D[7]#

D[8]#

D[9]#

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[20]#

M4

ADSTB[0]#

ADSTB[1]#

Y4

AN5

41

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

D[21]#

W41

N43

D[58]#

BC35

BC39

BA41

BB40

BA35

AU43

J7

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

D[29]#

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[59]#

D[60]#

U41

AA41

AB40

AD40

AC41

AA43

Y40

D[61]#

D[62]#

D[63]#

DBR#

DBSY#

J1

DEFER#

DINV[0]#

DINV[1]#

DINV[2]#

DINV[3]#

DPRSTP#

DPSLP#

DPWR#

DRDY#

N5

Y44

P40

R43

AJ41

BC37

G7

T44

AP44

AR43

AH40

AF40

AJ43

AG41

AF44

AH44

AM44

AN43

AM40

AK40

AG43

AP40

AN41

AL41

AV38

AT44

AV40

AU41

AW41

AR41

BA37

BB38

AY36

AT40

B8

C41

F38

K40

U43

AK44

AY40

J41

DSTBN[0]#

DSTBN[1]#

DSTBN[2]#

DSTBN[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

FERR#

W43

AL43

AY38

D4

GTLREF

AW43

H2

HIT#

HITM#

F2

IERR#

B40

F10

D8

IGNNE#

INIT#

LINT0

C9

LINT1

C5

LOCK#

N1

PRDY#

AV10

AV2

PREQ#

Datasheet

42

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

PROCHOT#

D38

BD10

E7

VCC

AA33

AB16

AB18

AB20

AB22

AB24

AB26

AB28

AB30

AB32

AC33

AD16

AD18

AD20

AD22

AD24

AD26

AD28

AD30

AD32

AE33

AF16

AF18

AF20

AF22

AF24

AF26

AF28

AF30

AF32

AG33

AH16

AH18

AH20

AH22

AH24

AH26

PSI#

PWRGOOD

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

RESET#

RS[0]#

RS[1]#

RS[2]#

RSVD01

RSVD02

RSVD03

RSVD04

RSVD05

RSVD06

RSVD07

SLP#

VCC

R1

R5

U1

P4

W5

G5

K2

H4

K4

V2

Y2

AG5

AL5

J9

F4

H8

D10

E5

SMI#

STPCLK#

TCK

F8

AV4

AW7

AU1

E37

D40

C43

AE41

AY10

AC43

B10

BB34

BD34

AW5

L1

TDI

TDO

TEST1

TEST2

TEST3

TEST4

TEST5

TEST6

THERMTRIP#

THRMDA

THRMDC

TMS

TRDY#

TRST#

AV8

43

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VCC

AH28

AH30

AH32

AJ33

VCC

AT16

AT18

AT20

AT22

AT24

AT26

AT28

AT30

AT32

AT34

AU33

AV14

AV16

AV18

AV20

AV22

AV24

AV26

AV28

AV30

AV32

AY14

AY16

AY18

AY20

AY22

AY24

AY26

AY28

AY30

AY32

B16

VCC

AK16

AK18

AK20

AK22

AK24

AK26

AK28

AK30

AK32

AL33

AM14

AM16

AM18

AM20

AM22

AM24

AM26

AM28

AM30

AM32

AN33

AP14

AP16

AP18

AP20

AP22

AP24

AP26

AP28

AP30

AP32

AR33

AT14

B18

B20

B22

B24

B26

Datasheet

44

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VCC

B28

B30

VCC

F30

F32

G33

H16

H18

H20

H22

H24

H26

H28

H30

H32

J33

VCC

BB14

BB16

BB18

BB20

BB22

BB24

BB26

BB28

BB30

BB32

BD14

BD16

BD18

BD20

BD22

BD24

BD26

BD28

BD30

BD32

D16

K16

K18

K20

K22

K24

K26

K28

K30

K32

L33

M16

M18

M20

M22

M24

M26

M28

M30

M32

N33

P16

P18

P20

P22

D18

D20

D22

D24

D26

D28

D30

F16

F18

F20

F22

F24

F26

F28

45

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VCC

P24

P26

P28

P30

P32

R33

T16

T18

T20

T22

T24

T26

T28

T30

T32

U33

V16

V18

V20

V22

V24

V26

V28

V30

V32

W33

Y16

Y18

Y20

Y22

Y24

Y26

Y28

Y30

Y32

B34

D34

VCCP

A13

A33

VCC

VCCA

VCCP

AA7

AA9

AA11

AA13

AA35

AA37

AB10

AB12

AB14

AB36

AB38

AC7

AC9

AC11

AC13

AC35

AC37

AD14

AE7

AE9

AE11

AE13

AE35

AE37

AF10

AF12

AF14

AF36

AF38

AG7

AG9

AG11

AG13

AG35

AG37

Datasheet

46

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VCCP

AH14

AJ7

VCCP

C13

C33

D12

D14

D32

E11

E13

E33

E35

F12

F14

F34

F36

G11

G13

G35

H12

H14

H36

J11

J13

J35

J37

K10

K12

K14

K36

K38

L7

VCCP

AJ9

AJ11

AJ13

AJ35

AJ37

AK10

AK12

AK14

AK36

AK38

AL7

AL9

AL11

AL13

AL35

AL37

AN7

AN9

AN11

AN13

AN35

AN37

AP10

AP12

AP36

AP38

AR7

AR9

L9

AR11

AR13

AU11

AU13

B12

L11

L13

L35

L37

M14

N7

B14

B32

N9

47

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VCCP

N11

N13

N35

N37

P10

P12

P14

P36

P38

R7

VID[2]

BB10

BB8

BC5

BB4

AY4

VCCP

VCCSENSE

VID[0]

VID[1]

VID[3]

VID[4]

VID[5]

VID[6]

VSS

A5

A7

A9

A11

A15

R9

A17

R11

R13

R35

R37

T14

U7

A19

A21

A23

A25

A27

A29

U9

A31

U11

U13

U35

U37

V10

V12

V14

V36

V38

W7

A39

A41

AA3

AA15

AA17

AA19

AA21

AA23

AA25

AA27

AA29

AA31

AA39

AB6

AB8

AB34

AB42

AC3

AC15

W9

W11

W13

W35

W37

Y14

BD12

BD8

BC7

Datasheet

48

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VSS

AC17

AC19

AC21

AC23

AC25

AC27

AC29

AC31

AC39

AD6

VSS

AG23

AG25

AG27

AG29

AG31

AG39

AH6

VSS

AH8

AH10

AH12

AH34

AH36

AH38

AH42

AJ3

AD8

AD10

AD12

AD34

AD36

AD38

AD42

AE3

AJ15

AJ17

AJ19

AJ21

AJ23

AJ25

AJ27

AJ29

AJ31

AJ39

AK6

AE15

AE17

AE19

AE21

AE23

AE25

AE27

AE29

AE31

AE39

AF6

AK8

AK34

AK42

AL3

AF8

AF34

AF42

AG3

AL15

AL17

AL19

AL21

AL23

AL25

AL27

AG15

AG17

AG19

AG21

49

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VSS

AL29

AL31

AL39

AM6

VSS

AR37

AR39

AT6

VSS

AT8

AM8

AT10

AT12

AT36

AT38

AT42

AU3

AM10

AM12

AM34

AM36

AM38

AM42

AN3

AU7

AU9

AN15

AN17

AN19

AN21

AN23

AN25

AN27

AN29

AN31

AN39

AP6

AU15

AU17

AU19

AU21

AU23

AU25

AU27

AU29

AU31

AU35

AU37

AU39

AV6

AP8

AP34

AP42

AR3

AV12

AV34

AV36

AV42

AV44

AW1

AR15

AR17

AR19

AR21

AR23

AR25

AR27

AR29

AR31

AR35

AW3

AW9

AW11

AW13

AW15

AW17

Datasheet

50

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VSS

AW19

AW21

AW23

AW25

AW27

AW29

AW31

AW33

AW35

AW37

AW39

AY6

VSS

BB2

BB6

VSS

BB12

BB36

BB42

BC3

BC9

BC11

BC15

BC17

BC19

BC21

BC23

BC25

BC27

BC29

BC31

BC33

BC41

BD4

BD6

BD36

BD38

BD40

C3

AY12

AY34

AY42

AY44

B4

B6

B36

B42

BA1

BA3

BA9

BA11

BA13

BA15

BA17

BA19

BA21

BA23

BA25

BA27

BA29

BA31

BA33

BA39

BA43

C11

C15

C17

C19

C21

C23

C25

C27

C29

C31

C39

D2

51

Datasheet

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VSS

D6

D36

D42

D44

E1

VSS

H42

J3

VSS

J15

J17

J19

J21

J23

J25

J27

J29

J31

J39

K6

E3

E9

E15

E17

E19

E21

E23

E25

E27

E29

E31

E39

F6

K8

K34

K42

L3

L15

L17

L19

L21

L23

L25

L27

L29

L31

L39

M6

F42

F44

G1

G3

G9

G15

G17

G19

G21

G23

G25

G27

G29

G31

G37

H6

M8

M10

M12

M34

M36

M38

M42

N3

H10

H34

H38

N15

Datasheet

52

Package Mechanical Specifications and Pin Information

Table 13.

Signal Listing by Ball

Number

Table 13.

Signal Listing by Ball

Number

Signal Name

Ball Number

Signal Name

Ball Number

VSS

N17

N19

N21

N23

N25

N27

N29

N31

N39

P6

VSS

U19

U21

U23

U25

U27

U29

U31

U39

V6

VSS

VSSSENSE

V8

P8

V34

V42

W3

P34

P42

R3

W15

W17

W19

W21

W23

W25

W27

W29

W31

W39

Y6

R15

R17

R19

R21

R23

R25

R27

R29

R31

R39

T6

Y8

T8

Y10

Y12

Y34

Y36

Y38

Y42

BC13

T10

T12

T34

T36

T38

T42

U3

U5

U15

U17

53

Datasheet

Package Mechanical Specifications and Pin Information

4.3

Alphabetical Signals Reference

Table 14.

Signal Description (Sheet 1 of 9)

Name

Type

Description

A[35:3]# (Address) define a 2³⁶-byte physical memory address

space. In sub-phase 1 of the address phase, these pins transmit the

address of a transaction. In sub-phase 2, these pins transmit

transaction type information. These signals must connect the

appropriate pins of both agents on the processor FSB. A[35:3]# are

source-synchronous signals and are latched into the receiving

buffers by ADSTB[1:0]#. Address signals are used as straps, which

are sampled before RESET# is deasserted.

Input/

Output

A[35:3]#

If A20M# (Address-20 Mask) is asserted, the processor masks

physical address Bit 20 (A20#) before looking up a line in any

internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address

wrap-around at the 1-MB boundary. Assertion of A20M# is only

supported in real mode.

A20M#

Input

A20M# is an asynchronous signal. However, to ensure recognition

of this signal following an input/output write instruction, it must be

valid along with the TRDY# assertion of the corresponding input/

output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[35:3]# and REQ[4:0]# pins. All bus

agents observe the ADS# activation to begin parity checking,

protocol checking, address decode, internal snoop, or deferred

reply ID match operations associated with the new transaction.

Input/

Output

ADS#

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their

rising and falling edges. Strobes are associated with signals as

shown below.

Input/

Output

ADSTB[1:0]#

Signals

REQ[4:0]#, A[16:3]# ADSTB[0]#

A[35:17]# ADSTB[1]#

Associated Strobe

The differential pair BCLK (Bus Clock) determines the FSB

frequency. All FSB agents must receive these signals to drive their

outputs and latch their inputs.

BCLK[1:0]

BNR#

Input

All external timing parameters are specified with respect to the

rising edge of BCLK0 crossing V_CROSS

.

BNR# (Block Next Request) is used to assert a bus stall by any bus

agent who is unable to accept new bus transactions. During a bus

stall, the current bus owner cannot issue any new transactions.

Input/

Output

Datasheet

54

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 2 of 9)

Name

Type

Description

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals. They are outputs from the processor that indicate

the status of breakpoints and programmable counters used for

monitoring processor performance. BPM[3:0]# should connect the

appropriate pins of all processor FSB agents.This includes debug or

performance monitoring tools.

Output

BPM[2:1]#

BPM[3,0]#

Input/

Output

Refer to the appropriate eXtended Debug Port: Debug Port Design

Guide for UP and DP Platforms for more detailed information.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the FSB. It must connect the appropriate pins of both FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes

the other agent to stop issuing new requests, unless such requests

are part of an ongoing locked operation. The priority agent keeps

BPRI# asserted until all of its requests are completed, then releases

the bus by deasserting BPRI#.

BPRI#

Input

BR0# is used by the processor to request the bus. The arbitration is

done between the processor (Symmetric Agent) and GMCH (High

Priority Agent).

Input/

Output

BR0#

BSEL[2:0] (Bus Select) are used to select the processor input clock

frequency. Table 3 defines the possible combinations of the signals

and the frequency associated with each combination. The required

frequency is determined by the processor, chipset and clock

synthesizer. All agents must operate at the same frequency.

BSEL[2:0]

Output

Analog

COMP[3:0] must be terminated on the system board using

precision (1% tolerance) resistors.

COMP[3:0]

Refer to the appropriate platform design guide for more details on

implementation.

D[63:0]# (Data) are the data signals. These signals provide a

64-bit data path between the FSB agents, and must connect the

appropriate pins on both agents. The data driver asserts DRDY# to

indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four

times in a common clock period. D[63:0]# are latched off the

falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of

16 data signals correspond to a pair of one DSTBP# and one

DSTBN#. The following table shows the grouping of data signals to

data strobes and DINV#.

Quad-Pumped Signal Groups

DSTBN#/

Input/

Output

D[63:0]#

Data Group

DINV#

DSTBP#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DINV# pins determine the polarity of the data

signals. Each group of 16 data signals corresponds to one DINV#

signal. When the DINV# signal is active, the corresponding data

group is inverted and therefore sampled active high.

55

Datasheet

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 3 of 9)

Name

Type

Description

DBR# (Data Bus Reset) is used only in processor systems where no

debug port is implemented on the system board. DBR# is used by a

debug port interposer so that an in-target probe can drive system

reset. If a debug port is implemented in the system, DBR# is a no

connect in the system. DBR# is not a processor signal.

DBR#

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for

driving data on the FSB to indicate that the data bus is in use. The

data bus is released after DBSY# is deasserted. This signal must

connect the appropriate pins on both FSB agents.

Input/

Output

DBSY#

DEFER# is asserted by an agent to indicate that a transaction

cannot be ensured in-order completion. Assertion of DEFER# is

normally the responsibility of the addressed memory or input/

output agent. This signal must connect the appropriate pins of both

FSB agents.

DEFER#

Input

DINV[3:0]# (Data Bus Inversion) are source synchronous and

indicate the polarity of the D[63:0]# signals. The DINV[3:0]#

signals are activated when the data on the data bus is inverted. The

bus agent will invert the data bus signals if more than half the bits,

within the covered group, would change level in the next cycle.

DINV[3:0]# Assignment To Data Bus

Input/

Output

Bus Signal

Data Bus Signals

DINV[3:0]#

DINV[3]#

DINV[2]#

DINV[1]#

DINV[0]#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DPRSTP#, when asserted on the platform, causes the processor to

transition from the Deep Sleep State to the Deeper Sleep state or

C6 state. To return to the Deep Sleep State, DPRSTP# must be

deasserted. DPRSTP# is driven by the ICH9M chipset.

DPRSTP#

Input

DPSLP# when asserted on the platform causes the processor to

transition from the Sleep State to the Deep Sleep state. To return to

the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by

the ICH9M chipset.

DPSLP#

DPWR#

DRDY#

DPWR# is a control signal used by the chipset to reduce power on

the processor data bus input buffers. The processor drives this pin

during dynamic FSB frequency switching.

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common

clock data transfer, DRDY# may be deasserted to insert idle clocks.

This signal must connect the appropriate pins of both FSB agents.

Input/

Output

Datasheet

56

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 4 of 9)

Name

Type

Description

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

DSTBN[0]#

D[15:0]#, DINV[0]#

Input/

Output

DSTBN[3:0]#

D[31:16]#, DINV[1]# DSTBN[1]#

D[47:32]#, DINV[2]# DSTBN[2]#

D[63:48]#, DINV[3]# DSTBN[3]#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

DSTBP[0]#

D[15:0]#, DINV[0]#

Input/

Output

DSTBP[3:0]#

D[31:16]#, DINV[1]# DSTBP[1]#

D[47:32]#, DINV[2]# DSTBP[2]#

D[63:48]#, DINV[3]# DSTBP[3]#

FERR# (Floating-point Error)/PBE# (Pending Break Event) is a

multiplexed signal and its meaning is qualified with STPCLK#. When

STPCLK# is not asserted, FERR#/PBE# indicates a floating point

when the processor detects an unmasked floating-point error.

FERR# is similar to the ERROR# signal on the Intel® 387

coprocessor, and is included for compatibility with systems using

Microsoft MS-DOS*-type floating-point error reporting. When

STPCLK# is asserted, an assertion of FERR#/PBE# indicates that

the processor has a pending break event waiting for service. The

assertion of FERR#/PBE# indicates that the processor should be

returned to the Normal state. When FERR#/PBE# is asserted,

indicating a break event, it will remain asserted until STPCLK# is

deasserted. Assertion of PREQ# when STPCLK# is active will also

cause an FERR# break event.

FERR#/PBE#

Output

For additional information on the pending break event functionality,

including identification of support of the feature and enable/disable

information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32

Architectures Software Developer's Manuals and the Intel®

Processor Identification and CPUID Instruction application note.

Refer to the appropriate platform design guide for termination

requirements.

GTLREF determines the signal reference level for AGTL+ input pins.

GTLREF should be set at 2/3 V_CCP. GTLREF is used by the AGTL+

receivers to determine if a signal is a Logical 0 or Logical 1.

GTLREF

Input

Refer to the appropriate platform design guide for details on

GTLREF implementation.

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Either FSB agent may assert both HIT#

and HITM# together to indicate that it requires a snoop stall that

can be continued by reasserting HIT# and HITM# together.

HIT#

Input/

Output

HITM#

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57

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 5 of 9)

Name

Type

Description

IERR# (Internal Error) is asserted by the processor as the result of

an internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the FSB. This transaction may optionally

be converted to an external error signal (e.g., NMI) by system core

logic. The processor will keep IERR# asserted until the assertion of

RESET#, BINIT#, or INIT#.

IERR#

Output

Refer to the appropriate platform design guide for termination

requirements.

IGNNE# (Ignore Numeric Error) is asserted to force the processor

to ignore a numeric error and continue to execute non-control

floating-point instructions. If IGNNE# is deasserted, the processor

generates an exception on a non-control floating-point instruction if

a previous floating-point instruction caused an error. IGNNE# has

no effect when the NE bit in Control Register 0 (CR0) is set.

IGNNE#

Input

IGNNE# is an asynchronous signal. However, to ensure recognition

of this signal following an input/output write instruction, it must be

valid along with the TRDY# assertion of the corresponding input/

output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside

the processor without affecting its internal caches or floating-point

registers. The processor then begins execution at the power-on

Reset vector configured during power-on configuration. The

processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure

recognition of this signal following an input/output write instruction,

it must be valid along with the TRDY# assertion of the

INIT#

Input

corresponding input/output write bus transaction. INIT# must

connect the appropriate pins of both FSB agents.

If INIT# is sampled active on the active-to-inactive transition of

RESET#, then the processor executes its Built-in Self-Test (BIST)

Refer to the appropriate platform design guide for termination

requirements.

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins

of all APIC Bus agents. When the APIC is disabled, the LINT0 signal

becomes INTR, a maskable interrupt request signal, and LINT1

becomes NMI, a nonmaskable interrupt. INTR and NMI are

backward-compatible with the signals of those names on the

Pentium processor. Both signals are asynchronous.

LINT[1:0]

Input

Both of these signals must be software configured via BIOS

programming of the APIC register space to be used either as NMI/

INTR or LINT[1:0]. Because the APIC is enabled by default after

Reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK# indicates to the system that a transaction must occur

atomically. This signal must connect the appropriate pins of both

FSB agents. For a locked sequence of transactions, LOCK# is

asserted from the beginning of the first transaction to the end of

the last transaction.

Input/

Output

LOCK#

When the priority agent asserts BPRI# to arbitrate for ownership of

the FSB, it will wait until it observes LOCK# deasserted. This

enables symmetric agents to retain ownership of the FSB

throughout the bus locked operation and ensure the atomicity of

lock.

Datasheet

58

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 6 of 9)

Name

Type

Description

Probe Ready signal used by debug tools to determine processor

debug readiness.

PRDY#

Output

Refer to the appropriate eXtended Debug Port: Debug Port Design

Guide for UP and DP Platforms for more detailed information.

Probe Request signal used by debug tools to request debug

operation of the processor.

PREQ#

Input

Refer to the appropriate eXtended Debug Port: Debug Port Design

Guide for UP and DP Platforms for more detailed information.

As an output, PROCHOT# (Processor Hot) will go active when the

processor temperature monitoring sensor detects that the

processor has reached its maximum safe operating temperature.

This indicates that the processor Thermal Control Circuit (TCC) has

been activated, if enabled. As an input, assertion of PROCHOT# by

the system will activate the TCC, if enabled. The TCC will remain

active until the system deasserts PROCHOT#.

Input/

Output

PROCHOT#

By default PROCHOT# is configured as an output. The processor

must be enabled via the BIOS for PROCHOT# to be configured as

bidirectional.

Refer to the appropriate platform design guide for termination

requirements.

This signal may require voltage translation on the motherboard.

Refer to the appropriate platform design guide for more details.

Processor Power Status Indicator signal. This signal is asserted

when the processor is both in the normal state (HFM to LFM) and in

lower power states (Deep Sleep and Deeper Sleep). Refer to the

Intel® MVP-6 Mobile Processor and Mobile Chipset Voltage

Regulation Specification for more details on the PSI# signal.

PSI#

Output

PWRGOOD (Power Good) is a processor input. The processor

requires this signal to be a clean indication that the clocks and

power supplies are stable and within their specifications. ‘Clean’

implies that the signal remains low (capable of sinking leakage

current), without glitches, from the time that the power supplies

are turned on until they come within specification. The signal must

then transition monotonically to a high state. PWRGOOD can be

driven inactive at any time, but clocks and power must again be

stable before a subsequent rising edge of PWRGOOD. The

PWRGOOD signal must be supplied to the processor; it is used to

protect internal circuits against voltage sequencing issues. It should

be driven high throughout boundary scan operation.

PWRGOOD

Input

Refer to the appropriate platform design guide for termination

requirements.

REQ[4:0]# (Request Command) must connect the appropriate pins

of both FSB agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are

source synchronous to ADSTB[0]#.

Input/

Output

REQ[4:0]#

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59

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 7 of 9)

Name

Type

Description

Asserting the RESET# signal resets the processor to a known state

and invalidates its internal caches without writing back any of their

contents. For a power-on Reset, RESET# must stay active for at

least two milliseconds after V_CCand BCLK have reached their

proper specifications. On observing active RESET#, both FSB

agents will deassert their outputs within two clocks. All processor

straps must be valid within the specified setup time before RESET#

is deasserted.

RESET#

Input

Refer to the appropriate platform design guide for termination

requirements and implementation details. There is a 55 Ω

(nominal) on die pull-up resistor on this signal.

RS[2:0]# (Response Status) are driven by the response agent (the

agent responsible for completion of the current transaction), and

must connect the appropriate pins of both FSB agents.

RS[2:0]#

RSVD

Input

These pins are RESERVED and must be left unconnected on the

board. However, it is recommended that routing channels to these

pins on the board be kept open for possible future use. Refer to the

appropriate platform design guide for details.

Reserved/

No

Connect

SLP# (Sleep), when asserted in Stop-Grant state, causes the

processor to enter the Sleep state. During Sleep state, the

processor stops providing internal clock signals to all units, leaving

only the Phase-Locked Loop (PLL) still operating. Processors in this

state will not recognize snoops or interrupts. The processor will

recognize only assertion of the RESET# signal, deassertion of SLP#,

and removal of the BCLK input while in Sleep state. If SLP# is

deasserted, the processor exits Sleep state and returns to Stop-

Grant state, restarting its internal clock signals to the bus and

processor core units. If DPSLP# is asserted while in the Sleep state,

the processor will exit the Sleep state and transition to the Deep

Sleep state.

SLP#

Input

SMI# (System Management Interrupt) is asserted asynchronously

by system logic. On accepting a System Management Interrupt, the

processor saves the current state and enters System Management

Mode (SMM). An SMI Acknowledge transaction is issued and the

processor begins program execution from the SMM handler.

SMI#

Input

If an SMI# is asserted during the deassertion of RESET#, then the

processor will tristate its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to

enter a low power Stop-Grant state. The processor issues a Stop-

Grant Acknowledge transaction, and stops providing internal clock

signals to all processor core units except the FSB and APIC units.

The processor continues to snoop bus transactions and service

interrupts while in Stop-Grant state. When STPCLK# is deasserted,

the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus

clock; STPCLK# is an asynchronous input.

STPCLK#

TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

TCK

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

60

Datasheet

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 8 of 9)

Name

Type

Description

TDO (Test Data Out) transfers serial test data out of the processor.

TDO provides the serial output needed for JTAG specification

support.

TDO

Output

TEST1,

TEST2,

TEST3,

TEST4,

TEST5,

TEST6

Refer to the appropriate platform design guide for further TEST1,

TEST2, TEST3, TEST4, TEST5, TEST6 termination requirements and

implementation details.

Input

THRMDA

THRMDC

Other

Thermal Diode Anode.

Thermal Diode Cathode.

The processor protects itself from catastrophic overheating by use

of an internal thermal sensor. This sensor is set well above the

normal operating temperature to ensure that there are no false

trips. The processor will stop all execution when the junction

temperature exceeds approximately 125 °C. This is signalled to the

system by the THERMTRIP# (Thermal Trip) pin.

THERMTRIP#

Output

Refer to the appropriate platform design guide for termination

requirements.

TMS (Test Mode Select) is a JTAG specification support signal used

by debug tools.

TMS

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY#

must connect the appropriate pins of both FSB agents.

TRDY#

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

Refer to the appropriate eXtended Debug Port: Debug Port Design

Guide for UP and DP Platforms for more detailed information.

TRST#

Input

V_CC

V_SS

Input

Processor core power supply.

Processor core ground node.

V_CCAprovides isolated power for the internal processor core PLLs_.

Refer to the appropriate platform design guide for complete

implementation details.

V_CCA

V_CCP

Input

Processor I/O Power Supply.

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61

Package Mechanical Specifications and Pin Information

Table 14.

Signal Description (Sheet 9 of 9)

Name

Type

Description

V

_{CC_SENSE}together with V_{SS_SENSE}are voltage feedback signals to

Intel® MVP6 that control the 2.1 mΩ loadline at the processor die.

It should be used to sense voltage near the silicon with little noise.

Refer to the platform design guide for termination and routing

recommendations.

V_{CC_SENSE}

Output

VID[6:0] (Voltage ID) pins are used to support automatic selection

of power supply voltages (V_CC). Unlike some previous generations

of processors, these are CMOS signals that are driven by the

processor. The voltage supply for these pins must be valid before

the VR can supply V_CCto the processor. Conversely, the VR output

must be disabled until the voltage supply for the VID pins becomes

valid. The VID pins are needed to support the processor voltage

specification variations. See Table 2 for definitions of these pins.

The VR must supply the voltage that is requested by the pins, or

disable itself.

VID[6:0]

Output

V_{SS_SENSE}together with V_{CC_SENSE}are voltage feedback signals to

Intel MVP6 that control the 2.1-mΩ loadline at the processor die. It

should be used to sense ground near the silicon with little noise.

Refer to the platform design guide for termination and routing

recommendations.

V_{SS_SENSE}

§

62

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

Maintaining the proper thermal environment is key to reliable, long-term system

operation. A complete thermal solution includes both component and system-level

thermal management features. To allow for the optimal operation and long-term

reliability of Intel processor-based systems, the system/processor thermal solution

should be designed so the processor remains within the minimum and maximum

junction temperature (T_J) specifications at the corresponding thermal design power

(TDP).

Caution:

Operating the processor outside these operating limits may result in permanent

damage to the processor and potentially other components in the system.

Table 15.

Power Specifications for the Dual-Core and Single-Core Standard Voltage (SV)

Processors

Processor

Number

Core Frequency &

Voltage

Thermal Design

Power

Symbol

Unit

Notes

TDP

900

2.2 GHz

Parameter

35

W

1, 4, 5

Symbol

Min

Typ

Max

Unit

Notes

P_AH,

Auto Halt, Stop Grant Power

—

13.9

W

2, 6

P_SGNT

P_SLP

P_DPSLP

T_J

Sleep Power

—

0

—

13.1

5.5

W

°C

2, 6

3, 4

Deep Sleep Power

Junction Temperature

105

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

As measured by the activation of the on-die Intel® Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specifications.

5.

6.

At Tj of 105 ^oC.

At Tj of 50 ^oC.

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63

Thermal Specifications and Design Considerations

Table 16.

Power Specifications for the Single-Core Ultra Low Voltage Processors (ULV,

10 W)

Processor

Number

Core Frequency &

Voltage

Thermal Design

Power

Symbol

Unit

Notes

723

743

10

W

1, 4, 5

Notes

1.2 GHz

TDP

1.3 GHz

1

Symbol

Parameter

Min

Typ Max

Unit

P_AH,

Auto Halt, Stop Grant Power

—

2.9

W

2, 6

P_SGNT

P_SLP

P_DPSLP

T_J

Sleep Power

—

0

—

2.5

1.3

100

W

°C

2, 6

3, 4

Deep Sleep Power

Junction Temperature

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

4.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specifications.

5.

6.

At Tj of 100 ^oC

At Tj of 50 °C

Table 17.

Power Specifications for the Single-Core Ultra Low Voltage (ULV, 5.5 W)

Processors

Processor

Number

Core Frequency &

Voltage

Thermal Design

Power

Symbol

Unit

Notes

TDP

722

1.2 GHz

Parameter

5.5

W

1, 4, 5

Symbol

Min

Typ

Max

Unit

Notes

P_AH,

Auto Halt, Stop Grant Power

—

2.1

W

2, 6

P_SGNT

P_SLP

P_DPSLP

T_J

Sleep Power

—

0

—

1.8

0.7

100

W

°C

2, 6

2, 7

3, 4

Deep Sleep Power

Junction Temperature

NOTES:

1.

The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate.

Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the

temperature indicated.

2.

3.

As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal

Monitor’s automatic mode is used to indicate that the maximum T_Jhas been reached.

Refer to Section 5.1 for more details.

64

Datasheet

Thermal Specifications and Design Considerations

4.

The Intel Thermal Monitor automatic mode must be enabled for the processor to operate

within specifications.

At Tj of 100 ^oC

At Tj of 50 °C

5.

6.

7.

At Tj of 35 °C

5.1

Monitoring Die Temperature

The processor incorporates three methods of monitoring die temperature:

• Thermal Diode

• Intel® Thermal Monitor

• Digital Thermal Sensor

5.1.1

Thermal Diode

Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current

characteristics of a substrate PNP transistor. Since these characteristics are a function

of temperature, in principle one can use these parameters to calculate silicon

temperature values. For older silicon process technologies (i.e., Intel Core 2 Duo Mobile

Processor and earlier processor), it is possible to simplify the voltage/current and

temperature relationships by treating the substrate transistor as though it were a

simple diffusion diode. In this case, the assumption is that the beta of the transistor

does not impact the calculated temperature values. The resultant “diode” model

essentially predicts a quasi linear relationship between the base/emitter voltage

differential of the PNP transistor and the applied temperature (one of the

proportionality constants in this relationship is processor specific, and is known as the

diode ideality factor). Realization of this relationship is accomplished with the SMBus

thermal sensor that is connected to the transistor.

The processor is built on Intel’s advanced 45-nm processor technology. Due to this new

highly advanced processor technology, it is no longer possible to model the substrate

transistor as a simple diode. To accurately calculate silicon temperature one must use a

full bi-polar junction transistor-type model. In this model, the voltage/current and

temperature characteristics include an additional process dependant parameter which

is known as the transistor “beta”. System designers should be aware that the current

thermal sensors on Santa Rosa platforms may not be configured to account for “beta”

and should work with their SMB thermal sensor vendors to ensure they have a part

capable of reading the thermal diode in BJT model.

Offset between the thermal diode-based temperature reading and the Intel Thermal

Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic

mode activation of the thermal control circuit. This temperature offset must be taken

into account when using the processor thermal diode to implement power management

events. This offset is different than the diode Toffset value programmed into the

processor Model-Specific Register (MSR).

Table 18 to Table 19 provide the diode interface and transistor model specifications.

Table 18.

Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

A24

A25

Thermal diode anode

Thermal diode cathode

Datasheet

65

Thermal Specifications and Design Considerations

Table 19.

Thermal Diode Parameters Using Transistor Model

Symbol

Parameter

Min

Typ

Max

Unit

Notes

I_FW

I_E

Forward Bias Current

Emitter Current

5

—

200

1.008

0.5

μA

1

n_Q

Transistor Ideality

0.997

0.1

3.0

1.001

0.4

2, 3, 4

2, 3

2

Beta

R_T

Series Resistance

4.5

7.0

Ω

NOTES:

1.

2.

3.

4.

Intel does not support or recommend operation of the thermal diode under reverse bias.

Characterized across a temperature range of 50-100 °C.

Not 100% tested. Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

/n

I

_C= I_S* (e ^qVBE ^kT–1)

Q

where I_S= saturation current, q = electronic charge, V_BE= voltage across the transistor

base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute

temperature (Kelvin).

5.1.2

Intel® Thermal Monitor

The Intel Thermal Monitor helps control the processor temperature by activating the

TCC (Thermal Control Circuit) when the processor silicon reaches its maximum

operating temperature. The temperature at which the Intel Thermal Monitor activates

the TCC is not user configurable. Bus traffic is snooped in the normal manner and

interrupt requests are latched (and serviced during the time that the clocks are on)

while the TCC is active.

With a properly designed and characterized thermal solution, it is anticipated that the

TCC would only be activated for very short periods of time when running the most

power-intensive applications. The processor performance impact due to these brief

periods of TCC activation is expected to be minor and hence not detectable. An under-

designed thermal solution that is not able to prevent excessive activation of the TCC in

the anticipated ambient environment may cause a noticeable performance loss and

may affect the long-term reliability of the processor. In addition, a thermal solution that

is significantly under designed may not be capable of cooling the processor even when

the TCC is active continuously.

The Intel Thermal Monitor controls the processor temperature by modulating (starting

and stopping) the processor core clocks when the processor silicon reaches its

maximum operating temperature. The Intel Thermal Monitor uses two modes to

activate the TCC: automatic mode and on-demand mode. If both modes are activated,

automatic mode takes precedence.

The automatic mode is called Intel Thermal Monitor 1 (TM1). This modes are selected

by writing values to the MSRs of the processor. After automatic mode is enabled, the

TCC will activate only when the internal die temperature reaches the maximum allowed

value for operation.

When TM1 is enabled and a high temperature situation exists, the clocks will be

modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times

are processor speed-dependent and will decrease linearly as processor core frequencies

increase. Once the temperature has returned to a non-critical level, modulation ceases

and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid

active/inactive transitions of the TCC when the processor temperature is near the trip

66

Datasheet

Thermal Specifications and Design Considerations

point. The duty cycle is factory configured and cannot be modified. Also, automatic

mode does not require any additional hardware, software drivers, or interrupt handling

routines. Processor performance will be decreased by the same amount as the duty

cycle when the TCC is active.

The Intel Thermal Monitor automatic mode must be enabled through BIOS for

the processor to be operating within specifications. Intel recommends TM1 be

enabled on the processors.

TM1 features are also referred to as Adaptive Thermal Monitoring features.

The TCC may also be activated via on-demand mode. If Bit 4 of the ACPI Intel Thermal

Monitor control register is written to a 1, the TCC will be activated immediately

independent of the processor temperature. When using on-demand mode to activate

the TCC, the duty cycle of the clock modulation is programmable via Bits 3:1 of the

same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is

fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be

programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments.

On-demand mode may be used at the same time automatic mode is enabled, however,

if the system tries to enable the TCC via on-demand mode at the same time automatic

mode is enabled and a high temperature condition exists, automatic mode will take

precedence.

An external signal, PROCHOT# (processor hot) is asserted when the processor detects

that its temperature is above the thermal trip point. Bus snooping and interrupt

latching are also active while the TCC is active.

Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also

includes one ACPI register, one performance counter register, three MSR, and one I/O

pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal

Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt

upon the assertion or deassertion of PROCHOT#.

PROCHOT# will not be asserted when the processor is in the Stop Grant,

Sleep, Deep Sleep, low-power states, hence the thermal diode reading must

be used as a safeguard to maintain the processor junction temperature within

maximum specification. If the platform thermal solution is not able to maintain the

processor junction temperature within the maximum specification, the system must

initiate an orderly shutdown to prevent damage. If the processor enters one of the

above low-power states with PROCHOT# already asserted, PROCHOT# will remain

asserted until the processor exits the low-power state and the processor junction

temperature drops below the thermal trip point. However, PROCHOT# will de-assert for

the duration of Intel Deep Power Down (C6) state residency.

If Thermal Monitor automatic mode is disabled, the processor will be operating out of

specification. Regardless of enabling the automatic or on-demand modes, in the event

of a catastrophic cooling failure, the processor will automatically shut down when the

silicon has reached a temperature of approximately 125 °C. At this point the

THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor

activity and does not generate any bus cycles. When THERMTRIP# is asserted, the

processor core voltage must be shut down within the time specified in Chapter 3.

In all cases the Intel Thermal Monitor feature must be enabled for the processor to

remain within specification.

5.1.3

Digital Thermal Sensor

The processor also contains an on-die Digital Thermal Sensor (DTS) that can be read

via an MSR (no I/O interface). Each core of the processor will have a unique digital

thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the

Datasheet

67

Thermal Specifications and Design Considerations

preferred method of reading the processor die temperature since it can be located

much closer to the hottest portions of the die and can thus more accurately track the

die temperature and potential activation of processor core clock modulation via the

Thermal Monitor. The DTS is only valid while the processor is in the normal operating

state (the Normal package level low-power state).

Unlike traditional thermal devices, the DTS outputs a temperature relative to the

maximum supported operating temperature of the processor (T_J,max). It is the

responsibility of software to convert the relative temperature to an absolute

temperature. The temperature returned by the DTS will always be at or below T_J,max

.

Catastrophic temperature conditions are detectable via an Out Of Specification status

bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating

out of specification and immediate shutdown of the system should occur. The processor

operation and code execution is not ensured once the activation of the Out of

Specification status bit is set.

The DTS-relative temperature readout corresponds to the Thermal Monitor (TM1)

trigger point. When the DTS indicates maximum processor core temperature has been

reached, the TM1 hardware thermal control mechanism will activate. The DTS and TM1

temperature may not correspond to the thermal diode reading since the thermal diode

is located in a separate portion of the die and thermal gradient between the individual

core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary

substantially due to changes in processor power, mechanical and thermal attach, and

software application. The system designer is required to use the DTS to ensure proper

operation of the processor within its temperature operating specifications.

Changes to the temperature can be detected via two programmable thresholds located

in the processor MSRs. These thresholds have the capability of generating interrupts

via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software

Developer's Manuals for specific register and programming details.

5.2

5.3

Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and

temperature gradient. This feature is intended for graceful shutdown before the

THERMTRIP# is activated. If the processor’s TM1 are triggered and the temperature

remains high, an Out Of Spec status and sticky bit are latched in the status MSR

register and generates a thermal interrupt.

PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die

temperature has reached its maximum operating temperature. If TM1 is enabled, then

the TCC will be active when PROCHOT# is asserted. The processor can be configured to

generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the an

interrupt upon the assertion or deassertion of PROCHOT#. Refer to the Intel® 64 and

IA-32 Architectures Software Developer's Manuals for specific register and

programming details.

The processor implements a bi-directional PROCHOT# capability to allow system

designs to protect various components from overheating situations. The PROCHOT#

signal is bi-directional in that it can either signal when the processor has reached its

maximum operating temperature or be driven from an external source to activate the

TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal

protection of system components.

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Datasheet

Thermal Specifications and Design Considerations

Only a single PROCHOT# pin exists at a package level of the processor. When either

core's thermal sensor trips, PROCHOT# signal will be driven by the processor package.

If only TM1 is enabled, PROCHOT# will be asserted regardless of which core is above its

TCC temperature trip point, and both cores will have their core clocks modulated. It is

important to note that Intel recommends TM1 to be enabled in BIOS.

When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores,

then both processor cores will have their core clocks modulated. It should be noted that

Force TM1, enabled via BIOS, does not have any effect on external PROCHOT#.

PROCHOT# may be used for thermal protection of voltage regulators (VR). System

designers can create a circuit to monitor the VR temperature and activate the TCC

when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)

and activating the TCC, the VR will cool down as a result of reduced processor power

consumption. Bi-directional PROCHOT# can allow VR thermal designs to target

maximum sustained current instead of maximum current. Systems should still provide

proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case

of system cooling failure. The system thermal design should allow the power delivery

circuitry to operate within its temperature specification even while the processor is

operating at its TDP. With a properly designed and characterized thermal solution, it is

anticipated that bi-directional PROCHOT# would only be asserted for very short periods

of time when running the most power-intensive applications. An under-designed

thermal solution that is not able to prevent excessive assertion of PROCHOT# in the

anticipated ambient environment may cause a noticeable performance loss.

§

Datasheet

69


型号：	AV80585VG0091MPSLGAN
厂家：	INTEL
描述：	Microprocessor, 64-Bit, 1200MHz, CMOS, PBGA956, 22 X 22 MM, LOW HALOGEN FREE, UFCBGA8-956 时钟外围集成电路
文件：	总69页 (文件大小：967K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AV80585VG0091MPSLGAN [INTEL]

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