AV8062700834912/SR00U [INTEL]
RISC Microprocessor, 64-Bit, 3400MHz, CMOS;
| 型号： | AV8062700834912/SR00U |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 64-Bit, 3400MHz, CMOS |
| 文件： | 总170页 (文件大小：3681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
2nd Generation Intel Core™
®
Processor Family Mobile and Intel
®
Celeron Processor Family Mobile
Datasheet, Volume 1
®
Supporting Intel Core™ i7 Mobile Extreme Edition Processor Series and
®
Intel Core™ i5 and i7 Mobile Processor Series
®
®
Supporting Intel Celeron Mobile Processor Series
This is Volume 1 of 2
September 2012
Document Number: 324692-006
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absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future
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operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Enhanced Intel SpeedStep® Technology; See the Processor Spec Finder or contact your Intel representative for more information.
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a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,
an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing
Group and specific software for some uses. For more information, see http://www.intel.com/technology/security/
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
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and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the
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notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting
wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see http://www.intel.com/technology/
platform-technology/intel-amt/
Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see http://www.intel.com/
technology/turboboost.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,
not across different processor families. See www.intel.com/products/processor_number for details.
Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced
for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion
or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user.
Intel, Intel Core Celeron, Speedstep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2012, Intel Corporation. All rights reserved.
2
Datasheet, Volume 1
Contents
1
Introduction............................................................................................................11
1.1
Processor Feature Details ...................................................................................13
1.1.1 Supported Technologies ..........................................................................13
Interfaces ........................................................................................................13
1.2.1 System Memory Support.........................................................................13
1.2.2 PCI Express* .........................................................................................14
1.2.3 Direct Media Interface (DMI)....................................................................15
1.2.4 Platform Environment Control Interface (PECI)...........................................16
1.2.5 Processor Graphics .................................................................................16
1.2.6 Embedded DisplayPort* (eDP)..................................................................17
1.2.7 Intel® Flexible Display Interface (Intel® FDI) .............................................17
Power Management Support ...............................................................................17
1.3.1 Processor Core.......................................................................................17
1.3.2 System.................................................................................................17
1.3.3 Memory Controller..................................................................................17
1.3.4 PCI Express* .........................................................................................17
1.3.5 Direct Media Interface (DMI)....................................................................17
1.3.6 Processor Graphics Controller...................................................................18
Thermal Management Support ............................................................................18
Package...........................................................................................................18
Terminology .....................................................................................................18
Related Documents............................................................................................20
1.2
1.3
1.4
1.5
1.6
1.7
2
Interfaces................................................................................................................21
2.1
System Memory Interface...................................................................................21
2.1.1 System Memory Technology Supported .....................................................21
2.1.2 System Memory Timing Support...............................................................22
2.1.3 System Memory Organization Modes.........................................................22
2.1.3.1 Single-Channel Mode.................................................................22
2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode ...........22
2.1.4 Rules for Populating Memory Slots............................................................23
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)..........24
2.1.5.1 Just-in-Time Command Scheduling..............................................24
2.1.5.2 Command Overlap ....................................................................24
2.1.5.3 Out-of-Order Scheduling............................................................24
2.1.6 Memory Type Range Registers (MTRRs) Enhancement.................................24
2.1.7 Data Scrambling ....................................................................................24
2.1.8 DRAM Clock Generation...........................................................................24
PCI Express* Interface.......................................................................................25
2.2.1 PCI Express* Architecture .......................................................................25
2.2.1.1 Transaction Layer .....................................................................26
2.2.1.2 Data Link Layer ........................................................................26
2.2.1.3 Physical Layer ..........................................................................26
2.2.2 PCI Express* Configuration Mechanism .....................................................27
2.2.3 PCI Express Graphics..............................................................................27
2.2.4 PCI Express* Lanes Connection................................................................28
Direct Media Interface (DMI)...............................................................................28
2.3.1 DMI Error Flow.......................................................................................28
2.3.2 Processor / PCH Compatibility Assumptions................................................28
2.3.3 DMI Link Down ......................................................................................29
Processor Graphics Controller (GT) ......................................................................29
2.2
2.3
2.4
Datasheet, Volume 1
3
2.4.1 3D and Video Engines for Graphics Processing ........................................... 30
2.4.1.1 3D Engine Execution Units......................................................... 30
2.4.1.2 3D Pipeline.............................................................................. 30
2.4.1.3 Video Engine ........................................................................... 31
2.4.1.4 2D Engine ............................................................................... 31
2.4.2 Processor Graphics Display...................................................................... 32
2.4.2.1 Display Planes.......................................................................... 32
2.4.2.2 Display Pipes ........................................................................... 33
2.4.2.3 Display Ports ........................................................................... 33
2.4.2.4 Embedded DisplayPort*............................................................. 33
2.4.3 Intel® Flexible Display Interface (Intel® FDI)............................................. 33
2.4.4 Multi-Graphics Controller Multi-Monitor Support ......................................... 34
Platform Environment Control Interface (PECI) ..................................................... 34
Interface Clocking............................................................................................. 34
2.6.1 Internal Clocking Requirements ............................................................... 34
2.5
2.6
3
Technologies........................................................................................................... 35
3.1
Intel® Virtualization Technology (Intel® VT)......................................................... 35
3.1.1 Intel® Virtualization Technology (Intel® VT) for
IA-32, Intel® 64 and Intel® Architecture
(Intel® VT-x) Objectives......................................................................... 35
3.1.2 Intel® Virtualization Technology (Intel® VT) for
IA-32, Intel® 64 and Intel® Architecture
(Intel® VT-x) Features ........................................................................... 36
3.1.3 Intel® Virtualization Technology (Intel® VT) for Directed
I/O (Intel® VT-d) Objectives ................................................................... 36
3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed
I/O (Intel® VT-d) Features...................................................................... 37
3.1.5 Intel® Virtualization Technology (Intel® VT) for Directed
I/O (Intel® VT-d) Features Not Supported................................................. 37
Intel® Trusted Execution Technology (Intel® TXT)................................................. 38
Intel® Hyper-Threading Technology (Intel® HT Technology)................................... 38
Intel® Turbo Boost Technology........................................................................... 39
3.4.1 Intel® Turbo Boost Technology Frequency................................................. 39
3.4.2 Intel® Turbo Boost Technology Graphics Frequency.................................... 40
Intel® Advanced Vector Extensions (Intel® AVX)................................................... 40
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) .................. 40
3.6.1 PCLMULQDQ Instruction ......................................................................... 41
Intel® 64 Architecture x2APIC ............................................................................ 41
3.2
3.3
3.4
3.5
3.6
3.7
4
Power Management ................................................................................................ 43
4.1
Advanced Configuration and Power Interface (ACPI) States Supported..................... 44
4.1.1 System States....................................................................................... 44
4.1.2 Processor Core / Package Idle States........................................................ 44
4.1.3 Integrated Memory Controller States........................................................ 44
4.1.4 PCI Express* Link States ........................................................................ 45
4.1.5 Direct Media Interface (DMI) States ......................................................... 45
4.1.6 Processor Graphics Controller States ........................................................ 45
4.1.7 Interface State Combinations .................................................................. 45
Processor Core Power Management..................................................................... 46
4.2.1 Enhanced Intel® SpeedStep® Technology ................................................. 46
4.2.2 Low-Power Idle States............................................................................ 47
4.2.3 Requesting Low-Power Idle States ........................................................... 48
4.2.4 Core C-states........................................................................................ 49
4.2.4.1 Core C0 State.......................................................................... 49
4.2.4.2 Core C1/C1E State ................................................................... 49
4.2.4.3 Core C3 State.......................................................................... 49
4.2
4
Datasheet, Volume 1
4.2.4.4 Core C6 State...........................................................................49
4.2.4.5 Core C7 State...........................................................................49
4.2.4.6 C-State Auto-Demotion..............................................................50
4.2.5 Package C-States ...................................................................................50
4.2.5.1 Package C0..............................................................................51
4.2.5.2 Package C1/C1E .......................................................................52
4.2.5.3 Package C3 State......................................................................52
4.2.5.4 Package C6 State......................................................................52
4.2.5.5 Package C7 State......................................................................53
4.2.5.6 Dynamic L3 Cache Sizing ...........................................................53
Integrated Memory Controller (IMC) Power Management ........................................53
4.3.1 Disabling Unused System Memory Outputs ................................................53
4.3.2 DRAM Power Management and Initialization...............................................54
4.3.2.1 Initialization Role of CKE............................................................55
4.3.2.2 Conditional Self-Refresh.............................................................55
4.3.2.3 Dynamic Power-down Operation .................................................56
4.3.2.4 DRAM I/O Power Management....................................................56
PCI Express* Power Management........................................................................56
Direct Media Interface (DMI) Power Management ..................................................56
Graphics Power Management ..............................................................................57
4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)
4.3
4.4
4.5
4.6
(also known as CxSR).............................................................................57
4.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)..............57
4.6.3 Graphics Render C-State .........................................................................57
4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT) ..................................58
4.6.5 Intel® Graphics Dynamic Frequency..........................................................58
4.6.6 Display Power Savings Technology 6.0 (DPST) ...........................................58
4.6.7 Automatic Display Brightness (ADB)..........................................................59
4.6.8 Intel® Seamless Display Refresh Rate Switching Technology (Intel® SDRRS
Technology) ..........................................................................................59
Thermal Power Management...............................................................................59
4.7
5
Thermal Management..............................................................................................61
5.1
5.2
Thermal Design Power (TDP) and Junction Temperature (Tj) ...................................61
Thermal Considerations......................................................................................61
5.2.1 Intel® Turbo Boost Technology Power Control and Reporting........................62
5.2.2 Package Power Control............................................................................63
5.2.3 Power Plane Control................................................................................63
5.2.4 Turbo Time Parameter ............................................................................63
Thermal and Power Specifications........................................................................64
Thermal Management Features ...........................................................................67
5.4.1 Processor Package Thermal Features.........................................................67
5.4.1.1 Adaptive Thermal Monitor ..........................................................68
5.4.1.2 Digital Thermal Sensor ..............................................................70
5.4.1.3 PROCHOT# Signal.....................................................................71
5.4.2 Processor Core Specific Thermal Features..................................................73
5.4.2.1 On-Demand Mode.....................................................................73
5.4.3 Memory Controller Specific Thermal Features.............................................73
5.4.3.1 Programmable Trip Points ..........................................................73
5.4.4 Platform Environment Control Interface (PECI)...........................................74
5.4.4.1 Fan Speed Control with Digital Thermal Sensor .............................74
5.3
5.4
6
Signal Description ...................................................................................................75
6.1
6.2
6.3
6.4
System Memory Interface Signals........................................................................76
Memory Reference and Compensation Signals.......................................................77
Reset and Miscellaneous Signals..........................................................................78
PCI Express*-Based Interface Signals ..................................................................79
Datasheet, Volume 1
5
6.5
6.6
6.7
6.8
6.9
Embedded DisplayPort* (eDP) Signals ................................................................. 79
Intel® Flexible Display Interface (Intel® FDI) Signals............................................. 80
Direct Media Interface (DMI) Signals ................................................................... 80
Phase Lock Loop (PLL) Signals............................................................................ 80
Test Access Points (TAP) Signals......................................................................... 81
6.10 Error and Thermal Protection Signals................................................................... 81
6.11 Power Sequencing Signals.................................................................................. 82
6.12 Processor Power Signals .................................................................................... 82
6.13 Sense Signals................................................................................................... 83
6.14 Ground and Non-Critical to Function (NCTF) Signals .............................................. 83
6.15 Future Compatibility Signals............................................................................... 84
6.16 Processor Internal Pull-Up / Pull-Down Resistors ................................................... 84
7
Electrical Specifications .......................................................................................... 85
7.1
7.2
Power and Ground Pins...................................................................................... 85
Decoupling Guidelines ....................................................................................... 85
7.2.1 Voltage Rail Decoupling .......................................................................... 85
7.2.2 PLL Power Supply .................................................................................. 85
Voltage Identification (VID)................................................................................ 86
System Agent (SA) VCC VID ............................................................................... 90
Reserved or Unused Signals ............................................................................... 90
Signal Groups................................................................................................... 91
Test Access Port (TAP) Connection ...................................................................... 93
Storage Condition Specifications ......................................................................... 93
DC Specifications.............................................................................................. 94
7.9.1 Voltage and Current Specifications ........................................................... 95
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10 Platform Environmental Control Interface (PECI) DC Specifications.........................101
7.10.1 PECI Bus Architecture............................................................................101
7.10.2 PECI DC Characteristics.........................................................................102
7.10.3 Input Device Hysteresis.........................................................................103
8
9
Processor Pin and Signal Information ....................................................................105
8.1
8.2
Processor Pin Assignments................................................................................105
Package Mechanical Information ........................................................................155
DDR Data Swizzling................................................................................................167
6
Datasheet, Volume 1
Figures
1-1 Mobile Platform System Block Diagram Example .........................................................12
2-1 Intel® Flex Memory Technology Operation..................................................................23
2-2 PCI Express* Layering Diagram ................................................................................25
2-3 Packet Flow through the Layers ................................................................................26
2-4 PCI Express* Related Register Structures in the Processor............................................27
2-5 PCI Express* Typical Operation 16 lanes Mapping .......................................................28
2-6 Processor Graphics Controller Unit Block Diagram........................................................29
2-7 Processor Display Block Diagram...............................................................................32
4-1 Power States..........................................................................................................43
4-2 Idle Power Management Breakdown of the Processor Cores ..........................................47
4-3 Thread and Core C-State Entry and Exit.....................................................................47
4-4 Package C-State Entry and Exit ................................................................................51
5-1 Package Power Control ............................................................................................63
5-2 Frequency and Voltage Ordering ...............................................................................69
7-1 Example for PECI Host-clients Connection ................................................................ 102
7-2 Input Device Hysteresis......................................................................................... 103
8-1 rPGA988B (Socket-G2) Pinmap (Top View, Upper-Left Quadrant) ................................ 106
8-2 rPGA988B (Socket-G2) Pinmap (Top View, Upper-Right Quadrant) .............................. 107
8-3 rPGA988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant) ................................ 108
8-4 rPGA988B (Socket-G2) Pinmap (Top View, Lower-Right Quadrant) .............................. 109
8-5 BGA1224 Ballmap (Top View, Upper-Left Quadrant) .................................................. 121
8-6 BGA1224 Ballmap (Top View, Upper-Right Quadrant) ................................................ 122
8-7 BGA1224 Ballmap (Top View, Lower-Left Quadrant) .................................................. 123
8-8 BGA1224 Ballmap (Top View, Lower-Right Quadrant) ................................................ 124
8-9 BGA1023 Ballmap (Top View, Upper-Left Quadrant) .................................................. 140
8-10 BGA1023 Ballmap (Top View, Upper-Right Quadrant) ................................................ 141
8-11 BGA1023 Ballmap (Top View, Lower-Left Quadrant) .................................................. 142
8-12 BGA1023 Ballmap (Top View, Lower-Right Quadrant) ................................................ 143
8-13 Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 1 of 2) ............................... 155
8-14 Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 2 of 2) ............................... 156
8-15 Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 1 of 2) ............................... 157
8-16 Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 2 of 2) ............................... 158
8-17 Processor BGA1023 2C (GT2) Mechanical Package (Sheet 1 of 2) ................................ 159
8-18 Processor BGA1023 2C (GT2) Mechanical Package (Sheet 2 of 2) ................................ 160
8-19 Processor BGA1224 4C (GT2) Mechanical Package (Sheet 1 of 2) ................................ 161
8-20 Processor BGA1224 4C (GT2) Mechanical Package (Sheet 2 of 2) ................................ 162
8-21 Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 1 of 2) ............................... 163
8-22 Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 2 of 2) ............................... 164
8-23 Processor BGA1023 2C (GT1) Mechanical Package (Sheet 1 of 2) ................................ 165
8-24 Processor BGA1023 2C (GT1) Mechanical Package (Sheet 2 of 2) ................................ 166
Tables
1-1 PCI Express* Supported Configurations in Mobile Products...........................................14
1-2 Terminology ..........................................................................................................18
1-3 Related Documents ................................................................................................20
2-1 Supported SO-DIMM Module Configurations...............................................................21
2-2 DDR3 System Memory Timing Support......................................................................22
2-3 Reference Clock .....................................................................................................34
4-1 System States .......................................................................................................44
4-2 Processor Core / Package State Support....................................................................44
4-3 Integrated Memory Controller States ........................................................................44
4-4 PCI Express* Link States.........................................................................................45
4-5 Direct Media Interface (DMI) States..........................................................................45
Datasheet, Volume 1
7
4-6 Processor Graphics Controller States ........................................................................ 45
4-7 G, S, and C State Combinations............................................................................... 45
4-8 D, S, and C State Combination ................................................................................ 46
4-9 Coordination of Thread Power States at the Core Level ............................................... 48
4-10 P_LVLx to MWAIT Conversion.................................................................................. 48
4-11 Coordination of Core Power States at the Package Level.............................................. 51
4-12 Targeted Memory State Conditions........................................................................... 56
5-1 Thermal Design Power (TDP) Specifications............................................................... 65
5-2 Junction Temperature Specification .......................................................................... 65
5-3 Package Turbo Parameters...................................................................................... 65
5-4 Idle Power Specifications ........................................................................................ 67
6-1 Signal Description Buffer Types ............................................................................... 75
6-2 Memory Channel A Signals...................................................................................... 76
6-3 Memory Channel B Signals...................................................................................... 77
6-4 Memory Reference and Compensation ...................................................................... 77
6-5 Reset and Miscellaneous Signals .............................................................................. 78
6-6 PCI Express* Graphics Interface Signals ................................................................... 79
6-7 Embedded DisplayPort* Signals............................................................................... 79
6-8 Intel® Flexible Display Interface (Intel® FDI) ............................................................ 80
6-9 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface....................... 80
6-10 Phase Lock Loop (PLL) Signals................................................................................. 80
6-11 Test Access Points (TAP) Signals.............................................................................. 81
6-12 Error and Thermal Protection Signals........................................................................ 81
6-13 Power Sequencing Signals ...................................................................................... 82
6-14 Processor Power Signals ......................................................................................... 82
6-15 Sense Signals ....................................................................................................... 83
6-16 Ground and Non-Critical to Function (NCTF) Signals ................................................... 83
6-17 Future Compatibility Signals.................................................................................... 84
6-18 Processor Internal Pull-Up / Pull-Down Resistors ........................................................ 84
7-1 IMVP7 Voltage Identification Definition ..................................................................... 87
7-2 VCCSA_VID configuration ....................................................................................... 90
7-3 Signal Groups1...................................................................................................... 91
7-4 Storage Condition Ratings....................................................................................... 94
7-5 Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications.......... 95
7-6 Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications........................ 96
7-7 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications....................... 97
7-8 System Agent (VCCSA) Supply DC Voltage and Current Specifications............................ 97
7-9 Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications ........................... 97
7-10 Processor Graphics (VAXG) Supply DC Voltage and Current Specifications ..................... 98
7-11 DDR3 Signal Group DC Specifications ....................................................................... 99
7-12 Control Sideband and TAP Signal Group DC Specifications..........................................100
7-13 PCI Express* DC Specifications...............................................................................100
7-14 Embedded DisplayPort* DC Specifications................................................................101
7-15 PECI DC Electrical Limits........................................................................................102
8-1 rPGA988B Processor Pin List by Pin Name ................................................................110
8-2 BGA1224 Processor Ball List by Ball Name................................................................125
8-3 BGA1023 Processor Ball List by Ball Name................................................................144
9-1 DDR Data Swizzling Table – Channel A ....................................................................168
9-2 DDR Data Swizzling Table – Channel B ....................................................................169
8
Datasheet, Volume 1
Revision History
Revision
Number
Description
Date
001
• Initial Release
January 2011
®
• Added Intel Core™ i7-2677M, i7-2637M, and i5-2557M
processors
002
June 2011
®
®
• Added Intel Celeron B800 and 847 processors
®
®
003
004
• Added Intel Celeron 787 and 857 processors
July 2011
July 2011
®
®
• Added Intel Celeron B710 processor
®
• Added Intel Core™ i7-2960XM, i7-2860QM, i7-2760QM, and
September
2011
i7-2640M processors
005
006
®
®
• Added Intel Celeron B840 processor
September
2012
®
®
• Added Intel Celeron B830, 887 processors
§ §
Datasheet, Volume 1
9
10
Datasheet, Volume 1
Introduction
1 Introduction
The 2nd Generation Intel® Core™ processor family mobile and Intel® Celeron®
processor family mobile are the next generation of 64-bit, multi-core mobile processor
built on 32- nanometer process technology. Based on a new micro-architecture, the
processor is designed for a two-chip platform. The two-chip platform consists of a
processor and Platform Controller Hub (PCH). The platform enables higher
performance, lower cost, easier validation, and improved x-y footprint. The processor
includes Integrated Display Engine, Processor Graphics and Integrated Memory
Controller and is designed for mobile platforms. The processor comes with either 6 or
12 Processor Graphics execution units (EU). The processor may be offered in a
rPGA988B, BGA1224 or BGA1023 package. Figure 1-1 shows an example platform
block diagram.
This document provides DC electrical specifications, signal integrity, differential
signaling specifications, pinout and signal definitions, interface functional descriptions,
thermal specifications, and additional feature information pertinent to the
implementation and operation of the processor on its respective platform.
Note:
Note:
Note:
Throughout this document, the 2nd Generation Intel® Core™ processor family mobile
and Intel® Celeron® processor family mobile may be referred to simply as “processor”.
Throughout this document, the Intel® Core™ i7 Extreme Edition mobile processor
series refers to the Intel® Core™ i7-2920XM processor.
Throughout this document, the Intel® Core™ i7 mobile processor series refers to the
Intel® Core™ i7-2960XM, i7-2860QM, i7-2820QM, i7-2760QM, i7-2720QM, i7-2677M,
i7-2640M, i7-2637M, and i7-2620M processors.
Note:
Note:
Note:
Note:
Throughout this document, the Intel® Core™ i5 mobile processor series refers to the
Intel® Core™ i5-2557M, i5-2540M, and i5-2520M processors.
Throughout this document, the Intel® Celeron® processor family mobile refers to the
Intel® Celeron® B830, B800, B710, 887, 857, 847, B840, and 787 processors.
Throughout this document, the Intel® 6 Series Chipset Platform Controller Hub may
also be referred to as “PCH”.
Some processor features are not available on all platforms. Refer to the processor
specification update for details.
Datasheet, Volume 1
11
Introduction
Figure 1-1. Mobile Platform System Block Diagram Example
12
Datasheet, Volume 1
Introduction
1.1
Processor Feature Details
• Four or two execution cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data second-level cache (L2) for each core
• Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores
1.1.1
Supported Technologies
• Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)
• Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel®
Architecture (Intel® VT-x)
• Intel® Active Management Technology 7.0 (Intel® AMT 7.0)
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Hyper-Threading Technology (Intel® HT Technology)
• Intel® 64 Architecture
• Execute Disable Bit
• Intel® Turbo Boost Technology
• Intel® Advanced Vector Extensions (Intel® AVX)
• Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
• PCLMULQDQ Instruction
1.2
Interfaces
1.2.1
System Memory Support
• Two channels of DDR3 memory with a maximum of one SO-DIMM per channel
• Single-channel and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory DDR3 data transfer rates of 1066 MT/s, 1333 MT/s, and 1600 MT/s
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• Non-ECC, unbuffered DDR3 SO-DIMMs only
• Theoretical maximum memory bandwidth of
— 17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s
— 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s
• 1Gb, 2Gb, and 4Gb DDR3 DRAM technologies are supported for x8 and x16 devices
— Using 4Gb device technologies, the largest memory capacity possible is 16 GB,
assuming dual-channel mode with two x8, dual-ranked, un-buffered, non-ECC,
SO-DIMM memory configuration.
• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
Datasheet, Volume 1
13
Introduction
• Memory organizations
— Single-channel modes
— Dual-channel modes - Intel® Flex Memory Technology:
- Dual-channel symmetric (Interleaved)
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Asynchronous ODT
• Intel® Fast Memory Access (Intel® FMA)
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
1.2.2
PCI Express*
• PCI Express* port(s) are fully-compliant with the PCI Express Base Specification,
Revision 2.0.
• Processor with mobile PCH supported configurations
Table 1-1.
PCI Express* Supported Configurations in Mobile Products
Configuration
Organization
Mobile
1x8
2x4
Graphics
I/O
1
2
3
2x8
Graphics, I/O
Graphics, I/O
1x16
• The port may negotiate down to narrower widths
— Support for x16/x8/x4/x1 widths for a single PCI Express mode
• 2.5 GT/s and 5.0 GT/s PCI Express* frequencies are supported
• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1
• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism; accessing the device configuration
space in a flat memory mapped fashion
• Automatic discovery, negotiation, and training of link out of reset
14
Datasheet, Volume 1
Introduction
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0
— DMI -> PCI Express* Port 0
— DMI -> PCI Express* Port 1
— PCI Express* Port 0 -> DMI
— PCI Express* Port 1 -> DMI
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• PCI Express* reference clock is 100-MHz differential clock
• Power Management Event (PME) functions
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Static lane numbering reversal
— Does not support dynamic lane reversal, as defined (optional) by the PCI
Express Base Specification.
• Supports Half Swing “low-power/low-voltage” mode.
Note:
The processor does not support PCI Express* Hot-Plug.
1.2.3
Direct Media Interface (DMI)
• DMI 2.0 support
• Four lanes in each direction
• 5 GT/s point-to-point DMI interface to PCH is supported
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4
• Shares 100-MHz PCI Express* reference clock
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
Datasheet, Volume 1
15
Introduction
• Supports the following traffic types to or from the PCH
— DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage”
1.2.4
1.2.5
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The processors support the PECI 3.0
Specification.
Processor Graphics
• The Processor Graphics contains a refresh of the sixth generation graphics core
enabling substantial gains in performance and lower power consumption. Up to 12
EU Support.
• Next Generation Intel Clear Video Technology HD support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience.
— Encode/transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray disc S3D content using HDMI (V.1.4 with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 7, XP, Windows Vista*, OSX, Linux OS Support
• DX10.1, DX10, DX9 support
• OGL 3.0 support
16
Datasheet, Volume 1
Introduction
1.2.6
Embedded DisplayPort* (eDP)
• Stand alone dedicated port (unlike previous generation processor that shared pins
with PCIe interface)
®
®
1.2.7
Intel Flexible Display Interface (Intel FDI)
• For SKUs with graphics, Intel FDI carries display traffic from the Processor Graphics
in the processor to the legacy display connectors in the PCH
• Based on DisplayPort standard
• Two independent links – one for each display pipe
• Four unidirectional downstream differential transmitter pairs
— Scalable down to 3X, 2X, or 1X based on actual display bandwidth
requirements
— Fixed frequency 2.7 GT/s data rate
• Two sideband signals for Display synchronization
— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)
• One Interrupt signal used for various interrupts from the PCH
— FDI_INT signal shared by both Intel FDI Links
• PCH supports end-to-end lane reversal across both links
• Common 100-MHz reference clock
1.3
Power Management Support
1.3.1
Processor Core
• Full support of Advanced Configuration and Power Interface (ACPI) C-states as
implemented by the following processor C-states
— C0, C1, C1E, C3, C6, C7
• Enhanced Intel SpeedStep® Technology
1.3.2
1.3.3
System
• S0, S3, S4, S5
Memory Controller
• Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))
• Dynamic power-down
1.3.4
1.3.5
PCI Express*
• L0s and L1 ASPM power management capability
Direct Media Interface (DMI)
• L0s and L1 ASPM power management capability
Datasheet, Volume 1
17
Introduction
1.3.6
Processor Graphics Controller
• Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR
• Intel® Graphics Performance Modulation Technology (Intel® GPMT)
• Intel Smart 2D Display Technology (Intel S2DDT)
• Graphics Render C-State (RC6)
• Intel Seamless Display Refresh Rate Switching with Embedded DisplayPort*
1.4
Thermal Management Support
• Digital Thermal Sensor
• Intel Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Open and Closed Loop Throttling
• Memory Thermal Throttling
• External Thermal Sensor (TS-on-DIMM and TS-on-Board)
• Render Thermal Throttling
• Fan speed control with DTS
1.5
Package
• The processor is available on two packages:
— A 37.5 x 37.5 mm rPGA package (rPGA988B)
— A 31 x 24 mm BGA package (BGA1023 or BGA1224)
1.6
Terminology
Table 1-2.
Terminology (Sheet 1 of 3)
Term
Description
ACPI
BLT
Advanced Configuration and Power Interface
Block Level Transfer
CRT
DDR3
DMA
DMI
DP
Cathode Ray Tube
Third-generation Double Data Rate SDRAM memory technology
Direct Memory Access
Direct Media Interface
DisplayPort*
DTS
eDP*
Digital Thermal Sensor
Embedded DisplayPort*
Enhanced Intel
Technology that provides power management capabilities to laptops.
SpeedStep® Technology
EU
Execution Unit
18
Datasheet, Volume 1
Introduction
Table 1-2.
Terminology (Sheet 2 of 3)
Term
Description
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
Execute Disable Bit
IMC
Integrated Memory Controller
Intel® 64 Technology
Intel® DPST
Intel® FDI
64-bit memory extensions to the IA-32 architecture
Intel® Display Power Saving Technology
Intel® Flexible Display Interface
Intel® TXT
Intel® Trusted Execution Technology
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
Intel® Virtualization
Technology
Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
Intel® VT-d
IOV
I/O Virtualization
ITPM
LCD
Integrated Trusted Platform Module
Liquid Crystal Display
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
LVDS
NCTF
Non-Critical to Function. NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Platform Controller Hub. The new, 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCH
PECI
Platform Environment Control Interface
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
PEG
Processor
Processor Core
The 64-bit, single-core or multi-core component (package).
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Processor Graphics
Intel® Processor Graphics
A unit of DRAM corresponding four to eight devices in parallel. These devices are
usually, but not always, mounted on a single side of a SO-DIMM.
Rank
SCI
System Control Interrupt. Used in ACPI protocol.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
Storage Conditions
TAC
TAP
Thermal Averaging Constant.
Test Access Point
TDP
VAXG
Thermal Design Power.
Graphics core power supply.
Datasheet, Volume 1
19
Introduction
Table 1-2.
Terminology (Sheet 3 of 3)
Term
Description
VCC
Processor core power supply.
High Frequency I/O logic power supply
PLL power supply
VCCIO
VCCPLL
System Agent (memory controller, DMI, PCIe controllers, and display engine)
power supply
VCCSA
VDDQ
VLD
VSS
x1
DDR3 power supply.
Variable Length Decoding.
Processor ground.
Refers to a Link or Port with one Physical Lane.
Refers to a Link or Port with sixteen Physical Lanes.
Refers to a Link or Port with four Physical Lanes.
Refers to a Link or Port with eight Physical Lanes.
x16
x4
x8
1.7
Related Documents
Refer to Table 1-3 for additional information.
Table 1-3.
Related Documents
Document
Document Number/ Location
2nd Generation Intel® Core™ Processor Family Mobile and Intel®
Celeron® Processor Family Mobile Datasheet, Volume 2
www.intel.com/Assets/PDF/datas
heet/324803.pdf
2nd Generation Intel® Core™ Processor Family Mobile and Intel®
Celeron® Processor Family Mobile Specification Update
www.intel.com/Assets/PDF/specu
pdate/324693.pdf
Intel® 6 Series Chipset and Intel® C200 Series Chipset Datasheet
www.intel.com/Assets/PDF/datas
heet/324645.pdf
Intel® 6 Series Chipset and Intel® C200 Series Chipset Thermal
Mechanical Specifications and Design Guidelines
www.intel.com/Assets/PDF/desig
nguide/324647.pdf
Advanced Configuration and Power Interface Specification 3.0
PCI Local Bus Specification 3.0
http://www.acpi.info/
http://www.pcisig.com/specifica-
tions
Intel® TXT Measured Launched Environment Developer’s Guide
Intel® 64 Architecture x2APIC Specification
http://www.intel.com/technology
/security
http://www.intel.com/products/pr
ocessor/manuals/
PCI Express* Base Specification 2.0
DDR3 SDRAM Specification
http://www.pcisig.com
http://www.jedec.org
http://www.vesa.org
DisplayPort* Specification
Intel® 64 and IA-32 Architectures Software Developer's Manuals
http://www.intel.com/products/pr
ocessor/manuals/index.htm
Volume 1: Basic Architecture
253665
253666
253667
253668
253669
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
§ §
20
Datasheet, Volume 1
Interfaces
2 Interfaces
This chapter describes the interfaces supported by the processor.
2.1
System Memory Interface
2.1.1
System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two
independent, 64-bit wide channels each accessing one DIMM. It supports a maximum
of one unbuffered non-ECC DDR3 DIMM per-channel; thus, allowing up to two device
ranks per-channel.
• DDR3 Data Transfer Rates
— 1066 MT/s (PC3-8500), 1333 MT/s (PC3-10600), 1600 MT/s (PC-12800)
• DDR3 SO-DIMM Modules
— Raw Card A – Dual Ranked x16 unbuffered non-ECC
— Raw Card B – Single Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
— Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC
• DDR3 DRAM Device Technology
Standard 1-Gb, 2-Gb, and 4-Gb technologies and addressing are supported for x16 and
x8 devices. There is no support for memory modules with different technologies or
capacities on opposite sides of the same memory module. If one side of a memory
module is populated, the other side is either identical or empty.
Table 2-1.
Supported SO-DIMM Module Configurations1,2
# of
Raw
Card
Version
# of
DRAM
Devices
# of
#ofBanks
Inside
DRAM
DIMM
Capacity
DRAM Device
Technology
DRAM
Organization
Physical
Device
Ranks
Row/Col
Page Size
Address Bits
1 GB
2 GB
1 GB
2 GB
512 MB
1 GB
2 GB
4 GB
8 GB
1 Gb
2 Gb
1 Gb
2 Gb
1 Gb
2 Gb
1 Gb
2 Gb
4 Gb
64 M x 16
128 M x 16
128 M x 8
256 M x 8
64 M x 16
128 M x 16
128 M x 8
256 M x 8
512 M x 8
8
8
2
2
1
1
1
1
2
2
2
13/10
14/10
14/10
15/10
13/10
14/10
14/10
15/10
16/ 10
8
8
8
8
8
8
8
8
8
8K
8K
8K
8K
8K
8K
8K
8K
8K
A
B
C
8
8
4
4
16
16
16
F
Notes:
1.
2.
System memory configurations are based on availability and are subject to change.
Interface does not support ULV/LV memory modules or ULV/LV DIMMs.
Datasheet, Volume 1
21
Interfaces
2.1.2
System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
Table 2-2.
DDR3 System Memory Timing Support
Transfer
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
CMD
Mode
Segment
Rate
Notes1
(MT/s)
1066
1333
1600
7
9
7
9
7
9
6
7
8
6
6
7
1n/2n
1n/2n
1n/2n
1n/2n
1n/2n
1n/2n
Extreme
Edition (XE)
and
Quad Core SV
11
7
11
7
11
7
Dual Core SV,
Low voltage
and Ultra low
voltage
1066
1333
8
8
8
9
9
9
Notes:
1.
System memory timing support is based on availability and is subject to change.
2.1.3
2.1.3.1
2.1.3.2
System Memory Organization Modes
The IMC supports two memory organization modes—single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
®
Dual-Channel Mode – Intel Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a
symmetric and an asymmetric zone. The symmetric zone starts at the lowest address
in each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note:
Channels A and B can be mapped for physical channels 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
22
Datasheet, Volume 1
Interfaces
Figure 2-1. Intel® Flex Memory Technology Operation
2.1.3.2.1
Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note:
The DRAM device technology and width may vary from one channel to the other.
2.1.4
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one DIMM connector
per channel. The usage of DIMM modules with different latencies is allowed. For dual-
channel modes, both channels must have an DIMM connector populated. For single-
channel mode, only a single-channel can have a DIMM connector populated.
Datasheet, Volume 1
23
Interfaces
®
2.1.5
Technology Enhancements of Intel Fast Memory Access
®
(Intel FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2
2.1.5.3
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6
2.1.7
Memory Type Range Registers (MTRRs) Enhancement
The processor has 2 additional MTRRs (total 10 MTRRs). These additional MTRRs are
specially important in supporting larger system memory beyond 4 GB.
Data Scrambling
The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the
data bus. Past experience has demonstrated that traffic on the data bus is not random
and can have energy concentrated at specific spectral harmonics creating high di/dt
that is generally limited by data patterns that excite resonance between the package
inductance and on-die capacitances. As a result, the memory controller uses a data
scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce
the impact of any excessive di/dt.
2.1.8
DRAM Clock Generation
Every supported DIMM has two differential clock pairs. There are a total of four clock
pairs driven directly by the processor to two DIMMs.
24
Datasheet, Volume 1
Interfaces
2.2
PCI Express* Interface
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
The processor has one PCI Express controller that can support one external x16 PCI
Express Graphics Device. The primary PCI Express Graphics port is referred to as
PEG 0.
2.2.1
PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI
Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction that provides a 250 MB/s communications channel in each direction
(500 MB/s total). That is close to twice the data rate of classic PCI. The fact that
8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The external graphics ports support Gen2 speed as well. At 5.0 GT/s,
Gen 2 operation results in twice as much bandwidth per lane as compared to Gen 1
operation. When operating with two PCIe controllers, each controller can be operating
at either 2.5 GT/s or 5.0 GT/s.
The PCI Express architecture is specified in three layers—Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-2 for the PCI Express Layering Diagram.
Figure 2-2. PCI Express* Layering Diagram
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
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through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side, the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 2-3. Packet Flow through the Layers
2.2.1.1
2.2.1.2
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets that are used for Link management functions.
2.2.1.3
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
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2.2.2
PCI Express* Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
Figure 2-4. PCI Express* Related Register Structures in the Processor
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(that consists of the remaining configuration space). The PCI-compatible region can be
accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for
details of both the PCI-compatible and PCI Express Enhanced configuration
mechanisms and transaction rules.
2.2.3
PCI Express Graphics
The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port. The
PEG port is compliant with the PCI Express Base Specification, Revision 2.0.
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2.2.4
PCI Express* Lanes Connection
Figure 2-5 demonstrates the PCIe lanes mapping.
Figure 2-5. PCI Express* Typical Operation 16 lanes Mapping
2.3
Direct Media Interface (DMI)
Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported.
Note:
Only DMI x4 configuration is supported.
2.3.1
DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
2.3.2
Processor / PCH Compatibility Assumptions
®
The processor is compatible with the Intel 6 Series Chipset PCH. The processor is
not compatible with any previous PCH products.
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2.3.3
DMI Link Down
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This link behavior is controlled
by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
2.4
Processor Graphics Controller (GT)
New Graphics Engine Architecture includes 3D compute elements, Multi-format
hardware-assisted decode/encode Pipeline, and Mid-Level Cache (MLC) for superior
high definition playback, video quality, and improved 3D performance and Media.
Display Engine in the Uncore handles delivering the pixels to the screen. GSA (Graphics
in System Agent) is the primary Channel interface for display memory accesses and
“PCI-like” traffic in and out.
Figure 2-6. Processor Graphics Controller Unit Block Diagram
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2.4.1
3D and Video Engines for Graphics Processing
The 3D graphics pipeline architecture simultaneously operates on different primitives or
on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the
following performance and power-management enhancements:
• Up to 12 Execution units (EUs)
• Hierarchal-Z
• Video quality enhancements
2.4.1.1
3D Engine Execution Units
• Supports up to 12 EUs. The EUs perform 128-bit wide execution per clock.
• Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel
processing.
2.4.1.2
3D Pipeline
2.4.1.2.1
Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been
included to better support legacy D3D APIs as well as SGI OpenGL*.
2.4.1.2.2
2.4.1.2.3
Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from the
VF unit, in the order received.
Geometry Shader (GS) Stage
The GS stage receives inputs from the VS stage. Compiled application-provided GS
programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.
2.4.1.2.4
2.4.1.2.5
Clip Stage
The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming
vertices, and accepts/rejects 3D objects based on its Clip algorithm.
Strips and Fans (SF) Stage
The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to some
extent.
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2.4.1.2.6
Windower/IZ (WIZ) Stage
The WIZ unit performs an early depth test, which removes failing pixels and eliminates
unnecessary processing overhead.
The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels. The Windower is also capable of performing dithering, whereby the illusion of a
higher resolution when using low-bpp channels in color buffers is possible. Color
dithering diffuses the sharp color bands seen on smooth-shaded objects.
2.4.1.3
2.4.1.4
Video Engine
The Video Engine handles the non-3D (media/video) applications. It includes support
for VLD and MPEG2 decode in hardware.
2D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of
2D instructions. To take advantage of the 3D during engine’s functionality, some BLT
functions make use of the 3D renderer.
2.4.1.4.1
2.4.1.4.2
Processor Graphics VGA Registers
The 2D registers consists of original VGA registers and others to support graphics
modes that have color depths, resolutions, and hardware acceleration features that go
beyond the original VGA standard.
Logical 128-Bit Fixed BLT and 256 Fill Engine
This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The
128-bit BLT engine provides hardware acceleration of block transfers of pixel data for
many common Windows operations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data alignment
• To perform logical operations (raster ops)
The rectangular block of data does not change, as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per
pixel.
The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTs
can be either opaque or transparent. Opaque transfers move the data specified to the
destination. Transparent transfers compare destination color to source color and write
according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the BLT engine specifies which area in
memory to begin the BLT transfer. Hardware is included for all 256 raster operations
(source, pattern, and destination) defined by Microsoft, including transparent BLT.
The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting
software to set up instruction buffers and use batch processing. The BLT engine can
perform hardware clipping during BLTs.
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2.4.2
Processor Graphics Display
The Processor Graphics controller display pipe can be broken down into three
components:
• Display Planes
• Display Pipes
• Embedded DisplayPort* and Intel® FDI
Figure 2-7. Processor Display Block Diagram
2.4.2.1
Display Planes
A display plane is a single displayed surface in memory and contains one image
(desktop, cursor, overlay). It is the portion of the display hardware logic that defines
the format and location of a rectangular region of memory that can be displayed on
display output device and delivers that data to a display pipe. This is clocked by the
Core Display Clock.
2.4.2.1.1
2.4.2.1.2
Planes A and B
Planes A and B are the main display planes and are associated with Pipes A and B
respectively. The two display pipes are independent, allowing for support of two
independent display streams. They are both double-buffered, which minimizes latency
and improves visual quality.
Sprite A and B
Sprite A and Sprite B are planes optimized for video decode, and are associated with
Planes A and B respectively. Sprite A and B are also double-buffered.
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2.4.2.1.3
Cursors A and B
Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,
and are associated with Planes A and B respectively. These planes support resolutions
up to 256 x 256 each.
2.4.2.1.4
2.4.2.2
Video Graphics Array (VGA)
VGA is used for boot, safe mode, legacy games, etc. It can be changed by an
application without OS/driver notification, due to legacy requirements.
Display Pipes
The display pipe blends and synchronizes pixel data received from one or more display
planes and adds the timing of the display output device upon which the image is
displayed. This is clocked by the Display Reference clock inputs.
The display pipes A and B operate independently of each other at the rate of 1 pixel per
clock. They can attach to any of the display ports. Each pipe sends display data to the
PCH over the Intel Flexible Display Interface (Intel FDI).
2.4.2.3
2.4.2.4
Display Ports
The display ports consist of output logic and pins that transmit the display data to the
associated encoding logic and send the data to the display device (that is, LVDS,
HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are
now repartitioned and driven from the PCH with the exception of the DisplayPort.
Embedded DisplayPort*
The Processor Graphics supports the Embedded DisplayPort* (eDP) interface, intended
for display devices that are integrated into the system (such as laptop LCD panel).
The DisplayPort (abbreviated DP) is different than the generic term display port. The
DisplayPort specification is a VESA standard. DisplayPort consolidates internal and
external connection methods to reduce device complexity, support cross industry
applications, and provide performance scalability. The eDP interface supports link-
speeds of 1.62 Gbps and 2.7 Gbps on 1, 2, or 4 data lanes. The eDP supports -0.5%
SSC and non-SSC clock settings.
®
®
2.4.3
Intel Flexible Display Interface (Intel FDI)
The Intel Flexible Display Interface (Intel® FDI) is a proprietary link for carrying display
traffic from the Processor Graphics controller to the PCH display I/Os. Intel® FDI
supports two independent channels—one for pipe A and one for pipe B.
• Each channel has four transmit (Tx) differential pairs used for transporting pixel
and framing data from the display engine.
• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS
signaling).
• One display interrupt line input (1-V CMOS signaling).
• Intel® FDI may dynamically scalable down to 2X or 1X based on actual display
bandwidth requirements.
• Common 100-MHz reference clock.
• Each channel transports at a rate of 2.7 Gbps.
• PCH supports end-to-end lane reversal across both channels (no reversal support
required in the processor).
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2.4.4
Multi-Graphics Controller Multi-Monitor Support
The processor supports simultaneous use of the Processor Graphics Controller (GT) and
a x16 PCI Express Graphics (PEG) device.
The processor supports a maximum of 2 displays connected to the PEG card in parallel
with up to 2 displays connected to the processor and PCH.
Note:
When supporting Multi Graphics controllers Multi-Monitors, “drag and drop” between
monitors and the 2x8 PEG is not supported.
2.5
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (processor) and a PECI master. The processor implements a PECI interface
to:
• Allow communication of processor thermal and other information to the PECI
master.
• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.
2.6
Interface Clocking
2.6.1
Internal Clocking Requirements
Table 2-3.
Reference Clock
Reference Input Clock
Input Frequency
Associated PLL
BCLK/BCLK#
DPLL_REF_CLK/DPLL_REF_CLK#
100 MHz
120 MHz
Processor/Memory/Graphics/PCIe/DMI/FDI
Embedded DisplayPort (eDP)
§ §
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Technologies
3 Technologies
This chapter provides a high-level description of Intel technologies implemented in the
processor.
The implementation of the features may vary between the processor SKUs.
Details on the different technologies of Intel processors and other relevant external
notes are located at the Intel technology web site: http://www.intel.com/technology/
3.1
Intel® Virtualization Technology (Intel® VT)
Intel Virtualization Technology (Intel® VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets. Intel Virtualization Technology (Intel VT-x) added hardware support in the
processor to improve the virtualization performance and robustness. Intel Virtualization
Technology for Directed I/O (Intel VT-d) adds chipset hardware implementation to
support and improve I/O virtualization performance and robustness.
Intel VT-x specifications and functional descriptions are included in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:
http://www.intel.com/products/processor/manuals/index.htm
The Intel VT-d specification and other VT documents can be referenced at:
http://www.intel.com/technology/virtualization/index.htm
®
®
3.1.1
Intel Virtualization Technology (Intel VT) for
®
®
IA-32, Intel 64 and Intel Architecture
®
(Intel VT-x) Objectives
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual
Machine Monitor (VMM) can use Intel VT-x features to provide improved a reliable
virtualized platform. By using Intel VT-x, a VMM is:
• Robust: VMMs no longer need to use paravirtualization or binary translation. This
means that they will be able to run off-the-shelf OSs and applications without any
special steps.
• Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86
processors.
• More reliable: Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
• More secure: The use of hardware transitions in the VMM strengthens the isolation
of VMs and further prevents corruption of one VM from affecting others on the
same system.
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®
®
3.1.2
Intel Virtualization Technology (Intel VT) for
®
®
IA-32, Intel 64 and Intel Architecture
®
(Intel VT-x) Features
The processor core supports the following Intel VT-x features:
• Extended Page Tables (EPT)
— EPT is hardware assisted page table virtualization
— It eliminates VM exits from guest OS to the VMM for shadow page-table
maintenance
• Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (such as
TLBs)
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest OS after an amount
of time specified by the VMM. The VMM sets a timer value before entering a
guest
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
assurances
• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest OS from internal
(malicious software based) attack by preventing relocation of key system data
structures like IDT (interrupt descriptor table), GDT (global descriptor table),
LDT (local descriptor table), and TSS (task segment selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
®
®
3.1.3
Intel Virtualization Technology (Intel VT) for Directed
®
I/O (Intel VT-d) Objectives
The key Intel VT-d objectives are domain-based isolation and hardware-based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Virtualization allows
for the creation of one or more partitions on a single system. This could be multiple
partitions in the same operating system, or there can be multiple operating system
instances running on the same system – offering benefits such as system
consolidation, legacy migration, activity partitioning, or security.
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®
®
3.1.4
Intel Virtualization Technology (Intel VT) for Directed
®
I/O (Intel VT-d) Features
The processor supports the following Intel VT-d features:
• Memory controller and Processor Graphics comply with Intel® VT-d 1.2
specification.
• Two VT-d DMA remap engines.
— iGraphics DMA remap engine
— DMI/PEG
• Support for root entry, context entry, and default context
• 39-bit guest physical address and host physical address widths
• Support for 4K page sizes only
• Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
• Support for both leaf and non-leaf caching
• Support for boot protection of default page table
• Support for non-caching of invalid page table entries
• Support for hardware based flushing of translated but pending writes and pending
reads, on IOTLB invalidation
• Support for page-selective IOTLB invalidation
• MSI cycles (MemWr to address FEEx_xxxxh) not translated
— Translation faults result in cycle forwarding to VBIOS region (byte enables
masked for writes). Returned data may be bogus for internal agents, PEG/DMI
interfaces return unsupported request status
• Interrupt Remapping is supported
• Queued invalidation is supported.
• VT-d translation bypass address range is supported (Pass Through)
Note:
Intel VT-d Technology may not be available on all SKUs.
®
®
3.1.5
Intel Virtualization Technology (Intel VT) for Directed
®
I/O (Intel VT-d) Features Not Supported
The following features are not supported by the processor with Intel VT-d:
• No support for PCISIG endpoint caching (ATS)
• No support for Intel VT-d read prefetching/snarfing (that is, translations within a
cacheline are not stored in an internal buffer for reuse for subsequent translations).
• No support for advance fault reporting
• No support for super pages
• No support for Intel VT-d translation bypass address range (such usage models
need to be resolved with VMM help in setting up the page tables correctly)
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3.2
Intel® Trusted Execution Technology (Intel® TXT)
Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements
that provide the building blocks for creating trusted platforms.
The Intel TXT platform helps to provide the authenticity of the controlling environment
such that those wishing to rely on the platform can make an appropriate trust decision.
The Intel TXT platform determines the identity of the controlling environment by
accurately measuring and verifying the controlling software.
Another aspect of the trust decision is the ability of the platform to resist attempts to
change the controlling environment. The Intel TXT platform will resist attempts by
software processes to change the controlling environment or bypass the bounds set by
the controlling environment.
Intel TXT is a set of extensions designed to provide a measured and controlled launch
of system software that will then establish a protected environment for itself and any
additional software that it may execute.
These extensions enhance two areas:
• The launching of the Measured Launched Environment (MLE)
• The protection of the MLE from potential corruption
The enhanced platform provides these launch and control interfaces using Safer Mode
Extensions (SMX).
The SMX interface includes the following functions:
• Measured/Verified launch of the MLE
• Mechanisms to ensure the above measurement is protected and stored in a secure
location
• Protection mechanisms that allow the MLE to control attempts to modify itself
For more information, refer to the Intel® TXT Measured Launched Environment
Developer’s Guide in http://www.intel.com/technology/security.
3.3
Intel® Hyper-Threading Technology (Intel® HT
Technology)
The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology),
that allows an execution core to function as two logical processors. While some
execution resources (such as caches, execution units, and buses) are shared, each
logical processor has its own architectural state with its own set of general-purpose
registers and control registers. This feature must be enabled using the BIOS and
requires operating system support.
Intel recommends enabling Intel HT Technology with Microsoft Windows 7*, Microsoft
Windows Vista*, Microsoft Windows* XP Professional/Windows* XP Home, and
disabling Intel HT Technology using the BIOS for all previous versions of Windows
operating systems. For more information on Intel HT Technology, see
http://www.intel.com/technology/platform-technology/hyper-threading/.
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3.4
Intel® Turbo Boost Technology
Compared with previous generation products, Intel Turbo Boost Technology will
increase the ratio of application power to TDP. Thus, thermal solutions and platform
cooling that are designed to less than thermal design guidance might experience
thermal and performance issues since more applications will tend to run at the
maximum power limit for significant periods of time.
Note:
Intel Turbo Boost Technology may not be available on all SKUs.
Intel Turbo Boost Technology is a feature that allows the processor to opportunistically
and automatically run faster than its rated operating core and/or render clock
frequency when there is sufficient power headroom, and the product is within specified
temperature and current limits. The Intel Turbo Boost Technology feature is designed to
increase performance of both multi-threaded and single-threaded workloads. The
processor supports a Turbo mode where the processor can use the thermal capacity
associated with package and run at power levels higher than TDP power for short
durations. This improves the system responsiveness for short, bursty usage conditions.
The turbo feature needs to be properly enabled by BIOS for the processor to operate
with maximum performance. Since the turbo feature is configurable and dependent on
many platform design limits outside of the processor control, the maximum
performance cannot be ensured.
Turbo Mode availability is independent of the number of active cores; however, the
Turbo Mode frequency is dynamic and dependent on the instantaneous application
power load, the number of active cores, user configurable settings, operating
environment, and system design.
®
3.4.1
Intel Turbo Boost Technology Frequency
The processor's rated frequency assumes that all execution cores are active and are at
the sustained thermal design power (TDP). However, under typical operation not all
cores are active or at executing a high power workload. Therefore, most applications
are consuming less than the TDP at the rated frequency. Intel Turbo Boost Technology
takes advantage of the available TDP headroom and active cores are able to increase
their operating frequency.
To determine the highest performance frequency amongst active cores, the processor
takes the following into consideration to recalculate turbo frequency during runtime:
• The number of cores operating in the C0 state.
• The estimated core current consumption.
• The estimated package prior and present power consumption.
• The package temperature.
Any of these factors can affect the maximum frequency for a given workload. If the
power, current, or thermal limit is reached, the processor will automatically reduce the
frequency to stay with its TDP limit.
Note:
Intel Turbo Technology processor frequencies are only active if the operating system is
requesting the P0 state. For more information on P-states and C-states refer to
Chapter 4, “Power Management”.
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Technologies
®
3.4.2
Intel Turbo Boost Technology Graphics Frequency
The graphics render frequency is selected dynamically based on graphics workload
demand as permitted by the processor turbo control. The processor can optimize both
processor and Processor Graphics performance through power sharing. The processor
cores and the processor graphics core share a package power limit. If the graphics core
is not consuming enough power to reach the package power limit, the cores can
increase frequency to take advantage of the unused thermal power headroom. The
opposite can happen when the processor cores are not consuming enough power to
reach the package power limit. For the Processor Graphics, this could mean an increase
in the render core frequency (above its rated frequency) and increased graphics
performance. Both the processor core(s) and the graphics render core can increase
frequency higher than possible without power sharing.
Note:
Processor utilization of turbo graphic frequencies requires that the Intel Graphics driver
to be properly installed. Turbo graphic frequencies are not dependent on the operating
system processor P-state requests and may turbo while the processor is in any
processor P-states.
3.5
Intel® Advanced Vector Extensions (Intel® AVX)
Intel Advanced Vector Extensions (Intel AVX) is the latest expansion of the Intel
instruction set. It extends the Intel Streaming SIMD Extensions (Intel SSE) from 128-
bit vectors into 256-bit vectors. Intel AVX addresses the continued need for vector
floating-point performance in mainstream scientific and engineering numerical
applications, visual processing, recognition, data-mining/synthesis, gaming, physics,
cryptography and other areas of applications. The enhancement in Intel AVX allows for
improved performance due to wider vectors, new extensible syntax, and rich
functionality including the ability to better manage, rearrange, and sort data. For more
information on Intel AVX, see http://www.intel.com/software/avx
3.6
Intel® Advanced Encryption Standard New
Instructions (Intel® AES-NI)
The processor supports Advanced Encryption Standard New Instructions (Intel AES-NI)
that are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast
and secure data encryption and decryption based on the Advanced Encryption Standard
(AES). Intel AES-NI are valuable for a wide range of cryptographic applications; such
as, applications that perform bulk encryption/decryption, authentication, random
number generation, and authenticated encryption. AES is broadly accepted as the
standard for both government and industry applications, and is widely deployed in
various protocols.
Intel AES-NI consists of six Intel SSE instructions. Four instructions, AESENC,
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and
decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for
supporting AES, offering security, high performance, and a great deal of flexibility.
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3.6.1
PCLMULQDQ Instruction
The processor supports the carry-less multiplication instruction, PCLMULQDQ.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
3.7
Intel® 64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides a key mechanism
for interrupt delivery. This extension is intended primarily to increase processor
addressability.
Specifically, x2APIC:
• Retains all key elements of compatibility to the xAPIC architecture
— delivery modes
— interrupt and processor priorities
— interrupt sources
— interrupt destination types
• Provides extensions to scale processor addressability for both the logical and
physical destination modes
• Adds new features to enhance performance of interrupt delivery
• Reduces complexity of logical destination mode interrupt delivery on link based
architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
• Support for two modes of operation to provide backward compatibility and
extensibility for future platform innovations
— In xAPIC compatibility mode, APIC registers are accessed through a memory
mapped interface to a 4 KB page, identical to the xAPIC architecture.
— In x2APIC mode, APIC registers are accessed through Model Specific Register
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly
increased processor addressability and some enhancements on interrupt
delivery.
• Increased range of processor addressability in x2APIC mode
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt
processor addressability up to 4G-1 processors in physical destination mode. A
processor implementation of x2APIC architecture can support fewer than 32-
bits in a software transparent fashion.
— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC
ID is partitioned into two sub-fields—a 16-bit cluster ID and a 16-bit logical ID
within the cluster. Consequently, ((2^20) -16) processors can be addressed in
logical destination mode. Processor implementations can support fewer than
16 bits in the cluster ID sub-field and logical ID sub-field in a software agnostic
fashion.
Datasheet, Volume 1
41
Technologies
• More efficient MSR interface to access APIC registers
— To enhance inter-processor and self directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR based interfaces in the x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in the x2APIC mode.
• The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically,
the software semantics for using the Interrupt Command Register (ICR) and End Of
Interrupt (EOI) registers have been modified to allow for more efficient delivery
and dispatching of interrupts.
The x2APIC extensions are made available to system software by enabling the local
x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new
Operating System and a new BIOS are both needed, with special support for the
x2APIC mode.
The x2APIC architecture provides backward compatibility to the xAPIC architecture and
forward extendibility for future Intel platform innovations.
Note:
Intel x2APIC technology may not be available on all processor SKUs.
For more information, refer to the Intel® 64 Architecture x2APIC Specification at
http://www.intel.com/products/processor/manuals/
§ §
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4 Power Management
This chapter provides information on the following power management topics:
• Advanced Configuration and Power Interface (ACPI) States
• Processor Core
• Integrated Memory Controller (IMC)
• PCI Express*
• Direct Media Interface (DMI)
• Processor Graphics Controller
Figure 4-1. Power States
Datasheet, Volume 1
43
Power Management
4.1
Advanced Configuration and Power Interface
(ACPI) States Supported
The ACPI states supported by the processor are described in this section.
4.1.1
System States
Table 4-1.
System States
State
Description
G0/S0
Full On
G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor).
G1/S4
G2/S5
G3
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
Soft off. All power lost (except wakeup on PCH). Total reboot.
Mechanical off. All power (AC and battery) removed from system.
4.1.2
Processor Core / Package Idle States
Table 4-2.
Processor Core / Package State Support
State
Description
C0
C1
Active mode, processor executing code
AutoHALT state
C1E
AutoHALT state with lowest frequency and voltage operating point
Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache to the L3
shared cache. Clocks are shut off to each core.
C3
C6
C7
Execution cores in this state save their architectural state before removing core voltage.
Execution cores in this state behave similarly to the C6 state. If all execution cores request C7,
L3 cache ways are flushed until it is cleared.
4.1.3
Integrated Memory Controller States
Table 4-3.
Integrated Memory Controller States
State
Description
Power up
CKE asserted. Active mode
CKE de-asserted (not self-refresh) with all banks closed
Pre-charge
Power-down
Active Power- CKE de-asserted (not self-refresh) with minimum one bank active
Down
Self-Refresh
CKE de-asserted using device self-refresh
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4.1.4
PCI Express* Link States
Table 4-4.
PCI Express* Link States
State
Description
L0
L0s
L1
Full on – Active transfer state
First Active Power Management low power state – Low exit latency
Lowest Active Power Management – Longer exit latency
Lowest power state (power-off) – Longest exit latency
L3
4.1.5
Direct Media Interface (DMI) States
Table 4-5.
Direct Media Interface (DMI) States
State
Description
L0
L0s
L1
Full on – Active transfer state
First Active Power Management low power state – Low exit latency
Lowest Active Power Management – Longer exit latency
Lowest power state (power-off) – Longest exit latency
L3
4.1.6
Processor Graphics Controller States
Table 4-6.
Processor Graphics Controller States
State
Description
D0
Full on, display active
Power-off
D3 Cold
4.1.7
Interface State Combinations
Table 4-7.
G, S, and C State Combinations
Processor
Package
(C) State
Global
(G) State
Sleep
(S) State
Processor State
System Clocks
Description
G0
G0
G0
G0
G1
G1
G2
G3
S0
S0
S0
S0
S3
S4
S5
NA
C0
Full On
Auto-Halt
On
On
Full On
Auto-Halt
C1/C1E
C3
Deep Sleep
On
Deep Sleep
Deep Power-down
Suspend to RAM
Suspend to Disk
Soft Off
C6/C7
Deep Power-down
On
Power off
Power off
Power off
Power off
Off, except RTC
Off, except RTC
Off, except RTC
Power off
Hard off
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Power Management
Table 4-8.
D, S, and C State Combination
Graphics Adapter
Sleep (S) State
Package (C) State
Description
(D) State
D0
D0
D0
D0
D3
S0
S0
S0
S0
S0
C0
C1/C1E
C3
Full On, Displaying
Auto-Halt, Displaying
Deep sleep, Displaying
Deep Power Down, Displaying
Not displaying
C6/C7
Any
Not displaying, Graphics Core is
powered off
D3
D3
S3
S4
N/A
N/A
Not displaying, suspend to disk
4.2
Processor Core Power Management
While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power
C-states have longer entry and exit latencies.
®
®
4.2.1
Enhanced Intel SpeedStep Technology
The following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps to an optimized voltage. This voltage is signaled by the SVID bus to the
voltage regulator. Once the voltage is established, the PLL locks on to the
target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on SVID bus.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
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4.2.2
Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor package level. Thread-level C-states are
available if Intel HT Technology is enabled.
Caution:
Long term reliability cannot be assured unless all the Low Power Idle States are
enabled.
Figure 4-2. Idle Power Management Breakdown of the Processor Cores
Entry and exit of the C-States at the thread and core level are shown in Figure 4-3.
Figure 4-3. Thread and Core C-State Entry and Exit
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
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Power Management
Table 4-9.
Coordination of Thread Power States at the Core Level
Thread 1
Processor Core
C-State
C0
C0
C0
C0
C0
C0
C1
C0
C3
C0
C6
C7
C0
C0
C1
C3
C6
C7
C0
C11
C3
C11
C11
C11
C11
C11
C3
C11
C3
Thread 0
C3
C6
C6
C3
C6
C7
Note: If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.
4.2.3
Requesting Low-Power Idle States
The primary software interfaces for requesting low power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions using I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Note:
The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in
Table 4-10.
Table 4-10. P_LVLx to MWAIT Conversion
P_LVLx
MWAIT(Cx)
Notes
P_LVL2
P_LVL3
MWAIT(C3)
MWAIT(C6)
MWAIT(C7)
MWAIT(C7)
C6. No sub-states allowed.
C7. No sub-states allowed.
C7. No sub-states allowed.
P_LVL4
P_LVL5+
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note:
When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on
an interrupt, even if interrupts are masked by EFLAGS.IF.
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4.2.4
Core C-states
The following are general rules for all core C-states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (such as Thread
0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See
Table 4-7.
• A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered using an
MWAIT instruction
• For core C1/C1E, core C3, and core C6/C7, an interrupt directed toward a single
thread wakes only that thread. However, since both threads are no longer at the
same core C-state, the core resolves to C0.
• A system reset re-initializes all processor cores.
4.2.4.1
4.2.4.2
Core C0 State
The normal operating state of a core where code is being executed.
Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 4.2.5.2.
4.2.4.3
Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
4.2.4.4
4.2.4.5
Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
Core C7 State
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to
the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same
behavior as the core C6 state unless the core is the last one in the package to enter the
C7 state. If it is, that core is responsible for flushing L3 cache ways. The processor
supports the C7s substate. When an MWAIT(C7) command is issued with a C7s
sub-state hint, the entire L3 cache is flushed in one step as opposed to flushing the L3
cache in multiple steps.
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Power Management
4.2.4.6
C-State Auto-Demotion
In general, deeper C-states such as C6 or C7 have long latencies and have higher
energy entry/exit costs. The resulting performance and energy penalties become
significant when the entry/exit frequency of a deeper C-state is high. Therefore,
incorrect or inefficient usage of deeper C-states have a negative impact on battery life
idle. To increase residency and improve battery life idle in deeper C-states, the
processor supports C-state auto-demotion.
There are two C-State auto-demotion options:
• C7/C6 to C3
• C7/C6/C3 To C1
The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 is based on each
core’s immediate residency history. Upon each core C6/C7 request, the core C-state is
demoted to C3 or C1 until a sufficient amount of residency has been established. At
that point, a core is allowed to go into C3/C6 or C7. Each option can be run
concurrently or individually.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
4.2.5
Package C-States
The processor supports C0, C1/C1E, C3, C6, and C7 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package C-
states unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
— For package C-states, the processor is not required to enter C0 before entering
any other C-state.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
Table 4-11 shows package C-state resolution for a dual-core processor. Figure 4-4
summarizes package C-state transitions.
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Table 4-11. Coordination of Core Power States at the Package Level
Core 1
Package C-State
C0
C0
C0
C0
C0
C0
C1
C0
C3
C0
C6
C0
C7
C0
C0
C1
C3
C6
C7
C11
C11
C11
C11
C11
C3
C11
C3
C11
C3
Core 0
C3
C6
C6
C3
C6
C7
Note: If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.
Figure 4-4. Package C-State Entry and Exit
4.2.5.1
Package C0
This is the normal operating state for the processor. The processor remains in the
normal state when at least one of its cores is in the C0 or C1 state or when the platform
has not granted permission to the processor to go into a low power state. Individual
cores may be in lower power idle states while the package is in C0.
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Power Management
4.2.5.2
Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low power state when:
• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state.
The package enters the C1E state when:
• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES.
No notification to the system occurs upon entry to C1/C1E.
4.2.5.3
Package C3 State
A processor enters the package C3 low power state when:
• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform.
• The platform has not granted a request to a package C6/C7 state but has allowed a
package C6 state.
In package C3-state, the L3 shared cache is valid.
4.2.5.4
Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
• The platform has not granted a package C7 request but has allowed a C6 package
state.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable
in this state. The processor remains in package C6 state as long as any part of the L3
cache is active.
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4.2.5.5
Package C7 State
The processor enters the package C7 low power state when all cores are in the C7 state
and the L3 cache is completely flushed. The last core to enter the C7 state begins to
shrink the L3 cache by N-ways until the entire L3 cache has been emptied. This allows
further power savings.
Core break events are handled the same way as in package C3 or C6. However, snoops
are not sent to the processor in package C7 state because the platform, by granting the
package C7 state, has acknowledged that the processor possesses no snoopable
information. This allows the processor to remain in this low power state and maximize
its power savings.
Upon exit of the package C7 state, the L3 cache is not immediately re-enabled. It
re-enables once the processor has stayed out of C6 or C7 for an preset amount of time.
Power is saved since this prevents the L3 cache from being re-populated only to be
immediately flushed again.
4.2.5.6
Dynamic L3 Cache Sizing
Upon entry into the package C7 state, the L3 cache is reduced by N-ways until it is
completely flushed. The number of ways, N, is dynamically chosen per concurrent C7
entry. Similarly, upon exit, the L3 cache is gradually expanded based on internal
heuristics.
4.3
Integrated Memory Controller (IMC) Power
Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
4.3.1
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as SO-DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with an SO-DIMM
present, the SO-DIMM is not ensured to maintain data integrity.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
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Power Management
4.3.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals that the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
The CKE is one of the power-save means. When CKE is off the internal DDR clock is
disabled and the DDR power is reduced. The power-saving differs according the
selected mode and the DDR type used. For more information, please refer to the IDD
table in the DDR specification.
The DDR specification defines 3 levels of power-down that differ in power-saving and in
wakeup time:
1. Active power-down (APD): This mode is entered if there are open pages when
de-asserting CKE. In this mode the open pages are retained. Power-saving in this
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this
mode is fined by tXP – small number of cycles.
2. Precharged power-down (PPD): This mode is entered if all banks in DDR are
precharged when de-asserting CKE. Power-saving in this mode is intermediate –
better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP. Difference from APD mode is that when waking-
up all page-buffers are empty
3. DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this mode
is the best among all power-modes. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP, but also tXPDLL (10 – 20 according to DDR
type) cycles until first data transfer is allowed.
The processor supports 5 different types of power-down. The different modes are the
power-down modes supported by DDR3 and combinations of these. The type of CKE
power-down is defined by the configuration. The are options are:
1. No power-down
2. APD: The rank enters power-down as soon as idle-timer expires, no matter what is
the bank status
3. PPD: When idle timer expires the MC sends PRE-all to rank and then enters power-
down
4. DLL-off: same as option (2) but DDR is configured to DLL-off
5. APD, change to PPD (APD-PPD): Begins as option (1), and when all page-close
timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to PPD
APD, change to DLL-off (APD_DLLoff) – Begins as option (1), and when all page-
close timers of the rank are expired, it wakes the rank, issues PRE-all and returns
to DLL-off power-down
The CKE is determined per rank when it is inactive. Each rank has an idle-counter. The
idle-counter starts counting as soon as the rank has no accesses, and if it expires, the
rank may enter power-down while no new transactions to the rank arrive to queues.
The idle-counter begins counting at the last incoming transaction arrival.
It is important to understand that since the power-down decision is per rank, the MC
can find many opportunities to power-down ranks even while running memory
intensive applications, and savings are significant (may be a few watts, according to
the DDR specification). This is significant when each channel is populated with more
ranks.
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Datasheet, Volume 1
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Selection of power modes should be according to power-performance or thermal trade-
offs of a given system:
• When trying to achieve maximum performance and power or thermal consideration
is not an issue: use no power-down.
• In a system that tries to minimize power-consumption, try to use the deepest
power-down mode possible – DLL-off or APD_DLLoff.
• In high-performance systems with dense packaging (that is, complex thermal
design) the power-down mode should be considered in order to reduce the heating
and avoid DDR throttling caused by the heating.
Control of the power-mode through CRB-BIOS: The BIOS selects by default no-power-
down. There are knobs to change the power-down selected mode.
Another control is the idle timer expiration count. This is set through PM_PDWN_config
bits 7:0 (MCHBAR +4CB0). As this timer is set to a shorter time, the MC will have more
opportunities to put DDR in power-down. The minimum recommended value for this
register is 15. There is no BIOS hook to set this register. Customers who choose to
change the value of this register can do it by changing the BIOS. For experiments, this
register can be modified in real time if BIOS did not lock the MC registers.
Note:
In APD, APD-PPD, and APD-DLLoff there is no point in setting the idle-counter in the
same range of page-close idle timer.
Another option associated with CKE power-down is the S_DLL-off. When this option is
enabled, the SBR I/O slave DLLs go off when all channel ranks are in power-down. (Do
not confuse it with the DLL-off mode, in which the DDR DLLs are off). This mode
requires to define the I/O slave DLL wakeup time.
4.3.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2
Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3, C6, and C7 low-power states. Intel RMPM functionality
depends on the graphics/display state (relevant only when processor graphics is being
used), as well as memory traffic patterns generated by other connected I/O devices.
The target behavior is to enter self-refresh as long as there are no memory requests to
service.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the
processor core flushes pending cycles and then enters all SDRAM ranks into self-
refresh. The CKE signals remain LOW so the SDRAM devices perform self-refresh.
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Power Management
Table 4-12. Targeted Memory State Conditions
Mode
Memory State with Processor Graphics
Memory State with External Graphics
Dynamic memory rank power down based on Dynamic memory rank power down based on
C0, C1, C1E
idle conditions.
idle conditions.
If the Processor Graphics engine is idle and
there are no pending display requests, then
enter self-refresh. Otherwise, use dynamic
memory rank power down based on idle
conditions.
If there are no memory requests, then enter
self-refresh. Otherwise, use dynamic
memory rank power down based on idle
conditions.
C3, C6, C7
S3
S4
Self-Refresh Mode.
Self-Refresh Mode.
Memory power down (contents lost).
Memory power down (contents lost)
4.3.2.3
Dynamic Power-down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power-down state.
The processor core controller can be configured to put the devices in active power-
down (CKE de-assertion with open pages) or precharge power-down (CKE de-assertion
with all pages closed). Precharge power-down provides greater power savings but has
a bigger performance impact, since all pages will first be closed before putting the
devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
4.3.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-
DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4
PCI Express* Power Management
• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.
Note:
Note:
PEG interface does not support Hot Plug.
Power impact may be observed when PEG link disable power management state is
used.
4.5
Direct Media Interface (DMI) Power Management
• Active power management support using L0s/L1 state.
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4.6
Graphics Power Management
®
®
4.6.1
Intel Rapid Memory Power Management (Intel RMPM)
(also known as CxSR)
The Intel Rapid Memory Power Management puts rows of memory into self refresh
mode during C3/C6/C7 to allow the system to remain in the lower power states longer.
Mobile processors routinely save power during runtime conditions by entering the C3,
C6, or C7 state. Intel RMPM is an indirect method of power saving that can have a
significant effect on the system as a whole.
®
4.6.2
Intel Graphics Performance Modulation Technology
®
(Intel GPMT)
Intel Graphics Power Modulation Technology (Intel GPMT) is a method for saving power
in the graphics adapter while continuing to display and process data in the adapter. This
method will switch the render frequency and/or render voltage dynamically between
higher and lower power states supported on the platform based on render engine
workload. When the system is running in battery mode, and if the end user launches
applications such as 3D or Video, the graphics software may switch the render
frequency dynamically between higher and lower power/performance states depending
on the render engine workload.
In products where Intel® Graphics Dynamic Frequency (also known as Turbo Boost
Technology) is supported and enabled, the functionality of Intel GPMT will be
maintained by Intel® Graphics Dynamic Frequency (also known as Turbo Boost
Technology).
4.6.3
Graphics Render C-State
Render C-State (RC6) is a technique designed to optimize the average power to the
graphics render engine during times of idleness of the render engine. Render C-state is
entered when the graphics render engine, blitter engine and the video engine have no
workload being currently worked on and no outstanding graphics memory transactions.
When the idleness condition is met, the Integrated Graphics will program the VR into a
low voltage state (~0.4 V) through the SVID bus.
Render C-State (RC6) is a technique designed to optimize the average power to the
graphics render engine during times of idleness of the render engine. Render C-state is
entered when the graphics render engine, blitter engine and the video engine have no
workload being currently worked on and no outstanding graphics memory transactions.
When the idleness condition is met, the Processor Graphics will program the VR into a
low voltage state (0-~0.4 V) through the SVID bus.
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®
®
4.6.4
Intel Smart 2D Display Technology (Intel S2DDT)
Intel S2DDT reduces display refresh memory traffic by reducing memory reads
required for display refresh. Power consumption is reduced by less accesses to the IMC.
S2DDT is only enabled in single pipe mode.
Intel S2DDT is most effective with:
• Display images well suited to compression, such as text windows, slide shows, and
so on. Poor examples are 3D games.
• Static screens such as screens with significant portions of the background showing
2D applications, processor benchmarks, and so on, or conditions when the
processor is idle. Poor examples are full-screen 3D games and benchmarks that flip
the display image at or near display refresh rates.
®
4.6.5
Intel Graphics Dynamic Frequency
Intel® Graphics Dynamic Frequency Technology is the ability of the processor and
graphics cores to opportunistically increase frequency and/or voltage above the
ensured processor and graphics frequency for the given part. Intel® Graphics Dynamic
Frequency Technology is a performance feature that makes use of unused package
power and thermals to increase application performance. The increase in frequency is
determined by how much power and thermal budget is available in the package, and
the application demand for additional processor or graphics performance. The
processor core control is maintained by an embedded controller. The graphics driver
dynamically adjusts between P-States to maintain optimal performance, power, and
thermals. The graphics driver will always place the graphics engine in its lowest
possible P-State; thereby, acting in the same capacity as Intel GPMT.
4.6.6
Display Power Savings Technology 6.0 (DPST)
This is a mobile only supported power management feature.
The Intel® DPST technique achieves backlight power savings while maintaining a good
visual experience. This is accomplished by adaptively enhancing the displayed image
while decreasing the backlight brightness simultaneously. The goal of this technique is
to provide equivalent end-user-perceived image quality at a decreased backlight power
level.
1. The original (input) image produced by the operating system or application is
analyzed by the Intel® DPST subsystem. An interrupt to Intel® DPST software is
generated whenever a meaningful change in the image attributes is detected. (A
meaningful change is when the Intel® DPST software algorithm determines that
enough brightness, contrast, or color change has occurred to the displaying images
that the image enhancement and backlight control needs to be altered.)
2. Intel® DPST subsystem applies an image-specific enhancement to increase image
contrast, brightness, and other attributes.
3. A corresponding decrease to the backlight brightness is applied simultaneously to
produce an image with similar user-perceived quality (such as brightness) as the
original image.
Intel® DPST 5.0 has improved the software algorithms and has minor hardware
changes to better handle backlight phase-in and ensures the documented and validated
method to interrupt hardware phase-in.
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Power Management
4.6.7
Automatic Display Brightness (ADB)
This is a mobile only supported power management feature.
Intel® Automatic Display Brightness feature dynamically adjusts the backlight
brightness based upon the current ambient light environment. This feature requires an
additional sensor to be on the panel front. The sensor receives the changing ambient
light conditions and sends the interrupts to the Intel Graphics driver. As per the change
in Lux, (current ambient light illuminance), the new backlight setting can be adjusted
through BLC (see section 11). The converse applies for a brightly lit environment.
Intel® Automatic Display Brightness increases the back light setting.
®
4.6.8
Intel Seamless Display Refresh Rate Switching
®
Technology (Intel SDRRS Technology)
This is a mobile only supported power management feature.
When a Local Flat Panel (LFP) supports multiple refresh rates, the Intel® Display
Refresh Rate Switching power conservation feature can be enabled. The higher refresh
rate will be used when on plugged in power or when the end user has not
selected/enabled this feature. The graphics software will automatically switch to a
lower refresh rate for maximum battery life when the notebook is on battery power and
when the user has selected/enabled this feature.
There are two distinct implementations of Intel® DRRS—static and seamless. The static
Intel® Display Refresh Rate Switching Technology (Intel® DRRS Technology) method
uses a mode change to assign the new refresh rate. The seamless Intel® Seamless
Display Refresh Rate Switching Technology (Intel® SDRRS Technology) method is able
to accomplish the refresh rate assignment without a mode change and therefore does
not experience some of the visual artifacts associated with the mode change (SetMode)
method.
4.7
Thermal Power Management
See Section 4.6 for all graphics thermal power management-related features.
§ §
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Thermal Management
5 Thermal Management
The thermal solution provides both the component-level and the system-level thermal
management. To allow for the optimal operation and long-term reliability of Intel
processor-based systems, the system/processor thermal solution should be designed
so that the processor:
• Remains below the maximum junction temperature (Tj,Max) specification at the
maximum thermal design power (TDP).
• Conforms to system constraints, such as system acoustics, system skin-
temperatures, and exhaust-temperature requirements.
Caution:
Thermal specifications given in this chapter are on the component and package level
and apply specifically to the 2nd Generation Intel® Core™ processor family mobile and
Intel® Celeron® processor family mobile. Operating the processor outside the specified
limits may result in permanent damage to the processor and potentially other
components in the system.
5.1
Thermal Design Power (TDP) and Junction
Temperature (Tj)
The processor TDP is the maximum sustained power that should be used for design of
the processor thermal solution. TDP represents an expected maximum sustained power
from realistic applications. TDP may be exceeded for short periods of time or if running
a “power virus” workload. Due to Intel Turbo Boost Technology, applications are
expected to run closer to TDP more often as the processor attempts to take advantage
of available headroom in the platform to maximize performance.
The processor may also exceed the TDP for short durations after a period of lower
power operation due to its turbo feature. This feature is intended to take advantage of
available thermal capacitance in the thermal solution for momentary high power
operation. The duration and time of such operation can be limited by platform runtime
configurable registers within the processor.
The processor integrates multiple processor and graphics cores on a single die. This
may result in differences in the power distribution across the die and must be
considered when designing the thermal solution.
5.2
Thermal Considerations
Intel Turbo Boost Technology allows processor cores and Processor Graphics cores to
run faster than the baseline frequency. During a turbo event, the processor can exceed
its TDP power for brief periods. Turbo is invoked opportunistically and automatically as
long as the processor is conforming to its temperature, power delivery, and current
specification limits. Thus, thermal solutions and platform cooling that are designed to
be less than thermal design guidance may experience thermal and performance issues
since more applications will tend to run at or near the maximum power limit for
significant periods of time.
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®
5.2.1
Intel Turbo Boost Technology Power Control and
Reporting
When operating in the turbo mode, the processor will monitor its own power and adjust
the turbo frequency to maintain the average power within limits over a thermally
significant time period. The package, processor core, and graphic core powers are
estimated using architectural counters and do not rely on any input from the platform.
The behavior of turbo is dictated by the following controls that are accessible using
MSR, MMIO, or PECI interfaces:
• POWER_LIMIT_1: TURBO_POWER_LIMIT, MSR 610h, bits 14:0. This value sets
the exponentially weighted moving average power limit over a long time period.
This is normally aligned to the TDP of the part and steady-state cooling capability of
the thermal solution. This limit may be set lower than TDP, real-time, for specific
needs, such as responding to a thermal event. If set lower than TDP, the processor
may not be able to honor this limit for all workloads since this control only applies
in the turbo frequency range; a very high powered application may exceed
POWER_LIMIT_1, even at non-turbo frequencies. The default value is the TDP for
the SKU.
• POWER_LIMIT_1_TIME: TURBO _POWER_LIMIT, MSR 610h, bits 23:17. This
value is a time parameter that adjusts the algorithm behavior. The exponentially
weighted moving average turbo algorithm will use this parameter to maintain time
averaged power at or below POWER_LIMIT_1. The default value is 1 second;
however, 28 seconds is recommended for most mobile applications.
• POWER_LIMIT_2: TURBO_POWER_LIMIT, MSR 610h, bits 46:32. This value
establishes the upper power limit of turbo operation above TDP, primarily for
platform power supply considerations. Power may exceed this limit for up to
10 mS. The default for this limit is 1.25 x TDP.
The following considerations and limitations apply to the power monitoring feature:
• Calibration applies to the processor family and is not conducted on a part-by-part
basis. Therefore, some difference between actual and reported power may be
observed.
• Power monitoring is calibrated with a variety of common, realistic workloads near
Tj_max. Workloads with power characteristic markedly different from those used
during the calibration process or lower temperatures may result in increased
differences between actual and estimated power.
• In the event an uncharacterized workload or power “virus” application were to
result in exceeding programmed power limits, the processor Thermal Control
Circuitry (TCC) will protect the processor when properly enabled. Adaptive Thermal
Monitor must be enabled for the processor to remain within specification.
Illustration of Intel Turbo Boost Technology power control is shown in the following
sections and figures. Multiple controls operate simultaneously allowing for
customization for multiple system thermal and power limitations. These controls allow
for turbo optimizations within system constraints.
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5.2.2
Package Power Control
The package power control allows for customization to implement optimal turbo within
platform power delivery and package thermal solution limitations.
Figure 5-1. Package Power Control
5.2.3
5.2.4
Power Plane Control
The processor core and graphics core power plane controls allow for customization to
implement optimal turbo within voltage regulator thermal limitations. It is possible to
use these power plane controls to protect the voltage regulator from overheating due
to extended high currents. Power limiting per plane cannot be ensured in all usages.
This function is similar to the package level long duration window control.
Turbo Time Parameter
'Turbo Time Parameter' is a mathematical parameter (units in seconds) that controls
the processor turbo algorithm using an exponentially weighted moving average of
energy usage. During a maximum power turbo event of about 1.25 x TDP, the
processor could sustain Power_Limit_2 for up to approximately 1.5 the Turbo Time
Parameter. If the power value and/or ‘Turbo Time Parameter’ is changed during
runtime, it may take a period of time (possibly up to approximately 3 to 5 times the
‘Turbo Time Parameter’, depending on the magnitude of the change and other factors)
for the algorithm to settle at the new control limits.
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5.3
Thermal and Power Specifications
The following notes apply to Table 5-1, Table 5-2, Table 5-3, and Table 5-4.
Notes
Description
The TDPs given are not the maximum power the processor can generate. Analysis indicates that
real applications are unlikely to cause the processor to consume the theoretical maximum power
dissipation for sustained periods of time.
1
TDP workload may consist of a combination of a CPU-core intensive and a graphics-core
intensive applications.
2
3
4
5
The thermal solution needs to ensure that the processor temperature does not exceed the
maximum junction temperature (Tj,max) limit, as measured by the DTS and the critical
temperature bit.
The processor junction temperature is monitored by Digital Temperature Sensors (DTS). For DTS
accuracy, refer to Section 5.4.1.2.1.
Digital Thermal Sensor (DTS) based fan speed control is required to achieve optimal thermal
performance. Intel recommends full cooling capability well before the DTS reading reaches
Tj,Max. An example of this is Tj,Max – 10 ºC.
The idle power specifications are not 100% tested. These power specifications are determined
by the characterization at higher temperatures and extrapolating the values for the junction
temperature indicated.
6
7
8
At Tj of Tj,max
At Tj of 50 ºC
9
At Tj of 35 ºC
10
Can be modified at runtime by MSR writes, with MMIO and with PECI commands
'Turbo Time Parameter' is a mathematical parameter (unit in seconds) that controls the
processor turbo algorithm using a moving average of energy usage. Avoid setting the Turbo
Time Parameter to a value less than 0.1 seconds. Refer to Section 5.2.4 for further information.
11
12
Shown limit is a time averaged power, based upon the Turbo Time Parameter. Absolute product
power may exceed the set limits for short durations or under virus or uncharacterized
workloads.
Processor will be controlled to specified power limit as described in Section 5.2.1. If the power
value and/or ‘Turbo Time Parameter’ is changed during runtime, it may take a short period of
time (approximately 3 to 5 times the ‘Turbo Time Parameter’) for the algorithm to settle at the
new control limits.
13
14
15
This is a hardware default setting and not a behavioral characteristic of the part.
For controllable turbo workloads, the limit may be exceeded for up to 10 ms
Tjmax for some Dual Core SV SKUs in rPGA package will be 85 °C. Refer to Dear Customer
Letters (DCLs) or contact your field representative to get details of SKUs that have Tjmax of
85 °C.
16
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Datasheet, Volume 1
Thermal Management
Table 5-1.
Thermal Design Power (TDP) Specifications
CPU Core
Frequency
ProcessorGraphics
Core frequency
Thermal Design
Power
Segment
State
Units
Notes
2.5 GHz up to
3.5 GHz
650 MHz up to
1300 MHz
HFM
LFM
HFM
LFM
HFM
LFM
HFM
LFM
HFM
LFM
55
36
45
33
35
26
25
12
17
10
Extreme
W
1, 2, 7
Edition (XE)
650 MHz up to
1300 MHz
800 MHz
2.2 GHz up to
3.4 GHz
650 MHz up to
1300 MHz
Quad Core SV
Dual Core SV
Low Voltage
W
W
W
W
1, 2, 7
1, 2, 7
1, 2, 7
1, 2, 7
650 MHz up to
1300 MHz
800 MHz
2.5 GHz up to
3.4 GHz
650 MHz up to
1300 MHz
650 MHz up to
1300 MHz
800 MHz
2.1 GHz up to
3.2 GHz
500 MHz up to
1100 MHz
500 MHz up to
1100 MHz
800 MHz
1.4 GHz up to
2.7 GHz
350 MHz up to
1000 MHz
Ultra Low
Voltage
350 MHz up to
1000 MHz
800 MHz
Table 5-2.
Junction Temperature Specification
Package Turbo
Parameter
Segment
Symbol
Min
Default
Max
Units
Notes
Extreme Edition
(XE)
TJ
Junction temperature limit
0
—
100
°C
3, 4, 5,
Quad Core SV
Dual Core SV
Low Voltage
TJ
TJ
TJ
Junction temperature limit
Junction temperature limit
Junction temperature limit
0
0
0
—
—
—
100
100
100
°C
°C
°C
3, 4, 5,
3, 4, 5, 16
3, 4, 5
Ultra Low
Voltage
TJ
Junction temperature limit
0
—
100
°C
3, 4, 5
Table 5-3.
Package Turbo Parameters (Sheet 1 of 2)
H/W
Default
Segment
Symbol
Package Turbo Parameter
Min
Max
Units
Notes
Processor turbo long duration time
window
(POWER_LIMIT_1_TIME in
TURBO_POWER_LIMIT MSR 0610h
bits [23:17])
TurboTime
Parameter
(package)
10, 11,
14
N/A
1
N/A
s
'Long duration' turbo power limit
Extreme
Edition
(XE)
Long P
(package)
10,12,13,
14
(POWER_LIMIT_1 in
TURBO_POWER_LIMIT MSR 0610h
bits [14:0])
N/A
N/A
55
N/A
N/A
W
W
'Short duration' turbo power limit
Short P
(package)
10, 14,
15
(POWER_LIMIT_2 in
TURBO_POWER_LIMIT MSR 0610h
bits [46:32])
1.25 x 55
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Thermal Management
Table 5-3.
Package Turbo Parameters (Sheet 2 of 2)
H/W
Default
Segment
Symbol
Package Turbo Parameter
Min
Max
Units
Notes
Processor turbo long duration time
window
(POWER_LIMIT_1_TIME in
TURBO_POWER_LIMIT MSR 0610h
bits [23:17])
TurboTime
Parameter
(package)
10, 11,
14
0.001
1
64
S
'Long duration' turbo power limit
Quad Core
SV
Long P
(package)
10,12,13,
14
(POWER_LIMIT_1 in
TURBO_POWER_LIMIT MSR 0610h
bits [14:0])
40
40
45
48
60
W
W
'Short duration' turbo power limit
Short P
(package)
10, 14,
15
(POWER_LIMIT_2 in
TURBO_POWER_LIMIT MSR 0610h
bits [46:32])
1.25 x 45
Processor turbo long duration time
window
(POWER_LIMIT_1_TIME in
TURBO_POWER_LIMIT MSR 0610h
bits [23:17])
TurboTime
Parameter
(package)
10, 11,
14
0.001
1
64
S
'Long duration' turbo power limit
Dual Core
SV
Long P
(package)
10, 12,
13, 14
(POWER_LIMIT_1 in
TURBO_POWER_LIMIT MSR 0610h
bits [14:0])
28
28
35
36
44
W
W
'Short duration' turbo power limit
Short P
(package)
10, 14,
15
(POWER_LIMIT_2 in
TURBO_POWER_LIMIT MSR 0610h
bits [46:32])
1.25 x 35
Processor turbo long duration time
window
(POWER_LIMIT_1_TIME in
TURBO_POWER_LIMIT MSR 0610h
bits [23:17])
TurboTime
Parameter
(package)
10, 11,
14
0.001
1
32
S
'Long duration' turbo power limit
Low
Voltage
Long P
(package)
10, 12,
13, 14
(POWER_LIMIT_1 in
TURBO_POWER_LIMIT MSR 0610h
bits [14:0])
24
24
25
28
36
W
W
'Short duration' turbo power limit
Short P
(package)
10, 14,
15
(POWER_LIMIT_2 in
TURBO_POWER_LIMIT MSR 0610h
bits [46:32])
1.25 x 25
Processor turbo long duration time
window
(POWER_LIMIT_1_TIME in
TURBO_POWER_LIMIT MSR 0610h
bits [23:17])
TurboTime
Parameter
(package)
0.001
1
32
S
10,11,14
'Long duration' turbo power limit
Ultra Low
Voltage
Long P
(package)
10,12,
13, 14
(POWER_LIMIT_1 in
TURBO_POWER_LIMIT MSR 0610h
bits [14:0])
—
—
17
—
—
W
W
'Short duration' turbo power limit
Short P
(package)
(POWER_LIMIT_2 in
TURBO_POWER_LIMIT MSR 0610h
bits [46:32])
1.25 x 17
10,14,15
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Table 5-4.
Idle Power Specifications
Idle Parameter
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
12.5
4
Segment
Symbol
Units
Notes
Idle power in the Package
C1e state
PC1E
W
6, 8
Idle power in the Package
C6 state
Extreme
Edition (XE)
PC6
PC7
PC1E
PC6
PC7
PC1E
PC6
PC7
PC1E
PC6
PC7
PC1E
PC6
PC7
W
W
W
W
W
W
W
W
W
W
W
W
W
W
6, 9
6, 9
6, 8
6, 9
6, 9
6, 8
6, 9
6, 9
6, 8
6, 9
6, 9
6, 8
6, 9
6, 9
Idle power in the Package
C7state
3.85
11
Idle power in the Package
C1e state
Idle power in the Package
C6 state
Quad Core SV
Dual Core SV
Low Voltage
3.9
3.8
8.8
3.1
2.95
6.4
2.5
2.35
5.8
2.3
2.2
Idle power in the Package
C7state
Idle power in the Package
C1e state
Idle power in the Package
C6 state
Idle power in the Package
C7state
Idle power in the Package
C1e state
Idle power in the Package
C6 state
Idle power in the Package
C7state
Idle power in the Package
C1e state
Idle power in the Package
C6 state
Ultra Low
Voltage
Idle power in the Package
C7state
5.4
Thermal Management Features
This section covers thermal management features for the processor.
5.4.1
Processor Package Thermal Features
This section covers thermal management features for the entire processor complex
(including the processor core, the graphics core, and integrated memory controller
hub), and will be referred to as processor package, or by simply the package.
Occasionally the package will operate in conditions that exceed its maximum allowable
operating temperature. This can be due to internal overheating or due to overheating in
the entire system. To protect itself and the system from thermal failure, the package is
capable of reducing its power consumption and thereby its temperature to attempt to
remain within normal operating limits using the Adaptive Thermal Monitor.
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The Adaptive Thermal Monitor can be activated when any package temperature,
monitored by a digital thermal sensor (DTS), meets or exceeds its maximum junction
temperature specification (TJ,max) and asserts PROCHOT#. The thermal control circuit
(TCC) can be activated prior to TJ,max by use of the TCC activation offset. The assertion
of PROCHOT# activates the thermal control circuit (TCC), and causes both the
processor core and graphics core to reduce frequency and voltage adaptively. The TCC
will remain active as long as any package temperature exceeds its specified limit.
Therefore, the Adaptive Thermal Monitor will continue to reduce the package frequency
and voltage until the TCC is de-activated.
Note:
Adaptive Thermal Monitor protection is always enabled.
5.4.1.1
Adaptive Thermal Monitor
The purpose of the Adaptive Thermal Monitor is to reduce processor core power
consumption and temperature until it operates at or below its maximum operating
temperature (according for TCC activation offset). Processor core power reduction is
achieved by:
• Adjusting the operating frequency (using the core ratio multiplier) and input
voltage (using the SVID bus).
• Modulating (starting and stopping) the internal processor core clocks (duty cycle).
The temperature at which the Adaptive Thermal Monitor activates the Thermal Control
Circuit is factory calibrated and is not user configurable. The default value is software
visible in the TEMPERATURE_TARGET (1A2h) MSR, Bits 23:16. The Adaptive Thermal
Monitor does not require any additional hardware, software drivers, or interrupt
handling routines. The Adaptive Thermal Monitor is not intended as a mechanism to
maintain processor TDP. The system design should provide a thermal solution that can
maintain TDP within its intended usage range.
5.4.1.1.1
Frequency / Voltage Control
Upon TCC activation, the processor core attempts to dynamically reduce processor core
power by lowering the frequency and voltage operating point. The operating points are
automatically calculated by the processor core itself and do not require the BIOS to
program them as with previous generations of Intel processors. The processor core will
scale the operating points such that:
• The voltage will be optimized according to the temperature, the core bus ratio, and
number of cores in deep C-states.
• The core power and temperature are reduced while minimizing performance
degradation.
A small amount of hysteresis has been included to prevent an excessive amount of
operating point transitions when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum
operating temperature the operating frequency and voltage will transition back to the
normal system operating point. This is illustrated in Figure 5-2.
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Figure 5-2. Frequency and Voltage Ordering
Once a target frequency/bus ratio is resolved, the processor core will transition to the
new target automatically.
• On an upward operating point transition, the voltage transition precedes the
frequency transition.
• On a downward transition, the frequency transition precedes the voltage transition.
When transitioning to a target core operating voltage, a new VID code to the voltage
regulator is issued. The voltage regulator must support dynamic VID steps to support
this method.
During the voltage change:
• It will be necessary to transition through multiple VID steps to reach the target
operating voltage.
• Each step is 5 mV for Intel MVP-7.0 compliant VRs.
• The processor continues to execute instructions. However, the processor will halt
instruction execution for frequency transitions.
If a processor load-based Enhanced Intel SpeedStep Technology / P-state transition
(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are
two possible outcomes:
• If the P-state target frequency is higher than the processor core optimized target
frequency, the p-state transition will be deferred until the thermal event has been
completed.
• If the P-state target frequency is lower than the processor core optimized target
frequency, the processor will transition to the P-state operating point.
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5.4.1.1.2
Clock Modulation
If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor
event, the Adaptive Thermal Monitor will use clock modulation. Clock modulation is
done by alternately turning the clocks off and on at a duty cycle (ratio between clock
“on” time and total time) specific to the processor. The duty cycle is factory configured
to 25% on and 75% off and cannot be modified. The period of the duty cycle is
configured to 32 microseconds when the TCC is active. Cycle times are independent of
processor frequency. A small amount of hysteresis has been included to prevent
excessive clock modulation when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum
operating temperature, and the hysteresis timer has expired, the TCC goes inactive and
clock modulation ceases. Clock modulation is automatically engaged as part of the TCC
activation when the frequency/voltage targets are at their minimum settings. Processor
performance will be decreased by the same amount as the duty cycle when clock
modulation is active. Snooping and interrupt processing are performed in the normal
manner while the TCC is active.
5.4.1.2
Digital Thermal Sensor
Each processor execution core has an on-die Digital Thermal Sensor (DTS) that detects
the core’s instantaneous temperature. The DTS is the preferred method of monitoring
processor die temperature because:
• It is located near the hottest portions of the die.
• It can accurately track the die temperature and ensure that the Adaptive Thermal
Monitor is not excessively activated.
Temperature values from the DTS can be retrieved through:
• A software interface using processor Model Specific Register (MSR).
• A processor hardware interface as described in Section 5.4.4.
Note:
When temperature is retrieved by processor MSR, it is the instantaneous temperature
of the given core. When temperature is retrieved using PECI, it is the average of the
highest DTS temperature in the package over a 256 ms time window. Intel
recommends using the PECI reported temperature for platform thermal control that
benefits from averaging, such as fan speed control. The average DTS temperature may
not be a good indicator of package Adaptive Thermal Monitor activation or rapid
increases in temperature that triggers the Out of Specification status bit within the
PACKAGE_THERM_STATUS MSR 01B1h and IA32_THERM_STATUS MSR 19Ch.
Code execution is halted in C1–C7. Therefore, temperature cannot be read using the
processor MSR without bringing a core back into C0. However, temperature can still be
monitored through PECI in lower C-states except for C7.
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (Tj,max), regardless of
TCC activation offset. It is the responsibility of software to convert the relative
temperature to an absolute temperature. The absolute reference temperature is
readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the
DTS is an implied negative integer indicating the relative offset from Tj,max. The DTS
does not report temperatures greater than Tj,max
.
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The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor
trigger point. When a package DTS indicates that it has reached the TCC activation (a
reading of 0h, except when the TCC activation offset is changed), the TCC will activate
and indicate a Adaptive Thermal Monitor event. A TCC activation will lower both IA core
and graphics core frequency, voltage or both.
Changes to the temperature can be detected using two programmable thresholds
located in the processor thermal MSRs. These thresholds have the capability of
generating interrupts using the core's local APIC. Refer to the Intel® 64 and IA-32
Architectures Software Developer's Manuals for specific register and programming
details.
5.4.1.2.1
5.4.1.3
Digital Thermal Sensor Accuracy (Taccuracy)
The error associated with DTS measurement will not exceed ±5 °C at Tj,max. The DTS
measurement within the entire operating range will meet a ±5 °C accuracy.
PROCHOT# Signal
PROCHOT# (processor hot) is asserted when the processor core temperature has
reached its maximum operating temperature (Tj,max). See Figure 5-2 for a timing
diagram of the PROCHOT# signal assertion relative to the Adaptive Thermal Response.
Only a single PROCHOT# pin exists at a package level. When any core arrives at the
TCC activation point, the PROCHOT# signal will be asserted. PROCHOT# assertion
policies are independent of Adaptive Thermal Monitor enabling.
Note:
Bus snooping and interrupt latching are active while the TCC is active.
5.4.1.3.1
Bi-Directional PROCHOT#
By default, the PROCHOT# signal is defined as an output only. However, the signal may
be configured as bi-directional. When configured as a bi-directional signal, PROCHOT#
can be used for thermally protecting other platform components should they overheat
as well. When PROCHOT# is driven by an external device:
• the package will immediately transition to the minimum operation points (voltage
and frequency) supported by the processor and graphics cores. This is contrary to
the internally-generated Adaptive Thermal Monitor response.
• Clock modulation is not activated.
The TCC will remain active until the system de-asserts PROCHOT#. The processor can
be configured to generate an interrupt upon assertion and de-assertion of the
PROCHOT# signal.
Note:
Toggling PROCHOT# more than once in 1.5ms period will result in constant Pn state of
the processor.
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Thermal Management
5.4.1.3.2
Voltage Regulator Protection
PROCHOT# may be used for thermal protection of voltage regulators (VR). System
designers can create a circuit to monitor the VR temperature and activate the TCC
when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)
and activating the TCC, the VR will cool down as a result of reduced processor power
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target thermal
design current (ICCTDC) instead of maximum current. Systems should still provide
proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case
of system cooling failure. Overall, the system thermal design should allow the power
delivery circuitry to operate within its temperature specification even while the
processor is operating at its TDP.
5.4.1.3.3
Thermal Solution Design and PROCHOT# Behavior
With a properly designed and characterized thermal solution, it is anticipated that
PROCHOT# will only be asserted for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable.
However, an under-designed thermal solution that is not able to prevent excessive
assertion of PROCHOT# in the anticipated ambient environment may:
• Cause a noticeable performance loss.
• Result in prolonged operation at or above the specified maximum junction
temperature and affect the long-term reliability of the processor.
• May be incapable of cooling the processor even when the TCC is active continuously
(in extreme situations).
5.4.1.3.4
Low-Power States and PROCHOT# Behavior
If the processor enters a low-power package idle state such as C3 or C6/C7 with
PROCHOT# asserted, PROCHOT# will remain asserted until:
• The processor exits the low-power state
• The processor junction temperature drops below the thermal trip point.
For the package C7 state, PROCHOT# may de-assert for the duration of C7 state
residency even if the processor enters the idle state operating at the TCC activation
temperature. The PECI interface is fully operational during all C-states and it is
expected that the platform continues to manage processor (“package”) core thermals
even during idle states by regularly polling for thermal data over PECI.
5.4.1.3.5
5.4.1.3.6
THERMTRIP# Signal
Regardless of enabling the automatic or on-demand modes, in the event of a
catastrophic cooling failure, the package will automatically shut down when the silicon
has reached an elevated temperature that risks physical damage to the product. At this
point the THERMTRIP# signal will go active.
Critical Temperature Detection
Critical Temperature detection is performed by monitoring the package temperature.
This feature is intended for graceful shutdown before the THERMTRIP# is activated;
however, the processor execution is not ensured between critical temperature and
THERMTRIP#. If the package's Adaptive Thermal Monitor is triggered and the
temperature remains high, a critical temperature status and sticky bit are latched in the
PACKAGE_THERM_STATUS MSR 1B1h and also generates a thermal interrupt if
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enabled. For more details on the interrupt mechanism, refer to the Intel® 64 and IA-32
Architectures Software Developer's Manuals.
5.4.2
Processor Core Specific Thermal Features
5.4.2.1
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption using clock modulation. This
mechanism is referred to as “On-Demand” mode and is distinct from Adaptive Thermal
Monitor and bi-directional PROCHOT#. The processor platforms must not rely on
software usage of this mechanism to limit the processor temperature. On-Demand
Mode can be done using processor MSR or chipset I/O emulation.
On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor.
However, if the system software tries to enable On-Demand mode at the same time the
TCC is engaged, the factory configured duty cycle of the TCC will override the duty
cycle selected by the On-Demand mode. If the I/O based and MSR-based On-Demand
modes are in conflict, the duty cycle selected by the I/O emulation-based On-Demand
mode will take precedence over the MSR-based On-Demand Mode.
5.4.2.1.1
MSR Based On-Demand Mode
If Bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will
immediately reduce its power consumption using modulation of the internal core clock,
independent of the processor temperature. The duty cycle of the clock modulation is
programmable using Bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In this
mode, the duty cycle can be programmed in either 12.5% or 6.25% increments
(discoverable using CPU ID). Thermal throttling using this method will modulate each
processor core’s clock independently.
5.4.2.1.2
I/O Emulation-Based On-Demand Mode
I/O emulation-based clock modulation provides legacy support for operating system
software that initiates clock modulation through I/O writes to ACPI defined processor
clock control registers on the chipset (PROC_CNT). Thermal throttling using this
method will modulate all processor cores simultaneously.
5.4.3
Memory Controller Specific Thermal Features
The memory controller provides the ability to initiate memory throttling based upon
memory temperature. The memory temperature can be provided to the memory
controller using PECI or can be estimated by the memory controller based upon
memory activity. The temperature trigger points are programmable by memory
mapped IO registers.
5.4.3.1
Programmable Trip Points
This memory controller provides programmable critical, hot and warm trip points.
Crossing a critical trip point forces a system shutdown. Crossing a hot or warm trip
point will initiate throttling. The amount of memory throttle at each trip point is
programmable.
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Thermal Management
5.4.4
Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) is a one-wire interface that provides
a communication channel between Intel processor and chipset components to external
monitoring devices. The processor implements a PECI interface to allow communication
of processor thermal information to other devices on the platform. The processor
provides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated at
the factory to provide a digital representation of relative processor temperature.
Averaged DTS values are read using the PECI interface.
The PECI physical layer is a self-clocked one-wire bus that begins each bit with a
driven, rising edge from an idle level near zero volts. The duration of the signal driven
high depends on whether the bit value is a Logic 0 or Logic 1. PECI also includes
variable data transfer rate established with every message. The single wire interface
provides low board routing overhead for the multiple load connections in the congested
routing area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability to transfer
critical device operating conditions and configuration information.
5.4.4.1
Fan Speed Control with Digital Thermal Sensor
Digital Thermal Sensor based fan speed control (TFAN) is a recommended feature to
achieve optimal thermal performance. At the TFAN temperature, Intel recommends full
cooling capability well before the DTS reading reaches Tj,max. An example of this would
be TFAN = Tj,max – 10 ºC.
§ §
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Signal Description
6 Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type.
Notations
Signal Type
I
Input Pin
Output Pin
O
I/O
Bi-directional Input/Output Pin
The signal description also includes the type of buffer used for the particular signal (see
Table 6-1).
Table 6-1.
Signal Description Buffer Types
Signal
Description
PCI Express interface signals. These signals are compatible with PCI Express* 2.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe specification.
PCI Express*
Embedded Display Port interface signals. These signals are compatible with VESA
Revision 1.0 DP specifications and the interface is AC coupled. The buffers are not
3.3-V tolerant.
eDP
FDI
DMI
Intel Flexible Display interface signals. These signals are based on PCI Express* 2.0
Signaling Environment AC Specifications (2.7 GT/s), but are DC coupled. The buffers
are not 3.3-V tolerant.
Direct Media Interface signals. These signals are based on PCI Express* 2.0 Signaling
Environment AC Specifications (5 GT/s), but are DC coupled. The buffers are not
3.3-V tolerant.
CMOS
DDR3
CMOS buffers. 1.1-V tolerant
DDR3 buffers: 1.5-V tolerant
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
A
Ref
Voltage reference signal
Asynchronous1
Signal has no timing relationship with any reference clock.
Notes:
1. Qualifier for a buffer type.
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Signal Description
6.1
System Memory Interface Signals
Table 6-2.
Memory Channel A Signals
Direction/
Buffer Type
Signal Name
Description
Bank Select: These signals define which banks are selected within
O
DDR3
SA_BS[2:0]
SA_WE#
each SDRAM rank.
Write Enable Control Signal: This signal is used with SA_RAS# and
SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
O
DDR3
RAS Control Signal: This signal is used with SA_CAS# and SA_WE#
O
DDR3
SA_RAS#
SA_CAS#
(along with SA_CS#) to define the SRAM Commands.
CAS Control Signal: This signal is used with SA_RAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
O
DDR3
Data Strobes: SA_DQS[7:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SA_DQS[7:0] and its SA_DQS#[7:0] during read and write
transactions.
I/O
DDR3
SA_DQS[7:0]
SA_DQS#[7:0]
Data Bus: Channel A data signal interface to the SDRAM data bus.
I/O
DDR3
SA_DQ[63:0]
SA_MA[15:0]
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
O
DDR3
SDRAM Differential Clock: Channel A SDRAM Differential clock signal
pair. The crossing of the positive edge of SA_CK and the negative edge
of its complement SA_CK# are used to sample the command and
control signals on the SDRAM.
O
DDR3
SA_CK[1:0]
SDRAM Inverted Differential Clock: Channel A SDRAM Differential
clock signal-pair complement.
O
DDR3
SA_CK#[1:0]
Clock Enable: (1 per rank). These signals are used to:
•
•
•
Initialize the SDRAMs during power-up
Power-down SDRAM ranks
Place all SDRAM ranks into and out of self-refresh during STR
O
DDR3
SA_CKE[1:0]
Chip Select: (1 per rank). These signals are used to select particular
SDRAM components during the active state. There is one Chip Select
for each SDRAM rank.
O
DDR3
SA_CS#[1:0]
SA_ODT[1:0]
On Die Termination: Active Termination Control.
O
DDR3
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Datasheet, Volume 1
Signal Description
Table 6-3.
Memory Channel B Signals
Direction/
Buffer Type
Signal Name
Description
Bank Select: These signals define which banks are selected within
O
DDR3
SB_BS[2:0]
SB_WE#
each SDRAM rank.
Write Enable Control Signal: This signal is used with SB_RAS# and
SB_CAS# (along with SB_CS#) to define the SDRAM Commands.
O
DDR3
RAS Control Signal: This signal is used with SB_CAS# and SB_WE#
O
DDR3
SB_RAS#
SB_CAS#
(along with SB_CS#) to define the SRAM Commands.
CAS Control Signal: This signal is used with SB_RAS# and SB_WE#
(along with SB_CS#) to define the SRAM Commands.
O
DDR3
Data Strobes: SB_DQS[7:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SB_DQS[8:0] and its SB_DQS#[7:0] during read and write
transactions.
I/O
DDR3
SB_DQS[7:0]
SB_DQS#[7:0]
Data Bus: Channel B data signal interface to the SDRAM data bus.
I/O
DDR3
SB_DQ[63:0]
SB_MA[15:0]
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
O
DDR3
SDRAM Differential Clock: Channel B SDRAM Differential clock signal
pair. The crossing of the positive edge of SB_CK and the negative edge
of its complement SB_CK# are used to sample the command and
control signals on the SDRAM.
O
DDR3
SB_CK[1:0]
SDRAM Inverted Differential Clock: Channel B SDRAM Differential
clock signal-pair complement.
O
DDR3
SB_CK#[1:0]
Clock Enable: (1 per rank). These signals are used to:
•
•
•
Initialize the SDRAMs during power-up.
Power-down SDRAM ranks.
Place all SDRAM ranks into and out of self-refresh during STR.
O
DDR3
SB_CKE[1:0]
Chip Select: (1 per rank). These signals are used to select particular
SDRAM components during the active state. There is one Chip Select
for each SDRAM rank.
O
DDR3
SB_CS#[1:0]
SB_ODT[1:0]
On Die Termination: Active Termination Control.
O
DDR3
6.2
Memory Reference and Compensation Signals
Table 6-4.
Memory Reference and Compensation
Direction/
Buffer Type
Signal Name
Description
System Memory Impedance Compensation:
I
A
SM_RCOMP[2:0]
SM_VREF
DDR3 Reference Voltage: This provides reference voltage to the
DDR3 interface and is defined as VDDQ/2.
I
A
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Signal Description
6.3
Reset and Miscellaneous Signals
Table 6-5.
Reset and Miscellaneous Signals
Direction/
Buffer Type
Signal Name
Description
Configuration Signals: The CFG signals have a default value of '1' if not
terminated on the board.
•
CFG[1:0]: Reserved configuration lane. A test point may be placed on
the board for this lane.
•
CFG[2]: PCI Express* Static x16 Lane Numbering Reversal
— 1 = Normal operation
— 0 = Lane numbers reversed
CFG[3]: Reserved
•
•
CFG[4]: eDP enable
I
CFG[17:0]
— 1 = Disabled
CMOS
— 0 = Enabled
CFG[6:5]: PCI Express Bifurcation
•
•
— 00 = 1 x8, 2 x4 PCI Express
— 01 = Reserved
— 10 = 2 x8 PCI Express
— 11 = 1 x16 PCI Express
CFG[17:7]: Reserved configuration lanes. A test point may be placed
on the board for these lands.
Power Management Sync: A sideband signal to communicate power
I
PM_SYNC
RESET#
management status from the platform to the processor.
CMOS
Platform Reset pin driven by the PCH
I
CMOS
RESERVED: All signals that are RSVD and RSVD_NCTF must be left
unconnected on the board. However, Intel recommends that all RSVD_TP
signals have using test points.
No Connect
Test Point
Non-Critical
to Function
RSVD
RSVD_TP
RSVD_NCTF
DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One
common to all channels.
O
CMOS
SM_DRAMRST#
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Datasheet, Volume 1
Signal Description
6.4
PCI Express*-Based Interface Signals
Table 6-6.
PCI Express* Graphics Interface Signals
Direction/
Buffer Type
Signal Name
Description
PCI Express Input Current Compensation
I
A
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PCI Express Current Compensation
PCI Express Resistance Compensation
PCI Express Receive Differential Pair
PCI Express Transmit Differential Pair
I
A
I
A
PEG_RX[15:0]
PEG_RX#[15:0]
I
PCI Express
PEG_TX[15:0]
O
PEG_TX#[15:0]
PCI Express
6.5
Embedded DisplayPort* (eDP) Signals
Table 6-7.
Embedded DisplayPort* Signals
Direction/
Buffer Type
Signal Name
Description
eDP_TX[3:0]
Embedded DisplayPort Transmit Differential Pair
O
eDP_TX#[3:0]
Diff
eDP_AUX
eDP_AUX#
Embedded DisplayPort Auxiliary Differential Pair
Embedded DisplayPort Hot Plug Detect:
I/O
Diff
I
eDP_HPD#
Asynchronous
CMOS
Embedded DisplayPort Current Compensation
Embedded DisplayPort Current Compensation
I
A
eDP_COMPIO
eDP_ICOMPO
I
A
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Signal Description
6.6
Intel® Flexible Display Interface (Intel® FDI)
Signals
Table 6-8.
Intel® Flexible Display Interface (Intel® FDI)
Direction/
Buffer Type
Signal Name
Description
FDI0_TX[3:0]
FDI0_TX#[3:0]
Intel® Flexible Display Interface Transmit Differential Pair –
Pipe A
O
FDI
Intel® Flexible Display Interface Frame Sync – Pipe A
Intel® Flexible Display Interface Line Sync – Pipe A
I
FDI0_FSYNC[0]
FDI0_LSYNC[0]
CMOS
I
CMOS
FDI1_TX[3:0]
FD1I_TX#[3:0]
Intel® Flexible Display Interface Transmit Differential Pair –
Pipe B
O
FDI
Intel® Flexible Display Interface Frame Sync – Pipe B
Intel® Flexible Display Interface Line Sync – Pipe B
Intel® Flexible Display Interface Hot Plug Interrupt
I
FDI1_FSYNC[1]
FDI1_LSYNC[1]
CMOS
I
CMOS
I
FDI_INT
Asynchronous
CMOS
6.7
Direct Media Interface (DMI) Signals
Table 6-9.
Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface
Direction/
Buffer Type
Signal Name
Description
DMI_RX[3:0]
DMI Input from PCH: Direct Media Interface receive differential pair.
I
DMI_RX#[3:0]
DMI
DMI_TX[3:0]
DMI Output to PCH: Direct Media Interface transmit differential pair.
O
DMI_TX#[3:0]
DMI
6.8
Phase Lock Loop (PLL) Signals
Table 6-10. Phase Lock Loop (PLL) Signals
Direction/
Buffer Type
Signal Name
Description
BCLK
Differential bus clock input to the processor
I
BCLK#
Diff Clk
DPLL_REF_CLK
Embedded Display Port PLL Differential Clock In: 120 MHz.
I
DPLL_REF_CLK#
Diff Clk
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Datasheet, Volume 1
Signal Description
6.9
Test Access Points (TAP) Signals
Table 6-11. Test Access Points (TAP) Signals
Direction/
Buffer Type
Signal Name
Description
Breakpoint and Performance Monitor Signals: These signals are
outputs from the processor that indicate the status of breakpoints
and programmable counters used for monitoring processor
performance.
I/O
CMOS
BPM#[7:0]
BCLK_ITP
BCLK_ITP#
These pins are connected in parallel to the top side debug probe to
enable debug capacities.
I
DBR# is used only in systems where no debug port is implemented
on the system board. DBR# is used by a debug port interposer so
that an in-target probe can drive system reset.
DBR#
PRDY#
PREQ#
TCK
O
O
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
Asynchronous
CMOS
PREQ# is used by debug tools to request debug operation of the
processor.
I
Asynchronous
CMOS
TCK (Test Clock): This signal provides the clock input for the
processor Test Bus (also known as the Test Access Port). TCK must be
driven low or allowed to float during power on Reset.
I
CMOS
TDI (Test Data In): This signal transfers serial test data into the
processor. TDI provides the serial input needed for JTAG specification
support.
I
TDI
CMOS
TDO (Test Data Out): This signal transfers serial test data out of the
processor. TDO provides the serial output needed for JTAG
specification support.
O
TDO
Open Drain
TMS (Test Mode Select): A JTAG specification support signal used by
debug tools.
I
TMS
CMOS
TRST# (Test Reset): This signal resets the Test Access Port (TAP)
logic. TRST# must be driven low during power on Reset.
I
TRST#
CMOS
6.10
Error and Thermal Protection Signals
Table 6-12. Error and Thermal Protection Signals (Sheet 1 of 2)
Direction/
Buffer Type
Signal Name
Description
Catastrophic Error: This signal indicates that the system has
experienced a catastrophic error and cannot continue to operate. The
processor will set this for non-recoverable machine check errors or
other unrecoverable internal errors.
On the processor, CATERR# is used for signaling the following types of
errors:
O
CMOS
CATERR#
•
•
Legacy MCERRs – CATERR# is asserted for 16 BCLKs.
Legacy IERRs – CATERR# remains asserted until warm or cold
reset.
PECI (Platform Environment Control Interface): A serial sideband
interface to the processor, it is used primarily for thermal, power, and
error management.
I/O
PECI
Asynchronous
Processor Hot: PROCHOT# goes active when the processor
temperature monitoring sensor(s) detects that the processor has
reached its maximum safe operating temperature. This indicates that
the processor Thermal Control Circuit (TCC) has been activated, if
enabled. This signal can also be driven to the processor to activate the
TCC.
CMOS Input/
Open-Drain
Output
PROCHOT#
Datasheet, Volume 1
81
Signal Description
Table 6-12. Error and Thermal Protection Signals (Sheet 2 of 2)
Direction/
Buffer Type
Signal Name
Description
Thermal Trip: The processor protects itself from catastrophic
overheating by use of an internal thermal sensor. This sensor is set
well above the normal operating temperature to ensure that there are
no false trips. The processor will stop all execution when the junction
temperature exceeds approximately 130 °C. This is signaled to the
system by the THERMTRIP# pin.
O
THERMTRIP#
Asynchronous
CMOS
6.11
Power Sequencing Signals
Table 6-13. Power Sequencing Signals
Direction/
Buffer Type
Signal Name
Description
SM_DRAMPWROK Processor Input: Connects to PCH
DRAMPWROK.
I
SM_DRAMPWROK
UNCOREPWRGOOD
Asynchronous
CMOS
The processor requires this input signal to be a clean indication that
the VCCSA, VCCIO, VAXG, and VDDQ, power supplies are stable and
within specifications. This requirement applies, regardless of the S-
state of the processor. 'Clean' implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time
that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high
state. This is connected to the PCH PROCPWRGD signal.
I
Asynchronous
CMOS
SKTOCC#
SKTOCC# (Socket Occupied)/PROC_DETECT (Processor
Detect): Pulled down directly (0 Ohms) on the processor package to
ground. There is no connection to the processor silicon for this signal.
System board designers may use this signal to determine if the
processor is present.
(rPGA only)
PROC_DETECT#
(BGA)
6.12
Processor Power Signals
Table 6-14. Processor Power Signals (Sheet 1 of 2)
Direction/
Buffer Type
Signal Name
Description
VCC
VCCIO
VDDQ
VAXG
Processor core power rail
Ref
Ref
Ref
Ref
Ref
Ref
Processor power for I/O
Processor I/O supply voltage for DDR3
Graphics core power supply.
VCCPLL
VCCSA
VCCPLL provides isolated power for internal processor PLLs
System Agent power supply
VCCPQE
(BGA Only)
Filtered, low noise derivative of VCCIO
Ref
82
Datasheet, Volume 1
Signal Description
Table 6-14. Processor Power Signals (Sheet 2 of 2)
Direction/
Buffer Type
Signal Name
Description
VCCDQ
(BGA Only)
Filtered, low noise derivative of VDDQ
Ref
VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal serial
synchronous interface used to transfer power management information
between the processor and the voltage regulator controllers. This serial
VID interface replaces the parallel VID interface on previous
processors.
I/O
O
I
VIDSOUT
VIDSCLK
VIDALERT#
CMOS
Voltage selection for VCCSA: This pin must have a pull down resistor
to ground.
O
CMOS
VCCSA_VID[1]
6.13
Sense Signals
Table 6-15. Sense Signals
Direction/
Buffer Type
Signal Name
Description
VCC_SENSE and VSS_SENSE provide an isolated, low impedance
connection to the processor core voltage and ground. They can be
used to sense or measure voltage near the silicon.
VCC_SENSE
VSS_SENSE
O
Analog
VAXG_SENSE and VSSAXG_SENSE provide an isolated, low
impedance connection to the VAXG voltage and ground. They can
be used to sense or measure voltage near the silicon.
VAXG_SENSE
VSSAXG_SENSE
O
Analog
VCCIO_SENSE and VSS_SENSE_VCCIO provide an isolated, low
impedance connection to the processor VCCIO voltage and ground.
They can be used to sense or measure voltage near the silicon.
VCCIO_SENSE
VSS_SENSE_VCCIO
O
Analog
VDDQ_SENSE and VSS_SENSE_VDDQ provides an isolated, low
impedance connection to the VDDQ voltage and ground. They can
be used to sense or measure voltage near the silicon.
VDDQ_SENSE
VSS_SENSE_VDDQ
O
Analog
VCCSA_SENSE provide an isolated, low impedance connection to
the processor system agent voltage. It can be used to sense or
measure voltage near the silicon.
O
VCCSA_SENSE
Analog
Die Validation Sense:
O
VCC_DIE_SENSE
Analog
VCC_VAL_SENSE
VSS_VAL_SENSE
VCC Validation Sense:
O
Analog
VAXG_VAL_SENSE
V
AXG Validation Sense:
O
VSSAXG_VAL_SENSE
Analog
6.14
Ground and Non-Critical to Function (NCTF)
Signals
Table 6-16. Ground and Non-Critical to Function (NCTF) Signals
Direction/
Buffer Type
Signal Name
Description
VSS
Processor ground node
GND
Non-Critical to Function: These pins are for package mechanical
reliability.
VSS_NCTF
(BGA Only)
Daisy Chain- These pins are for solder joint reliability and non-critical to
function. For BGA only.
DC_TEST_xx#
Datasheet, Volume 1
83
Signal Description
6.15
Future Compatibility Signals
Table 6-17. Future Compatibility Signals
Direction/
Buffer Type
Signal Name
Description
This pin is for compatibility with future platforms. A pull-up resistor
to VCPLL is required if connected to the DF_TVS strap on the PCH.
PROC_SELECT#
Memory Channel A/B DIMM DQ Voltage Reference: These
signals are not used by the processors and are for future compatibility
only. No connection is required.
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Voltage selection for VCCIO: This pin must be pulled high on the
motherboard, when using dual rail voltage regulator, which will be
used for future compatibility.
VCCIO_SEL
Voltage selection for VCCSA: This pin must have a pull down
resistor to ground.
VCCSA_VID[0]
6.16
Processor Internal Pull-Up / Pull-Down Resistors
Table 6-18. Processor Internal Pull-Up / Pull-Down Resistors
Signal Name
Pull-Up / Pull-Down
Rail
Value
BPM[7:0]
PRDY#
PREQ#
TCK
Pull Up
Pull Up
Pull Up
Pull Down
Pull Up
Pull Up
Pull Up
Pull Up
VCCIO
VCCIO
VCCIO
VSS
65–165
65–165
65–165
5–15 k
5–15 k
5–15 k
5–15 k
5–15 k
TDI
VCCIO
VCCIO
VCCIO
VCCIO
TMS
TRST#
CFG[17:0]
§ §
84
Datasheet, Volume 1
Electrical Specifications
7 Electrical Specifications
7.1
Power and Ground Pins
The processor has VCC, VCCIO, VDDQ, VCCPLL, VCCSA, VAXG and VSS (ground) inputs
for on-chip power distribution. All power pins must be connected to their respective
processor power planes, while all VSS pins must be connected to the system ground
plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
The VCC pins and VAXG pins must be supplied with the voltage determined by the
processor Serial Voltage IDentification (SVID) interface. Table 7-1 specifies the voltage
level for the various VIDs.
7.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low- and full-power states. To keep
voltages within specification, output decoupling must be properly designed.
Caution:
Design the board to ensure that the voltage provided to the processor remains within
the specifications listed in Table 7-3. Failure to do so can result in timing violations or
reduced lifetime of the processor.
7.2.1
Voltage Rail Decoupling
The voltage regulator solution must:
• provide sufficient decoupling to compensate for large current swings generated
during different power mode transitions.
• provide low parasitic resistance from the regulator to the socket.
• meet voltage and current specifications as defined in Table 7-3.
7.2.2
PLL Power Supply
An on-die PLL filter solution is implemented on the processor.
Datasheet, Volume 1
85
Electrical Specifications
7.3
Voltage Identification (VID)
The VID specifications for the processor VCC and VAXG are defined by the VR12/IMVP7
SVID Protocol. The processor uses three signals for the serial voltage identification
interface to support automatic selection of voltages. Table 7-1 specifies the voltage
level corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this
table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
must disable itself. See the VR12/IMVP7 SVID Protocol for further details. The VID
codes will change due to temperature and/or current load changes in order to minimize
the power of the part. A voltage range is provided in Table 7-1. The specifications are
set so that one voltage regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in Table 7-5. The processor provides the ability to operate while
transitioning to an adjacent VID and its associated voltage. This will represent a DC
shift in the loadline.
Note:
Transitions above the maximum specified VID are not permitted. Table 7-5 includes VID
step sizes and DC shift ranges. Minimum and maximum voltages must be maintained.
The VR used must be capable of regulating its output to the value defined by the new
VID values issued. DC specifications for dynamic VID transitions are included in
Table 7-5 and Table 7-10. See the VR12/IMVP7 SVID Protocol for further details.
86
Datasheet, Volume 1
Electrical Specifications
h
Table 7-1.
IMVP7 Voltage Identification Definition (Sheet 1 of 3)
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
HEX VCC_MAX
HEX
VCC_MAX
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
9
0.00000
0.25000
0.25500
0.26000
0.26500
0.27000
0.27500
0.28000
0.28500
0.29000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
8
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0.88500
0.89000
0.89500
0.90000
0.90500
0.91000
0.91500
0.92000
0.92500
0.93000
0.93500
0.94000
0.94500
0.95000
0.95500
0.96000
0.96500
0.97000
0.97500
0.98000
0.98500
0.99000
0.99500
1.00000
1.00500
1.01000
1.01500
1.02000
1.02500
1.03000
1.03500
1.04000
1.04500
1.05000
1.05500
1.06000
1.06500
1.07000
1.07500
1.08000
1.08500
1.09000
1.09500
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
A
A
A
A
A
A
A
A
A
A
A
A 0.29500
B 0.30000
C 0.30500
D 0.31000
E
F
0
1
2
3
4
5
6
7
8
9
0.31500
0.32000
0.32500
0.33000
0.33500
0.34000
0.34500
0.35000
0.35500
0.36000
0.36500
0.37000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A 0.37500
B 0.38000
C 0.38500
D 0.39000
E
F
0
1
2
3
4
5
6
7
8
9
0.39500
0.40000
0.40500
0.41000
0.41500
0.42000
0.42500
0.43000
0.43500
0.44000
0.44500
0.45000
0
1
2
3
4
5
6
7
8
9
A
A 0.45500
Datasheet, Volume 1
87
Electrical Specifications
Table 7-1.
IMVP7 Voltage Identification Definition (Sheet 2 of 3)
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
HEX VCC_MAX
HEX
VCC_MAX
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
B 0.46000
C 0.46500
D 0.47000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
B
C
D
E
F
1.10000
1.10500
1.11000
1.11500
1.12000
1.12500
1.13000
1.13500
1.14000
1.14500
1.15000
1.15500
1.16000
1.16500
1.17000
1.17500
1.18000
1.18500
1.19000
1.19500
1.20000
1.20500
1.21000
1.21500
1.22000
1.22500
1.23000
1.23500
1.24000
1.24500
1.25000
1.25500
1.26000
1.26500
1.27000
1.27500
1.28000
1.28500
1.29000
1.29500
1.30000
1.30500
1.31000
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
E
F
0
1
2
3
4
5
6
7
8
9
0.47500
0.48000
0.48500
0.49000
0.49500
0.50000
0.50500
0.51000
0.51500
0.52000
0.52500
0.53000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A 0.53500
B 0.54000
C 0.54500
D 0.55000
E
F
0
1
2
3
4
5
6
7
8
9
0.55500
0.56000
0.56500
0.57000
0.57500
0.58000
0.58500
0.59000
0.59500
0.60000
0.60500
0.61000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A 0.61500
B 0.62000
C 0.62500
D 0.63000
E
F
0
1
2
3
4
5
0.63500
0.64000
0.64500
0.65000
0.65500
0.66000
0.66500
0.67000
0
1
2
3
4
5
88
Datasheet, Volume 1
Electrical Specifications
Table 7-1.
IMVP7 Voltage Identification Definition (Sheet 3 of 3)
VID VID VID VID VID VID VID VID
VID VID VID VID VID VID VID VID
HEX VCC_MAX
HEX
VCC_MAX
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
7
8
9
0.67500
0.68000
0.68500
0.69000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
6
7
8
9
A
B
C
D
E
F
1.31500
1.32000
1.32500
1.33000
1.33500
1.34000
1.34500
1.35000
1.35500
1.36000
1.36500
1.37000
1.37500
1.38000
1.38500
1.39000
1.39500
1.40000
1.40500
1.41000
1.41500
1.42000
1.42500
1.43000
1.43500
1.44000
1.44500
1.45000
1.45500
1.46000
1.46500
1.47000
1.47500
1.48000
1.48500
1.49000
1.49500
1.50000
1.50500
1.51000
1.51500
1.52000
D
D
D
D
D
D
D
D
D
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
A 0.69500
B 0.70000
C 0.70500
D 0.71000
E
F
0
1
2
3
4
5
6
7
8
9
0.71500
0.72000
0.72500
0.73000
0.73500
0.74000
0.74500
0.75000
0.75500
0.76000
0.76500
0.77000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A 0.77500
B 0.78000
C 0.78500
D 0.79000
E
F
0
1
2
3
4
5
6
7
8
9
0.79500
0.80000
0.80500
0.81000
0.81500
0.82000
0.82500
0.83000
0.83500
0.84000
0.84500
0.85000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
F
A 0.85500
B 0.86000
C 0.86500
D 0.87000
F
F
F
F
E
F
0.87500
0.88000
F
F
Datasheet, Volume 1
89
Electrical Specifications
7.4
System Agent (SA) VCC VID
The VccSA is configured by the processor output pins VCCSA_VID[1:0].
VCCSA_VID[0] output default logic state is low for the 2nd Generation Intel® Core™
processor family mobile and Intel® Celeron® processor family mobile. Logic high is
reserved for future compatibility.
VCCSA_VID[1] output default logic state is low – will not change the SA voltage. Logic
high will reduce the voltage.
Note:
During boot, the processor’s VccSA is 0.9 V.
Table 7-2 specifies the different VCCSA_VID configurations.
Table 7-2.
VCCSA_VID configuration
Selected VCCSA
(XE and SV
segments)
Selected VCCSA
(LV and ULV
segments)
Processor family
VCCSA_VID[0] VCCSA_VID[1]
2nd Generation Intel®
Core™ processor family
mobile, Intel® Celeron®
processor family mobile
0
0
0
1
0.9 V
0.8 V
0.9 V
0.85 V
Future Intel processors
1
1
0
1
Note 1
Note 1
Note 1
Note 1
Notes:
1.
Some of VCCSA configurations are reserved for future Intel processor families.
7.5
Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD – these signals should not be connected
• RSVD_TP – these signals should be routed to a test point
• RSVD_NCTF – these signals are non-critical to function and may be left un-
connected
Arbitrary connection of these signals to VCC, VCCIO, VDDQ, VCCPLL, VCCSA, VAXG, VSS, or
to any other signal (including each other) may result in component malfunction or
incompatibility with future processors. See Chapter 8 for a pin listing of the processor
and the location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
90
Datasheet, Volume 1
Electrical Specifications
7.6
Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 7-3. The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals, have On-
Die Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board.
Table 7-3.
Signal Groups1 (Sheet 1 of 3)
Signal Group
Type
Signals
System Reference Clock
BCLK, BCLK#
DPLL_REF_CLK, DPLL_REF_CLK#
Differential
CMOS Input
DDR3 Reference Clocks2
Differential
SA_CK[1:0], SA_CK#[1:0]
SB_CK[1:0], SB_CK#[1:0]
DDR3 Output
DDR3 Output
DDR3 Command Signals2
SA_BS[2:0], SB_BS[2:0]
SA_WE#, SB_WE#
SA_RAS#, SB_RAS#
SA_CAS#, SB_CAS#
SA_MA[15:0], SB_MA[15:0]
Single Ended
DDR3 Control Signals2
SA_CKE[1:0], SB_CKE[1:0]
SA_CS#[1:0], SB_CS#[1:0]
SA_ODT[1:0], SB_ODT[1:0]
SM_DRAMRST#
Single Ended
DDR3 Output
DDR3 Data Signals2
Single ended
DDR3 Bi-directional
DDR3 Bi-directional
SA_DQ[63:0], SB_DQ[63:0]
SA_DQS[7:0], SA_DQS#[7:0]
SB_DQS[7:0], SB_DQS#[7:0]
Differential
DDR3 Compensation
Analog Bi-directional
Analog Input
SM_RCOMP[2:0]
SM_VREF
DDR3 Reference
TAP (ITP/XDP)
Input
BCLK_ITP, BCLK_ITP#
TCK, TDI, TMS, TRST#
TDO
Single Ended
Single Ended
Single Ended
CMOS Input
Open-Drain Output
Output
DBR#
Asynchronous CMOS
Bi-Directional
Single Ended
Single Ended
Single Ended
BPM#[7:0]
PREQ#
Asynchronous CMOS
Input
Asynchronous CMOS
Output
PRDY#
Datasheet, Volume 1
91
Electrical Specifications
Table 7-3.
Signal Groups1 (Sheet 2 of 3)
Signal Group
Type
Signals
Control Sideband
Single Ended
CMOS Input
CFG[17:0]
PROCHOT#
Asynchronous
CMOS/Open Drain Bi-
directional
Single Ended
Asynchronous CMOS
Output
Single Ended
Single Ended
Single Ended
THERMTRIP#, CATERR#
Asynchronous CMOS
Input
SM_DRAMPWROK, UNCOREPWRGOOD4,
PM_SYNC, RESET#
Asynchronous Bi-
directional
PECI
Voltage Regulator
Single Ended
CMOS Input
VIDALERT#
VIDSCLK
Single Ended
Open Drain Output
CMOS Output
Single Ended
VCCSA_VID[1]
Bi-directional CMOS
Input/Open Drain
Output
Single Ended
Single Ended
VIDSOUT
VCCSA_SENSE
VCC_DIE_SENSE
Analog Output
VCC_SENSE, VSS_SENSE
VCCIO_SENSE, VSS_SENSE_VCCIO
VAXG_SENSE, VSSAXG_SENSE
VCC_VAL_SENSE, VSS_VAL_SENSE
VAXG_VAL_SENSE, VSSAXG_VAL_SENSE
Differential
Analog Output
Power / Ground / Other
3
VCC, VCCIO, VCCSA, VCCPLL, VDDQ, VAXG, VCCPQE ,
Power
3
VCCDQ
3
Ground
VSS, VSS_NCTF , DC_TEST_xx#
Single Ended
No Connect
Test Point
Other
RSVD, RSVD_NCTF
RSVD_TP
SKTOCC#, PROC_DETECT#3
PCI Express* Graphics
Differential
PCI Express Input
PCI Express Output
Analog Input
PEG_RX[15:0], PEG_RX#[15:0]
Differential
PEG_TX[15:0], PEG_TX#[15:0]
Single Ended
PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO
Embedded DisplayPort*
Differential
eDP Output
eDP_TX[3:0], eDP_TX#[3:0]
eDP_AUX, eDP_AUX#
Differential
eDP Bi-directional
Asynchronous CMOS
Input
Single Ended
eDP_HPD#
Single Ended
Analog Input
eDP_ICOMPO, eDP_COMPIO
Direct Media Interface (DMI)
Differential
Differential
DMI Input
DMI_RX[3:0], DMI_RX#[3:0]
DMI_TX[3:0], DMI_TX#[3:0]
DMI Output
92
Datasheet, Volume 1
Electrical Specifications
Table 7-3.
Signal Groups1 (Sheet 3 of 3)
Signal Group
Intel® FDI
Type
Signals
FDI0_FSYNC, FDI1_FSYNC, FDI0_LSYNC,
FDI1_LSYNC
Single Ended
Single Ended
CMOS Input
Asynchronous CMOS
Input
FDI_INT
FDI0_TX[3:0], FDI0_TX#[3:0], FDI1_TX[3:0],
FDI1_TX#[3:0]
Differential
FDI Output
Future Compatibility
PROC_SELECT#,
VCCSA_VID[0],
VCCIO_SEL,
SA_DIMM_VREFDQ, SB_DIMM_VREFDQ
Notes:
1.
2.
3.
4.
Refer to Chapter 6 for signal description details.
SA and SB refer to DDR3 Channel A and DDR3 Channel B.
These signals only apply to BGA packages.
The maximum rise/fall time of UNCOREPWRGOOD is 20 ns.
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least 10 BCLKs with a maximum Trise/Tfall of 6 ns for the processor to recognize
the proper signal state. See Section 7.10 for the DC specifications.
7.7
7.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.6-
2003 standards. Some small portion of the I/O pins may support only one of these
standards.
Storage Condition Specifications
Environmental storage condition limits define the temperature and relative humidity
that the device is exposed to while being stored in a moisture barrier bag. The specified
storage conditions are for component level prior to board attach.
Table 7-5 specifies absolute maximum and minimum storage temperature limits that
represent the maximum or minimum device condition beyond which damage, latent or
otherwise, may occur. The table also specifies sustained storage temperature, relative
humidity, and time-duration limits. These limits specify the maximum or minimum
device storage conditions for a sustained period of time. Failure to adhere to the
following specifications can affect long term reliability of the processor.
Datasheet, Volume 1
93
Electrical Specifications
Table 7-4.
Storage Condition Ratings
Symbol
Parameter
Min
Max
Notes
The non-operating device storage
temperature. Damage (latent or otherwise)
may occur when exceeded for any length of
time.
Tabsolute storage
-25 °C
125 °C
1, 2, 3, 4
The ambient storage temperature (in shipping
media) for a sustained period of time
Tsustained storage
Tshort term storage
RHsustained storage
-5 °C
40 °C
85 °C
5, 6
The ambient storage temperature (in shipping
media) for a short period of time.
-20 °C
The maximum device storage relative humidity
for a sustained period of time.
60% at 24 °C
6, 7
7
A prolonged or extended period of time;
typically associated with customer shelf life.
30
Months
Timesustained storage
Timeshort term storage
Notes:
0 Months
0 hours
A short-period of time;
72 hours
1.
2.
3.
4.
5.
Refers to a component device that is not assembled in a board or socket and is not electrically connected to
a voltage reference or I/O signal.
Specified temperatures are not to exceed values based on data collected. Exceptions for surface mount
reflow are specified by the applicable JEDEC standard. Non-adherence may affect processor reliability.
Tabsolute storage applies to the unassembled component only and does not apply to the shipping media,
moisture barrier bags, or desiccant.
Component product device storage temperature qualification methods may follow JESD22-A119 (low temp)
and JESD22-A103 (high temp) standards when applicable for volatile memory.
Intel branded products are specified and certified to meet the following temperature and humidity limits
that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50%
to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits
are not specified for non-Intel branded boards.
6.
7.
The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisture
sensitive devices removed from the moisture barrier bag.
Nominal temperature and humidity conditions and durations are given and tested within the constraints
imposed by Tsustained storage and customer shelf life in applicable Intel boxes and bags.
7.9
DC Specifications
The processor DC specifications in this section are defined at the processor
pins, unless noted otherwise. See Chapter 8 for the processor pin listings and
Chapter 6 for signal definitions.
• The DC specifications for the DDR3 signals are listed in Table 7-11. Control
Sideband and Test Access Port (TAP) are listed in Table 7-12.
• Table 7-5 lists the DC specifications for the processor and are valid only while
meeting specifications for junction temperature, clock frequency, and input
voltages. Care should be taken to read all notes associated with each parameter.
• AC tolerances for all DC rails include dynamic load currents at switching frequencies
up to 1 MHz.
94
Datasheet, Volume 1
Electrical Specifications
7.9.1
Voltage and Current Specifications
Table 7-5.
Processor Core (VCC) Active and Idle Mode DC Voltage and Current
Specifications (Sheet 1 of 2)
Symbol
Parameter
Segment
Min
Typ
Max
Unit
Note
XE
0.8
0.8
0.8
0.75
0.7
1.35
1.35
1.35
1.3
SV-QC
SV-DC
LV
VID Range for Highest
Frequency Mode (Includes
Turbo Mode Operation)
1, 2, 6,
8
HFM_VID
—
V
ULV
1.2
XE
0.65
0.65
0.65
0.65
0.65
0.95
0.95
0.95
0.9
SV-QC
SV-DC
LV
VID Range for Lowest
Frequency Mode
LFM_VID
VCC
—
V
V
A
1, 2, 8
2, 3
ULV
0.9
VCC for processor core
0.3–1.52
—
XE
97
94
53
43
33
SV-QC
SV-DC
LV
Maximum Processor Core
ICC
ICCMAX
—
—
—
—
4, 6, 8
ULV
XE
62
52
36
25
21.5
SV-QC
SV-DC
LV
ICC_TDC
Thermal Design ICC
—
—
—
A
A
5, 6, 8
ULV
XE
31
28
11.6
17.6
12.5
SV-QC
SV-DC
LV
ICC_LFM
ICC at LFM
5
ULV
XE
6
SV-QC
SV-DC
LV
5.5
2.5
3.8
2.6
IC6/C7
ICC at C6/C7 Idle-state
Voltage Tolerance
A
10
ULV
PS0
—
—
—
—
—
—
±15
±12
TOLVCC
PS1
mV
7, 9
PS2, PS3
±11.5
±15
PS0 &
Icc >
TDC+30%
—
—
—
—
PS0 &
Icc
TDC+30%
±10
Ripple
Ripple Tolerance
VID resolution
mV
mV
7, 9
PS1
PS2
PS3
—
—
—
—
—
—
—
5
±13
-7.5/ +18.5
-7.5/ +27.5
—
VR Step
Datasheet, Volume 1
95
Electrical Specifications
Table 7-5.
Processor Core (VCC) Active and Idle Mode DC Voltage and Current
Specifications (Sheet 2 of 2)
Symbol
Parameter
Segment
Min
Typ
Max
Unit
Note
XE
-1.9
-1.9
-1.9
-2.9
-2.9
SV-QC
SV-DC
LV
SLOPELL
Processor Loadline
—
—
mΩ
ULV
Notes:
1.
Unless otherwise noted, all specifications in this table are based on post-silicon estimates and simulations
or empirical data.
2.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. This
differs from the VID employed by the processor during a power or thermal management event (Intel
Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
3.
4.
5.
6.
7.
8.
9.
Processor core VR to be designed to electrically support this current.
Processor core VR to be designed to thermally support this current indefinitely.
This specification assumes that Intel Turbo Boost Technology is enabled.
Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated.
Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
PSx refers to the voltage regulator power state as set by the SVID protocol.
10. Idle power specification is measured under temperature condition of 35 oC.
Table 7-6.
Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
Voltage for the memory controller
and shared cache defined at the
motherboard VCCIO_SENSE and
VSS_SENSE_VCCIO
VCCIO
—
1.05
—
V
VCCIO Tolerance defined across
VCCIO_SENSE and VSS_SENSE_VCCIO
DC: ±2% including ripple
AC: ±3%
TOLCCIO
%
A
ICCMAX_VCCIO
ICCTDC_VCCIO
Max Current for VCCIO Rail
—
—
—
—
8.5
8.5
Thermal Design Current (TDC) for
VCCIO Rail
A
Note: Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
96
Datasheet, Volume 1
Electrical Specifications
Table 7-7.
Memory Controller (VDDQ) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
Processor I/O supply voltage for
DDR3 (DC + AC specification)
VDDQ(DC+AC)
—
1.5
—
V
VDDQ Tolerance
DC= ±3%
AC= ±2%
TOLDDQ
%
AC+DC= ±5%
ICCMAX_VDDQ
Max Current for VDDQ Rail
—
—
—
5
A
1
Average Current for VDDQ Rail
during Standby
ICCAVG_VDDQ
(Standby)
66
133
mA
Notes:
1. The current supplied to the SO-DIMM modules is not included in this specification.
Table 7-8.
System Agent (VCCSA) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
Voltage for the System Agent and
VCCSA_SENSE
VCCSA
0.75
—
0.90
V
TOLCCSA
VCCSA Tolerance
AC+DC= ±5%
—
%
A
ICCMAX_VCCSA
Max Current for VCCSA Rail
—
—
6
6
Thermal Design Current (TDC) for
VCCSA Rail
ICCTDC_VCCSA
Slew Rate
—
—
A
Voltage Ramp rate (dV/dT)
0.5
10
mV/us
Note: Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
Table 7-9.
Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
PLL supply voltage (DC + AC
specification)
VCCPLL
—
1.8
v
V
TOLCCPLL
VCCPLL Tolerance
AC+DC= ±5%
—
%
A
ICCMAX_VCCPLL Max Current for VCCPLL Rail
—
—
1.2
1.2
Thermal Design Current (TDC) for
VCCPLL Rail
ICCTDC_VCCPLL
—
A
Note: Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
Datasheet, Volume 1
97
Electrical Specifications
Table 7-10. Processor Graphics (VAXG) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note1,5
Active VID Range for VAXG
XE, SV-QC, SV-DC
LV
ULV
0.65
0.65
0.65
1.35
1.35
1.35
GFX_VID
VAXG
—
V
V
2, 3
Processor Graphics core voltage
0 – 1.52
Max Current for Processor
Graphics Rail
XE, SV-QC, SV-DC (GT2)
SV-DC (GT1)
LV (GT2)
ULV (GT2)
ULV (GT1)
33
24
33
26
16
ICCMAX_VAXG
—
—
—
—
A
A
Thermal Design Current (TDC)
for Processor Graphics Rail
XE, SV-QC, SV-DC (GT2)
SV-DC (GT1)
LV (GT2)
21.5
20
21.5
10
ICCTDC_VAXG
ULV (GT2)
ULV (GT1)
8
VAXG Tolerance
Ripple Tolerance
PS0,PS1
PS2,PS3
PS0, PS1
PS2
—
—
—
—
—
±15
±11.5
mV
mV
mV
mV
mV
4
4
4
4
TOLAXG
Ripple
±18
-7.5/+18.5
-7.5/+27.5
PS3
VAXG Loadline
LLAXG
GT2 based units
GT1 based units
-3.9
-4.6
m
Notes:
1.
Unless otherwise noted, all specifications in this table are based on post-silicon estimates and simulations
or empirical data.
2.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. This
differs from the VID employed by the processor during a power or thermal management event (Intel
Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
3.
4.
5.
PSx refers to the voltage regulator power state as set by the SVID protocol.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. This
differs from the VID employed by the processor during a power or thermal management event (Intel
Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
98
Datasheet, Volume 1
Electrical Specifications
Table 7-11. DDR3 Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Min
Typ
Max
Units Notes1
VIL
VIH
VIL
VIH
—
SM_VREF + 0.1
—
—
—
—
—
SM_VREF -0.1
V
V
V
V
2, 4, 11
3, 11
10
Input High Voltage
—
VDDQ*0.55 -0.1
—
Input Low Voltage (SM_DRAMPWROK)
Input High Voltage (SM_DRAMPWROK) VDDQ*0.55 +0.1
10
Output Low Voltage
—
(VDDQ / 2)* (RON
/(RON+RTERM))
VOL
VOH
—
—
6
Output High Voltage
—
VDDQ - ((VDDQ / 2)*
(RON/(RON+RTERM))
V
4, 6
RON_UP(DQ) DDR3 Data Buffer pull-up Resistance
RON_DN(DQ) DDR3 Data Buffer pull-down Resistance
24.31
22.88
28.6
28.6
32.9
5
5
34.32
DDR3 On-die termination equivalent
RODT(DQ)
83
41.5
100
50
117
65
resistance for data signals
DDR3 On-die termination DC working
VODT(DC)
0.43*VCC
0.5*VCC
0.56*VCC
V
point (driver set to receive mode)
RON_UP(CK) DDR3 Clock Buffer pull-up Resistance
RON_DN(CK) DDR3 Clock Buffer pull-down Resistance
20.8
20.8
26
26
28.6
31.2
5
5
DDR3 Command Buffer pull-up
RON_UP(CMD)
Resistance
16
20
22
5
DDR3 Command Buffer pull-down
RON_DN(CMD)
Resistance
16
16
16
20
20
20
24
22
24
5
5
5
RON_UP(CTL) DDR3 Control Buffer pull-up Resistance
DDR3 Control Buffer pull-down
RON_DN(CTL)
Resistance
Input Leakage Current (DQ, CK)
0V
0.2*VDDQ
0.8*VDDQ
VDDQ
± 0.75
± 0.55
± 0.9
ILI
—
—
—
—
mA
mA
± 1.4
Input Leakage Current (CMD, CTL)
0V
0.2*VDDQ
0.8*VDDQ
VDDQ
± 0.85
± 0.65
± 1.10
± 1.65
ILI
SM_RCOMP0 Command COMP Resistance
SM_RCOMP1 Data COMP Resistance
SM_RCOMP2 ODT COMP Resistance
138.6
25.74
198
140
26
141.4
26.26
202
8
8
8
200
Notes:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
value.
3.
4.
VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply with the
signal quality specifications.
This is the pull up/down driver resistance.
5.
6.
7.
8.
RTERM is the termination on the DIMM and in not controlled by the Processor.
The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx resistors
are to VSS
.
9.
DDR3 values are pre-silicon estimations and are subject to change.
10. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDDQ * 0.55 ±200 mV and the
edge must be monotonic.
11. SM_VREF is defined as VDDQ/2.
Datasheet, Volume 1
99
Electrical Specifications
Table 7-12. Control Sideband and TAP Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Min
Max
Units
Notes1
VIL
VIH
VOL
VOH
RON
ILI
—
VCCIO * 0.3
V
V
2
Input High Voltage
Output Low Voltage
Output High Voltage
Buffer on Resistance
Input Leakage Current
VCCIO * 0.7
—
VCCIO * 0.1
—
2, 4
2
—
V
VCCIO * 0.9
V
2, 4
23
—
73
A
±200
3
Notes:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
The VCCIO referred to in these specifications refers to instantaneous VCCIO
.
For VIN between 0 V and VCCIO. Measured when the driver is tristated.
VIH and VOH may experience excursions above VCCIO. However, input signal drivers must comply with the
signal quality specifications.
.
Table 7-13. PCI Express* DC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes1
Differential Peak-to-Peak Tx Voltage
Swing
VTX-DIFF-p-p
0.4
0.5
0.6
V
3
Tx AC Peak Common Mode Output
Voltage (Gen 1 Only)
VTX_CM-AC-p
0.8
1
1.2
mV
1, 2, 6
DC Differential Tx Impedance (Gen 1
Only)
ZTX-DIFF-DC
ZRX-DC
80
40
80
—
—
—
120
60
1, 10
1, 8, 9
1
DC Common Mode Rx Impedance
DC Differential Rx Impedance (Gen1
Only)
ZRX-DIFF-DC
120
Differential Rx Input Peak-to-Peak
Voltage (Gen 1 only)
VRX-DIFFp-p
0.175
—
1.2
V
1, 11
VRX_CM-AC-p
PEG_ICOMPO
PEG_ICOMPI
PEG_RCOMPO
Rx AC Peak Common Mode Input Voltage
Comp Resistance
—
—
25
25
25
150
mV
1, 7
4, 5
4, 5
4, 5
24.75
24.75
24.75
25.25
25.25
25.25
Comp Resistance
Comp Resistance
Notes:
1.
2.
Refer to the PCI Express Base Specification for more details.
VTX-AC-CM-PP and VTX-AC-CM-P are defined in the PCI Express Base Specification. Measurement is made over
at least 10^6 UI.
3.
4.
5.
6.
7.
As measured with compliance test load. Defined as 2*|VTXD+ – VTXD- |.
COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to VCCIO
PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor. Intel allows using 24.9 1% resistors.
RMS value.
Measured at Rx pins into a pair of 50-terminations into ground. Common mode peak voltage is defined by
the expression: max{|(Vd+ - Vd-) – V-CMDC|}.
DC impedance limits are needed to ensure Receiver detect.
.
8.
9.
The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to
ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately
and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 ±20%) must be within the
specified range by the time Detect is entered.
10. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
11. This specification is the same as VRX-EYE
100
Datasheet, Volume 1
Electrical Specifications
Table 7-14. Embedded DisplayPort* DC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
eDP_HPD#
VIL
Input Low Voltage
Input High Voltage
-0.1
—
—
0.3 * VCCIO
VCCIO
V
V
VIH
0.7 * VCCIO
eDP_AUX, eDP_AUX#
AUX Peak-to-Peak Voltage at the
transmitting device
0.4
—
—
0.6
1
1
V
AUX-DIFFp-p (Tx)
AUX Peak-to-Peak Voltage at the
receiving device
0.32
1.36
V
VAUX-DIFFp-p (Rx)
eDP COMPs
eDP_ICOMPI
eDP_COMPIO
Comp Resistance
Comp Resistance
24.75
24.75
25
25
25.25
25.25
2, 3
2, 3
Notes:
1.
VAUX-DIFFp-p = 2*|VAUXP – VAUXM|. Refer to the VESA DisplayPort Standard specification for more
details.
2.
3.
COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to VSS
.
eDP_ICOMPO, eDP_ICOMPI, eDP_RCOMPO are the same resistor.
7.10
Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external Adaptive Thermal Monitor devices.
The processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read the DTS temperature for thermal management and fan speed control. More
detailed information may be found in the Platform Environment Control Interface
(PECI) Specification.
7.10.1
PECI Bus Architecture
The PECI architecture based on wired OR bus that the clients (such as 2nd Generation
Intel® Core™ processor family mobile PECI) can pull up high (with strong drive).
The idle state on the bus is near zero.
Figure 7-1 demonstrates PECI design and connectivity, while the host/originator can be
3rd party PECI host, and one of the PECI client is a 2nd Generation Intel® Core™
processor family mobile PECI and Intel® Celeron® processor family mobile PECI device.
Datasheet, Volume 1
101
Electrical Specifications
Figure 7-1. Example for PECI Host-clients Connection
7.10.2
PECI DC Characteristics
The PECI interface operates at a nominal voltage set by VCCIO The set of DC electrical
specifications shown in Table 7-15 are used with devices normally operating from a
V
CCIO interface supply. VCCIO nominal levels will vary between processor families. All
PECI devices will operate at the VCCIO level determined by the processor installed in the
system. For specific nominal VCCIO levels, refer to Table 7-6.
Table 7-15. PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes1
Rup
Vin
Internal pull up resistance
Input Voltage Range
15
45
Ohm
V
3
-0.15
VCCIO
Vhysteresis
Vn
Hysteresis
0.1 * VCCIO
N/A
V
Negative-Edge Threshold Voltage
Positive-Edge Threshold Voltage
Bus Capacitance per Node
Pad Capacitance
0.275 * VCCIO
0.500 * VCCIO
V
Vp
0.550 * VCCIO
0.725 * VCCIO
V
Cbus
N/A
0.7
—
10
1.8
pF
pF
mA
mA
mA
mA
mA
Cpad
Ileak000
Ileak025
Ileak050
Ileak075
Ileak100
leakage current @ 0V
0.6
2
2
2
2
2
leakage current @ 0.25*VCCIO
leakage current @ 0.50*VCCIO
leakage current @ 0.75*VCCIO
leakage current @ VCCIO
—
0.4
—
0.2
—
0.13
0.10
—
Notes:
1.
2.
3.
VCCIO supplies the PECI interface. PECI behavior does not affect VCCIO min/max specifications.
The leakage specification applies to powered devices on the PECI bus.
The PECI buffer internal pull up resistance measured at 0.75*VCCIO
102
Datasheet, Volume 1
Electrical Specifications
7.10.3
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design.
Figure 7-2. Input Device Hysteresis
§ §
Datasheet, Volume 1
103
Electrical Specifications
104
Datasheet, Volume 1
Processor Pin and Signal Information
8 Processor Pin and Signal
Information
8.1
Processor Pin Assignments
• Table 8-1, Table 8-2 and Table 8-3 all pins ordered alphabetically for the rPGA988B
BGA1224 and BGA1023 package respectively.
• Figure 8-1, Figure 8-2, Figure 8-3 and Figure 8-4 show the Top-Down view of the
rPGA988B pinmap.
• Figure 8-5, Figure 8-6, Figure 8-7 and Figure 8-8 show the Top-Down view of the
BGA1224 ballmap.
• Figure 8-9, Figure 8-10, Figure 8-11 and Figure 8-12 show the Top-Down view of
the BGA1023 ballmap.
Datasheet, Volume 1
105
Processor Pin and Signal Information
Figure 8-1. rPGA988B (Socket-G2) Pinmap (Top View, Upper-Left Quadrant)
106
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-2. rPGA988B (Socket-G2) Pinmap (Top View, Upper-Right Quadrant)
Datasheet, Volume 1
107
Processor Pin and Signal Information
Figure 8-3. rPGA988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant)
108
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-4. rPGA988B (Socket-G2) Pinmap (Top View, Lower-Right Quadrant)
Datasheet, Volume 1
109
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
BCLK
BCLK#
A28
A27
Diff Clk
Diff Clk
Diff Clk
Diff Clk
I
I
DMI_TX[3]
DPLL_REF_CLK
DPLL_REF_CLK#
eDP_AUX
C21
A16
A15
C15
D15
A18
DMI
Diff Clk
Diff Clk
eDP
O
I
BCLK_ITP
BCLK_ITP#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
CATERR#
CFG[0]
AN35
AM35
I
I
I
I/O
I/O
I
AT28 Asynch CMOS
AR29 Asynch CMOS
AR30 Asynch CMOS
AT30 Asynch CMOS
AP32 Asynch CMOS
AR31 Asynch CMOS
AT31 Asynch CMOS
AR32 Asynch CMOS
AL33 Asynch CMOS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
eDP_AUX#
eDP
eDP_COMPIO
eDP_HPD#
eDP_ICOMPO
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
Analog
B16 Asynch CMOS
I
A17
C18
E16
D16
F15
C17
F16
C16
G15
Analog
eDP
eDP
eDP
eDP
eDP
eDP
eDP
eDP
I
O
O
O
O
O
O
O
O
I
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
eDP_TX[1]
CFG[1]
I
eDP_TX[2]
CFG[2]
I
eDP_TX[3]
CFG[3]
I
FDI_INT
H20 Asynch CMOS
CFG[4]
I
FDI0_FSYNC
FDI0_LSYNC
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_FSYNC
FDI1_LSYNC
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
KEY
J18
J19
CMOS
CMOS
FDI
I
CFG[5]
I
I
CFG[6]
I
A21
H19
E19
F18
A22
G19
E20
G18
J17
O
O
O
O
O
O
O
O
I
CFG[7]
I
FDI
CFG[8]
I
FDI
CFG[9]
I
FDI
CFG[10]
I
FDI
CFG[11]
I
FDI
CFG[12]
I
FDI
CFG[13]
I
FDI
CFG[14]
I
CMOS
CMOS
FDI
CFG[15]
I
H17
B21
C20
D18
E17
B20
C19
D19
F17
B1
I
CFG[16]
I
O
O
O
O
O
O
O
O
N/A
I/O
I
CFG[17]
I
FDI
DBR#
AL35 Asynch CMOS
O
I
FDI
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
FDI
I
FDI
I
FDI
I
FDI
I
FDI
I
N/A
I
PECI
AN33
J22
Asynch
Analog
Analog
Analog
PCIe
PCIe
PCIe
PCIe
PCIe
I
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
O
O
O
O
O
O
O
J21
I
H22
K33
M35
L34
J35
I
I
I
I
I
J32
I
110
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
I
I
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PM_SYNC
PRDY#
L28
K30
K27
J29
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
J27
I
H28
G28
E28
F28
D27
E26
D25
I
I
I
I
I
I
PEG_RX[1]
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
I
AM34 Asynch CMOS
AP29 Asynch CMOS
AP27 Asynch CMOS
PEG_RX[2]
I
O
I
PEG_RX[3]
I
PREQ#
PEG_RX[4]
I
PROC_SELECT#
PROCHOT#
RESET#
RSVD
C26
N/A
O
I/O
I
PEG_RX[5]
I
AL32 Asynch CMOS
PEG_RX[6]
I
AR33 Asynch CMOS
PEG_RX[7]
I
C30
A31
B30
B29
D30
B31
A30
C29
F25
F24
F23
D24
G25
G24
E23
D23
AT26
AG7
AE7
W8
PEG_RX[8]
I
RSVD
PEG_RX[9]
I
RSVD
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
I
RSVD
I
RSVD
I
RSVD
I
RSVD
I
RSVD
I
RSVD
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
J28
RSVD
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
RSVD
RSVD
RSVD
T8
RSVD
L7
RSVD
J20
RSVD
J16
RSVD
AM33
J15
RSVD
PEG_TX[1]
RSVD
H16
G16
B18
PEG_TX[2]
RSVD
PEG_TX[3]
RSVD
Datasheet, Volume 1
111
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
RSVD
AK32
AK2
AJ32
AJ27
AJ26
AT34
B35
B34
A34
A33
AT33
AT2
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_DIMM_VREFDQ
SA_DQ[0]
V10
AK3
AL3
B4
DDR3
DDR3
DDR3
N/A
O
RSVD
O
RSVD
O
RSVD
O
RSVD
C5
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_CK#[0]
SA_CK#[1]
SA_CK[0]
SA_CK[1]
SA_CKE[0]
SA_DQ[1]
D5
SA_DQ[2]
D3
SA_DQ[3]
D2
SA_DQ[4]
D6
SA_DQ[5]
C6
SA_DQ[6]
C2
SA_DQ[7]
C3
AT1
SA_DQ[8]
F10
F8
AR35
AR34
AR1
AP35
C35
W9
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
G10
G9
F9
F7
G8
W10
AA4
AA3
AB4
AB3
AG1
AH1
AG2
AH2
T9
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
T10
AA2
AB1
AB2
AA1
AD6
AE6
AD5
AE5
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AE10
AF10
V6
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
O
O
O
O
O
O
O
O
AE8
AA6
AB5
AB6
AA5
V9
112
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
AK9
AH8
AH9
AL9
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_ODT[0]
SA_ODT[1]
SA_RAS#
AD8
V4
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
N/A
O
O
W4
AF8
V5
O
O
AL8
O
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
C4
V7
O
AH3
AG3
AD9
AF9
AA9
AA7
R6
O
O
O
SA_WE#
O
SB_BS[0]
O
SB_BS[1]
O
SB_BS[2]
O
SB_CAS#
AA10
AD2
AD1
AE2
AE1
R9
O
SB_CK#[0]
SB_CK#[1]
SB_CK[0]
O
O
O
SB_CK[1]
O
SB_CKE[0]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_DIMM_VREFDQ
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
O
R10
AD3
AE3
D1
O
O
O
G6
O
J3
C9
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M6
A7
AL6
D10
C8
AM8
AR12
AM15
D4
A9
A8
D9
F6
D8
K3
G4
N6
F4
AL5
F1
AM9
AR11
AM14
AD10
W1
G1
G5
F5
F2
SA_MA[1]
O
G2
SA_MA[2]
W2
O
J7
SA_MA[3]
W7
O
J8
SA_MA[4]
V3
O
K10
K9
SA_MA[5]
V2
O
SA_MA[6]
W3
O
J9
SA_MA[7]
W6
O
J10
K8
SA_MA[8]
V1
O
SA_MA[9]
W5
O
K7
Datasheet, Volume 1
113
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
M5
N4
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_ODT[0]
SB_ODT[1]
SB_RAS#
SB_WE#
AP15
C7
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
Analog
Asynch CMOS
DDR3
Analog
Analog
Analog
Analog
CMOS
CMOS
CMOS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
N2
G3
N1
J6
M4
M3
N5
AN6
AP8
AK11
AP14
AA8
T7
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
D7
O
R7
O
T6
O
T2
O
T4
O
T3
O
R2
O
T5
O
R3
O
AB7
R1
O
O
T1
O
AB10
R5
O
O
R4
O
AE4
AD4
AB8
AB9
AN34
V8
O
O
O
O
SKTOCC#
SM_DRAMPWROK
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
SM_VREF
O
I
R8
O
AK1
A5
I/O
I/O
I/O
I
A4
AL1
AR26
AR28
AP26
TCK
I
TDI
I
TDO
O
THERMTRIP#
TMS
AN32 Asynch CMOS
O
AR27
AP30
CMOS
CMOS
I
F3
TRST#
I
K6
UNCOREPWRGOOD
VAXG
AP33 Asynch CMOS
I
N3
AH17
AH18
AH20
AH21
PWR
PWR
PWR
PWR
AN5
AP9
AK12
VAXG
VAXG
VAXG
114
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
AH23
AH24
AJ17
AJ18
AJ20
AJ21
AJ23
AJ24
AK17
AK18
AK20
AK21
AK23
AK24
AL17
AL18
AL20
AL21
AL23
AL24
AM17
AM18
AM20
AM21
AM23
AM24
AN17
AN18
AN20
AN21
AN23
AN24
AP17
AP18
AP20
AP21
AP23
AP24
AR17
AR18
AR20
AR21
AR23
AR24
AT17
AT18
AT20
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VAXG
VAXG
VAXG
VAXG_SENSE
VAXG_VAL_SENSE
VCC
AT21
AT23
AT24
AK35
AJ31
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AG27
PWR
PWR
PWR
Analog
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
O
O
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Datasheet, Volume 1
115
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AG35
P26
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VCC
VCC
V35
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
AH27
AJ35
AJ33
J23
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
Analog
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
P27
VCC
P28
VCC
P29
VCC_DIE_SENSE
VCC_SENSE
VCC_VAL_SENSE
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
O
O
O
P30
P31
P32
P33
A11
A12
AC10
AG10
AH10
AH13
B12
C11
C12
D11
D12
E11
E12
F11
P34
P35
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
V26
V27
V28
V29
V30
V31
V32
V33
V34
F12
G12
H11
H12
J11
J12
L10
P10
U10
Y10
A13
A14
B14
C13
C14
D13
D14
E14
116
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
VCCIO
VCCIO
F13
F14
G13
G14
H14
J13
J14
A19
B10
A2
PWR
PWR
PWR
PWR
PWR
PWR
PWR
N/A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A35
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AC2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO_SEL
VCCIO_SENSE
VCCPLL
VCCPLL
VCCPLL
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VDDQ
O
O
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
CMOS
CMOS
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
CMOS
CMOS
CMOS
GND
GND
GND
GND
GND
GND
A6
B6
H25
H26
J24
J25
J26
L26
M26
M27
H23
C22
C24
AC1
AC4
AC7
AF1
AF4
AF7
P1
AC3
AC5
AC6
AC8
AC9
AD7
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE9
O
O
O
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
AF2
VDDQ
P4
AF3
VDDQ
P7
AF5
VDDQ
U1
AF6
VDDQ
U4
AG4
VDDQ
U7
AG8
VDDQ
Y1
AG9
VDDQ
Y4
AH16
AH19
AH22
AH25
AH26
AH28
AH29
AH30
AH32
AH34
AH35
VDDQ
Y7
VIDALERT#
VIDSCLK
VIDSOUT
VSS
AJ29
AJ30
AJ28
A20
A23
A26
A29
A3
I
O
I/O
VSS
VSS
VSS
VSS
VSS
A32
Datasheet, Volume 1
117
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH4
AH7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM7
AN10
AN13
AN16
AN19
AN22
AN25
AN27
AN30
AN4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AJ1
AJ10
AJ13
AJ16
AJ19
AJ2
AJ22
AJ25
AJ3
AN7
AJ4
AP1
AJ7
AP10
AP13
AP16
AP19
AP22
AP25
AP28
AP31
AP34
AP4
AK10
AK13
AK16
AK19
AK22
AK25
AK27
AK30
AK33
AK4
AP7
AK7
AR10
AR13
AR16
AR19
AR2
AL10
AL13
AL16
AL19
AL2
AR22
AR25
AR4
AL22
AL25
AL28
AL31
AL34
AL4
AR7
AT10
AT13
AT16
AT19
AT22
AT25
AT27
AT29
AT3
AL7
AM1
AM10
AM13
AM16
AM19
AM2
AT32
AT35
AT4
AM22
AM25
AM29
AM3
AT7
B11
AM4
B13
118
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B15
B17
B19
B2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G17
G20
G23
G26
G29
G32
G35
H1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B22
B3
B5
B7
B8
H10
H13
H15
H18
H2
B9
C1
C10
C23
C25
C27
C28
C31
C34
D17
D20
D26
D29
D32
D35
E1
H21
H24
H27
H3
H30
H33
H4
H5
H6
H7
H8
H9
E10
E13
E15
E18
E2
J31
J34
K26
K29
K32
K35
L1
E21
E24
E27
E3
L2
L27
L3
E30
E4
L30
L33
L4
E5
E6
E7
L5
E8
L6
E9
L8
F19
F22
F29
F31
F34
G11
L9
M34
N26
N27
N28
N29
Datasheet, Volume 1
119
Processor Pin and Signal Information
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Table 8-1.
rPGA988B Processor Pin
List by Pin Name
Pin Name
Pin # Buffer Type
Dir
Pin Name
Pin # Buffer Type
Dir
VSS
VSS
N30
N31
N32
N33
N34
N35
P2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Analog
Analog
VSS_VAL_SENSE
VSSAXG_SENSE
AH33
AK34
Analog
Analog
Analog
O
O
O
VSS
VSSAXG_VAL_SENSE AH31
VSS
VSS
VSS
VSS
VSS
P3
VSS
P5
VSS
P6
VSS
P8
VSS
P9
VSS
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
U2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U3
VSS
U5
VSS
U6
VSS
U8
VSS
U9
VSS
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
Y2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y3
VSS
Y5
VSS
Y6
VSS
Y8
VSS
Y9
VSS_SENSE
VSS_SENSE_VCCIO
AJ34
A10
O
O
120
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-5. BGA1224 Ballmap (Top View, Upper-Left Quadrant)
Datasheet, Volume 1
121
Processor Pin and Signal Information
Figure 8-6. BGA1224 Ballmap (Top View, Upper-Right Quadrant)
122
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-7. BGA1224 Ballmap (Top View, Lower-Left Quadrant)
Datasheet, Volume 1
123
Processor Pin and Signal Information
Figure 8-8. BGA1224 Ballmap (Top View, Lower-Right Quadrant)
124
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
BCLK
BCLK#
D5
C6
Diff Clk
Diff Clk
Diff Clk
Diff Clk
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
Asynch CMOS
CMOS
I
DC_TEST_BH3
DC_TEST_BH63
DC_TEST_BH65
DC_TEST_BJ2
DC_TEST_BJ4
DC_TEST_BJ62
DC_TEST_BJ64
DC_TEST_C2
DC_TEST_C64
DC_TEST_D1
DC_TEST_D65
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
BH3
BH63
BH65
BJ2
BJ4
BJ62
BJ64
C2
N/A
N/A
I
BCLK_ITP
BCLK_ITP#
BPM#[0]
K63
K65
C62
D61
E62
F63
D59
F61
F59
G60
H53
B57
D57
B55
A54
A58
D55
C56
E54
J54
I
N/A
I
N/A
I/O
N/A
BPM#[1]
I/O
N/A
BPM#[2]
I/O
N/A
BPM#[3]
I/O
N/A
BPM#[4]
I/O
C64
D1
N/A
BPM#[5]
I/O
N/A
BPM#[6]
I/O
I/O
O
I
D65
N10
R10
R8
N/A
BPM#[7]
DMI
I
I
CATERR#
CFG[0]
DMI
DMI
I
CFG[1]
CMOS
I
U10
N8
DMI
I
CFG[2]
CMOS
I
DMI
I
CFG[3]
CMOS
I
DMI_RX[1]
T9
DMI
I
CFG[4]
CMOS
I
DMI_RX[2]
R6
DMI
I
CFG[5]
CMOS
I
DMI_RX[3]
U8
DMI
I
CFG[6]
CMOS
I
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
N4
DMI
O
O
O
O
O
O
O
O
I
CFG[7]
CMOS
I
R4
DMI
CFG[8]
CMOS
I
P1
DMI
CFG[9]
G56
F55
K55
F57
E58
H57
H55
D53
K57
H61
A4
CMOS
I
U6
DMI
CFG[10]
CMOS
I
N2
DMI
CFG[11]
CMOS
I
DMI_TX[1]
R2
DMI
CFG[12]
CMOS
I
DMI_TX[2]
P3
DMI
CFG[13]
CMOS
I
DMI_TX[3]
T5
DMI
CFG[14]
CMOS
I
DPLL_REF_CLK
DPLL_REF_CLK#
eDP_AUX
AJ4
AJ2
AE4
AE2
AC2
AE8
AB1
AG2
AF1
AE6
AG6
AG4
AF3
AF7
AG8
AD9
Diff Clk
Diff Clk
eDP
CFG[15]
CMOS
I
I
CFG[16]
CMOS
I
I/O
I/O
I
CFG[17]
CMOS
I
eDP_AUX#
eDP
DBR#
Asynch CMOS
N/A
O
eDP_COMPIO
eDP_HPD#
Analog
Asynch CMOS
Analog
eDP
DC_TEST_A4
DC_TEST_A62
DC_TEST_A64
DC_TEST_B3
DC_TEST_B63
DC_TEST_B65
DC_TEST_BF1
DC_TEST_BF65
DC_TEST_BG2
DC_TEST_BG64
DC_TEST_BH1
I
A62
A64
B3
N/A
eDP_ICOMPO
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
I
N/A
O
O
O
O
O
O
O
O
I
N/A
eDP
B63
B65
BF1
BF65
BG2
BG64
BH1
N/A
eDP
N/A
eDP
N/A
eDP
N/A
eDP_TX[1]
eDP
N/A
eDP_TX[2]
eDP
N/A
eDP_TX[3]
eDP
N/A
FDI_INT
Asynch CMOS
Datasheet, Volume 1
125
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
FDI0_FSYNC
FDI0_LSYNC
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_FSYNC
FDI1_LSYNC
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
PECI
AC8
AB7
V7
CMOS
CMOS
FDI
I
I
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
F19
K19
H17
K15
G14
J16
K13
F11
K11
F9
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
I
I
O
O
O
O
O
O
O
O
I
I
W8
AA8
AC10
W6
W10
Y9
FDI
I
FDI
I
FDI
I
FDI
I
FDI
I
FDI
I
AA10
AA2
AB3
U4
FDI
I
CMOS
CMOS
FDI
H9
I
I
H7
I
O
O
O
O
O
O
O
O
I/O
I
G6
I
W2
V1
FDI
A22
B23
C18
D21
B19
E20
A14
D17
B15
E16
D13
A10
B11
D9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
FDI
Y5
FDI
U2
FDI
W4
V3
FDI
FDI
AA6
F53
G2
FDI
Asynch
Analog
Analog
Analog
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
H1
I
F3
I
F23
H23
H21
H19
J20
G18
K17
F15
H15
H13
H11
J12
E8
I
I
I
I
B7
I
E12
C22
D23
A18
B21
D19
F21
C14
B17
D15
F17
B13
C10
D11
B9
I
I
PEG_TX[1]
I
PEG_TX[2]
I
PEG_TX[3]
I
PEG_TX[4]
I
PEG_TX[5]
I
PEG_TX[6]
I
PEG_TX[7]
G10
J8
I
PEG_TX[8]
I
PEG_TX[9]
F7
I
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
G22
K23
K21
I
PEG_RX[1]
I
PEG_RX[2]
I
126
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
PEG_TX[14]
PEG_TX[15]
PM_SYNC
PRDY#
PREQ#
PROC_DETECT#
PROC_SELECT#
PROCHOT#
RESET#
RSVD
D7
PCIe
O
O
I
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BC14
BB57
BB43
BB25
BB17
BB15
BB13
BA48
BA16
AY45
AY41
AY17
AY15
AY13
AW50
AW46
AW42
AW14
AJ10
AJ6
F13
PCIe
K53
Asynch CMOS
Asynch CMOS
Asynch CMOS
Analog
J62
O
I
H65
B59
O
O
I/O
I
AH9
N/A
H51
Asynch CMOS
Asynch CMOS
K51
G64
RSVD
BJ42
BJ34
BJ22
BH43
BH35
BH25
BH23
BH21
BH19
BG62
BG34
BG26
BG22
BG4
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AH5
AD5
AC6
AC4
AA4
P7
RSVD
RSVD
RSVD
RSVD
BF63
BF43
BF41
BF35
BF25
BF23
BF21
BF19
BF3
RSVD
RSVD
N6
RSVD
M9
RSVD
M5
RSVD
L10
RSVD
L6
RSVD
L4
RSVD
L2
RSVD
BE32
BE16
BE6
K49
K47
K9
RSVD
RSVD
RSVD
BD33
BD29
BD19
BD15
BD13
BC42
BC30
K7
RSVD
K5
RSVD
J50
RSVD
J4
RSVD
J2
RSVD
H49
H47
RSVD
Datasheet, Volume 1
127
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
RSVD
RSVD
H5
G52
G48
G4
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
BG6
AY9
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RSVD
AW8
RSVD
BB7
RSVD
F5
BC8
RSVD
D49
D25
D3
BE4
RSVD
AW12
AV11
BB11
BA12
BE8
RSVD
RSVD
C52
RSVD
C24
RSVD
C4
RSVD
B53
BA10
BD11
BE12
BB49
AY49
BE52
BD51
BD49
BE48
BA52
AY51
BC54
AY53
AW54
AY55
BD53
BB53
BE56
BA56
BD57
BF61
BA60
BB61
BE60
BD63
BB59
BC58
AW58
AY59
AL60
AP61
AW60
RSVD
B25
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_CKE[0]
SA_CKE[1]
SA_CK#[0]
SA_CK#[1]
SA_CK[0]
SA_CK[1]
SA_CS#[0]
SA_CS#[1]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
BA36
BC38
BB19
BE44
BC18
BD17
BA32
AY33
BB31
AW34
BD41
BD45
AL6
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AL8
AP7
AM5
AK7
AL10
AN10
AM9
AR10
AR8
AV7
AY5
AT5
AR6
AW6
AT9
BA6
BA8
128
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
AY57
AN60
AR60
AN8
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SB_CKE[0]
SB_CKE[1]
SB_CK#[0]
SB_CK#[1]
SB_CK[0]
BD25
BJ26
BH33
BH37
BF33
BF37
BE40
BH41
AL4
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
O
O
O
AU6
O
BC6
SB_CK[1]
O
BD9
SB_CS#[0]
SB_CS#[1]
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
O
BC50
BB55
BD59
AU60
AN6
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AK3
AP3
AR2
AU8
AL2
BD5
AK1
BC10
BB51
BD55
BD61
AV61
BD27
BA28
BB27
AW26
BB23
BA24
AY21
BD21
BC22
BB21
AW38
AW22
BA20
BB45
BE20
AW18
BB41
BC46
BE36
BA44
BJ38
BD37
AY29
BH39
AP1
AR4
AV3
AU4
BA4
BB1
SA_MA[1]
O
AV1
SA_MA[2]
O
AU2
SA_MA[3]
O
BA2
SA_MA[4]
O
BB3
SA_MA[5]
O
BC2
SA_MA[6]
O
BF7
SA_MA[7]
O
BF11
BJ10
BC4
SA_MA[8]
O
SA_MA[9]
O
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_ODT[0]
SA_ODT[1]
SA_RAS#
O
BH7
O
BH11
BG10
BJ14
BG14
BF17
BJ18
BF13
BH13
BH17
BG18
BH49
BF47
BH53
O
O
O
O
O
O
O
SA_WE#
O
SB_BS[0]
O
SB_BS[1]
O
SB_BS[2]
O
SB_CAS#
O
Datasheet, Volume 1
129
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
BG50
BF49
BH47
BF53
BJ50
BF55
BH55
BJ58
BH59
BJ54
BG54
BG58
BF59
BA64
BC62
AU62
AW64
BA62
BC64
AU64
AW62
AR64
AT65
AL64
AM65
AR62
AT63
AL62
AM63
AN4
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_ODT[0]
SB_ODT[1]
SB_RAS#
SB_WE#
AY65
AN64
BF31
BH31
BB37
BC34
BF27
BB33
BH27
BG30
BH29
BF29
AY37
BJ30
AW30
BA40
BB29
BE28
BG42
BH45
BG38
BF39
AY25
BE24
BJ46
BG46
BF45
BJ44
J58
DDR3
DDR3
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
SM_DRAMPWROK
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
SM_VREF
TCK
Asynch CMOS
DDR3
O
I/O
I/O
I/O
I
Analog
Analog
Analog
Analog
CMOS
CMOS
CMOS
Asynch CMOS
CMOS
CMOS
Asynch CMOS
PWR
I
TDI
K61
I
AW2
TDO
K59
O
O
I
BH9
THERMTRIP#
TMS
F51
BF15
BF51
BH57
AY63
AN62
AN2
H59
TRST#
H63
I
UNCOREPWRGOOD
VAXG
C60
I
AH65
AH63
AH61
AH58
AH56
AG64
AG62
AG60
VAXG
PWR
VAXG
PWR
AW4
VAXG
PWR
BF9
VAXG
PWR
BH15
BH51
BF57
VAXG
PWR
VAXG
PWR
VAXG
PWR
130
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
AF58
AF56
AE64
AE62
AE60
AD65
AD63
AD61
AD58
AD56
AB65
AB63
AB61
AB58
AB56
AA64
AA62
AA60
Y58
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG_SENSE
VAXG_VAL_SENSE
VCC
N56
N52
N49
M65
M63
M61
M59
M55
M53
M48
L56
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
L52
L48
F49
B49
R46
R42
R40
R36
R34
R29
R27
R23
R21
N45
N43
N39
N37
N33
N30
N26
N24
N20
M46
M42
M40
M36
M34
M29
M27
M23
M21
L44
O
O
VCC
VCC
VCC
Y56
VCC
W64
W62
W60
V65
VCC
VCC
VCC
VCC
V63
VCC
V61
VCC
V58
VCC
V56
VCC
T65
VCC
T63
VCC
T61
VCC
T58
VCC
T56
VCC
R64
VCC
R62
VCC
R60
VCC
R55
VCC
R53
VCC
R48
VCC
N64
VCC
N62
VCC
N60
VCC
N58
VCC
Datasheet, Volume 1
131
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L40
L38
L34
L32
L28
L26
L22
K45
K43
K41
K37
K35
K31
K29
K25
J44
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VCC
VCC
F29
F25
E44
E40
E38
E34
E32
E28
E26
D45
D43
D41
D37
D35
D31
D29
C44
C40
C38
C34
C32
C28
C26
B45
B43
B41
B37
B35
B31
B29
A44
A40
A38
A34
A32
A28
A26
F47
B47
D47
AV23
AT23
AP23
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
Analog
Analog
PWR
PWR
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J40
VCC
J38
VCC
J34
VCC
J32
VCC
J28
VCC
J26
VCC
H45
H43
H41
H37
H35
H31
H29
H25
G44
G40
G38
G34
G32
G28
G26
F45
F43
F41
F37
F35
F31
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_DIE_SENSE
VCC_SENSE
VCC_VAL_SENSE
VCCDQ
VCCDQ
VCCDQ
O
O
O
132
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VCCDQ
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
AL23
AV55
AV53
AV48
AV17
AV15
AV12
AU58
AU56
AU52
AU49
AU20
AU18
AT55
AT53
AT48
AT17
AT15
AT12
AR58
AR56
AR52
AR49
AR20
AR18
AR16
AR14
AP55
AP53
AP48
AN58
AN56
AN52
AN49
AN20
AN18
AN16
AN14
AM11
AL55
AL53
AL48
AL17
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VCCIO
VCCIO
AL15
AL12
AK58
AK56
AJ17
AJ15
AJ12
AH16
AH14
AH11
AF16
AF14
AE17
AE15
AE12
AD11
AC17
AC15
AC12
AB16
AB14
Y16
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
N/A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
Y14
VCCIO
Y11
VCCIO_SEL
VCCIO_SENSE
VCCPLL
VCCPLL
VCCPLL
VCCPQE
VCCPQE
VCCPQE
VCCPQE
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
AJ8
O
O
AW10
AK65
AK63
AK61
AV21
AT21
AP21
AL21
W17
W15
W12
U17
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
U15
U12
T16
T14
T11
N18
Datasheet, Volume 1
133
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VDDQ
N16
N14
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
CMOS
CMOS
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ_SENSE
VIDALERT#
VIDSCLK
VIDSOUT
VSS
AT46
AT42
AT40
AT36
AT34
AT29
AT27
AR45
AR43
AR39
AR37
AR33
AR30
AR26
AR24
AP46
AP42
AP40
AP36
AP34
AP29
AP27
AN45
AN43
AN39
AN37
AN33
AN30
AN26
AN24
AL46
AL42
AL40
AL36
AL34
AL29
AL27
AY19
B51
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
CMOS
CMOS
CMOS
GND
GND
M17
M15
M12
M11
L18
L14
K3
O
O
O
AE10
AG10
BJ36
BJ28
BG40
BG32
BD47
BD43
BD39
BD31
BD23
BB35
AY47
AY43
AY39
AY35
AY31
AY27
AY23
AV46
AV42
AV40
AV36
AV34
AV29
AV27
AU45
AU43
AU39
AU37
AU33
AU30
AU26
AU24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
O
I
VDDQ
VDDQ
D51
O
VDDQ
A50
I/O
VDDQ
BJ56
BJ52
VDDQ
VSS
134
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BJ48
BJ40
BJ32
BJ24
BJ20
BJ16
BJ12
BJ8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC40
BC36
BC32
BC28
BC26
BC24
BC20
BC16
BC12
BB65
BB63
BB47
BB39
BB9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BG60
BG56
BG52
BG48
BG44
BG36
BG28
BG24
BG20
BG16
BG12
BG8
BB5
BA58
BA54
BA50
BA46
BA42
BA38
BA34
BA30
BA26
BA22
BA18
BA14
AY61
AY11
AY7
BF5
BE62
BE58
BE54
BE50
BE46
BE42
BE38
BE34
BE30
BE26
BE22
BE18
BE14
BE10
BD35
BD7
AY3
AY1
AW56
AW52
AW48
AW44
AW40
AW36
AW32
AW28
AW24
AW16
AV65
BD3
BC60
BC56
BC52
BC48
BC44
Datasheet, Volume 1
135
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV63
AV59
AV57
AV50
AV44
AV38
AV31
AV25
AV19
AV9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AP31
AP25
AP19
AP17
AP15
AP12
AP11
AP9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AP5
AN54
AN47
AN41
AN35
AN28
AN22
AM61
AM7
AV5
AU54
AU47
AU41
AU35
AU28
AU22
AU16
AU14
AT61
AT57
AT50
AT44
AT38
AT31
AT25
AT19
AT11
AT7
AM3
AM1
AL57
AL50
AL44
AL38
AL31
AL25
AL19
AK16
AK14
AK11
AK9
AT3
AT1
AK5
AR54
AR47
AR41
AR35
AR28
AR22
AP65
AP63
AP57
AP50
AP44
AP38
AJ64
AJ62
AJ60
AJ57
AH7
AH3
AH1
AG57
AG17
AG15
AG12
AF65
136
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF63
AF61
AF11
AF9
AF5
AE57
AD16
AD14
AD7
AD3
AD1
AC64
AC62
AC60
AC57
AB11
AB9
AB5
AA57
AA17
AA15
AA12
Y65
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R44
R38
R31
R25
R19
R17
R15
R12
P65
P63
P61
P11
P9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P5
N54
N47
N41
N35
N28
N22
M57
M50
M44
M38
M31
M25
M19
M7
Y63
Y61
Y7
Y3
Y1
W57
V16
V14
V11
V9
M3
M1
L64
L62
L60
L58
L54
L50
L46
L42
L36
L30
L24
L20
L16
V5
U64
U62
U60
U57
T7
T3
T1
R57
R50
Datasheet, Volume 1
137
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
Ball Name
Ball #
Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L12
L8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
E52
E48
E46
E42
E36
E30
E24
E22
E18
E14
E10
E6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K39
K33
K27
K1
J64
J60
J56
J52
J48
J46
J42
J36
J30
J24
J22
J18
J14
J10
J6
E4
D63
D39
D33
D27
C58
C54
C50
C46
C42
C36
C30
C20
C16
C12
C8
H39
H33
H27
H3
G62
G58
G54
G50
G46
G42
G36
G30
G24
G20
G16
G12
G8
B39
B33
B27
A56
A52
A42
A36
A30
A24
A20
A16
A12
A8
F39
F33
F27
E60
E56
BJ60
BJ6
138
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-2. BGA1224 Processor Ball
List by Ball Name
Ball Name
Ball #
Buffer Type
Dir
VSS_NCTF
VSS_NCTF
BH61
BH5
BE64
BE2
BD65
BD1
F65
F1
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
E64
E2
VSS_NCTF
VSS_NCTF
B61
B5
VSS_NCTF
VSS_NCTF
A60
A6
VSS_NCTF
VSS_SENSE
VSS_SENSE_VDDQ
VSS_VAL_SENSE
VSSAXG_SENSE
VSSAXG_VAL_SENSE
VSS_SENSE_VCCIO
A46
AW20
C48
E50
A48
AU10
Analog
Analog
Analog
Analog
Analog
Analog
O
O
O
O
O
O
Datasheet, Volume 1
139
Processor Pin and Signal Information
Figure 8-9. BGA1023 Ballmap (Top View, Upper-Left Quadrant)
140
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-10. BGA1023 Ballmap (Top View, Upper-Right Quadrant)
Datasheet, Volume 1
141
Processor Pin and Signal Information
Figure 8-11. BGA1023 Ballmap (Top View, Lower-Left Quadrant)
142
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-12. BGA1023 Ballmap (Top View, Lower-Right Quadrant)
Datasheet, Volume 1
143
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
BCLK
BCLK#
J3
H2
Diff Clk
Diff Clk
Diff Clk
Diff Clk
I
I
I
I
DC_TEST_BG61
DC_TEST_C4
DC_TEST_C59
DC_TEST_C61
DC_TEST_D1
DC_TEST_D3
DC_TEST_D61
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
BG61
C4
N/A
N/A
BCLK_ITP
BCLK_ITP#
BPM#[0]
N59
N58
G58
E55
E59
G55
G59
H60
J59
C59
C61
D1
N/A
N/A
Asynch CMOS I/O
Asynch CMOS I/O
Asynch CMOS I/O
Asynch CMOS I/O
Asynch CMOS I/O
Asynch CMOS I/O
Asynch CMOS I/O
Asynch CMOS I/O
N/A
BPM#[1]
D3
N/A
BPM#[2]
D61
M2
P6
N/A
BPM#[3]
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
DMI
Diff Clk
Diff Clk
eDP
I
I
BPM#[4]
BPM#[5]
P1
I
BPM#[6]
P10
N3
I
BPM#[7]
J61
I
CATERR#
CFG[0]
C49
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
Asynch CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Asynch CMOS
N/A
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
DMI_RX[1]
P7
I
DMI_RX[2]
P3
I
CFG[1]
DMI_RX[3]
P11
K1
I
CFG[2]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
O
O
O
O
O
O
O
O
I
CFG[3]
M8
N4
CFG[4]
CFG[5]
R2
CFG[6]
K3
CFG[7]
DMI_TX[1]
M7
P4
CFG[8]
DMI_TX[2]
CFG[9]
DMI_TX[3]
T3
CFG[10]
DPLL_REF_CLK
DPLL_REF_CLK#
eDP_AUX
AG3
AG1
AF4
AG4
AF3
CFG[11]
I
CFG[12]
I/O
I/O
I
CFG[13]
eDP_AUX#
eDP
CFG[14]
eDP_COMPIO
eDP_HPD#
Analog
CFG[15]
F51
D52
L53
AG11 Asynch CMOS
I
CFG[16]
eDP_ICOMPO
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
AD2
AC3
AC4
AE11
AE7
AC1
AA4
AE10
AE6
U11
AA11
AA10
U7
Analog
eDP
I
CFG[17]
O
O
O
O
O
O
O
O
I
DBR#
K58
A4
eDP
DC_TEST_A4
DC_TEST_A58
DC_TEST_A59
DC_TEST_A61
DC_TEST_BD1
DC_TEST_BD61
DC_TEST_BE1
DC_TEST_BE3
DC_TEST_BE59
DC_TEST_BE61
DC_TEST_BG1
DC_TEST_BG3
DC_TEST_BG4
DC_TEST_BG58
DC_TEST_BG59
eDP
A58
A59
A61
BD1
BD61
BE1
BE3
BE59
BE61
BG1
BG3
BG4
BG58
BG59
N/A
eDP
N/A
eDP
N/A
eDP_TX[1]
eDP
N/A
eDP_TX[2]
eDP
N/A
eDP_TX[3]
eDP
N/A
FDI_INT
Asynch CMOS
CMOS
CMOS
FDI
N/A
FDI0_FSYNC
FDI0_LSYNC
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
I
N/A
I
N/A
O
O
O
O
O
O
N/A
W11
W1
FDI
N/A
FDI
N/A
AA6
U6
FDI
N/A
FDI
N/A
W10
FDI
144
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
FDI0_TX[2]
FDI0_TX[3]
FDI1_FSYNC
FDI1_LSYNC
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
PECI
W3
AA7
AC12
AG8
W6
V4
FDI
FDI
O
O
I
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PM_SYNC
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
PCIe
PCIe
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
CMOS
CMOS
FDI
PCIe
I
PCIe
O
O
O
O
O
O
O
O
I/O
I
PCIe
FDI
PCIe
Y2
FDI
PCIe
AC9
W7
T4
FDI
PCIe
FDI
PCIe
FDI
PCIe
AA3
AC8
A48
G3
FDI
PCIe
FDI
PCIe
Asynch
Analog
Analog
Analog
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
PCIe
H13
M10
F10
D9
PCIe
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PCIe
G1
I
PCIe
G4
I
PCIe
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
I
J4
PCIe
I
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
PCIe
I
PCIe
I
PCIe
I
PCIe
I
PCIe
I
PCIe
I
PCIe
I
PCIe
I
PCIe
I
PCIe
A8
I
PCIe
B6
I
PCIe
H8
I
PCIe
E5
I
PCIe
K7
I
PCIe
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
I
K4
PCIe
PEG_RX[1]
I
C48
N53
N55
C57
F49
C45
D44
BG26
BG22
BG7
BF23
BE26
BE24
BE22
Asynch CMOS
Asynch CMOS
Asynch CMOS
Analog
N/A
PEG_RX[2]
I
PRDY#
O
I
PEG_RX[3]
I
PREQ#
PEG_RX[4]
I
PROC_DETECT#
PROC_SELECT#
PROCHOT#
RESET#
O
O
PEG_RX[5]
I
PEG_RX[6]
I
Asynch CMOS I/O
PEG_RX[7]
I
Asynch CMOS
I
PEG_RX[8]
I
RSVD
PEG_RX[9]
I
RSVD
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
F8
I
RSVD
C8
I
RSVD
C5
I
RSVD
H6
I
RSVD
F6
I
RSVD
Datasheet, Volume 1
145
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
RSVD
RSVD
BE7
BD26
BD25
BD22
BD21
BB21
BB19
BA22
BA19
AY22
AY21
AV19
AU21
AU19
AT49
AT21
AM15
AM14
AH2
SA_DQ[2]
SA_DQ[3]
AP11
AL6
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RSVD
SA_DQ[4]
AJ10
AJ8
RSVD
SA_DQ[5]
RSVD
SA_DQ[6]
AL8
RSVD
SA_DQ[7]
AL7
RSVD
SA_DQ[8]
AR11
AP6
RSVD
SA_DQ[9]
RSVD
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
AU6
RSVD
AV9
RSVD
AR6
RSVD
AP8
RSVD
AT13
AU13
BC7
RSVD
RSVD
RSVD
BB7
RSVD
BA13
BB11
BA7
RSVD
RSVD
RSVD
AG13
W14
U14
BA9
RSVD
BB9
RSVD
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
RSVD
P13
RSVD
N50
RSVD
N42
RSVD
M14
RSVD
M13
RSVD
L47
RSVD
L45
RSVD
L42
RSVD
K48
RSVD
K24
RSVD
H48
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_CKE[0]
SA_CKE[1]
SA_CK#[0]
SA_CK#[1]
SA_CK[0]
SA_CK[1]
SA_CS#[0]
SA_CS#[1]
SA_DQ[0]
SA_DQ[1]
BD37
BF36
BA28
BE39
AY26
BB26
AV36
AU40
AU36
AT40
BB40
BC41
AG6
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
AJ6
146
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
AL11
AR8
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SA_ODT[0]
SA_ODT[1]
SA_RAS#
AY40
BA41
BD39
AT41
BG39
BD42
AT22
AV43
AR22
BF27
AY34
BB36
BA34
BA36
BE41
BE47
AL4
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
O
O
O
SA_WE#
O
SB_BS[0]
O
SB_BS[1]
O
SB_BS[2]
O
SB_CAS#
O
SB_CKE[0]
SB_CKE[1]
SB_CK#[0]
SB_CK#[1]
SB_CK[0]
O
O
O
O
O
SB_CK[1]
O
SB_CS#[0]
SB_CS#[1]
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AV11
AT17
AV45
AY51
AT55
AK55
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
SA_MA[1]
O
BE9
SA_MA[2]
O
BD9
SA_MA[3]
O
BD13
BF12
BF8
SA_MA[4]
O
SA_MA[5]
O
SA_MA[6]
O
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
SA_MA[7]
O
SA_MA[8]
O
SA_MA[9]
O
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
O
O
O
O
O
O
Datasheet, Volume 1
147
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
AL3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_ODT[0]
SB_ODT[1]
SB_RAS#
SB_WE#
SM_DRAMPWROK
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
SM_VREF
TCK
AR59
AK61
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
AT43
BG47
BF40
BD45
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
BE45 Asynch CMOS
AT30
BF44
BE43
BG43
AY43
L56
DDR3
Analog
Analog
Analog
Analog
CMOS
CMOS
CMOS
Asynch CMOS
CMOS
CMOS
Asynch CMOS
PWR
O
I/O
I/O
I/O
I
I
TDI
M60
I
TDO
L59
O
O
I
THERMTRIP#
TMS
D45
L55
TRST#
J58
I
AV3
UNCOREPWRGOOD
VAXG
B46
I
BG11
BD17
BG51
BA59
AT60
AK59
AM2
AE46
AD59
AD58
AD56
AD55
AD53
AD52
AD51
AD50
AD48
AD47
AC61
VAXG
PWR
VAXG
PWR
VAXG
PWR
VAXG
PWR
VAXG
PWR
VAXG
PWR
AV1
VAXG
PWR
BE11
BD18
BE51
BA61
VAXG
PWR
VAXG
PWR
VAXG
PWR
VAXG
PWR
148
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG_SENSE
VAXG_VAL_SENSE
VCC
AB59
AB58
AB56
AB55
AB53
AB52
AB51
AB50
AB47
AA46
Y61
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
Analog
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N34
N30
N26
L40
L36
L33
L28
L25
K42
K39
K37
K35
K34
K32
K29
K27
K26
J42
J40
J38
J37
J35
J34
J32
J29
J28
J26
J25
H40
H38
H37
H35
H34
H32
H29
H28
H26
H25
G42
F42
F38
F37
F34
F32
F28
F26
F25
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Y48
W61
W56
W55
W53
W52
W51
W50
V59
V58
V56
V55
V53
V52
V51
V50
V48
V47
U46
T61
T59
T58
T48
P61
P56
P55
P53
P52
P51
P50
P48
P47
N45
F45
O
O
H45
N38
Datasheet, Volume 1
149
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
VCC
VCC
E38
E37
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
Analog
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO_SEL
VCCIO_SENSE
VCCPLL
VCCPLL
VCCPLL
VCCPQE
VCCPQE
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
AL15
AL14
AK51
AK50
AJ47
AJ43
AJ25
AJ21
AJ17
AJ15
AJ14
AG51
AG50
AG48
AG21
AG20
AG17
AG16
AG15
AF46
AF20
AF18
AF16
AE15
AE14
AD21
AD18
AD16
AC13
AB20
AB17
AA15
AA14
W17
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
N/A
VCC
E34
VCC
E32
VCC
E28
VCC
E26
VCC
D42
D39
D37
D34
D32
D27
C42
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C39
VCC
C37
VCC
C34
VCC
C32
VCC
C27
VCC
C26
VCC
A42
VCC
A39
VCC
A38
VCC
A35
VCC
A34
VCC
A31
VCC
A29
VCC
A26
VCC_DIE_SENSE
VCC_SENSE
VCC_VAL_SENSE
VCCDQ
VCCDQ
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
F48
O
O
O
F43
H43
AN26
AM28
AN48
AN45
AN42
AN20
AM47
AM43
AM21
AM17
AM16
AL48
AL45
AL26
AL22
AL20
AL16
W16
BC22
AN16
BC4
O
O
Analog
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
BC1
BB3
AN22
AM25
W20
V21
V18
V17
V16
150
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VDDQ
U15
R21
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
CMOS
CMOS
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Analog
CMOS
CMOS
CMOS
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BG41
BG37
BG28
BG24
BG21
BG17
BG13
BG9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R18
R16
P20
P17
N22
N20
N16
BE5
L21
BD56
BD52
BD48
BD44
BD40
BD36
BD32
BD27
BD23
BD19
BD16
BD12
BD8
L17
U10
O
O
O
D48
D49
BG33
BB28
BA40
AW26
AV41
AR40
AR36
AR34
AR32
AR30
AR28
AR26
AN38
AN34
AN30
AM40
AM36
AM33
AL42
AL38
AL34
AL30
AJ40
AJ36
AJ33
AJ28
BC43
A44
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
BC57
BC13
BC5
VDDQ
VDDQ
VDDQ
BB53
BA51
BA48
BA32
BA26
BA21
BA17
BA11
BA1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
AY58
AY55
AY49
AY45
AY41
AY36
AY30
AY19
AY14
AY9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ_SENSE
VIDALERT#
VIDSCLK
VIDSOUT
VSS
O
I
B43
O
C44
I/O
BG53
BG49
BG45
AY4
VSS
AW61
AW43
VSS
Datasheet, Volume 1
151
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AW13
AW7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM42
AM38
AM34
AM30
AM26
AM22
AM20
AM13
AM4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AV55
AV48
AV40
AV34
AV22
AV21
AV17
AU51
AU32
AU28
AU11
AU7
AL61
AL47
AL43
AL40
AL36
AL33
AL28
AL25
AL21
AL17
AL13
AL10
AK52
AK1
AU1
AT58
AT52
AT45
AT36
AT19
AT14
AT4
AR61
AR48
AR41
AR21
AR17
AR13
AR7
AJ48
AJ45
AJ42
AJ38
AJ34
AJ30
AJ26
AJ22
AJ20
AJ16
AJ13
AJ7
AP55
AP51
AP10
AP7
AN54
AN50
AN47
AN43
AN40
AN36
AN33
AN28
AN25
AN21
AN1
AH58
AH4
AG61
AG52
AG47
AG18
AG14
AG10
AG7
AM58
AM48
AM45
AF59
AF58
AF56
152
Datasheet, Volume 1
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF55
AF53
AF52
AF51
AF50
AF48
AF47
AF21
AF17
AF1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U8
T56
T55
T53
T52
T51
T50
T47
T1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R46
R20
R17
R4
AE13
AE8
AD61
AD20
AD17
AD4
P59
P58
P21
P18
P16
P14
P9
AC46
AC14
AC10
AC6
AB61
AB48
AB21
AB18
AB16
AA56
AA55
AA53
AA52
AA51
AA50
AA13
AA8
N61
N56
N52
N51
N48
N47
N43
N40
N36
N33
N28
N25
N21
N17
N1
AA1
Y59
Y58
M58
M15
M11
M6
Y47
Y4
W46
W21
W18
W15
W13
W8
M4
L61
L48
L43
L38
L34
L30
L26
V61
V20
U13
Datasheet, Volume 1
153
Processor Pin and Signal Information
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Table 8-3.
BGA1023 Processor Ball
List by Ball Name
Ball Name
Ball # Buffer Type
Dir
Ball Name
Ball # Buffer Type
Dir
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L22
L20
L16
K51
K21
K11
K8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
D4
C40
C35
C29
A53
A49
A45
A40
A37
A33
A28
A25
A21
A17
A13
A9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSS
VSS
VSS
VSS
VSS
J55
J49
J1
VSS
VSS
VSS
H58
H53
H21
H17
H14
H10
H4
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SENSE
VSS_SENSE_VDDQ
VSS_VAL_SENSE
VSSAXG_SENSE
VSSAXG_VAL_SENSE
VSS_SENSE_VCCIO
BG57
BG5
BE58
BE4
BD59
BD3
BC61
E61
E1
G61
G51
G48
G6
F55
F40
F35
F29
F19
F15
F13
E40
E35
E29
E25
E3
D59
C58
C3
A57
A5
G43
BA43
K43
G45
K45
AN17
Analog
Analog
Analog
Analog
Analog
Analog
O
O
O
O
O
O
D58
D54
D50
D46
D43
D40
D35
D29
D26
D22
D18
D14
D10
D6
154
Datasheet, Volume 1
Processor Pin and Signal Information
8.2
Package Mechanical Information
Figure 8-13. Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 1 of 2)
Datasheet, Volume 1
155
Processor Pin and Signal Information
Figure 8-14. Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 2 of 2)
156
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-15. Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 1 of 2)
Datasheet, Volume 1
157
Processor Pin and Signal Information
Figure 8-16. Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 2 of 2)
158
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-17. Processor BGA1023 2C (GT2) Mechanical Package (Sheet 1 of 2)
Datasheet, Volume 1
159
Processor Pin and Signal Information
Figure 8-18. Processor BGA1023 2C (GT2) Mechanical Package (Sheet 2 of 2)
160
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-19. Processor BGA1224 4C (GT2) Mechanical Package (Sheet 1 of 2)
Datasheet, Volume 1
161
Processor Pin and Signal Information
Figure 8-20. Processor BGA1224 4C (GT2) Mechanical Package (Sheet 2 of 2)
162
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-21. Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 1 of 2)
Datasheet, Volume 1
163
Processor Pin and Signal Information
Figure 8-22. Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 2 of 2)
164
Datasheet, Volume 1
Processor Pin and Signal Information
Figure 8-23. Processor BGA1023 2C (GT1) Mechanical Package (Sheet 1 of 2)
Datasheet, Volume 1
165
Processor Pin and Signal Information
Figure 8-24. Processor BGA1023 2C (GT1) Mechanical Package (Sheet 2 of 2)
§ §
166
Datasheet, Volume 1
DDR Data Swizzling
9 DDR Data Swizzling
To achieve better memory performance and better memory timing; Intel design
performed the DDR Data pin swizzling which will allow a better use of the product
across different platforms. Swizzling has no effect on functional operation and is
invisible to the OS/SW.
However, during debug, swizzling needs to be taken into consideration; thus, swizzling
data is presented in this chapter. When placing DIMM logic analyzer, the design
engineer must pay attention to the swizzling table to perform an efficient memory
debug.
Datasheet, Volume 1
167
DDR Data Swizzling
Table 9-1.
DDR Data Swizzling
Table – Channel A
Table 9-1.
DDR Data Swizzling
Table – Channel A
Pin
Number
rPGA
Pin
Number
BGA1023 BGA1224
Pin
Number
Pin
Number
rPGA
Pin
Number
BGA1023 BGA1224
Pin
Number
MC Pin
Name
MC Pin
Name
Pin Name
Pin Name
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
C5
D5
AG6
AJ6
AL6
AL8
DQ01
DQ02
DQ07
DQ06
DQ03
DQ00
DQ05
DQ04
DQ08
DQ10
DQ14
DQ15
DQ09
DQ11
DQ13
DQ12
DQ18
DQ20
DQ22
DQ21
DQ16
DQ17
DQ19
DQ23
DQ27
DQ25
DQ30
DQ31
DQ24
DQ26
DQ28
DQ29
DQ35
DQ32
DQ38
DQ39
DQ33
DQ36
DQ34
DQ37
DQ42
DQ43
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AJ9
AK9
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
AW54
AY55
BD53
BB53
BE56
BA56
BD57
BF61
BA60
BB61
BE60
BD63
BB59
BC58
AW58
AY59
AL60
AP61
AW60
AY57
AN60
AR60
DQ44
DQ47
DQ41
DQ40
DQ46
DQ45
DQ51
DQ50
DQ53
DQ52
DQ49
DQ48
DQ54
DQ55
DQ58
DQ56
DQ60
DQ61
DQ57
DQ59
DQ63
DQ62
D3
AP11
AL6
AP7
AH8
D2
AM5
AK7
AH9
D6
AJ10
AJ8
AL9
C6
AL10
AN10
AM9
AR10
AR8
AL8
C2
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
C3
AL7
F10
F8
AR11
AP6
G10
G9
AU6
AV7
AV9
AY5
F9
AR6
AT5
F7
AP8
AR6
G8
AT13
AU13
BC7
AW6
AT9
G7
K4
BA6
K5
BB7
BA8
K1
BA13
BB11
BA7
BG6
J1
AY9
J5
AW8
BB7
J4
BA9
J2
BB9
BC8
K2
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BE4
M8
N10
N8
AW12
AV11
BB11
BA12
BE8
N7
M10
M9
N9
BA10
BD11
BE12
BB49
AY49
BE52
BD51
BD49
BE48
BA52
AY51
BC54
AY53
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
168
Datasheet, Volume 1
DDR Data Swizzling
Table 9-2. DDR Data Swizzling
Table – Channel B
Table 9-2. DDR Data Swizzling
Table – Channel B
Pin
Number
rPGA
Pin
Number
BGA1023 BGA1224
Pin
Number
MC
Pin
Name
Pin
Number
rPGA
Pin
Number
BGA1023 BGA1224
Pin
Number
MC
Pin
Name
Pin Name
Pin Name
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AT5
AT6
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
BJ58
BH59
BJ54
DQ47
DQ46
DQ40
DQ42
DQ45
DQ41
DQ51
DQ49
DQ52
DQ48
DQ53
DQ50
DQ55
DQ54
DQ56
DQ58
DQ61
DQ62
DQ57
DQ59
DQ63
DQ60
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
C9
A7
AL4
AL1
AL4
AK3
DQ03
DQ02
DQ05
DQ04
DQ00
DQ01
DQ06
DQ07
DQ11
DQ10
DQ12
DQ14
DQ08
DQ09
DQ13
DQ15
DQ19
DQ18
DQ20
DQ22
DQ17
DQ16
DQ21
DQ23
DQ25
DQ30
DQ29
DQ28
DQ24
DQ31
DQ27
DQ26
DQ36
DQ38
DQ34
DQ35
DQ39
DQ37
DQ33
DQ32
DQ44
DQ43
AP6
D10
C8
AN3
AP3
AN8
BG54
BG58
BF59
BA64
BC62
AU62
AW64
BA62
BC64
AU64
AW62
AR64
AT65
AL64
AM65
AR62
AT63
AL62
AM63
AR4
AR2
AR6
A9
AK4
AL2
AR5
A8
AK3
AK1
AR9
D9
AN4
AP1
AJ11
AT8
D8
AR1
AR4
G4
F4
AU4
AV3
AT9
AT2
AU4
AH11
AR8
F1
AV4
BA4
G1
G5
F5
BA4
BB1
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AU3
AV1
AR3
AU2
F2
AY2
BA2
G2
J7
BA3
BB3
BE9
BC2
J8
BD9
BF7
K10
K9
BD13
BF12
BF8
BF11
BJ10
BC4
J9
J10
K8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BH7
BH11
BG10
BJ14
BG14
BF17
BJ18
BF13
BH13
BH17
BG18
BH49
BF47
BH53
BG50
BF49
BH47
BF53
BJ50
BF55
BH55
K7
M5
N4
N2
N1
M4
N5
§ §
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
Datasheet, Volume 1
169
DDR Data Swizzling
170
Datasheet, Volume 1
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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