BP87C51FC12_技术文档

87C51FA/87C51FB/87C51FC/87C51FC-20

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Automotive

Y

FX Core Architecture Device

Quick Pulse Programming Algorithm

Boolean Processor

Y

Extended Automotive Temperature

b

a

Range ( 40 C to 125 C Ambient)

§

Available in 12 MHz, 16 MHz and

32 Programmable I/O Lines

7 Interrupt Sources

Y

20 MHz Versions

Four Level Interrupt Priority

Y

High Performance CHMOS EPROM

Programmable Serial Channel with:

Ð Framing Error Detection

Ð Automatic Address Recognition

Three 16-Bit Timer/Counters

Ð Timer 2 (Up/Down Counter)

Y

Programmable Counter Array with:

Ð High Speed Output,

Ð Compare/Capture,

Y

TTL and CMOS Compatible Logic

Levels

Y

64K External Program Memory Space

64K External Data Memory Space

Ð Pulse Width Modulator,

Ð Watchdog Timer Capabilities

Y

One-to-Three Level Program Lock

System on EPROM

MCS -51 Fully Compatible Instruction

É

Set

8K On-Chip User Programmable

EPROM in 87C51FA

Y

Power Saving Idle and Power Down

Modes

16K On-Chip User Programmable

EPROM in 87C51FB

Y

ONCE (On-Circuit Emulation) Mode

RFI Reduction Mode

32K On-Chip User Programmable

EPROM in 87C51FC

Available in PLCC and PDIP Packages

256 Bytes of On-Chip Data RAM

MEMORY ORGANIZATION

PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the 87C51FA On-Chip EPROM.

Up to 16 Kbytes of the program memory can reside in the 87C51FB on-chip EPROM. Up to 32 Kbytes of the

program memory can reside in the 87C51FC on-chip EPROM. In addition the device can address up to 64K of

program memory external to the chip.

DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of

external data memory.

The Intel 87C51FA/87C51FB/87C51FC is a single-chip control-oriented microcontroller which is fabricated on

Intel’s reliable CHMOS EPROM technology. Being a member of the MCS-51 family, the 87C51FB/87C51FC

uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the

existing MCS-51 family of products. The 87C51FA is an enhanced version of the 87C51. The 87C51FB is an

enhanced version of the 87C51FA. The 87C51FC is an enhanced version of the 87C51FB. With 8 Kbytes of

program memory in the 87C51FA and 16 Kbytes of program memory in the 87C51FB and 32 Kbytes of

program memory in the 87C51FC, it is an even more powerful microcontroller for applications that require

Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as brake and traction

control.

For the remainder of this document, the 87F51FA, 87C51FB and 87C51FC will be referred to as the

87C51FA/FB/FC.

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

©

COPYRIGHT INTEL CORPORATION, 1995

September 1993

Order Number: 270961-003

AUTOMOTIVE 87C51FA/FB/FC/FC-20

270961–1

Figure 1. 87C51FB/FC Block Diagram

With the commercial standard temperature range,

operational characteristics are guaranteed over the

temperature range of 0 C to 70 C ambient. With the

extended temperature range option, operational

characteristics are guaranteed over the temperature

87C51FA/FB/FC PRODUCT OPTIONS

§

Intel’s extended and automotive temperature range

products are designed to meet the needs of those

applications whose operating requirements exceed

commercial standards.

2

AUTOMOTIVE 87C51FA/FB/FC/FC-20

PIN DESCRIPTIONS

b

a

range of 40 C to 85 C ambient. For the automo-

tive temperature range option, operational charac-

§

teristics are guaranteed over the temperature range

a

tended, and commercial temperature versions of the

MCS-51 product families are available with or with-

out burn-in options.

V

: Supply voltage.

CC

b

of 40 C to 125 C ambient. The automotive, ex-

§

: Circuit ground.

SS

: Secondary ground (in PLCC only). Provided to

SS1

reduce ground bounce and improve power supply

by-passing.

As shown in Figure 2 temperature, burn-in, and

package options are identified by a one- or two-letter

prefix to the part number.

NOTE:

This pin is NOT a substitute for V pin (pin 22).

SS

Port 0: Port 0 is an 8-bit, open drain, bidirectional

I/O port. As an output port each pin can sink several

LS TTL inputs. Port 0 pins that have 1’s written to

them float, and in that state can be used as high-im-

pedance inputs.

270961–2

*Example:

AN87C51FA/FB/FC indicates an automotive temperature range version of the 87C51FA/FB/FC in a PLCC package

with 16 Kbyte/32 Kbyte EPROM program memory.

Figure 2. Package Options

Table 1. Temperature Options

Operating

Temperature

Classification

Temperature

Designation

Burn-In

Options

Temperature

C Ambient

§

b

a

Extended

T

L

40 to 85

Standard

Extended

a

40 to 85

b

a

Automotive

A

B

40 to 125

Standard

Extended

a

40 to 125

3

AUTOMOTIVE 87C51FA/FB/FC/FC-20

Port 0 is also the multiplexed low-order address and

data bus during accesses to external Program and

Data Memory. In this application it uses strong inter-

nal pullups when emitting 1’s, and can source and

sink several LS TTL inputs.

PACKAGES

Part

Prefix

Package Type

87C51FA/FB/FC

P

40-Pin Plastic DIP

44-Pin PLCC

N

Port 0 also receives the code bytes during EPROM

programming, and outputs the code bytes during

program verification. External pullup resistors are re-

quired during program verification.

DIP

Port 1: Port 1 is an 8-bit bidirectional I/O port with

internal pullups. The Port 1 output buffers can drive

LS TTL inputs. Port 1 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 1

pins that are externally pulled low will source current

(I , on the data sheet) because of the internal pull-

IL

ups.

In addition, Port 1 serves the functions of the follow-

ing special features of the 87C51FB/FC:

Port Pin

Alternate Function

P1.0

T2 (External Count Input to

Timer/Counter 2)

P1.1

T2EX (Timer/Counter 2 Capture/

Reload Trigger and Direction Control)

ECI (External Count Input to the PCA)

CEX0 (External I/O for Compare/

Capture Module 0)

P1.2

P1.3

270961–3

PAD (PLCC)

P1.4

P1.5

P1.6

P1.7

CEX1 (External I/O for Compare/

Capture Module 1)

CEX2 (External I/O for Compare/

Capture Module 2)

CEX3 (External I/O for Compare/

Capture Module 3)

CEX4 (External I/O for Compare/

Capture Module 4)

Port 1 receives the low-order address bytes during

EPROM programming and verifying.

Port 2: Port 2 is an 8-bit bidirectional I/O port with

internal pullups. The Port 2 output buffers can drive

LS TTL inputs. Port 2 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 2

pins that are externally pulled low will source current

270961–4

*EPROM only

(I , on the data sheet) because of the internal pull-

IL

ups.

**Do not connect reserved pins.

Diagrams are for pin reference only. Package sizes are

not to scale.

Figure 3. Pin Connections (Top View)

4

AUTOMOTIVE 87C51FA/FB/FC/FC-20

Port 2 emits the high-order address byte during

fetches from external Program Memory and during

accesses to external Data Memory that use 16-bit

In normal operation ALE is emitted at a constant

rate of (/6 the oscillator frequency, and may be used

for external timing or clocking purposes. Note, how-

ever, that one ALE pulse is skipped during each ac-

cess to external Data Memory.

@

addresses (MOVX

DPTR). In this application it

uses strong internal pullups when emitting 1’s. Dur-

ing accesses to external Data Memory that use 8-bit

@

addresses (MOVX

of the P2 Special Function Register.

Ri), Port 2 emits the contents

Throughout the remainder of this data sheet, ALE

will refer to the signal coming out of the ALE/PROG

pin, and the pin will be referred to as the ALE/PROG

pin.

Some Port 2 pins receive the high-order address bits

during EPROM programming and program verifica-

tion.

PSEN: Program Store Enable is the read strobe to

external Program Memory.

Port 3: Port 3 is an 8-bit bidirectional I/O port with

internal pullups. The Port 3 output buffers can drive

LS TTL inputs. Port 3 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 3

pins that are externally pulled low will source current

When the 87C51FA/FB/FC is executing code from

external Program Memory, PSEN is activated twice

each machine cycle, except that two PSEN activa-

tions are skipped during each access to external

Data Memory.

(I , on the data sheet) because of the pullups.

IL

EA/V

:

External Access enable. EA must be

strapped to V in order to enable the device to

PP

Port 3 also serves the functions of various special

features of the MCS-51 Family, as listed below:

SS

fetch code from external Program Memory locations

0000H to 0FFFFH. Note, however, that if either of

the Program Lock bits are programmed, EA will be

internally latched on reset.

Port Pin

Alternate Function

RXD (serial input port)

TXD (serial output port)

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

EA should be strapped to V

executions.

for internal program

CC

INT0 (external interrupt 0)

INT1 (external interrupt 1)

This pin also receives the programming supply volt-

age (V ) during EPROM programming.

PP

T0 (Timer 0 external input)

T1 (Timer 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

XTAL1: Input to the inverting oscillator amplifier.

XTAL2: Output from the inverting oscillator amplifier.

RST: Reset input. A high on this pin for two machine

cycles while the oscillator is running resets the de-

vice. The port pins will be driven to their reset condi-

OSCILLATOR CHARACTERISTICS

tion when a minimum V

oscillator is running or not. An internal pulldown re-

sistor permits a power-on reset with only a capacitor

is applied, whether the

IH1

XTAL1 and XTAL2 are the input and output, respec-

tively, of an inverting amplifier which can be config-

ured for use as an on-chip oscillator, as shown in

Figure 4. Either a quartz crystal or ceramic resonator

may be used. More detailed information concerning

the use of the on-chip oscillator is available in Appli-

cation Note AP-155, ‘‘Oscillators for Microcontrol-

lers’’, and in Application Note AP-486, ‘‘Oscillator

Design for Microcontrollers’’.

connected to V

.

CC

ALE/PROG: Address Latch Enable output pulse for

latching the low byte of the address during accesses

to external memory. This pin (ALE/PROG) is also

the program pulse input during EPROM program-

ming for the 87C51FA/FB/FC.

5

AUTOMOTIVE 87C51FA/FB/FC/FC-20

To drive the device from an external clock source,

XTAL1 should be driven, while XTAL2 floats, as

shown in Figure 5. There are no requirements on the

duty cycle of the external clock signal, since the in-

put to the internal clocking circuitry is through a di-

vide-by-two flip-flop, but minimum and maximum

high and low times specified on the data sheet must

be observed.

IDLE MODE

The user’s software can invoke the Idle Mode. When

the microcontroller is in this mode, power consump-

tion is reduced. The Special Function Registers and

the onboard RAM retain their values during Idle, but

the processor stops executing instructions. Idle

Mode will be exited if the chip is reset or if an en-

abled interrupt occurs. The PCA timer/counter can

optionally be left running or paused during Idle

Mode.

An external oscillator may encounter as much as

100 pF load at XTAL1 when it starts up. This is due

to interaction between the amplifier and its feedback

capacitance. Once the external signal meets V and

IL

specifications the capacitance will not exceed

V

IH

20 pF.

POWER DOWN MODE

To save even more power, a Power Down mode can

be invoked by software. In this mode, the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed. The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated.

On the 87C51FA/FB/FC either a hardware reset or

external interrupt can cause an exit from Power

Down. Reset redefines all the SFRs but does not

change the on-chip RAM. An external interrupt al-

lows both the SFRs and the on-chip RAM to retain

their values.

270961–5

e

g

30 pF 10 pF for Crystals

C1, C2

For Ceramic Resonators, contact resonator manufac-

turer.

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before V is

Figure 4. Oscillator Connections

CC

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms).

With an external interrupt. INT0 or INT1 must be en-

abled and configured as level-sensitive. Holding the

pin low restarts the oscillator (the oscillator must be

allowed time to stabilize after start up, before this pin

is released high) but bringing the pin back high com-

pletes the exit. Once the interrupt is serviced, the

next instruction to be executed after RETI will be the

one following the instruction that put the device into

Power Down.

270961–6

Figure 5. External Clock Drive Configuration

6

AUTOMOTIVE 87C51FA/FB/FC/FC-20

While the device is in ONCE Mode, the Port 0 pins

float, and the other port pins and ALE and PSEN are

weakly pulled high. The oscillator circuit remains ac-

tive. While the 87C51FA/FB/FC is in this mode, an

emulator or test CPU can be used to drive the circuit.

Normal operation is restored when a normal reset is

applied.

DESIGN CONSIDERATION

When the Idle mode is terminated by a hardware

reset, the device normally resumes program execu-

tion, from where it left off, up to two machine cycles

before the internal reset algorithm takes control. On-

chip hardware inhibits access to internal RAM in this

event, but access to the port pins is not inhibited. To

eliminate the possibility of an unexpected write when

Idle is terminated by reset, the instruction following

the one that invokes Idle should not be one that

writes to a port pin or to external memory.

RFI REDUCTION MODE

The RFI reduction feature can be used only if exter-

nal program memory is not required since this mode

disables the ALE pin during instruction code fetches.

By writing a logical one to the LSB of the Auxiliary

Register (address 08EH), the ALE is disabled for in-

struction code fetches and the output is weakly held

high. When a logical zero is written, the ALE pin is

enabled allowing it to generate the Address Latch

Enable signal. This bit is cleared by reset. Once dis-

abled, ALE remains disabled until it is reset by soft-

ware or until a hardware reset occurs.

ONCE MODE

The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates

testing and debugging of systems using the

87C51FA/FB/FC without removing it from the cir-

cuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and

PSEN is high;

2. Hold ALE low as RST is deactivated.

Table 2. Status of the External Pins during Idle and Power Down

Program

Memory

Mode

Idle

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Internal

External

Internal

External

1

0

1

0

Data

Float

Data

Float

Data

Address

Data

Idle

Power Down

Data

NOTE:

For more detailed information on the reduced power modes refer to current Embedded Applications Handbook, and Applica-

tion Note AP-252, ‘‘Designing with the 80C51BH.’’

7

AUTOMOTIVE 87C51FA/FB/FC/FC-20

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains information on

products in the sampling and initial production phases

of development. The specifications are subject to

change without notice. Verify with your local Intel

Sales office that you have the latest data sheet be-

fore finalizing a design.

b

a

Ambient Temperature Under Bias 40 C to 125 C

§

b

a

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

§

Voltage on EA/V Pin to V ÀÀÀÀÀÀÀ0V to 13.0V

a

PP

SS

b a

ÀÀ 0.5V to 6.5V

Voltage on Any Other Pin to V

SS

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

I

Per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA

OL

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

(Based on package heat transfer limitations, not

device power consumption)

a

Typical Junction Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ 135 C

§

a

(Based on ambient temperature at 125 C)

§

Typical Thermal Resistance Junction-to-Ambient

(i ):

JA

PDIP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ45 C/W

§

PLCC ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46 C/W

§

ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION

e b

a

40 C to 125 C; V

e

SS

g

5V 20%; V

DC CHARACTERISTICS: (T

0V)

Test Conditions

§

A

CC

Typ

(Note 4)

Symbol

Parameter

Input Low Voltage

Min

Max

Unit

b

V

0.5

0.2 V

0.1

0.3

V

IL

CC

Input Low Voltage EA

0

IL1

IH

a

0.5

Input High Voltage

(Except XTAL1, RST, EA)

0.2 V

0.9

V

CC

a

V

Input High Voltage (XTAL1, RST)

0.7 V

V

CC

0.5

V

IH1

OL

CC

e

Output Low Voltage (Note 5)

(Ports 1, 2 and 3)

0.3

0.45

1.0

I

100 mA (Note 1)

1.6 mA (Note 1)

3.5 mA (Note 1)

200 mA (Note 1)

3.2 mA (Note 1)

7.0 mA (Note 1)

OL

OH

V

Output Low Voltage (Note 5)

(Port 0, ALE, PSEN)

0.3

V

OL1

OH

0.45

1.0

V

b

e b

Output High Voltage

(Ports 1, 2 and 3)

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

0.3

V

10 mA

30 mA

60 mA

200 mA

3.2 mA

7.0 mA

0.7

1.5

0.3

0.7

1.5

V

Output High Voltage

(Port 0 in External Bus Mode,

ALE, PSEN)

V

OH1

V

b

g

e

0.45V

I

Logical 0 Input Current

(Ports 1, 2 and 3)

75

10

mA

V

IL

IN

k

V

I

Input Leakage Current (Port 0)

mA 0.45V

V

IN

LI1

CC

b

e

2V

Logical 1 to 0 Transition Current

(Ports 1, 2 and 3)

750

mA

V

TL

IN

RRST RST Pulldown Resistor

40

225

KX

@

1 MHz, 25 C

CIO

Pin Capacitance

10

pF

§

I

Power Supply Current:

(Note 3)

CC

Running at 16/20 MHz (Figure 6)

Idle Mode at 16/20 MHz (Figure 6)

Power Down Mode

26/28

5

15

35/40

12/14

100

mA

8

AUTOMOTIVE 87C51FA/FB/FC/FC-20

NOTES:

1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and

OL

Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed

0.8V. It may be desirable to qualify ALE or other signals with Schmitt triggers or CMOS-level input logic.

2. Capacitive loading on Ports 0 and 2 cause the V

address lines are stabilizing.

3. See Figures 6–9 for test conditions. Minimum V

on ALE and PSEN to drop below the 0.9 V specification when the

CC

OH

for Power Down is 2V.

CC

4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and

5V.

5. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

OL

Maximum I per 8-bit portÐ

10mA

OL

Port 0:

Ports 1, 2 and 3:

Maximum total I for all output pins:

26 mA

15 mA

71 mA

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater

OL OL

than the listed test conditions.

All other pins disconnected

e

5 ns

270961–8

e

TCLCH

TCHCL

270961–7

I

Max at other frequencies is given by:

CC

Active Mode

Figure 7. I Test Condition, Active Mode

CC

e

c

a

Osc Freq) 15

I

Max

(1.25

CC

Idle Mode

Max

e

c

a

4

I

(0.5

Osc Freq)

is in mA.

CC

Where Osc Freq is in MHz, I

CC

Figure 6. I vs Frequency

CC

All other pins disconnected

e

270961–9

All other pins disconnected

270961–10

e

TCLCH

TCHCL

5 ns

Figure 9. I Test Condition, Power Down Mode.

CC

Figure 8. I Test Condition Idle Mode

CC

e

V

2.0V to 5.5V.

CC

270961–11

e

5 ns.

Figure 10. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH

CC

TCHCL

9

AUTOMOTIVE 87C51FA/FB/FC/FC-20

L: Logic level LOW, or ALE

P: PSEN

EXPLANATION OF THE AC SYMBOLS

Q: Output Data

R: RD signal

T: Time

Each timing symbol has 5 characters. The first char-

acter is always a ‘T’ (stands for time). The other

characters, depending on their positions, stand for

the name of a signal or the logical status of that

signal. The following is a list of all the characters and

what they stand for.

V: Valid

W: WR signal

X: No longer a valid logic level

Z: Float

A: Address

C: Clock

For example,

D: Input Data

H: Logic level HIGH

I: Instruction (program memory contents)

e

T

Time from Address Valid to ALE Low

Time from ALE Low to PSEN Low

AVLL

LLPL

e b

a

e

100 pF, Load Capacitance for All Other Outputs

e

SS

g

5V 20%, V

AC CHARACTERISTICS (T

for Port 0, ALE/PROG and PSEN

40 C to 125 C, V

0V, Load Capacitance

e

80 pF)

§

A

e

CC

ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION

EXTERNAL PROGRAM MEMORY CHARACTERISTICS

12 MHz

Variable Oscillator

Oscillator

Symbol

Parameter

Units

87C51FA/FB/FC 87C51FC-20

/

Min

Max

Min

Max

1/T

Oscillator Frequency

3.5

16/20

MHz

ns

CLCL

b

40

T

ALE Pulse Width

127

43

2T

LHLL

CLCL

b

Address Valid to ALE Low

Address Hold After ALE Low

T

40

ns

AVLL

LLAX

LLIV

CLCL

b

53

30

ns

b

ALE Low to Valid

Instruction In

234

145

4T

100/

75*

ns

CLCL

b

T

ALE Low to PSEN Low

PSEN Pulse Width

53

T

30

ns

LLPL

PLPH

PLIV

CLCL

b

45

205

3T

CLCL

b

PSEN Low to Valid

Instruction In

3T

105/

90*

CLCL

T

Input Inst. Hold After

PSEN Trans

0

ns

PXIX

PXIZ

AVIV

PLAZ

b

Input Inst. Float After

PSEN Trans

59

312

10

T

25/

20*

CLCL

b

Address Valid to Valid

Instruction In

5T

105

CLCL

PSEN Low to Address

Float

10

b

T

RD Pulse Width

WR Pulse Width

400

6T

100

ns

RLRH

CLCL

WLWH

CLCL

10

AUTOMOTIVE 87C51FA/FB/FC/FC-20

e b

a

e

0V, Load Capaci-

SS

g

AC CHARACTERISTICS (T

40 C to 125 C, V

§

5V

20%, V

§

A

CC

e

tance for Port 0, ALE/PROG and PSEN

(Continued)

100 pF, Load Capacitance for All Other Outputs

80 pF)

ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION

EXTERNAL PROGRAM MEMORY CHARACTERISTICS (Continued)

12 MHz

Variable Oscillator

Oscillator

Symbol

Parameter

Units

87C51FA/FB/FC 87C51FC-20

/

Min

Max

Min

Max

b

T

RD Low to Valid Data In

252

5T

165/

95*

ns

RLDV

CLCL

T

Data Hold After RD High

Data Float After RD High

ALE Low to Valid Data In

0

ns

RHDX

RHDZ

LLDV

b

107

517

2T

60

CLCL

b

8T

150/

90*

CLCL

b

CLCL

b

T

Address Valid to Valid Data In

585

300

9T

165/

90*

ns

AVDV

CLCL

b

a

50

T

ALE Low to RD or WR Low

Address Valid to WR Low

200

203

3T

50

3T

CLCL

ns

LLWL

AVWL

CLCL

b

4T

CLCL

4T

130/

90*

b

CLCL

b

T

Data Valid before WR Low

Data Hold after WR High

Data Valid to WR High

33

T

50/

35*

ns

QVWX

WHQX

QVWH

CLCL

b

T

50/

40*

CLCL

b

433

7T

150/

70*

CLCL

T

RD Low to Address Float

0

ns

RLAZ

b

a

40

RD or WR High to ALE High

43

123

T

40

T

WHLH

CLCL

NOTE:

*Timings specified for the 87C51FC-20 are valid at 20 MHz only. For timing information below 20 MHz, use the 87C51FA/

FB/FC timings.

11

AUTOMOTIVE 87C51FA/FB/FC/FC-20

EXTERNAL PROGRAM MEMORY READ CYCLE

270961–12

EXTERNAL DATA MEMORY READ CYCLE

270961–13

EXTERNAL DATA MEMORY WRITE CYCLE

270961–14

12

AUTOMOTIVE 87C51FA/FB/FC/FC-20

SERIAL PORT TIMINGÐSHIFT REGISTER MODE

e b

a

40 C to 125 C; V

e

5V 20%; V

SS

e

80 pF

g

Test Conditions: T

0V; Load Capacitance

Variable Oscillator

Min Max

12T

§

A

CC

12 MHz Oscillator

Symbol

Parameter

Units

Min

1

Max

T

Serial Port Clock Cycle Time

ms

XLXL

CLCL

b

CLCL

Output Data Setup to Clock

Rising Edge

700

10T

133

ns

QVXH

b

T

Output Data Hold after

Clock Rising Edge

50

0

2T

117

ns

XHQX

XHDX

XHDV

CLCL

0

Input Data Hold After Clock

Rising Edge

b

133

Clock Rising Edge to Input

Data Valid

700

10T

CLCL

SHIFT REGISTER MODE TIMING WAVEFORMS

270961–15

EXTERNAL CLOCK DRIVE

Symbol

1/T

Parameter

Min

Max

Units

Oscillator Frequency

87C51FA/FB/FC

3.5

16/20

MHz

CLCL

T

High Time

Low Time

Rise Time

Fall Time

20

ns

CHCX

CLCX

CLCH

CHCL

20

EXTERNAL CLOCK DRIVE WAVEFORMS

270961–16

13

AUTOMOTIVE 87C51FA/FB/FC/FC-20

AC TESTING INPUT, OUTPUT WAVEFORMS

FLOAT WAVEFORMS

270961–18

port pin is no longer floating when

100 mV change from load voltage occurs, and begins to float

when a 100 mV change from the loaded V /V level occurs.

270961–17

For timing purposes

a

b

and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V

AC Inputs during testing are driven at V

0.5V for a Logic ‘‘1’’

CC

IH

OH OL

min for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’.

IL

t

g

20 mA.

I /I

OL OH

Table 3. EPROM Programming Modes

ALE/

EA/

Mode

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

PROG

V

PP

Program Code Data

Verify Code Data

H

L

ß

H

12.75V

H

L

H

L

H

L

H

L

H

Program Encryption

Array Address 0–3FH

ß

12.75V

H

Program Lock

Bits

Bit 1

Bit 2

Bit 3

H

L

ß

H

12.75V

H

L

H

L

H

L

H

L

H

L

H

L

Read Signature Byte

L

DEFINITION OF TERMS

(EPROM PROGRAMMING)

PROGRAMMING THE EPROM

The part must be running with a 4 MHz to 6 MHz

oscillator. The address of an EPROM location to be

programmed is applied to address lines while the

code byte to be programmed in that location is ap-

plied to data lines. Control and program signals must

be held at the levels indicated in Table 3. Normally

ADDRESS LINES: P1.0–P1.7, P2.0–P2.5, P3.4–

P3.5 respectively for A0–A13.

DATA LINES: P0.0–P0.7 for D0–D7.

EA/V is held at logic high until just before ALE/

PP

PROG is to be pulsed. The EA/V is raised to V

CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,

P3.6, P3.7

,

PP

is re-

PP

ALE/PROG is pulsed low and then EA/V

PP

turned to a high (also refer to timing diagrams).

PROGRAM SIGNALS: ALE/PROG, EA/V

PP

NOTE:

maximum for any amount of

Exceeding the V

PP

time could damage the device permanently. The

source must be well regulated and free of

glitches.

V

PP

14

AUTOMOTIVE 87C51FA/FB/FC/FC-20

270961–19

*See Table 2 for proper input on these pins

Figure 11. Programming the EPROM

Repeat 1 through 5 changing the address and data

for the entire array or until the end of the object file is

reached.

PROGRAMMING ALGORITHM

Refer to Table 3 and Figures 11 and 12 for address,

data, and control signals set up. To program the

87C51FA/FB/FC the following sequence must be

exercised.

PROGRAM VERIFY

1. Input the valid address on the address lines.

2. Input the appropriate data byte on the data lines.

Program verify may be done after each byte or block

of bytes is programmed. In either case a complete

verify of the programmed array will ensure reliable

programming of the 87C51FA/FB/FC.

3. Activate the correct combination of control sig-

nals.

g

to 12.75V 0.25V.

4. Raise EA/V from V

PP

CC

The lock bits cannot be directly verified. Verification

of the lock bits is done by observing that their fea-

tures are enabled. Refer to the EPROM Program

Lock section in this data sheet.

5. Pulse ALE/PROG 5 times for the EPROM array,

and 25 times for the encryption table and the lock

bits.

270961–20

5 Pulses

Figure 12. Programming Signal’s Waveforms

15

AUTOMOTIVE 87C51FA/FB/FC/FC-20

EPROM Program Lock

Encryption Array

The 87C51FA/FB/FC program lock system, when

programmed, protects the onboard program against

software piracy.

Within the EPROM array are 64 bytes of Encryption

Array that are initially unprogrammed (all 1’s). Every

time that a byte is addressed during a verify, 6 ad-

dress lines are used to select a byte of the Encryp-

tion Array. This byte is then exclusive-NOR’ed

(XNOR) with the code byte, creating an Encryption

Verify byte. The algorithm, with the array in the un-

programmed state (all 1’s), will return the code in it’s

original, unmodified form. For programming the En-

cryption Array, refer to Table 3 (EPROM Program-

ming Mode).

The 87C51FA/FB/FC has a 3-level program lock

system and a 64-byte encryption array. Since this is

an EPROM device, all locations are user program-

mable. See Table 4.

Program Lock Bits

The 87C51FA/FB/FC has 3 programmable lock bits

that when programmed according to Table 4 will

provide different levels of protection for the on-chip

code and data.

Reading the Signature Bytes

The 87C51FA/FB/FC has 3 signature bytes in loca-

tions 30H, 31H and 60H. To read these bytes follow

the procedure for EPROM verify, but activate the

control lines provided in Table 3 for Read Signature

Byte.

Erasing the EPROM also erases the encryption ar-

ray and the program lock bits, returning the part to

full functionality.

e

Location: 30H

89H

31H

60H

58H

FBH (for an FB part)

FCH (for an FC part)

Table 4. Program Lock Bits and the Features

Protection Type

Program Lock Bits

LB1

LB2

LB3

1

2

U

No Program Lock features enabled. (Code verify will still be encrypted by the

Encryption Array if programmed.)

P

U

MOVC instructions executed from external program memory are disabled

from fetching code bytes from internal memory, EA is sampled and latched on

Reset, and further programming of the EPROM is disabled.

3

4

P

U

P

Same as 2, also verify is disabled.

Same as 3, also external execution is disabled.

Any other combination of the lock bits is not defined.

16

AUTOMOTIVE 87C51FA/FB/FC/FC-20

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

e

0V)

SS

g

5V 20%; V

(T

A

21 C to 27 C; V

§

CC

ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION

Symbol

Parameter

Min

Max

13.0

75

Units

V

Programming Supply Voltage

Programming Supply Current

Oscillator Frequency

12.5

PP

I

mA

PP

1/T

4

6

MHz

CLCL

AVGL

GHAX

T

Address Setup to PROG Low

Address Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

48T

CLCL

T

48T

T

DVGL

GHDX

T

(Enable) High to V

PP

EHSH

SHGL

GHSL

GLGH

V

PP

V

PP

Setup to PROG Low

10

ms

Hold after PROG

10

90

T

PROG Width

110

T

Address to Data Valid

ENABLE Low to Data Valid

Data Float after ENABLE

PROG High to PROG Low

48T

AVQV

CLCL

T

48T

ELQV

EHQZ

GHGL

T

0

10

ms

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

270961–21

17

AUTOMOTIVE 87C51FA/FB/FC/FC-20

DATA SHEET REVISION HISTORY

The following are key differences between this data sheet and the -002 revision of the data sheet:

1. The data sheet has been revised from the 87C51FB/87C51FC to the 87C51FA/87C51FB/87C51FC/

87C51FC-20 and includes the 20 MHz 87C51FC.

2. RST pin in Figure 3 has been changed to RESET pin.

3. Reference to Application Note AP-486 was added on page 5.

4. The I

specification has been corrected in the D.C. Characteristics section.

CC

5. The 20 MHz I

max values have been added.

CC

6. 20 MHz 87C51FC timings information were added to the External Program Memory Characteristics table.

DATA SHEET REVISION HISTORY

The following are key differences between this data sheet and the -001 version of the data sheet:

1. ‘‘NC’’ pin labels changed to ‘‘Reserved’’ in Figure 3.

2. Capacitor value for ceramic resonators deleted in Figure 4.

3. Replaced A0–A15 with P1.0–P1.7, P2.0–P2.5 (EPROM programming and verification waveforms).

4. Replaced D0–D7 with P0 (EPROM programming and verification waveforms).

5. Combined the 87C51FB and 87C51FC data sheets.

The following are the key differences between the previous 87C51FB data sheet versions and this new data

sheet (rev-001):

1. The data sheet has been revised from a 83C51FB/87C51FB to an 87C51FB data sheet only.

e

g

5V 20% instead of V

CC

2. The data sheet has been revised to specify AC and DC parameters to V

g

5V 10%.

CC

3. The 87C51FB is now offered in a 3.5 MHz–20 MHz version.

4. The RST description has been modified to clarify the reset operation when the oscillator is not running.

5. Figure 4 (Oscillator Connections) has been changed for Ceramic Resonators.

6. A description of RFI Reduction Mode has been added.

7. V , I , I and I

OH1 IL TL

DC Characteristics have been revised.

CC

8. Note 1 of the DC Characteristics has been clarified.

9. The External Clock Drive diagram has been modified to include 16 MHz and 20 MHz device types.

10. The Float Waveforms diagram has been revised for greater clarity.

11. Table 4, EPROM Programming Modes, has been modified, included logic levels for P3.3 and three pro-

gram lock bits.

12. The Encryption Array section now states that six address lines are used to select a byte from the Encryp-

tion Array instead of five.

13. The I specification in the EPROM Programming and Verification Characteristics has been increased to

PP

75 mA.

18


型号：	BP87C51FC12
厂家：	INTEL
描述：	Microcontroller, 8-Bit, OTPROM, 12MHz, CMOS, PDIP40, PLASTIC, DIP-40 可编程只读存储器微控制器光电二极管
文件：	总18页 (文件大小：254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BP87C51FC12 [INTEL]

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