BX80525U800256E [INTEL]
Microprocessor, 32-Bit, 800MHz, CMOS,;
| 型号： | BX80525U800256E |
| 厂家： | 
INTEL |
| 描述： | Microprocessor, 32-Bit, 800MHz, CMOS, |
| 文件： | 总102页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Pentium® III Processor for the SC242 at
450 MHz to 800 MHz
Datasheet
Product Features
■ Available in 800EB, 733, 667, 600B,
600EB, 533B, and 533EB MHz speeds
support a 133 MHz system bus (‘B’ denotes
support for a 133 MHz system bus; ‘E’
denotes support for Advanced Transfer
Cache and Advanced System Buffering)
■ Available in 800, 750, 700, 650, 600E, 600,
550E, 550, 500, and 450 MHz speeds
support a 100 MHz system bus (‘E’ denotes
support for Advanced Transfer Cache and
Advanced System Buffering)
■ Available in versions that incorporate
256 KB Advanced Transfer Cache (on-die,
full speed Level 2 (L2) cache with Error
Correcting Code (ECC)) or versions that
incorporate a discrete, half-speed, 512 KB
in-package L2 cache with ECC
■ Binary compatible with applications
running on previous members of the Intel
microprocessor line
■ Dynamic execution micro architecture
■ Power Management capabilities
—System Management mode
—Multiple low-power states
■ Intel Processor Serial Number
■ Optimized for 32-bit applications running
on advanced 32-bit operating systems
■ Single Edge Contact Cartridge (S.E.C.C.)
and S.E.C.C.2 packaging technology; the
S.E.C. cartridges deliver high performance
with improved handling protection and
socketability
■ Integrated high performance 16 KB
instruction and 16 KB data, nonblocking,
level one cache
■ Dual Independent Bus (DIB) architecture
increases bandwidth and performance over
single-bus processors
■ Internet Streaming SIMD Extensions for
enhanced video, sound and 3D
performance
■ Enables systems which are scaleable up to
two processors
■ Error-correcting code for System Bus data
The Pentium® III processor is designed for high-performance desktops and for workstations and
servers. It is binary compatible with previous Intel Architecture processors. The Pentium III
processor provides great performance for applications running on advanced operating systems
such as Windows* 98, Windows NT and UNIX*. This is achieved by integrating the best
attributes of Intel processors—the dynamic execution, Dual Independent Bus architecture plus
Intel MMX™ technology and Internet Streaming SIMD Extensions—bringing a new level of
performance for systems buyers. The Pentium III processor is scaleable to two processors in a
multiprocessor system and extends the power of the Pentium II processor with performance
headroom for business media, communication and internet capabilities. Systems based on
Pentium III processors also include the latest features to simplify system management and lower
the cost of ownership for large and small business environments. The Pentium III processor
offers great performance for today’s and tomorrow’s applications.
December 1999
Order Number: 244452-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1999
*Third-party brands and names are the property of their respective owners.
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Contents
1.0
Introduction.........................................................................................................................9
1.1
Terminology.........................................................................................................10
1.1.1 S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology ..................10
1.1.2 Processor Naming Convention...............................................................11
Related Documents.............................................................................................11
1.2
2.0
Electrical Specifications....................................................................................................13
2.1
2.2
Processor System Bus and VREF .......................................................................................... 13
Clock Control and Low Power States..................................................................14
2.2.1 Normal State—State 1 ...........................................................................15
2.2.2 AutoHALT Powerdown State—State 2...................................................15
2.2.3 Stop-Grant State—State 3 .....................................................................15
2.2.4 HALT/Grant Snoop State—State 4 ........................................................16
2.2.5 Sleep State—State 5..............................................................................16
2.2.6 Deep Sleep State—State 6 ....................................................................16
2.2.7 Clock Control..........................................................................................17
Power and Ground Pins ......................................................................................17
Decoupling Guidelines ........................................................................................17
2.4.1 Processor VCCCORE Decoupling............................................................17
2.4.2 Processor System Bus AGTL+ Decoupling............................................18
Processor System Bus Clock and Processor Clocking.......................................18
Voltage Identification...........................................................................................18
Processor System Bus Unused Pins...................................................................20
Processor System Bus Signal Groups ................................................................20
2.8.1 Asynchronous vs. Synchronous for System Bus Signals.......................21
2.8.2 System Bus Frequency Select Signal (BSEL0)......................................21
Test Access Port (TAP) Connection....................................................................23
Maximum Ratings................................................................................................24
Processor DC Specifications...............................................................................25
AGTL+ System Bus Specifications .....................................................................29
System Bus AC Specifications............................................................................30
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
3.0
Signal Quality Specifications............................................................................................38
3.1
BCLK, PICCLK, and PWRGOOD Signal Quality Specifications and
Measurement Guidelines ....................................................................................38
3.2
AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and
Measurement Guidelines ....................................................................................39
3.2.1 Overshoot/Undershoot Magnitude .........................................................39
3.2.2 Overshoot/Undershoot Pulse Duration...................................................40
3.2.3 Overshoot/Undershoot Activity Factor....................................................40
3.2.4 Reading Overshoot/Undershoot Specification Tables............................41
3.2.5 Determining if a System meets the Overshoot/Undershoot
Specifications .........................................................................................42
3.3
AGTL+ and Non-AGTL+ Ringback Specifications and Measurement
Guidelines ...........................................................................................................44
3.3.1 Settling Limit Guideline...........................................................................46
Datasheet
3
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
4.0
5.0
Thermal Specifications and Design Considerations.........................................................47
4.1
Thermal Specifications........................................................................................48
4.1.1 Thermal Diode........................................................................................50
S.E.C.C. and S.E.C.C.2 Mechanical Specifications.........................................................51
5.1
5.2
5.3
5.4
5.5
5.6
S.E.C.C. Mechanical Specifications....................................................................51
S.E.C.C.2 Mechanical Specification....................................................................58
S.E.C.C.2 Structural Mechanical Specification ...................................................64
Processor Package Materials Information ..........................................................66
Intel® Pentium® III Processor Signal Listing........................................................66
Intel® Pentium® III Processor Core Pad to Substrate Via Assignments..............75
5.6.1 Processor Core Pad Via Assignments (CPUID 067xh)..........................75
5.6.2 Processor Core Signal Assignments (CPUID 067xh) ............................75
5.6.3 Processor Core Pad Via Assignments (CPUID 068xh)..........................88
6.0
Boxed Processor Specifications.......................................................................................89
6.1
6.2
Introduction .........................................................................................................89
Fan Heatsink Mechanical Specifications.............................................................89
6.2.1 Boxed Processor Fan Heatsink Dimensions..........................................89
6.2.2 Boxed Processor Fan Heatsink Weight..................................................91
6.2.3 Boxed Processor Retention Mechanism................................................91
Fan Heatsink Electrical Requirements................................................................92
6.3.1 Fan Heatsink Power Supply...................................................................92
Fan Heatsink Thermal Specifications..................................................................93
6.4.1 Boxed Processor Cooling Requirements ...............................................93
6.3
6.4
7.0
Intel® Pentium® III Processor Signal Description .............................................................94
7.1
7.2
Alphabetical Signals Reference ..........................................................................94
Signal Summaries.............................................................................................101
4
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figures
1
2
3
4
Second Level (L2) Cache Implementation ...........................................................7
AGTL+ Bus Topology..........................................................................................12
Stop Clock State Machine...................................................................................12
BSEL[1:0] Example for a 100 MHz System Design
(100 MHz Processor Installed)............................................................................20
5
6
BSEL[1:0] Example for a 100/133 MHz Capable System
(100 MHz Processor Installed)............................................................................21
BSEL[1:0] Example for a 100/133 MHz Capable System
(133 MHz Processor Installed)............................................................................21
BCLK, PICCLK, and TCK Generic Clock Waveform...........................................33
System Bus Valid Delay Timings ........................................................................33
System Bus Setup and Hold Timings..................................................................34
System Bus Reset and Configuration Timings....................................................34
Power-On Reset and Configuration Timings.......................................................34
Test Timings (TAP Connection) ..........................................................................35
Test Reset Timings .............................................................................................35
BCLK and PICCLK Generic Clock Waveform.....................................................36
Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot
7
8
9
10
11
12
13
14
15
Waveform............................................................................................................42
Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance .................44
Signal Overshoot/Undershoot, Settling Limit, and Ringback 1............................44
S.E.C.Cartridge — 3-Dimensional View..............................................................45
S.E.C.Cartridge 2 — Substrate View ..................................................................46
Processor Functional Die Layout (CPUID 068xh)...............................................47
S.E.C.C. Packaged Processor — Multiple Views................................................49
S.E.C.C. Packaged Processor — Extended Thermal Plate Side Dimensions....50
S.E.C.C. Packaged Processor — Bottom View Dimensions...............................50
S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,
and Cover Lug Dimensions.................................................................................51
S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,
and Cover Detail Dimensions (Reference Dimensions Only)..............................52
S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions ...............................................................................................53
S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions, Continued.............................................................................54
16
17
18
19
20
21
22
23
24
25
26
27
28
29
S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions..........................................................................................................54
S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions, Detail A...........................................................................................55
Intel® Pentium® III Processor Markings (S.E.C.C. Packaged Processor) ...........55
S.E.C.C.2 Packaged Processor — Multiple Views..............................................56
S.E.C.C.2 Packaged Processor Assembly — Primary View...............................57
S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions ......57
S.E.C.C.2 Packaged Processor Assembly — Heat Sink Attach Boss Section ...58
S.E.C.C.2 Packaged Processor Assembly — Side View....................................58
Detail View of Cover in the Vicinity of the Substrate Attach Features.................58
S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
30
31
32
33
34
35
36
37
Dimensions..........................................................................................................59
38
S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
Dimensions (Detail A)..........................................................................................59
Datasheet
5
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
39
40
41
42
43
44
45
46
47
48
49
S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) — Keep In Zones ...60
S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) — Keep In Zones ...60
S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) — Keep-Out Zone..61
S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) — Keep-Out Zone..61
Intel® Pentium® III Processor Markings (S.E.C.C.2 Package) ............................62
Substrate Deflection Away From Heat Sink........................................................62
Substrate Deflection Toward the Heatsink..........................................................63
S.E.C.C.2 Packaged Processor Specifications...................................................63
Processor Core Pad Via Assignments................................................................73
Intel® Pentium® III Processor S.E.C.C. 2 Via Map..............................................84
Boxed Intel® Pentium® III Processor in the S.E.C.C.2 Packaging
(Fan Power Cable Not Shown) ...........................................................................85
50
51
Side View Space Requirements for the Boxed Processor with
S.E.C.C.2 Packaging ..........................................................................................86
Front View Space Requirements for the Boxed Processor with
S.E.C.C.2 Packaging ..........................................................................................86
Top View Air Space Requirements for the Boxed Processor..............................87
Boxed Processor Fan Heatsink Power Cable Connector Description ................88
Recommended Baseboard Power Header Placement Relative to
52
53
54
Fan Power Connector and Intel® Pentium® III Processor ...................................89
Tables
1
2
3
4
5
6
7
8
Processor Identification.........................................................................................9
Related Documents.............................................................................................10
Voltage Identification Definition ..........................................................................17
System Bus Signal Groups .................................................................................19
Frequency Select Truth Table for BSEL[1:0] ......................................................20
Absolute Maximum Ratings (CPUID 067xh).......................................................22
Absolute Maximum Ratings (CPUID 068xh).......................................................23
Voltage and Current Specifications.....................................................................24
AGTL+ Signal Groups DC Specifications ...........................................................26
Non-AGTL+ Signal Group DC Specifications .....................................................27
AGTL+ Bus Specifications .................................................................................28
System Bus AC Specifications (Clock) at Processor Core Pins ........................29
Valid System Bus, Core Frequency, and Cache Bus Frequencies ....................30
System Bus AC Specifications (AGTL+ Signal Group) at the
9
10
11
12
13
14
Processor Core Pins ..........................................................................................30
15
System Bus AC Specifications (CMOS Signal Group) at the
Processor Core Pins ..........................................................................................31
System Bus AC Specifications (Reset Conditions) ............................................31
System Bus AC Specifications (APIC Clock and APIC I/O) at the
16
17
Processor Core Pins ..........................................................................................31
18
19
System Bus AC Specifications (TAP Connection) at the Processor
Core Pins ...........................................................................................................32
BCLK, PICCLK, and PWRGOOD Signal Quality Specifications at the
Processor Core ..................................................................................................36
100 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance ....................40
133 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance ....................41
33 MHz Non-AGTL+ Signal Group Overshoot/Undershoot Tolerance ..............41
Signal Ringback Specifications for Signal Simulation ........................................43
AGTL+ and Non-AGTL+ Signal Groups Ringback Tolerance Specifications .....43
20
21
22
23
24
6
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Thermal Specifications for S.E.C.C. Packaged Processors ...............................46
Thermal Specifications for S.E.C.C.2 Packaged Processors..............................47
Thermal Diode Parameters1 ...............................................................................48
Thermal Diode Interface......................................................................................48
Description Table for Processor Markings (S.E.C.C. Packaged Processor).......56
Description Table for Processor Markings (S.E.C.C.2 Packaged Processor).....62
S.E.C.C.2 Pressure Specifications......................................................................63
S.E.C.C. Materials...............................................................................................64
S.E.C.C.2 Materials.............................................................................................64
Signal Listing in Order by Pin Number ................................................................65
Signal Listing in Order by Signal Name...............................................................69
Via Listing in Order by Signal Name ...................................................................74
Via Listing in Order by Via Location ....................................................................79
Boxed Processor Fan Heatsink Spatial Dimensions...........................................87
Fan Heatsink Power and Signal Specifications...................................................88
Baseboard Fan Power Connector Location ........................................................89
Signal Description ...............................................................................................90
Output Signals.....................................................................................................97
Input Signals........................................................................................................97
Input/Output Signals (Single Driver)....................................................................98
Input/Output Signals (Multiple Driver) .................................................................98
Datasheet
7
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
8
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
1.0
Introduction
The Intel® Pentium® III processor is the next member of the P6 family, in the Intel IA-32 processor
line. Like the Intel® Pentium® II processor, the Intel® Pentium® III processor implements the
Dynamic Execution microarchitecture - a unique combination of multiple branch prediction, data
flow analysis, and speculative execution. This enables these processors to deliver higher
performance than the Pentium processor, while maintaining binary compatibility with all previous
Intel Architecture processors. The Pentium III processor also executes MMX™ technology
instructions for enhanced media and communication performance just as it’s predecessor, the
Pentium II processor. The Pentium III processor executes Internet Streaming SIMD Extensions for
enhanced floating point and 3-D application performance. In addition, the Pentium III processor
extends the concept of processor identification with the addition of a processor serial number.
Refer to the Intel® Processor Serial Number application note (Order Number 245125) for more
detailed information. The Pentium III processor utilizes multiple low-power states such as
AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times.
The Pentium III processor utilizes the same multiprocessing system bus technology as the
Pentium II processor. This allows for a higher level of performance for both uni-processor and two-
way multiprocessor (2-way MP) systems. Please see the Pentium® III Processor Specification
Update (Order Number 244453) for guidelines on which processors can be mixed in an MP
system. Memory is cacheable for 4 GB of addressable memory space, allowing significant
headroom for desktop systems.
The Pentium III processor is available with two different second level (L2) cache implementations.
The “Discrete” cache version (CPUID 067xh) uses commercially available parts for the L2 cache.
The L2 cache is composed of an external (to processor silicon) TagRAM and burst pipelined
synchronous static RAM (BSRAM), as seen in Figure 1. The “Advanced Transfer Cache”
(CPUID 068xh) does not use commercially available L2 cache parts. Its L2 cache resides entirely
within the processor silicon, as seen in Figure 1. Refer to Table 1 to determine the L2 cache
implementation for each Pentium III processor.
Pentium III processors are offered in either Single Edge Contact Cartridge (S.E.C.C.) or Single
Edge Contact Cartridge 2 (S.E.C.C.2) package technologies. The S.E.C.C. package has the
following features: an extended thermal plate, a cover, and a substrate with an edge finger
connection. The extended thermal plate allows heatsink attachment or customized thermal
solutions. The S.E.C.C.2 package has a cover and a substrate with an edge finger connection. This
allows the thermal solutions to be placed directly onto the processor core package. The edge finger
connection maintains socketability for system configuration. The edge finger connector is called
the ‘SC242 connector’ in this and other documentation.
Figure 1. Second Level (L2) Cache Implementation
L2
Processor
Core
Processor
Core
Tag
L2
Discrete Cache
Advanced Transfer Cache
Datasheet
9
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
1.1
Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to
a hex ‘A’ (H= High logic level, L= Low logic level).
The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the
AGPset components), and other bus agents. The system bus is a multiprocessing interface to
processors, memory, and I/O. The term “cache bus” refers to the interface between the processor
and the L2 cache components (TagRAM and BSRAMs). The cache bus does NOT connect to the
system bus, and is not visible to other agents on the system bus.
1.1.1
S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology
The following terms are used often in this document and are explained here for clarification:
• Pentium® III processor—The entire product including internal components, substrate, cover
and in S.E.C.C. packaged processors, an extended thermal plate.
• S.E.C.C.—The processor package technology called “Single Edge Contact Cartridge.”
• S.E.C.C.2—The follow-on to S.E.C.C. processor package technology. This differs from its
predecessor in that it has no extended thermal plate, thus reducing thermal resistance.
• Processor substrate—The FR4 board on which components are mounted inside the S.E.C.C.
or S.E.C.C.2 packaged processor (with or without components attached).
• Processor core—The processor’s execution engine.
• Extended Thermal Plate—This S.E.C.C. package feature is the surface used to attach a
heatsink or other thermal solution to the processor.
• Cover—The plastic casing that covers the backside of the substrate.
• Latch arms—An S.E.C.C. package feature which can be used as a means for securing the
processor in a retention mechanism.
• OLGA - Organic Land Grid Array. This package technology permits attaching the heatsink
directly to the die.
Additional terms referred to in this and other related documentation:
• SC242—The 242-contact slot connector (previously referred to as Slot 1 connector) that the
S.E.C.C. and S.E.C.C.2 plug into, just as the Pentium® Pro processor uses Socket 8.
• Retention mechanism—A mechanical piece which holds the S.E.C.C. or S.E.C.C.2 packaged
processor in the SC242 connector.
• Heatsink support—The support pieces that are mounted on the baseboard to provide added
support for heatsinks.
• Keep-out zone—The area on or near an S.E.C.C. or S.E.C.C.2 packaged processor substrate
that systems designs can not utilize.
• Keep-in zone—The area of the center of an S.E.C.C. or S.E.C.C.2 packaged processor
substrate that thermal solutions may utilize.
The L2 cache, TagRAM and BSRAM die, are industry designated names.
10
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
1.1.2
Processor Naming Convention
A letter(s) is added to certain processors (e.g., 600B MHz) when the core frequency alone may not
uniquely identify the processor. Below is a summary what the letter means as well as a table
listing all Pentium III processors currently available.
• “B” — 133 MHz System Bus Frequency
• “E” — Processor with “Advanced Transfer Cache” (CPUID 068xh)
Table 1. Processor Identification
Core
Frequency
(MHz)
System Bus
Frequency
(MHz)
L2 Cache Size
(Kbytes)
1
Processor
L2 Cache Type
CPUID
450
500
450
500
533
533
550
550
600
600
600
600
650
667
700
733
750
800
800
100
100
133
133
100
100
100
133
100
133
100
133
100
133
100
100
133
512
512
512
256
512
256
512
512
256
256
256
256
256
256
256
256
256
Discrete
Discrete
Discrete
067xh
067xh
067xh
068xh
067xh
068xh
067xh
067xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
068xh
533B
533EB
550
2
ATC
Discrete
2
550E
600
ATC
Discrete
Discrete
600B
600E
600EB
650
2
ATC
2
ATC
2
ATC
2
667
ATC
2
700
ATC
2
733
ATC
2
750
ATC
2
800
ATC
2
800EB
ATC
NOTES:
®
1. Refer to the Pentium III Processor Specification Update for the exact CPUID for each processor.
2. ATC = Advanced Transfer Cache. ATC is an L2 Cache integrated on the same die as the processor core.
With ATC, the interface between the processor core and L2 Cache is 256-bits wide, runs at the same
frequency as the processor core and has enhanced buffering.
1.2
Related Documents
The reader of this specification should also be familiar with material and concepts in the
documents listed in Table 2. These documents, and a complete list of Pentium III processor
reference material, can be found on the Intel Developers’ Insight web site located at
http://developer.intel.com.
Datasheet
11
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 2. Related Documents
Document
Intel Order Number
®
AP-485, Intel Processor Identification and the CPUID Instruction
241618
243330
243333
243334
®
AP-585, Pentium II Processor GTL+ Guidelines
AP-588, Mechanical and Assembly Technology for S.E.C. Cartridge Processors
AP-589, Design for EMI
AP-826, Mechanical Assembly and Customer Manufacturing Technology for
S.E.P. Packages
243748
244454
244457
245087
245086
AP-902, S.E.C.C.2 Heatsink Installation and Removal
AP-903, Mechanical Assembly and Customer Manufacturing Technology for
Processor in S.E.C.C.2 Packages
®
AP-905, Pentium III Processor Thermal Design Guidelines
®
AP-906, 100 MHz AGTL+ Layout Guidelines for the Pentium III Processor and
®
Intel 440BX AGPset
®
AP-907, Pentium III Processor Power Distribution Guidelines
245085
245119
243867
243193
243190
243191
243192
244001
243657
243502
†
®
Intel Processor Serial Number
CK97 Clock Synthesizer Design Guidelines
®
Intel Architecture Software Developer's Manual
Volume I: Basic Architecture
Volume II: Instruction Set Reference
Volume III: System Programming Guide
P6 Family of Processors Hardware Developer’s Manual
®
Pentium II Processor at 350, 400 and 450 MHz datasheet
®
Pentium II Processor Developer’s Manual
®
Pentium III Processor I/O Buffer Models
®
Pentium III Processor Specification Update
244453
243409
243397
243773
SC242 Bus Termination Card Design Guidelines
Slot 1 Connector Specification
VRM 8.2 DC-DC Converter Design Guidelines
†
These models are available in Viewlogic* XTK* model format (formerly known as QUAD format) at the Intel
Developer’s Website at http://developer.intel.com.
12
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
2.0
Electrical Specifications
2.1
Processor System Bus and V
REF
Most Intel® Pentium® III processor signals use a variation of the low voltage Gunning Transceiver
Logic (GTL) signaling technology.
The Pentium Pro processor system bus specification is similar to the GTL specification, but was
enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the Pentium® II
Processor Developer’s Manual (Order Number 243502).
The Pentium III processor varies from the Pentium Pro processor in its output buffer
implementation. The buffers that drive the system bus signals on the Pentium III processor are
actively driven to VCCCORE for one clock cycle after the low to high transition to improve rise
times. These signals should still be considered open-drain and require termination to a supply that
provides the high signal level. Because this specification is different from the GTL+ specification,
it is referred to as AGTL+ in this and other documentation. AGTL+ logic and GTL+ logic are
compatible with each other and may both be used on the same system bus. For more information on
AGTL+ routing, see AP-906, 100 MHz AGTL+ Layout Guidelines for the Pentium III® Processor
and Intel® 440BX AGPset (Order Number 245086) or the appropriate platform design guide.
AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by the
receivers to determine if a signal is a logical 0 or a logical 1, and is generated on the S.E.C.C. and
S.E.C.C.2 packages for the processor core. Local VREF copies should be generated on the baseboard
for all other devices on the AGTL+ system bus. Termination (usually a resistor at each end of the
signal trace) is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor contains termination resistors that provide termination for one end
of the Pentium III processor system bus. These specifications assume another resistor at the end of
each signal trace to ensure adequate signal quality for the AGTL+ signals; see Table 11 for the bus
termination voltage specifications for AGTL+. Refer to the Pentium® II Processor Developer’s
Manual (Order Number 243502) for the GTL+ bus specification. Solutions exist for single-ended
termination as well, though this implementation changes system design. Figure 2 is a schematic
representation of AGTL+ bus topology with Pentium III processors.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
Pentium III processor system bus including trace lengths is highly recommended when designing a
system with a heavily loaded AGTL+ bus, especially for systems using a single set of termination
resistors (i.e., those on the processor substrate). Such designs will not match the solution space
allowed for by installation of termination resistors on the baseboard. See Intel’s Developer’s
Website (http://developer.intel.com) to download the Pentium® III Processor I/O Buffer Models,
Viewlogic* XTK* model format (formerly known as QUAD format).
Datasheet
13
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 2. AGTL+ Bus Topology
Pentium®III
ASIC
Pentium III
Processor
Processor
2.2
Clock Control and Low Power States
Pentium III processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to
reduce power consumption by stopping the clock to internal sections of the processor, depending
on each particular state. See Figure 3 for a visual representation of the Pentium III processor low
power states.
Figure 3. Stop Clock State Machine
HALT Instruction and
HALT Bus Cycle Generated
1. Normal State
2. Auto HALT Power Down State
BCLK running.
INIT#, BINIT#, INTR,
SMI#, RESET#
Normal execution.
Snoops and interrupts allowed.
STPCLK# Asserted
STPCLK# De-asserted
and Stop-Grant State
STPCLK#
Asserted
STPCLK#
De-asserted
Snoop
Event
Occurs
Snoop
Event
Serviced
entered from
AutoHALT
Snoop Event Occurs
Snoop Event Serviced
3. Stop Grant State
4. HALT/Grant Snoop State
BCLK running.
BCLK running.
Snoops and interrupts allowed.
Service snoops to caches.
SLP#
SLP#
Asserted
De-asserted
5. Sleep State
BCLK running.
No snoops or interrupts allowed.
BCLK
Input
BCLK
Input
Stopped
Restarted
6. Deep Sleep State
BCLK stopped.
No snoops or interrupts allowed.
PCB757a
14
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Intel Architecture Software Developer’s
Manual, Volume 3: System Programming Guide (Order Number 243192).
Due to the inability of processors to recognize bus transactions during the Sleep and Deep Sleep
states, 2-way MP systems are not allowed to have one processor in Sleep/Deep Sleep state and the
other processor in Normal or Stop-Grant state simultaneously.
2.2.1
2.2.2
Normal State—State 1
This is the normal operating state for the processor.
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide (Order Number 243192) for more information.
FLUSH# will be serviced during the AutoHALT state, and the processor will return to the
AutoHALT state.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
2.2.3
Stop-Grant State—State 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# and FLUSH# will not be serviced during Stop-Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 2.2.4). A transition to the Sleep state (see Section 2.2.5) will occur with the
assertion of the SLP# signal.
While in Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only
serviced when the processor returns to the Normal state. Only one occurrence of each event will be
recognized and serviced upon return to the Normal state.
Datasheet
15
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
2.2.4
HALT/Grant Snoop State—State 4
The processor will respond to snoop transactions on the Pentium III processor system bus while in
Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the
Pentium III processor system bus has been serviced (whether by the processor or another agent on
the Pentium III processor system bus). After the snoop is serviced, the processor will return to the
Stop-Grant state or AutoHALT Power Down state, as appropriate.
2.2.5
Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted,
causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or
AutoHALT states.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input (see Section 2.2.6). Once in the Sleep or Deep Sleep states, the
SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a
minimum assertion of one BCLK period.
2.2.6
Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK is
stopped. It is recommended that the BCLK input be held low during the Deep Sleep State.
Stopping of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
16
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
2.2.7
Clock Control
The processor provides the clock signal to the L2 cache. During AutoHALT Power Down and
Stop-Grant states, the processor will process a system bus snoop. The processor will not stop the
clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the Halt/
Grant Snoop state will allow the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it will not respond to interrupts or snoop
transactions. During the Sleep state, the clock to the L2 cache is not stopped. During the Deep
Sleep state, the clock to the L2 cache is stopped. The clock to the L2 cache will be restarted only
after the internal clocking mechanism for the processor is stable (i.e., the processor has re-entered
Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3
Power and Ground Pins
For clean on-chip power distribution, Pentium III processors have 27 VCC (power) and 30 VSS
(ground) inputs. The 27 VCC pins are further divided to provide the different voltage levels to the
components. VCCCORE inputs for the processor core and some L2 cache components account for
19 of the VCC pins, while 4 VTT inputs (1.5 V) are used to provide an AGTL+ termination voltage
to the processor and 3 VCCL2/VCC3.3 inputs (3.3 V) are either used for the off-chip L2 cache
TagRAM and BSRAMs (CPUID 067xh) or for the voltage clamp logic (CPUID 068xh). One VCC
5
pin is provided for use by test equipment and tools. VCC , VCCL2/VCC3.3, and VCCCORE must
5
remain electrically separated from each other. On the circuit board, all VCCCORE pins must be
connected to a voltage island and all VCCL2/VCC3.3 pins must be connected to a separate voltage
island (an island is a portion of a power plane that has been divided, or an entire plane). Similarly,
all VSS pins must be connected to a system ground plane.
Note: The voltage clamp logic acts as a voltage translator between the processor’s 1.5 V tolerant CMOS
signals and the 2.5 V CMOS voltage on the motherboard. This logic is only available with
Pentium III processors with CPUID=068xh.
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 8. Failure to do so can result in timing violations or a reduced lifetime
of the processor.
2.4.1
Processor VCCCORE Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep an interconnect resistance from the regulator (or VRM pins) to the SC242 connector of
less than 0.3 mΩ. This can be accomplished by keeping a maximum distance of 1.0 inches between
the regulator output and SC242 connector. The recommended VCCCORE interconnect is a 2.0 inch
wide by 1.0 inch long (maximum distance between the SC242 connector and the VRM connector)
Datasheet
17
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
plane segment with a 1-ounce plating. Bulk decoupling for the large current swings when the part
is powering on, or entering/exiting low power states, is provided on the voltage regulation module
(VRM). If using Intel’s enabled VRM solutions see developer.intel.com for the specification and a
list of qualified vendors. The VCCCORE input should be capable of delivering a recommended
minimum dIccCORE/dt (defined in Table 8) while maintaining the required tolerances (also defined
in Table 8).
2.4.2
Processor System Bus AGTL+ Decoupling
The Pentium III processor contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling must be provided for by the system baseboard for proper AGTL+ bus
operation. See AP-906, 100 MHz AGTL+ Layout Guidelines for the Pentium® III Processor and
Intel® 440BX AGPset (Order Number 245086) or the appropriate platform design guide, AP-907,
Pentium® III Processor Power Distribution Guidelines (Order Number 245085), and the GTL+
buffer specification in the Pentium® II Processor Developer's Manual (Order Number 243502) for
more information.
2.5
2.6
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the Pentium III processor system bus
interface. All Pentium III processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the P6 Family of Processors Hardware Developer's Manual
(Order Number 244001) for further details.
Voltage Identification
There are five voltage identification pins on the SC242 connector. These pins can be used to
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines
the voltage required by the processor core. The VID pins are needed to cleanly support voltage
specification variations on current and future Pentium III processors. VID[4:0] are defined in
Table 3. A ‘1’ in this table refers to an open pin and a ‘0’ refers to a short to ground. The power
supply must supply the voltage that is requested or disable itself.
To ensure a system is ready for current and future Pentium III processors, the range of values in
bold in Table 3 should be supported. A smaller range will risk the ability of the system to migrate
to a higher performance Pentium III processor and/or maintain compatibility with current
Pentium III processors.
18
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 3. Voltage Identification Definition 1, 2
Processor Pins
VID1
VID4
VID3
VID2
VID0
Vcc
CORE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.30
1.35
1.40
1.45
1.50
1.55
3
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
3
3
3
3
3
3
3
3
3
No Core
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on baseboard.
®
3. To ensure a system is ready for the Pentium III processor, the values in BOLD in Table 3 should be
supported.
Note that the ‘11111’ (all opens) ID can be used to detect the absence of a processor core in a given
connector as long as the power supply used does not affect these lines. Detection logic and pull-ups
should not affect VID inputs at the power source (see Section 7.0).
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power
source of the regulator only if required by the regulator or external logic monitoring the VID[4:0]
signals. The power source chosen must be guaranteed to be stable whenever the supply to the
Datasheet
19
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-
DC converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. A resistor of greater than or equal to 10 kΩ may be used to connect the VID signals to the
converter input.
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VCC
/
L2
VCC3.3, VSS, or to any other signal (including each other) can result in component malfunction or
incompatibility with future Pentium III processors. See Section 5.5 for a pin listing of the processor
and the location of each RESERVED pin.
All TESTHI pins must be connected to 2.5 V via 1 kΩ -10 kΩ pull-up resistor.
PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to
2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each
APIC data line.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused AGTL+ inputs should be left as no connects; AGTL+ termination is provided
on the processor. Unused active low CMOS inputs should be connected through a resistor to 2.5 V.
Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
For unused pins, it is suggested that ~10 kΩ resistors be used for pull-ups (except for PICD[1:0]
discussed above), and ~1 kΩ resistors be used as pull-downs.
2.8
Processor System Bus Signal Groups
In order to simplify the following discussion, the Pentium III processor system bus signals have
been combined into groups by buffer type. All Pentium III processor system bus outputs are open
drain and require a high-level source provided externally by the termination or pull-up resistor.
However, the Pentium III processor includes on-cartridge (CPUID 067xh) or on-die (CPUID
068xh) termination.
AGTL+ input signals have differential input buffers, which use VREF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
EMI pins may be connected to baseboard ground and/or to chassis ground through zero ohm (0Ω)
resistors. The 0Ω resistors should be placed in close proximity to the SC242 connector. The path to
chassis ground should be short in length and have a low impedance.
The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5 V. The CMOS,
APIC, and TAP outputs are open drain and should be pulled high to 2.5 V. This ensures not only
correct operation for current Pentium III processors, but compatibility with future Pentium III
processors as well.
The groups and the signals contained within each group are shown in Table 4. Refer to Section 7.0
for a description of these signals.
20
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 4. System Bus Signal Groups
Group Name
Signals
AGTL+ Input
BPRI#, BR1#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
PRDY#
AGTL+ Output
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0# , D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
AGTL+ I/O
1
2
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD ,
SMI#, SLP# , STPCLK#
CMOS Input5
3
4
CMOS Output5
FERR#, IERR#, THERMTRIP#
System Bus Clock BCLK
APIC Clock
APIC I/O5
PICCLK
PICD[1:0]
TAP Input5
TAP Output5
TCK, TDI, TMS, TRST#
TDO
VCC
CORE
BSEL[1:0], EMI, TESTHI, Reserved
, VCC /VCC , VCC , VID[4:0], VTT, VSS, SLOTOCC#, THERMDP, THERMDN,
L2 3.3 5
Power/Other6
NOTES:
1. The BR0# pin is the only BREQ# signal that is bidirectional. The internal BREQ# signals are mapped onto
BR# pins after the agent ID is determined. See Section 7.0 for more information.
2. See Section 7.0 for information on the PWRGOOD signal.
3. See Section 7.0 for information on the SLP# signal.
4. See Section 7.0 for information on the THERMTRIP# signal.
5. These signals are specified for 2.5 V operation.
6. VCC
is the power supply for the processor core.
CORE
VCC /VCC is described in Section 2.3.
L2
3.3
VID[4:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate VREF on the processor substrate.
VSS is system ground.
TESTHI should be connected to 2.5 V with a 1 kΩ –10 kΩ resistor.
®
VCC is not connected to the Pentium III processor core. This supply is used for the test equipment and
5
tools.
SLOTOCC# is described in Section 7.0.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
EMI pins are described in Section 7.0.
THERMDP, THERMDN are described in Section 7.0.
2.8.1
2.8.2
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK.
All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK.
System Bus Frequency Select Signal (BSEL0)
The BSEL[1:0] signals (BSEL0 is also known as 100/66#) are used to select the system bus
frequency for the Pentium III processor(s). Table 5 defines the possible combinations of the signals
and the frequency associated with each combination. The frequency is determined by the
processor(s), and frequency synthesizer. All system bus agents must operate at the same core and
system bus frequency in a 2-way MP Pentium III processor configuration. In a 2-way MP system
Datasheet
21
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
design, the BSEL[1:0] signals must be connected to the BSEL[1:0] pins of both processors. The
Pentium III processor operates at either a 100 MHz or 133 MHz system bus frequency, but not
both. 66 MHz system bus operation is not supported.
For systems that support only a 100 MHz system bus clock, resistors on the processor cartridge
will tie the BSEL1 signal to ground (as shown in Figure 4). This signal can either be left as a no
connect or tied to ground as shown below. The BSEL0 should be pulled up to 3.3 V with a 220 Ω
resistor, and provided as a frequency driver to the clock driver/synthesizer.
On baseboards which support operation at either 100 or 133 MHz, the BSEL[1:0] signals should be
pulled up to 3.3 V with a 220 Ω resistor (as shown in Figure 5 and Figure 6) and BSEL1 is
provided as a frequency selection signal to the clock driver/synthesizer. The BSEL0 signal can also
be incorporated into system shutdown logic on the baseboard (thus forcing the system to shutdown
as long as the BSEL0 signal is low). Figure 4 shows this routing example with a 100 MHz
Pentium III processor. Figure 5 shows the same routing example with a 133 MHz Pentium III
processor.
Table 5. Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Frequency
0
0
1
1
0
1
0
1
66MHz (unsupported)
100 MHz
Reserved
133MHz
Figure 4. BSEL[1:0] Example for a 100 MHz System Design (100 MHz Processor Installed)
Intel® Pentium® III Processor
0
Ω
0
Ω
3.3V
GND
S
C
2
4
2
BSEL1
CK100
GND
220
Ω
Processor
Core
100/66#
1
ΚΩ
3.3 ΚΩ
GND
BSEL0
22
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 5. BSEL[1:0] Example for a 100/133 MHz Capable System
(100 MHz Processor Installed)
3.3V
CK133
220
Ω
Intel ® Pentium ® III Processor
133/100#
0
0
Ω
Ω
3.3V
GND
BSEL1
S
C
2
4
2
220
Ω
Processor
Core
System
Shutdown
Logic
1
3.3
ΚΩ
ΚΩ
GND
BSEL0
Figure 6. BSEL[1:0] Example for a 100/133 MHz Capable System
(133 MHz Processor Installed)
3.3V
CK133
220
Ω
Intel® Pentium® III Processor
ΚΩ
3.3 ΚΩ
133/100#
1
3.3V
GND
BSEL1
S
C
2
4
2
220
Ω
Processor
Core
System
Shutdown
Logic
1
3.3
ΚΩ
ΚΩ
GND
BSEL0
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Pentium III processor be first in the TAP chain and followed by any other
components within the system. A translation buffer should be used to connect to the rest of the
chain unless one of the other components is capable of accepting a 2.5 V input. Similar
considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be
required with each driving a different voltage level.
The Debug Port should be placed at the start and end of the TAP chain with the TDI of the first
component coming from the Debug Port and the TDO from the last component going to the Debug
Port. In a 2-way MP system, be cautious when including an empty SC242 connector in the scan
chain. All connectors in the scan chain must have a processor installed to complete the chain or the
system must support a method to bypass the empty connectors; SC242 terminator substrates should
not connect TDI to TDO in order to avoid placing the TDO pull-up resistors in parallel. See SC242
Terminator Card Design Guidelines (Order Number 243409) for more details.
Datasheet
23
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
2.10
Maximum Ratings
Table 6 contains Pentium III processor stress ratings only. Functional operation at the absolute
maximum and minimum is not implied nor guaranteed. The processor should not receive a clock
while subjected to these conditions. Functional operating conditions are given in the AC and DC
tables in Section 2.11 and Section 2.13. Extended exposure to the maximum ratings may affect
device reliability. Furthermore, although the processor contains protective circuitry to resist
damage from static electric discharge, one should always take precautions to avoid high static
voltages or electric fields.
Table 6. Absolute Maximum Ratings (CPUID 067xh)
Symbol
Parameter
Min
Max
Unit
Notes
TSTORAGE
Processor storage temperature
–40
85
°C
Any processor supply voltage with
respect to VSS
Operating
voltage + 1.0
VCC
–0.5
–0.3
–0.3
V
V
V
1, 2
(All)
AGTL+ buffer DC input voltage with
respect to VSS
Vin
Vin
VCCCORE + 0.7
3.3
AGTL
CMOS
CMOS buffer DC input voltage with
respect to VSS
3
IVID
Max VID pin current
5
5
mA
mA
ISLOTOCC
Max SLOTOCC# pin current
Mech Max
Latch Arms
Mechanical integrity of latch arms
50
50
Cycles
4, 7
5, 6
Mech Max
Edge Fingers
Mechanical integrity of processor edge
fingers
Insertions/
Extractions
NOTES:
1. Operating voltage is the voltage to which the component is designed to operate. See Table 8.
2. This rating applies to the VCC
processor.
, VCC /VCC , VCC , and any input (except as noted below) to the
CORE
L2 3.3 5
3. Parameter applies to CMOS, APIC, and TAP bus signal groups only.
4. The mechanical integrity of the latch arms is specified to last a maximum of 50 cycles.
5. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/
extraction cycles.
6. While insertion/extraction cycling above 50 insertions will cause an increase in the contact resistance (above
0.1 Ω) and a degradation in the material integrity of the edge finger gold plating, it is possible to have
processor functionality above the specified limit. The actual number of insertions before processor failure will
vary based upon system configuration and environmental conditions.
7. This specification only applies to S.E.C.C. packaged processors.
24
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 7. Absolute Maximum Ratings (CPUID 068xh)
Symbol
Parameter
Min
Max
Unit
Notes
T
Processor storage temperature
–40
85
°C
STORAGE
VCC
VTT
and
Processor core voltage and Termination
supply voltage with respect to VSS
CORE
-0.5
2.1
V
VCC /VCC
L2 3.3
VCC
with respect to VSS
–0.5
VTT – 2.3
–0.7
5.0
V
V
1
3.3
Vin
Vin
1.5 V buffer input voltage
2.5 V buffer input voltage
Max VID pin current
VSS + 2.3
2, 3, 5
4
1.5
2.5
3.3
5
V
IVID
mA
mA
ISLOTOCC
Mech Max
Max SLOTOCC# pin current
5
Mechanical integrity of processor edge
fingers
Insertions/
Extractions
50
6, 7
Edge Fingers
NOTES:
1. Operating voltage is the voltage to which the component is designed to operate. See Table 7.
2. Input voltage can never be above VSS + 2.3 V.
3. Input voltage can never be below VTT - 2.3 V.
4. Parameter applies to the 2.5 V processor core signals (BCLK, PICCLK, and PWRGOOD).
5. Parameter applies to the 1.5 V processor core signals (all signals except BCLK, PICCLK, and PWRGOOD).
6. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/
extraction cycles.
7. While insertion/extraction cycling above 50 insertions will cause an increase in the contact resistance (above
0.1Ω) and a degradation in the material integrity of the edge finger gold plating, it is possible to have
processor functionality above the specified limit. The actual number of insertions before processor failure will
vary based upon system configuration and environmental conditions.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the Pentium III processor core pins,
edge fingers, and at the SC242 connector pins. See Section 7.0 for the processor edge finger signal
definitions and Section 5.0 for the core pin locations and the signal listing.
Most of the signals on the Pentium III processor system bus are in the AGTL+ signal group. These
signals are specified to be terminated to 1.5 V. The DC specifications for these signals are listed in
Table 9.
To allow connection with other devices, the Clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 10.
Table 8 through Table 11 list the DC specifications for Pentium III processors. Specifications are
valid only while meeting specifications for case temperature, clock frequency, and input voltages.
Care should be taken to read all notes associated with each parameter.
Datasheet
25
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 8. Voltage and Current Specifications
1
Symbol
Parameter
Core Freq
Min
Typ
Max
Unit
Notes
450 MHz
500 MHz
533B MHz
533EB MHz
550 MHz
550E MHz
600 MHz
600B MHz
600E MHz
600EB MHz
650 MHz
667 MHz
700 MHz
733 MHz
750 MHz
800 MHz
800EB MHz
2.00
2.00
2.00
1.65
2.00
1.65
2.05
2.05
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
1.65
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
VCC
VCC for processor core
CORE
VCC for second level
cache or voltage clamp
logic
VCC
VCC
/
9
L2
3.135
1.365
3.3
3.465
1.635
V
V
3.3 V ±5%
3.3
AGTL+ bus termination
voltage
6
VTT
1.50
1.5 ±9%
Baseboard
Tolerance,
Static
Processor core voltage
static tolerance level at
SC242 pins
–0.070
–0.080
0.070
0.040
V
V
2, 7, 18
2, 7, 19
Baseboard
Tolerance,
Transient
Processor core voltage
transient tolerance level at
SC242 pins
–0.140
–0.080
0.140
0.050
V
V
2, 7, 18
2, 7, 19
VCC
CORE
Tolerance,
Static
Processor core voltage
static tolerance level at
edge fingers
–0.085
–0.110
0.085
0.040
V
V
2, 8, 18
2, 8, 19
VCC
CORE
Tolerance,
Transient
Processor core voltage
transient tolerance level at
edge fingers
–0.170
–0.110
0.170
0.080
V
V
2, 8, 18
2, 8, 19
450 MHz
500 MHz
533B MHz
533EB MHz
550 MHz
550E MHz
600 MHz
600B MHz
600E MHz
600EB MHz
650 MHz
667 MHz
700 MHz
733 MHz
750 MHz
800 MHz
800EB MHz
14.5
16.1
16.7
11.0
17.0
11.0
17.8
17.8
13.3
13.3
13.3
13.3
14.6
14.6
15.0
16.0
16.0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2, 3, 10, 11
2, 3, 10, 11
2, 3, 10, 11
2, 3, 20
2, 3, 10, 11
2, 3, 20
2, 3, 10, 11
2, 3, 10, 11
2, 3, 20
2, 3, 20
2, 3, 20
2, 3, 20
2, 3, 20
ICC
CORE
ICC for processor core
2, 3, 20
2, 3, 20
2, 3, 20
2, 3, 20
450 MHz
500 MHz
533B MHz
550 MHz
600 MHz
1.08
1.21
1.29
1.33
1.45
1.45
A
A
A
A
A
2, 9, 10, 18
2, 9, 10, 18
2, 9, 10, 18
2, 9, 10, 18
ICC
L2
ICC for second level cache
2, 9, 10, 18
600B MHz
Termination voltage
supply current
IVTT
2.7
A
12
26
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 8. Voltage and Current Specifications (Continued)
1
Symbol
Parameter
Core Freq
Min
Typ
Max
Unit
Notes
450 MHz
500 MHz
533B MHz
533EB MHz
550 MHz
550E MHz
600 MHz
600B MHz
600E MHz
600EB MHz
650 MHz
667 MHz
700 MHz
733 MHz
750 MHz
800 MHz
800EB MHz
1.20
1.40
1.49
2.50
1.54
2.50
1.68
1.68
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
2, 10, 13
ICC Stop-Grant for
processor core
ISG
nt
ICC Stop-Grant for second
level cache
ISG
0.1
A
2, 9, 10, 18
ntL2
450 MHz
500 MHz
533B MHz
533EB MHz
550 MHz
550E MHz
600 MHz
600B MHz
600E MHz
600EB MHz
650 MHz
667 MHz
700 MHz
733 MHz
750 MHz
800 MHz
800EB MHz
0.80
0.90
1.00
2.50
1.00
2.50
1.00
1.00
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
ICC Sleep for processor
core
ISLP
ICC Sleep for second level
cache
ISL
0.1
A
2, 9, 10, 18
PL2
ICC Deep Sleep for
processor core
0.50
2.20
A
A
2, 10, 18
2, 10, 19
IDSLP
ICC Deep Sleep for second
level cache
IDSL
0.1
20
1
A
2, 9, 10, 18
PL2
Power supply current slew
rate
dICC
CORE
/dt
A/µs 2, 14, 15, 16
L2 cache power supply
current slew rate
dICC /dt
A/µs 14, 15, 16, 18
L2
Termination current slew
rate
See
dICCVTT/dt
VCC
8
A/µs
14, 15
16, 17
Table 11
5 V ±5%
17
5 V supply voltage
4.75
5.00
1.0
5.25
V
A
5
ICC
ICC for 5 V supply voltage
5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
®
2. This specification applies to Pentium III processors. For baseboard compatibility information on Pentium II
®
processors, refer to the Pentium II Processor at 350, 400 and 450 MHz datasheet (Order Number 243657).
3. VCC
and Icc
supply the processor core.
CORE
CORE
4. A variable voltage source should exist on all systems in the event that a different voltage is required. See
Section 2.6 and Table 1 for more information.
5. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to
the processor.
Datasheet
27
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
6. V must be held to 1.5 V ±9%. It is recommended that V be held to 1.5 V ±3% while the Pentium III
TT
TT
processor system bus is idle. This is measured at the processor edge fingers across a 20 MHz bandwidth.
7. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the
bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops (and
impedance discontinuities) across the connector, processor edge fingers, and to the processor core.
VCC
must return to within the static voltage specification within 100 µs after a transient event; see the
CORE
VRM 8.2 DC-DC Converter Design Guidelines (Order Number 243773) for further details.
8. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The
requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the
processor edge fingers and to the processor core. VCC
must return to within the static voltage
CORE
specification within 100 µs after a transient event.
9. VCC /VCC and I
/I
supply the second level cache (“Discrete” cache type only). Unless otherwise
L2
3.3
CCL2 CC3.3
noted, this specification applies to all Pentium III processor cache sizes. Systems should be designed for
these specifications, even if a smaller cache size is used.
10.Max ICC measurements are measured at VCC max voltage, maximum temperature, under maximum signal
loading conditions. The Max Icc currents specified do not occur simultaneously under the stress
measurement condition.
11.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VCC
CORE
(VCC
). In this case, the maximum current level for the regulator, Icc
, can be reduced from
CORE_TYP
CORE_REG
the specified maximum current Icc
and is calculated by the equation:
CORE _MAX
Icc
= Icc
× VCC
/ (VCC
CORE_TYP
+ VCC
Tolerance, Transient)
CORE
CORE_REG
CORE_MAX
CORE_TYP
12.The current specified is the current required for a single Pentium III processor. A similar amount of current is
drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended
termination is used (see Section 2.1).
13.The current specified is also for AutoHALT state.
14.Maximum values are specified by design/characterization at nominal VCC
and nominal VCC /VCC
.
3.3
CORE
L2
15.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
16.dI /dt specifications are measured and specified at the SC242 connector pins.
CC
17.Vcc and ICC are not used by the Pentium III processors. The VCC supply is used for the test equipment
5
5
5
and tools.
®
18.This specification applies to the Pentium III processor with CPUID=067xh.
19.This specification applies to the Pentium III processor with CPUID=068xh.
®
20.Max I measurements are measured at VCC nominal voltage, maximum temperature, under maximum
CC
signal loading conditions. The Max Icc currents specified do not occur simultaneously under the stress
measurement condition.
Table 9. AGTL+ Signal Groups DC Specifications 1, 4, 5
Symbol
Parameter
Min
Max
Unit
Notes
–0.30
–0.15
0.82
VREF - 0.20
V
V
12
13
V
V
Input Low Voltage
IL
1.22
VREF + 0.20
VTT
VTT
2, 3, 12
2, 3, 13
Input High Voltage
Buffer On Resistance
Leakage Current
V
IH
Ron
16.67
Ω
9
±100
±100
µA
µA
6, 7, 8, 12
6, 10, 11, 13
I
L
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to Pentium III processor frequencies.
2. V and V
for the Pentium III processor may experience excursions up to 200 mV above VTT for a single
IH
OH
system bus clock. However, input signal drivers must comply with the signal quality specifications in Section
3.0.
3. Minimum and maximum VTT are given in Table 11.
4. Parameter correlated to measure into a 25Ω resistor terminated to 1.5 V.
5. I for the Pentium III processor may experience excursions of up to a 12 mA for a single bus clock.
OH
6. Leakage current affects input, output, and I/O signals.
7. (0 ≤ V ≤ 2.0 V +5%).
IN
8. (0 ≤ V
≤ 2.0 V +5%).
OUT
9. Refer to the Pentium III I/O Buffer Models for I/V characteristics.
10.(0 ≤ V ≤ 1.5 V +5%).
IN
11. (0 ≤ V
≤ 1.5 V +5%).
OUT
®
12.This specification applies to the Pentium III processor with CPUID=067xh.
®
13.This specification applies to the Pentium III processor with CPUID=068xh.
28
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 10. Non-AGTL+ Signal Group DC Specifications 1
Symbol
Parameter
Min
Max
Unit
Notes
–0.30
–0.15
–0.30
–0.30
–0.15
0 . 5
0 . 7
0 . 5
0 . 7
0.7
V
V
V
V
V
3, 8
3, 9, 10
2, 9; BCLK only
2, 9; PICCLK only
2, 9; PWRGOOD only
V
Input Low Voltage
IL
1.7
1.7
2.0
2.625
2.625
2.625
V
V
V
3, 8
3, 9, 10
2, 9; BCLK, PICCLK,
and PWRGOOD only
V
Input High Voltage
IH
0.4
0.5
V
V
3, 4, 8
3, 4, 9
V
V
Output Low Voltage
Output High Voltage
OL
All outputs are open-
drain
N/A
14
2.625
V
OH
I
I
Output Low Current
Leakage Current
mA
µA
3
OL
±100
5, 6, 7
L
NOTES:
®
®
1. Unless otherwise noted, all specifications in this table apply to all Intel Pentium III processor frequencies.
2. These values are specified at the processor core pins.
3. These values are specified at the processor edge fingers.
4. Parameter measured at 14 mA (for use with TTL inputs).
5. Leakage current affects input, output and I/O signals.
6. (0 ≤ V ≤ 2.5 V +5%).
IN
7. (0 ≤ V
≤ 2.5 V +5%).
OUT
®
8. This specification applies to the Pentium III processor with CPUID=067xh.
®
9. This specification applies to the Pentium III processor with CPUID=068xh.
10.Parameters apply to all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD.
2.12
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the VTT voltage supply and generally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called VREF
.
Table 11 lists the nominal specification for the AGTL+ termination voltage (VTT). The AGTL+
reference voltage (VREF) is generated on the processor substrate for the processor core, but should
be set to 2/3 VTT for other AGTL+ logic using a voltage divider on the baseboard. It is important
that the baseboard impedance be specified and held to a ±15% tolerance, and that the intrinsic trace
capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on
the GTL+ buffer specification, see the Pentium® II Processor Developer's Manual (Order Number
243502) and AP-585, Pentium® II Processor GTL+ Guidelines (Order Number 243330).
Datasheet
29
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 11. AGTL+ Bus Specifications 1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
VTT
RTT
Bus Termination Voltage
Termination Resistor
1.365
1.50
56
1.635
V
Ω
V
3
4
5
V
Bus Reference Voltage
0.95
2/3 VTT
1.05
REF
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Pentium III processors contain AGTL+ termination resistors at the end of each signal trace on the processor
substrate. Pentium III processors generate V
VTT supplied through the SC 242 connector.
on the processor substrate by using a voltage divider on
REF
3. VTT must be held to 1.5 V ±9%; dICC
/dt is specified in Table 8. It is recommended that VTT be held to
VTT
1.5 V ±3% while the Pentium III processor system bus is idle. This is measured at the processor edge
fingers.
4. RTT must be held within a tolerance of ±5%
5. V
is generated on the processor substrate to be 2/3 VTT ±2% nominally.
REF
2.13
System Bus AC Specifications
The Pentium III processor system bus timings specified in this section are defined at the Pentium III
processor core pads. Unless otherwise specified, timings are tested at the processor core during
manufacturing. See Section 7.0 for the Pentium III processor edge connector signal definitions. See
Section 5.6 for the Pentium III processor closest accessible core pad to substrate via assignment.
Table 12 through Table 18 list the AC specifications associated with the Pentium III processor
system bus. These specifications are broken into the following categories: Table 12 through
Table 13 contain the system bus clock core frequency and cache bus frequencies, Table 14 contains
the AGTL+ specifications, Table 15 contains the CMOS signal group specifications, Table 16
contains timings for the Reset conditions, Table 17 covers APIC bus timing, and Table 18 covers
TAP timing.
All Pentium II processor system bus AC specifications for the AGTL+ signal group are relative to
the rising edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and ‘1’
logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium III processor in Viewlogic XTK model format (formerly known as QUAD format) as
the Pentium® III Processor I/O Buffer Models on Intel’s Developer’s Website
(http://developer.intel.com.) AGTL+ layout guidelines are also available in AP-906, 100 MHz
AGTL+ Layout Guidelines for the Pentium® III Processor and Intel® 440BX AGPset (Order
Number 245086) or the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
30
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 12. System Bus AC Specifications (Clock) at Processor Core Pins 1, 2, 3
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
100.00
133.33
MHz
MHz
4, 10
4, 11
System Bus Frequency
10.0
7.5
ns
ns
7
7
4, 5, 10
4, 5, 11
T1: BCLK Period
T2: BCLK Period Stability
T3: BCLK High Time
±250
ps
7
7, 9
2.5
1.4
ns
ns
7
7
@>2.0 V, 10
@>2.0 V, 11
6, 10
2.4
1.4
ns
ns
7
7
@<0.5 V
@<0.5 V
T4: BCLK Low Time
6, 11
8, 10, 11
8, 10, 11
T5: BCLK Rise Time
T6: BCLK Fall Time
0.4
0.4
1.60
1.60
ns
ns
7
7
(0.5 V–2.0 V)
(2.0 V–0.5 V)
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core
pins.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.
4. The internal core clock frequency is derived from the Pentium III processor system bus clock. The system
bus clock to core clock ratio is fixed for each processor. Individual processors will only operate at their
specified system bus frequency, either 100MHz or 133 MHz. Table 13 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor core pin. The jitter
present must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer.
8. Not 100% tested. Specified by design characterization as a clock driver requirement.
9. The average period over a 1uS period of time must be greater than the minimum specified period.
10.This specification applies to the Pentium III processor with a system bus frequency of 100 MHz.
11.This specification applies to the Pentium III processor with a system bus frequency of 133 MHz.
Datasheet
31
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 13. Valid System Bus, Core Frequency, and Cache Bus Frequencies 1
Processor Core Frequency (MHz) BCLK Frequency (MHz) Frequency Multiplier L2 Cache (MHz)
450
500
450.00
500.00
533.33
533.33
550.00
550.00
600.00
600.00
600.00
600.00
650.00
666.67
700.00
733.33
750.00
800.00
800.00
100.00
100.00
133.33
133.33
100.00
100.00
100.00
133.33
100.00
133.33
100.00
133.33
100.00
133.33
100.00
100.00
133.33
9/2
5
225.00
250.00
266.66
533.33
275.00
550.00
300.00
300.00
600.00
600.00
650.00
666.67
700.00
733.33
750.00
800.00
800.00
533B
533EB
550
4
4
11/2
11/2
6
550E
600
600B
600E
600EB
650
9/2
6
9/2
13/2
5
667
700
7
733
11/2
15/2
8
750
800
800EB
6
NOTE:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins 1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
4, 10, 13
5, 11, 13
5, 11, 12, 14
-0.20
-0.14
-0.10
3.15
2.20
2.70
ns
ns
ns
8
8
8
T7: AGTL+ Output Valid Delay
1.90
1.20
1.20
ns
ns
ns
9
9
9
6, 7, 8, 11, 13
6, 7, 8, 12, 13
6, 7, 8, 11, 12, 14
T8: AGTL+ Input Setup Time
T9: AGTL+ Input Hold Time
0.85
0.58
0.80
ns
ns
ns
9
9
9
9, 11, 13
9, 12, 13
9, 11, 12, 14
T10: RESET# Pulse Width
1.00
ms
11
7, 10
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.
4. Valid delay timings for these signals are specified into 25Ω to 1.5 V and with VREF at 1.0 V.
5. Valid delay timings for these signals are specified into 50Ω to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchronous.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.This should be measured after VCC
11.This specification applies to the Pentium III processor with a system bus frequency of 100 MHz.
12.This specification applies to the Pentium III processor with a system bus frequency of 133 MHz.
13.This specification applies to the Pentium III processor with CPUID=067xh.
, VCC /VCC , and BCLK become stable.
CORE
L2 3.3
®
®
®
®
14.This specification applies to the Pentium III processor with CPUID=068xh.
32
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 15. System Bus AC Specifications (CMOS Signal Group) at the
Processor Core Pins 1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
Active and Inactive
states
2
BCLKs
BCLKs
8
T15: PWRGOOD Inactive Pulse Width
10
8, 11
5
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.7 V at the processor core
pins. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. When driven inactive or after VCC
, VCC /VCC , and BCLK become stable.
CORE
L2 3.3
Table 16. System Bus AC Specifications (Reset Conditions) 1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Setup Time
Before deassertion
of RESET#
4
BCLKs
10
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time
After clock that
deasserts RESET#
2
20
BCLKs
10
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
.
Table 17. System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Core Pins 1, 2, 3
T# Parameter
T21: PICCLK Frequency
Min
Max
Unit
Figure
Notes
2.0
33.3
MHz
ns
T22: PICCLK Period
30.0
12.0
12.0
0.25
0.25
500.0
7
7
7
7
7
T23: PICCLK High Time
T24: PICCLK Low Time
T25: PICCLK Rise Time
T26: PICCLK Fall Time
ns
ns
3.0
3.0
ns
ns
8.0
5.0
ns
ns
9
9
4 , 7
4, 8
T27: PICD[1:0] Setup Time
T28: PICD[1:0] Hold Time
2.5
1.5
1.5
1.5
ns
ns
ns
ns
9
8
8
8
4
T29: PICD[1:0] Valid Delay
10
8.7
4, 5, 6, 7
4, 5, 6, 8
4, 5, 6, 8
T29a: PICD[1:0] Valid Delay (Rising Edge)
T29b: PICD[1:0] Valid Delay (Falling Edge)
12.0
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
core pins. All APIC I/O signal timings are referenced at 1.25 V (CPUID 067xh) or 0.75 V (CPUID 068xh) at
the processor core pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into a 150Ω load pulled up to 2.5 V +5%.
®
7. This specification applies to the Pentium III processor with CPUID=067xh.
®
8. This specification applies to the Pentium III processor with CPUID=068xh.
Datasheet
33
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 18. System Bus AC Specifications (TAP Connection) at the Processor Core Pins 1, 2, 3
T# Parameter
T30: TCK Frequency
Min
Max
Unit
Figure
Notes
16.667
MHz
ns
T31: TCK Period
60.0
7
10, 11
25.0
25.0
n s
ns
7
7
@1.7 V
@V
T32: TCK High Time
10, 12
10, 12
+ 0.20 V
10, 11
REF
25.0
25.0
n s
ns
7
7
@0.7 V
@V
T33: TCK Low Time
T34: TCK Rise Time
– 0.20 V
REF
4, 10, 11
5.0
5.0
n s
ns
(0.7 V–1.7 V)
7
7
(V
(V
– 0.20 V) –
REF
REF
10, 12
+ 0.20 V)
4, 10
5.0
5.0
n s
ns
7
7
(1.7 V–0.7 V)
T35: TCK Fall Time
(V
(V
+ 0.20 V) –
REF
REF
10, 12
– 0.20 V)
10
T36: TRST# Pulse Width
40.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
12
12
12
12
12
12
12
12
Asynchronous
5
T37: TDI, TMS Setup Time
T38: TDI, TMS Hold Time
14.0
1.0
5
T39: TDO Valid Delay
10.0
25.0
25.0
25.0
6, 7
T40: TDO Float Delay
6, 7, 10
6, 8, 9
6, 8, 9, 10
5, 8, 9
5, 8, 9
T41: All Non-Test Outputs Valid Delay
T42: All Non-Test Inputs Setup Time
T43: All Non-Test Inputs Setup Time
T44: All Non-Test Inputs Hold Time
2.0
5.0
13.0
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 1.25 V (CPUID 067xh) or 0.75 V
(CPUID 068xh) at the processor core pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V
(CPUID 067xh) or 0.75 V (CPUID 068xh) at the processor core pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
®
11.This specification applies to the Pentium III processor with CPUID=067xh.
®
12.This specification applies to the Pentium III processor with CPUID=068xh.
34
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Note: For Figure 7 through Figure 13, the following apply:
1. Figure 7 through Figure 13 are to be used in conjunction with Table 12 through Table 18.
2. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK
rising edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor core pins.
Pentium III
Figure 7. BCLK, PICCLK, and TCK Generic Clock Waveform
th
tr
V3
V2
CLK
V1
tf
tl
tp
Tr
Tf
Th
Tl
=
=
=
=
=
T5, T25, T34, (Rise Time)
T6, T26, T35, (Fall Time)
T3, T23, T32, (High Time)
T4, T24, T33, (Low Time)
Tp
T1, T22, T31 (BCLK, TCK, PICCLK Period)
V1 = BCLK = 0.5V, PICCLK = 0.7V, and TCK = 0.7V (CPUID 067xh) or V
- 0.20V (CPUID 068xh)
V2 = BCLK = 1.25V, PICCLK = 1.25V and TCK = 1.25V (CPUID 067xh) or 0.R7E5FV (CPUID 068xh)
V3 = BCLK = 2.0V, PICCLK = 1.7V (CPUID 067xh) or 2.0V (CPUID 068xh),
TCK = 1.7V (CPUID 067xh) or V
- 0.20V (CPUID 068xh)
REF
Figure 8. System Bus Valid Delay Timings
CLK
Tx
Tx
Valid
Valid
V
Signal
Tpw
Tx
= T7, T29, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V
= 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or 0.75V (CPUID 068xh)
for APIC and TAP signal groups
Datasheet
35
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 9. System Bus Setup and Hold Timings
CLK
Th
Ts
V
Valid
Signal
Ts = T8, T27 (Setup Time)
Th = T9, T28 (Hold Time)
V
= 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or
0.75V (CPUID 068xh) for APIC and TAP signal groups
Figure 10. System Bus Reset and Configuration Timings
BCLK
Tu
Tt
RESET#
Tv
Tw
Tx
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
Valid
Tt = T9 (AGTL+ Input Hold Time)
Tu = T8 (AGTL+ Input Setup Time)
Tv = T10 (RESET# Pulse Width)
Tw = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
Tx = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
Figure 11. Power-On Reset and Configuration Timings
BCLK
Vccp ,
Vcc,
VREF
VIH,
min
P W R G O O D
RESET#
VIL,
max
Ta
Tb
Ta = T15 (PWRGOOD Inactive Pulse)
Tb = T10 (RESET# Pulse Width)
36
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 12. Test Timings (TAP Connection)
TCK
V
Tv
Tr
Tw
V
TDI, TMS
Ts
Input
Signal
Tx
Ty
Tu
Tz
T D O
Output
Signal
Tr = T43 (All Non-Test Inputs Setup Time)
Ts = T44 (All Non-Test Inputs Hold Time)
Tu = T40 (TDO Float Delay)
Tv = T37 (TDI, TMS Setup Time)
Tw = T38 (TDI, TMS Hold TIme)
Tx = T39 (TDO Valid Delay)
Ty = T41 (All Non-Test Outputs Valid Delay)
Tz = T42 (All Non-Test Outputs Float Time)
V
= 1.25V (CPUID 067xh) or 0.75V (CPUID 068xh)
Figure 13. Test Reset Timings
TRST#
V
Tq
Tq = T36 (TRST# Pulse Width)
= 1.25V (CPUID 067xh) or 0.75V (CPUID 068xh)
V
Datasheet
37
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
3.0
Signal Quality Specifications
Signals driven on the Pentium III processor system bus should meet signal quality specifications to
ensure that the components read data properly and to ensure that incoming signals do not affect the
long term reliability of the component. Specifications are provided for simulation and
measurement at the processor core; they should not be tested at the edge fingers.
The AGTL+ and non-AGTL+ signal quality specifications listed in this section apply to
Pentium III processors with CPUID=068xh. It is recommended that these specifications be used
with Pentium III processors with CPUID=067xh, however any deviations from these guidelines
must be verified with the specifications listed in the Pentium® II Processor Developer's Manual
(Order Number 243502).
3.1
BCLK, PICCLK, and PWRGOOD Signal Quality
Specifications and Measurement Guidelines
Table 19 describes the signal quality specifications at the processor core for the Pentium III
processor system bus clock (BCLK), APIC clock (PICCLK), and PWRGOOD signals. Figure 14
describes the signal quality waveform for the system bus clock at the processor core pins.
Table 19. BCLK, PICCLK, and PWRGOOD Signal Quality Specifications at the
Processor Core 1
V# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: V Absolute Voltage Range
–0.7
3.3
V
V
14
14
IN
V2: Rising Edge Ringback
V3: Falling Edge Ringback
NOTES:
2.0
2
0.5
0.7
V
V
14
14
2
3
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V (rising) or V (falling) voltage limits. This
IH
IL
specification is an absolute value.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the PICCLK signal can dip back to after passing the V (rising) or V (falling) voltage limits. This
IH
IL
specification is an absolute value.
Figure 14. BCLK and PICCLK Generic Clock Waveform
T3/T23
V3
V4
V2
V1
V5
V3
T6/T26
T5/T25
T4/T24
38
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
3.2
AGTL+ and Non-AGTL+ Overshoot/Undershoot
Specifications and Measurement Guidelines
Overshoot/Undershoot is the absolute value of the maximum voltage differential across the input
buffer relative termination voltage (VTT). The overshoot/undershoot guideline limits transitions
beyond VTT or VSS due to the fast signal edge rates. The processor can be damaged by repeated
overshoot/undershoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e., if
the overshoot/undershoot is great enough). Determining the impact of an overshoot/undershoot
condition requires knowledge of the Magnitude, the Pulse Duration, and the Activity Factor.
When performing simulations to determine impact of overshoot/undershoot, ESD diodes must be
properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot/undershoot protection. ESD diodes modeled within the Intel provided Pentium® III
Processor I/O Buffer Models do not clamp overshoot/undershoot and will yield correct simulation
results. If other I/O buffer models are being used to characterize Pentium® III processor
performance, care must be taken to ensure that ESD models do not clamp extreme voltage levels.
The Intel-provided Pentium® III Processor I/O Buffer Models also contains I/O capacitance
characterization. Therefore, removing the ESD diodes from the I/O buffer model will impact
results and may yield excessive overshoot/undershoot.
3.2.1
Overshoot/Undershoot Magnitude
Overshoot/Undershoot Magnitude describes the maximum potential difference between a signal
and its voltage reference level, VSS (overshoot) and VTT (undershoot). While overshoot can be
measured relative to VSS using one probe (probe to signal - GND lead to VSS), undershoot must be
measured relative to VTT. This could be accomplished by simultaneously measuring the VTT plane
while measuring the signal undershoot. The true waveform can then be calculated by the
oscilloscope itself or by the following oscilloscope date file analysis:
Converted Undershoot Waveform = VTT- Signal_measured
Note: The Converted Undershoot Waveform appears as a positive (overshoot) signal.
Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact
must be determined independently.
After the conversion, the Undershoot/Overshoot Specifications (Table 20 through Table 22) can be
applied to the Converted Undershoot Waveform using the same Magnitude and Pulse Duration
Specifications (Table 20 through Table 22) as with an overshoot waveform.
Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications
(Table 20 through Table 22). These specifications must not be violated at any time regardless of
bus activity or system state. Within these specifications are threshold levels that define different
allowed Pulse Durations. Provided that the magnitude of the overshoot/undershoot is within the
Absolute Maximum Specifications, the impact of the Overshoot/Undershoot Magnitude may be
determined based upon the Pulse Duration and Activity Factor.
Datasheet
39
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
3.2.2
Overshoot/Undershoot Pulse Duration
Overshoot/Undershoot Pulse duration describes the total time an overshoot/undershoot event
exceeds the Overshoot/Undershoot Reference Voltage (VOS_REF = 1.635 V). The total time could
encompass several oscillations above the Reference Voltage. Multiple overshoot/undershoot pulses
within a single overshoot/undershoot event may need to be measured to determine the total Pulse
Duration.
Note: Oscillations below the Reference Voltage can not be subtracted from the total Overshoot/
Undershoot Pulse Duration.
Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered
together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the
individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that
total event.
3.2.3
Overshoot/Undershoot Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other
clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY
OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot)
waveform occurs one time in every 200 clock cycles.
The Overshoot/Undershoot Specifications (Table 20 through Table 22) show the Maximum Pulse
Duration allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each
Table entry is independent of all others, meaning that the Pulse Duration reflects the existence of
Overshoot/Undershoot Events of that Magnitude ONLY. A platform with an overshoot/undershoot
that just meets the Pulse Duration for a specific Magnitude where the AF < 1, means that there can
be NO other Overshoot/Undershoot events, even of lesser Magnitude (note that if AF = 1, then the
event occurs at all times and no other events can occur).
Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact
must be determined independently.
Note: Activity factor for AGTL+ signals is referenced to BCLK frequency.
Note: Activity factor for CMOS signals is referenced to PICCLK frequency.
40
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
3.2.4
Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the Pentium III processor is not a simple single value.
Instead, many factors are needed to determine what the over/undershoot specification is. In
addition to the magnitude of the overshoot, the following parameters must also be known: the
width of the overshoot (as measured above 1.635 V) and the Activity Factor (AF). To determine
the allowed overshoot for a particular overshoot event, you must do the following:
1. Determine the signal group that particular signal falls into. If the signal is an AGTL+ signal
operating with a 100 MHz system bus, use Table 20. If the signal is an AGTL+ signal
operating with a 133 MHz system bus, use Table 21. If the signal is a CMOS signal, use
Table 22.
2. Determine the Magnitude of the overshoot (relative to VSS).
3. Determine the Activity Factor (how often does this overshoot occur?).
4. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)
allowed.
5. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse
Duration measured is less than the Pulse Duration shown in the table, then the signal meets the
specifications.
The above procedure is similar for undershoots after the undershoot waveform has been converted
to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events
as they are mutually exclusive.
Below is an example showing how the maximum pulse duration is determined for a given
waveform and how it relates to a measured value:
Platform Information:
• Signal Group = 133 MHz AGTL+
• Overshoot Magnitude (measured) = 2.3 V
• Pulse Duration (measured) = 1.6 ns
• Activity Factor (measured) = 0.1
Corresponding Maximum Pulse Duration Specification = 1.9 ns
Given the above parameters and using table 21 (AF = 0.1 column), the maximum allowed pulse
duration is 1.9 ns. Since the measured pulse duration is 1.6 ns, this particular overshoot event
passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/
undershoot events meet the specifications.
Datasheet
41
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
3.2.5
Determining if a System meets the Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications (Table 20 through Table 22) specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However, most systems will have
multiple overshoot and/or undershoot events that each have their own set of parameters
(magnitude, duration, and AF). While each overshoot on its own may meet the overshoot
specification, when you add the total impact of all overshoot events, the system may exceed the
specifications. A guideline to ensure a system passes the overshoot and undershoot specifications is
shown below.
1. Ensure no signal (AGTL+ or 1.5 V non-AGTL+) ever exceeds the 1.635 V
OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
specifications in the following tables. This means that whenever the over/undershoot event
occurs, it always over/undershoots to the same level.
OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magnitude and compare the results against the AF = 1 specifications
(note: multiple overshoot/undershoot events within one clock cycle must have their pulse
durations summed together to determine the total pulse duration). If all of these worst case
overshoot or undershoot events meet the specifications (measured time < specifications) in the
table where AF = 1, then the system passes.
Table 20. 100 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance 1, 2, 3, 4, 5
Maximum Pulse Duration
Overshoot/Undershoot
Unit
Figure
Magnitude
AF = 0.01
AF = 0.1
AF = 1
2.3 V
2.25 V
2.2 V
20
20
20
20
20
20
20
2.53
4.93
9.1
16.6
20
0.25
0.49
0.91
1.67
3.0
ns
ns
ns
ns
ns
ns
ns
15
15
15
15
15
15
15
2.15 V
2.1 V
2.05 V
2.0 V
20
5.5
20
10
NOTES:
1. BCLK period is 10 ns.
2. These values are specified at the processor core pins.
3. Overshoot/Undershoot Magnitude = 2.3 V is an absolute value and should never be exceeded.
4. Overshoot is measured relative to VSS, while undershoot is measured relative to VTT.
5. Overshoot/Undershoot Pulse Duration is measured relative to 1.635 V.
42
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 21. 133 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance 1, 2, 3, 4, 5
Maximum Pulse Duration
Overshoot/Undershoot
Unit
Figure
Magnitude
AF = 0.01
AF = 0.1
AF = 1
2.3 V
2.25 V
2.2 V
15
15
15
15
15
15
15
1.9
3.7
6.8
12.5
15
0.19
0.37
0.68
1.25
2.28
4.1
ns
ns
ns
ns
ns
ns
ns
15
15
15
15
15
15
15
2.15 V
2.1 V
2.05 V
2.0 V
15
15
7.5
NOTES:
1. BCLK period is 7.5 ns.
2. These values are specified at the processor core pins.
3. Overshoot/Undershoot Magnitude = 2.3 V is an absolute value and should never be exceeded.
4. Overshoot is measured relative to VSS, while undershoot is measured relative to VTT.
5. Overshoot/Undershoot Pulse Duration is measured relative to 1.635 V.
Table 22. 33 MHz Non-AGTL+ Signal Group Overshoot/Undershoot Tolerance 1, 2, 3, 4, 5, 6
Maximum Pulse Duration
Overshoot/Undershoot
Unit
Figure
Magnitude
AF = 0.01
AF = 0.1
AF = 1
2.3 V
2.25 V
2.2 V
60
60
60
60
60
60
60
7.6
14.8
27.2
50
0.76
1.48
2.7
5
ns
ns
ns
ns
ns
ns
ns
15
15
15
15
15
15
15
2.15 V
2.1 V
60
9.1
16.4
30
2.05 V
2.0 V
60
60
NOTES:
1. PICCLK period is 30 ns.
2. This table applies to all 1.5 V tolerant non-AGTL+ signals. BCLK, PICCLK, and PWRGOOD are the only non-
AGTL+ signals that are 2.5 V tolerant at the processor core pins.
3. These values are specified at the processor core pins.
4. Overshoot/Undershoot Magnitude = 2.3 V is an absolute value and should never be exceeded.
5. Overshoot is measured relative to VSS, while undershoot is measured relative to VTT.
6. Overshoot/Undershoot Pulse Duration is measured relative to 1.635 V.
Datasheet
43
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 15. Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot Waveform
Time Dependent
Overshoot
Converted Undershoot
Waveform
Max
2.3V
2.2V
2.1V
2.0V
1.635V
VTT
Overshoot
Magnitude
Undershoot
Magnitude
Vss
Overshoot
Magnitude
=
Signal - Vss
VTT - Signal
Undershoot
Magnitude
=
Time Dependent
Undershoot
3.3
AGTL+ and Non-AGTL+ Ringback Specifications and
Measurement Guidelines
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. (See Figure 16 for an illustration of ringback.) Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for both AGTL+ and non-AGTL+ signals.
When performing simulations to determine the impact of ringback, ESD diodes must be properly
characterized. The Intel provided Pentium III Processor I/O Buffer Models contain I/O capacitance
characterization. Therefore, removing the ESD diodes from the I/O buffer model will impact
results and may yield incorrect ringback. If other I/O buffer models are being used to characterize
Pentium III processor performance, care must be taken to ensure that ESD models account for the
I/O capacitance. See Table 24 for the signal ringback specifications for both AGTL+ and
non-AGTL+ signals for simulations at the processor core.
44
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 23. Signal Ringback Specifications for Signal Simulation 1
Maximum Ringback
Input Signal Group
AGTL+
Transition
(with Input Diodes Present)
Unit
Figure
0 → 1
1 → 0
0 → 1
1 → 0
0 → 1
V
+ 0.200
- 0.200
V
V
V
V
V
16
16
16
16
16
REF
AGTL+
V
REF
2
2
Non-AGTL+ Signals
Non-AGTL+ Signals
PWRGOOD
1.7
0.7
2.00
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies and
cache sizes.
2. Non-AGTL+ signals except PWRGOOD.
There are three signal quality parameters defined for both AGTL+ and non-AGTL+ signals:
overshoot/undershoot, ringback, and settling limit. All three signal quality parameters are shown in
Table 24 for the AGTL+ and non-AGTL+ signal group.
Table 24. AGTL+ and Non-AGTL+ Signal Groups Ringback Tolerance Specifications 1, 2, 3, 4
T# Parameter
Min
Unit
Figure
Notes
4, 8
α
α
: Overshoot
100
0.50
–200
200
mV
ns
14
14
14
14
14
τ
τ
: Minimum Time at High
ρ
ρ
: Amplitude of Ringback
mV
mV
ns
5, 6, 7, 8
8
φ
φ
: Final Settling Voltage
δ
δ
: Duration of Squarewave Ringback
N/A
NOTES:
®
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies and
cache sizes.
2. These values are specified at the processor core pins.
V
3. Specifications are for the edge rate of 0.3 - 0.8
/ . See Figure 16 for the generic waveform.
ns
4. Please see Table 22 for maximum allowable overshoot.
5. Ringback between V + 100 mV and V + 200 mV or V
–200 mV and V – 100 mV requires the
REF
REF
REF
REF
®
flight time measurements to be adjusted as described in the AGTL+ Specification (Pentium II Developers
Manual). Ringback below V + 100mV or above V – 100 mV is not supported.
REF
REF
6. Intel recommends simulations not exceed a ringback value of V
sources of system noise.
± 200 mV to allow margin for other
REF
7. A negative value for ρρ indicates that the amplitude of ringback is above V
. (i.e., f = -100 mV specifies the
REF
signal cannot ringback below V
+ 100 mV).
REF
8. φφ and ρρ: are measured relative to V
. αα: is measured relative to V
+ 200 mV.
REF
REF
Datasheet
45
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 16. Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance
τ
α
VREF + 0.2
φ
VREF
ρ
VREF - 0.2
δ
0.7V Clk Ref
Vstart
Clock
Time
Note: High to low case is analogous
Figure 17. Signal Overshoot/Undershoot, Settling Limit, and Ringback 1
Settling Limit
Overshoot
V
HI
Rising-Edge
Ringback
Falling-Edge
Ringback
Settling Limit
V
LO
V
SS
Time
Undershoot
3.3.1
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10 percent of the total signal swing (VHI - VLO
)
above and below its final value. A signal should be within the settling limits of its final value, when
either in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
46
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
4.0
Thermal Specifications and Design Considerations
Limited quantities of Pentium III processors utilize S.E.C.C. package technology. This technology
uses an extended thermal plate for heatsink attachment. The extended thermal plate interface is
intended to provide accessibility for multiple types of thermal solutions. The majority of SC242-
based Pentium III processors use S.E.C.C.2 packaging technology. S.E.C.C.2 package technology
does not incorporate an extended thermal plate.
This chapter provides needed data for designing a thermal solution. However, for the correct
thermal measuring processes please refer to AP-905, Pentium® III Processor Thermal Design
Guidelines (Order Number 245087).
Figure 18 provides a 3-dimensional view of an S.E.C.C. package. This figure illustrates the thermal
plate location. Figure 19 provides a substrate view of an S.E.C.C.2 package.
Figure 18. S.E.C.Cartridge — 3-Dimensional View
Left Latch
Cover
Right Latch
Extended Thermal Plate
Datasheet
47
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 19. S.E.C.Cartridge 2 — Substrate View
OLGA Package
L2 Cache
(CPUID 067xh Only
Substrate View
4.1
Thermal Specifications
Table 25 and Table 26 provide the thermal design power dissipation and maximum and minimum
temperatures for Pentium III processors with S.E.C.C. and S.E.C.C.2 package technologies
respectively. While the processor core dissipates the majority of the thermal power, thermal power
dissipated by the L2 cache also impacts the overall processor power specification. This total
thermal power is referred to as processor power in the following specifications. Systems should
design for the highest possible processor power, even if a processor with a lower thermal
dissipation is planned.
Table 25. Thermal Specifications for S.E.C.C. Packaged Processors 1
Extended
Processor
L2 Cache Processor
Thermal
Plate Power
(W)
Min
Max
Min
Max
Core
Frequency
(MHz)
2
3
Size
(KBs)
Power
(W)
T
T
T
T
PLATE
(°C)
PLATE
(°C)
COVER
(°C)
COVER
(°C)
450
500
512
512
25.3
28.0
25.5
28.2
5
5
70
70
5
5
75
75
NOTES:
1. These values are specified at nominal VCC
for the processor core and nominal VCC /VCC for the L2
L2 3.3
CORE
cache (if applicable).
2. Processor power includes the power dissipated by the processor core, the L2 cache, and the AGTL + bus
termination. The maximum power for each of these components does not occur simultaneously.
3. Extended Thermal Plate power is the processor power that is dissipated through the extended thermal plate.
48
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 26. Thermal Specifications for S.E.C.C.2 Packaged Processors1
Proc.
Core
Freq.
(MHz)
L2
Proc.
Core
Power
(W)
L2
Proc.
Power
(W)
Power
Max
JUNCTION
(°C)
T
L2 Cache
Min T
L2 Cache
Max T
Min
COVER
(°C)
Max
COVER
(°C)
JUNCTION
3
Cache
Size
Cache
Power
(W)
2
4
Density
T
Offset
T
T
CASE
CASE
2
(W/cm )
(°C)
(°C)
(°C)
(Kbytes)
5
450
500
512
512
512
256
512
256
512
512
256
256
256
256
256
256
256
256
256
25.3
28.0
29.7
17.6
30.8
18.2
34.5
34.5
19.8
19.8
21.5
22.0
23.1
24.1
24.7
26.4
26.4
25.3
28.0
29.7
17.4
30.8
18.0
34.5
34.5
19.6
19.6
21.3
21.8
22.9
23.9
24.5
26.2
26.2
1.26
1.33
1.37
N/A
1.37
N/A
1.60
1.60
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
21.6
90
90
90
82
80
82
85
85
82
82
82
82
80
80
80
80
80
4.8
4.8
4.8
5
105
105
105
N/A
105
N/A
105
105
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
5
23.9
5
5
533B
533EB
550
25.4
5
6
7
24.2
2.6
N/A
5
5
26.3
4.8
6
7
550E
600
25.1
2.6
N/A
5
5
29.5
4.8
4.8
5
600B
600E
600EB
650
29.5
5
6
7
27.3
2.9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6
7
27.3
2.9
6
7
29.5
3.1
6
7
667
30.5
3.2
6
7
700
31.8
3.3
6
7
733
33.2
3.5
6
7
750
34.0
3.7
6
7
800
36.4
3.8
6
7
800EB
36.4
3.8
NOTES:
1. These values are specified at nominal VCC
for the processor core and nominal VCC /VCC for the L2
L2 3.3
CORE
cache (if applicable).
2. Processor power includes the power dissipated by the processor core, the L2 cache, and the AGTL + bus
termination. The maximum power for each of these components does not occur simultaneously.
3. T
is the worst-case difference between the thermal reading from the on-die thermal diode
JUNCTIONOFFSET
and the hottest location on the processor’s core.
4. Power density is the maximum power the processor die can dissipate (i.e. processor power) divided by the
die area over which the power is generated.
5. Power for these processors is generated over the entire processor die (see Figure 40 for processor die
dimensions).
6. Power for these processors is generated over the core area (see Figure 20 for processor die and core area
dimensions). Thermal solution designs should compensate for this smaller heat flux area (core) and not
assume that the power is uniformly distributed across the entire die area (core + cache).
7. TJUNCTION offset values do not include any thermal diode kit measurement error. Diode kit measurement
®
®
error must be added to the TJUNCTION offset value from the table, as outlined in the Intel Pentium III
processor Thermal Metrology for CPUID-068h Family Processors. Intel has characterized the use of the
Analog Devices AD1021 diode measurement kit and found its measurement error to be 1 °C.
Figure 20. Processor Functional Die Layout (CPUID 068xh)
0.362”
0.292”
Die Area = 1.05 cm2
Cache Area
Cache Area = 0.32 cm2
Core Area = 0.73 cm2
Die Area
0.16 in2
0.05 in2
0.170”
0.448”
Core Area
0.11 in2
Datasheet
49
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
For S.E.C.C. packaged processors, the extended thermal plate is the attach location for all thermal
solutions. The maximum and minimum extended thermal plate temperatures are specified in
Table 25. For S.E.C.C.2 packaged processors, thermal solutions attach to the processor by
connecting through the substrate to the cover. The maximum and minimum temperatures of the
pertinent locations are specified in Table 26. A thermal solution should be designed to ensure the
temperature of the specified locations never exceeds these temperatures.
The total processor power is a result of heat dissipated by the processor core and L2 cache. The
overall system chassis thermal design must comprehend the entire processor power. In S.E.C.C.
packaged processors, the extended thermal plate power is a component of this power, and is
primarily composed of the processor core and the L2 cache dissipating heat through the extended
thermal plate. The heatsink need only be designed to dissipate the extended thermal plate power.
See Table 25 for current Pentium III processor S.E.C.C. thermal design specifications.
No extended thermal plate exists for S.E.C.C.2 packaged processors, so thermal solutions have to
attach directly to the processor core package. The total processor power dissipated by an S.E.C.C.2
processor is a combination of heat dissipated by both the processor core and L2 cache. Pentium III
processors that use a “Discrete” L2 cache have a separate TCASE specification (Table 26) for the
surface mounted BSRAM components on the substrate. TJUNCTION encompasses the L2 cache for
processors that utilize the “Advanced Transfer Cache”, therefore no separate cache measurement is
required.
Specifics on how to measure these specifications are outlined in AP-905, Pentium® III Processor
Thermal Design Guidelines (Order Number 245087).
4.1.1
Thermal Diode
The Pentium III processor incorporates an on-die diode that may be used to monitor the die
temperature (junction temperature). A thermal sensor located on the baseboard, or a stand-alone
measurement kit, may monitor the die temperature of the Pentium III processor for thermal
management or instrumentation purposes. Table 27 and Table 28 provide the diode parameter and
interface specifications.
Table 27. Thermal Diode Parameters1
Symbol
Min
Typ
Max
Unit
Notes
I
5
500
uA
1
forward bias
1.0000
1.0057
1.0065
1.0080
1.0173
1.0125
2, 3, 4
2, 3, 5
n_ideality
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. At room temperature with a forward bias of 630 mV.
3. n_ideality is the diode ideality factor parameter, as represented by the diode equation:
I=Io(e (Vd*q)/(nkT) - 1).
®
4. This specification applies to the Pentium III processor with CPUID=067xh.
®
5. This specification applies to the Pentium III processor with CPUID=068xh.
Table 28. Thermal Diode Interface
Pin Name
SC 242 Connector Signal #
Pin Description
THERMDP
THERMDN
B14
B15
diode anode (p_junction)
diode cathode (n_junction)
50
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
5.0
S.E.C.C. and S.E.C.C.2 Mechanical Specifications
Intel® Pentium® III processors use either S.E.C.C. or S.E.C.C.2 package technology. Both package
types contain the processor core, L2 cache, and other passive components. The cartridges connect
to the baseboard through an edge connector. Mechanical specifications for the processor are given
in this section. See Section 1.1.1 for a complete terminology listing.
5.1
S.E.C.C. Mechanical Specifications
S.E.C.C. package drawings and dimension details are provided in Figure 21 through Figure 30.
Figure 21 shows multiple views of the Pentium III processor in an S.E.C.C. package; Figure 22
through Figure 25 show the package dimensions; Figure 26 and Figure 27 show the extended
thermal plate dimensions; and Figure 28 and Figure 29 provide details of the processor substrate
edge finger contacts. Figure 30 and Table 29 contain processor marking information. See
Section 5.2 for S.E.C.C.2 mechanical specifications.
The processor edge connector defined in this document is referred to as the “SC242 connector.”
See the Slot 1 Connector Specification (Order Number 243397) for further details on the SC242
connector.
Note: For Figure 21 through Figure 43, the following apply:
1. Unless otherwise specified, the following drawings are dimensioned in inches.
2. All dimensions provided with tolerances are guaranteed to be met for all normal production
product.
3. Figures and drawings labeled as “Reference Dimensions” are provided for informational
purposes only. Reference Dimensions are extracted from the mechanical design database and
are nominal dimensions with no tolerance information applied. Reference Dimensions are
NOT checked as part of the processor manufacturing. Unless noted as such, dimensions in
parentheses without tolerances are Reference Dimensions.
4. Drawings are not to scale.
Figure 21. S.E.C.C. Packaged Processor — Multiple Views
Top View
Thermal
Plate
Left Latch
Right Latch
Cover
Right
Side
Thermal Plate
Side View
Left
Cover Side view
Right
Right
Left
Datasheet
51
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 22. S.E.C.C. Packaged Processor — Extended Thermal Plate Side Dimensions
3.805±.020
(0.750)
(1.500)
2.473±.016
2.070±.020
1.235±.020
2X .125±.005
2X .342±.005
These dimensions are from the bottom
of the substrate edge fingers
2X .365±.005
1.745±.005
1.877±.020
Figure 23. S.E.C.C. Packaged Processor — Bottom View Dimensions
5.255±.006
Cover
Thermal Plate
2.181±.015
3.243±.015
5.341±.010
5.505±.010
52
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 24. S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,
and Cover Lug Dimensions
2X 0.238
2X0.103
2X 0.174 ±0.005
±0.005
2X 0.647
±0.020
2X 0.488
±0.020
Left
2X 0.058
±0.005
2X 0.136
0.005
±
2X 0.253
Datasheet
53
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 25. S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,
and Cover Detail Dimensions (Reference Dimensions Only)
0.075
0.236
0.122
0.113
0.084
Detail A
Detail B
(Bottom Side View)
0.120 Min.
0.316
0.116
0.082
0.216
0.291
0.276
45°
Detail C
Detail D
Detail E
Note: All dimensions without tolerance information
are considered reference dimensions only
54
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 26. S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions
Datasheet
55
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 27. S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions, Continued
0.0032
/
1.000
x
1.000
1.250
2.500
Figure 28. S.E.C.C. Packaged Processor Substrate — Edge Finger Contact Dimensions
Thermal Plate
Cover
Pin A1
70°
Pin A121
.045
Y
Substrate
See Detail A in
+.007
.062
Next Figure
1.85
-.005
2.835
Z
W
2.992
2.01
5.000
X
NOTE:
All dimensions without tolerance information are
considered reference dimensions only.
56
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 29. S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions, Detail A
.098
.098
Pin A74
Pin A73
.010
.008
.360
.045
.236
.138 ±.005
Y
.039
.074 ±.002
121 X 0.16 ±.002
W
121 X 0.043 ±.002
.008
.002
Z W
Z
.008
.002
Z W
Z
.037
NOTE:
1. All dimensions without tolerance information are considered reference dimensions only.
Figure 30. Intel® Pentium® III Processor Markings (S.E.C.C. Packaged Processor)
see note
Note: Please refer to the
Intel® Pentium® III Processor
Specification Update for this
information
Hologram
Loation
Pentium®
!!!
Datasheet
57
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 29. Description Table for Processor Markings (S.E.C.C. Packaged Processor)
Code Letter
Description
A
C
D
E
F
Logo
Trademark
Logo
Product Name
Dynamic Mark Area – with 2-D matrix
5.2
S.E.C.C.2 Mechanical Specification
S.E.C.C.2 drawings and dimension details are provided in Figure 31 through Figure 43. Figure 31
shows multiple views of the Pentium III processor in an S.E.C.C.2 package; Figure 32 through
Figure 36 show an S.E.C.C.2 package dimensions; Figure 37 and Figure 38 provide dimensions of
the processor substrate edge finger contacts; Figure 39 shows the heatsink solution keep-in zone;
Figure 41 shows multiple views of an S.E.C.C.2 packaged processor keep-out zone; and Figure 43
and Table contain processor marking information. See Section 5.1 for S.E.C.C. Mechanical
Specifications.
Figure 31. S.E.C.C.2 Packaged Processor — Multiple Views
Top View
Cover
OLGA Package
L2 Cache
(CPUID 067xh Only
Pentium®
!!!
Substrate View
Right Side
View
Cover Side View
58
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 32. S.E.C.C.2 Packaged Processor Assembly — Primary View
L2 Cache
(CPUID 067xh Only
PLGA
0.725 ±0.13 0.954 ±0.13
CPUID 067xh
CPUID 068xh 0.685 ±0.13 0.954 ±0.13
Figure 33. S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions
OLGA
+.015
-.012
CPUID 067xh = .021
+.015
-.012
CPUID 068xh = .017
4.918 ±0.006
1.849 ±0.010
0.615 ±0.013
2.440 ±0.005
1.546
±0.013
5.000 ±0.016
Datasheet
59
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 34. S.E.C.C.2 Packaged Processor Assembly — Heat Sink Attach Boss Section
φ
0.112 ±0.001
φ
0.005
φ
0.025 ±0.001
Substrate
0.100
+0.007
-0.005
0.283
0.062
0.020 ±0.010
0.154
5.0°
Cover
82.0°
Dimensions in inches
Figure 35. S.E.C.C.2 Packaged Processor Assembly — Side View
OLGA
CPUID 067xh = 0.094" ±0.005"
CPUID 068xh = 0.090" ±0.005"
Core Package
TQFP BS RAM
Package
(067xh)
0.129 ±0.025
0.061 ±0.005
0.365 ±0.025
Z
See Figure 36
Y
Dimensions in inches
Figure 36. Detail View of Cover in the Vicinity of the Substrate Attach Features
0.075
-Z-
0.280
0.340
Dimensions in inches
60
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 37. S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact Dimensions
+.007
.062
.045
-.005
Figure 38. S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
Dimensions (Detail A)
Pin A74
Pin A73
.010
.008
.360
.045
.236
.138 ±.005
.039
Y
.074 ±.002
121 X 0.16 ±.002
W
121 X 0.043 ±.002
.008
.002
Z W
Z
.008
.002
Z W
Z
.037
NOTE:
1. All dimensions without tolerance information are considered reference dimensions only.
Datasheet
61
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 39. S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) — Keep In Zones
PRIMARY SIDE
.448
NON-KEEPOUT AREA
.0275 TYP MAX
NON-KEEPOUT AREA
.405
Figure 40. S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) — Keep In Zones
PRIMARY SIDE
..632
NON-KEEPOUT AREA
.0275 TYP MAX
NON-KEEPOUT AREA
0.448
62
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 41. S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) — Keep-Out Zone
Keep Out Zone (Bottom Side View)
Figure 42. S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) — Keep-Out Zone
Keep Out Zone (Front Side View)
.362
.44
.448
Keep Out Zone (Bottom Side View)
Datasheet
63
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 43. Intel® Pentium® III Processor Markings (S.E.C.C.2 Package)
Keep Out Zone (Front Side View)
F
See N ote
D
C
Dynamic Mark Area
A
NOTE:
®
Please refer to the Pentium III
Processor Specification Update
for this information.
Hologram
Location
Pentium®
!!!
Table 30. Description Table for Processor Markings (S.E.C.C.2 Packaged Processor)
Code Letter
Description
A
C
D
F
Logo
Trademark
Logo
Dynamic Mark Area – with 2-D matrix
5.3
S.E.C.C.2 Structural Mechanical Specification
The intention of the structural specification for S.E.C.C.2 is to ensure that the package will not be
exposed to excessive stresses that could adversely affect device reliability. Figure 44 illustrates the
deflection specification for deflections away from the heatsink. Figure 45 illustrates the deflection
specification in the direction of the heatsink.
The heatsink attach solution must not induce permanent stress into the S.E.C.C.2 substrate with the
exception of a uniform load to maintain the heatsink to the processor thermal interface. Figure 46
and Table 31 define the pressure specification.
Figure 44. Substrate Deflection Away From Heat Sink
Processor Substrate
0.025
64
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 45. Substrate Deflection Toward the Heatsink
.160 in. max. deflection
0.050
Processor Substrate
Figure 46. S.E.C.C.2 Packaged Processor Specifications
.080 in. max. deflection
F
Table 31. S.E.C.C.2 Pressure Specifications
Parameter
Maximum
Unit
Figure
46
Notes
Static Compressive Force
20
lbf
1
100
75
lbf
lbf
46
46
2
3
Transient Compressive Force
NOTES:
1. This is the maximum static force that can be applied by the heatsink to maintain the heatsink and processor
interface.
2. This specification applies to a uniform load.
3. This specification applies to a nonuniform load.
Datasheet
65
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
5.4
Processor Package Materials Information
Both the S.E.C.C. and S.E.C.C.2 processor packages are comprised of multiple pieces to make the
complete assembly. This section provides the weight of each piece and the entire package. Table 32
and Table 33 contain piece-part information of the S.E.C.C. and S.E.C.C.2 processor packages,
respectively.
Table 32. S.E.C.C. Materials
S.E.C.C. Piece
Piece Material
Maximum Piece Weight (Grams)
Extended Thermal Plate
Latch Arms
Aluminum 6063-T6
GE Lexan 940-V0, 30% glass filled
GE Lexan 940-V0
84.0
Less than 2.0 per latch arm
Cover
24.0
®
Total Pentium III Processor
112.0
Table 33. S.E.C.C.2 Materials
S.E.C.C.2 Piece
Piece Material
Maximum Piece Weight (Grams)
Cover
GE Lexan 940-V0
18.0
54.0
®
Total Pentium III Processor
®
®
5.5
Intel Pentium III Processor Signal Listing
Table 34 and Table 35 provide the processor edge finger signal definitions. The signal locations on
the SC242 edge connector are to be used for signal routing, simulation, and component placement
on the baseboard.
Table 34 is the Pentium III processor substrate edge finger listing in order by pin number.
66
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 34. Signal Listing in Order by Pin Number (Sheet 1 of 4)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
Power/Other
A1
VTT
Power/Other
B1
EMI
A2
GND
Power/Other
Power/Other
CMOS Output
CMOS Input
Power/Other
CMOS Output
CMOS Input
TAP Input
B2
FLUSH#
SMI#
CMOS Input
CMOS Input
CMOS Input
Power/Other
CMOS Input
TAP Input
A3
VTT
B3
A4
IERR#
A20M#
GND
B4
INIT#
A5
B5
VTT
A6
B6
STPCLK#
TCK
A7
FERR#
IGNNE#
TDI
B7
A8
B8
SLP#
CMOS Input
Power/Other
TAP Input
A9
B9
VTT
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
GND
Power/Other
TAP Output
CMOS Input
Power/Other
Power/Other
CMOS Output
Power/Other
CMOS Input
Power/Other
APIC I/O
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
TMS
TDO
TRST#
Reserved
TAP Input
PWRGOOD
TESTHI
BSEL1
THERMTRIP#
Reserved
LINT0/INTR
GND
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Input
Power/Other
APIC Clock
AGTL+ I/O
Power/Other
Power/Other
APIC I/O
VCC
CORE
THERMDP
THERMDN
LINT1/NMI
VCC
CORE
PICCLK
BP2#
PICD0
PREQ#
BP3#
CMOS Input
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Reserved
BSEL0
PICD1
GND
BPM0#
BINIT#
DEP0#
GND
PRDY#
BPM1#
AGTL+ Output
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
VCC
CORE
DEP2#
DEP4#
DEP7#
DEP1#
DEP3#
DEP5#
GND
VCC
CORE
D62#
D58#
D63#
DEP6#
D61#
D55#
VCC
CORE
GND
D56#
D50#
D54#
D60#
D53#
D57#
VCC
CORE
Datasheet
67
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 34. Signal Listing in Order by Pin Number (Sheet 2 of 4)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
AGTL+ I/O
A38
GND
Power/Other
B38
D59#
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
D46#
D49#
D51#
GND
D42#
D45#
D39#
GND
Reserved
D43#
D37#
GND
D33#
D35#
D31#
GND
D30#
D27#
D24#
GND
D23#
D21#
D16#
GND
D13#
D11#
D10#
GND
D14#
D9#
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
AGTL+I/O
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
D48#
D52#
EMI
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ Input
AGTL+ Input
D41#
D47#
D44#
VCC
CORE
D36#
D40#
D34#
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
System Bus
VCC
CORE
D38#
D32#
D28#
VCC
CORE
D29#
D26#
D25#
VCC
CORE
D22#
D19#
D18#
EMI
D20#
D17#
D15#
VCC
CORE
D12#
D7#
D6#
D8#
VCC
D4#
D2#
D0#
VCC
CORE
GND
D5#
D3#
D1#
CORE
GND
BCLK
RESET#
BR1#
68
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 34. Signal Listing in Order by Pin Number (Sheet 3 of 4)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Reserved
Signal Group
Power/Other.
A76
BR0#
AGTL+I/O
B76
A77
BERR#
GND
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
Power/Other
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ Input
AGTL+ Input
AGTL+ Input
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ Input
Power/Other
B77
VCC
CORE
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ Input
Power/Other
AGTL+ I/O
AGTL+ Input
Power/Other
Power/Other
A78
B78
A35#
A32#
A29#
EMI
A79
A33#
B79
A80
A34#
B80
A81
A30#
B81
A82
GND
B82
A26#
A24#
A28#
A83
A31#
B83
A84
A27#
B84
A85
A22#
B85
VCC
CORE
A86
GND
B86
A20#
A21#
A25#
A87
A23#
B87
A88
Reserved
A19#
B88
A89
B89
VCC
CORE
A90
GND
B90
A15#
A17#
A11#
A91
A18#
B91
A92
A16#
B92
A93
A13#
B93
VCC
CORE
A94
GND
B94
A12#
A8#
A95
A14#
B95
A96
A10#
B96
A7#
A97
A5#
B97
VCC
A3#
A6#
EMI
CORE
A98
GND
B98
A99
A9#
B99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
A111
A112
A113
A4#
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
B111
B112
B113
BNR#
GND
SLOTOCC#
REQ0#
BPRI#
TRDY#
DEFER#
GND
REQ1#
REQ4#
VCC
CORE
LOCK#
DRDY#
RS0#
REQ2#
REQ3#
HITM#
GND
VCC
5
HIT#
DBSY#
RS1#
Reserved
RS2#
Reserved
VCC /VCC
L2 3.3
Datasheet
69
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 34. Signal Listing in Order by Pin Number (Sheet 4 of 4)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
AGTL+ I/O
A114
A115
A116
A117
A118
A119
A120
A121
GND
Power/Other
B114
B115
B116
B117
B118
B119
B120
B121
RP#
ADS#
Reserved
AP0#
GND
AGTL+ I/O
RSP#
AP1#
AGTL+ Input
AGTL+ I/O
Power/Other
AGTL+ I/O
VCC /VCC
L2
Power/Other
AGTL+ I/O
3.3
3.3
Power/Other
Power/Other
Power/Other
Power/Other
AERR#
VID3
VID2
Power/Other
Power/Other
Power/Other
VID1
VID0
VID4
VCC /VCC
L2
Table 35 is the Pentium III processor substrate edge connector listing in order by signal name.
70
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 35. Signal Listing in Order by
Signal Name (Sheet 1 of 8)
Table 35. Signal Listing in Order by
Signal Name (Sheet 2 of 8)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
B98
A3#
AGTL+ I/O
B116
A75
A77
A24
A101
B19
A21
A23
B24
A103
A76
B75
B21
A14
B72
A73
B71
A72
B70
A71
B68
B67
A69
A68
A65
A64
B66
A63
A67
B64
A61
B63
B60
B59
B62
A60
B58
AP1#
AGTL+ I/O
A100
A97
B99
B96
B95
A99
A96
B92
B94
A93
A95
B90
A92
B91
A91
A89
B86
A5
A4#
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
CMOS Input
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
BCLK
BERR#
BINIT#
BNR#
BP2#
BP3#
BPM0#
BPM1#
BPRI#
BR0#
BR1#
BSEL0
BSEL1
D0#
System Bus
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ Input
AGTL+I/O
AGTL+ Input
Power/Other
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADS#
AERR#
AP0#
D1#
D2#
D3#
D4#
B87
A85
A87
B83
B88
B82
A84
B84
B80
A81
A83
B79
A79
A80
B78
A115
B118
A117
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
Datasheet
71
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 35. Signal Listing in Order by
Signal Name (Sheet 3 of 8)
Table 35. Signal Listing in Order by
Signal Name (Sheet 4 of 8)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
A59
D23#
AGTL+ I/O
A35
D60#
AGTL+ I/O
A57
B56
B55
A56
B52
B54
A55
A53
B51
A51
B48
A52
B46
A49
B50
A45
B47
B42
A43
A48
B44
A44
A39
B43
B39
A40
B35
A41
B40
A36
B36
A33
B34
A37
B31
B38
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
A32
B30
B32
A111
A105
A25
A27
B26
A28
B27
A29
A31
B28
B107
B1
D61#
D62#
D63#
DBSY#
DEFER#
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
DRDY#
EMI
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ Input
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS Output
CMOS Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B41
B61
B81
B100
A7
EMI
EMI
EMI
EMI
FERR#
FLUSH#
GND
B2
A2
A6
GND
A10
A18
A22
A26
A30
A34
A38
A42
A46
A50
A54
A58
A62
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
72
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 35. Signal Listing in Order by
Signal Name (Sheet 5 of 8)
Table 35. Signal Listing in Order by
Signal Name (Sheet 6 of 8)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
A66
GND
Power/Other
A116
B12
B20
B76
B112
B74
B114
B108
A112
B111
B115
B101
B8
Reserved
Power/Other
A70
A74
A78
A82
A86
A90
A94
A98
A102
A106
A110
A114
A118
B110
A109
A4
GND
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AGTL+ I/O
Reserved
Reserved
Reserved
Reserved
RESET#
RP#
Power/Other
Power/Other
Power/Other.
Power/Other
AGTL+ Input
AGTL+ I/O
GND
GND
GND
GND
GND
GND
RS0#
AGTL+ Input
AGTL+ Input
AGTL+ Input
AGTL+ Input
Power/Other
CMOS Input
CMOS Input
CMOS Input
TAP Input
GND
RS1#
GND
RS2#
GND
RSP#
GND
SLOTOCC#
SLP#
GND
GND
B3
SMI#
HIT#
B6
STPCLK#
TCK
HITM#
IERR#
IGNNE#
INIT#
AGTL+ I/O
B7
CMOS Output
CMOS Input
CMOS Input
CMOS Input
CMOS Input
AGTL+ I/O
A9
TDI
TAP Input
A8
A11
A13
B15
B14
A15
B10
A104
B11
B109
B13
B17
B25
B29
B33
B37
B45
B49
B53
B57
B65
TDO
TAP Output
Power/Other
Power/Other
Power/Other
CMOS Output
TAP Input
B4
TESTHI
THERMDN
THERMDP
THERMTRIP#
TMS
A17
B16
B106
B18
A19
B22
B23
A20
A12
B102
B103
A107
A108
B104
A16
A47
A88
A113
LINT0/INTR
LINT1/NMI
LOCK#
PICCLK
PICD0
PICD1
PRDY#
PREQ#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
Reserved
Reserved
Reserved
Reserved
APIC Clock
APIC I/O
TRDY#
TRST#
AGTL+ Input
TAP Input
APIC I/O
AGTL+ Output
CMOS Input
CMOS Input
AGTL+ I/O
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
5
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Power/Other
Power/Other
Power/Other
Power/Other
Datasheet
73
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 35. Signal Listing in Order by
Signal Name (Sheet 7 of 8)
Table 35. Signal Listing in Order by
Signal Name (Sheet 8 of 8)
Pin
No.
Pin
No.
Pin Name
Signal Group
Pin Name
Signal Group
B69
VCC
Power/Other
B121
B120
A120
A119
B119
A121
A1
VCC
L2
Power/Other
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
L2
B73
B77
B85
B89
B93
B97
B105
B113
B117
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VID0
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VID1
VID2
VID3
VID4
V
V
V
V
TT
TT
TT
TT
A3
B5
B9
L2
74
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
®
®
5.6
Intel Pentium III Processor Core Pad to Substrate Via
Assignments
These test points are the closest locations to the processor core die pad and should be used to
validate processor core timings and signal quality on the back of the S.E.C.C. or the S.E.C.C.2
package. Please see the SECC Disassembly Process Application Note for the instructions on
removing the cover of the SECC package.
5.6.1
Processor Core Pad Via Assignments (CPUID 067xh)
Figure 47 shows the via locations on the back of the processor substrate.
Figure 47. Processor Core Pad Via Assignments
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
proc_core_pad_vias
5.6.2
Processor Core Signal Assignments (CPUID 067xh)
Table 36 and Table 37 shows the signal to via and the via to signal assignments, respectively.
Datasheet
75
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 36. Via Listing in Order by Signal
Name
Table 36. Via Listing in Order by Signal
Name (Continued)
Signal Name
Via Locations
Signal Name
Via Locations
A3#
A4#
S18
W18
T18
U18
Y19
W19
V18
V19
W20
X20
V20
Y20
T21
W21
V21
Y21
W23
V24
P23
V23
T22
U22
T24
S20
S23
T23
U23
R21
S22
S21
R24
Q20
R23
Q21
X21
X13
S16
X15
BCLK
BERR#
BINT#
BNR#
BP2#
BP3#
BPM0#
BPM1#
BPRI#
BR0#
BR1#
BSEL0
BSEL1
D0#
R6
Q23
G17
S17
C16
G16
B17
E17
T15
V14
T16
N23
V2
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADS#
AERR#
AP0#
AP1#
M21
M22
M19
M24
L23
M20
L20
L19
L22
L21
K23
K20
K24
K19
K25
K22
J24
J25
J21
I22
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
J23
J22
I23
K21
J20
76
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 36. Via Listing in Order by Signal
Name (Continued)
Table 36. Via Listing in Order by Signal
Name (Continued)
Signal Name
Via Locations
Signal Name
Via Locations
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
I24
H23
H22
H20
I21
D63#
DBSY#
DEFER#
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
DRDY#
FERR#
FLUSH#
HIT#
D19
Y14
X17
H17
D18
C18
G18
E18
H18
B19
F18
Y16
P25
O19
V13
W14
Q25
O21
P22
F15
E14
V15
B16
D16
H16
D17
E16
N21
U17
Y17
S15
W15
W16
P21
S14
W13
S13
T13
I19
H24
H21
G24
E25
G23
F23
F21
G25
E24
D25
C24
C23
G22
F24
D23
D22
E23
E22
B22
H19
D21
D24
C21
E21
B20
C19
B21
E19
E20
G19
F19
D20
HITM#
IERR#
IGNNE#
INIT#
LINT[0]
LINT[1]
LOCK#
PICCLK
PICD[0]
PICD[1]
PRDY#
PREQ#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESET#
RP#
RS0#
RS1#
RS2#
Datasheet
77
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 36. Via Listing in Order by Signal
Name
Table 36. Via Listing in Order by Signal
Name (Continued)
Signal Name
Via Locations
Signal Name
Via Locations
A3#
A4#
S18
W18
T18
U18
Y19
W19
V18
V19
W20
X20
V20
Y20
T21
W21
V21
Y21
W23
V24
P23
V23
T22
U22
T24
S20
S23
T23
U23
R21
S22
S21
R24
Q20
R23
Q21
X21
X13
S16
X15
BCLK
BERR#
BINT#
BNR#
BP2#
BP3#
BPM0#
BPM1#
BPRI#
BR0#
BR1#
BSEL0
BSEL1
D0#
R6
Q23
G17
S17
C16
G16
B17
E17
T15
V14
T16
N23
V2
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADS#
AERR#
AP0#
AP1#
M21
M22
M19
M24
L23
M20
L20
L19
L22
L21
K23
K20
K24
K19
K25
K22
J24
J25
J21
I22
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
J23
J22
I23
K21
J20
78
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 36. Via Listing in Order by Signal
Name (Continued)
Table 36. Via Listing in Order by Signal
Name (Continued)
Signal Name
Via Locations
Signal Name
Via Locations
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
I24
H23
H22
H20
I21
D63#
DBSY#
DEFER#
DEP0#
DEP1#
DEP2#
DEP3#
DEP4#
DEP5#
DEP6#
DEP7#
DRDY#
FERR#
FLUSH#
HIT#
D19
Y14
X17
H17
D18
C18
G18
E18
H18
B19
F18
Y16
P25
O19
V13
W14
Q25
O21
P22
F15
E14
V15
B16
D16
H16
D17
E16
N21
U17
Y17
S15
W15
W16
P21
S14
W13
S13
T13
I19
H24
H21
G24
E25
G23
F23
F21
G25
E24
D25
C24
C23
G22
F24
D23
D22
E23
E22
B22
H19
D21
D24
C21
E21
B20
C19
B21
E19
E20
G19
F19
D20
HITM#
IERR#
IGNNE#
INIT#
LINT[0]
LINT[1]
LOCK#
PICCLK
PICD[0]
PICD[1]
PRDY#
PREQ#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESET#
RP#
RS0#
RS1#
RS2#
Datasheet
79
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 36. Via Listing in Order by Signal
Name (Continued)
Table 36. Via Listing in Order by Signal
Name (Continued)
Signal Name
Via Locations
Signal Name
Via Locations
RSP#
SLP#
V16
O22
Q24
P24
O20
O23
N19
M23
N24
M25
O24
X18
N20
A2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J1
J5
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
SMI#
J8
STPCLK#
TCK
J10
J12
J14
J16
K2
TDI
TDO
THERMTRIP#
THRMDN
THRMDP
TMS
L8
L10
L12
L14
L16
M2
TRDY#
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
A4
N2
B1
N4
B2
N6
B6
N8
B9
N10
N12
N16
P8
B25
C14
D5
E1
P10
P12
P14
P16
Q22
R5
E4
E6
E10
E12
F14
G3
R7
G8
R8
G10
G12
G14
H2
R10
R12
R14
R16
R18
S19
S24
T4
H8
H10
H25
I17
80
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 36. Via Listing in Order by Signal
Name (Continued)
Table 36. Via Listing in Order by Signal
Name (Continued)
Signal Name
Via Locations
Signal Name
Via Locations
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T5
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
I12
I14
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
T12
T19
U2
I16
I18
I20
U14
W1
W6
W9
W24
X2
J6
J7
J9
J11
J13
J15
J17
J18
K6
X14
Y22
Y23
X24
U3
VSS
K8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K10
K12
K14
K16
K18
L2
U4
A1
A3
B11
B24
C17
C20
C22
C25
D4
L18
L25
M6
M8
M10
M12
M14
M16
M18
N1
D6
F6
F10
F17
F20
F22
F25
G4
N18
O8
O10
O12
O14
O16
P18
I1
I2
I8
I10
Datasheet
81
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 36. Via Listing in Order by Signal
Name (Continued)
Table 36. Via Listing in Order by Signal
Name (Continued)
Signal Name
Via Locations
Signal Name
Via Locations
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Q8
Q10
Q12
Q14
Q16
Q18
R4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
S5
U13
U16
U19
U20
U21
U24
V22
W17
W22
X1
R9
R11
R13
R15
R17
R19
R22
R25
S3
X7
X16
X19
X22
X23
S4
82
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 37. Via Listing in Order by Via
Location
Table 37. Via Listing in Order by Via
Location (Continued)
Via Locations
Signal Name
Via Locations
Signal Name
A1
A2
VSS
D23
D24
D25
E1
D45#
D52#
D40#
VCC
CORE
A3
VSS
A4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
B1
E4
B2
E6
B6
E10
E12
E14
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
F6
B9
B11
B16
B17
B19
B20
B21
B22
B24
B25
C14
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
D4
VSS
LINT[1]
PREQ#
BPM1#
DEP4#
D58#
D59#
D54#
D48#
D47#
D39#
D34#
VSS
PICCLK
BPM0#
DEP6#
D55#
D57#
D49#
VSS
VCC
VCC
CORE
CORE
BP2#
VSS
DEP2#
D56#
VSS
F10
F14
F15
F17
F18
F19
F20
F21
F22
F23
F24
F25
G3
VSS
VCC
CORE
LINT[0]
VSS
D53#
VSS
DEP7#
D61#
VSS
D42#
D41#
VSS
D37#
VSS
VSS
D5
VCC
D36#
D44#
VSS
CORE
D6
VSS
D16
D17
D18
D19
D20
D21
D22
PICD[0]
PRDY#
DEP1#
D63#
VCC
CORE
G4
VSS
G8
VCC
VCC
VCC
VCC
CORE
CORE
CORE
CORE
D62#
G10
G12
G14
D51#
D46#
Datasheet
83
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 37. Via Listing in Order by Via
Location (Continued)
Table 37. Via Listing in Order by Via
Location (Continued)
Via Locations
Signal Name
Via Locations
Signal Name
G16
G17
G18
G19
G22
G23
G24
G25
H2
BP3#
BINT#
DEP3#
D60#
D43#
D35#
D33#
D38#
J6
VSS
VSS
J7
J8
VCC
CORE
VSS
VCC
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J20
J21
J22
J23
J24
J25
K2
CORE
VSS
VCC
CORE
VSS
VCC
VCC
VCC
VCC
CORE
CORE
CORE
CORE
VSS
VCC
H8
H10
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
I1
CORE
PICD[1]
DEP0#
DEP5#
D50#
VSS
VSS
D24#
D18#
D21#
D20#
D16#
D17#
D28#
D32#
D27#
D26#
D31#
VCC
CORE
VCC
K6
VSS
VSS
CORE
VSS
K8
I2
VSS
VSS
VSS
VSS
VSS
VSS
K10
K12
K14
K16
K18
K19
K20
K21
K22
K23
K24
K25
L02
L08
L10
L12
VSS
I8
VSS
I10
VSS
I12
VSS
I14
VSS
I16
D13#
D11#
D23#
D15#
D10#
D12#
D14#
VSS
I17
VCC
CORE
I18
VSS
D30#
VSS
I19
I20
I21
D29#
D19#
D22#
D25#
I22
I23
I24
VCC
CORE
CORE
CORE
J1
VCC
VCC
VCC
CORE
CORE
J5
VCC
84
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 37. Via Listing in Order by Via
Location (Continued)
Table 37. Via Listing in Order by Via
Location (Continued)
Via Locations
Signal Name
Via Locations
Signal Name
L14
L16
L18
L19
L20
L21
L22
L23
L25
M2
VCC
VCC
O8
O10
O12
O14
O16
O19
O20
O21
O22
O23
O24
P8
VSS
VSS
CORE
CORE
VSS
VSS
D7#
D6#
D9#
D8#
D4#
VSS
VSS
VSS
FLUSH#
TCK
IGNNE#
SLP#
TDI
VCC
CORE
M6
VSS
VSS
TMS
M8
VCC
VCC
VCC
VCC
VCC
CORE
CORE
CORE
CORE
CORE
M10
M12
M14
M16
M18
M19
M20
M21
M22
M23
M24
M25
N1
VSS
P10
P12
P14
P16
P18
P21
P22
P23
P24
P25
Q8
VSS
VSS
VSS
VSS
VSS
D2#
RESET#
INIT#
A20M#
STPCLK#
FERR#
VSS
D5#
D0#
D1#
THERMTRIP#
D3#
THRMDP
VSS
Q10
Q12
Q14
Q16
Q18
Q20
Q21
Q22
Q23
Q24
Q25
R4
VSS
VSS
N2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
CORE
CORE
CORE
CORE
CORE
CORE
CORE
N4
VSS
N6
VSS
N8
A33#
A35#
N10
N12
N16
N18
N19
N20
N21
N23
N24
VCC
CORE
BERR#
SMI#
VSS
TDO
TRST#
IERR#
VSS
PWRGOOD
BSEL0
R5
VCC
CORE
R6
BCLK
THRMDN
R7
VCC
CORE
Datasheet
85
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 37. Via Listing in Order by Via
Location (Continued)
Table 37. Via Listing in Order by Via
Location (Continued)
Via Locations
Signal Name
Via Locations
Signal Name
R8
R9
VCC
T16
T18
T19
T21
T22
T23
T24
U02
U03
U04
U13
U14
U16
U17
U18
U19
U20
U21
U22
U23
U24
V2
BR1#
A5#
CORE
CORE
CORE
CORE
CORE
CORE
VSS
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R21
R22
R23
R24
R25
S3
VCC
VCC
CORE
VSS
A15#
A22#
A27#
A24#
VCC
VSS
VCC
VSS
VCC
CORE
VCC
VSS
VSS
VSS
VSS
VCC
VSS
VCC
CORE
A29#
VSS
VSS
REQ0#
A6#
A34#
A32#
VSS
VSS
VSS
VSS
VSS
S4
VSS
A23#
A28#
VSS
S5
VSS
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
T4
RS1#
RP#
BSEL1
HIT#
BR0#
LOCK#
RSP#
A9#
REQ2#
AP0#
BNR#
A3#
V13
V14
V15
V16
V18
V19
V20
V21
V22
V23
V24
W1
VCC
CORE
A25#
A10#
A13#
A17#
VSS
A31#
A30#
A26#
VCC
A21#
A20#
CORE
CORE
CORE
CORE
CORE
VCC
VCC
VCC
VCC
T5
VCC
VCC
VCC
CORE
CORE
CORE
T9
W6
T12
T13
T15
W9
RS2#
BPRI#
W13
W14
RS0#
HITM#
86
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 37. Via Listing in Order by Via
Location (Continued)
Table 37. Via Listing in Order by Via
Location (Continued)
Via Locations
Signal Name
Via Locations
Signal Name
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
X01
X02
X07
X13
X14
X15
X16
REQ3#
REQ4#
VSS
X17
X18
X19
X20
X21
X22
X23
X24
Y14
Y16
Y17
Y19
Y20
Y21
Y22
Y23
DEFER#
TRDY#
VSS
A4#
A12#
ADS#
VSS
A8#
A11#
A16#
VSS
VSS
VSS
A19#
DBSY#
DRDY#
REQ1#
A7#
VCC
CORE
CORE
VSS
VCC
VSS
A14#
A18#
AERR#
VCC
VCC
CORE
CORE
CORE
AP1#
VCC
VSS
Datasheet
87
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
5.6.3
Processor Core Pad Via Assignments (CPUID 068xh)
Figure 48 shows the via locations on the back of the processor substrate.
Figure 48. Intel® Pentium® III Processor S.E.C.C. 2 Via Map
88
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
6.0
Boxed Processor Specifications
6.1
Introduction
The Pentium III processor is also offered as an Intel boxed processor. Intel boxed processors are
intended for system integrators who build systems from baseboards and components. Boxed
Pentium III processors are supplied with an attached fan heatsink. This section documents
baseboard and system requirements for the fan heatsink that will be supplied with the boxed
Pentium III processor. This section is particularly important for original equipment manufacturer’s
(OEM's) that manufacture baseboards for system integrators. Unless otherwise noted, all figures in
this section are dimensioned in inches. Figure 49 shows a mechanical representation of a boxed
Pentium III processor in the S.E.C.C.2 package. Boxed Pentium III processors are not available in
the S.E.C.C. package.
Note: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
Figure 49. Boxed Intel® Pentium® III Processor in the S.E.C.C.2 Packaging
(Fan Power Cable Not Shown)
Heatsink
S.E.C.C. 2 Cover
Fan Power
Connector
Fan
Fan
Shroud
6.2
Fan Heatsink Mechanical Specifications
This section documents the mechanical specifications of the boxed Pentium III processor fan
heatsinks. Baseboard manufacturers and system designers should take into account the spacial
requirement for the boxed Pentium III processor in the S.E.C.C.2 package.
6.2.1
Boxed Processor Fan Heatsink Dimensions
The boxed processor is shipped with an attached fan heatsink. Clearance is required around the fan
heatsink to ensure unimpeded air flow for proper cooling. Spacial requirements and dimensions for
the boxed processor in S.E.C.C.2 package are shown in Figure 50 (Side View), Figure 51 (Front
View), and Figure 52 (Top View). All dimensions are in inches.
Datasheet
89
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 50. Side View Space Requirements for the Boxed Processor with S.E.C.C.2 Packaging
Figure 51. Front View Space Requirements for the Boxed Processor with S.E.C.C.2 Packaging
90
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 52. Top View Air Space Requirements for the Boxed Processor
Table 38. Boxed Processor Fan Heatsink Spatial Dimensions
Fig.Ref. Refersto
Label
Figure
Dimensions (Inches)
Min
Typ
Max
S.E.C.C.2 Fan Heatsink Depth (off processor
substrate)
A
50
1.48
B
C
D
50
51
51
S.E.C.C.2 Fan Heatsink Height Above Baseboard
S.E.C.C.2 Fan Heatsink Height
0.4
2.2
4.9
S.E.C.C.2 Fan Heatsink Width (plastic shroud only)
S.E.C.C.2 Power Cable Connector Location From
Edge of Fan Heatsink Shroud
E
51
1.4
1.45
F
52
52
Airflow keep out zones from end of fan heatsink
Airflow keepout zones from face of fan heatsink
0.40
0.20
G
6.2.2
6.2.3
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 225 grams. See Section 4.0 and
Section 5.0 for details on the processor weight and heatsink requirements.
Boxed Processor Retention Mechanism
The boxed processor requires processor retention mechanism(s) to secure the processor in the 242-
contact slot connector. S.E.C.C.2 processors must use either retention mechanisms described in
AP-826, Mechanical Assembly and Customer Manufacturing Technology for S.E.P. Packages
(Order Number 243748) or Universal Retention Mechanisms that accept S.E.C.C., S.E.P.P. and
S.E.C.C.2 packaged processors. The boxed processor will not ship with a retention mechanism.
Baseboards designed for use by system integrators must include retention mechanisms that support
the S.E.C.C.2 package and the appropriate installation instructions.
Baseboards designed to accept both Pentium II processors and Pentium III processors have
component height restrictions for passive heatsink support designs, as described in AP-588,
Mechanical and Assembly Technology for S.E.C. Cartridge Processors (Order Number 243333).
Datasheet
91
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
6.3
Fan Heatsink Electrical Requirements
6.3.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be
shipped with the boxed processor to draw power from a power header on the baseboard. The power
cable connector and pinout are shown in Figure 53. Baseboards must provide a matched power
header to support the boxed processor. Table 39 contains specifications for the input and output
signals at the fan heatsink connector. The cable length will be 7.0 ±0.25 inches. The fan heatsink
outputs a SENSE signal, which is an open-collector output, that pulses at a rate of two pulses per
Ω
fan revolution. A baseboard pull-up resistor (~12 k ) provides VOH to match the baseboard-
mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the
SENSE signal is not used, pin 3 of the connector should be tied to GND.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the baseboard
documentation, or on the baseboard itself. Figure 53 shows the location of the fan power connector
relative to the 242-contact slot connector. The baseboard power header should be positioned within
4.75 inches (lateral) of the fan power connector.
Figure 53. Boxed Processor Fan Heatsink Power Cable Connector Description
Pin
1
Signal
GND
Straight square pin, 3-pin terminal housing with
polarizing ribs and friction locking ramp.
2
3
+12V
0.100" pin pitch, 0.025" square pin width.
SENSE
Waldom/Molex P/N 22-01-3037 or equivalent.
Match with straight pin, friction lock header on motherboard
Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3,
or equivalent.
1
2
3
Table 39. Fan Heatsink Power and Signal Specifications
Description
Min
Typ
Max
+12 V: 12 volt fan power supply
9 V
12 V
13.8 V
100 mA
10 mA
I : Fan current draw
C
Ics: Fan sense signal current
SENSE: SENSE frequency (baseboard should pull this
pin up to appropriate VCC with resistor)
2 pulses per
fan revolution
92
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Figure 54. Recommended Baseboard Power Header Placement Relative to Fan Power
Connector and Intel® Pentium® III Processor
242-Contact Slot Connector
Fan power connector location
V
(1.56 inches above motherboard
W
X
Motherboard fan power header should be
positioned within 4.75 inches of the fan
power connector (lateral distance).
Table 40. Baseboard Fan Power Connector Location
Fig. Ref.
Labels
Dimensions (Inches)
Min
Typ
1.44
1.45
Max
Approximate perpendicular distance of the fan power connector
from the center of the 242-contact slot connector
V
Approximate parallel distance of the fan power connector from
the edge of the 242-contact slot connector
W
X
Lateral distance of the baseboard fan power header location
from the fan power connector
4.75
6.4
Fan Heatsink Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution utilized by the boxed
processor.
6.4.1
Boxed Processor Cooling Requirements
The boxed processor will be directly cooled with a fan heatsink. However, meeting the processor's
temperature specification is also function of the thermal design of the entire system, and ultimately
the responsibility of the system integrator. Refer to Section 4.0 for processor temperature
specifications. The boxed processor fan heatsink is able to keep the processor temperature within
the specifications (see Table 25 and Table 26) in chassis that provide good thermal management.
For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to
the fan heatsink is unimpeded. Airspace is required around the fan to ensure that the airflow
through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the
cooling efficiency and decreases fan life. Figure 52 illustrates an acceptable airspace clearance for
the fan heatsink. It is also recommended that the air temperature entering the fan be kept below
45 °C (see Figure 52 for measurement location). Again, meeting the processor's temperature
specification is the responsibility of the system integrator. Refer to Section 4.0 for processor
temperature specifications.
Datasheet
93
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
7.0
Intel®Pentium® III Processor Signal Description
This section provides an alphabetical listing of all Intel® Pentium® III processor signals. The tables
at the end of this section summarize the signals by direction: output, input, and I/O.
7.1
Alphabetical Signals Reference
Table 41. Signal Description
Name
Type
Description
The A[35:3]# (Address) signals define a 236-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
A[35:3]#
I/O
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
®
pins to determine their power-on configuration. See the Pentium II Processor
Developer’s Manual (Order Number 243502) for details.
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of
A20M# is only supported in real mode.
A20M#
I
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all processor system bus agents.
ADS#
I/O
I/O
The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate pins on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
AERR#
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are
low and low if an odd number of covered signals are low. This allows parity to be
high when all the covered signals are high. AP[1:0]# should connect the appropriate
pins of all processor system bus agents.
AP[1:0]#
BCLK
I/O
The BCLK (Bus Clock) signal determines the bus frequency. All processor system
bus agents must receive this signal to drive their outputs and latch their inputs on
the BCLK rising edge.
I
All external timing parameters are specified with respect to the BCLK signal.
94
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 41. Signal Description (Continued)
Name
Type
Description
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents, and must connect the appropriate pins of all such agents, if used. However,
®
Pentium III processors do not observe assertions of the BERR# signal.
BERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
BERR#
I/O
•
•
•
Enabled or disabled.
Asserted optionally for internal errors along with IERR#.
Asserted optionally by the request initiator of a bus transaction after it observes an
error.
•
Asserted by any bus agent when it observes an error in a bus transaction.
The BINIT# (Bus Initialization) signal may be observed and driven by all processor
system bus agents, and if used must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled during power on configuration, BINIT# is
asserted to signal any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, all bus state machines are reset and any data which was in
transit is lost. All agents reset their rotating ID for bus arbitration to the state after
Reset, and internal count information is lost. The L1 and L2 caches are not
affected.
BINIT#
I/O
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor system
bus agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BNR#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
BP[3:2]#
I/O
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
BPM[1:0]#
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
processor system bus. It must connect the appropriate pins of all processor system
bus agents. Observing BPRI# active (as asserted by the priority agent) causes all
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BPRI#
I
Datasheet
95
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 41. Signal Description (Continued)
Name
Type
Description
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
BR0# (I/O) and BR1# Signals Rotating Interconnect
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BREQ1#
BR0#
BR1#
BR1#
BR0#
BR0#
I/O
I
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its
symmetric agent ID. All agents then configure their pins to match the appropriate bu
signal protocol, as shown below.
BR1#
BR[1:0]# Signal Agent IDs
Pin Sampled Active in RESET#
Agent ID
BR0#
BR1#
0
1
These signals are used to select the system bus frequency. A BSEL[1:0] = “01” will
select a 100 MHz system bus and a BSEL[1:0] = “11” will select a 133 MHz system
bus frequency. The frequency is determined by the processor(s), chipset, and
frequency synthesizer capabilities. All system bus agents must operate at the same
frequency. The Pentium III processor operates at 100 MHz and 133 MHz system
bus frequencies. Individual processors will only operate at their specified system
bus frequency. Either 100 MHz or 133 MHz, not both.
BSEL[1:0]
I/O
On motherboards which support operation at either 66 MHz or 100 MHz, a
BSEL[1:0] = “x0” will select a 66 MHz system bus frequency.
These signals must be pulled up to 3.3V with 1KΩ resistors and provided as
frequency selection signal to the clock driver/synthesizer. If the system
motherboard is not capable of operating at 133 MHz, it should ground the BSEL1
signal and generate a 100 MHz system bus frequency. See Section 2.8.2 for
implementation details.
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
D[63:0]#
DBSY#
I/O
I/O
I
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor system bus agents.
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEFER#
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DEP[7:0]#
DRDY#
I/O
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
96
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 41. Signal Description (Continued)
Name
Type
Description
EMI pins should be connected to baseboard ground and/or to chassis ground
through zero ohm (0Ω) resistors. The zero ohm resistors should be placed in close
proximity to the processor connector. The path to chassis ground should be short in
length and have a low impedance. These pins are used for EMI management
purposes.
EMI
I
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting.
FERR#
O
When the FLUSH# input signal is asserted, processors write back all data in the
Modified state from their internal caches and invalidate all internal cache lines. At
the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal
remains asserted.
FLUSH#
I
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH#
to determine its power-on configuration. See the P6 Family of Processors
Hardware Developer’s Manual (Order Number 244001) for details.
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all processor system
bus agents. Any such agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
HIT#
I/O
I/O
HITM#
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the processor system bus. This transaction may optionally be
converted to an external error signal (e.g., NMI) by system core logic. The
processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or
INIT#.
IERR#
O
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE#
I
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1 or L2) caches or floating-point
registers. Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to handle
snoop requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all processor system bus agents.
INIT#
I
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of
all APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Pentium processor. Both signals are asynchronous.
LINT[1:0]
I
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
Datasheet
97
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 41. Signal Description (Continued)
Name
Type
Description
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor system bus agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning of
the first transaction end of the last transaction.
LOCK#
I/O
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
PICCLK
I
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message
passing on the APIC bus, and must connect the appropriate pins of all processors
and core logic or I/O APIC components on the APIC bus.
PICD[1:0]
I/O
The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PRDY#
PREQ#
O
I
The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The
processor requires this signal to be a clean indication that the clocks and power
supplies (VCC
, etc.) are stable and within their specifications. Clean implies
CORE
that the signal will remain low (capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high (2.5 V) state.
The figure below illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in Table 15, and be followed by a 1 ms RESET#
pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
PWRGOOD
I
PWRGOOD Relationship at Power-On
BCLK
VCC
,
VCCP
,
VREF
V
IH,min
PWRGOOD
1 msec
RESET#
D0026-00
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
REQ[4:0]#
I/O
98
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 41. Signal Description (Continued)
Name
Type
Description
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. RESET# must
remain active for one microsecond for a “warm” Reset; for a power-on Reset,
RESET# must stay active for at least one millisecond after VCC
and CLK have
CORE
reached their proper specifications. On observing active RESET#, all processor
system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the P6
Family of Processors Hardware Developer’s Manual (Order Number 244001) for
details.
RESET#
I
The processor may have its outputs tristated via power-on configuration.
Otherwise, if INIT# is sampled active during the active-to-inactive transition of
RESET#, the processor will execute its Built-in Self-Test (BIST). Whether or not
BIST is executed, the processor will begin program execution at the power on
Reset vector (default 0_FFFF_FFF0h). RESET# must connect the appropriate pins
of all processor system bus agents.
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of
all processor system bus agents.
RP#
I/O
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RS[2:0]#
I
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
RSP#
I
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
The SLOTOCC# signal is defined to allow a system design to detect the presence
of a terminator card or processor in a SC242 connector. Combined with the VID
combination of VID[4:0]= 11111 (see Section 2.6), a system can determine if a
SC242 connector is occupied, and whether a processor core is present. See the
table below for states and values for determining the type of cartridge in the SC242
connector.
SC242 Occupation Truth Table
Signal
Value
Status
SLOTOCC#
O
0
SLOTOCC#
VID[4:0]
Anything other
than ‘11111’
Processor with core in SC242 connector.
SLOTOCC#
VID[4:0]
0
Terminator cartridge in SC242 connector
(i.e., no core present).
11111
SLOTOCC#
VID[4:0]
1
SC242 connector not occupied.
Any value
Datasheet
99
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 41. Signal Description (Continued)
Name
Type
Description
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SLP#
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
SMI#
I
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
STPCLK#
The TCK (Test Clock) signal provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TCK
I
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDI
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TDO
TESTHI
O
I
The TESTHI signal must be connected to a 2.5 V power source through a 1-100 kΩ
resistor for proper processor operation.
THERMDN
THERMDP
O
I
Thermal Diode Cathode. Used to calculate core temperature. See Section 4.1.
Thermal Diode Anode. Used to calculate core temperature. See Section 4.1.
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains
latched, and the processor stopped, until RESET# goes active. There is no
hysteresis built into the thermal sensor itself; as long as the die temperature drops
below the trip level, a RESET# pulse will reset the processor and execution will
continue. If the temperature has not dropped below the trip level, the processor will
continue to drive THERMTRIP# and remain stopped.
THERMTRIP#
O
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TMS
I
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRDY#
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset. This can be done with a 680 ohm pull-
down resistor.
TRST#
I
The VID[4:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See Table 3 for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
VID[4:0]
O
100
Datasheet
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
7.2
Signal Summaries
Table 42 through Table 45 list attributes of the processor output, input, and I/O signals.
Table 42. Output Signals
Name
Active Level
Clock
Signal Group
FERR#
IERR#
Low
Low
Low
Low
High
Low
High
Asynch
Asynch
BCLK
CMOS Output
CMOS Output
AGTL+ Output
Power/Other
TAP Output
PRDY#
SLOTOCC#
TDO
Asynch
TCK
THERMTRIP#
VID[4:0]
Asynch
Asynch
CMOS Output
Power/Other
Table 43. Input Signals
Name
Active Level
Clock
Signal Group
Qualified
A20M#
BPRI#
BR1#
Low
Low
Low
High
Low
Low
Low
Low
High
High
High
High
Low
High
Low
Low
Low
Low
Low
Low
High
High
High
High
Low
Low
Asynch
BCLK
BCLK
—
CMOS Input
AGTL+ Input
AGTL+ Input
System Bus Clock
AGTL+ Input
CMOS Input
CMOS Input
CMOS Input
CMOS Input
CMOS Input
CMOS Input
APIC Clock
CMOS Input
CMOS Input
AGTL+ Input
AGTL+ Input
AGTL+ Input
CMOS Input
CMOS Input
CMOS Input
TAP Input
Always1
Always
Always
BCLK
Always
DEFER#
FLUSH#
IGNNE#
INIT#
BCLK
Asynch
Asynch
Asynch
Asynch
Asynch
Asynch
—
Always
Always1
Always1
Always1
INTR
APIC disabled mode
APIC enabled mode
APIC disabled mode
Always
LINT[1:0]
NMI
PICCLK
PREQ#
PWRGOOD
RESET#
RS[2:0]#
RSP#
Asynch
Asynch
BCLK
BCLK
BCLK
Asynch
Asynch
Asynch
—
Always
Always
Always
Always
Always
SLP#
During Stop-Grant state
SMI#
STPCLK#
TCK
TDI
TCK
TAP Input
TESTHI
TMS
Asynch
TCK
Power/Other
TAP Input
Always
TRST#
TRDY#
Asynch
BCLK
TAP Input
AGTL+ Input
NOTE:
1. Synchronous assertion with active TDRY# ensures synchronization.
Datasheet
101
Pentium® III Processor for the SC242 at 450 MHz to 800 MHz
Table 44. Input/Output Signals (Single Driver)
Name
Active Level
Clock
Signal Group
Qualified
BSEL[1:0]
A[35:3]#
ADS#
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Asynch
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
Power/Other
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
Always
ADS#, ADS#+1
Always
AP[1:0]#
BR0#
ADS#, ADS#+1
Always
BP[3:2]#
BPM[1:0]#
D[63:0]#
DBSY#
Always
Always
DRDY#
Always
DEP[7:0]#
DRDY#
LOCK#
DRDY#
Always
Always
REQ[4:0]#
RP#
ADS#, ADS#+1
ADS#, ADS#+1
Table 45. Input/Output Signals (Multiple Driver)
Name
Active Level
Clock
Signal Group
Qualified
AERR#
BERR#
BNR#
Low
Low
Low
Low
Low
Low
High
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
PICCLK
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
AGTL+ I/O
APIC I/O
ADS#+3
Always
Always
Always
Always
Always
Always
BINIT#
HIT#
HITM#
PICD[1:0]
102
Datasheet
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