BX80557E4600/SLA94 [INTEL]
RISC Microprocessor, 64-Bit, 2400MHz, CMOS, PBGA775;型号: | BX80557E4600/SLA94 |
厂家: | INTEL |
描述: | RISC Microprocessor, 64-Bit, 2400MHz, CMOS, PBGA775 |
文件: | 总118页 (文件大小:1765K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
Intel Core™2 Extreme Processor
Δ
®
X6800 and Intel Core™2 Duo
Δ
Desktop Processor E6000 and
Δ
E4000 Series
Datasheet
—on 65 nm Process in the 775-land LGA Package and supporting Intel® 64
±
Architecture and supporting Intel® Virtualization Technology
March 2008
Document Number: 313278-008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT
INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in
clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular
feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/
processor_number for details.
®
Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor
will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software
configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or
consult with your system vendor for more information.
®
®
®
No computer system can provide absolute security under all conditions. Intel Trusted Execution Technology (Intel TXT) is a security technology under
development by Intel and requires for operation a computer system with Intel Virtualization Technology, a Intel Trusted Execution Technology-enabled
Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual
machine monitor. In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group
and specific software for some uses.
®
®
±Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM) and, for some
uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations
and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
®
®
The Intel Core™2 Duo desktop processor E6000 and E4000 series and Intel Core™2 Extreme processor X6800 may contain design defects or errors
known as errata which may cause the product to deviate from published specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Core, Core Inside, Intel Inside, Intel Leap ahead, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S.
and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2006–2008 Intel Corporation.
2
Datasheet
Contents
1
Introduction............................................................................................................ 11
1.1
Terminology ..................................................................................................... 12
1.1.1 Processor Terminology............................................................................ 12
References ....................................................................................................... 14
1.2
2
Electrical Specifications........................................................................................... 15
2.1
2.2
Power and Ground Lands.................................................................................... 15
Decoupling Guidelines........................................................................................ 15
2.2.1 VCC Decoupling ..................................................................................... 15
2.2.2 Vtt Decoupling....................................................................................... 15
2.2.3 FSB Decoupling...................................................................................... 16
Voltage Identification......................................................................................... 16
Market Segment Identification (MSID) ................................................................. 18
Reserved, Unused, and TESTHI Signals ................................................................ 18
Voltage and Current Specification........................................................................ 19
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 19
2.6.2 DC Voltage and Current Specification........................................................ 20
2.6.3 VCC Overshoot ....................................................................................... 24
2.6.4 Die Voltage Validation............................................................................. 24
Signaling Specifications...................................................................................... 25
2.7.1 FSB Signal Groups.................................................................................. 25
2.7.2 CMOS and Open Drain Signals ................................................................. 27
2.7.3 Processor DC Specifications ..................................................................... 27
2.7.3.1 GTL+ Front Side Bus Specifications ............................................. 28
2.7.4 Clock Specifications................................................................................ 29
2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................ 29
2.7.6 FSB Frequency Select Signals (BSEL[2:0])................................................. 29
2.7.7 Phase Lock Loop (PLL) and Filter .............................................................. 30
2.7.8 BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 30
2.7.9 BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 32
PECI DC Specifications....................................................................................... 33
2.3
2.4
2.5
2.6
2.7
2.8
Package Mechanical Specifications .......................................................................... 35
3
3.1
Package Mechanical Drawing............................................................................... 35
3.1.1 Processor Component Keep-Out Zones...................................................... 39
3.1.2 Package Loading Specifications ................................................................ 39
3.1.3 Package Handling Guidelines.................................................................... 39
3.1.4 Package Insertion Specifications............................................................... 40
3.1.5 Processor Mass Specification.................................................................... 40
3.1.6 Processor Materials................................................................................. 40
3.1.7 Processor Markings................................................................................. 40
3.1.8 Processor Land Coordinates..................................................................... 43
4
5
Land Listing and Signal Descriptions ....................................................................... 45
4.1
4.2
Processor Land Assignments............................................................................... 45
Alphabetical Signals Reference............................................................................ 68
Thermal Specifications and Design Considerations .................................................. 77
5.1
Processor Thermal Specifications......................................................................... 77
5.1.1 Thermal Specifications ............................................................................ 77
5.1.2 Thermal Metrology ................................................................................. 84
Processor Thermal Features................................................................................ 84
5.2.1 Thermal Monitor..................................................................................... 84
5.2.2 Thermal Monitor 2.................................................................................. 85
5.2.3 On-Demand Mode .................................................................................. 86
5.2
Datasheet
3
5.2.4 PROCHOT# Signal ..................................................................................87
5.2.5 THERMTRIP# Signal................................................................................87
Thermal Diode...................................................................................................88
Platform Environment Control Interface (PECI) ......................................................90
5.4.1 Introduction...........................................................................................90
5.4.1.1 Key Difference with Legacy Diode-Based Thermal
5.3
5.4
Management ............................................................................90
5.4.2 PECI Specifications .................................................................................92
5.4.2.1 PECI Device Address..................................................................92
5.4.2.2 PECI Command Support.............................................................92
5.4.2.3 PECI Fault Handling Requirements...............................................92
5.4.2.4 PECI GetTemp0() Error Code Support ..........................................92
6
Features ..................................................................................................................93
6.1
6.2
Power-On Configuration Options ..........................................................................93
Clock Control and Low Power States.....................................................................93
6.2.1 Normal State .........................................................................................94
6.2.2 HALT and Extended HALT Powerdown States ..............................................94
6.2.2.1 HALT Powerdown State ..............................................................94
6.2.2.2 Extended HALT Powerdown State ................................................95
6.2.3 Stop Grant and Extended Stop Grant States...............................................95
6.2.3.1 Stop Grant State.......................................................................95
6.2.3.2 Extended Stop Grant State.........................................................96
6.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop
State, and Stop Grant Snoop State ...........................................................96
6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................96
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop
State.......................................................................................96
6.3
Enhanced Intel® SpeedStep® Technology .............................................................96
7
Boxed Processor Specifications................................................................................99
7.1
Mechanical Specifications..................................................................................100
7.1.1 Boxed Processor Cooling Solution Dimensions...........................................100
7.1.2 Boxed Processor Fan Heatsink Weight .....................................................101
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip
Assembly.............................................................................................101
Electrical Requirements ....................................................................................101
7.2.1 Fan Heatsink Power Supply ....................................................................101
Thermal Specifications......................................................................................103
7.3.1 Boxed Processor Cooling Requirements....................................................103
7.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor
7.2
7.3
X6800 Only) ........................................................................................105
7.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor
E6000 and E4000 Series Only) ...............................................................105
8
Balanced Technology Extended (BTX) Boxed Processor Specifications...................107
8.1
Mechanical Specifications..................................................................................108
8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor
Cooling Solution Dimensions ..................................................................108
8.1.2 Boxed Processor Thermal Module Assembly Weight ...................................110
8.1.3 Boxed Processor Support and Retention Module (SRM) ..............................111
Electrical Requirements ....................................................................................112
8.2.1 Thermal Module Assembly Power Supply..................................................112
Thermal Specifications......................................................................................114
8.3.1 Boxed Processor Cooling Requirements....................................................114
8.3.2 Variable Speed Fan...............................................................................114
8.2
8.3
9
Debug Tools Specifications ....................................................................................117
9.1
Logic Analyzer Interface (LAI) ...........................................................................117
9.1.1 Mechanical Considerations .....................................................................117
9.1.2 Electrical Considerations........................................................................117
4
Datasheet
Figures
1
2
3
4
5
6
7
8
9
VCC Static and Transient Tolerance............................................................................. 23
VCC Overshoot Example Waveform ............................................................................. 24
Differential Clock Waveform ...................................................................................... 31
Differential Clock Crosspoint Specification ................................................................... 31
Differential Measurements......................................................................................... 31
Differential Clock Crosspoint Specification ................................................................... 32
Processor Package Assembly Sketch........................................................................... 35
Processor Package Drawing Sheet 1 of 3 ..................................................................... 36
Processor Package Drawing Sheet 2 of 3 ..................................................................... 37
10 Processor Package Drawing Sheet 3 of 3 ..................................................................... 38
11 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB..................................... 40
12 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB................................... 41
13 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processors E6000 Series with 2 MB L2 Cache............................................................... 41
14 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processors E4000 Series with 2 MB L2 Cache............................................................... 42
15 Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800................. 42
16 Processor Land Coordinates and Quadrants (Top View) ................................................. 43
17 land-out Diagram (Top View – Left Side)..................................................................... 46
18 land-out Diagram (Top View – Right Side)................................................................... 47
19 Thermal Profile 1 ..................................................................................................... 79
20 Thermal Profile 2 ..................................................................................................... 80
21 Thermal Profile 3 ..................................................................................................... 81
22 Thermal Profile 4 ..................................................................................................... 82
23 Thermal Profile 5 ..................................................................................................... 83
24 Case Temperature (TC) Measurement Location ............................................................ 84
25 Thermal Monitor 2 Frequency and Voltage Ordering...................................................... 86
26 Processor PECI Topology........................................................................................... 90
27 Conceptual Fan Control on PECI-Based Platforms ......................................................... 91
28 Conceptual Fan Control on Thermal Diode-Based Platforms............................................ 91
29 Processor Low Power State Machine ........................................................................... 94
30 Mechanical Representation of the Boxed Processor ....................................................... 99
31 Space Requirements for the Boxed Processor (Side View)............................................ 100
32 Space Requirements for the Boxed Processor (Top View)............................................. 100
33 Space Requirements for the Boxed Processor (Overall View)........................................ 101
34 Boxed Processor Fan Heatsink Power Cable Connector Description................................ 102
35 Baseboard Power Header Placement Relative to Processor Socket................................. 103
36 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) ................. 104
37 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................. 104
38 Boxed Processor Fan Heatsink Set Points................................................................... 106
39 Mechanical Representation of the Boxed Processor with a Type I TMA ........................... 109
40 Mechanical Representation of the Boxed Processor with a Type II TMA .......................... 110
41 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out
Volumes ............................................................................................................... 111
42 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out
Volume................................................................................................................. 112
43 Assembly Stack Including the Support and Retention Module ....................................... 113
44 Boxed Processor TMA Power Cable Connector Description............................................ 114
45 Balanced Technology Extended (BTX) Mainboard Power Header Placement
(hatched area) ...................................................................................................... 115
46 Boxed Processor TMA Set Points............................................................................... 117
Datasheet
5
Tables
1
2
3
4
5
6
7
8
9
Reference Documents ...............................................................................................14
Voltage Identification Definition..................................................................................17
Market Segment Selection Truth Table for MSID[1:0] ...................................................18
Absolute Maximum and Minimum Ratings ....................................................................20
Voltage and Current Specifications..............................................................................20
VCC Static and Transient Tolerance .............................................................................22
VCC Overshoot Specifications......................................................................................24
FSB Signal Groups....................................................................................................25
Signal Characteristics................................................................................................26
10 Signal Reference Voltages .........................................................................................26
11 GTL+ Signal Group DC Specifications ..........................................................................27
12 Open Drain and TAP Output Signal Group DC Specifications ...........................................27
13 CMOS Signal Group DC Specifications..........................................................................28
14 GTL+ Bus Voltage Definitions.....................................................................................28
15 Core Frequency to FSB Multiplier Configuration.............................................................29
16 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................30
17 Front Side Bus Differential BCLK Specifications.............................................................30
18 Front Side Bus Differential BCLK Specifications.............................................................32
19 PECI DC Electrical Limits ...........................................................................................33
20 Processor Loading Specifications.................................................................................39
21 Package Handling Guidelines......................................................................................39
22 Processor Materials...................................................................................................40
23 Alphabetical Land Assignments...................................................................................48
24 Numerical Land Assignment.......................................................................................58
25 Signal Description (Sheet 1 of 9)................................................................................68
26 Processor Thermal Specifications................................................................................78
27 Thermal Profile 1......................................................................................................79
28 Thermal Profile 2......................................................................................................80
29 Thermal Profile 3......................................................................................................81
30 Thermal Profile 4......................................................................................................82
31 Thermal Profile 5......................................................................................................83
32 Thermal “Diode” Parameters using Diode Model............................................................88
33 Thermal “Diode” Parameters using Transistor Model......................................................89
34 Thermal Diode Interface............................................................................................89
35 GetTemp0() Error Codes ...........................................................................................92
36 Power-On Configuration Option Signals .......................................................................93
37 Fan Heatsink Power and Signal Specifications.............................................................102
38 Fan Heatsink Power and Signal Specifications.............................................................106
39 TMA Power and Signal Specifications.........................................................................113
40 TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed
Processors.............................................................................................................115
6
Datasheet
Revision History
Revision
Number
Description
Date
July 2006
-001
-002
•
•
Initial release
Corrected L1 Cache information
®
September 2006
•
•
•
•
•
•
•
Added Intel Core™2 Duo Desktop Processor E4300 information
Updated Table 5, DC Voltage and Current Specification
Added Section 2.3, PECI DC Specifications
Updated Section 5.3, Platform Environment Control Interface (PECI)
Updated Section 7.1.2, Boxed Processor Fan Heatsink Weight
Updated Table 37, Fan Heatsink Power and Signal Specifications
-003
January 2007
®
Added Section 7.3.2, Fan Speed Control Operation Intel Core2 Extreme Processor
X6800 Only) and Section 7.3.3, Fan Speed Control Operation (Intel Core2 Duo Desktop
®
Processor E6000 and E4000 series Only)
®
-004
-005
•
•
Added Intel Core™2 Duo Desktop Processor E6420, E6320, and E4400 information
April 2007
July 2007
®
Added Intel Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500
information.
Added specifications for 1333 MHz FSB.
Added support for Extended Stop Grant State, Extended Stop Grant Snoop States.
Added new thermal profile table and figure.
•
•
•
®
-006
-007
-008
•
•
•
Added Intel Core™2 Duo Desktop Processor E4400 with CPUID = 065Dh.
August 2007
October 2007
March 2008
®
Added Intel Core™2 Duo Desktop Processor E4600
®
Added Intel Core™2 Duo Desktop Processor E4700
Datasheet
7
8
Datasheet
®
Intel Core™2 Extreme Processor
®
X6800 and Intel Core™2 Duo
Desktop Processor E6000 and
E4000 Series Features
• Available at 2.93 GHz (Intel Core™2 Extreme
• Binary compatible with applications running on
processor X6800 only)
previous members of the Intel microprocessor line
• Available at 3.00 GHz, 2.66 GHz, 2.40 GHz,
2.33 GHz, 2.13 GHz, and 1.86 GHz (Intel Core™2
Duo desktop processor E6850, E6750, E6700,
E6600, E6540, E6540, E6420, E6400, E6320, and
E6300 only)
• Advance Dynamic Execution
• Very deep out-of-order execution
• Enhanced branch prediction
• Optimized for 32-bit applications running on
advanced 32-bit operating systems
• Available at 2.40 GHz, 2.20 GHz, 2.00 GHz, and
1.80 GHz and (Intel Core™2 Duo desktop processor
E4700, E4600, E4500, E4400, and E4300 only)
• Two 32-KB Level 1 data caches
• 4 MB Intel® Advanced Smart Cache (Intel Core™2
Extreme processor X6800 and Intel Core™2 Duo
desktop processor E6850, E6750, E6700, E6540,
E6540, E6600, E6420, and E6320, only)
• Enhanced Intel SpeedStep® Technology
• Supports Intel® 64 architecture
• Supports Intel® Virtualization Technology (Intel
Core™2 Extreme processor X6800 and Intel
Core™2 Duo desktop processor E6000 series only)
• 2 MB Intel® Advanced Smart Cache (Intel Core™2
Duo desktop processor E6400, E6300, E4700,
E4600, E4500, E4400, and E4300 only)
• Supports Execute Disable Bit capability
• Intel® Advanced Digital Media Boost
• Supports Intel® Trusted Execution Technology
(Intel® TXT) (Intel Core2 Duo desktop processors
E6850, E6750, and E6550 only)
• Enhanced floating point and multimedia unit for
enhanced video, audio, encryption, and 3D
performance
• Power Management capabilities
• System Management mode
• Multiple low-power states
• FSB frequency at 1333 MHz (Intel Core2 Duo
desktop processors E6850, E6750, E6550, and
E6540 only)
• FSB frequency at 1066 MHz (Intel Core™2 Extreme
processor X6800 and Intel Core™2 Duo desktop
processor E6700, E6600, E6420, E6400, E6320,
and E6300 only)
• 8-way cache associativity provides improved cache
hit rate on load/store operations
• 775-land Package
• FSB frequency at 800 MHz (Intel Core™2 Duo
desktop processor E4000 series only)
The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000, E4000
series deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to
deliver performance across applications and usages where end-users can truly appreciate and
experience the performance. These applications include Internet audio and streaming video, image
processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user
environments.
Intel® 64 architecture enables the processor to execute operating systems and applications written to
take advantage of the Intel 64 architecture. The processor supporting Enhanced Intel SpeedStep®
technology allows tradeoffs to be made between performance and power consumption.
The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000, E4000
series also include the Execute Disable Bit capability. This feature, combined with a supported
operating system, allows memory to be marked as executable or non-executable.
The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 series
support Intel® Virtualization Technology. Virtualization Technology provides silicon-based functionality
that works together with compatible Virtual Machine Monitor (VMM) software to improve on software-
only solutions.
The Intel Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel® Trusted
Execution Technology (Intel® TXT). Intel® Trusted Execution Technology (Intel® TXT) is a security
technology.
§ §
Datasheet
9
10
Datasheet
Introduction
1
Introduction
The Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop
processor E6000 and E4000 series combine the performance of the previous generation
of desktop products with the power efficiencies of a low-power microarchitecture to
enable smaller, quieter systems. These processors are 64-bit processors that maintain
compatibility with IA-32 software.
The Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop
processor E6000 and E4000 series use Flip-Chip Land Grid Array (FC-LGA6) package
technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket,
referred to as the LGA775 socket.
Note:
Note:
In this document, unless otherwise specified, the Intel® Core™2 Duo desktop
processor E6000 series refers to Intel® Core™2 Duo desktop processors E6850, E6750,
E6550, E6540, E6700, E6600, E6420, E6400, E6320, and E6300. The Intel® Core™2
Duo desktop processor E4000 series refers to Intel® Core™2 Duo desktop processor
E4700, E4600, E4500, E4400, and E4300.
In this document, unless otherwise specified, the Intel® Core™2 Extreme processor
X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 series are referred
to as “processor.”
The processors support several Advanced Technologies including the Execute Disable
Bit, Intel® 64 architecture, and Enhanced Intel SpeedStep® Technology. The Intel
Core™2 Duo desktop processor E6000 series and Intel Core™2 Extreme processor
X6800 support Intel® Virtualization Technology (Intel VT). In addition, the Intel
Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel® Trusted
Execution Technology (Intel® TXT).
The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol
like the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST)
of address and data to improve performance by transferring data four times per bus
clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a "double-
clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 10.7 GB/s.
Intel has enabled support components for the processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.
The processor includes an address bus power-down capability which removes power
from the address and data signals when the FSB is not in use. This feature is always
enabled on the processor.
Datasheet
11
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
The phrase “Front Side Bus” refers to the interface between the processor and system
core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to
processors, memory, and I/O.
1.1.1
Processor Terminology
Commonly used terms are explained here for clarification:
• Intel® Core™2 Extreme processor X6800 — Dual core processor in the FC-
LGA6 package with a 4 MB L2 cache.
• Intel® Core™2 Duo desktop processor E6850, E6750, E6550, E6540,
E6700, E6600, E6420, and E6320, — Dual core processor in the FC-LGA6
package with a 4 MB L2 cache.
• Intel® Core™2 Duo desktop processor E6400, E6300, E4700, E4600,
E4500, E4400, and E4300— Dual core processor in the FC-LGA6 package with a
2 MB L2 cache.
• Processor — For this document, the term processor is the generic form of the
Intel® Core™2 Duo desktop processor E6000 and E4000 series and the Intel®
Core™2 Extreme processor X6800. The processor is a single package that contains
one or more execution units.
• Keep-out zone — The area on or near the processor that system design can not
use.
• Processor core — Processor core die with integrated L2 cache.
• LGA775 socket — The processors mate with the system board through a surface
mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any
mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
12
Datasheet
Introduction
• Functional operation — Refers to normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.
• Execute Disable Bit — Allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code attempts
to run in non-executable memory the processor raises an error to the operating
system. This feature can prevent some classes of viruses or worms that exploit
buffer over run vulnerabilities and can thus help improve the overall security of the
system. See the Intel® Architecture Software Developer's Manual for more detailed
information.
• Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing
the processor to execute operating systems and applications written to take
advantage of Intel 64 architecture. Further details on Intel 64 architecture and
programming model can be found in the Intel® Extended Memory 64 Technology
Software Developer Guide at http://www.intel.com/technology/intel64/index.htm.
• Enhanced Intel SpeedStep® Technology — Enhanced Intel Speedstep®
technology allows trade-offs to be made between performance and power
consumptions, based on processor utilization. This may lower average power
consumption (in conjunction with OS support).
• Intel® Virtualization Technology (Intel VT) — Intel Virtualization Technology
provides silicon-based functionality that works together with compatible Virtual
Machine Monitor (VMM) software to improve upon software-only solutions. Because
this virtualization hardware provides a new architecture upon which the operating
system can run directly, it removes the need for binary translation. Thus, it helps
eliminate associated performance overhead and vastly simplifies the design of the
VMM, in turn allowing VMMs to be written to common standards and to be more
robust. See the Intel® Virtualization Technology Specification for the IA-32 Intel®
Architecture for more details.
• Intel® Trusted Execution Technology (Intel® TXT)— Intel® Trusted Execution
Technology (Intel® TXT) is a security technology under development by Intel and
requires for operation a computer system with Intel® Virtualization Technology, a
Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS,
Authenticated Code Modules, and an Intel or other Intel Trusted Execution
Technology compatible measured virtual machine monitor. In addition, Intel Trusted
Execution Technology requires the system to contain a TPMv1.2 as defined by the
Trusted Computing Group and specific software for some uses.
Datasheet
13
Introduction
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document.
Table 1.
Reference Documents
Document
Location
www.intel.com/design/
processor/specupdt/
313279.htm
Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo
Desktop Processor E6000 and E4000 Series Specification Update
http://www.intel.com/
design/processor/
designex/317804.htm
Intel® Core™2 Duo Processor and Intel® Pentium® Dual Core
Processor Thermal and Mechanical Design Guidelines
Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme
Edition, Intel® Pentium® 4 Processor, Intel® Core™2 Duo Extreme
Processor X6800 Thermal and Mechanical Design Guidelines
http://www.intel.com/
design/pentiumXE/
designex/306830.htm
Balanced Technology Extended (BTX) System Design Guide
www.formfactors.org
http://www.intel.com/
design/processor/
applnots/313214.htm
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket
http://intel.com/design/
Pentium4/guides/
302666.htm
LGA775 Socket Mechanical Design Guide
http://www.intel.com/
technology/computing/
vptech/index.htm
Intel® Virtualization Technology Specification for the IA-32 Intel®
Architecture
Intel® Trusted Exectuion Technology (Intel® TXT) Specification for
the IA-32 Intel® Architecture
http://www.intel.com/
technology/security/
Intel® 64 and IA-32 Intel Architecture Software Developer's Manuals
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference, A-M
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
http://www.intel.com/
products/processor/
manuals/
§ §
14
Datasheet
Electrical Specifications
2
Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and
signals. DC electrical characteristics are provided.
2.1
Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power
distribution. All power lands must be connected to VCC, while all VSS lands must be
connected to a system ground plane. The processor VCC lands must be supplied the
voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as VTT provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
VTT specifications outlined in Table 5.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of
the component.
2.2.1
2.2.2
V
Decoupling
CC
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket.
VTT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To insure compliance with the specifications, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution would consist of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors.
Datasheet
15
Electrical Specifications
2.2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC pins (see Chapter 2.6.3 for VCC overshoot
specifications). Refer to Table 13 for the DC specifications for these signals. Voltages
for each processor frequency is provided in Table 5.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 5. Refer to the Intel® Core™2 Duo
Desktop Processor E6000 and E4000 Series and Intel® Core™2 Extreme Processor
X6800 Specification Update for further details on specific valid core frequency and VID
values of the processor. Note this differs from the VID employed by the processor
during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep®
Technology, or Extended HALT State).
The processor uses six voltage identification signals, VID[6:1], to support automatic
selection of power supply voltages. Table 2 specifies the voltage level corresponding to
the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to
a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket defines VID [7:0], VID7 and VID0 are not used
on the processor; VID0 and VID7 are strapped to VSS on the processor package. VID0
and VID7 must be connected to the VR controller for compatibility with future
processors.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the load
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 5 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.
The VRM or VRD used must be capable of regulating its output to the value defined by
the new VID. DC specifications for dynamic VID transitions are included in Table 5 and
Table 6. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket for further details.
16
Datasheet
Electrical Specifications
Table 2.
Voltage Identification Definition
VID6 VID5 VID4 VID3 VID2 VID1 VID (V)
VID6 VID5 VID4 VID3 VID2 VID1 VID (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
OFF
Datasheet
17
Electrical Specifications
2.4
Market Segment Identification (MSID)
The MSID[1:0] signals may be used as outputs to determine the Market Segment of
the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can
be used to prevent 130 W TDP processors from booting on boards optimized for 65 W
TDP.
Market Segment Selection Truth Table for MSID[1:0]1 2 3 4
,
,
,
Table 3.
MSID1
MSID0
Description
Intel® Core™2 Duo desktop processor E6000 and E4000 series and the
Intel® Core™2 Extreme processor X6800
0
0
0
1
0
1
Reserved
Reserved
Reserved
1
1
NOTES:
1. The MSID[1:0] signals are provided to indicate the Market Segment for the processor
and may be used for future processor compatibility or for keying. Circuitry on the
motherboard may use these signals to identify the processor installed.
2. These signals are not connected to the processor die.
3. A logic 0 is achieved by pulling the signal to ground on the package.
4. A logic 1 is achieved by leaving the signal as a no connect on the package.
2.5
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,
VTT, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.
In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 8 for details on GTL+ signals that do not include on-die termination.
Unused active high inputs, should be connected through a resistor to ground (VSS).
Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RTT). For details, see Table 14.
TAP and CMOS signals do not include on-die termination. Inputs and used outputs must
be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing.
All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor
that matches the nominal trace impedance.
18
Datasheet
Electrical Specifications
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals
However, utilization of boundary scan test will not be functional if these lands are
connected together. For optimum noise margin, all pull-up resistor values used for
TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of
the board transmission line traces. For example, if the nominal trace impedance is 50 Ω,
then a value between 40 Ω and 60 Ω should be used.
2.6
Voltage and Current Specification
2.6.1
Absolute Maximum and Minimum Ratings
Table 4 specifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and
long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Datasheet
19
Electrical Specifications
Table 4.
Absolute Maximum and Minimum Ratings
Symbol
VCC
Parameter
Min
Max
Unit Notes1, 2
Core voltage with respect to VSS
–0.3
1.55
V
V
-
-
FSB termination voltage with
respect to VSS
VTT
TC
–0.3
1.55
See
Chapter 5
See
Chapter 5
Processor case temperature
°C
°C
-
3, 4,
5
TSTORAGE
Processor storage temperature
–40
85
NOTES:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the
processor.
3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must
not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits
will not affect the long-term reliability of the device. For functional operation, refer to the
processor case temperature specifications.
4. This rating applies to the processor and does not include any tray or packaging.
5. Failure to adhere to this specification can affect the long term reliability of the processor.
2.6.2
DC Voltage and Current Specification
Table 5.
Voltage and Current Specifications
2
Symbol
VID Range
Parameter
Min
Typ
Max
Unit Notes1,
3
VID
Processor Number VCC for
0.8500
—
1.5
V
(4 MB L2 Cache)
775_VR_CONFIG_06
E6850
3.00 GHz
2.66 GHz
2.66 GHz
2.40 GHz
2.33 GHz
2.33 GHz
2.13 GHz
1.86 GHz
E6750
E6700
E6600
E6550
E6540
E6420
E6320
Processor Number VCC for
Refer to Table 6 and
Figure 1
4, 5,
6
VCC
V
(4 MB L2 Cache)
775_VR_CONFIG_05B
X6800
2.93 GHz
Processor Number VCC for
(2 MB L2 Cache)
775_VR_CONFIG_06
E6400
2.13 GHz
1.86 GHz
2.60 GHz
2.40 GHz
2.20 GHz
2.00 GHz
1.80 GHz
E6300
E4700
E4600,
E4500
E4400
E4300
VCC_BOOT
Default VCC voltage for initial power up
—
1.10
—
V
20
Datasheet
Electrical Specifications
Table 5.
Voltage and Current Specifications
2
Symbol
Parameter
Min
Typ
Max
Unit Notes1,
VCCPLL
PLL VCC
Processor Number ICC for
775_VR_CONFIG_06
- 5%
1.50
+ 5%
E6850
E6750
E6700
E6600
E6550
3.00 GHz
2.66 GHz
2.66 GHz
2.40 GHz
2.33 GHz
2.33 GHz
2.13 GHz
1.86 GHz
2.60 GHz
2.40 GHz
2.20 GHz
2.00 GHz
1.80 GHz
75
75
75
75
75
75
75
75
75
75
75
75
75
—
—
E6540
E6400/E6420
E6300/E6320
E4700
7
ICC
A
E4600
E4500
E4400
E4300
Processor Number ICC for
775_VR_CONFIG_05B
—
1.14
—
—
1.20
—
X6800
2.93 GHz
90
FSB termination voltage
(DC + AC specifications)
8
VTT
1.26
V
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per
pin
VTT_OUT_LEFT and
VTT_OUT_RIGHT ICC
9
580
mA
ICC for VTT supply before VCC stable
ICC for VTT supply after VCC stable
ICC for PLL land
4.5
4.6
10
ITT
—
—
A
ICC_VCCPLL
ICC_GTLREF
NOTES:
—
—
—
—
130
200
mA
ICC for GTLREF
μA
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
These specifications will be updated with characterized data from silicon measurements at a later date.
2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such
that two processors at the same frequency may have different settings within the VID range. Note this differs
from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep® Technology, or Extended HALT State).
4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different
voltage is required. See Section 2.3 and Table 2 for more information.
5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket
with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The
maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system
is not coupled into the oscilloscope probe.
6. Refer to Table 6 and Figure 1 for the minimum, typical, and maximum VCC allowed for a given current. The
processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given
current.
7. ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details.
8. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured
at the land.
9. Baseboard bandwidth is limited to 20 MHz.
10.This is maximum total current drawn from VTT plane by only the processor. This specification does not include
the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total ITT drawn by the
system. This parameter is based on design characterization and is not tested.
Datasheet
21
Electrical Specifications
Table 6.
VCC Static and Transient Tolerance
Voltage Deviation from VID Setting (V)1, 2, 3, 4
ICC (A)
Maximum Voltage
Typical Voltage
Minimum Voltage
1.30 mΩ
1.425 mΩ
1.55 mΩ
0
0.000
-0.007
-0.013
-0.020
-0.026
-0.033
-0.039
-0.046
-0.052
-0.059
-0.065
-0.072
-0.078
-0.085
-0.091
-0.098
-0.019
-0.026
-0.033
-0.040
-0.048
-0.055
-0.062
-0.069
-0.076
-0.083
-0.090
-0.097
-0.105
-0.112
-0.119
-0.126
-0.038
-0.046
-0.054
-0.061
-0.069
-0.077
-0.085
-0.092
-0.100
-0.108
-0.116
-0.123
-0.131
-0.139
-0.147
-0.154
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed
as shown in Section 2.6.3.
2. This table is intended to aid in reading discrete points on Figure 1.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor
VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR
implementation details.
4. Adherence to this loadline specification is required to ensure reliable processor operation.
22
Datasheet
Electrical Specifications
Figure 1.
VCC Static and Transient Tolerance
Icc [A]
40
0
10
20
30
50
60
70
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
Vcc Maximum
Vcc Typical
Vcc Minimum
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
2.
3.
This loadline specification shows the deviation from the VID set point.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline
guidelines and VR implementation details.
Datasheet
23
Electrical Specifications
2.6.3
V
Overshoot
CC
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the
maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 7.
VCC Overshoot Specifications
Symbol
Parameter
Min
Max
Unit Figure Notes
1
VOS_MAX Magnitude of VCC overshoot above VID
TOS_MAX Time duration of VCC overshoot above VID
NOTES:
—
—
50
25
mV
2
2
1
μs
1.
Adherence to these specifications is required to ensure reliable processor operation.
Figure 2.
VCC Overshoot Example Waveform
Example Overshoot Waveform
VOS
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
OS: Overshoot above VID
V
NOTES:
1.
2.
V
OS is measured overshoot voltage.
TOS is measured time duration above VID.
2.6.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 7 when measured
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in
duration may be ignored. These measurements of processor die level overshoot must
be taken with a bandwidth limited oscilloscope set to a greater than or equal to
100 MHz bandwidth limit.
24
Datasheet
Electrical Specifications
2.7
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for
GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals.
2.7.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 8 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 8.
FSB Signal Groups (Sheet 1 of 2)
Signal Group
Type
Signals1
GTL+ Common
Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#,
HIT#, HITM#, LOCK#
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#3
A[35:17]#3
ADSTB0#
ADSTB1#
GTL+ Source
Synchronous I/O
Synchronous to
assoc. strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Synchronous to
BCLK[1:0]
GTL+ Strobes
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Datasheet
25
Electrical Specifications
Table 8.
FSB Signal Groups (Sheet 2 of 2)
Signal Group
Type
Signals1
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
SMI#, STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#,
BSEL[2:0], VID[6:1]
CMOS
Open Drain Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO
PROCHOT#4
Open Drain Input/
Output
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]2
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Power/Other
NOTES:
1.
2.
Refer to Section 4.2 for signal descriptions.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
3.
4.
PROCHOT# signal type is open drain output and CMOS input.
.
Table 9.
Signal Characteristics
Signals with RTT
Signals with No RTT
A20M#, BCLK[1:0], BSEL[2:0],
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:1], GTLREF[1:0], TCK, TDI, TMS,
TRST#, VTT_SEL, MSID[1:0]
Open Drain Signals1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, FCx
NOTES:
1. Signals that do not have RTT, nor are actively driven to their high-voltage level.
.
Table 10.
Signal Reference Voltages
GTLREF
VTT/2
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD1, SMI#, STPCLK#, TCK1,
TDI1, TMS1, TRST#1
NOTES:
1. These signals also have hysteresis added to the reference voltage. See Table 12 for more
information.
26
Datasheet
Electrical Specifications
2.7.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least four BCLKs in order for the processor to recognize the proper
signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing
requirements for entering and leaving the low power states.
2.7.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 11.
GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes1
2,
3
VIL
VIH
VOH
Input Low Voltage
Input High Voltage
Output High Voltage
-0.10
GTLREF – 0.10
VTT + 0.10
VTT
V
V
V
4, 5,
5, 3
3
GTLREF + 0.10
VTT – 0.10
VTT_MAX
[(RTT_MIN)+(2*RON_MIN)]
/
IOL
ILI
Output Low Current
N/A
N/A
N/A
10
A
-
6
Input Leakage Current
± 100
µA
µA
Ω
Output Leakage
Current
7
ILO
± 100
13
RON
Buffer On Resistance
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low
value.
3. The VTT referred to in these specifications is the instantaneous VTT.
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high
value.
5. VIH and VOH may experience excursions above VTT.
6. Leakage to VSS with land held at VTT.
7. Leakage to VTT with land held at 300 mV.
.
Table 12.
Open Drain and TAP Output Signal Group DC Specifications
Symbol
Parameter
Output Low Voltage
Min
Max
Unit Notes1
VOL
VOH
0
0.20
V
V
-
2
Output High Voltage
Output Low Current
Output Leakage Current
VTT – 0.05 VTT + 0.05
3
4
IOL
16
50
mA
µA
ILO
N/A
± 200
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VOH is determined by the value of the external pull-up resister to VTT.
3. Measured at VTT * 0.2.
4. For Vin between 0 and VOH
.
Datasheet
27
Electrical Specifications
.
Table 13.
CMOS Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Min
Max
Unit Notes1
2,
3
VIL
VIH
-0.10
VTT * 0.70
-0.10
VTT * 0.30
VTT + 0.10
VTT * 0.10
VTT + 0.10
4.70
V
V
3, 4, 5
Input High Voltage
3
3, 6, 5
3, 7
3, 7
8
VOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Input Leakage Current
Output Leakage Current
V
VOH
IOL
0.90 * VTT
1.70
V
mA
mA
µA
µA
IOH
1.70
4.70
ILI
N/A
± 100
9
ILO
N/A
± 100
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low
value.
3. The VTT referred to in these specifications refers to instantaneous VTT.
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high
value.
5. VIH and VOH may experience excursions above VTT.
6. All outputs are open drain.
7. IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT.
8. Leakage to VSS with land held at VTT.
9. Leakage to VTT with land held at 300 mV.
2.7.3.1
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 9 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
Table 14.
GTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units Notes1
2
GTLREF_PU GTLREF pull up resistor
GTLREF_PD GTLREF pull down resistor
124 * 0.99
210 * 0.99
45
124
210
124 * 1.01
210 * 1.01
55
Ω
2
Ω
3
RTT
Termination Resistance
COMP Resistance
50
Ω
4
COMP[3:0]
COMP8
NOTES:
49.40
49.90
24.90
50.40
Ω
4
COMP Resistance
24.65
25.15
Ω
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each
GTLEREF land).
3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
4. COMP resistance must be provided on the system board with 1% resistors. See the applicable
platform design guide for implementation details. COMP[3:0] and COMP8 resistors are tied to
VSS
.
28
Datasheet
Electrical Specifications
2.7.4
2.7.5
Clock Specifications
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to Table 15 for the processor supported
ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel Field representative. Platforms using a CK505
Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8.
Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications
in Section 2.7.9.
Table 15.
Core Frequency to FSB Multiplier Configuration
Multiplication of
Core Frequency
Core Frequency
Core Frequency
System Core
Frequency to FSB
Frequency
(200 MHz BCLK/ (266 MHz BCLK/
(333 MHz BCLK/ Notes1, 2
1333 MHz FSB)
800 MHz FSB)
1066 MHz FSB)
1/6
1/7
1.20 GHz
1.40 GHz
1.60 GHz
1.80 GHz
2 GHz
1.60 GHz
1.87 GHz
2.13 GHz
2.40 GHz
2.66 GHz
2.93 GHz
3.20 GHz
2.00 GHz
2.33 GHz
2.66 GHz
3.00 GHz
3.33 GHz
3.66 GHz
4.00 GHz
-
-
-
-
-
-
1/8
1/9
1/10
1/11
2.2 GHz
2.4 GHz
1/12
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
2.7.6
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 16 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 operate at
1333 MHz (selected by the 333 MHz BCLK[2:0] frequency). The Intel Core2 Duo
desktop processors E6700, E6600, E6420, E6400, E6320, and E6300 operate at
1066 MHz (selected by the 266 MHz BCLK[2:0] frequency). The Intel Core2 Extreme
processor X6800 operates at a 1066 MHz FSB frequency (selected by a 266 MHz
BCLK[1:0] frequency). The Intel Core2 Duo desktop processors E4700, E4600, E4500,
E4400 and E4300 operate at a 800 MHz FSB frequency (selected by a 200 MHz
BCLK[1:0] frequency).
Datasheet
29
Electrical Specifications
Table 16.
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
L
L
H
H
L
266 MHz
RESERVED
RESERVED
200 MHz
L
H
H
H
H
L
L
H
H
H
H
L
RESERVED
RESERVED
RESERVED
333 MHz
H
H
L
L
2.7.7
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 5 for DC specifications.
2.7.8
BCLK[1:0] Specifications (CK505 based Platforms)
Table 17.
Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit Figure Notes1
2
VL
Input Low Voltage
Input High Voltage
-0.30
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
N/A
1.15
0.550
0.140
1.4
V
V
3
3
2
VH
3, 4,
5
VCROSS(abs) Absolute Crossing Point
0.300
N/A
V
3, 4
3, 4
3
4
6
6
7
ΔVCROSS
VOS
Range of Crossing Points
Overshoot
V
N/A
V
VUS
Undershoot
-0.300
0.300
-5
N/A
V
3
VSWING
ILI
Differential Output Swing
Input Leakage Current
Pad Capacitance
N/A
V
5
5
μA
pF
8
Cpad
.95
1.45
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. "Steady state" voltage, not including overshoot or undershoot.
3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0
equals the falling edge of BCLK1.
4. VHavg is the statistical average of the VH measured by the oscilloscope.
5. The crossing point must meet the absolute and relative crossing point specifications
simultaneously.
6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as
the absolute value of the minimum voltage.
7. Measurement taken from differential waveform.
8. Cpad includes die capacitance only. No package parasitics are included.
30
Datasheet
Electrical Specifications
Figure 3.
Differential Clock Waveform
CLK 0
VCROSS Max
550 mV
VCROSS
Median + 75 mV
VCROSS
VCROSS
median
median
VCROSS
VCROSS Min
300 mV
Median - 75 mV
CLK 1
High Time
Low Time
Period
Figure 4.
Differential Clock Crosspoint Specification
650
600
550
500
550 mV
550 + 0.5 (VHavg - 700)
450
400
300 + 0.5 (VHavg - 700)
350
300
250
200
300 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 5.
Differential Measurements
Slew_rise
Slew _fall
+150 mV
0.0V
+150mV
0.0V
V_swing
-150 mV
-150mV
Diff
Datasheet
31
Electrical Specifications
2.7.9
BCLK[1:0] Specifications (CK410 based Platforms)
Table 18.
Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit Figure Notes1
VL
Input Low Voltage
Input High Voltage
-0.150
0.660
0.000
0.700
N/A
V
V
3
3
-
-
VH
0.850
Absolute Crossing
Point
2,
3
VCROSS(abs)
VCROSS(rel)
ΔVCROSS
0.250
N/A
N/A
N/A
0.550
V
V
V
3, 4
3, 4
3, 4
Relative Crossing
Point
0.250 +
0.5(VHavg – 0.700)
0.550 +
0.5(VHavg – 0.700)
4, 3, 5
Range of Crossing
Points
N/A
0.140
-
6
7
8
9
VOS
VUS
Overshoot
N/A
-0.300
N/A
N/A
N/A
N/A
VH + 0.3
N/A
V
V
V
V
3
3
3
3
Undershoot
VRBM
Ringback Margin
Threshold Region
0.200
N/A
VTM
VCROSS – 0.100
VCROSS + 0.100
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
3. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
4. VHavg is the statistical average of the VH measured by the oscilloscope.
5. VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes.
6. Overshoot is defined as the absolute value of the maximum voltage.
7. Undershoot is defined as the absolute value of the minimum voltage.
8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
Figure 6.
Differential Clock Crosspoint Specification
650
600
550
500
550 mV
550 + 0.5 (VHavg - 700)
450
400
250 + 0.5 (VHavg - 700)
350
300
250
200
250 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
32
Datasheet
Electrical Specifications
2.8
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors (may also include chipset components in the future) and
external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital
converters calibrated at the factory for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
Table 19.
PECI DC Electrical Limits
Symbol
Definition and Conditions
Input Voltage Range
Min
Max
Units Notes1
Vin
-0.15
VTT
—
V
2
Vhysteresis Hysteresis
0.1 * VTT
V
Vn
Vp
Negative-edge threshold voltage
0.275 * VTT
0.550 * VTT
0.500 * VTT
0.725 * VTT
V
V
Positive-edge threshold voltage
High level output source
(VOH = 0.75 * VTT)
Isource
-6.0
0.5
N/A
1.0
mA
mA
Low level output sink
(VOL = 0.25 * VTT)
Isink
3
Ileak+
Ileak-
High impedance state leakage to VTT
High impedance leakage to GND
Bus capacitance per node
N/A
N/A
50
10
10
—
µA
3
µA
4
Cbus
N/A
pF
Vnoise
Signal noise immunity above 300 MHz
0.1 * VTT
Vp-p
NOTES:
1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer
to Table 4 for VTT specifications.
2. The input buffers use a Schmitt-triggered input design for improved noise immunity.
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
§ §
Datasheet
33
Electrical Specifications
34
Datasheet
Package Mechanical Specifications
3
Package Mechanical
Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that
interfaces with the motherboard via an LGA775 socket. The package consists of a
processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)
is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 7 shows a sketch of
the processor package components and how they are assembled together. Refer to the
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
The package components shown in Figure 7 include the following:
• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors
Figure 7.
Processor Package Assembly Sketch
Core (die)
TIM
IHS
Substrate
Capacitors
LGA775 Socket
System Board
NOTE:
1.
Socket and System Board are included for reference and are not part of processor
package.
3.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 8 and Figure 9. The drawings
include dimensions necessary to design a thermal solution for the processor. These
dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the processor Thermal and
Mechanical Design Guidelines.
Datasheet
35
Package Mechanical Specifications
Figure 8.
Processor Package Drawing Sheet 1 of 3
36
Datasheet
Package Mechanical Specifications
Figure 9.
Processor Package Drawing Sheet 2 of 3
Datasheet
37
Package Mechanical Specifications
Figure 10.
Processor Package Drawing Sheet 3 of 3
38
Datasheet
Package Mechanical Specifications
3.1.1
3.1.2
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keep-
out zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 8 and Figure 9 for keep-out
zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
Package Loading Specifications
Table 20 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solution. The minimum loading specification must be
maintained by any thermal and mechanical solutions.
.
Table 20.
Processor Loading Specifications
Parameter
Minimum
Maximum
Notes
1, 2,
3
Static
80 N [17 lbf]
—
311 N [70 lbf]
756 N [170 lbf]
1, 3, 4
Dynamic
NOTES:
1. These specifications apply to uniform compressive loading in a direction normal to the
processor IHS.
2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also
provide the minimum specified load on the processor package.
3. These specifications are based on limited testing for design characterization. Loading limits are
for the package only and do not include the limits of the processor socket.
4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
3.1.3
Package Handling Guidelines
Table 21 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 21.
Package Handling Guidelines
Parameter
Maximum Recommended
Notes
1,
2
Shear
Tensile
Torque
311 N [70 lbf]
111 N [25 lbf]
2, 3
2, 4
3.95 N-m [35 lbf-in]
NOTES:
1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2. These guidelines are based on limited testing for design characterization.
3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS
surface.
4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the
IHS top surface.
Datasheet
39
Package Mechanical Specifications
3.1.4
3.1.5
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The
socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all
the components that are included in the package.
3.1.6
Processor Materials
Table 22 lists some of the package components and associated materials.
Table 22.
Processor Materials
Component
Material
Integrated Heat Spreader (IHS)
Substrate
Nickel Plated Copper
Fiber Reinforced Resin
Gold Plated Copper
Substrate Lands
3.1.7
Processor Markings
Figure 11 through Figure 15show the topside markings on the processor. The diagrams
are to aid in the identification of the processor.
Figure 11.
Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processor E6000 Series with 4 MB L2 Cache with 1333 MHz FSB
M
INTEL ©'05 E6850
INTEL® CORE™2 DUO
SLxxx [COO]
3.00GHZ/4M/1333/06
e4
[FPO]
ATPO
S/N
40
Datasheet
Package Mechanical Specifications
Figure 12.
Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB
M
INTEL ©'05
INTEL® CORE™2 DUO
6700 SLxxx [COO]
2.66GHZ/4M/1066/06
e4
[FPO]
ATPO
S/N
Figure 13.
Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processors E6000 Series with 2 MB L2 Cache
M
INTEL ©'05
INTEL® CORE™2 DUO
6400 SLxxx [COO]
2.13GHZ/2M/1066/06
e4
[FPO]
ATPO
S/N
Datasheet
41
Package Mechanical Specifications
Figure 14.
Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop
Processors E4000 Series with 2 MB L2 Cache
M
INTEL ©'05 E4500
INTEL® CORE™2 DUO
SLxxx [COO]
2.20GHZ/2M/800/06
e4
[FPO]
ATPO
S/N
E
E
Figure 15.
Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800
M
INTEL ©'05
INTEL® CORE™2 EXTREME
6800 SLxxx [COO]
2.93GHZ/4M/1066/05B
e4
[FPO]
ATPO
S/N
42
Datasheet
Package Mechanical Specifications
3.1.8
Processor Land Coordinates
Figure 16 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
.
Figure 16.
Processor Land Coordinates and Quadrants (Top View)
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
Socket 775
Quadrants
Top View
W
V
W
Address/
UV Common Clock/
U
T
T
Async
R
R
P
N
M
L
P
N
M
L
K
K
J
J
H
H
G
F
G
F
E
E
D
C
B
A
D
C
B
A
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
VTT / Clocks
Data
§ §
Datasheet
43
Package Mechanical Specifications
44
Datasheet
Land Listing and Signal Descriptions
4
Land Listing and Signal
Descriptions
This chapter provides the processor land assignment and signal descriptions.
4.1
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
in Figure 17 and Figure 18. These figures represent the land-out arranged by land
number and they show the physical location of each signal on the package land array
(top view). Table 23 provides a listing of all processor lands ordered alphabetically by
land (signal) name. Table 24 provides a listing of all processor lands ordered by land
number.
Datasheet
45
Land Listing and Signal Descriptions
Figure 17.
land-out Diagram (Top View – Left Side)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AN
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
AA
Y
W
V
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
U
T
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
P
N
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M
L
K
J
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
FC34
VSS
FC31
FC33
VCC
H
BSEL1
BSEL2
FC15
FC32
BSEL0
RSVD
FC26
VTT
BCLK1
BCLK0
VSS
TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET#
D47#
VSS
D44#
D43#
D42#
VSS
DSTBN2# DSTBP2#
D35#
D38#
D39#
VSS
D36#
D37#
VSS
D32#
VSS
D31#
D30#
D33#
VSS
G
F
VTT_SEL TESTHI0 TESTHI2 TESTHI7
RSVD
RSVD
D41#
VSS
VSS
VSS
VTT
VSS
VTT
VSS
VTT
FC10
VSS
D45#
D46#
D40#
DBI2#
D34#
RSVD
E
D
VTT
VTT
VTT
VCCPLL
D48#
D49#
VCCIO
PLL
VTT
VTT
VTT
VTT
VTT
VSS
VSS
D58#
DBI3#
VSS
D54#
DSTBP3#
VSS
D51#
C
B
A
VTT
VTT
30
VTT
VTT
29
VTT
VTT
28
VTT
VTT
27
VTT
VTT
26
VTT
VTT
25
VSS
FC23
24
VSSA
VCCA
23
D63#
D62#
22
D59#
VSS
21
VSS
RSVD
20
D60#
D61#
19
D57#
VSS
18
VSS
D56#
17
D55#
DSTBN3#
16
D53#
VSS
15
46
Datasheet
Land Listing and Signal Descriptions
Figure 18.
land-out Diagram (Top View – Right Side)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VID_SELE
CT
VSS_MB_
REGULATION
VCC_MB_
REGULATION
VSS_
SENSE
VCC_
SENSE
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
AN
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VID7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC40
VID3
FC8
VID6
VID1
VSS
VID5
VID4
VSS
VID2
VRDSEL
ITP_CLK0
ITP_CLK1
VSS
VID0
PROCHOT#
VSS
VSS
THERMDA
THERMDC
BPM1#
VSS
AM
AL
AK
AJ
VCC
VSS
VCC
A35#
VSS
A34#
A33#
A31#
A27#
VSS
BPM0#
RSVD
VCC
A32#
A30#
A28#
RSVD
VSS
AH
AG
AF
AE
AD
AC
AB
VCC
A29#
VSS
BPM5#
VSS
BPM3#
BPM4#
VSS
TRST#
TDO
VCC
SKTOCC#
VCC
RSVD
A22#
VSS
FC18
TCK
ADSTB1#
A25#
A24#
FC36
BPM2#
DBR#
TDI
VCC
RSVD
A26#
VSS
TMS
VCC
A17#
FC37
IERR#
VSS
VTT_OUT_
RIGHT
VCC
VCC
VCC
VSS
VSS
VSS
VSS
A23#
VSS
A21#
A20#
VSS
VSS
FC17
FC39
VSS
AA
Y
A19#
A18#
FC0
TESTHI12/
FC44
A16#
TESTHI1
MSID0
W
VCC
VCC
VCC
VSS
VSS
VSS
VSS
A10#
VSS
A14#
A12#
A9#
A15#
A13#
A11#
VSS
FC30
VSS
RSVD
FC29
FC4
MSID1
FC28
V
U
T
COMP1
FERR#/
PBE#
VCC
VSS
ADSTB0#
VSS
A8#
VSS
COMP3
R
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
A4#
VSS
RSVD
RSVD
A5#
VSS
RSVD
A7#
INIT#
VSS
SMI#
TESTHI11
PWRGOOD
VSS
P
N
M
L
IGNNE#
REQ2#
VSS
STPCLK# THERMTRIP#
A3#
A6#
VSS
TESTHI13
VSS
LINT1
REQ3#
VSS
REQ0#
A20M#
LINT0
K
VTT_OUT_
LEFT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VSS
REQ4#
VSS
REQ1#
TESTHI10
PECI
VSS
FC22
VSS
FC3
J
H
FC35
GTLREF1
COMP2
GTLREF0
FC27
TESTHI9/
FC43
TESTHI8/
FC42
D29#
D27#
DSTBN1#
DBI1#
FC38
D16#
BPRI#
DEFER#
RSVD
G
D28#
VSS
VSS
D24#
DSTBP1#
VSS
D23#
VSS
VSS
D18#
D19#
VSS
D17#
VSS
VSS
FC21
RSVD
VSS
RS1#
FC20
VSS
VSS
HITM#
HIT#
BR0#
TRDY#
VSS
FC5
VSS
F
E
D
C
D26#
D25#
D21#
D22#
RSVD
D20#
RSVD
D15#
D12#
ADS#
RSVD
DRDY#
VSS
D52#
VSS
D14#
D11#
VSS
FC38
DSTBN0#
VSS
D3#
D1#
VSS
LOCK#
BNR#
VSS
D50#
14
COMP8
COMP0
13
D13#
VSS
12
VSS
D9#
11
D10#
D8#
10
DSTBP0#
VSS
VSS
DBI0#
8
D6#
D7#
7
D5#
VSS
6
VSS
D4#
5
D0#
D2#
4
RS0#
RS2#
3
DBSY#
VSS
2
B
A
9
1
Datasheet
47
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
A3#
A4#
L5
P6
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
BNR#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BR0#
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
COMP8
D0#
C2
Common Clock Input/Output
AJ2 Common Clock Input/Output
AJ1 Common Clock Input/Output
AD2 Common Clock Input/Output
AG2 Common Clock Input/Output
AF2 Common Clock Input/Output
AG3 Common Clock Input/Output
A5#
M5
L4
A6#
A7#
M4
R4
T5
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A20M#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADS#
ADSTB0#
ADSTB1#
BCLK0
BCLK1
U6
T4
G8
F3
Common Clock
Input
Common Clock Input/Output
U5
U4
V5
V4
W5
AB6
W6
Y6
G29
H30
G30
A13
T1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Input
Input
G2
Input
R1
Input
B13
B4
Input
Y4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
K3
AA4
Asynch CMOS
Input
D1#
C5
Source Synch Input/Output
D2#
A4
AD6 Source Synch Input/Output
D3#
C6
AA5
AB5
AC5
AB4
AF5
AF4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
D4#
A5
D5#
B6
D6#
B7
D7#
A7
D8#
A10
A11
B10
C11
D8
D9#
AG6 Source Synch Input/Output
AG4 Source Synch Input/Output
AG5 Source Synch Input/Output
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
AH4
AH5
AJ5
AJ6
D2
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Common Clock Input/Output
Source Synch Input/Output
B12
C12
D11
G9
F8
R6
F9
AD5 Source Synch Input/Output
E9
F28
Clock
Clock
Input
Input
D7
G28
E10
48
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
D61#
D62#
A19
A22
B22
A8
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
D63#
DBI0#
DBI1#
DBI2#
DBI3#
DBR#
DBSY#
DEFER#
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FC0
G11
D19
C20
AC2
B2
Power/Other
Common Clock Input/Output
Common Clock Input
Output
G7
C1
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
C8
G12
G20
A16
B9
E12
G19
C17
Y1
FC3
J2
Power/Other
FC4
T2
Power/Other
FC5
F2
Power/Other
FC8
AK6
E24
H29
Y3
Power/Other
FC10
Power/Other
FC15
Power/Other
FC17
Power/Other
FC18
AE3
E5
Power/Other
FC20
Power/Other
FC21
F6
Power/Other
FC22
J3
Power/Other
FC23
A24
E29
G1
Power/Other
FC26
Power/Other
FC27
Power/Other
FC28
U1
Power/Other
FC29
U2
Power/Other
FC30
U3
Power/Other
FC31
J16
H15
Power/Other
FC32
Power/Other
Datasheet
49
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
FC33
FC34
H16
J17
H4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Power/Other
Power/Other
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
RS0#
D16
E23
E6
FC35
FC36
AD3
AB3
G10
C9
E7
FC37
F23
F29
G6
N4
FC38
FC38
FC39
AA2
AM6
R3
FC40
N5
FERR#/PBE#
GTLREF0
GTLREF1
HIT#
Output
Input
Input
P5
H1
V2
H2
G23 Common Clock
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
Input
Input
Input
Input
D4
Common Clock Input/Output
Common Clock Input/Output
B3
F5
Common Clock
Common Clock
Common Clock
Power/Other
Asynch CMOS
Asynch CMOS
TAP
HITM#
E4
RS1#
IERR#
AB2
N2
Asynch CMOS
Asynch CMOS
Asynch CMOS
TAP
Output
Input
Input
Input
Input
Input
Input
RS2#
A3
IGNNE#
INIT#
SKTOCC#
SMI#
AE8
P2
P3
ITP_CLK0
ITP_CLK1
LINT0
AK3
AJ3
K1
STPCLK#
TCK
M3
AE1
AD1
AF1
F26
W3
H5
TAP
Asynch CMOS
Asynch CMOS
TDI
TAP
LINT1
L1
TDO
TAP
LOCK#
C3
Common Clock Input/Output
TESTHI0
TESTHI1
TESTHI10
TESTHI11
Power/Other
Power/Other
Power/Other
Power/Other
MSID0
W1
V1
Power/Other
Power/Other
Output
Output
MSID1
PECI
G5
Power/Other Input/Output
Asynch CMOS Input/Output
P1
PROCHOT#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
AL2
N1
TESTHI12/
FC44
W2
Power/Other
Input
Power/Other
Input
TESTHI13
TESTHI2
L2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
TAP
Input
Input
Input
Input
Input
Input
Input
Input
Input
K4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
F25
G25
G27
G26
G24
F24
G3
J5
TESTHI3
M6
K6
TESTHI4
TESTHI5
J6
TESTHI6
A20
AC4
AE4
AE6
AH2
D1
TESTHI7
TESTHI8/FC42
TESTHI9/FC43
THERMDA
THERMDC
THERMTRIP#
TMS
G4
AL1
AK1
M2
Output
Input
D14
AC1
50
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
TRDY#
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E3
Common Clock
TAP
Input
Input
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF22
AF8
Power/Other
Power/Other
Power/Other
AG1
AA8
AB8
Power/Other
Power/Other
AF9
AG11 Power/Other
AG12 Power/Other
AG14 Power/Other
AG15 Power/Other
AG18 Power/Other
AG19 Power/Other
AG21 Power/Other
AG22 Power/Other
AG25 Power/Other
AG26 Power/Other
AG27 Power/Other
AG28 Power/Other
AG29 Power/Other
AG30 Power/Other
AC23 Power/Other
AC24 Power/Other
AC25 Power/Other
AC26 Power/Other
AC27 Power/Other
AC28 Power/Other
AC29 Power/Other
AC30 Power/Other
AC8
Power/Other
AD23 Power/Other
AD24 Power/Other
AD25 Power/Other
AD26 Power/Other
AD27 Power/Other
AD28 Power/Other
AD29 Power/Other
AD30 Power/Other
AG8
AG9
Power/Other
Power/Other
AH11 Power/Other
AH12 Power/Other
AH14 Power/Other
AH15 Power/Other
AH18 Power/Other
AH19 Power/Other
AH21 Power/Other
AH22 Power/Other
AH25 Power/Other
AH26 Power/Other
AH27 Power/Other
AH28 Power/Other
AH29 Power/Other
AH30 Power/Other
AD8
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23
AE9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AH8
AH9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AJ11
AJ12
AJ14
AJ15
Datasheet
51
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AM19 Power/Other
AM21 Power/Other
AM22 Power/Other
AM25 Power/Other
AM26 Power/Other
AM29 Power/Other
AM30 Power/Other
AJ9
AM8
AM9
Power/Other
Power/Other
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AN11 Power/Other
AN12 Power/Other
AN14 Power/Other
AN15 Power/Other
AN18 Power/Other
AN19 Power/Other
AN21 Power/Other
AN22 Power/Other
AN25 Power/Other
AN26 Power/Other
AN29 Power/Other
AN30 Power/Other
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AN8
AN9
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AL9
AM11 Power/Other
AM12 Power/Other
AM14 Power/Other
AM15 Power/Other
AM18 Power/Other
52
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J28
J29
J30
J8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T27
T28
T29
T30
T8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J9
K23
K24
K25
K26
K27
K28
K29
K30
K8
U23
U24
U25
U26
U27
U28
U29
U30
U8
L8
V8
M23
M24
M25
M26
M27
M28
M29
M30
M8
W23
W24
W25
W26
W27
W28
W29
W30
W8
N23
N24
N25
N26
N27
N28
N29
N30
N8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y8
P8
VCC_MB_
REGULATION
AN5
Power/Other
Output
Output
R8
VCC_SENSE
VCCA
AN3
A23
C23
D23
AN7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
T23
T24
T25
T26
VCCIOPLL
VCCPLL
VID_SELECT
Output
Datasheet
53
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VRDSEL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM2
AL5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Output
Output
Output
Output
Output
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC7
AD4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AM3
AL6
AD7
AE10
AE13
AE16
AE17
AE2
AK4
AL4
AM5
AM7
AL3
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE5
A12
A15
A18
A2
A21
A6
A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AE7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AF30
AF6
AF7
AG10 Power/Other
AG13 Power/Other
AG16 Power/Other
AG17 Power/Other
AG20 Power/Other
AC3
AC6
54
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG23 Power/Other
AG24 Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK5
AK7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AG7
AH1
Power/Other
Power/Other
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL7
AH10 Power/Other
AH13 Power/Other
AH16 Power/Other
AH17 Power/Other
AH20 Power/Other
AH23 Power/Other
AH24 Power/Other
AH3
AH6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AM1
AH7
AM10 Power/Other
AM13 Power/Other
AM16 Power/Other
AM17 Power/Other
AM20 Power/Other
AM23 Power/Other
AM24 Power/Other
AM27 Power/Other
AM28 Power/Other
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AM4
AN1
Power/Other
Power/Other
AN10 Power/Other
AN13 Power/Other
AN16 Power/Other
AN17 Power/Other
AJ7
AK10 Power/Other
AK13 Power/Other
AK16 Power/Other
AK17 Power/Other
AN2
Power/Other
AN20 Power/Other
AN23 Power/Other
AN24 Power/Other
AN27 Power/Other
AN28 Power/Other
AK2
Power/Other
AK20 Power/Other
AK23 Power/Other
AK24 Power/Other
AK27 Power/Other
AK28 Power/Other
AK29 Power/Other
AK30 Power/Other
B1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B11
B14
B17
B20
Datasheet
55
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B24
B5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B8
C10
C13
C16
C19
C22
C24
C4
C7
D12
D15
D18
D21
D24
D3
H6
D5
H7
D6
H8
D9
H9
E11
E14
E17
E2
J4
J7
K2
K5
E20
E25
E26
E27
E28
E8
K7
L23
L24
L25
L26
L27
L28
L29
L3
F10
F13
F16
F19
F22
F4
L30
L6
L7
F7
M1
H10
H11
M7
N3
56
Datasheet
Land Listing and Signal Descriptions
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Signal Buffer
Land Signal Buffer
Land Name
Direction
Land Name
Direction
#
Type
#
Type
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N6
N7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
W7
Y2
Y5
Y7
Power/Other
Power/Other
Power/Other
Power/Other
P23
P24
P25
P26
P27
P28
P29
P30
P4
VSS_MB_
REGULATION
AN6
Power/Other
Output
Output
VSS_SENSE
VSSA
VTT
AN4
B23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
J1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT
P7
VTT
R2
VTT
R23
R24
R25
R26
R27
R28
R29
R30
R5
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
R7
VTT
T3
VTT
T6
VTT
T7
VTT
U7
VTT
V23
V24
V25
V26
V27
V28
V29
V3
VTT
VTT
VTT
VTT
VTT_OUT_LEFT
Output
Output
Output
VTT_OUT_RIG
HT
AA1
F27
Power/Other
Power/Other
VTT_SEL
V30
V6
V7
W4
Datasheet
57
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
A2
A3
VSS
Power/Other
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C1
VSS
D13#
COMP8
VSS
Power/Other
RS2#
D02#
D04#
VSS
Common Clock
Input
Source Synch Input/Output
A4
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Input
A5
A6
D53#
D55#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A7
D07#
DBI0#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A8
A9
D57#
D60#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
B1
D08#
D09#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D59#
D63#
VSSA
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
COMP0
D50#
VSS
Power/Other
Input
Source Synch Input/Output
Power/Other
Power/Other
DSTBN3#
D56#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
VTT
Power/Other
VTT
Power/Other
D61#
RESERVED
VSS
Source Synch Input/Output
VTT
Power/Other
VTT
Power/Other
Power/Other
VTT
Power/Other
D62#
VCCA
FC23
VTT
Source Synch Input/Output
Power/Other
DRDY#
BNR#
LOCK#
VSS
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Power/Other
C2
Power/Other
C3
Power/Other
C4
VTT
Power/Other
C5
D01#
D03#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
C6
VTT
Power/Other
C7
VTT
Power/Other
C8
DSTBN0#
FC38
VSS
Source Synch Input/Output
Power/Other
VTT
Power/Other
C9
VSS
Power/Other
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
Power/Other
B2
DBSY#
RS0#
D00#
VSS
Common Clock Input/Output
D11#
D14#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B3
Common Clock
Input
B4
Source Synch Input/Output
Power/Other
B5
D52#
D51#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B6
D05#
D06#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B7
B8
DSTBP3#
D54#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
B9
DSTBP0#
D10#
Source Synch Input/Output
Source Synch Input/Output
B10
58
Datasheet
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D1
DBI3#
D58#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D29
D30
E2
VTT
VTT
VSS
Power/Other
Power/Other
Power/Other
VCCIOPLL
VSS
Power/Other
E3
TRDY#
HITM#
FC20
Common Clock
Input
Power/Other
E4
Common Clock Input/Output
Power/Other
VTT
Power/Other
E5
VTT
Power/Other
E6
RESERVED
RESERVED
VSS
VTT
Power/Other
E7
VTT
Power/Other
E8
Power/Other
VTT
Power/Other
E9
D19#
D21#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
F2
RESERVED
ADS#
VSS
D2
Common Clock Input/Output
Power/Other
DSTBP1#
D26#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D3
D4
HIT#
VSS
Common Clock Input/Output
Power/Other
D5
D33#
D34#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D6
VSS
Power/Other
D7
D20#
D12#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D8
D39#
D40#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D22#
D15#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D42#
D45#
RESERVED
FC10
Source Synch Input/Output
Source Synch Input/Output
D25#
RESERVED
VSS
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
VSS
RESERVED
D49#
VSS
VSS
Power/Other
Source Synch Input/Output
Power/Other
VSS
Power/Other
VSS
Power/Other
DBI2#
D48#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
FC26
Power/Other
FC5
Power/Other
F3
BR0#
VSS
Common Clock Input/Output
Power/Other
D46#
VCCPLL
VSS
Source Synch Input/Output
Power/Other
F4
F5
RS1#
FC21
Common Clock
Power/Other
Power/Other
Input
Power/Other
F6
VTT
Power/Other
F7
VSS
VTT
Power/Other
F8
D17#
D18#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VTT
Power/Other
F9
VTT
Power/Other
F10
Datasheet
59
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
G1
D23#
D24#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
H1
D44#
D47#
RESET#
TESTHI6
TESTHI3
TESTHI5
TESTHI4
BCLK1
BSEL0
BSEL2
GTLREF0
GTLREF1
VSS
Source Synch Input/Output
Source Synch Input/Output
VSS
Common Clock
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
D28#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D30#
VSS
D37#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D38#
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D41#
Source Synch Input/Output
Source Synch Input/Output
Power/Other
D43#
VSS
H2
RESERVED
TESTHI7
TESTHI2
TESTHI0
VTT_SEL
BCLK0
H3
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Input
Input
Input
Output
Input
H4
FC35
TESTHI10
VSS
H5
Input
H6
H7
VSS
H8
VSS
RESERVED
FC27
H9
VSS
Power/Other
Power/Other
Power/Other
Power/Other
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
VSS
G2
COMP2
TESTHI8/FC42
TESTHI9/FC43
PECI
Input
Input
Input
VSS
G3
VSS
G4
VSS
G5
Power/Other Input/Output
VSS
G6
RESERVED
DEFER#
BPRI#
FC32
FC33
VSS
G7
Common Clock
Common Clock
Input
Input
G8
G9
D16#
Source Synch Input/Output
Power/Other
VSS
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
FC38
VSS
DBI1#
DSTBN1#
D27#
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
VSS
VSS
VSS
D29#
VSS
D31#
VSS
D32#
VSS
D36#
VSS
D35#
VSS
DSTBP2#
DSTBN2#
VSS
FC15
60
Datasheet
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
Type
H30
J1
BSEL1
VTT_OUT_LEFT
FC3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
K23
K24
K25
K26
K27
K28
K29
K30
L1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J2
J3
FC22
VSS
J4
J5
REQ1#
REQ4#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J6
J7
J8
VCC
LINT1
TESTHI13
VSS
Asynch CMOS
Power/Other
Power/Other
Input
Input
J9
VCC
L2
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K1
VCC
L3
VCC
L4
A06#
A03#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
L5
VCC
L6
VCC
L7
VSS
Power/Other
VCC
L8
VCC
Power/Other
FC31
FC34
VCC
L23
L24
L25
L26
L27
L28
L29
L30
M1
VSS
Power/Other
VSS
Power/Other
VSS
Power/Other
VCC
VSS
Power/Other
VCC
VSS
Power/Other
VCC
VSS
Power/Other
VCC
VSS
Power/Other
VCC
VSS
Power/Other
VCC
VSS
Power/Other
VCC
M2
THERMTRIP#
STPCLK#
A07#
A05#
REQ2#
VSS
Asynch CMOS
Asynch CMOS
Output
Input
VCC
M3
VCC
M4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
M5
VCC
M6
VCC
M7
LINT0
VSS
Asynch CMOS
Power/Other
Asynch CMOS
Input
M8
VCC
Power/Other
K2
M23
M24
M25
M26
M27
M28
M29
VCC
Power/Other
K3
A20M#
REQ0#
VSS
Input
VCC
Power/Other
K4
Source Synch Input/Output
Power/Other
VCC
Power/Other
K5
VCC
Power/Other
K6
REQ3#
VSS
Source Synch Input/Output
Power/Other
VCC
Power/Other
K7
VCC
Power/Other
K8
VCC
Power/Other
VCC
Power/Other
Datasheet
61
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
M30
N1
VCC
Power/Other
R7
R8
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
PWRGOOD
IGNNE#
VSS
Power/Other
Asynch CMOS
Power/Other
Input
Input
N2
R23
R24
R25
R26
R27
R28
R29
R30
T1
N3
VSS
N4
RESERVED
RESERVED
VSS
VSS
N5
VSS
N6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch CMOS
Asynch CMOS
Power/Other
VSS
N7
VSS
VSS
N8
VCC
VSS
N23
N24
N25
N26
N27
N28
N29
N30
P1
VCC
VSS
VCC
COMP1
FC4
Input
VCC
T2
VCC
T3
VSS
VCC
T4
A11#
A09#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
T5
VCC
T6
VCC
T7
VSS
Power/Other
TESTHI11
SMI#
INIT#
VSS
Input
Input
Input
T8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC28
FC29
FC30
A13#
A12#
A10#
VSS
Power/Other
P2
T23
T24
T25
T26
T27
T28
T29
T30
U1
Power/Other
P3
Power/Other
P4
Power/Other
P5
RESERVED
A04#
VSS
Power/Other
P6
Source Synch Input/Output
Power/Other
Power/Other
P7
Power/Other
P8
VCC
Power/Other
Power/Other
P23
P24
P25
P26
P27
P28
P29
P30
R1
VSS
Power/Other
Power/Other
VSS
Power/Other
Power/Other
VSS
Power/Other
U2
Power/Other
VSS
Power/Other
U3
Power/Other
VSS
Power/Other
U4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
Power/Other
U5
VSS
Power/Other
U6
VSS
Power/Other
U7
COMP3
VSS
Power/Other
Power/Other
Asynch CMOS
Input
U8
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
R2
U23
U24
U25
U26
U27
Power/Other
R3
FERR#/PBE#
A08#
VSS
Output
Power/Other
R4
Source Synch Input/Output
Power/Other
Power/Other
R5
Power/Other
R6
ADSTB0#
Source Synch Input/Output
Power/Other
62
Datasheet
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
Type
U28
U29
U30
V1
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Y5
Y6
VSS
A19#
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Power/Other
Source Synch Input/Output
Power/Other
VCC
Y7
MSID1
RESERVED
VSS
Output
Y8
Power/Other
V2
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Power/Other
V3
Power/Other
Power/Other
V4
A15#
A14#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
V5
Power/Other
V6
Power/Other
V7
VSS
Power/Other
Power/Other
V8
VCC
Power/Other
Power/Other
V23
V24
V25
V26
V27
V28
V29
V30
W1
W2
W3
W4
W5
W6
W7
W8
W23
W24
W25
W26
W27
W28
W29
W30
Y1
VSS
Power/Other
Power/Other
VSS
Power/Other
AA1 VTT_OUT_RIGHT Power/Other
Output
VSS
Power/Other
AA2
AA3
FC39
VSS
Power/Other
Power/Other
VSS
Power/Other
VSS
Power/Other
AA4
A21#
A23#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
Power/Other
AA5
VSS
Power/Other
AA6
VSS
Power/Other
AA7
VSS
Power/Other
MSID0
Power/Other
Output
Input
Input
AA8
VCC
Power/Other
TESTHI12/FC44 Power/Other
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
VSS
Power/Other
TESTHI1
VSS
Power/Other
Power/Other
VSS
Power/Other
VSS
Power/Other
A16#
A18#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
Power/Other
VSS
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
AB2
IERR#
FC37
A26#
A24#
A17#
VSS
Asynch CMOS
Power/Other
Output
VCC
Power/Other
AB3
VCC
Power/Other
AB4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
Power/Other
AB5
VCC
Power/Other
AB6
VCC
Power/Other
AB7
FC0
Power/Other
AB8
VCC
Power/Other
Y2
VSS
Power/Other
AB23
AB24
AB25
VSS
Power/Other
Y3
FC17
A20#
Power/Other
VSS
Power/Other
Y4
Source Synch Input/Output
VSS
Power/Other
Datasheet
63
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
AB26
AB27
AB28
AB29
AB30
AC1
VSS
VSS
VSS
VSS
VSS
TMS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
AE3
AE4
FC18
RESERVED
VSS
Power/Other
AE5
Power/Other
AE6
RESERVED
VSS
AE7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
Input
AE8
SKTOCC#
VCC
Output
AC2
DBR#
VSS
Power/Other
Power/Other
Output
AE9
AC3
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AF1
VSS
AC4
RESERVED
A25#
VSS
VCC
AC5
Source Synch Input/Output
Power/Other
VCC
AC6
VSS
AC7
VSS
Power/Other
VCC
AC8
VCC
Power/Other
VCC
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD1
VCC
Power/Other
VSS
VCC
Power/Other
VSS
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
VSS
VCC
Power/Other
VCC
VCC
Power/Other
VCC
VCC
Power/Other
VCC
TDI
TAP
Input
VSS
AD2
BPM2#
FC36
VSS
Common Clock Input/Output
Power/Other
VSS
AD3
VSS
AD4
Power/Other
VSS
AD5
ADSTB1#
A22#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS
AD6
VSS
AD7
VSS
AD8
VCC
Power/Other
TDO
Output
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AE1
VCC
Power/Other
AF2
BPM4#
VSS
Common Clock Input/Output
Power/Other
VCC
Power/Other
AF3
VCC
Power/Other
AF4
A28#
A27#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VCC
Power/Other
AF5
VCC
Power/Other
AF6
VCC
Power/Other
AF7
VSS
Power/Other
VCC
Power/Other
AF8
VCC
Power/Other
VCC
Power/Other
AF9
VCC
Power/Other
TCK
TAP
Input
AF10
AF11
VSS
Power/Other
AE2
VSS
Power/Other
VCC
Power/Other
64
Datasheet
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
Type
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
AH2
RESERVED
VSS
A32#
A33#
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VSS
AH3
Power/Other
VSS
AH4
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
AH5
VSS
AH6
VSS
AH7
VSS
AH8
VSS
AH9
TRST#
BPM3#
BPM5#
A30#
A31#
A29#
VSS
Input
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AG2
Common Clock Input/Output
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
AG3
AG4
AG5
AG6
AG7
AG8
VCC
VCC
VSS
Power/Other
AG9
Power/Other
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
VSS
Power/Other
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Datasheet
65
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Type
Land
#
Signal Buffer
Land Name
Direction
Land Name
Direction
Type
AH30
AJ1
VCC
BPM1#
BPM0#
ITP_CLK1
VSS
Power/Other
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AL1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input/Output
AJ2
VCC
AJ3
TAP
Input
VCC
AJ4
Power/Other
VSS
AJ5
A34#
A35#
VSS
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
AJ6
VCC
AJ7
VSS
AJ8
VCC
VSS
AJ9
VCC
VCC
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK1
AK2
AK3
AK4
AK5
AK6
AK7
AK8
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VCC
THERMDA
PROCHOT#
VRDSEL
VID5
VID1
VID3
VSS
VSS
AL2
Asynch CMOS Input/Output
Power/Other
VSS
AL3
VCC
AL4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
VCC
AL5
VSS
AL6
VSS
AL7
VSS
AL8
VCC
VSS
AL9
VCC
THERMDC
VSS
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
VSS
VCC
ITP_CLK0
VID4
VSS
TAP
Input
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
VSS
VCC
FC8
VCC
VSS
VSS
VCC
VSS
66
Datasheet
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Signal Buffer
Land
#
Signal Buffer
Type
Land Name
Direction
Land Name
Direction
Type
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AM1
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VID0
VID2
VSS
VID6
FC40
VID7
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AM27
AM28
AM29
AM30
AN1
VSS
VSS
VCC
VCC
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AN2
AN3
VCC_SENSE
VSS_SENSE
Power/Other
Power/Other
Output
Output
AN4
VCC_MB_
REGULATION
AN5
AN6
Power/Other
Power/Other
Output
VSS_MB_
REGULATION
Output
Output
AN7
VID_SELECT
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AN8
AN9
AM2
Output
Output
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AM3
AM4
AM5
Output
Output
AM6
AM7
AM8
AM9
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
Datasheet
67
Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins/lands of all agents on the processor FSB. A[35:3]#
are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
Input/
Output
A[35:3]#
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See Section 6.1 for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-MB boundary. Assertion of A20M# is only supported
in real mode.
A20M#
Input
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All
bus agents observe the ADS# activation to begin protocol checking,
address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
Input/
Output
ADS#
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
Input/
Output
Signals
Associated Strobe
ADSTB[1:0]#
REQ[4:0]#, A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All processor FSB agents must receive these signals to
drive their outputs and latch their inputs.
BCLK[1:0]
BNR#
Input
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS
.
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
Input/
Output
68
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[5:0]# should connect the
appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
port. PRDY# is a processor output used by debug tools to determine
processor debug readiness.
Input/
Output
BPM[5:0]#
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor.
These signals do not have on-die termination.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor FSB. It must connect the appropriate pins/lands of all
processor FSB agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by de-asserting BPRI#.
BPRI#
BR0#
Input
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
Input/
Output
This signal does not have on-die termination and must be
terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to
select the processor input clock frequency. Table 16 defines the
possible combinations of the signals and the frequency associated
with each combination. The required frequency is determined by
the processor, chipset and clock synthesizer. All agents must
operate at the same frequency. For more information about these
signals, including termination recommendations refer to
Section 2.7.6.
BSEL[2:0]
Output
Analog
COMP8
COMP[3:0] and COMP8 must be terminated to VSS on the system
board using precision resistors.
COMP[3:0]
Datasheet
69
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
D[63:0]# (Data) are the data signals. These signals provide a 64-
bit data path between the processor FSB agents, and must connect
the appropriate pins/lands on all such agents. The data driver
asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to data
strobes and DBI#.
Quad-Pumped Signal Groups
Input/
Output
D[63:0]#
DSTBN#/
DSTBP#
Data Group
DBI#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals
are activated when the data on the data bus is inverted. If more
than half the data bits, within a 16-bit group, would have been
asserted electrically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Input/
Output
DBI[3:0]#
Data Bus
Bus Signal
Signals
DBI3#
DBI2#
DBI1#
DBI0#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DBR# (Debug Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
DBR#
Output debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is in
Input/
DBSY#
use. The data bus is released after DBSY# is de-asserted. This
Output
signal must connect the appropriate pins/lands on all processor FSB
agents.
70
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
DEFER#
Input
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
Input/
Output
DRDY#
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
Input/
Output
DSTBN[3:0]#
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
Input/
Output
DSTBP[3:0]#
FC signals are signals that are available for compatibility with other
processors.
FCx
Other
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a
pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal
state. For additional information on the pending break event
functionality, including the identification of support of the feature
and enable/disable information, refer to volume 3 of the Intel
Architecture Software Developer's Manual and the Intel Processor
Identification and the CPUID Instruction application note.
FERR#/PBE#
Output
GTLREF[1:0] determine the signal reference level for GTL+ input
signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1.
GTLREF[1:0]
Input
Datasheet
71
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can
be continued by reasserting HIT# and HITM# together.
HIT#
HITM#
IERR#
Input/
Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
Output
This signal does not have on-die termination. Refer to Section 2.6.2
for termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to the processor to
ignore a numeric error and continue to execute noncontrol floating-
point instructions. If IGNNE# is de-asserted, the processor
generates an exception on a noncontrol floating-point instruction if
a previous floating-point instruction caused an error. IGNNE# has
no effect when the NE bit in control register 0 (CR0) is set.
IGNNE#
Input
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the
appropriate pins/lands of all processor FSB agents.
INIT#
Input
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in
the system, ITP_CLK[1:0] are no connects in the system. These are
not processor signals.
ITP_CLK[1:0]
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins/lands of all APIC Bus agents. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
LINT[1:0]
Input
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
72
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of
all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
Input/
Output
LOCK#
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity
of lock.
These signals indicate the Market Segment for the processor. Refer
to Table 3 for additional information.
MSID[1:0]
PECI
Output
Input/ PECI is a proprietary one-wire bus interface. See Section 5.4 for
Output details.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor
has reached its maximum safe operating temperature. This
Input/ indicates that the processor Thermal Control Circuit (TCC) has been
Output activated, if enabled. As an input, assertion of PROCHOT# by the
system will activate the TCC, if enabled. The TCC will remain active
until the system de-asserts PROCHOT#. See Section 5.2.4 for more
details.
PROCHOT#
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable
before a subsequent rising edge of PWRGOOD.
PWRGOOD
REQ[4:0]#
RESET#
Input
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins/
Input/ lands of all processor FSB agents. They are asserted by the current
Output bus owner to define the currently active transaction type. These
signals are source synchronous to ADSTB0#.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least one millisecond after VCC and BCLK have reached their proper
specifications. On observing active RESET#, all FSB agents will de-
assert their outputs within two clocks. RESET# must not be kept
Input
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1.
This signal does not have on-die termination and must be
terminated on the system board.
Datasheet
73
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
All RESERVED lands must remain unconnected. Connection of these
lands to VCC, VSS, VTT, or to any other signal (including each other)
can result in component malfunction or incompatibility with future
processors.
RESERVED
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins/lands of all processor FSB
agents.
RS[2:0]#
SKTOCC#
Input
SKTOCC# (Socket Occupied) will be pulled to ground by the
Output processor. System board designers may use this signal to determine
if the processor is present.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
SMI#
Input
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-asserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
STPCLK#
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TCK
TDI
Input
Input
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
TDO
Output TDO provides the serial output needed for JTAG specification
support.
TESTHI[13:0] must be connected to the processor’s appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal
description) through a resistor for proper processor operation. See
TESTHI[13:0]
Input
Section 2.5 for more details.
THERMDA
THERMDC
Other Thermal Diode Anode. See Section 5.3.
Other Thermal Diode Cathode. See Section 5.3.
74
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a
temperature approximately 20 °C above the maximum TC.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a level beyond where permanent
silicon damage may occur. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus, halting program
execution) in an attempt to reduce the processor junction
temperature. To protect the processor, its core voltage (VCC) must
THERMTRIP#
Output be removed following the assertion of THERMTRIP#. Driving of the
THERMTRIP# signal is enabled within 10 μs of the assertion of
PWRGOOD (provided VTT and VCC are valid) and is disabled on de-
assertion of PWRGOOD (if VTT or VCC are not valid, THERMTRIP#
may also be disabled). Once activated, THERMTRIP# remains
latched until PWRGOOD, VTT, or VCC is de-asserted. While the de-
assertion of the PWRGOOD, VTT, or VCC will de-assert THERMTRIP#,
if the processor’s junction temperature remains at or above the trip
level, THERMTRIP# will again be asserted within 10 μs of the
assertion of PWRGOOD (provided VTT and VCC are valid).
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TMS
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
TRDY#
TRST#
Input
Input
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
VCC are the power pins for the processor. The voltage supplied to
these pins is determined by the VID[7:0] pins.
VCC
Input
Input
VCCPLL
VCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
VCC_SENSE
Output core power (VCC). It can be used to sense or measure voltage near
the silicon with little noise.
This land is provided as a voltage regulator feedback sense point for
V
CC. It is connected internally in the processor package to the sense
VCC_MB_
REGULATION
Output point land U27 as described in the Voltage Regulator-Down (VRD)
11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket.
VID[7:0] (Voltage ID) signals are used to support automatic
selection of power supply voltages (VCC). Refer to the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket for more information. The
voltage supply for these signals must be valid before the VR can
Output supply VCC to the processor. Conversely, the VR output must be
disabled until the voltage supply for the VID signals becomes valid.
The VID signals are needed to support the processor voltage
specification variations. See Table 2 for definitions of these signals.
The VR must supply the voltage that is requested by the signals, or
disable itself.
VID[7:0]
This land is tied high on the processor package and is used by the
VR to choose the proper VID table. Refer to the Voltage Regulator-
Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
VID_SELECT
Output
Desktop LGA775 Socket for more information.
Datasheet
75
Land Listing and Signal Descriptions
Table 25.
Signal Description (Sheet 1 of 9)
Name
Type
Description
This input should be left as a no connect in order for the processor
to boot. The processor will not boot on legacy platforms where this
VRDSEL
Input
land is connected to VSS
.
VSS are the ground pins for the processor and should be connected
to the system ground plane.
VSS
Input
Input
VSSA
VSSA is the isolated ground for internal PLLs.
VSS_SENSE is an isolated low impedance connection to processor
VSS_SENSE
Output core VSS. It can be used to sense or measure ground near the
silicon with little noise.
This land is provided as a voltage regulator feedback sense point for
V
SS. It is connected internally in the processor package to the sense
VSS_MB_
REGULATION
Output point land V27 as described in the Voltage Regulator-Down (VRD)
11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket.
VTT
Input
Miscellaneous voltage supply.
VTT_OUT_LEFT
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to
Output provide a voltage supply for some signals that require termination
to VTT on the motherboard.
VTT_OUT_RIGHT
VTT_SEL
The VTT_SEL signal is used to select the correct VTT voltage level for
Output the processor. This land is connected internally in the package to
VTT.
§ §
76
Datasheet
Thermal Specifications and Design Considerations
5
Thermal Specifications and
Design Considerations
5.1
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as described in Section 5.1.1. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions can include active or passive
heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system
level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
Note:
The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.
5.1.1
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum case temperature (TC)
specifications when operating at or below the Thermal Design Power (TDP) value listed
per frequency in Table 26. Thermal solutions not designed to provide this level of
thermal capability may affect the long-term reliability of the processor and system. For
more details on thermal solution design, refer to the appropriate Thermal and
Mechanical Design Guidelines (see Section 1.2).
The processor uses a methodology for managing processor temperatures which is
intended to support acoustic noise reduction through fan speed control. Selection of the
appropriate fan speed is based on the relative temperature data reported by the
processor’s Platform Environment Control Interface (PECI) bus as described in
Section 5.4.1.1. The temperature reported over PECI is always a negative value and
represents a delta below the onset of thermal control circuit (TCC) activation, as
indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control
must be designed to take these conditions in to account. Systems that do not alter the
fan speed only need to ensure the case temperature meets the thermal profile
specifications.
To determine a processor's case temperature specification based on the thermal profile,
it is necessary to accurately measure processor power dissipation. Intel has developed
a methodology for accurate power measurement that correlates to Intel test
temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical
Design Guidelines (see Section 1.2) and the Processor Power Characterization
Methodology for the details of this methodology.
The case temperature is defined at the geometric top center of the processor. Analysis
indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
Datasheet
77
Thermal Specifications and Design Considerations
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table 26 instead of the maximum processor power consumption. The Thermal Monitor
feature is designed to protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2. In all cases the Thermal Monitor and
Thermal Monitor 2 feature must be enabled for the processor to remain within
specification.
Table 26.
Processor Thermal Specifications
Core
Frequency
(GHz)
Thermal
Design
Extended
HALT
775_VR_
Processor
Number
Minimum Maximum TC
CONFIG_05B/
Notes
T
C (°C)
(°C)
Power (W)1,2 Power (W)3
06 Guidance4
5,6
5,6
E6850
E6750
E6550
E6540
E6700
E6600
E6420
E6320
E4700
E4600
E4500
E4400
E6400
E6400
E6300
E6300
E4400
E4300
3.00
2.66
2.33
2.33
2.66
2.40
2.13
1.86
2.40
2.40
2.20
2.00
2.13
2.13
1.86
1.86
2.00
1.80
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
65.0
8.0
8.0
5
5
5
5
5
5
5
5
5
5
5
5
Thermal
Profile 1
775_VR_CONFIG
_06
5,6
(SeeTable 27,
Figure 19)
8.0
5,6
8.0
7,8
22.0/12.0
22.0/12.0
12.0
12.0
8.0
Thermal
Profile 2
7,8
775_VR_CONFIG
_06
7,8
(SeeTable 28,
Figure 20)
7,8
5,6
Thermal
Profile 3
5,9
8.0
775_VR_CONFIG
_06
5,9
(SeeTable 29,
Figure 21)
8.0
5,9
8.0
7, 10
7,8
12.0
22.0
12.0
22.0
12.0
12.0
5
Thermal
Profile 4
7, 10
7,8
775_VR_CONFIG
_06
(SeeTable 30,
Figure 22)
5
5
5
7, 10
7,10
Thermal
Profile 5
775_VR_CONFIG
_05B
7,8
X6800
2.93
75.0
22.0
5
(See Table 31
Figure 23)
NOTES:
1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power
that the processor can dissipate.
2. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP.
Therefore, the maximum TC will vary depending on the TDP of the individual processor. Refer to thermal profile
figure and associated table for the allowed combinations of power and TC.
®
®
3. Refer to the “Component Identification Information” section of the Intel Core™2 Extreme and Intel Core™2 Duo Desktop
Processor Specification Update for processor specific Idle power.
4. 775_VR_CONFIG_06/775_VR_CONFIG_05B guidelines provide a design target for meeting future thermal requirements.
5. Specification is at 35 °C T and typical voltage loadline.
C
6. These processors have CPUID = 06FBh.
7. Specification is at 50 °C T and typical voltage loadline.
C
8. These processors have CPUID = 06F6h.
9. These processors have CPUID = 06FDh.
10.These processors have CPUID = 06F2h.
78
Datasheet
Thermal Specifications and Design Considerations
Table 27.
Thermal Profile 1
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
0
2
44.7
45.5
46.4
47.2
48.1
48.9
49.7
50.6
51.4
52.3
53.1
53.9
24
26
28
30
32
34
36
38
40
42
44
46
54.8
55.6
56.5
57.3
58.1
59.0
59.8
60.7
61.5
62.3
63.2
64.0
48
50
52
54
56
58
60
62
64
65
64.9
65.7
66.5
67.4
68.2
69.1
69.9
70.7
71.6
72.0
4
6
8
10
12
14
16
18
20
22
NOTE: For the Intel® Core™2 Duo Desktop processor E6x50 series with 4 MB L2 Cache and
CPUID = 06FBh, and Intel® Core™2 Duo Desktop processor E6540 with 4 MB L2 Cache
and CPUID = 06FBh.
Figure 19.
Thermal Profile 1
NOTE: For the Intel® Core™2 Duo Desktop processor E6x50 series with 4 MB L2 Cache and
CPUID = 06FBh, and Intel® Core™2 Duo Desktop processorr E6540 with 4 MB L2 Cache
and CPUID = 06FBh.
Datasheet
79
Thermal Specifications and Design Considerations
Table 28.
Thermal Profile 2
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
0
2
43.2
43.7
44.2
44.8
45.3
45.8
46.3
46.8
47.4
47.9
48.4
48.9
24
26
28
30
32
34
36
38
40
42
44
46
49.4
50.0
50.5
51.0
51.5
52.0
52.6
53.1
53.6
54.1
54.6
55.2
48
50
52
54
56
58
60
62
64
65
55.7
56.2
56.7
57.2
57.8
58.3
58.8
59.3
59.8
60.1
4
6
8
10
12
14
16
18
20
22
NOTE: For the Intel® Core™2 Duo Desktop processor E6000 series with 4 MB L2 Cache and
CPUID = 06F6h.
Figure 20.
Thermal Profile 2
65.0
60.0
55.0
y = 0.26x + 43.2
50.0
45.0
40.0
0
10
20
30
Power (W)
40
50
60
NOTE: For the Intel® Core™2 Duo Desktop processor E6000 series with 4 MB L2 Cache and
CPUID = 06F6h.
80
Datasheet
Thermal Specifications and Design Considerations
Table 29.
Thermal Profile 3
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
0
2
45.3
46.2
47.0
47.9
48.7
49.6
50.5
51.3
52.2
53.0
53.9
54.8
24
26
28
30
32
34
36
38
40
42
44
46
55.6
56.5
57.3
58.2
59.1
59.9
60.8
61.6
62.5
63.4
64.2
65.1
48
50
52
54
56
58
60
62
64
65
65.9
66.8
67.7
68.5
69.4
70.2
71.1
72.0
72.8
73.3
4
6
8
10
12
14
16
18
20
22
NOTE: For the Intel® Core™2 Duo Desktop processor E4000 series with 2 MB L2 Cache and
CPUID = 06FDh, and for the Intel® Core™2 Duo Desktop processor E4700 with 2 MB L2
Cache and CPUID = 06FBh.
Figure 21.
Thermal Profile 3
NOTE: For the Intel® Core™2 Duo Desktop processor E4000 series with 2 MB L2 Cache and
CPUID = 06FDh, and for the Intel® Core™2 Duo Desktop processor E4700 with 2 MB L2
Cache and CPUID = 06FBh.
Datasheet
81
Thermal Specifications and Design Considerations
Table 30.
Thermal Profile 4
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
0
2
43.2
43.8
44.3
44.9
45.4
46.0
46.6
47.1
47.7
48.2
48.8
49.4
24
26
28
30
32
34
36
38
40
42
44
46
49.9
50.5
51.0
51.6
52.2
52.7
53.3
53.8
54.4
55.0
55.5
56.1
48
50
52
54
56
58
60
62
64
65
56.6
57.2
57.8
58.3
58.9
59.4
60.0
60.6
61.1
61.4
4
6
8
10
12
14
16
18
20
22
NOTE: For the Intel® Core™2 Duo Desktop processor E6000 and E4000 series with 2 MB L2
Cache and CPUID = 06F2h, and for the Intel® Core™2 Duo Desktop processor E6000
series with 2 MB L2 Cache and CPUID = 06F6h.
Figure 22.
Thermal Profile 4
65.0
60.0
y = 0.28x + 43.2
55.0
50.0
45.0
40.0
0
10
20
30
Power (W)
40
50
60
NOTE: For the Intel® Core™2 Duo Desktop processor E6000 and E4000 series with 2 MB L2
Cache and CPUID = 06F2h, and for the Intel® Core™2 Duo Desktop processor E6000
series with 2 MB L2 Cache and CPUID = 06F6h.
82
Datasheet
Thermal Specifications and Design Considerations
Table 31.
Thermal Profile 5
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
Power
(W)
Maximum
Tc (°C)
0
2
43.2
43.7
44.1
44.6
45.0
45.5
46.0
46.4
46.9
47.3
47.8
48.3
48.7
26
28
30
32
34
36
38
40
42
44
46
48
50
49.2
49.6
50.1
50.6
51.0
51.5
51.9
52.4
52.9
53.3
53.8
54.2
54.7
52
54
56
58
60
62
64
66
68
70
72
74
75
55.2
55.6
56.1
56.5
57.0
57.5
57.9
58.2
58.8
59.3
59.8
60.2
60.4
4
6
8
10
12
14
16
18
20
22
24
NOTE: For the Intel® Core™2 Extreme processor X6800.
Figure 23.
Thermal Profile 5
65.0
60.0
55.0
50.0
45.0
40.0
y = 0.23x + 43.2
0
10
20
30
40
50
60
70
Power (W)
NOTE: For the Intel® Core™2 Extreme processor X6800.
Datasheet
83
Thermal Specifications and Design Considerations
5.1.2
Thermal Metrology
The maximum and minimum case temperatures (TC) for the processor is specified in
Table 26. This temperature specification is meant to help ensure proper operation of
the processor. Figure 24 illustrates where Intel recommends TC thermal measurements
should be made. For detailed guidelines on temperature measurement methodology,
refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
Figure 24.
Case Temperature (TC) Measurement Location
Measure TC atthispoint
(geometric center of the package)
37.5 mm
5.2
Processor Thermal Features
5.2.1
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the
thermal control circuit (TCC) when the processor silicon reaches its maximum operating
temperature. The TCC reduces processor power consumption by modulating (starting
and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The
temperature at which Thermal Monitor activates the thermal control circuit is not user
configurable and is not software visible. Bus traffic is snooped in the normal manner,
and interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off
and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will
not be off for more than 3.0 microseconds when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss,
84
Datasheet
Thermal Specifications and Design Considerations
and in some cases may result in a TC that exceeds the specified maximum temperature
and may affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under-designed may not be capable of cooling the processor even
when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical
Design Guidelines (see Section 1.2) for information on designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
5.2.2
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor
temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust
its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor
power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage. The first operating point
represents the normal operating condition for the processor. Under this condition, the
core-frequency-to-FSB multiple used by the processor is that contained in the
appropriate MSR and the VID is that specified in Table 5. These parameters represent
normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new
frequency. This transition occurs very rapidly (on the order of 5 μs). During the
frequency transition, the processor is unable to service any bus requests, and
consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and
kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps to support Thermal Monitor 2. During the
voltage change, it will be necessary to transition through multiple VID codes to reach
the target operating voltage. Each step will likely be one VID table entry (see Table 5).
The processor continues to execute instructions during the voltage transition.
Operation at the lower voltage reduces the power consumption of the processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point. Transition of the VID code
will occur first, to insure proper operation once the processor reaches its normal
operating frequency. Refer to Figure 25 for an illustration of this ordering.
Datasheet
85
Thermal Specifications and Design Considerations
Figure 25.
Thermal Monitor 2 Frequency and Voltage Ordering
TTM2
Temperature
Frequency
fMAX
fTM2
VID
VIDTM2
VID
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on
demand mode. The Thermal Monitor TCC, however, can be activated through the use of
the on demand mode.
5.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems using the
processor must not rely on software usage of this mechanism to limit the processor
temperature.
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor and Thermal Monitor 2
features. On-Demand mode is intended as a means to reduce system level power
consumption. Systems must not rely on software usage of this mechanism to limit the
processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the
processor will immediately reduce its power consumption via modulation (starting and
stopping) of the internal core clock, independent of the processor temperature. When
using On-Demand mode, the duty cycle of the clock modulation is programmable via
bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty
cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/ 12.5% off in 12.5%
increments. On-Demand mode may be used in conjunction with the Thermal Monitor;
however, if the system tries to enable On-Demand mode at the same time the TCC is
engaged, the factory configured duty cycle of the TCC will override the duty cycle
selected by the On-Demand mode.
86
Datasheet
Thermal Specifications and Design Considerations
5.2.4
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT#.
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that one or both cores has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will
remain active until the system de-asserts PROCHOT#.
PROCHOT# allows for some protection of various components from over-temperature
situations. The PROCHOT# signal is bi-directional in that it can either signal when the
processor (either core) has reached its maximum operating temperature or be driven
from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
PROCHOT# can allow VR thermal designs to target maximum sustained current instead
of maximum current. Systems should still provide proper cooling for the VR, and rely
on PROCHOT# only as a backup in case of system cooling failure. The system thermal
design should allow the power delivery circuitry to operate within its temperature
specification even while the processor is operating at its Thermal Design Power. With a
properly designed and characterized thermal solution, it is anticipated that PROCHOT#
would only be asserted for very short periods of time when running the most power
intensive applications. An under-designed thermal solution that is not able to prevent
excessive assertion of PROCHOT# in the anticipated ambient environment may cause a
noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on
implementing the bi-directional PROCHOT# feature.
5.2.5
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 25. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.
Datasheet
87
Thermal Specifications and Design Considerations
5.3
Thermal Diode
The processor incorporates an on-die PNP transistor where the base emitter junction is
used as a thermal "diode", with its collector shorted to ground. A thermal sensor
located on the system board may monitor the die temperature of the processor for
thermal management and fan speed control. Table 32,Table 33, and Table 34 provide
the "diode" parameter and interface specifications. Two different sets of "diode"
parameters are listed in Table 32 and Table 33. The Diode Model parameters (Table 32)
apply to traditional thermal sensors that use the Diode Equation to determine the
processor temperature. Transistor Model parameters (Table 33) have been added to
support thermal sensors that use the transistor equation method. The Transistor Model
may provide more accurate temperature measurements when the diode ideality factor
is closer to the maximum or minimum limits. This thermal "diode" is separate from the
Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the
Thermal Monitor.
TCONTROL is a temperature specification based on a temperature reading from the
thermal diode. The value for TCONTROL will be calibrated in manufacturing and
configured for each processor. When TDIODE is above TCONTROL, then TC must be at or
below TC_MAX as defined by the thermal profile in Table 28; otherwise, the processor
temperature can be maintained at TCONTROL (or lower) as measured by the thermal
diode.
Table 32.
Thermal “Diode” Parameters using Diode Model
Symbol
IFW
Parameter
Min
Typ
Max
Unit
Notes
Forward Bias Current
Diode Ideality Factor
Series Resistance
5
—
200
1.050
6.24
µA
-
1
n
1.000
2.79
1.009
4.52
2, 3, 4
2, 3, 5
RT
Ω
NOTES:
1.
2.
3.
4.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Characterized across a temperature range of 50 – 80 °C.
Not 100% tested. Specified by design characterization.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by
the diode equation:
FW = IS * (e qV /nkT –1)
D
I
where IS = saturation current, q = electronic charge, VD = voltage across the diode,
k = Boltzmann Constant, and T = absolute temperature (Kelvin).
5.
The series resistance, RT, is provided to allow for a more accurate measurement of the
junction temperature. RT, as defined, includes the lands of the processor but does not
include any socket resistance or board trace resistance between the socket and the
external remote diode thermal sensor. RT can be used by remote diode thermal sensors
with automatic series resistance cancellation to calibrate out this error term. Another
application is that a temperature offset can be manually calculated and programmed into
an offset register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT * (N–1) * IFWmin] / [nk/q * ln N]
where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann
Constant, q = electronic charge.
88
Datasheet
Thermal Specifications and Design Considerations
Table 33.
Thermal “Diode” Parameters using Transistor Model
Symbol
IFW
Parameter
Min
Typ
Max
Unit
Notes
Forward Bias Current
Emitter Current
5
—
—
200
200
µA
µA
-
1, 2
IE
5
nQ
Transistor Ideality
0.997
0.391
2.79
1.001
—
1.005
0.760
6.24
3, 4, 5
3, 4
Beta
RT
Series Resistance
4.52
Ω
3, 6
NOTES:
1.
2.
3.
4.
5.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Same as IFW in Table 32.
Characterized across a temperature range of 50–80 °C.
Not 100% tested. Specified by design characterization.
The ideality factor, nQ, represents the deviation from ideal transistor model behavior as
exemplified by the equation for the collector current:
IC = IS * (e qV /n kT –1)
BE
Q
Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor
base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
temperature (Kelvin).
The series resistance, RT, provided in the Diode Model Table (Table 32) can be used for
more accurate readings as needed.
6.
The processor does not support the diode correction offset that exists on other Intel
processors
Table 34.
Thermal Diode Interface
Signal
Signal Name
Land Number
Description
THERMDA
THERMDC
AL1
AK1
diode anode
diode cathode
Datasheet
89
Thermal Specifications and Design Considerations
5.4
Platform Environment Control Interface (PECI)
5.4.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues. Figure 26
shows an example of the PECI topology in a system. PECI uses CRC checking on the
host side to ensure reliable transfers between the host and client devices. Also, data
transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to
2 Mbps). The PECI interface on the processor is disabled by default and must be
enabled through BIOS.
Figure 26.
Processor PECI Topology
Land G5
PECI Host
Controller
Domain 0
5.4.1.1
Key Difference with Legacy Diode-Based Thermal Management
Fan speed control solutions based on PECI uses a TCONTROL value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the TCONTROL value as negative. Thermal management algorithms
should use the relative temperature value delivered over PECI in conjunction with the
TCONTROL MSR value to control or optimize fan speeds. Figure 27 shows a conceptual
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
90
Datasheet
Thermal Specifications and Design Considerations
.
Figure 27.
Conceptual Fan Control on PECI-Based Platforms
TCONTROL
Setting
TCC Activation
Temperature
PECI = 0
Max
PECI = -10
Fan Speed
(RPM)
Min
PECI = -20
Temperature
Note: Not intended to depict actual implementation
.
Figure 28.
Conceptual Fan Control on Thermal Diode-Based Platforms
TCONTROL
Setting
TCC Activation
Temperature
TDIODE = 90 °C
Max
DIODE = 80 °C
Fan Speed
(RPM)
T
Min
TDIODE = 70 °C
Temperature
Datasheet
91
Thermal Specifications and Design Considerations
5.4.2
PECI Specifications
5.4.2.1
PECI Device Address
The PECI device address for the socket is 30h. For more information on PECI domains,
refer to the Platform Environment Control Interface Specification.
5.4.2.2
5.4.2.3
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command
function and codes.
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damaging states. It is recommended that the PECI host controller take
appropriate action to protect the client processor device if valid temperature readings
have not been obtained in response to three consecutive gettemp()s or for a one
second time interval. The host controller may also implement an alert to software in the
event of a critical or continuous fault condition.
5.4.2.4
PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
Table 35.
Table 35.
GetTemp0() Error Codes
Error Code
8000h
Description
General sensor error
Sensor is operational, but has detected a temperature below its operational
range (underflow).
8002h
§ §
92
Datasheet
Features
6
Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 36.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
Table 36.
Power-On Configuration Option Signals
Signal1 2 3
,
,
Configuration Option
Output tristate
SMI#
Execute BIST
A3#
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
A25#
BR0#
A[8:5]#, A[24:11]#, A[35:26]#
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address signals not identified in this table as configuration options should not
be asserted during RESET#.
3. Disabling of any of the cores within the processor must be handled by
configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow
for the disabling of a single core.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 29 for a visual representation of the processor low
power states.
Datasheet
93
Features
Figure 29.
Processor Low Power State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Extended HALT or HALT
State
- BCLK running
- Snoops and interrupts
allowed
Normal State
INIT#, INTR, NMI, SMI#, RESET#,
FSB interrupts
- Normal Execution
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Extended HALT Snoop or
HALT Snoop State
- BCLK running
- Service Snoops to caches
Extended Stop Grant
State or Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Extended Stop Grant
Snoop or Stop Grant
Snoop State
- BCLK running
- Service Snoops to caches
Snoop Event Occurs
Snoop Event Serviced
6.2.1
6.2.2
Normal State
This is the normal operating state for the processor.
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its
specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the following sections for details about the HALT and Extended HALT states.
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted; however, the other processor continues normal operation.
The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.
94
Datasheet
Features
The system can generate a STPCLK# while the processor is in the HALT powerdown
state. When the system de-asserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT Power powerdown, the processor processes bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown state must be enabled via the BIOS for the processor to remain within
its specification.
The processor automatically transitions to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
While in Extended HALT state, the processor processes bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will resume operation at the lower
frequency, transitions the VID to the original value and then changes the bus ratio back
to the original value.
6.2.3
Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the following sections for details about the Stop Grant and Extended Stop Grant
states.
6.2.3.1
Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop Grant state. A transition back to the Normal state occurs with the de-assertion
of the STPCLK# signal.
A transition to the Grant Snoop state occurs when the processor detects a snoop on the
FSB (see Section 6.2.4).
While in the Stop Grant State, SMI#, INIT#, and LINT[1:0] is latched by the processor,
and only serviced when the processor returns to the Normal State. Only one occurrence
of each event will be recognized upon return to the Normal state.
While in Stop Grant state, the processor processes a FSB snoop.
Datasheet
95
Features
6.2.3.2
Extended Stop Grant State
Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted
and Extended Stop Grant has been enabled via the BIOS.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended Stop Grant state. When entering the low power
state, the processor will first switch to the lower bus ratio and then transition to the
lower VID.
The processor exits the Extended Stop Grant state when a break event occurs. When
the processor exits the Extended Stop Grant state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.4
Extended HALT State, HALT Snoop State, Extended Stop
Grant Snoop State, and Stop Grant Snoop State
The Extended HALT Snoop State is used in conjunction with the new Extended HALT
state. If Extended HALT state is not enabled in the BIOS, the default Snoop State
entered will be the HALT Snoop State. Refer to the following sections for details on
HALT Snoop State, Stop Grant Snoop State and Extended HALT Snoop State, and
Extended Stop Grant Snoop State.
6.2.4.1
6.2.4.2
HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop Grant state
or in HALT Power Down state. During a snoop transaction, the processor enters the
HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor returns to the Stop Grant state or HALT
Power Down state, as appropriate.
Extended HALT Snoop State, Extended Stop Grant Snoop State
The processor will remain in the lower bus ratio and VID operating point of the
Extended HALT state or Extended Stop Grant state. While in the Extended HALT Snoop
State or Extended Stop Grant Snoop State, snoops are handled the same way as in the
HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced, the
processor will return to the Extended HALT state or Extended Stop Grant state.
6.3
Enhanced Intel® SpeedStep® Technology
The processor supports Enhanced Intel SpeedStep® Technology. This technology
enables the processor to switch between multiple frequency and voltage points, which
results in platform power savings. Enhanced Intel SpeedStep Technology requires
support for dynamic VID transitions in the platform. Switching between voltage/
frequency states is software controlled.
Note:
Not all processors are capable of supporting Enhanced Intel SpeedStep® Technology.
More details on which processor frequencies support this feature is provided in the
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series and Intel® Core™2
Extreme Processor X6800 Specification Update.
Enhanced Intel SpeedStep® Technology creates processor performance states (P-
states) or voltage/frequency operating points. P-states are lower power capability
states within the Normal state as shown in Figure 29. Enhanced Intel SpeedStep®
Technology enables real-time dynamic switching between frequency and voltage
96
Datasheet
Features
points. It alters the performance of the processor by changing the bus to core
frequency ratio and voltage. This allows the processor to run at different core
frequencies and voltages to best serve the performance and power requirements of the
processor and system. The processor has hardware logic that coordinates the
requested voltage (VID) between the processor cores. The highest voltage that is
requested for either of the processor cores is selected for that processor package. Note
that the front side bus is not altered; only the internal core frequency is changed. To
run at reduced power consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep® Technology:
• Multiple voltage/frequency operating points provide optimal performance at
reduced power consumption.
• Voltage/frequency selection is software controlled by writing to processor MSRs
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, VCC is incremented
in steps (+12.5 mV) by placing a new value on the VID signals and the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts
to the new frequency and VCC is then decremented in steps (-12.5 mV) by
changing the target VID through the VID signals.
§ §
Datasheet
97
Features
98
Datasheet
Boxed Processor Specifications
7
Boxed Processor Specifications
The processor is also offered as an Intel boxed processor. Intel boxed processors are
intended for system integrators who build systems from baseboards and standard
components. The boxed processor will be supplied with a cooling solution. This chapter
documents baseboard and system requirements for the cooling solution that will be
supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators. Figure 30 shows a mechanical
representation of a boxed processor.
Note:
Note:
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets].
Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the appropriate Thermal and Mechanical Design
Guidelines (see Section 1.2) for further guidance.
Figure 30.
Mechanical Representation of the Boxed Processor
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
Datasheet
99
Boxed Processor Specifications
7.1
Mechanical Specifications
7.1.1
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The
boxed processor will be shipped with an unattached fan heatsink. Figure 30 shows a
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 31 (Side View), and Figure 32 (Top View).
The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 36 and Figure 37. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 31.
Space Requirements for the Boxed Processor (Side View)
95.0
[3.74]
81.3
[3.2]
10.0
25.0
[0.39]
[0.98]
Figure 32.
Space Requirements for the Boxed Processor (Top View)
NOTES:
1.
Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.
100
Datasheet
Boxed Processor Specifications
Figure 33.
Space Requirements for the Boxed Processor (Overall View)
Boxed Proc OverallView
7.1.2
7.1.3
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5
and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for
details on the processor weight and heatsink requirements.
Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.
7.2
Electrical Requirements
7.2.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 34. Baseboards
must provide a matched power header to support the boxed processor. Table 37
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal that is an open- collector output that pulses at
a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.
The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the
connector labeled as CONTROL.
Datasheet
101
Boxed Processor Specifications
The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and
does not support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 35 shows the
location of the fan power connector relative to the processor socket. The baseboard
power header should be positioned within 110 mm [4.33 inches] from the center of the
processor socket.
Figure 34.
Boxed Processor Fan Heatsink Power Cable Connector Description
Signal
Pin
Straight square pin, 4-pin terminal housing with
polarizing ribs and friction locking ramp.
1
2
3
4
GND
+12 V
0.100" pitch, 0.025" square pin width.
SENSE
CONTROL
Match with straight pin, friction lock header on
mainboard.
3 4
1 2
Table 37.
Fan Heatsink Power and Signal Specifications
Description
Min
Typ
Max
Unit
Notes
+12 V: 12 volt fan power supply
11.4
12
12.6
V
-
IC:
- Maximum fan steady-state current draw
- Average fan steady-state current draw
- Max fan start-up current draw
—
—
—
—
1.2
0.5
2.2
1.0
—
—
—
—
A
A
A
-
- Fan start-up current draw maximum
duration
Second
pulses per
fan
1
SENSE: SENSE frequency
—
2
—
revolution
2,
3
CONTROL
21
25
28
Hz
NOTES:
1. Baseboard should pull this pin up to 5 V with a resistor.
2. Open drain type, pulse width modulated.
3. Fan will have pull-up resistor for this signal to maximum of 5.25 V.
102
Datasheet
Boxed Processor Specifications
Figure 35.
Baseboard Power Header Placement Relative to Processor Socket
R110
[4.33]
B
C
7.3
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the
boxed processor.
7.3.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
temperature specification is listed in Chapter 5. The boxed processor fan heatsink is
able to keep the processor temperature within the specifications (see Table 26) in
chassis that provide good thermal management. For the boxed processor fan heatsink
to operate properly, it is critical that the airflow provided to the fan heatsink is
unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan
heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling
efficiency and decreases fan life. Figure 36 and Figure 37 illustrate an acceptable
airspace clearance for the fan heatsink. The air temperature entering the fan should be
kept below 38 ºC. Again, meeting the processor's temperature specification is the
responsibility of the system integrator.
Datasheet
103
Boxed Processor Specifications
Figure 36.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
Figure 37.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)
104
Datasheet
Boxed Processor Specifications
®
7.3.2
Fan Speed Control Operation (Intel Core2 Extreme
Processor X6800 Only)
The boxed processor fan heatsink is designed to operate continuously at full speed to
allow maximum user control over fan speed. The fan speed can be controlled by
hardware and software from the motherboard. This is accomplished by varying the duty
cycle of the Control signal on the 4th pin (see Table 38). The motherboard must have a
4-pin fan header and must be designed with a fan speed controller with PWM output
and Digital Thermometer measurement capabilities. For more information on specific
motherboard requirements for 4-wire based fan speed control, refer to the Intel®
Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, Intel® Pentium®
Processor, Intel® Core™2 Duo Extreme Processor X6800 Thermal and Mechanical
Design Guidelines.
4
The Internal chassis temperature should be kept below 39 ºC. Meeting the processor's
temperature specification (see Chapter 5) is the responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor's power header to
ensure proper operation of the fan for the boxed processor. See Table 38 for specific
requirements.
®
7.3.3
Fan Speed Control Operation (Intel Core2 Duo Desktop
Processor E6000 and E4000 Series Only)
If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin
motherboard header, it will operate as follows:
The boxed processor fan will operate at different speeds over a short range of
internal chassis temperatures. This allows the processor fan to operate at a lower
speed and noise level, while internal chassis temperatures are low. If internal
chassis temperature increases beyond a lower set point, the fan speed will rise
linearly with the internal temperature until the higher set point is reached. At that
point, the fan speed is at its maximum. As fan speed increases, so does fan noise
levels. Systems should be designed to provide adequate air around the boxed
processor fan heatsink that remains cooler than lower set point. These set points,
represented in Figure 38 and Table 38, can vary by a few degrees from fan heatsink
to fan heatsink. The internal chassis temperature should be kept below 38 ºC.
Meeting the processor's temperature specification (see Chapter 5) is the
responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor's power header to
ensure proper operation of the variable speed fan for the boxed processor. Refer to
Table 38 for the specific requirements.
Figure 38.
Boxed Processor Fan Heatsink Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X
Y
Z
Internal Chassis Temperature (Degrees C)
Datasheet
105
Boxed Processor Specifications
Table 38.
Fan Heatsink Power and Signal Specifications
Boxed Processor Fan
Heatsink Set Point (°C)
Boxed Processor Fan Speed
When the internal chassis temperature is below or equal to
Notes
this set point, the fan operates at its lowest speed.
Recommended maximum internal chassis temperature for
nominal operating environment.
X ≤ 30
1
When the internal chassis temperature is at this point, the
fan operates between its lowest and highest speeds.
Recommended maximum internal chassis temperature for
worst-case operating environment.
Y = 35
-
-
When the internal chassis temperature is above or equal to
this set point, the fan operates at its highest speed.
Z ≥ 38
NOTES:
1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin
motherboard header and the motherboard is designed with a fan speed controller with
PWM output (CONTROL see Table 37) and remote thermal diode measurement
capability the boxed processor will operate as follows:
As processor power has increased the required thermal solutions have generated
increasingly more noise. Intel has added an option to the boxed processor that allows
system integrators to have a quieter system in the most common usage.
The 4th wire PWM solution provides better control over chassis acoustics. This is
achieved by more accurate measurement of processor die temperature through the
processor's temperature diode (T-diode). Fan RPM is modulated through the use of an
ASIC located on the motherboard that sends out a PWM control signal to the 4th pin
of the connector labeled as CONTROL. The fan speed is based on actual processor
temperature instead of internal ambient chassis temperatures.
If the new 4-pin active fan heat sink solution is connected to an older 3-pin
baseboard processor fan header it will default back to a thermistor controlled mode,
allowing compatibility with existing 3-pin baseboard designs. Under thermistor
controlled mode, the fan RPM is automatically varied based on the Tinlet temperature
measured by a thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed
control, refer to the appropriate Thermal and Mechanical Design Guidelines (see
Section 1.2).
§ §
106
Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
8
Balanced Technology Extended
(BTX) Boxed Processor
Specifications
The processor is offered as an Intel boxed processor. Intel boxed processors are
intended for system integrators who build systems from largely standard components.
The boxed processor will be supplied with a cooling solution known as the Thermal
Module Assembly (TMA). Each processor will be supplied with one of the two available
types of TMAs – Type I or Type II. This chapter documents motherboard and system
requirements for both the TMAs that will be supplied with the boxed processor in the
775-land LGA package. This chapter is particularly important for OEMs that
manufacture motherboards for system integrators. Figure 39 shows a mechanical
representation of a boxed processor in the 775-land LGA package with a Type I TMA.
Figure 40 illustrates a mechanical representation of a boxed processor in the 775-land
LGA package with Type II TMA.
Note:
Note:
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and
inches [in brackets].
Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the appropriate Thermal and Mechanical Design
Guidelines (see Section 1.2) for further guidance.
Figure 39.
Mechanical Representation of the Boxed Processor with a Type I TMA
NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but
the basic shape and size will remain the same.
Datasheet
107
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 40.
Mechanical Representation of the Boxed Processor with a Type II TMA
NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but
the basic shape and size will remain the same.
8.1
Mechanical Specifications
8.1.1
Balanced Technology Extended (BTX) Type I and Type II
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor TMA. The
boxed processor will be shipped with an unattached TMA. Figure 41 shows a
mechanical representation of the boxed processor in the 775-land LGA package for
Type I TMA. Figure 42 shows a mechanical representation of the boxed processor in the
775-land LGA package for Type II TMA. The physical space requirements and
dimensions for the boxed processor with assembled fan thermal module are shown.
108
Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 41.
Requirements for the Balanced Technology Extended (BTX) Type I Keep-out
Volumes
NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.
Datasheet
109
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 42.
Requirements for the Balanced Technology Extended (BTX) Type II Keep-out
Volume
NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.
8.1.2
Boxed Processor Thermal Module Assembly Weight
The boxed processor thermal module assembly for Type I BTX will not weigh more than
1200 grams. The boxed processor thermal module assembly for Type II BTX will not
weigh more than 1200 grams. See Chapter 3 and the appropriate Thermal and
Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and
thermal module assembly requirements.
110
Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
8.1.3
Boxed Processor Support and Retention Module (SRM)
The boxed processor TMA requires an SRM assembly provided by the chassis
manufacturer. The SRM provides the attach points for the TMA and provides structural
support for the board by distributing the shock and vibration loads to the chassis base
pan. The boxed processor TMA will ship with the heatsink attach clip assembly, duct
and screws for attachment. The SRM must be supplied by the chassis hardware vendor.
See the Support and Retention Module(SRM) External Design Requirements Document,
Balanced Technology Extended (BTX) System Design Guide, and the appropriate
Thermal and Mechanical Design Guidelines (see Section 1.2) for more detailed
information regarding the support and retention module and chassis interface and
keepout zones. Figure 43 illustrates the assembly stack including the SRM.
Figure 43.
Assembly Stack Including the Support and Retention Module
Thermal Module Assembly
• Heatsink & Fan
• Clip
• Structural Duct
Motherboard
SRM
Chassis Pan
Datasheet
111
Balanced Technology Extended (BTX) Boxed Processor Specifications
8.2
Electrical Requirements
8.2.1
Thermal Module Assembly Power Supply
The boxed processor's Thermal Module Assembly (TMA) requires a +12 V power supply.
The TMA will include power cable to power the integrated fan and will plug into the 4-
wire fan header on the baseboard. The power cable connector and pinout are shown in
Figure 44. Baseboards must provide a compatible power header to support the boxed
processor. Table 39contains specifications for the input and output signals at the TMA.
The TMA outputs a SENSE signal, which is an open-collector output that pulses at a rate
of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the
system board-mounted fan speed monitor requirements, if applicable. Use of the
SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should
be tied to GND.
The TMA receives a Pulse Width Modulation (PWM) signal from the motherboard from
the 4th pin of the connector labeled as CONTROL.
Note:
The boxed processor’s TMA requires a constant +12 V supplied to pin 2 and does not
support variable voltage control or 3-pin PWM control.
The power header on the baseboard must be positioned to allow the TMA power cable
to reach it. The power header identification and location should be documented in the
platform documentation, or on the system board itself. Figure 45 shows the location of
the fan power connector relative to the processor socket. The baseboard power header
should be positioned within 4.33 inches from the center of the processor socket.
Figure 44.
Boxed Processor TMA Power Cable Connector Description
Signal
Pin
Straight square pin, 4-pin terminal housing with
polarizing ribs and friction locking ramp.
1
2
3
4
GND
+12 V
0.100" pitch, 0.025" square pin width.
SENSE
CONTROL
Match with straight pin, friction lock header on
mainboard.
3 4
1 2
112
Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
Table 39.
TMA Power and Signal Specifications
Description
Min
Typ
Max
Unit
Notes
+12V: 12 volt fan power supply
10.2
12
13.8
V
IC:
- Peak Fan current draw
- Fan start-up current draw
—
—
—
1.0
—
1.5
2.0
1.0
A
A
- Fan start-up current draw maximum
duration
—
Second
pulses per
fan
1
SENSE: SENSE frequency
—
2
—
revolution
2,
3
CONTROL
21
25
28
kHz
NOTES:
1. Baseboard should pull this pin up to 5V with a resistor.
2. Open Drain Type, Pulse Width Modulated.
3. Fan will have a pull-up resistor for this signal to maximum 5.25 V.
Figure 45.
Balanced Technology Extended (BTX) Mainboard Power Header Placement
(hatched area)
Datasheet
113
Balanced Technology Extended (BTX) Boxed Processor Specifications
8.3
Thermal Specifications
This section describes the cooling requirements of the thermal module assembly
solution used by the boxed processor.
8.3.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a TMA. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
case temperature specification is listed in Chapter 5. The boxed processor TMA is able
to keep the processor temperature within the specifications (see Table 26) for chassis
that provide good thermal management. For the boxed processor TMA to operate
properly, it is critical that the airflow provided to the TMA is unimpeded. Airflow of the
TMA is into the duct and out of the rear of the duct in a linear flow. Blocking the airflow
to the TMA inlet reduces the cooling efficiency and decreases fan life. Filters will reduce
or impede airflow which will result in a reduced performance of the TMA. The air
temperature entering the fan should be kept below 35.5 °C. Meeting the processor's
temperature specification is the responsibility of the system integrator.
In addition, Type I TMA must be used with Type I chassis only and Type II TMA with
Type II chassis only. Type I TMA will not fit in a Type II chassis due to the height
difference. In the event a Type II TMA is installed in a Type I chassis, the gasket on the
chassis will not seal against the Type II TMA and poor acoustic performance will occur
as a result.
8.3.2
Variable Speed Fan
The boxed processor fan operates at different speeds over a short range of
temperatures based on a thermistor located in the fan hub area. This allows the boxed
processor fan to operate at a lower speed and noise level while thermistor
temperatures are low. If the thermistor senses a temperatures increase beyond a lower
set point, the fan speed will rise linearly with the temperature until the higher set point
is reached. At that point, the fan speed is at its maximum. As fan speed increases, so
do fan noise levels. These set points are represented in Figure 46 and Table 40. The
internal chassis temperature should be kept below 35.5 ºC. Meeting the processor’s
temperature specification (see Chapter 5) is the responsibility of the system integrator.
Note:
The motherboard must supply a constant +12 V to the processor’s power header to
ensure proper operation of the variable speed fan for the boxed processor (refer to
Table 40) for the specific requirements).
114
Datasheet
Balanced Technology Extended (BTX) Boxed Processor Specifications
Figure 46.
Boxed Processor TMA Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X
Y
Z
Internal Chassis Temperature (Degrees C)
Table 40.
TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed
Processors
Boxed Processor
TMA Set Point
(ºC)
Boxed Processor Fan Speed
Notes
When the internal chassis temperature is below or equal to this
set point, the fan operates at its lowest speed. Recommended
maximum internal chassis temperature for nominal operating
environment.
X ≤ 23
1
When the internal chassis temperature is at this point, the fan
operates between its lowest and highest speeds.
Recommended maximum internal chassis temperature for
worst-case operating environment.
Y = 29
When the internal chassis temperature is above or equal to this
set point, the fan operates at its highest speed.
Z ≥ 35.5
1
NOTES:
1.
Set point variance is approximately ±1°C from Thermal Module Assembly to Thermal
Module Assembly.
If the boxed processor TMA 4-pin connector is connected to a 4-pin motherboard
header and the motherboard is designed with a fan speed controller with PWM output
(see CONTROL in Table 39) and remote thermal diode measurement capability, the
boxed processor will operate as described in the following paragraphs.
As processor power has increased, the required thermal solutions have generated
increasingly more noise. Intel has added an option to the boxed processor that allows
system integrators to have a quieter system in the most common usage.
The 4-wire PWM controlled fan in the TMA solution provides better control over chassis
acoustics. It allows better granularity of fan speed and lowers overall fan speed than a
voltage-controlled fan. Fan RPM is modulated through the use of an ASIC located on
Datasheet
115
Balanced Technology Extended (BTX) Boxed Processor Specifications
the motherboard that sends out a PWM control signal to the 4th pin of the connector
labeled as CONTROL. The fan speed is based on a combination of actual processor
temperature and thermistor temperature.
If the 4-wire PWM controlled fan in the TMA solution is connected to a 3-pin baseboard
processor fan header it will default back to a thermistor controlled mode, allowing
compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode,
the fan RPM is automatically varied based on the Tinlet temperature measured by a
thermistor located at the fan inlet.
For more details on specific motherboard requirements for 4-wire based fan speed
control, refer to the appropriate Thermal and Mechanical Design Guidelines (see
Section 1.2).
§ §
116
Datasheet
Debug Tools Specifications
9
Debug Tools Specifications
9.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get
specific information about their logic analyzer interfaces. The following information is
general in nature. Specific information must be obtained from the logic analyzer
vendor.
Due to the complexity of systems, the LAI is critical in providing the ability to probe and
capture FSB signals. There are two sets of considerations to keep in mind when
designing a system that can make use of an LAI: mechanical and electrical.
9.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug
into the processor socket, while the processor lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection
between the processor and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be
obtained from the logic analyzer vendor. System designers must make sure that the
keepout volume remains unobstructed inside the system. Note that it is possible that
the keepout volume reserved for the LAI may differ from the space normally occupied
by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
9.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system
level simulations to prove that their tool will work in the system. Contact the logic
analyzer vendor for electrical specifications and load models for the LAI solution it
provides.
§ §
Datasheet
117
Debug Tools Specifications
118
Datasheet
相关型号:
©2020 ICPDF网 联系我们和版权申明