BXM80535GC1400E_技术文档

Intel^®Pentium^®M Processor

Datasheet

April 2004

Order Number: 252612-003

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patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information

contained herein supersedes previously published specifications on these devices from Intel.

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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

THE INTEL® PENTIUM® M PROCESSOR MAY CONTAIN DESIGN DEFECTS OR ERRORS KNOWN AS ERRATA WHICH MAY CAUSE THE PRODUCT TO DEVIATE FROM

PUBLISHED SPECIFICATIONS. CURRENT CHARACTERIZED ERRATA ARE AVAILABLE ON REQUEST.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-

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Intel, Intel logo, Pentium, and Intel SpeedStep, and Intel Centrino are registered trademarks or trademarks of Intel Corporation and its subsidiaries in

the United States and other countries.

* Other brands and names are the property of their respective owners.

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Intel^®Pentium^®M Processor Datasheet

Contents

1

Introduction ......................................................................................................................7

1.1

1.2

Terminology ...........................................................................................................8

References.............................................................................................................9

2

Low Power Features ......................................................................................................11

2.1

Clock Control and Low Power States...................................................................11

2.1.1 Normal State ...........................................................................................11

2.1.2 AutoHALT Powerdown State...................................................................11

2.1.3 HALT/Grant Snoop State ........................................................................12

2.1.4 Sleep State..............................................................................................12

2.1.5 Deep Sleep State....................................................................................13

2.1.6 Deeper Sleep State.................................................................................13

Enhanced Intel SpeedStep^®Technology.............................................................13

Processor System Bus Low Power Enhancements.............................................14

Processor Power Status Indicator (PSI#) Signal..................................................15

2.2

2.3

2.4

3

Electrical Specifications................................................................................................17

3.1

3.2

3.3

System Bus and GTLREF....................................................................................17

Power and Ground Pins.......................................................................................17

Decoupling Guidelines.........................................................................................17

3.3.1 VCC Decoupling......................................................................................18

3.3.2 System Bus AGTL+ Decoupling..............................................................18

3.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking ........................18

Voltage Identification............................................................................................18

Catastrophic Thermal Protection..........................................................................20

Signal Terminations and Unused Pins.................................................................20

System Bus Signal Groups..................................................................................20

CMOS Signals .....................................................................................................21

Maximum Ratings ................................................................................................22

3.4

3.5

3.6

3.7

3.8

3.9

3.10 Processor DC Specifications................................................................................22

4

5

Package Mechanical Specifications and Pin Information ..........................................39

4.1

4.2

Processor Pin-Out and Pin List............................................................................47

Alphabetical Signals Reference ...........................................................................62

Thermal Specifications and Design Considerations ..................................................69

5.1

Thermal Specifications.........................................................................................71

5.1.1 Thermal Diode.........................................................................................71

5.1.2 Intel Thermal Monitor ..............................................................................72

6

Debug Tools Specifications ..........................................................................................75

6.1

Logic Analyzer Interface (LAI)..............................................................................75

6.1.1 Mechanical Considerations.....................................................................75

6.1.2 Electrical Considerations.........................................................................75

Intel^®Pentium^®M Processor Datasheet

3

Figures

1

Clock Control States................................................................................................................... 11

2

3

4

5

6

7

8

9

Illustration of Active State VCC Static and Ripple Tolerances (Highest Frequency Mode)........28

Illustration of Deep Sleep State Voltage Tolerances (Lowest Frequency Mode) ....................... 30

Micro-FCPGA Package Top and Bottom Isometric Views ......................................................... 39

Micro-FCPGA Package - Top and Side Views........................................................................... 40

Micro-FCPGA Package - Bottom View.......................................................................................41

Intel Pentium M Processor Die Offset ........................................................................................ 41

Micro-FCBGA Package Top and Bottom Isometric Views ......................................................... 43

Micro-FCBGA Package Top and Side Views ............................................................................. 44

Micro-FCBGA Package Bottom View .........................................................................................46

The Coordinates of the Processor Pins as Viewed From the Top of the Package..................... 48

10

11

4

Intel^®Pentium^®M Processor Datasheet

Tables

1

2

3

4

5

6

7

References ...................................................................................................................................9

Voltage Identification Definition ..................................................................................................19

System Bus Pin Groups..............................................................................................................21

Processor DC Absolute Maximum Ratings.................................................................................22

Voltage and Current Specifications ............................................................................................23

Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Active State) ....27

Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Deep Sleep

State) ..........................................................................................................................................29

Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Active State) ....31

Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Deep Sleep

State) ..........................................................................................................................................32

Voltage Tolerances for Low Voltage Intel Pentium M Processors (Active State) .......................33

Voltage Tolerances for Low Voltage Intel Pentium M Processors (Deep Sleep State) ..............34

Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Active State)...............35

Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Deep Sleep State)......36

System Bus Differential BCLK Specifications.............................................................................37

AGTL+ Signal Group DC Specifications.....................................................................................37

CMOS Signal Group DC Specifications......................................................................................38

Open Drain Signal Group DC Specifications..............................................................................38

Micro-FCPGA Package Dimensions...........................................................................................42

Micro-FCBGA Package Dimensions...........................................................................................45

Pin Listing by Pin Name..............................................................................................................49

Pin Listing by Pin Number ..........................................................................................................55

Signal Description.......................................................................................................................62

Power Specifications for the Intel Pentium M Processor............................................................70

Thermal Diode Interface .............................................................................................................71

Thermal Diode Specifications.....................................................................................................71

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Intel^®Pentium^®M Processor Datasheet

5

Revision History

Document

Revision

Number

Description

Date

March 2003

252612

001

Initial release of datasheet

Updates include:

•

Added specifications for Intel Pentium M Processor 1.7 GHz, Low

Voltage Pentium M processor 1.2 GHz, and Ultra Low Voltage

Pentium M processor 1 GHz in Table 5 and Table 23

252612

002

June 2003

Updates include:

•

Added specifications for Intel Pentium M Processor Low Voltage

252612

003

1.30 GHz, and Intel Pentium M Processor Ultra Low Voltage 1.10 March 2004

GHz in Table 5 and Table 23

•

Updated DINV[3:0]# and BPM[3]# pin direction

6

Intel^®Pentium^®M Processor Datasheet

Introduction

1 Introduction

This document provides electrical, mechanical, and thermal specifications for the Intel^®Pentium^®

M processor.

The Intel Pentium M processor is offered at the following core frequencies:

• 1.30 GHz

• 1.40 GHz

• 1.50 GHz

• 1.60 GHz

• 1.70 GHz

The Low Voltage Intel Pentium M processor is offerred at the following core frequencies:

• 1.10 GHz

• 1.20 GHz

• 1.30 GHz

The Ultra Low Voltage Intel Pentium M processor is offered at the following core frequencies:

• 900 MHz

• 1.00 GHz

• 1.10 GHz

Key features of the Intel Pentium M processor incldue:

• Supports Intel^®Architecture with Dynamic Execution

• High performance, low-power core

• On-die, primary 32-kB instruction cache and 32-kB write-back data cache

• On-die, 1-MB second level cache with Advanced Transfer Cache Architecture

• Advanced Branch Prediction and Data Prefetch Logic

• Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in

multimedia applications including 3D graphics, video decoding/encoding, and speech

recognition.

• 400-MHz, Source-Synchronous processor system bus to improve performance by transferring

data four times per bus clock (4X data transfer rate, as in AGP 4X).

• Advanced Power Management features including Enhanced Intel SpeedStep^®technology

• Micro-FCPGA and Micro-FCBGA packaging technologies

• Manufactured on Intel’s advanced 0.13 micron process technology with copper interconnect.

• Support for MMX^™technology

• Internet Streaming SIMD instructions and full compatibility with IA-32 software.

Intel^®Pentium^®M Processor Datasheet

7

Introduction

• Micro-op Fusion and Advanced Stack Management that reduce the number of micro-ops

handled by the processor.

• Advanced branch prediction architecture that significantly reduces the number of mispredicted

branches.

• Double-precision floating-point instructions enhance performance for applications that require

greater range and precision, including scientific and engineering applications and advanced 3D

geometry techniques, such as ray tracing.

Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other Intel

products.

The Intel Pentium M processor is offered in two packages: a socketable Micro Flip-Chip Pin Grid

Array (Micro-FCPGA) and a surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA)

package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero

insertion force (ZIF) socket, which is referred to as the mPGA479M socket.

1.1

Terminology

A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a

hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

“System Bus” refers to the interface between the processor and system core logic (also known as

the chipset components).

8

Intel^®Pentium^®M Processor Datasheet

Introduction

1.2

References

Material and concepts available in the following documents may be beneficial when reading this

document. Also, please note that “platform design guides,” when used throughout this document,

refers to the following documents: Intel^®855PM MHz Chipset Platform Design Guide and Intel^®

855GM Chipset Platform Design Guide.

Table 1. References

Document

Order Number

Intel^®855PM Chipset Platform Design Guide

Intel^®855PM Chipset Datasheet

http://developer.intel.com

Intel^®855PM Chipset Specification Update

Intel^®855GM Chipset Platform Design Guide

Intel^®855GM Chipset Datasheet

Intel^®855GM Chipset Specification Update

Intel^®Pentium^®M Processor Specification Update

Intel Architecture Software Developer's Manual

Volume I: Basic Architecture

Volume II: Instruction Set Reference

Volume III: System Programming Guide

ITP700 Debug Port Design Guide

http://developer.intel.com

NOTE: Contact your Intel representative for the latest revision and order number of this document.

Intel^®Pentium^®M Processor Datasheet

9

Introduction

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IIntel^®Pentium^®M Processor Datasheet

Low Power Features

2 Low Power Features

2.1

Clock Control and Low Power States

The Intel Pentium M processor supports the AutoHALT, Stop-Grant, Sleep, Deep Sleep, and

Deeper Sleep states for optimal power management. See Figure 1 for a visual representation of the

processor low-power states.

Figure 1. Clock Control States

SLP# asserted

STPCLK# asserted

Stop

Grant

Normal

Sleep

STPCLK# de-asserted

SLP# de-asserted

STPCLK#

asserted

halt

break

DPSLP#

de-asserted

DPSLP#

asserted

snoop

serviced

HLT

snoop

occurs

STPCLK#

de-asserted

instruction

core voltage raised

snoop

occurs

HALT/

Grant

Snoop

Deeper

Sleep

Deep

Sleep

Auto Halt

snoop

serviced

core voltage lowered

V0001-04

Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

2.1.1

2.1.2

Normal State

This is the normal operating state for the processor.

AutoHALT Powerdown State

AutoHALT is a low-power state entered when the processor executes the HALT instruction. The

processor transitions to the Normal state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI,

INTR), or PSB interrupt message. RESET# will cause the processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal state or the

AutoHALT Powerdown state. See the Intel Architecture Software Developer's Manual, Volume III:

System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state.

When the system deasserts the STPCLK# interrupt, the processor will return execution to the

HALT state.

Intel^®Pentium^®M Processor Datasheet

11

Low Power Features

While in AutoHALT Powerdown state, the processor will process bus snoops. Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks

after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle.

Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven

(allowing the level to return to V_CCP) for minimum power drawn by the termination resistors in this

state. In addition, all other input pins on the system bus should be driven to the inactive state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the

STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be

deasserted ten or more bus clocks after the de-assertion of SLP#.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the

system bus (see Section 2.1.3). A transition to the Sleep state (see Section 2.1.4) will occur with the

assertion of the SLP# signal.

While in the Stop-Grant state, SMI#, INIT# and LINT[1:0] will be latched by the processor, and

only serviced when the processor returns to the Normal state. Only one occurrence of each event

will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process snoops on the system bus and it will latch

interrupts delivered on the system bus.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if

there is any pending interrupt latched within the processor. Pending interrupts that are blocked by

the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to

system logic that it should return the processor to the Normal state

2.1.3

2.1.4

HALT/Grant Snoop State

The processor will respond to snoop or interrupt transactions on the system bus while in Stop-Grant

state or in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor

enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the

system bus has been serviced (whether by the processor or another agent on the system bus) or the

interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will

return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

Sleep State

The Sleep state is a low power state in which the processor maintains its context, maintains the

phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered

from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon

the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the

Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state are out of

specification and may result in unapproved operation.

Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will

cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching

interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or

RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an

input signal before the processor has returned to Stop-Grant state will result in unpredictable

behavior.

12

Intel^®Pentium^®M Processor Datasheet

Low Power Features

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in

the RESET# pin specification, then the processor will reset itself, ignoring the transition through

Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and

STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the

processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power state, the Deep

Sleep state by asserting the DPSLP# pin. (See Section 2.1.5.) While the processor is in the Sleep

state, the SLP# pin must be deasserted if another asynchronous system bus event needs to occur.

2.1.5

Deep Sleep State

Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep

Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped

during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings

on Intel 855PM and Intel 855GM chipset-based platforms are as follows:

• Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The platform clock

chip will stop/tristate BCLK within 2 BCLKs +/- a few nanoseconds.

• Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The platform clock

chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6

BCLK periods later.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-started after

DPSLP# deassertion as described above. A period of 30 microseconds (to allow for PLL

stabilization) must occur before the processor can be considered to be in the Sleep state. Once in

the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions of signals are allowed on the system bus while the

processor is in Deep Sleep state. Any transition on an input signal before the processor has returned

to Stop-Grant state will result in unpredictable behavior.

2.1.6

2.2

Deeper Sleep State

The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally

identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage

regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer

to the platform design guides for details.

Enhanced Intel SpeedStep^®Technology

The Intel Pentium M processor features Enhanced Intel SpeedStep^®technology. Unlike previous

implementations of Intel SpeedStep technology, this technology enables the processor to switch

between multiple frequency and voltage points instead of two. This will enable superior

performance with optimal power savings. Switching between states is software controlled unlike

previous implementations where the GHI# pin is used to toggle between two states. The following

are the key features of Enhanced Intel SpeedStep technology:

• Multiple voltage/frequency operating points provide optimal performance at the lowest power.

• Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model

Specific Registers) thus eliminating chipset dependency.

Intel^®Pentium^®M Processor Datasheet

13

Low Power Features

— If the target frequency is higher than the current frequency, Vcc is ramped up by placing a

new value on the VID pins and the PLL then locks to the new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the new

frequency and the Vcc is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in progress, the

new transition is deferred until its completion.

• The processor controls voltage ramp rates internally to ensure glitch free transitions.

• Low transition latency and large number of transitions possible per second.

— Processor core (including L2 cache) is unavailable for up to 10 µs during the frequency

transition

— The bus protocol (BNR# mechanism) is used to block snooping

• No bus master arbiter disable required prior to transition and no processor cache flush

necessary.

• Improved Intel Thermal Monitor mode.

— When the on-die thermal sensor indicates that the die temperature is too high, the

processor can automatically perform a transition to a lower frequency/voltage specified in

a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to acceptable

levels, an up transition to the previous frequency/voltage point occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling

better system level thermal management.

2.3

Processor System Bus Low Power Enhancements

The Intel Pentium M processor incorporates the following processor system bus low power

enhancements:

• Dynamic FSB power down

• BPRI# control for address and control input buffers

• Dynamic on-die termination disabling

• Low VCCP (I/O termination voltage)

The Intel Pentium M processor incorporates the DPWR# signal that controls the Data Bus input

buffers on the processor. The DPWR# signal disables the buffers when not used and activates them

only when data bus activity occurs, resulting in significant power savings with no performance

impact. BPRI# control also allows the processor address and control input buffers to be turned off

when the BPRI# signal is inactive. The On Die Termination on the processor PSB buffers is

disabled when the signals are driven low, resulting in additional power savings. The low I/O

termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/

O switching power at all times.

14

Intel^®Pentium^®M Processor Datasheet

Low Power Features

2.4

Processor Power Status Indicator (PSI#) Signal

The Intel Pentium M processor incorporates the PSI# signal that is asserted when the processor is

in a low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry

and deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage

regulator, resulting in platform power savings and extended battery life. PSI# can also be used to

simplify voltage regulator designs since it removes the need for integrated 100 µs timers required

to mask the PWRGOOD signal during Deeper Sleep transitions. It also reduces PWRGOOD

monitoring requirements in the Deeper Sleep state.

Intel^®Pentium^®M Processor Datasheet

15

Low Power Features

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IIntel^®Pentium^®M Processor Datasheet

Electrical Specifications

3 Electrical Specifications

3.1

System Bus and GTLREF

The Intel Pentium M processor system bus signals use Advanced Gunning Transceiver Logic

(AGTL+) signalling technology, a variant of GTL+ signalling technology with low power

enhancements. This signalling technology provides improved noise margins and reduced ringing

through low-voltage swings and controlled edge rates. The termination voltage level for the Intel

Pentium M processor AGTL+ signals is VCCP = 1.05 V (nominal). Due to speed improvements to

data and address bus, signal integrity and platform design methods have become more critical than

with previous processor families. Design guidelines for the Intel Pentium M processor system bus

are detailed in the platform design guides.

The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine

if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board.

Termination resistors are provided on the processor silicon and are terminated to its I/O voltage

(VCCP). The Intel 855PM and Intel 855GM chipsets also provide on-die termination, thus

eliminating the need to terminate the bus on the system board for most AGTL+ signals.

Refer to the platform design guides for board level termination resistor requirements.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

system bus, including trace lengths, is highly recommended when designing a system.

3.2

3.3

Power and Ground Pins

For clean on-chip power distribution, the Intel Pentium M processor has a large number of V_CC

(power) and V_SS(ground) inputs. All power pins must be connected to V_CCpower planes while all

V_SSpins must be connected to system ground planes. Use of multiple power and ground planes is

recommended to reduce I*R drop. Please refer to the platform design guides for more details. The

processor V_CCpins must be supplied the voltage determined by the VID (Voltage ID) pins.

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large average current swings between low and full power states. This may cause

voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.

Care must be taken in the board design to ensure that the voltage provided to the processor remains

within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced

lifetime of the component. For further information and design guidelines, refer to the platform

design guides.

Intel^®Pentium^®M Processor Datasheet

17

Electrical Specifications

3.3.1

V_CCDecoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low-power states, must be

provided by the voltage regulator solution. For more details on decoupling recommendations,

please refer to the platform design guides. It is strongly recommended that the layout and

decoupling recommendations in the design guides be followed.

3.3.2

3.3.3

System Bus AGTL+ Decoupling

Intel Pentium M processors integrate signal termination on the die as well as incorporate high

frequency decoupling capacitance on the processor package. Decoupling must also be provided by

the system motherboard for proper AGTL+ bus operation. For more information, refer to the

platform design guides.

System Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the

processor. As in previous generation processors, the Intel Pentium M processor core frequency is a

multiple of the BCLK[1:0] frequency. In regards to processor clocking, the Intel Pentium M

processor uses a differential clocking implementation.

3.4

Voltage Identification

The Intel Pentium M processor uses six voltage identification pins, VID[5:0], to support automatic

selection of power supply voltages. The VID pins for the Intel Pentium M processor are CMOS

outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to

the state of VID[5:0]. A “1” in this refers to a high-voltage level and a “0” refers to low-voltage

level.

18

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 2. Voltage Identification Definition

VID

V_CC

V

V_CC

V

5

4

3

2

1

0

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.196

1.164

1.148

1.132

1.116

1.100

1.084

1.068

1.052

1.036

1.020

1.004

0.988

0.972

0.956

0.940

0.924

0.908

0.892

0.876

0.860

0.844

0.828

0.812

0.796

0.780

0.764

0.748

0.732

0.716

0.700

1.708

1.676

1.660

1.644

1.628

1.612

1.596

1.580

1.564

1.548

1.532

1.516

1.500

1.484

1.468

1.452

1.436

1.420

1.404

1.388

1.372

0

1

0

1

0

1

0

1

1.356

1.340

1.324

1.308

1.292

1.276

1.260

1.244

1.228

1.212

Intel^®Pentium^®M Processor Datasheet

19

Electrical Specifications

3.5

Catastrophic Thermal Protection

The Intel Pentium M processor supports the THERMTRIP# signal for catastrophic thermal

protection. An external thermal sensor should also be used to protect the processor and the system

against excessive temperatures. Even with the activation of THERMTRIP#, that halts all processor

internal clocks and activity, leakage current can be high enough such that the processor cannot be

protected in all conditions without the removal of power to the processor. If the external thermal

sensor detects a catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP#

signal is asserted, the VCC supply to the processor must be turned off within

500 ms to prevent permanent silicon damage due to thermal runaway.

3.6

Signal Terminations and Unused Pins

All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to V_CC, V_SS, or

to any other signal (including each other) can result in component malfunction or incompatibility

with future Intel Pentium M processors. See Section 4.2 for a pin listing of the processor and the

location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is

provided on the processor silicon. Unused active high inputs should be connected through a resistor

to ground (V_SS). Unused outputs can be left unconnected.

For details on signal terminations, please refer to the platform design guides. TAP signal

termination requirements are also discussed in ITP700 Debug Port Design Guide.

The TEST1, TEST2, and TEST3 pins must be left unconnected but should have a stuffing option

connection to V_SSseparately using 1-kΩ, pull-down resistors.

3.7

System Bus Signal Groups

To simplify the following discussion, the system bus signals have been combined into groups by

buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference

level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the

AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group

as well as the AGTL+ I/O group when driving.

Table 3 identifies which signals are common clock, source synchronous, and asynchronous.

Common clock signals which are dependent upon the crossing of the rising edge of BCLK0 and the

falling edge of BCLK1. Source synchronous signals are relative to their respective strobe lines

(data and address) as well as the rising edge of BCLK0. Asychronous signals are still present

(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.

20

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 3. System Bus Pin Groups

Signal Group

Type

Signals

Synchronous

to BCLK[1:0]

BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#,

TRDY#

AGTL+ Common Clock Input

AGTL+ Common Clock I/O

Synchronous

to BCLK[1:0]

ADS#, BNR#, BPM[3:0]#¹, BR0#, DBSY#, DRDY#, HIT#,

HITM#, LOCK#, PRDY#¹

Signals

Associated Strobe

ADSTB[0]#

REQ[4:0]#, A[16:3]#

A[31:17]#

ADSTB[1]#

Synchronous

AGTL+ Source Synchronous I/O to associated

strobe

D[15:0]#, DINV0#

D[31:16]#, DINV1#

D[47:32]#, DINV2#

D[63:48]#, DINV3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

Synchronous

AGTL+ Strobes

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

to BCLK[1:0]

A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/

NMI, PWRGOOD, SMI#, SLP#, STPCLK#

CMOS Input

Asynchronous

Open Drain Output

CMOS Output

Asynchronous FERR#, IERR#, PROCHOT#, THERMTRIP#

Asynchronous PSI#, VID[5:0]

Synchronous

CMOS Input

TCK, TDI, TMS, TRST#

to TCK

Synchronous

TDO

Open Drain Output

System Bus Clock

to TCK

Clock

BCLK[1:0], ITP_CLK[1:0]

COMP[3:0], DBR#², GTLREF, RSVD, TEST3, TEST2,

TEST1, THERMDA, THERMDC, V_CC, V_CCA[3:0], V_CCP,

Power/Other

V

_CCQ[1:0], V_{CC_SENSE}, V_SS,V_{SS_SENSE}

NOTES:

1. BPM[2:0]# and PRDY# are AGTL+ output only signals.

2. In processor systems where there is no debug port implemented on the system board, these signals are used

to support a debug port interposer. In systems with the debug port implemented on the system board, these

signals are no connects

3.8

CMOS Signals

CMOS input signals are shown in Table 3. Legacy output FERR#, IERR# and other non-AGTL+

signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. All of the CMOS

signals are required to be asserted for at least three BCLKs in order for the chipset to recognize

them. See Section 3.10 for the DC specifications of the CMOS signal groups.

Intel^®Pentium^®M Processor Datasheet

21

Electrical Specifications

3.9

Maximum Ratings

Table 4 lists the processor’s maximum environmental stress ratings. The processor should not

receive a clock while subjected to these conditions. Functional operating parameters are listed in

the DC tables. Extended exposure to the maximum ratings may affect device reliability.

Furthermore, although the processor includes protective circuitry to resist damage from Electro

Static Discharge (ESD), system designers must always take precautions to avoid high static

voltages or electric fields.

Table 4. Processor DC Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

Processor storage

temperature

TSTORAGE

–40

85

°C

2

Any processor supply

voltage with respect to V_SS

V_CC

-0.3

-0.1

1.75

V

1

AGTL+ buffer DC input

voltage with respect to V_SS

V_inAGTL+

V_{inAsynch_CMOS}

1, 2

CMOS buffer DC input

voltage with respect to V_SS

NOTES:

1. This rating applies to any processor pin.

2. Contact Intel for storage requirements in excess of one year.

3.10

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless

noted otherwise. See Table 15 for the pin signal definitions and signal pin assignments. Most of

the signals on the processor system bus are in the AGTL+ signal group and the DC specifications

for these signals are also listed. DC specifications for the CMOS group are listed in Table 16.

Table 5 through Table 16 list the DC specifications for the Intel Pentium M processor and are valid

only while meeting specifications for junction temperature, clock frequency, and input voltages.

The Highest Frequency (HFM) and Lowest Frequency Modes (LFM) refer to the highest and

lowest core operating frequencies supported on the processor. Active Mode load line specifications

apply in all states except in the Deep Sleep and Deeper Sleep states. V_CC,BOOTis the default

voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified

otherwise, all specifications for the Intel Pentium M processor are at Tjunction = 100°C. Care

should be taken to read all notes associated with each parameter.

22

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 5. Voltage and Current Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes

Intel Pentium M processor 1.70

GHz Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

1.70 GHz

1.40 GHz

1.20 GHz

1.00 GHz

800 MHz

600 MHz

1.484

1.308

1.228

1.116

1.004

0.956

V_CC17

V

1, 2

Intel Pentium M processor 1.60

GHz Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

1.60 GHz

1.40 GHz

1.20 GHz

1.00 GHz

800 MHz

600 MHz

V_CC16

1.484

1.420

1.276

1.164

1.036

0.956

V

1, 2

Intel Pentium M processor 1.50

GHz Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

1.50 GHz

1.40 GHz

1.20 GHz

1.00 GHz

800 MHz

600 MHz

1.484

1.452

1.356

1.228

1.116

0.956

V_CC15

V

1, 2

Intel Pentium M processor 1.40

GHz Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

V_CC14

1.40 GHz

1.20 GHz

1.00 GHz

800 MHz

600 MHz

1.484

1.436

1.308

1.180

0.956

V

1, 2

Intel Pentium M processor 1.30

GHz Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

V_CC13

1.30 GHz

1.20 GHz

1.00 GHz

800 MHz

600 MHz

1.388

1.356

1.292

1.260

0.956

V

1, 2

Intel^®Pentium^®M Processor Datasheet

23

Electrical Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes

Low Voltage Intel Pentium M

processor 1.30 GHz

Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

1.30 GHz

1.20 GHz

1.10 GHz

1.00 GHz

900 MHz

800 MHz

600 MHz

1.180

1.164

1.100

1.020

1.004

0.988

0.956

V_CCLV13

V

1,2

Low Voltage Intel Pentium M

processor 1.20 GHz

Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

V_CCLV12

1.180

1.164

1.100

1.020

1.004

0.956

V

1,2

1.20 GHz

1.10 GHz

1.00 GHz

900 MHz

800 MHz

600 MHz

Low Voltage Intel Pentium M

processor 1.10 GHz

Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

V_{C CLV11}

1.180

1.164

1.100

1.020

0.956

V

1, 2

1.10 GHz

1.00 GHz

900 MHz

800 MHz

600 MHz

Ultra Low Voltage Intel Pentium M

processor 1.10 GHz

Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

V_CCULV11

1.004

0.988

0.972

0.956

0.844

1.10 GHz

1.00 GHz

900 MHz

800 MHz

600 MHz

Ultra Low Voltage Intel Pentium M

processor 1.00 GHz

Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

V_CCULV10

V

1, 2

1.004

0.988

0.972

0.844

1.00 GHz

900 MHz

800 MHz

600 MHz

24

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes

Ultra Low Voltage Intel Pentium M

processor 900 MHz

Core V_CCfor Enhanced Intel

SpeedStep technology operating

points:

V_CCULV9

V

1, 2

1.004

0.988

0.844

900 MHz

800 MHz

600 MHz

Default V_CCVoltage for initial

power up

V_CC,BOOT

1.14

1.20

1.26

2

V_CCP

V_CCA

AGTL+ Termination Voltage

PLL Supply Voltage

0.997

1.71

1.05

1.8

1.102

1.89

V

2

V_CCDPRSLP,TRTransient Deeper Sleep voltage

V_CCDPRSLP,STStatic Deeper Sleep voltage

0.695

0.705

0.748

0.795

0.785

I_CCfor Intel Pentium M processors

I_CCDES

Recommended Design Target

25

A

5

I_CCfor Intel Pentium M processors

by Frequency/Voltage:

600 MHz & 0.844 V

600 MHz & 0.956 V

900 MHz & 1.004 V

1.00 GHz & 1.004 V

1.10 GHz & 1.004 V

1.10 GHz & 1.180 V

1.20 GHz & 1.180 V

1.30 GHz & 1.180 V

1.30 GHz & 1.388 V

1.40 GHz & 1.484 V

1.50 GHz & 1.484 V

1.60 GHz & 1.484 V

1.70 GHz & 1.484 V

5

6.8

9

12

12.5

19

18

21

I_CC

A

3

I_CCAuto-Halt & Stop-Grant at:

0.844 V (ULV Pentium M)

0.956 V

1.004 V (ULV Pentium M)

1.180 V

1.388 V (Pentium M 1.30 GHz)

1.484 V

1.8

3.3

2.7

4.7

9.4

8.6

I_AH,

A

4

I_SGNT

I_CCSleep at:

0.844 V (ULV Pentium M)

0.956 V

1.004 V (ULV Pentium M)

1.180 V

1.388 V (Pentium M 1.30 GHz)

1.484 V

1.7

3.3

2.6

4.6

9.2

8.4

I_SLP

I_CCDeep Sleep at:

0.844 V (ULV Pentium M)

0.956 V

1.004 V (ULV Pentium M)

1.180 V

1.388 V (Pentium M 1.30 GHz)

1.484 V

1.6

3.1

2.3

4.2

8.8

7.8

I_DSLP

A

4

I_DPRSLP

I_CCDeeper Sleep

1.8

Intel^®Pentium^®M Processor Datasheet

25

Electrical Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes

I_CCDeeper Sleep (ULV Intel

Pentium M only)

I_DPRSLPULV

1.2

A

4

V_CCpower supply current slew

rate

dI_CC/DT

0.5

A/ns 6, 7

I_CCA

I_CCP

I_CCfor V_CCAsupply

I_CCfor V_CCPsupply

120

2.5

mA

A

NOTES:

1. The typical values shown are the VID encoded voltages. Static and Ripple tolerances (for minimum and

maximum voltages) are defined in the load line tables i.e. Table 6 through Table 13.

2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the

processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe

capacitance, and 1-Mohm minimum impedance. The maximum length of ground wire on the probe should be

less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

3. Specified at V_CC,STATIC(nominal) under maximum signal loading conditions.

4. Specified at the VID voltage.

5. The I_CCDES(max) specification comprehends future processor HFM frequencies. Platforms should be

designed to this specification.

6. Based on simulations and averaged over the duration of any change in current. Specified by design/

characterization at nominal V_CC. Not 100% tested.

7. Measured at the bulk capacitors on the motherboard.

26

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 6. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Active

State)

Highest Frequency Mode: VID = 1.484 V,

Offset = 0%

Lowest Frequency Mode: VID = 0.956 V,

Offset = 0%

Mode

STATIC

Min Max

Ripple

Min

STATIC

Min Max

Ripple

Min Max

I_CC, A V_CC, V

Max

1.516

1.513

1.511

1.508

1.505

1.502

1.500

1.497

1.494

1.491

1.488

1.486

1.483

1.480

1.477

1.475

1.472

1.469

1.466

1.463

1.461

1.458

1.455

1.452

1.450

1.447

1.444

1.441

0

1.484 1.462 1.506 1.452

1.481 1.459 1.503 1.449

1.478 1.456 1.501 1.446

1.476 1.453 1.498 1.443

1.473 1.451 1.495 1.441

1.470 1.448 1.492 1.438

1.467 1.445 1.490 1.435

1.465 1.442 1.487 1.432

1.462 1.440 1.484 1.430

1.459 1.437 1.481 1.427

1.456 1.434 1.478 1.424

0.0

0.4

0.7

1.1

1.4

1.8

2.1

2.5

2.9

3.2

3.6

3.9

4.3

4.7

5.0

5.4

5.7

6.1

6.4

6.8

0.956

0.955

0.954

0.953

0.952

0.951

0.950

0.948

0.947

0.946

0.945

0.944

0.943

0.942

0.941

0.940

0.939

0.938

0.937

0.936

0.942 0.970 0.932 0.980

0.941 0.969 0.931 0.979

0.940 0.968 0.930 0.978

0.938 0.967 0.928 0.977

0.937 0.966 0.927 0.976

0.936 0.965 0.926 0.975

0.935 0.964 0.925 0.974

0.934 0.963 0.924 0.973

0.933 0.962 0.923 0.972

0.932 0.961 0.922 0.971

0.931 0.960 0.921 0.970

0.930 0.959 0.920 0.969

0.929 0.957 0.919 0.967

0.928 0.956 0.918 0.966

0.927 0.955 0.917 0.965

0.926 0.954 0.916 0.964

0.924 0.953 0.914 0.963

0.923 0.952 0.913 0.962

0.922 0.951 0.912 0.961

0.921 0.950 0.911 0.960

0.9

1.9

2.8

3.7

4.6

5.6

6.5

7.4

8.3

9.3

10.2 1.453 1.431 1.476 1.421

11.1 1.451 1.428 1.473 1.418

12.0 1.448 1.426 1.470 1.416

13.0 1.445 1.423 1.467 1.413

13.9 1.442 1.420 1.465 1.410

14.8 1.440 1.417 1.462 1.407

15.7 1.437 1.415 1.459 1.405

16.7 1.434 1.412 1.456 1.402

17.6 1.431 1.409 1.453 1.399

18.5 1.428 1.406 1.451 1.396

19.4 1.426 1.403 1.448 1.393

20.4 1.423 1.401 1.445 1.391

21.3 1.420 1.398 1.442 1.388

22.2 1.417 1.395 1.440 1.385

23.1 1.415 1.392 1.437 1.382

24.1 1.412 1.390 1.434 1.380

25.0 1.409 1.387 1.431 1.377

Intel^®Pentium^®M Processor Datasheet

27

Electrical Specifications

Figure 2. Illustration of Active State V_CCStatic and Ripple Tolerances (Highest Frequency

Mode)

Highest-Frequency Mode (VID = 1.484V): Active

1.540

1.520

1.500

1.484

1.480

1.460

1.440

1.420

1.400

1.380

1.360

0

5

10

15

20

25

Icc, A

STATIC

Static Min

Static Max

Ripple Min

Ripple Max

28

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 7. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Deep Sleep State)

Highest Frequency Mode: VID = 1.484 V,

Offset = 1.2%

Lowest Frequency Mode: VID = 0.956 V,

Offset = 1.2%

Mode

STATIC

Min Max

Ripple

Min Max

STATIC

Min Max

Ripple

Min Max

I

_CC, A V_CC, V

I_CC, A V_CC, V

0.0

0.5

1.0

1.6

2.1

2.6

3.1

3.6

4.2

4.7

5.2

5.7

6.2

6.8

7.3

7.8

1.466 1.444 1.488 1.434 1.498

1.465 1.442 1.487 1.432 1.497

1.463 1.441 1.485 1.431 1.495

1.462 1.439 1.484 1.429 1.494

1.460 1.438 1.482 1.428 1.492

1.458 1.436 1.481 1.426 1.491

1.457 1.435 1.479 1.425 1.489

1.455 1.433 1.478 1.423 1.488

1.454 1.431 1.476 1.421 1.486

1.452 1.430 1.474 1.420 1.484

1.451 1.428 1.473 1.418 1.483

1.449 1.427 1.471 1.417 1.481

1.447 1.425 1.470 1.415 1.480

1.446 1.424 1.468 1.414 1.478

1.444 1.422 1.467 1.412 1.477

1.443 1.421 1.465 1.411 1.475

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

0.945 0.930 0.959 0.920 0.969

0.944 0.930 0.958 0.920 0.968

0.943 0.929 0.958 0.919 0.968

0.943 0.928 0.957 0.918 0.967

0.942 0.928 0.956 0.918 0.966

0.941 0.927 0.956 0.917 0.966

0.941 0.926 0.955 0.916 0.965

0.940 0.926 0.955 0.916 0.965

0.940 0.925 0.954 0.915 0.964

0.939 0.925 0.953 0.915 0.963

0.938 0.924 0.953 0.914 0.963

0.938 0.923 0.952 0.913 0.962

0.937 0.923 0.951 0.913 0.961

0.936 0.922 0.951 0.912 0.961

0.936 0.922 0.950 0.912 0.960

0.936 0.921 0.950 0.911 0.960

Intel^®Pentium^®M Processor Datasheet

29

Electrical Specifications

Figure 3. Illustration of Deep Sleep State Voltage Tolerances (Lowest Frequency Mode)

Lowest-FrequencyMode (VID = 0.956V): Deep Sleep

0.980

0.970

0.960

0.950

0.940

0.930

0.920

0.910

0.900

0.945

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Icc, A

STATIC

Static Min

Static Max

Ripple Min

Ripple Max

30

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 8. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Active

State)

Highest Frequency Mode: VID = 1.388 V,

Offset = 0%

Lowest Frequency Mode: VID = 0.956 V,

Offset = 0%

Mode

STATIC

Min Max

Ripple

Min Max

STATIC

Min Max

Ripple

Min Max

V

_CC, A V_CC, V

I_CC, A V_CC, V

0

1.388 1.367 1.409 1.357 1.419

1.385 1.364 1.406 1.354 1.416

1.382 1.362 1.403 1.352 1.413

1.380 1.359 1.400 1.349 1.410

1.377 1.356 1.398 1.346 1.408

1.374 1.353 1.395 1.343 1.405

1.371 1.351 1.392 1.341 1.402

1.369 1.348 1.389 1.338 1.399

1.366 1.345 1.387 1.335 1.397

1.363 1.342 1.384 1.332 1.394

1.360 1.339 1.381 1.329 1.391

0.0 0.956 0.942 0.970 0.932 0.980

0.4 0.955 0.941 0.969 0.931 0.979

0.7 0.954 0.940 0.968 0.930 0.978

1.1 0.953 0.938 0.967 0.928 0.977

1.4 0.952 0.937 0.966 0.927 0.976

1.8 0.951 0.936 0.965 0.926 0.975

2.1 0.950 0.935 0.964 0.925 0.974

2.5 0.948 0.934 0.963 0.924 0.973

2.9 0.947 0.933 0.962 0.923 0.972

3.2 0.946 0.932 0.961 0.922 0.971

3.6 0.945 0.931 0.960 0.921 0.970

3.9 0.944 0.930 0.959 0.920 0.969

4.3 0.943 0.929 0.957 0.919 0.967

4.7 0.942 0.928 0.956 0.918 0.966

5.0 0.941 0.927 0.955 0.917 0.965

5.4 0.940 0.926 0.954 0.916 0.964

5.7 0.939 0.924 0.953 0.914 0.963

6.1 0.938 0.923 0.952 0.913 0.962

6.4 0.937 0.922 0.951 0.912 0.961

6.8 0.936 0.921 0.950 0.911 0.960

0.9

1.9

2.8

3.7

4.6

5.6

6.5

7.4

8.3

9.3

10.2 1.357 1.337 1.378 1.327 1.388

11.1 1.355 1.334 1.375 1.324 1.385

12.0 1.352 1.331 1.373 1.321 1.383

13.0 1.349 1.328 1.370 1.318 1.380

13.9 1.346 1.326 1.367 1.316 1.377

14.8 1.344 1.323 1.364 1.313 1.374

15.7 1.341 1.320 1.362 1.310 1.372

16.7 1.338 1.317 1.359 1.307 1.369

17.6 1.335 1.314 1.356 1.304 1.366

18.5 1.332 1.312 1.353 1.302 1.363

19.4 1.330 1.309 1.350 1.299 1.360

20.4 1.327 1.306 1.348 1.296 1.358

21.3 1.324 1.303 1.345 1.293 1.355

22.2 1.321 1.301 1.342 1.291 1.352

23.1 1.319 1.298 1.339 1.288 1.349

24.1 1.316 1.295 1.337 1.285 1.347

25.0 1.313 1.292 1.334 1.282 1.344

Intel^®Pentium^®M Processor Datasheet

31

Electrical Specifications

Table 9. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Deep

Sleep State)

Highest Frequency Mode: VID =1.388 V,

Offset = 1.2%

Lowest Frequency Mode: VID = 0.956 V,

Offset = 1.2%

Mode

STATIC

Min Max

Ripple

Min Max

STATIC

Min Max

Ripple

Min Max

I

_CC, A V_CC, V

I_CC, A V_CC, V

0.0

0.6

1.2

1.8

2.3

2.9

3.5

4.1

4.7

5.3

5.9

6.5

7.0

7.6

8.2

8.8

1.371 1.351 1.392 1.341 1.402

1.370 1.349 1.390 1.339 1.400

1.368 1.347 1.389 1.337 1.399

1.366 1.345 1.387 1.335 1.397

1.364 1.343 1.385 1.333 1.395

1.363 1.342 1.383 1.332 1.393

1.361 1.340 1.382 1.330 1.392

1.359 1.338 1.380 1.328 1.390

1.357 1.336 1.378 1.326 1.388

1.356 1.335 1.376 1.325 1.386

1.354 1.333 1.375 1.323 1.385

1.352 1.331 1.373 1.321 1.383

1.350 1.329 1.371 1.319 1.381

1.348 1.328 1.369 1.318 1.379

1.347 1.326 1.368 1.316 1.378

1.345 1.324 1.366 1.314 1.376

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

0.945 0.930 0.959 0.920 0.969

0.944 0.930 0.958 0.920 0.968

0.943 0.929 0.958 0.919 0.968

0.943 0.928 0.957 0.918 0.967

0.942 0.928 0.956 0.918 0.966

0.941 0.927 0.956 0.917 0.966

0.941 0.926 0.955 0.916 0.965

0.940 0.926 0.955 0.916 0.965

0.940 0.925 0.954 0.915 0.964

0.939 0.925 0.953 0.915 0.963

0.938 0.924 0.953 0.914 0.963

0.938 0.923 0.952 0.913 0.962

0.937 0.923 0.951 0.913 0.961

0.936 0.922 0.951 0.912 0.961

0.936 0.922 0.950 0.912 0.960

0.936 0.921 0.950 0.911 0.960

32

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 10. Voltage Tolerances for Low Voltage Intel Pentium M Processors (Active State)

Highest Frequency Mode: VID = 1.180 V,

Offset = 0%

Lowest Frequency Mode: VID = 0.956 V,

Offset = 0%

Mode

STATIC

Min Max

Ripple

Min Max

STATIC

Min Max

Ripple

Min Max

V

_CC, A V_CC, V

I_CC, A V_CC, V

0

1.180 1.162 1.198 1.152 1.208

1.179 1.161 1.196 1.151 1.206

1.177 1.160 1.195 1.150 1.205

1.176 1.158 1.194 1.148 1.204

1.175 1.157 1.192 1.147 1.202

1.173 1.156 1.191 1.146 1.201

1.172 1.154 1.190 1.144 1.200

1.171 1.153 1.188 1.143 1.198

1.169 1.152 1.187 1.142 1.197

1.168 1.150 1.186 1.140 1.196

1.167 1.149 1.184 1.139 1.194

1.165 1.148 1.183 1.138 1.193

1.164 1.146 1.182 1.136 1.192

1.163 1.145 1.180 1.135 1.190

1.161 1.144 1.179 1.134 1.189

1.160 1.142 1.178 1.132 1.188

1.159 1.141 1.176 1.131 1.186

1.157 1.140 1.175 1.130 1.185

1.156 1.138 1.174 1.128 1.184

1.155 1.137 1.172 1.127 1.182

1.153 1.136 1.171 1.126 1.181

1.152 1.134 1.170 1.124 1.180

1.151 1.133 1.168 1.123 1.178

0.0 0.956 0.942 0.970 0.932 0.980

0.4 0.955 0.941 0.969 0.931 0.979

0.7 0.954 0.940 0.968 0.930 0.978

1.1 0.953 0.938 0.967 0.928 0.977

1.4 0.952 0.937 0.966 0.927 0.976

1.8 0.951 0.936 0.965 0.926 0.975

2.1 0.950 0.935 0.964 0.925 0.974

2.5 0.948 0.934 0.963 0.924 0.973

2.9 0.947 0.933 0.962 0.923 0.972

3.2 0.946 0.932 0.961 0.922 0.971

3.6 0.945 0.931 0.960 0.921 0.970

3.9 0.944 0.930 0.959 0.920 0.969

4.3 0.943 0.929 0.957 0.919 0.967

4.7 0.942 0.928 0.956 0.918 0.966

5.0 0.941 0.927 0.955 0.917 0.965

5.4 0.940 0.926 0.954 0.916 0.964

5.7 0.939 0.924 0.953 0.914 0.963

6.1 0.938 0.923 0.952 0.913 0.962

6.4 0.937 0.922 0.951 0.912 0.961

6.8 0.936 0.921 0.950 0.911 0.960

0.4

0.9

1.3

1.8

2.2

2.7

3.1

3.6

4.0

4.4

4.9

5.3

5.8

6.2

6.7

7.1

7.6

8.0

8.4

8.9

9.3

9.8

10.2 1.149 1.132 1.167 1.122 1.177

10.7 1.148 1.130 1.166 1.120 1.176

11.1 1.147 1.129 1.164 1.119 1.174

11.6 1.145 1.128 1.163 1.118 1.173

12.0 1.144 1.126 1.162 1.116 1.172

Intel^®Pentium^®M Processor Datasheet

33

Electrical Specifications

Table 11. Voltage Tolerances for Low Voltage Intel Pentium M Processors (Deep Sleep State)

Highest Frequency Mode: VID = 1.180 V,

Offset = 1.2%

Lowest Frequency Mode: VID = 0.956 V,

Offset = 1.2%

Mode

STATIC

Min Max

Ripple

Min Max

STATIC

Min Max

Ripple

Min Max

I

_CC, A V_CC, V

I_CC, A V_CC, V

0.0

0.3

0.6

0.8

1.1

1.4

1.7

2.0

2.2

2.5

2.8

3.1

3.4

3.6

3.9

4.2

1.166 1.148 1.184 1.138 1.194

1.165 1.147 1.183 1.137 1.193

1.164 1.146 1.182 1.136 1.192

1.163 1.146 1.181 1.136 1.191

1.162 1.145 1.180 1.135 1.190

1.162 1.144 1.179 1.134 1.189

1.161 1.143 1.179 1.133 1.189

1.160 1.142 1.178 1.132 1.188

1.159 1.141 1.177 1.131 1.187

1.158 1.141 1.176 1.131 1.186

1.157 1.140 1.175 1.130 1.185

1.157 1.139 1.174 1.129 1.184

1.156 1.138 1.173 1.128 1.183

1.155 1.137 1.173 1.127 1.183

1.154 1.136 1.172 1.126 1.182

1.153 1.136 1.171 1.126 1.181

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

0.945 0.930 0.959 0.920 0.969

0.944 0.930 0.958 0.920 0.968

0.943 0.929 0.958 0.919 0.968

0.943 0.928 0.957 0.918 0.967

0.942 0.928 0.956 0.918 0.966

0.941 0.927 0.956 0.917 0.966

0.941 0.926 0.955 0.916 0.965

0.940 0.926 0.955 0.916 0.965

0.940 0.925 0.954 0.915 0.964

0.939 0.925 0.953 0.915 0.963

0.938 0.924 0.953 0.914 0.963

0.938 0.923 0.952 0.913 0.962

0.937 0.923 0.951 0.913 0.961

0.936 0.922 0.951 0.912 0.961

0.936 0.922 0.950 0.912 0.960

0.936 0.921 0.950 0.911 0.960

34

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 12. Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Active State)

Highest Frequency Mode: VID = 1.004 V,

Offset = 0%

Lowest Frequency Mode: VID = 0.844 V,

Offset = 0%

Mode

STATIC

Min Max

Ripple

Min Max

STATIC

Min Max

Ripple

Min Max

V

_CC, A V_CC, V

I_CC, A V_CC, V

0

1.004 0.989 1.019 0.979 1.029

1.003 0.988 1.018 0.978 1.028

1.002 0.987 1.017 0.977 1.027

1.001 0.986 1.016 0.976 1.026

1.000 0.985 1.015 0.975 1.025

0.999 0.984 1.014 0.974 1.024

0.998 0.983 1.013 0.973 1.023

0.997 0.982 1.012 0.972 1.022

0.996 0.981 1.011 0.971 1.021

0.995 0.980 1.010 0.970 1.020

0.994 0.979 1.009 0.969 1.019

0.993 0.978 1.008 0.968 1.018

0.992 0.977 1.007 0.967 1.017

0.991 0.976 1.006 0.966 1.016

0.990 0.975 1.005 0.965 1.015

0.989 0.974 1.004 0.964 1.014

0.988 0.973 1.003 0.963 1.013

0.987 0.972 1.002 0.962 1.012

0.986 0.971 1.001 0.961 1.011

0.985 0.970 1.000 0.960 1.010

0.984 0.969 0.999 0.959 1.009

0.983 0.968 0.998 0.958 1.008

0.982 0.967 0.997 0.957 1.007

0.981 0.966 0.996 0.956 1.006

0.980 0.965 0.995 0.955 1.005

0.979 0.964 0.994 0.954 1.004

0.978 0.963 0.993 0.953 1.003

0.977 0.962 0.992 0.952 1.002

0.0 0.844 0.831 0.857 0.821 0.867

0.3 0.843 0.831 0.856 0.821 0.866

0.5 0.842 0.830 0.855 0.820 0.865

0.8 0.842 0.829 0.854 0.819 0.864

1.1 0.841 0.828 0.854 0.818 0.864

1.3 0.840 0.827 0.853 0.817 0.863

1.6 0.839 0.827 0.852 0.817 0.862

1.8 0.838 0.826 0.851 0.816 0.861

2.1 0.838 0.825 0.850 0.815 0.860

2.4 0.837 0.824 0.850 0.814 0.860

2.6 0.836 0.823 0.849 0.813 0.859

2.9 0.835 0.823 0.848 0.813 0.858

3.2 0.835 0.822 0.847 0.812 0.857

3.4 0.834 0.821 0.846 0.811 0.856

3.7 0.833 0.820 0.846 0.810 0.856

3.9 0.832 0.820 0.845 0.810 0.855

4.2 0.831 0.819 0.844 0.809 0.854

4.5 0.831 0.818 0.843 0.808 0.853

4.7 0.830 0.817 0.842 0.807 0.852

5.0 0.829 0.816 0.842 0.806 0.852

0.3

0.7

1.0

1.3

1.7

2.0

2.3

2.7

3.0

3.3

3.7

4.0

4.3

4.7

5.0

5.3

5.7

6.0

6.3

6.7

7.0

7.3

7.7

8.0

8.3

8.7

9.0

Intel^®Pentium^®M Processor Datasheet

35

Electrical Specifications

Table 13. Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Deep Sleep

State)

Highest Frequency Mode: VID = 1.004 V,

Offset = 1.2%

Lowest Frequency Mode: VID = 0.844 V,

Offset = 1.2%

Mode

STATIC

Min Max

Ripple

Min Max

STATIC

Min Max

Ripple

Min Max

I

_CC, A V_CC, V

I_CC, A V_CC, V

0.0

0.2

0.3

0.5

0.6

0.8

0.9

1.1

1.2

1.4

1.5

1.7

1.8

2.0

2.1

2.3

0.992 0.977 1.007 0.967 1.017

0.992 0.976 1.007 0.966 1.017

0.991 0.976 1.006 0.966 1.016

0.990 0.975 1.005 0.965 1.015

0.989 0.974 1.004 0.964 1.014

0.988 0.973 1.003 0.963 1.013

0.987 0.972 1.002 0.962 1.012

0.986 0.971 1.002 0.961 1.012

0.986 0.971 1.001 0.961 1.011

0.986 0.970 1.001 0.960 1.011

0.985 0.970 1.000 0.960 1.010

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

0.834 0.821 0.847 0.811 0.857

0.834 0.821 0.846 0.811 0.856

0.833 0.821 0.846 0.811 0.856

0.833 0.820 0.846 0.810 0.856

0.833 0.820 0.845 0.810 0.855

0.832 0.820 0.845 0.810 0.855

0.832 0.819 0.845 0.809 0.855

0.832 0.819 0.844 0.809 0.854

0.831 0.819 0.844 0.809 0.854

0.831 0.818 0.844 0.808 0.854

0.831 0.818 0.843 0.808 0.853

0.830 0.818 0.843 0.808 0.853

0.830 0.817 0.843 0.807 0.853

0.830 0.817 0.842 0.807 0.852

0.829 0.817 0.842 0.807 0.852

0.829 0.816 0.842 0.806 0.852

36

Intel^®Pentium^®M Processor Datasheet

Electrical Specifications

Table 14. System Bus Differential BCLK Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes¹

V_L

V_H

Input Low Voltage

Input High Voltage

Crossing Voltage

0

V

0.660

0.25

0.710

0.35

0.850

0.55

V_CROSS

2

6

Range of Crossing Points

N/A

0.140

V

∆V_CROSS

V_TH

Threshold Region

Input Leakage Current

Pad Capacitance

V_CROSS-0.100

V_CROSS+0.100

± 100

V

3

4

5

I^LI

µA

pF

Cpad

1.8

2.3

2.75

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of

BCLK1.

3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver

switches. It includes input threshold hysteresis.

4. For Vin between 0 V and V_H.

5. Cpad includes die capacitance only. No package parasitics are included.

6. ∆V_CROSSis defined as the total variation of all crossing voltages as defined in note 2.

Table 15. AGTL+ Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes¹

VCCP

I/O Voltage

0.997

1.05

1.102

V

2/3 VCCP -

2%

2/3 VCCP +

2%

GTLREF

Reference Voltage

2/3 VCCP

V

5

V^IH

V^IL

Input High Voltage

Input Low Voltage

GTLREF+0.1

-0.1

VCCP+0.1

V

3,5

2

GTLREF-0.1

V^OH

R_TT

R^ON

I^LI

Output High Voltage

Termination Resistance

Buffer On Resistance

Input Leakage Current

Pad Capacitance

VCCP

55

5

47

63

Ω

6

17.7

24.7

32.9

± 100

2.75

W

µA

pF

4

7

Cpad

1.8

2.3

8

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. V^ILis defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.

3. V^IHis defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

4. This is the pull down driver resistance. Measured at 0.31*VCCP. R_ON(min) = 0.38*R_TT,R_ON(typ) = 0.45*R

TT,

R_ON(max) = 0.52*R_TT.

5. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these

specifications is the instantaneous VCCP.

6. R_TTis the on-die termination resistance measured at V_OLof the AGTL+ output driver. Measured at

0.31*VCCP. R_TTis connected to VCCP on die.

7. Specified with on die R_TTand R_ONare turned off.

8. Cpad includes die capacitance only. No package parasitics are included.

Intel^®Pentium^®M Processor Datasheet

37

Electrical Specifications

.

Table 16. CMOS Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes¹

VCCP

I/O Voltage

0.997

1.05

1.102

V

Input Low Voltage

CMOS

V^IL

-0.1

0.3*VCCP

V

2

VIH

V^OL

V^OH

I^OL

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Current

Output High Current

Leakage Current

0.7*VCCP

-0.1

VCCP+0.1

0.1*VCCP

VCCP+0.1

4.08

V

2

3

4

5

6

0

0.9*VCCP

1.49

VCCP

V

mA

µA

pF

I^OH

1.49

4.08

I_LI

± 100

Cpad

Pad Capacitance

1.0

2.3

3.0

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The VCCP referred to in these specifications refers to instantaneous VCCP.

3. Measured at 0.1*VCCP.

4. Measured at 0.9*VCCP.

5. For Vin between 0V and VCCP. Measured when the driver is tristated.

6. Cpad includes die capacitance only. No package parasitics are included.

Table 17. Open Drain Signal Group DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit Notes¹

VOH

V^OL

I^OL

Output High Voltage

Output Low Voltage

Output Low Current

Leakage Current

VCCP

V

3

0

0.20

50

16

mA

µA

pF

2

4

5

I_LO

± 200

3.0

Cpad

Pad Capacitance

1.7

2.3

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Measured at 0.2 V

3. V_OHis determined by value of the external pullup resistor to VCCP. Please refer to the design guide for

details.

4. For Vin between 0 V and V_OH

.

5. Cpad includes die capacitance only. No package parasitics are included.

38

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

4 Package Mechanical

Specifications and Pin Information

The Intel Pentium M processor is available in 478-pin, Micro-FCPGA and 479-ball, Micro-

FCBGA packages. The Low Voltage and Ultra Low Voltage Intel Pentium M processors are

available only in the Micro-FCBGA package. Different views of the Micro-FCPGA package are

shown in Figure 4 throughFigure 6. Package dimensions are shown inTable 18. Different views of

the Micro-FCBGA package are shown in Figure 8 through Figure 10. Package dimensions are

shown in Table 19. The Intel Pentium M Processor Die Offset is illustrated in Figure 7.

The Micro-FCBGA may have capacitors placed in the area surrounding the die. Because the die-

side capacitors are electrically conductive, and only slightly shorter than the die height, care should

be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may

short the capacitors, and possibly damage the device or render it inactive. The use of an insulating

material between the capacitors and any thermal solution is recommended to prevent capacitor

shorting.

Figure 4. Micro-FCPGA Package Top and Bottom Isometric Views

PACKAGE KEEPOUT

CAPACITOR AREA

DIE

LABEL

TOP VIEW

BOTTOM VIEW

NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details.

Intel^®Pentium^®M Processor Datasheet

39

Package Mechanical Specifications and Pin Information

Figure 5. Micro-FCPGA Package - Top and Side Views

0.286

A

SUBST RATE KEEPOUT ZONE

DO NOT CONT ACT PA CKAGE

INSIDE THIS LINE

7 (K 1)

8 places

5 (K)

4 plac es

1.25 MA X

(A3)

D1

35 (D)

Ø 0.3 2 (B)

478 places

E1

A2

2.03 ± 0.08

35 (E)

(A 1)

P IN A1 CORN ER

NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details.

40

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Figure 6. Micro-FCPGA Package - Bottom View

14 (K3)

AF

AD

A B

Y

A E

A C

A A

W

U

V

T

R

P

1 4 (K3)

N

M

K

L

J

H

G

F

E

D

C

B

A

1

3

5

7

9

1 1 13

12

1 5

17

19

21 2 3

22

25

25X 1.27

(e)

2

4

6

8

10

14

1 6

18

20

24

26

25X 1.2 7

(e )

NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details.

Figure 7. Intel Pentium M Processor Die Offset

(G )

D 1

(F)

E 1

Intel^®Pentium^®M Processor Datasheet

41

Package Mechanical Specifications and Pin Information

Table 18. Micro-FCPGA Package Dimensions

Symbol Parameter

Min

Max

Unit

A

Overall height, top of die to package seating plane

1.88

2.02

mm

Overall height, top of die to PCB surface, including

socket (Refer to Note 1)

-

4.74

1.95

5.16

2.11

mm

each

kPa

g

A1

A2

A3

B

Pin length

Die height

0.82

Pin-side capacitor height

Pin diameter

-

1.25

0.36

35.1

0.28

34.9

D

Package substrate length

Package substrate width

Die length

E

D1

E1

F

10.56

7.84

17.5

1.133

1.27

5

Die width

To Package Substrate Center

Die Offset from Package Center

Pin pitch

G

e

K

Package edge keep-out

Package corner keep-out

Pin-side capacitor boundary

Pin tip radial true position

Pin count

K1

K3

-

7

14

<=0.254

478

N

Pdie

W

Allowable pressure on the die for thermal solution

Package weight

-

689

4.5

Package Surface Flatness

0.286

mm

NOTE: Overall height with socket is based on design dimensions of the Micro-FCPGA package with no thermal

solution attached. Values are based on design specifications and tolerances. This dimension is subject

to change based on socket design, OEM motherboard design or OEM SMT process.

42

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Figure 8. Micro-FCBGA Package Top and Bottom Isometric Views

PACKAGE KEEPOUT

CAPACITOR AREA

DIE

LABEL

TOP VIEW

BOTTOM VIEW

Intel^®Pentium^®M Processor Datasheet

43

Package Mechanical Specifications and Pin Information

Figure 9. Micro-FCBGA Package Top and Side Views

SUBSTRATE KEEPOUT ZONE

DO NOT CONTACT PACKAGE

INSIDE THIS LINE

7 (K1)

8 places

0.20

A

5 (K)

4 places

A2

D1

35 (D)

Ø 0.78 (b)

479 places

E1

K2

35 (E)

PIN A1 CORNER

NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 19 for details.

44

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 19. Micro-FCBGA Package Dimensions

Symbol Parameter

Min

Max

Unit

A

Overall height, as delivered (Refer to Note 1)

2.60

2.85

mm

each

mm

kPa

g

A2

b

Die height

0.82

0.78

Ball diameter

D

Package substrate length

Package substrate width

Die length

34.9

35.1

E

D1

E1

F

10.56

7.84

17.5

1.133

1.27

5

Die width

To Package Substrate Center

Die Offset from Package Center

Ball pitch

G

e

K

Package edge keep-out

Package corner keep-out

Die-side capacitor height

Package edge to first ball center

Ball count

K1

K2

S

7

-

0.7

1.625

479

N

-

Solder ball coplanarity

Allowable pressure on the die for thermal solution

Package weight

0.2

Pdie

W

689

4.5

NOTE: Overall height as delivered. Values are based on design specifications and tolerances. This dimension

is subject to change based on OEM motherboard design or OEM SMT process.

Intel^®Pentium^®M Processor Datasheet

45

Package Mechanical Specifications and Pin Information

Figure 10. Micro-FCBGA Package Bottom View

1.625 (S)

4 places

AF

AE

AD

AC

AB

AA

Y

1.625 (S)

4 places

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

13 15 17

11

10 12 14 16 18

5

7

9

19 21 23 25

25X 1.27

(e)

2

4

6

8

22 24 26

20

25X 1.27

(e)

NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 19 for details.

46

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

4.1

Processor Pin-Out and Pin List

Figure 11 on the next page shows the top view pinout of the Intel Pentium M processor. The pin list

arranged in two different formats is shown in Table 19 and Table 20.

Intel^®Pentium^®M Processor Datasheet

47

Package Mechanical Specifications and Pin Information

Figure 11.

The Coordinates of the Processor Pins as Viewed From the Top of the Package

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

18

19 20 21 22 23 24

25

26

A

B

A

B

ITP_CLK

[1]

THER

MDC

ITP_CLK

[0]

IGNNE# IERR# VSS

SLP# DBR#

VSS BPM[2]# PRDY# VSS

BPM

TDO

TCK

VSS

D[0]#

VSS

D[6]# D[2]#

VSS

D[4]# D[1]#

VSS

PROC THER

HOT# MDA

VCCA[1] RSVD

VSS

SMI#

VSS

INIT#

TEST1

VSS

VSS DPSLP#

VSS PREQ# RESET# VSS TRST# BCLK1 BCLK0 VSS

D[7]# D[3]#

VSS D[13]# D[9]#

DS TBP DSTBN

VSS

D[5]#

[1]#

C

D

C

STP

VSS

BPM

[0]#

BPM

[3]#

THERM

A20M# RSVD

VSS

TMS

TDI

VSS RSVD VSS TEST3

VSS DPWR# D[8]#

VSS

VSS D[15]# D[12]#

CLK#

TRIP#

[0]#

D

DINV

[0]#

LINT0

VSS FERR# LINT1

PWR

VCC

VSS

VCC

VSS

VCCP VSS VCCP VSS VCCP VSS VCCP VSS

VCC

VSS

VCC

VSS

VCC

VSS D[10]#

VSS

E

PSI# VID[0]

VCC

VSS

VCC

VSS

VCC

VSS

VCCP VSS VCCP VSS VCCP VSS

VCC

VSS

VCC

VSS

D[14]# D[11]# VSS

RSVD

VSS

VCC

GOOD

F

VSS

VID[1] VID[2]

VSS

VCCP VSS VCCP VSS VCCP VSS VCCP VSS

VSS VCC

VSS D[21]# VCCA[0]

TEST2

G

RSVD

VSS VID[3] VID[4] VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VSS D[22]# D[17]#

VSS

H

RS[0]# DRDY# VSS VID[5]

VSS LOCK# BPRI# VSS

VSS

VCC

VCC D[16]# D[20]# VSS D[29]#

DINV

J

VSS D[23]#

VSS D[25]#

[1]#

K

This page intentionally left blank.

DS TBN

[1]#

RS[1]# VSS

HIT# HITM# VSS VCCP

VCC

VSS

D[31]# VSS

L

DSTBP

[1]#

DEFER# VCCP

VSS

BNR# RS[2]# VSS

VCCP VSS D[18]#

VSS D[26]#

M

N

M

N

DBSY# TRDY# VSS

VSS VCCP

VSS VCCP D[24]# VSS D[28]# D[19]#

VSS

VCCA[2] ADS #

VSS

BR0# VCCP VSS

VCCP VSS

VSS D[27]# D[30]# VSS

COMP COMP

VSS VCCP VCCQ[0] VSS

TOP VIEW

P

REQ

VSS

[3]#

REQ

[1]#

A[3]#

VSS

VSS VCCP

[0]

[1]

R

REQ

VSS

VCCP

A[6]#

VSS

VCCP

VSS

D[39]# D[37]# VSS D[38]#

[0]#

T

REQ

[4]#

REQ

[2]#

DINV

[2]#

A[9]#

A[4]#

VSS

VSS VCCP

VSS VCCP VSS

D[34]# VSS

U

ADSTB

[0]#

A[13]# VSS

VCC

VSS

VCCP VSS D[35]# VSS D[43]# D[41]#

V

VSS

A[7]# A[5]#

VCC

VSS

VCC D[36]# D[42]# VSS D[44]#

DS TBP DSTBN

W

Y

W

Y

VCC

A[8]# A[10]# VSS VCCQ[1] VCC

VSS

VCC

VSS

VCC

VSS

[2]#

A[12]# VSS A[15]#

VSS

VCC

VSS

VCC D[45]# VSS D[47]# D[32]#

A[11]#

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

VSS

VSS A[16]# A[14]# VSS

COMP COMP

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

D[40]# D[33]# VSS D[46]#

VSS D[50]# D[48]# VSS

VSS

VCC VSS

VCC

A[24]#

[3]

[2]

VSS A[20]# A[18]# VSS

A[25]# A[19]# VSS

VCC D[51]#

VSS D[52]# D[49]#

VSS D[53]# VCCA[3]

RSVD

DINV

VSS

VSS A[23]# A[21]# VSS

A[28]# VSS

VCC

VSS

VCC

D[60]# VSS D[54]# D[57]# VSS GTLREF

DS TBN DSTBP

A[26]#

[3]#

ADSTB

[1]#

VCC

VSS

A[30]# A[27]# VSS A[22]#

VCC

VSS D[59]# D[55]# VSS

VSS

VCC

[3]#

SENSE

VSS

SENSE

A[31]# VSS A[29]# A[17]# VSS

A[31]#

RSVD

VSS D[58]# VSS D[62]# D[56]# VSS D[61]# D[63]#

VCC vss

1

2

3

4

5

6

7

8

9

10 11 12 13

14 15

16

17 18 19 20 21 22

23

24 25 26

Pin B2 is depopulated on the Micro-FCPGA package

VSS

VCC

Other

48

IIntel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 20. Pin Listing by Pin Name

Number

Signal Buffer

Type

Pin Name

Direction

Table 20. Pin Listing by Pin Name

BPM[0]#

C8

Common Clock Output

Common Clock Input/Output

Common Clock Input

BPM[1]#

BPM[2]#

BPM[3]#

BPRI#

BR0#

B8

Number

Signal Buffer

Type

Pin Name

Direction

A9

A[3]#

P4

Source Synch

CMOS

Input/Output

Input

C9

A[4]#

U4

J3

A[5]#

V3

N4

Common Clock Input/Output

A[6]#

R3

COMP[0]

COMP[1]

COMP[2]

COMP[3]

D[0]#

P25

P26

AB2

AB1

A19

A25

A22

B21

A24

B26

A21

B20

C20

B24

D24

E24

C26

B23

E23

C25

H23

G25

L23

M26

H24

F25

G24

J23

M23

J25

L26

N24

M25

Power/Other

Source Synch

Input/Output

A[7]#

V2

A[8]#

W1

T4

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A20M#

ADS#

W2

Y4

D[1]#

Y1

D[2]#

U1

D[3]#

AA3

Y3

D[4]#

D[5]#

AA2

AF4

AC4

AC7

AC3

AD3

AE4

AD2

AB4

AC6

AD5

AE2

AD6

AF3

AE1

AF1

C2

D[6]#

D[7]#

D[8]#

D[9]#

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

D[16]#

D[17]#

D[18]#

D[19]#

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

N2

Common Clock Input/Output

ADSTB[0]#

ADSTB[1]#

BCLK[0]

BCLK[1]

BNR#

U3

Source Synch

Bus Clock

Input/Output

Input

AE5

B15

B14

L1

Bus Clock

Input

Common Clock Input/Output

Intel^®Pentium^®M Processor Datasheet

49

Package Mechanical Specifications and Pin Information

Table 20. Pin Listing by Pin Name

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

D[29]#

H26

Source Synch

CMOS

Input/Output

Output

DINV[1]#

J26

T24

AD20

B7

Source Synch

CMOS

Input/Output

Input

D[30]#

D[31]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#

DBR#

N25

DINV[2]#

DINV[3]#

DPSLP#

DPWR#

DRDY#

K25

Y26

AA24

T25

C19

H2

Common Clock Input

Common Clock Input/Output

U23

DSTBN[0]#

DSTBN[1]#

DSTBN[2]#

DSTBN[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

FERR#

C23

K24

W25

AE24

C22

L24

W24

AE25

D3

Source Synch

Open Drain

Input/Output

Output

V23

R24

R26

R23

AA23

U26

V24

U25

V26

GTLREF

HIT#

AD26

K3

Power/Other

Input

Y23

Common Clock Input/Output

AA26

Y25

HITM#

K4

IERR#

A4

Open Drain

CMOS

Output

Input

input

Input

AB25

AC23

AB24

AC20

AC22

AC25

AD23

AE22

AF23

AD24

AF20

AE21

AD21

AF25

AF22

AF26

A7

IGNNE#

INIT#

A3

B5

CMOS

ITP_CLK[0]

ITP_CLK[1]

LINT0

A16

A15

D1

CMOS

LINT1

D4

CMOS

LOCK#

J2

Common Clock Input/Output

Common Clock Output

Common Clock Input

PRDY#

A10

B10

B17

E1

PREQ#

PROCHOT#

PSI#

Open Drain

CMOS

Output

PWRGOOD

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

RESET#

RS[0]#

E4

CMOS

Input

R2

Source Synch

Input/Output

P3

T2

P1

T1

DBSY#

DEFER#

DINV[0]#

M2

Common Clock Input/Output

Common Clock Input

B11

H1

Common Clock Input

L4

D25

Source Synch

Input/Output

RS[1]#

K1

50

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 20. Pin Listing by Pin Name

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

RS[2]#

L2

Common Clock Input

Reserved

VCC

G5

Power/Other

RSVD

SLP#

AF7

B2

VCC

G21

H6

Reserved

C14

C3

Reserved

H22

Reserved

J5

E26

G1

Reserved

J21

Reserved

K22

AC1

A6

Reserved

U5

CMOS

Input

Output

V6

SMI#

B4

CMOS

V22

STPCLK#

TCK

C6

CMOS

W5

A13

C12

A12

C5

CMOS

W21

Y6

TDI

CMOS

TDO

Open Drain

Test

Y22

TEST1

TEST2

TEST3

THERMDA

THERMDC

AA5

AA7

AA9

AA11

AA13

AA15

AA17

AA19

AA21

AB6

AB8

AB10

AB12

AB14

AB16

AB18

AB20

AB22

AC9

AC11

AC13

AC15

AC17

AC19

AD8

F23

C16

B18

A18

Test

Power/Other

Open Drain

CMOS

THERMTRIP# C17

Output

Input

TMS

TRDY#

TRST#

VCC

C11

M3

Common Clock Input

B13

D6

CMOS

Input

Power/Other

D8

D18

D20

D22

E5

E7

E9

E17

E19

E21

F6

F8

F18

F20

F22

Intel^®Pentium^®M Processor Datasheet

51

Package Mechanical Specifications and Pin Information

Table 20. Pin Listing by Pin Name

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

VCC

AD10

AD12

AD14

AD16

AD18

AE9

AE11

AE13

AE15

AE17

AE19

AF8

AF10

AF12

AF14

AF16

AF18

F26

Power/Other

VCCP

P6

Power/Other

CMOS

VCC

VCCP

VCCQ[0]

VCCQ[1]

VCCSENSE

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VSS

P22

R5

VCC

R21

T6

VCC

T22

U21

P23

W4

AE7

E2

VCC

Output

VCC

Output

VCC

F2

CMOS

VCC

F3

CMOS

VCC

G3

CMOS

VCC

G4

CMOS

VCC

H4

CMOS

VCC

A2

Power/Other

VCCA[0]

VCCA[1]

VCCA[2]

VCCA[3]

VCCP

VSS

A5

B1

VSS

A8

N1

VSS

A11

A14

A17

A20

A23

A26

B3

AC26

D10

D12

D14

D16

E11

VSS

E13

VSS

B6

E15

VSS

B9

F10

VSS

B12

B16

B19

B22

B25

C1

F12

VSS

F14

VSS

F16

VSS

K6

VSS

L5

VSS

L21

VSS

C4

M6

VSS

C7

M22

N5

VSS

C10

C13

C15

VSS

N21

VSS

52

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 20. Pin Listing by Pin Name

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

VSS

C18

C21

C24

D2

Power/Other

VSS

G6

Power/Other

VSS

G22

G23

G26

H3

D5

D7

H5

D9

H21

H25

J1

D11

D13

D15

D17

D19

D21

D23

D26

E3

J4

J6

J22

J24

K2

K5

K21

K23

K26

L3

E6

E8

E10

E12

E14

E16

E18

E20

E22

E25

F1

L6

L22

L25

M1

M4

M5

M21

M24

N3

F4

F5

N6

F7

N22

N23

N26

P2

F9

F11

F13

F15

F17

F19

F21

F24

G2

P5

P21

P24

R1

R4

R6

Intel^®Pentium^®M Processor Datasheet

53

Package Mechanical Specifications and Pin Information

Table 20. Pin Listing by Pin Name

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

VSS

R22

R25

T3

Power/Other

VSS

AB7

Power/Other

VSS

AB9

AB11

AB13

AB15

AB17

AB19

AB21

AB23

AB26

AC2

T5

T21

T23

T26

U2

U6

U22

U24

V1

AC5

V4

AC8

V5

AC10

AC12

AC14

AC16

AC18

AC21

AC24

AD1

V21

V25

W3

W6

W22

W23

W26

Y2

AD4

Y5

AD7

Y21

Y24

AA1

AA4

AA6

AA8

AA10

AA12

AA14

AA16

AA18

AA20

AA22

AA25

AB3

AB5

AD9

AD11

AD13

AD15

AD17

AD19

AD22

AD25

AE3

AE6

AE8

AE10

AE12

AE14

AE16

AE18

54

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 20. Pin Listing by Pin Name

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

VSS

AE20

AE23

AE26

AF2

Power/Other

A23

VSS

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

VSS

A24

D[4]#

D[1]#

VSS

Input/Output

VSS

A25

VSS

A26

VSS

AF5

AA1

VSS

AF9

AA2

A[16]#

A[14]#

VSS

Input/Output

VSS

AF11

AF13

AF15

AF17

AF19

AF21

AF24

AF6

AA3

VSS

AA4

VSS

AA5

VCC

VSS

AA6

VSS

AA7

VCC

VSS

AA8

VSS

AA9

VCC

VSS

VSSSENSE

Output

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

VCC

VSS

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

VCC

VSS

Pin Name

Direction

A2

VSS

Power/Other

CMOS

VCC

VSS

A3

IGNNE#

IERR#

VSS

Input

A4

Open Drain

Power/Other

CMOS

Output

VCC

VSS

A5

A6

SLP#

Input

VCC

VSS

A7

DBR#

VSS

CMOS

Output

A8

Power/Other

VCC

VSS

A9

BPM[2]#

PRDY#

VSS

Common Clock Output

Power/Other

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

D[40]#

D[33]#

VSS

Input/Output

TDO

Open Drain

CMOS

Output

Input

TCK

D[46]#

COMP[3]

COMP[2]

VSS

Input/Output

VSS

Power/Other

CMOS

ITP_CLK[1]

ITP_CLK[0]

VSS

input

AB2

CMOS

AB3

Power/Other

Source Synch

Power/Other

Source Synch

AB4

A[24]#

VSS

Input/Output

THERMDC

D[0]#

AB5

Input/Output

AB6

VCC

VSS

AB7

D[6]#

Input/Output

AB8

VCC

VSS

D[2]#

AB9

Intel^®Pentium^®M Processor Datasheet

55

Package Mechanical Specifications and Pin Information

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

VCC

Power/Other

Source Synch

Power/Other

Reserved

AC23

AC24

AC25

AC26

AD1

D[49]#

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

VSS

VCC

VSS

D[53]#

VCCA[3]

VSS

Input/Output

VCC

VSS

AD2

A[23]#

A[21]#

VSS

Input/Output

VCC

VSS

AD3

AD4

VCC

VSS

AD5

A[26]#

A[28]#

VSS

Input/Output

AD6

VCC

VSS

AD7

AD8

VCC

VSS

AD9

VSS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

VCC

D[50]#

D[48]#

VSS

Input/Output

VSS

VCC

VSS

RSVD

VSS

VCC

AC2

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

VSS

AC3

A[20]#

A[18]#

VSS

Input/Output

VCC

AC4

VSS

AC5

VCC

AC6

A[25]#

A[19]#

VSS

Input/Output

VSS

AC7

DINV[3]#

D[60]#

VSS

Input/Output

AC8

AC9

VCC

VSS

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

D[54]#

D[57]#

VSS

Input/Output

VCC

VSS

VCC

VSS

GTLREF

A[30]#

A[27]#

VSS

Input/Output

VCC

VSS

AE2

AE3

VCC

VSS

AE4

A[22]#

ADSTB[1]#

VSS

Input/Output

AE5

VCC

D[51]#

VSS

AE6

Input/Output

AE7

VCCSENSE

VSS

Output

AE8

D[52]#

AE9

VCC

56

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

VSS

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Reserved

AF23

AF24

AF25

AF26

B1

D[56]#

Source Synch

Power/Other

Source Synch

Power/Other

Reserved

Input/Output

VCC

VSS

D[61]#

D[63]#

VCCA[1]

RSVD

VSS

Input/Output

VCC

VSS

VCC

B2

VSS

B3

Power/Other

CMOS

VCC

B4

SMI#

Input

VSS

B5

INIT#

CMOS

VCC

B6

VSS

Power/Other

CMOS

VSS

B7

DPSLP#

BPM[1]#

VSS

Input

D[59]#

D[55]#

VSS

Input/Output

B8

Common Clock Output

Power/Other

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

PREQ#

RESET#

VSS

Common Clock Input

Power/Other

DSTBN[3]#

DSTBP[3]#

VSS

Input/Output

TRST#

BCLK[1]

BCLK[0]

VSS

CMOS

Input

A[31]#

VSS

Input/Output

Bus Clock

AF2

Bus Clock

AF3

A[29]#

A[17]#

VSS

Input/Output

Power/Other

Open Drain

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

CMOS

AF4

PROCHOT#

THERMDA

VSS

Output

AF5

AF6

VSSSENSE

RSVD

VCC

Output

AF7

D[7]#

Input/Output

AF8

Power/Other

Source Synch

Power/Other

Source Synch

D[3]#

AF9

VSS

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

VCC

D[13]#

D[9]#

Input/Output

VSS

VCC

VSS

D[5]#

Input/Output

Input

VCC

VSS

C2

A20M#

RSVD

VSS

VCC

C3

Reserved

VSS

C4

Power/Other

Test

VCC

C5

TEST1

STPCLK#

VSS

C6

CMOS

Input

D[58]#

VSS

Input/Output

C7

Power/Other

C8

BPM[0]#

BPM[3]#

Common Clock Output

D[62]#

C9

Common Clock Input/Output

Intel^®Pentium^®M Processor Datasheet

57

Package Mechanical Specifications and Pin Information

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

VSS

Power/Other

CMOS

D23

D24

D25

D26

E1

VSS

Power/Other

Source Synch

Power/Other

CMOS

TMS

Input

D[10]#

DINV[0]#

VSS

Input/Output

TDI

CMOS

Input

VSS

Power/Other

Reserved

Power/Other

Test

RSVD

VSS

PSI#

VID[0]

VSS

Output

E2

CMOS

TEST3

THERMTRIP#

VSS

E3

Power/Other

CMOS

Open Drain

Power/Other

Output

E4

PWRGOOD

VCC

Input

E5

Power/Other

Source Synch

Power/Other

Reserved

DPWR#

D[8]#

VSS

Common Clock Input

E6

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

CMOS

Input/Output

E7

VCC

E8

VSS

DSTBP[0]#

DSTBN[0]#

VSS

Input/Output

E9

VCC

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

VSS

VCCP

VSS

D[15]#

D[12]#

LINT0

VSS

Input/Output

Input

VCCP

VSS

D2

Power/Other

Open Drain

CMOS

VCCP

VSS

D3

FERR#

LINT1

VSS

Output

Input

D4

VCC

D5

Power/Other

VSS

D6

VCC

D7

VSS

D8

VCC

D9

VSS

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

VCCP

VSS

D[14]#

D[11]#

VSS

Input/Output

VCCP

VSS

RSVD

VSS

VCCP

VSS

Power/Other

CMOS

F2

VID[1]

VID[2]

VSS

Output

VCCP

VSS

F3

CMOS

F4

Power/Other

VCC

F5

VSS

F6

VCC

F7

VSS

F8

VCC

F9

VSS

58

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

VCCP

Power/Other

Test

H25

H26

J1

VSS

Power/Other

Source Synch

Power/Other

VSS

D[29]#

VSS

Input/Output

VCCP

VSS

J2

LOCK#

BPRI#

VSS

Common Clock Input/Output

Common Clock Input

Power/Other

VCCP

VSS

J3

J4

VCCP

VSS

J5

VCC

Power/Other

J6

VSS

Power/Other

VCC

J21

J22

J23

J24

J25

J26

K1

VCC

Power/Other

VSS

Power/Other

VCC

D[23]#

VSS

Source Synch

Power/Other

Source Synch

Input/Output

VSS

VCC

D[25]#

DINV[1]#

RS[1]#

VSS

Input/Output

TEST2

VSS

Power/Other

Source Synch

Power/Other

Reserved

Common Clock Input

Power/Other

D[21]#

VCCA[0]

RSVD

VSS

Input/Output

K2

K3

HIT#

Common Clock Input/Output

Power/Other

K4

HITM#

VSS

G2

Power/Other

CMOS

K5

G3

VID[3]

VID[4]

VCC

Output

K6

VCCP

VSS

Power/Other

G4

CMOS

K21

K22

K23

K24

K25

K26

L1

Power/Other

G5

Power/Other

Source Synch

Power/Other

VCC

Power/Other

G6

VSS

Power/Other

G21

G22

G23

G24

G25

G26

H1

VCC

DSTBN[1]#

D[31]#

VSS

Source Synch

Power/Other

Input/Output

VSS

D[22]#

D[17]#

VSS

Input/Output

BNR#

RS[2]#

VSS

Common Clock Input/Output

Common Clock Input

Power/Other

L2

L3

RS[0]#

DRDY#

VSS

Common Clock Input

Common Clock Input/Output

Power/Other

L4

DEFER#

VCCP

VSS

Common Clock Input

Power/Other

H2

L5

H3

L6

Power/Other

H4

VID[5]

VSS

CMOS

Output

L21

L22

L23

L24

L25

L26

M1

VCCP

VSS

Power/Other

H5

Power/Other

Source Synch

Power/Other

H6

VCC

D[18]#

DSTBP[1]#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

H21

H22

H23

H24

VSS

VCC

D[16]#

D[20]#

Input/Output

D[26]#

VSS

Input/Output

Intel^®Pentium^®M Processor Datasheet

59

Package Mechanical Specifications and Pin Information

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

Number

Signal Buffer

Type

Pin Name

Direction

Pin Name

Direction

M2

DBSY#

Common Clock Input/Output

Common Clock Input

Power/Other

R5

VCCP

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

CMOS

M3

TRDY#

VSS

R6

VSS

M4

R21

R22

R23

R24

R25

R26

T1

VCCP

VSS

M5

VSS

Power/Other

M6

VCCP

VSS

Power/Other

D[39]#

D[37]#

VSS

Input/Output

M21

M22

M23

M24

M25

M26

N1

Power/Other

VCCP

D[24]#

VSS

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

D[38]#

REQ[4]#

REQ[2]#

VSS

Input/Output

D[28]#

D[19]#

VCCA[2]

ADS#

VSS

Input/Output

T2

T3

T4

A[9]#

VSS

Input/Output

N2

Common Clock Input/Output

Power/Other

T5

N3

T6

VCCP

VSS

N4

BR0#

VCCP

VSS

Common Clock Input/Output

Power/Other

T21

T22

T23

T24

T25

T26

U1

N5

VCCP

VSS

N6

Power/Other

N21

N22

N23

N24

N25

N26

P1

VCCP

VSS

Power/Other

DINV[2]#

D[34]#

VSS

Input/Output

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

VSS

Power/Other

D[27]#

D[30]#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

A[13]#

VSS

Input/Output

U2

U3

ADSTB[0]#

A[4]#

VCC

Input/Output

REQ[3]#

VSS

Input/Output

U4

P2

U5

P3

REQ[1]#

A[3]#

Input/Output

U6

VSS

P4

U21

U22

U23

U24

U25

U26

V1

VCCP

VSS

P5

VSS

P6

VCCP

VSS

D[35]#

VSS

Input/Output

P21

P22

P23

P24

P25

P26

R1

VCCP

VCCQ[0]

VSS

D[43]#

D[41]#

VSS

Input/Output

COMP[0]

COMP[1]

VSS

Input/Output

V2

A[7]#

A[5]#

VSS

Input/Output

V3

V4

R2

REQ[0]#

A[6]#

Input/Output

V5

VSS

R3

V6

VCC

R4

VSS

V21

VSS

60

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 21. Pin Listing by Pin Number

Number

Signal Buffer

Type

Pin Name

Direction

V22

V23

V24

V25

V26

W1

W2

W3

W4

W5

W6

W21

W22

W23

W24

W25

W26

Y1

VCC

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

D[36]#

D[42]#

VSS

Input/Output

D[44]#

A[8]#

Input/Output

A[10]#

VSS

VCCQ[1]

VCC

VSS

VCC

VSS

DSTBP[2]#

DSTBN[2]#

VSS

Input/Output

A[12]#

VSS

Input/Output

Y2

Y3

A[15]#

A[11]#

VSS

Input/Output

Y4

Y5

Y6

VCC

Y21

Y22

Y23

Y24

Y25

Y26

VSS

VCC

D[45]#

VSS

Input/Output

D[47]#

D[32]#

Input/Output

Intel^®Pentium^®M Processor Datasheet

61

Package Mechanical Specifications and Pin Information

4.2

Alphabetical Signals Reference

Table 22. Signal Description (Sheet 1 of 7)

Name

Type

Description

A[31:3]# (Address) define a 2³²-byte physical memory address space. In sub-

phase 1 of the address phase, these pins transmit the address of a transaction.

In sub-phase 2, these pins transmit transaction type information. These signals

must connect the appropriate pins of both agents on the Intel Pentium M

processor system bus. A[31:3]# are source synchronous signals and are latched

into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps

which are sampled before RESET# is deasserted.

Input/

Output

A[31:3]#

If A20M# (Address-20 Mask) is asserted, the processor masks physical address

bit 20 (A20#) before looking up a line in any internal cache and before driving a

read/write transaction on the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#

is only supported in real mode.

A20M#

ADS#

Input

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the TRDY#

assertion of the corresponding Input/Output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS#

activation to begin parity checking, protocol checking, address decode, internal

snoop, or deferred reply ID match operations associated with the new

transaction.

Input/

Output

Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and

falling edges. Strobes are associated with signals as shown below.

Input/

Output

Signals

Associated Strobe

ADSTB[1:0]#

REQ[4:0]#, A[16:3]#

A[31:17]#

ADSTB[0]#

ADSTB[1]#

The differential pair BCLK (Bus Clock) determines the system bus frequency. All

processor system bus agents must receive these signals to drive their outputs

and latch their inputs.

BCLK[1:0]

BNR#

Input

BNR# (Block Next Request) is used to assert a bus stall by any bus agent that is

unable to accept new bus transactions. During a bus stall, the current bus owner

cannot issue any new transactions.

Input/

Output

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor

signals. They are outputs from the processor that indicate the status of

breakpoints and programmable counters used for monitoring processor

performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium

M processor system bus agents.This includes debug or performance monitoring

tools.

BPM[2:0]#

BPM[3]

Output

Input/

Output

Please refer to the platform design guides and ITP700 Debug Port Design Guide

for more detailed information.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

system bus. It must connect the appropriate pins of both processor system bus

agents. Observing BPRI# active (as asserted by the priority agent) causes the

other agent to stop issuing new requests, unless such requests are part of an

ongoing locked operation. The priority agent keeps BPRI# asserted until all of its

requests are completed, then releases the bus by deasserting BPRI#.

BPRI#

BR0#

Input

BR0# is used by the processor to request the bus. The arbitration is done

between the Intel Pentium M processor (Symmetric Agent) and the MCH-M

(High Priority Agent) of the Intel 855PM or Intel 855GM chipset.

Input/

Output

62

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 22. Signal Description (Sheet 2 of 7)

Name

Type

Description

COMP[3:0] must be terminated on the system board using precision (1%

tolerance) resistors. Refer to the platform design guides for more implementation

details.

COMP[3:0]

Analog

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor system bus agents, and must connect the appropriate

pins on both agents. The data driver asserts DRDY# to indicate a valid data

transfer.

D[63:0]# are quad-pumped signals and will thus be driven four times in a

common clock period. D[63:0]# are latched off the falling edge of both

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a

pair of one DSTBP# and one DSTBN#. The following table shows the grouping

of data signals to data strobes and DINV#.

Quad-Pumped Signal Groups

DSTBN#/

Input/

Output

D[63:0]#

Data Group

DINV#

DSTBP#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DINV# pins determine the polarity of the data signals. Each

group of 16 data signals corresponds to one DINV# signal. When the DINV#

signal is active, the corresponding data group is inverted and therefore sampled

active high.

DBR# (Data Bus Reset) is used only in processor systems where no debug port

is implemented on the system board. DBR# is used by a debug port interposer

so that an in-target probe can drive system reset. If a debug port is implemented

in the system, DBR# is a no connect. DBR# is not a processor signal.

DBR#

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on

the processor system bus to indicate that the data bus is in use. The data bus is

released after DBSY# is deasserted. This signal must connect the appropriate

pins on both processor system bus agents.

Input/

Output

DBSY#

DEFER#

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the

responsibility of the addressed memory or Input/Output agent. This signal must

connect the appropriate pins of both processor system bus agents.

Input

DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the

polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the

data on the data bus is inverted. The bus agent will invert the data bus signals if

more than half the bits, within the covered group, would change level in the next

cycle.

DINV[3:0]# Assignment To Data Bus

Input/

Output

DINV[3:0]#

Bus Signal

Data Bus Signals

DINV[3]#

DINV[2]#

DINV[1]#

DINV[0]#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

Intel^®Pentium^®M Processor Datasheet

63

Package Mechanical Specifications and Pin Information

Table 22. Signal Description (Sheet 3 of 7)

Name

Type

Description

DPSLP# when asserted on the platform causes the processor to transition from

the Sleep state to the Deep Sleep state. In order to return to the Sleep state,

DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and

also connects to the MCH-M component of the Intel 855PM or Intel 855GM

chipset.

DPSLP#

Input

DPWR# is a control signal from the Intel 855PM and Intel 855GM chipsets used

to reduce power on the Intel Pentium M data bus input buffers.

DPWR#

DRDY#

Input

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

indicating valid data on the data bus. In a multi-common clock data transfer,

DRDY# may be deasserted to insert idle clocks. This signal must connect the

appropriate pins of both processor system bus agents.

Input/

Output

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DINV[0]#

D[31:16]#, DINV[1]#

D[47:32]#, DINV[2]#

D[63:48]#, DINV[3]#

DSTBN[0]#

DSTBN[1]#

DSTBN[2]#

DSTBN[3]#

Input/

Output

DSTBN[3:0]#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DINV[0]#

D[31:16]#, DINV[1]#

D[47:32]#, DINV[2]#

D[63:48]#, DINV[3]#

DSTBP[0]#

DSTBP[1]#

DSTBP[2]#

DSTBP[3]#

Input/

Output

DSTBP[3:0]#

FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed

signal and its meaning is qualified by STPCLK#. When STPCLK# is not

asserted, FERR#/PBE# indicates a floating point when the processor detects an

unmasked floating-point error. FERR# is similar to the ERROR# signal on the

Intel 80387 coprocessor, and is included for compatibility with systems using

MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an

assertion of FERR#/PBE# indicates that the processor has a pending break

event waiting for service. The assertion of FERR#/PBE# indicates that the

processor should be returned to the Normal state. When FERR#/PBE# is

asserted, indicating a break event, it will remain asserted until STPCLK# is

deasserted. Assertion of PREQ# when STPCLK# is active will also cause an

FERR# break event. For additional information on the pending break event

functionality, including identification of support for the feature and enable/disable

information, refer to Volume 3 of the Intel ^Architecture Software Developer’s

Manual and the Intel ^Processor Identification and CPUID Instruction

application note.

FERR#/PBE#

Output

For termination requirements please refer to the platform design guides.

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF

should be set at 2/3 V_CCP. GTLREF is used by the AGTL+ receivers to determine

if a signal is a logical 0 or logical 1. Please refer to the platform design guides for

details on GTLREF implementation.

GTLREF

Input

64

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 22. Signal Description (Sheet 4 of 7)

Name

Type

Description

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Either system bus agent may assert both HIT# and HITM# together to

indicate that it requires a snoop stall, which can be continued by reasserting

HIT# and HITM# together.

HIT#

HITM#

Input/

Output

IERR# (Internal Error) is asserted by a processor as the result of an internal

error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction

on the processor system bus. This transaction may optionally be converted to an

external error signal (e.g., NMI) by system core logic. The processor will keep

IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

IERR#

Output

For termination requirements please refer to the platform design guides.

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is deasserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE#

Input

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the TRDY#

assertion of the corresponding Input/Output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside the processor

without affecting its internal caches or floating-point registers. The processor

then begins execution at the power on Reset vector configured during power on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure recognition of

this signal following an Input/Output Write instruction, it must be valid along with

the TRDY# assertion of the corresponding Input/Output Write bus transaction.

INIT# must connect the appropriate pins of both processor system bus agents.

INIT#

Input

If INIT# is sampled active on the active to inactive transition of RESET#, then the

processor executes its Built-in Self-Test (BIST)

For termination requirements please refer to the platform design guides.

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems

where no debug port is implemented on the system board. ITP_CLK[1:0] are

used as BCLK[1:0] references for a debug port implemented on an interposer. If

a debug port is implemented in the system, ITP_CLK[1:0] are no connects.

These are not processor signals.

ITP_CLK[1:0]

Input

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC

Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a

maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable

interrupt. INTR and NMI are backward compatible with the signals of those

names on the Pentium processor. Both signals are asynchronous.

LINT[1:0]

Both of these signals must be software configured using BIOS programming of

the APIC register space and used either as NMI/INTR or LINT[1:0]. Because the

APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is

the default configuration.

LOCK# indicates to the system that a transaction must occur atomically. This

signal must connect the appropriate pins of both processor system bus agents.

For a locked sequence of transactions, LOCK# is asserted from the beginning of

the first transaction to the end of the last transaction.

Input/

Output

LOCK#

When the priority agent asserts BPRI# to arbitrate for ownership of the

processor system bus, it will wait until it observes LOCK# deasserted. This

enables symmetric agents to retain ownership of the processor system bus

throughout the bus locked operation and ensure the atomicity of lock.

Intel^®Pentium^®M Processor Datasheet

65

Package Mechanical Specifications and Pin Information

Table 22. Signal Description (Sheet 5 of 7)

Name

Type

Description

Probe Ready signal used by debug tools to determine processor debug

readiness.

PRDY#

Output

Please refer to the ITP700 Debug Port Design Guide and the platform design

guides for more implementation details.

Probe Request signal used by debug tools to request debug operation of the

processor.

PREQ#

Input

Please refer to the ITP700 Debug Port Design Guide and the platform design

guides for more implementation details.

PROCHOT# (Processor Hot) will go active when the processor temperature

monitoring sensor detects that the processor has reached its maximum safe

operating temperature. This indicates that the processor Thermal Control Circuit

has been activated, if enabled. See Chapter 5 for more details.

PROCHOT#

Output

For termination requirements please refer to the platform design guides.

This signal may require voltage translation on the motherboard. Please refer to

the platform design guides for more details.

Processor Power Status Indicator signal. This signal is asserted when the

processor is in a lower state (Deep Sleep and Deeper Sleep). See Section 2.1.3

for more details.

PSI#

PWRGOOD (Power Good) is a processor input. The processor requires this

signal as a clean indication that the clocks and power supplies are stable and

within their specifications. ‘Clean’ implies that the signal will remain low (capable

of sinking leakage current), without glitches, from the time that the power

supplies are turned on until they come within specification. The signal must then

transition monotonically to a high state. PWRGOOD can be driven inactive at

any time, but clocks and power must again be stable before a subsequent rising

edge of PWRGOOD.

PWRGOOD

Input

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout the boundary scan operation.

For termination requirements please refer to the platform design guides.

REQ[4:0]# (Request Command) must connect the appropriate pins of both

processor system bus agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are source

synchronous to ADSTB[0]#.

Input/

Output

REQ[4:0]#

RESET#

Asserting the RESET# signal resets the processor to a known state and

invalidates its internal caches without writing back any of their contents. For a

power-on Reset, RESET# must stay active for at least two milliseconds after

VCC and BCLK have reached their proper specifications. On observing active

RESET#, both system bus agents will deassert their outputs within two clocks.

All processor straps must be valid within the specified setup time before

RESET# is deasserted.

Input

Please refer to the ITP700 Debug Port Design Guide and the platform design

guides for termination requirements and implementation details. There is a 55

ohm (nominal) on die pullup resistor on this signal.

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of both processor system bus agents.

RS[2:0]#

RSVD

These pins are RESERVED and must be left unconnected on the board.

However, it is recommended that routing channels to these pins on the board be

kept open for possible future use. Please refer to the platform design guides for

more details.

Reserved/

No

Connect

66

Intel^®Pentium^®M Processor Datasheet

Package Mechanical Specifications and Pin Information

Table 22. Signal Description (Sheet 6 of 7)

Name

Type

Description

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter

the Sleep state. During Sleep state, the processor stops providing internal clock

signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.

Processors in this state will not recognize snoops or interrupts. The processor

will recognize only assertion of the RESET# signal, deassertion of SLP#, and

removal of the BCLK input while in Sleep state. If SLP# is deasserted, the

processor exits Sleep state and returns to Stop-Grant state, restarting its internal

clock signals to the bus and processor core units. If DPSLP# is asserted while in

the Sleep state, the processor will exit the Sleep state and transition to the Deep

Sleep state.

SLP#

Input

SMI# (System Management Interrupt) is asserted asynchronously by system

logic. On accepting a System Management Interrupt, the processor saves the

current state and enter System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the processor begins program execution

from the SMM handler.

SMI#

Input

If SMI# is asserted during the deassertion of RESET# the processor will tristate

its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low

power Stop-Grant state. The processor issues a Stop-Grant Acknowledge

transaction, and stops providing internal clock signals to all processor core units

except the system bus and APIC units. The processor continues to snoop bus

transactions and service interrupts while in Stop-Grant state. When STPCLK# is

deasserted, the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#

is an asynchronous input.

STPCLK#

TCK (Test Clock) provides the clock input for the processor Test Bus (also

known as the Test Access Port).

TCK

TDI

Input

Please refer to the ITP700 Debug Port Design Guide and the platform design

guides for termination requirements and implementation details.

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

Please refer to the ITP700 Debug Port Design Guide and the platform design

guides for termination requirements and implementation details.

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TDO

Output

Input

Please refer to the ITP700 Debug Port Design Guide and the platform design

guides for termination requirements and implementation details.

TEST1,

TEST2,

TEST3

TEST1, TEST2, and TEST3 must be left unconnected but should have a stuffing

option connection to V_SSseparately using 1-k, pull-down resistors. Please refer

to the platform design guides for more details.

THERMDA

THERMDC

Other

Thermal Diode Anode.

Thermal Diode Cathode.

The processor protects itself from catastrophic overheating by use of an internal

thermal sensor. This sensor is set well above the normal operating temperature

to ensure that there are no false trips. The processor will stop all execution when

the junction temperature exceeds approximately 125°C. This is signalled to the

system by the THERMTRIP# (Thermal Trip) pin.

THERMTRIP#

Output

Input

For termination requirements please refer to the platform design guides.

TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

TMS

Please refer to the ITP700 Debug Port Design Guide and the platform design

guides for termination requirements and implementation details.

Intel^®Pentium^®M Processor Datasheet

67

Package Mechanical Specifications and Pin Information

Table 22. Signal Description (Sheet 7 of 7)

Name

Type

Description

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of both system bus agents.

TRDY#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven low during power on Reset. Please refer to the ITP700 Debug Port

Design Guide and the platform design guides for termination requirements and

implementation details.

TRST#

Input

V_CC

Input

Processor core power supply.

V

_CCAprovides isolated power for the internal processor core PLL’s. Refer to the

V_CCA[3:0]

V_CCP

platform design guides for complete implementation details.

Processor I/O Power Supply.

Quiet power supply for on die COMP circuitry. These pins should be connected

to V_CCPon the motherboard. However, these connections should enable addition

of decoupling on the V_CCQlines if necessary.

V

_CCQ[1:0]

Input

V

_CCSENSEis an isolated low impedance connection to processor core power

(V_CC). It can be used to sense or measure power near the silicon with little noise.

Please refer to the platform design guides for termination recommendations and

more details.

V_CCSENSE

VID[5:0]

V_SSSENSE

Output

VID[5:0] (Voltage ID) pins are used to support automatic selection of power

supply voltages (Vcc). Unlike some previous generations of processors, these

are CMOS signals that are driven by the Intel Pentium M processor. The voltage

supply for these pins must be valid before the VR can supply Vcc to the

processor. Conversely, the VR output must be disabled until the voltage supply

for the VID pins becomes valid. The VID pins are needed to support the

processor voltage specification variations. See Table 3 for definitions of these

pins. The VR must supply the voltage that is requested by the pins, or disable

itself.

Output

V

_SSSENSEis an isolated low impedance connection to processor core V_SS. It can

be used to sense or measure ground near the silicon with little noise. Please

refer to the platform design guides for termination recommendations and more

details.

68

Intel^®Pentium^®M Processor Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

The Intel Pentium M processor requires a thermal solution to maintain temperatures within

operating limits. A complete thermal solution includes both component and system level thermal

management features. Component level thermal solutions include active or passive heatsinks or

heat exchangers attached to the processor exposed die. The solution should make firm contact with

the die while maintaining processor mechanical specifications such as pressure. A typical system

level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally

coupled to the processor using a heat pipe or direct die attachment. A secondary fan or air from the

processor fan may also be used to cool other platform components or lower the internal ambient

temperature within the system. The processor must remain within the minimum and maximum

junction temperature (Tj) specifications at the corresponding Thermal Design Power (TDP) value

listed in Table 23. The maximum junction temperature is defined by an activation of the processor

Intel Thermal Monitor.

Refer to Section 5.1.2 for more details. Analysis indicates that real applications are unlikely to

cause the processor to consume the theoretical maximum power dissipation for sustained time

periods. Intel recommends that complete thermal solution designs target the Thermal Design

Power (TDP) indicated in Table 23. The Intel Thermal Monitor feature is designed to help protect

the processor in the unlikely event that an application exceeds the TDP recommendation for a

sustained period of time. For more details on the usage of this feature, refer to Section 5.1.2. In all

cases the Intel Thermal Monitor feature must be enabled for the processor to remain within

specification.

Intel^®Pentium^®M Processor Datasheet

69

Thermal Specifications and Design Considerations

Table 23. Power Specifications for the Intel Pentium M Processor

Core Frequency

Symbol

Thermal Design Power

Unit

Notes

& Voltage

1.70 GHz & 1.484 V

1.60 GHz & 1.484 V

1.50 GHz & 1.484 V

1.40 GHz & 1.484 V

1.30 GHz & 1.388 V

1.30 GHz & 1.180 V

1.20 GHz & 1.180 V

1.10 GHz & 1.180 V

1.10 GHz & 1.004 V

1.00 GHz & 1.004 V

900 MHz & 1.004V

600 MHz & 0.956 V

600 MHz & 0.844 V

24.5

22

12

7

TDP

W

At 100°C, Notes 1, 4

7

6

4

Symbol

Parameter

Min

Typ

Max

Unit

Notes

Auto Halt, Stop-Grant Power at:

1.484 V

7.3

3.2

1.7

1.8

0.9

1.388 V (Pentium M 1.30 GHz)

1.180 V

P_AH,

W

At 50°C, Note 2

P_SGNT

1.004 V (ULV Pentium M)

0.956 V

0.844 V (ULV Pentium M)

Sleep Power at:

1.484 V

7.0

3.0

1.5

1.7

0.8

1.388 V (Pentium M 1.30 GHz)

1.180 V

P_SLP

W

At 50°C, Note 2

1.004 V (ULV Pentium M)

0.956 V

0.844 V (ULV Pentium M)

Deep Sleep Power at:

1.484 V

5.1

5.4

2.2

1.0

1.1

0.55

1.388 V (Pentium M 1.30 GHz)

1.180 V

P_DSLP

W

At 35°C, Note 2

1.004 V (ULV Pentium M)

0.956 V

0.844 V (ULV Pentium M)

P_DPRSLPDeeper Sleep Power

0.55

0.37

100

W

°C

At 35°C, Note 2

Notes 3, 4

P_DPRSLPDeeper Sleep Power (ULV

Pentium M only)

ULV

T_J

Junction Temperature

0

NOTES:

1. The Thermal Design Power (TDP) specification should be used to design the processor thermal solution. The

TDP is not the maximum theoretical power the processor can dissipate.

70

Intel^®Pentium^®M Processor Datasheet

Thermal Specifications and Design Considerations

2. Not 100% tested. These power specifications are determined by characterization of the processor currents at

higher temperatures and extrapolating the values for the temperature indicated.

3. As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to

indicate that the maximum T_Jhas been reached. Refer to Section 5.1 for more details.

4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within

specifications.

5.1

Thermal Specifications

5.1.1

Thermal Diode

The Intel Pentium M processor incorporates two methods of monitoring die temperature, the Intel

Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1) must

be used to determine when the maximum specified processor junction temperature has been

reached. The second method, the thermal diode, can be read by an off-die analog/digital converter

(a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal

diode may be used to monitor the die temperature of the processor for thermal management or

instrumentation purposes but cannot be used to indicate that the maximum T_Jof the processor has

been reached. Please see Section 5.1.2 for thermal diode usage recommendation when the

PROCHOT# signal is not asserted.

Table 24 and Table 25 provide the diode interface and specifications.

Note: The reading of the external thermal sensor (on the motherboard) connected to the processor

thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die.

This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the

location of the thermal diode and the hottest location on the die, and time based variations in the die

temperature measurement. Time based variations can occur when the sampling rate of the thermal

diode (by the thermal sensor) is slower than the rate at which the T_Jtemperature can change.

The offset between the thermal diode based temperature reading and the Intel Thermal Monitor

reading can be characterized using the Intel Thermal Monitor’s automatic mode activation of the

thermal control circuit. This temperature offset must be taken into account when using the

processor thermal diode to implement power management events.

Table 24. Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

B18

A18

Thermal diode anode

Thermal diode cathode

Table 25. Thermal Diode Specifications

Symbol

Parameter

Min

Typ

Max

300

1.00289

Unit

Notes

I_FW

n

Forward Bias Current

Diode Ideality Factor

Series Resistance

5

µA

Note 1

1.00151

1.00220

3.06

Notes 2, 3, 4

2, 3, 5

R_T

ohms

NOTES:

Intel^®Pentium^®M Processor Datasheet

71

Thermal Specifications and Design Considerations

1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not

support or recommend operation of the thermal diode when the processor power supplies are not within their

specified tolerance range.

2. Characterized at 100°C.

3. Not 100% tested. Specified by design/characterization.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

equation:

I

_FW=I_s*(e^(qVD/nkT)-1)

Where I_S= saturation current, q = electronic charge, V_D= voltage across the diode, k = Boltzmann Constant,

and T = absolute temperature (Kelvin).

5. The series resistance, R_T, is provided to allow for a more accurate measurement of the diode junction

temperature. R_Tas defined, includes the pins of the processor but does not include any socket resistance or

board trace resistance between the socket and the external remote diode thermal sensor. R_Tcan be used by

remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.

Another application is that a temperature offset can be manually calculated and programmed into an offset

register in the remote diode thermal sensors as exemplified by the equation:

T_error= [R_T*(N-1)*I_FWmin]/[(no/q)*ln N]

5.1.2

Intel Thermal Monitor

The Intel Thermal Monitor helps control the processor temperature by activating the TCC when the

processor silicon reaches its maximum operating temperature. The temperature at which the Intel

Thermal Monitor activates the thermal control circuit (TCC) is not user configurable and is not

software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched

(and serviced during the time that the clocks are on) while the TCC is active.

With a properly designed and characterized thermal solution, it is anticipated that the TCC would

only be activated for very short periods of time when running the most power intensive

applications. The processor performance impact due to these brief periods of TCC activation is

expected to be so minor that it would not be detectable. An under-designed thermal solution that is

not able to prevent excessive activation of the TCC in the anticipated ambient environment may

cause a noticeable performance loss, and may affect the long-term reliability of the processor. In

addition, a thermal solution that is significantly under designed may not be capable of cooling the

processor even when the TCC is active continuously.

The Intel Thermal Monitor controls the processor temperature by modulating (starting and

stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep^®technology

transition when the processor silicon reaches its maximum operating temperature. The Intel

Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode. If

both modes are activated, Automatic mode takes precedence. The Intel Thermal Monitor

Automatic Mode must be enabled via BIOS for the processor to be operating within

specifications.There are two Automatic modes called Intel Thermal Monitor 1 and Intel Thermal

Monitor 2. These modes are selected by writing values to the Model Specific Registers (MSRs) of

the processor. After Automatic mode is enabled, the TCC will activate only when the internal die

temperature reaches the maximum allowed value for operation.

Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the

processor will perform an Enhanced Intel SpeedStep technology transition to a lower operating

point. When the processor temperature drops below the critical level, the processor will make an

Enhanced Intel SpeedStep technology transition to the last requested operating point. Intel Thermal

Monitor 2 is the recommended mode on the Intel Pentium M processor.

If a processor load-based Enhanced Intel SpeedStep technology transition (through MSR write) is

initiated when an Intel Thermal Monitor 2 period is active, there are two possible results:

1.If the processor load based Enhanced Intel SpeedStep technology transition target

frequency is higher than the Intel Thermal Monitor 2 transition based target frequency, the

processor load-based transition will be deferred until the Intel Thermal Monitor 2 event has

been completed.

72

Intel^®Pentium^®M Processor Datasheet

Thermal Specifications and Design Considerations

2.If the processor load-based Enhanced Intel SpeedStep technology transition target

frequency is

lower than the Intel Thermal Monitor 2 transition based target frequency, the processor will

transition to the processor load-based Enhanced Intel SpeedStep technology target

frequency point.

When Intel Thermal Monitor 1 is enabled, and a high temperature situation exists, the clocks will

be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are

processor speed dependent and will decrease linearly as processor core frequencies increase. After

the temperature has returned to a non-critical level, modulation ceases and the TCC goes inactive.

A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the

TCC when the processor temperature is near the trip point. The duty cycle is factory configured

and cannot be modified. Also, Automatic mode does not require any additional hardware, software

drivers or interrupt handling routines. Processor performance will be decreased by the same

amount as the duty cycle when the TCC is active, however, with a properly designed and

characterized thermal solution the TCC most likely will never be activated, or will be activated

only briefly during the most power intensive applications.

The TCC may also be activated using On-Demand mode. If bit 4 of the ACPI Intel Thermal

Monitor Control Register is written to a "1", the TCC will be activated immediately, independent of

the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of

the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor

Control Register. In Automatic mode, the duty cycle is fixed at 50% on, 50% off, in On-Demand

mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in

12.5% increments. On-Demand mode can be used at the same time Automatic mode is enabled,

however, if the system tries to enable the TCC via On-Demand mode at the same time Automatic

mode is enabled and a high temperature condition exists, Automatic mode will take precedence.

An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its

temperature is above the thermal trip point. Bus snooping and interrupt latching are also active

while the TCC is active.

Note: PROCHOT# will not be asserted when the processor is in the Stop-Grant, Sleep, Deep Sleep, and

Deeper Sleep low power states (internal clocks stopped), hence the thermal diode reading must be

used as a safeguard to maintain the processor junction temperature within the 100 °C (maximum)

specification. If the platform thermal solution is not able to maintain the processor junction

temperature within the maximum specification, the system must initiate an orderly shutdown to

prevent damage. If the processor enters one of the above low power states with PROCHOT#

already asserted, PROCHOT# will remain asserted until the processor exits the low power state

and the processor junction temperature drops below the thermal trip point.

If Automatic mode is disabled the processor will be operating out of specification. Whether the

automatic or On-Demand modes are enabled or not, in the event of a catastrophic cooling failure,

the processor will automatically shut down when the silicon has reached a temperature of

approximately 125 °C. At this point the system bus signal THERMTRIP# will go active.

THERMTRIP# activation is independent of processor activity and does not generate any bus

cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the

time specified in Chapter 3.

Intel^®Pentium^®M Processor Datasheet

73

Thermal Specifications and Design Considerations

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74

IIntel^®Pentium^®M Processor Datasheet

Debug Tools Specifications

6 Debug Tools Specifications

Please refer to the ITP700 Debug Port Design Guide and the platform design guides for

information regarding debug tools specifications.

6.1

Logic Analyzer Interface (LAI)

Intel is working with logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in

debugging Intel Pentium M processor systems. The following information is general in nature.

Specific information must be obtained from the logic analyzer vendor.

Due to the complexity of Intel Pentium M processor systems, the LAI is critical in providing the

ability to probe and capture system bus signals. There are two sets of considerations to keep in

mind when designing an Intel Pentium M processor system that can make use of an LAI:

mechanical and electrical.

6.1.1

6.1.2

Mechanical Considerations

The LAI is installed between the processor socket and the Intel Pentium M processor. The LAI pins

plug into the socket, while the Intel Pentium M processor pins plug into a socket on the LAI.

Cabling that is part of the LAI egresses the system to allow an electrical connection between the

Intel Pentium M processor and a logic analyzer. The maximum volume occupied by the LAI,

known as the keepout volume, as well as the cable egress restrictions, should be obtained from the

logic analyzer vendor. System designers must make sure that the keepout volume remains

unobstructed inside the system.

Electrical Considerations

The LAI will also affect the electrical performance of the system bus; therefore, it is critical to

obtain electrical load models from each of the logic analyzers to be able to run system level

simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for

electrical specifications and load models for the LAI solution they provide.

Intel^®Pentium^®M Processor Datasheet

75


型号：	BXM80535GC1400E
厂家：	INTEL
描述：	RISC Microprocessor, 64-Bit, 1400MHz, CMOS, PPGA478
文件：	总75页 (文件大小：1401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BXM80535GC1400E [INTEL]

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