CL8064701479801/SR1DM [INTEL]
RISC Microprocessor, 64-Bit, 1600MHz, CMOS;
| 型号： | CL8064701479801/SR1DM |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 64-Bit, 1600MHz, CMOS 外围集成电路 |
| 文件： | 总123页 (文件大小：2232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mobile 4th Generation Intel® Core™
Processor Family, Mobile Intel®
Pentium® Processor Family, and
Mobile Intel® Celeron® Processor
Family
Datasheet – Volume 1 of 2
Supporting 4th Generation Intel® Core™ processor based on Mobile
U-Processor and Y-Processor Lines
Supporting Mobile Intel® Pentium® and Mobile Intel® Celeron®
Processor Families
December 2013
Order No.: 329001-005
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OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND
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characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without
notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
This document contains information on products in the design phase of development.
Code Names are only for use by Intel to identify products, platforms, programs, services, etc. ("products") in development by Intel that have not been
made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as "commercial" names for products. Also,
they are not intended to function as trademarks.
For Enhanced Intel SpeedStep® Technology, see the Processor Spec Finder at http://ark.intel.com/ or contact your Intel representative for more
information.
Intel® AES-NI requires a computer system with an AES-NI enabled processor, as well as non-Intel software to execute the instructions in the correct
sequence. AES-NI is available on select Intel® processors. For availability, consult your reseller or system manufacturer. For more information, see
http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-instructions-aes-ni/.
Intel® Hyper-Threading Technology (Intel® HT Technology) is available on select Intel® Core™ processors. It requires an Intel® HT Technology enabled
system. Consult your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel® Core™
i5-750. For more information including details on which processors support Intel® HT Technology, visit http://www.intel.com/info/hyperthreading.
Intel® 64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific
hardware and software you use. Consult your PC manufacturer for more information. For more information, visit http://www.intel.com/
content/www/us/en/architecture-and-technology/microarchitecture/intel-64-architecture-general.html.
No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires a computer with
Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured
launched environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/
security.
Intel® Virtualization Technology (Intel® VT) requires a computer system with an enabled Intel® processor, BIOS, and virtual machine monitor (VMM).
Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be
compatible with all operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization.
Requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only available on select
Intel® processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system configuration. For more
information, visit http://www.intel.com/go/turbo.
Requires activation and a system with a corporate network connection, an Intel® AMT-enabled chipset, network hardware and software. For notebooks,
Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or powered
off. Results dependent upon hardware, setup and configuration.
Intel, Intel Core, Celeron, Pentium, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2013, Intel Corporation. All rights reserved.
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
2
December 2013
Order No.: 329001-005
Contents—Processors
Contents
Revision History..................................................................................................................9
1.0 Introduction................................................................................................................10
1.1 Supported Technologies.........................................................................................11
1.2 Power Management Support...................................................................................12
1.3 Thermal Management Support................................................................................12
1.4 Package Support...................................................................................................13
1.5 Processor Testability............................................................................................. 13
1.6 Terminology.........................................................................................................13
1.7 Related Documents...............................................................................................16
2.0 Interfaces................................................................................................................... 17
2.1 System Memory Interface......................................................................................17
2.1.1 System Memory Technology Supported.......................................................17
2.1.2 System Memory Timing Support................................................................. 19
2.1.3 System Memory Organization Modes........................................................... 19
2.1.4 System Memory Frequency........................................................................ 20
2.1.5 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements............... 20
2.1.6 Data Scrambling......................................................................................21
2.1.7 DRAM Clock Generation............................................................................. 21
2.1.8 DRAM Reference Voltage Generation........................................................... 21
2.2 Processor Graphics................................................................................................22
2.3 Processor Graphics Controller (GT)..........................................................................22
2.3.1 3D and Video Engines for Graphics Processing.............................................. 22
2.4 Digital Display Interface (DDI)................................................................................24
2.5 Platform Environmental Control Interface (PECI).......................................................29
2.5.1 PECI Bus Architecture................................................................................29
3.0 Technologies...............................................................................................................31
3.1 Intel® Virtualization Technology (Intel® VT)............................................................. 31
3.2 Intel® Trusted Execution Technology (Intel® TXT).....................................................35
3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)....................................... 36
3.4 Intel® Turbo Boost Technology 2.0..........................................................................37
3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)................................................37
3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI).......................38
3.7 Intel® 64 Architecture x2APIC................................................................................ 38
3.8 Power Aware Interrupt Routing (PAIR)....................................................................40
3.9 Execute Disable Bit............................................................................................... 40
3.10 Intel® Boot Guard...............................................................................................40
3.11 Supervisor Mode Execution Protection (SMEP)........................................................40
3.12 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)... 41
4.0 Power Management.................................................................................................... 42
4.1 Advanced Configuration and Power Interface (ACPI) States Supported.........................43
4.2 Processor Core Power Management......................................................................... 44
4.2.1 Enhanced Intel® SpeedStep® Technology Key Features..................................44
4.2.2 Low-Power Idle States...............................................................................45
4.2.3 Requesting Low-Power Idle States...............................................................46
4.2.4 Core C-State Rules....................................................................................46
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
3
Processors—Contents
4.2.5 Package C-States......................................................................................48
4.2.6 Package C-States and Display Resolutions....................................................51
4.3 Integrated Memory Controller (IMC) Power Management............................................53
4.3.1 Disabling Unused System Memory Outputs...................................................53
4.3.2 DRAM Power Management and Initialization..................................................53
4.3.3 DDR Electrical Power Gating (EPG)..............................................................56
4.4 Graphics Power Management..................................................................................56
4.4.1 Intel® Rapid Memory Power Management (Intel® RMPM)................................56
4.4.2 Graphics Render C-State............................................................................56
4.4.3 Intel® Smart 2D Display Technology (Intel® S2DDT)..................................... 56
4.4.4 Intel® Graphics Dynamic Frequency............................................................ 57
4.4.5 Intel® Display Power Saving Technology (Intel® DPST).................................57
4.4.6 Intel® Automatic Display Brightness ...........................................................57
4.4.7 Intel® Seamless Display Refresh Rate Technology (Intel® SDRRS
Technology)............................................................................................ 58
5.0 Thermal Management................................................................................................. 59
5.1 Thermal Considerations......................................................................................... 59
5.2 Intel® Turbo Boost Technology 2.0 Power Monitoring.................................................60
5.3 Intel® Turbo Boost Technology 2.0 Power Control..................................................... 60
5.3.1 Package Power Control.............................................................................. 60
5.3.2 Turbo Time Parameter...............................................................................61
5.4 Configurable TDP (cTDP) and Low-Power Mode......................................................... 61
5.4.1 Configurable TDP...................................................................................... 61
5.4.2 Low-Power Mode.......................................................................................62
5.5 Thermal and Power Specifications........................................................................... 62
5.6 Thermal Management Features...............................................................................65
5.6.1 Adaptive Thermal Monitor.......................................................................... 65
5.6.2 Digital Thermal Sensor.............................................................................. 67
5.6.3 PROCHOT# Signal.....................................................................................68
5.6.4 On-Demand Mode.....................................................................................70
5.6.5 Intel® Memory Thermal Management.......................................................... 70
5.6.6 Scenario Design Power (SDP)..................................................................... 71
6.0 Signal Description.......................................................................................................72
6.1 System Memory Interface Signals........................................................................... 72
6.2 Memory Compensation and Miscellaneous Signals..................................................... 75
6.3 Reset and Miscellaneous Signals............................................................................. 76
6.4 embedded DisplayPort* (eDP*) Signals....................................................................77
6.5 Display Interface Signals....................................................................................... 77
6.6 Testability Signals.................................................................................................77
6.7 Error and Thermal Protection Signals.......................................................................78
6.8 Power Sequencing Signals......................................................................................79
6.9 Processor Power Signals........................................................................................ 79
6.10 Sense Signals.....................................................................................................80
6.11 Ground and Non-Critical to Function (NCTF) Signals.................................................80
6.12 Processor Internal Pull-Up / Pull-Down Terminations................................................80
7.0 Electrical Specifications.............................................................................................. 82
7.1 Integrated Voltage Regulator..................................................................................82
7.2 Power and Ground Pins..........................................................................................82
7.3 VCC Voltage Identification (VID)..............................................................................82
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
4
December 2013
Order No.: 329001-005
Contents—Processors
7.4 Reserved or Unused Signals................................................................................... 87
7.5 Signal Groups.......................................................................................................87
7.6 Test Access Port (TAP) Connection.......................................................................... 89
7.7 DC Specifications.................................................................................................89
7.8 Voltage and Current Specifications.......................................................................... 90
7.8.1 Platform Environment Control Interface (PECI) DC Characteristics................... 96
7.8.2 Input Device Hysteresis............................................................................. 97
8.0 Package Specifications................................................................................................98
8.1 Package Mechanical Attributes................................................................................98
8.2 Package Loading Specifications...............................................................................98
8.3 Package Storage Specifications...............................................................................99
9.0 Processor Ball and Signal Information...................................................................... 100
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
5
Processors—Figures
Figures
1
2
3
4
5
6
7
8
9
Platform Block Diagram............................................................................................11
Intel® Flex Memory Technology Operations.................................................................20
Processor Display Architecture...................................................................................25
DisplayPort* Overview............................................................................................. 26
HDMI* Overview..................................................................................................... 27
PECI Host-Clients Connection Example....................................................................... 30
Device to Domain Mapping Structures........................................................................ 34
Processor Power States............................................................................................ 42
Processor Package and Core C-States.........................................................................43
10 Idle Power Management Breakdown of the Processor Cores ..........................................45
11 Package C-State Entry and Exit................................................................................. 49
12 Package Power Control.............................................................................................61
13 Input Device Hysteresis............................................................................................97
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
6
December 2013
Order No.: 329001-005
Tables—Processors
Tables
1
2
3
4
5
6
7
8
9
Terminology........................................................................................................... 13
Related Documents..................................................................................................16
Processor DIMM Support Summary by Product ........................................................... 17
Supported DDR3L / DDR3L-RS SO-DIMM Module Configurations ................................... 18
Supported LPDDR3 Memory Down Configurations........................................................ 18
Supported DDR3L / DDR3L-RS Memory Down Configurations........................................ 18
DRAM System Memory Timing Support.......................................................................19
Processor Supported Audio Formats over HDMI*and DisplayPort*.................................. 27
Multiple Display Configuration for U-Processor Line...................................................... 28
10 Multiple Display Configuration for Y-Processor Line.......................................................28
11 DisplayPort and embedded DisplayPort* Resolutions per Link Data Rate for U-
Processor Line.........................................................................................................29
12 DisplayPort and embedded DisplayPort* Resolutions per Link Data Rate for Y-
Processor Line.........................................................................................................29
13 System States.........................................................................................................43
14 Processor Core / Package State Support..................................................................... 43
15 Integrated Memory Controller States..........................................................................44
16 G, S, and C Interface State Combinations .................................................................. 44
17 Coordination of Core Power States at the Package Level............................................... 49
18 Deepest Package C-State Available – U-Processor Line and Y-Processor Line................... 52
19 Targeted Memory State Conditions............................................................................ 55
20 Intel® Turbo Boost Technology 2.0 Package Power Control Settings............................... 60
21 Configurable TDP Modes...........................................................................................62
22 Thermal Design Power (TDP) Specifications.................................................................63
23 Junction Temperature Specification............................................................................64
24 Maximum Idle Power Specification............................................................................. 64
25 Signal Description Buffer Types................................................................................. 72
26 DDR3L / DDR3L-RS Memory Channel A Interface (Memory-Down / SO-DIMM) Signals...... 72
27 DDR3L / DDR3L-RS Memory Channel B Interface (Memory-Down / SO-DIMM) Signals...... 73
28 LPDDR3 Memory Channel A Interface (Memory-Down) Signals.......................................74
29 LPDDR3 Memory Channel B Interface (Memory-Down) Signals.......................................75
30 LPDDR3 / DDR3L / DDR3L-RS Reference and Compensation Signals...............................75
31 Reset and Miscellaneous Signals................................................................................76
32 embedded Display Port* Signals................................................................................77
33 Display Interface Signals.......................................................................................... 77
34 Testability Signals....................................................................................................77
35 Error and Thermal Protection Signals..........................................................................78
36 Power Sequencing Signals........................................................................................ 79
37 Processor Power Signals...........................................................................................79
38 Sense Signals......................................................................................................... 80
39 Ground and Non-Critical to Function (NCTF) Signals..................................................... 80
40 Processor Internal Pull-Up / Pull-Down Terminations.................................................... 80
41 Voltage Regulator (VR) 12.5 Voltage Identification.......................................................83
42 Signal Groups......................................................................................................... 87
43 Processor Core Active and Idle Mode DC Voltage and Current Specifications.................... 90
44 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications.........................91
45 Vcc Sustain (VccST) Supply DC Voltage and Current Specifications..................................91
46 DDR3L / DDR3L-RS Signal Group DC Specifications......................................................92
47 LPDDR3 Signal Group DC Specifications......................................................................93
48 Digital Display Interface Group DC Specifications.........................................................95
49 embedded DisplayPort* (eDP*) Group DC Specifications...............................................95
50 CMOS Signal Group DC Specifications.........................................................................95
51 GTL Signal Group and Open Drain Signal Group DC Specifications..................................95
52 VR Enable CMOS Signal Group DC Specification........................................................... 96
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
7
Processors—Tables
53 VCOMP_OUT and VCCIO_TERM .................................................................................96
54 Platform Environment Control Interface (PECI) DC Electrical Limits................................ 97
55 Package Mechanical Attributes...................................................................................98
56 Package Loading Specifications..................................................................................98
57 Package Storage Specifications..................................................................................99
58 Ball List by Signal Name for DDR3L Configuration.......................................................100
59 Ball List by Signal Name for LPDDR3 Configuration.....................................................112
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
8
December 2013
Order No.: 329001-005
Revision History—Processors
Revision History
Revision
Description
Date
001
•
Initial Release
June 2013
•
•
•
Updated Section 1.1, Supported Technologies
Updated Table 3, Processor DIMM Support Summary by Product
Updated Table 4, Supported DDR3L / DDR3L-RS SO-DIMM
Module Configurations
•
•
•
Updated Section 2.4, Digital Display Interface (DDI)
Updated Figure 3, Processor Display Architecture
Updated Table 9, Multiple Display Configuration for U-Processor
Line
•
•
•
•
Added Table 10, Multiple Display Configuration for Y-Processor
Line
002
June 2013
Updated Table 11, DisplayPort and Embedded DisplayPort*
Resolutions per Link Data Rate for U-Processor Line
Added Table 12, DisplayPort and Embedded DisplayPort*
Resolutions per Link Data Rate for Y-Processor Line
Updated Table 16, Intel Turbo Boost Technology 2.0 Package
Power Control Settings
•
•
Updated Table 21, Thermal Design power (TDP) Specifications
Updated Table 23, Package Turbo Parameters
•
Added Mobile 4th Generation Intel® Core™ i7-4610Y, i5-4300Y,
i5-4302Y, i7-4600U, i5-4300U, i5-4202Y, i5-4210Y, i3-4012Y,
i3-4020Y, i3-4005U processors
•
•
•
Added Mobile Intel® Pentium® 3560Y and 3556U processors
Added Mobile Intel® Celeron® 2980U and 2995U processors
003
September 2013
Added Section 4.2.6, "Package C-States and Display
Resolutions".
004
005
•
Minor edits throughout for clarity
November 2013
December 2013
•
•
Added Mobile Intel® Pentium® 3558U and 3561Y processors
Added Mobile Intel® Celeron® 2981U and 2957U processors
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
9
Processors—Introduction
1.0
Introduction
The 4th Generation Intel® Core™ processor based on Mobile U-Processor and Y-
Processor Lines, Mobile Intel® Pentium® processor family, and Mobile Intel® Celeron®
processor family are 64-bit, multi-core processors built on 22-nanometer process
technology.
The processors are designed for a one-chip platform consisting of a Multi-Chip
Package (MCP) processor that includes a low-power Platform Controller Hub (PCH) die
on the same package as the processor die. See the following figure.
Throughout this document, the 4th Generation Intel® Core™ processor based on
Mobile U-Processor and Y-Processor Lines, Mobile Intel® Pentium® processor family,
and Mobile Intel® Celeron® processor family may be referred to simply as "processor".
Throughout this document, the 4th Generation Intel® Core™ processor based on
Mobile U-Processor and Y-Processor Lines refers to the Mobile 4th Generation Intel®
Core™i7-4650U, i7-4610Y, i7-4600U, i7-4558U, i7-4550U, i7-4500U, i5-4350U,
i5-4302Y, i5-4300Y, i5-4300U, i5-4288U, i5-4258U, i5-4250U, i5-4210Y, i5-4202Y,
i5-4200U, i5-4200Y, i3-4158U, i3-4012Y, i3-4005U, i3-4100U, i3-4010U, and
i3-4010Y processors.
Throughout this document, the Mobile Mobile Intel® Pentium® processor family refers
to the Intel® Pentium® 3561Y, 3560Y, 3558U, and 3556U processors.
Throughout this document, the Mobile Intel® Celeron® processor family refers to the
Intel® Celeron® 2981U, 2980U, 2957U, and 2955U processor.
Note:
Some processor features are not available on all platforms. Refer to the processor
Specification Update document for details.
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
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December 2013
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Introduction—Processors
Figure 1.
Platform Block Diagram
DDR3L/LPDDR3
DDR Ch.A
DDR Ch.B
DDIx2
eDP
Digital Display
Interface x 2
Embedded DisplayPort*
SATA
SSD Drive
USB 2.0
Cameras
BIOS/FW Flash
TPM
USB 2.0/3.0
HDA/I2S
USB 2.0/3.0 Ports
HD Audio Codec
SPI
SPI
PECI
SMBus
EC
I2C*
Touch Screen
USB 2.0
Fingerprint Sensor
I2C, UART or USB
BT/3G/4G
WiFi / WiMax
Gyro
GPS
GPIO
Gigabit Network
Connection
NFC
SD Slot
Magnetometer
Touch Pad
Accelometer
Ambient Light
Sensor
1.1
Supported Technologies
•
•
•
•
•
•
•
•
•
•
•
•
Intel® Virtualization Technology (Intel® VT)
Intel® Active Management Technology 9.5 (Intel® AMT 9.5 )
Intel® Trusted Execution Technology (Intel® TXT)
Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
Intel® Hyper-Threading Technology (Intel® HT Technology)
Intel® 64 Architecture
Execute Disable Bit
Intel® Turbo Boost Technology 2.0
Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
PCLMULQDQ Instruction
Intel® Secure Key
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
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Datasheet – Volume 1 of 2
11
Processors—Introduction
•
Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-
NI)
•
•
•
PAIR – Power Aware Interrupt Routing
SMEP – Supervisor Mode Execution Protection
Boot Guard
Note:
The availability of the features may vary between processor SKUs.
1.2
Power Management Support
Processor Core
•
Full support of ACPI C-states as implemented by the following processor C-states:
— C0, C1, C1E, C3, C6, C7, C8, C9, C10
•
Enhanced Intel SpeedStep® Technology
System
•
S0, S3, S4, S5
Memory Controller
•
•
Conditional self-refresh
Dynamic power-down
Processor Graphics Controller
•
•
•
•
•
Intel® Rapid Memory Power Management (Intel® RMPM)
Intel® Smart 2D Display Technology (Intel® S2DDT)
Graphics Render C-state (RC6)
Intel® Seamless Display Refresh Rate Switching with eDP port
Intel® Display Power Saving Technology (Intel® DPST)
1.3
Thermal Management Support
•
•
•
•
•
•
•
•
•
Digital Thermal Sensor
Adaptive Thermal Monitor
THERMTRIP# and PROCHOT# support
On-Demand Mode
Memory Open and Closed Loop Throttling
Memory Thermal Throttling
External Thermal Sensor (TS-on-DIMM and TS-on-Board)
Render Thermal Throttling
Fan speed control with DTS
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
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Introduction—Processors
1.4
1.5
Package Support
The processor is available in the following package:
A 40 mm x 24 mm x 1.5 mm BGA package (BGA1168)
•
Processor Testability
The processor includes boundary-scan for board and system level testability.
1.6
Terminology
Table 1.
Terminology
Term
Description
APD
Active Power-down
Bus/Device/Function
Ball Grid Array
B/D/F
BGA
BLC
Backlight Compensation
Block Level Transfer
Bits per pixel
BLT
BPP
CKE
Clock Enable
CLTM
DDI
Closed Loop Thermal Management
Digital Display Interface
DDR3
DDR3L
Third-generation Double Data Rate SDRAM memory technology
DDR3 Low Voltage
DDR3L-RS
DLL
DDR3 Low Voltage Reduced Standby Power
Delay-Locked Loop
DMA
DP
Direct Memory Access
DisplayPort*
DTS
Digital Thermal Sensor
EC
Embedded Controller
ECC
Error Correction Code
eDP*
EPG
embedded DisplayPort*
Electrical Power Gating
EU
Execution Unit
FMA
Floating-point fused Multiply Add instructions
Fan Speed Control
FSC
HDCP
HDMI*
HFM
High-bandwidth Digital Content Protection
High Definition Multimedia Interface
High Frequency Mode
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
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Datasheet – Volume 1 of 2
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Processors—Introduction
Term
Description
iDCT
IHS
GFX
GUI
IMC
Inverse Discrete
Integrated Heat Spreader
Graphics
Graphical User Interface
Integrated Memory Controller
Intel® 64
64-bit memory extensions to the IA-32 architecture
Technology
Intel® DPST
Intel® TSX-NI
Intel® TXT
Intel Display Power Saving Technology
Intel Transactional Synchronization Extensions - New Instructions
Intel Trusted Execution Technology
Intel Virtualization Technology. Processor virtualization, when used in conjunction
with Virtual Machine Monitor software, enables multiple, robust independent software
environments inside a single platform.
Intel® VT
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware
assist, under system software (Virtual Machine Manager or OS) control, for enabling
I/O device virtualization. Intel VT-d also brings robust security by providing protection
from errant DMAs by using DMA remapping, a key feature of Intel VT-d.
Intel® VT-d
IOV
ISI
I/O Virtualization
Inter-Symbol Interference
Integrated Trusted Platform Module
ITPM
Low Frequency Mode. LFM is Pn in the P-state table. It can be read at MSR CEh
[47:40].
LFM
LFP
Local Flat Panel
LPDDR3
MCP
Low-Power Third-generation Double Data Rate SDRAM memory technology
Multi-Chip Package
Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and
can be read from MSR CEh [55:48].
MFM
MLE
MLC
MSI
MSL
MSR
Measured Launched Environment
Mid-Level Cache
Message Signaled Interrupt
Moisture Sensitive Labeling
Model Specific Registers
Non-Critical to Function. NCTF locations are typically redundant ground or non-critical
reserved, so the loss of the solder joint continuity at end of life conditions will not
affect the overall product functionality.
NCTF
ODT
On-Die Termination
OLTM
Open Loop Thermal Management
Platform Compatibility Guide (PCG) (previously known as FMB) provides a design
target for meeting all planned processor frequency requirements.
PCG
PCH
Platform Controller Hub. The chipset with centralized platform capabilities including
the main I/O interfaces along with display connectivity, audio features, power
management, manageability, security, and storage features.
continued...
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Introduction—Processors
Term
Description
The Platform Environment Control Interface (PECI) is a one-wire interface that
provides a communication channel between Intel processor and chipset components
to external monitoring devices.
PECI
PL1, PL2
PPD
Power Limit 1 and Power Limit 2
Pre-charge Power-down
Processor
The 64-bit multi-core component (package)
The term “processor core” refers to Si die itself, which can contain multiple execution
cores. Each execution core has an instruction cache, data cache, and 256-KB L2
cache. All execution cores share the L3 cache.
Processor Core
Processor Graphics
Rank
Intel Processor Graphics
A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These
devices are usually, but not always, mounted on a single side of a SO-DIMM.
SCI
SDP
SF
System Control Interrupt. SCI is used in the ACPI protocol.
Scenario Design Power
Strips and Fans
SMM
SMX
System Management Mode
Safer Mode Extensions
A non-operational state. The processor may be installed in a platform, in a tray, or
loose. Processors may be sealed in packaging or exposed to free air. Under these
conditions, processor landings should not be connected to any supply voltages, have
any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed
packaging or a device removed from packaging material), the processor must be
handled in accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
Storage Conditions
SVID
TAC
TAP
Serial Voltage Identification
Thermal Averaging Constant
Test Access Point
The case temperature of the processor, measured at the geometric center of the top-
side of the TTV IHS.
TCASE
TCC
Thermal Control Circuit
TCONTROL is a static value that is below the TCC activation temperature and used as a
trigger point for fan speed control. When DTS > TCONTROL, the processor must comply
to the TTV thermal profile.
TCONTROL
Thermal Design Power: Thermal solution should be designed to dissipate this target
power level. TDP is not the maximum power that the processor can dissipate.
TDP
TLB
TTV
Translation Look-aside Buffer
Thermal Test Vehicle. A mechanically equivalent package that contains a resistive
heater in the die to evaluate thermal solutions.
Thermal Monitor. A power reduction feature designed to decrease temperature after
the processor has reached its maximum operating temperature.
TM
VCC
VDDQ
VF
Processor core power supply
DDR3L and LPDDR3 power supply.
Vertex Fetch
VID
Voltage Identification
continued...
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Processors—Introduction
Term
Description
VS
Vertex Shader
VLD
VMM
VR
Variable Length Decoding
Virtual Machine Monitor
Voltage Regulator
VSS
Processor ground
1.7
Related Documents
Table 2.
Related Documents
Document
Document Number /
Location
Mobile 4th Generation Intel® Core® Processor Family, Mobile Intel® Pentium®
Processor Family, and Mobile Intel® Celeron® Processor Family Datasheet, Volume
2 of 2
Supporting 4th Generation Intel® Core® processor based on Mobile U-Processor
and Y-Processor Lines
329002
328903
Mobile 4th Generation Intel® Core® Processor Family, Mobile Intel® Pentium®
Processor Family, and Mobile Intel® Celeron® Processor Family Specification
Update
Mobile 4th Generation Intel® Core® Processor I/O Family Datasheet
Mobile 4th Generation Intel® Core® Processor I/O Family Specification Update
Advanced Configuration and Power Interface 3.0
329003
329004
http://www.acpi.info/
http://
www.pcisig.com/
specifications
PCI Local Bus Specification 3.0
PCI Express Base Specification, Revision 2.0
DDR3 SDRAM Specification
http://www.pcisig.com
http://www.jedec.org
http://www.vesa.org
DisplayPort* Specification
http://www.intel.com/
products/processor/
manuals/index.htm
Intel® 64 and IA-32 Architectures Software Developer's Manuals
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Interfaces—Processors
2.0
Interfaces
2.1
System Memory Interface
•
Two channels of DDR3L/DDR3L-RS and LPDDR3 memory with Unbuffered Small
Outline Dual In-Line Memory Modules (SO-DIMM) with a maximum of one DIMM
per channel and memory down.
•
•
•
•
•
•
Single-channel and dual-channel memory organization modes
Data burst length of eight for all memory organization modes
DDR3L/DDR3L-RS I/O Voltage of 1.35V
64-bit wide channels
Non-ECC, Unbuffered DDR3L/DDR3L-RS SO-DIMMs and memory down
Theoretical maximum memory bandwidth of:
— 21.3 GB/s in dual-channel mode assuming DDR3L/DDR3L-RS/LPDDR3
1333 MT/s
— 25.6 GB/s in dual-channel mode assuming DDR3L/DDR3L-RS/LPDDR3
1600 MT/s
2.1.1
System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3L/DDR3L-RS and LPDDR3
protocols with two independent, 64-bit wide channels. It supports one unbuffered non-
ECC DDR3L/DDR3L-RS DIMM per channel; thus, allowing up to two device ranks per
channel.
Table 3.
Processor DIMM Support Summary by Product
Processors
TDP
28W
15W
Graphics
Configuration
DIMM Per
Channel
DDR3L /
DDR3L-RS
(MT/s)
LPDDR3
(MT/s)
GT3
GT3
GT2
GT1
1 DPC
1 DPC
1 DPC
1 DPC
1333/1600
1333/1600
1333/1600
1333/1600
N/A
1333/1600
1333/1600
1333/1600
U-Processor (Dual-Core)
Y-Processor (Dual-Core)
11.5W (6W
SDP / 4.5W
SDP)
GT1, GT2
1 DPC
1333/1600
1333/1600
Notes: 1. LPDDR3 support may vary between the processor SKUs.
2. DDR3L-RS is supported as a memory configuration. Actual validation checkout depends on parts
and vendor availability.
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Data Transfer Rates:
•
DDR3L-RS is supported as a memory configuration. Actual validation checkout
depends on parts and vendor availability.
•
•
1333 MT/s (PC3-10600)
1600 MT/s (PC3-12800)
SO-DIMM Modules:
•
Standard 2Gb and 4Gb technologies and addressing are supported for x8 and x16
devices. There is no support for memory modules with different technologies or
capacities on opposite sides of the same memory module. If one side of a memory
module is populated, the other side is either identical or empty.
LPDDR3 Memory Down:
•
•
Quad Ranked x16
Single and Dual Ranked x32
Table 4.
Supported DDR3L / DDR3L-RS SO-DIMM Module Configurations
Raw Card
Version
DIMM
Capacity
DRAM
Organization
# of DRAM
Devices
# of Row/Col
Address Bits
# of Banks
Inside DRAM
Page Size
A
B
C
F
4 GB
4 GB
2 GB
4 GB
8 GB
256 M x 16
512 M x 8
256 M x 16
256 M x 8
512 M x 8
8
8
15/10
16/10
15/10
15/10
16/10
8
8
8
8
8
8K
8K
8K
8K
8K
4
16
16
F
Table 5.
Supported LPDDR3 Memory Down Configurations
DIMM
Capacity
PKG Type
(Dies bits x
PKG bits)
Die
Density
PKG
Density
Dies Per
Channel
PKGs per
Channel
Physical
Device Rank
Banks
Inside
DRAM
Page
Size
2 GB
4 GB
8 GB
SDP 32 x32
DDP 32 x32
QDP 16 x32
4 Gb
4 Gb
4 Gb
4 Gb
8 Gb
2
4
8
2
2
2
1
2
2
8
8
8
8K
8K
8K
16 Gb
Note: SDP = Single Die Package, DDP = Dual Die Package, QDP = Quad Die Package
Table 6.
Supported DDR3L / DDR3L-RS Memory Down Configurations
System
Capacity Organization
DRAM
Dies Per
Package
PKG
Density
Die
Density
Dies Per
Channel
PKGs
Per
Channel
Physical
Device
Rank
Banks
Inside
DRAM
Page Size
2 GB
4 GB
8 GB
128 M x 16
256 M x 16
256 M x 16
SDP
SDP
DDP
2 Gb
4 Gb
8 Gb
2 Gb
4 Gb
4 Gb
4
4
8
4
4
4
1
1
2
8
8
8
8K
8K
8K
Note: SDP = Single Die Package, DDP = Dual Die Package
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2.1.2
System Memory Timing Support
The IMC supports the following DDR3L/DDR3L-RS Speed Bin, CAS Write Latency
(CWL), and command signal mode timings on the main memory interface:
•
•
•
•
•
tCL = CAS Latency
tRCD = Activate Command to READ or WRITE Command delay
tRP = PRECHARGE Command Period
CWL = CAS Write Latency
Command Signal modes = 1N indicates a new command may be issued every
clock and 2N indicates a new command may be issued every 2 clocks. Command
launch mode programming depends on the transfer rate and memory
configuration.
Table 7.
DRAM System Memory Timing Support
Segment
DRAM
Device
Transfer
Rate
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
DPC
(SO-
CMD
Mode
(MT/s)
DIMM
Only)
DDR3L/
DDR3L-RS
1333
1333
1600
1600
8/9
10
8/9
12
8/9
12
7
7
8
8
1
1
1
1
1N/2N
0.5N
U-Processor /
Y-Processor
(Dual Core)
LPDDR3
DDR3L/
DDR3L-RS
10/11
12
10/11
15
10/11
15
1N/2N
0.5N
LPDDR3
2.1.3
System Memory Organization Modes
The Integrated Memory Controller (IMC) supports two memory organization modes –
single-channel and dual-channel. Depending upon how the DIMM Modules are
populated in each memory channel, a number of different configurations can exist.
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
Dual-Channel Mode – Intel® Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into
symmetric and asymmetric zones. The symmetric zone starts at the lowest address in
each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note:
Channels A and B can be mapped for physical channel 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
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Processors—Interfaces
Figure 2.
Intel® Flex Memory Technology Operations
TOM
Non interleaved
C
access
B
C
Dual channel
interleaved access
B
B
B
CH A
CH B
CH A and CH B can be configured to be physical channels 0 or 1
B – The largest physical memory amount of the smaller size memory module
C – The remaining physical memory amount of the larger size memory module
Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request
can be sent before data from the first request has returned. If two consecutive cache
lines are requested, both may be retrieved simultaneously, since they are ensured to
be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A
and Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, the
IMC operates completely in Dual-Channel Symmetric mode.
Note:
The DRAM device technology and width may vary from one channel to the other.
2.1.4
System Memory Frequency
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports up to two DIMM connectors
per channel. If DIMMs with different latency are populated across the channels, the
BIOS will use the slower of the two latencies for both channels. For dual-channel mode
both channels must have a DIMM connector populated. For single-channel mode, only
a single channel can have a DIMM connector populated.
2.1.5
Intel® Fast Memory Access (Intel® FMA) Technology
Enhancements
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
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Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, the requests can be started
without interfering with the current request allowing for concurrent issuing of
requests. This allows for optimized bandwidth and reduced latency while maintaining
appropriate command spacing to meet system memory protocol.
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Pre-charge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back-to-back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the
IMC to further reduce latency and increase bandwidth efficiency.
2.1.6
Data Scrambling
The system memory controller incorporates a Data Scrambling feature to minimize the
impact of excessive di/dt on the platform system memory VRs due to successive 1s
and 0s on the data bus. Past experience has demonstrated that traffic on the data bus
is not random and can have energy concentrated at specific spectral harmonics
creating high di/dt, which is generally limited by data patterns that excite resonance
between the package inductance and on die capacitances. As a result, the system
memory controller uses a data scrambling feature to create pseudo-random patterns
on the system memory data bus to reduce the impact of any excessive di/dt.
2.1.7
2.1.8
DRAM Clock Generation
Every supported DIMM has two differential clock pairs. There are a total of four clock
pairs driven directly by the processor to two DIMMs.
DRAM Reference Voltage Generation
The memory controller has the capability of generating the DDR3L/DDR3L-RS
Reference Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ)
operations. The generated VREF can be changed in small steps, and an optimum VREF
value is determined for both during a cold boot through advanced DDR3L/DDR3L-RS
training procedures to provide the best voltage and signal margins.
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2.2
Processor Graphics
The processor graphics contains a generation 7.5 graphics core architecture. This
enables substantial gains in performance and lower power consumption over previous
generations. Up to 40 Execution Units are supported depending on the processor SKU.
•
Next Generation Intel Clear Video Technology HD Support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience
— Encode / transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray* disc S3D content using HDMI (1.4a specification
compliant with 3D)
•
DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
•
•
•
•
Advanced Scheduler 2.0, 1.0, XPDM support
Windows* 8, Windows* 7, OSX, Linux* operating system support
DirectX* 11.1, DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support.
OpenGL* 4.0, support
2.3
Processor Graphics Controller (GT)
The New Graphics Engine Architecture includes 3D compute elements, Multi-format
HW assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high
definition playback, video quality, and improved 3D performance and media.
The Display Engine handles delivering the pixels to the screen. GSA (Graphics in
System Agent) is the primary channel interface for display memory accesses and
“PCI-like” traffic in and out.
2.3.1
3D and Video Engines for Graphics Processing
The Gen 7.5 3D engine provides the following performance and power-management
enhancements.
3D Pipeline
The 3D graphics pipeline architecture simultaneously operates on different primitives
or on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine.
3D Engine Execution Units
•
•
Supports up to 40 EUs. The EUs perform 128-bit wide execution per clock.
Support SIMD8 instructions for vertex processing and SIMD16 instructions for
pixel processing.
Note:
See Figure 3 on page 25
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Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been
included to better support legacy D3D APIs as well as SGI OpenGL*.
Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from
the VF unit, in the order received.
Geometry Shader (GS) Stage
The GS stage receives inputs from the VS stage. Compiled application-provided GS
programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.
Clip Stage
The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of
incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.
Strips and Fans (SF) Stage
The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to
some extent.
Windower / IZ (WIZ) Stage
The WIZ unit performs an early depth test, which removes failing pixels and
eliminates unnecessary processing overhead.
The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels. The Windower is also capable of performing dithering, whereby the illusion of a
higher resolution when using low-bpp channels in color buffers is possible. Color
dithering diffuses the sharp color bands seen on smooth-shaded objects.
Video Engine
The Video Engine handles the non-3D (media/video) applications. It includes support
for VLD and MPEG2 decode in hardware.
2D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set
of 2D instructions. To take advantage of the 3D during engine’s functionality, some
BLT functions make use of the 3D renderer.
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Logical 128-Bit Fixed BLT and 256 Fill Engine
This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The
128-bit BLT engine provides hardware acceleration of block transfers of pixel data for
many common Windows operations. The BLT engine can be used for the following:
•
•
•
Move rectangular blocks of data between memory locations
Data alignment
To perform logical operations (raster ops)
The rectangular block of data does not change, as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per
pixel.
The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits.
BLTs can be either opaque or transparent. Opaque transfers move the data specified
to the destination. Transparent transfers compare destination color to source color and
write according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the BLT engine specifies which area in
memory to begin the BLT transfer. Hardware is included for all 256 raster operations
(source, pattern, and destination) defined by Microsoft*, including transparent BLT.
The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting
software to set up instruction buffers and use batch processing. The BLT engine can
perform hardware clipping during BLTs.
2.4
Digital Display Interface (DDI)
•
The processor supports:
— Two Digital Display (x4 DDI) interfaces that can be configured as DisplayPort*,
HDMI*. The DisplayPort* can be configured to use 1, 2, or 4 lanes depending
on the bandwidth requirements and link data rate of RBR (1.62 GT/s), HBR
(2.97 GT/s), and HBR2 (5.4 GT/s). When configured as HDMI*, the DDIx4
port can support 2.97 GT/s.
— One dedicated x4 embedded DisplayPort* (eDP*). Built-in displays are only
supported on eDP.
•
The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. The
DisplayPort* interface supports the VESA DisplayPort* Standard Version 1,
Revision 2.
•
•
The processor supports High-bandwidth Digital Content Protection (HDCP) for
high-definition content playback over digital interfaces.
The processor also integrates dedicated a Mini HD audio controller to drive audio
on integrated digital display interfaces, such as HDMI* and DisplayPort*. The HD
audio controller on the PCH would continue to support down CODECs, and so on.
The processor Mini HD audio controller supports two High-Definition Audio streams
simultaneously on any of the three digital ports.
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Interfaces—Processors
•
The processor supports streaming any 3 independent and simultaneous display
combination of DisplayPort*/HDMI*/eDP*/ monitors. In the case of 3
simultaneous displays, two High Definition Audio streams over the digital display
interfaces are supported.
•
•
Each digital port is capable of driving resolutions up to 3200x2000 at 60 Hz
through DisplayPort* and 4096x2304 at 24 Hz using HDMI*.
DisplayPort* Aux CH, DDC channel, Panel power sequencing, and HPD are
supported through the PCH.
Figure 3.
Processor Display Architecture
DP
Aux
Transcoder eDP*
DP encoder
eDP* Mux
X4 eDP
Timing, VDIP
DPT, SRID
eDP
Display
Pipe A
Transcoder A
DP / HDMI
Timing, VDIP
X4 DP /
HDMI
Transcoder B
DP / HDMI
Timing, VDIP
Display
Pipe B
X4 DP /
HDMI
Transcoder C
DP / HDMI
Timing, VDIP
Display
Pipe C
HD Audio
Controller
Audio
Codec
Display is the presentation stage of graphics. This involves:
•
•
•
•
•
•
•
Pulling rendered data from memory
Converting raw data into pixels
Blending surfaces into a frame
Organizing pixels into frames
Optionally scaling the image to the desired size
Re-timing data for the intended target
Formatting data according to the port output standard
DisplayPort*
DisplayPort* is a digital communication interface that uses differential signaling to
achieve a high-bandwidth bus interface designed to support connections between PCs
and monitors, projectors, and TV displays.
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A DisplayPort* consists of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal.
The Main Link is a unidirectional, high-bandwidth, and low latency channel used for
transport of isochronous data streams such as uncompressed video and audio. The
Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link
management and device control. The Hot-Plug Detect (HPD) signal serves as an
interrupt request for the sink device.
The processor is designed in accordance with the VESA DisplayPort* Standard Version
1.2a. The processor supports VESA DisplayPort* PHY Compliance Test Specification
1.2a and VESA DisplayPort* Link Layer Compliance Test Specification 1.2a.
Figure 4.
DisplayPort* Overview
Source Device
DisplayPort Tx
Sink Device
DisplayPort Rx
Main Link
(Isochronous Streams)
AUX CH
(Link/Device Managemet)
Hot-Plug Detect
(Interrupt Request)
High-Definition Multimedia Interface (HDMI*)
The High-Definition Multimedia Interface* (HDMI*) is provided for transmitting
uncompressed digital audio and video signals from DVD players, set-top boxes, and
other audiovisual sources to television sets, projectors, and other video displays. It
can carry high quality multi-channel audio data and all standard and high-definition
consumer electronics video formats. The HDMI display interface connecting the
processor and display devices uses transition minimized differential signaling (TMDS)
to carry audiovisual information through the same HDMI cable.
HDMI includes three separate communications channels — TMDS, DDC, and the
optional CEC (consumer electronics control). CEC is not supported on the processor.
As shown in the following figure, the HDMI cable carries four differential pairs that
make up the TMDS data and clock channels. These channels are used to carry video,
audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by
an HDMI Source to determine the capabilities and characteristics of the Sink.
Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS
data channels. The video pixel clock is transmitted on the TMDS clock channel and is
used by the receiver for data recovery on the three data channels. The digital display
data signals driven natively through the PCH are AC coupled and needs level shifting
to convert the AC coupled signals to the HDMI compliant digital signals.
The processor HDMI interface is designed in accordance with the High-Definition
Multimedia Interface with 3D, 4K, Deep Color, and x.v.Color.
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Figure 5.
HDMI* Overview
HDMI Sink
HDMI Source
HDMI Tx
HDMI Rx
TMDS Data Channel 0
l 1
TMDS Data Channe
TMDS Data Channel 2
TMDS Clock Channel
Hot-Plug Detect
Display Data Channel (DDC)
CEC Line (optional)
embedded DisplayPort*
embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard
oriented towards applications such as notebook and All-In-One PCs. Like DisplayPort,
embedded DisplayPort also consists of a Main Link, Auxiliary channel, and an optional
Hot-Plug Detect signal.
Integrated Audio
•
•
HDMI and display port interfaces carry audio along with video.
Processor supports two DMA controllers to output two High Definition audio
streams on two digital ports simultaneously.
•
Supports only the internal HDMI and DP CODECs.
Table 8.
Processor Supported Audio Formats over HDMI*and DisplayPort*
Audio Formats
HDMI*
Yes
DisplayPort*
AC-3 Dolby* Digital
Dolby Digital Plus
DTS-HD*
Yes
Yes
Yes
Yes
Yes
Yes
LPCM, 192 kHz/24 bit, 8 Channel
Yes
Dolby TrueHD, DTS-HD Master Audio*
(Lossless Blu-Ray Disc* Audio Format)
Yes
Yes
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The processor will continue to support Silent stream. Silent stream is an integrated
audio feature that enables short audio streams, such as system events to be heard
over the HDMI and DisplayPort monitors. The processor supports silent streams over
the HDMI and DisplayPort interfaces at 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz sampling rates.
Multiple Display Configurations
The following multiple display configuration modes are supported (with appropriate
driver software):
•
Single Display is a mode with one display port activated to display the output to
one display device.
•
Intel Display Clone is a mode with up to three display ports activated to drive the
display content of same color depth setting but potentially different refresh rate
and resolution settings to all the active display devices connected.
•
Extended Desktop is a mode with up to three display ports activated to drive the
content with potentially different color depth, refresh rate, and resolution settings
on each of the active display devices connected.
The digital ports on the processor can be configured to support DisplayPort*/HDMI.
The following table shows examples of valid three display configurations through the
processor.
Table 9.
Multiple Display Configuration for U-Processor Line
Display 1
Display 2
Display 3
Maximum
Resolution Display
1
Maximum
Resolution
Display 2
Maximum
Resolution
Display 3
3200x2000 @
60 Hz
HDMI
DP
HDMI
DP
eDP
eDP
eDP
4096x2304 @ 24 Hz
3200x2000 @
60 Hz
3200x2000 @ 60 Hz
3200x2000 @
60 Hz
3200x2000 @
60 Hz
HDMI
DP
4096x2304 @ 24Hz
Note: DP and eDP resolutions in this table are supported for 4 lanes with link data rate HBR2 at 24 bits per
pixel (bpp) and single stream mode of operation.
Table 10.
Multiple Display Configuration for Y-Processor Line
Display 1
Display 2
Display 3
Maximum
Resolution Display
1
Maximum
Resolution
Display 2
Maximum
Resolution
Display 3
2880x1620 @
60 Hz
HDMI
DP
HDMI
DP
eDP
eDP
eDP
4096x2304 @ 24 Hz
2880x1620 @
60 Hz
2880x1620 @ 60 Hz
2880x1620 @
60 Hz
2880x1620 @
60 Hz
HDMI
DP
4096x2304 @ 24 Hz
Note: 1. DP and eDP resolutions in this table are supported for 4 lanes with link data rate HBR2 at 24 bits
per pixel (bpp) and single stream mode of operation.
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Table 11.
DisplayPort and embedded DisplayPort* Resolutions per Link Data Rate for
U-Processor Line
Link Data Rate
Lane Count
2
1
4
RBR
HBR
1064x600
1280x960
1920x1200
1400x1050
1920x1200
2880x1800
2240x1400
2880x1800
3200x2000
HBR2
Note: The above resolutions are valid at 60 Hz refresh rate and 24 bits per pixel (bpp).
Table 12.
DisplayPort and embedded DisplayPort* Resolutions per Link Data Rate for Y-
Processor Line
Link Data Rate
Lane Count
2
1
4
RBR
HBR
1064x600
1280x960
1400x1050
1920x1200
2240x1400
2880x1620 @ 60 Hz
Note: The above resolutions are valid at 60 Hz refresh rate and 24 bits per pixel (bpp).
High-bandwidth Digital Content Protection (HDCP)
HDCP is the technology for protecting high-definition content against unauthorized
copy or unreceptive between a source (computer, digital set top boxes, and so on)
and the sink (panels, monitor, and TVs). The processor supports HDCP 1.4 for content
protection over wired displays (HDMI*, and DisplayPort*).
The HDCP 1.4 keys are integrated into the processor and customers are not required
to physically configure or handle the keys.
2.5
Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and external components, like Super I/O (SIO) and Embedded
Controllers (EC), to provide processor temperature, Turbo, Configurable TDP, and
memory throttling control mechanisms and many other services. PECI is used for
platform thermal management and real time control and configuration of processor
features and performance.
2.5.1
PECI Bus Architecture
The PECI architecture is based on a wired-OR bus that the clients (as processor PECI)
can pull up high (with strong drive).
The idle state on the bus is near zero.
The following figure demonstrates PECI design and connectivity. While the host/
originator can be a third party PECI host, one of the PECI clients is a processor PECI
device.
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Figure 6.
PECI Host-Clients Connection Example
VTT
VTT
Q3
nX
Q1
nX
PECI
Q2
1X
CPECI
<10pF/Node
PECI Client
Host / Originator
Additional
PECI Clients
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3.0
Technologies
This chapter provides a high-level description of Intel technologies implemented in the
processor.
The implementation of the features may vary between the processor SKUs.
Details on the different technologies of Intel processors and other relevant external
notes are located at the Intel technology web site: http://www.intel.com/technology/
3.1
Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets.
Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel®
Architecture (Intel® VT-x) added hardware support in the processor to improve the
virtualization performance and robustness. Intel® Virtualization Technology for
Directed I/O (Intel VT-d) extends Intel® VT-x by adding hardware assisted support to
improve I/O device virtualization performance.
Intel® VT-x specifications and functional descriptions are included in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:
http://www.intel.com/products/processor/manuals/index.htm
The Intel VT-d specification and other Intel VT documents can be referenced at:
http://www.intel.com/technology/virtualization/index.htm
https://sharedspaces.intel.com/sites/PCDC/SitePages/Ingredients/ingredient.aspx?
ing=VT
Intel® VT-x Objectives
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual
Machine Monitor (VMM) can use Intel VT-x features to provide an improved reliable
virtualized platform. By using Intel VT-x, a VMM is:
•
Robust: VMMs no longer need to use paravirtualization or binary translation. This
means that off-the-shelf operating systems and applications can be run without
any special steps.
•
Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA
x86 processors.
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•
•
More reliable: Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
More secure: The use of hardware transitions in the VMM strengthens the
isolation of VMs and further prevents corruption of one VM from affecting others
on the same system.
Intel® VT-x Features
The processor supports the following Intel VT-x features:
•
•
•
Extended Page Table (EPT) Accessed and Dirty Bits
— EPT A/D bits enabled VMMs to efficiently implement memory management and
page classification algorithms to optimize VM memory operations, such as de-
fragmentation, paging, live migration, and check-pointing. Without hardware
support for EPT A/D bits, VMMs may need to emulate A/D bits by marking EPT
paging-structures as not-present or read-only, and incur the overhead of EPT
page-fault VM exits and associated software processing.
Extended Page Table Pointer (EPTP) switching
— EPTP switching is a specific VM function. EPTP switching allows guest software
(in VMX non-root operation, supported by EPT) to request a different EPT
paging-structure hierarchy. This is a feature by which software in VMX non-
root operation can request a change of EPTP without a VM exit. Software can
choose among a set of potential EPTP values determined in advance by
software in VMX root operation.
Pause loop exiting
— Support VMM schedulers seeking to determine when a virtual processor of a
multiprocessor virtual machine is not performing useful work. This situation
may occur when not all virtual processors of the virtual machine are currently
scheduled and when the virtual processor in question is in a loop involving the
PAUSE instruction. The new feature allows detection of such loops and is thus
called PAUSE-loop exiting.
The processor core supports the following Intel VT-x features:
•
Extended Page Tables (EPT)
— EPT is hardware assisted page table virtualization.
— It eliminates VM exits from the guest operating system to the VMM for shadow
page-table maintenance.
•
Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (such as
TLBs).
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
•
Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest operating system
after an amount of time specified by the VMM. The VMM sets a timer value
before entering a guest.
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
guarantees.
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•
Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest operating system
from an internal (malicious software based) attack by preventing relocation of
key system data structures like IDT (interrupt descriptor table), GDT (global
descriptor table), LDT (local descriptor table), and TSS (task segment
selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
Intel® VT-d Objectives
The key Intel VT-d objectives are domain-based isolation and hardware-based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Intel VT-d provides
accelerated I/O performance for a virtualized platform and provides software with the
following capabilities:
•
•
•
•
I/O device assignment and security: for flexibly assigning I/O devices to VMs and
extending the protection and isolation properties of VMs for I/O operations.
DMA remapping: for supporting independent address translations for Direct
Memory Accesses (DMA) from devices.
Interrupt remapping: for supporting isolation and routing of interrupts from
devices and external interrupt controllers to appropriate VMs.
Reliability: for recording and reporting to system software DMA and interrupt
errors that may otherwise corrupt memory or impact VM isolation.
Intel VT-d accomplishes address translation by associating a transaction from a given
I/O device to a translation table associated with the Guest to which the device is
assigned. It does this by means of the data structure in the following illustration. This
table creates an association between the device's PCI Express* Bus/Device/Function
(B/D/F) number and the base address of a translation table. This data structure is
populated by a VMM to map devices to translation tables in accordance with the device
assignment restrictions above, and to include a multi-level translation table (VT-d
Table) that contains Guest specific address translations.
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Figure 7.
Device to Domain Mapping Structures
(Dev 31, Func 7)
Context entry 255
(Dev 0, Func 1)
(Dev 0, Func 0)
Context entry 0
Context entry Table
For bus N
Address Translation
Structures for Domain A
(Bus 255)
(Bus N)
Root entry 255
Root entry N
(Bus 0)
Root entry 0
Root entry table
Context entry 255
Context entry 0
Address Translation
Structures for Domain B
Context entry Table
For bus 0
Intel VT-d functionality, often referred to as an Intel VT-d Engine, has typically been
implemented at or near a PCI Express host bridge component of a computer system.
This might be in a chipset component or in the PCI Express functionality of a processor
with integrated I/O. When one such Intel VT-d engine receives a PCI Express
transaction from a PCI Express bus, it uses the B/D/F number associated with the
transaction to search for an Intel VT-d translation table. In doing so, it uses the B/D/F
number to traverse the data structure shown in the above figure. If it finds a valid
Intel VT-d table in this data structure, it uses that table to translate the address
provided on the PCI Express bus. If it does not find a valid translation table for a given
translation, this results in an Intel VT-d fault. If Intel VT-d translation is required, the
Intel VT-d engine performs an N-level table walk.
For more information, refer to Intel® Virtualization Technology for Directed I/O
Architecture Specification http://download.intel.com/technology/computing/vptech/
Intel(r)_VT_for_Direct_IO.pdf
Intel® VT-d Features
The processor supports the following Intel VT-d features:
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•
•
Memory controller and processor graphics comply with the Intel VT-d 1.2
Specification
Two Intel VT-d DMA remap engines
— iGFX DMA remap engine
— Default DMA remap engine (covers all devices except iGFX)
Support for root entry, context entry, and default context
39-bit guest physical address and host physical address widths
Support for 4 KB page sizes
•
•
•
•
Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
•
•
•
•
Support for both leaf and non-leaf caching
Support for boot protection of default page table
Support for non-caching of invalid page table entries
Support for hardware-based flushing of translated but pending writes and pending
reads, on IOTLB invalidation
•
•
Support for Global, Domain specific, and Page specific IOTLB invalidation
MSI cycles (MemWr to address FEEx_xxxxh) not translated
— Translation faults result in cycle forwarding to VBIOS region (byte enables
masked for writes). Returned data may be bogus for internal agents; PEG/DMI
interfaces return unsupported request status
•
•
•
Interrupt remapping is supported
Queued invalidation is supported
Intel VT-d translation bypass address range is supported (Pass Through)
The processor supports the following added new Intel VT-d features:
•
•
4-level Intel VT-d Page walk: Both default Intel VT-d engine, as well as the IGD
Intel VT-d engine, are upgraded to support 4-level Intel VT-d tables (adjusted
guest address width 48 bits)
Intel VT-d superpage: support of Intel VT-d superpage (2 MB, 1 GB) for the
default Intel VT-d engine (that covers all devices except IGD)
IGD Intel VT-d engine does not support superpage and BIOS should disable
superpage in default Intel VT-d engine when iGFX is enabled.
Note:
Intel VT-d Technology may not be available on all SKUs.
3.2
Intel® Trusted Execution Technology (Intel® TXT)
Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements
that provide the building blocks for creating trusted platforms.
The Intel TXT platform helps to provide the authenticity of the controlling environment
such that those wishing to rely on the platform can make an appropriate trust
decision. The Intel TXT platform determines the identity of the controlling environment
by accurately measuring and verifying the controlling software.
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Another aspect of the trust decision is the ability of the platform to resist attempts to
change the controlling environment. The Intel TXT platform will resist attempts by
software processes to change the controlling environment or bypass the bounds set by
the controlling environment.
Intel TXT is a set of extensions designed to provide a measured and controlled launch
of system software that will then establish a protected environment for itself and any
additional software that it may execute.
These extensions enhance two areas:
•
•
The launching of the Measured Launched Environment (MLE).
The protection of the MLE from potential corruption.
The enhanced platform provides these launch and control interfaces using Safer Mode
Extensions (SMX).
The SMX interface includes the following functions:
•
•
Measured/Verified launch of the MLE.
Mechanisms to ensure the above measurement is protected and stored in a secure
location.
•
Protection mechanisms that allow the MLE to control attempts to modify itself.
The processor also offers additional enhancements to System Management Mode
(SMM) architecture for enhanced security and performance. The processor provides
new MSRs to:
•
•
•
•
•
•
Enable a second SMM range
Enable SMM code execution range checking
Select whether SMM Save State is to be written to legacy SMRAM or to MSRs
Determine if a thread is going to be delayed entering SMM
Determine if a thread is blocked from entering SMM
Targeted SMI, enable/disable threads from responding to SMIs both VLWs and IPI
For the above features, BIOS must test the associated capability bit before attempting
to access any of the above registers.
For more information, refer to the Intel® Trusted Execution Technology Measured
Launched Environment Programming Guide.
3.3
Intel® Hyper-Threading Technology (Intel® HT
Technology)
The processor supports Intel Hyper-Threading Technology (Intel HT Technology) that
allows an execution core to function as two logical processors. While some execution
resources, such as caches, execution units, and buses are shared, each logical
processor has its own architectural state with its own set of general-purpose registers
and control registers. This feature must be enabled using the BIOS and requires
operating system support.
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Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 and
Microsoft Windows* 7 and disabling Intel HT Technology using the BIOS for all
previous versions of Windows* operating systems. For more information on Intel HT
Technology, see http://www.intel.com/technology/platform-technology/hyper-
threading/.
3.4
Intel® Turbo Boost Technology 2.0
The Intel Turbo Boost Technology 2.0 allows the processor core to opportunistically
and automatically run faster than its rated operating frequency/render clock, if it is
operating below power, temperature, and current limits. The Intel Turbo Boost
Technology 2.0 feature is designed to increase performance of both multi-threaded
and single-threaded workloads.
Compared with previous generation products, Intel Turbo Boost Technology 2.0 will
increase the ratio of application power to TDP. Thus, thermal solutions and platform
cooling that are designed to less than thermal design guidance might experience
thermal and performance issues since more applications will tend to run at the
maximum power limit for significant periods of time.
Note:
Intel Turbo Boost Technology 2.0 may not be available on all SKUs.
Intel® Turbo Boost Technology 2.0 Frequency
To determine the highest performance frequency amongst active cores, the processor
takes the following into consideration:
•
•
•
•
The number of cores operating in the C0 state.
The estimated core current consumption.
The estimated package prior and present power consumption.
The package temperature.
Any of these factors can affect the maximum frequency for a given workload. If the
power, current, or thermal limit is reached, the processor will automatically reduce the
frequency to stay within its TDP limit. Turbo processor frequencies are only active if
the operating system is requesting the P0 state. For more information on P-states and
C-states, see Power Management on page 42.
3.5
Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
Intel Advanced Vector Extensions 2.0 (Intel AVX2) is the latest expansion of the Intel
instruction set. Intel AVX2 extends the Intel Advanced Vector Extensions (Intel AVX)
with 256-bit integer instructions, floating-point fused multiply add (FMA) instructions,
and gather operations. The 256-bit integer vectors benefit math, codec, image, and
digital signal processing software. FMA improves performance in face detection,
professional imaging, and high performance computing. Gather operations increase
vectorization opportunities for many applications. In addition to the vector extensions,
this generation of Intel processors adds new bit manipulation instructions useful in
compression, encryption, and general purpose software.
For more information on Intel AVX, see http://www.intel.com/software/avx
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3.6
Intel® Advanced Encryption Standard New Instructions
(Intel® AES-NI)
The processor supports Intel Advanced Encryption Standard New Instructions (Intel
AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that
enable fast and secure data encryption and decryption based on the Advanced
Encryption Standard (AES). Intel AES-NI are valuable for a wide range of
cryptographic applications, such as applications that perform bulk encryption/
decryption, authentication, random number generation, and authenticated encryption.
AES is broadly accepted as the standard for both government and industry
applications, and is widely deployed in various protocols.
Intel AES-NI consists of six Intel SSE instructions. Four instructions, AESENC,
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption
and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for
supporting AES; offering security, high performance, and a great deal of flexibility.
PCLMULQDQ Instruction
The processor supports the carry-less multiplication instruction, PCLMULQDQ.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
Intel® Secure Key
The processor supports Intel® Secure Key (formerly known as Digital Random Number
Generator (DRNG)), a software visible random number generation mechanism
supported by a high quality entropy source. This capability is available to
programmers through the RDRAND instruction. The resultant random number
generation capability is designed to comply with existing industry standards in this
regard (ANSI X9.82 and NIST SP 800-90).
Some possible usages of the RDRAND instruction include cryptographic key generation
as used in a variety of applications, including communication, digital signatures,
secure storage, and so on.
3.7
Intel® 64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides key
mechanisms for interrupt delivery. This extension is primarily intended to increase
processor addressability.
Specifically, x2APIC:
•
Retains all key elements of compatibility to the xAPIC architecture:
— Delivery modes
— Interrupt and processor priorities
— Interrupt sources
— Interrupt destination types
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•
Provides extensions to scale processor addressability for both the logical and
physical destination modes
•
•
Adds new features to enhance performance of interrupt delivery
Reduces complexity of logical destination mode interrupt delivery on link based
architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
•
Support for two modes of operation to provide backward compatibility and
extensibility for future platform innovations:
— In xAPIC compatibility mode, APIC registers are accessed through memory
mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
— In x2APIC mode, APIC registers are accessed through Model Specific Register
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly
increased processor addressability and some enhancements on interrupt
delivery.
•
Increased range of processor addressability in x2APIC mode:
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt
processor addressability up to 4G–1 processors in physical destination mode.
A processor implementation of x2APIC architecture can support fewer than 32-
bits in a software transparent fashion.
— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical
x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit
logical ID within the cluster. Consequently, ((2^20) – 16) processors can be
addressed in logical destination mode. Processor implementations can support
fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a
software agnostic fashion.
•
•
More efficient MSR interface to access APIC registers:
— To enhance inter-processor and self-directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR-based interfaces in x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in x2APIC mode.
The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically,
the software semantics for using the Interrupt Command Register (ICR) and End
Of Interrupt (EOI) registers have been modified to allow for more efficient delivery
and dispatching of interrupts.
•
•
The x2APIC extensions are made available to system software by enabling the
local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a
new operating system and a new BIOS are both needed, with special support for
x2APIC mode.
The x2APIC architecture provides backward compatibility to the xAPIC architecture
and forward extendible for future Intel platform innovations.
Note:
Intel x2APIC Technology may not be available on all SKUs.
For more information, see the Intel® 64 Architecture x2APIC Specification at http://
www.intel.com/products/processor/manuals/.
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Processors—Technologies
3.8
Power Aware Interrupt Routing (PAIR)
The processor includes enhanced power-performance technology that routes
interrupts to threads or cores based on their sleep states. As an example, for energy
savings, it routes the interrupt to the active cores without waking the deep idle cores.
For performance, it routes the interrupt to the idle (C1) cores without interrupting the
already heavily loaded cores. This enhancement is mostly beneficial for high-interrupt
scenarios like Gigabit LAN, WLAN peripherals, and so on.
3.9
Execute Disable Bit
The Execute Disable Bit allows memory to be marked as executable when combined
with a supporting operating system. If code attempts to run in non-executable
memory, the processor raises an error to the operating system. This feature can
prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the Intel® 64 and
IA-32 Architectures Software Developer's Manuals for more detailed information.
3.10
Intel® Boot Guard
Intel® Boot Guard can help protect the platform boot integrity by preventing execution
of unauthorized boot blocks. With Intel® Boot Guard, platform manufacturers can
create boot policies such that invocation of an unauthorized (or untrusted) boot block
will trigger the platform protection per the manufacturer's defined policy.
With verification based in the hardware, Intel® Boot Guard extends the trust boundary
of the platform boot process down to the hardware level.
Intel® Boot Guard accomplishes this by:
•
Providing hardware-based Static Root of Trust for Measurement (S-RTM) and the
Root of Trust for Verification (RTV) using Intel architectural components.
•
•
Providing architectural definition for platform manufacturer Boot Policy.
Enforcing manufacture provided Boot Policy using Intel architectural components.
Benefits of this protection is that Intel® Boot Guard can help maintain platform
integrity by preventing re-purposing of the manufacturer’s hardware to run an
unauthorized software stack.
Note:
Intel® Boot Guard technology availability may vary between the different SKUs.
3.11
Supervisor Mode Execution Protection (SMEP)
The processor introduces a new mechanism that provides the next level of system
protection by blocking malicious software attacks from user mode code when the
system is running in the highest privilege level. This technology helps to protect from
virus attacks and unwanted code from harming the system. For more information,
refer to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A
at: http://www.intel.com/Assets/PDF/manual/253668.pdf
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3.12
Intel® Transactional Synchronization Extensions - New
Instructions (Intel® TSX-NI)
New on the processor are the Intel Transactional Synchronization Extensions - New
Instructions (Intel TSX-NI). Intel TSX-NI provides a set of instruction extensions that
allow programmers to specify regions of code for transactional synchronization.
Programmers can use these extensions to achieve the performance of fine-grain
locking while actually programming using coarse-grain locks. Details on Intel TSX-NI
are in the Intel® Architecture Instruction Set Extensions Programming Reference.
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Processors—Power Management
4.0
Power Management
This chapter provides information on the following power management topics:
•
•
•
•
Advanced Configuration and Power Interface (ACPI) States
Processor Core
Integrated Memory Controller (IMC)
Processor Graphics Controller
Figure 8.
Processor Power States
G0 – Working
S0 – Processor powered on (full on mode / connected standby mode)
C0 – Active mode
P0
Pn
C1 – Auto halt
C1E – Auto halt, low freq, low voltage
C3 – L1/L2 caches flush, clocks off
C6 – save core states before shutdown and PLL off
C7 – C6 + L3 cache flush
C8 – C7 internal voltage removal from all power domains
C9 – C8+VCC input to 0V
C10 – C9+VR12.6 shut off or PS4
G1 – Sleeping
S3 cold – Sleep – Suspend To Ram (STR)
S4 – Hibernate – Suspend To Disk (STD), Wakeup on PCH
G2 – Soft Off
S5 – Soft Off – no power,Wakeup on PCH
G3 – Mechanical Off
* Note: Power states availability may vary between the different SKUs
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Figure 9.
Processor Package and Core C-States
CORE STATE
C0 C1 C1E C3 C6 C7 C8 C9 C10
One or more cores or GT executing instructions
C0
C3
C6
C7
C8
C9
C10
All cores and GT in C3 or deeper, L3 may be flushed and turned off, memory in self refresh, some Uncore
clocks stopped, some Uncore voltages reduced
All cores and GT in C6 or deeper, L3 may be flushed and turned off, memory in self refresh, all Uncore
clocks stopped, some Uncore voltages reduced
Package C6 + L3 flushed and turned off, additional Uncore voltages reduced
Package C7 + most Uncore voltages reduced to 0V
Package C8 + VR12.6 in low power state
Package C9 + VR12.6 turned off
Core behaves the same as Core C6 state
All core clocks are stopped, core state saved and voltage reduce to 0V
Cores flush L1/L2 into L3, all core clocks are stopped
Core halted, most core clocks stopped and voltage reduced to Pn
Core halted, most core clocks stopped
Core is executing code
Possible combination of core/package states
Impossible combination of core/package states
Note: The “core state” relates to the core which is in the HIGHEST power state in the package (most active)
4.1
Advanced Configuration and Power Interface (ACPI)
States Supported
This section describes the ACPI states supported by the processor.
Table 13.
System States
State
G0/S0
G0/S0
Description
Full On Mode, Display On.
Connected Standby Mode, Display Off.
Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the
processor).
G1/S3-Cold
G1/S4
G2/S5
G3
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
Soft off. All power lost (except wakeup on PCH). Total reboot.
Mechanical off. All power removed from system.
Table 14.
Processor Core / Package State Support
State
Description
Active mode, processor executing code.
C0
C1
AutoHALT state.
C1E
AutoHALT state with lowest frequency and voltage operating point.
Execution cores in C3 state flush their L1 instruction cache, L1 data cache, and L2 cache
to the L3 shared cache. Clocks are shut off to each core.
C3
C6
Execution cores in this state save their architectural state before removing core voltage.
continued...
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State
Description
Execution cores in this state behave similarly to the C6 state. If all execution cores
request C7 state, L3 cache ways are flushed until it is cleared. If the entire L3 cache is
flushed, voltage will be removed from the L3 cache. Power removal to SA, Cores and L3
will reduce power consumption.
C7
C7 state plus voltage is removed from all power domains after required state is saved. PLL
is powered down.
C8
C9
C8 state plus processor VCC input voltage at 0 V.
C10
C9 state plus VR12.6 is set to low-power state, near shut off.
Table 15.
Integrated Memory Controller States
State
Description
Power up
CKE asserted. Active mode.
Pre-charge
Power-down
CKE de-asserted (not self-refresh) with all banks closed.
CKE de-asserted (not self-refresh) with minimum one bank active.
CKE de-asserted using device self-refresh.
Active Power-
down
Self-Refresh
Table 16.
G, S, and C Interface State Combinations
Global
(G)
State
Sleep (S)
State
Processor
Package (C)
State
Processor
State
System Clocks
Description
G0
G0
G0
S0
S0
S0
C0
C1/C1E
C3
Full On
Auto-Halt
Deep Sleep
On
On
On
Full On
Auto-Halt
Deep Sleep
Deep Power-
down
G0
G0
S0
S0
C6/C7
On
On
Deep Power-down
Deeper Power-
down
C8/C9/C10
G1
G1
G2
G3
S3
S4
S5
NA
Power off
Power off
Power off
Power off
Off, except RTC
Off, except RTC
Off, except RTC
Power off
Suspend to RAM
Suspend to Disk
Soft Off
Hard off
4.2
Processor Core Power Management
While executing code, Enhanced Intel SpeedStep® Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and
voltage operating point is defined by ACPI as a P-state. When the processor is not
executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In
general, deeper power C-states have longer entry and exit latencies.
4.2.1
Enhanced Intel® SpeedStep® Technology Key Features
The following are the key features of Enhanced Intel SpeedStep Technology:
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•
•
Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— Once the voltage is established, the PLL locks on to the target frequency.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested among all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
•
•
The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
4.2.2
Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However,
higher C-states have longer exit and entry latencies. Resolution of C-states occur at
the thread, processor core, and processor package level. Thread-level C-states are
available if Intel Hyper-Threading Technology is enabled.
Caution:
Long term reliability cannot be assured unless all the Low-Power Idle States are
enabled.
Figure 10.
Idle Power Management Breakdown of the Processor Cores
Thread 0
Thread 1
Thread 0
Thread 1
Core 0 State
Core N State
Processor Package State
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While individual threads can request low-power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
4.2.3
Requesting Low-Power Idle States
The primary software interfaces for requesting low-power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions using I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result
in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality.
Any P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx)
like request. The reads fall through like a normal I/O instruction.
Note:
When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The
MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx
I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a
wakeup on an interrupt, even if interrupts are masked by EFLAGS.IF.
4.2.4
Core C-State Rules
The following are general rules for all core C-states, unless specified otherwise:
•
A core C-state is determined by the lowest numerical thread state (such as Thread
0 requests C1E state while Thread 1 requests C3 state, resulting in a core C1E
state). See the G, S, and C Interface State Combinations table.
•
A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered using an
MWAIT/Timed MWAIT instruction
— The deadline corresponding to the Timed MWAIT instruction expires
An interrupt directed toward a single thread wakes only that thread.
•
•
If any thread in a core is in active (in C0 state), the core's C-state will resolve to
C0 state.
•
•
Any interrupt coming into the processor package may wake any core.
A system reset re-initializes all processor cores.
Core C0 State
The normal operating state of a core where code is being executed.
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Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software
Developer’s Manual for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E state, see Package C-States on page 48.
Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because
the core’s caches are flushed, the processor does not wake any core that is in the C3
state when either a snoop is detected or when another core accesses cacheable
memory.
Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or
an MWAIT(C6) instruction. Before entering core C6 state, the core will save its
architectural state to a dedicated SRAM. Once complete, a core will have its voltage
reduced to zero volts. During exit, the core is powered on and its architectural state is
restored.
Core C7-C10 States
Individual threads of a core can enter the C7, C8, C9, or C10 state by initiating a
P_LVL4, P_LVL5, P_LVL6, P_LVL7 I/O read (respectively) to the P_BLK or by an
MWAIT(C7/C8/C9/C10) instruction. The core C7–C10 state exhibits the same behavior
as the core C6 state.
C-State Auto-Demotion
In general, deeper C-states, such as C6 or C7 state, have long latencies and have
higher energy entry/exit costs. The resulting performance and energy penalties
become significant when the entry/exit frequency of a deeper C-state is high.
Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on
battery life and idle power. To increase residency and improve battery life and idle
power in deeper C-states, the processor supports C-state auto-demotion.
There are two C-state auto-demotion options:
•
•
C7/C6 to C3 state
C7/C6/C3 To C1 state
The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 state is based on
each core’s immediate residency history and interrupt rate . If the interrupt rate
experienced on a core is high and the residence in a deep C-state between such
interrupts is low, the core can be demoted to a C3 or C1 state. A higher interrupt
pattern is required to demote a core to C1 state as compared to C3 state.
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This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
4.2.5
Package C-States
The processor supports C0, C1/C1E, C3, C6, C7, C8, C9, and C10 power states.The
following is a summary of the general rules for package C-state entry. These apply to
all package C-states, unless specified otherwise:
•
A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
•
A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
— For package C-states, the processor is not required to enter C0 state before
entering any other C-state.
— Entry into a package C-state may be subject to auto-demotion – that is, the
processor may keep the package in a deeper package C-state than requested
by the operating system if the processor determines, using heuristics, that the
deeper C-state results in better power/performance.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
•
If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0 state.
— If the break event is masked, the processor attempts to re-enter its previous
package state.
•
If the break event was due to a memory access or snoop request,
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or
snoop request is serviced and the package remains in the higher power C-
state.
The following table shows package C-state resolution for a dual-core processor. The
following figure summarizes package C-state transitions.
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Table 17.
Coordination of Core Power States at the Package Level
Package C-State
Core 1
C7
C0
C0
C0
C0
C0
C0
C0
C0
C0
C1
C0
C3
C0
C11
C3
C3
C3
C3
C3
C3
C6
C0
C11
C3
C6
C6
C6
C6
C6
C8
C0
C11
C3
C6
C7
C8
C8
C8
C9
C0
C11
C3
C6
C7
C8
C9
C9
C10
C0
C0
C1
C3
C0
C11
C3
C6
C7
C7
C7
C7
C11
C11
C11
C11
C11
C11
C11
C11
C3
C6
Core 0
C6
C7
C7
C8
C9
C8
C9
C10
C10
Note: 1. If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.
Figure 11.
Package C-State Entry and Exit
Package C0
Package C1/C1E
Package C3
Package C6
Package C7
Package C8
Package C9
Package C10
Package C0 State
This is the normal operating state for the processor. The processor remains in the
normal state when at least one of its cores is in the C0 or C1 state or when the
platform has not granted permission to the processor to go into a low-power state.
Individual cores may be in lower power idle states while the package is in C0 state.
Package C1/C1E State
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low-power state when:
•
•
At least one core is in the C1 state.
The other cores are in a C1 or deeper power state.
The package enters the C1E state when:
All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
•
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•
•
All cores are in a power state deeper than C1/C1E state; however, the package
low-power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.
All cores have requested C1 state using HLT or MWAIT(C1) and C1E auto-
promotion is enabled in IA32_MISC_ENABLES.
No notification to the system occurs upon entry to C1/C1E state.
Package C2 State
Package C2 state is an internal processor state that cannot be explicitly requested by
software. A processor enters Package C2 state when:
•
All cores and graphics have requested a C3 or deeper power state; however,
constraints (LTR, programmed timer events in the near future, and so on) prevent
entry to any state deeper than C 2 state. Or,
•
All cores and graphics are in the C3 or deeper power states, and a memory access
request is received. Upon completion of all outstanding memory requests, the
processor transitions back into a deeper package C-state.
Package C3 State
A processor enters the package C3 low-power state when:
•
•
At least one core is in the C3 state.
The other cores are in a C3 state or deeper power state and the processor has
been granted permission by the platform.
•
The platform has not granted a request to a package C6/C7 or deeper state,
however, has allowed a package C6 state.
In package C3 state, the L3 shared cache is valid.
Package C6 State
A processor enters the package C6 low-power state when:
•
•
At least one core is in the C6 state.
The other cores are in a C6 or deeper power state and the processor has been
granted permission by the platform.
•
•
The platform has not granted a package C7 state or deeper request; however, has
allowed a package C6 state.
If the cores are requesting C7 state, but the platform is limiting to a package C6
state, the last level cache in this case can be flushed.
In package C6 state all cores have saved their architectural state and have had their
core voltages reduced to zero volts. It is possible the L3 shared cache is flushed and
turned off in package C6 state. If at least one core is requesting C6 state, the L3
cache will not be flushed.
Package C7 State
The processor enters the package C7 low-power state when all cores are in the C7
state. In package C7, the processor will take action to remove power from portions of
the system agent.
Core break events are handled the same way as in package C3 or C6 state.
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Package C8 State
The processor enters C8 states when the core with the highest state is C8.
The package C8 state is similar to package C7 state; however, in addition, all
internally generated voltage rails are turned off and the input VCC is reduced to 1.15 V
to 1.3 V.
Package C9 State
The processor enters package C9 states when the core with the highest state is C9.
The package C9 state is similar to package C8 state; in addition, the input VCC is
changed to 0 V.
Package C10 State
The processor enters C10 states when the core with the highest state is C10.
The package C10 state is similar to the package C9 state; in addition, the VR12.6 is in
PS4 low-power state, which is near to shut off of the VR12.6.
Dynamic L3 Cache Sizing
When all cores request C7 or deeper C-state, internal heuristics is dynamically flushes
the L3 cache. Once the cores enter a deep C-state, depending on their MWAIT
substate request, the L3 cache is either gradually flushed N-ways at a time or flushed
all at once. Upon the cores exiting to C0, the L3 cache is gradually expanded based on
internal heuristics.
4.2.6
Package C-States and Display Resolutions
The integrated graphics engine has the frame buffer located in system memory. When
the display is updated, the graphics engine fetches display data from system memory.
Different screen resolutions and refresh rates have different memory latency
requirements. These requirements may limit the deepest Package C-state the
processor can enter. Other elements that may affect the deepest Package C-state
available are the following:
•
•
•
•
Display is on or off
Single or multiple displays
Native or non-native resolution
Panel Self Refresh (PSR) technology
Note:
Display resolution is not the only factor influencing the deepest Package C-state the
processor can get into. Device latencies, interrupt response latencies, and core C-
states are among other factors that influence the final package C-state the processor
can enter.
The following table lists display resolutions and deepest available package C-State.
The display resolutions are examples using common values for blanking and pixel
rate. Actual results will vary. The table shows the deepest possible Package C-state.
System workload, system idle, and AC or DC power also affect the deepest possible
Package C-state.
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Table 18.
Deepest Package C-State Available – U-Processor Line and Y-Processor Line
Panel Self Refresh
(PSR)
Number of Displays 1
Native Resolution 2
Deepest Available
Package C-State
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Single
Single
800x600 60 Hz
1024x768 60 Hz
1280x1024 60 Hz
1920x1080 60 Hz
1920x1200 60 Hz
1920x1440 60 Hz
2048x1536 60 Hz
2560x1600 60 Hz
2560x1920 60 Hz
2880x1620 60 Hz
2880x1800 60 Hz 3
3200x1800 60 Hz 3
3200x2000 60 Hz 3
3840x2160 30 Hz
4096x2160 24 Hz
800x600 60 Hz
PC7
PC7
PC7
PC7
PC7
PC6
PC6
PC6
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC7
PC6
PC6
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC2
PC2
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
Multiple
1024x768 60 Hz
1280x1024 60 Hz
1920x1080 60 Hz
1920x1200 60 Hz
1920x1440 60 Hz
2048x1536 60 Hz
2560x1600 60 Hz
2560x1920 60 Hz
2880x1620 60 Hz
2880x1800 60 Hz 3
3200x1800 60 Hz 3
3200x2000 60 Hz 3
3840x2160 30 Hz
4096x2160 24 Hz
PC2
continued...
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Panel Self Refresh
Number of Displays 1
Single
Native Resolution 2
Any native resolution 4
Any native resolution 1
Deepest Available
Package C-State
(PSR)
Enabled
PC7
Same as PSR disabled for
the given resolution with
multiple displays
Enabled
Multiple
Notes: 1. For multiple display cases, the resolution listed is the highest native resolution of all enabled
displays, and PSR is internally disabled; that is, dual display with one 800x600 60 Hz display and
one 2560x1600 60 Hz display will result in a deepest available package C-state of PC2.
2. For non-native resolutions, PSR is internally disabled, and the deepest available package C-State
will be between that of the PSR disabled native resolution and the PSR disabled non-native
resolution.; that is, a native 3200x1800 60 Hz panel using non-native 1920x1080 60 Hz
resolution will result in a deepest available package C-State between PC2 and PC7.
3. Resolution not supported by Y-Processor line.
4. Microcode Update rev 00000010 or newer must be used.
4.3
Integrated Memory Controller (IMC) Power Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
4.3.1
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory in which it is not
connected to any actual memory devices is tri-stated. The benefits of disabling unused
SM signals are:
•
•
Reduced power consumption.
Reduced possible overshoot/undershoot signal quality issues seen by the
processor I/O buffer receivers caused by reflections from potentially un-
terminated transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be determined that
the rows are not populated. This is due to the fact that when CKE is tri-stated with
DRAMs present, the DRAMs are not ensured to maintain data integrity. CKE tri-state
should be enabled by BIOS where appropriate, since at reset all rows must be
assumed to be populated.
CKE tristate should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
4.3.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the memory
interface.The processor drives four CKE pins, one per rank.
The CKE is one of the power-save means. When CKE is off, the internal DDR clock is
disabled and the DDR power is reduced. The power-saving differs according to the
selected mode and the DDR type used. For more information, refer to the IDD table in
the DDR specification.
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The processor supports four different types of power-down modes in package C0. The
different power-down modes can be enabled through configuring
"PM_PDWN_config_0_0_0_MCHBAR". The type of CKE power-down can be configured
through PDWN_mode (bits 15:12) and the idle timer can be configured through
PDWN_idle_counter (bits 11:0). The different power-down modes supported are:
•
•
No power-down (CKE disable)
Active power-down (APD): This mode is entered if there are open pages when
de-asserting CKE. In this mode the open pages are retained. Power-saving in this
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this
mode is defined by tXP – small number of cycles. For this mode, DRAM DLL must
be on.
•
•
PPD/DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this
mode is the best among all power modes. Power consumption is defined by
IDD2P1. Exiting this mode is defined by tXP, but also tXPDLL (10–20 according to
DDR type) cycles until first data transfer is allowed. For this mode, DRAM DLL
must be off.
Pre-charged power-down (PPD): This mode is entered if all banks in DDR are
pre-charged when de-asserting CKE. Power saving in this mode is intermediate –
better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP. The difference from APD mode is that when
waking-up all page-buffers are empty.) The LPDDR does not have a DLL. As a
result, the power savings are as good as PPD/DLL-off, but will have lower exit
latency and higher performance.
The CKE is determined per rank, whenever it is inactive. Each rank has an idle-
counter. The idle-counter starts counting as soon as the rank has no accesses, and if
it expires, the rank may enter power-down while no new transactions to the rank
arrives to queues. The idle-counter begins counting at the last incoming transaction
arrival.
It is important to understand that since the power-down decision is per rank, the IMC
can find many opportunities to power down ranks, even while running memory
intensive applications; the savings are significant (may be few Watts, according to the
DDR specification). This is significant when each channel is populated with more
ranks.
Selection of power modes should be according to power-performance or thermal
trade-offs of a given system:
•
•
•
When trying to achieve maximum performance and power or thermal
consideration is not an issue – use no power-down
In a system which tries to minimize power-consumption, try using the deepest
power-down mode possible – PPD/DLL-off with a low idle timer value
In high-performance systems with dense packaging (that is, tricky thermal
design) the power-down mode should be considered in order to reduce the heating
and avoid DDR throttling caused by the heating.
The default value that BIOS configures in "PM_PDWN_config_0_0_0_MCHBAR" is
6080h – that is, PPD/DLL-off mode with idle timer of 80h, or 128 DCLKs. This is a
balanced setting with deep power-down mode and moderate idle timer value.
The idle timer expiration count defines the # of DCKLs that a rank is idle that causes
entry to the selected powermode. As this timer is set to a shorter time, the IMC will
have more opportunities to put DDR in power-down. There is no BIOS hook to set this
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register. Customers choosing to change the value of this register can do it by
changing it in the BIOS. For experiments, this register can be modified in real time if
BIOS does not lock the IMC registers.
4.3.2.1
4.3.2.2
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3L/DDR3L-RS reset pin) once power is applied. It must be driven
LOW by the DDR controller to make sure the SDRAM components float DQ and DQS
during power-up. CKE signals remain LOW (while any reset is active) until the BIOS
writes to a configuration register. Using this method, CKE is ensured to remain
inactive for much longer than the specified 200 micro-seconds after power and clocks
to SDRAM devices are stable.
Conditional Self-Refresh
During S0 idle state, system memory may be conditionally placed into self-refresh
state when the processor is in package C3 or deeper power state. Refer to Intel®
Rapid Memory Power Management (Intel® RMPM) for more details on conditional self-
refresh with Intel HD Graphics enabled.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,
the processor core flushes pending cycles and then enters SDRAM ranks that are not
used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the
SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for package C3 or deeper power states as
long as there are no memory requests to service.
Table 19.
Targeted Memory State Conditions
Mode
Memory State with Processor Graphics
Memory State with External Graphics
Dynamic memory rank power-down based on
idle conditions.
Dynamic memory rank power-down based on
idle conditions.
C0, C1, C1E
If the processor graphics engine is idle and
there are no pending display requests, then
enter self-refresh. Otherwise, use dynamic
memory rank power-down based on idle
conditions.
If there are no memory requests, then enter
self-refresh. Otherwise, use dynamic memory
rank power-down based on idle conditions.
C3, C6, C7
or deeper
S3
S4
Self-Refresh Mode
Self-Refresh Mode
Memory power-down (contents lost)
Memory power-down (contents lost)
4.3.2.3
Dynamic Power-Down
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power-down state.
The processor core controller can be configured to put the devices in active power-
down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-
assertion with all pages closed). Pre-charge power-down provides greater power
savings, but has a bigger performance impact since all pages will first be closed before
putting the devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
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4.3.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks, CKE, ODE, and CS signals are controlled per DIMM rank and will be powered
down for unused ranks.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.3.3
DDR Electrical Power Gating (EPG)
The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the
processor is at C3 or deeper power state.
In C3 or deeper power state, the processor internally gates VDDQ for the majority of
the logic to reduce idle power while keeping all critical DDR pins such as CKE and
VREF in the appropriate state.
In C7 or deeper power state, the processor internally gates VccST for all non-critical
state to reduce idle power.
In S3 or C-state transitions, the DDR does not go through training mode and will
restore the previous training information.
4.4
Graphics Power Management
4.4.1
Intel® Rapid Memory Power Management (Intel® RMPM)
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory
into self-refresh when the processor is in package C3 or deeper power state to allow
the system to remain in the lower power states longer for memory not reserved for
graphics memory. Intel RMPM functionality depends on graphics/display state
(relevant only when processor graphics is being used), as well as memory traffic
patterns generated by other connected I/O devices.
4.4.2
4.4.3
Graphics Render C-State
Render C-state (RC6) is a technique designed to optimize the average power to the
graphics render engine during times of idleness. RC6 is entered when the graphics
render engine, blitter engine, and the video engine have no workload being currently
worked on and no outstanding graphics memory transactions. When the idleness
condition is met, the processor graphics will program the graphics render engine
internal power rail into a low voltage state.
Intel® Smart 2D Display Technology (Intel® S2DDT)
Intel S2DDT reduces display refresh memory traffic by reducing memory reads
required for display refresh. Power consumption is reduced by less accesses to the
IMC. Intel S2DDT is only enabled in single pipe mode.
Intel S2DDT is most effective with:
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•
•
Display images well suited to compression, such as text windows, slide shows, and
so on. Poor examples are 3D games.
Static screens such as screens with significant portions of the background showing
2D applications, processor benchmarks, and so on, or conditions when the
processor is idle. Poor examples are full-screen 3D games and benchmarks that
flip the display image at or near display refresh rates.
4.4.4
Intel® Graphics Dynamic Frequency
Intel Graphics Dynamic Frequency Technology is the ability of the processor and
graphics cores to opportunistically increase frequency and/or voltage above the
guaranteed processor and graphics frequency for the given part. Intel Graphics
Dynamic Frequency Technology is a performance feature that makes use of unused
package power and thermals to increase application performance. The increase in
frequency is determined by how much power and thermal budget is available in the
package, and the application demand for additional processor or graphics
performance. The processor core control is maintained by an embedded controller.
The graphics driver dynamically adjusts between P-States to maintain optimal
performance, power, and thermals. The graphics driver will always try to place the
graphics engine in the most energy efficient P-state.
4.4.5
Intel® Display Power Saving Technology (Intel® DPST)
The Intel DPST technique achieves backlight power savings while maintaining a good
visual experience. This is accomplished by adaptively enhancing the displayed image
while decreasing the backlight brightness simultaneously. The goal of this technique is
to provide equivalent end-user-perceived image quality at a decreased backlight
power level.
1. The original (input) image produced by the operating system or application is
analyzed by the Intel DPST subsystem. An interrupt to Intel DPST software is
generated whenever a meaningful change in the image attributes is detected. (A
meaningful change is when the Intel DPST software algorithm determines that
enough brightness, contrast, or color change has occurred to the displaying
images that the image enhancement and backlight control needs to be altered.)
2. Intel DPST subsystem applies an image-specific enhancement to increase image
contrast, brightness, and other attributes.
3. A corresponding decrease to the backlight brightness is applied simultaneously to
produce an image with similar user-perceived quality (such as brightness) as the
original image.
Intel DPST 6.0 has improved the software algorithms and has minor hardware
changes to better handle backlight phase-in and ensures the documented and
validated method to interrupt hardware phase-in.
4.4.6
Intel® Automatic Display Brightness
The Intel Automatic Display Brightness feature dynamically adjusts the backlight
brightness based upon the current ambient light environment. This feature requires an
additional sensor to be on the panel front. The sensor receives the changing ambient
light conditions and sends the interrupts to the Intel Graphics driver. As per the
change in Lux, (current ambient light illuminance), the new backlight setting can be
adjusted through BLC. The converse applies for a brightly lit environment. Intel
Automatic Display Brightness increases the backlight setting.
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4.4.7
Intel® Seamless Display Refresh Rate Technology (Intel®
SDRRS Technology)
When a Local Flat Panel (LFP) supports multiple refresh rates, the Intel Display
Refresh Rate Switching power conservation feature can be enabled. The higher refresh
rate will be used when plugged in with an AC power adaptor or when the end user has
not selected/enabled this feature. The graphics software will automatically switch to a
lower refresh rate for maximum battery life when the notebook is on battery power
and when the user has selected/enabled this feature. There are two distinct
implementations of Intel DRRS – static and seamless. The static Intel DRRS method
uses a mode change to assign the new refresh rate. The seamless Intel DRRS method
is able to accomplish the refresh rate assignment without a mode change and
therefore does not experience some of the visual artifacts associated with the mode
change (SetMode) method.
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5.0
Thermal Management
The thermal solution provides both component-level and system-level thermal
management. To allow for the optimal operation and long-term reliability of Intel
processor-based systems, the system/processor thermal solution should be designed
so that the processor:
•
Remains below the maximum junction temperature (TjMax) specification at the
maximum thermal design power (TDP).
•
Conforms to system constraints, such as system acoustics, system skin-
temperatures, and exhaust-temperature requirements.
Caution: Thermal specifications given in this chapter are on the component and
package level and apply specifically to the processor. Operating the processor outside
the specified limits may result in permanent damage to the processor and potentially
other components in the system.
5.1
Thermal Considerations
The processor TDP is the maximum sustained power that should be used for design of
the processor thermal solution. TDP represents an expected maximum sustained
power from realistic applications. TDP may be exceeded for short periods of time or if
running a "power virus" workload.
The processor integrates multiple processing and graphics cores and PCH on a single
package.This may result in differences in the power distribution across the die and
must be considered when designing the thermal solution.
Intel® Turbo Boost Technology 2.0 allows processor cores and processor graphics
cores to run faster than the guaranteed frequency. It is invoked opportunistically and
automatically as long as the processor is conforming to its temperature, power
delivery, and current specification limits. When Intel Turbo Boost Technology 2.0 is
enabled:
•
Applications are expected to run closer to TDP more often as the processor will
attempt to maximize performance by taking advantage of available TDP headroom
in the processor package.
•
The processor may exceed the TDP for short durations to use any available
thermal capacitance within the thermal solution. The duration and time of such
operation can be limited by platform runtime configurable registers within the
processor.
•
Thermal solutions and platform cooling that are designed to less than thermal
design guidance may experience thermal and performance issues since more
applications will tend to run at or near TDP for significant periods of time.
Note:
Intel Turbo Boost Technology 2.0 availability may vary between the different SKUs.
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5.2
5.3
Intel® Turbo Boost Technology 2.0 Power Monitoring
When operating in turbo mode, the processor monitors its own power and adjusts the
turbo frequencies to maintain the average power within limits over a thermally
significant time period. The processor calculates the package power that consists of
the processor core power and graphics core power. In the event that a workload
causes the power to exceed program power limits, the processor will protect itself
using the Adaptive Thermal Monitor.
Intel® Turbo Boost Technology 2.0 Power Control
Illustration of Intel Turbo Boost Technology 2.0 power control is shown in the
following sections and figures. Multiple controls operate simultaneously allowing for
customization for multiple system thermal and power limitations. These controls allow
for turbo optimizations within system constraints and are accessible using MSR, MMIO,
or PECI interfaces
5.3.1
Package Power Control
The package power control allows for customization to implement optimal turbo within
platform power delivery and package thermal solution limitations.
Table 20.
Intel® Turbo Boost Technology 2.0 Package Power Control Settings
MSR:
MSR_TURBO_POWER_LIMIT
610h
Address:
Control
Bit
Default
Description
•
•
This value sets the average power limit over a long time
period. This is normally aligned to the TDP of the part and
steady-state cooling capability of the thermal solution. The
default value is the TDP for the SKU.
PL1 limit may be set lower than TDP in real time for specific
needs, such as responding to a thermal event. If it is set
lower than TDP, the processor may require to use frequencies
below the guaranteed P1 frequency to control the low-power
limits. The PL1 Clamp bit [16] should be set to enable the
processor to use frequencies below P1 to control the set-
power limit.
POWER_LIMIT_1 (PL1)
14:0
SKU TDP
•
PL1 limit may be set higher than TDP. If set higher than TDP,
the processor could stay at that power level continuously and
cooling solution improvements may be required.
This value is a time parameter that adjusts the algorithm
behavior to maintain time averaged power at or below PL1. The
hardware default value is 1 second; however, 28 seconds is
recommended for most mobile applications.
POWER_LIMIT_1_TIME
(Turbo Time Parameter)
23:17
46:32
1 sec
PL2 establishes the upper power limit of turbo operation above
TDP, primarily for platform power supply considerations. Power
may exceed this limit for up to 10 ms. The default for this limit is
1.25 x TDP; however, the BIOS may reprogram the default value
to maximize the performance within platform power supply
considerations. Setting this limit to TDP will limit the processor to
only operate up to the TDP. It does not disable turbo because
turbo is opportunistic and power/temperature dependent. Many
workloads will allow some turbo frequencies for powers at or
below TDP.
POWER_LIMIT_2 (PL2)
1.25 x TDP
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Figure 12.
Package Power Control
5.3.2
Turbo Time Parameter
Turbo Time Parameter is a mathematical parameter (units in seconds) that controls
the Intel Turbo Boost Technology 2.0 algorithm using moving average of energy
usage. During a maximum power turbo event of about 1.25 x TDP, the processor
could sustain PL2 for up to approximately 1.5 times the Turbo Time Parameter. If the
power value and/or Turbo Time Parameter is changed during runtime, it may take
approximately 3 to 5 times the Turbo Time Parameter for the algorithm to settle at the
new control limits. The time varies depending on the magnitude of the change and
other factors. There is an individual Turbo Time Parameter associated with Package
Power Control.
5.4
Configurable TDP (cTDP) and Low-Power Mode
Configurable TDP (cTDP) and Low-Power Mode (LPM) form a design vector where the
processor behavior and package TDP are dynamically adjusted to a desired system
performance and power envelope. Configurable TDP and Low-Power Mode
technologies are not battery life improvement technologies; however, the technologies
offer opportunities to differentiate system design while running active workloads on
select processor SKUs through scalability, configureability, and adaptability. The
scenarios or methods by which each technology is used are customizable, but typically
involve changes to TDP with a resultant change in performance depending on system
usage. Either technology can be triggered by (but not limited to) changes in operating
system power policies, or hardware events such as docking a system, flipping a
switch, or pressing a button. cTDP and LPM are designed to be configured dynamically
and do not require an operating system reboot.
5.4.1
Configurable TDP
Note:
Configurable TDP availability may vary between the different SKUs.
With cTDP, the processor is now capable of altering the maximum sustained power
with an alternate guaranteed frequency. Configurable TDP allows operation in
situations where extra cooling is available or situations where a cooler and quieter
mode of operation is desired. Configurable TDP can be enabled using Intel's DPTF
driver or through HW/EC firmware. Enabling cTDP using the DPTF driver is
recommended as Intel does not provide specific application or EC source code.
cTDP consists of three modes as shown in the following table.
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Table 21.
Configurable TDP Modes
Mode
Description
This is the processor's rated frequency and TDP.
Nominal
TDP-Up
When extra cooling is available, this mode specifies a higher TDP and higher
guaranteed frequency versus the nominal mode.
TDP-Down
When a cooler or quieter mode of operation is desired, this mode specifies a lower TDP
and lower guaranteed frequency versus the nominal mode.
In each mode, the Intel Turbo Boost Technology 2.0 power and frequency ranges are
reprogrammed and the OS is given a new effective HFM operating point. The Intel
DPTF driver assists in all these operations. The cTDP mode does not change the max
per-core turbo frequency.
5.4.2
Low-Power Mode
Low-Power Mode (LPM) can provide cooler and quieter system operation. By
combining several active power limiting techniques, the processor can consume less
power while running at equivalent low frequencies. Active power is defined as
processor power consumed while a workload is running and does not refer to the
power consumed during idle modes of operation. LPM is only available using the Intel
DPTF driver.
Through the DPTF driver, LPM can be configured to use each of the following methods
to reduce active power:
•
•
•
•
•
•
Restricting Intel Turbo Boost Power limits and IA core Turbo Boost availability
Off-Lining core activity (Move processor traffic to a subset of cores)
Placing an IA Core at LFM or MFM (Minimum Frequency Mode)
Utilizing IA clock modulation
Reducing number of active EUs to GT2 equivalent (Applicable for GT3 SKUs Only)
LPM power as listed in the TDP Specifications table is defined at a point which IA
cores working at MFM, GT = RPn and 1 core active
Off-lining core activity is the ability to dynamically scale a workload to a limited subset
of cores in conjunction with a lower turbo power limit. It is one of the main vectors
available to reduce active power. However, not all processor activity is ensured to be
able to shift to a subset of cores. Shifting a workload to a limited subset of cores
allows other cores to remain idle and save power. Therefore, when LPM is enabled,
less power is consumed at equivalent frequencies.
Minimum Frequency Mode (MFM) of operation, which is the lowest linear frequency
supported at the LFM voltage, has been made available for use under LPM for further
reduction in active power beyond LFM capability to enable cooler and quieter modes of
operation.
5.5
Thermal and Power Specifications
The following notes apply to Table 22 on page 63 and Table 23 on page 64.
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Note
Definition
The TDPs given are not the maximum power the processor can generate. Analysis indicates that real applications
are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of
time.
1
2
3
TDP workload may consist of a combination of processor-core intensive and graphics-core intensive applications.
The thermal solution needs to ensure that the processor temperature does not exceed the maximum junction
temperature (TjMAX) limit, as measured by the DTS and the critical temperature bit.
The processor junction temperature is monitored by Digital Temperature Sensors (DTS). For DTS accuracy, refer to
Digital Thermal Sensor Accuracy (Taccuracy) on page 68.
4
5
6
Digital Thermal Sensor (DTS) based fan speed control is required to achieve optimal thermal performance. Intel
recommends full cooling capability well before the DTS reading reaches TjMAX. An example of this is TjMAX – 10 ºC.
The idle power specifications are not 100% tested. These power specifications are determined by the
characterization at higher temperatures and extrapolating the values for the junction temperature indicated.
7
8
At Tj of TjMAX
At Tj of 50 ºC
9
At Tj of 35 ºC
10
Can be modified at runtime by MSR writes, with MMIO and with PECI commands.
'Turbo Time Parameter' is a mathematical parameter (unit in seconds) that controls the processor turbo algorithm
using a moving average of energy usage. Do not set the Turbo Time Parameter to a value less than 0.1 seconds.
Refer to Turbo Time Parameter on page 61 for further information.
11
12
Shown limit is a time averaged power, based upon the Turbo Time Parameter. Absolute product power may exceed
the set limits for short durations or under virus or uncharacterized workloads.
Processor will be controlled to specified power limit as described in Intel Turbo Boost Technology 2.0 Power
Monitoring on page 60. If the power value and/or 'Turbo Time Parameter' is changed during runtime, it may take a
short period of time (approximately 3 to 5 times the 'Turbo Time Parameter') for the algorithm to settle at the new
control limits.
13
14
15
16
17
This is a hardware default setting and not a behavioral characteristic of the part.
For controllable turbo workloads, limit may be exceeded for up to 10 ms.
Refer to Table 21 on page 62 for the definitions of 'TDP-Nominal', 'TDP-Up', 'TDP-Down'.
LPM power level is an opportunistic power and is not a guaranteed value as usages and implementations may vary.
Power limits may vary depending on if the product supports the 'TDP-up' and/or 'TDP-down' modes. Default power
limits can be found in the PKG_PWR_SKU MSR (614h).
18
19
20
21
May vary based on SKU.
cTDP down power is based on GT2 equivalent graphics configuration. cTDP down does not decrease the number of
active Processor Graphics EUs, but relies on Power Budget Management (PL1) to achieve the specified power level.
Hardware default values might be overridden by the BIOS.
Table 22.
Thermal Design Power (TDP) Specifications
Segment
State
Processor Core
Frequency
Processor
Graphics Core
Frequency
Thermal Design
Power
Units
Notes
TDP-Nominal /
HFM
2.0 GHz up to
2.8 GHz
28
U-Processor
(Dual Core)
200 MHz up to
1200 MHz
1, 2, 7,
16, 17,
18
TDP-Down /
LFM
W
28W
GT3
800 MHz
800 MHz
23
LPM
200 MHz
22.5
continued...
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Segment
State
Processor Core
Frequency
Processor
Graphics Core
Frequency
Thermal Design
Power
Units
Notes
TDP Nominal /
HFM
1.3 GHz up to
1.7 GHz
15
U-Processor
(Dual Core)
200 MHz up to
1100 MHz
1, 2, 7,
16, 17,
18
TDP-Down /
LFM
W
15W
GT3
800 MHz
800 MHz
11.5
LPM
200 MHz
11
25
TDP-Up
1.6 GHz up to
2.3 GHz
TDP Nominal /
HFM
U-Processor
(Dual Core)
200 MHz up to
1100 MHz
15
1, 2, 7,
16, 17,
18
W
15W
GT2
TDP-Down /
LFM
800 MHz
800 MHz
11.5
11
LPM
200 MHz
TDP Nominal /
HFM
1.3 GHz up to
1.4 GHz
11.5
Y-Processor
(Dual Core)
200 MHz up to
850 MHz
TDP-Down /
LFM
9.5 (6W SDP / 4.5W
SDP)
W
19
11.5W (6W
SDP / 4.5W
SDP)
800 MHz
600 MHz
LPM
200 MHz
9
Table 23.
Junction Temperature Specification
Segment
Symbol
Package Turbo
Parameter
Min
Default
Max
Units
Notes
U-Processor (Dual
Core)
Junction temperature
limit
Tj
0
0
—
—
100
100
ºC
ºC
3, 4, 5
3, 4, 5
Y-Processor (Dual
Core)
Junction temperature
limit
Tj
Table 24.
Maximum Idle Power Specification
Symbol
Parameter
U-Processor
15W with GT3
U-Processor
28W with GT3
Y-Processor
6W SDP /
4.5W SDP
with GT2
Unit
Note
Min
Max
Min
Max
Min
Max
Package power in Package C7
state
PPACKAGE(C7)
PPACKAGE(C8)
PPACKAGE(C9)
PPACKAGE(C10)
—
0.95
—
1.5
—
0.85
W
W
W
W
1, 3
1
Package power in Package C8
state
—
—
—
0.12
0.052
0.052
—
—
—
0.18
0.1
—
—
—
0.1
Package power in Package C9
state
0.04
0.04
1
Package power in Package C10
state
0.1
1
Package power in System
S3/S4/S5 and M3 state
(internal Suspend)
PPACKAGE(Sx/M3)
INT_SUS
—
—
60
50
—
—
60
50
—
—
60
50
mW
1, 2
Package power in System
S3/S4/S5 and Moff state
(internal Suspend)
PPACKAGE(Sx/Moff)
INT_SUS
mW
1, 2
continued...
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Symbol
Parameter
U-Processor
15W with GT3
U-Processor
28W with GT3
Y-Processor
6W SDP /
4.5W SDP
with GT2
Unit
Note
Min
Max
Min
Max
Min
Max
Package power in System
S3/S4/S5 and M3 state
(external Suspend)
PPACKAGE(Sx/M3)
EXT_SUS
—
51
—
51
—
51
mW
1, 2
Package power in System
S3/S4/S5 and Moff state
(external Suspend)
PPACKAGE(Sx/Moff)
EXT_SUS
—
—
33
19
—
—
33
19
—
—
33
19
mW
mW
1, 2
1, 2
Package power in System Deep
Sx state
PPACKAGE(Deep Sx)
Notes: 1. Package power includes both MCP components: processor and PCH.
2. Measured at Tj = 35 °C.
3. The C7 power is measured with LLC ON.
5.6
Thermal Management Features
Occasionally the processor may operate in conditions that are near to its maximum
operating temperature. This can be due to internal overheating or overheating within
the platform. To protect the processor and the platform from thermal failure, several
thermal management features exist to reduce package power consumption and
thereby temperature in order to remain within normal operating limits. Furthermore,
the processor supports several methods to reduce memory power.
5.6.1
Adaptive Thermal Monitor
The purpose of the Adaptive Thermal Monitor is to reduce processor core power
consumption and temperature until it operates at or below its maximum operating
temperature. Processor core power reduction is achieved by:
•
•
Adjusting the operating frequency (using the core ratio multiplier) and voltage.
Modulating (starting and stopping) the internal processor core clocks (duty cycle).
The Adaptive Thermal Monitor can be activated when the package temperature,
monitored by any digital thermal sensor (DTS) meets or exceeds its maximum
operating temperature. The maximum operating temperature implies either maximum
junction temperature TjMAX, or TjMAX minus TCC Activation offset.
Exceeding the maximum operating temperature activates the thermal control circuit
(TCC), if enabled. When activated the thermal control circuit (TCC) causes both the
processor core and graphics core to reduce frequency and voltage adaptively. The
Adaptive Thermal Monitor will remain active as long as the package temperature
exceeds its specified limit. Therefore, the Adaptive Thermal Monitor will continue to
reduce the package frequency and voltage until the TCC is de-activated.
TjMAX is factory calibrated and is not user configurable. The default value is software
visible in the TEMPERATURE_TARGET (0x1A2) MSR, bits [23:16]. The
TEMPERATURE_TARGET value stays the same when TCC Activation offset is enabled.
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The Adaptive Thermal Monitor does not require any additional hardware, software
drivers, or interrupt handling routines. It is not intended as a mechanism to maintain
processor TDP. The system design should provide a thermal solution that can maintain
TDP within its intended usage range.
Note:
Adaptive Thermal Monitor protection is always enabled.
5.6.1.1
Thermal Control Circuit (TCC) Activation Offset
TCC Activation Offset can be used to activate the Adaptive Thermal Monitor at
temperatures lower than TjMAX. It is the preferred thermal protection mechanism for
Intel Turbo Boost Technology 2.0 operation since ACPI passive throttling states will
pull the processor out of turbo mode operation when triggered. An offset (in degrees
Celsius) can be written to the TEMPERATURE_TARGET (0x1A2) MSR, bits [29:24]. This
value will be subtracted from the value found in bits [23:16]. The default offset is
0 °C, where throttling will occur at TjMAX. The offset should be set lower than any
other protection such as ACPI _PSV trip points.
5.6.1.2
Frequency / Voltage Control
Upon Adaptive Thermal Monitor activation, the processor core attempts to dynamically
reduce processor core power by lowering the frequency and voltage operating point.
The operating points are automatically calculated by the processor core itself and do
not require the BIOS to program them as with previous generations of Intel
processors. The processor core will scale the operating points such that:
•
The voltage will be optimized according to the temperature, the core bus ratio,
and number of cores in deep C-states.
•
The core power and temperature are reduced while minimizing performance
degradation.
Once the temperature has dropped below the maximum operating temperature, the
operating frequency and voltage will transition back to the normal system operating
point.
Once a target frequency/bus ratio is resolved, the processor core will transition to the
new target automatically.
•
•
•
On an upward operating point transition, the voltage transition precedes the
frequency transition.
On a downward transition, the frequency transition precedes the voltage
transition.
The processor continues to execute instructions. However, the processor will halt
instruction execution for frequency transitions.
If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition
(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there
are two possible outcomes:
•
If the P-state target frequency is higher than the processor core optimized target
frequency, the P-state transition will be deferred until the thermal event has been
completed.
•
If the P-state target frequency is lower than the processor core optimized target
frequency, the processor will transition to the P-state operating point.
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5.6.1.3
Clock Modulation
If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor
event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is
done by alternately turning the clocks off and on at a duty cycle (ratio between clock
"on" time and total time) specific to the processor. The duty cycle is factory configured
to 25% on and 75% off and cannot be modified. The period of the duty cycle is
configured to 32 microseconds when the Adaptive Thermal Monitor is active. Cycle
times are independent of processor frequency. A small amount of hysteresis has been
included to prevent excessive clock modulation when the processor temperature is
near its maximum operating temperature. Once the temperature has dropped below
the maximum operating temperature, and the hysteresis timer has expired, the
Adaptive Thermal Monitor goes inactive and clock modulation ceases. Clock
modulation is automatically engaged as part of the Adaptive Thermal Monitor
activation when the frequency/voltage targets are at their minimum settings.
Processor performance will be decreased by the same amount as the duty cycle when
clock modulation is active. Snooping and interrupt processing are performed in the
normal manner while the Adaptive Thermal Monitor is active.
5.6.2
Digital Thermal Sensor
Each processor execution core has an on-die Digital Thermal Sensor (DTS) that
detects the core's instantaneous temperature. The DTS is the preferred method of
monitoring processor die temperature because:
•
•
It is located near the hottest portions of the die.
It can accurately track the die temperature and ensure that the Adaptive Thermal
Monitor is not excessively activated.
Temperature values from the DTS can be retrieved through:
•
•
A software interface using processor Model Specific Register (MSR).
A processor hardware interface as described in Platform Environmental Control
Interface (PECI) on page 29.
When temperature is retrieved by the processor MSR, it is the instantaneous
temperature of the given core. When temperature is retrieved using PECI, it is the
average of the highest DTS temperature in the package over a 256 ms time window.
Intel recommends using the PECI reported temperature for platform thermal control
that benefits from averaging, such as fan speed control. The average DTS
temperature may not be a good indicator of package Adaptive Thermal Monitor
activation or rapid increases in temperature that triggers the Out of Specification
status bit within the PACKAGE_THERM_STATUS MSR 1B1h and IA32_THERM_STATUS
MSR 19Ch.
Code execution is halted in C1 or deeper C-states. Package temperature can still be
monitored through PECI in lower C-states.
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (TjMAX), regardless of
TCC activation offset. It is the responsibility of software to convert the relative
temperature to an absolute temperature. The absolute reference temperature is
readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the
DTS is an implied negative integer indicating the relative offset from TjMAX. The DTS
does not report temperatures greater than TjMAX. The DTS-relative temperature
readout directly impacts the Adaptive Thermal Monitor trigger point. When a package
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DTS indicates that it has reached the TCC activation (a reading of 0h, except when the
TCC activation offset is changed), the TCC will activate and indicate an Adaptive
Thermal Monitor event. A TCC activation will lower both IA core and graphics core
frequency, voltage, or both. Changes to the temperature can be detected using two
programmable thresholds located in the processor thermal MSRs. These thresholds
have the capability of generating interrupts using the core's local APIC. Refer to the
Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register
and programming details.
5.6.2.1
5.6.2.2
Digital Thermal Sensor Accuracy (Taccuracy)
The error associated with DTS measurements will not exceed ±5 °C within the entire
operating range.
Fan Speed Control with Digital Thermal Sensor
Digital Thermal Sensor based fan speed control (TFAN) is a recommended feature to
achieve optimal thermal performance. At the TFAN temperature, Intel recommends full
cooling capability well before the DTS reading reaches TjMAX
.
5.6.3
PROCHOT# Signal
PROCHOT# (processor hot) is asserted when the processor temperature has reached
its maximum operating temperature (TjMAX). Only a single PROCHOT# pin exists at a
package level. When any core arrives at the TCC activation point, the PROCHOT#
signal will be asserted. PROCHOT# assertion policies are independent of Adaptive
Thermal Monitor enabling.
5.6.3.1
Bi-Directional PROCHOT#
By default, the PROCHOT# signal is set to bi-directional. However, it is recommended
to configure the signal as an input only. When configured as an input or bi-directional
signal, PROCHOT# can be used for thermally protecting other platform components in
case the components overheat as well. When PROCHOT# is driven by an external
device:
•
The package will immediately transition to the lowest P-State (Pn) supported by
the processor and graphics cores. This is contrary to the internally-generated
Adaptive Thermal Monitor response.
•
Clock modulation is not activated.
The processor package will remain at the lowest supported P-state until the system
de-asserts PROCHOT#. The processor can be configured to generate an interrupt upon
assertion and de-assertion of the PROCHOT# signal.
Note:
When PROCHOT# is configured as a bi-directional signal and PROCHOT# is asserted
by the processor, it is impossible for the processor to detect a system assertion of
PROCHOT#. The system assertion will have to wait until the processor de-asserts
PROCHOT# before PROCHOT# action can occur due to the system assertion. While the
processor is hot and asserting PROCHOT#, the power is reduced; however, the
reduction rate is slower than the system PROCHOT# response of < 100 us. The
processor thermal control is staged in smaller increments over many milliseconds. This
may cause several milliseconds of delay to a system assertion of PROCHOT# while the
output function is asserted.
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5.6.3.2
Voltage Regulator Protection using PROCHOT#
PROCHOT# may be used for thermal protection of voltage regulators (VR). System
designers can create a circuit to monitor the VR temperature and assert PROCHOT#
and, if enabled, activate the TCC when the temperature limit of the VR is reached.
When PROCHOT# is configured as a bi-directional or input only signal, if the system
assertion of PROCHOT# is recognized by the processor, it will result in an immediate
transition to the lowest P-State (Pn) supported by the processor and graphics cores.
Systems should still provide proper cooling for the VR and rely on bi-directional
PROCHOT# only as a backup in case of system cooling failure. Overall, the system
thermal design should allow the power delivery circuitry to operate within its
temperature specification even while the processor is operating at its TDP.
5.6.3.3
Thermal Solution Design and PROCHOT# Behavior
With a properly designed and characterized thermal solution, it is anticipated that
PROCHOT# will only be asserted for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable.
However, an under-designed thermal solution that is not able to prevent excessive
assertion of PROCHOT# in the anticipated ambient environment may:
•
•
Cause a noticeable performance loss.
Result in prolonged operation at or above the specified maximum junction
temperature and affect the long-term reliability of the processor.
•
May be incapable of cooling the processor even when the TCC is active
continuously (in extreme situations).
5.6.3.4
Low-Power States and PROCHOT# Behavior
Depending on package power levels during package C-states, outbound PROCHOT#
may de-assert while the processor is idle as power is removed from the signal. Upon
wakeup, if the processor is still hot, the PROCHOT# will re-assert, although typically
package idle state residency should resolve any thermal issues. The PECI interface is
fully operational during all C-states and it is expected that the platform continues to
manage processor core and package thermals even during idle states by regularly
polling for thermal data over PECI.
5.6.3.5
5.6.3.6
THERMTRIP# Signal
Regardless of enabling the automatic or on-demand modes, in the event of a
catastrophic cooling failure, the package will automatically shut down when the silicon
has reached an elevated temperature that risks physical damage to the product. At
this point the THERMTRIP# signal will go active.
Critical Temperature Detection
Critical Temperature detection is performed by monitoring the package temperature.
This feature is intended for graceful shutdown before the THERMTRIP# is activated.
However, the processor execution is not guaranteed between critical temperature and
THERMTRIP#. If the Adaptive Thermal Monitor is triggered and the temperature
remains high, a critical temperature status and sticky bit are latched in the
PACKAGE_THERM_STATUS MSR 1B1h and the condition also generates a thermal
interrupt, if enabled. For more details on the interrupt mechanism, refer to the Intel®
64 and IA-32 Architectures Software Developer’s Manual.
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5.6.4
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption using clock modulation. This
mechanism is referred to as "On-Demand" mode and is distinct from Adaptive Thermal
Monitor and bi-directional PROCHOT#. The processor platforms must not rely on
software usage of this mechanism to limit the processor temperature. On-Demand
Mode can be accomplished using processor MSR or chipset I/O emulation. On-Demand
Mode may be used in conjunction with the Adaptive Thermal Monitor. However, if the
system software tries to enable On-Demand mode at the same time the TCC is
engaged, the factory configured duty cycle of the TCC will override the duty cycle
selected by the On-Demand mode. If the I/O based and MSR-based On-Demand
modes are in conflict, the duty cycle selected by the I/O emulation-based On-Demand
mode will take precedence over the MSR-based On-Demand Mode.
5.6.4.1
MSR Based On-Demand Mode
If Bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will
immediately reduce its power consumption using modulation of the internal core clock,
independent of the processor temperature. The duty cycle of the clock modulation is
programmable using bits [3:1] of the same IA32_CLOCK_MODULATION MSR. In this
mode, the duty cycle can be programmed in either 12.5% or 6.25% increments
(discoverable using CPUID). Thermal throttling using this method will modulate each
processor core's clock independently.
5.6.4.2
5.6.5
I/O Emulation-Based On-Demand Mode
I/O emulation-based clock modulation provides legacy support for operating system
software that initiates clock modulation through I/O writes to ACPI defined processor
clock control registers on the chipset (PROC_CNT). Thermal throttling using this
method will modulate all processor cores simultaneously.
Intel® Memory Thermal Management
The processor provides thermal protection for system memory by throttling memory
traffic when using either DIMM modules or a memory down implementation. Two
levels of throttling are supported by the processor – either a warm threshold or hot
threshold that is customizable through memory mapped I/O registers. Throttling
based on the warm threshold should be an intermediate level of throttling. Throttling
based on the hot threshold should be the most severe. The amount of throttling is
dynamically controlled by the processor.
Memory temperature can be acquired through an on-board thermal sensor (TS-on-
Board), retrieved by an embedded controller and reported to the processor through
the PECI 3.0 interface. This methodology is known as PECI injected temperatures and
is a method of Closed Loop Thermal Management (CLTM). CLTM requires the use of a
physical thermal sensor. EXTTS# is another method of CLTM; however, it is only
capable of reporting memory thermal status to the processor. EXTTS# consists of two
GPIO pins on the PCH where the state of the pins is communicated internally to the
processor.
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When a physical thermal sensor is not available to report temperature, the processor
supports Open Loop Thermal Management (OLTM) that estimates the power
consumed per rank of the memory using the processor DRAM power meter. A per rank
power is associated with the warm and hot thresholds that, when exceeded, may
trigger memory thermal throttling.
5.6.6
Scenario Design Power (SDP)
Scenario Design Power (SDP) is a usage-based design specification, and provides an
additional reference design point for power constrained platforms. SDP is a specified
power level under a specific scenario workload, temperature, and frequency.
Intel recommends setting POWER_LIMIT_1 (PL1) to the system cooling capability
(SDP level, or higher). While the SDP specification is characterized at Tj of 80 °C, the
functional limit for the product remains at TjMAX. Customers may choose to have the
processor invoke TCC Activation Throttling at 80 °C, but is not required.
The processors that have SDP specified can still exceed SDP under certain workloads,
such as TDP workloads. TDP power dissipation is still possible with the intended usage
models, and protection mechanisms to handle levels beyond cooling capabilities are
recommended. Intel recommends using such thermal control mechanisms to manage
situations where power may exceed the thermal design capability.
Note:
Note:
cTDP-Down mode is required for Intel® Core™ processor products in order to achieve
SDP.
Although SDP is defined at 80 °C, the TCC activation temperature is 100 °C, and may
be changed in BIOS to 80 °C.
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Processors—Signal Description
6.0
Signal Description
This chapter describes the processor signals. The signals are arranged in functional
groups according to the associated interface or category. The following notations are
used to describe the signal type.
Notation
Signal Type
I
Input pin
O
Output pin
I/O
Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal
(see the following table).
Table 25.
Signal Description Buffer Types
Signal
CMOS
Description
CMOS buffers. 1.05V- tolerant
DDR3L/DDR3L-
RS
DDR3L/DDR3L-RS buffers: 1.35 V-tolerant
LPDDR3
A
LPDDR3 buffers: 1.2 V- tolerant
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
GTL
Gunning Transceiver Logic signaling technology
Voltage Regulator Asynchronous CMOS output
VR Enable
CMOS
Ref
Voltage reference signal
1
Asynchronous
Signal has no timing relationship with any reference clock.
1. Qualifier for a buffer type.
6.1
System Memory Interface Signals
Table 26.
DDR3L / DDR3L-RS Memory Channel A Interface (Memory-Down / SO-DIMM)
Signals
Signal Name
Description
Direction / Buffer
Type
Bank Select: These signals define which banks are selected
within each SDRAM rank.
SA_BS[2:0]
O
Write Enable Control Signal: This signal is used with
SA_RAS# and SA_CAS# (along with SA_CS#) to define the
SDRAM Commands.
SA_WE#
O
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Signal Name
SA_RAS#
Description
Direction / Buffer
Type
RAS Control Signal: This signal is used with SA_CAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
O
O
CAS Control Signal: This signal is used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
SA_CAS#
Data Strobes: SA_DQS[7:0] and its complement signal
group make up a differential strobe pair. The data is captured
at the crossing point of SA_DQS[7:0] and its SA_DQS#[7:0]
during read and write transactions.
SA_DQSP[7:0]
SA_DQSN[7:0]
I/O
Data Bus: Channel A data signal interface to the SDRAM data
bus.
SA_DQ[63:0]
SA_MA[15:0]
I/O
O
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair. The crossing of the positive edge of SA_CKP
and the negative edge of its complement SA_CKN are used to
sample the command and control signals on the SDRAM.
SA_CKP[1:0]
SA_CKN[1:0]
O
O
Chip Select: (1 per rank). These signals are used to select
particular SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
SA_CS#[1:0]
Clock Enable: (1 per rank). These signals are used to:
•
•
•
Initialize the SDRAMs during power-up
Power down SDRAM ranks
SA_CKE[3:0]
SA_ODT
O
O
Place all SDRAM ranks into and out of self-refresh during
STR
•
•
When 1R DDR3L (SODIMM/MD) CKE[0] is used
When 2R DDR3L (SODIMM/MD) CKE[1:0] are used
On Die Termination: Active Termination Control.
Table 27.
DDR3L / DDR3L-RS Memory Channel B Interface (Memory-Down / SO-DIMM)
Signals
Signal Name
Description
Direction / Buffer
Type
Bank Select: These signals define which banks are selected
within each SDRAM rank.
SB_BS[2:0]
O
O
Write Enable Control Signal: This signal is used with
SB_RAS# and SB_CAS# (along with SB_CS#) to define the
SDRAM Commands.
SB_WE#
SB_RAS#
SB_CAS#
RAS Control Signal: This signal is used with SB_CAS# and
SB_WE# (along with SB_CS#) to define the SRAM
Commands.
O
O
CAS Control Signal: This signal is used with SB_RAS# and
SB_WE# (along with SB_CS#) to define the SRAM
Commands.
Data Strobes: SB_DQS[7:0] and its complement signal
group make up a differential strobe pair. The data is captured
at the crossing point of SB_DQS[7:0] and its SB_DQS#[7:0]
during read and write transactions.
SB_DQSP[7:0]
SB_DQSN[7:0]
I/O
Data Bus: Channel A data signal interface to the SDRAM data
bus.
SB_DQ[63:0]
I/O
continued...
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Processors—Signal Description
Signal Name
Description
Direction / Buffer
Type
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
SB_MA[15:0]
O
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair. The crossing of the positive edge of SB_CKP
and the negative edge of its complement SB_CKN are used to
sample the command and control signals on the SDRAM.
SB_CKP[1:0]
SB_CKN[1:0]
O
Chip Select: (1 per rank). These signals are used to select
particular SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
SB_CS#[1:0]
O
Clock Enable: (1 per rank). These signals are used to:
•
•
•
Initialize the SDRAMs during power-up
Power down SDRAM ranks
SB_CKE[3:0]
SB_ODT
O
O
Place all SDRAM ranks into and out of self-refresh during
STR
•
•
When 1R DDR3L (SODIMM/MD) CKE[0] is used
When 2R DDR3L (SODIMM/MD) CKE[1:0] are used
On Die Termination: Active Termination Control.
Table 28.
LPDDR3 Memory Channel A Interface (Memory-Down) Signals
Signal Name
Description
Direction / Buffer
Type
Data Bus: Channel A data signal interface to the SDRAM data
bus.
SA_DQ[63:0]
I/O
Data Strobes: SA_DQS[7:0] and its complement signal
group make up a differential strobe pair. The data is captured
at the crossing point of SA_DQS[7:0] and its SA_DQS#[7:0]
during read and write transactions.
SA_DQSP[7:0]
SA_DQSN[7:0]
I/O
Command Address: These signals are used to provide the
multiplexed command and address to the SDRAM.
SA_CAA[9:0]
SA_CAB[9:0]
O
O
Command Address: These signals are used to provide the
multiplexed command and address to the SDRAM.
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair. The crossing of the positive edge of SA_CKP
and the negative edge of its complement SA_CKN are used to
sample the command and control signals on the SDRAM.
SA_CKP[1:0]
SA_CKN[1:0]
O
O
Chip Select: (1 per rank). These signals are used to select
particular SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
SA_CS#[1:0]
Clock Enable: (1 per rank). These signals are used to:
•
•
•
Initialize the SDRAMs during power-up
Power down SDRAM ranks
Place all SDRAM ranks into and out of self-refresh during
STR
SA_CKE[3:0]
SA_ODT
O
O
•
•
When 1R LPDDR3 CKE[0] and CKE[2] are used for Rank 0
When 2R LPDDR3 CKE[0] and CKE[2] are used for Rank 0
& CKE[1] and CKE[3] are used for Rank 1
On Die Termination: Active Termination Control.
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Table 29.
LPDDR3 Memory Channel B Interface (Memory-Down) Signals
Signal Name
Description
Direction / Buffer
Type
Data Bus: Channel A data signal interface to the SDRAM data
bus.
SB_DQ[63:0]
I/O
Data Strobes: SB_DQS[7:0] and its complement signal group
make up a differential strobe pair. The data is captured at the
crossing point of SB_DQS[7:0] and its SB_DQS#[7:0] during
read and write transactions.
SB_DQSP[7:0]
SB_DQSN[7:0]
I/O
Command Address: These signals are used to provide the
multiplexed command and address to the SDRAM.
SB_CAA[9:0]
SB_CAB[9:0]
O
O
Command Address: These signals are used to provide the
multiplexed command and address to the SDRAM.
SDRAM Differential Clock: Channel A SDRAM Differential
clock signal pair. The crossing of the positive edge of SB_CKP
and the negative edge of its complement SB_CKN are used to
sample the command and control signals on the SDRAM.
SB_CKP[1:0]
SB_CKN[1:0]
O
O
Chip Select: (1 per rank). These signals are used to select
particular SDRAM components during the active state. There is
one Chip Select for each SDRAM rank.
SB_CS#[1:0]
Clock Enable: (1 per rank). These signals are used to:
•
•
•
•
•
Initialize the SDRAMs during power-up
Power down SDRAM ranks.
SB_CKE[3:0]
SB_ODT
O
O
Place all SDRAM into and out of self-refresh during STR.
When 1R LPDDR3 CKE[0] and CKE[2] are used for Rank0
When 2R LPDDR3 CKE[0] and CKE[2] are used for Rank 0
and CKE[1] and CKE[3] are used for Rank 1
On Die Termination: Active Termination Control.
6.2
Memory Compensation and Miscellaneous Signals
Table 30.
LPDDR3 / DDR3L / DDR3L-RS Reference and Compensation Signals
Signal Name
Description
Direction /
Buffer Type
SM_RCOMP[2:0]
System Memory Impedance Compensation:
I
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
Memory Channel A/B DIMM DQ Voltage Reference:
The output pins are connected to the MD/DIMMs, and holds
VDDQ/2 as reference voltage.
O
System Memory Power Gate Control: This signal
disables the platform memory VTT regulator in C8 and
deeper and S3 states.
SM_PG_CNTL1
CMOS OUTPUT
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Processors—Signal Description
6.3
Reset and Miscellaneous Signals
Table 31.
Reset and Miscellaneous Signals
Signal Name
Description
Direction /
Buffer Type
Configuration Signals: The CFG signals have a default value of
'1' if not terminated on the board.
•
CFG[2:0]: Reserved configuration lane. A test point may be
placed on the board for these lanes.
•
CFG[3]: MSR Privacy Bit Feature
— 1 = Debug capability is determined by
IA32_Debug_Interface_MSR (C80h) bit[0] setting
I/O
CFG[19:0]
— 0 = IA32_Debug_Interface_MSR (C80h) bit[0] default
setting overridden
GTL
•
•
CFG[4]: eDP enable
— 1 = Disabled
— 0 = Enabled
CFG[19:5]: Reserved configuration lanes. A test point may
be placed on the board for these lands.
Configuration resistance compensation. Use a 49.9 Ω ±1%
resistor to ground.
CFG_RCOMP
FC_x
—
FC (Future Compatibility) signals are signals that are available for
compatibility with other processors. A test point may be placed
on the board for these lands.
Signal is for IFDIM testing only.
I
IST_TRIGGER
CMOS
Signal is for debug. If both THERMTRIP# and this signal are
simultaneously asserted, the processor has encountered an
unrecoverable power delivery fault and has engaged automatic
shutdown as a result.
O
IVR_ERROR
CMOS
RESERVED: All signals that are RSVD and RSVD_NCTF must be
left unconnected on the board. Intel recommends that all
RSVD_TP signals have via test points.
No Connect
Test Point
RSVD
RSVD_TP
RSVD_NCTF
Non-Critical to
Function
TESTLO should be individually connected to VSS through a
resistor.
TESTLO_x
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Signal Description—Processors
6.4
embedded DisplayPort* (eDP*) Signals
Table 32.
embedded Display Port* Signals
Signal Name
Description
Direction / Buffer Type
eDP_TXP[3:0]
eDP_TXN[3:0]
embedded DisplayPort Transmit Differential Pair
embedded DisplayPort Auxiliary Differential Pair
embedded DisplayPort Current Compensation
O
eDP
eDP_AUXP
eDP_AUXN
O
eDP
I/O
A
eDP_RCOMP
Low voltage multipurpose DISP_UTIL pin on the
processor for backlight modulation control of
embedded panels and S3D device control for active
shutter glasses. This pin will co-exist with
functionality similar to existing BKLTCTL pin on the
PCH.
O
eDP_DISP_UTIL
Asynchronous CMOS
6.5
Display Interface Signals
Table 33.
Display Interface Signals
Signal Name
Description
Direction / Buffer
Type
DDIB_TXP[3:0]
DDIB_TXN[3:0]
Digital Display Interface Transmit Differential Pair
Digital Display Interface Transmit Differential Pair
O
DP*/HDMI*
DDIC_TXP[3:0]
DDIC_TXN[3:0]
O
DP*/HDMI*
6.6
Testability Signals
Table 34.
Testability Signals
Signal Name
Description
Direction / Buffer
Type
Breakpoint and Performance Monitor Signals:
Outputs from the processor that indicate the status of
breakpoints and programmable counters used for
monitoring processor performance.
I/O
BPM#[7:0]
CMOS
Processor Ready: This signal is a processor output
used by debug tools to determine processor debug
readiness.
O
PRDY#
PREQ#
Asynchronous CMOS
Processor Request: This signal is used by debug tools
to request debug operation of the processor.
I
Asynchronous CMOS
Test Clock: This signal provides the clock input for the
processor Test Bus (also known as the Test Access
Port). This signal must be driven low or allowed to float
during power on Reset.
I
PROC_TCK
PROC_TDI
GTL
Processor Test Data In: This signal transfers serial
test data into the processor. This signal provides the
serial input needed for JTAG specification support.
I
GTL
continued...
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Processors—Signal Description
Signal Name
Description
Direction / Buffer
Type
Processor Test Data Out: This signal transfers serial
test data out of the processor. This signal provides the
serial output needed for JTAG specification support.
O
PROC_TDO
Open Drain
Processor Test Mode Select: This is a JTAG
specification supported signal used by debug tools.
I
PROC_TMS
GTL
Processor Test Reset: This signal resets the Test
Access Port (TAP) logic. This signal must be driven low
during power on Reset.
I
PROC_TRST#
GTL
6.7
Error and Thermal Protection Signals
Table 35.
Error and Thermal Protection Signals
Signal Name
Description
Direction / Buffer
Type
Catastrophic Error: This signal indicates that the system has
experienced a catastrophic error and cannot continue to
operate. The processor will set this for non-recoverable
machine check errors or other unrecoverable internal errors.
CATERR# is used for signaling the following types of errors:
Legacy MCERRs, CATERR# is asserted for 16 BCLKs. Legacy
IERRs, CATERR# remains asserted until warm or cold reset.
O
CATERR#
GTL
Platform Environment Control Interface: A serial
sideband interface to the processor, it is used primarily for
thermal, power, and error management.
I/O
PECI
Asynchronous
Processor Hot: PROCHOT# goes active when the processor
temperature monitoring sensor(s) detects that the processor
has reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit (TCC) has
been activated, if enabled. This signal can also be driven to
the processor to activate the TCC.
GTL Input
Open-Drain Output
PROCHOT#
Thermal Trip: The processor protects itself from catastrophic
overheating by use of an internal thermal sensor. This sensor
is set well above the normal operating temperature to ensure
that there are no false trips. The processor will stop all
execution when the junction temperature exceeds
approximately 130 °C. This is signaled to the system by the
THERMTRIP# pin.
O
Asynchronous OD
THERMTRIP#
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6.8
Power Sequencing Signals
Table 36.
Power Sequencing Signals
Signal Name
Description
Direction / Buffer
Type
The processor requires this input signal to be a clean
indication that the VCC and VDDQ power supplies are
stable and within specifications. This requirement
applies regardless of the S-state of the processor.
'Clean' implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the
time that the power supplies are turned on until the
supplies come within specification. The signal must
then transition monotonically to a high state.
I
PROCPWRGD
Asynchronous CMOS
The processor requires this input signal to be a clean
indication that the VCCST and VDDQ power supplies are
stable and within specifications. This single must have
a valid level during both S0 and S3 power states.
'Clean' implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the
time that the power supplies are turned on until the
supplies come within specification. The signal must
then transition monotonically to a high state."
I
VCCST_PWRGD
PROC_DETECT#
Asynchronous CMOS
(Processor Detect): This signal is pulled down
directly (0 Ohms) on the processor package to ground.
There is no connection to the processor silicon for this
signal. System board designers may use this signal to
determine if the processor is present.
—
6.9
Processor Power Signals
Table 37.
Processor Power Signals
Signal Name
Description
Direction / Buffer
Type
VCC
Processor main power rail.
Ref
Ref
Ref
Processor I/O supply voltage for DDR3L/DDR3L-RS/
LPDDR3.
VDDQ
VCCST
Sustain voltage for the processor in standby modes
VIDALERT#, VIDSCLK, and VIDSCLK comprise a three
signal serial synchronous interface used to transfer
power management information between the
processor and the voltage regulator controllers.
VIDSOUT
VIDSCLK
I/O CMOS
O CMOS
I CMOS
VIDALERT#
Sideband output from the processor which controls
disabling of the VR when the processor is in the C10
state. This signal will be used to disable the VR only if
the processor is configured to support VR disabling
using VR_CURRENT_CONFIG MSR (601h).
O
VR_EN
VR Enable CMOS
Sideband signal which indicates to the processor that
the external voltage regulator for the VCC power rail is
valid.
I
VR_READY
CMOS
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Processors—Signal Description
6.10
Sense Signals
Table 38.
Sense Signals
Signal Name
Description
Direction /
Buffer Type
VCC_SENSE and VSS_SENSE provide an isolated, low-
impedance connection to the processor input VCC voltage
and ground. The signals can be used to sense or measure
voltage near the silicon.
VCC_SENSE
VSS_SENSE
O
A
6.11
Ground and Non-Critical to Function (NCTF) Signals
Table 39.
Ground and Non-Critical to Function (NCTF) Signals
Signal Name
Description
Direction /
Buffer Type
VSS
Processor ground node
GND
—
Non-Critical to Function: These signals are for package
mechanical reliability.
VSS_NCTF
Daisy Chain Non-Critical to Function: These signals are
for BGA solder joint reliability testing and are non-critical to
function.
These signals are connected on the processor package as
follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Package A1 Corner
DAISY_CHAIN_NCTF_B2 to DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2 to DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_A3 to DAISY_CHAIN_NCTF_A4
Package A63 Corner
DAISY_CHAIN_NCTF_A62 to DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_B61 to DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63 to DAISY_CHAIN_NCTF_A60
Package AY1 Corner
DAISY_CHAIN_NCTF_[Ball #]
DAISY_CHAIN_NCTF_AW1 to DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AY3 to DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AY2 to DAISY_CHAIN_NCTF_AV1
Package AY63 Corner
DAISY_CHAIN_NCTF_AY60 to
DAISY_CHAIN_NCTF_AW61
•
•
DAISY_CHAIN_NCTF_AY61 to
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AY62 to
DAISY_CHAIN_NCTF_AW63
6.12
Processor Internal Pull-Up / Pull-Down Terminations
Table 40.
Processor Internal Pull-Up / Pull-Down Terminations
Signal Name
BPM[7:0]
Pull Up / Pull Down
Pull Up
Rail
VccIO
VccIO
VccST
Value
40–60 Ω
40–60 Ω
30–70 Ω
PREQ#
Pull Up
PROC_TDI
Pull Up
continued...
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Signal Description—Processors
Signal Name
Pull Up / Pull Down
Pull Up
Rail
VccST
VccST
VccST
Value
30–70 Ω
5–8 kΩ
30–70 Ω
PROC_TMS
CFG[19:0]
CATERR#
Pull Up
Pull Up
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Processors—Electrical Specifications
7.0
Electrical Specifications
This chapter provides the processor electrical specifications including integrated
voltage regulator (VR), VCC Voltage Identification (VID), reserved and unused signals,
signal groups, Test Access Points (TAP), and DC specifications.
7.1
Integrated Voltage Regulator
A new feature to the processor is the integration of platform voltage regulators into
the processor. Due to this integration, the processor has one main voltage rail (VCC)
and a voltage rail for the memory interface (VDDQ) , compared to six voltage rails on
previous processors. The VCC voltage rail will supply the integrated voltage regulators
which in turn will regulate to the appropriate voltages for the cores, cache, system
agent, and graphics. This integration allows the processor to better control on-die
voltages to optimize between performance and power savings. The processor VCC rail
will remain a VID-based voltage with a loadline similar to the core voltage rail (also
called VCC) in previous processors.
7.2
7.3
Power and Ground Pins
The processor has VCC, VDDQ, and VSS (ground) pins for on-chip power distribution.
All power pins must be connected to their respective processor power planes; all VSS
pins must be connected to the system ground plane. Use of multiple power and
ground planes is recommended to reduce I*R drop. The VCC pins must be supplied
with the voltage determined by the processor Serial Voltage IDentification (SVID)
interface. Table 41 on page 83 specifies the voltage level for the various VIDs.
VCC Voltage Identification (VID)
The processor uses three signals for the serial voltage identification interface to
support automatic selection of voltages. The following table specifies the voltage level
corresponding to the 8-bit VID value transmitted over serial VID. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
must disable itself. VID signals are CMOS push/pull drivers. See Table 50 on page
95 for the DC specifications for these signals. The VID codes will change due to
temperature and/or current load changes to minimize the power of the part. A voltage
range is provided in Voltage and Current Specifications on page 90. The
specifications are set so that one voltage regulator can operate with all supported
frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in Voltage and Current Specifications on page 90. The
processor provides the ability to operate while transitioning to an adjacent VID and its
associated voltage. This will represent a DC shift in the loadline.
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Electrical Specifications—Processors
Table 41.
Voltage Regulator (VR) 12.5 Voltage Identification
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
Hex
VCC
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
B
i
t
Hex
VCC
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
00h
0.0000
0.5000
0.5100
0.5200
0.5300
0.5400
0.5500
0.5600
0.5700
0.5800
0.5900
0.6000
0.6100
0.6200
0.6300
0.6400
0.6500
0.6600
0.6700
0.6800
0.6900
0.7000
0.7100
0.7200
0.7300
0.7400
0.7500
0.7600
0.7700
0.7800
0.7900
0.8000
0.8100
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
21h
0.8200
0.8300
0.8400
0.8500
0.8600
0.8700
0.8800
0.8900
0.9000
0.9100
0.9200
0.9300
0.9400
0.9500
0.9600
0.9700
0.9800
0.9900
1.0000
1.0100
1.0200
1.0300
1.0400
1.0500
1.0600
1.0700
1.0800
1.0900
1.1000
1.1100
1.1200
1.1300
1.1400
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
83
Processors—Electrical Specifications
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7
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1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
42h
1.1500
1.1600
1.1700
1.1800
1.1900
1.2000
1.2100
1.2200
1.2300
1.2400
1.2500
1.2600
1.2700
1.2800
1.2900
1.3000
1.3100
1.3200
1.3300
1.3400
1.3500
1.3600
1.3700
1.3800
1.3900
1.4000
1.4100
1.4200
1.4300
1.4400
1.4500
1.4600
1.4700
1.4800
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64h
1.4900
1.5000
1.5100
1.5200
1.5300
1.5400
1.5500
1.5600
1.5700
1.5800
1.5900
1.6000
1.6100
1.6200
1.6300
1.6400
1.6500
1.6600
1.6700
1.6800
1.6900
1.7000
1.7100
1.7200
1.7300
1.7400
1.7500
1.7600
1.7700
1.7800
1.7900
1.8000
1.8100
1.8200
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
80h
81h
82h
83h
84h
85h
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
84
December 2013
Order No.: 329001-005
Electrical Specifications—Processors
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1
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1
1
1
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1
1
1
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1
1
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0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
86h
1.8300
1.8400
1.8500
1.8600
1.8700
1.8800
1.8900
1.9000
1.9100
1.9200
1.9300
1.9400
1.9500
1.9600
1.9700
1.9800
1.9900
2.0000
2.0100
2.0200
2.0300
2.0400
2.0500
2.0600
2.0700
2.0800
2.0900
2.1000
2.1100
2.1200
2.1300
2.1400
2.1500
2.1600
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A8h
2.1700
2.1800
2.1900
2.2000
2.2100
2.2200
2.2300
2.2400
2.2500
2.2600
2.2700
2.2800
2.2900
2.3000
2.3100
2.3200
2.3300
2.3400
2.3500
2.3600
2.3700
2.3800
2.3900
2.4000
2.4100
2.4200
2.4300
2.4400
2.4500
2.4600
2.4700
2.4800
2.4900
2.5000
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
85
Processors—Electrical Specifications
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7
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1
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1
1
1
1
1
1
1
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1
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1
1
1
1
1
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1
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1
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CAh
2.5100
2.5200
2.5300
2.5400
2.5500
2.5600
2.5700
2.5800
2.5900
2.6000
2.6100
2.6200
2.6300
2.6400
2.6500
2.6600
2.6700
2.6800
2.6900
2.7000
2.7100
2.7200
2.7300
2.7400
2.7500
2.7600
2.7700
2.7800
2.7900
2.8000
2.8100
2.8200
2.8300
2.8400
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ECh
2.8500
2.8600
2.8700
2.8800
2.8900
2.9000
2.9100
2.9200
2.9300
2.9400
2.9500
2.9600
2.9700
2.9800
2.9900
3.0000
3.0100
3.0200
3.0300
3.0400
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
continued...
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Electrical Specifications—Processors
7.4
Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
•
•
•
RSVD – these signals should not be connected
RSVD_TP – these signals should be routed to a test point
RSVD_NCTF – these signals are non-critical to function and may be left un-
connected
Arbitrary connection of these signals to VCC, VDDQ, VSS, or to any other signal
(including each other) may result in component malfunction or incompatibility with
future processors. See Signal Description on page 72 for a pin listing of the processor
and the location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
7.5
Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in the following
table. The buffer type indicates which signaling technology and specifications apply to
the signals. All the differential signals and selected DDR3L/DDR3L-RS/LPDDR3 and
Control Sideband signals have On-Die Termination (ODT) resistors. Some signals do
not have ODT and need to be terminated on the board.
Note:
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least 10 BCLKs with maximum Trise/Tfall of 6 ns for the processor to recognize the
proper signal state. See the DC Specifications section and AC Specifications section.
Table 42.
Signal Groups
Signal Group
Type
Signals
DDR3L / DDR3L-RS / LPDDR3 Reference Clocks 2
Differential
DDR3L/DDR3L-RS/ SA_CKP[1:0], SA_CKN[1:0], SB_CKP[1:0], SB_CKN[1:0]
LPDDR3 Output
DDR3L / DDR3L-RS/LPDDR3 Command Signals 2
Single ended
DDR3L/DDR3L-RS/ DDR3L/DDR3L-RS Mode
LPDDR3 Output
LPDDR3 Mode
SA_BS2, SB_BS2
SA_BS1, SB_BS1
SA_BS0, SB_BS0
SA_WE#, SB_WE#
SA_RAS#, SB_RAS#
SA_CAS#, SB_CAS#
SA_CAA5, SB_CAA5
SA_CAB6, SB_CAB6
SA_CAB4, SB_CAB4
SA_CAB2, SB_CAB2
SA_CAB3, SB_CAB3
SA_CAB1, SB_CAB1
continued...
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Signal Group
Type
Signals
SA_MA15, SB_MA15
SA_MA14, SB_MA14
SA_MA13, SB_MA13
SA_MA12, SB_MA12
SA_MA11, SB_MA11
SA_MA10, SB_MA10
SA_MA9, SB_MA9
SA_MA8, SB_MA8
SA_MA7, SB_MA7
SA_MA6, SB_MA6
SA_MA5, SB_MA5
SA_MA4, SB_MA4
SA_MA3, SB_MA3
SA_MA2, SB_MA2
SA_MA1, SB_MA1
SA_MA0, SB_MA0
SA_CAA8, SB_CAA8
SA_CAA9, SB_CAA9
SA_CAB0, SB_CAB0
SA_CAA6, SB_CAA6
SA_CAA7, SB_CAA7
SA_CAB7, SB_CAB7
SA_CAA1, SB_CAA1
SA_CAA3, SB_CAA3
SA_CAA4, SB_CAA4
SA_CAA2, SB_CAA2
SA_CAA0, SB_CAA0
N/A
N/A
SA_CAB5, SB_CAB5
SA_CAB8, SB_CAB8
SA_CAB9, SB_CAB9
DDR3L / DDR3L-RS Control Signals 2
Single ended
DDR3L/DDR3L-RS
Output
SA_CKE[3:0], SB_CKE[3:0], SA_CS#[1:0], SB_CS#[1:0],
SA_ODT0, SB_ODT0, SM_PG_CNTL1
DDR3L / DDR3L-RS Data Signals 2
Single ended
DDR3L/DDR3L-RS
Bi-directional
SA_DQ[63:0], SB_DQ[63:0]
Differential
DDR3L/DDR3L-RS
Bi-directional
SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0], SB_DQSN[7:0]
DDR3L / DDR3L-RS Reference Voltage Signals
DDR3L/DDR3L-RS
Output
SM_VREF_CA, SM_VREF_DQ1, SM_VREF_DQ0
Testability (ITP/XDP)
Single ended
Single ended
Single ended
Single ended
Single ended
Control Sideband
Single ended
GTL Input
GTL
PROC_TCK, PROC_TDI, PROC_TMS, PROC_TRST#
PROC_TDO
BPM#[7:0]
PREQ#
GTL
GTL
GTL
PRDY#
GTL Input/Open
Drain Output
PROCHOT#
IVR_ERROR
THERMTRIP#
Single ended
Single ended
Asynchronous
CMOS Output
Open Drain Output
continued...
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Signal Group
Single ended
Type
Signals
GTL
CATERR#
Single ended
Asynchronous
CMOS Input
RESET#, PROCPWRGD, PWR_DEBUG# , VCCST_PWRGD
Single ended
Asynchronous Bi-
directional
PECI
Single ended
GTL Bi-directional
CFG[19:0]
Voltage Regulator
Single ended
VR Enable CMOS
Output
VR_EN
Single ended
Single ended
Single ended
Single ended
Differential
CMOS Input
VR_READY
CMOS Input
VIDALERT#
Open Drain Output
CMOS I/O
VIDSCLK
VIDSOUT
Analog Output
VCC_SENSE, VSS_SENSE
Power / Ground / Other
Single ended Power
VCC, VDDQ, VCCST
VSS, VSS_NCTF 3
RSVD, RSVD_NCTF
RSVD_TP
Ground
No Connect
Test Point
Other
DAISY_CHAIN_NCTF_[ball #]
Digital Display Interface
Differential DDI Output
DDIB_TXP[3:0], DDIB_TXN[3:0], DDIC_TXP[3:0],
DDIC_TXN[3:0]]
Notes: 1. See Signal Description on page 72 for signal description details.
2. SA and SB refer to DDR3L/DDR3L-RS Channel A and DDR3L/DDR3L-RS Channel B.
7.6
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port
(TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any
other components within the system. A translation buffer should be used to connect to
the rest of the chain unless one of the other components is capable of accepting an
input of the appropriate voltage. Two copies of each signal may be required with each
driving a different voltage level.
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE
1149.6-2003 standards. A few of the I/O pins may support only one of those
standards.
7.7
DC Specifications
The processor DC specifications in this section are defined at the processor pins,
unless noted otherwise. See Signal Description on page 72 for the processor pin
listings and signal definitions.
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Processors—Electrical Specifications
•
•
The DC specifications for the DDR3L/DDR3L-RS/LPDDR3 signals are listed in the
Voltage and Current Specifications section.
The Voltage and Current Specifications section lists the DC specifications for the
processor and are valid only while meeting specifications for junction temperature,
clock frequency, and input voltages. Read all notes associated with each
parameter.
•
AC tolerances for all DC rails include dynamic load currents at switching
frequencies up to 1 MHz.
7.8
Voltage and Current Specifications
Table 43.
Processor Core Active and Idle Mode DC Voltage and Current Specifications
Symbol
Parameter
Segment
Min
Typ
Max
Unit
Note1
Voltage Range for
Processor Active
Operating Mode
Operating
Voltage
All
1.6
—
1.84
V
1, 2, 7
Voltage Range for
Processor Idle Mode All
(Package C6/C7)
Idle Voltage
1.5
—
—
—
—
1.65
40
V
A
1, 2, 7
U-
Processors
28W
U-
Processors
Maximum Processor
Core ICC
—
32
ICCMAX
4, 6, 7
15W
Y-Processors
11.5W (6W
SDP / 4.5W
SDP)
—
—
25
PS0, PS1
PS2, PS3
PS0
—
—
—
—
—
—
—
—
—
—
—
—
±20
±20
TOLVCC
Ripple
Voltage Tolerance
Ripple Tolerance
mV
mV
6, 8
6, 8
±15
PS1
±15
PS2
+50/-15
+60/-15
PS3
Loadline slope
within the VR
regulation loop
capability
R_DC_LL
R_AC_LL
—
—
—
—
- 2.0
- 7.0
—
—
mV
mΩ
—
—
Loadline slope in
response to
dynamic load
increase events
continued...
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Symbol
Parameter
Segment
Min
—
Typ
—
Max
500
200
Unit
μs
Note1
—
Max Overshoot
time
T_OVS_Max
V_OVS
—
Max Overshoot
—
—
—
mV
—
Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or
empirical data.
2. Each processor is programmed with a maximum valid voltage identification value (VID) that is
set at manufacturing and cannot be altered. Individual maximum VID values are calibrated
during manufacturing such that two processors at the same frequency may have different
settings within the VID range. Note that this differs from the VID employed by the processor
during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep
Technology, or Low-Power States).
3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands
at the socket with a 20 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1
MΩ minimum impedance. The maximum length of ground wire on the probe should be less than
5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
4. Processor core VR to be designed to electrically support this current.
5. Processor core VR to be designed to thermally support this current indefinitely.
6. Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are
violated.
7. Long term reliability cannot be assured in conditions above or below Maximum/Minimum
functional limits.
8. PSx refers to the voltage regulator power state as set by the SVID protocol.
Table 44.
Memory Controller (VDDQ) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
Processor I/O supply
voltage for DDR3L/DDR3L-
RS
VDDQ (DDR3L/DDR3L-RS)
—
1.35
—
V
2, 3
Processor I/O supply
voltage for LPDDR3
VDDQ (LPDDR3)
TOLDDQ
—
-5
—
—
1.20
—
—
5
V
%
A
2, 3
2, 3
1
VDDQ Tolerance (AC+DC)
IccMAX_VDDQ (DDR3L/
DDR3L-RS)
Max Current for VDDQ Rail
(DDR3L/DDR3L-RS)
—
1.4
1.1
Max Current for VDDQ Rail
(LPDDR3)
—
A
1
IccMAX_VDDQ (LPDDR3)
Notes: 1. The current supplied to the DIMM modules is not included in this specification.
2. Includes AC and DC error, where the AC noise is bandwidth limited to under 20 MHz.
3. No requirement on the breakdown of AC versus DC noise.
Table 45.
Vcc Sustain (VccST) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
Processor Vcc Sustain
supply voltage
VccST
- 5%
1.05
+ 5%
V
Maximum Current for
VccST
IccMAX_VccST
—
—
100
mA
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Table 46.
DDR3L / DDR3L-RS Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Input High Voltage
Min
—
Typ
Max
0.43*VDDQ
—
Units
Notes1
2, 4, 11
3, 11
VIL
VDDQ/2
VDDQ/2
V
V
VIH
0.57*VDDQ
Input Low Voltage
(SM_DRAMPWROK)
VIL
—
—
—
0.15*VDDQ
1.0
V
V
—
Input High Voltage
(SM_DRAMPWROK)
VIH
0.45*VDDQ
10, 12
DDR3L/DDR3L-RS Data
Buffer pull-up
Resistance
RON_UP(DQ)
20
20
26
32
Ω
5, 11
DDR3L/DDR3L-RS Data
Buffer pull-down
Resistance
RON_DN(DQ)
26
50
32
62
Ω
Ω
5, 11
11
DDR3L/DDR3L-RS On-
die termination
equivalent resistance
for data signals
RODT(DQ)
38
DDR3L/DDR3L-RS On-
die termination DC
working point (driver
set to receive mode)
VODT(DC)
0.45*VDDQ
0.5*VDDQ
0.55*VDDQ
V
11
DDR3L/DDR3L-RS Clock
Buffer pull-up
Resistance
5, 11,
13
RON_UP(CK)
20
20
15
15
19
19
40
40
26
26
20
20
25
25
80
80
32
32
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
DDR3L/DDR3L-RS Clock
Buffer pull-down
Resistance
5, 11,
13
RON_DN(CK)
DDR3L/DDR3L-RS
Command Buffer pull-
up Resistance
5, 11,
13
RON_UP(CMD)
RON_DN(CMD)
RON_UP(CTL)
25
DDR3L/DDR3L-RS
Command Buffer pull-
down Resistance
5, 11,
13
25
DDR3L/DDR3L-RS
Control Buffer pull-up
Resistance
5, 11,
13
31
DDR3L/DDR3L-RS
Control Buffer pull-down
Resistance
5, 11,
13
RON_DN(CTL)
31
System Memory Power
Gate Control Buffer
Pull-Up Resistance
RON_UP(SM_PG_CNTL1)
130
130
13
13
System Memory Power
RON_DN(SM_PG_CNTL1) Gate Control Buffer
Pull-Down Resistance
Input Leakage Current
(DQ, CK)
0V
ILI
—
—
0.7
mA
—
0.2*VDDQ
0.8*VDDQ
continued...
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Electrical Specifications—Processors
Symbol
Parameter
Min
Typ
Max
Units
Notes1
Input Leakage Current
(CMD, CTL)
0V
ILI
—
—
1.0
mA
—
0.2*VDDQ
0.8*VDDQ
Command COMP
Resistance
SM_RCOMP0
198
200
202
Ω
8
SM_RCOMP1
SM_RCOMP2
Data COMP Resistance
ODT COMP Resistance
118.8
99
120
100
121.2
101
Ω
Ω
8
8
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a
logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a
logical high value.
4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply
with the signal quality specifications.
5. This is the pull up/down driver resistance.
6. RTERM is the termination on the DIMM and in not controlled by the processor.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the
two sets.
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx
resistors are to VSS
.
9. SM_DRAMPWROK rise and fall time must be < 50 ns measured between VDDQ *0.15 and VDDQ
*0.47.
10.SM_VREF is defined as VDDQ/2.
11.Maximum-minimum range is correct; however, center point is subject to change during MRC
boot training.
12.Processor may be damaged if VIH exceeds the maximum voltage for extended periods.
13.The MRC during boot training might optimize RON outside the range specified.
Table 47.
LPDDR3 Signal Group DC Specifications
Symbol
VIL
Parameter
Input Low Voltage
Input High Voltage
Min
—
Typ.
Max
0.43*VDDQ
—
Unit
V
Note
2, 4, 12
3, 11
VDDQ /2
VDDQ /2
VIH
VIL
0.57*VDDQ
V
Input Low Voltage
(SM_DRAMPWROK)
—
0.45*VDDQ
30
—
—
0.15*VDDQ
1.0*VDDQ
50
V
V
—
Input High Voltage
(SM_DRAMPWROK)
VIH
10, 12
5, 11
5, 11
LPDDR3 Data Buffer pull-
up Resistance
RON_UP(DQ)
40
40
Ω
Ω
LPDDR3 Data Buffer pull-
down Resistance
RON_DN(DQ)
30
50
LPDDR3 On-die
termination equivalent
resistance for data signals
RODT(DQ)
150
200
250
Ω
11
LPDDR3 On-die
termination DC working
point (driver set to receive
mode)
VODT(DC)
0.45*VDDQ
0.5*VDDQ
0.55*VDDQ
V
11
LPDDR3 Clock Buffer pull-
up Resistance
RON_UP(CK)
30
40
50
Ω
5, 11
continued...
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Processors—Electrical Specifications
Symbol
Parameter
Min
Typ.
Max
Unit
Note
LPDDR3 Clock Buffer pull-
down Resistance
RON_DN(CK)
30
40
50
Ω
5, 11
LPDDR3 Command Buffer
pull-up Resistance
RON_UP(CMD)
RON_DN(CMD)
RON_UP(CTL)
RON_DN(CTL)
RON_UP(RST)
RON_DN(RST)
19
19
19
19
40
40
25
25
25
25
80
80
31
31
Ω
Ω
Ω
Ω
Ω
Ω
5, 11
5, 11
5, 11
5, 11
—
LPDDR3 Command Buffer
pull-down Resistance
LPDDR3 Control Buffer
pull-up Resistance
31
LPDDR3 Control Buffer
pull-down Resistance
31
LPDDR3 Reset Buffer pull-
up Resistance
130
130
LPDDR3 Reset Buffer pull-
up Resistance
—
Input Leakage Current
(DQ, CK)
0V
ILI
—
—
—
—
0.4
0.6
mA
mA
—
—
0.2* VDDQ
0.8*VDDQ
Input Leakage Current
(CMD,CTL)
0V
ILI
0.2*VDDQ
0.8*VDDQ
SM_RCOMP0
SM_RCOMP1
ODT COMP Resistance
Data COMP Resistance
198
200
120
202
Ω
Ω
8
8
118.8
121.2
Command COMP
Resistance
SM_RCOMP2
99
100
101
Ω
8
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a
logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a
logical high value.
4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply
with the signal quality specifications.
5. This is the pull up/down driver resistance.
6. RTERM is the termination on the DIMM and in not controlled by the processor.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the
two sets.
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx
resistors are to VSS
.
9. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDDQ * 0.30 ±100 mV
and the edge must be monotonic.
10.SM_VREF is defined as VDDQ/2
11.Maximum-minimum range is correct; however, center point is subject to change during MRC
boot training.
12.Processor may be damaged if VIH exceeds the maximum voltage for extended periods.
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Electrical Specifications—Processors
Table 48.
Digital Display Interface Group DC Specifications
Symbol
VIL
Parameter
HPD Input Low Voltage
Min
—
Typ
—
Max
0.8
Units
V
V
VIH
HPD Input High Voltage
2.25
—
3.6
Aux peak-to-peak voltage at transmitting
device
Vaux(Tx)
0.39
0.32
—
—
1.38
1.36
V
V
Aux peak-to-peak voltage at receiving
device
Vaux(Rx)
Table 49.
embedded DisplayPort* (eDP*) Group DC Specifications
Symbol
Parameter
Min
0.1*VCC
0.9*VCC
100
Typ
—
Max
—
Units
VOL
VOH
RUP
eDP_DISP_UTIL Output Low Voltage
eDP_DISP_UTIL Output High Voltage
eDP_DISP_UTIL Internal pull-up
eDP_DISP_UTIL Internal pull-down
V
V
—
—
—
—
Ω
Ω
RDOWN
100
—
—
Aux peak-to-peak voltage at
transmitting device
Vaux(Tx)
0.39
—
1.38
V
Aux peak-to-peak voltage at receiving
device
Vaux(Rx)
0.32
—
1.36
V
eDP_RCOMP
COMP Resistance
24.75
25
25.25
Ω
Note: 1. COMP resistance is to VCOMP_OUT.
Table 50.
CMOS Signal Group DC Specifications
Symbol
Parameter
Min
Max
Units
Notes1
2
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Buffer on Resistance
—
VccST* 0.7
—
VccST* 0.3
V
V
V
V
Ω
VIH
VOL
VOH
RON
—
2, 4
2
VccST * 0.1
VccST * 0.9
23
—
2, 4
73
Input Leakage
Current
ILI
—
±150
μA
3
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VccST referred to in these specifications refers to instantaneous VCCIO_OUT.
3. For VIN between “0” V and VccST. Measured when the driver is tri-stated.
4. VIH and VOH may experience excursions above VccST . However, input signal drivers must comply
with the signal quality specifications.
Table 51.
GTL Signal Group and Open Drain Signal Group DC Specifications
Symbol
Parameter
Min
Max
Units
Notes1
Input Low Voltage (TAP, except
PROC_TCK, PROC_TRST#)
VIL
—
VccST * 0.6
V
2
Input High Voltage (TAP, except
PROC_TCK, PROC_TRST#)
VIH
VccST * 0.72
—
V
2, 4
continued...
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Processors—Electrical Specifications
Symbol
VIL
Parameter
Min
Max
Units
Notes1
Input Low Voltage (PROC_TCK,
PROC_TRST#)
—
VccST * 0.3
V
2
Input High Voltage (PROC_TCK,
PROC_TRST#)
VIH
VccST * 0.7
—
V
2, 4
VHYSTERESIS
RON
Hysteresis Voltage
VccST * 0.2
—
V
Ω
V
—
—
Buffer on Resistance (TDO)
Input Low Voltage (other GTL)
Input High Voltage (other GTL)
Buffer on Resistance (CFG/BPM)
Buffer on Resistance (other GTL)
Input Leakage Current
7
17
VccST * 0.6
—
VIL
—
2
VIH
VccST * 0.72
V
2, 4
—
RON
16
12
—
24
Ω
Ω
μA
RON
28
—
ILI
±150
3
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The VccST referred to in these specifications refers to instantaneous VccST
.
3. For VIN between 0 V and VccST. Measured when the driver is tri-stated.
4. VIH and VOH may experience excursions above VccST. However, input signal drivers must comply
with the signal quality specifications.
Table 52.
Table 53.
VR Enable CMOS Signal Group DC Specification
Symbol
Parameter
Buffer on Resistance
Hysteresis Voltage
Min
Max
Units
Notes
RON
VHYSTERESIS
30
70
Ω
0.15*
VccST
—
V
VCOMP_OUT and VCCIO_TERM
Symbol
VCOMP_OUT
VCCIO_TERM
Parameter
Termination Voltage
Termination Voltage
Typ
1.0
1.0
Max
—
Units
Notes
1, 3, 4
2
V
V
—
Notes: 1. VCOMP_OUT may only be used to connect eDP_RCOMP.
2. Internal processor power for signal termination.
7.8.1
Platform Environment Control Interface (PECI) DC
Characteristics
The PECI interface operates at a nominal voltage set by VccST. The set of DC electrical
specifications shown in the following table is used with devices normally operating
from a VccST interface supply.
VccST nominal levels will vary between processor families. All PECI devices will operate
at the VccST level determined by the processor installed in the system.
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Electrical Specifications—Processors
Table 54.
Platform Environment Control Interface (PECI) DC Electrical Limits
Symbol
Definition and Conditions
Internal pull up resistance
Input Voltage Range
Hysteresis
Min
15
Max
45
Units
Notes1
Rup
Vin
Ω
V
V
3
-0.15
VccST
N/A
—
—
Vhysteresis
Vn
0.1 * VccST
Negative-Edge Threshold
Voltage
0.500
0.275 * VccST
0.550 * VccST
V
V
—
—
* VccST
Positive-Edge Threshold
Voltage
Vp
0.725 * VccST
Cbus
Bus Capacitance per Node
Pad Capacitance
N/A
0.7
—
10
1.8
0.6
pF
pF
—
—
—
Cpad
Ileak000
leakage current at 0 V
mA
leakage current at 0.25*
VccST
Ileak025
Ileak050
—
—
0.4
0.2
mA
mA
—
—
leakage current at 0.50*
VccST
leakage current at 0.75*
VccST
Ileak075
Ileak100
—
—
0.13
0.10
mA
mA
—
—
leakage current at VccST
Notes: 1. VccST supplies the PECI interface. PECI behavior does not affect VccST minimum / maximum
specifications.
2. The leakage specification applies to powered devices on the PECI bus.
3. The PECI buffer internal pull-up resistance measured at 0.75* VccST
.
7.8.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use the following figure as a guide for input
buffer design.
Figure 13.
Input Device Hysteresis
VTTD
Maximum VP
Minimum VP
PECI High Range
Minimum
Valid Input
Hysteresis
Signal Range
Maximum VN
Minimum VN
PECI Ground
PECI Low Range
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Processors—Package Specifications
8.0
Package Specifications
8.1
Package Mechanical Attributes
The U-Processor line and Y-Processor line use a Flip Chip technology and Multi-Chip
package (MCP) available in a Ball Grid Array (BGA) package. The following table
provides an overview of the mechanical attributes of this package.
Table 55.
Package Mechanical Attributes
Parameter
U-Processor Line and Y-Processor Line
Package Type
Interconnect
Lead Free
Flip Chip Ball Grid Array
Ball Grid Array (BGA)
Package
Technology
Yes
Halogenated Flame Retardant Free
Solder Ball Composition
Ball/Pin Count
Yes
SAC 405
1168
Grid Array Pattern
Balls Anywhere
Package
Configuration
Land Side Capacitors
Die Side Capacitors
Die Configuration
Yes
No
Multi-Chip Package (MCP) / 2 dies
40.0 mm x 24.0 mm
0.65 mm
Nominal Package Size
Min Ball/Pin pitch
Package
Dimensions
8.2
Package Loading Specifications
Table 56.
Package Loading Specifications
Maximum Static Normal Load
U-Processor Line
Limit
Notes
1, 2, 3
1, 2, 3
67 N (15 lbf)
22 N (15 lbf)
Y-Processor Line
U-Processor Line/ Y-Processor Line
BGA
67 N (15 lbf)
1, 2, 3
Notes: 1. The thermal solution attach mechanism must not induce continuous stress to the package. It
may only apply a uniform load to the die to maintain a thermal interface.
2. This specification applies to the uniform compressive load in the direction perpendicular to the
dies’ top surface.
3. This specification is based on limited testing for design characterization.
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Package Specifications—Processors
8.3
Package Storage Specifications
Table 57.
Package Storage Specifications
Parameter
Description
Min
Max
Notes
The non-operating device storage temperature.
Damage (latent or otherwise) may occur when
subjected to this temperature for any length of
time.
TABSOLUTE STORAGE
-25 °C
125 °C
1, 2, 3
The ambient storage temperature limit (in
shipping media) for a sustained period of time.
TSUSTAINED STORAGE
-5 °C
40 °C
4, 5
5, 6
6
The maximum device storage relative humidity for
a sustained period of time.
RHSUSTAINED STORAGE
60% @ 24 °C
A prolonged or extended period of time: typically
associated with customer shelf life.
0
6
TIMESUSTAINED STORAGE
months
months
Notes: 1. Refers to a component device that is not assembled in a board or socket that is not to be
electrically connected to a voltage reference or I/O signals.
2. Specified temperatures are based on data collected. Exceptions for surface mount reflow are
specified by applicable JEDEC standards.
3. TABSOLUTE STORAGE applies to the unassembled component only and does not apply to the shipping
media, moisture barrier bags or desiccant.
4. Intel-branded board products are certified to meet the following temperature and humidity limits
that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C, Humidity
50% to 90%, non-condensing with a maximum wet bulb of 28 °C). Post board attach storage
temperature limits are not specified for non-Intel branded boards.
5. The JEDEC, J-JSTD-020 moisture level rating and associated handling practices apply to all
moisture sensitive devices removed from the moisture barrier bag.
6. Nominal temperature and humidity conditions and durations are given and tested within the
constraints imposed by TSUSTAINED STORAGE and customer shelf life in applicable Intel boxes and
bags.
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Processors—Processor Ball and Signal Information
9.0
Processor Ball and Signal Information
This chapter provides the processor Ball information.
Table 58.
Ball List by Signal Name for DDR3L Configuration
Signal Name
Ball #
AJ8
Signal Name
CFG[4]
Ball #
AA60
Signal Name
Ball #
ACPRESENT /
GPIO31
DAISY_CHAIN_NCT A3
F_A3
CFG[5]
Y62
Y61
Y60
V62
V61
V63
AF2
AD2
AF4
APWROK
AB5
AN4
DAISY_CHAIN_NCT A4
F_A4
CFG[6]
BATLOW# /
GPIO72
CFG[7]
DAISY_CHAIN_NCT A60
F_A60
CFG[8]
BMBUSY# /
GPIO76
P1
DAISY_CHAIN_NCT A61
F_A61
CFG[9]
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
CATERR#
CFG[0]
CFG[1]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG[2]
CFG[3]
J60
CFG_RCOMP
CL_CLK
CL_DATA
CL_RST#
DAISY_CHAIN_NCT A62
F_A62
H60
H61
H62
K59
H63
K60
J61
DAISY_CHAIN_NCT AV1
F_AV1
DAISY_CHAIN_NCT AW1
F_AW1
CLKOUT_ITPXDP_N B35
CLKOUT_ITPXDP_P A35
DAISY_CHAIN_NCT AW2
F_AW2
CLKOUT_LPC_0
AN15
DAISY_CHAIN_NCT AW3
F_AW3
CLKOUT_LPC_1
AP15
C43
B41
C41
B38
A39
B37
C42
A41
B42
C37
B39
A37
V5
K61
AC60
AC62
V60
U60
T63
DAISY_CHAIN_NCT AW61
F_AW61
CLKOUT_PCIE_N0
CLKOUT_PCIE_N1
CLKOUT_PCIE_N2
CLKOUT_PCIE_N3
CLKOUT_PCIE_N4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P0
CLKOUT_PCIE_P1
CLKOUT_PCIE_P2
CLKOUT_PCIE_P3
CLKOUT_PCIE_P4
CLKOUT_PCIE_P5
DAISY_CHAIN_NCT AW62
F_AW62
DAISY_CHAIN_NCT AW63
F_AW63
DAISY_CHAIN_NCT AY2
F_AY2
T62
DAISY_CHAIN_NCT AY3
F_AY3
T61
DAISY_CHAIN_NCT AY60
F_AY60
T60
AA62
AA61
U63
U62
AC63
DAISY_CHAIN_NCT AY61
F_AY61
DAISY_CHAIN_NCT AY62
F_AY62
DAISY_CHAIN_NCT B2
F_B2
CLKRUN# /
GPIO32
continued...
continued...
AA63
continued...
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Processor Ball and Signal Information—Processors
Signal Name
Ball #
Signal Name
DDPB_CTRLDATA
DDPB_HPD
Ball #
C9
Signal Name
GPIO25
Ball #
AM4
DAISY_CHAIN_NCT B3
F_B3
C8
B6
GPIO26
GPIO27
GPIO28
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO8
AN3
AN5
AD7
AK4
AG5
AG3
AB6
U4
DAISY_CHAIN_NCT B61
F_B61
DDPC_AUXN
DDPC_AUXP
A6
DAISY_CHAIN_NCT B62
F_B62
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_HPD
D9
D11
A8
DAISY_CHAIN_NCT B63
F_B63
DAISY_CHAIN_NCT C1
F_C1
DEVSLP0 / GPIO33 P2
DEVSLP1 / GPIO38 L2
DEVSLP2 / GPIO39 N5
DAISY_CHAIN_NCT C2
F_C2
Y3
DCPRTC
AE7
AD10
AD8
AH13
J13
DIFFCLK_BIASREF
DPWROK
C26
P3
DCPSUS1
AV5
AW7
A45
B45
B8
R5
DCPSUS1
DSWVRMEN
EDP_AUXN
EDP_AUXP
eDP_BKLCTL
eDP_BKLEN
EDP_DISP_UTIL
EDP_HPD
L1
DCPSUS2
L4
DCPSUS3
L3
DCPSUS4
AB8
AG19
AG20
C54
B58
B55
A57
C55
C58
A55
B57
C51
C53
C49
A53
C50
B54
B50
B53
C5
U7
DCPSUSBYP
DCPSUSBYP
DDI1_TXN[0]
DDI1_TXN[1]
DDI1_TXN[2]
DDI1_TXN[3]
DDI1_TXP[0]
DDI1_TXP[1]
DDI1_TXP[2]
DDI1_TXP[3]
DDI2_TXN[0]
DDI2_TXN[1]
DDI2_TXN[2]
DDI2_TXN[3]
DDI2_TXP[0]
DDI2_TXP[1]
DDI2_TXP[2]
DDI2_TXP[3]
DDPB_AUXN
DDPB_AUXP
DDPB_CTRLCLK
A9
AG6
AP1
AL4
AT5
AU2
AM3
K2
A43
D6
EDP_RCOMP
EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3
EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3
eDP_VDDEN
GPIO10
D20
C45
A47
C47
A49
B46
B47
C46
B49
C6
GPIO9
GSPI_MOSI /
GPIO90
GSPI0_CLK /
GPIO84
L6
R6
N6
L8
L5
R7
N7
GSPI0_CS# /
GPIO83
GSPI0_MISO /
GPIO85
GSPI0_MOSI /
GPIO86
AM2
AT3
AH4
AD6
Y1
GSPI1_CLK /
GPIO88
GPIO13
GPIO14
GSPI1_CS# /
GPIO87
GPIO15
GSPI1_MISO /
GPIO89
GPIO16
GPIO17
T3
B5
HDA_BCLK /
I2S0_SCLK
AW8
GPIO24
AD5
B9
continued...
continued...
continued...
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Processors—Processor Ball and Signal Information
Signal Name
Ball #
AW10
Signal Name
PCH_TRST#
PCIE_IREF
Ball #
AU62
Signal Name
PETn5_L3
Ball #
B22
HDA_DOCK_EN# /
I2S1_TXD
B27
A27
U2
PETp1 / USB3Tp3
PETp2 / USB3Tp4
PETp3
C31
A31
B30
A29
C22
A23
C21
A21
U6
HDA_DOCK_RST#
/ I2S1_SFRM
AV10
AU8
PCIE_RCOMP
PCIECLKRQ0# /
GPIO18
HDA_RST# /
I2S_MCLK
PETp4
PCIECLKRQ1# /
GPIO19
Y5
HDA_SDI0 /
I2S0_RXD
AY10
AU12
AU11
AV11
PETp5_L0
PETp5_L1
PCIECLKRQ2# /
GPIO20
AD1
N1
U5
T2
HDA_SDI1 /
I2S1_RXD
PETp5_L2
PCIECLKRQ3# /
GPIO21
HDA_SDO /
I2S0_TXD
PETp5_L3
PIRQA# / GPIO77
PIRQB# / GPIO78
PIRQC# / GPIO79
PIRQD# / GPIO80
PLTRST#
PCIECLKRQ4# /
GPIO22
HDA_SYNC /
I2S0_SFRM
P4
PCIECLKRQ5# /
GPIO23
HSIOPC / GPIO71
I2C0_SCL / GPIO5
I2C0_SDA / GPIO4
I2C1_SCL / GPIO7
I2C1_SDA / GPIO6
I2S1_SCLK
INTRUDER#
INTVRMEN
Y2
N4
F3
N2
PECI
N62
G17
F15
G11
F13
F10
F8
F2
AG7
AD4
J62
PERn1 / USB3Rn3
PERn2 / USB3Rn4
PERn3
F1
PME#
G4
PRDY#
AY8
AU6
AV7
AE63
AU14
AW12
AY12
AW11
AM7
PREQ#
K62
D61
AY15
E60
F63
F62
E61
E59
K63
C61
H59
AL7
V4
PERn4
PROC_DETECT#
PROC_OPI_RCOMP
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PROCHOT#
PROCPWRGD
PWR_DEBUG#
PWRBTN#
RCIN# / GPIO82
RSMRST#
PERn5_L0
PERn5_L1
PERn5_L2
PERn5_L3
PERp1 / USB3Rp3
PERp2 / USB3Rp4
PERp3
JTAGX
H10
E6
LAD0
LAD1
F17
G15
F11
G13
E10
E8
LAD2
LAD3
LAN_PHY_PWR_CT
RL / GPIO12
PERp4
PERp5_L0
PERp5_L1
PERp5_L2
PERp5_L3
PETn1 / USB3Tn3
PETn2 / USB3Tn4
PETn3
LFRAME#
AV12
AL3
OC0# / GPIO40
OC1# / GPIO41
OC2# / GPIO42
OC3# / GPIO43
PCH_OPI_RCOMP
PCH_PWROK
PCH_TCK
G10
F6
AT1
AH2
AW6
W23
Y22
B43
T59
AD60
C30
B31
C29
B29
C23
B23
AV3
RSVD
AW15
AY7
RSVD
RSVD
PETn4
AE62
AD61
AE61
RSVD
PETn5_L0
PETn5_L1
PETn5_L2
PCH_TDI
RSVD
PCH_TDO
RSVD
AD59
B21
PCH_TMS
AD62
continued...
continued...
continued...
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Processor Ball and Signal Information—Processors
Signal Name
RSVD
Ball #
AA59
Signal Name
RSVD
Ball #
D15
Signal Name
RTCX1
Ball #
AW5
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AE60
AC59
AG58
V59
RSVD
AU10
AU15
E1
RTCX2
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AY5
RSVD
AU35
AV35
AY41
AU34
AU43
AW43
AY42
AY43
AU37
AW36
AV37
AY36
AP33
AR32
AH63
AH62
AP63
AP62
AM61
AM60
AP61
AP60
AY58
AW58
AY56
AW56
AK63
AV58
AU58
AV56
AU56
AY54
AW54
RSVD
RSVD
D1
U59
AL1
RSVD
J20
RSVD
H18
AN10
AM10
L59
AP7
RSVD
AM11
AV62
D58
P20
RSVD
RSVD
RSVD
J58
RSVD
Y20
R20
N60
AV2
AF20
AB21
AY14
AW14
E15
RSVD
AC20
V21
RSVD
RSVD
N58
AC58
AB23
AD23
AA23
AE59
K18
RSVD
RSVD
RSVD
RSVD
RSVD
E13
RSVD
AL11
AC4
A5
RSVD
M20
K21
RSVD
RSVD
M21
AV63
AU63
C63
C62
A51
N23
T23
#N/A
#N/A
U10
R23
L11
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
IVR_ERROR
IST_TRIGGER
RSVD_TP
RTCRST#
K10
F22
B51
P60
H22
J21
P61
N59
N61
L60
AT2
AU44
AV44
AU7
AY52
continued...
continued...
continued...
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Processors—Processor Ball and Signal Information
Signal Name
#N/A
Ball #
AW52
Signal Name
#N/A
Ball #
AK61
Signal Name
#N/A
Ball #
AV40
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AV54
AU54
AK62
AV52
AU52
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AH61
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AY23
AW23
AH60
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AV19
AU19
AV17
AU17
AK60
AM63
AM62
AJ61
#N/A
AW39
AY39
AU40
AP32
AY34
AW34
A12
#N/A
#N/A
#N/A
#N/A
#N/A
SATA_IREF
SATA_RCOMP
C12
AN62
AV57
AV53
AW30
AV26
AW22
AV18
AJ62
SATA_Rn0 /
PERn6_L3
J5
SATA_Rn1 /
PERn6_L2
J8
SATA_Rn2 /
PERn6_L1
J6
SATA_Rn3 /
PERn6_L0
F5
SATA_Rp0 /
PERp6_L3
H5
SATA_Rp1 /
PERp6_L2
H8
AN61
AW57
AW53
AV30
AW26
AV22
AW18
AU36
AY37
AP35
AW41
AU41
AR35
AV42
AU42
AR38
AP36
AU39
SATA_Rp2 /
PERp6_L1
H6
SATA_Rp3 /
PERp6_L0
E5
SATA_Tn0 /
PETn6_L3
B15
A17
B14
C17
A15
B17
C15
D17
SATA_Tn1 /
PETn6_L2
SATA_Tn2 /
PETn6_L1
SATA_Tn3 /
PETn6_L0
SATA_Tp0 /
PETp6_L3
SATA_Tp1 /
PETp6_L2
SATA_Tp2 /
PETp6_L1
SATA_Tp3 /
PETp6_L0
SATA0GP / GPIO34 V1
SATA1GP / GPIO35 U1
AW17
AR36
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
104
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
Ball #
Signal Name
#N/A
Ball #
AM49
Signal Name
#N/A
Ball #
AL18
SATA2GP / GPIO36 V6
SATA3GP / GPIO37 AC1
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AK49
AM48
AK48
AK57
AM51
AK51
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AL58
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AR21
AR22
AK58
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AR57
AK20
AM20
AR18
AP18
AN57
AP55
AR55
AM58
AM55
AL43
AL48
AN28
AN25
AN21
AN18
AN58
AN55
AL42
AL49
AM28
AM25
AM21
AM18
AP40
AR40
AK36
AV47
AU47
AK33
AR46
AP46
AP42
AR42
SATALED#
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
U3
AL35
AM36
AU49
AM33
AM38
AK38
AN38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AP58
AR58
AM54
AK54
AL55
AK55
AR54
AN54
AK40
AK42
AM43
AM45
AM57
AK45
AK43
AM40
AM42
AM46
AK46
AK18
AR45
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
105
Processors—Processor Ball and Signal Information
Signal Name
#N/A
Ball #
AP45
Signal Name
SMBCLK
Ball #
AP2
Signal Name
Ball #
UART0_RTS# /
GPIO93
J2
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AW46
AY46
AY47
AU46
AL32
AM35
AK35
E3
SMBDATA
AH1
AL2
UART0_RXD /
GPIO91
J1
SML0ALERT# /
GPIO60
UART0_TXD /
GPIO92
K3
J4
SML0CLK
AN1
AK1
AU4
SML0DATA
UART1_CTS# /
GPIO3
SML1ALERT# /
PCHHOT# /
GPIO73
UART1_RST# /
GPIO2
J3
SML1CLK / GPIO75 AU3
UART1_RXD /
GPIO0
K4
G2
SDIO_CLK /
GPIO64
SML1DATA /
GPIO74
AH3
UART1_TXD /
GPIO1
SDIO_CMD /
GPIO65
F4
SPI_CLK
AA3
Y7
USB2n0
USB2n1
USB2n2
USB2n3
USB2n4
USB2n5
USB2n6
USB2n7
USB2p0
USB2p1
USB2p2
USB2p3
USB2p4
USB2p5
USB2p6
USB2p7
USB3Rn1
USB3Rn2
USB3Rp1
USB3Rp2
USB3Tn1
USB3Tn2
USB3Tp1
USB3Tp2
USBRBIAS
AN8
AR7
SDIO_D0 / GPIO66 D3
SDIO_D1 / GPIO67 E4
SDIO_D2 / GPIO68 C3
SDIO_D3 / GPIO69 E2
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_IO2
Y4
AR8
AC2
Y6
AR10
AM15
AM13
AP11
AR13
AM8
AT7
SDIO_POWER_EN / C4
GPIO70
SPI_IO3
AF1
AA4
AA2
V2
SPI_MISO
SPI_MOSI
SPKR / GPIO81
SRTCRST#
SERIRQ
T4
SLP_A#
AL5
AJ7
AF3
AT4
AJ6
SLP_LAN#
SLP_S0#
SLP_S3#
SLP_S4#
AV6
AG4
SUS_STAT# /
GPIO61
AP8
SUSACK#
AK2
AE6
AV4
AT10
AL15
AN13
AN11
AP13
G20
SLP_S5# / GPIO63 AP5
SUSCLK / GPIO62
SLP_SUS#
AP4
SUSWARN# /
SUSPWRDNACK /
GPIO30
SLP_WLAN# /
GPIO29
AM5
SYS_PWROK
SYS_RESET#
TD_IREF
AG2
AC3
B12
AK8
AL8
C34
C35
D60
G1
SM_DRAMRST#
#N/A
AV15
AV61
AU60
AV60
AU61
AP49
AR51
AP51
AN2
E18
#N/A
TESTLOW_AK8
TESTLOW_AL8
TESTLOW_C34
TESTLOW_C35
THERMTRIP#
H20
#N/A
F18
#N/A
C33
#N/A
B33
#N/A
B34
#N/A
UART0_CTS# /
GPIO94
A33
SMBALERT# /
GPIO11
AJ11
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
106
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
USBRBIAS#
VCC
Ball #
AJ10
Signal Name
VCC
Ball #
F40
Signal Name
VCC1_05
Ball #
AE8
F59
AB57
AD57
AG57
C24
C28
C32
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
VCC
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC3_3
AF22
H11
H15
J11
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AG16
AG17
V8
VCC
VCC
VCC
VCC
VCC
VCC
VCC3_3
W9
VCC
VCC
VCC3_3
K14
K16
A20
AA21
W21
AE9
AF9
AG8
AG13
AG14
J18
VCC
VCC
VCC3_3
VCC
VCC
VCCACLKPLL
VCCAPLL
VCCAPLL
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCCLK
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCCLK
K19
J17
VCC
VCC
VCCCLK
VCC
VCC
VCCCLK
T21
R21
AH10
AH14
M9
VCC
VCC
VCCCLK
VCC
VCC
VCCDSW3_3
VCCHDA
VCCHSIO
VCCHSIO
VCCHSIO
VCCIO_OUT
VCOMP_OUT
VCCRTC
VCC
VCC
K23
K57
L22
M23
M57
P57
U57
W57
E63
P9
VCC
VCC
VCC
VCC
K9
VCC
VCC
L10
VCC
VCC
A59
E20
AG10
B11
U8
VCC
VCC
VCC
VCC
VCC
VCC
VCCSATA3PLL
VCCSDIO
VCCSDIO
VCCSPI
VCC
VCC_SENSE
VCC1_05
VCC1_05
VCC
T9
VCC
F36
N8
Y8
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
107
Processors—Processor Ball and Signal Information
Signal Name
VCCST
Ball #
AC22
Signal Name
VSS
Ball #
A32
Signal Name
VSS
Ball #
AH17
VCCST
AE22
AE23
B59
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A36
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
VCCST
A40
VCCST_PWRGD
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCTS1_5
VCCUSB3PLL
VDDQ
A48
AH11
AA9
A52
A56
AC9
AA1
AE20
AE21
J15
A44
AA58
AB10
AB20
AE5
B18
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
L62
VDDQ
AB22
AB7
VDDQ
VDDQ
AC61
AD3
VDDQ
VDDQ
AD63
AE10
AD21
AE58
AR43
C39
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VIDALERT#
VIDSCLK
VIDSOUT
VR_EN
AF11
AF12
AF14
AF15
AF17
AF18
AG21
AG23
AG1
N63
L63
F60
VR_READY
VSS
C59
P62
VSS
D63
P22
VSS
VSS
N21
VSS
A11
AG11
AG60
AG61
AG62
VSS
A14
VSS
A18
VSS
A24
VSS
A28
AG63
AJ58
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
108
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
VSS
Ball #
AJ60
Signal Name
VSS
Ball #
AN36
Signal Name
VSS
Ball #
AR49
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ63
AK23
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
D62
AP31
AP38
AP39
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AV16
AV20
AV24
AV28
AN35
AP48
AV33
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
109
Processors—Processor Ball and Signal Information
Signal Name
VSS
Ball #
AV34
Signal Name
VSS
Ball #
AY59
Signal Name
VSS
Ball #
D34
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
AV59
AV8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY6
AY4
B20
B24
B26
B28
B32
C38
B36
B4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D50
D51
D53
D54
D55
D57
D59
E11
E17
F42
F20
D5
AW16
AW24
AW33
AW35
AW37
AW4
B40
B44
C14
B48
B52
B56
B60
C11
C18
C20
C25
C27
D12
D14
D18
D21
D23
D25
D26
D27
D29
D2
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY51
AY53
F26
F30
F34
F38
G6
F46
F50
F54
F58
F61
G18
D30
D31
AY57
D33
G22
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
110
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
VSS
Ball #
G3
Signal Name
VSS
Ball #
V3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G5
VSS
V7
G8
VSS
W20
Y10
U9
H13
H17
H57
J10
J22
J59
J63
K1
VSS
VSS
VSS
Y59
Y63
W22
V58
AH46
V23
AH16
E62
AJ5
VSS
VSS
VSS
VSS
VSS
K12
R22
L13
L15
L17
L18
L20
L58
L61
L7
VSS
VSS_SENSE
WAKE#
XTAL24_IN
XTAL24_OUT
A25
B25
M22
N10
N3
C57
P59
P63
R10
R8
T1
T58
D8
U20
U22
U61
V10
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
111
Processors—Processor Ball and Signal Information
Table 59.
Ball List by Signal Name for LPDDR3 Configuration
Signal Name
Ball #
AJ8
Signal Name
CFG_RCOMP
CL_CLK
Ball #
V63
Signal Name
Ball #
ACPRESENT /
GPIO31
DAISY_CHAIN_NCT AW61
F_AW61
AF2
AD2
AF4
APWROK
AB5
AN4
DAISY_CHAIN_NCT AW62
F_AW62
CL_DATA
BATLOW# /
GPIO72
CL_RST#
DAISY_CHAIN_NCT AW63
F_AW63
CLKOUT_ITPXDP_N B35
CLKOUT_ITPXDP_P A35
BMBUSY# /
GPIO76
P1
DAISY_CHAIN_NCT AY2
F_AY2
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
CATERR#
CFG[0]
CFG[1]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
J60
CLKOUT_LPC_0
AN15
DAISY_CHAIN_NCT AY3
F_AY3
H60
H61
H62
K59
H63
K60
J61
CLKOUT_LPC_1
AP15
C43
B41
C41
B38
A39
B37
C42
A41
B42
C37
B39
A37
V5
DAISY_CHAIN_NCT AY60
F_AY60
CLKOUT_PCIE_N0
CLKOUT_PCIE_N1
CLKOUT_PCIE_N2
CLKOUT_PCIE_N3
CLKOUT_PCIE_N4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P0
CLKOUT_PCIE_P1
CLKOUT_PCIE_P2
CLKOUT_PCIE_P3
CLKOUT_PCIE_P4
CLKOUT_PCIE_P5
DAISY_CHAIN_NCT AY61
F_AY61
DAISY_CHAIN_NCT AY62
F_AY62
DAISY_CHAIN_NCT B2
F_B2
K61
AC60
AC62
V60
U60
T63
DAISY_CHAIN_NCT B3
F_B3
DAISY_CHAIN_NCT B61
F_B61
DAISY_CHAIN_NCT B62
F_B62
DAISY_CHAIN_NCT B63
F_B63
T62
DAISY_CHAIN_NCT C1
F_C1
CLKRUN# /
GPIO32
T61
DAISY_CHAIN_NCT C2
F_C2
DAISY_CHAIN_NCT A3
F_A3
T60
AA62
AA61
U63
U62
AC63
AA63
AA60
Y62
DCPRTC
AE7
DAISY_CHAIN_NCT A4
F_A4
DCPSUS1
AD10
AD8
AH13
J13
DAISY_CHAIN_NCT A60
F_A60
DCPSUS1
DCPSUS2
DAISY_CHAIN_NCT A61
F_A61
DCPSUS3
DAISY_CHAIN_NCT A62
F_A62
DCPSUS4
AB8
DCPSUSBYP
DCPSUSBYP
DDI1_TXN[0]
DDI1_TXN[1]
DDI1_TXN[2]
DDI1_TXN[3]
AG19
AG20
C54
DAISY_CHAIN_NCT AV1
F_AV1
Y61
DAISY_CHAIN_NCT AW1
F_AW1
Y60
B58
DAISY_CHAIN_NCT AW2
F_AW2
V62
B55
V61
DAISY_CHAIN_NCT AW3
F_AW3
A57
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
112
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
DDI1_TXP[0]
DDI1_TXP[1]
DDI1_TXP[2]
DDI1_TXP[3]
DDI2_TXN[0]
DDI2_TXN[1]
DDI2_TXN[2]
DDI2_TXN[3]
DDI2_TXP[0]
DDI2_TXP[1]
DDI2_TXP[2]
DDI2_TXP[3]
DDPB_AUXN
DDPB_AUXP
Ball #
C55
Signal Name
EDP_TXN1
Ball #
A47
Signal Name
GPIO9
Ball #
AM3
C58
A55
B57
C51
C53
C49
A53
C50
B54
B50
B53
C5
EDP_TXN2
EDP_TXN3
EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3
eDP_VDDEN
GPIO10
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO8
C47
A49
B46
B47
C46
B49
C6
GSPI_MOSI /
GPIO90
K2
GSPI0_CLK /
GPIO84
L6
GSPI0_CS# /
GPIO83
R6
GSPI0_MISO /
GPIO85
N6
GSPI0_MOSI /
GPIO86
L8
AM2
AT3
AH4
AD6
Y1
GSPI1_CLK /
GPIO88
L5
GSPI1_CS# /
GPIO87
R7
GSPI1_MISO /
GPIO89
N7
B5
T3
HDA_BCLK /
I2S0_SCLK
AW8
AW10
AV10
AU8
AY10
AU12
AU11
AV11
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPB_HPD
B9
AD5
AM4
AN3
AN5
AD7
AK4
AG5
AG3
AB6
U4
HDA_DOCK_EN# /
I2S1_TXD
C9
C8
HDA_DOCK_RST#
/ I2S1_SFRM
DDPC_AUXN
DDPC_AUXP
B6
HDA_RST# /
I2S_MCLK
A6
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_HPD
D9
HDA_SDI0 /
I2S0_RXD
D11
A8
HDA_SDI1 /
I2S1_RXD
DEVSLP0 / GPIO33 P2
DEVSLP1 / GPIO38 L2
DEVSLP2 / GPIO39 N5
HDA_SDO /
I2S0_TXD
HDA_SYNC /
I2S0_SFRM
Y3
DIFFCLK_BIASREF
DPWROK
C26
P3
HSIOPC / GPIO71
I2C0_SCL / GPIO5
I2C0_SDA / GPIO4
I2C1_SCL / GPIO7
I2C1_SDA / GPIO6
I2S1_SCLK
Y2
AV5
AW7
A45
B45
B8
R5
F3
DSWVRMEN
EDP_AUXN
L1
F2
L4
F1
EDP_AUXP
L3
G4
eDP_BKLCTL
eDP_BKLEN
EDP_DISP_UTIL
EDP_HPD
U7
AY8
AU6
AV7
AE63
A9
AG6
AP1
AL4
AT5
INTRUDER#
A43
D6
INTVRMEN
JTAGX
EDP_RCOMP
EDP_TXN0
D20
LAD0
AU14
C45
AU2
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
113
Processors—Processor Ball and Signal Information
Signal Name
LAD1
Ball #
AW12
Signal Name
PERn5_L3
Ball #
E6
Signal Name
PROC_TDI
Ball #
F63
LAD2
LAD3
AY12
AW11
AM7
PERp1 / USB3Rp3
PERp2 / USB3Rp4
PERp3
F17
G15
F11
G13
E10
E8
PROC_TDO
PROC_TMS
PROC_TRST#
PROCHOT#
PROCPWRGD
PWR_DEBUG#
PWRBTN#
RCIN# / GPIO82
RSMRST#
RSVD
F62
E61
LAN_PHY_PWR_CT
RL / GPIO12
E59
PERp4
K63
LFRAME#
AV12
AL3
PERp5_L0
C61
OC0# / GPIO40
OC1# / GPIO41
OC2# / GPIO42
OC3# / GPIO43
PCH_OPI_RCOMP
PCH_PWROK
PCH_TCK
PERp5_L1
H59
AL7
AT1
PERp5_L2
G10
F6
AH2
AV3
PERp5_L3
V4
PETn1 / USB3Tn3
PETn2 / USB3Tn4
PETn3
C30
B31
C29
B29
C23
B23
B21
B22
C31
A31
B30
A29
C22
A23
C21
A21
U6
AW6
W23
Y22
AW15
AY7
RSVD
AE62
AD61
AE61
AD62
AU62
B27
PETn4
RSVD
B43
PCH_TDI
PETn5_L0
RSVD
T59
PCH_TDO
PETn5_L1
RSVD
AD60
AD59
AA59
AE60
AC59
AG58
V59
PCH_TMS
PETn5_L2
RSVD
PCH_TRST#
PCIE_IREF
PETn5_L3
RSVD
PETp1 / USB3Tp3
PETp2 / USB3Tp4
PETp3
RSVD
PCIE_RCOMP
A27
RSVD
PCIECLKRQ0# /
GPIO18
U2
RSVD
PETp4
RSVD
PCIECLKRQ1# /
GPIO19
Y5
PETp5_L0
RSVD
U59
PCIECLKRQ2# /
GPIO20
AD1
N1
U5
T2
PETp5_L1
RSVD
AL1
PETp5_L2
RSVD
AP7
PCIECLKRQ3# /
GPIO21
PETp5_L3
RSVD
AM11
AV62
D58
P20
PCIECLKRQ4# /
GPIO22
PIRQA# / GPIO77
PIRQB# / GPIO78
PIRQC# / GPIO79
PIRQD# / GPIO80
PLTRST#
RSVD
P4
RSVD
PCIECLKRQ5# /
GPIO23
N4
RSVD
PECI
N62
G17
F15
G11
F13
F10
F8
N2
RSVD
R20
PERn1 / USB3Rn3
PERn2 / USB3Rn4
PERn3
AG7
AD4
J62
K62
D61
AY15
RSVD
N60
AV2
PME#
RSVD
PRDY#
RSVD
AF20
AB21
AY14
AW14
PERn4
PREQ#
RSVD
PERn5_L0
PERn5_L1
PERn5_L2
PROC_DETECT#
PROC_OPI_RCOMP
PROC_TCK
RSVD
RSVD
H10
E60
RSVD
E15
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
114
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
RSVD
Ball #
E13
Signal Name
RSVD
Ball #
K18
Signal Name
#N/A
Ball #
AM61
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AL11
AC4
A5
RSVD
M20
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AM60
AP61
AP60
AY58
AW58
AY56
AW56
AK63
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AK62
AV52
AU52
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AH61
AY27
AW27
AY25
AW25
RSVD
K21
RSVD
M21
N23
T23
#N/A
AV63
AU63
C63
#N/A
U10
R23
L11
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
IVR_ERROR
IST_TRIGGER
RSVD_TP
RTCRST#
RTCX1
RTCX2
#N/A
C62
A51
K10
F22
B51
P60
H22
J21
P61
N59
AT2
N61
AU44
AV44
D15
AU10
AU15
E1
L60
AU7
AW5
AY5
AU35
AV35
AY41
AU34
AU43
AW43
AY42
AY43
AU37
AW36
AV37
AY36
AP33
AR32
AH63
AH62
AP63
#N/A
D1
#N/A
J20
#N/A
H18
AN10
AM10
L59
#N/A
#N/A
#N/A
#N/A
J58
#N/A
Y20
#N/A
AC20
V21
N58
AC58
AB23
AD23
AA23
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AE59
#N/A
AP62
AV27
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
115
Processors—Processor Ball and Signal Information
Signal Name
#N/A
Ball #
AU27
Signal Name
#N/A
Ball #
AV30
Signal Name
Ball #
E5
SATA_Rp3 /
PERp6_L0
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AV25
AU25
AY23
AW23
AH60
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AK61
AV19
AU19
AV17
AU17
AK60
AM63
AM62
AJ61
#N/A
AW26
AV22
AW18
AU36
AY37
AP35
AW41
AU41
AR35
AV42
AU42
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP32
AY34
AW34
A12
SATA_Tn0 /
PETn6_L3
B15
A17
B14
C17
A15
B17
C15
D17
#N/A
#N/A
SATA_Tn1 /
PETn6_L2
#N/A
SATA_Tn2 /
PETn6_L1
#N/A
#N/A
SATA_Tn3 /
PETn6_L0
#N/A
SATA_Tp0 /
PETp6_L3
#N/A
#N/A
SATA_Tp1 /
PETp6_L2
#N/A
SATA_Tp2 /
PETp6_L1
#N/A
#N/A
SATA_Tp3 /
PETp6_L0
#N/A
SATA0GP / GPIO34 V1
SATA1GP / GPIO35 U1
SATA2GP / GPIO36 V6
SATA3GP / GPIO37 AC1
#N/A
#N/A
#N/A
#N/A
SATALED#
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
U3
#N/A
AL35
AM36
AU49
AM33
AM38
AK38
AN38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AP58
AR58
#N/A
#N/A
#N/A
#N/A
SATA_IREF
SATA_RCOMP
C12
AN62
AV57
AV53
AW30
AV26
AW22
AV18
AJ62
SATA_Rn0 /
PERn6_L3
J5
SATA_Rn1 /
PERn6_L2
J8
SATA_Rn2 /
PERn6_L1
J6
SATA_Rn3 /
PERn6_L0
F5
H5
H8
SATA_Rp0 /
PERp6_L3
SATA_Rp1 /
PERp6_L2
AN61
AW57
SATA_Rp2 /
PERp6_L1
H6
AM54
AW53
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
116
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
#N/A
Ball #
AK54
Signal Name
#N/A
Ball #
AK26
Signal Name
#N/A
Ball #
AL49
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AL55
AK55
AR54
AN54
AK40
AK42
AM43
AM45
AM57
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AK57
AM51
AK51
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AL58
AN26
AR26
AR25
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AM26
AK25
AL25
AR21
AR22
AK58
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AR57
AK20
AM20
AR18
AP18
AN57
AP55
AR55
AM58
AM55
AL43
AL48
AN28
AN25
AN21
AN18
AN58
AN55
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
#N/A
AM28
AM25
AM21
AM18
AP40
AR40
AK36
AV47
AU47
AK33
AR46
AP46
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AL32
AM35
AK35
E3
SDIO_CLK /
GPIO64
SDIO_CMD /
GPIO65
F4
SDIO_D0 / GPIO66 D3
SDIO_D1 / GPIO67 E4
SDIO_D2 / GPIO68 C3
SDIO_D3 / GPIO69 E2
SDIO_POWER_EN / C4
GPIO70
SERIRQ
T4
SLP_A#
AL5
SLP_LAN#
AJ7
AP25
AL42
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
117
Processors—Processor Ball and Signal Information
Signal Name
SLP_S0#
Ball #
AF3
Signal Name
Ball #
AG4
Signal Name
USB2p2
Ball #
AP8
SUS_STAT# /
GPIO61
SLP_S3#
SLP_S4#
AT4
AJ6
USB2p3
USB2p4
USB2p5
USB2p6
USB2p7
USB3Rn1
USB3Rn2
USB3Rp1
USB3Rp2
USB3Tn1
USB3Tn2
USB3Tp1
USB3Tp2
USBRBIAS
USBRBIAS#
VCC
AT10
AL15
AN13
AN11
AP13
G20
E18
SUSACK#
AK2
AE6
AV4
SUSCLK / GPIO62
SLP_S5# / GPIO63 AP5
SUSWARN# /
SUSPWRDNACK /
GPIO30
SLP_SUS#
AP4
SLP_WLAN# /
GPIO29
AM5
SYS_PWROK
SYS_RESET#
TD_IREF
AG2
AC3
B12
AK8
AL8
C34
C35
D60
G1
SM_DRAMRST#
#N/A
AV15
AV61
AU60
AV60
AU61
AP49
AR51
AP51
AN2
H20
F18
#N/A
TESTLOW_AK8
TESTLOW_AL8
TESTLOW_C34
TESTLOW_C35
THERMTRIP#
#N/A
C33
B33
B34
A33
AJ11
AJ10
F59
#N/A
#N/A
#N/A
#N/A
UART0_CTS# /
GPIO94
SMBALERT# /
GPIO11
UART0_RTS# /
GPIO93
J2
SMBCLK
AP2
AH1
AL2
UART0_RXD /
GPIO91
J1
VCC
AB57
AD57
AG57
C24
C28
C32
C36
C40
C44
C48
C52
C56
E23
SMBDATA
VCC
SML0ALERT# /
GPIO60
UART0_TXD /
GPIO92
K3
J4
VCC
SML0CLK
AN1
AK1
AU4
UART1_CTS# /
GPIO3
VCC
SML0DATA
VCC
UART1_RST# /
GPIO2
J3
SML1ALERT# /
PCHHOT# /
GPIO73
VCC
UART1_RXD /
GPIO0
K4
G2
VCC
SML1CLK / GPIO75 AU3
VCC
UART1_TXD /
GPIO1
SML1DATA /
GPIO74
AH3
VCC
USB2n0
USB2n1
USB2n2
USB2n3
USB2n4
USB2n5
USB2n6
USB2n7
USB2p0
USB2p1
AN8
VCC
SPI_CLK
AA3
Y7
AR7
VCC
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_IO2
AR8
VCC
Y4
AR10
AM15
AM13
AP11
AR13
AM8
VCC
AC2
Y6
VCC
E25
VCC
E27
SPI_IO3
AF1
AA4
AA2
V2
VCC
E29
SPI_MISO
SPI_MOSI
SPKR / GPIO81
SRTCRST#
VCC
E31
VCC
E33
AT7
VCC
E35
AV6
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
118
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
VCC
Ball #
E37
Signal Name
VCC
Ball #
G55
Signal Name
VCCCLK
Ball #
J17
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
VCC
G57
H23
J23
VCCCLK
T21
VCC
VCCCLK
R21
VCC
VCCDSW3_3
VCCHDA
VCCHSIO
VCCHSIO
VCCHSIO
VCCIO_OUT
VCOMP_OUT
VCCRTC
AH10
AH14
M9
VCC
K23
K57
L22
VCC
VCC
K9
VCC
M23
M57
P57
U57
W57
E63
P9
L10
VCC
A59
VCC
E20
VCC
AG10
B11
VCC
VCCSATA3PLL
VCCSDIO
VCCSDIO
VCCSPI
VCC_SENSE
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCACLKPLL
VCCAPLL
VCCAPLL
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCCLK
VCCCLK
U8
T9
N8
Y8
AE8
AF22
H11
H15
J11
VCCST
AC22
AE22
AE23
B59
VCCST
VCCST
VCCST_PWRGD
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCTS1_5
VCCUSB3PLL
VDDQ
AH11
AA9
AC9
AE20
AE21
J15
AG16
AG17
V8
W9
K14
K16
A20
AA21
W21
AE9
AF9
AG8
AG13
AG14
J18
B18
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
G53
K19
VDDQ
AY44
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
119
Processors—Processor Ball and Signal Information
Signal Name
VDDQ
Ball #
AY50
Signal Name
VSS
Ball #
C39
Signal Name
VSS
Ball #
AJ23
VIDALERT#
VIDSCLK
VIDSOUT
VR_EN
VR_READY
VSS
L62
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF11
AF12
AF14
AF15
AF17
AF18
AG21
AG23
AG1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ25
AJ27
AJ29
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
N63
L63
F60
C59
P62
VSS
D63
P22
VSS
VSS
N21
A11
A14
A18
A24
A28
A32
A36
A40
A48
A52
A56
AA1
A44
AA58
AB10
AB20
AE5
AB22
AB7
AC61
AD3
AD63
AE10
AD21
AE58
VSS
AG11
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR43
AJ14
AL51
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
120
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
VSS
Ball #
AL52
Signal Name
VSS
Ball #
AP3
Signal Name
VSS
Ball #
AU28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL54
AL57
AL60
AL61
AM1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AP31
AP38
AP39
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AP48
AR49
AR5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
D62
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
AV59
AV8
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AW16
AW24
AW33
AW35
AW37
AW4
AP10
AP17
AP20
AP22
AP23
AP26
AU16
AU18
AU20
AU22
AU24
AW40
AW42
AW44
AP29
AU26
AW47
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
121
Processors—Processor Ball and Signal Information
Signal Name
VSS
Ball #
AW50
Signal Name
VSS
Ball #
C25
Signal Name
VSS
Ball #
F42
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY51
AY53
AY57
AY59
AY6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C27
D12
D14
D18
D21
D23
D25
D26
D27
D29
D2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F20
D5
F26
F30
F34
F38
G6
F46
F50
F54
F58
F61
G18
G22
G3
D30
D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D50
D51
D53
D54
D55
D57
D59
E11
G5
AY4
G8
B20
H13
H17
H57
J10
J22
J59
J63
K1
B24
B26
B28
B32
C38
B36
B4
B40
K12
R22
L13
L15
L17
L18
L20
L58
L61
B44
C14
B48
B52
B56
B60
C11
C18
C20
E17
L7
continued...
continued...
continued...
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
Datasheet – Volume 1 of 2
122
December 2013
Order No.: 329001-005
Processor Ball and Signal Information—Processors
Signal Name
VSS
Ball #
M22
VSS
N10
N3
VSS
VSS
C57
P59
P63
R10
R8
VSS
VSS
VSS
VSS
VSS
T1
VSS
T58
D8
VSS
VSS
U20
U22
U61
V10
V3
VSS
VSS
VSS
VSS
VSS
V7
VSS
W20
Y10
U9
VSS
VSS
VSS
Y59
Y63
W22
V58
AH46
V23
AH16
E62
AJ5
A25
B25
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
WAKE#
XTAL24_IN
XTAL24_OUT
Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron®
Processor Family
December 2013
Order No.: 329001-005
Datasheet – Volume 1 of 2
123
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