DJCE6210882133 [INTEL]
Audio/Video Demodulator, AM, CMOS, 7 X 7 MM, LQFP-64;
| 型号： | DJCE6210882133 |
| 厂家： | 
INTEL |
| 描述： | Audio/Video Demodulator, AM, CMOS, 7 X 7 MM, LQFP-64 |
| 文件： | 总19页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CE6210
DVB-C Cable Demodulator
Data Sheet
June 2006
Features
•
DVB-C EN300429 and ITU-T J.83 annex A/C
Ordering Information
compliant QAM demodulator
DJCE6210 882133 64-pin LQFP Trays
•
•
•
•
•
•
•
•
•
•
•
Conventional IF and low IF input supported
QAM constellations 16, 32, 64, 128 and 256
Symbol rates up to 9 MBaud
WJCE6210 882214 64-pin LQFP* Trays
*Pb free
-40 C to +85 C
o
o
Blind acquisition of all symbol rates
•
•
RF level detect facility via a separate ADC
Blind acquisition of QAM constellations
Single IF filter bandwidth for all symbol rates
Signal level, BER and SNR indicators
Programmable IF/RF AGC take-over point
Power down mode under software control
Parallel and serial MPEG outputs
Very low driver software overhead due to on-chip
state-machine control.
•
General purpose programmable timer
Applications
•
•
•
•
Set-top boxes
External 4 or 27 MHz clock or single low-cost
Digital cable ready TV applications
Cable modems
SMATV/MATV receivers
10 MHz crystal
•
•
•
•
Small package size LQFP64 7x7 mm
Power consumption <300 mW at 6.9 MBaud
5 V tolerant 2-wire bus control interface
5 V tolerant GPIO port and AGC outputs
Figure 1 - System Diagram
1
Intel Corporation
D55750-001
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright © 2006 Intel Corporation. All rights reserved.
CE6210
Data Sheet
Description
The CE6210 is a DVB-C and ITU-T annex A/C QAM demodulator. This low power cable demodulator includes
standard Intel features of auto signal acquisition, fast blind-scan capability, software/ hardware power down, RF
level, BER and SNR detection. The CE6210 represents the latest in QAM demodulation for DVB cable. Together
with a cable tuner, a full digital cable receiver front-end can be realized. Either conventional intermediate
frequencies such as 36 or 44 MHz or low intermediate frequencies can be used - see application below. The
CE6210 requires only a single channel filter bandwidth of 8 MHz nominal for full DVB and ITU-T annex A/C
performance. The low power consumption, small package form factor and integrated software/hardware power-
down modes help reduce the system BoM (bill of materials) in cost sensitive applications. The device is packaged
in a 7 x 7 mm 64-pin LQFP.
Functional Description
The CE6210 accepts an analog signal from the tuner, either at low Intermediate Frequency (IF) or conventional IF
up to 50 MHz, and delivers an MPEG2 compliant transport stream. It contains a single 10-bit analog-to-Digital
Converter (ADC), a digital QAM demodulator and Forward Error Correcting (FEC) decoder. The QAM demodulator
supports QAM constellations 16 to 256. Both the QAM demodulator and the FEC are DVB and ITU-T J.83
annex A/C compliant.
Figure 2 - CE6210 Functional Diagram
The ADC uses a fixed sample rate greater than four times the maximum symbol rate. Hence for 1 to 9 MBaud
applications, the signal has to be sampled at a frequency around 36 MHz. The spectrum of the analog signal being
sampled may be located at near-zero IF (e.g. centered at 9 MHz) or it may be located at a conventional IF such as
36.2 MHz or 43.5 MHz.
First consider the case of IF sampling a 1 to 7 MBaud QAM signal centered at 36.2 MHz intermediate frequency.
The sampling frequency chosen for this application is 28.9 MHz. This sampling process will fold the 36.2 MHz IF
spectrum to one centered at 7.3 MHz.
Second consider the case of IF sampling a 1 to 6 MBaud QAM signal centered at 43.5 MHz IF. The sampling
frequency chosen for this application is 25 MHz. This sampling process will result in a QAM spectrum centered at
6.5 MHz.
In the second case the sampling process results in spectral inversion. Even in first case the IF spectrum may be
spectrally inverted. However, spectral inversion is not an issue with CE6210 since it automatically detects and
corrects for this in the digital domain.
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Intel Corporation
CE6210
Data Sheet
The digital signal is first mixed down to baseband. However, as a result of tuning errors this signal will not be
centered at zero frequency. CE6210 has an automatic frequency control (AFC) loop that can track out tuning errors
and hence in the tracking phase this signal will be centered at zero frequency. The AFC loop can typically
compensate for +/-350 kHz frequency offsets. Larger offsets can be corrected by programming on-chip registers.
The baseband signal is filtered to reduce the effect of adjacent channels. Additional on-chip digital filtering is
provided for low symbol rate applications. For example, it is possible to demodulate and decode a 1 MBaud QAM
signal using only one external 8 MHz SAW filter.
CE6210 has complete blind acquisition capability. It can automatically search and lock on to any QAM constellation
in the set 16, 32, 64, 128 and 256. It can compensate for spectral inversion. It can also automatically acquire a
symbol rate in the range 1 to 7 MBaud correcting for any tuning errors and adapting the filter bandwidths to signal
bandwidth. All these functions are implemented using a sophisticated built-in control state machine with no software
intervention.
The symbol-spaced equalizer in the CE6210 is designed to acquire the QAM signal in blind mode, i.e., with no
training sequence, and then to track the signal in the decision feedback mode. The equalizer has a feed-forward
segment and a feedback segments. The tap partitioning between feed-forward and feedback is fully programmable.
The symbol timing and phase recovery functions with the CE6210 are fully digital. The timing recovery phase
locked loop has a built in timing sweep to enable the CE6210 to lock on to unknown symbol rates. The phase
recovery loop has been optimised to overcome phase noise degradation caused by typical tuners.
The CE6210 QAM demodulator has built in control mechanisms to overcome signal degradation due to impulse
noise in cable systems. The most significant bits of the demodulated I/Q symbols are differentially decoded to
remove multiples of 90 degree phase ambiguity in demodulation. The QAM symbols are then demapped into a bit
stream, using the constellation definitions provided by DVB and ITU-T. The number of bits per symbol is eight for
QAM-256, seven for QAM-128, six for QAM-64, five for QAM-32 and four for QAM-16.
The bitstream is aligned into bytes and then into 204-byte frames by the Frame Alignment Unit. These frames are
deinterleaved as defined by DVB to improve the resilience of the system to error bursts. The (204,188) Reed-
Solomon decoder, which follows the deinterleaver, can correct up to eight byte-errors per frame. This also
generates an uncorrectable error flag for blocks with more than eight byte-errors. In addition, the CE6210 Reed-
Solomon decoder keeps a count of the number of uncorrectable blocks and the number of bit errors corrected. The
former will give an indication on the quality of the MPEG output and the latter provides the Bit Error Rate in QAM
demodulation.
The decoder packets are then descrambled to reverse the energy dispersal function introduced by the transmitter.
The output of the device is a stream of regularly spaced MPEG packets. The MPEG byte clock frequency is
automatically adapted to be the minimum needed for a given symbol rate and QAM constellation. Alternatively the
MPEG bytes can be clocked out using an externally provided byte clock. There is also an option for bit-serial
output.
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Intel Corporation
CE6210
Data Sheet
Figure 3 - Typical CE6210 Application
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Intel Corporation
CE6210
Data Sheet
1.0 Pin & Package Details
1.1 Pin Outline
Figure 4 below shows the pin functions of the CE6210.
Figure 4 - Pin Outline
1.2 Pin Allocation
Pin
Function
Vdd
Pin
Function
GPP0
Pin
Function
Pin
Function
1
2
3
4
5
6
7
17
18
19
20
21
22
23
33
34
35
36
37
38
39
Vdd
49
50
51
52
53
54
55
MDO0
CVdd
Gnd
SADD4
RESET
SLEEP
PLLTest
PLLVdd
Gnd
RFLev
MDO1
MDO2
MDO3
MDO4
MDO5
Vdd
Gnd
SADD3
SADD2
IRQ
CVdd
SADD1
SADD0
AGC2/GPP1
CVdd
Table 1 - Pin Names - numeric
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Intel Corporation
CE6210
Data Sheet
Pin
Function
Gnd
Pin
Function
Pin
Function
AGC1
Pin
Function
8
24
25
26
27
28
29
30
31
32
XTI
40
41
42
43
44
45
46
47
48
56
57
58
59
60
61
62
63
64
Gnd
9
CLK1
DATA1
CVdd
Gnd
XTO
Gnd
CVdd
Gnd
10
11
12
13
14
15
16
Gnd
CVdd
Vdd
OSCMode
AVdd
Gnd
MDO6
MDO7
MOCLK
BKERR
MICLK
Gnd
Gnd
SMTest
STATUS
Gnd
CLK2
DATA2
MOSTRT
MOVAL
VIN
VIN
Vdd
Gnd
Table 1 - Pin Names - numeric (continued)
Function
AGC1
Pin
Function
Pin
Function
MDO2
Pin
Function
SADD1
Pin
40
39
28
62
9
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
GPP0
IRQ
MDO0
MDO1
12
15
23
26
29
32
35
41
44
56
58
64
17
6
51
52
53
54
59
60
63
61
47
48
27
21
22
19
34
38
37
5
AGC2/GPP1
AVdd
MDO3
SADD2
SADD3
SADD4
SLEEP
SMTest
STATUS
Vdd
MDO4
4
MDO5
18
20
13
14
1
BKERR
CLK1
MDO6
CLK2
45
2
MDO7
CVdd
MICLK
MOCLK
MOSTRT
MOVAL
OSCMode
PLLTest
PLLVdd
RESET
RFLev
CVdd
7
CVdd
11
36
42
57
10
46
3
Vdd
16
33
43
55
30
31
24
25
CVdd
Vdd
CVdd
Vdd
CVdd
Vdd
DATA1
DATA2
Gnd
VIN
VIN
49
50
XTI
Gnd
8
SADD0
XTO
Table 2 - Pin Names - alphabetical order
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Intel Corporation
CE6210
Data Sheet
1.3 Pin Description
Pin Description Table
I/
O
V 1
Pin No
Name
Pin Description
Type
mA
MPEG pins
3.3
1
1
1
47
48
MOSTRT
MOVAL
MPEG packet start
MPEG data valid
MPEG data outputs
O
3.3
3.3
O
O
CMOS
Tristate
49-54,
59-60
MDO(0:5)
MDO(6:7)
3.3
3.3
3.3
3.3
5
1
1
61
MOCLK
BKERR
MICLK
STATUS
IRQ
MPEG output clock
Block error output
MPEG input clock
Status output
O
O
I
62
63
CMOS
1
6
14
O
O
Open drain
6
Interrupt output
Control pins
5
5
9
CLK1
Serial clock
Serial data
I
CMOS
6
10
DATA1
I/
Open drain
O
1.8
1.8
24
25
XTI
Low phase noise crystal
oscillator
I
CMOS
XTO
I/
O
5
20
SLEEP
SADD(4:0)
SMTest
CLK2
Device power down
Serial address set
I
I
I
3.3
3.3
5
4, 5,18,37,38
13
45
Production test (only set low)
Serial clock tuner
6
6
I/
Open drain
O
5
46
DATA2
Serial data tuner
Primary AGC
I/
O
5
5
6
6
40
39
AGC1
O
AGC2/GPP1
Secondary AGC or general
I/O
I/
O
5
5
6
17
19
GPP0
General purpose I/O
I/
O
RESET
Device reset - active low
I
CMOS
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Intel Corporation
CE6210
Data Sheet
Pin Description Table (continued)
Pin No Name
I/
Pin Description
Type
CMOS
V 1
3.3
mA
O
27
OSCMode
Crystal oscillator mode:
Low = crystal oscillator
High = external clock
I
21
PLLTest
PLL test - do not connect
O
(tristated)
Analog inputs
I
I
30
31
VIN
VIN
ADC positive input
ADC negative input
Analog input
nominally
±400 mV
AC coupled
RFLev
3.3
1.8
34
RF level ADC input
Analog input
nominally
3.3 V for
I
max. level
Supply pins
2
S
S
S
S
28
AVdd
CVdd
ADC analog supply
2, 7, 11, 36, 42,
57
Core logic power
2
22
PLLVdd
Vdd
PLL supply
3.3
0
1, 16, 33, 43, 55
I/O ring power
2
(#33 is to ADC only )
3, 8, 12, 15, 23,
26, 29, 32, 35, 41,
44, 56, 58, 64
Gnd
Core, analog and I/O
3
S
grounds
1. This column is the nominal maximum for a given pin. Pins listed as 5 V can tolerate voltages up to 5 V (inputs have threshold
voltages related to the 3V3 supply).
2. Pins #22, #28 and #33 should have separate supply lines from the digital supplies of the same voltage.
3. Decoupling capacitors should be used from every Gnd pin to its adjacent supply pin, with the capacitor as close as possible to
the pins. Pin #26 is provided to allow the oscillator to be ringed.
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Intel Corporation
CE6210
Data Sheet
2.0 Interfaces
2.1 2-wire Bus
2.1.1 Host
The primary 2-wire bus serial interface uses pins:
•
•
DATA1 (pin #10) serial data, the most significant bit is sent first.
CLK1 (pin #9) serial clock.
The 2-wire bus address is determined by applying Vdd or Gnd to the SADD[4:0] pins.
In CNIM evaluation applications, the 2-wire bus address is 0001 111 R/W with the pins connected as follows:
ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1]
Not programmable
Gnd Gnd
SADD[4] SADD[3] SADD[2] SADD[1] SADD[0]
Gnd Vdd Vdd Vdd Vdd
When the CE6210 is powered up, the RESET pin 9 should be held low for at least 50 ms after Vdd has reached
normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus
address. ADDR[0] is the R/W bit.
The circuit works as a slave transmitter with the address lsb set high or as a slave receiver with the lsb set low. In
receive mode, the first data byte is written to the RADD virtual register, which forms the register address. The
RADD register takes an 8-bit value that determines which of 256 possible register addresses is written to by the
following byte. Not all addresses are valid and many are reserved registers that must not be changed from their
default values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to
access the reserved registers accidentally.
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address
is not recognized, the CE6210 will ignore all activity until a valid chip address is received. The 2-wire bus START
command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a
particular read register with a write command, followed immediately with a read data command. If required, this
could next be followed with a write command to continue from the latest address. RADD would not be sent in this
case. Finally, a STOP command should be sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out
is the contents of register 00.
2.1.2 Tuner
The CE6210 has two GPP (general purpose port) pins which are normally configured to provide a secondary 2-wire
bus, allowing the main serial bus to be connected through to the tuner only when it is necessary to communicate
with the tuner.
This reduces the electrical noise seen by the tuner and improves the performance. The allocation of the pins is:
pin 45 = CLK2 or GPP3; pin 46 = DATA2 or GPP2.
Pass-through mode is selected by setting register Tuner_Ctl (0x56) [b0] = ‘1’, otherwise, if this bit is ‘0’, then there is
no connection between the two serial buses. In this same register, bit [b2] must also be set to a ‘1’ to enable the
pins for serial use rather than as general purpose port pins. See also register GPP_Ctl address 0x55 for details of
using these pins as GPPs.
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Intel Corporation
CE6210
Data Sheet
2.1.3 Examples of 2-wire Bus Messages:
KEY:
S
P
A
Start condition
Stop condition
Acknowledge
W
R
Write (= 0)
Read (= 1)
NA NOT Acknowledge
RADD Register Address
Italics CE6210 output
Write operation - as a slave receiver:
S
DEVICE
W
A
RADD
(n)
A
DATA
A
DATA
(reg n+1)
A
P
ADDRESS
(reg n)
Read operation - CE6210 as a slave transmitter:
S
DEVICE
R
A
DATA
A
DATA
A
DATA NA
P
ADDRESS
(reg 0)
(reg 1)
(reg 2)
Write/read operation with repeated start - CE6210 as a slave transmitter:
S
DEVICE
W
A
RADD
(n)
A
S
DEVICE
R
A
DATA
A
DATA
NA
P
ADDRESS
ADDRESS
(reg n)
(reg n+1)
2.1.4 Primary 2-wire Bus Timing
tBUFF
Sr
P
DATA1
tLOW
tR
tF
CLK1
P
S
tSU;STO
tHIGH
tSU;DAT tSU;STA
tHD;STA
tHD;DAT
Figure 5 - Primary 2-wire Bus Timing
Where:
S = Start
Sr = Restart, i.e., start without stopping first
P = Stop
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Intel Corporation
CE6210
Data Sheet
Value
Parameter
CLK clock frequency (Primary)
Symbol
Unit
Min.
Max.
1
f
t
t
t
t
t
t
t
t
t
t
0
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
Bus free time between a STOP and START condition.
Hold time (repeated) START condition.
LOW period of CLK clock.
200
BUFF
HD;STA
LOW
200
1300
600
200
100
100
HIGH period of CLK clock.
HIGH
SU;STA
HD;DAT
SU;DAT
R
Set-up time for a repeated START condition.
Data hold time (when input).
Data set-up time
2
Rise time of both CLK and DATA signals.
Fall time of both CLK and DATA signals, (100pF to ground).
Set-up time for a STOP condition.
note
20
F
200
SU;STO
Table 3 - Timing of 2-Wire Bus
1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.
2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
2.2 MPEG
2.2.1 Data Output Header Format
188 byte packet output
184 Transport packet bytes
Transport
Packet
Header
4 bytes
1st byte
2nd byte
0
1
0
0
0
1
1
1
TEI
MDO[7]
MDO[0]
Figure 6 - DVB Transport Packet Header Byte
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Intel Corporation
CE6210
Data Sheet
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally when the TEI_En bit in the MCLK_CTL register (0x77) is set high (default), the TEI bit of any
uncorrectable packet will automatically be set to ‘1’. If TEI_En bit is low then TEI bit will not be changed (but note
that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at
output).
2.2.2 MPEG Data Output Signals
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data pins as outputs. The maximum
movement in the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be a
continuously running clock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is
shown in Figure 7 with MOCLKINV = ‘1’, the default state, see register 0x50.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK
(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during
the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of
a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet
where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.
188 byte packet n
1st byte packet n
MOCLKINV=1
1st byte packet n+1
MOCLK
MDO7:0
MOSTRT
MOVAL
BKERR
Tp
Ti
Figure 7 - MPEG Output Data Waveforms
2.2.3 MPEG Output Timing
o
Maximum delay conditions: Vdd = 3.0 V, CVdd = 1.62 V, Tamb = 85 C, Output load = 10 pF.
o
Minimum delay conditions: Vdd = 3.6 V, CVdd = 1.98 V, Tamb = -40 C, Output load = 10 pF.
MOCLK frequency = 45.06 MHz.
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Intel Corporation
CE6210
Data Sheet
2.2.4 MOCLKINV = 1
Delay Conditions
Maximum Minimum
Parameter
Units
Data output delay t
3.0
7.0
7.0
1.0
10.0
10.0
D
Setup Time t
ns
SU
Hold Time t
H
MOCLK
tD
MDO
MOSTRT
MOVAL
}
BKERR
tSU
tH
Figure 8 - MPEG Timing - MOCLKINV = 1
2.2.5 MOCLKINV = 0
MDOSWAP = 0
Delay Conditions
Maximum Minimum
Parameter
Units
Data output delay t
3.0
18.0
1.0
1.0
20.0
0.2
D
Setup Time t
ns
SU
Hold Time t
H
The hold time is better when MOCLKINV = 1, therefore this should be used if possible.
MOCLK
tD
MDO
MOSTRT
MOVAL
}
tSU
BKERR
tH
Figure 9 - MPEG Timing - MOCLKINV = 0
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Intel Corporation
CE6210
Data Sheet
3.0 Electrical Characteristics
3.1 Recommended Operating Condition
Parameter
Symbol
Min.
Typ.
Max.
Units
Core power supply voltage
CVdd
Vdd
1.71
3.13
3.99
9.99
1.8
3.3
1.89
3.47
27.01
16.01
400
V
V
Periphery power supply voltage
1
Input clock frequency (note )
Fxt1
Fxt2
Fclk1
MHz
MHz
kHz
°C
Crystal oscillator frequency
2
CLK1 clock frequency (with 10 MHz or above)
Ambient operating temperature
-40
85
1. When not using a crystal, XTI may be driven from an external source over the frequency range shown.
2. The maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 kHz with
a 4.0 MHz clock.
3.2 Absolute Maximum Ratings
Maximum Operating Conditions
Parameter
Symbol
Min.
Max
4.5
Unit
Vdd
CVdd
Vi
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
V
Power supply
2.3
Voltage on input pins (5 V rated)
Voltage on input pins (3.3 V rated)
Voltage on input pins (1.8 V rated, e.g., XTI)
Voltage on output pins (5 V rated)
Voltage on output pins (3.3 V rated)
Voltage on output pins (1.8 V rated, e.g., XTO)
Storage temperature
5.5
V
V
Vi
6.5
Vi
CVdd + 0.3
5.5
V
Vo
V
Vo
Vdd + 0.3
CVdd + 0.3
V
Vo
V
Tstg
Top
Tj
-55
150
°C
°C
°C
kV
Operating ambient temperature
Junction temperature
-40
85
125
ESD protection (human body model)
4
Note 1: Stresses exceeding these listed under 'Absolute Ratings' may induce failure. Exposure to absolute maximum ratings for
extended periods may reduce reliability. Functionality at or above these conditions is not implied.
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Intel Corporation
CE6210
Data Sheet
3.3 Crystal Specification
Parallel resonant fundamental frequency (preferred) 9.99 to 16.01 MHz.
Tolerance over operating temperature range ±25 ppm.
Tolerance overall ±50 ppm.
Nominal load capacitance 30 pF.
Equivalent series resistance <50 Ω
Figure 10 - Crystal Oscillator Circuit
3.3.1 Selection of External Components
The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is
greater than unity. Correct selection of the two capacitors is very important and the following method is
recommended to obtain values for C1 and C2.
3.3.1.1 Loop Gain Equation
Although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to
ensure that oscillations will occur across all variations in temperature, process and supply voltage, and that the
circuit will exhibit good start-up characteristics.
C
.g
C
+ C
in
1
1
-1
out
C
m
out
- Equation 1
- Equation 2
A =
+
+
R .C
Z
Z
in
f
in
in
o
1
out
Z =
in
2
(2.π.f.C ) .ESR
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Intel Corporation
CE6210
Data Sheet
3.3.1.2 List of Equation Parameters
A
total loop gain (between 5 and 25)
C1 + Cpar
Cin
Cout C2 + Cpar
Cpar parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track
capacitances, package capacitance and cell input capacitance. Normally Cpar ≈ 4 pF.
Zo
gm
Rf
9.143 kΩ - output impedance of amplifier at 1.8 V operation - typical
8.736mA/V - transconductance of amplifier at 1.8 V operation -typical
2.3MΩ - internal feedback resistor
ESR
f
maximum equivalent series resistance of crystal - given by crystal manufacturer (Ω)
fundamental frequency of crystal (Hz)
3.3.1.3 Calculating Crystal Power Dissipation
To calculate the power dissipated in a crystal the following equation can be used:
2
V
pp
8.Z
P =
- Equation 3
c
in
Pc = power dissipated in crystal at resonant frequency (W)
Vpp = maximum peak to peak output swing of amplifier is 1.8 V for all CVdd
Zin = crystal network impedance (see Equation 2)
3.3.1.4 Capacitor Values
Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with
Equation 4 below.
g
A
2
1
1
m
.
- Equation 4
C = C
=
-
-
in
out
2
when: C = C = C - C
par
(2.π.f) .ESR
1
2
out
R
Z
f
o
Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.
Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the
resulting crystal load capacitance C (see Equation 5) is close to the crystal manufacturers recommended C
L
L
(standard values for C are 15 pF, 20 pF and 30 pF). The crystal will then operate very near its specified frequency.
L
C
C
. C
in
out
out
- Equation 5
C =
C
par12
+
L
+ C
in
C
par12 = parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin
capacitance (including any socket used) and the printed circuit board’s track-to-track capacitance.
C
≈ 2pF.
par12
If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s
recommended C may be acceptable. Larger values of C tend to reduce the influence of circuit variations and
L
L
tolerances on frequency stability. Smaller values of C tend to reduce startup time and crystal power dissipation.
L
Care must however be taken that C does not fall outside the crystal pulling range or the circuit may fail to start up
L
16
Intel Corporation
CE6210
Data Sheet
altogether. It is also possible to quote C to the crystal manufacturer who can then cut a crystal to order which will
L
resonate, under the specified load conditions, at the desired frequency.
Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is
not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain
condition is still satisfied. This must be done using Equation 1.
C
C
2
Note:
2 >
> 0.5
1
3.3.1.5 Oscillator/Clock Application Notes
•
On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible.
Other signal tracks must not be allowed to cross through this area. The component tracks should preferably
be ringed by a ground track connected to the chip ground (0 V) on adjacent pins either side of the crystal
pins. It is also advisable to provide a ground plane for the circuit to reduce noise.
•
•
External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0 V and
CVdd) and current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the
cell’s amplitude clamping circuit.
An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To
limit the current taken from the signal source a resistor should be placed between the clock source and XTI.
The recommended value for this series resistor is 470 Ω for a clock signal switching between 0 V and CVdd
(1V8). The current the clock source needs to source/sink is then <1.9 mA. The XTO pin must be left
unconnected in this configuration.
•
•
AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty
cycle of the OSCOUT signal cannot be guaranteed in such a configuration.
AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that
the circuit shown in Figure 11 be used to correctly bias the oscillator inputs: The common-mode voltage VCM
for XTI and XTO, (set by the 15 kΩ and 22 kΩ resistors) must be 800 mV < VCM < CVdd and the amplitude
Vpp of the clock signal must be >400 mV.
XTO
XTI
Vdd
OSCMODE
36k
100k
10nF
External clock
22k
10nF
Figure 11 - External Clocking via AC Coupling
•
External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode
voltage VCM for the differential clock signals must be 800 mV < VCM < CVdd, and the peak-to-peak signal
amplitude Vpp must be >400 mV. It is recommended that differential clock signals have VCM = 1.0 V. For
Vpp > 400 mV a resistor of >390 Ω in series with XTI or XTO may be required to limit the current taken from
or supplied to the clock sources.
17
Intel Corporation
CE6210
Data Sheet
3.4 Electrical Characteristics
Conditions (unless specified otherwise):Tamb = 25°CCVdd = 1.8 VVdd = 3.3 V
DC Electrical Characteristics
Parameter
Conditions/Pin
Symbol
Min.
Typ.
Max.
Unit
Core voltage
CVdd
Vdd
1.71
3.13
1.8
3.3
1.89
3.47
V
Peripheral voltage
Core current
V
Default settings
CIdd
Idd
120
2.2
mA
mA
mW
mW
Peripheral current
Total power
Ptot1
Ptot2
223
2.55
Total power (stand-
by)
ADCs powered down.
MPEG outputs tri-stated
Total power (sleep)
Pin 20 = logic ‘1’ & ADCs powered
down
Ptot3
Vol
0.10
mW
V
Output low level
2, 6 or 12 mA per output (see section
1.3, Pin Description)
0.4
Output high level
Output leakage
2, 6 or 12 mA per output
Voh
2.4
V
Tri-state when off or open-drain when
high
±1
µA
All outputs except XTO, CLK1 & open-
2.7
3.3
pF
pF
Output capacitance drain types. Excludes packaging
contribution (~0.35pF)
Open-drain outputs.
Excludes packaging
contribution (~0.35pF)
Input low level
Input high level
Vil
0.8
V
V
Vih
2.0
Input leakage
Vin = 0 or Vdd
±1
µA
pF
Input capacitance
Excludes packaging contribution
(~0.35pF)
1.5
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Intel Corporation
CE6210
Data Sheet
AC Electrical Characteristics
Parameter
Conditions/Pin
Min.
Typ.
Max.
Unit
ADC Full-scale input single range (single- Differential source is
1.6
Vpp
ended or differential)
recommended
Per input pin
ADC analog input resistance
ADC input common mode voltage level
25
kΩ
V
1
0.9
3.3
RF ADC Full-scale input single range
(single-ended)
Vpp
RF ADC analog input resistance
RF ADC input common mode voltage
System clock frequency
25
1.65
kΩ
V
2
30.00
3.99
100
MHz
MHz
3
Input clock frequency (note )
See Section 3.3.1.5 for
details.
27.01
Crystal oscillator frequency
See Section 3.3 for details
9.99
16.01
400
MHz
kHz
4
CLK1 clock frequency
(with 10 MHz xtal or above)
MPEG clock input frequency
5
6
On pin #63
note
65
MHz
1. Actually CVdd/2
2. Actually Vdd/2
3. When not using a crystal, XTI may be driven from an external source over the frequency range shown.
4. The maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 kHz with a
4.0 MHz clock.
5. Must be calculated from the data input rate.
6. Must be lower than the system clock.
19
Intel Corporation
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